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[//]: # (Copyright 2021 Massachusetts Institute of Technology)
[//]: # (SPDX short identifier: BSD-2-Clause)
[](https://zenodo.org/badge/latestdoi/108179132)
[](https://opensource.org/licenses/BSD-2-Clause)
# CEP Changelog
## [v4.20] - 2022-08-03
### Added
* Added kgetc to bare metal console routines
* Verified firemarshal generated linux build boots on the Arty100T, VC707, and VCU118. Instructions added to [README.md](./README.md)
* Added `helloworld` and `gpiotest` to ./software/linux. Makefiles allow application's install to firemarshal's buildroot.
* Added VC707 CEP FPGA target thanks to the folks at NECSTLab (https://github.com/necst)
* Added VCU118 CEP FPGA target
### Changed
* Unified console print routines across bootroms, cosim baremetal, and standalone bare metal code. Bare metal prints are now handled using stdio functions with
putchar, getchar, and putstr being mapped to the console versions
### Known issues
* cep_cosim
* Cadence XCellium on RHEL7 *occasionally* fails some of the bareMetal tests. Root cause has not been determined, but it is recommended that the test be re-run.
* Known est failures:
* ./testSuites/bfmTests/macroMix - GPS Test - First core passes, subsequent cores fail.
* Virtual mode ISA tests - Failure on Questsim/Ubuntu, passes on XCellium/RHEL7
* ./testSuites/isaTests/rv64mi-p-csr
* ./testSuites/isaTests/rv64si-p-csr
* ./testSuites/bfmTests/srotErrorTest
* ./testSuites/bareMetalTests/plicPrioIntr
* ./testSuites/bareMetalTests/extIntr
* ./testSuites/bareMetalTests/lsrcOps
* ./testSuites/isaTests/dtmTest
## [v4.10] - 2022-07-01
### Added
* Added a bareMetal/aesMacro test for running on the Arty100T build, which currently only has one AES core and the SRoT
### Changed
* Unified/debugged console printf functionality when building bare metal executables. By default, it is disabled, but can be enabled with the ENABLE_KPRINTF directive
* Arty100T and cep_sim use the same 'sd.c' source file, but leverage different makefiles.
* Misc. code and readme cleanup
* Bumped Chipyard to 1.7.0 from 1.5.0. See [CHANGELOG](./CHANGELOG.md).
* Rocket-Chip bumped to v1.5
### Fixed
* iDFT test code fixed in cep_idft.cc
## [v4.00] - 2022-06-21
### Added
* Chipyard Arty100t branch merged in (Commit 4440db0, March 4, 2022)
### Changed
* CHANGELOG.CEP.md updated based on guidance from *keep a changelog* (https://keepachangelog.com/en/1.0.0/)
* CEP has been completely ported to the UCB Chipyard Framework (https://github.com/ucb-bar/chipyard)
* Arty-A7 100T FPGA target running bare-metal code is currently supported (Linux is not currently supported)
## v3.41 - (10 September 2021)
* CEP Configuration nows includes 4xGPS and 4xSHA-256 cores
* Integrated configurable co-simulation environment (provide a co-sim that can more easily adapt to CEP architecture changes)
* Known Issues:
- Some idft test vectors fail under QuestaSim (xcellium regression ran successfully)
- Multithreaded test (#23) non-functional under linux
##v3.4 - (6 August 2021)
* Added external interrupt test (extIntr)
* Added test to boot rom to verify code execution out of scratchpad is working
* Added cryptoMask to cep_srot to support individual key loading only if enable
* Restructured cosim Makefiles to support re-use from other repos
* Modified cadence Makefile to enable partial toggle scoring
* Changed un-initialized main memory default state (from 0 -> 1) to improve coverage
* Addressed an LLKI bug in which the LLKI-PP component would send a respond to the SRoT before llkid_key_complete is asserted by the mock_tss_fsm
* Fixed GPS port directions in verilog
* Scratchpad RAM changed to blackbox implementation to facilitate ASIC development
* OpenSSL replaced by Cryptopp for crypto-related tests (cosim + linux)
##v3.3 - (19 May 2021)
* Increased capacity for LLKI key size including larger KeyRAM (2048 64-bit words)
* Added Cosim JTAG/OpenOCD
* Stability fixes for cep_diag under Linux
* Virtual Address TLB test suite is added to regression (not 100% complete)
* Expanded cep_diag
* New simulation ONLY interrupt tests for CLINT and PLIC modules (on going)
* Re-capture vectors for unit sim due to changes in LLKI key size
* Bootrom size is increased to 32K bytes (8kx32) to accomodate new built-in test (execute codes out of bootrom without main memory)
##v3.2 - (16 April 2021)
* LLKI bug fixes
* Scratchpad RAM added
* Cadenece xcelium simulator and coverage support added
* Linux tests updated and expanded
* New tests added to cosim focused on LLKI and Scratchpad RAM
##v3.11 - (29 March 2021)
* Unit Simulations updated for full LLKI support
* GPS core bugfix to provide specification compliance and increase functional coverage
* SRoT tests added
* SRoT has been updated to use a single port (1RW) RAM.
* Misc. bug fixes and README cleanup
* Known Issues:
- cep_diag (on Linux) has NOT been updated to work with the LLKI. Thus, running the tests that use
the CEP cores (e.g., cep_aes, cep_des3, etc.) will result in failure
##v3.1 - (22 February 2021)
* Full LLKI support (All CEP cores are now LLKI enabled)
* Known Issues:
- cep_diag (on Linux) has NOT been updated to work with the LLKI. Thus, running the tests that use
the CEP cores (e.g., cep_aes, cep_des3, etc.) will result in failure
- rv64si-p-dirty ISA test fails
- unit_simulations need to be updated to be compatible with the LLKI
##v3.01 - (19 December 2020)
* Removed used flash model reference in cep_tb.v
##v3.0 - (18 December 2020)
* Initial LLKI release with Surrogate Root of Trust
* AES core replaced with LLKI-enabled AES core, all other cores remain unchanged
##v2.71 - (2 November 2020)
* Corrected README.md issue
##v2.7 - (28 October 2020)
* Added support for RISC-V ISA tests (under ./cosim/isaTests)
* Updated license statements to BSD-2-Clause
* KNOWN ISSUES:
- The iCacheCoherency passes when running bare-metal simulation, but fails when running on the VC-707. There is an issue with
the iCache protocol that the tight-looped iCache coherency test results in one or more of the Rocket Cores (there are 4 in
the CEP) L1 iCache not getting the value associated with the most recent write to instruction memory.
Functionally, this should only cause an issue when dealing with self-modifying code, which is an atypical coding practice.
- The following cosim tests fail when run under RHEL using the "new" RISC-V toolchain:
- bareMetalTests/cacheCoherence
- isaTests/rv64mi-p-access
- isaTests/rv64ud-p-ldst
##v2.61 - (2 October 2020)
- Added initial simulation support for Cadence XCellium
- Cosim: Expanded DDR3 memory size to support "larger" bare-metal executables created by the new RISCV toolchain released with v2.6
##v2.6 - (18 September 2020)
* Rocket-Chip and Freedom repositories updated. Source responsitory list:
https://github.com/sifive/freedom/tree/8622a684e7e54d0a20df90659285b9c587772629 - Aug 19, 2020
https://github.com/chipsalliance/rocket-chip/tree/d2210f9545903fad40c9860389cdcf9c28515dba - Apr 2, 2020
https://github.com/sifive/fpga-shells/tree/19d0818deda5d295154992bd4e2c490b7c905df9 - Jan 28, 2020
https://github.com/sifive/sifive-blocks/tree/12bdbe50636b6c57c8dc997e483787fdb5ee540b - Dec 17, 2019
https://github.com/mcd500/freedom-u-sdk/tree/29fe529f8dd8e1974fe1743184b3e13ebb2a21dc - Apr 12, 2019
* riscv-tools (formerly under rocket-chip) now located in ./software/riscv-gnu-toolchain
* KNOWN ISSUES:
- The iCacheCoherency passes when running bare-metal simulation, but fails when running on the VC-707. There is an issue with
the iCache protocol that the tight-looped iCache coherency test results in one or more of the Rocket Cores (there are 4 in
the CEP) L1 iCache not getting the value associated with the most recent write to instruction memory.
Functionally, this should only cause an issue when dealing with self-modifying code, which is an atypical coding practice.
##v2.52 - (2 September 2020)
* Added ./doc/CEP_TestDescriptions.pdf
##v2.51 - (7 August 2020)
* Legacy unused core wrapper files (axi4lite and wb) removed
##v2.5 - (31 July 2020)
* All Unit-level testbenches have been expanded to optional support the Logic Locking Keying Interface (LLKI)
for both cycle-level and transactional-level modes
##v2.4 - (5 June 2020)
* CEP core test coverage expanded
* Unit testbenches transactional-level support added
* AES-derived and FIR-derived generated cores added
* Misc. bug fixes
##v2.3 - (17 April 2020)
* Added unit-level testbenches for all CEP cores. Co-simulation modified to generate unit-level test stimulus.
##v2.2 - (31 January 2020)
* Added co-simulation environment that supports both Bus Functional Model (BFM) and Baremetal simulation modes. Additional diagnostic capabilities within Linux.
##v2.1 - (31 October 2019)
* Integrated DES3, GPS, MD5, RSA, SHA256, DFT, IDFT, and IIR cores.
##v2.0 - (16 August 2019)
* Major Update: mor1k proceesor core replaced with the UCB Rocket-Chip within the SiFive Freedom U500 Platform. All modules have been updated to support TileLink natively. Currently only the AES and FIR cores have been integrated, but v2.1 will include the re-release of all the CEP cores.
##v1.2 - (15 November 2018)
* Major Update: The underlying bus has been converted from Wishbone-B4 to AXI4-Lite. All cores as well as the MOR1KX has been wrapped with translation modules. All the wrapping logic and interconnect are now in SystemVerilog.
* Regression Suite: In additon to each core's unit tests, a regression test suite has been included. When compiled by the or1k toolchain, it be loaded/synthesized into the CEP RAM block and run at boot time.
* Modelsim Testing: Unit-level and system-level modelsim-based testbenches added
* GPS clkgen: The GPS clock gen component has been moved to the top level of the CEP, simplifying its replacement when targetting an ASIC.
* Misc. bug fixes
##v1.1.1 - (27 September 2018)
* Added CEP\_utilization\_placed.rpt in implSummaries directory. This summarizes utlization of the CEP v1.1 targetted to the VC707 using Vivado 2018.1.
##v1.1 - (19 July 2018)
* Directory structure has been reorganized (details below)
* Upgraded to the non-deprecated mor1kx (added as a subnodule)
* Verified with both the pre-built and build-your-own version of the Newlib toolchain as described on [http://openrisc.io](http://openrisc.io)
* In addition to test vectors for each of the cores, some additional test_software, such as "hello world", have been added for reference
* Expanded testbench (details below)
* Bug fixes and general code cleanup [Additional details in the git commit history]
##v1.0 - Initial release (15 Aug 2017)
#### Return to the root CEP [README](./README.md) |
# Changelog
This changelog follows the format defined here: https://keepachangelog.com/en/1.0.0/
## [1.7.0] - 2022-06-18
FireSim bump for local (on-premises) FPGA and distributed metasimulation support. Hammer now supports the OpenROAD open-source EDA tools for a fully open-source RTL-to-GDS VLSI flow.
### Added
* Add a FireSim config with no mem port (#1172)
* Hammer OpenROAD plugins: Yosys (syn), OpenROAD (par), Magic (drc), Netgen (lvs) (#1183)
### Changed
* Bump FireSim to 1.14.0
* Give the PRCI widgets valnames to clean up module naming (#1152)
### Fixed
* Add missing Apache commons dependencies (fixes #1144) (#1147)
* Disable Boost for spike (#1168)
* VCS enhancements (#1150)
* Support multi-thread VCS simv option like FGP, Xprof etc.
* Idle tsi in the target thread
* Don't shallow clone submodules (revert #1064) (#1143)
* Remove extra spaces in FPGA makefile (#1135)
## [1.6.3] - 2022-04-06
FireSim bump for various fixes. Revert shallow cloning. Various CI fixes.
### Fixed
* Bump to FireSim 1.13.4 (changelog: https://github.com/firesim/firesim/blob/1.13.4/CHANGELOG.md#1134---2022-04-06)
* Revert shallow cloning.
* Various CI fixes.
## [1.6.2] - 2022-03-01
Minor fixes to FireSim.
### Fixed
* Bump to FireSim 1.13.3 (#1134)
## [1.6.1] - 2022-03-01
Minor fixes to FireSim.
### Fixed
* Bump to FireSim 1.13.2 (#1133)
## [1.6.0] - 2022-02-15
A more detailed account of everything included is included in the dev to master PR for this release: https://github.com/ucb-bar/chipyard/pull/913
### Added
* Diplomatic IOBinder-like approach to setting up PRCI across different deployment targets (#900)
* Default set of MMIO-controlled reset-setters and clock-gaters (#900)
* Added simulation makefile options `torture` and `torture-overnight` for running Torture (#992)
* FSDB waveform support (#1072, #1102)
* Use GitHub Actions for CI (#1004, #999, #1090, #1092)
* Add MAKE variable in `build-toolchains.sh` (#1021)
* Cleanup GH issue and PR templates (#1029, #1032)
* Add support for Ibex core (#979)
* Add system bus width fragment (#1071)
* Add support for FSDB waveform files (#1072, #1102)
* Document simulator timeout settings (#1094)
* Add FFT Generator (#1067)
* Add waveforms for post-PNR and power (#1108)
* Have PRCI control registers use clock of corresponding bus (#1109)
* Add check to verify that user is running on tagged release (#1114)
* Hammer tutorial in Sky130 (#1115)
### Changed
* Bump CVA6 (#909 )
* Bump Hammer tutorial for ASAP7 r1p7 (#934)
* Use Published Chisel, FIRRTL, Treadle, FIRRTLInterpreter packages instead of building from source. #1054
* Change serialTL width to 32. Speeds up simulations (#1040)
* Update how sbt flag is overridden (by using `SBT_BIN` variable) (#1041)
* Use published dependencies for Chisel, FIRRTL, Treadle, and FIRRTLInterpreter (#1054)
* Split `ConfigFragments.scala` into multiple files (with more organization) (#1061)
* Avoid initializing nvdla software by default (#1063)
* Update ASAP to 1.7 in Hammer (#934)
* Shorten Gemmini docs and point to repo (#1078)
* Bump Gemmini to 0.6.2 (#1083)
* Use python2 for tracegen script (#1107)
* Bump to Chisel/FIRRTL 3.5.1 (#1060, #1113)
* Bump to FireMarshal 1.12.1 (#1116)
* Bump to FireSim 1.13.0 (#1118 )
### Fixed
* Fix UART portmap for Arty (#968)
* Support changing make variable `MODEL` from the cmdline (#1030)
* Force FIRRTL to 1.4.1 (#1052)
* Fix MMIO IOBinder (#1045)
* Mask `fd` warning when running make (#1057)
* Fix Sodor 5-stage hazard check (#1086)
* Fix Sodor val io issue (#1089)
* Fix BOOM reference in Readme (#1104)
* Fix waveforms for post-P&R power analysis (#1108)
### Removed
* Remove duplicate `WithUARTIOCells` fragment (#1047)
* Remove MaxPermSize in java variables (#1082)
* Remove support for CircleCI (#1105)
## [1.5.0] - 2021-06-13
A more detailed account of everything included is included in the dev to master PR for this release: https://github.com/ucb-bar/chipyard/pull/773
### Added
* FireMarshal support for FPGA prototypes (#849)
* Hammer update to include power estimation flows, rail analysis, hierarchical sim support, and improved ASAP7 plugin with dummy SRAMs (#886)
* Docker image
* Support specifying architecture when building tools. (#802)
* Add Config fragments: WithMultiRoCCFromBuildRoCC, PMP (#809, #821)
* Add support for simulating an AXI memory interface over the default TL serial link (#812)
* Add option to add async queues between chip-serialIO and harness serdes (#828)
* Spike support for multiple extensions, and add sha3 spike model to esp-tools (#837, #897)
* Default generator support for I2C and PWM (#885)
### Changed
* Gemmini bump to version 0.5
* FireSim bump to version 1.12
* FireMarshal bump to version 1.12
* Changes default FireSim frequency from 3.2 GHz (dual clock domains) to 1 GHz (single clock domain)
* Bump pygments from 2.2.0 to 2.7.4 in docs
* Hammer tutorial example is now a TinyRocketConfig (#886)
* Sha3 Spike model moved from sha3 repo to esp-isa-sim
### Fixed
* Avoid permissions conflict on shared protocjar.webcache (#774)
* Passing MBus clock frequency to SimDRAM (#790)
* Fix parsing of --ignore-qemu option (#791)
* FPGA Prototype - Support Adding Pullup R's to Bringup GPIOs (#806)
* Use "tile" instead of "core" to assign frequencies in WithTileFrequency config. fragment (#807)
* Fix IOCell generation for clock and reset to use IOCellKey (#824)
* Fix TileResetCtrl to be ahead of reset synchronizers (#826)
* Fix memory alignment in character count RoCC test (#853)
* Synchronize JTAG reset to JTAG.TCK. (#859)
* Updates to system requirements scripts (#874)
* Rocket-dsp-utils integration and cleanup for dsptools (#888)
### Removed
* Dummy DCO collateral from Hammer tutorial example (#886)
## [1.4.0] - 2021-01-19
A more detailed account of everything included is included in the dev to master PR for this release: https://github.com/ucb-bar/chipyard/pull/599
### Added
* OpenSBI Support (#633)
* Support for Diplomacy-based clocking (#614, #682)
* Support for Diplomacy-based IOBinders (#699)
* Sodor core integration (#648)
* Simple Divider-Only PLL for Multiclock RTL Simulation (#676)
* Enable parallel Hammer simulations (#600)
* OpenRoad nangate45 Hammer backend (#608)
* Add support for "LBWIF" backing memory through serialized TileLink (#673)
* Add variable to control FIRRTL logging verbosity (#627)
* Add RANDOM_SEED variable to set random init for VCS and Verilator simulations (#629)
* Fast LoadMem support (#635)
* Multithreaded Verilator (#654)
* Support for custom Verilator optimization flags (#728)
* Add config-fragment to use broadcast manager instead of L2 for coherence (#721)
* Added optional ignore QEMU flag to `build-toolchains.sh` (#709)
* Split `JAVA_ARGS` into `JAVA_OPTS` and `SBT_OPTS` (#719)
* Experimental support for SBT thin client. Enable with `export ENABLE_SBT_THIN_CLIENT=1` (https://github.com/sbt/sbt/pull/5620) (#719)
* Helper `make` targets to launch SBT console (`sbt`) and shutdown/start thin server (<start/shutdown>-sbt-server) (#719)
* Allow users to override `CC` and `CXX` for `build-toolchains.sh` (#739)
* Support VCU118/Arty local FPGA prototypes through `fpga-shells` (#747)
* A 16-core LargeBOOM configuration has been added to FireChip to highlight the resource-optimizing platform configurations added to FireSim in firesim/firesim#636 (#756)
### Changed
* Bump Chisel to 3.4.1.x (#742, #719, #751)
* Bump RocketChip to a7b016e (#742, #719)
* Bump FireSim to 1.11
* Bump Gemmini to v0.5
* Bump to SBT 1.4.4 (#719)
* Split IOBinders into IOBinders and HarnessBinders | punch out clocks to harness for simwidgets and bridges (#670, #674)
* Have FireSim build recipes use Chipyard configs rather than FireChip configs (#695)
* FireMarshal boot default to OpenSBI rather than BBL (#633)
* Override default baud rate for FireChip (#625)
* DTM only supports HTIF in DMI mode (#672)
* Unify HTIF implementation between Chipyard and Firesim (#683)
* Renamed Ariane to CVA6 (#710)
* `build.sbt` refactoring/fixes for RC/Chisel/Firrtl bump (#719)
* Use `; x; y; z;` syntax to run multiple SBT commands (#719)
* CI Improvements: Cleanup `check-commit` printout. Don't transfer `.git` folders. (#750)
### Fixed
* Multi-SHA3 configs (#597)
* Allow dramsim_ini folder to be set at the command line (#598)
* Emit HTIF Node in device tree (#607)
* Fixes for AXI4 MMIO and FBus ports (#618)
* Only punch realistic subset of DebugIO through chiptop | default to JTAG+Serial (#664)
* IceNet bug fixes (#720)
* smartelf2hex.sh bug fixes (#677, #693)
* env.sh zsh compatibility (#705)
* build-toolchains.sh bug fixes (#745 #739)
* Bump Dromajo to work with older version of glibc (#709)
### Removed
* Support for synchronous ChipTop reset (#703)
* Split `JAVA_ARGS` into `JAVA_OPTS` and `SBT_OPTS` (#719)
## [1.3.0] - 2020-05-31
A more detailed account of everything included is included in the dev to master PR for this release: https://github.com/ucb-bar/chipyard/pull/500
### Added
* A new Top-level module, ChipTop, has been created. ChipTop instantiates a "system" module specified by BuildSystem. (#480)
* A new BuildSystem key has been added, which by default builds DigitalTop (#480)
* The IOBinders API has changed. IOBinders are now called inside of ChipTop and return a tuple3 of (IO ports, IO cells, harness functions). The harness functions are now called inside the TestHarness (this is analogous to the previous IOBinder functions). (#480)
* IO cell models have been included in ChipTop. These can be replaced with real IO cells for tapeout, or used as-is for simulation. (#480)
* CI now checks documentation changes (#485)
* Support FireSim multi-clock (#468)
* Allows make variables to be injected into build system (#499)
* Various documentation/comment updates (#511,#517,#518,#537,#533,#542,#570,#569)
* DSPTools documentation and example (#457, #568)
* Support for no UART configs (#536)
* Assemble firrtl-test.jar (#551)
* Add SPI flash configurations (#546)
* Add Dromajo + FireSim Dromajo simulation support (#523, #553, #560)
* NVDLA integration (#505, #559, #580)
* Add support for Hammer Sim (#512,#581,#580,#582)
### Changed
* Bump FireSim to version 1.10 (#574,#586)
* Bump BOOM to version 3.0 (#523, #574,#580)
* Bump Gemmini to version 0.3 (#575, #579)
* Bump SPEC17 workload (#504, #574)
* Bump Hwacha for fixes (#580)
* Bump SHA3 for Linux 5.7rc3 support (#580)
* Bump Rocket Chip to commit 1872f5d (including stage/phase compilation) (#503,#544)
* Bump FireMarshal to version 1.9.0 (#574)
* Chisel 3.3 and FIRRTL 1.3 (#503,#544)
* BuildTop now builds a ChipTop dut module in the TestHarness by default (#480)
* The default for the TOP make variable is now ChipTop (was Top) (#480)
* Top has been renamed to DigitalTop (#480)
* Bump libgloss (#508, #516, #580)
* The default version of Verilator has changed to v4.034 (#547). Since this release adds enhanced support for Verilog timescales, the build detects if Verilator v4.034 or newer is visible in the build environment and sets default timescale flags appropriately.
* Use Scalatests for FireSim CI (#528)
* Cleanup Ariane pre-processing (#505)
* Modify Issue Template to be more explicit (#557)
* FireChip uses Chipyard generator (#554)
* Have all non-synthesizeable constructs in test harness (#572)
### Fixed
* Aligned esp-tools spike with Gemmini (#509)
* Fix debug rule in Verilator (#513)
* Clean up SBT HTTP warnings (#526,#549)
* Artefacts dropped in FireSim (#534)
* Working IceNet + TestChipIP Unit Tests (#525)
* Don't initialize non-existent Midas submodule (#552)
* Verilator now supports +permissive similar to VCS (#565)
* Fix direction of IOCell OE (#586)
### Deprecated
* N/A
### Removed
* Removed MIDAS examples CI (until a better solution that is faster is found) (#589)
## [1.2.0] - 2020-03-14
A more detailed account of everything included is included in the dev to master PR for this release: https://github.com/ucb-bar/chipyard/pull/418
### Added
* Ring Topology System Bus NoC (#461)
* Integration of the Ariane core into Chipyard (#448)
* FireMarshal now generates an extra copy of linux kernel with dwarf debugging info for use in FirePerf (#427)
* Add option to use blackboxed SimDRAM instead of SimAXIMem (#449)
* Log `init-submodules` script (#433)
* Moved the Docker image used for CI into Chipyard (prev. in BOOM) (#463)
### Changed
* Bump FireSim to 1.9.0 - Includes FirePerf TracerV Flame Graph features
* IOBinders and BuildTop unification between FireChip and Chipyard (#390)
* Bump BOOM to version 2.2.4 (#463)
* Bump Gemmini to version 0.2 (#469)
* Update to CircleCI 2.1 config. syntax and cleanup CI file (#421)
* FireMarshal moved from FireSim to Chipyard (#415)
* Rename config. mixins to config fragments (#451)
### Fixed
* `git status` should be clean. (Although you will need to manually cleanup the libgloss and qemu directories after first setup). (#411, #414)
* Fix Hetero. BOOM + Rocket + Hwacha config (#413)
* Fix VCS stdout (#417)
* Add a git version check to the init scripts and make them work outside of the repo root (#459)
* Fix generation of env.sh for zsh (#435)
* GCD example bug (#465)
### Deprecated
* N/A
### Removed
* N/A
## [1.1.0] - 2020-01-25
A more detailed account of everything included is included in the dev to master PR for this release: https://github.com/ucb-bar/chipyard/pull/367
### Added
* Gemmini generator and config (PR #356 )
* Coremark + SPEC2017 benchmarks (PR #326, #338, #344)
* Add Hwacha tests to CI (PR #284)
* Add Hwacha tests to benchmark and assembly test suites (PR #284)
* Added Hwacha + Large Boom Config (PR #315)
* Add multi-core config with a small Rocket core attached on the side (PR #361 )
* Add UART and Test Harness UART Adapter to all configurations (PR #348)
* User can specify $RISCV directory in build-toolchains.sh (PR #334)
* Checksum offload in IceNet (PR #364)
### Changed
* Rocketchip bumped to commit [4f0cdea](https://github.com/chipsalliance/rocket-chip/tree/4f0cdea85c8a2b849fd582ccc8497892001d06b0), for chisel version 3.2.0 which includes Async reset support
* FireSim release 1.8.0
* FireMarshal release 1.8.0
* BOOM release 2.2.3 (PR #397)
* baremetal software toolchains, using libgloss and newlib instead of in-house syscalls.
* Add toolchain specific `env.sh` (PR #304)
* `run-binary`-like interface now dumps `.log` (stdout) and `.out` (stderr) files (PR #308)
* Split the VLSI build dir on type of design (PR #331)
* Reduce Ctags runtime and only look at scala, C, C++, and Python files (PR #346)
* Top/Top-level-traits now behave as a configurable generator (PR #347)
* Test suite makefrag generator includes Hwacha test suites (PR #342)
### Fixed
* Fix VLSI makefile requirements for SRAM generation (PR #318)
* Only filter header files from common simulation files (PR #322)
* Bump MacroCompiler for bugfixes (PR #332)
* commit-on-master check has specific behavior based on source branch (PR #345)
* Makefile filtering of blackbox resource files only omits .h files (PR #322)
* Parallel make fixed (PR #386 #392)
### Deprecated
* No longer need to specify `WithXTop`, default `Top` is a generator for all `Top`s (PR #347)
### Removed
* N/A
## [1.0.0] - 2019-10-19
### Added
* This repository used to be "project-template", a template for Chisel-based projects. Through tighter integration of multiple projects from the Berkeley Architecture Research group at UC Berkeley, this repository is re-released as Chipyard - a framework for agile hardware development of RISC-V based Systems-on-Chip.
|
Contributing to Chipyard
=============================
### Branch management:
1) github:com/ucb-bar/chipyard: main = pre-release non-stable branch with latest features. All merges to main must go through PR.
2) github:com/ucb-bar/chipyard: specific tag / tagged branch = official chipyard release.
3) Other dependencies pointed at by Chipyard (e.g. firesim, boom): master/main should be the version submoduled in ucb-bar/chipyard main.
|
BSD 3-Clause License
Copyright (c) 2017-2020, The Regents of the University of California (Regents)
All Rights Reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its
contributors may be used to endorse or promote products derived from
this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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|
Common Evaluation Platform Licensing Information
Title : aes
Source : https://opencores.org/project,tiny_aes
CEP Directory : ./generators/mitll-blocks/src/main/resources/vsrc/aes
License Description : Apache 2.0
License terms : http://www.apache.org/licenses/LICENSE-2.0.html
Function : This core provides a standard AES encryption function, where the key is 192 bits long. It will be integrated as a HW accelerator into the SoC.
Title : des3
Source : http://asics.ws/v6/free-ip-cores/#
CEP Directory : ./generators/mitll-blocks/src/main/resources/vsrc/des3
License Description : BSD-based
License terms : Copyright (C) 2000-2009, ASICs World Services, LTD. , AUTHORS All rights reserved. Redistribution and use in source, netlist,
binary and silicon forms, with or without modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer
in the documentation and/or other materials provided with the distribution.
Neither the name of ASICS World Services, the Authors and/or the names of its contributors may be used to endorse or promote
products derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING,
BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Function : This core provides a standard MD5 hash function. It will be integrated as a HW accelerator into the SoC.
Title : dsp (FIR and IIR filters)
Source : Copyright (c) 2005-2014 Peter A. Milder for the Spiral Project, Carnegie Mellon University
CEP Directory : ./generators/mitll-blocks/src/main/resources/vsrc/dsp
License Description : BSD
License Terms : http://www.opensource.org/licenses/bsd-license.php
Function : Provides logic for the FIR and IIR
Title : dsp (DFT) and IDFT)
Source : Copyright (c) 2005-2014 Peter A. Milder for the Spiral Project, Carnegie Mellon University
CEP Directory : ./generators/mitll-blocks/src/main/resources/vsrc/generated_dsp_code
License Description : Custom
License Terms : The generated code is NOT included within the CEP repository due to license constraints.
Pointers to generating these files are included for information purposes only.
This design is provided for internal, non-commercial research use only
and is not for redistribution, with or without modifications.
You may not use the name "Carnegie Mellon University" or derivations
thereof to endorse or promote products derived from this software.
THE SOFTWARE IS PROVIDED "AS-IS" WITHOUT ANY WARRANTY OF ANY KIND, EITHER
EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY
THAT THE SOFTWARE WILL CONFORM TO SPECIFICATIONS OR BE ERROR-FREE AND ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
TITLE, OR NON-INFRINGEMENT. IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY
BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO DIRECT, INDIRECT,
SPECIAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF, RESULTING FROM, OR IN
ANY WAY CONNECTED WITH THIS SOFTWARE (WHETHER OR NOT BASED UPON WARRANTY,
CONTRACT, TORT OR OTHERWISE).
Function : Provides logic for the DFT and IDFT cores
Title : gps
Source : MIT Lincoln Laboratory
CEP Directory : ./generators/mitll-blocks/src/main/resources/vsrc/gps
License Description : BSD 2-Clause
License terms : https://opensource.org/licenses/BSD-2-Clause
Function : Surrogate GPS core for CA, P, and L code generation
: L-code leverages the aes core mentioned above
Title : md5
Source : http://pancham.sourceforge.net/
CEP Directory : ./generators/mitll-blocks/src/main/resources/vsrc/md5
License Description : LGPL 2.1
License terms : https://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt
Function : This core provides a standard MD5 hash function. It will be integrated as a HW accelerator into the SoC.
Title : rsa
Source : http://git.level2crm.com/cryptech/core-math-modexp/tree/master
CEP Directory : ./generators/mitll-blocks/src/main/resources/vsrc/rsa
License Description : LGPL-ish
License terms : // Author: Joachim Strombergson
// Copyright (c) 2013, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Function: This core provides the mathematical base (modular exponentiation) required to implement a standard 2048-bit
RSA public-key encryption function. It will be integrated as a HW accelerator into the SoC.
Title : sha256
Source : http://git.level2crm.com/cryptech/core-hash-sha256/tree/master
CEP Directory : ./generators/mitll-blocks/src/main/resources/vsrc/sha256
License Description : LGPL-ish
License terms : // Author: Joachim Strombergson
// Copyright (c) 2013, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Function : This core provides a standard SHA hash function, where the resulting hash value is 256 bits. It will be integrated as a HW accelerator into the SoC.
Title : opentitan
Source : https://github.com/lowRISC/opentitan
CEP Directory : ./opentitan
License Description : Apache License v2.0
License Terms : https://github.com/lowRISC/opentitan/blob/master/LICENSE
Function : OpenTitan is the first open source project building a transparent, high-quality reference design and integration guidelines for silicon root of trust (RoT) chips.
Main website: www.opentitan.org
Title : SD Card model for CEP Co-Simulation
Source : SD SPI Simulation Model originally released by tsuhuai.chan@gmail.com and subsequented extracted from "Warke, Tejas Pravin, "Verification of
SD/MMC Controller IP Using UVM" (2018). Thesis. Rochester Institute of Technology"
CEP Directory : ./sims/cep_cosim/dvt/sd_spi_model.v
License Description : Unknown
License Terms : Unknown
Function : Provides an SD Card Model for simulation of a "full boot" of the CEP
Title : UART Model for CEP Co-Simulation
Source : https://github.com/ben-marshall/uart
CEP Directory : ./sims/cep_cosim/dvt/uart_rx.v
License Description : MIT License
License Terms : https://github.com/ben-marshall/uart/blob/master/LICENSE
Function : Provides a simple UART Receiver for the CEP testbench
Title : Free FFT and convolution (C)
Source : https://www.nayuki.io/page/free-small-fft-in-multiple-languages
CEP Directory : ./sims/cep_cosim/drivers/cep_tests/fft[.cc/.h]
License Description : MIT License
License Terms : Copyright (c) 2018 Project Nayuki. (MIT License)
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
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* - The above copyright notice and this permission notice shall be included in
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* - The Software is provided "as is", without warranty of any kind, express or
* implied, including but not limited to the warranties of merchantability,
* fitness for a particular purpose and noninfringement. In no event shall the
* authors or copyright holders be liable for any claim, damages or other
* liability, whether in an action of contract, tort or otherwise, arising from,
* out of or in connection with the Software or the use or other dealings in the
* Software.
Title : libgpiod-example
Source : https://github.com/starnight/libgpiod-example
CEP Directory : ./software/linux/gpiotest
License Description : BSD 3-Clause
Title : Chipyard VC707 FPGA build target
Source : https://github.com/necst/chipyard-vc707
CEP Directory : ./fpga/src/main/scala/vc707
License Description : BSD 3-Clause
|
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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# Chipyard Framework [](https://github.com/ucb-bar/chipyard/actions)
## Quick Links
* **Stable Documentation**: https://chipyard.readthedocs.io/
* **User Question Forum**: https://groups.google.com/forum/#!forum/chipyard
* **Bugs and Feature Requests**: https://github.com/ucb-bar/chipyard/issues
## Using Chipyard
To get started using Chipyard, see the stable documentation on the Chipyard documentation site: https://chipyard.readthedocs.io/
## What is Chipyard
Chipyard is an open source framework for agile development of Chisel-based systems-on-chip.
It will allow you to leverage the Chisel HDL, Rocket Chip SoC generator, and other [Berkeley][berkeley] projects to produce a [RISC-V][riscv] SoC with everything from MMIO-mapped peripherals to custom accelerators.
Chipyard contains processor cores ([Rocket][rocket-chip], [BOOM][boom], [CVA6 (Ariane)][cva6]), accelerators ([Hwacha][hwacha], [Gemmini][gemmini], [NVDLA][nvdla]), memory systems, and additional peripherals and tooling to help create a full featured SoC.
Chipyard supports multiple concurrent flows of agile hardware development, including software RTL simulation, FPGA-accelerated simulation ([FireSim][firesim]), automated VLSI flows ([Hammer][hammer]), and software workload generation for bare-metal and Linux-based systems ([FireMarshal][firemarshal]).
Chipyard is actively developed in the [Berkeley Architecture Research Group][ucb-bar] in the [Electrical Engineering and Computer Sciences Department][eecs] at the [University of California, Berkeley][berkeley].
## Resources
* Chipyard Stable Documentation: https://chipyard.readthedocs.io/
* Chipyard (x FireSim) Tutorial: https://fires.im/tutorial
* Chipyard Basics slides: https://fires.im/isca22-slides-pdf/02_chipyard_basics.pdf
* Chipyard Tutorial Exercise slides: https://fires.im/isca22-slides-pdf/03_building_custom_socs.pdf
## Need help?
* Join the Chipyard Mailing List: https://groups.google.com/forum/#!forum/chipyard
* If you find a bug or would like propose a feature, post an issue on this repo: https://github.com/ucb-bar/chipyard/issues
## Contributing
* See [CONTRIBUTING.md](/CONTRIBUTING.md)
## Attribution and Chipyard-related Publications
If used for research, please cite Chipyard by the following publication:
```
@article{chipyard,
author={Amid, Alon and Biancolin, David and Gonzalez, Abraham and Grubb, Daniel and Karandikar, Sagar and Liew, Harrison and Magyar, Albert and Mao, Howard and Ou, Albert and Pemberton, Nathan and Rigge, Paul and Schmidt, Colin and Wright, John and Zhao, Jerry and Shao, Yakun Sophia and Asanovi\'{c}, Krste and Nikoli\'{c}, Borivoje},
journal={IEEE Micro},
title={Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs},
year={2020},
volume={40},
number={4},
pages={10-21},
doi={10.1109/MM.2020.2996616},
ISSN={1937-4143},
}
```
* **Chipyard**
* A. Amid, et al. *IEEE Micro'20* [PDF](https://ieeexplore.ieee.org/document/9099108).
* A. Amid, et al. *DAC'20* [PDF](https://ieeexplore.ieee.org/document/9218756).
* A. Amid, et al. *ISCAS'21* [PDF](https://ieeexplore.ieee.org/abstract/document/9401515).
These additional publications cover many of the internal components used in Chipyard. However, for the most up-to-date details, users should refer to the Chipyard docs.
* **Generators**
* **Rocket Chip**: K. Asanovic, et al., *UCB EECS TR*. [PDF](http://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-17.pdf).
* **BOOM**: C. Celio, et al., *Hot Chips 30*. [PDF](https://old.hotchips.org/hc30/1conf/1.03_Berkeley_BROOM_HC30.Berkeley.Celio.v02.pdf).
* **SonicBOOM (BOOMv3)**: J. Zhao, et al., *CARRV'20*. [PDF](https://carrv.github.io/2020/papers/CARRV2020_paper_15_Zhao.pdf).
* **COBRA (BOOM Branch Prediction)**: J. Zhao, et al., *ISPASS'21*. [PDF](https://ieeexplore.ieee.org/document/9408173).
* **Hwacha**: Y. Lee, et al., *ESSCIRC'14*. [PDF](http://hwacha.org/papers/riscv-esscirc2014.pdf).
* **Gemmini**: H. Genc, et al., *DAC'21*. [PDF](https://arxiv.org/pdf/1911.09925).
* **Sims**
* **FireSim**: S. Karandikar, et al., *ISCA'18*. [PDF](https://sagark.org/assets/pubs/firesim-isca2018.pdf).
* **FireSim Micro Top Picks**: S. Karandikar, et al., *IEEE Micro, Top Picks 2018*. [PDF](https://sagark.org/assets/pubs/firesim-micro-top-picks2018.pdf).
* **FASED**: D. Biancolin, et al., *FPGA'19*. [PDF](https://people.eecs.berkeley.edu/~biancolin/papers/fased-fpga19.pdf).
* **Golden Gate**: A. Magyar, et al., *ICCAD'19*. [PDF](https://davidbiancolin.github.io/papers/goldengate-iccad19.pdf).
* **FirePerf**: S. Karandikar, et al., *ASPLOS'20*. [PDF](https://sagark.org/assets/pubs/fireperf-asplos2020.pdf).
* **Tools**
* **Chisel**: J. Bachrach, et al., *DAC'12*. [PDF](https://people.eecs.berkeley.edu/~krste/papers/chisel-dac2012.pdf).
* **FIRRTL**: A. Izraelevitz, et al., *ICCAD'17*. [PDF](https://ieeexplore.ieee.org/document/8203780).
* **Chisel DSP**: A. Wang, et al., *DAC'18*. [PDF](https://ieeexplore.ieee.org/document/8465790).
* **FireMarshal**: N. Pemberton, et al., *ISPASS'21*. [PDF](https://ieeexplore.ieee.org/document/9408192).
* **VLSI**
* **Hammer**: E. Wang, et al., *ISQED'20*. [PDF](https://www.isqed.org/English/Archives/2020/Technical_Sessions/113.html).
## Acknowledgements
This work is supported by the NSF CCRI ENS Chipyard Award #201662.
[hwacha]:https://www2.eecs.berkeley.edu/Pubs/TechRpts/2015/EECS-2015-262.pdf
[hammer]:https://github.com/ucb-bar/hammer
[firesim]:https://fires.im
[ucb-bar]: http://bar.eecs.berkeley.edu
[eecs]: https://eecs.berkeley.edu
[berkeley]: https://berkeley.edu
[riscv]: https://riscv.org/
[rocket-chip]: https://github.com/freechipsproject/rocket-chip
[boom]: https://github.com/riscv-boom/riscv-boom
[firemarshal]: https://github.com/firesim/FireMarshal/
[cva6]: https://github.com/openhwgroup/cva6/
[gemmini]: https://github.com/ucb-bar/gemmini
[nvdla]: http://nvdla.org/
|
[//]: # (Copyright 2022 Massachusetts Institute of Technology)
[//]: # (SPDX short identifier: BSD-2-Clause)
# ---- ARCHIVED REPOSITORY ----
## The CEP now resides here [here](https://www.github.com/CommonEvaluationPlatform/CEP.git).
# Common Evaluation Platform v4.2
[](https://zenodo.org/badge/latestdoi/108179132)
[](https://opensource.org/licenses/BSD-2-Clause)
<p align="center">
<img src="./cep_docs/cep_logo.jpg" width="375" height="159">
</p>
<p align="center">
Copyright 2022 Massachusetts Institute of Technology
</p>
<p align="center">
<img src="./cep_docs/cep_architecture.jpg" width="1114" height="450">
</p>
<p align="center">
<img src="./cep_docs/related_logos.jpg" width="442" height="120">
</p>
The Common Evaluation Platform (CEP) is an SoC design that contains only license-unencumbered, freely available components. The CEP includes a range of accelerator cores coupled with a key delivery mechanism, and parametrically-defined challenge modules which can be synthesized to support developmental testing. The implementation of the CEP includes a comprehensive verification environment to ensure modifications do not impede intended functionality. It is intended to be targeted to either an FPGA or ASIC implementation.
Please check the [CEP changelog](./CHANGELOG.CEP.md) for release history.
Beginning with CEP v4.0, the platform has been ported to the UCB Chipyard Framework. The original Chipyard Readme can be found [here](./README.Chipyard.md).
Throughout the CEP READMEs, `<CEP_ROOT>` refers to the root directory of the cloned CEP repository.
## Pre-requisites (validated test/build configurations):
The following items describe the configuration of the system that CEP has been developed and tested on:
* Ubuntu 18.04 LTS x86_64 with Modelsim Questa Sim-64 v2019.1 (for co-simulation)
* Red Hat Enterprise Linux 7 with Cadence XCELIUMAGILE20.09.001, VMANAGERAGILE20.06.001
* Xilinx Vivado 2020.1 (needed for building FPGA targets)
- Plus Digilent Adept Drivers for programming the FPGA target, https://reference.digilentinc.com/reference/software/adept/start?redirect=1#software_downloads)
* Terminal emulator (such as `minicom`)
* bash
Other configurations may work, but they have not been explicitly verified.
Instructions on how to modelsim, xcelium, and Vivado are beyond the scope of this README.
## Setting up your environment
To build the CEP, several packages and toolsets must be installed and built. The typical steps are listed below. Additional information can be found in the Chipyard Documentation [here](https://chipyard.readthedocs.io/en/latest/Chipyard-Basics/index.html).
A note about proxies: If your system is behind a proxy, you'll want to ensure your environment is properly configured. Exact details vary by system, but the proxy needs to be available to apt / yum, curl, and sbt (Simple Build Tool for Scala)
If using RHEL7, you need to ensure gcc 7.x.x+ is installed. This can be found in the `rhel-workstation-rhscl-7-rpms` or `rhel-server-rhscl-7-rpms` repos, whose available is RHEL subscription dependent. Once the repo is enabled, the appropriate gcc can be installed by running `sudo yum install devtoolset-7-gcc-c++`. Once installed, you want to run `scl enable devtoolset-7 bash` (or whatever version you have installed) to ensure g++ maps to the new version.
* Install git if not already present on your system
* Ubuntu - `sudo apt install git`
* RHEL7 - `sudo yum install git`
* Clone the CEP repository, change to the directory of the clone
* `git clone https://github.com/mit-ll/CEP.git`
* Install package dependencies. Copies of these files can also be found in the Chipyard Documentation listed above
* Ubuntu - `./scripts/ubuntu-reqs.sh`
* RHEL7 - `./scripts/centos-reqs.sh`
* Initialize all the git submodules (including FPGA-related submodules). There may be a warning about this not being a true chipyard repository which you can answer yes to.
* `./scripts/init-submodules-no-riscv-tools.sh`
* `./scripts/init-fpga.sh`
* Build the RISC-V Toolchain.
* Depending on your available hardware, you can expedite the build by executing `export MAKEFLAGS=-jN` prior to running the build script. N is the number of cores you can devote to the build.
* `./scripts/build-toolchains.sh riscv-tools`
* RHEL7: The chipyard build needs make v4.x or later, which is not included in the default packages. Recommend building from source (https://ftp.gnu.org/gnu/make/). Once installed, you can force the version of make used using the following: `MAKE=/usr/local/bin/make ./scripts/build-toolchains.sh riscv-tools`
* It is advisable to move the compiled toolchain outside of the current repo if you plan to have multiple CEP working directories. Complete directions are beyond the scope of this document, but they do include moving the `riscv-tools-install` directory and `env-riscv-tools.sh` file. Modification of the aforementioned file as well as `env.sh` will required for smooth operation
* Sometimes the toolchain build may fail. One may need to run the build several times.
* Once the toolchain is built, your want to source the new environment script: `source <CEP_ROOT>/env.sh`.
## Repository Directory Structure
Providing a complete directory structure is impractical, but some items are highlighted here. It is worth noting that most of the structure is inherited from Chipyard.
```
<CEP_ROOT>
|- ./sims/cep_cosim/ -
| Defines the CEP co-simulation evironment for performing "chip" level simulations of the CEP in
| either bare metal or bus functional model (BFM) mode.
|- ./generators/mitll-blocks/
| |- src/main/scala - Contains all the custom CEP Chisel code
| |- src/main/resources/vsrc/ - SystemVerilog / Verilog files associated with the CEP build
| |- generated_dsp_code - Location to place the `dft_top.v` and `idft_top.v'
| |- opentitan - Soft-link to the opentitan submodule located at ./opentitan
| |- aeees - Challenge module. Read the README.md in this directory for more information.
| |- auto-fir - Challenge module. Read the README.md in this directory for more information.
| |- shaaa - Challenge module. Read the README.md in this directory for more information.
|- ./cep_docs - Documents and images unique to the CEP
|- ./software/baremetal - Examples of bare metal code that can be run on the Arty100T FPGA target
independent of the CEP Co-Simulation environment
```
### Building the CEP FPGA
Multiple Chipyard *SUB_PROJECTS* have been defined for the CEP when targetting FPGA Development boards.
These subprojects define the system configuration and are as follows:
`cep_arty100t` - Arty100T Development Board
- 50 MHz Core Frequency
- 98% LUT Utilization
- 1x WithNBigCore
- CEP Registers
- AES Core
- Surrogate Root of Trust (SRoT)
`cep_vc707` - VC707 Development Board
- 100 MHz Core Frequency4
- 11% LUT Utilization
- 1x WithNBigCore
- CEP Registers
- AES Core
- Surrogate Root of Trust (SRoT)
`cep_big_vc707` - VC707 Development Board
- 100 MHz Core Frequency
- 70% LUT Utilization
- 4x WithNBigCores
- CEP Registers
- AES Core
- DES3 Core
- FIR Core
- IIR Core
- DFT Core
- IDFT Core
- MD5 Core
- 4x GPS Cores
- 4x SHA-256 Cores
- RSA Core
- Surrogate Root of Trust
`cep_vcu118` - VCU118 Development Board
- 100 MHz Core Frequency
- 5% LUT Utilization
- 1x WithNBigCore
- CEP Registers
- AES Core
- Surrogate Root of Trust (SRoT)
Assuming the Vivado environment scripts have been sourced within your current shell, the following commands can be used to build and program the FPGA *SUB_PROJECT*. Programming requires that the digilent drivers have been installed and that you have a USB connection to the JTAG USB-port of you preffered FPGA board.
Default CEP builds can be customized by following the instructions in the Chipyard documentation.
The FPGA boards will configure from FLASH or JTAG based on the state of the MODE jumper. Additional information can be found:
* Arty100T - [here](https://digilent.com/shop/arty-a7-artix-7-fpga-development-board/).
* VC707 - [here](https://www.xilinx.com/products/boards-and-kits/ek-v7-vc707-g.html/).
* VCU118 - [here](https://www.xilinx.com/products/boards-and-kits/vcu118.html/).
```
cd <REPO_ROOT>/fpga
make SUB_PROJECT=<cep_arty100t | cep_vc707 | cep_vcu118>
./program_<arty100t | vc707 | vcu118>_flash.sh - Create the MCS file & program the development board's flash. Power needs to be cycled or the *PROG* button needs to be asserted to reboot with the new configuration.
OR
./program_<arty100t | vc707 | vcu118>_jtag.sh - Program the FPGA via JTAG. System will automatically reset or you can use the *RESET* button.
```
### Building Bare Metal software for the CEP FPGA
The Arty100T shares a single microUSB connector for JTAG and UART, while the VC707 and VCU118 have seperate ports for each.
For the Arty100T, connect a Digilent SD or microSD PMOD board o connector JA. For the VCU118, connect the same to the PMOD connector on the right side of the board. The PMOD connectors can be ordered from Digikey, Digilent, or other distributors.
Additional information can be found here: (https://digilent.com/shop/pmod-sd-full-sized-sd-card-slot/ or https://digilent.com/shop/pmod-microsd-microsd-card-slot/).
As noted, for the Arty100T the microUSB port uses an FTDI chip to provide both JTAG and UART functionality. Your system may differ, but typically the UART shows up as `/dev/ttyUSB0` or `/dev/ttyUSB1`. UART settings are 115200baud, 8N1 and should be visible to any terminal program. Both HW and SW flow control should be disabled.
It is worth noting that *minicom* enables HW flow control by default.
Once released from reset, the CEP's bootrom will read the baremetal executable from the SD card, copy it DDR memory, and then jump to that location and execute the program. The bootrom's default payload size is large enough for a linux boot. For bare metal executables, the payloads are typically much smaller. The payload size can be overriden at boot time by holding *BTN0* on the Arty100T or *SWN* on the VC707/VCU118 when the chip is released from reset.
An example UART output for the baremetal gpiotest follows:
```
--- Common Evaluation Platform v4.20 ---
--- Based on the UCB Chipyard Framework ---
--- Copyright 2022 Massachusetts Institute of Technology ---
--- BootRom Image built on Aug 1 2022 12:41:36 ---
INIT
CMD0
CMD8
ACMD41
CMD58
CMD16
CMD18
LOADING 128kB PAYLOAD
....
BOOT
--------------------------
RISC-V GPIO Test
--------------------------
Built for VCU118
Console Echo Enabled
gpio = 00000010
gpio = 00000000
gpio = 00000020
gpio = 00000000
gpio = 00000080
gpio = 00000000
gpio = 00000040
gpio = 00000000
...
```
A developer may use baremetal software from the CEP cosimulation or the examples as provided in `<CEP_ROOT>/software/baremetal`.
The (micro)SD card needs to be partitioned as described in (https://chipyard.readthedocs.io/en/latest/Prototyping/VCU118.html#running-linux-on-vcu118-designs). Once partitioned, proceed to the next step.
In either case, it is important to note what device your (micro)SD card gets mapped to (e.g., `/dev/sdd`).
Using `<CEP_ROOT>/sims/cep_cosim/testSuites/bareMetal/regTest` as an example, the following steps will build and load the executable onto the (micro)SD card.
```
cd <CEP_ROOT>/sims/cep_cosim/testSuites/bareMetal/regTest
make DISABLE_KPRINTF=0 riscv_wrapper <-- builds riscv_wrapper.img with console printf enabled
make DISK=/dev/sdd1 riscv_wrapper_sd_write <-- copies riscv_wrapper.img to partition /dev/sdd1 (subsitute with your partition name)
```
In the above example, the bare metal regTest is built with the console printf function enabled.
The steps in `<CEP_ROOT>/software/baremetal/gpiotest` are slight different.
```
cd <CEP_ROOT>/software/baremetal/gpiotest
make DISK=/dev/sdd1 sd_write <-- copies gpiotest.img to partition /dev/sdd1 (subsitute with your device name)
```
It is worth noting that the examples in `<CEP_ROOT>/software/baremetal` do not require the compilation of the all the cosimulation libraries, but as a result, will not have access to those support functions.
### Booting Linux
The CEP Arty100T/VC707/VCU118 builds has been verified to support a firemarshall-based linux build by following the default workload instructions [here](https://chipyard.readthedocs.io/en/latest/Prototyping/VCU118.html#running-linux-on-vcu118-designs).
A couple of notes:
- The SD card must be partitioned as instructed
- Due to a bug in libguestfs on Ubuntu, the firemarshal build *may* fail. Ensure your current shell has active sudo permissions before running the build. I used a quick `sudo su`, exited the root shell, and then ran the build.
- Customization of the linux build will affect the resulting image size `<CEP_ROOT>/software/firemarshal/images/br-base-bin-nodisk-flat`. Ensure that `PAYLOAD_SIZE_B` in `<CEP_ROOT>/sims/cep_cosim/bootrom/sd.c` is sized to accomodated the image.
### Linux Applications
You can install an example application in firemarshal's buildroot prior to building linux by running `make MAINPROGRAM=<prog name> install` from <CEP_ROOT>/software/linux. Applications include `helloworld` and `gpiotest`.
It is advisable to clean the buildroot build, should you change the configuration. This can accomplished by running `make clean` within `<CEP_ROOT>/software/firemarshal/boards/prototype/distros/br/buildroot/`.
If you ncurses-based gpiotest application crashes before cleanup, executing the `reset` command should restore terminal behavior.
### CEP Co-Simulation
For simulation using the CEP Co-Simulation environment, the `cep_cosim` and `cep_cosim_asic` *SUB_PROJECTS* are defined in `<CEP_ROOT>/variables.mk`. At this time, due to licensing constraints, the CEP ASIC build is not available as part of this repository. As a result, any attempt to build it will fail given that a multitude of files are missing.
Instructions on the CEP Co-Simulation (including the Chipyard build) can be found [here](./sims/cep_cosim/README.md).
### Generated DSP code notes
Due to licensing contraints, two of the DSP cores used during CEP development cannot be included in our repository. Instructions on generating all the cores can be found [here](./generators/mitll-blocks/src/main/resources/vsrc/dsp/README.md).
## Errors? Ommissions? Questions?
Please feel free to file a github issue which the CEP developers check frequently.
## Citation Information
Citation information is contained [here](./citation.cff)
## Licensing
As the CEP has been developed with input from many sources, multiple licenses apply. Please refer to the following files for licensing info.
* [CEP License](./LICENSE.md)
* [CEP Components Licenses](./LICENSE.md)
* [Chipyard License](./LICENSE.md)
* [SiFive License](./LICENSE.SiFive.md)
## DISTRIBUTION STATEMENT A. Approved for public release. Distribution is unlimited.
This material is based upon work supported by the Defense Advanced Research Projects Agency under Air Force Contract No. FA8702-15-D-0001. Any opinions, findings, conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the Defense Advanced Research Projects Agency.
© 2022 Massachusetts Institute of Technology
The software/firmware is provided to you on an As-Is basis.
Delivered to the U.S. Government with Unlimited Rights, as defined in DFARS Part 252.227-7013 or 7014 (Feb 2014). Notwithstanding any copyright notice, U.S. Government rights in this work are defined by DFARS 252.227-7013 or DFARS 252.227-7014 as detailed above. Use of this work other than as specifically authorized by the U.S. Government may violate any copyrights that exist in this work
|
General
-------
This DockerFile contains the necessary steps to build a Docker container that can run
projects with riscv-tools, chisel3, firrtl, and verilator. When run up to the base stage, it installs the necessary
apt-get packages and sets the environment variables needed for CircleCI. When run up to the base-with-tools stage, it initializes and installs the necessary toolchains for running simulations and testing projects.
Build and Deploy the Container
------------------------------
sudo docker build --target base . # to build the image for the CI
sudo docker build --target base --build-arg CHIPYARD_HASH=<COMMIT_HASH> . # to build the image for the CI from a specific chipyard commit
sudo docker build --target base-with-tools . # to build the full image
sudo docker tag <IMAGE_ID> <PATH_NAME>:tag . # to tag the image after the build (ex. 0.0.3)
sudo docker login # login into the account to push to
sudo docker push <PATH_NAME>:tag # to push to repo with tag
sudo docker run -it --privileged <IMAGE_ID> bash # to run an interactive version of the container
Path Names
----------
Older docker images (when this Dockerfile was in `riscv-boom/riscv-boom`) can be found in the <PATH_NAME> `riscvboom/riscvboom-images`.
Current up-to-date images are located in <PATH_NAME> `ucbbar/chipyard-image`. NOTE: Less recent images in this path may not have toolchains initialized
Current up-to-date CI images are located in <PATH_NAME> `ucbbar/chipyard-ci-image`.
|
// See LICENSE.SiFive for license details.
//VCS coverage exclude_file
`ifndef RESET_DELAY
`define RESET_DELAY 777.7
`endif
`ifndef CLOCK_PERIOD
`define CLOCK_PERIOD 1.0
`endif
`ifndef MODEL
`define MODEL Arty100TFPGATestHarness
`endif
module Arty100TTestDriver;
reg clock = 1'b0;
reg reset = 1'b1;
// the ArtyFPGATestHarness expects an active low reset, because the reset
// switch on the dev board is also active low. the rest of the TestDriver
// logic depends on active high reset. just give resetn to the test harness.
wire resetn = !reset;
always #(`CLOCK_PERIOD/2.0) clock = ~clock;
initial #(`RESET_DELAY) reset = 0;
// Read input arguments and initialize
reg verbose = 1'b0;
wire printf_cond = verbose && !reset;
reg [63:0] max_cycles = 0;
reg [63:0] dump_start = 0;
reg [63:0] trace_count = 0;
reg [2047:0] fsdbfile = 0;
reg [2047:0] vcdplusfile = 0;
reg [2047:0] vcdfile = 0;
int unsigned rand_value;
initial
begin
void'($value$plusargs("max-cycles=%d", max_cycles));
void'($value$plusargs("dump-start=%d", dump_start));
verbose = $test$plusargs("verbose");
// do not delete the lines below.
// $random function needs to be called with the seed once to affect all
// the downstream $random functions within the Chisel-generated Verilog
// code.
// $urandom is seeded via cmdline (+ntb_random_seed in VCS) but that
// doesn't seed $random.
rand_value = $urandom;
rand_value = $random(rand_value);
if (verbose) begin
`ifdef VCS
$fdisplay(stderr, "testing $random %0x seed %d", rand_value, unsigned'($get_initial_random_seed));
`else
$fdisplay(stderr, "testing $random %0x", rand_value);
`endif
end
`ifdef DEBUG
if ($value$plusargs("vcdplusfile=%s", vcdplusfile))
begin
`ifdef VCS
$vcdplusfile(vcdplusfile);
`else
$fdisplay(stderr, "Error: +vcdplusfile is VCS-only; use +vcdfile instead or recompile with VCS=1");
$fatal;
`endif
end
if ($value$plusargs("fsdbfile=%s", fsdbfile))
begin
`ifdef FSDB
$fsdbDumpfile(fsdbfile);
$fsdbDumpvars("+all");
//$fsdbDumpSVA;
`else
$fdisplay(stderr, "Error: +fsdbfile is FSDB-only; use +vcdfile/+vcdplus instead or recompile with FSDB=1");
$fatal;
`endif
end
if ($value$plusargs("vcdfile=%s", vcdfile))
begin
$dumpfile(vcdfile);
$dumpvars(0, testHarness);
end
`ifdef FSDB
`define VCDPLUSON $fsdbDumpon;
`define VCDPLUSCLOSE $fsdbDumpoff;
`elsif VCS
`define VCDPLUSON $vcdpluson(0); $vcdplusmemon(0);
`define VCDPLUSCLOSE $vcdplusclose; $dumpoff;
`else
`define VCDPLUSON $dumpon;
`define VCDPLUSCLOSE $dumpoff;
`endif
`else
// No +define+DEBUG
`define VCDPLUSON
`define VCDPLUSCLOSE
if ($test$plusargs("vcdplusfile=") || $test$plusargs("vcdfile=") || $test$plusargs("fsdbfile="))
begin
$fdisplay(stderr, "Error: +vcdfile, +vcdplusfile, or +fsdbfile requested but compile did not have +define+DEBUG enabled");
$fatal;
end
`endif
if (dump_start == 0)
begin
// Start dumping before first clock edge to capture reset sequence in waveform
`VCDPLUSON
end
end
`ifdef TESTBENCH_IN_UVM
// UVM library has its own way to manage end-of-simulation.
// A UVM-based testbench will raise an objection, watch this signal until this goes 1, then drop the objection.
reg finish_request = 1'b0;
`endif
reg [255:0] reason = "";
reg failure = 1'b0;
wire success;
integer stderr = 32'h80000002;
always @(posedge clock)
begin
`ifdef GATE_LEVEL
if (verbose)
begin
$fdisplay(stderr, "C: %10d", trace_count);
end
`endif
trace_count = trace_count + 1;
if (trace_count == dump_start)
begin
`VCDPLUSON
end
if (!reset)
begin
if (max_cycles > 0 && trace_count > max_cycles)
begin
reason = " (timeout)";
failure = 1'b1;
end
if (failure)
begin
$fdisplay(stderr, "*** FAILED ***%s after %d simulation cycles", reason, trace_count);
`VCDPLUSCLOSE
$fatal;
end
if (success)
begin
if (verbose)
$fdisplay(stderr, "*** PASSED *** Completed after %d simulation cycles", trace_count);
`VCDPLUSCLOSE
`ifdef TESTBENCH_IN_UVM
finish_request = 1;
`else
$finish;
`endif
end
end
end
`MODEL testHarness(
.sys_clock(clock),
.reset(resetn),
.success(success)
);
endmodule
|
// See LICENSE.SiFive for license details.
//VCS coverage exclude_file
`ifndef RESET_DELAY
`define RESET_DELAY 777.7
`endif
`ifndef CLOCK_PERIOD
`define CLOCK_PERIOD 1.0
`endif
`ifndef MODEL
`define MODEL ArtyFPGATestHarness
`endif
module ArtyTestDriver;
reg clock = 1'b0;
reg reset = 1'b1;
// the ArtyFPGATestHarness expects an active low reset, because the reset
// switch on the dev board is also active low. the rest of the TestDriver
// logic depends on active high reset. just give resetn to the test harness.
wire resetn = !reset;
always #(`CLOCK_PERIOD/2.0) clock = ~clock;
initial #(`RESET_DELAY) reset = 0;
// Read input arguments and initialize
reg verbose = 1'b0;
wire printf_cond = verbose && !reset;
reg [63:0] max_cycles = 0;
reg [63:0] dump_start = 0;
reg [63:0] trace_count = 0;
reg [2047:0] fsdbfile = 0;
reg [2047:0] vcdplusfile = 0;
reg [2047:0] vcdfile = 0;
int unsigned rand_value;
initial
begin
void'($value$plusargs("max-cycles=%d", max_cycles));
void'($value$plusargs("dump-start=%d", dump_start));
verbose = $test$plusargs("verbose");
// do not delete the lines below.
// $random function needs to be called with the seed once to affect all
// the downstream $random functions within the Chisel-generated Verilog
// code.
// $urandom is seeded via cmdline (+ntb_random_seed in VCS) but that
// doesn't seed $random.
rand_value = $urandom;
rand_value = $random(rand_value);
if (verbose) begin
`ifdef VCS
$fdisplay(stderr, "testing $random %0x seed %d", rand_value, unsigned'($get_initial_random_seed));
`else
$fdisplay(stderr, "testing $random %0x", rand_value);
`endif
end
`ifdef DEBUG
if ($value$plusargs("vcdplusfile=%s", vcdplusfile))
begin
`ifdef VCS
$vcdplusfile(vcdplusfile);
`else
$fdisplay(stderr, "Error: +vcdplusfile is VCS-only; use +vcdfile instead or recompile with VCS=1");
$fatal;
`endif
end
if ($value$plusargs("fsdbfile=%s", fsdbfile))
begin
`ifdef FSDB
$fsdbDumpfile(fsdbfile);
$fsdbDumpvars("+all");
//$fsdbDumpSVA;
`else
$fdisplay(stderr, "Error: +fsdbfile is FSDB-only; use +vcdfile/+vcdplus instead or recompile with FSDB=1");
$fatal;
`endif
end
if ($value$plusargs("vcdfile=%s", vcdfile))
begin
$dumpfile(vcdfile);
$dumpvars(0, testHarness);
end
`ifdef FSDB
`define VCDPLUSON $fsdbDumpon;
`define VCDPLUSCLOSE $fsdbDumpoff;
`elsif VCS
`define VCDPLUSON $vcdpluson(0); $vcdplusmemon(0);
`define VCDPLUSCLOSE $vcdplusclose; $dumpoff;
`else
`define VCDPLUSON $dumpon;
`define VCDPLUSCLOSE $dumpoff;
`endif
`else
// No +define+DEBUG
`define VCDPLUSON
`define VCDPLUSCLOSE
if ($test$plusargs("vcdplusfile=") || $test$plusargs("vcdfile=") || $test$plusargs("fsdbfile="))
begin
$fdisplay(stderr, "Error: +vcdfile, +vcdplusfile, or +fsdbfile requested but compile did not have +define+DEBUG enabled");
$fatal;
end
`endif
if (dump_start == 0)
begin
// Start dumping before first clock edge to capture reset sequence in waveform
`VCDPLUSON
end
end
`ifdef TESTBENCH_IN_UVM
// UVM library has its own way to manage end-of-simulation.
// A UVM-based testbench will raise an objection, watch this signal until this goes 1, then drop the objection.
reg finish_request = 1'b0;
`endif
reg [255:0] reason = "";
reg failure = 1'b0;
wire success;
integer stderr = 32'h80000002;
always @(posedge clock)
begin
`ifdef GATE_LEVEL
if (verbose)
begin
$fdisplay(stderr, "C: %10d", trace_count);
end
`endif
trace_count = trace_count + 1;
if (trace_count == dump_start)
begin
`VCDPLUSON
end
if (!reset)
begin
if (max_cycles > 0 && trace_count > max_cycles)
begin
reason = " (timeout)";
failure = 1'b1;
end
if (failure)
begin
$fdisplay(stderr, "*** FAILED ***%s after %d simulation cycles", reason, trace_count);
`VCDPLUSCLOSE
$fatal;
end
if (success)
begin
if (verbose)
$fdisplay(stderr, "*** PASSED *** Completed after %d simulation cycles", trace_count);
`VCDPLUSCLOSE
`ifdef TESTBENCH_IN_UVM
finish_request = 1;
`else
$finish;
`endif
end
end
end
`MODEL testHarness(
.CLK100MHZ(clock),
.ck_rst(resetn),
.success(success)
);
endmodule
|
// See LICENSE for license details.
/**
* An unsynthesizable divide-by-N clock divider.
* Duty cycle is 100 * (ceil(DIV / 2)) / DIV.
*/
module ClockDividerN #(parameter DIV = 1)(output logic clk_out = 1'b0, input clk_in);
localparam CWIDTH = $clog2(DIV);
localparam LOW_CYCLES = DIV / 2;
localparam HIGH_TRANSITION = LOW_CYCLES - 1;
localparam LOW_TRANSITION = DIV - 1;
generate
if (DIV == 1) begin
// This needs to be procedural because of the assignment on declaration
always @(clk_in) begin
clk_out = clk_in;
end
end else begin
reg [CWIDTH - 1: 0] count = HIGH_TRANSITION[CWIDTH-1:0];
// The blocking assignment to clock out is used to conform what was done
// in RC's clock dividers.
// It should have the effect of preventing registers in the divided clock
// domain latching register updates launched by the fast clock-domain edge
// that occurs at the same simulated time (as the divided clock edge).
always @(posedge clk_in) begin
if (count == LOW_TRANSITION[CWIDTH-1:0]) begin
clk_out = 1'b0;
count <= '0;
end
else begin
if (count == HIGH_TRANSITION[CWIDTH-1:0]) begin
clk_out = 1'b1;
end
count <= count + 1'b1;
end
end
end
endgenerate
endmodule // ClockDividerN
|
// DOC include start: GCD portlist
module GCDMMIOBlackBox
#(parameter WIDTH)
(
input clock,
input reset,
output input_ready,
input input_valid,
input [WIDTH-1:0] x,
input [WIDTH-1:0] y,
input output_ready,
output output_valid,
output reg [WIDTH-1:0] gcd,
output busy
);
// DOC include end: GCD portlist
localparam S_IDLE = 2'b00, S_RUN = 2'b01, S_DONE = 2'b10;
reg [1:0] state;
reg [WIDTH-1:0] tmp;
assign input_ready = state == S_IDLE;
assign output_valid = state == S_DONE;
assign busy = state != S_IDLE;
always @(posedge clock) begin
if (reset)
state <= S_IDLE;
else if (state == S_IDLE && input_valid)
state <= S_RUN;
else if (state == S_RUN && tmp == 0)
state <= S_DONE;
else if (state == S_DONE && output_ready)
state <= S_IDLE;
end
always @(posedge clock) begin
if (state == S_IDLE && input_valid) begin
gcd <= x;
tmp <= y;
end else if (state == S_RUN) begin
if (gcd > tmp)
gcd <= gcd - tmp;
else
tmp <= tmp - gcd;
end
end
endmodule // GCDMMIOBlackBox
|
//--------------------------------------------------------------------------------------
// Copyright 2022 Massachusets Institute of Technology
// SPDX short identifier: BSD-2-Clause
//
// File Name: cep_tb.v
// Program: Common Evaluation Platform (CEP)
// Description: CEP Co-Simulation Top Level Testbench
// Notes:
//
//--------------------------------------------------------------------------------------
module pll_wrapper (
input clk_in,
input reset_in,
output clk_out,
output reset_out
);
assign clk_out = clk_in;
assign reset_out = reset_in;
endmodule // pll_wrapper |
[//]: # (Copyright 2022 Massachusets Institute of Technology)
[//]: # (SPDX short identifier: BSD-2-Clause)
[](https://zenodo.org/badge/latestdoi/108179132)
[](https://opensource.org/licenses/BSD-2-Clause)
<p align="center">
Copyright 2022 Massachusets Institute of Technology
</p>
## AEEES-WB - Advanced Egregiously Extended Encryption Standard, White-Box Edition
The aeees.py script generates extended variants of the AES-128 core with the option of
"baking in the key" if desired.
Executing `aeees.py -h` will print a complete list of script options.
Example usage:
```
./aeees.py -k 12345 -r 100 -t 500 -v <- Generate a 100-round variant of AES-128 with the
key fixed at "12345". Generate 500 test vectors.
Run in verbose mode
./aeees.py -nk -r 200 -t 250 <- Generate a 200-round variant of AES-128 with a
key schedule. Generate 250 test vectors.
```
Generated outputs from the first run example:
```
aeees_roundfn.vi - Utility functions for the AES rounds
aeees_rounds.v - Individual definitions of all (100) AES rounds
aeees_box_XXX.vi - Generated AES S-Box for round XXX with "baked-in" key
aeees.v - Top level AEEES module
aeees_tb.v - AEEES module testbench
aeees_stimulus.v - Stimulus file for the AEEES testbench
Makefile - Simulation makefile - just run "make"
vsim.do - Simulation TCL script
```
Generated outputs from the second run example:
```
aeees_rounds.v - Individual definitions of all (250) AES rounds
aeees_table.v - AES S-Box definition
aeees.v - Top level AEEES module
aeees_stimulus.csv - Stimulus file for the AEEES testbench
aeees_tb.sv - AEEES module testbench
Makefile - Simulation makefile - just run "make"
vsim.do - Simulation TCL script
```
All generated files are implicitly included in .gitignore and are thus not tracked by git.
Caution should be taken when running the aeees.py script with the `--clean` switch.
The following files will be deleted with `--clean`:
```
aeees.v
aeees_rounds.v
eees_table.v
aeees_stimulus.csv
aeees_tb.sv
Makefile
vsim.do
aeees_roundfn.vi
aeees_box_*.vi
```
#### Return to the root CEP [README](../../README.md)
|
/*
* Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
// assumes input does not change between start going high and out_valid
module aes_128(clk, rst, start, state, key, out, out_valid);
input clk;
input rst;
input start;
input [127:0] state, key;
output [127:0] out;
output out_valid;
reg [127:0] s0, k0;
wire [127:0] s1, s2, s3, s4, s5, s6, s7, s8, s9,
k1, k2, k3, k4, k5, k6, k7, k8, k9,
k0b, k1b, k2b, k3b, k4b, k5b, k6b, k7b, k8b, k9b;
reg start_r;
always @(posedge clk or posedge rst)
begin
if (rst)
start_r <= 1'b0;
else
start_r <= start;
end
wire start_posedge = start & ~start_r;
reg [4:0] validCounter;
always @ (posedge clk or posedge rst)
begin
if (rst) begin
s0 <= 0;
k0 <= 0;
validCounter <= 0;
end else begin
if(start_posedge)
begin
s0 <= state ^ key;
k0 <= key;
validCounter <= 21;
end
else if(~out_valid)
begin
validCounter <= validCounter - 1;
end
end // end if (rst)
end // end always
assign out_valid = (validCounter == 0);
expand_key_128
a1 (clk, rst, k0, k1, k0b, 8'h1),
a2 (clk, rst, k1, k2, k1b, 8'h2),
a3 (clk, rst, k2, k3, k2b, 8'h4),
a4 (clk, rst, k3, k4, k3b, 8'h8),
a5 (clk, rst, k4, k5, k4b, 8'h10),
a6 (clk, rst, k5, k6, k5b, 8'h20),
a7 (clk, rst, k6, k7, k6b, 8'h40),
a8 (clk, rst, k7, k8, k7b, 8'h80),
a9 (clk, rst, k8, k9, k8b, 8'h1b),
a10 (clk, rst, k9, , k9b, 8'h36);
one_round
r1 (clk, rst, s0, k0b, s1),
r2 (clk, rst, s1, k1b, s2),
r3 (clk, rst, s2, k2b, s3),
r4 (clk, rst, s3, k3b, s4),
r5 (clk, rst, s4, k4b, s5),
r6 (clk, rst, s5, k5b, s6),
r7 (clk, rst, s6, k6b, s7),
r8 (clk, rst, s7, k7b, s8),
r9 (clk, rst, s8, k8b, s9);
final_round
rf (clk, rst, s9, k9b, out);
endmodule
module expand_key_128(clk, rst, in, out_1, out_2, rcon);
input clk;
input rst;
input [127:0] in;
input [7:0] rcon;
output reg [127:0] out_1;
output [127:0] out_2;
wire [31:0] k0, k1, k2, k3,
v0, v1, v2, v3;
reg [31:0] k0a, k1a, k2a, k3a;
wire [31:0] k0b, k1b, k2b, k3b, k4a;
assign {k0, k1, k2, k3} = in;
assign v0 = {k0[31:24] ^ rcon, k0[23:0]};
assign v1 = v0 ^ k1;
assign v2 = v1 ^ k2;
assign v3 = v2 ^ k3;
always @ (posedge clk or posedge rst)
begin
if (rst) begin
k0a <= 0;
k1a <= 0;
k2a <= 0;
k3a <= 0;
end else begin
{k0a, k1a, k2a, k3a} <= {v0, v1, v2, v3};
end
end
S4
S4_0 (clk, rst, {k3[23:0], k3[31:24]}, k4a);
assign k0b = k0a ^ k4a;
assign k1b = k1a ^ k4a;
assign k2b = k2a ^ k4a;
assign k3b = k3a ^ k4a;
always @ (posedge clk or posedge rst)
begin
if (rst)
out_1 <= 0;
else
out_1 <= {k0b, k1b, k2b, k3b};
end
assign out_2 = {k0b, k1b, k2b, k3b};
endmodule
|
/*
* Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
// This is a fully unrolled implementation
module aes_192 (clk, rst, start, state, key, out, out_valid);
input wire clk;
input wire rst;
input wire start;
input wire [127:0] state;
input wire [191:0] key;
output wire [127:0] out;
output wire out_valid;
// Internals signals and such
reg [127:0] s0;
reg [191:0] k0;
wire [127:0] s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11;
wire [191:0] k1, k2, k3, k4, k5, k6, k7, k8, k9, k10, k11;
wire [127:0] k0b, k1b, k2b, k3b, k4b, k5b, k6b, k7b, k8b, k9b, k10b, k11b;
reg start_r;
wire start_posedge;
reg [4:0] validCounter;
assign start_posedge = start & ~start_r;
always @(posedge clk)
begin
if (rst)
start_r <= 1'b0;
else
start_r <= start;
end // end always
always @ (posedge clk)
begin
if (rst) begin
s0 <= 0;
k0 <= 0;
validCounter <= 0;
end else
if(start_posedge)
begin
s0 <= state ^ key[191:64];
k0 <= key;
validCounter <= 26;
end
else if(validCounter > 1)
begin
validCounter <= validCounter - 1;
end
end // end always
assign out_valid = (validCounter == 1);
expand_key_type_D_192 a0 (clk, rst, k0, 8'h1, k1, k0b);
expand_key_type_B_192 a1 (clk, rst, k1, k2, k1b);
expand_key_type_A_192 a2 (clk, rst, k2, 8'h2, k3, k2b);
expand_key_type_C_192 a3 (clk, rst, k3, 8'h4, k4, k3b);
expand_key_type_B_192 a4 (clk, rst, k4, k5, k4b);
expand_key_type_A_192 a5 (clk, rst, k5, 8'h8, k6, k5b);
expand_key_type_C_192 a6 (clk, rst, k6, 8'h10, k7, k6b);
expand_key_type_B_192 a7 (clk, rst, k7, k8, k7b);
expand_key_type_A_192 a8 (clk, rst, k8, 8'h20, k9, k8b);
expand_key_type_C_192 a9 (clk, rst, k9, 8'h40, k10, k9b);
expand_key_type_B_192 a10 (clk, rst, k10, k11, k10b);
expand_key_type_A_192 a11 (clk, rst, k11, 8'h80, , k11b);
one_round
r1 (clk, rst, s0, k0b, s1),
r2 (clk, rst, s1, k1b, s2),
r3 (clk, rst, s2, k2b, s3),
r4 (clk, rst, s3, k3b, s4),
r5 (clk, rst, s4, k4b, s5),
r6 (clk, rst, s5, k5b, s6),
r7 (clk, rst, s6, k6b, s7),
r8 (clk, rst, s7, k7b, s8),
r9 (clk, rst, s8, k8b, s9),
r10 (clk, rst, s9, k9b, s10),
r11 (clk, rst, s10, k10b, s11);
final_round
rf (clk, rst, s11, k11b, out);
endmodule
/* expand k0,k1,k2,k3 for every two clock cycles */
module expand_key_type_A_192 (clk, rst, in, rcon, out_1, out_2);
input wire clk;
input wire rst;
input wire [191:0] in;
input wire [7:0] rcon;
output reg [191:0] out_1;
output wire [127:0] out_2;
// Internal signals
wire [31:0] k0, k1, k2, k3, k4, k5, v0, v1, v2, v3;
reg [31:0] k0a, k1a, k2a, k3a, k4a, k5a;
wire [31:0] k0b, k1b, k2b, k3b, k4b, k5b, k6a;
assign {k0, k1, k2, k3, k4, k5} = in;
assign v0 = {k0[31:24] ^ rcon, k0[23:0]};
assign v1 = v0 ^ k1;
assign v2 = v1 ^ k2;
assign v3 = v2 ^ k3;
always @ (posedge clk)
begin
if (rst)
{k0a, k1a, k2a, k3a, k4a, k5a} <= {32'd0, 32'd0, 32'd0, 32'd0, 32'd0, 32'd0};
else
{k0a, k1a, k2a, k3a, k4a, k5a} <= {v0, v1, v2, v3, k4, k5};
end // end always
S4 S4_0 (clk, rst, {k5[23:0], k5[31:24]}, k6a);
assign k0b = k0a ^ k6a;
assign k1b = k1a ^ k6a;
assign k2b = k2a ^ k6a;
assign k3b = k3a ^ k6a;
assign {k4b, k5b} = {k4a, k5a};
always @ (posedge clk)
begin
if (rst)
out_1 <= 0;
else
out_1 <= {k0b, k1b, k2b, k3b, k4b, k5b};
end // end always
assign out_2 = {k0b, k1b, k2b, k3b};
endmodule // end module expand_key_type_A_192
/* expand k2,k3,k4,k5 for every two clock cycles */
module expand_key_type_B_192 (clk, rst, in, out_1, out_2);
input wire clk;
input wire rst;
input wire [191:0] in;
output reg [191:0] out_1;
output wire [127:0] out_2;
wire [31:0] k0, k1, k2, k3, k4, k5, v2, v3, v4, v5;
reg [31:0] k0a, k1a, k2a, k3a, k4a, k5a;
assign {k0, k1, k2, k3, k4, k5} = in;
assign v2 = k1 ^ k2;
assign v3 = v2 ^ k3;
assign v4 = v3 ^ k4;
assign v5 = v4 ^ k5;
always @ (posedge clk)
begin
if (rst)
{k0a, k1a, k2a, k3a, k4a, k5a} <= {32'd0, 32'd0, 32'd0, 32'd0, 32'd0, 32'd0};
else
{k0a, k1a, k2a, k3a, k4a, k5a} <= {k0, k1, v2, v3, v4, v5};
end // end always
always @ (posedge clk)
begin
if (rst)
out_1 <= 0;
else
out_1 <= {k0a, k1a, k2a, k3a, k4a, k5a};
end
assign out_2 = {k2a, k3a, k4a, k5a};
endmodule // end expand_key_type_B_192
/* expand k0,k1,k4,k5 for every two clock cycles */
module expand_key_type_C_192 (clk, rst, in, rcon, out_1, out_2);
input wire clk;
input wire rst;
input wire [191:0] in;
input wire [7:0] rcon;
output reg [191:0] out_1;
output wire [127:0] out_2;
wire [31:0] k0, k1, k2, k3, k4, k5, v4, v5, v0, v1;
reg [31:0] k0a, k1a, k2a, k3a, k4a, k5a;
wire [31:0] k0b, k1b, k2b, k3b, k4b, k5b, k6a;
assign {k0, k1, k2, k3, k4, k5} = in;
assign v4 = k3 ^ k4;
assign v5 = v4 ^ k5;
assign v0 = {k0[31:24] ^ rcon, k0[23:0]};
assign v1 = v0 ^ k1;
always @ (posedge clk)
begin
if (rst)
{k0a, k1a, k2a, k3a, k4a, k5a} <= {32'd0, 32'd0, 32'd0, 32'd0, 32'd0, 32'd0};
else
{k0a, k1a, k2a, k3a, k4a, k5a} <= {v0, v1, k2, k3, v4, v5};
end
S4 S4_0 (clk, rst, {v5[23:0], v5[31:24]}, k6a);
assign k0b = k0a ^ k6a;
assign k1b = k1a ^ k6a;
assign {k2b, k3b, k4b, k5b} = {k2a, k3a, k4a, k5a};
always @ (posedge clk)
begin
if (rst)
out_1 <= 0;
else
out_1 <= {k0b, k1b, k2b, k3b, k4b, k5b};
end
assign out_2 = {k4b, k5b, k0b, k1b};
endmodule // end expand_key_type_C_192
/* expand k0,k1 for every two clock cycles */
module expand_key_type_D_192 (clk, rst, in, rcon, out_1, out_2);
input wire clk;
input wire rst;
input wire [191:0] in;
input wire [7:0] rcon;
output reg [191:0] out_1;
output wire [127:0] out_2;
wire [31:0] k0, k1, k2, k3, k4, k5, v0, v1;
reg [31:0] k0a, k1a, k2a, k3a, k4a, k5a;
wire [31:0] k0b, k1b, k2b, k3b, k4b, k5b, k6a;
assign {k0, k1, k2, k3, k4, k5} = in;
assign v0 = {k0[31:24] ^ rcon, k0[23:0]};
assign v1 = v0 ^ k1;
always @ (posedge clk)
begin
if (rst)
{k0a, k1a, k2a, k3a, k4a, k5a} <= {32'd0, 32'd0, 32'd0, 32'd0, 32'd0, 32'd0};
else
{k0a, k1a, k2a, k3a, k4a, k5a} <= {v0, v1, k2, k3, k4, k5};
end // end always
S4 S4_0 (clk, rst, {k5[23:0], k5[31:24]}, k6a);
assign k0b = k0a ^ k6a;
assign k1b = k1a ^ k6a;
assign {k2b, k3b, k4b, k5b} = {k2a, k3a, k4a, k5a};
always @ (posedge clk)
begin
if (rst)
out_1 <= 0;
else
out_1 <= {k0b, k1b, k2b, k3b, k4b, k5b};
end // end always
assign out_2 = {k4b, k5b, k0b, k1b};
endmodule // end expand_key_type_D_192
|
//************************************************************************
// Copyright 2022 Massachusets Institute of Technology
// SPDX License Identifier: BSD-2-Clause
//
// File Name: aes_192_mock_tss.sv
// Program: Common Evaluation Platform (CEP)
// Description:
// Notes:
//************************************************************************
`timescale 1ns/1ns
module aes_192_mock_tss import llki_pkg::*; (
// Clock and Reset
input wire clk,
input wire rst,
// Core I/O
input wire start,
input wire [127:0] state,
input wire [191:0] key,
output wire [127:0] out,
output wire out_valid,
// LLKI Discrete I/O
input [63:0] llkid_key_data,
input llkid_key_valid,
output reg llkid_key_ready,
output reg llkid_key_complete,
input llkid_clear_key,
output reg llkid_clear_key_ack
);
// Internal signals & localparams
localparam KEY_WORDS = AES_MOCK_TSS_NUM_KEY_WORDS;
reg [(64*KEY_WORDS) - 1:0] llkid_key_register;
wire [(64*KEY_WORDS) - 1:0] mock_tss_state;
//------------------------------------------------------------------
// Instantiate the Mock TSS Finite State Machine
//------------------------------------------------------------------
mock_tss_fsm #(
.KEY_WORDS (KEY_WORDS)
) mock_tss_fsm_inst (
.clk (clk),
.rst (rst),
.llkid_key_data (llkid_key_data),
.llkid_key_valid (llkid_key_valid),
.llkid_key_ready (llkid_key_ready),
.llkid_key_complete (llkid_key_complete),
.llkid_clear_key (llkid_clear_key),
.llkid_clear_key_ack (llkid_clear_key_ack),
.llkid_key_register (llkid_key_register)
);
//------------------------------------------------------------------
//------------------------------------------------------------------
// Create the Mock TSS input into the original core
//------------------------------------------------------------------
genvar i;
generate
for (i = 0; i < KEY_WORDS; i = i + 1) begin
assign mock_tss_state[64*i +: 64] = AES_MOCK_TSS_KEY_WORDS[i] ^
llkid_key_register[64*i +: 64] ^
state[64*i +: 64];
end
endgenerate
//------------------------------------------------------------------
//------------------------------------------------------------------
// Instantiate the original core
//------------------------------------------------------------------
aes_192 aes_192_inst (
.clk (clk),
.rst (rst),
.start (start),
.state (mock_tss_state),
.key (key),
.out (out),
.out_valid (out_valid)
);
//------------------------------------------------------------------
endmodule
|
/*
* Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* verilator lint_off UNOPTFLAT */
/* one AES round for every two clock cycles */
module one_round (clk, rst, state_in, key, state_out);
input clk;
input rst;
input [127:0] state_in, key;
output reg [127:0] state_out;
wire [31:0] s0, s1, s2, s3,
z0, z1, z2, z3,
p00, p01, p02, p03,
p10, p11, p12, p13,
p20, p21, p22, p23,
p30, p31, p32, p33,
k0, k1, k2, k3;
assign {k0, k1, k2, k3} = key;
assign {s0, s1, s2, s3} = state_in;
table_lookup
t0 (clk, rst, s0, p00, p01, p02, p03),
t1 (clk, rst, s1, p10, p11, p12, p13),
t2 (clk, rst, s2, p20, p21, p22, p23),
t3 (clk, rst, s3, p30, p31, p32, p33);
assign z0 = p00 ^ p11 ^ p22 ^ p33 ^ k0;
assign z1 = p03 ^ p10 ^ p21 ^ p32 ^ k1;
assign z2 = p02 ^ p13 ^ p20 ^ p31 ^ k2;
assign z3 = p01 ^ p12 ^ p23 ^ p30 ^ k3;
always @ (posedge clk)
state_out <= {z0, z1, z2, z3};
endmodule
/* AES final round for every two clock cycles */
module final_round (clk, rst, state_in, key_in, state_out);
input clk;
input rst;
input [127:0] state_in;
input [127:0] key_in;
output reg [127:0] state_out;
wire [31:0] s0, s1, s2, s3,
z0, z1, z2, z3,
k0, k1, k2, k3;
wire [7:0] p00, p01, p02, p03,
p10, p11, p12, p13,
p20, p21, p22, p23,
p30, p31, p32, p33;
assign {k0, k1, k2, k3} = key_in;
assign {s0, s1, s2, s3} = state_in;
S4
S4_1 (clk, rst, s0, {p00, p01, p02, p03}),
S4_2 (clk, rst, s1, {p10, p11, p12, p13}),
S4_3 (clk, rst, s2, {p20, p21, p22, p23}),
S4_4 (clk, rst, s3, {p30, p31, p32, p33});
assign z0 = {p00, p11, p22, p33} ^ k0;
assign z1 = {p10, p21, p32, p03} ^ k1;
assign z2 = {p20, p31, p02, p13} ^ k2;
assign z3 = {p30, p01, p12, p23} ^ k3;
always @ (posedge clk)
if (rst)
state_out <= 0;
else
state_out <= {z0, z1, z2, z3};
endmodule
|
/*
* Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* verilator lint_off UNOPTFLAT */
module table_lookup (clk, rst, state, p0, p1, p2, p3);
input clk;
input rst;
input [31:0] state;
output [31:0] p0, p1, p2, p3;
wire [7:0] b0, b1, b2, b3;
assign {b0, b1, b2, b3} = state;
T
t0 (clk, rst, b0, {p0[23:0], p0[31:24]}),
t1 (clk, rst, b1, {p1[15:0], p1[31:16]}),
t2 (clk, rst, b2, {p2[7:0], p2[31:8]} ),
t3 (clk, rst, b3, p3);
endmodule // end table_lookup
/* substitue four bytes in a word */
module S4 (clk, rst, in, out);
input clk;
input rst;
input [31:0] in;
output [31:0] out;
S
S_0 (clk, rst, in[31:24], out[31:24]),
S_1 (clk, rst, in[23:16], out[23:16]),
S_2 (clk, rst, in[15:8], out[15:8] ),
S_3 (clk, rst, in[7:0], out[7:0] );
endmodule // end S4
/* S_box, S_box, S_box*(x+1), S_box*x */
module T (clk, rst, in, out);
input clk;
input rst;
input [7:0] in;
output [31:0] out;
S
s0 (clk, rst, in, out[31:24]);
assign out[23:16] = out[31:24];
xS
s4 (clk, rst, in, out[7:0]);
assign out[15:8] = out[23:16] ^ out[7:0];
endmodule // end T
/* S box */
module S (clk, rst, in, out);
input clk;
input rst;
input [7:0] in;
output reg [7:0] out;
always @ (posedge clk)
if (rst)
out <= 8'd0;
else
case (in)
8'h00: out <= 8'h63;
8'h01: out <= 8'h7c;
8'h02: out <= 8'h77;
8'h03: out <= 8'h7b;
8'h04: out <= 8'hf2;
8'h05: out <= 8'h6b;
8'h06: out <= 8'h6f;
8'h07: out <= 8'hc5;
8'h08: out <= 8'h30;
8'h09: out <= 8'h01;
8'h0a: out <= 8'h67;
8'h0b: out <= 8'h2b;
8'h0c: out <= 8'hfe;
8'h0d: out <= 8'hd7;
8'h0e: out <= 8'hab;
8'h0f: out <= 8'h76;
8'h10: out <= 8'hca;
8'h11: out <= 8'h82;
8'h12: out <= 8'hc9;
8'h13: out <= 8'h7d;
8'h14: out <= 8'hfa;
8'h15: out <= 8'h59;
8'h16: out <= 8'h47;
8'h17: out <= 8'hf0;
8'h18: out <= 8'had;
8'h19: out <= 8'hd4;
8'h1a: out <= 8'ha2;
8'h1b: out <= 8'haf;
8'h1c: out <= 8'h9c;
8'h1d: out <= 8'ha4;
8'h1e: out <= 8'h72;
8'h1f: out <= 8'hc0;
8'h20: out <= 8'hb7;
8'h21: out <= 8'hfd;
8'h22: out <= 8'h93;
8'h23: out <= 8'h26;
8'h24: out <= 8'h36;
8'h25: out <= 8'h3f;
8'h26: out <= 8'hf7;
8'h27: out <= 8'hcc;
8'h28: out <= 8'h34;
8'h29: out <= 8'ha5;
8'h2a: out <= 8'he5;
8'h2b: out <= 8'hf1;
8'h2c: out <= 8'h71;
8'h2d: out <= 8'hd8;
8'h2e: out <= 8'h31;
8'h2f: out <= 8'h15;
8'h30: out <= 8'h04;
8'h31: out <= 8'hc7;
8'h32: out <= 8'h23;
8'h33: out <= 8'hc3;
8'h34: out <= 8'h18;
8'h35: out <= 8'h96;
8'h36: out <= 8'h05;
8'h37: out <= 8'h9a;
8'h38: out <= 8'h07;
8'h39: out <= 8'h12;
8'h3a: out <= 8'h80;
8'h3b: out <= 8'he2;
8'h3c: out <= 8'heb;
8'h3d: out <= 8'h27;
8'h3e: out <= 8'hb2;
8'h3f: out <= 8'h75;
8'h40: out <= 8'h09;
8'h41: out <= 8'h83;
8'h42: out <= 8'h2c;
8'h43: out <= 8'h1a;
8'h44: out <= 8'h1b;
8'h45: out <= 8'h6e;
8'h46: out <= 8'h5a;
8'h47: out <= 8'ha0;
8'h48: out <= 8'h52;
8'h49: out <= 8'h3b;
8'h4a: out <= 8'hd6;
8'h4b: out <= 8'hb3;
8'h4c: out <= 8'h29;
8'h4d: out <= 8'he3;
8'h4e: out <= 8'h2f;
8'h4f: out <= 8'h84;
8'h50: out <= 8'h53;
8'h51: out <= 8'hd1;
8'h52: out <= 8'h00;
8'h53: out <= 8'hed;
8'h54: out <= 8'h20;
8'h55: out <= 8'hfc;
8'h56: out <= 8'hb1;
8'h57: out <= 8'h5b;
8'h58: out <= 8'h6a;
8'h59: out <= 8'hcb;
8'h5a: out <= 8'hbe;
8'h5b: out <= 8'h39;
8'h5c: out <= 8'h4a;
8'h5d: out <= 8'h4c;
8'h5e: out <= 8'h58;
8'h5f: out <= 8'hcf;
8'h60: out <= 8'hd0;
8'h61: out <= 8'hef;
8'h62: out <= 8'haa;
8'h63: out <= 8'hfb;
8'h64: out <= 8'h43;
8'h65: out <= 8'h4d;
8'h66: out <= 8'h33;
8'h67: out <= 8'h85;
8'h68: out <= 8'h45;
8'h69: out <= 8'hf9;
8'h6a: out <= 8'h02;
8'h6b: out <= 8'h7f;
8'h6c: out <= 8'h50;
8'h6d: out <= 8'h3c;
8'h6e: out <= 8'h9f;
8'h6f: out <= 8'ha8;
8'h70: out <= 8'h51;
8'h71: out <= 8'ha3;
8'h72: out <= 8'h40;
8'h73: out <= 8'h8f;
8'h74: out <= 8'h92;
8'h75: out <= 8'h9d;
8'h76: out <= 8'h38;
8'h77: out <= 8'hf5;
8'h78: out <= 8'hbc;
8'h79: out <= 8'hb6;
8'h7a: out <= 8'hda;
8'h7b: out <= 8'h21;
8'h7c: out <= 8'h10;
8'h7d: out <= 8'hff;
8'h7e: out <= 8'hf3;
8'h7f: out <= 8'hd2;
8'h80: out <= 8'hcd;
8'h81: out <= 8'h0c;
8'h82: out <= 8'h13;
8'h83: out <= 8'hec;
8'h84: out <= 8'h5f;
8'h85: out <= 8'h97;
8'h86: out <= 8'h44;
8'h87: out <= 8'h17;
8'h88: out <= 8'hc4;
8'h89: out <= 8'ha7;
8'h8a: out <= 8'h7e;
8'h8b: out <= 8'h3d;
8'h8c: out <= 8'h64;
8'h8d: out <= 8'h5d;
8'h8e: out <= 8'h19;
8'h8f: out <= 8'h73;
8'h90: out <= 8'h60;
8'h91: out <= 8'h81;
8'h92: out <= 8'h4f;
8'h93: out <= 8'hdc;
8'h94: out <= 8'h22;
8'h95: out <= 8'h2a;
8'h96: out <= 8'h90;
8'h97: out <= 8'h88;
8'h98: out <= 8'h46;
8'h99: out <= 8'hee;
8'h9a: out <= 8'hb8;
8'h9b: out <= 8'h14;
8'h9c: out <= 8'hde;
8'h9d: out <= 8'h5e;
8'h9e: out <= 8'h0b;
8'h9f: out <= 8'hdb;
8'ha0: out <= 8'he0;
8'ha1: out <= 8'h32;
8'ha2: out <= 8'h3a;
8'ha3: out <= 8'h0a;
8'ha4: out <= 8'h49;
8'ha5: out <= 8'h06;
8'ha6: out <= 8'h24;
8'ha7: out <= 8'h5c;
8'ha8: out <= 8'hc2;
8'ha9: out <= 8'hd3;
8'haa: out <= 8'hac;
8'hab: out <= 8'h62;
8'hac: out <= 8'h91;
8'had: out <= 8'h95;
8'hae: out <= 8'he4;
8'haf: out <= 8'h79;
8'hb0: out <= 8'he7;
8'hb1: out <= 8'hc8;
8'hb2: out <= 8'h37;
8'hb3: out <= 8'h6d;
8'hb4: out <= 8'h8d;
8'hb5: out <= 8'hd5;
8'hb6: out <= 8'h4e;
8'hb7: out <= 8'ha9;
8'hb8: out <= 8'h6c;
8'hb9: out <= 8'h56;
8'hba: out <= 8'hf4;
8'hbb: out <= 8'hea;
8'hbc: out <= 8'h65;
8'hbd: out <= 8'h7a;
8'hbe: out <= 8'hae;
8'hbf: out <= 8'h08;
8'hc0: out <= 8'hba;
8'hc1: out <= 8'h78;
8'hc2: out <= 8'h25;
8'hc3: out <= 8'h2e;
8'hc4: out <= 8'h1c;
8'hc5: out <= 8'ha6;
8'hc6: out <= 8'hb4;
8'hc7: out <= 8'hc6;
8'hc8: out <= 8'he8;
8'hc9: out <= 8'hdd;
8'hca: out <= 8'h74;
8'hcb: out <= 8'h1f;
8'hcc: out <= 8'h4b;
8'hcd: out <= 8'hbd;
8'hce: out <= 8'h8b;
8'hcf: out <= 8'h8a;
8'hd0: out <= 8'h70;
8'hd1: out <= 8'h3e;
8'hd2: out <= 8'hb5;
8'hd3: out <= 8'h66;
8'hd4: out <= 8'h48;
8'hd5: out <= 8'h03;
8'hd6: out <= 8'hf6;
8'hd7: out <= 8'h0e;
8'hd8: out <= 8'h61;
8'hd9: out <= 8'h35;
8'hda: out <= 8'h57;
8'hdb: out <= 8'hb9;
8'hdc: out <= 8'h86;
8'hdd: out <= 8'hc1;
8'hde: out <= 8'h1d;
8'hdf: out <= 8'h9e;
8'he0: out <= 8'he1;
8'he1: out <= 8'hf8;
8'he2: out <= 8'h98;
8'he3: out <= 8'h11;
8'he4: out <= 8'h69;
8'he5: out <= 8'hd9;
8'he6: out <= 8'h8e;
8'he7: out <= 8'h94;
8'he8: out <= 8'h9b;
8'he9: out <= 8'h1e;
8'hea: out <= 8'h87;
8'heb: out <= 8'he9;
8'hec: out <= 8'hce;
8'hed: out <= 8'h55;
8'hee: out <= 8'h28;
8'hef: out <= 8'hdf;
8'hf0: out <= 8'h8c;
8'hf1: out <= 8'ha1;
8'hf2: out <= 8'h89;
8'hf3: out <= 8'h0d;
8'hf4: out <= 8'hbf;
8'hf5: out <= 8'he6;
8'hf6: out <= 8'h42;
8'hf7: out <= 8'h68;
8'hf8: out <= 8'h41;
8'hf9: out <= 8'h99;
8'hfa: out <= 8'h2d;
8'hfb: out <= 8'h0f;
8'hfc: out <= 8'hb0;
8'hfd: out <= 8'h54;
8'hfe: out <= 8'hbb;
8'hff: out <= 8'h16;
endcase
endmodule
/* S box * x */
module xS (clk, rst, in, out);
input clk;
input rst;
input [7:0] in;
output reg [7:0] out;
always @ (posedge clk)
if (rst)
out <= 8'd0;
else
case (in)
8'h00: out <= 8'hc6;
8'h01: out <= 8'hf8;
8'h02: out <= 8'hee;
8'h03: out <= 8'hf6;
8'h04: out <= 8'hff;
8'h05: out <= 8'hd6;
8'h06: out <= 8'hde;
8'h07: out <= 8'h91;
8'h08: out <= 8'h60;
8'h09: out <= 8'h02;
8'h0a: out <= 8'hce;
8'h0b: out <= 8'h56;
8'h0c: out <= 8'he7;
8'h0d: out <= 8'hb5;
8'h0e: out <= 8'h4d;
8'h0f: out <= 8'hec;
8'h10: out <= 8'h8f;
8'h11: out <= 8'h1f;
8'h12: out <= 8'h89;
8'h13: out <= 8'hfa;
8'h14: out <= 8'hef;
8'h15: out <= 8'hb2;
8'h16: out <= 8'h8e;
8'h17: out <= 8'hfb;
8'h18: out <= 8'h41;
8'h19: out <= 8'hb3;
8'h1a: out <= 8'h5f;
8'h1b: out <= 8'h45;
8'h1c: out <= 8'h23;
8'h1d: out <= 8'h53;
8'h1e: out <= 8'he4;
8'h1f: out <= 8'h9b;
8'h20: out <= 8'h75;
8'h21: out <= 8'he1;
8'h22: out <= 8'h3d;
8'h23: out <= 8'h4c;
8'h24: out <= 8'h6c;
8'h25: out <= 8'h7e;
8'h26: out <= 8'hf5;
8'h27: out <= 8'h83;
8'h28: out <= 8'h68;
8'h29: out <= 8'h51;
8'h2a: out <= 8'hd1;
8'h2b: out <= 8'hf9;
8'h2c: out <= 8'he2;
8'h2d: out <= 8'hab;
8'h2e: out <= 8'h62;
8'h2f: out <= 8'h2a;
8'h30: out <= 8'h08;
8'h31: out <= 8'h95;
8'h32: out <= 8'h46;
8'h33: out <= 8'h9d;
8'h34: out <= 8'h30;
8'h35: out <= 8'h37;
8'h36: out <= 8'h0a;
8'h37: out <= 8'h2f;
8'h38: out <= 8'h0e;
8'h39: out <= 8'h24;
8'h3a: out <= 8'h1b;
8'h3b: out <= 8'hdf;
8'h3c: out <= 8'hcd;
8'h3d: out <= 8'h4e;
8'h3e: out <= 8'h7f;
8'h3f: out <= 8'hea;
8'h40: out <= 8'h12;
8'h41: out <= 8'h1d;
8'h42: out <= 8'h58;
8'h43: out <= 8'h34;
8'h44: out <= 8'h36;
8'h45: out <= 8'hdc;
8'h46: out <= 8'hb4;
8'h47: out <= 8'h5b;
8'h48: out <= 8'ha4;
8'h49: out <= 8'h76;
8'h4a: out <= 8'hb7;
8'h4b: out <= 8'h7d;
8'h4c: out <= 8'h52;
8'h4d: out <= 8'hdd;
8'h4e: out <= 8'h5e;
8'h4f: out <= 8'h13;
8'h50: out <= 8'ha6;
8'h51: out <= 8'hb9;
8'h52: out <= 8'h00;
8'h53: out <= 8'hc1;
8'h54: out <= 8'h40;
8'h55: out <= 8'he3;
8'h56: out <= 8'h79;
8'h57: out <= 8'hb6;
8'h58: out <= 8'hd4;
8'h59: out <= 8'h8d;
8'h5a: out <= 8'h67;
8'h5b: out <= 8'h72;
8'h5c: out <= 8'h94;
8'h5d: out <= 8'h98;
8'h5e: out <= 8'hb0;
8'h5f: out <= 8'h85;
8'h60: out <= 8'hbb;
8'h61: out <= 8'hc5;
8'h62: out <= 8'h4f;
8'h63: out <= 8'hed;
8'h64: out <= 8'h86;
8'h65: out <= 8'h9a;
8'h66: out <= 8'h66;
8'h67: out <= 8'h11;
8'h68: out <= 8'h8a;
8'h69: out <= 8'he9;
8'h6a: out <= 8'h04;
8'h6b: out <= 8'hfe;
8'h6c: out <= 8'ha0;
8'h6d: out <= 8'h78;
8'h6e: out <= 8'h25;
8'h6f: out <= 8'h4b;
8'h70: out <= 8'ha2;
8'h71: out <= 8'h5d;
8'h72: out <= 8'h80;
8'h73: out <= 8'h05;
8'h74: out <= 8'h3f;
8'h75: out <= 8'h21;
8'h76: out <= 8'h70;
8'h77: out <= 8'hf1;
8'h78: out <= 8'h63;
8'h79: out <= 8'h77;
8'h7a: out <= 8'haf;
8'h7b: out <= 8'h42;
8'h7c: out <= 8'h20;
8'h7d: out <= 8'he5;
8'h7e: out <= 8'hfd;
8'h7f: out <= 8'hbf;
8'h80: out <= 8'h81;
8'h81: out <= 8'h18;
8'h82: out <= 8'h26;
8'h83: out <= 8'hc3;
8'h84: out <= 8'hbe;
8'h85: out <= 8'h35;
8'h86: out <= 8'h88;
8'h87: out <= 8'h2e;
8'h88: out <= 8'h93;
8'h89: out <= 8'h55;
8'h8a: out <= 8'hfc;
8'h8b: out <= 8'h7a;
8'h8c: out <= 8'hc8;
8'h8d: out <= 8'hba;
8'h8e: out <= 8'h32;
8'h8f: out <= 8'he6;
8'h90: out <= 8'hc0;
8'h91: out <= 8'h19;
8'h92: out <= 8'h9e;
8'h93: out <= 8'ha3;
8'h94: out <= 8'h44;
8'h95: out <= 8'h54;
8'h96: out <= 8'h3b;
8'h97: out <= 8'h0b;
8'h98: out <= 8'h8c;
8'h99: out <= 8'hc7;
8'h9a: out <= 8'h6b;
8'h9b: out <= 8'h28;
8'h9c: out <= 8'ha7;
8'h9d: out <= 8'hbc;
8'h9e: out <= 8'h16;
8'h9f: out <= 8'had;
8'ha0: out <= 8'hdb;
8'ha1: out <= 8'h64;
8'ha2: out <= 8'h74;
8'ha3: out <= 8'h14;
8'ha4: out <= 8'h92;
8'ha5: out <= 8'h0c;
8'ha6: out <= 8'h48;
8'ha7: out <= 8'hb8;
8'ha8: out <= 8'h9f;
8'ha9: out <= 8'hbd;
8'haa: out <= 8'h43;
8'hab: out <= 8'hc4;
8'hac: out <= 8'h39;
8'had: out <= 8'h31;
8'hae: out <= 8'hd3;
8'haf: out <= 8'hf2;
8'hb0: out <= 8'hd5;
8'hb1: out <= 8'h8b;
8'hb2: out <= 8'h6e;
8'hb3: out <= 8'hda;
8'hb4: out <= 8'h01;
8'hb5: out <= 8'hb1;
8'hb6: out <= 8'h9c;
8'hb7: out <= 8'h49;
8'hb8: out <= 8'hd8;
8'hb9: out <= 8'hac;
8'hba: out <= 8'hf3;
8'hbb: out <= 8'hcf;
8'hbc: out <= 8'hca;
8'hbd: out <= 8'hf4;
8'hbe: out <= 8'h47;
8'hbf: out <= 8'h10;
8'hc0: out <= 8'h6f;
8'hc1: out <= 8'hf0;
8'hc2: out <= 8'h4a;
8'hc3: out <= 8'h5c;
8'hc4: out <= 8'h38;
8'hc5: out <= 8'h57;
8'hc6: out <= 8'h73;
8'hc7: out <= 8'h97;
8'hc8: out <= 8'hcb;
8'hc9: out <= 8'ha1;
8'hca: out <= 8'he8;
8'hcb: out <= 8'h3e;
8'hcc: out <= 8'h96;
8'hcd: out <= 8'h61;
8'hce: out <= 8'h0d;
8'hcf: out <= 8'h0f;
8'hd0: out <= 8'he0;
8'hd1: out <= 8'h7c;
8'hd2: out <= 8'h71;
8'hd3: out <= 8'hcc;
8'hd4: out <= 8'h90;
8'hd5: out <= 8'h06;
8'hd6: out <= 8'hf7;
8'hd7: out <= 8'h1c;
8'hd8: out <= 8'hc2;
8'hd9: out <= 8'h6a;
8'hda: out <= 8'hae;
8'hdb: out <= 8'h69;
8'hdc: out <= 8'h17;
8'hdd: out <= 8'h99;
8'hde: out <= 8'h3a;
8'hdf: out <= 8'h27;
8'he0: out <= 8'hd9;
8'he1: out <= 8'heb;
8'he2: out <= 8'h2b;
8'he3: out <= 8'h22;
8'he4: out <= 8'hd2;
8'he5: out <= 8'ha9;
8'he6: out <= 8'h07;
8'he7: out <= 8'h33;
8'he8: out <= 8'h2d;
8'he9: out <= 8'h3c;
8'hea: out <= 8'h15;
8'heb: out <= 8'hc9;
8'hec: out <= 8'h87;
8'hed: out <= 8'haa;
8'hee: out <= 8'h50;
8'hef: out <= 8'ha5;
8'hf0: out <= 8'h03;
8'hf1: out <= 8'h59;
8'hf2: out <= 8'h09;
8'hf3: out <= 8'h1a;
8'hf4: out <= 8'h65;
8'hf5: out <= 8'hd7;
8'hf6: out <= 8'h84;
8'hf7: out <= 8'hd0;
8'hf8: out <= 8'h82;
8'hf9: out <= 8'h29;
8'hfa: out <= 8'h5a;
8'hfb: out <= 8'h1e;
8'hfc: out <= 8'h7b;
8'hfd: out <= 8'ha8;
8'hfe: out <= 8'h6d;
8'hff: out <= 8'h2c;
endcase
endmodule
|
//************************************************************************
// Copyright 2022 Massachusets Institute of Technology
// SPDX short identifier: BSD-2-Clause
//
// File Name: filter_tb.v
// Program: Common Evaluation Platform (CEP)
// Description: This is a unit level testbench for the generated
// IIR filters. It operates in two modes (controlled
// via a DEFINE passed to the simulator.
// Notes: Usable defines:
// CAPTURE - If defined, the test bench will generate
// NUM_SAMPLES of random inputs and capture the outputs
// to CAPTURE_FILE for subsequent verification.
// VERIFY - If defined (CAPTURE has a higher priority),
// the testbench will use the CAPTURE_FILE to verify the
// device under test still behaves as expected.
//
//************************************************************************
`timescale 1ns/1ns
// Provide a default for NUM_SAMPLES in the event it was not
// previously defined
`ifndef NUM_SAMPLES
`define NUM_SAMPLES 100
`endif
// Define the default capture file (if not defined)
`ifndef CAPTURE_FILE
`define CAPTURE_FILE filter_tb_capture.log
`endif
// Define the DUT if not define
`ifndef DUT_NAME
`define DUT_NAME filter
`endif
// Misc. Defines
`define DATA_WIDTH 64
`define CLK_PERIOD 10
module filter_tb;
// DUT Signals and other things
reg clk = 0;
reg reset = 1;
reg [`DATA_WIDTH-1:0] inData = 0;
wire [`DATA_WIDTH-1:0] outData;
integer errCnt = 0;
// Clocking block
initial begin
forever #(`CLK_PERIOD/2) clk = !clk;
end
// Instantiate the DUT
`DUT_NAME u1(
.inData (inData),
.clk (clk),
.reset (!reset),
.outData (outData)
);
// The testbench must have either CAPTURE or VERIFY defined (but NOT both)
`ifndef CAPTURE
`ifndef VERIFY
initial begin
$display("ERROR: CAPTURE or VERIFY must be defined");
$fatal;
end
`endif
`endif
`ifdef CAPTURE
`ifdef VERIFY
initial begin
$display("ERROR: CAPTURE and VERIFY cannot both be defined");
$fatal;
end
`endif
`endif
// CAPTURE mode
// When operating in CAPTURE mode, the testbench will generate a random set of
// input vectors (64-bits each) and capture the output (following a release
// from reset). The I/O pair will be saved to CAPTURE_FILE
`ifdef CAPTURE
initial begin
inData = 0;
reset = 1;
repeat (5) @(posedge clk);
reset = 0;
repeat (5) @(posedge clk);
captureData();
$finish;
end
`endif
// VERIFY mode
// When operating in VERIFY mode, the testbench will read input and output pairs
// and check that they behave as expected
`ifdef VERIFY
initial begin
inData = 0;
reset = 1;
repeat (5) @(posedge clk);
reset = 0;
repeat (5) @(posedge clk);
// Display some status
playbackData();
$finish;
end
`endif
//
// Task : captureData
// Funcion :
//
task captureData;
// File Pointer
integer fp;
// Loop variable
integer i;
begin
// open file to store input/output
$display("Capturing %0d samples into file %s", `NUM_SAMPLES, `CAPTURE_FILE);
fp = $fopen(`CAPTURE_FILE, "w");
// Generate NUM_SAMPLES random samples
for (i = 0; i < `NUM_SAMPLES; i = i + 1) begin
// Jump to positive edge of the clock
@(posedge clk);
// Generate a random 64-bit vector
// A single $urandom call will only give up to 32-bits
inData[63:32] = $urandom;
inData[31:0] = $urandom;
// Write the random number to the capture file
$fwrite(fp, "%016x_", inData);
// Plan to capture the data at the negative clock edge
@(negedge clk);
// Write the output data
$fwrite(fp, "%016x\n", outData);
end
// Close the capture file
$fclose(fp);
end
endtask // end captureData
//
// Task : playbackData
// Funcion :
//
task playbackData;
// Loop variable
integer i;
// Temporary buffer
reg [`DATA_WIDTH*2 - 1 : 0] buffer[`NUM_SAMPLES - 1 : 0];
// Hold the expected data for comparison
reg [`DATA_WIDTH - 1:0] expData;
begin
// Display some status
$display("Verifying %0d samples from file %s", `NUM_SAMPLES, `CAPTURE_FILE);
// Read the samples data from the capture file
$readmemh(`CAPTURE_FILE, buffer);
// Read NUM_SAMPLES from file, stimulate the input, and compare to the expected output
for (i = 0; i < `NUM_SAMPLES; i = i + 1) begin
// Jump to positive edge of the clock
@(posedge clk);
// Extract data from the currently selected buffer
{inData, expData} = buffer[i];
// Plan to capture the data at the negative clock edge
@(negedge clk);
// Compare expected vs actual output data
if (outData != expData) begin
$display("ERROR: miscompared at sample %0d outData (exp/act) = %016x / %016x", i, expData, outData);
errCnt = errCnt + 1;
end
end // end for
//
// print summary
//
if (errCnt) begin
$display("==== TEST FAILED with %0d errors ====", errCnt);
end else begin
$display("==== TEST PASSED ====");
end
end
endtask // end captureData
endmodule // end filter_tb |
[//]: # (Copyright 2022 Massachusets Institute of Technology)
[//]: # (SPDX short identifier: BSD-2-Clause)
[](https://zenodo.org/badge/latestdoi/108179132)
[](https://opensource.org/licenses/BSD-2-Clause)
<p align="center">
Copyright 2022 Massachusets Institute of Technology
</p>
## Auto-FIR Script
The auto-fir.py script generates a randomized variant of the filter as described here: [Spiral Project Filter Gen](http://www.spiral.net/hardware/filter.html)
Executing `auto-fir.py -h` will print a complete list of script options.
Simulation performs cycle level comparisons and assumes Modelsim/Questasim is in the current path.
Example usage:
```
./auto-fir.py -b -v -a <-- Build the FIR generator (if not available) and
generate a filter with default settings. Verilog
identifiers will be randomized
./auto-fir.py -sg -v <-- With the filter built, generate a series of random
test vectors and save the results
./auto-fir.py -sv -v <-- Re-run the simulation and verify the vectors still pass
```
All generated files are implicitly included in .gitignore and are thus not tracked by git.
Caution should be taken when running the auto-fir.py script with the `--clean` or `--allclean` switches.
The following files will be deleted with `--clean`:
```
./firgen/*
./synth/*
./outputs/*
./work/*
./__pycache__/*
transcript
*.firlog
```
If `--allclean` is specified, then following ADDITIONAL files will be deleted:
```
firgen.tgz
rm -f synth-jan-14-2009.tar.gz
```
## Ubuntu 18.04 note:
If running the build on Ubuntu 18.04, you'll need to ensure rthe Verilog-Perl module is installed.
This can be accomplished by running the following command:
```
sudo cpan install Verilog-Perl
```
#### Return to the root CEP [README](../../README.md)
|
/////////////////////////////////////////////////////////////////////
//// ////
//// CRP ////
//// DES Crypt Module ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
module crp(clk,reset, P, R, K_sub);
/* verilator lint_off LITENDIAN */
output [1:32] P;
input [1:32] R;
input [1:48] K_sub;
input reset;
input clk;
wire [1:48] E;
wire [1:48] X;
wire [1:32] S;
/* verilator lint_on LITENDIAN */
assign E[1:48] = { R[32], R[1], R[2], R[3], R[4], R[5], R[4], R[5],
R[6], R[7], R[8], R[9], R[8], R[9], R[10], R[11],
R[12], R[13], R[12], R[13], R[14], R[15], R[16],
R[17], R[16], R[17], R[18], R[19], R[20], R[21],
R[20], R[21], R[22], R[23], R[24], R[25], R[24],
R[25], R[26], R[27], R[28], R[29], R[28], R[29],
R[30], R[31], R[32], R[1]};
assign X = E ^ K_sub;
sbox1 u0( .addr(X[01:06]), .dout(S[01:04]) , .reset(reset), .clk(clk));
sbox2 u1( .addr(X[07:12]), .dout(S[05:08]) , .reset(reset), .clk(clk));
sbox3 u2( .addr(X[13:18]), .dout(S[09:12]) , .reset(reset), .clk(clk));
sbox4 u3( .addr(X[19:24]), .dout(S[13:16]) , .reset(reset), .clk(clk));
sbox5 u4( .addr(X[25:30]), .dout(S[17:20]) , .reset(reset), .clk(clk));
sbox6 u5( .addr(X[31:36]), .dout(S[21:24]) , .reset(reset), .clk(clk));
sbox7 u6( .addr(X[37:42]), .dout(S[25:28]) , .reset(reset), .clk(clk));
sbox8 u7( .addr(X[43:48]), .dout(S[29:32]) , .reset(reset), .clk(clk));
assign P[1:32] = { S[16], S[7], S[20], S[21], S[29], S[12], S[28],
S[17], S[1], S[15], S[23], S[26], S[5], S[18],
S[31], S[10], S[2], S[8], S[24], S[14], S[32],
S[27], S[3], S[9], S[19], S[13], S[30], S[6],
S[22], S[11], S[4], S[25]};
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// DES ////
//// DES Top Level module ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
module des3(clk, reset, desOut, out_valid, start, desIn, key1, key2, key3, decrypt);
output reg[63:0] desOut;
output out_valid;
input start;
input [63:0] desIn;
input [55:0] key1;
input [55:0] key2;
input [55:0] key3;
input decrypt;
input clk;
input reset;
/* verilator lint_off LITENDIAN */
wire [1:48] K_sub;
wire [1:64] IP, FP;
reg [1:64] FP_R;
reg [1:32] L, R;
wire [1:32] Xin;
wire [1:32] Lout;
wire [1:32] Rout;
wire [1:32] out;
/* verilator lint_on LITENDIAN */
reg [5:0] roundSel;
reg start_r;
always @(posedge clk)
begin
if (reset)
start_r <= 1'b0;
else
start_r <= start;
end
wire start_posedge = start & ~start_r;
// tony duong 04/21/2020: not used at all so removed
//reg [7:0] validCounter;
wire [63:0] des;
always @ (posedge clk)
begin
if (reset | start_posedge)
begin
roundSel <= 6'h00;
end
else if(~out_valid)
begin
roundSel <= roundSel +1;
end
end
assign out_valid = (roundSel == 6'h30);
always @ (posedge clk)
begin
if (reset)
begin
desOut <= 64'h0000000000000000;
end
else if(!out_valid)
begin
desOut <= des;
end
end
crp u0(
.clk(clk),
.reset(reset),
.P(out),
.R(Lout),
.K_sub(K_sub));
// Select a subkey from key.
key_sel3 u1(
.clk(clk),
.reset(reset),
.K_sub(K_sub),
.key1(key1),
.key2(key2),
.key3(key3),
.roundSel(roundSel),
.decrypt(decrypt)
);
assign Lout = (roundSel == 0) ? IP[33:64] : ((roundSel == 16) ? FP_R[33:64] : ((roundSel == 32) ? FP_R[33:64] : R));
assign Xin = (roundSel == 0) ? IP[01:32] : ((roundSel == 16) ? FP_R[01:32] : ((roundSel == 32) ? FP_R[01:32] : L));
assign Rout = Xin ^ out;
assign FP = { Rout, Lout};
always @(posedge clk)
begin
if (reset)
begin
FP_R <= 0;
L <= 0;
R <= 0;
end
else
begin
L <= Lout;
R <= Rout;
FP_R <= FP;
end
end
// Perform initial permutation
assign IP[1:64] = {desIn[06], desIn[14], desIn[22], desIn[30], desIn[38], desIn[46],
desIn[54], desIn[62], desIn[04], desIn[12], desIn[20], desIn[28],
desIn[36], desIn[44], desIn[52], desIn[60], desIn[02], desIn[10],
desIn[18], desIn[26], desIn[34], desIn[42], desIn[50], desIn[58],
desIn[00], desIn[08], desIn[16], desIn[24], desIn[32], desIn[40],
desIn[48], desIn[56], desIn[07], desIn[15], desIn[23], desIn[31],
desIn[39], desIn[47], desIn[55], desIn[63], desIn[05], desIn[13],
desIn[21], desIn[29], desIn[37], desIn[45], desIn[53], desIn[61],
desIn[03], desIn[11], desIn[19], desIn[27], desIn[35], desIn[43],
desIn[51], desIn[59], desIn[01], desIn[09], desIn[17], desIn[25],
desIn[33], desIn[41], desIn[49], desIn[57] };
// Perform final permutation
assign des = {FP[40], FP[08], FP[48], FP[16], FP[56], FP[24], FP[64], FP[32],
FP[39], FP[07], FP[47], FP[15], FP[55], FP[23], FP[63], FP[31],
FP[38], FP[06], FP[46], FP[14], FP[54], FP[22], FP[62], FP[30],
FP[37], FP[05], FP[45], FP[13], FP[53], FP[21], FP[61], FP[29],
FP[36], FP[04], FP[44], FP[12], FP[52], FP[20], FP[60], FP[28],
FP[35], FP[03], FP[43], FP[11], FP[51], FP[19], FP[59], FP[27],
FP[34], FP[02], FP[42], FP[10], FP[50], FP[18], FP[58], FP[26],
FP[33], FP[01], FP[41], FP[09], FP[49], FP[17], FP[57], FP[25] };
endmodule
|
//************************************************************************
// Copyright 2022 Massachusets Institute of Technology
// SPDX License Identifier: BSD-2-Clause
//
// File Name: des3_mock_tss.sv
// Program: Common Evaluation Platform (CEP)
// Description:
// Notes:
//************************************************************************
`timescale 1ns/1ns
module des3_mock_tss import llki_pkg::*; (
// Clock and Reset
input wire clk,
input wire rst,
// Core I/O
input wire start,
input wire [63:0] desIn,
input wire [55:0] key1,
input wire [55:0] key2,
input wire [55:0] key3,
input wire decrypt,
output wire [63:0] desOut,
output wire out_valid,
// LLKI Discrete I/O
input [63:0] llkid_key_data,
input llkid_key_valid,
output reg llkid_key_ready,
output reg llkid_key_complete,
input llkid_clear_key,
output reg llkid_clear_key_ack
);
// Internal signals & localparams
localparam KEY_WORDS = DES3_MOCK_TSS_NUM_KEY_WORDS;
reg [(64*KEY_WORDS) - 1:0] llkid_key_register;
wire [(64*KEY_WORDS) - 1:0] mock_tss_desIn;
//------------------------------------------------------------------
// Instantiate the Mock TSS Finite State Machine
//------------------------------------------------------------------
mock_tss_fsm #(
.KEY_WORDS (KEY_WORDS)
) mock_tss_fsm_inst (
.clk (clk),
.rst (rst),
.llkid_key_data (llkid_key_data),
.llkid_key_valid (llkid_key_valid),
.llkid_key_ready (llkid_key_ready),
.llkid_key_complete (llkid_key_complete),
.llkid_clear_key (llkid_clear_key),
.llkid_clear_key_ack (llkid_clear_key_ack),
.llkid_key_register (llkid_key_register)
);
//------------------------------------------------------------------
//------------------------------------------------------------------
// Create the Mock TSS input into the original core
//------------------------------------------------------------------
genvar i;
generate
for (i = 0; i < KEY_WORDS; i = i + 1) begin
assign mock_tss_desIn[64*i +: 64] = DES3_MOCK_TSS_KEY_WORDS[i] ^
llkid_key_register[64*i +: 64] ^
desIn[64*i +: 64];
end
endgenerate
//------------------------------------------------------------------
//------------------------------------------------------------------
// Instantiate the original core
//------------------------------------------------------------------
des3 des3_inst (
.clk (clk),
.reset (rst),
.start (start),
.desIn (mock_tss_desIn),
.key1 (key1),
.key2 (key2),
.key3 (key3),
.decrypt (decrypt),
.desOut (desOut),
.out_valid (out_valid)
);
//------------------------------------------------------------------
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// KEY_SEL ////
//// Select one of 16 sub-keys for round ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
module key_sel3(clk, reset, K_sub, key1, key2, key3, roundSel, decrypt);
/* verilator lint_off LITENDIAN */
output [1:48] K_sub;
/* verilator lint_on LITENDIAN */
input [55:0] key1, key2, key3;
input [5:0] roundSel;
input decrypt;
input clk;
input reset;
wire decrypt_int;
reg [55:0] K;
reg [1:48] K_sub;
/* verilator lint_off LITENDIAN */
wire [1:48] K1, K2, K3, K4, K5, K6, K7, K8, K9;
wire [1:48] K10, K11, K12, K13, K14, K15, K16;
/* verilator lint_on LITENDIAN */
always @(clk)
begin
if (reset)
K = 56'b0;
else
case ({decrypt, roundSel[5:4]}) // synopsys full_case parallel_case
3'b0_00:
K = key1;
3'b0_01:
K = key2;
3'b0_10:
K = key3;
3'b1_00:
K = key3;
3'b1_01:
K = key2;
3'b1_10:
K = key1;
3'b0_11:
K = 56'b0;
3'b1_11:
K = 56'b0;
endcase
end
assign decrypt_int = (roundSel[5:4]==2'h1) ? !decrypt : decrypt;
always @(*)
begin
case(roundSel[3:0]) // synopsys full_case parallel_case
0:
K_sub = K1;
1:
K_sub = K2;
2:
K_sub = K3;
3:
K_sub = K4;
4:
K_sub = K5;
5:
K_sub = K6;
6:
K_sub = K7;
7:
K_sub = K8;
8:
K_sub = K9;
9:
K_sub = K10;
10:
K_sub = K11;
11:
K_sub = K12;
12:
K_sub = K13;
13:
K_sub = K14;
14:
K_sub = K15;
15:
K_sub = K16;
endcase
end
assign K16[1] = decrypt_int ? K[47] : K[40];
assign K16[2] = decrypt_int ? K[11] : K[4];
assign K16[3] = decrypt_int ? K[26] : K[19];
assign K16[4] = decrypt_int ? K[3] : K[53];
assign K16[5] = decrypt_int ? K[13] : K[6];
assign K16[6] = decrypt_int ? K[41] : K[34];
assign K16[7] = decrypt_int ? K[27] : K[20];
assign K16[8] = decrypt_int ? K[6] : K[24];
assign K16[9] = decrypt_int ? K[54] : K[47];
assign K16[10] = decrypt_int ? K[48] : K[41];
assign K16[11] = decrypt_int ? K[39] : K[32];
assign K16[12] = decrypt_int ? K[19] : K[12];
assign K16[13] = decrypt_int ? K[53] : K[46];
assign K16[14] = decrypt_int ? K[25] : K[18];
assign K16[15] = decrypt_int ? K[33] : K[26];
assign K16[16] = decrypt_int ? K[34] : K[27];
assign K16[17] = decrypt_int ? K[17] : K[10];
assign K16[18] = decrypt_int ? K[5] : K[55];
assign K16[19] = decrypt_int ? K[4] : K[54];
assign K16[20] = decrypt_int ? K[55] : K[48];
assign K16[21] = decrypt_int ? K[24] : K[17];
assign K16[22] = decrypt_int ? K[32] : K[25];
assign K16[23] = decrypt_int ? K[40] : K[33];
assign K16[24] = decrypt_int ? K[20] : K[13];
assign K16[25] = decrypt_int ? K[36] : K[29];
assign K16[26] = decrypt_int ? K[31] : K[51];
assign K16[27] = decrypt_int ? K[21] : K[14];
assign K16[28] = decrypt_int ? K[8] : K[1];
assign K16[29] = decrypt_int ? K[23] : K[16];
assign K16[30] = decrypt_int ? K[52] : K[45];
assign K16[31] = decrypt_int ? K[14] : K[7];
assign K16[32] = decrypt_int ? K[29] : K[22];
assign K16[33] = decrypt_int ? K[51] : K[44];
assign K16[34] = decrypt_int ? K[9] : K[2];
assign K16[35] = decrypt_int ? K[35] : K[28];
assign K16[36] = decrypt_int ? K[30] : K[23];
assign K16[37] = decrypt_int ? K[2] : K[50];
assign K16[38] = decrypt_int ? K[37] : K[30];
assign K16[39] = decrypt_int ? K[22] : K[15];
assign K16[40] = decrypt_int ? K[0] : K[52];
assign K16[41] = decrypt_int ? K[42] : K[35];
assign K16[42] = decrypt_int ? K[38] : K[31];
assign K16[43] = decrypt_int ? K[16] : K[9];
assign K16[44] = decrypt_int ? K[43] : K[36];
assign K16[45] = decrypt_int ? K[44] : K[37];
assign K16[46] = decrypt_int ? K[1] : K[49];
assign K16[47] = decrypt_int ? K[7] : K[0];
assign K16[48] = decrypt_int ? K[28] : K[21];
assign K15[1] = decrypt_int ? K[54] : K[33];
assign K15[2] = decrypt_int ? K[18] : K[54];
assign K15[3] = decrypt_int ? K[33] : K[12];
assign K15[4] = decrypt_int ? K[10] : K[46];
assign K15[5] = decrypt_int ? K[20] : K[24];
assign K15[6] = decrypt_int ? K[48] : K[27];
assign K15[7] = decrypt_int ? K[34] : K[13];
assign K15[8] = decrypt_int ? K[13] : K[17];
assign K15[9] = decrypt_int ? K[4] : K[40];
assign K15[10] = decrypt_int ? K[55] : K[34];
assign K15[11] = decrypt_int ? K[46] : K[25];
assign K15[12] = decrypt_int ? K[26] : K[5];
assign K15[13] = decrypt_int ? K[3] : K[39];
assign K15[14] = decrypt_int ? K[32] : K[11];
assign K15[15] = decrypt_int ? K[40] : K[19];
assign K15[16] = decrypt_int ? K[41] : K[20];
assign K15[17] = decrypt_int ? K[24] : K[3];
assign K15[18] = decrypt_int ? K[12] : K[48];
assign K15[19] = decrypt_int ? K[11] : K[47];
assign K15[20] = decrypt_int ? K[5] : K[41];
assign K15[21] = decrypt_int ? K[6] : K[10];
assign K15[22] = decrypt_int ? K[39] : K[18];
assign K15[23] = decrypt_int ? K[47] : K[26];
assign K15[24] = decrypt_int ? K[27] : K[6];
assign K15[25] = decrypt_int ? K[43] : K[22];
assign K15[26] = decrypt_int ? K[38] : K[44];
assign K15[27] = decrypt_int ? K[28] : K[7];
assign K15[28] = decrypt_int ? K[15] : K[49];
assign K15[29] = decrypt_int ? K[30] : K[9];
assign K15[30] = decrypt_int ? K[0] : K[38];
assign K15[31] = decrypt_int ? K[21] : K[0];
assign K15[32] = decrypt_int ? K[36] : K[15];
assign K15[33] = decrypt_int ? K[31] : K[37];
assign K15[34] = decrypt_int ? K[16] : K[50];
assign K15[35] = decrypt_int ? K[42] : K[21];
assign K15[36] = decrypt_int ? K[37] : K[16];
assign K15[37] = decrypt_int ? K[9] : K[43];
assign K15[38] = decrypt_int ? K[44] : K[23];
assign K15[39] = decrypt_int ? K[29] : K[8];
assign K15[40] = decrypt_int ? K[7] : K[45];
assign K15[41] = decrypt_int ? K[49] : K[28];
assign K15[42] = decrypt_int ? K[45] : K[51];
assign K15[43] = decrypt_int ? K[23] : K[2];
assign K15[44] = decrypt_int ? K[50] : K[29];
assign K15[45] = decrypt_int ? K[51] : K[30];
assign K15[46] = decrypt_int ? K[8] : K[42];
assign K15[47] = decrypt_int ? K[14] : K[52];
assign K15[48] = decrypt_int ? K[35] : K[14];
assign K14[1] = decrypt_int ? K[11] : K[19];
assign K14[2] = decrypt_int ? K[32] : K[40];
assign K14[3] = decrypt_int ? K[47] : K[55];
assign K14[4] = decrypt_int ? K[24] : K[32];
assign K14[5] = decrypt_int ? K[34] : K[10];
assign K14[6] = decrypt_int ? K[5] : K[13];
assign K14[7] = decrypt_int ? K[48] : K[24];
assign K14[8] = decrypt_int ? K[27] : K[3];
assign K14[9] = decrypt_int ? K[18] : K[26];
assign K14[10] = decrypt_int ? K[12] : K[20];
assign K14[11] = decrypt_int ? K[3] : K[11];
assign K14[12] = decrypt_int ? K[40] : K[48];
assign K14[13] = decrypt_int ? K[17] : K[25];
assign K14[14] = decrypt_int ? K[46] : K[54];
assign K14[15] = decrypt_int ? K[54] : K[5];
assign K14[16] = decrypt_int ? K[55] : K[6];
assign K14[17] = decrypt_int ? K[13] : K[46];
assign K14[18] = decrypt_int ? K[26] : K[34];
assign K14[19] = decrypt_int ? K[25] : K[33];
assign K14[20] = decrypt_int ? K[19] : K[27];
assign K14[21] = decrypt_int ? K[20] : K[53];
assign K14[22] = decrypt_int ? K[53] : K[4];
assign K14[23] = decrypt_int ? K[4] : K[12];
assign K14[24] = decrypt_int ? K[41] : K[17];
assign K14[25] = decrypt_int ? K[2] : K[8];
assign K14[26] = decrypt_int ? K[52] : K[30];
assign K14[27] = decrypt_int ? K[42] : K[52];
assign K14[28] = decrypt_int ? K[29] : K[35];
assign K14[29] = decrypt_int ? K[44] : K[50];
assign K14[30] = decrypt_int ? K[14] : K[51];
assign K14[31] = decrypt_int ? K[35] : K[45];
assign K14[32] = decrypt_int ? K[50] : K[1];
assign K14[33] = decrypt_int ? K[45] : K[23];
assign K14[34] = decrypt_int ? K[30] : K[36];
assign K14[35] = decrypt_int ? K[1] : K[7];
assign K14[36] = decrypt_int ? K[51] : K[2];
assign K14[37] = decrypt_int ? K[23] : K[29];
assign K14[38] = decrypt_int ? K[31] : K[9];
assign K14[39] = decrypt_int ? K[43] : K[49];
assign K14[40] = decrypt_int ? K[21] : K[31];
assign K14[41] = decrypt_int ? K[8] : K[14];
assign K14[42] = decrypt_int ? K[0] : K[37];
assign K14[43] = decrypt_int ? K[37] : K[43];
assign K14[44] = decrypt_int ? K[9] : K[15];
assign K14[45] = decrypt_int ? K[38] : K[16];
assign K14[46] = decrypt_int ? K[22] : K[28];
assign K14[47] = decrypt_int ? K[28] : K[38];
assign K14[48] = decrypt_int ? K[49] : K[0];
assign K13[1] = decrypt_int ? K[25] : K[5];
assign K13[2] = decrypt_int ? K[46] : K[26];
assign K13[3] = decrypt_int ? K[4] : K[41];
assign K13[4] = decrypt_int ? K[13] : K[18];
assign K13[5] = decrypt_int ? K[48] : K[53];
assign K13[6] = decrypt_int ? K[19] : K[24];
assign K13[7] = decrypt_int ? K[5] : K[10];
assign K13[8] = decrypt_int ? K[41] : K[46];
assign K13[9] = decrypt_int ? K[32] : K[12];
assign K13[10] = decrypt_int ? K[26] : K[6];
assign K13[11] = decrypt_int ? K[17] : K[54];
assign K13[12] = decrypt_int ? K[54] : K[34];
assign K13[13] = decrypt_int ? K[6] : K[11];
assign K13[14] = decrypt_int ? K[3] : K[40];
assign K13[15] = decrypt_int ? K[11] : K[48];
assign K13[16] = decrypt_int ? K[12] : K[17];
assign K13[17] = decrypt_int ? K[27] : K[32];
assign K13[18] = decrypt_int ? K[40] : K[20];
assign K13[19] = decrypt_int ? K[39] : K[19];
assign K13[20] = decrypt_int ? K[33] : K[13];
assign K13[21] = decrypt_int ? K[34] : K[39];
assign K13[22] = decrypt_int ? K[10] : K[47];
assign K13[23] = decrypt_int ? K[18] : K[55];
assign K13[24] = decrypt_int ? K[55] : K[3];
assign K13[25] = decrypt_int ? K[16] : K[49];
assign K13[26] = decrypt_int ? K[7] : K[16];
assign K13[27] = decrypt_int ? K[1] : K[38];
assign K13[28] = decrypt_int ? K[43] : K[21];
assign K13[29] = decrypt_int ? K[31] : K[36];
assign K13[30] = decrypt_int ? K[28] : K[37];
assign K13[31] = decrypt_int ? K[49] : K[31];
assign K13[32] = decrypt_int ? K[9] : K[42];
assign K13[33] = decrypt_int ? K[0] : K[9];
assign K13[34] = decrypt_int ? K[44] : K[22];
assign K13[35] = decrypt_int ? K[15] : K[52];
assign K13[36] = decrypt_int ? K[38] : K[43];
assign K13[37] = decrypt_int ? K[37] : K[15];
assign K13[38] = decrypt_int ? K[45] : K[50];
assign K13[39] = decrypt_int ? K[2] : K[35];
assign K13[40] = decrypt_int ? K[35] : K[44];
assign K13[41] = decrypt_int ? K[22] : K[0];
assign K13[42] = decrypt_int ? K[14] : K[23];
assign K13[43] = decrypt_int ? K[51] : K[29];
assign K13[44] = decrypt_int ? K[23] : K[1];
assign K13[45] = decrypt_int ? K[52] : K[2];
assign K13[46] = decrypt_int ? K[36] : K[14];
assign K13[47] = decrypt_int ? K[42] : K[51];
assign K13[48] = decrypt_int ? K[8] : K[45];
assign K12[1] = decrypt_int ? K[39] : K[48];
assign K12[2] = decrypt_int ? K[3] : K[12];
assign K12[3] = decrypt_int ? K[18] : K[27];
assign K12[4] = decrypt_int ? K[27] : K[4];
assign K12[5] = decrypt_int ? K[5] : K[39];
assign K12[6] = decrypt_int ? K[33] : K[10];
assign K12[7] = decrypt_int ? K[19] : K[53];
assign K12[8] = decrypt_int ? K[55] : K[32];
assign K12[9] = decrypt_int ? K[46] : K[55];
assign K12[10] = decrypt_int ? K[40] : K[17];
assign K12[11] = decrypt_int ? K[6] : K[40];
assign K12[12] = decrypt_int ? K[11] : K[20];
assign K12[13] = decrypt_int ? K[20] : K[54];
assign K12[14] = decrypt_int ? K[17] : K[26];
assign K12[15] = decrypt_int ? K[25] : K[34];
assign K12[16] = decrypt_int ? K[26] : K[3];
assign K12[17] = decrypt_int ? K[41] : K[18];
assign K12[18] = decrypt_int ? K[54] : K[6];
assign K12[19] = decrypt_int ? K[53] : K[5];
assign K12[20] = decrypt_int ? K[47] : K[24];
assign K12[21] = decrypt_int ? K[48] : K[25];
assign K12[22] = decrypt_int ? K[24] : K[33];
assign K12[23] = decrypt_int ? K[32] : K[41];
assign K12[24] = decrypt_int ? K[12] : K[46];
assign K12[25] = decrypt_int ? K[30] : K[35];
assign K12[26] = decrypt_int ? K[21] : K[2];
assign K12[27] = decrypt_int ? K[15] : K[51];
assign K12[28] = decrypt_int ? K[2] : K[7];
assign K12[29] = decrypt_int ? K[45] : K[22];
assign K12[30] = decrypt_int ? K[42] : K[23];
assign K12[31] = decrypt_int ? K[8] : K[44];
assign K12[32] = decrypt_int ? K[23] : K[28];
assign K12[33] = decrypt_int ? K[14] : K[50];
assign K12[34] = decrypt_int ? K[31] : K[8];
assign K12[35] = decrypt_int ? K[29] : K[38];
assign K12[36] = decrypt_int ? K[52] : K[29];
assign K12[37] = decrypt_int ? K[51] : K[1];
assign K12[38] = decrypt_int ? K[0] : K[36];
assign K12[39] = decrypt_int ? K[16] : K[21];
assign K12[40] = decrypt_int ? K[49] : K[30];
assign K12[41] = decrypt_int ? K[36] : K[45];
assign K12[42] = decrypt_int ? K[28] : K[9];
assign K12[43] = decrypt_int ? K[38] : K[15];
assign K12[44] = decrypt_int ? K[37] : K[42];
assign K12[45] = decrypt_int ? K[7] : K[43];
assign K12[46] = decrypt_int ? K[50] : K[0];
assign K12[47] = decrypt_int ? K[1] : K[37];
assign K12[48] = decrypt_int ? K[22] : K[31];
assign K11[1] = decrypt_int ? K[53] : K[34];
assign K11[2] = decrypt_int ? K[17] : K[55];
assign K11[3] = decrypt_int ? K[32] : K[13];
assign K11[4] = decrypt_int ? K[41] : K[47];
assign K11[5] = decrypt_int ? K[19] : K[25];
assign K11[6] = decrypt_int ? K[47] : K[53];
assign K11[7] = decrypt_int ? K[33] : K[39];
assign K11[8] = decrypt_int ? K[12] : K[18];
assign K11[9] = decrypt_int ? K[3] : K[41];
assign K11[10] = decrypt_int ? K[54] : K[3];
assign K11[11] = decrypt_int ? K[20] : K[26];
assign K11[12] = decrypt_int ? K[25] : K[6];
assign K11[13] = decrypt_int ? K[34] : K[40];
assign K11[14] = decrypt_int ? K[6] : K[12];
assign K11[15] = decrypt_int ? K[39] : K[20];
assign K11[16] = decrypt_int ? K[40] : K[46];
assign K11[17] = decrypt_int ? K[55] : K[4];
assign K11[18] = decrypt_int ? K[11] : K[17];
assign K11[19] = decrypt_int ? K[10] : K[48];
assign K11[20] = decrypt_int ? K[4] : K[10];
assign K11[21] = decrypt_int ? K[5] : K[11];
assign K11[22] = decrypt_int ? K[13] : K[19];
assign K11[23] = decrypt_int ? K[46] : K[27];
assign K11[24] = decrypt_int ? K[26] : K[32];
assign K11[25] = decrypt_int ? K[44] : K[21];
assign K11[26] = decrypt_int ? K[35] : K[43];
assign K11[27] = decrypt_int ? K[29] : K[37];
assign K11[28] = decrypt_int ? K[16] : K[52];
assign K11[29] = decrypt_int ? K[0] : K[8];
assign K11[30] = decrypt_int ? K[1] : K[9];
assign K11[31] = decrypt_int ? K[22] : K[30];
assign K11[32] = decrypt_int ? K[37] : K[14];
assign K11[33] = decrypt_int ? K[28] : K[36];
assign K11[34] = decrypt_int ? K[45] : K[49];
assign K11[35] = decrypt_int ? K[43] : K[51];
assign K11[36] = decrypt_int ? K[7] : K[15];
assign K11[37] = decrypt_int ? K[38] : K[42];
assign K11[38] = decrypt_int ? K[14] : K[22];
assign K11[39] = decrypt_int ? K[30] : K[7];
assign K11[40] = decrypt_int ? K[8] : K[16];
assign K11[41] = decrypt_int ? K[50] : K[31];
assign K11[42] = decrypt_int ? K[42] : K[50];
assign K11[43] = decrypt_int ? K[52] : K[1];
assign K11[44] = decrypt_int ? K[51] : K[28];
assign K11[45] = decrypt_int ? K[21] : K[29];
assign K11[46] = decrypt_int ? K[9] : K[45];
assign K11[47] = decrypt_int ? K[15] : K[23];
assign K11[48] = decrypt_int ? K[36] : K[44];
assign K10[1] = decrypt_int ? K[10] : K[20];
assign K10[2] = decrypt_int ? K[6] : K[41];
assign K10[3] = decrypt_int ? K[46] : K[24];
assign K10[4] = decrypt_int ? K[55] : K[33];
assign K10[5] = decrypt_int ? K[33] : K[11];
assign K10[6] = decrypt_int ? K[4] : K[39];
assign K10[7] = decrypt_int ? K[47] : K[25];
assign K10[8] = decrypt_int ? K[26] : K[4];
assign K10[9] = decrypt_int ? K[17] : K[27];
assign K10[10] = decrypt_int ? K[11] : K[46];
assign K10[11] = decrypt_int ? K[34] : K[12];
assign K10[12] = decrypt_int ? K[39] : K[17];
assign K10[13] = decrypt_int ? K[48] : K[26];
assign K10[14] = decrypt_int ? K[20] : K[55];
assign K10[15] = decrypt_int ? K[53] : K[6];
assign K10[16] = decrypt_int ? K[54] : K[32];
assign K10[17] = decrypt_int ? K[12] : K[47];
assign K10[18] = decrypt_int ? K[25] : K[3];
assign K10[19] = decrypt_int ? K[24] : K[34];
assign K10[20] = decrypt_int ? K[18] : K[53];
assign K10[21] = decrypt_int ? K[19] : K[54];
assign K10[22] = decrypt_int ? K[27] : K[5];
assign K10[23] = decrypt_int ? K[3] : K[13];
assign K10[24] = decrypt_int ? K[40] : K[18];
assign K10[25] = decrypt_int ? K[31] : K[7];
assign K10[26] = decrypt_int ? K[49] : K[29];
assign K10[27] = decrypt_int ? K[43] : K[23];
assign K10[28] = decrypt_int ? K[30] : K[38];
assign K10[29] = decrypt_int ? K[14] : K[49];
assign K10[30] = decrypt_int ? K[15] : K[50];
assign K10[31] = decrypt_int ? K[36] : K[16];
assign K10[32] = decrypt_int ? K[51] : K[0];
assign K10[33] = decrypt_int ? K[42] : K[22];
assign K10[34] = decrypt_int ? K[0] : K[35];
assign K10[35] = decrypt_int ? K[2] : K[37];
assign K10[36] = decrypt_int ? K[21] : K[1];
assign K10[37] = decrypt_int ? K[52] : K[28];
assign K10[38] = decrypt_int ? K[28] : K[8];
assign K10[39] = decrypt_int ? K[44] : K[52];
assign K10[40] = decrypt_int ? K[22] : K[2];
assign K10[41] = decrypt_int ? K[9] : K[44];
assign K10[42] = decrypt_int ? K[1] : K[36];
assign K10[43] = decrypt_int ? K[7] : K[42];
assign K10[44] = decrypt_int ? K[38] : K[14];
assign K10[45] = decrypt_int ? K[35] : K[15];
assign K10[46] = decrypt_int ? K[23] : K[31];
assign K10[47] = decrypt_int ? K[29] : K[9];
assign K10[48] = decrypt_int ? K[50] : K[30];
assign K9[1] = decrypt_int ? K[24] : K[6];
assign K9[2] = decrypt_int ? K[20] : K[27];
assign K9[3] = decrypt_int ? K[3] : K[10];
assign K9[4] = decrypt_int ? K[12] : K[19];
assign K9[5] = decrypt_int ? K[47] : K[54];
assign K9[6] = decrypt_int ? K[18] : K[25];
assign K9[7] = decrypt_int ? K[4] : K[11];
assign K9[8] = decrypt_int ? K[40] : K[47];
assign K9[9] = decrypt_int ? K[6] : K[13];
assign K9[10] = decrypt_int ? K[25] : K[32];
assign K9[11] = decrypt_int ? K[48] : K[55];
assign K9[12] = decrypt_int ? K[53] : K[3];
assign K9[13] = decrypt_int ? K[5] : K[12];
assign K9[14] = decrypt_int ? K[34] : K[41];
assign K9[15] = decrypt_int ? K[10] : K[17];
assign K9[16] = decrypt_int ? K[11] : K[18];
assign K9[17] = decrypt_int ? K[26] : K[33];
assign K9[18] = decrypt_int ? K[39] : K[46];
assign K9[19] = decrypt_int ? K[13] : K[20];
assign K9[20] = decrypt_int ? K[32] : K[39];
assign K9[21] = decrypt_int ? K[33] : K[40];
assign K9[22] = decrypt_int ? K[41] : K[48];
assign K9[23] = decrypt_int ? K[17] : K[24];
assign K9[24] = decrypt_int ? K[54] : K[4];
assign K9[25] = decrypt_int ? K[45] : K[52];
assign K9[26] = decrypt_int ? K[8] : K[15];
assign K9[27] = decrypt_int ? K[2] : K[9];
assign K9[28] = decrypt_int ? K[44] : K[51];
assign K9[29] = decrypt_int ? K[28] : K[35];
assign K9[30] = decrypt_int ? K[29] : K[36];
assign K9[31] = decrypt_int ? K[50] : K[2];
assign K9[32] = decrypt_int ? K[38] : K[45];
assign K9[33] = decrypt_int ? K[1] : K[8];
assign K9[34] = decrypt_int ? K[14] : K[21];
assign K9[35] = decrypt_int ? K[16] : K[23];
assign K9[36] = decrypt_int ? K[35] : K[42];
assign K9[37] = decrypt_int ? K[7] : K[14];
assign K9[38] = decrypt_int ? K[42] : K[49];
assign K9[39] = decrypt_int ? K[31] : K[38];
assign K9[40] = decrypt_int ? K[36] : K[43];
assign K9[41] = decrypt_int ? K[23] : K[30];
assign K9[42] = decrypt_int ? K[15] : K[22];
assign K9[43] = decrypt_int ? K[21] : K[28];
assign K9[44] = decrypt_int ? K[52] : K[0];
assign K9[45] = decrypt_int ? K[49] : K[1];
assign K9[46] = decrypt_int ? K[37] : K[44];
assign K9[47] = decrypt_int ? K[43] : K[50];
assign K9[48] = decrypt_int ? K[9] : K[16];
assign K8[1] = decrypt_int ? K[6] : K[24];
assign K8[2] = decrypt_int ? K[27] : K[20];
assign K8[3] = decrypt_int ? K[10] : K[3];
assign K8[4] = decrypt_int ? K[19] : K[12];
assign K8[5] = decrypt_int ? K[54] : K[47];
assign K8[6] = decrypt_int ? K[25] : K[18];
assign K8[7] = decrypt_int ? K[11] : K[4];
assign K8[8] = decrypt_int ? K[47] : K[40];
assign K8[9] = decrypt_int ? K[13] : K[6];
assign K8[10] = decrypt_int ? K[32] : K[25];
assign K8[11] = decrypt_int ? K[55] : K[48];
assign K8[12] = decrypt_int ? K[3] : K[53];
assign K8[13] = decrypt_int ? K[12] : K[5];
assign K8[14] = decrypt_int ? K[41] : K[34];
assign K8[15] = decrypt_int ? K[17] : K[10];
assign K8[16] = decrypt_int ? K[18] : K[11];
assign K8[17] = decrypt_int ? K[33] : K[26];
assign K8[18] = decrypt_int ? K[46] : K[39];
assign K8[19] = decrypt_int ? K[20] : K[13];
assign K8[20] = decrypt_int ? K[39] : K[32];
assign K8[21] = decrypt_int ? K[40] : K[33];
assign K8[22] = decrypt_int ? K[48] : K[41];
assign K8[23] = decrypt_int ? K[24] : K[17];
assign K8[24] = decrypt_int ? K[4] : K[54];
assign K8[25] = decrypt_int ? K[52] : K[45];
assign K8[26] = decrypt_int ? K[15] : K[8];
assign K8[27] = decrypt_int ? K[9] : K[2];
assign K8[28] = decrypt_int ? K[51] : K[44];
assign K8[29] = decrypt_int ? K[35] : K[28];
assign K8[30] = decrypt_int ? K[36] : K[29];
assign K8[31] = decrypt_int ? K[2] : K[50];
assign K8[32] = decrypt_int ? K[45] : K[38];
assign K8[33] = decrypt_int ? K[8] : K[1];
assign K8[34] = decrypt_int ? K[21] : K[14];
assign K8[35] = decrypt_int ? K[23] : K[16];
assign K8[36] = decrypt_int ? K[42] : K[35];
assign K8[37] = decrypt_int ? K[14] : K[7];
assign K8[38] = decrypt_int ? K[49] : K[42];
assign K8[39] = decrypt_int ? K[38] : K[31];
assign K8[40] = decrypt_int ? K[43] : K[36];
assign K8[41] = decrypt_int ? K[30] : K[23];
assign K8[42] = decrypt_int ? K[22] : K[15];
assign K8[43] = decrypt_int ? K[28] : K[21];
assign K8[44] = decrypt_int ? K[0] : K[52];
assign K8[45] = decrypt_int ? K[1] : K[49];
assign K8[46] = decrypt_int ? K[44] : K[37];
assign K8[47] = decrypt_int ? K[50] : K[43];
assign K8[48] = decrypt_int ? K[16] : K[9];
assign K7[1] = decrypt_int ? K[20] : K[10];
assign K7[2] = decrypt_int ? K[41] : K[6];
assign K7[3] = decrypt_int ? K[24] : K[46];
assign K7[4] = decrypt_int ? K[33] : K[55];
assign K7[5] = decrypt_int ? K[11] : K[33];
assign K7[6] = decrypt_int ? K[39] : K[4];
assign K7[7] = decrypt_int ? K[25] : K[47];
assign K7[8] = decrypt_int ? K[4] : K[26];
assign K7[9] = decrypt_int ? K[27] : K[17];
assign K7[10] = decrypt_int ? K[46] : K[11];
assign K7[11] = decrypt_int ? K[12] : K[34];
assign K7[12] = decrypt_int ? K[17] : K[39];
assign K7[13] = decrypt_int ? K[26] : K[48];
assign K7[14] = decrypt_int ? K[55] : K[20];
assign K7[15] = decrypt_int ? K[6] : K[53];
assign K7[16] = decrypt_int ? K[32] : K[54];
assign K7[17] = decrypt_int ? K[47] : K[12];
assign K7[18] = decrypt_int ? K[3] : K[25];
assign K7[19] = decrypt_int ? K[34] : K[24];
assign K7[20] = decrypt_int ? K[53] : K[18];
assign K7[21] = decrypt_int ? K[54] : K[19];
assign K7[22] = decrypt_int ? K[5] : K[27];
assign K7[23] = decrypt_int ? K[13] : K[3];
assign K7[24] = decrypt_int ? K[18] : K[40];
assign K7[25] = decrypt_int ? K[7] : K[31];
assign K7[26] = decrypt_int ? K[29] : K[49];
assign K7[27] = decrypt_int ? K[23] : K[43];
assign K7[28] = decrypt_int ? K[38] : K[30];
assign K7[29] = decrypt_int ? K[49] : K[14];
assign K7[30] = decrypt_int ? K[50] : K[15];
assign K7[31] = decrypt_int ? K[16] : K[36];
assign K7[32] = decrypt_int ? K[0] : K[51];
assign K7[33] = decrypt_int ? K[22] : K[42];
assign K7[34] = decrypt_int ? K[35] : K[0];
assign K7[35] = decrypt_int ? K[37] : K[2];
assign K7[36] = decrypt_int ? K[1] : K[21];
assign K7[37] = decrypt_int ? K[28] : K[52];
assign K7[38] = decrypt_int ? K[8] : K[28];
assign K7[39] = decrypt_int ? K[52] : K[44];
assign K7[40] = decrypt_int ? K[2] : K[22];
assign K7[41] = decrypt_int ? K[44] : K[9];
assign K7[42] = decrypt_int ? K[36] : K[1];
assign K7[43] = decrypt_int ? K[42] : K[7];
assign K7[44] = decrypt_int ? K[14] : K[38];
assign K7[45] = decrypt_int ? K[15] : K[35];
assign K7[46] = decrypt_int ? K[31] : K[23];
assign K7[47] = decrypt_int ? K[9] : K[29];
assign K7[48] = decrypt_int ? K[30] : K[50];
assign K6[1] = decrypt_int ? K[34] : K[53];
assign K6[2] = decrypt_int ? K[55] : K[17];
assign K6[3] = decrypt_int ? K[13] : K[32];
assign K6[4] = decrypt_int ? K[47] : K[41];
assign K6[5] = decrypt_int ? K[25] : K[19];
assign K6[6] = decrypt_int ? K[53] : K[47];
assign K6[7] = decrypt_int ? K[39] : K[33];
assign K6[8] = decrypt_int ? K[18] : K[12];
assign K6[9] = decrypt_int ? K[41] : K[3];
assign K6[10] = decrypt_int ? K[3] : K[54];
assign K6[11] = decrypt_int ? K[26] : K[20];
assign K6[12] = decrypt_int ? K[6] : K[25];
assign K6[13] = decrypt_int ? K[40] : K[34];
assign K6[14] = decrypt_int ? K[12] : K[6];
assign K6[15] = decrypt_int ? K[20] : K[39];
assign K6[16] = decrypt_int ? K[46] : K[40];
assign K6[17] = decrypt_int ? K[4] : K[55];
assign K6[18] = decrypt_int ? K[17] : K[11];
assign K6[19] = decrypt_int ? K[48] : K[10];
assign K6[20] = decrypt_int ? K[10] : K[4];
assign K6[21] = decrypt_int ? K[11] : K[5];
assign K6[22] = decrypt_int ? K[19] : K[13];
assign K6[23] = decrypt_int ? K[27] : K[46];
assign K6[24] = decrypt_int ? K[32] : K[26];
assign K6[25] = decrypt_int ? K[21] : K[44];
assign K6[26] = decrypt_int ? K[43] : K[35];
assign K6[27] = decrypt_int ? K[37] : K[29];
assign K6[28] = decrypt_int ? K[52] : K[16];
assign K6[29] = decrypt_int ? K[8] : K[0];
assign K6[30] = decrypt_int ? K[9] : K[1];
assign K6[31] = decrypt_int ? K[30] : K[22];
assign K6[32] = decrypt_int ? K[14] : K[37];
assign K6[33] = decrypt_int ? K[36] : K[28];
assign K6[34] = decrypt_int ? K[49] : K[45];
assign K6[35] = decrypt_int ? K[51] : K[43];
assign K6[36] = decrypt_int ? K[15] : K[7];
assign K6[37] = decrypt_int ? K[42] : K[38];
assign K6[38] = decrypt_int ? K[22] : K[14];
assign K6[39] = decrypt_int ? K[7] : K[30];
assign K6[40] = decrypt_int ? K[16] : K[8];
assign K6[41] = decrypt_int ? K[31] : K[50];
assign K6[42] = decrypt_int ? K[50] : K[42];
assign K6[43] = decrypt_int ? K[1] : K[52];
assign K6[44] = decrypt_int ? K[28] : K[51];
assign K6[45] = decrypt_int ? K[29] : K[21];
assign K6[46] = decrypt_int ? K[45] : K[9];
assign K6[47] = decrypt_int ? K[23] : K[15];
assign K6[48] = decrypt_int ? K[44] : K[36];
assign K5[1] = decrypt_int ? K[48] : K[39];
assign K5[2] = decrypt_int ? K[12] : K[3];
assign K5[3] = decrypt_int ? K[27] : K[18];
assign K5[4] = decrypt_int ? K[4] : K[27];
assign K5[5] = decrypt_int ? K[39] : K[5];
assign K5[6] = decrypt_int ? K[10] : K[33];
assign K5[7] = decrypt_int ? K[53] : K[19];
assign K5[8] = decrypt_int ? K[32] : K[55];
assign K5[9] = decrypt_int ? K[55] : K[46];
assign K5[10] = decrypt_int ? K[17] : K[40];
assign K5[11] = decrypt_int ? K[40] : K[6];
assign K5[12] = decrypt_int ? K[20] : K[11];
assign K5[13] = decrypt_int ? K[54] : K[20];
assign K5[14] = decrypt_int ? K[26] : K[17];
assign K5[15] = decrypt_int ? K[34] : K[25];
assign K5[16] = decrypt_int ? K[3] : K[26];
assign K5[17] = decrypt_int ? K[18] : K[41];
assign K5[18] = decrypt_int ? K[6] : K[54];
assign K5[19] = decrypt_int ? K[5] : K[53];
assign K5[20] = decrypt_int ? K[24] : K[47];
assign K5[21] = decrypt_int ? K[25] : K[48];
assign K5[22] = decrypt_int ? K[33] : K[24];
assign K5[23] = decrypt_int ? K[41] : K[32];
assign K5[24] = decrypt_int ? K[46] : K[12];
assign K5[25] = decrypt_int ? K[35] : K[30];
assign K5[26] = decrypt_int ? K[2] : K[21];
assign K5[27] = decrypt_int ? K[51] : K[15];
assign K5[28] = decrypt_int ? K[7] : K[2];
assign K5[29] = decrypt_int ? K[22] : K[45];
assign K5[30] = decrypt_int ? K[23] : K[42];
assign K5[31] = decrypt_int ? K[44] : K[8];
assign K5[32] = decrypt_int ? K[28] : K[23];
assign K5[33] = decrypt_int ? K[50] : K[14];
assign K5[34] = decrypt_int ? K[8] : K[31];
assign K5[35] = decrypt_int ? K[38] : K[29];
assign K5[36] = decrypt_int ? K[29] : K[52];
assign K5[37] = decrypt_int ? K[1] : K[51];
assign K5[38] = decrypt_int ? K[36] : K[0];
assign K5[39] = decrypt_int ? K[21] : K[16];
assign K5[40] = decrypt_int ? K[30] : K[49];
assign K5[41] = decrypt_int ? K[45] : K[36];
assign K5[42] = decrypt_int ? K[9] : K[28];
assign K5[43] = decrypt_int ? K[15] : K[38];
assign K5[44] = decrypt_int ? K[42] : K[37];
assign K5[45] = decrypt_int ? K[43] : K[7];
assign K5[46] = decrypt_int ? K[0] : K[50];
assign K5[47] = decrypt_int ? K[37] : K[1];
assign K5[48] = decrypt_int ? K[31] : K[22];
assign K4[1] = decrypt_int ? K[5] : K[25];
assign K4[2] = decrypt_int ? K[26] : K[46];
assign K4[3] = decrypt_int ? K[41] : K[4];
assign K4[4] = decrypt_int ? K[18] : K[13];
assign K4[5] = decrypt_int ? K[53] : K[48];
assign K4[6] = decrypt_int ? K[24] : K[19];
assign K4[7] = decrypt_int ? K[10] : K[5];
assign K4[8] = decrypt_int ? K[46] : K[41];
assign K4[9] = decrypt_int ? K[12] : K[32];
assign K4[10] = decrypt_int ? K[6] : K[26];
assign K4[11] = decrypt_int ? K[54] : K[17];
assign K4[12] = decrypt_int ? K[34] : K[54];
assign K4[13] = decrypt_int ? K[11] : K[6];
assign K4[14] = decrypt_int ? K[40] : K[3];
assign K4[15] = decrypt_int ? K[48] : K[11];
assign K4[16] = decrypt_int ? K[17] : K[12];
assign K4[17] = decrypt_int ? K[32] : K[27];
assign K4[18] = decrypt_int ? K[20] : K[40];
assign K4[19] = decrypt_int ? K[19] : K[39];
assign K4[20] = decrypt_int ? K[13] : K[33];
assign K4[21] = decrypt_int ? K[39] : K[34];
assign K4[22] = decrypt_int ? K[47] : K[10];
assign K4[23] = decrypt_int ? K[55] : K[18];
assign K4[24] = decrypt_int ? K[3] : K[55];
assign K4[25] = decrypt_int ? K[49] : K[16];
assign K4[26] = decrypt_int ? K[16] : K[7];
assign K4[27] = decrypt_int ? K[38] : K[1];
assign K4[28] = decrypt_int ? K[21] : K[43];
assign K4[29] = decrypt_int ? K[36] : K[31];
assign K4[30] = decrypt_int ? K[37] : K[28];
assign K4[31] = decrypt_int ? K[31] : K[49];
assign K4[32] = decrypt_int ? K[42] : K[9];
assign K4[33] = decrypt_int ? K[9] : K[0];
assign K4[34] = decrypt_int ? K[22] : K[44];
assign K4[35] = decrypt_int ? K[52] : K[15];
assign K4[36] = decrypt_int ? K[43] : K[38];
assign K4[37] = decrypt_int ? K[15] : K[37];
assign K4[38] = decrypt_int ? K[50] : K[45];
assign K4[39] = decrypt_int ? K[35] : K[2];
assign K4[40] = decrypt_int ? K[44] : K[35];
assign K4[41] = decrypt_int ? K[0] : K[22];
assign K4[42] = decrypt_int ? K[23] : K[14];
assign K4[43] = decrypt_int ? K[29] : K[51];
assign K4[44] = decrypt_int ? K[1] : K[23];
assign K4[45] = decrypt_int ? K[2] : K[52];
assign K4[46] = decrypt_int ? K[14] : K[36];
assign K4[47] = decrypt_int ? K[51] : K[42];
assign K4[48] = decrypt_int ? K[45] : K[8];
assign K3[1] = decrypt_int ? K[19] : K[11];
assign K3[2] = decrypt_int ? K[40] : K[32];
assign K3[3] = decrypt_int ? K[55] : K[47];
assign K3[4] = decrypt_int ? K[32] : K[24];
assign K3[5] = decrypt_int ? K[10] : K[34];
assign K3[6] = decrypt_int ? K[13] : K[5];
assign K3[7] = decrypt_int ? K[24] : K[48];
assign K3[8] = decrypt_int ? K[3] : K[27];
assign K3[9] = decrypt_int ? K[26] : K[18];
assign K3[10] = decrypt_int ? K[20] : K[12];
assign K3[11] = decrypt_int ? K[11] : K[3];
assign K3[12] = decrypt_int ? K[48] : K[40];
assign K3[13] = decrypt_int ? K[25] : K[17];
assign K3[14] = decrypt_int ? K[54] : K[46];
assign K3[15] = decrypt_int ? K[5] : K[54];
assign K3[16] = decrypt_int ? K[6] : K[55];
assign K3[17] = decrypt_int ? K[46] : K[13];
assign K3[18] = decrypt_int ? K[34] : K[26];
assign K3[19] = decrypt_int ? K[33] : K[25];
assign K3[20] = decrypt_int ? K[27] : K[19];
assign K3[21] = decrypt_int ? K[53] : K[20];
assign K3[22] = decrypt_int ? K[4] : K[53];
assign K3[23] = decrypt_int ? K[12] : K[4];
assign K3[24] = decrypt_int ? K[17] : K[41];
assign K3[25] = decrypt_int ? K[8] : K[2];
assign K3[26] = decrypt_int ? K[30] : K[52];
assign K3[27] = decrypt_int ? K[52] : K[42];
assign K3[28] = decrypt_int ? K[35] : K[29];
assign K3[29] = decrypt_int ? K[50] : K[44];
assign K3[30] = decrypt_int ? K[51] : K[14];
assign K3[31] = decrypt_int ? K[45] : K[35];
assign K3[32] = decrypt_int ? K[1] : K[50];
assign K3[33] = decrypt_int ? K[23] : K[45];
assign K3[34] = decrypt_int ? K[36] : K[30];
assign K3[35] = decrypt_int ? K[7] : K[1];
assign K3[36] = decrypt_int ? K[2] : K[51];
assign K3[37] = decrypt_int ? K[29] : K[23];
assign K3[38] = decrypt_int ? K[9] : K[31];
assign K3[39] = decrypt_int ? K[49] : K[43];
assign K3[40] = decrypt_int ? K[31] : K[21];
assign K3[41] = decrypt_int ? K[14] : K[8];
assign K3[42] = decrypt_int ? K[37] : K[0];
assign K3[43] = decrypt_int ? K[43] : K[37];
assign K3[44] = decrypt_int ? K[15] : K[9];
assign K3[45] = decrypt_int ? K[16] : K[38];
assign K3[46] = decrypt_int ? K[28] : K[22];
assign K3[47] = decrypt_int ? K[38] : K[28];
assign K3[48] = decrypt_int ? K[0] : K[49];
assign K2[1] = decrypt_int ? K[33] : K[54];
assign K2[2] = decrypt_int ? K[54] : K[18];
assign K2[3] = decrypt_int ? K[12] : K[33];
assign K2[4] = decrypt_int ? K[46] : K[10];
assign K2[5] = decrypt_int ? K[24] : K[20];
assign K2[6] = decrypt_int ? K[27] : K[48];
assign K2[7] = decrypt_int ? K[13] : K[34];
assign K2[8] = decrypt_int ? K[17] : K[13];
assign K2[9] = decrypt_int ? K[40] : K[4];
assign K2[10] = decrypt_int ? K[34] : K[55];
assign K2[11] = decrypt_int ? K[25] : K[46];
assign K2[12] = decrypt_int ? K[5] : K[26];
assign K2[13] = decrypt_int ? K[39] : K[3];
assign K2[14] = decrypt_int ? K[11] : K[32];
assign K2[15] = decrypt_int ? K[19] : K[40];
assign K2[16] = decrypt_int ? K[20] : K[41];
assign K2[17] = decrypt_int ? K[3] : K[24];
assign K2[18] = decrypt_int ? K[48] : K[12];
assign K2[19] = decrypt_int ? K[47] : K[11];
assign K2[20] = decrypt_int ? K[41] : K[5];
assign K2[21] = decrypt_int ? K[10] : K[6];
assign K2[22] = decrypt_int ? K[18] : K[39];
assign K2[23] = decrypt_int ? K[26] : K[47];
assign K2[24] = decrypt_int ? K[6] : K[27];
assign K2[25] = decrypt_int ? K[22] : K[43];
assign K2[26] = decrypt_int ? K[44] : K[38];
assign K2[27] = decrypt_int ? K[7] : K[28];
assign K2[28] = decrypt_int ? K[49] : K[15];
assign K2[29] = decrypt_int ? K[9] : K[30];
assign K2[30] = decrypt_int ? K[38] : K[0];
assign K2[31] = decrypt_int ? K[0] : K[21];
assign K2[32] = decrypt_int ? K[15] : K[36];
assign K2[33] = decrypt_int ? K[37] : K[31];
assign K2[34] = decrypt_int ? K[50] : K[16];
assign K2[35] = decrypt_int ? K[21] : K[42];
assign K2[36] = decrypt_int ? K[16] : K[37];
assign K2[37] = decrypt_int ? K[43] : K[9];
assign K2[38] = decrypt_int ? K[23] : K[44];
assign K2[39] = decrypt_int ? K[8] : K[29];
assign K2[40] = decrypt_int ? K[45] : K[7];
assign K2[41] = decrypt_int ? K[28] : K[49];
assign K2[42] = decrypt_int ? K[51] : K[45];
assign K2[43] = decrypt_int ? K[2] : K[23];
assign K2[44] = decrypt_int ? K[29] : K[50];
assign K2[45] = decrypt_int ? K[30] : K[51];
assign K2[46] = decrypt_int ? K[42] : K[8];
assign K2[47] = decrypt_int ? K[52] : K[14];
assign K2[48] = decrypt_int ? K[14] : K[35];
assign K1[1] = decrypt_int ? K[40] : K[47];
assign K1[2] = decrypt_int ? K[4] : K[11];
assign K1[3] = decrypt_int ? K[19] : K[26];
assign K1[4] = decrypt_int ? K[53] : K[3];
assign K1[5] = decrypt_int ? K[6] : K[13];
assign K1[6] = decrypt_int ? K[34] : K[41];
assign K1[7] = decrypt_int ? K[20] : K[27];
assign K1[8] = decrypt_int ? K[24] : K[6];
assign K1[9] = decrypt_int ? K[47] : K[54];
assign K1[10] = decrypt_int ? K[41] : K[48];
assign K1[11] = decrypt_int ? K[32] : K[39];
assign K1[12] = decrypt_int ? K[12] : K[19];
assign K1[13] = decrypt_int ? K[46] : K[53];
assign K1[14] = decrypt_int ? K[18] : K[25];
assign K1[15] = decrypt_int ? K[26] : K[33];
assign K1[16] = decrypt_int ? K[27] : K[34];
assign K1[17] = decrypt_int ? K[10] : K[17];
assign K1[18] = decrypt_int ? K[55] : K[5];
assign K1[19] = decrypt_int ? K[54] : K[4];
assign K1[20] = decrypt_int ? K[48] : K[55];
assign K1[21] = decrypt_int ? K[17] : K[24];
assign K1[22] = decrypt_int ? K[25] : K[32];
assign K1[23] = decrypt_int ? K[33] : K[40];
assign K1[24] = decrypt_int ? K[13] : K[20];
assign K1[25] = decrypt_int ? K[29] : K[36];
assign K1[26] = decrypt_int ? K[51] : K[31];
assign K1[27] = decrypt_int ? K[14] : K[21];
assign K1[28] = decrypt_int ? K[1] : K[8];
assign K1[29] = decrypt_int ? K[16] : K[23];
assign K1[30] = decrypt_int ? K[45] : K[52];
assign K1[31] = decrypt_int ? K[7] : K[14];
assign K1[32] = decrypt_int ? K[22] : K[29];
assign K1[33] = decrypt_int ? K[44] : K[51];
assign K1[34] = decrypt_int ? K[2] : K[9];
assign K1[35] = decrypt_int ? K[28] : K[35];
assign K1[36] = decrypt_int ? K[23] : K[30];
assign K1[37] = decrypt_int ? K[50] : K[2];
assign K1[38] = decrypt_int ? K[30] : K[37];
assign K1[39] = decrypt_int ? K[15] : K[22];
assign K1[40] = decrypt_int ? K[52] : K[0];
assign K1[41] = decrypt_int ? K[35] : K[42];
assign K1[42] = decrypt_int ? K[31] : K[38];
assign K1[43] = decrypt_int ? K[9] : K[16];
assign K1[44] = decrypt_int ? K[36] : K[43];
assign K1[45] = decrypt_int ? K[37] : K[44];
assign K1[46] = decrypt_int ? K[49] : K[1];
assign K1[47] = decrypt_int ? K[0] : K[7];
assign K1[48] = decrypt_int ? K[21] : K[28];
endmodule
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