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shailja
/
fine-tuned-codegen-6B-Verilog
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0
Text Generation
Transformers
PyTorch
shailja/Verilog_GitHub
codegen
code
Eval Results
Inference Endpoints
arxiv:
2212.11140
License:
bigcode-openrail-m
Model card
Files
Files and versions
Community
1
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main
fine-tuned-codegen-6B-Verilog
/
config.json
Commit History
Upload CodeGenForCausalLM
bd9ca6b
shailja
commited on
Sep 18, 2022
shailja
commited on
