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shailja
/
fine-tuned-codegen-6B-Verilog
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Text Generation
Transformers
PyTorch
shailja/Verilog_GitHub
codegen
code
Eval Results
Inference Endpoints
arxiv:
2212.11140
License:
bigcode-openrail-m
Model card
Files
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22eb0de
fine-tuned-codegen-6B-Verilog
Commit History
Upload fine-tuned-codegen-6B-1gpu.tar.zst
22eb0de
shailja
commited on
Nov 24, 2022
Upload fine-tuned-codegen-6B-1gpu.tar.zst
d4eb8af
shailja
commited on
Nov 16, 2022
Upload 3 files
a0106f3
shailja
commited on
Nov 7, 2022
Upload CodeGenForCausalLM
bd9ca6b
shailja
commited on
Sep 18, 2022
initial commit
16cca11
shailja
commited on
Sep 18, 2022
shailja
commited on
