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shailja
/
fine-tuned-codegen-16B-Verilog
like
10
Text Generation
Transformers
PyTorch
shailja/Verilog_GitHub
codegen
code
Eval Results
Inference Endpoints
arxiv:
2212.11140
License:
bigcode-openrail-m
Model card
Files
Files and versions
Community
3
Train
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Use this model
refs/pr/3
fine-tuned-codegen-16B-Verilog
Commit History
Adding `safetensors` variant of this model
3fdf085
verified
SFconvertbot
commited on
Apr 12
Update README.md
ea3cbb6
shailja
commited on
Aug 30, 2023
Update README.md
2196758
shailja
commited on
Aug 30, 2023
uploaded model
3bf4866
shailja-thakur
commited on
Dec 30, 2022
uploading 16B Verilog LLM
af0f1d3
shailja-thakur
commited on
Dec 30, 2022
initial commit
c3b0acc
shailja
commited on
Dec 30, 2022