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|---|
entity func19 is
end entity;
architecture test of func19 is
function maybe_not_return (x : integer) return integer is
begin
if x > 0 then
return x * 2;
end if;
end function;
signal x, y : integer := 0;
begin
p1: y <= maybe_not_return(x);
p2: process is
begin
x <= 55;
wait for 1 ns;
assert y = 110;
x <= -1;
wait for 1 ns;
assert false report "should not reach here: " & integer'image(y);
wait;
end process;
end architecture;
|
entity tb_fsm_5s is
end tb_fsm_5s;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_fsm_5s is
signal clk : std_logic;
signal rst : std_logic;
signal din : std_logic;
signal done : std_logic;
begin
dut: entity work.fsm_5s
port map (
done => done,
d => din,
clk => clk,
rst => rst);
process
constant dat : std_logic_vector := b"10010_10010_11000";
constant res : std_logic_vector := b"00001_00001_00000";
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
rst <= '1';
din <= '0';
pulse;
assert done = '0' severity failure;
-- Test the whole sequence.
rst <= '0';
for i in dat'range loop
din <= dat (i);
pulse;
assert done = res(i) severity failure;
end loop;
wait;
end process;
end behav;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COMB_RLE_CONCAT is
port(
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
INPUT_2 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
end COMB_RLE_CONCAT;
architecture rtl of COMB_RLE_CONCAT is
begin
process(INPUT_1, INPUT_2)
VARIABLE iValue : UNSIGNED(7 downto 0);
VARIABLE iCount : UNSIGNED(7 downto 0);
begin
iValue := SIGNED (INPUT_1( 11 downto 0));
iCount := UNSIGNED(INPUT_1( 3 downto 0));
iValue := iValue - TO_SIGNED(2048, 12);
OUTPUT_1 <= "0000000000000000" & STD_LOGIC_VECTOR( iCount ) & STD_LOGIC_VECTOR( iValue );
end process;
end rtl;
|
-------------------------------------------------------------------------------
-- Title : UART
-- Project : UART
-------------------------------------------------------------------------------
-- File : utils.vhd
-- Author : Philippe CARTON
-- (philippe.carton2@libertysurf.fr)
-- Organization:
-- Created : 15/12/2001
-- Last update : 8/1/2003
-- Platform : Foundation 3.1i
-- Simulators : ModelSim 5.5b
-- Synthesizers: Xilinx Synthesis
-- Targets : Xilinx Spartan
-- Dependency : IEEE std_logic_1164
-------------------------------------------------------------------------------
-- Description: VHDL utility file
-------------------------------------------------------------------------------
-- Copyright (c) notice
-- This core adheres to the GNU public license
--
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number :
-- Version :
-- Date :
-- Modifier : name <email>
-- Description :
--
------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Revision list
-- Version Author Date Changes
--
-- 1.0 Philippe CARTON 19 December 2001 New model
-- philippe.carton2@libertysurf.fr
-------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Synchroniser:
-- Synchronize an input signal (C1) with an input clock (C).
-- The result is the O signal which is synchronous of C, and persist for
-- one C clock period.
--------------------------------------------------------------------------------
library IEEE,STD;
use IEEE.std_logic_1164.all;
entity synchroniser is
port (
C1 : in std_logic;-- Asynchronous signal
C : in std_logic;-- Clock
O : out std_logic);-- Synchronised signal
end synchroniser;
architecture Behaviour of synchroniser is
signal C1A : std_logic;
signal C1S : std_logic;
signal R : std_logic;
begin
RiseC1A : process(C1,R)
begin
if Rising_Edge(C1) then
C1A <= '1';
end if;
if (R = '1') then
C1A <= '0';
end if;
end process;
SyncP : process(C,R)
begin
if Rising_Edge(C) then
if (C1A = '1') then
C1S <= '1';
else C1S <= '0';
end if;
if (C1S = '1') then
R <= '1';
else R <= '0';
end if;
end if;
if (R = '1') then
C1S <= '0';
end if;
end process;
O <= C1S;
end Behaviour;
-------------------------------------------------------------------------------
-- Counter
-- This counter is a parametrizable clock divider.
-- The count value is the generic parameter Count.
-- It is CE enabled. (it will count only if CE is high).
-- When it overflow, it will emit a pulse on O.
-- It can be reseted to 0.
-------------------------------------------------------------------------------
library IEEE,STD;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Counter is
port (
Clk : in std_logic; -- Clock
Reset : in std_logic; -- Reset input
CE : in std_logic; -- Chip Enable
Count : in std_logic_vector (15 downto 0); -- Count revolution
O : out std_logic); -- Output
end Counter;
architecture Behaviour of Counter is
begin
counter : process(Clk,Reset,Count)
variable Cnt : unsigned (15 downto 0);
begin
if Reset = '1' then
Cnt := unsigned(Count);
O <= '0';
elsif Rising_Edge(Clk) then
if CE = '1' then
if Cnt = 1 then
O <= '1';
Cnt := unsigned(Count);
else
O <= '0';
Cnt := Cnt - 1;
end if;
else O <= '0';
end if;
end if;
end process;
end Behaviour;
|
--- Pipeline a function, using synthesis register retiming feature.
entity function_pipeline is
generic (
type datai_t;
type datao_t;
function fun(datai : datai_t) return datao_t;
constant stages_c : natural);
port (
signal clk_i : in bit;
signal datai_i : in datai_t;
signal datao_o : out datao_t);
-- These assertions crash Questa 10.5c. Too fancy together with VHDL-2008?
--OFFpsl default clock is rising_edge(clk_i);
--OFFpsl assert next[stages_c] (always datao_o = fun(prev(datai_i, stages_c)));
end;
architecture output_pipeline of function_pipeline is
type pipeline_t is array(stages_c-1 downto 0) of datao_t;
signal pl : pipeline_t;
begin
gen_pipeline : if stages_c > 0 generate
process(clk_i)
begin
if rising_edge(clk_i) then
pl <= pl(pl'left-1 downto 0) & fun(datai_i);
end if;
end process;
datao_o <= pl(pl'left);
else generate
datao_o <= fun(datai_i);
end generate;
end;
architecture input_pipeline of function_pipeline is
type pipeline_t is array(stages_c-2 downto 0) of datai_t;
signal pl : pipeline_t;
begin
gen_pipeline : if stages_c > 0 generate
process(clk_i)
begin
if rising_edge(clk_i) then
if stages_c > 1 then
pl <= pl(pl'left-1 downto 0) & datai_i;
datao_o <= fun(pl(pl'left));
else
datao_o <= fun(datai_i);
end if;
end if;
end process;
else generate
datao_o <= fun(datai_i);
end generate;
end;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_700 is
port (
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0);
eq : out std_logic
);
end cmp_700;
architecture augh of cmp_700 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_700 is
port (
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0);
eq : out std_logic
);
end cmp_700;
architecture augh of cmp_700 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_700 is
port (
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0);
eq : out std_logic
);
end cmp_700;
architecture augh of cmp_700 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
|
-- megafunction wizard: %LPM_COMPARE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COMPARE
-- ============================================================
-- File Name: lpm_compare1.vhd
-- Megafunction Name(s):
-- LPM_COMPARE
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_compare1 IS
PORT
(
dataa : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
ageb : OUT STD_LOGIC
);
END lpm_compare1;
ARCHITECTURE SYN OF lpm_compare1 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1_bv : BIT_VECTOR (9 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (9 DOWNTO 0);
COMPONENT lpm_compare
GENERIC (
lpm_hint : STRING;
lpm_representation : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
ageb : OUT STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (9 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire1_bv(9 DOWNTO 0) <= "0000101011";
sub_wire1 <= To_stdlogicvector(sub_wire1_bv);
ageb <= sub_wire0;
LPM_COMPARE_component : LPM_COMPARE
GENERIC MAP (
lpm_hint => "ONE_INPUT_IS_CONSTANT=YES",
lpm_representation => "UNSIGNED",
lpm_type => "LPM_COMPARE",
lpm_width => 10
)
PORT MAP (
dataa => dataa,
datab => sub_wire1,
ageb => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AeqB NUMERIC "0"
-- Retrieval info: PRIVATE: AgeB NUMERIC "1"
-- Retrieval info: PRIVATE: AgtB NUMERIC "0"
-- Retrieval info: PRIVATE: AleB NUMERIC "0"
-- Retrieval info: PRIVATE: AltB NUMERIC "0"
-- Retrieval info: PRIVATE: AneB NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: PortBValue NUMERIC "43"
-- Retrieval info: PRIVATE: Radix NUMERIC "10"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SignedCompare NUMERIC "0"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: isPortBConstant NUMERIC "1"
-- Retrieval info: PRIVATE: nBit NUMERIC "10"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=YES"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "10"
-- Retrieval info: USED_PORT: ageb 0 0 0 0 OUTPUT NODEFVAL "ageb"
-- Retrieval info: USED_PORT: dataa 0 0 10 0 INPUT NODEFVAL "dataa[9..0]"
-- Retrieval info: CONNECT: @dataa 0 0 10 0 dataa 0 0 10 0
-- Retrieval info: CONNECT: @datab 0 0 10 0 43 0 0 10 0
-- Retrieval info: CONNECT: ageb 0 0 0 0 @ageb 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
-- megafunction wizard: %LPM_COMPARE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COMPARE
-- ============================================================
-- File Name: lpm_compare1.vhd
-- Megafunction Name(s):
-- LPM_COMPARE
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_compare1 IS
PORT
(
dataa : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
ageb : OUT STD_LOGIC
);
END lpm_compare1;
ARCHITECTURE SYN OF lpm_compare1 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1_bv : BIT_VECTOR (9 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (9 DOWNTO 0);
COMPONENT lpm_compare
GENERIC (
lpm_hint : STRING;
lpm_representation : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
ageb : OUT STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (9 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire1_bv(9 DOWNTO 0) <= "0000101011";
sub_wire1 <= To_stdlogicvector(sub_wire1_bv);
ageb <= sub_wire0;
LPM_COMPARE_component : LPM_COMPARE
GENERIC MAP (
lpm_hint => "ONE_INPUT_IS_CONSTANT=YES",
lpm_representation => "UNSIGNED",
lpm_type => "LPM_COMPARE",
lpm_width => 10
)
PORT MAP (
dataa => dataa,
datab => sub_wire1,
ageb => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AeqB NUMERIC "0"
-- Retrieval info: PRIVATE: AgeB NUMERIC "1"
-- Retrieval info: PRIVATE: AgtB NUMERIC "0"
-- Retrieval info: PRIVATE: AleB NUMERIC "0"
-- Retrieval info: PRIVATE: AltB NUMERIC "0"
-- Retrieval info: PRIVATE: AneB NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: PortBValue NUMERIC "43"
-- Retrieval info: PRIVATE: Radix NUMERIC "10"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SignedCompare NUMERIC "0"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: isPortBConstant NUMERIC "1"
-- Retrieval info: PRIVATE: nBit NUMERIC "10"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=YES"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "10"
-- Retrieval info: USED_PORT: ageb 0 0 0 0 OUTPUT NODEFVAL "ageb"
-- Retrieval info: USED_PORT: dataa 0 0 10 0 INPUT NODEFVAL "dataa[9..0]"
-- Retrieval info: CONNECT: @dataa 0 0 10 0 dataa 0 0 10 0
-- Retrieval info: CONNECT: @datab 0 0 10 0 43 0 0 10 0
-- Retrieval info: CONNECT: ageb 0 0 0 0 @ageb 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- axi_qspi_xip_if.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_qspi_xip_if.vhd
-- Version: v3.0
-- Description: This is the top-level design file for the AXI Quad SPI core
-- in XIP mode.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_arith.all;
-- use ieee.std_logic_signed.all;
use ieee.std_logic_misc.all;
-- library unsigned is used for overloading of "=" which allows integer to
-- be compared to std_logic_vector
use ieee.std_logic_unsigned.all;
library axi_lite_ipif_v3_0_4;
use axi_lite_ipif_v3_0_4.axi_lite_ipif;
use axi_lite_ipif_v3_0_4.ipif_pkg.all;
library lib_fifo_v1_0_5;
use lib_fifo_v1_0_5.async_fifo_fg;
library lib_cdc_v1_0_2;
use lib_cdc_v1_0_2.cdc_sync;
library axi_quad_spi_v3_2_8;
use axi_quad_spi_v3_2_8.all;
library unisim;
use unisim.vcomponents.FDRE;
use unisim.vcomponents.FD;
use unisim.vcomponents.FDR;
-------------------------------------------------------------------------------
entity axi_qspi_xip_if is
generic(
-- General Parameters
C_FAMILY : string := "virtex7";
Async_Clk : integer := 0;
C_SUB_FAMILY : string := "virtex7";
-------------------------
C_SPI_MEM_ADDR_BITS : integer ; -- default is 24 bit, options are 24 or 32 bits
-------------------------
-- C_AXI4_CLK_PS : integer := 10000;--AXI clock period
-- C_EXT_SPI_CLK_PS : integer := 10000;--ext clock period
C_XIP_FIFO_DEPTH : integer := 64;-- Fixed value for XIP mode.
C_SCK_RATIO : integer := 16;--default in legacy mode
C_NUM_SS_BITS : integer range 1 to 32:= 1;
C_NUM_TRANSFER_BITS : integer := 8; -- Fixed 8 bit for XIP mode
-------------------------
C_SPI_MODE : integer range 0 to 2 := 0; -- used for differentiating
-- Standard, Dual or Quad mode
-- in Ports as well as internal
-- functionality
C_USE_STARTUP : integer range 0 to 1 := 1; --
C_SPI_MEMORY : integer range 0 to 3 := 1; -- 0 - mixed mode,
-- 1 - winbond,
-- 2 - numonyx
-- 3 - spansion
-- used to differentiate
-- internal look up table
-- for commands.
-------------------------
-- AXI4 Lite Interface Parameters
--*C_S_AXI_ADDR_WIDTH : integer range 32 to 32 := 32;
C_S_AXI_ADDR_WIDTH : integer range 7 to 7 := 7;
C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
-------------------------
--*C_BASEADDR : std_logic_vector := x"FFFFFFFF";
--*C_HIGHADDR : std_logic_vector := x"00000000";
-------------------------
-- AXI4 Full Interface Parameters
--*C_S_AXI4_ADDR_WIDTH : integer range 32 to 32 := 32;
C_S_AXI4_ADDR_WIDTH : integer ;-- range 32 to 32 := 32;
C_S_AXI4_DATA_WIDTH : integer range 32 to 32 := 32;
C_S_AXI4_ID_WIDTH : integer range 1 to 16 := 4;
-------------------------
--*C_AXI4_BASEADDR : std_logic_vector := x"FFFFFFFF";
--*C_AXI4_HIGHADDR : std_logic_vector := x"00000000";
-------------------------
C_XIP_FULL_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_0100_0000", -- IP user0 base address
X"0000_0000_01FF_FFFF" -- IP user0 high address
);
C_XIP_FULL_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
2,
1 -- User0 CE Number
)
);
port(
-- external async clock for SPI interface logic
EXT_SPI_CLK : in std_logic;
S_AXI4_ACLK : in std_logic;
Rst_to_spi : in std_logic;
S_AXI4_ARESET : in std_logic;
-------------------------------
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
------------------------------------
-- AXI Write Address Channel Signals
------------------------------------
S_AXI4_AWID : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_AWADDR : in std_logic_vector((C_SPI_MEM_ADDR_BITS-1) downto 0);
S_AXI4_AWLEN : in std_logic_vector(7 downto 0);
S_AXI4_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI4_AWBURST : in std_logic_vector(1 downto 0);
S_AXI4_AWLOCK : in std_logic; -- not supported in design
S_AXI4_AWCACHE : in std_logic_vector(3 downto 0);-- not supported in design
S_AXI4_AWPROT : in std_logic_vector(2 downto 0);-- not supported in design
S_AXI4_AWVALID : in std_logic;
S_AXI4_AWREADY : out std_logic;
---------------------------------------
-- AXI4 Full Write Data Channel Signals
---------------------------------------
S_AXI4_WDATA : in std_logic_vector((C_S_AXI4_DATA_WIDTH-1)downto 0);
S_AXI4_WSTRB : in std_logic_vector(((C_S_AXI4_DATA_WIDTH/8)-1) downto 0);
S_AXI4_WLAST : in std_logic;
S_AXI4_WVALID : in std_logic;
S_AXI4_WREADY : out std_logic;
-------------------------------------------
-- AXI4 Full Write Response Channel Signals
-------------------------------------------
S_AXI4_BID : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_BRESP : out std_logic_vector(1 downto 0);
S_AXI4_BVALID : out std_logic;
S_AXI4_BREADY : in std_logic;
-----------------------------------
-- AXI Read Address Channel Signals
-----------------------------------
S_AXI4_ARID : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_ARADDR : in std_logic_vector((C_SPI_MEM_ADDR_BITS-1) downto 0);
S_AXI4_ARLEN : in std_logic_vector(7 downto 0);
S_AXI4_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI4_ARBURST : in std_logic_vector(1 downto 0);
S_AXI4_ARLOCK : in std_logic; -- not supported in design
S_AXI4_ARCACHE : in std_logic_vector(3 downto 0);-- not supported in design
S_AXI4_ARPROT : in std_logic_vector(2 downto 0);-- not supported in design
S_AXI4_ARVALID : in std_logic;
S_AXI4_ARREADY : out std_logic;
--------------------------------
-- AXI Read Data Channel Signals
--------------------------------
S_AXI4_RID : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_RDATA : out std_logic_vector((C_S_AXI4_DATA_WIDTH-1) downto 0);
S_AXI4_RRESP : out std_logic_vector(1 downto 0);
S_AXI4_RLAST : out std_logic;
S_AXI4_RVALID : out std_logic;
S_AXI4_RREADY : in std_logic;
--------------------------------
XIPSR_CPHA_CPOL_ERR : in std_logic;
TO_XIPSR_trans_error : out std_logic;
--------------------------------
TO_XIPSR_mst_modf_err : out std_logic;
TO_XIPSR_axi_rx_full : out std_logic;
TO_XIPSR_axi_rx_empty : out std_logic;
XIPCR_1_CPOL : in std_logic;
XIPCR_0_CPHA : in std_logic;
-------------------------------
--*SPI port interface * --
-------------------------------
IO0_I : in std_logic; -- MOSI signal in standard SPI
IO0_O : out std_logic;
IO0_T : out std_logic;
-------------------------------
IO1_I : in std_logic; -- MISO signal in standard SPI
IO1_O : out std_logic;
IO1_T : out std_logic;
-----------------
-- quad mode pins
-----------------
IO2_I : in std_logic;
IO2_O : out std_logic;
IO2_T : out std_logic;
---------------
IO3_I : in std_logic;
IO3_O : out std_logic;
IO3_T : out std_logic;
---------------------------------
-- common pins
----------------
SPISEL : in std_logic;
-----
SCK_I : in std_logic;
SCK_O_reg : out std_logic;
SCK_T : out std_logic;
-----
SS_I : in std_logic_vector((C_NUM_SS_BITS-1) downto 0);
SS_O : out std_logic_vector((C_NUM_SS_BITS-1) downto 0);
SS_T : out std_logic
---------------------------------
);
end entity axi_qspi_xip_if;
--------------------------------------------------------------------------------
architecture imp of axi_qspi_xip_if is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
constant NEW_LOGIC : integer := 0; -- 3/29/2013
constant ACTIVE_LOW_RESET : std_logic := '0';
constant CMD_BITS_LENGTH : integer:= 8; -- 3/29/2013
-----
-- code coverage -- function assign_addr_bits (logic_info : integer) return integer is
-- code coverage -- variable addr_width_24 : integer:= 24;
-- code coverage -- variable addr_width_32 : integer:= 32;
-- code coverage -- begin
-- code coverage -- if logic_info = 0 then -- old logic for 24 bit addressing
-- code coverage -- return addr_width_24;
-- code coverage -- else
-- code coverage -- return addr_width_32;
-- code coverage -- end if;
-- code coverage -- end function assign_addr_bits;
signal nm_wr_en_CMD : std_logic_vector(7 downto 0);
signal nm_4byte_addr_en_CMD : std_logic_vector(7 downto 0);
type NM_WR_EN_STATE_TYPE is
(NM_WR_EN_IDLE, -- decode command can be combined here later
NM_WR_EN,
NM_WR_EN_DONE
);
signal nm_wr_en_cntrl_ps : NM_WR_EN_STATE_TYPE;
signal nm_wr_en_cntrl_ns : NM_WR_EN_STATE_TYPE;
signal wr_en_under_process : std_logic;
signal wr_en_under_process_d1 : std_logic;
signal load_wr_en, wr_en_done_reg : std_logic;
signal wr_en_done_d1, wr_en_done_d2 : std_logic;
signal wr_en_done : std_logic;
signal data_loaded, cmd_sent : std_logic;
type NM_32_BIT_WR_EN_STATE_TYPE is
(NM_32_BIT_IDLE, -- decode command can be combined here later
NM_32_BIT_EN,
NM_32_BIT_EN_DONE
);
signal nm_sm_4_byte_addr_ps : NM_32_BIT_WR_EN_STATE_TYPE;
signal nm_sm_4_byte_addr_ns : NM_32_BIT_WR_EN_STATE_TYPE;
signal four_byte_en_under_process : std_logic;
signal four_byte_addr_under_process_d1 : std_logic;
signal load_4_byte_addr_en, four_byte_en_done, four_byte_en_done_reg : std_logic;
-----
-- constant declaration
constant FAST_READ : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0):="00001011"; -- 0B
constant FAST_READ_DUAL_IO : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0):="00111011"; -- 3B
constant FAST_READ_QUAD_IO : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0):="10111011"; -- BB
constant C_RD_COUNT_WIDTH_INT : integer := clog2(C_XIP_FIFO_DEPTH);
constant C_WR_COUNT_WIDTH_INT : integer := clog2(C_XIP_FIFO_DEPTH);
constant RX_FIFO_CNTR_WIDTH : integer := clog2(C_XIP_FIFO_DEPTH);
constant XIP_MIN_SIZE : std_logic_vector(31 downto 0):= X"00ffffff";-- 24 bit address
--constant XIP_ADDR_BITS : integer := 24;
constant XIP_ADDR_BITS : integer := C_SPI_MEM_ADDR_BITS; -- assign_addr_bits(NEW_LOGIC);
constant RESET_ACTIVE : std_logic := '1';
constant COUNT_WIDTH : INTEGER := log2(C_NUM_TRANSFER_BITS)+1;
constant ACTIVE_HIGH_RESET : std_logic := '1';
constant ZERO_RX_FIFO_CNT : std_logic_vector(RX_FIFO_CNTR_WIDTH-1 downto 0) := (others => '0');
signal rx_fifo_count: std_logic_vector(RX_FIFO_CNTR_WIDTH-1 downto 0);
constant ALL_1 : std_logic_vector(0 to RX_FIFO_CNTR_WIDTH-1)
:= (others => '0');
signal updown_cnt_en_rx,down_cnt_en_rx : std_logic;
type AXI_IF_STATE_TYPE is
(
IDLE, -- decode command can be combined here later
RD_BURST
);
signal xip_sm_ps: AXI_IF_STATE_TYPE;
signal xip_sm_ns: AXI_IF_STATE_TYPE;
type STATE_TYPE is
(IDLE, -- decode command can be combined here later
CMD_SEND,
HPM_DUMMY,
ADDR_SEND,
TEMP_ADDR_SEND,
--DUMMY_SEND,
DATA_SEND,
TEMP_DATA_SEND,
DATA_RECEIVE,
TEMP_DATA_RECEIVE
);
signal qspi_cntrl_ns : STATE_TYPE;
signal qspi_cntrl_ps : STATE_TYPE;
type WB_STATE_TYPE is
(WB_IDLE, -- decode command can be combined here later
WB_WR_HPM,
WB_DONE
);
signal wb_cntrl_ns : WB_STATE_TYPE;
signal wb_cntrl_ps : WB_STATE_TYPE;
signal valid_decode : std_logic;
signal s_axi_arready_cmb : std_logic;
signal temp_i : std_logic;
signal SS_frm_axi : std_logic_vector(C_NUM_SS_BITS-1 downto 0);
signal SS_frm_axi_int : std_logic_vector(C_NUM_SS_BITS-1 downto 0);
signal SS_frm_axi_reg : std_logic_vector(C_NUM_SS_BITS-1 downto 0);
signal type_of_burst : std_logic; --_vector(1 downto 0);
signal axi_length : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);
signal size_length : std_logic_vector(1 downto 0);
signal S_AXI4_RID_reg : std_logic_vector(C_S_AXI4_ID_WIDTH-1 downto 0);
signal XIP_ADDR : std_logic_vector(XIP_ADDR_BITS-1 downto 0);
signal one_byte_transfer : std_logic;
signal two_byte_transfer : std_logic;
signal four_byte_transfer: std_logic;
signal dtr_length : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);
signal write_length : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);
signal s_axi_rvalid_i : std_logic;
signal dtr_cntr_empty : std_logic;
signal last_bt_one_data_cmb : std_logic;
signal last_data_cmb : std_logic;
signal last_data_acked : std_logic;
signal last_data : std_logic;
signal rd_error_int : std_logic;
signal Data_From_Rx_FIFO : std_logic_vector(C_S_AXI4_DATA_WIDTH-1 downto 0);
signal S_AXI4_RRESP_i : std_logic_vector(1 downto 0);
signal S_AXI4_RDATA_i : std_logic_vector(C_S_AXI4_DATA_WIDTH-1 downto 0);
-- signal s_axi_rvalid_i : std_logic;
signal s_axi_rvalid_cmb : std_logic;
signal xip_pr_state_idle : std_logic;
signal pr_state_idle : std_logic;
signal rready_i : std_logic;
signal wrap_around_to_axi_clk : std_logic;
signal spiXfer_done_to_axi_1 : std_logic;
signal Rx_FIFO_Empty : std_logic;
signal IO0_T_cntrl_axi : std_logic;
signal IO1_T_cntrl_axi : std_logic;
signal IO2_T_cntrl_axi : std_logic;
signal IO3_T_cntrl_axi : std_logic;
signal SCK_T_cntrl_axi : std_logic;
signal load_axi_data_frm_axi : std_logic;
--signal Transmit_addr_int : std_logic_vector(23 downto 0); -- 3/30/2013
signal Transmit_addr_int : std_logic_vector(XIP_ADDR_BITS-1 downto 0); -- 3/30/2013
signal Rx_FIFO_rd_ack : std_logic;
signal Data_To_Rx_FIFO : std_logic_vector(C_S_AXI4_DATA_WIDTH-1 downto 0);
signal store_date_in_drr_fifo : std_logic;
--signal Rx_FIFO_Empty : std_logic;
signal Rx_FIFO_almost_Full : std_logic;
signal Rx_FIFO_almost_Empty : std_logic;
--signal pr_state_idle : std_logic;
signal spiXfer_done_frm_spi_clk: std_logic;
signal mst_modf_err_frm_spi_clk: std_logic;
signal wrap_around_frm_spi_clk : std_logic;
signal one_byte_xfer_frm_axi_clk : std_logic;
signal two_byte_xfer_frm_axi_clk : std_logic;
signal four_byte_xfer_frm_axi_clk : std_logic;
signal load_axi_data_frm_axi_clk : std_logic;
--signal Transmit_Addr_frm_axi_clk : std_logic_vector(23 downto 0); -- 3/30/2013
signal Transmit_Addr_frm_axi_clk : std_logic_vector(XIP_ADDR_BITS-1 downto 0);-- 3/30/2013
signal CPOL_frm_axi_clk : std_logic;
signal CPHA_frm_axi_clk : std_logic;
signal SS_frm_axi_clk : std_logic_vector(C_NUM_SS_BITS-1 downto 0);
signal type_of_burst_frm_axi_clk : std_logic; -- _vector(1 downto 0);
signal type_of_burst_frm_axi : std_logic; -- _vector(1 downto 0);
signal axi_length_frm_axi_clk : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);
signal dtr_length_frm_axi_clk : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);
signal load_axi_data_to_spi_clk : std_logic;
--signal Transmit_Addr_to_spi_clk : std_logic_vector(23 downto 0); -- 3/30/2013
signal Transmit_Addr_to_spi_clk : std_logic_vector(XIP_ADDR_BITS-1 downto 0); -- 3/30/2013
signal last_7_addr_bits : std_logic_vector(7 downto 0);
signal CPOL_to_spi_clk : std_logic;
signal CPHA_to_spi_clk : std_logic;
signal SS_to_spi_clk : std_logic_vector(C_NUM_SS_BITS-1 downto 0);
signal type_of_burst_to_spi : std_logic;
signal type_of_burst_to_spi_clk : std_logic;
signal axi_length_to_spi_clk : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);
signal dtr_length_to_spi_clk : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);
--signal wrap_around_to_axi_clk : std_logic;
signal spi_addr : std_logic_vector(31 downto 0);
signal spi_addr_i : std_logic_vector(XIP_ADDR_BITS-1 downto 0); -- (23 downto 0);
signal spi_addr_int : std_logic_vector(XIP_ADDR_BITS-1 downto 0); -- (23 downto 0);
signal spi_addr_wrap : std_logic_vector(XIP_ADDR_BITS-1 downto 0); -- (23 downto 0);
signal spi_addr_wrap_1 : std_logic_vector(XIP_ADDR_BITS-1 downto 0); -- (23 downto 0);
--signal Transmit_Addr_to_spi_clk : std_logic_vector(23 downto 0);
signal load_wrap_addr : std_logic;
signal wrap_two : std_logic;
signal wrap_four : std_logic;
signal wrap_eight : std_logic;
signal wrap_sixteen : std_logic;
signal SPIXfer_done_int : std_logic;
signal size_length_cntr : std_logic_vector(1 downto 0);
signal size_length_cntr_fixed : std_logic_vector(1 downto 0);
signal length_cntr : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);
signal cmd_addr_sent : std_logic;
signal SR_5_Tx_Empty, SR_5_Tx_Empty_d1, SR_5_Tx_Empty_d2 : std_logic;
signal wrap_around : std_logic;
signal rst_wrap_around : std_logic;
--signal pr_state_idle : std_logic;
signal one_byte_xfer_to_spi_clk : std_logic;
signal two_byte_xfer_to_spi_clk : std_logic;
signal four_byte_xfer_to_spi_clk : std_logic;
--signal store_date_in_drr_fifo : std_logic;
signal Data_To_Rx_FIFO_int : std_logic_vector(C_S_AXI4_DATA_WIDTH-1 downto 0);
signal SPIXfer_done_int_pulse_d2 : std_logic;
signal receive_Data_int : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);
--signal Data_To_Rx_FIFO : std_logic_vector(7 downto 0);
--signal load_axi_data_to_spi_clk : std_logic;
signal Tx_Data_d1 : std_logic_vector(31 downto 0);
signal Tx_Data_d2 : std_logic_vector(39 downto 0);
signal internal_count : std_logic_vector(3 downto 0);
signal SPI_cmd : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);
signal Transmit_Data : std_logic_vector(0 to C_NUM_TRANSFER_BITS-1);
signal Data_Dir : std_logic;
signal Data_Mode_1 : std_logic;
signal Data_Mode_0 : std_logic;
signal Data_Phase : std_logic;
signal Quad_Phase : std_logic;
signal Addr_Mode_1 : std_logic;
signal Addr_Mode_0 : std_logic;
signal Addr_Bit : std_logic;
signal Addr_Phase : std_logic;
signal CMD_Mode_1 : std_logic;
signal CMD_Mode_0 : std_logic;
--signal cmd_addr_cntr : std_logic_vector(2 downto 0);
--signal cmd_addr_sent : std_logic;
signal transfer_start : std_logic;
signal last_bt_one_data : std_logic;
--signal SPIXfer_done_int : std_logic;
signal actual_SPIXfer_done_int : std_logic;
signal transfer_start_d1 : std_logic;
signal transfer_start_d2 : std_logic;
signal transfer_start_d3 : std_logic;
signal transfer_start_pulse : std_logic;
signal SPIXfer_done_int_d1 : std_logic;
signal SPIXfer_done_int_pulse : std_logic;
signal SPIXfer_done_int_pulse_d1 : std_logic;
--signal SPIXfer_done_int_pulse_d2 : std_logic;
signal SPIXfer_done_int_pulse_d3 : std_logic;
--signal SPIXfer_done_int : std_logic;
signal mode_1 : std_logic;
signal mode_0 : std_logic;
signal Count : std_logic_vector(COUNT_WIDTH downto 0);
--signal receive_Data_int : std_logic_vector(7 downto 0);
signal rx_shft_reg_mode_0011 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal Sync_Set : std_logic;
signal Sync_Reset : std_logic;
signal sck_o_int : std_logic;
signal sck_d1 : std_logic;
signal sck_d2 : std_logic;
signal sck_rising_edge : std_logic;
signal Shift_Reg : std_logic_vector(0 to C_NUM_TRANSFER_BITS-1);
signal Serial_Dout_0 : std_logic;
signal Serial_Dout_1 : std_logic;
signal Serial_Dout_2 : std_logic;
signal Serial_Dout_3 : std_logic;
signal pr_state_cmd_ph : std_logic;
--signal qspi_cntrl_ps : std_logic;
signal stop_clock : std_logic;
signal stop_clock_reg : std_logic;
signal pr_state_data_receive : std_logic;
signal pr_state_non_idle : std_logic;
--signal pr_state_idle : std_logic;
--signal pr_state_cmd_ph : std_logic;
--signal SPIXfer_done_int_pulse : std_logic;
signal no_slave_selected : std_logic;
--signal rst_wrap_around : std_logic;
signal IO0_T_control : std_logic;
signal IO1_T_control : std_logic;
signal IO2_T_control : std_logic;
signal IO3_T_control : std_logic;
signal addr_cnt : std_logic_vector(2 downto 0);
signal addr_cnt1 : std_logic_vector(1 downto 0);
signal pr_state_addr_ph : std_logic;
signal SS_tri_state_en_control : std_logic;
signal SCK_tri_state_en_control : std_logic;
signal IO0_tri_state_en_control : std_logic;
signal IO1_tri_state_en_control : std_logic;
signal IO2_tri_state_en_control : std_logic;
signal IO3_tri_state_en_control : std_logic;
signal IO0_T_cntrl_spi : std_logic;
signal MODF_strobe_int : std_logic;
signal SPISEL_sync : std_logic;
signal spisel_d1 : std_logic;
signal MODF_strobe : std_logic;
signal Allow_MODF_Strobe : std_logic;
signal sck_o_in : std_logic;
--signal SCK_O_reg : std_logic;
signal slave_mode : std_logic;
--signal pr_state_non_idle : std_logic;
signal mst_modf_err_to_axi_clk : std_logic;
signal mst_modf_err_to_axi4_clk : std_logic;
signal Rx_FIFO_Full_to_axi4_clk : std_logic;
signal Rx_FIFO_Full_to_axi_clk : std_logic;
signal Rx_FIFO_Full : std_logic;
signal Rx_FIFO_Full_org : std_logic;
signal Rx_FIFO_Empty_Synced_in_SPI_domain : std_logic;
signal Rx_FIFO_Empty_Synced_in_AXI_domain : std_logic;
signal one_byte_xfer : std_logic;
signal two_byte_xfer : std_logic;
signal four_byte_xfer : std_logic;
signal XIP_trans_error : std_logic;
signal XIP_trans_cdc_to_error : std_logic;
signal load_cmd : std_logic;
signal load_cmd_to_spi_clk : std_logic;
--signal load_axi_data_frm_axi_clk : std_logic;
signal load_cmd_frm_axi_clk : std_logic;
signal axi_len_two : std_logic;
signal axi_len_four : std_logic;
signal axi_len_eight : std_logic;
signal axi_len_sixteen : std_logic;
signal reset_inversion : std_logic;
signal new_tr : std_logic;
signal SR_5_Tx_Empty_int : std_logic;
signal only_last_count : std_logic;
signal rx_fifo_cntr_rst, rx_fifo_not_empty : std_logic;
signal store_date_in_drr_fifo_d1 : std_logic;
signal store_date_in_drr_fifo_d2 : std_logic;
signal store_date_in_drr_fifo_d3 : std_logic;
signal xip_ns_state_idle : std_logic;
signal wrap_around_d1 : std_logic;
signal wrap_ack : std_logic;
signal wrap_ack_1 : std_logic;
signal wrap_around_d2 : std_logic;
signal wrap_around_d3 : std_logic;
signal start_after_wrap : std_logic;
signal store_last_b4_wrap : std_logic;
signal wrp_addr_len_16_siz_32 : std_logic;
signal wrp_addr_len_8_siz_32 : std_logic;
signal wrp_addr_len_4_siz_32 : std_logic;
signal wrp_addr_len_2_siz_32 : std_logic;
signal wrp_addr_len_16_siz_16 : std_logic;
signal wrp_addr_len_8_siz_16 : std_logic;
signal wrp_addr_len_4_siz_16 : std_logic;
signal wrp_addr_len_2_siz_16, start_after_wrap_d1 : std_logic;
signal SS_O_1 : std_logic_vector((C_NUM_SS_BITS-1) downto 0);
signal WB_wr_en_CMD : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);-- (7 downto 0);
signal WB_wr_sr_CMD : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);-- (7 downto 0);
signal WB_wr_sr_DATA : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);-- (7 downto 0);
signal WB_wr_hpm_CMD : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);-- (7 downto 0);
signal wb_wr_en_done : std_logic;
signal wb_wr_sr_done : std_logic;
signal wb_wr_sr_data_done : std_logic;
signal wb_wr_hpm_done : std_logic;
signal load_wr_en_cmd : std_logic;
signal load_wr_sr_cmd : std_logic;
signal load_wr_sr_d0 : std_logic;
signal load_wr_sr_d1 : std_logic;
signal load_rd_sr : std_logic;
signal load_wr_hpm : std_logic;
signal wb_hpm_done : std_logic;
signal wb_hpm_done_reg : std_logic;
signal dis_sr_5_empty_reg : std_logic;
signal dis_sr_5_empty : std_logic;
signal wb_hpm_done_frm_spi,wb_hpm_done_frm_spi_clk,wb_hpm_done_to_axi : std_logic;
signal hpm_under_process : std_logic;
signal hpm_under_process_d1 : std_logic;
signal s_axi_rlast_cmb : std_logic;
signal store_date_in_drr_fifo_en : std_logic;
signal XIP_trans_error_cmb, XIP_trans_error_d1, XIP_trans_error_d2, XIP_trans_error_d3 : std_logic;
signal axi4_tr_over_d1, axi4_tr_over_d2 : std_logic;
signal arready_d1, arready_d2, arready_d3 : std_logic;
signal XIPSR_CPHA_CPOL_ERR_d1, XIPSR_CPHA_CPOL_ERR_d2 : std_logic;
signal axi4_tr_over_d3 : std_logic;
signal last_data_acked_int_2 : std_logic;
signal XIP_trans_error_int_2 : std_logic;
signal s_axi_arready_int_2 : std_logic;
-- signal XIP_trans_error_cmb : std_logic;
-- signal axi4_tr_over_d1, axi4_tr_over_d2 : std_logic;
-- signal arready_d1, arready_d2, arready_d3 : std_logic;
-- signal XIPSR_CPHA_CPOL_ERR_d1, XIPSR_CPHA_CPOL_ERR_d2 : std_logic;
-- signal axi4_tr_over_d3 : std_logic;
-- signal last_data_acked_int_2 : std_logic;
-- signal XIP_trans_error_int_2 : std_logic;
-- signal s_axi_arready_int_2 : std_logic;
signal Rx_FIFO_Empty_d1, Rx_FIFO_Empty_d2 : std_logic;
signal XIPSR_CPHA_CPOL_ERR_4 : std_logic;
--signal mst_modf_err_to_axi4clk: std_logic;
signal xip_done : std_logic;
signal en_xip : std_logic;
signal new_tr_at_axi4 : std_logic;
signal axi4_tr_over : std_logic;
signal fifo_ren :std_logic;
--attribute ASYNC_REG : string;
--attribute ASYNC_REG of XIP_TRANS_ERROR_AXI2AXI4_CDC : label is "TRUE";
--attribute ASYNC_REG of Rx_FIFO_Empty_AXI42AXI : label is "TRUE";
--attribute ASYNC_REG of CPHA_CPOL_ERR_AXI2AXI4_CDC : label is "TRUE";
--attribute ASYNC_REG of ARREADY_PULSE_AXI42AXI_CDC: label is "TRUE";
--attribute ASYNC_REG of AXI4_TR_OVER_AXI42AXI_CDC : label is "TRUE";
constant LOGIC_CHANGE : integer range 0 to 1 := 1;
constant MTBF_STAGES_AXI2S : integer range 0 to 6 := 3 ;
constant MTBF_STAGES_S2AXI : integer range 0 to 6 := 4 ;
constant MTBF_STAGES_AXI2AXILITE : integer range 0 to 6 := 4 ;
-----
begin
-----
S_AXI4_WREADY <= '0';
S_AXI4_BID <= (others => '0');
S_AXI4_BRESP <= (others => '0');
S_AXI4_BVALID <= '0';
S_AXI4_AWREADY<= '0';
RX_FIFO_EMPTY_SYNC_AXI4_2_AXI_CDC : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1, -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => 2
)
port map (
prmry_aclk => S_AXI4_ACLK ,
prmry_resetn => '0',
prmry_in => Rx_FIFO_Empty,
scndry_aclk => S_AXI_ACLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => '0' ,
scndry_out => Rx_FIFO_Empty_Synced_in_AXI_domain
);
RX_FIFO_EMPTY_SYNC_AXI_2_SPI_CDC : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1, -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => 2
)
port map (
prmry_aclk => S_AXI4_ACLK ,
prmry_resetn => '0',
prmry_in => Rx_FIFO_Empty,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => '0' ,
scndry_out => Rx_FIFO_Empty_Synced_in_SPI_domain
);
Rx_FIFO_Full <= Rx_FIFO_Full_org and not Rx_FIFO_Empty_Synced_in_SPI_domain;
valid_decode <= S_AXI4_ARVALID and xip_pr_state_idle;
reset_inversion <= not S_AXI4_ARESET;
-- address decoder and CS generation in AXI interface
I_DECODER : entity axi_quad_spi_v3_2_8.qspi_address_decoder
generic map
(
C_BUS_AWIDTH => XIP_ADDR_BITS, -- C_S_AXI4_ADDR_WIDTH,
C_S_AXI4_MIN_SIZE => XIP_MIN_SIZE,
C_ARD_ADDR_RANGE_ARRAY=> C_XIP_FULL_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_XIP_FULL_ARD_NUM_CE_ARRAY,
C_FAMILY => "nofamily"
)
port map
(
Bus_clk => S_AXI4_ACLK, -- in std_logic;
Bus_rst => reset_inversion, -- in std_logic;
Address_In_Erly => S_AXI4_ARADDR(XIP_ADDR_BITS-1 downto 0), -- in std_logic_vector(0 to C_BUS_AWIDTH-1);
Address_Valid_Erly => s_axi_arready_cmb, -- in std_logic;
Bus_RNW => valid_decode, -- in std_logic;
Bus_RNW_Erly => valid_decode, -- in std_logic;
CS_CE_ld_enable => s_axi_arready_cmb, -- in std_logic;
Clear_CS_CE_Reg => temp_i, -- in std_logic;
RW_CE_ld_enable => s_axi_arready_cmb, -- in std_logic;
CS_for_gaps => open, -- out std_logic;
-- Decode output signals
CS_Out => SS_frm_axi,
RdCE_Out => open,
WrCE_Out => open
);
-------------------------------------------------
STORE_AXI_ARBURST_P: process (S_AXI4_ACLK) is
begin
if (S_AXI4_ACLK'event and S_AXI4_ACLK='1') then
if (S_AXI4_ARESET = ACTIVE_HIGH_RESET) then -- S_AXI4_ARESET is already inverted and made active high
type_of_burst <= '0';-- "01"; -- default is INCR burst
elsif(s_axi_arready_cmb = '1')then
type_of_burst <= S_AXI4_ARBURST(1) ;
end if;
end if;
end process STORE_AXI_ARBURST_P;
-----------------------
S_AXI4_ARREADY_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
S_AXI4_ARREADY <= '0';
else
S_AXI4_ARREADY <= s_axi_arready_cmb;
end if;
end if;
end process S_AXI4_ARREADY_P;
-- S_AXI4_ARREADY <= s_axi_arready_cmb;
STORE_AXI_LENGTH_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
axi_length <= (others => '0');
elsif(s_axi_arready_cmb = '1')then
axi_length <= S_AXI4_ARLEN;
end if;
end if;
end process STORE_AXI_LENGTH_P;
---------------------------------------------------
STORE_AXI_SIZE_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
size_length <= (others => '0');
elsif(s_axi_arready_cmb = '1')then
size_length <= S_AXI4_ARSIZE(1 downto 0);
end if;
end if;
end process STORE_AXI_SIZE_P;
-------------------------------------------------------------------------------
REG_RID_P: process (S_AXI4_ACLK) is
begin
if (S_AXI4_ACLK'event and S_AXI4_ACLK='1') then
if (S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
S_AXI4_RID_reg <= (others=> '0');
elsif(s_axi_arready_cmb = '1')then
S_AXI4_RID_reg <= S_AXI4_ARID ;
end if;
end if;
end process REG_RID_P;
----------------------
S_AXI4_RID <= S_AXI4_ARID when (s_axi_arready_cmb = '1') else S_AXI4_RID_reg; --kar S_AXI4_RID_reg
-----------------------------
OLD_LOGIC_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
STORE_AXI_ADDR_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
XIP_ADDR <= (others => '0');
elsif(s_axi_arready_cmb = '1')then
XIP_ADDR <= S_AXI4_ARADDR(23 downto 0);-- support for 24 bit address
end if;
end if;
end process STORE_AXI_ADDR_P;
end generate OLD_LOGIC_GEN;
---------------------------
NEW_LOGIC_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
STORE_AXI_ADDR_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
XIP_ADDR <= (others => '0');
elsif(s_axi_arready_cmb = '1')then
XIP_ADDR <= S_AXI4_ARADDR(C_SPI_MEM_ADDR_BITS-1 downto 0);-- support for 24 or 32 bit address
end if;
end if;
end process STORE_AXI_ADDR_P;
end generate NEW_LOGIC_GEN;
---------------------------
------------------------------------------------------------------------------
ONE_BYTE_XFER_P:process(S_AXI4_ACLK) is
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
one_byte_xfer <= '0';
elsif(s_axi_arready_cmb = '1')then
one_byte_xfer <= not(or_reduce(S_AXI4_ARSIZE(1 downto 0)));
end if;
end if;
end process ONE_BYTE_XFER_P;
TWO_BYTE_XFER_P:process(S_AXI4_ACLK) is
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
two_byte_xfer <= '0';
elsif(s_axi_arready_cmb = '1')then
two_byte_xfer <= S_AXI4_ARSIZE(0);
end if;
end if;
end process TWO_BYTE_XFER_P;
FOUR_BYTE_XFER_P:process(S_AXI4_ACLK) is
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
four_byte_xfer <= '0';
elsif(s_axi_arready_cmb = '1')then
four_byte_xfer <= S_AXI4_ARSIZE(1);
end if;
end if;
end process FOUR_BYTE_XFER_P;
---------------------------------------------------------------------------------
STORE_DTR_LENGTH_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
dtr_length <= (others => '0');
elsif(s_axi_arready_cmb = '1')then
dtr_length <= S_AXI4_ARLEN;-- + "00000001";
-- elsif(S_AXI4_RREADY = '1' and s_axi_rvalid_i = '1') then
--elsif(Rx_FIFO_rd_ack = '1') then
elsif(fifo_ren = '1') then
dtr_length <= dtr_length - '1';
end if;
end if;
end process STORE_DTR_LENGTH_P;
-----------------------------------------------------
STORE_WRITE_LENGTH_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then -- if(xip_sm_ps = IDLE)then
write_length <= (others => '0');
elsif(s_axi_arready_cmb = '1')then
write_length <= S_AXI4_ARLEN + "00000001";
elsif(spiXfer_done_to_axi_1 = '1')then
write_length <= write_length - '1';
end if;
end if;
end process STORE_WRITE_LENGTH_P;
-----------------------------------------------------
--dtr_cntr_empty <= or_Reduce(dtr_length);
-----------------------------------------------------
last_bt_one_data_cmb <= not(or_reduce(dtr_length(C_NUM_TRANSFER_BITS-1 downto 1))) and
dtr_length(0) and
S_AXI4_RREADY;
last_data_cmb <= not(or_reduce(dtr_length(C_NUM_TRANSFER_BITS-1 downto 0)));
RX_FIFO_FULL_CNTR_I : entity axi_quad_spi_v3_2_8.counter_f
generic map(
C_NUM_BITS => RX_FIFO_CNTR_WIDTH,
C_FAMILY => "nofamily"
)
port map(
Clk => S_AXI4_ACLK, -- in
Rst => S_AXI4_ARESET, -- '0', -- in
-- coverage off
Load_In => ALL_1, -- in
-- coverage on
Count_Enable => updown_cnt_en_rx, -- in
----------------
Count_Load => s_axi_arready_cmb,-- in
----------------
Count_Down => down_cnt_en_rx, -- in
Count_Out => rx_fifo_count, -- out std_logic_vector
Carry_Out => open -- out
);
updown_cnt_en_rx <= s_axi_arready_cmb or
spiXfer_done_to_axi_1 or
(down_cnt_en_rx); -- this is to make the counter enable for decreasing.
down_cnt_en_rx <= S_AXI4_RREADY and s_axi_rvalid_i;
only_last_count <= not(or_reduce(rx_fifo_count(RX_FIFO_CNTR_WIDTH-1 downto 0))) and
last_data_cmb;
rx_fifo_not_empty <= or_reduce(rx_fifo_count(RX_FIFO_CNTR_WIDTH-1 downto 0));
LAST_DATA_ACKED_P: process (S_AXI4_ACLK) is
-----------------
begin
-----
if (S_AXI4_ACLK'event and S_AXI4_ACLK='1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
last_data_acked <= '0';
else
if(S_AXI4_RREADY = '1' and last_data_acked = '1') then -- AXI Ready and Rlast active
last_data_acked <= '0';
elsif(S_AXI4_RREADY = '0' and last_data_acked = '1')then-- AXI not Ready and Rlast active, then hold the RLAST signal
last_data_acked <= '1';
else
last_data_acked <=(last_data_cmb and
Rx_FIFO_rd_ack);
end if;
end if;
end if;
end process LAST_DATA_ACKED_P;
------------------------------
S_AXI4_RLAST <= '1' when (last_data_cmb='1' and S_AXI4_ARESET /= ACTIVE_HIGH_RESET ) else '0';--last_data_acked;
--------------------------------
S_AXI4_RDATA_RESP_P : process (S_AXI4_ACLK) is
begin
if S_AXI4_ACLK'event and S_AXI4_ACLK = '1' then
if (S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
S_AXI4_RRESP_i <= (others => '0');
--karS_AXI4_RDATA_i <= (others => '0');
else-- if(S_AXI4_RREADY = '1' )then -- and (Rx_FIFO_Empty = '0')then
S_AXI4_RRESP_i <= --(rd_error_int or mst_modf_err_to_axi_clk) & '0';
(mst_modf_err_to_axi4_clk) & '0';
--karS_AXI4_RDATA_i <= Data_From_Rx_FIFO;
end if;
end if;
end process S_AXI4_RDATA_RESP_P;
--------------------------------
S_AXI4_RRESP <= (mst_modf_err_to_axi4_clk) & '0';--S_AXI4_RRESP_i;
S_AXI4_RDATA <= Data_From_Rx_FIFO;--S_AXI4_RDATA_i;
-------------------------------
-----------------------------
-- S_AXI_RVALID_I_P : below process generates the RVALID response on read channel
----------------------
--karS_AXI_RVALID_I_P : process (S_AXI4_ACLK) is
--kar begin
--kar if S_AXI4_ACLK'event and S_AXI4_ACLK = '1' then
--kar if (S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
--kar s_axi_rvalid_i <= '0';
--kar elsif(S_AXI4_RREADY = '1' and (s_axi_rvalid_i = '1')) then -- and (s_axi_rvalid_i = '1') then -- AXI Ready and Rlast active
--kar s_axi_rvalid_i <= '0';--not(Rx_FIFO_Empty);--Rx_FIFO_rd_ack; -- '0';
--kar elsif(S_AXI4_RREADY = '1' and (s_axi_rvalid_i = '0')) then -- and (s_axi_rvalid_i = '1') then -- AXI Ready and Rlast active
--kar s_axi_rvalid_i <= not(Rx_FIFO_Empty);--Rx_FIFO_rd_ack; -- '0';
--kar elsif(S_AXI4_RREADY = '0') and (s_axi_rvalid_i = '1') then
--kar s_axi_rvalid_i <= s_axi_rvalid_i;
--kar else
--kar s_axi_rvalid_i <= not(Rx_FIFO_Empty);--Rx_FIFO_rd_ack;
--kar end if;
--kar end if;
--karend process S_AXI_RVALID_I_P;
-----------------------------
--karS_AXI_RVALID_I_P : process (S_AXI4_ACLK) is
--kar begin
--kar if S_AXI4_ACLK'event and S_AXI4_ACLK = '1' then
--kar if (S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
--kar s_axi_rvalid_i <= '0';
--kar else
--kar s_axi_rvalid_i <= not(Rx_FIFO_Empty);
--kar end if;
--kar end if;
--kar end process S_AXI_RVALID_I_P;
s_axi_rvalid_i <= not(Rx_FIFO_Empty);
S_AXI4_RVALID <= s_axi_rvalid_i;
fifo_ren <= S_AXI4_RREADY and s_axi_rvalid_i;
-- -----------------------------
--fifo_non_empty <= not(Rx_FIFO_Empty);
-----------------------------
-- REN_Generation : below process generates the Fifo_Ren
----------------------
--karREN_Generation : process (S_AXI4_ACLK) is
--kar begin
--kar if S_AXI4_ACLK'event and S_AXI4_ACLK = '1' then
--kar if (S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
--kar fifo_ren <= '0';
--kar elsif(S_AXI4_RREADY = '1' and (s_axi_rvalid_i = '1')) then
--kar fifo_ren <= '1';
--kar else
--kar fifo_ren <= '0';--Rx_FIFO_rd_ack;
--kar end if;
--kar end if;
--karend process REN_Generation;
-----------------------------
xip_pr_state_idle <= '1' when xip_sm_ps = IDLE else '0';
xip_ns_state_idle <= '1' when xip_sm_ns = IDLE else '0';
rready_i <= S_AXI4_RREADY and not last_data_cmb;
------------------------------------------------------------------------------
XIP_trans_error_cmb <= not(or_reduce(S_AXI4_ARBURST)) and (S_AXI4_ARVALID);
-- XIP_TR_ERROR_PULSE_STRETCH_1: single pulse for AXI4 transaction error
LOGIC_GENERATION_FDR : if (Async_Clk = 0) generate
attribute ASYNC_REG : string;
attribute ASYNC_REG of XIP_TRANS_ERROR_AXI2AXI4_CDC : label is "TRUE";
--attribute ASYNC_REG of Rx_FIFO_Empty_AXI42AXI : label is "TRUE";
attribute ASYNC_REG of CPHA_CPOL_ERR_AXI2AXI4_CDC : label is "TRUE";
attribute ASYNC_REG of ARREADY_PULSE_AXI42AXI_CDC: label is "TRUE";
attribute ASYNC_REG of AXI4_TR_OVER_AXI42AXI_CDC : label is "TRUE";
begin
XIP_TR_ERROR_PULSE_STRETCH_1: process(S_AXI4_ACLK)is
begin
if(S_AXI4_ACLK'event and S_AXI4_ACLK= '1') then
if(S_AXI4_ARESET = '1') then
XIP_trans_error_int_2 <= '0';
else
XIP_trans_error_int_2 <= XIP_trans_error_cmb xor
XIP_trans_error_int_2;
end if;
end if;
end process XIP_TR_ERROR_PULSE_STRETCH_1;
-------------------------------------
XIP_TRANS_ERROR_AXI2AXI4_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => XIP_trans_error_d1,
C => S_AXI_ACLK,
D => XIP_trans_error_int_2,
R => S_AXI_ARESETN
);
XIP_TRANS_ERROR_AXI2AXI4_1: component FDR
generic map(INIT => '0'
)port map (
Q => XIP_trans_error_d2,
C => S_AXI_ACLK,
D => XIP_trans_error_d1,
R => S_AXI_ARESETN
);
XIP_TRANS_ERROR_AXI2AXI4_2: component FDR
generic map(INIT => '0'
)port map (
Q => XIP_trans_error_d3,
C => S_AXI_ACLK,
D => XIP_trans_error_d2,
R => S_AXI_ARESETN
);
XIP_trans_error <= XIP_trans_error_d2 xor XIP_trans_error_d3;
------------------------------------------------------------------------------
--mst_modf_err_to_axi <= mst_modf_err_d2;
-- TO XIP Status Register
-- LAST_DATA_PULSE_STRETCH_1: single pulse for AXI4 transaction completion
LAST_DATA_PULSE_STRETCH_1: process(S_AXI4_ACLK)is
begin
if(S_AXI4_ACLK'event and S_AXI4_ACLK= '1') then
if(S_AXI4_ARESET = '1') then
last_data_acked_int_2 <= '0';
else
last_data_acked_int_2 <= last_data_acked xor
last_data_acked_int_2;
end if;
end if;
end process LAST_DATA_PULSE_STRETCH_1;
-------------------------------------
AXI4_TR_OVER_AXI42AXI_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => axi4_tr_over_d1,
C => S_AXI_ACLK,
D => last_data_acked_int_2,
R => S_AXI_ARESETN
);
AXI4_TR_OVER_AXI42AXI_1: component FDR
generic map(INIT => '0'
)port map (
Q => axi4_tr_over_d2,
C => S_AXI_ACLK,
D => axi4_tr_over_d1,
R => S_AXI_ARESETN
);
AXI4_TR_OVER_AXI42AXI_2: component FDR
generic map(INIT => '0'
)port map (
Q => axi4_tr_over_d3,
C => S_AXI_ACLK,
D => axi4_tr_over_d2,
R => S_AXI_ARESETN
);
axi4_tr_over <= axi4_tr_over_d2 xor axi4_tr_over_d3;
-------------------------------------------------------------
-- ARREADY_PULSE_STRETCH_1: single pulse for AXI4 transaction acceptance
ARREADY_PULSE_STRETCH_1: process(S_AXI4_ACLK)is
begin
if(S_AXI4_ACLK'event and S_AXI4_ACLK= '1') then
if(S_AXI4_ARESET = '1') then
s_axi_arready_int_2 <= '0';
else
s_axi_arready_int_2 <= s_axi_arready_cmb xor
s_axi_arready_int_2;
end if;
end if;
end process ARREADY_PULSE_STRETCH_1;
-------------------------------------
ARREADY_PULSE_AXI42AXI_CDC: component FDR
generic map(INIT => '1'
)port map (
Q => arready_d1,
C => S_AXI_ACLK,
D => s_axi_arready_int_2,
R => S_AXI_ARESETN
);
ARREADY_PULSE_AXI42AXI_2: component FDR
generic map(INIT => '1'
)port map (
Q => arready_d2,
C => S_AXI_ACLK,
D => arready_d1,
R => S_AXI_ARESETN
);
ARREADY_PULSE_AXI42AXI_3: component FDR -- 2/21/2012
generic map(INIT => '1'
)port map (
Q => arready_d3,
C => S_AXI_ACLK,
D => arready_d2,
R => S_AXI_ARESETN
);
new_tr_at_axi4 <= arready_d2 xor arready_d3;
-------------------------------------
------------------------------------------------------------------------------
-- CPHA_CPOL_ERR_AXI2AXI4_CDC: CDC flop at cross clock boundary
CPHA_CPOL_ERR_AXI2AXI4_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => XIPSR_CPHA_CPOL_ERR_d1,
C => S_AXI4_ACLK,
D => XIPSR_CPHA_CPOL_ERR,
R => S_AXI4_ARESET
);
CPHA_CPOL_ERR_AXI2AXI4_1: component FDR
generic map(INIT => '0'
)port map (
Q => XIPSR_CPHA_CPOL_ERR_d2,
C => S_AXI4_ACLK,
D => XIPSR_CPHA_CPOL_ERR_d1,
R => S_AXI4_ARESET
);
XIPSR_CPHA_CPOL_ERR_4 <= XIPSR_CPHA_CPOL_ERR_d2;
-------------------------------------------------------------------------------
end generate LOGIC_GENERATION_FDR;
LOGIC_GENERATION_CDC : if (Async_Clk = 1) generate
--=================================================================================
XIP_TR_ERROR_PULSE_STRETCH_1_P: process(S_AXI4_ACLK)is
begin
if(S_AXI4_ACLK'event and S_AXI4_ACLK= '1') then
if(S_AXI4_ARESET = '1') then
XIP_trans_error_int_2 <= '0';
else
XIP_trans_error_int_2 <= XIP_trans_error_cmb xor
XIP_trans_error_int_2;
end if;
end if;
end process XIP_TR_ERROR_PULSE_STRETCH_1_P;
XIP_TRANS_ERROR_AXI42AXI: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2AXILITE
)
port map (
prmry_aclk => S_AXI4_ACLK ,
prmry_resetn => S_AXI_ARESETN ,
prmry_in => XIP_trans_error_int_2 ,
scndry_aclk => S_AXI_ACLK ,
prmry_vect_in => (others => '0') ,
scndry_resetn => S_AXI_ARESETN ,
scndry_out => XIP_trans_error_d2
);
XIP_TR_ERROR_PULSE_STRETCH_1: process(S_AXI_ACLK)is
begin
if(S_AXI_ACLK'event and S_AXI_ACLK= '1') then
XIP_trans_error_d3 <= XIP_trans_error_d2 ;
end if;
end process XIP_TR_ERROR_PULSE_STRETCH_1;
XIP_trans_cdc_to_error <= XIP_trans_error_d2 xor XIP_trans_error_d3;
XIP_trans_error <= XIP_trans_cdc_to_error;
--=================================================================================
LAST_DATA_PULSE_STRETCH_1_CDC: process(S_AXI4_ACLK)is
begin
if(S_AXI4_ACLK'event and S_AXI4_ACLK= '1') then
if(S_AXI4_ARESET = '1') then
last_data_acked_int_2 <= '0';
--axi4_tr_over_d1 <= '0';
else
last_data_acked_int_2 <= last_data_acked xor
last_data_acked_int_2;
--axi4_tr_over_d1 <= last_data_acked_int_2;
end if;
end if;
end process LAST_DATA_PULSE_STRETCH_1_CDC;
AXI4_TR_OVER_AXI42AXI: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 1 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2AXILITE
)
port map (
prmry_aclk => S_AXI4_ACLK ,
prmry_resetn => S_AXI4_ARESET ,
prmry_in => last_data_acked_int_2 ,
scndry_aclk => S_AXI_ACLK ,
prmry_vect_in => (others => '0') ,
scndry_resetn => S_AXI_ARESETN ,
scndry_out => axi4_tr_over_d2
);
LAST_DATA_PULSE_STRETCH_1: process(S_AXI_ACLK)is
begin
if(S_AXI_ACLK'event and S_AXI_ACLK= '1') then
axi4_tr_over_d3 <= axi4_tr_over_d2 ;
-- end if;
end if;
end process LAST_DATA_PULSE_STRETCH_1;
axi4_tr_over <= axi4_tr_over_d2 xor axi4_tr_over_d3;
--=================================================================================
ARREADY_PULSE_STRETCH_1_CDC: process(S_AXI4_ACLK)is
begin
if(S_AXI4_ACLK'event and S_AXI4_ACLK= '1') then
if(S_AXI4_ARESET = '1') then
s_axi_arready_int_2 <= '1';
--arready_d1 <= '0';
else
s_axi_arready_int_2 <= s_axi_arready_cmb xor
s_axi_arready_int_2;
--arready_d1 <= s_axi_arready_int_2;
end if;
end if;
end process ARREADY_PULSE_STRETCH_1_CDC;
ARREADY_PULSE_AXI42AXI: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 1 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2AXILITE
)
port map (
prmry_aclk => S_AXI4_ACLK ,
prmry_resetn => S_AXI4_ARESET ,
prmry_in => s_axi_arready_int_2 ,
scndry_aclk => S_AXI_ACLK ,
prmry_vect_in => (others => '0') ,
scndry_resetn => S_AXI_ARESETN ,
scndry_out => arready_d2
);
ARREADY_PULSE_STRETCH_1: process(S_AXI_ACLK)is
begin
if(S_AXI_ACLK'event and S_AXI_ACLK= '1') then
arready_d3 <= arready_d2;
-- end if;
end if;
end process ARREADY_PULSE_STRETCH_1;
new_tr_at_axi4 <= arready_d2 xor arready_d3;
--==================================================================================
CPHA_CPOL_ERR_AXI2AXI4: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2AXILITE
)
port map (
prmry_aclk => S_AXI_ACLK ,
prmry_resetn => S_AXI_ARESETN ,
prmry_in => XIPSR_CPHA_CPOL_ERR ,
scndry_aclk => S_AXI4_ACLK ,
prmry_vect_in => (others => '0') ,
scndry_resetn => S_AXI4_ARESET ,
scndry_out => XIPSR_CPHA_CPOL_ERR_4
);
--==================================================================================
end generate LOGIC_GENERATION_CDC;
TO_XIPSR_axi_rx_empty <= Rx_FIFO_Empty_Synced_in_AXI_domain;
--XIPSR_RX_EMPTY_P: process(S_AXI_ACLK)is
--begin
-- if(S_AXI_ACLK'event and S_AXI_ACLK = '1')then
-- if(S_AXI_ARESETN = ACTIVE_HIGH_RESET) then
-- TO_XIPSR_axi_rx_empty <= '1';
-- elsif(axi4_tr_over = '1')then
-- TO_XIPSR_axi_rx_empty <= '1';
-- elsif(new_tr_at_axi4 = '1')then
-- TO_XIPSR_axi_rx_empty <= '0';
-- end if;
-- end if;
--end process XIPSR_RX_EMPTY_P;
-------------------------------------
TO_XIPSR_trans_error <= XIP_trans_error;
TO_XIPSR_mst_modf_err <= mst_modf_err_to_axi_clk;
TO_XIPSR_axi_rx_full <= Rx_FIFO_Full_to_axi_clk;
-- XIP_PS_TO_NS_PROCESS: stores the next state memory
XIP_PS_TO_NS_PROCESS: process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
xip_sm_ps <= IDLE;
else
xip_sm_ps <= xip_sm_ns;
end if;
end if;
end process XIP_PS_TO_NS_PROCESS;
-----------------------------
-- XIP_SM_P: below state machine is AXI interface state machine and controls the
-- acceptance of new transaction as well as monitors data transaction
XIP_SM_P:process(
xip_sm_ps ,
S_AXI4_ARVALID ,
S_AXI4_RREADY ,
S_AXI4_ARBURST ,
XIP_trans_error_cmb ,
mst_modf_err_to_axi4_clk,
Rx_FIFO_Full_to_Axi4_clk,
XIPSR_CPHA_CPOL_ERR_4 ,
Rx_FIFO_Empty ,
wb_hpm_done_to_axi ,
spiXfer_done_to_axi_1 ,
last_data_cmb ,
Rx_FIFO_rd_ack ,--,
last_data_acked
--wrap_around_to_axi_clk ,
--last_bt_one_data_cmb ,
--Rx_FIFO_Empty ,
--only_last_count ,
--rx_fifo_not_empty ,
--rx_fifo_count ,
)is
begin
-----
s_axi_arready_cmb <= '0';
load_axi_data_frm_axi <= '0';
load_cmd <= '0';
s_axi_rlast_cmb <= '0';
s_axi_rvalid_cmb <= '0';
last_data <= '0';
--IO0_T_cntrl_axi <= '1';
--IO1_T_cntrl_axi <= '1';
--IO2_T_cntrl_axi <= '1';
--IO3_T_cntrl_axi <= '1';
--SCK_T_cntrl_axi <= '1';
temp_i <= '0';
case xip_sm_ps is
when IDLE => --if(XIP_cmd_error = '0') then
if(S_AXI4_ARVALID = '1') and
(XIP_trans_error_cmb = '0') and
(mst_modf_err_to_axi4_clk = '0') and
(Rx_FIFO_Full_to_axi4_clk = '0') and
(XIPSR_CPHA_CPOL_ERR_4 = '0') and
(Rx_FIFO_Empty = '1') and
(wb_hpm_done_to_axi = '1')
then
s_axi_arready_cmb <= S_AXI4_ARVALID;
load_axi_data_frm_axi <= S_AXI4_ARVALID;
load_cmd <= S_AXI4_ARVALID;
xip_sm_ns <= RD_BURST;
else
xip_sm_ns <= IDLE;
end if;
when RD_BURST =>
--if(last_data_cmb = '1') and (Rx_FIFO_rd_ack = '1') then--(rx_fifo_count = "000001") then
if (last_data_acked = '1') then
if(S_AXI4_RREADY = '1') then
temp_i <= '1';
xip_sm_ns <= IDLE;
else
xip_sm_ns <= RD_BURST;
end if;
else
xip_sm_ns <= RD_BURST;
end if;
-- coverage off
when others => xip_sm_ns <= IDLE;
-- coverage on
end case;
end process XIP_SM_P;
----------------------
-- AXI_24_BIT_ADDR_STORE_GEN: stores 24 bit axi address
AXI_24_BIT_ADDR_STORE_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
LOAD_TRANSMIT_ADDR_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
Transmit_addr_int <= (others => '0');
elsif(load_axi_data_frm_axi = '1') then
Transmit_addr_int <= S_AXI4_ARADDR(23 downto 0);-- & XIPCR_7_0_CMD;
end if;
end if;
end process LOAD_TRANSMIT_ADDR_P;
end generate AXI_24_BIT_ADDR_STORE_GEN;
-----------------------------------------
-- AXI_32_BIT_ADDR_STORE_GEN: stores 32 bit axi address
AXI_32_BIT_ADDR_STORE_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate -- 3/30/2013 updated for 32 or 24 bit addressing modes
begin
LOAD_TRANSMIT_ADDR_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
Transmit_addr_int <= (others => '0');
elsif(load_axi_data_frm_axi = '1') then
Transmit_addr_int <= S_AXI4_ARADDR(C_SPI_MEM_ADDR_BITS-1 downto 0);-- & XIPCR_7_0_CMD;
end if;
end if;
end process LOAD_TRANSMIT_ADDR_P;
end generate AXI_32_BIT_ADDR_STORE_GEN;
-----------------------------------------
-- 24/32-bit --
-- AXI Clk domain -- __________________ SPI clk domain
--Dout --|AXI clk |-- Din
--Rd_en --| |-- Wr_en
--Rd_clk --| |-- Wr_clk
--| |--
--Rx_FIFO_Empty --| Rx FIFO |-- Rx_FIFO_Full_org
--Rx_FIFO_almost_Empty --| |-- Rx_FIFO_almost_Full
--Rx_FIFO_occ_Reversed --| |--
--Rx_FIFO_rd_ack --| |--
--| |--
--| |--
--| |--
--|__________________|--
-------------------------------------------------------------------------------
XIP_RECEIVE_FIFO_II: entity lib_fifo_v1_0_5.async_fifo_fg
generic map(
-- 3/30/2013 starts
C_PRELOAD_LATENCY => 0 ,-- this is newly added and async_fifo_fg is referred from proc common v4_0
C_PRELOAD_REGS => 1 ,-- this is newly added and async_fifo_fg is referred from proc common v4_0
-- 3/30/2013 ends
-- variables
C_ALLOW_2N_DEPTH => 1 , -- : Integer := 0; -- New paramter to leverage FIFO Gen 2**N depth
C_FAMILY => C_FAMILY , -- : String := "virtex5"; -- new for FIFO Gen
C_DATA_WIDTH => C_S_AXI4_DATA_WIDTH , -- : integer := 16;
C_FIFO_DEPTH => C_XIP_FIFO_DEPTH , -- : integer := 256;
C_RD_COUNT_WIDTH => C_RD_COUNT_WIDTH_INT, -- : integer := 3 ;
C_WR_COUNT_WIDTH => C_WR_COUNT_WIDTH_INT, -- : integer := 3 ;
C_HAS_ALMOST_EMPTY => 1 , -- : integer := 1 ;
C_HAS_ALMOST_FULL => 1 , -- : integer := 1 ;
C_HAS_RD_ACK => 1 , -- : integer := 0 ;
C_HAS_RD_COUNT => 1 , -- : integer := 1 ;
C_HAS_WR_ACK => 1 , -- : integer := 0 ;
C_HAS_WR_COUNT => 1 , -- : integer := 1 ;
-- constants
C_HAS_RD_ERR => 0 , -- : integer := 0 ;
C_HAS_WR_ERR => 0 , -- : integer := 0 ;
C_RD_ACK_LOW => 0 , -- : integer := 0 ;
C_RD_ERR_LOW => 0 , -- : integer := 0 ;
C_WR_ACK_LOW => 0 , -- : integer := 0 ;
C_WR_ERR_LOW => 0 , -- : integer := 0
C_ENABLE_RLOCS => 0 , -- : integer := 0 ; -- not supported in FG
C_USE_BLOCKMEM => 0 -- : integer := 1 ; -- 0 = distributed RAM, 1 = BRAM
)
port map(
Dout => Data_From_Rx_FIFO , -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
Rd_en => fifo_ren , --S_AXI4_RREADY , -- : in std_logic := '0';
Rd_clk => S_AXI4_ACLK , -- : in std_logic := '1';
Rd_ack => Rx_FIFO_rd_ack , -- : out std_logic;
------
Din => Data_To_Rx_FIFO , -- : in std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0');
Wr_en => store_date_in_drr_fifo_en , --SPIXfer_done_Rx_Wr_en, -- , -- : in std_logic := '1';
Wr_clk => EXT_SPI_CLK , -- : in std_logic := '1';
Wr_ack => open, -- Rx_FIFO_wr_ack_open, -- : out std_logic;
------
Full => Rx_FIFO_Full_org, --Rx_FIFO_Full, -- : out std_logic;
Empty => Rx_FIFO_Empty , -- : out std_logic;
Almost_full => Rx_FIFO_almost_Full , -- : out std_logic;
Almost_empty => Rx_FIFO_almost_Empty , -- : out std_logic;
Rd_count => open , -- : out std_logic_vector(C_RD_COUNT_WIDTH-1 downto 0);
------
Ainit => Rst_to_spi ,--reset_RcFIFO_ptr_int, -- reset_RcFIFO_ptr_to_spi_clk ,--Rx_FIFO_ptr_RST , -- : in std_logic := '1';
Wr_count => open , -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
Rd_err => rd_error_int , -- : out std_logic;
Wr_err => open -- : out std_logic
);
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- from SPI clock
spiXfer_done_frm_spi_clk <= store_date_in_drr_fifo_en; --spiXfer_done_int;
mst_modf_err_frm_spi_clk <= not SPISEL_sync; -- 9/7/2013 -- MODF_strobe; -- 9/7/2013
--wrap_around_frm_spi_clk <= wrap_around;
wb_hpm_done_frm_spi_clk <= wb_hpm_done;
-- from AXI clocks
--size_length_frm_axi_clk <= size_length;
one_byte_xfer_frm_axi_clk <= one_byte_xfer;
two_byte_xfer_frm_axi_clk <= two_byte_xfer;
four_byte_xfer_frm_axi_clk <= four_byte_xfer;
load_axi_data_frm_axi_clk <= load_axi_data_frm_Axi;-- 1 bit
Transmit_Addr_frm_axi_clk <= Transmit_addr_int; -- 24 bit
load_cmd_frm_axi_clk <= load_cmd;
CPOL_frm_axi_clk <= XIPCR_1_CPOL; -- 1 bit
CPHA_frm_axi_clk <= XIPCR_0_CPHA; -- 1 bit
SS_frm_axi_clk <= SS_frm_axi; -- _reg; -- based upon C_NUM_SS_BITS
type_of_burst_frm_axi_clk <= type_of_burst; -- 1 bit signal take MSB only to differentiate WRAP and INCR burst
axi_length_frm_axi_clk <= axi_length; -- 8 bit used for WRAP transfer
dtr_length_frm_axi_clk <= dtr_length; -- 8 bit used for internbal counter
XIP_CLK_DOMAIN_SIGNALS:entity axi_quad_spi_v3_2_8.xip_cross_clk_sync
generic map(
C_S_AXI4_DATA_WIDTH => C_S_AXI4_DATA_WIDTH ,
Async_Clk => Async_Clk ,
C_NUM_SS_BITS => C_NUM_SS_BITS ,
C_SPI_MEM_ADDR_BITS => XIP_ADDR_BITS
)
port map(
EXT_SPI_CLK => EXT_SPI_CLK ,
S_AXI4_ACLK => S_AXI4_ACLK ,
S_AXI4_ARESET => S_AXI4_ARESET ,
S_AXI_ACLK => S_AXI_ACLK ,
S_AXI_ARESETN => S_AXI_ARESETN ,
Rst_from_axi_cdc_to_spi => Rst_to_spi ,
----------------------------
spiXfer_done_cdc_from_spi => spiXfer_done_frm_spi_clk ,
spiXfer_done_cdc_to_axi_1 => spiXfer_done_to_axi_1 ,
----------------------------
mst_modf_err_cdc_from_spi => mst_modf_err_frm_spi_clk ,
mst_modf_err_cdc_to_axi => mst_modf_err_to_axi_clk ,
mst_modf_err_cdc_to_axi4 => mst_modf_err_to_axi4_clk ,
----------------------------
one_byte_xfer_cdc_from_axi => one_byte_xfer_frm_axi_clk ,
one_byte_xfer_cdc_to_spi => one_byte_xfer_to_spi_clk ,
----------------------------
two_byte_xfer_cdc_from_axi => two_byte_xfer_frm_axi_clk ,
two_byte_xfer_cdc_to_spi => two_byte_xfer_to_spi_clk ,
----------------------------
four_byte_xfer_cdc_from_axi => four_byte_xfer_frm_axi_clk ,
four_byte_xfer_cdc_to_spi => four_byte_xfer_to_spi_clk ,
----------------------------
load_axi_data_cdc_from_axi => load_axi_data_frm_axi_clk ,
load_axi_data_cdc_to_spi => load_axi_data_to_spi_clk ,
----------------------------
Transmit_Addr_cdc_from_axi => Transmit_Addr_frm_axi_clk ,
Transmit_Addr_cdc_to_spi => Transmit_Addr_to_spi_clk ,
----------------------------
load_cmd_cdc_from_axi => load_cmd_frm_axi_clk ,
load_cmd_cdc_to_spi => load_cmd_to_spi_clk ,
----------------------------
CPOL_cdc_from_axi => CPOL_frm_axi_clk ,
CPOL_cdc_to_spi => CPOL_to_spi_clk ,
----------------------------
CPHA_cdc_from_axi => CPHA_frm_axi_clk ,
CPHA_cdc_to_spi => CPHA_to_spi_clk ,
------------------------------
SS_cdc_from_axi => SS_frm_axi_clk ,
SS_cdc_to_spi => SS_to_spi_clk ,
----------------------------
type_of_burst_cdc_from_axi => type_of_burst_frm_axi_clk ,
type_of_burst_cdc_to_spi => type_of_burst_to_spi_clk ,
----------------------------
axi_length_cdc_from_axi => axi_length_frm_axi_clk ,
axi_length_cdc_to_spi => axi_length_to_spi_clk ,
----------------------------
dtr_length_cdc_from_axi => dtr_length_frm_axi_clk ,
dtr_length_cdc_to_spi => dtr_length_to_spi_clk , --,
----------------------------
Rx_FIFO_Full_cdc_from_spi => Rx_FIFO_Full ,
Rx_FIFO_Full_cdc_to_axi => Rx_FIFO_Full_to_axi_clk ,
Rx_FIFO_Full_cdc_to_axi4 => Rx_FIFO_Full_to_axi4_clk ,
----------------------------
wb_hpm_done_cdc_from_spi => wb_hpm_done_frm_spi_clk ,
wb_hpm_done_cdc_to_axi => wb_hpm_done_to_axi
);
-------------------------------------------------------------------------------
-- STORE_NEW_TR_P: This process is used in INCR and WRAP to check for any new transaction from AXI
STORE_NEW_TR_32_BIT_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-----
-------------------------------------
STORE_NEW_TR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
new_tr <= '0';
elsif( (load_axi_data_to_spi_clk = '1')
or (load_wr_hpm = '1') -- needed for enabling 32 bit addressing mode
or (load_wr_en = '1') -- needed for write enabling before enabling the 32 bit addressing mode
) then
new_tr <= '1';
elsif(SR_5_Tx_Empty_int = '1') then --(wrap_around = '0' and qspi_cntrl_ns = IDLE)then
new_tr <= '0';
end if;
end if;
end process STORE_NEW_TR_P;
-------------------------------------
end generate STORE_NEW_TR_32_BIT_ADDR_GEN;
---------------------------------------------
STORE_NEW_TR_24_BIT_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-----
-------------------------------------
STORE_NEW_TR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
new_tr <= '0';
elsif( (load_axi_data_to_spi_clk = '1')
or (load_wr_hpm = '1')
-- or (load_wr_en = '1')
) then
new_tr <= '1';
elsif(SR_5_Tx_Empty_int = '1') then --(wrap_around = '0' and qspi_cntrl_ns = IDLE)then
new_tr <= '0';
end if;
end if;
end process STORE_NEW_TR_P;
-------------------------------------
end generate STORE_NEW_TR_24_BIT_ADDR_GEN;
-------------------------------------------------------------------------------
-- STORE_INITAL_ADDR_P: The address frm AXI should be stored in the SPI environment
-- as the address generation logic will work in this domain.
STORE_24_BIT_SPI_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-----
-------------------------------------
STORE_INITAL_ADDR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
spi_addr <= (others => '0');
elsif(load_axi_data_to_spi_clk = '1')then
spi_addr <= "00000000" & Transmit_Addr_to_spi_clk;-- (31 downto 8);
elsif(load_wrap_addr = '1')then -- and (type_of_burst_to_spi = '1') then
spi_addr <= "00000000" & spi_addr_wrap;
end if;
end if;
end process STORE_INITAL_ADDR_P;
-------------------------------------
end generate STORE_24_BIT_SPI_ADDR_GEN;
-----------------------------------------
STORE_32_BIT_SPI_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate -- 3/30/2013
begin
-----
----------------------------------
STORE_INITAL_ADDR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
spi_addr <= (others => '0');
elsif(load_axi_data_to_spi_clk = '1')then
spi_addr <= Transmit_Addr_to_spi_clk;-- (31 downto 0);
elsif(load_wrap_addr = '1')then -- and (type_of_burst_to_spi = '1') then
spi_addr <= spi_addr_wrap;
end if;
end if;
end process STORE_INITAL_ADDR_P;
----------------------------------
end generate STORE_32_BIT_SPI_ADDR_GEN;
---------------------------------------
-------------------------------------------------------------------------------
-- below signals will store the length of AXI transaction in the SPI domain
axi_len_two <= not(or_Reduce(axi_length_to_spi_clk(3 downto 1))) and
axi_length_to_spi_clk(0);
axi_len_four <= not(or_Reduce(axi_length_to_spi_clk(3 downto 2))) and
and_reduce(axi_length_to_spi_clk(1 downto 0));
axi_len_eight <= not(axi_length_to_spi_clk(3)) and
and_Reduce(axi_length_to_spi_clk(2 downto 0));
axi_len_sixteen <= and_reduce(axi_length_to_spi_clk(3 downto 0));
-------------------------------------------------------------------------------
-- below signals store the WRAP information in SPI domain
wrap_two <= '1' when (type_of_burst_to_spi_clk = '1' and
axi_len_two = '1')
else
'0';
wrap_four <= '1' when (type_of_burst_to_spi_clk = '1' and
axi_len_four = '1')
else
'0';
wrap_eight <= '1' when (type_of_burst_to_spi_clk = '1' and
axi_len_eight = '1')
else
'0';
wrap_sixteen <= '1' when (type_of_burst_to_spi_clk = '1' and
axi_len_sixteen = '1')
else
'0';
-------------------------------------------------------------------------------
-- SPI_ADDRESS_REG: This process stores the initial address coming from the AXI in
-- two registers. one register will store this address till the
-- transaction ends, while other will be updated based upon type of
-- transaction as well as at the end of each SPI transfer. this is
-- used for internal use only.
SPI_24_BIT_ADDRESS_REG_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-----
SPI_ADDRESS_REG : process(EXT_SPI_CLK) is
--variable xfer : std_logic_vector(2 downto 0);
begin
-- xfer := four_byte_xfer_to_spi_clk & two_byte_xfer_to_spi_clk & one_byte_xfer_to_spi_clk;
if (EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if (Rst_to_spi = RESET_ACTIVE) then
spi_addr_i <= (others => '0');
spi_addr_int <= (others => '0');
else
if (load_cmd_to_spi_clk = '1') then
spi_addr_i <= Transmit_Addr_to_spi_clk(23 downto 0);
spi_addr_int <= Transmit_Addr_to_spi_clk(23 downto 0);
-- below is address generation for the WRAP mode
elsif (type_of_burst_to_spi_clk = '1') and
(SPIXfer_done_int_pulse_d2 = '1') and
(cmd_addr_sent = '1') then
spi_addr_int(23 downto 0) <= spi_addr_int(23 downto 0) + '1';
case size_length_cntr is
when "00" => -- 8-bit access
if(wrap_two = '1') then
spi_addr_i(23 downto 1) <= spi_addr_i(23 downto 1);
spi_addr_i(0) <= not (spi_addr_i(0));
elsif(wrap_four = '1') then -- the byte address increment will take 2 address bits
spi_addr_i(23 downto 2) <= spi_addr_i(23 downto 2);
spi_addr_i(1 downto 0) <= spi_addr_i(1 downto 0) + "01";
elsif(wrap_eight = '1') then -- the byte address increment will take 3 address bits
spi_addr_i(23 downto 3) <= spi_addr_i(23 downto 3);
spi_addr_i(2 downto 0) <= spi_addr_i(2 downto 0) + "001";
elsif(wrap_sixteen = '1') then -- the byte address increment will take 4 address bits for 16's wrap
spi_addr_i(23 downto 4) <= spi_addr_i(23 downto 4);
spi_addr_i(3 downto 0) <= spi_addr_i(3 downto 0) + "0001";
else
spi_addr_i <= spi_addr_i + "0001";
end if;
when "01" => -- 16-bit access
if(wrap_two = '1') then
spi_addr_i(23 downto 2) <= spi_addr_i(23 downto 2);
spi_addr_i(1 downto 0) <= spi_addr_i(1 downto 0) + "10";
elsif(wrap_four = '1') then
spi_addr_i(23 downto 3) <= spi_addr_i(23 downto 3);
spi_addr_i(2 downto 0) <= spi_addr_i(2 downto 0) + "010";
elsif(wrap_eight = '1') then
spi_addr_i(23 downto 4) <= spi_addr_i(23 downto 4);
spi_addr_i(3 downto 0) <= spi_addr_i(3 downto 0) + "0010";
elsif(wrap_sixteen = '1') then
spi_addr_i(23 downto 5) <= spi_addr_i(23 downto 5);
spi_addr_i(4 downto 0) <= spi_addr_i(4 downto 0) + "00010";
else
spi_addr_i <= spi_addr_i + "0010";
end if;
when "10" => -- 32-bit access
if(wrap_two = '1') then
spi_addr_i(23 downto 3) <= spi_addr_i(23 downto 3);
spi_addr_i(2 downto 0) <=spi_addr_i(2 downto 0) + "100";
elsif(wrap_four = '1') then
spi_addr_i(23 downto 4) <= spi_addr_i(23 downto 4);
spi_addr_i(3 downto 0) <=spi_addr_i(3 downto 0) + "0100";
elsif(wrap_eight = '1') then
spi_addr_i(23 downto 5) <= spi_addr_i(23 downto 5);
spi_addr_i(4 downto 0) <=spi_addr_i(4 downto 0) + "00100";
elsif(wrap_sixteen = '1') then
spi_addr_i(23 downto 6) <= spi_addr_i(23 downto 6);
spi_addr_i(5 downto 0) <=spi_addr_i(5 downto 0) + "000100";
else
spi_addr_i <= spi_addr_i + "0100";
end if;
-- coverage off
when others =>
spi_addr_i <= spi_addr_i;
-- coverage on
end case;
-- below is address generation for the INCR mode
elsif (type_of_burst_to_spi_clk = '0') and
(SPIXfer_done_int_pulse_d2 = '1') and
(cmd_addr_sent = '1') then
spi_addr_i(23 downto 0) <= spi_addr_i(23 downto 0) + '1';
end if;
end if;
end if;
end process SPI_ADDRESS_REG;
----------------------------------
end generate SPI_24_BIT_ADDRESS_REG_GEN;
----------------------------------------
SPI_32_BIT_ADDRESS_REG_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-----
SPI_ADDRESS_REG : process(EXT_SPI_CLK) is
--variable xfer : std_logic_vector(2 downto 0);
begin
-- xfer := four_byte_xfer_to_spi_clk & two_byte_xfer_to_spi_clk & one_byte_xfer_to_spi_clk;
if (EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if (Rst_to_spi = RESET_ACTIVE) then
spi_addr_i <= (others => '0');
spi_addr_int <= (others => '0');
else
if (load_cmd_to_spi_clk = '1') then
spi_addr_i <= Transmit_Addr_to_spi_clk(31 downto 0);
spi_addr_int <= Transmit_Addr_to_spi_clk(31 downto 0);
-- below is address generation for the WRAP mode
elsif (type_of_burst_to_spi_clk = '1') and
(SPIXfer_done_int_pulse_d2 = '1') and
(cmd_addr_sent = '1') then
spi_addr_int(31 downto 0) <= spi_addr_int(31 downto 0) + '1';
case size_length_cntr is
when "00" => -- 8-bit access
if(wrap_two = '1') then
spi_addr_i(31 downto 1) <= spi_addr_i(31 downto 1);
spi_addr_i(0) <= not (spi_addr_i(0));
elsif(wrap_four = '1') then -- the byte address increment will take 2 address bits
spi_addr_i(31 downto 2) <= spi_addr_i(31 downto 2);
spi_addr_i(1 downto 0) <= spi_addr_i(1 downto 0) + "01";
elsif(wrap_eight = '1') then -- the byte address increment will take 3 address bits
spi_addr_i(31 downto 3) <= spi_addr_i(31 downto 3);
spi_addr_i(2 downto 0) <= spi_addr_i(2 downto 0) + "001";
elsif(wrap_sixteen = '1') then -- the byte address increment will take 4 address bits for 16's wrap
spi_addr_i(31 downto 4) <= spi_addr_i(31 downto 4);
spi_addr_i(3 downto 0) <= spi_addr_i(3 downto 0) + "0001";
else
spi_addr_i <= spi_addr_i + "0001";
end if;
when "01" => -- 16-bit access
if(wrap_two = '1') then
spi_addr_i(31 downto 2) <= spi_addr_i(31 downto 2);
spi_addr_i(1 downto 0) <= spi_addr_i(1 downto 0) + "10";
elsif(wrap_four = '1') then
spi_addr_i(31 downto 3) <= spi_addr_i(31 downto 3);
spi_addr_i(2 downto 0) <= spi_addr_i(2 downto 0) + "010";
elsif(wrap_eight = '1') then
spi_addr_i(31 downto 4) <= spi_addr_i(31 downto 4);
spi_addr_i(3 downto 0) <= spi_addr_i(3 downto 0) + "0010";
elsif(wrap_sixteen = '1') then
spi_addr_i(31 downto 5) <= spi_addr_i(31 downto 5);
spi_addr_i(4 downto 0) <= spi_addr_i(4 downto 0) + "00010";
else
spi_addr_i <= spi_addr_i + "0010";
end if;
when "10" => -- 32-bit access
if(wrap_two = '1') then
spi_addr_i(31 downto 3) <= spi_addr_i(31 downto 3);
spi_addr_i(2 downto 0) <=spi_addr_i(2 downto 0) + "100";
elsif(wrap_four = '1') then
spi_addr_i(31 downto 4) <= spi_addr_i(31 downto 4);
spi_addr_i(3 downto 0) <=spi_addr_i(3 downto 0) + "0100";
elsif(wrap_eight = '1') then
spi_addr_i(31 downto 5) <= spi_addr_i(31 downto 5);
spi_addr_i(4 downto 0) <=spi_addr_i(4 downto 0) + "00100";
elsif(wrap_sixteen = '1') then
spi_addr_i(31 downto 6) <= spi_addr_i(31 downto 6);
spi_addr_i(5 downto 0) <=spi_addr_i(5 downto 0) + "000100";
else
spi_addr_i <= spi_addr_i + "0100";
end if;
-- coverage off
when others =>
spi_addr_i <= spi_addr_i;
-- coverage on
end case;
-- below is address generation for the INCR mode
elsif (type_of_burst_to_spi_clk = '0') and
(SPIXfer_done_int_pulse_d2 = '1') and
(cmd_addr_sent = '1') then
spi_addr_i(31 downto 0) <= spi_addr_i(31 downto 0) + '1';
end if;
end if;
end if;
end process SPI_ADDRESS_REG;
end generate SPI_32_BIT_ADDRESS_REG_GEN;
----------------------------------------
-- SPI_WRAP_ADDR_REG: this is separate process used for WRAP address generation
SPI_24_WRAP_ADDR_REG_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
SPI_WRAP_ADDR_REG : process(EXT_SPI_CLK) is
--variable xfer : std_logic_vector(2 downto 0);
begin
-- xfer := four_byte_xfer_to_spi_clk & two_byte_xfer_to_spi_clk & one_byte_xfer_to_spi_clk;
if (EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if (Rst_to_spi = RESET_ACTIVE) then
spi_addr_wrap <= (others => '0');
else
if (load_cmd_to_spi_clk = '1') then
spi_addr_wrap <= Transmit_Addr_to_spi_clk(23 downto 0);
elsif(wrap_ack_1 = '1') then
spi_addr_wrap <= spi_addr_wrap_1;
-- below is address generation for the WRAP mode
elsif (type_of_burst_to_spi_clk = '1') and
(store_date_in_drr_fifo = '1') and
(cmd_addr_sent = '1') then
case size_length_cntr_fixed is
when "00" => -- 8-bit access
if(wrap_two = '1') then
spi_addr_wrap(23 downto 1) <= spi_addr_wrap(23 downto 1);
spi_addr_wrap(0) <= not (spi_addr_wrap(0));
elsif(wrap_four = '1') then -- the byte address increment will take 2 address bits
spi_addr_wrap(23 downto 2) <= spi_addr_wrap(23 downto 2);
spi_addr_wrap(1 downto 0) <= spi_addr_wrap(1 downto 0) + "01";
elsif(wrap_eight = '1') then -- the byte address increment will take 3 address bits
spi_addr_wrap(23 downto 3) <= spi_addr_wrap(23 downto 3);
spi_addr_wrap(2 downto 0) <= spi_addr_wrap(2 downto 0) + "001";
elsif(wrap_sixteen = '1') then -- the byte address increment will take 4 address bits for 16's wrap
spi_addr_wrap(23 downto 4) <= spi_addr_wrap(23 downto 4);
spi_addr_wrap(3 downto 0) <= spi_addr_wrap(3 downto 0) + "0001";
else
spi_addr_wrap <= spi_addr_wrap + "0001";
end if;
when "01" => -- 16-bit access
if(wrap_two = '1') then
spi_addr_wrap(23 downto 2) <= spi_addr_wrap(23 downto 2);
spi_addr_wrap(1 downto 0) <= spi_addr_wrap(1 downto 0) + "10";
elsif(wrap_four = '1') then
spi_addr_wrap(23 downto 3) <= spi_addr_wrap(23 downto 3);
spi_addr_wrap(2 downto 0) <= spi_addr_wrap(2 downto 0) + "010";
elsif(wrap_eight = '1') then
spi_addr_wrap(23 downto 4) <= spi_addr_wrap(23 downto 4);
spi_addr_wrap(3 downto 0) <= spi_addr_wrap(3 downto 0) + "0010";
elsif(wrap_sixteen = '1') then
spi_addr_wrap(23 downto 5) <= spi_addr_wrap(23 downto 5);
spi_addr_wrap(4 downto 0) <= spi_addr_wrap(4 downto 0) + "00010";
else
spi_addr_wrap <= spi_addr_wrap + "0010";
end if;
when "10" => -- 32-bit access
if(wrap_two = '1') then
spi_addr_wrap(23 downto 3) <= spi_addr_wrap(23 downto 3);
spi_addr_wrap(2 downto 0) <=spi_addr_wrap(2 downto 0) + "100";
elsif(wrap_four = '1') then
spi_addr_wrap(23 downto 4) <= spi_addr_wrap(23 downto 4);
spi_addr_wrap(3 downto 0) <=spi_addr_wrap(3 downto 0) + "0100";
elsif(wrap_eight = '1') then
spi_addr_wrap(23 downto 5) <= spi_addr_wrap(23 downto 5);
spi_addr_wrap(4 downto 0) <=spi_addr_wrap(4 downto 0) + "00100";
elsif(wrap_sixteen = '1') then
spi_addr_wrap(23 downto 6) <= spi_addr_wrap(23 downto 6);
spi_addr_wrap(5 downto 0) <=spi_addr_wrap(5 downto 0) + "000100";
else
spi_addr_wrap <= spi_addr_wrap + "0100";
end if;
-- coverage off
when others =>
spi_addr_wrap <= spi_addr_wrap;
-- coverage on
end case;
end if;
end if;
end if;
end process SPI_WRAP_ADDR_REG;
end generate SPI_24_WRAP_ADDR_REG_GEN;
--------------------------------------
SPI_32_WRAP_ADDR_REG_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
SPI_WRAP_ADDR_REG : process(EXT_SPI_CLK) is
--variable xfer : std_logic_vector(2 downto 0);
begin
-- xfer := four_byte_xfer_to_spi_clk & two_byte_xfer_to_spi_clk & one_byte_xfer_to_spi_clk;
if (EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if (Rst_to_spi = RESET_ACTIVE) then
spi_addr_wrap <= (others => '0');
else
if (load_cmd_to_spi_clk = '1') then
spi_addr_wrap <= Transmit_Addr_to_spi_clk(31 downto 0);
elsif(wrap_ack_1 = '1') then
spi_addr_wrap <= spi_addr_wrap_1;
-- below is address generation for the WRAP mode
elsif (type_of_burst_to_spi_clk = '1') and
(store_date_in_drr_fifo = '1') and
(cmd_addr_sent = '1') then
case size_length_cntr_fixed is
when "00" => -- 8-bit access
if(wrap_two = '1') then
spi_addr_wrap(31 downto 1) <= spi_addr_wrap(31 downto 1);
spi_addr_wrap(0) <= not (spi_addr_wrap(0));
elsif(wrap_four = '1') then -- the byte address increment will take 2 address bits
spi_addr_wrap(31 downto 2) <= spi_addr_wrap(31 downto 2);
spi_addr_wrap(1 downto 0) <= spi_addr_wrap(1 downto 0) + "01";
elsif(wrap_eight = '1') then -- the byte address increment will take 3 address bits
spi_addr_wrap(31 downto 3) <= spi_addr_wrap(31 downto 3);
spi_addr_wrap(2 downto 0) <= spi_addr_wrap(2 downto 0) + "001";
elsif(wrap_sixteen = '1') then -- the byte address increment will take 4 address bits for 16's wrap
spi_addr_wrap(31 downto 4) <= spi_addr_wrap(31 downto 4);
spi_addr_wrap(3 downto 0) <= spi_addr_wrap(3 downto 0) + "0001";
else
spi_addr_wrap <= spi_addr_wrap + "0001";
end if;
when "01" => -- 16-bit access
if(wrap_two = '1') then
spi_addr_wrap(31 downto 2) <= spi_addr_wrap(31 downto 2);
spi_addr_wrap(1 downto 0) <= spi_addr_wrap(1 downto 0) + "10";
elsif(wrap_four = '1') then
spi_addr_wrap(31 downto 3) <= spi_addr_wrap(31 downto 3);
spi_addr_wrap(2 downto 0) <= spi_addr_wrap(2 downto 0) + "010";
elsif(wrap_eight = '1') then
spi_addr_wrap(31 downto 4) <= spi_addr_wrap(31 downto 4);
spi_addr_wrap(3 downto 0) <= spi_addr_wrap(3 downto 0) + "0010";
elsif(wrap_sixteen = '1') then
spi_addr_wrap(31 downto 5) <= spi_addr_wrap(31 downto 5);
spi_addr_wrap(4 downto 0) <= spi_addr_wrap(4 downto 0) + "00010";
else
spi_addr_wrap <= spi_addr_wrap + "0010";
end if;
when "10" => -- 32-bit access
if(wrap_two = '1') then
spi_addr_wrap(31 downto 3) <= spi_addr_wrap(31 downto 3);
spi_addr_wrap(2 downto 0) <=spi_addr_wrap(2 downto 0) + "100";
elsif(wrap_four = '1') then
spi_addr_wrap(31 downto 4) <= spi_addr_wrap(31 downto 4);
spi_addr_wrap(3 downto 0) <=spi_addr_wrap(3 downto 0) + "0100";
elsif(wrap_eight = '1') then
spi_addr_wrap(31 downto 5) <= spi_addr_wrap(31 downto 5);
spi_addr_wrap(4 downto 0) <=spi_addr_wrap(4 downto 0) + "00100";
elsif(wrap_sixteen = '1') then
spi_addr_wrap(31 downto 6) <= spi_addr_wrap(31 downto 6);
spi_addr_wrap(5 downto 0) <=spi_addr_wrap(5 downto 0) + "000100";
else
spi_addr_wrap <= spi_addr_wrap + "0100";
end if;
-- coverage off
when others =>
spi_addr_wrap <= spi_addr_wrap;
-- coverage on
end case;
end if;
end if;
end if;
end process SPI_WRAP_ADDR_REG;
----------------------------------
end generate SPI_32_WRAP_ADDR_REG_GEN;
--------------------------------------
-------------------------------------------------------------------------------
-- SPI_WRAP_ADDR_REG: this is separate process used for WRAP address generation
LOAD_SPI_WRAP_ADDR_REG : process(EXT_SPI_CLK) is
begin
-----
if (EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if (Rst_to_spi = RESET_ACTIVE) then
spi_addr_wrap_1 <= (others => '0');
else
if (wrap_around = '1') then
-- below is address generation for the WRAP mode
case size_length_cntr_fixed is
when "00" => -- 8-bit access
if(wrap_two = '1') then
spi_addr_wrap_1 <= spi_addr_wrap + '1';
elsif(wrap_four = '1') then -- the byte address increment will take 2 address bits
spi_addr_wrap_1 <= spi_addr_wrap + "01";
elsif(wrap_eight = '1') then -- the byte address increment will take 3 address bits
spi_addr_wrap_1 <= spi_addr_wrap + "001";
elsif(wrap_sixteen = '1') then -- the byte address increment will take 4 address bits for 16's wrap
spi_addr_wrap_1 <= spi_addr_wrap + "0001";
else
spi_addr_wrap_1 <= spi_addr_wrap + "0001";
end if;
when "01" => -- 16-bit access
if(wrap_two = '1') then
spi_addr_wrap_1 <= spi_addr_wrap + "10";
elsif(wrap_four = '1') then
spi_addr_wrap_1 <= spi_addr_wrap + "010";
elsif(wrap_eight = '1') then
spi_addr_wrap_1 <= spi_addr_wrap + "0010";
elsif(wrap_sixteen = '1') then
spi_addr_wrap_1 <= spi_addr_wrap + "00010";
else
spi_addr_wrap_1 <= spi_addr_wrap + "0010";
end if;
when "10" => -- 32-bit access
if(wrap_two = '1') then
spi_addr_wrap_1 <=spi_addr_wrap + "100";
elsif(wrap_four = '1') then
spi_addr_wrap_1 <=spi_addr_wrap + "0100";
elsif(wrap_eight = '1') then
spi_addr_wrap_1 <=spi_addr_wrap + "00100";
elsif(wrap_sixteen = '1') then
spi_addr_wrap_1 <=spi_addr_wrap + "000100";
else
spi_addr_wrap_1 <=spi_addr_wrap + "0100";
end if;
-- coverage off
when others =>
spi_addr_wrap_1 <= spi_addr_wrap;
-- coverage on
end case;
end if;
end if;
end if;
end process LOAD_SPI_WRAP_ADDR_REG;
-------------------------------------------------------------------------------
-- WRAP_AROUND_GEN_P : WRAP boundary detection logic
WRAP_AROUND_GEN_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if( (Rst_to_spi = '1')
or(rst_wrap_around = '1')
) then
wrap_around <= '0';
elsif(type_of_burst_to_spi_clk = '1')then
case size_length_cntr_fixed is
when "00" => -- byte transfer
if(wrap_two = '1') and
(spi_addr_wrap(1) = '1') and
(store_date_in_drr_fifo = '1')then -- then
wrap_around <= --spi_addr_wrap(1) and
not SR_5_Tx_Empty;
elsif(wrap_four = '1') and
(spi_addr_wrap(1 downto 0) = "11") and
(store_date_in_drr_fifo = '1')then -- then -- the byte address increment will take 2 address bits
wrap_around <= --and_reduce(spi_addr_wrap(1 downto 0)) and
not SR_5_Tx_Empty;
elsif(wrap_eight = '1') and
(spi_addr_wrap(2 downto 0) = "111") and
(store_date_in_drr_fifo = '1')then -- then -- the byte address increment will take 3 address bits
wrap_around <= --and_reduce(spi_addr_wrap(2 downto 0)) and
not SR_5_Tx_Empty;
elsif(wrap_sixteen = '1') and
(spi_addr_wrap(3 downto 0) = "1111") and
(store_date_in_drr_fifo = '1')then -- the byte address increment will take 4 address bits for 16's wrap
wrap_around <= --and_reduce(spi_addr_wrap(3 downto 0)) and
not SR_5_Tx_Empty;
else
wrap_around <= '0';
end if;
when "01" => -- 16-bit access
if(wrap_two = '1') then -- and (spi_addr_wrap(1 downto 0) = "10") and (store_date_in_drr_fifo = '1')then
wrap_around <= not SR_5_Tx_Empty and
store_date_in_drr_fifo and
wrp_addr_len_2_siz_16;
elsif(wrap_four = '1') then -- and (spi_addr_wrap(2 downto 0) = "110") and (store_date_in_drr_fifo = '1')then
wrap_around <= not SR_5_Tx_Empty and
store_date_in_drr_fifo and
wrp_addr_len_4_siz_16;
elsif(wrap_eight = '1') then -- and (spi_addr_wrap(3 downto 0) = "1110") and (store_date_in_drr_fifo = '1')then
wrap_around <= not SR_5_Tx_Empty and
store_date_in_drr_fifo and
wrp_addr_len_8_siz_16;
elsif(wrap_sixteen = '1') then -- and (spi_addr_wrap(4 downto 0) = "11110") and (store_date_in_drr_fifo = '1') then
wrap_around <= not SR_5_Tx_Empty and
store_date_in_drr_fifo and
wrp_addr_len_16_siz_16;
else
wrap_around <= '0';
end if;
when "10" => -- 32-bit access
if(wrap_two = '1') then -- and (spi_addr_wrap(2 downto 0) = "100") and (store_date_in_drr_fifo = '1') then
wrap_around <= not SR_5_Tx_Empty and
store_date_in_drr_fifo and
wrp_addr_len_2_siz_32;
elsif(wrap_four = '1') then -- and (spi_addr_wrap(3 downto 0) = "1100") and (store_date_in_drr_fifo = '1') then
wrap_around <= not SR_5_Tx_Empty and
store_date_in_drr_fifo and
wrp_addr_len_4_siz_32;
elsif(wrap_eight = '1') then -- and (spi_addr_wrap(4 downto 0) = "11100") and (store_date_in_drr_fifo = '1') then
wrap_around <= not SR_5_Tx_Empty and
store_date_in_drr_fifo and
wrp_addr_len_8_siz_32;
elsif(wrap_sixteen = '1') then --and (spi_addr_wrap(5 downto 0) = "111100") and (store_date_in_drr_fifo = '1') then
wrap_around <= not SR_5_Tx_Empty and
store_date_in_drr_fifo and
wrp_addr_len_16_siz_32;
else
wrap_around <= '0';
end if;
-- coverage off
when others => wrap_around <= wrap_around;
-- coverage on
end case;
end if;
end if;
end process WRAP_AROUND_GEN_P;
-------------------------------------------------------------------------------
load_wrap_addr <= wrap_around;
wrp_addr_len_16_siz_32 <= '1' when (spi_addr_wrap(5 downto 0) = "111100") else '0';
wrp_addr_len_8_siz_32 <= '1' when (spi_addr_wrap(4 downto 0) = "11100") else '0';
wrp_addr_len_4_siz_32 <= '1' when (spi_addr_wrap(3 downto 0) = "1100") else '0';
wrp_addr_len_2_siz_32 <= '1' when (spi_addr_wrap(2 downto 0) = "100") else '0';
-----------------------------------------------------------------------------------
wrp_addr_len_16_siz_16 <= '1' when (spi_addr_wrap(4 downto 0) = "11110") else '0';
wrp_addr_len_8_siz_16 <= '1' when (spi_addr_wrap(3 downto 0) = "1110") else '0';
wrp_addr_len_4_siz_16 <= '1' when (spi_addr_wrap(2 downto 0) = "110") else '0';
wrp_addr_len_2_siz_16 <= '1' when (spi_addr_wrap(1 downto 0) = "10") else '0';
-----------------------------------------------------------------------------------
-- LEN_CNTR_P: This is data length counter. this counter will start decrementing
-- only when the first 4 bytes are transferred from SPI.
LEN_CNTR_24_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-----
LEN_CNTR_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
length_cntr <= (others => '0');
elsif(load_wr_hpm='1') then
length_cntr <= "00000011";
elsif(load_cmd_to_spi_clk = '1')then
length_cntr <= dtr_length_to_spi_clk;
elsif((SPIXfer_done_int = '1') and
(((size_length_cntr = "00") and
(cmd_addr_sent = '1')
)or
(hpm_under_process_d1 = '1'))
)then
length_cntr <= length_cntr - "00000001";
end if;
end if;
end process LEN_CNTR_P;
-----------------------
end generate LEN_CNTR_24_BIT_GEN;
---------------------------------
LEN_CNTR_32_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-----
LEN_CNTR_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
length_cntr <= (others => '0');
elsif(load_wr_hpm='1') then
length_cntr <= "00000000";
elsif(load_cmd_to_spi_clk = '1')then
length_cntr <= dtr_length_to_spi_clk;
elsif((SPIXfer_done_int = '1') and
(((size_length_cntr = "00") and
(cmd_addr_sent = '1')
)or
(hpm_under_process_d1 = '1') or (wr_en_under_process_d1 = '1'))
)then
length_cntr <= length_cntr - "00000001";
end if;
end if;
end process LEN_CNTR_P;
-----------------------
end generate LEN_CNTR_32_BIT_GEN;
---------------------------------
-------------------------------------------------------------------------------
SR_5_TX_EMPTY_32_BIT_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
SR_5_Tx_Empty_int<= (not(or_reduce(length_cntr)) and
store_date_in_drr_fifo and
cmd_addr_sent)
or
(-- (hpm_under_process_d1 or wr_en_under_process_d1) and
(hpm_under_process or wr_en_under_process) and
not(or_reduce(length_cntr)) and
SPIXfer_done_int_pulse);
-- LEN_CNTR_P: This is data length counter. this counter will start decrementing
-- only when the first 4 bytesfor 24 bit addressing and 5 bytes for 32 bit addressing mode are transferred from SPI.
SR_5_TX_EMPTY_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
SR_5_Tx_Empty <= '1';
elsif(load_cmd_to_spi_clk = '1') or (load_wr_hpm = '1') or (load_wr_en = '1') then
SR_5_Tx_Empty <= '0';
elsif(SR_5_Tx_Empty_int = '1')then
SR_5_Tx_Empty <= '1';
end if;
end if;
end process SR_5_TX_EMPTY_P;
end generate SR_5_TX_EMPTY_32_BIT_ADDR_GEN;
-------------------------------------------------------------------------------
SR_5_TX_EMPTY_24_BIT_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
SR_5_Tx_Empty_int<= (not(or_reduce(length_cntr)) and
store_date_in_drr_fifo and
cmd_addr_sent)
or
(-- (hpm_under_process_d1 or wr_en_under_process_d1) and
(hpm_under_process
--or wr_en_under_process
)
and
not(
or_reduce(length_cntr))
and
SPIXfer_done_int_pulse
);
-- LEN_CNTR_P: This is data length counter. this counter will start decrementing
-- only when the first 4 bytesfor 24 bit addressing and 5 bytes for 32 bit addressing mode are transferred from SPI.
SR_5_TX_EMPTY_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
SR_5_Tx_Empty <= '1';
elsif(load_cmd_to_spi_clk = '1') or (load_wr_hpm = '1')
--or (load_wr_en = '1')
then
SR_5_Tx_Empty <= '0';
elsif(SR_5_Tx_Empty_int = '1')then
SR_5_Tx_Empty <= '1';
end if;
end if;
end process SR_5_TX_EMPTY_P;
end generate SR_5_TX_EMPTY_24_BIT_ADDR_GEN;
-------------------------------------------
DELAY_FIFO_EMPTY_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
SR_5_Tx_Empty_d1 <= '1';
SR_5_Tx_Empty_d2 <= '1';
else
SR_5_Tx_Empty_d1 <= SR_5_Tx_Empty;
SR_5_Tx_Empty_d2 <= SR_5_Tx_Empty_d1;
end if;
end if;
end process DELAY_FIFO_EMPTY_P;
-------------------------------------------------------------------------------
last_bt_one_data <= not(or_reduce(length_cntr(7 downto 1))) and length_cntr(0);
-------------------------------------------------------------------------------
SIZE_CNTR_LD_SPI_CLK_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
size_length_cntr_fixed <= (others => '0');
size_length_cntr <= (others => '0');
elsif(
(pr_state_idle = '1') or ((SPIXfer_done_int = '1') and
(size_length_cntr = "00"))
)then
--if(one_byte_xfer_to_spi_clk = '1' )then
-- size_length_cntr_fixed <= "00";
-- size_length_cntr <= "00"; -- 1 byte
--els
if(two_byte_xfer_to_spi_clk = '1')then
size_length_cntr_fixed <= "01";
size_length_cntr <= "01"; -- half word
elsif(four_byte_xfer_to_spi_clk = '1') then
size_length_cntr_fixed <= "10";
size_length_cntr <= "11"; -- word
else
size_length_cntr_fixed <= "00";
size_length_cntr <= "00"; -- other and one_byte_xfer_to_spi_clk = '1' is merged here
end if;
elsif(SPIXfer_done_int = '1') and
(one_byte_xfer_to_spi_clk = '0')and
(cmd_addr_sent = '1') then -- (size_length_cntr /= "00") then
size_length_cntr <= size_length_cntr - "01";
end if;
end if;
end process SIZE_CNTR_LD_SPI_CLK_P;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
store_date_in_drr_fifo <= not(or_reduce(size_length_cntr)) and
SPIXfer_done_int and
cmd_addr_sent;
-------------------------------------------------------------------------------
STORE_STROBE_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
store_date_in_drr_fifo_d1 <= '0';
store_date_in_drr_fifo_d2 <= '0';
store_date_in_drr_fifo_d3 <= '0';
else
store_date_in_drr_fifo_d1 <= store_date_in_drr_fifo;
store_date_in_drr_fifo_d2 <= store_date_in_drr_fifo_d1;
store_date_in_drr_fifo_d3 <= store_date_in_drr_fifo_d2;
end if;
end if;
end process STORE_STROBE_SPI_CLK_P;
-------------------------------------------------------------------------------
MD_12_WR_EN_TO_FIFO_GEN: if C_SPI_MODE = 1 or C_SPI_MODE = 2 generate
begin
-----
--------------------------------------------------------------------
WB_FIFO_WR_EN_GEN: if C_SPI_MEMORY = 1 generate
begin
-----
store_date_in_drr_fifo_en <= store_date_in_drr_fifo_d3;
end generate WB_FIFO_WR_EN_GEN;
--------------------------------------------------------------------
NM_FIFO_WR_EN_GEN: if C_SPI_MEMORY = 2 generate
begin
-----
STORE_DATA_24_BIT_ADDRESS_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
store_date_in_drr_fifo_en <= store_date_in_drr_fifo_d3;
end generate STORE_DATA_24_BIT_ADDRESS_GEN;
-------------------------------------------
STORE_DATA_32_BIT_ADDRESS_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
store_date_in_drr_fifo_en <= store_date_in_drr_fifo_d3;
end generate STORE_DATA_32_BIT_ADDRESS_GEN;
-------------------------------------------
end generate NM_FIFO_WR_EN_GEN;
--------------------------------------------------------------------
SP_FIFO_WR_EN_GEN: if C_SPI_MEMORY = 3 generate
begin
-----
STORE_DATA_24_BIT_ADDRESS_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
store_date_in_drr_fifo_en <= store_date_in_drr_fifo_d3;
end generate STORE_DATA_24_BIT_ADDRESS_GEN;
-------------------------------------------
STORE_DATA_32_BIT_ADDRESS_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
store_date_in_drr_fifo_en <= store_date_in_drr_fifo_d3;
end generate STORE_DATA_32_BIT_ADDRESS_GEN;
-------------------------------------------
end generate SP_FIFO_WR_EN_GEN;
--------------------------------------------------------------------
end generate MD_12_WR_EN_TO_FIFO_GEN;
MD_0_WR_EN_TO_FIFO_GEN: if C_SPI_MODE = 0 generate
begin
-----
WB_FIFO_WR_EN_GEN: if C_SPI_MEMORY = 1 generate
begin
-----
store_date_in_drr_fifo_en <= store_date_in_drr_fifo;
end generate WB_FIFO_WR_EN_GEN;
NM_FIFO_WR_EN_GEN: if C_SPI_MEMORY = 2 generate
begin
-----
store_date_in_drr_fifo_en <= store_date_in_drr_fifo;
end generate NM_FIFO_WR_EN_GEN;
SP_FIFO_WR_EN_GEN: if C_SPI_MEMORY = 3 generate
begin
-----
store_date_in_drr_fifo_en <= store_date_in_drr_fifo;
end generate SP_FIFO_WR_EN_GEN;
end generate MD_0_WR_EN_TO_FIFO_GEN;
-------------------------------------------------------------------------------
SHIFT_TX_REG_24_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
SHIFT_TX_REG_SPI_CLK_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1')then
Tx_Data_d1 <= (others => '0');
elsif(load_wr_hpm = '1') then
Tx_Data_d1(31 downto 24) <= WB_wr_hpm_CMD;
Tx_Data_d1(23 downto 0) <= (others => '0');
elsif(load_axi_data_to_spi_clk = '1')then
Tx_Data_d1 <= SPI_cmd & Transmit_Addr_to_spi_clk; -- & SPI_cmd;-- (31 downto 8);
elsif(wrap_around = '1') then
Tx_Data_d1 <= SPI_cmd & spi_addr_wrap;--spi_addr_i & SPI_cmd;
elsif(SPIXfer_done_int = '1')then
Tx_Data_d1 <= --"11111111" & -- Tx_Data_d1(7 downto 0) &
-- --Tx_Data_d1(31 downto 8);
-- Tx_Data_d1(31 downto 8);
Tx_Data_d1(23 downto 0) & "11111111";
end if;
end if;
end process SHIFT_TX_REG_SPI_CLK_P;
Transmit_Data <= Tx_Data_d1(31 downto 24);
end generate SHIFT_TX_REG_24_BIT_GEN;
-------------------------------------------------------
SHIFT_TX_REG_32_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
SHIFT_TX_REG_SPI_CLK_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1')then
Tx_Data_d1 <= (others => '0');
--last_7_addr_bits <= (others => '0');
elsif(load_wr_en = '1') then
Tx_Data_d1(31 downto 24) <= "00000110"; ---nm_wr_en_CMD;
Tx_Data_d1(23 downto 0) <= (others => '0');
elsif(load_wr_hpm = '1')then
Tx_Data_d1(31 downto 24) <= "10110111"; ---nm_4byte_addr_en_CMD;
Tx_Data_d1(23 downto 0) <= (others => '0');
elsif(load_axi_data_to_spi_clk = '1')then
Tx_Data_d1 <= SPI_cmd & Transmit_Addr_to_spi_clk(31 downto 8); -- & SPI_cmd;-- (31 downto 8);
last_7_addr_bits <= Transmit_Addr_to_spi_clk(7 downto 0);
-- internal_count <= (others => '0');
elsif(wrap_around = '1') then
Tx_Data_d1 <= SPI_cmd & spi_addr_wrap(31 downto 8);--spi_addr_i & SPI_cmd;
last_7_addr_bits <= spi_addr_wrap(7 downto 0);
elsif(SPIXfer_done_int = '1') then -- and internal_count < "0101")then
Tx_Data_d1 <= --"11111111" & -- Tx_Data_d1(7 downto 0) &
-- --Tx_Data_d1(31 downto 8);
-- Tx_Data_d1(31 downto 8);
Tx_Data_d1(23 downto 0) & -- Transmit_Addr_to_spi_clk(7 downto 0);
-- spi_addr_wrap(7 downto 0);
last_7_addr_bits(7 downto 0);
-- internal_count <= internal_count + "0001";
--elsif(SPIXfer_done_int = '1' and internal_count = "0101") then
-- Tx_Data_d1 <= (others => '1');
end if;
end if;
end process SHIFT_TX_REG_SPI_CLK_P;
Transmit_Data <= Tx_Data_d1(31 downto 24);
-- STORE_INFO_P:process(EXT_SPI_CLK)is
-- -----
-- begin
-- -----
-- if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
-- if(Rst_to_spi = '1')then
-- data_loaded <= '0';
-- cmd_sent <= '0';
-- elsif(load_axi_data_to_spi_clk = '1' or wrap_around = '1) then
-- data_loaded <= '1';
-- elsif(data_loaded = '1' and SPIXfer_done_int = '1') then
-- cmd_sent <= '1';
-- end if;
-- end if;
-- end process STORE_INFO_P;
end generate SHIFT_TX_REG_32_BIT_GEN;
-------------------------------------------------------
-- Transmit_Data <= Tx_Data_d1(31 downto 24);
-------------------------------------------------------
-------------------------------------------------------------------------------
STD_MODE_CONTROL_GEN: if C_SPI_MODE = 0 generate
-----
begin
-----
WB_MEM_STD_MD_GEN: if C_SPI_MODE = 0 and C_SPI_MEMORY = 1 generate
-----------
signal cmd_addr_cntr : std_logic_vector(2 downto 0);
signal hw_wd_cntr : std_logic_vector(1 downto 0);
-----
begin
-----
wb_hpm_done <= '1';
load_wr_en <= '0';-- 4/12/2013 applicable only for Numonyx memories
---- Std mode command = 0x0B - Fast Read
SPI_cmd <= "00001011"; -- FAST_READ
-- |<---- cmd error
-- WB 000 000 0100 0<-cmd error
-- NM 000 000 0100 0
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
---------------------------
-- CMD_ADDR_CNTR_P: in each SPI transaction, the first 5 transactions are of
-- CMD, A0, A1, A2 and dummy. Total 5 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 5 bytes are transferred.
-- below counter is for that purpose only. This is applicable only for Winbond memory.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or (wrap_around = '1') then
cmd_addr_cntr <= "000";
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1')then
cmd_addr_cntr <= "000";
cmd_addr_sent <= wrap_around;
elsif(SPIXfer_done_int = '1')then
if(cmd_addr_cntr = "101")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
----------------------------
-- TWO_BIT_CNTR_P: This is specifically used for HW data storage
TWO_BIT_CNTR_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') or (wrap_around = '1') then
hw_wd_cntr <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1')then
hw_wd_cntr <= hw_wd_cntr + "01";
end if;
end if;
end process TWO_BIT_CNTR_P;
----------------------------------------------
STORE_RX_DATA_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') then
Data_To_Rx_FIFO_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1') then
if(one_byte_xfer_to_spi_clk = '1') then
case spi_addr_i(1 downto 0) is
when "00" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 8) &
receive_Data_int;
when "01" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 16)&
receive_Data_int &
Data_To_Rx_FIFO_int(7 downto 0);
when "10" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 24)&
receive_Data_int &
Data_To_Rx_FIFO_int(15 downto 0);
when "11" =>
Data_To_Rx_FIFO_int <= receive_Data_int &
Data_To_Rx_FIFO_int(23 downto 0);
when others => null;
end case;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '0') then -- adjustment for half word
if(spi_addr_i(1) = '0') then
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);-- & receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= receive_Data_int & Data_To_Rx_FIFO_int(15 downto 8);-- & receive_Data_int;
else
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);-- & receive_Data_int;
Data_To_Rx_FIFO_int(31 downto 16)<= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 24);-- & receive_Data_int;
end if;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '1') then -- adjustment for half word
if(hw_wd_cntr = "00") then -- fill in D0
Data_To_Rx_FIFO_int(31 downto 8) <= Data_To_Rx_FIFO_int(31 downto 8);
Data_To_Rx_FIFO_int(7 downto 0) <= receive_Data_int;
elsif(hw_wd_cntr = "01")then -- fill in D1
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);
Data_To_Rx_FIFO_int(15 downto 8) <= receive_Data_int;
Data_To_Rx_FIFO_int(7 downto 0) <= Data_To_Rx_FIFO_int(7 downto 0);
elsif(hw_wd_cntr = "10")then -- fill in D2
Data_To_Rx_FIFO_int(31 downto 24) <= Data_To_Rx_FIFO_int(31 downto 24);
Data_To_Rx_FIFO_int(23 downto 16) <= receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);
else
Data_To_Rx_FIFO_int(31 downto 24) <= receive_Data_int;
Data_To_Rx_FIFO_int(23 downto 0) <= Data_To_Rx_FIFO_int(23 downto 0);
end if;
else -- adjustment for complete word
--Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(23 downto 0) & receive_Data_int;
Data_To_Rx_FIFO_int <= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 8);
end if;
end if;
end if;
end process STORE_RX_DATA_SPI_CLK_P;
----------------------------
Data_To_Rx_FIFO <= Data_To_Rx_FIFO_int;
---------------------------------------
RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
receive_Data_int <= (others => '0');
elsif(SPIXfer_done_int_pulse = '1') then
receive_Data_int <= rx_shft_reg_mode_0011;
elsif(SPIXfer_done_int_pulse_d1 = '1') and (cmd_addr_sent = '1')then
receive_Data_int <= receive_Data_int
((C_NUM_TRANSFER_BITS-2) downto 0) &
IO1_I ; --MISO_I;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS;
-----------------------------------------
end generate WB_MEM_STD_MD_GEN;
------------------------
--------------------------------------------------------------------------
NM_MEM_STD_MD_GEN: if C_SPI_MODE = 0 and C_SPI_MEMORY = 2 generate
signal cmd_addr_cntr : std_logic_vector(2 downto 0);
signal hw_wd_cntr : std_logic_vector(1 downto 0);
-----
begin
-----
---- Std mode command = 0x0B - Fast Read
STD_SPI_CMD_NM_24_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
SPI_cmd <= "00001011";-- FAST_READ - 0x0Bh
-- |<---- cmd error
-- NM 000 000 0100 0
four_byte_en_done <= '1';
wb_hpm_done <= '1';
DRIVE_CONTROL_SIG_P: process(EXT_SPI_CLK, wb_hpm_done, wr_en_done_reg ) is -- wb_hpm_done, wr_en_done_reg) is
variable temp: std_logic_vector(1 downto 0);
begin
temp := wb_hpm_done & wr_en_done_reg;
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
--case wb_hpm_done is
-- -- when "00"|"01" => -- write enable is under process
-- when '0' => -- write enable and/or Enable 4 byte addressing is under process
-- Data_Dir <= '0';
-- Data_Mode_1 <= '0';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '0';
-- --------------------
-- Quad_Phase <= '0';-- permanent '0'
-- --------------------
-- Addr_Mode_1 <= '0';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '0';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
-- -- when "01" => -- Enable 4 byte addressing is under process
-- -- Data_Dir <= '0';
-- -- Data_Mode_1 <= '0';
-- -- Data_Mode_0 <= '0';
-- -- Data_Phase <= '0';
-- -- --------------------
-- -- Quad_Phase <= '0';-- permanent '0'
-- -- --------------------
-- -- Addr_Mode_1 <= '0';
-- -- Addr_Mode_0 <= '0';
-- -- Addr_Bit <= '0';
-- -- Addr_Phase <= '0';
-- -- --------------------
-- -- CMD_Mode_1 <= '0';
-- -- CMD_Mode_0 <= '0';
-- -- when "10" => -- write enable is done and enable 4 byte addressing is also done
-- when '1' => -- write enable and enable 4 byte addressing is also done
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- -- coverage off
-- when others =>
-- Data_Dir <= '0';
-- Data_Mode_1 <= '0';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '0';
-- --------------------
-- Quad_Phase <= '0';-- permanent '0'
-- --------------------
-- Addr_Mode_1 <= '0';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '0';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
-- -- coverage on
--end case;
end if;
end process DRIVE_CONTROL_SIG_P;
---------------------------------------------------------------------
end generate STD_SPI_CMD_NM_24_BIT_GEN;
STD_SPI_CMD_NM_32_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
SPI_cmd <= "00001100";-- FAST_READ_4Byte - 0x0Ch
-- |<---- cmd error
-- NM 000 000 0100 0
--end generate STD_SPI_CMD_NM_32_BIT_GEN;
--NM_EN_32_ADDR_MD_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
--begin
-----
nm_wr_en_CMD <= "00000110"; -- 0x06 h Write Enable
nm_4byte_addr_en_CMD <= "10110111"; -- 0xB7 h Enable 4 Byte Addressing Mode
----------------------------------------------------
NM_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
nm_wr_en_cntrl_ps <= NM_WR_EN_IDLE;
wr_en_under_process_d1 <= '0';
wr_en_done_reg <= '0';
else
nm_wr_en_cntrl_ps <= nm_wr_en_cntrl_ns;
wr_en_under_process_d1 <= wr_en_under_process;
wr_en_done_reg <= wr_en_done;
end if;
end if;
end process NM_PS_TO_NS_PROCESS;
----------------------------------
--
NM_WR_EN_CNTRL_PROCESS: process(
nm_wr_en_cntrl_ps ,
--SPIXfer_done_int_pulse,
--SPIXfer_done_int ,
Rst_to_spi ,
SR_5_Tx_Empty ,
wr_en_done_reg
) is
-----
begin
-----
--load_wr_en_cmd <= '0';
--load_wr_sr_cmd <= '0';
--load_wr_sr_d0 <= '0';
--load_wr_sr_d1 <= '0';
load_wr_en <= '0';
wr_en_done <= '0';
wr_en_under_process <= '0';
case nm_wr_en_cntrl_ps is
when NM_WR_EN_IDLE => --load_wr_en_cmd <= '1';
load_wr_en <= '1';
wr_en_under_process <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN;
when NM_WR_EN => if (SR_5_Tx_Empty = '1')then
--wr_en_done <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN_DONE;
else
--wr_en_under_process <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN;
end if;
wr_en_done <= SR_5_Tx_Empty;
wr_en_under_process <= not SR_5_Tx_Empty;
when NM_WR_EN_DONE => if (Rst_to_spi = '1') then
nm_wr_en_cntrl_ns <= NM_WR_EN_IDLE;
else
nm_wr_en_cntrl_ns <= NM_WR_EN_DONE;
end if;
wr_en_done <= wr_en_done_reg;
end case;
end process NM_WR_EN_CNTRL_PROCESS;
----------------------------------------------------
NM_4_BYTE_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
nm_sm_4_byte_addr_ps <= NM_32_BIT_IDLE;
--four_byte_addr_under_process_d1 <= '0';
hpm_under_process_d1 <= '0';
wr_en_done_d1 <= '0';
wr_en_done_d2 <= '0';
wb_hpm_done_reg <= '0';
else
nm_sm_4_byte_addr_ps <= nm_sm_4_byte_addr_ns;
hpm_under_process_d1 <= hpm_under_process;
--four_byte_en_done_reg <= four_byte_en_done;
wr_en_done_d1 <= wr_en_done_reg; -- wr_en_done;
wr_en_done_d2 <= wr_en_done_d1;
wb_hpm_done_reg <= wb_hpm_done;
end if;
end if;
end process NM_4_BYTE_PS_TO_NS_PROCESS;
----------------------------------
--
NM_4_BYTE_ADDR_EN_PROCESS: process(
nm_sm_4_byte_addr_ps ,
Rst_to_spi ,
SR_5_Tx_Empty ,
wr_en_done_d2 ,
wb_hpm_done_reg
) is
-----
begin
-----
-- load_4_byte_addr_en <= '0';
load_wr_hpm <= '0';
wb_hpm_done <= '0';
hpm_under_process <= '0';
four_byte_en_done <= '0';
four_byte_en_under_process <= '0';
case nm_sm_4_byte_addr_ps is
when NM_32_BIT_IDLE => if (wr_en_done_d2 = '1') then
--load_wr_hpm <= '1';
--hpm_under_process <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN;
else
nm_sm_4_byte_addr_ns <= NM_32_BIT_IDLE;
end if;
load_wr_hpm <= wr_en_done_d2;
hpm_under_process <= wr_en_done_d2;
when NM_32_BIT_EN => if (SR_5_Tx_Empty = '1') then
-- wb_hpm_done <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN_DONE;
else
-- hpm_under_process <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN;
end if;
wb_hpm_done <= SR_5_Tx_Empty;
hpm_under_process <= not(SR_5_Tx_Empty);
when NM_32_BIT_EN_DONE => if(Rst_to_spi = '1')then
nm_sm_4_byte_addr_ns <= NM_32_BIT_IDLE;
else
-- if (SR_5_Tx_Empty = '1')then
-- --four_byte_en_done <= '1';
-- wb_hpm_done <= '1';
-- else
-- -- four_byte_en_under_process <= '1';
-- hpm_under_process <= '1';
-- end if;
-- four_byte_en_done <= four_byte_en_done_reg;
-- wb_hpm_done <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN_DONE;
end if;
wb_hpm_done <= wb_hpm_done_reg;
end case;
end process NM_4_BYTE_ADDR_EN_PROCESS;
--------------------------------------
DRIVE_CONTROL_SIG_P: process(EXT_SPI_CLK, wb_hpm_done, wr_en_done_reg) is -- wb_hpm_done, wr_en_done_reg) is
variable temp: std_logic_vector(1 downto 0);
begin
temp := wb_hpm_done & wr_en_done_reg;
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
case wb_hpm_done is
-- when "00"|"01" => -- write enable is under process
when '0' => -- write enable and/or Enable 4 byte addressing is under process
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- when "01" => -- Enable 4 byte addressing is under process
-- Data_Dir <= '0';
-- Data_Mode_1 <= '0';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '0';
-- --------------------
-- Quad_Phase <= '0';-- permanent '0'
-- --------------------
-- Addr_Mode_1 <= '0';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '0';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
-- when "10" => -- write enable is done and enable 4 byte addressing is also done
when '1' => -- write enable and enable 4 byte addressing is also done
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '1';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '1';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage off
when others =>
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage on
end case;
end if;
end process DRIVE_CONTROL_SIG_P;
---------------------------------------------------------------------
--end generate NM_EN_32_ADDR_MD_GEN;
end generate STD_SPI_CMD_NM_32_BIT_GEN;
---------------------------------------
-- wb_hpm_done <= four_byte_en_done;
--Data_Dir <= '0';
--Data_Mode_1 <= '0';
--Data_Mode_0 <= '0';
--Data_Phase <= '0';
----------------------
--Quad_Phase <= '0';-- permanent '0'
----------------------
--Addr_Mode_1 <= '0';
--Addr_Mode_0 <= '0';
--Addr_Bit <= '0';
--Addr_Phase <= '1';
----------------------
--CMD_Mode_1 <= '0';
--CMD_Mode_0 <= '0';
---------------------------
-----
RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
receive_Data_int <= (others => '0');
-- elsif(SPIXfer_done_int = '1') and (cmd_addr_cntr = "110")then
elsif(SPIXfer_done_int_pulse = '1') then
receive_Data_int <= rx_shft_reg_mode_0011;
elsif(SPIXfer_done_int_pulse_d1 = '1') and (cmd_addr_sent = '1')then
receive_Data_int <= receive_Data_int
((C_NUM_TRANSFER_BITS-2) downto 0) &
IO1_I ; --MISO_I;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS;
CMD_ADDR_24_BIT_CNTR_GEN : if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-- CMD_ADDR_CNTR_P: in each SPI transaction, the first 5 transactions are of
-- CMD, A0, A1, A2 and dummy. Total 5 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 5 bytes are transferred.
-- below counter is for that purpose only. Tihs is for 24 bit addressing mode only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or (wrap_around = '1') then
cmd_addr_cntr <= "000";
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1') then -- and store_date_in_drr_fifo_d3 = '1')then
cmd_addr_cntr <= "000";
cmd_addr_sent <= wrap_around;
elsif(SPIXfer_done_int = '1')then
if(cmd_addr_cntr = "101")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
----------------------------
end generate CMD_ADDR_24_BIT_CNTR_GEN;
--------------------------------------
CMD_ADDR_32_BIT_CNTR_GEN : if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-- * -- -----
-- * -- RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-- * -- -----
-- * -- begin
-- * -- -----
-- * -- if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
-- * -- if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
-- * -- receive_Data_int <= (others => '0');
-- * -- elsif(SPIXfer_done_int_pulse_d1 = '1') and (cmd_addr_sent = '1') then -- and (cmd_addr_cntr = "111")then
-- * -- receive_Data_int <= rx_shft_reg_mode_0011;
-- * -- end if;
-- * -- end if;
-- * -- end process RECEIVE_DATA_STROBE_PROCESS;
-- CMD_ADDR_CNTR_P: in each SPI transaction, the first 6 transactions are of
-- CMD, A0, A1, A2, A3 and dummy. Total 6 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 6 bytes are transferred.
-- below counter is for that purpose only. This is for 32 bit addressing mode only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or (wrap_around = '1') then
cmd_addr_cntr <= "000";
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1' and store_date_in_drr_fifo_d3 = '1')then
cmd_addr_cntr <= "000";
cmd_addr_sent <= wrap_around;
elsif(SPIXfer_done_int = '1' and wb_hpm_done = '1')then
if(cmd_addr_cntr = "110")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
----------------------------
end generate CMD_ADDR_32_BIT_CNTR_GEN;
--------------------------------------
-- TWO_BIT_CNTR_P: This is specifically used for HW data storage
TWO_BIT_CNTR_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') or (wrap_around = '1') then
hw_wd_cntr <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1')then
hw_wd_cntr <= hw_wd_cntr + "01";
end if;
end if;
end process TWO_BIT_CNTR_P;
----------------------------------------------
STORE_RX_DATA_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') then
Data_To_Rx_FIFO_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1') then
if(one_byte_xfer_to_spi_clk = '1') then
case spi_addr_i(1 downto 0) is
when "00" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 8) &
receive_Data_int;
when "01" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 16)&
receive_Data_int &
Data_To_Rx_FIFO_int(7 downto 0);
when "10" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 24)&
receive_Data_int &
Data_To_Rx_FIFO_int(15 downto 0);
when "11" =>
Data_To_Rx_FIFO_int <= receive_Data_int &
Data_To_Rx_FIFO_int(23 downto 0);
when others => null;
end case;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '0') then -- adjustment for half word
if(spi_addr_i(1) = '0') then
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);-- & receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= receive_Data_int & Data_To_Rx_FIFO_int(15 downto 8);-- & receive_Data_int;
else
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);-- & receive_Data_int;
Data_To_Rx_FIFO_int(31 downto 16)<= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 24);-- & receive_Data_int;
end if;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '1') then -- adjustment for half word
if(hw_wd_cntr = "00") then -- fill in D0
Data_To_Rx_FIFO_int(31 downto 8) <= Data_To_Rx_FIFO_int(31 downto 8);
Data_To_Rx_FIFO_int(7 downto 0) <= receive_Data_int;
elsif(hw_wd_cntr = "01")then -- fill in D1
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);
Data_To_Rx_FIFO_int(15 downto 8) <= receive_Data_int;
Data_To_Rx_FIFO_int(7 downto 0) <= Data_To_Rx_FIFO_int(7 downto 0);
elsif(hw_wd_cntr = "10")then -- fill in D2
Data_To_Rx_FIFO_int(31 downto 24) <= Data_To_Rx_FIFO_int(31 downto 24);
Data_To_Rx_FIFO_int(23 downto 16) <= receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);
else
Data_To_Rx_FIFO_int(31 downto 24) <= receive_Data_int;
Data_To_Rx_FIFO_int(23 downto 0) <= Data_To_Rx_FIFO_int(23 downto 0);
end if;
else -- adjustment for complete word
--Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(23 downto 0) & receive_Data_int;
Data_To_Rx_FIFO_int <= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 8);
end if;
end if;
end if;
end process STORE_RX_DATA_SPI_CLK_P;
----------------------------
Data_To_Rx_FIFO <= Data_To_Rx_FIFO_int;
---------------------------------------
end generate NM_MEM_STD_MD_GEN;
------------------------
SP_MEM_STD_MD_GEN: if C_SPI_MODE = 0 and C_SPI_MEMORY = 3 generate
signal cmd_addr_cntr : std_logic_vector(2 downto 0);
signal hw_wd_cntr : std_logic_vector(1 downto 0);
-----
begin
-----
---- Std mode command = 0x0B - Fast Read
STD_SPI_CMD_SP_24_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
SPI_cmd <= "00001011";-- FAST_READ - 0x0Bh
-- |<---- cmd error
-- NM 000 000 0100 0
four_byte_en_done <= '1';
wb_hpm_done <= '1';
DRIVE_CONTROL_SIG_P: process(EXT_SPI_CLK) is -- wb_hpm_done, wr_en_done_reg) is
variable temp: std_logic_vector(1 downto 0);
begin
temp := wb_hpm_done & wr_en_done_reg;
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
--case wb_hpm_done is
-- -- when "00"|"01" => -- write enable is under process
-- when '0' => -- write enable and/or Enable 4 byte addressing is under process
-- Data_Dir <= '0';
-- Data_Mode_1 <= '0';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '0';
-- --------------------
-- Quad_Phase <= '0';-- permanent '0'
-- --------------------
-- Addr_Mode_1 <= '0';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '0';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
-- -- when "01" => -- Enable 4 byte addressing is under process
-- -- Data_Dir <= '0';
-- -- Data_Mode_1 <= '0';
-- -- Data_Mode_0 <= '0';
-- -- Data_Phase <= '0';
-- -- --------------------
-- -- Quad_Phase <= '0';-- permanent '0'
-- -- --------------------
-- -- Addr_Mode_1 <= '0';
-- -- Addr_Mode_0 <= '0';
-- -- Addr_Bit <= '0';
-- -- Addr_Phase <= '0';
-- -- --------------------
-- -- CMD_Mode_1 <= '0';
-- -- CMD_Mode_0 <= '0';
-- -- when "10" => -- write enable is done and enable 4 byte addressing is also done
-- when '1' => -- write enable and enable 4 byte addressing is also done
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- -- coverage off
-- when others =>
-- Data_Dir <= '0';
-- Data_Mode_1 <= '0';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '0';
-- --------------------
-- Quad_Phase <= '0';-- permanent '0'
-- --------------------
-- Addr_Mode_1 <= '0';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '0';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
-- -- coverage on
--end case;
end if;
end process DRIVE_CONTROL_SIG_P;
---------------------------------------------------------------------
end generate STD_SPI_CMD_SP_24_BIT_GEN;
STD_SPI_CMD_SP_32_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
SPI_cmd <= "00001100";-- FAST_READ_4Byte - 0x0Ch
-- |<---- cmd error
-- NM 000 000 0100 0
--end generate STD_SPI_CMD_NM_32_BIT_GEN;
--NM_EN_32_ADDR_MD_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
--begin
-----
nm_wr_en_CMD <= "00000110"; -- 0x06 h Write Enable
nm_4byte_addr_en_CMD <= "10110111"; -- 0xB7 h Enable 4 Byte Addressing Mode
----------------------------------------------------
SP_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
nm_wr_en_cntrl_ps <= NM_WR_EN_IDLE;
wr_en_under_process_d1 <= '0';
wr_en_done_reg <= '0';
else
nm_wr_en_cntrl_ps <= nm_wr_en_cntrl_ns;
wr_en_under_process_d1 <= wr_en_under_process;
wr_en_done_reg <= wr_en_done;
end if;
end if;
end process SP_PS_TO_NS_PROCESS;
----------------------------------
--
SP_WR_EN_CNTRL_PROCESS: process(
nm_wr_en_cntrl_ps ,
--SPIXfer_done_int_pulse,
--SPIXfer_done_int ,
Rst_to_spi ,
SR_5_Tx_Empty ,
wr_en_done_reg
) is
-----
begin
-----
--load_wr_en_cmd <= '0';
--load_wr_sr_cmd <= '0';
--load_wr_sr_d0 <= '0';
--load_wr_sr_d1 <= '0';
load_wr_en <= '0';
wr_en_done <= '0';
wr_en_under_process <= '0';
case nm_wr_en_cntrl_ps is
when NM_WR_EN_IDLE => --load_wr_en_cmd <= '1';
load_wr_en <= '1';
wr_en_under_process <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN;
when NM_WR_EN => if (SR_5_Tx_Empty = '1')then
--wr_en_done <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN_DONE;
else
--wr_en_under_process <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN;
end if;
wr_en_done <= SR_5_Tx_Empty;
wr_en_under_process <= not SR_5_Tx_Empty;
when NM_WR_EN_DONE => if (Rst_to_spi = '1') then
nm_wr_en_cntrl_ns <= NM_WR_EN_IDLE;
else
nm_wr_en_cntrl_ns <= NM_WR_EN_DONE;
end if;
wr_en_done <= wr_en_done_reg;
end case;
end process SP_WR_EN_CNTRL_PROCESS;
----------------------------------------------------
SP_4_BYTE_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
nm_sm_4_byte_addr_ps <= NM_32_BIT_IDLE;
--four_byte_addr_under_process_d1 <= '0';
hpm_under_process_d1 <= '0';
wr_en_done_d1 <= '0';
wr_en_done_d2 <= '0';
wb_hpm_done_reg <= '0';
else
nm_sm_4_byte_addr_ps <= nm_sm_4_byte_addr_ns;
hpm_under_process_d1 <= hpm_under_process;
--four_byte_en_done_reg <= four_byte_en_done;
wr_en_done_d1 <= wr_en_done_reg; -- wr_en_done;
wr_en_done_d2 <= wr_en_done_d1;
wb_hpm_done_reg <= wb_hpm_done;
end if;
end if;
end process SP_4_BYTE_PS_TO_NS_PROCESS;
----------------------------------
--
SP_4_BYTE_ADDR_EN_PROCESS: process(
nm_sm_4_byte_addr_ps ,
Rst_to_spi ,
SR_5_Tx_Empty ,
wr_en_done_d2 ,
wb_hpm_done_reg
) is
-----
begin
-----
-- load_4_byte_addr_en <= '0';
load_wr_hpm <= '0';
wb_hpm_done <= '0';
hpm_under_process <= '0';
four_byte_en_done <= '0';
four_byte_en_under_process <= '0';
case nm_sm_4_byte_addr_ps is
when NM_32_BIT_IDLE => if (wr_en_done_d2 = '1') then
--load_wr_hpm <= '1';
--hpm_under_process <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN;
else
nm_sm_4_byte_addr_ns <= NM_32_BIT_IDLE;
end if;
load_wr_hpm <= wr_en_done_d2;
hpm_under_process <= wr_en_done_d2;
when NM_32_BIT_EN => if (SR_5_Tx_Empty = '1') then
-- wb_hpm_done <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN_DONE;
else
-- hpm_under_process <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN;
end if;
wb_hpm_done <= SR_5_Tx_Empty;
hpm_under_process <= not(SR_5_Tx_Empty);
when NM_32_BIT_EN_DONE => if(Rst_to_spi = '1')then
nm_sm_4_byte_addr_ns <= NM_32_BIT_IDLE;
else
-- if (SR_5_Tx_Empty = '1')then
-- --four_byte_en_done <= '1';
-- wb_hpm_done <= '1';
-- else
-- -- four_byte_en_under_process <= '1';
-- hpm_under_process <= '1';
-- end if;
-- four_byte_en_done <= four_byte_en_done_reg;
-- wb_hpm_done <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN_DONE;
end if;
wb_hpm_done <= wb_hpm_done_reg;
end case;
end process SP_4_BYTE_ADDR_EN_PROCESS;
--------------------------------------
DRIVE_CONTROL_SIG_P: process(EXT_SPI_CLK) is -- wb_hpm_done, wr_en_done_reg) is
variable temp: std_logic_vector(1 downto 0);
begin
temp := wb_hpm_done & wr_en_done_reg;
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
case wb_hpm_done is
-- when "00"|"01" => -- write enable is under process
when '0' => -- write enable and/or Enable 4 byte addressing is under process
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- when "01" => -- Enable 4 byte addressing is under process
-- Data_Dir <= '0';
-- Data_Mode_1 <= '0';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '0';
-- --------------------
-- Quad_Phase <= '0';-- permanent '0'
-- --------------------
-- Addr_Mode_1 <= '0';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '0';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
-- when "10" => -- write enable is done and enable 4 byte addressing is also done
when '1' => -- write enable and enable 4 byte addressing is also done
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '1';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '1';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage off
when others =>
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage on
end case;
end if;
end process DRIVE_CONTROL_SIG_P;
---------------------------------------------------------------------
--end generate NM_EN_32_ADDR_MD_GEN;
end generate STD_SPI_CMD_SP_32_BIT_GEN;
---------------------------------------
-- wb_hpm_done <= four_byte_en_done;
--Data_Dir <= '0';
--Data_Mode_1 <= '0';
--Data_Mode_0 <= '0';
--Data_Phase <= '0';
----------------------
--Quad_Phase <= '0';-- permanent '0'
----------------------
--Addr_Mode_1 <= '0';
--Addr_Mode_0 <= '0';
--Addr_Bit <= '0';
--Addr_Phase <= '1';
----------------------
--CMD_Mode_1 <= '0';
--CMD_Mode_0 <= '0';
---------------------------
-----
RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
receive_Data_int <= (others => '0');
-- elsif(SPIXfer_done_int = '1') and (cmd_addr_cntr = "110")then
elsif(SPIXfer_done_int_pulse = '1') then
receive_Data_int <= rx_shft_reg_mode_0011;
elsif(SPIXfer_done_int_pulse_d1 = '1') and (cmd_addr_sent = '1')then
receive_Data_int <= receive_Data_int
((C_NUM_TRANSFER_BITS-2) downto 0) &
IO1_I ; --MISO_I;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS;
CMD_ADDR_24_BIT_CNTR_GEN : if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-- CMD_ADDR_CNTR_P: in each SPI transaction, the first 5 transactions are of
-- CMD, A0, A1, A2 and dummy. Total 5 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 5 bytes are transferred.
-- below counter is for that purpose only. Tihs is for 24 bit addressing mode only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or (wrap_around = '1') then
cmd_addr_cntr <= "000";
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1') then -- and store_date_in_drr_fifo_d3 = '1')then
cmd_addr_cntr <= "000";
cmd_addr_sent <= wrap_around;
elsif(SPIXfer_done_int = '1')then
if(cmd_addr_cntr = "101")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
----------------------------
end generate CMD_ADDR_24_BIT_CNTR_GEN;
--------------------------------------
CMD_ADDR_32_BIT_CNTR_GEN : if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-- * -- -----
-- * -- RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-- * -- -----
-- * -- begin
-- * -- -----
-- * -- if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
-- * -- if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
-- * -- receive_Data_int <= (others => '0');
-- * -- elsif(SPIXfer_done_int_pulse_d1 = '1') and (cmd_addr_sent = '1') then -- and (cmd_addr_cntr = "111")then
-- * -- receive_Data_int <= rx_shft_reg_mode_0011;
-- * -- end if;
-- * -- end if;
-- * -- end process RECEIVE_DATA_STROBE_PROCESS;
-- CMD_ADDR_CNTR_P: in each SPI transaction, the first 6 transactions are of
-- CMD, A0, A1, A2, A3 and dummy. Total 6 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 6 bytes are transferred.
-- below counter is for that purpose only. This is for 32 bit addressing mode only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or (wrap_around = '1') then
cmd_addr_cntr <= "000";
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1' and store_date_in_drr_fifo_d3 = '1')then
cmd_addr_cntr <= "000";
cmd_addr_sent <= wrap_around;
elsif(SPIXfer_done_int = '1' and wb_hpm_done = '1')then
if(cmd_addr_cntr = "110")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
----------------------------
end generate CMD_ADDR_32_BIT_CNTR_GEN;
--------------------------------------
-- TWO_BIT_CNTR_P: This is specifically used for HW data storage
TWO_BIT_CNTR_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') or (wrap_around = '1') then
hw_wd_cntr <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1')then
hw_wd_cntr <= hw_wd_cntr + "01";
end if;
end if;
end process TWO_BIT_CNTR_P;
----------------------------------------------
STORE_RX_DATA_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') then
Data_To_Rx_FIFO_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1') then
if(one_byte_xfer_to_spi_clk = '1') then
case spi_addr_i(1 downto 0) is
when "00" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 8) &
receive_Data_int;
when "01" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 16)&
receive_Data_int &
Data_To_Rx_FIFO_int(7 downto 0);
when "10" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 24)&
receive_Data_int &
Data_To_Rx_FIFO_int(15 downto 0);
when "11" =>
Data_To_Rx_FIFO_int <= receive_Data_int &
Data_To_Rx_FIFO_int(23 downto 0);
when others => null;
end case;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '0') then -- adjustment for half word
if(spi_addr_i(1) = '0') then
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);-- & receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= receive_Data_int & Data_To_Rx_FIFO_int(15 downto 8);-- & receive_Data_int;
else
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);-- & receive_Data_int;
Data_To_Rx_FIFO_int(31 downto 16)<= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 24);-- & receive_Data_int;
end if;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '1') then -- adjustment for half word
if(hw_wd_cntr = "00") then -- fill in D0
Data_To_Rx_FIFO_int(31 downto 8) <= Data_To_Rx_FIFO_int(31 downto 8);
Data_To_Rx_FIFO_int(7 downto 0) <= receive_Data_int;
elsif(hw_wd_cntr = "01")then -- fill in D1
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);
Data_To_Rx_FIFO_int(15 downto 8) <= receive_Data_int;
Data_To_Rx_FIFO_int(7 downto 0) <= Data_To_Rx_FIFO_int(7 downto 0);
elsif(hw_wd_cntr = "10")then -- fill in D2
Data_To_Rx_FIFO_int(31 downto 24) <= Data_To_Rx_FIFO_int(31 downto 24);
Data_To_Rx_FIFO_int(23 downto 16) <= receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);
else
Data_To_Rx_FIFO_int(31 downto 24) <= receive_Data_int;
Data_To_Rx_FIFO_int(23 downto 0) <= Data_To_Rx_FIFO_int(23 downto 0);
end if;
else -- adjustment for complete word
--Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(23 downto 0) & receive_Data_int;
Data_To_Rx_FIFO_int <= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 8);
end if;
end if;
end if;
end process STORE_RX_DATA_SPI_CLK_P;
----------------------------
Data_To_Rx_FIFO <= Data_To_Rx_FIFO_int;
---------------------------------------
end generate SP_MEM_STD_MD_GEN;
end generate STD_MODE_CONTROL_GEN;
-------------------------------------------------------------------------------
DUAL_MODE_CONTROL_GEN: if C_SPI_MODE = 1 generate
signal cmd_addr_cntr : std_logic_vector(2 downto 0);-----
signal hw_wd_cntr : std_logic_vector(1 downto 0);
begin
-----
WB_MEM_DUAL_MD_GEN: if C_SPI_MEMORY = 1 generate
-----
begin
-----
wb_wr_hpm_CMD <= "10100011"; -- 0xA3 h HPM mode
--
----------------------------------------------------
WB_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
wb_cntrl_ps <= WB_IDLE;
hpm_under_process_d1 <= '0';
else
wb_cntrl_ps <= wb_cntrl_ns;
hpm_under_process_d1 <= hpm_under_process;
end if;
end if;
end process WB_PS_TO_NS_PROCESS;
----------------------------------
--
WB_DUAL_CNTRL_PROCESS: process(
wb_cntrl_ps ,
SPIXfer_done_int_pulse,
SPIXfer_done_int ,
Rst_to_spi ,
SR_5_Tx_Empty
) is
-----
begin
-----
load_wr_en_cmd <= '0';
load_wr_sr_cmd <= '0';
load_wr_sr_d0 <= '0';
load_wr_sr_d1 <= '0';
load_wr_hpm <= '0';
wb_hpm_done <= '0';
hpm_under_process <= '0';
case wb_cntrl_ps is
when WB_IDLE => --load_wr_en_cmd <= '1';
load_wr_hpm <= '1';
hpm_under_process <= '1';
wb_cntrl_ns <= WB_WR_HPM;
when WB_WR_HPM => if (SR_5_Tx_Empty = '1')then
wb_hpm_done <= '1';
wb_cntrl_ns <= WB_DONE;
else
hpm_under_process <= '1';
wb_cntrl_ns <= WB_WR_HPM;
end if;
when WB_DONE => if (Rst_to_spi = '1') then
wb_cntrl_ns <= WB_IDLE;
else
wb_hpm_done <= '1';
wb_cntrl_ns <= WB_DONE;
end if;
end case;
end process WB_DUAL_CNTRL_PROCESS;
---- Dual mode command = 0x3B - DOFR
--SPI_cmd <= "00111011";
SPI_cmd <= "10111011"; -- 0xBB - DIOFR
-- WB 0011 000 100 0
-- NM 0011 000 100 0<-cmd error
-- NM 0011 010 100 0<-cmd error -- For 0xbbh DIOFR
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '1';
Data_Phase <= '1';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '1'; -- <- '0' for DOFR, '1' for DIOFR
Addr_Bit <= '0';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
---------------------------------------------------------------------
--RECEIVE_DATA_WB_GEN: if C_SPI_MEMORY = 1 and C_SPI_MODE /=0 generate
--begin
-----
RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
receive_Data_int <= (others => '0');
elsif(SPIXfer_done_int_pulse = '1') then
receive_Data_int <= rx_shft_reg_mode_0011;
elsif(SPIXfer_done_int_pulse_d1 = '1') and (cmd_addr_sent = '1')then
receive_Data_int <= receive_Data_int
((C_NUM_TRANSFER_BITS-3) downto 0) &
IO1_I & -- MISO_I - MSB first
IO0_I ; -- MOSI_I
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS;
--end generate RECEIVE_DATA_WB_GEN;
---------------------------------------------------------------------
-- CMD_ADDR_CNTR_P: in each SPI transaction, the firs 4 transactions are of
-- CMD, A0, A1, A2. Total 4 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 4 bytes are transferred.
-- below counter is for that purpose only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or (store_last_b4_wrap = '1') then
cmd_addr_cntr <= "000";--(others => '1');
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1')then
cmd_addr_cntr <= "000";
cmd_addr_sent <= store_last_b4_wrap;
elsif(SPIXfer_done_int_pulse_d2 = '1')then
if(cmd_addr_cntr = "100")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
----------------------------
TWO_BIT_CNTR_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') or (store_last_b4_wrap = '1') then
hw_wd_cntr <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1')then
hw_wd_cntr <= hw_wd_cntr + "01";
end if;
end if;
end process TWO_BIT_CNTR_P;
----------------------------------------------
STORE_RX_DATA_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') then
Data_To_Rx_FIFO_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1') then
if(one_byte_xfer_to_spi_clk = '1') then
case spi_addr_i(1 downto 0) is
when "00" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 8) &
receive_Data_int;
when "01" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 16)&
receive_Data_int &
Data_To_Rx_FIFO_int(7 downto 0);
when "10" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 24)&
receive_Data_int &
Data_To_Rx_FIFO_int(15 downto 0);
when "11" =>
Data_To_Rx_FIFO_int <= receive_Data_int &
Data_To_Rx_FIFO_int(23 downto 0);
when others => null;
end case;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '0') then -- adjustment for half word
if(spi_addr_i(1) = '0') then
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);-- & receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= receive_Data_int & Data_To_Rx_FIFO_int(15 downto 8);-- & receive_Data_int;
else
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);-- & receive_Data_int;
Data_To_Rx_FIFO_int(31 downto 16)<= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 24);-- & receive_Data_int;
end if;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '1') then -- adjustment for half word
if(hw_wd_cntr = "00") then -- fill in D0
Data_To_Rx_FIFO_int(31 downto 8) <= Data_To_Rx_FIFO_int(31 downto 8);
Data_To_Rx_FIFO_int(7 downto 0) <= receive_Data_int;
elsif(hw_wd_cntr = "01")then -- fill in D1
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);
Data_To_Rx_FIFO_int(15 downto 8) <= receive_Data_int;
Data_To_Rx_FIFO_int(7 downto 0) <= Data_To_Rx_FIFO_int(7 downto 0);
elsif(hw_wd_cntr = "10")then -- fill in D2
Data_To_Rx_FIFO_int(31 downto 24) <= Data_To_Rx_FIFO_int(31 downto 24);
Data_To_Rx_FIFO_int(23 downto 16) <= receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);
else
Data_To_Rx_FIFO_int(31 downto 24) <= receive_Data_int;
Data_To_Rx_FIFO_int(23 downto 0) <= Data_To_Rx_FIFO_int(23 downto 0);
end if;
else -- adjustment for complete word
--Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(23 downto 0) & receive_Data_int;
Data_To_Rx_FIFO_int <= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 8);
end if;
end if;
end if;
end process STORE_RX_DATA_SPI_CLK_P;
----------------------------
Data_To_Rx_FIFO <= Data_To_Rx_FIFO_int;
---------------------------------------
end generate WB_MEM_DUAL_MD_GEN;
---------------=============-------------------------------------------
NM_MEM_DUAL_MD_GEN: if C_SPI_MEMORY = 2 generate
-----
begin
-----
--wb_hpm_done <= '1';
---- Dual mode command = 0x3B - DOFR
--SPI_cmd <= "00111011";
--------------------------------------------------------
DUAL_SPI_CMD_NM_24_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
-----
begin
-----
---------------------------
SPI_cmd <= "10111011"; -- 0xBB - DIOFR
wb_hpm_done <= '1';
---------------------------
Data_Dir <= '0';-- for BB
Data_Mode_1 <= '0';
Data_Mode_0 <= '1';
Data_Phase <= '1';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '1';
Addr_Bit <= '0';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
---------------------------
end generate DUAL_SPI_CMD_NM_24_GEN;
------------------------------------
DUAL_SPI_CMD_NM_32_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
-----
begin
-----
SPI_cmd <= "10111100"; -- 0xBCh - DIOFR_4Byte
end generate DUAL_SPI_CMD_NM_32_GEN;
------------------------------------
NM_EN_32_ADDR_MD_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-----
nm_wr_en_CMD <= "00000110"; -- 0x06 h Write Enable
nm_4byte_addr_en_CMD <= "10110111"; -- 0xB7 h Enable 4 Byte Addressing Mode
----------------------------------------------------
NM_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
nm_wr_en_cntrl_ps <= NM_WR_EN_IDLE;
wr_en_under_process_d1 <= '0';
wr_en_done_reg <= '0';
else
nm_wr_en_cntrl_ps <= nm_wr_en_cntrl_ns;
wr_en_under_process_d1 <= wr_en_under_process;
wr_en_done_reg <= wr_en_done;
end if;
end if;
end process NM_PS_TO_NS_PROCESS;
----------------------------------
--
NM_WR_EN_CNTRL_PROCESS: process(
nm_wr_en_cntrl_ps ,
--SPIXfer_done_int_pulse,
--SPIXfer_done_int ,
Rst_to_spi ,
SR_5_Tx_Empty ,
wr_en_done_reg
) is
-----
begin
-----
--load_wr_en_cmd <= '0';
--load_wr_sr_cmd <= '0';
--load_wr_sr_d0 <= '0';
--load_wr_sr_d1 <= '0';
load_wr_en <= '0';
wr_en_done <= '0';
wr_en_under_process <= '0';
case nm_wr_en_cntrl_ps is
when NM_WR_EN_IDLE => --load_wr_en_cmd <= '1';
load_wr_en <= '1';
wr_en_under_process <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN;
when NM_WR_EN => if (SR_5_Tx_Empty = '1')then
--wr_en_done <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN_DONE;
else
--wr_en_under_process <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN;
end if;
wr_en_done <= SR_5_Tx_Empty;
wr_en_under_process <= not SR_5_Tx_Empty;
when NM_WR_EN_DONE => if (Rst_to_spi = '1') then
nm_wr_en_cntrl_ns <= NM_WR_EN_IDLE;
else
nm_wr_en_cntrl_ns <= NM_WR_EN_DONE;
end if;
wr_en_done <= wr_en_done_reg;
end case;
end process NM_WR_EN_CNTRL_PROCESS;
----------------------------------------------------
NM_4_BYTE_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
nm_sm_4_byte_addr_ps <= NM_32_BIT_IDLE;
--four_byte_addr_under_process_d1 <= '0';
hpm_under_process_d1 <= '0';
wr_en_done_d1 <= '0';
wr_en_done_d2 <= '0';
wb_hpm_done_reg <= '0';
else
nm_sm_4_byte_addr_ps <= nm_sm_4_byte_addr_ns;
hpm_under_process_d1 <= hpm_under_process;
--four_byte_en_done_reg <= four_byte_en_done;
wr_en_done_d1 <= wr_en_done_reg; -- wr_en_done;
wr_en_done_d2 <= wr_en_done_d1;
wb_hpm_done_reg <= wb_hpm_done;
end if;
end if;
end process NM_4_BYTE_PS_TO_NS_PROCESS;
----------------------------------
--
NM_4_BYTE_ADDR_EN_PROCESS: process(
nm_sm_4_byte_addr_ps ,
Rst_to_spi ,
SR_5_Tx_Empty ,
wr_en_done_d2 ,
wb_hpm_done_reg
) is
-----
begin
-----
-- load_4_byte_addr_en <= '0';
load_wr_hpm <= '0';
wb_hpm_done <= '0';
hpm_under_process <= '0';
four_byte_en_done <= '0';
four_byte_en_under_process <= '0';
case nm_sm_4_byte_addr_ps is
when NM_32_BIT_IDLE => if (wr_en_done_d2 = '1') then
--load_wr_hpm <= '1';
--hpm_under_process <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN;
else
nm_sm_4_byte_addr_ns <= NM_32_BIT_IDLE;
end if;
load_wr_hpm <= wr_en_done_d2;
hpm_under_process <= wr_en_done_d2;
when NM_32_BIT_EN => if (SR_5_Tx_Empty = '1') then
-- wb_hpm_done <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN_DONE;
else
-- hpm_under_process <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN;
end if;
wb_hpm_done <= SR_5_Tx_Empty;
hpm_under_process <= not(SR_5_Tx_Empty);
when NM_32_BIT_EN_DONE => if(Rst_to_spi = '1')then
nm_sm_4_byte_addr_ns <= NM_32_BIT_IDLE;
else
-- if (SR_5_Tx_Empty = '1')then
-- --four_byte_en_done <= '1';
-- wb_hpm_done <= '1';
-- else
-- -- four_byte_en_under_process <= '1';
-- hpm_under_process <= '1';
-- end if;
-- four_byte_en_done <= four_byte_en_done_reg;
-- wb_hpm_done <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN_DONE;
end if;
wb_hpm_done <= wb_hpm_done_reg;
end case;
end process NM_4_BYTE_ADDR_EN_PROCESS;
--------------------------------------
DRIVE_CONTROL_SIG_P: process(EXT_SPI_CLK, wb_hpm_done, wr_en_done_reg) is -- wb_hpm_done, wr_en_done_reg) is
variable temp: std_logic_vector(1 downto 0);
begin
temp := wb_hpm_done & wr_en_done_reg;
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
case wb_hpm_done is
-- when "00"|"01" => -- write enable is under process
when '0' => -- write enable and/or Enable 4 byte addressing is under process
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- when "01" => -- Enable 4 byte addressing is under process
-- Data_Dir <= '0';
-- Data_Mode_1 <= '0';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '0';
-- --------------------
-- Quad_Phase <= '0';-- permanent '0'
-- --------------------
-- Addr_Mode_1 <= '0';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '0';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
-- when "10" => -- write enable is done and enable 4 byte addressing is also done
when '1' => -- write enable and enable 4 byte addressing is also done
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '1';
Data_Phase <= '1';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '1';
Addr_Bit <= '1';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage off
when others =>
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage on
end case;
end if;
end process DRIVE_CONTROL_SIG_P;
end generate NM_EN_32_ADDR_MD_GEN;
--------------------------------------
-- -- WB 0011 000 100 0
-- -- NM 0011 000 100 0<-cmd error
-- -- NM 0011 010 100 0<-cmd error -- For 0xbbh DIOFR
-- 0011 011 100 0
-- Data_Dir <= '0';<-- for BB -- '0';<-- for BC
-- Data_Mode_1 <= '0'; -- '0';
-- Data_Mode_0 <= '1'; -- '1';
-- Data_Phase <= '1'; -- '1';
-- -------------------- --
-- Quad_Phase <= '0';-- permanent '0' -- '0';
-- -------------------- --
-- Addr_Mode_1 <= '0'; -- '0';
-- Addr_Mode_0 <= '1'; -- '1';
-- Addr_Bit <= '0'; -- '1';
-- Addr_Phase <= '1'; -- '1';
-- -------------------- --
-- CMD_Mode_1 <= '0'; -- '0'
-- CMD_Mode_0 <= '0'; -- '0';
---------------------------------------------------------------------
-- RECEIVE_DATA_STROBE_PROCESS : Strobe data from shift register to receive
-- data register
--------------------------------
-- For a SCK ratio of 2 the Done needs to be delayed by an extra cycle
-- due to the serial input being captured on the falling edge of the PLB
-- clock. this is purely required for dealing with the real SPI slave memories.
--RECEIVE_DATA_NM_GEN: if C_SPI_MEMORY = 2 and C_SPI_MODE /=0 generate
--begin
-----
RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
receive_Data_int <= (others => '0');
elsif(SPIXfer_done_int_pulse = '1') then
receive_Data_int <= rx_shft_reg_mode_0011;
elsif(SPIXfer_done_int_pulse_d1 = '1') then
receive_Data_int <= receive_Data_int
((C_NUM_TRANSFER_BITS-3) downto 0) &
IO1_I & -- MISO_I - MSB first
IO0_I ; -- MOSI_I
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS;
--end generate RECEIVE_DATA_NM_GEN;
-----------------------------------------------------------------------------
CMD_ADDR_NM_24_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-- CMD_ADDR_CNTR_P: in each SPI transaction, the firs 4 transactions are of
-- CMD, A0, A1, A2. Total 4 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 4 bytes are transferred.
-- below counter is for that purpose only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or (store_last_b4_wrap = '1') then
cmd_addr_cntr <= "000";--(others => '1');
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1')then
cmd_addr_cntr <= "000";
cmd_addr_sent <= store_last_b4_wrap;
elsif(SPIXfer_done_int_pulse_d2 = '1')then
if(cmd_addr_cntr = "101")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
----------------------------
end generate CMD_ADDR_NM_24_BIT_GEN;
------------------------------------
CMD_ADDR_NM_32_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-- CMD_ADDR_CNTR_P: in each SPI transaction, the firs 5 transactions are of
-- CMD, A0, A1, A2, A3. Total 5 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 5 bytes are transferred.
-- below counter is for that purpose only. This is 4 byte addessing mode of NM memory.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or (store_last_b4_wrap = '1') then
cmd_addr_cntr <= "000";--(others => '1');
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1')then
cmd_addr_cntr <= "000";
cmd_addr_sent <= store_last_b4_wrap;
elsif(SPIXfer_done_int_pulse_d2 = '1')then
if(cmd_addr_cntr = "111")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
----------------------------
end generate CMD_ADDR_NM_32_BIT_GEN;
------------------------------------
TWO_BIT_CNTR_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') or (store_last_b4_wrap = '1') then
hw_wd_cntr <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1')then
hw_wd_cntr <= hw_wd_cntr + "01";
end if;
end if;
end process TWO_BIT_CNTR_P;
----------------------------------------------
STORE_RX_DATA_32_BIT_ADDR: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-----
STORE_RX_DATA_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') then
Data_To_Rx_FIFO_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d3 = '1') and (cmd_addr_sent = '1') then
if(one_byte_xfer_to_spi_clk = '1') then
case spi_addr_i(1 downto 0) is
when "00" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 8) &
receive_Data_int;
when "01" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 16)&
receive_Data_int &
Data_To_Rx_FIFO_int(7 downto 0);
when "10" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 24)&
receive_Data_int &
Data_To_Rx_FIFO_int(15 downto 0);
when "11" =>
Data_To_Rx_FIFO_int <= receive_Data_int &
Data_To_Rx_FIFO_int(23 downto 0);
when others => null;
end case;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '0') then -- adjustment for half word
if(spi_addr_i(1) = '0') then
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);-- & receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= receive_Data_int & Data_To_Rx_FIFO_int(15 downto 8);-- & receive_Data_int;
else
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);-- & receive_Data_int;
Data_To_Rx_FIFO_int(31 downto 16)<= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 24);-- & receive_Data_int;
end if;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '1') then -- adjustment for half word
if(hw_wd_cntr = "00") then -- fill in D0
Data_To_Rx_FIFO_int(31 downto 8) <= Data_To_Rx_FIFO_int(31 downto 8);
Data_To_Rx_FIFO_int(7 downto 0) <= receive_Data_int;
elsif(hw_wd_cntr = "01")then -- fill in D1
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);
Data_To_Rx_FIFO_int(15 downto 8) <= receive_Data_int;
Data_To_Rx_FIFO_int(7 downto 0) <= Data_To_Rx_FIFO_int(7 downto 0);
elsif(hw_wd_cntr = "10")then -- fill in D2
Data_To_Rx_FIFO_int(31 downto 24) <= Data_To_Rx_FIFO_int(31 downto 24);
Data_To_Rx_FIFO_int(23 downto 16) <= receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);
else
Data_To_Rx_FIFO_int(31 downto 24) <= receive_Data_int;
Data_To_Rx_FIFO_int(23 downto 0) <= Data_To_Rx_FIFO_int(23 downto 0);
end if;
else -- adjustment for complete word
--Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(23 downto 0) & receive_Data_int;
Data_To_Rx_FIFO_int <= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 8);
end if;
end if;
end if;
end process STORE_RX_DATA_SPI_CLK_P;
end generate STORE_RX_DATA_32_BIT_ADDR;
STORE_RX_DATA_24_BIT_ADDR: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-----
STORE_RX_DATA_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') then
Data_To_Rx_FIFO_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1') then
if(one_byte_xfer_to_spi_clk = '1') then
case spi_addr_i(1 downto 0) is
when "00" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 8) &
receive_Data_int;
when "01" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 16)&
receive_Data_int &
Data_To_Rx_FIFO_int(7 downto 0);
when "10" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 24)&
receive_Data_int &
Data_To_Rx_FIFO_int(15 downto 0);
when "11" =>
Data_To_Rx_FIFO_int <= receive_Data_int &
Data_To_Rx_FIFO_int(23 downto 0);
when others => null;
end case;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '0') then -- adjustment for half word
if(spi_addr_i(1) = '0') then
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);-- & receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= receive_Data_int & Data_To_Rx_FIFO_int(15 downto 8);-- & receive_Data_int;
else
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);-- & receive_Data_int;
Data_To_Rx_FIFO_int(31 downto 16)<= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 24);-- & receive_Data_int;
end if;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '1') then -- adjustment for half word
if(hw_wd_cntr = "00") then -- fill in D0
Data_To_Rx_FIFO_int(31 downto 8) <= Data_To_Rx_FIFO_int(31 downto 8);
Data_To_Rx_FIFO_int(7 downto 0) <= receive_Data_int;
elsif(hw_wd_cntr = "01")then -- fill in D1
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);
Data_To_Rx_FIFO_int(15 downto 8) <= receive_Data_int;
Data_To_Rx_FIFO_int(7 downto 0) <= Data_To_Rx_FIFO_int(7 downto 0);
elsif(hw_wd_cntr = "10")then -- fill in D2
Data_To_Rx_FIFO_int(31 downto 24) <= Data_To_Rx_FIFO_int(31 downto 24);
Data_To_Rx_FIFO_int(23 downto 16) <= receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);
else
Data_To_Rx_FIFO_int(31 downto 24) <= receive_Data_int;
Data_To_Rx_FIFO_int(23 downto 0) <= Data_To_Rx_FIFO_int(23 downto 0);
end if;
else -- adjustment for complete word
--Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(23 downto 0) & receive_Data_int;
Data_To_Rx_FIFO_int <= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 8);
end if;
end if;
end if;
end process STORE_RX_DATA_SPI_CLK_P;
end generate STORE_RX_DATA_24_BIT_ADDR;
----------------------------
Data_To_Rx_FIFO <= Data_To_Rx_FIFO_int;
---------------------------------------
end generate NM_MEM_DUAL_MD_GEN;
SP_MEM_DUAL_MD_GEN: if C_SPI_MEMORY = 3 generate
-----
begin
-----
--wb_hpm_done <= '1';
---- Dual mode command = 0x3B - DOFR
--SPI_cmd <= "00111011";
--------------------------------------------------------
DUAL_SPI_CMD_NM_24_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
-----
begin
-----
---------------------------
SPI_cmd <= "10111011"; -- 0xBB - DIOFR
wb_hpm_done <= '1';
---------------------------
Data_Dir <= '0';-- for BB
Data_Mode_1 <= '0';
Data_Mode_0 <= '1';
Data_Phase <= '1';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '1';
Addr_Bit <= '0';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
---------------------------
end generate DUAL_SPI_CMD_NM_24_GEN;
------------------------------------
DUAL_SPI_CMD_NM_32_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
-----
begin
-----
SPI_cmd <= "10111100"; -- 0xBCh - DIOFR_4Byte
end generate DUAL_SPI_CMD_NM_32_GEN;
------------------------------------
NM_EN_32_ADDR_MD_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-----
nm_wr_en_CMD <= "00000110"; -- 0x06 h Write Enable
nm_4byte_addr_en_CMD <= "10110111"; -- 0xB7 h Enable 4 Byte Addressing Mode
----------------------------------------------------
NM_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
nm_wr_en_cntrl_ps <= NM_WR_EN_IDLE;
wr_en_under_process_d1 <= '0';
wr_en_done_reg <= '0';
else
nm_wr_en_cntrl_ps <= nm_wr_en_cntrl_ns;
wr_en_under_process_d1 <= wr_en_under_process;
wr_en_done_reg <= wr_en_done;
end if;
end if;
end process NM_PS_TO_NS_PROCESS;
----------------------------------
--
NM_WR_EN_CNTRL_PROCESS: process(
nm_wr_en_cntrl_ps ,
--SPIXfer_done_int_pulse,
--SPIXfer_done_int ,
Rst_to_spi ,
SR_5_Tx_Empty ,
wr_en_done_reg
) is
-----
begin
-----
--load_wr_en_cmd <= '0';
--load_wr_sr_cmd <= '0';
--load_wr_sr_d0 <= '0';
--load_wr_sr_d1 <= '0';
load_wr_en <= '0';
wr_en_done <= '0';
wr_en_under_process <= '0';
case nm_wr_en_cntrl_ps is
when NM_WR_EN_IDLE => --load_wr_en_cmd <= '1';
load_wr_en <= '1';
wr_en_under_process <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN;
when NM_WR_EN => if (SR_5_Tx_Empty = '1')then
--wr_en_done <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN_DONE;
else
--wr_en_under_process <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN;
end if;
wr_en_done <= SR_5_Tx_Empty;
wr_en_under_process <= not SR_5_Tx_Empty;
when NM_WR_EN_DONE => if (Rst_to_spi = '1') then
nm_wr_en_cntrl_ns <= NM_WR_EN_IDLE;
else
nm_wr_en_cntrl_ns <= NM_WR_EN_DONE;
end if;
wr_en_done <= wr_en_done_reg;
end case;
end process NM_WR_EN_CNTRL_PROCESS;
----------------------------------------------------
NM_4_BYTE_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
nm_sm_4_byte_addr_ps <= NM_32_BIT_IDLE;
--four_byte_addr_under_process_d1 <= '0';
hpm_under_process_d1 <= '0';
wr_en_done_d1 <= '0';
wr_en_done_d2 <= '0';
wb_hpm_done_reg <= '0';
else
nm_sm_4_byte_addr_ps <= nm_sm_4_byte_addr_ns;
hpm_under_process_d1 <= hpm_under_process;
--four_byte_en_done_reg <= four_byte_en_done;
wr_en_done_d1 <= wr_en_done_reg; -- wr_en_done;
wr_en_done_d2 <= wr_en_done_d1;
wb_hpm_done_reg <= wb_hpm_done;
end if;
end if;
end process NM_4_BYTE_PS_TO_NS_PROCESS;
----------------------------------
--
NM_4_BYTE_ADDR_EN_PROCESS: process(
nm_sm_4_byte_addr_ps ,
Rst_to_spi ,
SR_5_Tx_Empty ,
wr_en_done_d2 ,
wb_hpm_done_reg
) is
-----
begin
-----
-- load_4_byte_addr_en <= '0';
load_wr_hpm <= '0';
wb_hpm_done <= '0';
hpm_under_process <= '0';
four_byte_en_done <= '0';
four_byte_en_under_process <= '0';
case nm_sm_4_byte_addr_ps is
when NM_32_BIT_IDLE => if (wr_en_done_d2 = '1') then
--load_wr_hpm <= '1';
--hpm_under_process <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN;
else
nm_sm_4_byte_addr_ns <= NM_32_BIT_IDLE;
end if;
load_wr_hpm <= wr_en_done_d2;
hpm_under_process <= wr_en_done_d2;
when NM_32_BIT_EN => if (SR_5_Tx_Empty = '1') then
-- wb_hpm_done <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN_DONE;
else
-- hpm_under_process <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN;
end if;
wb_hpm_done <= SR_5_Tx_Empty;
hpm_under_process <= not(SR_5_Tx_Empty);
when NM_32_BIT_EN_DONE => if(Rst_to_spi = '1')then
nm_sm_4_byte_addr_ns <= NM_32_BIT_IDLE;
else
-- if (SR_5_Tx_Empty = '1')then
-- --four_byte_en_done <= '1';
-- wb_hpm_done <= '1';
-- else
-- -- four_byte_en_under_process <= '1';
-- hpm_under_process <= '1';
-- end if;
-- four_byte_en_done <= four_byte_en_done_reg;
-- wb_hpm_done <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN_DONE;
end if;
wb_hpm_done <= wb_hpm_done_reg;
end case;
end process NM_4_BYTE_ADDR_EN_PROCESS;
--------------------------------------
DRIVE_CONTROL_SIG_P: process(EXT_SPI_CLK) is -- wb_hpm_done, wr_en_done_reg) is
variable temp: std_logic_vector(1 downto 0);
begin
temp := wb_hpm_done & wr_en_done_reg;
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
case wb_hpm_done is
-- when "00"|"01" => -- write enable is under process
when '0' => -- write enable and/or Enable 4 byte addressing is under process
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- when "01" => -- Enable 4 byte addressing is under process
-- Data_Dir <= '0';
-- Data_Mode_1 <= '0';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '0';
-- --------------------
-- Quad_Phase <= '0';-- permanent '0'
-- --------------------
-- Addr_Mode_1 <= '0';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '0';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
-- when "10" => -- write enable is done and enable 4 byte addressing is also done
when '1' => -- write enable and enable 4 byte addressing is also done
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '1';
Data_Phase <= '1';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '1';
Addr_Bit <= '1';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage off
when others =>
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage on
end case;
end if;
end process DRIVE_CONTROL_SIG_P;
end generate NM_EN_32_ADDR_MD_GEN;
--------------------------------------
-- -- WB 0011 000 100 0
-- -- NM 0011 000 100 0<-cmd error
-- -- NM 0011 010 100 0<-cmd error -- For 0xbbh DIOFR
-- 0011 011 100 0
-- Data_Dir <= '0';<-- for BB -- '0';<-- for BC
-- Data_Mode_1 <= '0'; -- '0';
-- Data_Mode_0 <= '1'; -- '1';
-- Data_Phase <= '1'; -- '1';
-- -------------------- --
-- Quad_Phase <= '0';-- permanent '0' -- '0';
-- -------------------- --
-- Addr_Mode_1 <= '0'; -- '0';
-- Addr_Mode_0 <= '1'; -- '1';
-- Addr_Bit <= '0'; -- '1';
-- Addr_Phase <= '1'; -- '1';
-- -------------------- --
-- CMD_Mode_1 <= '0'; -- '0'
-- CMD_Mode_0 <= '0'; -- '0';
---------------------------------------------------------------------
-- RECEIVE_DATA_STROBE_PROCESS : Strobe data from shift register to receive
-- data register
--------------------------------
-- For a SCK ratio of 2 the Done needs to be delayed by an extra cycle
-- due to the serial input being captured on the falling edge of the PLB
-- clock. this is purely required for dealing with the real SPI slave memories.
--RECEIVE_DATA_NM_GEN: if C_SPI_MEMORY = 2 and C_SPI_MODE /=0 generate
--begin
-----
RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
receive_Data_int <= (others => '0');
elsif(SPIXfer_done_int_pulse = '1') then
receive_Data_int <= rx_shft_reg_mode_0011;
elsif(SPIXfer_done_int_pulse_d1 = '1') then
receive_Data_int <= receive_Data_int
((C_NUM_TRANSFER_BITS-3) downto 0) &
IO1_I & -- MISO_I - MSB first
IO0_I ; -- MOSI_I
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS;
--end generate RECEIVE_DATA_NM_GEN;
-----------------------------------------------------------------------------
CMD_ADDR_NM_24_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-- CMD_ADDR_CNTR_P: in each SPI transaction, the firs 4 transactions are of
-- CMD, A0, A1, A2. Total 4 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 4 bytes are transferred.
-- below counter is for that purpose only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or (store_last_b4_wrap = '1') then
cmd_addr_cntr <= "000";--(others => '1');
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1')then
cmd_addr_cntr <= "000";
cmd_addr_sent <= store_last_b4_wrap;
elsif(SPIXfer_done_int_pulse_d2 = '1')then
if(cmd_addr_cntr = "100")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
----------------------------
end generate CMD_ADDR_NM_24_BIT_GEN;
------------------------------------
CMD_ADDR_NM_32_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-- CMD_ADDR_CNTR_P: in each SPI transaction, the firs 5 transactions are of
-- CMD, A0, A1, A2, A3. Total 5 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 5 bytes are transferred.
-- below counter is for that purpose only. This is 4 byte addessing mode of NM memory.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or (store_last_b4_wrap = '1') then
cmd_addr_cntr <= "000";--(others => '1');
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1')then
cmd_addr_cntr <= "000";
cmd_addr_sent <= store_last_b4_wrap;
elsif(SPIXfer_done_int_pulse_d2 = '1')then
if(cmd_addr_cntr = "110")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
----------------------------
end generate CMD_ADDR_NM_32_BIT_GEN;
------------------------------------
TWO_BIT_CNTR_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') or (store_last_b4_wrap = '1') then
hw_wd_cntr <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1')then
hw_wd_cntr <= hw_wd_cntr + "01";
end if;
end if;
end process TWO_BIT_CNTR_P;
----------------------------------------------
STORE_RX_DATA_32_BIT_ADDR: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-----
STORE_RX_DATA_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') then
Data_To_Rx_FIFO_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d3 = '1') and (cmd_addr_sent = '1') then
if(one_byte_xfer_to_spi_clk = '1') then
case spi_addr_i(1 downto 0) is
when "00" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 8) &
receive_Data_int;
when "01" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 16)&
receive_Data_int &
Data_To_Rx_FIFO_int(7 downto 0);
when "10" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 24)&
receive_Data_int &
Data_To_Rx_FIFO_int(15 downto 0);
when "11" =>
Data_To_Rx_FIFO_int <= receive_Data_int &
Data_To_Rx_FIFO_int(23 downto 0);
when others => null;
end case;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '0') then -- adjustment for half word
if(spi_addr_i(1) = '0') then
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);-- & receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= receive_Data_int & Data_To_Rx_FIFO_int(15 downto 8);-- & receive_Data_int;
else
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);-- & receive_Data_int;
Data_To_Rx_FIFO_int(31 downto 16)<= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 24);-- & receive_Data_int;
end if;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '1') then -- adjustment for half word
if(hw_wd_cntr = "00") then -- fill in D0
Data_To_Rx_FIFO_int(31 downto 8) <= Data_To_Rx_FIFO_int(31 downto 8);
Data_To_Rx_FIFO_int(7 downto 0) <= receive_Data_int;
elsif(hw_wd_cntr = "01")then -- fill in D1
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);
Data_To_Rx_FIFO_int(15 downto 8) <= receive_Data_int;
Data_To_Rx_FIFO_int(7 downto 0) <= Data_To_Rx_FIFO_int(7 downto 0);
elsif(hw_wd_cntr = "10")then -- fill in D2
Data_To_Rx_FIFO_int(31 downto 24) <= Data_To_Rx_FIFO_int(31 downto 24);
Data_To_Rx_FIFO_int(23 downto 16) <= receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);
else
Data_To_Rx_FIFO_int(31 downto 24) <= receive_Data_int;
Data_To_Rx_FIFO_int(23 downto 0) <= Data_To_Rx_FIFO_int(23 downto 0);
end if;
else -- adjustment for complete word
--Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(23 downto 0) & receive_Data_int;
Data_To_Rx_FIFO_int <= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 8);
end if;
end if;
end if;
end process STORE_RX_DATA_SPI_CLK_P;
end generate STORE_RX_DATA_32_BIT_ADDR;
STORE_RX_DATA_24_BIT_ADDR: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-----
STORE_RX_DATA_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') then
Data_To_Rx_FIFO_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1') then
if(one_byte_xfer_to_spi_clk = '1') then
case spi_addr_i(1 downto 0) is
when "00" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 8) &
receive_Data_int;
when "01" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 16)&
receive_Data_int &
Data_To_Rx_FIFO_int(7 downto 0);
when "10" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 24)&
receive_Data_int &
Data_To_Rx_FIFO_int(15 downto 0);
when "11" =>
Data_To_Rx_FIFO_int <= receive_Data_int &
Data_To_Rx_FIFO_int(23 downto 0);
when others => null;
end case;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '0') then -- adjustment for half word
if(spi_addr_i(1) = '0') then
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);-- & receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= receive_Data_int & Data_To_Rx_FIFO_int(15 downto 8);-- & receive_Data_int;
else
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);-- & receive_Data_int;
Data_To_Rx_FIFO_int(31 downto 16)<= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 24);-- & receive_Data_int;
end if;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '1') then -- adjustment for half word
if(hw_wd_cntr = "00") then -- fill in D0
Data_To_Rx_FIFO_int(31 downto 8) <= Data_To_Rx_FIFO_int(31 downto 8);
Data_To_Rx_FIFO_int(7 downto 0) <= receive_Data_int;
elsif(hw_wd_cntr = "01")then -- fill in D1
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);
Data_To_Rx_FIFO_int(15 downto 8) <= receive_Data_int;
Data_To_Rx_FIFO_int(7 downto 0) <= Data_To_Rx_FIFO_int(7 downto 0);
elsif(hw_wd_cntr = "10")then -- fill in D2
Data_To_Rx_FIFO_int(31 downto 24) <= Data_To_Rx_FIFO_int(31 downto 24);
Data_To_Rx_FIFO_int(23 downto 16) <= receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);
else
Data_To_Rx_FIFO_int(31 downto 24) <= receive_Data_int;
Data_To_Rx_FIFO_int(23 downto 0) <= Data_To_Rx_FIFO_int(23 downto 0);
end if;
else -- adjustment for complete word
--Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(23 downto 0) & receive_Data_int;
Data_To_Rx_FIFO_int <= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 8);
end if;
end if;
end if;
end process STORE_RX_DATA_SPI_CLK_P;
end generate STORE_RX_DATA_24_BIT_ADDR;
----------------------------
Data_To_Rx_FIFO <= Data_To_Rx_FIFO_int;
---------------------------------------
end generate SP_MEM_DUAL_MD_GEN;
end generate DUAL_MODE_CONTROL_GEN;
QUAD_MODE_CONTROL_GEN: if C_SPI_MODE = 2 generate
-----
begin
-----
-- WB 0011 0101 00 0<-cmd error
-- NM 001100101 00 0<-cmd error
WB_MEM_QUAD_MD_GEN:if C_SPI_MEMORY = 1 generate
signal cmd_addr_cntr : std_logic_vector(2 downto 0);
signal hw_wd_cntr : std_logic_vector(1 downto 0);
-----
begin
-----
wb_wr_hpm_CMD <= "10100011"; -- 0xA3 h HPM mode
--
----------------------------------------------------
WB_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
wb_cntrl_ps <= WB_IDLE;
hpm_under_process_d1 <= '0';
else
wb_cntrl_ps <= wb_cntrl_ns;
hpm_under_process_d1 <= hpm_under_process;
end if;
end if;
end process WB_PS_TO_NS_PROCESS;
----------------------------------
--
WB_DUAL_CNTRL_PROCESS: process(
wb_cntrl_ps ,
SPIXfer_done_int_pulse,
SPIXfer_done_int ,
Rst_to_spi ,
SR_5_Tx_Empty
) is
-----
begin
-----
load_wr_en_cmd <= '0';
load_wr_sr_cmd <= '0';
load_wr_sr_d0 <= '0';
load_wr_sr_d1 <= '0';
load_wr_hpm <= '0';
wb_hpm_done <= '0';
hpm_under_process <= '0';
case wb_cntrl_ps is
when WB_IDLE => load_wr_hpm <= '1';
hpm_under_process <= '1';
wb_cntrl_ns <= WB_WR_HPM;
when WB_WR_HPM => if (SR_5_Tx_Empty = '1')then
wb_hpm_done <= '1';
wb_cntrl_ns <= WB_DONE;
else
hpm_under_process <= '1';
wb_cntrl_ns <= WB_WR_HPM;
end if;
when WB_DONE => if (Rst_to_spi = '1') then
wb_cntrl_ns <= WB_IDLE;
else
wb_hpm_done <= '1';
wb_cntrl_ns <= WB_DONE;
end if;
end case;
end process WB_DUAL_CNTRL_PROCESS;
---- Quad mode command = 0x6B - QOFR Read
-- SPI_cmd <= "01101011";
-- 0101 000 100 0
---- Quad mode command = 0xEB - QIOFR Read
SPI_cmd <= "11101011";
-- 0101 100 100 0 -- QUAD_IO_FAST_RD
Data_Dir <= '0';
Data_Mode_1 <= '1';
Data_Mode_0 <= '0';
Data_Phase <= '1';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '1';-- '0' for QOFR and '1' for QIOFR
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
---------------------------------------------------------------------
--RECEIVE_DATA_WB_GEN: if C_SPI_MEMORY = 1 and C_SPI_MODE /=0 generate
--begin
-----
RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
receive_Data_int <= (others => '0');
elsif(SPIXfer_done_int_pulse = '1') then
receive_Data_int <= rx_shft_reg_mode_0011;
elsif(SPIXfer_done_int_pulse_d1 = '1') and (cmd_addr_sent = '1')then
receive_Data_int <= receive_Data_int
((C_NUM_TRANSFER_BITS-5) downto 0) &
IO3_I & -- MSB first
IO2_I &
IO1_I &
IO0_I ;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS;
--end generate RECEIVE_DATA_WB_GEN;
---------------------------------------------------------------------
-- CMD_ADDR_CNTR_P: in each SPI transaction, the firs 4 transactions are of
-- CMD, A0, A1, A2. Total 4 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 4 bytes are transferred.
-- below counter is for that purpose only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or (load_axi_data_to_spi_clk = '1') then
cmd_addr_cntr <= "000";--(others => '1');
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1')then
cmd_addr_cntr <= "000";
cmd_addr_sent <= store_last_b4_wrap;
elsif(SPIXfer_done_int_pulse_d2 = '1')then
if(cmd_addr_cntr = "110")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
----------------------------
TWO_BIT_CNTR_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') or (start_after_wrap = '1') then
hw_wd_cntr <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1')then
hw_wd_cntr <= hw_wd_cntr + "01";
end if;
end if;
end process TWO_BIT_CNTR_P;
STORE_RX_DATA_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') then
Data_To_Rx_FIFO_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1') then
if(one_byte_xfer_to_spi_clk = '1') then
case spi_addr_i(1 downto 0) is
when "00" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 8) &
receive_Data_int;
when "01" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 16)&
receive_Data_int &
Data_To_Rx_FIFO_int(7 downto 0);
when "10" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 24)&
receive_Data_int &
Data_To_Rx_FIFO_int(15 downto 0);
when "11" =>
Data_To_Rx_FIFO_int <= receive_Data_int &
Data_To_Rx_FIFO_int(23 downto 0);
when others => null;
end case;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '0') then -- adjustment for half word
if(spi_addr_i(1) = '0') then
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);-- & receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= receive_Data_int & Data_To_Rx_FIFO_int(15 downto 8);-- & receive_Data_int;
else
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);-- & receive_Data_int;
Data_To_Rx_FIFO_int(31 downto 16)<= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 24);-- & receive_Data_int;
end if;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '1') then -- adjustment for half word
if(hw_wd_cntr = "00") then -- fill in D0
Data_To_Rx_FIFO_int(31 downto 8) <= Data_To_Rx_FIFO_int(31 downto 8);
Data_To_Rx_FIFO_int(7 downto 0) <= receive_Data_int;
elsif(hw_wd_cntr = "01")then -- fill in D1
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);
Data_To_Rx_FIFO_int(15 downto 8) <= receive_Data_int;
Data_To_Rx_FIFO_int(7 downto 0) <= Data_To_Rx_FIFO_int(7 downto 0);
elsif(hw_wd_cntr = "10")then -- fill in D2
Data_To_Rx_FIFO_int(31 downto 24) <= Data_To_Rx_FIFO_int(31 downto 24);
Data_To_Rx_FIFO_int(23 downto 16) <= receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);
else
Data_To_Rx_FIFO_int(31 downto 24) <= receive_Data_int;
Data_To_Rx_FIFO_int(23 downto 0) <= Data_To_Rx_FIFO_int(23 downto 0);
end if;
else -- adjustment for complete word
--Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(23 downto 0) & receive_Data_int;
Data_To_Rx_FIFO_int <= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 8);
end if;
end if;
end if;
end process STORE_RX_DATA_SPI_CLK_P;
----------------------------
Data_To_Rx_FIFO <= Data_To_Rx_FIFO_int;
---------------------------------------
----------------------------
end generate WB_MEM_QUAD_MD_GEN;
-- NM 0011 0 0101 00 0<-cmd error
NM_MEM_QUAD_MD_GEN:if C_SPI_MEMORY = 2 generate
signal cmd_addr_cntr : std_logic_vector(3 downto 0);
signal hw_wd_cntr : std_logic_vector(1 downto 0);
begin
-----
--wb_hpm_done <= '1';
---- Quad mode command = 0x6B - QOFR Read - 0xEBh
--SPI_cmd <= -- "01101011";
-- 0101 1 000100 0
QUAD_SPI_CMD_NM_24_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
SPI_cmd <= "11101011"; -- QIOFR
-- 0101 1 100100 0
wb_hpm_done <= '1';
DRIVE_CONTROL_SIG_P: process(EXT_SPI_CLK, wb_hpm_done, wr_en_done_reg) is -- wb_hpm_done, wr_en_done_reg) is
variable temp: std_logic_vector(1 downto 0);
begin
temp := wb_hpm_done & wr_en_done_reg;
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
case wb_hpm_done is
-- when "00"|"01" => -- write enable is under process
when '0' => -- write enable and/or Enable 4 byte addressing is under process
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- when "01" => -- Enable 4 byte addressing is under process
-- Data_Dir <= '0';
-- Data_Mode_1 <= '0';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '0';
-- --------------------
-- Quad_Phase <= '0';-- permanent '0'
-- --------------------
-- Addr_Mode_1 <= '0';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '0';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
-- when "10" => -- write enable is done and enable 4 byte addressing is also done
when '1' => -- write enable and enable 4 byte addressing is also done
Data_Dir <= '0';
Data_Mode_1 <= '1';
Data_Mode_0 <= '0';
Data_Phase <= '1';
--------------------
Quad_Phase <= '1';-- permanent '0'
--------------------
Addr_Mode_1 <= '1';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage off
when others =>
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage on
end case;
end if;
end process DRIVE_CONTROL_SIG_P;
--------------------------------
end generate QUAD_SPI_CMD_NM_24_GEN;
QUAD_SPI_CMD_NM_32_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
SPI_cmd <= "11101100"; -- QIOFR_4Byte 0xECh
-- 0101 1 100100 0
end generate QUAD_SPI_CMD_NM_32_GEN;
NM_EN_32_ADDR_MD_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-----
nm_wr_en_CMD <= "00000110"; -- 0x06 h Write Enable
nm_4byte_addr_en_CMD <= "10110111"; -- 0xB7 h Enable 4 Byte Addressing Mode
----------------------------------------------------
NM_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
nm_wr_en_cntrl_ps <= NM_WR_EN_IDLE;
wr_en_under_process_d1 <= '0';
wr_en_done_reg <= '0';
else
nm_wr_en_cntrl_ps <= nm_wr_en_cntrl_ns;
wr_en_under_process_d1 <= wr_en_under_process;
wr_en_done_reg <= wr_en_done;
end if;
end if;
end process NM_PS_TO_NS_PROCESS;
----------------------------------
--
NM_WR_EN_CNTRL_PROCESS: process(
nm_wr_en_cntrl_ps ,
--SPIXfer_done_int_pulse,
--SPIXfer_done_int ,
Rst_to_spi ,
SR_5_Tx_Empty ,
wr_en_done_reg
) is
-----
begin
-----
--load_wr_en_cmd <= '0';
--load_wr_sr_cmd <= '0';
--load_wr_sr_d0 <= '0';
--load_wr_sr_d1 <= '0';
load_wr_en <= '0';
wr_en_done <= '0';
wr_en_under_process <= '0';
case nm_wr_en_cntrl_ps is
when NM_WR_EN_IDLE => --load_wr_en_cmd <= '1';
load_wr_en <= '1';
wr_en_under_process <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN;
when NM_WR_EN => if (SR_5_Tx_Empty = '1')then
--wr_en_done <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN_DONE;
else
--wr_en_under_process <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN;
end if;
wr_en_done <= SR_5_Tx_Empty;
wr_en_under_process <= not SR_5_Tx_Empty;
when NM_WR_EN_DONE => if (Rst_to_spi = '1') then
nm_wr_en_cntrl_ns <= NM_WR_EN_IDLE;
else
nm_wr_en_cntrl_ns <= NM_WR_EN_DONE;
end if;
wr_en_done <= wr_en_done_reg;
end case;
end process NM_WR_EN_CNTRL_PROCESS;
----------------------------------------------------
NM_4_BYTE_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
nm_sm_4_byte_addr_ps <= NM_32_BIT_IDLE;
--four_byte_addr_under_process_d1 <= '0';
hpm_under_process_d1 <= '0';
wr_en_done_d1 <= '0';
wr_en_done_d2 <= '0';
wb_hpm_done_reg <= '0';
else
nm_sm_4_byte_addr_ps <= nm_sm_4_byte_addr_ns;
hpm_under_process_d1 <= hpm_under_process;
--four_byte_en_done_reg <= four_byte_en_done;
wr_en_done_d1 <= wr_en_done_reg; -- wr_en_done;
wr_en_done_d2 <= wr_en_done_d1;
wb_hpm_done_reg <= wb_hpm_done;
end if;
end if;
end process NM_4_BYTE_PS_TO_NS_PROCESS;
----------------------------------
--
NM_4_BYTE_ADDR_EN_PROCESS: process(
nm_sm_4_byte_addr_ps ,
Rst_to_spi ,
SR_5_Tx_Empty ,
wr_en_done_d2 ,
wb_hpm_done_reg
) is
-----
begin
-----
-- load_4_byte_addr_en <= '0';
load_wr_hpm <= '0';
wb_hpm_done <= '0';
hpm_under_process <= '0';
four_byte_en_done <= '0';
four_byte_en_under_process <= '0';
case nm_sm_4_byte_addr_ps is
when NM_32_BIT_IDLE => if (wr_en_done_d2 = '1') then
--load_wr_hpm <= '1';
--hpm_under_process <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN;
else
nm_sm_4_byte_addr_ns <= NM_32_BIT_IDLE;
end if;
load_wr_hpm <= wr_en_done_d2;
hpm_under_process <= wr_en_done_d2;
when NM_32_BIT_EN => if (SR_5_Tx_Empty = '1') then
-- wb_hpm_done <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN_DONE;
else
-- hpm_under_process <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN;
end if;
wb_hpm_done <= SR_5_Tx_Empty;
hpm_under_process <= not(SR_5_Tx_Empty);
when NM_32_BIT_EN_DONE => if(Rst_to_spi = '1')then
nm_sm_4_byte_addr_ns <= NM_32_BIT_IDLE;
else
-- if (SR_5_Tx_Empty = '1')then
-- --four_byte_en_done <= '1';
-- wb_hpm_done <= '1';
-- else
-- -- four_byte_en_under_process <= '1';
-- hpm_under_process <= '1';
-- end if;
-- four_byte_en_done <= four_byte_en_done_reg;
-- wb_hpm_done <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN_DONE;
end if;
wb_hpm_done <= wb_hpm_done_reg;
end case;
end process NM_4_BYTE_ADDR_EN_PROCESS;
--------------------------------------
DRIVE_CONTROL_SIG_P: process(EXT_SPI_CLK, wb_hpm_done, wr_en_done_reg) is -- wb_hpm_done, wr_en_done_reg) is
variable temp: std_logic_vector(1 downto 0);
begin
temp := wb_hpm_done & wr_en_done_reg;
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
case wb_hpm_done is
-- when "00"|"01" => -- write enable is under process
when '0' => -- write enable and/or Enable 4 byte addressing is under process
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- when "01" => -- Enable 4 byte addressing is under process
-- Data_Dir <= '0';
-- Data_Mode_1 <= '0';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '0';
-- --------------------
-- Quad_Phase <= '0';-- permanent '0'
-- --------------------
-- Addr_Mode_1 <= '0';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '0';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
-- when "10" => -- write enable is done and enable 4 byte addressing is also done
when '1' => -- write enable and enable 4 byte addressing is also done
Data_Dir <= '0';
Data_Mode_1 <= '1';
Data_Mode_0 <= '0';
Data_Phase <= '1';
--------------------
Quad_Phase <= '1';-- permanent '0'
--------------------
Addr_Mode_1 <= '1';
Addr_Mode_0 <= '0';
Addr_Bit <= '1';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage off
when others =>
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage on
end case;
end if;
end process DRIVE_CONTROL_SIG_P;
--------------------------------
end generate NM_EN_32_ADDR_MD_GEN;
-------------------------------------
-- Data_Dir <= '0';
-- Data_Mode_1 <= '1';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '1';
-- --------------------
-- Quad_Phase <= '1';-- for NM this is 0
-- --------------------
-- Addr_Mode_1 <= '1';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '1';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
---------------------------------------------------------------------
-- RECEIVE_DATA_STROBE_PROCESS : Strobe data from shift register to receive
-- data register
--------------------------------
-- For a SCK ratio of 2 the Done needs to be delayed by an extra cycle
-- due to the serial input being captured on the falling edge of the PLB
-- clock. this is purely required for dealing with the real SPI slave memories.
--RECEIVE_DATA_NM_GEN: if C_SPI_MEMORY = 2 and C_SPI_MODE /=0 generate
--begin
-----
RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
receive_Data_int <= (others => '0');
elsif(SPIXfer_done_int_pulse = '1') then
receive_Data_int <= rx_shft_reg_mode_0011;
elsif(SPIXfer_done_int_pulse_d1 = '1') then
receive_Data_int <= receive_Data_int
((C_NUM_TRANSFER_BITS-5) downto 0) &
IO3_I & -- MSB first
IO2_I &
IO1_I &
IO0_I ;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS;
--end generate RECEIVE_DATA_NM_GEN;
-----------------------------------------------------------------------------
CMD_ADDR_NM_24_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-- CMD_ADDR_CNTR_P: in each SPI transaction, the firs 5 transactions are of
-- CMD, A0, A1, A2. Total 4 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 4 bytes are transferred.
-- below counter is for that purpose only. This is for 24 bit addressing of NM memories only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or
(load_axi_data_to_spi_clk = '1') or
(store_last_b4_wrap = '1') then
cmd_addr_cntr <= "0000";--(others => '1');
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1')then
cmd_addr_cntr <= "0000";
cmd_addr_sent <= store_last_b4_wrap;
elsif(SPIXfer_done_int_pulse_d2 = '1')then
if(cmd_addr_cntr = "1000")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "0001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
end generate CMD_ADDR_NM_24_BIT_GEN;
------------------------------------
CMD_ADDR_NM_32_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-- CMD_ADDR_CNTR_P: in each SPI transaction, the firs 6 transactions are of
-- CMD, A0, A1, A2, A3. Total 5 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 5 bytes are transferred.
-- below counter is for that purpose only. This is for 32 bit addressing of NM memories only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or
(load_axi_data_to_spi_clk = '1') or
(store_last_b4_wrap = '1') then
cmd_addr_cntr <= "0000";--(others => '1');
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1')then
cmd_addr_cntr <= "0000";
cmd_addr_sent <= store_last_b4_wrap;
elsif(SPIXfer_done_int_pulse_d2 = '1')then
if(cmd_addr_cntr = "1001")then -- note the differene in counter value
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "0001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
end generate CMD_ADDR_NM_32_BIT_GEN;
------------------------------------
TWO_BIT_CNTR_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') or (start_after_wrap = '1') then
hw_wd_cntr <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1')then
hw_wd_cntr <= hw_wd_cntr + "01";
end if;
end if;
end process TWO_BIT_CNTR_P;
---------------------------
STORE_RX_DATA_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') then
Data_To_Rx_FIFO_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1') then
if(one_byte_xfer_to_spi_clk = '1') then
case spi_addr_i(1 downto 0) is
when "00" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 8) &
receive_Data_int;
when "01" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 16)&
receive_Data_int &
Data_To_Rx_FIFO_int(7 downto 0);
when "10" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 24)&
receive_Data_int &
Data_To_Rx_FIFO_int(15 downto 0);
when "11" =>
Data_To_Rx_FIFO_int <= receive_Data_int &
Data_To_Rx_FIFO_int(23 downto 0);
when others => null;
end case;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '0') then -- adjustment for half word
if(spi_addr_i(1) = '0') then
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);-- & receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= receive_Data_int & Data_To_Rx_FIFO_int(15 downto 8);-- & receive_Data_int;
else
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);-- & receive_Data_int;
Data_To_Rx_FIFO_int(31 downto 16)<= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 24);-- & receive_Data_int;
end if;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '1') then -- adjustment for half word
if(hw_wd_cntr = "00") then -- fill in D0
Data_To_Rx_FIFO_int(31 downto 8) <= Data_To_Rx_FIFO_int(31 downto 8);
Data_To_Rx_FIFO_int(7 downto 0) <= receive_Data_int;
elsif(hw_wd_cntr = "01")then -- fill in D1
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);
Data_To_Rx_FIFO_int(15 downto 8) <= receive_Data_int;
Data_To_Rx_FIFO_int(7 downto 0) <= Data_To_Rx_FIFO_int(7 downto 0);
elsif(hw_wd_cntr = "10")then -- fill in D2
Data_To_Rx_FIFO_int(31 downto 24) <= Data_To_Rx_FIFO_int(31 downto 24);
Data_To_Rx_FIFO_int(23 downto 16) <= receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);
else
Data_To_Rx_FIFO_int(31 downto 24) <= receive_Data_int;
Data_To_Rx_FIFO_int(23 downto 0) <= Data_To_Rx_FIFO_int(23 downto 0);
end if;
else -- adjustment for complete word
--Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(23 downto 0) & receive_Data_int;
Data_To_Rx_FIFO_int <= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 8);
end if;
end if;
end if;
end process STORE_RX_DATA_SPI_CLK_P;
----------------------------
Data_To_Rx_FIFO <= Data_To_Rx_FIFO_int;
---------------------------------------
--------------------------------
end generate NM_MEM_QUAD_MD_GEN;
--------------------------------
SP_MEM_QUAD_MD_GEN:if C_SPI_MEMORY = 3 generate
signal cmd_addr_cntr : std_logic_vector(3 downto 0);
signal hw_wd_cntr : std_logic_vector(1 downto 0);
begin
-----
--wb_hpm_done <= '1';
---- Quad mode command = 0x6B - QOFR Read - 0xEBh
--SPI_cmd <= -- "01101011";
-- 0101 1 000100 0
QUAD_SPI_CMD_NM_24_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
SPI_cmd <= "11101011"; -- QIOFR
-- 0101 1 100100 0
wb_hpm_done <= '1';
DRIVE_CONTROL_SIG_P: process(EXT_SPI_CLK) is -- wb_hpm_done, wr_en_done_reg) is
variable temp: std_logic_vector(1 downto 0);
begin
temp := wb_hpm_done & wr_en_done_reg;
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
case wb_hpm_done is
-- when "00"|"01" => -- write enable is under process
when '0' => -- write enable and/or Enable 4 byte addressing is under process
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- when "01" => -- Enable 4 byte addressing is under process
-- Data_Dir <= '0';
-- Data_Mode_1 <= '0';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '0';
-- --------------------
-- Quad_Phase <= '0';-- permanent '0'
-- --------------------
-- Addr_Mode_1 <= '0';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '0';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
-- when "10" => -- write enable is done and enable 4 byte addressing is also done
when '1' => -- write enable and enable 4 byte addressing is also done
Data_Dir <= '0';
Data_Mode_1 <= '1';
Data_Mode_0 <= '0';
Data_Phase <= '1';
--------------------
Quad_Phase <= '1';-- permanent '0'
--------------------
Addr_Mode_1 <= '1';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage off
when others =>
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage on
end case;
end if;
end process DRIVE_CONTROL_SIG_P;
--------------------------------
end generate QUAD_SPI_CMD_NM_24_GEN;
QUAD_SPI_CMD_NM_32_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
SPI_cmd <= "11101100"; -- QIOFR_4Byte 0xECh
-- 0101 1 100100 0
end generate QUAD_SPI_CMD_NM_32_GEN;
NM_EN_32_ADDR_MD_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-----
nm_wr_en_CMD <= "00000110"; -- 0x06 h Write Enable
nm_4byte_addr_en_CMD <= "10110111"; -- 0xB7 h Enable 4 Byte Addressing Mode
----------------------------------------------------
NM_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
nm_wr_en_cntrl_ps <= NM_WR_EN_IDLE;
wr_en_under_process_d1 <= '0';
wr_en_done_reg <= '0';
else
nm_wr_en_cntrl_ps <= nm_wr_en_cntrl_ns;
wr_en_under_process_d1 <= wr_en_under_process;
wr_en_done_reg <= wr_en_done;
end if;
end if;
end process NM_PS_TO_NS_PROCESS;
----------------------------------
--
NM_WR_EN_CNTRL_PROCESS: process(
nm_wr_en_cntrl_ps ,
--SPIXfer_done_int_pulse,
--SPIXfer_done_int ,
Rst_to_spi ,
SR_5_Tx_Empty ,
wr_en_done_reg
) is
-----
begin
-----
--load_wr_en_cmd <= '0';
--load_wr_sr_cmd <= '0';
--load_wr_sr_d0 <= '0';
--load_wr_sr_d1 <= '0';
load_wr_en <= '0';
wr_en_done <= '0';
wr_en_under_process <= '0';
case nm_wr_en_cntrl_ps is
when NM_WR_EN_IDLE => --load_wr_en_cmd <= '1';
load_wr_en <= '1';
wr_en_under_process <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN;
when NM_WR_EN => if (SR_5_Tx_Empty = '1')then
--wr_en_done <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN_DONE;
else
--wr_en_under_process <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN;
end if;
wr_en_done <= SR_5_Tx_Empty;
wr_en_under_process <= not SR_5_Tx_Empty;
when NM_WR_EN_DONE => if (Rst_to_spi = '1') then
nm_wr_en_cntrl_ns <= NM_WR_EN_IDLE;
else
nm_wr_en_cntrl_ns <= NM_WR_EN_DONE;
end if;
wr_en_done <= wr_en_done_reg;
end case;
end process NM_WR_EN_CNTRL_PROCESS;
----------------------------------------------------
NM_4_BYTE_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
nm_sm_4_byte_addr_ps <= NM_32_BIT_IDLE;
--four_byte_addr_under_process_d1 <= '0';
hpm_under_process_d1 <= '0';
wr_en_done_d1 <= '0';
wr_en_done_d2 <= '0';
wb_hpm_done_reg <= '0';
else
nm_sm_4_byte_addr_ps <= nm_sm_4_byte_addr_ns;
hpm_under_process_d1 <= hpm_under_process;
--four_byte_en_done_reg <= four_byte_en_done;
wr_en_done_d1 <= wr_en_done_reg; -- wr_en_done;
wr_en_done_d2 <= wr_en_done_d1;
wb_hpm_done_reg <= wb_hpm_done;
end if;
end if;
end process NM_4_BYTE_PS_TO_NS_PROCESS;
----------------------------------
--
NM_4_BYTE_ADDR_EN_PROCESS: process(
nm_sm_4_byte_addr_ps ,
Rst_to_spi ,
SR_5_Tx_Empty ,
wr_en_done_d2 ,
wb_hpm_done_reg
) is
-----
begin
-----
-- load_4_byte_addr_en <= '0';
load_wr_hpm <= '0';
wb_hpm_done <= '0';
hpm_under_process <= '0';
four_byte_en_done <= '0';
four_byte_en_under_process <= '0';
case nm_sm_4_byte_addr_ps is
when NM_32_BIT_IDLE => if (wr_en_done_d2 = '1') then
--load_wr_hpm <= '1';
--hpm_under_process <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN;
else
nm_sm_4_byte_addr_ns <= NM_32_BIT_IDLE;
end if;
load_wr_hpm <= wr_en_done_d2;
hpm_under_process <= wr_en_done_d2;
when NM_32_BIT_EN => if (SR_5_Tx_Empty = '1') then
-- wb_hpm_done <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN_DONE;
else
-- hpm_under_process <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN;
end if;
wb_hpm_done <= SR_5_Tx_Empty;
hpm_under_process <= not(SR_5_Tx_Empty);
when NM_32_BIT_EN_DONE => if(Rst_to_spi = '1')then
nm_sm_4_byte_addr_ns <= NM_32_BIT_IDLE;
else
-- if (SR_5_Tx_Empty = '1')then
-- --four_byte_en_done <= '1';
-- wb_hpm_done <= '1';
-- else
-- -- four_byte_en_under_process <= '1';
-- hpm_under_process <= '1';
-- end if;
-- four_byte_en_done <= four_byte_en_done_reg;
-- wb_hpm_done <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN_DONE;
end if;
wb_hpm_done <= wb_hpm_done_reg;
end case;
end process NM_4_BYTE_ADDR_EN_PROCESS;
--------------------------------------
DRIVE_CONTROL_SIG_P: process(EXT_SPI_CLK) is -- wb_hpm_done, wr_en_done_reg) is
variable temp: std_logic_vector(1 downto 0);
begin
temp := wb_hpm_done & wr_en_done_reg;
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
case wb_hpm_done is
-- when "00"|"01" => -- write enable is under process
when '0' => -- write enable and/or Enable 4 byte addressing is under process
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- when "01" => -- Enable 4 byte addressing is under process
-- Data_Dir <= '0';
-- Data_Mode_1 <= '0';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '0';
-- --------------------
-- Quad_Phase <= '0';-- permanent '0'
-- --------------------
-- Addr_Mode_1 <= '0';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '0';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
-- when "10" => -- write enable is done and enable 4 byte addressing is also done
when '1' => -- write enable and enable 4 byte addressing is also done
Data_Dir <= '0';
Data_Mode_1 <= '1';
Data_Mode_0 <= '0';
Data_Phase <= '1';
--------------------
Quad_Phase <= '1';-- permanent '0'
--------------------
Addr_Mode_1 <= '1';
Addr_Mode_0 <= '0';
Addr_Bit <= '1';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage off
when others =>
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage on
end case;
end if;
end process DRIVE_CONTROL_SIG_P;
--------------------------------
end generate NM_EN_32_ADDR_MD_GEN;
-------------------------------------
-- Data_Dir <= '0';
-- Data_Mode_1 <= '1';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '1';
-- --------------------
-- Quad_Phase <= '1';-- for NM this is 0
-- --------------------
-- Addr_Mode_1 <= '1';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '1';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
---------------------------------------------------------------------
-- RECEIVE_DATA_STROBE_PROCESS : Strobe data from shift register to receive
-- data register
--------------------------------
-- For a SCK ratio of 2 the Done needs to be delayed by an extra cycle
-- due to the serial input being captured on the falling edge of the PLB
-- clock. this is purely required for dealing with the real SPI slave memories.
--RECEIVE_DATA_NM_GEN: if C_SPI_MEMORY = 2 and C_SPI_MODE /=0 generate
--begin
-----
RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
receive_Data_int <= (others => '0');
elsif(SPIXfer_done_int_pulse = '1') then
receive_Data_int <= rx_shft_reg_mode_0011;
elsif(SPIXfer_done_int_pulse_d1 = '1') then
receive_Data_int <= receive_Data_int
((C_NUM_TRANSFER_BITS-5) downto 0) &
IO3_I & -- MSB first
IO2_I &
IO1_I &
IO0_I ;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS;
--end generate RECEIVE_DATA_NM_GEN;
-----------------------------------------------------------------------------
CMD_ADDR_NM_24_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-- CMD_ADDR_CNTR_P: in each SPI transaction, the firs 5 transactions are of
-- CMD, A0, A1, A2. Total 4 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 4 bytes are transferred.
-- below counter is for that purpose only. This is for 24 bit addressing of NM memories only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or
(load_axi_data_to_spi_clk = '1') or
(store_last_b4_wrap = '1') then
cmd_addr_cntr <= "0000";--(others => '1');
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1')then
cmd_addr_cntr <= "0000";
cmd_addr_sent <= store_last_b4_wrap;
elsif(SPIXfer_done_int_pulse_d2 = '1')then
if(cmd_addr_cntr = "0110")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "0001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
end generate CMD_ADDR_NM_24_BIT_GEN;
------------------------------------
CMD_ADDR_NM_32_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-- CMD_ADDR_CNTR_P: in each SPI transaction, the firs 6 transactions are of
-- CMD, A0, A1, A2, A3. Total 5 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 5 bytes are transferred.
-- below counter is for that purpose only. This is for 32 bit addressing of NM memories only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or
(load_axi_data_to_spi_clk = '1') or
(store_last_b4_wrap = '1') then
cmd_addr_cntr <= "0000";--(others => '1');
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1')then
cmd_addr_cntr <= "0000";
cmd_addr_sent <= store_last_b4_wrap;
elsif(SPIXfer_done_int_pulse_d2 = '1')then
if(cmd_addr_cntr = "0111")then -- note the differene in counter value
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "0001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
end generate CMD_ADDR_NM_32_BIT_GEN;
------------------------------------
TWO_BIT_CNTR_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') or (start_after_wrap = '1') then
hw_wd_cntr <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1')then
hw_wd_cntr <= hw_wd_cntr + "01";
end if;
end if;
end process TWO_BIT_CNTR_P;
---------------------------
STORE_RX_DATA_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') then
Data_To_Rx_FIFO_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1') then
if(one_byte_xfer_to_spi_clk = '1') then
case spi_addr_i(1 downto 0) is
when "00" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 8) &
receive_Data_int;
when "01" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 16)&
receive_Data_int &
Data_To_Rx_FIFO_int(7 downto 0);
when "10" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 24)&
receive_Data_int &
Data_To_Rx_FIFO_int(15 downto 0);
when "11" =>
Data_To_Rx_FIFO_int <= receive_Data_int &
Data_To_Rx_FIFO_int(23 downto 0);
when others => null;
end case;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '0') then -- adjustment for half word
if(spi_addr_i(1) = '0') then
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);-- & receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= receive_Data_int & Data_To_Rx_FIFO_int(15 downto 8);-- & receive_Data_int;
else
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);-- & receive_Data_int;
Data_To_Rx_FIFO_int(31 downto 16)<= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 24);-- & receive_Data_int;
end if;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '1') then -- adjustment for half word
if(hw_wd_cntr = "00") then -- fill in D0
Data_To_Rx_FIFO_int(31 downto 8) <= Data_To_Rx_FIFO_int(31 downto 8);
Data_To_Rx_FIFO_int(7 downto 0) <= receive_Data_int;
elsif(hw_wd_cntr = "01")then -- fill in D1
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);
Data_To_Rx_FIFO_int(15 downto 8) <= receive_Data_int;
Data_To_Rx_FIFO_int(7 downto 0) <= Data_To_Rx_FIFO_int(7 downto 0);
elsif(hw_wd_cntr = "10")then -- fill in D2
Data_To_Rx_FIFO_int(31 downto 24) <= Data_To_Rx_FIFO_int(31 downto 24);
Data_To_Rx_FIFO_int(23 downto 16) <= receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);
else
Data_To_Rx_FIFO_int(31 downto 24) <= receive_Data_int;
Data_To_Rx_FIFO_int(23 downto 0) <= Data_To_Rx_FIFO_int(23 downto 0);
end if;
else -- adjustment for complete word
--Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(23 downto 0) & receive_Data_int;
Data_To_Rx_FIFO_int <= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 8);
end if;
end if;
end if;
end process STORE_RX_DATA_SPI_CLK_P;
----------------------------
Data_To_Rx_FIFO <= Data_To_Rx_FIFO_int;
---------------------------------------
--------------------------------
end generate SP_MEM_QUAD_MD_GEN;
end generate QUAD_MODE_CONTROL_GEN;
WRAP_DELAY_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) or (load_axi_data_to_spi_clk = '1') then
wrap_around_d1 <= '0';
wrap_around_d2 <= '0';
wrap_around_d3 <= '0';
--wrap_around_d4 <= '0';
else
wrap_around_d1 <= wrap_around;
wrap_around_d2 <= wrap_around_d1;
wrap_around_d3 <= wrap_around_d2;
--wrap_around_d4 <= wrap_around_d3;
end if;
end if;
end process WRAP_DELAY_P;
wrap_ack <= (not wrap_around_d2) and wrap_around_d1;
wrap_ack_1 <= (not wrap_around_d3) and wrap_around_d2;
start_after_wrap <= wrap_around_d2 and (not wrap_around_d1) and not SR_5_Tx_Empty;
store_last_b4_wrap <= wrap_around_d3 and (not wrap_around_d2);
--xsfer_start_aftr_wrap <= wrap_around_d4 and (not wrap_around_d3);
DELAY_START_AFTR_WRAP:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
start_after_wrap_d1 <= '0';
else
start_after_wrap_d1 <= start_after_wrap;
end if;
end if;
end process DELAY_START_AFTR_WRAP;
----------------------------------
TRANSFER_START_24_BIT_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-----
TRANSFER_START_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
transfer_start <= '0';
elsif(wrap_around = '1') then -- and (actual_SPIXfer_done_int = '1')then
transfer_start <= '0';
elsif(hpm_under_process_d1 = '1' and wb_hpm_done = '1')-- or
--(wr_en_under_process_d1 = '1' and wr_en_done = '1')
then
transfer_start <= '0';
elsif (load_axi_data_to_spi_clk = '1')
or (start_after_wrap_d1 = '1')
or (load_wr_hpm = '1')
--or (load_wr_en = '1')
then
transfer_start <= '1';
elsif(SR_5_Tx_Empty_int = '1') then
transfer_start <= '0';
end if;
end if;
end process TRANSFER_START_P;
end generate TRANSFER_START_24_BIT_ADDR_GEN;
TRANSFER_START_32_BIT_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-----
TRANSFER_START_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
transfer_start <= '0';
elsif(wrap_around = '1') then -- and (actual_SPIXfer_done_int = '1')then
transfer_start <= '0';
elsif(hpm_under_process_d1 = '1' and wb_hpm_done = '1') or
(wr_en_under_process_d1 = '1' and wr_en_done = '1')then
transfer_start <= '0';
elsif(load_axi_data_to_spi_clk = '1') or
(start_after_wrap_d1 = '1') or
(load_wr_hpm = '1') or
(load_wr_en = '1') then
transfer_start <= '1';
elsif(SR_5_Tx_Empty_int = '1') then
transfer_start <= '0';
end if;
end if;
end process TRANSFER_START_P;
end generate TRANSFER_START_32_BIT_ADDR_GEN;
-------------------------------------------------------------------------------
-- TRANSFER_START_1CLK_PROCESS : Delay transfer start by 1 clock cycle
--------------------------------
TRANSFER_START_1CLK_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) or (load_axi_data_to_spi_clk = '1') then
transfer_start_d1 <= '0';
transfer_start_d2 <= '0';
transfer_start_d3 <= '0';
else
transfer_start_d1 <= transfer_start;
transfer_start_d2 <= transfer_start_d1;
transfer_start_d3 <= transfer_start_d2;
end if;
end if;
end process TRANSFER_START_1CLK_PROCESS;
transfer_start_pulse <= --transfer_start and (not transfer_start_d1);
--transfer_start_d2 and (not transfer_start_d3);
transfer_start and (not(transfer_start_d1));
-------------------------------------------------------------------------------
-- TRANSFER_DONE_1CLK_PROCESS : Delay SPI transfer done signal by 1 clock cycle
-------------------------------
TRANSFER_DONE_1CLK_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) or (load_axi_data_to_spi_clk = '1') then
SPIXfer_done_int_d1 <= '0';
else
SPIXfer_done_int_d1 <= SPIXfer_done_int;
end if;
end if;
end process TRANSFER_DONE_1CLK_PROCESS;
--
-- transfer done pulse generating logic
SPIXfer_done_int_pulse <= SPIXfer_done_int and (not(SPIXfer_done_int_d1));
-------------------------------------------------------------------------------
-- TRANSFER_DONE_PULSE_DLY_PROCESS : Delay SPI transfer done pulse by 1 and 2
-- clock cycles
------------------------------------
-- Delay the Done pulse by a further cycle. This is used as the output Rx
-- data strobe when C_SCK_RATIO = 2
TRANSFER_DONE_PULSE_DLY_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) or (load_axi_data_to_spi_clk = '1') then
SPIXfer_done_int_pulse_d1 <= '0';
SPIXfer_done_int_pulse_d2 <= '0';
SPIXfer_done_int_pulse_d3 <= '0';
else
SPIXfer_done_int_pulse_d1 <= SPIXfer_done_int_pulse;
SPIXfer_done_int_pulse_d2 <= SPIXfer_done_int_pulse_d1;
SPIXfer_done_int_pulse_d3 <= SPIXfer_done_int_pulse_d2;
end if;
end if;
end process TRANSFER_DONE_PULSE_DLY_PROCESS;
--------------------------------------------
-------------------------------------------------------------------------------
-- RX_DATA_GEN1: Only for C_SCK_RATIO = 2 mode.
----------------
-- RX_DATA_SCK_RATIO_2_GEN1 : if C_SCK_RATIO = 2 generate
-----
-- begin
-----
-------------------------------------------------------------------------------
-- TRANSFER_DONE_PROCESS : Generate SPI transfer done signal. This will stop the SPI clock.
--------------------------
TRANSFER_DONE_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
SPIXfer_done_int <= '0';
elsif(transfer_start_pulse = '1') then
SPIXfer_done_int <= '0';
else
if(mode_1 = '1' and mode_0 = '0')then
SPIXfer_done_int <= Count(1) and
not(Count(0));
elsif(mode_1 = '0' and mode_0 = '1')then
SPIXfer_done_int <= not(Count(0)) and
Count(2) and
Count(1);
else
SPIXfer_done_int <= --Count(COUNT_WIDTH);
Count(COUNT_WIDTH-1) and
Count(COUNT_WIDTH-2) and
Count(COUNT_WIDTH-3) and
not Count(COUNT_WIDTH-4);
end if;
end if;
end if;
end process TRANSFER_DONE_PROCESS;
-- -- RECEIVE_DATA_STROBE_PROCESS : Strobe data from shift register to receive
-- -- data register
-- --------------------------------
-- -- For a SCK ratio of 2 the Done needs to be delayed by an extra cycle
-- -- due to the serial input being captured on the falling edge of the PLB
-- -- clock. this is purely required for dealing with the real SPI slave memories.
-- RECEIVE_DATA_NM_GEN: if C_SPI_MEMORY = 2 and C_SPI_MODE /=0 generate
-- begin
-- -----
-- RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-- -----
-- begin
-- -----
-- if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
-- if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
-- receive_Data_int <= (others => '0');
-- elsif(SPIXfer_done_int_pulse_d1 = '1') then -- and (cmd_addr_sent = '1')then
-- receive_Data_int <= rx_shft_reg_mode_0011;
-- end if;
-- end if;
-- end process RECEIVE_DATA_STROBE_PROCESS;
-- end generate RECEIVE_DATA_NM_GEN;
-- -----------------------------------------------------------------------------
-- -----------------------------------------------------------------------------
-- RECEIVE_DATA_WB_GEN: if C_SPI_MEMORY = 1 and C_SPI_MODE /=0 generate
-- begin
-- -----
-- RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-- -----
-- begin
-- -----
-- if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
-- if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
-- receive_Data_int <= (others => '0');
-- elsif(SPIXfer_done_int_pulse_d1 = '1') and (cmd_addr_sent = '1')then
-- receive_Data_int <= rx_shft_reg_mode_0011;
-- end if;
-- end if;
-- end process RECEIVE_DATA_STROBE_PROCESS;
-- end generate RECEIVE_DATA_WB_GEN;
-----------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- RATIO_OF_2_GENERATE : Logic to be used when C_SCK_RATIO is equal to 2
------------------------
RATIO_OF_2_GENERATE: if(C_SCK_RATIO = 2) generate
--------------------
---------------attribute IOB : string;
---------------attribute IOB of QSPI_SCK_T : label is "true";
begin
-----
-------------------------------------------------------------------------------
-- SCK_CYCLE_COUNT_PROCESS : Counts number of trigger pulses provided. Used for
-- controlling the number of bits to be transfered
-- based on generic C_NUM_TRANSFER_BITS
----------------------------
RATIO_2_SCK_CYCLE_COUNT_PROCESS: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) or (transfer_start = '0') or (store_last_b4_wrap = '1') then -- (wrap_ack_1 = '1')then
Count <= (others => '0');
elsif(SPIXfer_done_int = '1')then
Count <= (others => '0');
elsif((Count(COUNT_WIDTH) = '0') and
((CPOL_to_spi_clk and CPHA_to_spi_clk) = '0')) then
Count <= Count + 1;
elsif(transfer_start_d2 = '1') and (Count(COUNT_WIDTH) = '0') then
Count <= Count + 1;
end if;
end if;
end process RATIO_2_SCK_CYCLE_COUNT_PROCESS;
------------------------------------
SCK_SET_RESET_32_BIT_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-------------------------------------------------------------------------------
-- SCK_SET_GEN_PROCESS : Generate SET control for SCK_O_reg
------------------------
SCK_SET_GEN_PROCESS: process(CPOL_to_spi_clk,
CPHA_to_spi_clk,
SPIXfer_done_int,
transfer_start_pulse,--,
load_axi_data_to_spi_clk,
wrap_ack_1,
load_wr_hpm,
load_wr_en
) is
-----
begin
-----
if(SPIXfer_done_int = '1')or(load_axi_data_to_spi_clk = '1') or (load_wr_hpm = '1') or (load_wr_en = '1')then
Sync_Set <= (CPOL_to_spi_clk xor CPHA_to_spi_clk);
else
Sync_Set <= '0';
end if;
end process SCK_SET_GEN_PROCESS;
-------------------------------------------------------------------------------
-- SCK_RESET_GEN_PROCESS : Generate SET control for SCK_O_reg
--------------------------
SCK_RESET_GEN_PROCESS: process(CPOL_to_spi_clk,
CPHA_to_spi_clk,
transfer_start_pulse,
SPIXfer_done_int,
load_axi_data_to_spi_clk,
load_wr_hpm,
load_wr_en
)is
-----
begin
-----
if(SPIXfer_done_int = '1')or(load_axi_data_to_spi_clk = '1')or(load_wr_hpm = '1') or (load_wr_en = '1') then
Sync_Reset <= not(CPOL_to_spi_clk xor CPHA_to_spi_clk);
else
Sync_Reset <= '0';
end if;
end process SCK_RESET_GEN_PROCESS;
end generate SCK_SET_RESET_32_BIT_ADDR_GEN;
-------------------------------------------
SCK_SET_RESET_24_BIT_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-------------------------------------------------------------------------------
-- SCK_SET_GEN_PROCESS : Generate SET control for SCK_O_reg
------------------------
SCK_SET_GEN_PROCESS: process(CPOL_to_spi_clk,
CPHA_to_spi_clk,
SPIXfer_done_int,
transfer_start_pulse,--,
load_axi_data_to_spi_clk,
wrap_ack_1,
load_wr_hpm--,
--load_wr_en
) is
-----
begin
-----
if(SPIXfer_done_int = '1')or(load_axi_data_to_spi_clk = '1') or (load_wr_hpm = '1')
--or (load_wr_en = '1')
then
Sync_Set <= (CPOL_to_spi_clk xor CPHA_to_spi_clk);
else
Sync_Set <= '0';
end if;
end process SCK_SET_GEN_PROCESS;
-------------------------------------------------------------------------------
-- SCK_RESET_GEN_PROCESS : Generate SET control for SCK_O_reg
--------------------------
SCK_RESET_GEN_PROCESS: process(CPOL_to_spi_clk,
CPHA_to_spi_clk,
transfer_start_pulse,
SPIXfer_done_int,
load_axi_data_to_spi_clk,
load_wr_hpm--,
--load_wr_en
)is
-----
begin
-----
if(SPIXfer_done_int = '1')or(load_axi_data_to_spi_clk = '1')or(load_wr_hpm = '1')
--or (load_wr_en = '1')
then
Sync_Reset <= not(CPOL_to_spi_clk xor CPHA_to_spi_clk);
else
Sync_Reset <= '0';
end if;
end process SCK_RESET_GEN_PROCESS;
end generate SCK_SET_RESET_24_BIT_ADDR_GEN;
-------------------------------------------
-------------------------------------------------------------------------------
-- SCK_SET_RESET_PROCESS : Sync set/reset toggle flip flop controlled by
-- transfer_start signal
--------------------------
RATIO_2_SCK_SET_RESET_PROCESS: process(EXT_SPI_CLK)
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if((Rst_to_spi = RESET_ACTIVE) or (Sync_Reset = '1') or
(new_tr = '0') or (wrap_ack_1 = '1')) then
sck_o_int <= '0';
elsif(Sync_Set = '1') then
sck_o_int <= '1';
elsif (transfer_start = '1') then
sck_o_int <= (not sck_o_int);
end if;
end if;
end process RATIO_2_SCK_SET_RESET_PROCESS;
----------------------------------
-- DELAY_CLK: Delay the internal clock for a cycle to generate internal enable
-- -- signal for data register.
-------------
RATIO_2_DELAY_CLK: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if (Rst_to_spi = RESET_ACTIVE)then
sck_d1 <= '0';
sck_d2 <= '0';
else
sck_d1 <= sck_o_int;
sck_d2 <= sck_d1;
end if;
end if;
end process RATIO_2_DELAY_CLK;
------------------------------------
-- Rising egde pulse
sck_rising_edge <= sck_d2 and (not sck_d1);
-- CAPT_RX_FE_MODE_00_11: The below logic is to capture data for SPI mode of
--------------------------- 00 and 11.
-- Generate a falling edge pulse from the serial clock. Use this to
-- capture the incoming serial data into a shift register.
RATIO_2_CAPT_RX_FE_MODE_00_11 : process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then -- SPIXfer_done_int_pulse_d2
if (Rst_to_spi = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
rx_shft_reg_mode_0011 <= (others => '0');
elsif((sck_d2='0') and --(sck_rising_edge = '1') and
(Data_Dir='0') -- data direction = 0 is read mode
)then
-------
if(mode_1 = '0' and mode_0 = '0')then -- for Standard transfer
rx_shft_reg_mode_0011 <= rx_shft_reg_mode_0011
(1 to (C_NUM_TRANSFER_BITS-1)) &
IO1_I ; --MISO_I;
elsif(mode_1 = '0' and mode_0 = '1')then -- for Dual transfer
rx_shft_reg_mode_0011 <= rx_shft_reg_mode_0011
(2 to (C_NUM_TRANSFER_BITS-1)) &
IO1_I & -- MISO_I - MSB first
IO0_I ; -- MOSI_I
elsif(mode_1 = '1' and mode_0 = '0')then -- for Quad transfer
rx_shft_reg_mode_0011 <= rx_shft_reg_mode_0011
(4 to (C_NUM_TRANSFER_BITS-1)) &
IO3_I & -- MSB first
IO2_I &
IO1_I &
IO0_I ;
end if;
-------
else
rx_shft_reg_mode_0011<= rx_shft_reg_mode_0011;
end if;
end if;
end process RATIO_2_CAPT_RX_FE_MODE_00_11;
----------------------------------
QSPI_NM_MEM_DATA_CAP_GEN: if (C_SPI_MODE = 0 and (C_SPI_MEMORY = 0 or
C_SPI_MEMORY = 2))
or
(
( C_SPI_MODE = 1
or
C_SPI_MODE = 2
)
and
C_SPI_MEMORY = 2
)generate
--------------------------------------
begin
-----
-------------------------------------------------------------------------------
-- CAPTURE_AND_SHIFT_PROCESS : This logic essentially controls the entire
-- capture and shift operation for serial data in
------------------------------ master SPI mode only
RATIO_2_CAPTURE_AND_SHIFT_PROCESS: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
Shift_Reg(0 to C_NUM_TRANSFER_BITS -1) <= (others => '0');
Serial_Dout_0 <= '0';-- default values of the IO0_O
Serial_Dout_1 <= '0';
Serial_Dout_2 <= '0';
Serial_Dout_3 <= '0';
elsif(transfer_start = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1') then --
--if(Load_tx_data_to_shift_reg_int = '1') then
Shift_Reg <= Transmit_Data;
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Transmit_Data(0);
Serial_Dout_3 <= Quad_Phase;--pr_state_cmd_ph and Quad_Phase;-- this is to make the DQ3 bit 1 in quad command transfer mode.
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Transmit_Data(0); -- msb to IO1_O
Serial_Dout_0 <= Transmit_Data(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Transmit_Data(0); -- msb to IO3_O
Serial_Dout_2 <= Transmit_Data(1);
Serial_Dout_1 <= Transmit_Data(2);
Serial_Dout_0 <= Transmit_Data(3);
end if;
elsif(
(Count(0) = '0')
)then -- Shift Data on even
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Shift_Reg(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Shift_Reg(0); -- msb to IO1_O
Serial_Dout_0 <= Shift_Reg(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Shift_Reg(0); -- msb to IO3_O
Serial_Dout_2 <= Shift_Reg(1);
Serial_Dout_1 <= Shift_Reg(2);
Serial_Dout_0 <= Shift_Reg(3);
end if;
elsif(
(Count(0) = '1') --and
) then -- Capture Data on odd
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Shift_Reg <= Shift_Reg
(1 to C_NUM_TRANSFER_BITS -1) &
IO1_I ;-- MISO_I;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Shift_Reg <= Shift_Reg
(2 to C_NUM_TRANSFER_BITS -1) &
IO1_I &
IO0_I ;
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Shift_Reg <= Shift_Reg
(4 to C_NUM_TRANSFER_BITS -1) &
IO3_I &
IO2_I &
IO1_I &
IO0_I ;
end if;
end if;
end if;
end if;
end process RATIO_2_CAPTURE_AND_SHIFT_PROCESS;
----------------------------------------------
end generate QSPI_NM_MEM_DATA_CAP_GEN;
----------------------------------
QSPI_SP_MEM_DATA_CAP_GEN: if (C_SPI_MODE = 0 and (C_SPI_MEMORY = 0 or
C_SPI_MEMORY = 3))
or
(
( C_SPI_MODE = 1
or
C_SPI_MODE = 2
)
and
C_SPI_MEMORY = 3
)generate
--------------------------------------
begin
-----
-------------------------------------------------------------------------------
-- CAPTURE_AND_SHIFT_PROCESS : This logic essentially controls the entire
-- capture and shift operation for serial data in
------------------------------ master SPI mode only
RATIO_2_CAPTURE_AND_SHIFT_PROCESS: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
Shift_Reg(0 to C_NUM_TRANSFER_BITS -1) <= (others => '0');
Serial_Dout_0 <= '0';-- default values of the IO0_O
Serial_Dout_1 <= '0';
Serial_Dout_2 <= '0';
Serial_Dout_3 <= '0';
elsif(transfer_start = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1') then --
--if(Load_tx_data_to_shift_reg_int = '1') then
Shift_Reg <= Transmit_Data;
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Transmit_Data(0);
Serial_Dout_3 <= Quad_Phase;--pr_state_cmd_ph and Quad_Phase;-- this is to make the DQ3 bit 1 in quad command transfer mode.
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Transmit_Data(0); -- msb to IO1_O
Serial_Dout_0 <= Transmit_Data(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Transmit_Data(0); -- msb to IO3_O
Serial_Dout_2 <= Transmit_Data(1);
Serial_Dout_1 <= Transmit_Data(2);
Serial_Dout_0 <= Transmit_Data(3);
end if;
elsif(
(Count(0) = '0')
)then -- Shift Data on even
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Shift_Reg(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Shift_Reg(0); -- msb to IO1_O
Serial_Dout_0 <= Shift_Reg(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Shift_Reg(0); -- msb to IO3_O
Serial_Dout_2 <= Shift_Reg(1);
Serial_Dout_1 <= Shift_Reg(2);
Serial_Dout_0 <= Shift_Reg(3);
end if;
elsif(
(Count(0) = '1') --and
) then -- Capture Data on odd
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Shift_Reg <= Shift_Reg
(1 to C_NUM_TRANSFER_BITS -1) &
IO1_I ;-- MISO_I;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Shift_Reg <= Shift_Reg
(2 to C_NUM_TRANSFER_BITS -1) &
IO1_I &
IO0_I ;
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Shift_Reg <= Shift_Reg
(4 to C_NUM_TRANSFER_BITS -1) &
IO3_I &
IO2_I &
IO1_I &
IO0_I ;
end if;
end if;
end if;
end if;
end process RATIO_2_CAPTURE_AND_SHIFT_PROCESS;
----------------------------------------------
end generate QSPI_SP_MEM_DATA_CAP_GEN;
----------------------------------
QSPI_WINBOND_MEM_DATA_CAP_GEN: if (
(C_SPI_MODE = 0 and (C_SPI_MEMORY = 0 or
C_SPI_MEMORY = 1))
or
(
( C_SPI_MODE = 1
or
C_SPI_MODE = 2
)
and
C_SPI_MEMORY = 1
)) generate
-----------------------------------------
begin
-----
-------------------------------------------------------------------------------
-- CAPTURE_AND_SHIFT_PROCESS : This logic essentially controls the entire
-- capture and shift operation for serial data in
------------------------------ master SPI mode only
RATIO_2_CAPTURE_AND_SHIFT_PROCESS: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
Shift_Reg(0 to C_NUM_TRANSFER_BITS -1) <= (others => '0');
Serial_Dout_0 <= '0';-- default values of the IO0_O
Serial_Dout_1 <= '0';
Serial_Dout_2 <= '0';
Serial_Dout_3 <= '0';
elsif(transfer_start = '1') then
--if(Load_tx_data_to_shift_reg_int = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1') then --
Shift_Reg <= Transmit_Data;
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Transmit_Data(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;-- this is to make the DQ3 bit 1 in quad command transfer mode.
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Transmit_Data(0); -- msb to IO1_O
Serial_Dout_0 <= Transmit_Data(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Transmit_Data(0); -- msb to IO3_O
Serial_Dout_2 <= Transmit_Data(1);
Serial_Dout_1 <= Transmit_Data(2);
Serial_Dout_0 <= Transmit_Data(3);
end if;
elsif(
(Count(0) = '0') --and
)then -- Shift Data on even
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Shift_Reg(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Shift_Reg(0); -- msb to IO1_O
Serial_Dout_0 <= Shift_Reg(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Shift_Reg(0); -- msb to IO3_O
Serial_Dout_2 <= Shift_Reg(1);
Serial_Dout_1 <= Shift_Reg(2);
Serial_Dout_0 <= Shift_Reg(3);
end if;
elsif(
(Count(0) = '1') --and
) then -- Capture Data on odd
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Shift_Reg <= Shift_Reg
(1 to C_NUM_TRANSFER_BITS -1) &
IO1_I;-- MISO_I;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Shift_Reg <= Shift_Reg
(2 to C_NUM_TRANSFER_BITS -1) &
IO1_I &
IO0_I ;
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Shift_Reg <= Shift_Reg
(4 to C_NUM_TRANSFER_BITS -1) &
IO3_I &
IO2_I &
IO1_I &
IO0_I ;
end if;
end if;
end if;
end if;
end process RATIO_2_CAPTURE_AND_SHIFT_PROCESS;
----------------------------------------------
end generate QSPI_WINBOND_MEM_DATA_CAP_GEN;
------------------------------------------------------
--------------------------------
XIP_STD_DUAL_MODE_WB_MEM_GEN: if (
(C_SPI_MODE = 0 or C_SPI_MODE = 1) and
(
(C_SPI_MEMORY = 1 or C_SPI_MEMORY = 0)
)
)generate
--------------------------------
begin
-----
--------------------------------------------------
PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
qspi_cntrl_ps <= IDLE;
stop_clock_reg <= '0';
else
qspi_cntrl_ps <= qspi_cntrl_ns;
stop_clock_reg <= stop_clock;
end if;
end if;
end process PS_TO_NS_PROCESS;
-----------------------------
pr_state_data_receive <= '1' when qspi_cntrl_ps = DATA_RECEIVE else
'0';
pr_state_non_idle <= '1' when qspi_cntrl_ps /= IDLE else
'0';
pr_state_idle <= '1' when qspi_cntrl_ps = IDLE else
'0';
pr_state_cmd_ph <= '1' when qspi_cntrl_ps = CMD_SEND else
'0';
QSPI_CNTRL_PROCESS: process(
---------------------
new_tr ,
CMD_Mode_1 ,
CMD_Mode_0 ,
---------------------
Addr_Phase ,
Addr_Bit ,
Addr_Mode_1 ,
Addr_Mode_0 ,
---------------------
Data_Phase ,
Data_Dir ,
Data_Mode_1 ,
Data_Mode_0 ,
---------------------
addr_cnt ,
Quad_Phase ,
---------------------
SR_5_Tx_Empty ,
SPIXfer_done_int_pulse,
stop_clock_reg,
---------------------
qspi_cntrl_ps ,
no_slave_selected ,
---------------------
wrap_around ,
transfer_start ,
wrap_ack_1 ,
wb_hpm_done ,
hpm_under_process_d1
)is
-----
begin
-----
mode_1 <= '0';
mode_0 <= '0';
--------------
IO0_T_control <= '1';
IO1_T_control <= '1';
-------------
stop_clock <= '0';
-------------
rst_wrap_around <= '0';
-------------
case qspi_cntrl_ps is
when IDLE => if((SR_5_Tx_Empty = '0') and -- this will be used specially in case of WRAP transactions
(transfer_start = '1')and
(new_tr = '1')
)then
IO0_T_control <= CMD_Mode_0;
IO3_T_control <= not Quad_Phase;--
qspi_cntrl_ns <= CMD_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
stop_clock <= '1';
------------------------------------------------
when CMD_SEND => mode_1 <= CMD_Mode_1;
mode_0 <= CMD_Mode_0;
IO0_T_control <= CMD_Mode_0;
IO1_T_control <= (CMD_Mode_1) or (not CMD_Mode_0);
if(SPIXfer_done_int_pulse = '1')then
if(hpm_under_process_d1 = '1')then
qspi_cntrl_ns <= HPM_DUMMY;
elsif(Addr_Phase='1')then
qspi_cntrl_ns <= ADDR_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
else
qspi_cntrl_ns <= CMD_SEND;
end if;
------------------------------------------------
when HPM_DUMMY => IO0_T_control <= CMD_Mode_0;
IO1_T_control <= (CMD_Mode_1) or (not CMD_Mode_0);
if(SR_5_Tx_Empty='1') then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= HPM_DUMMY;
end if;
------------------------------------------------
when ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);-- (Addr_Mode_1) or(not Addr_Mode_0);
--stop_clock <= not SR_5_Tx_Empty;
if((SR_5_Tx_Empty='1') and
(Data_Phase='0')
) or (wrap_ack_1 = '1') then
if (no_slave_selected = '1') or (wrap_ack_1 = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
if(
(addr_cnt = "011") and -- 24 bit address
(Addr_Bit='0') and (Data_Phase='1')
)then
IO0_T_control <= '1';
IO1_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
end if;
------------------------------------------------
when TEMP_ADDR_SEND =>
mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);-- (Addr_Mode_1) or(not Addr_Mode_0);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= ADDR_SEND;
end if;
when DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
if(SR_5_Tx_Empty='1') or (wrap_ack_1 = '1')then
rst_wrap_around <= '1';
if(no_slave_selected = '1') or
(wrap_around = '1')then
qspi_cntrl_ns <= IDLE;
stop_clock <= wrap_ack_1;
else
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
when TEMP_DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
-- coverage off
when others => qspi_cntrl_ns <= IDLE;
------------------------------------------------
-- coverage on
end case;
-------------------------------
end process QSPI_CNTRL_PROCESS;
-------------------------------
pr_state_addr_ph <= '1' when (qspi_cntrl_ps = ADDR_SEND) else
'0';
QSPI_ADDR_CNTR_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(pr_state_addr_ph = '0') then
addr_cnt <= (others => '0');
elsif(pr_state_addr_ph = '1')then
addr_cnt <= addr_cnt + SPIXfer_done_int_pulse;
end if;
end if;
end process QSPI_ADDR_CNTR_PROCESS;
-----------------------------------
end generate XIP_STD_DUAL_MODE_WB_MEM_GEN;
------------------------------------------
--------------------------------------------------
XIP_STD_DUAL_MODE_NM_MEM_GEN: if ((C_SPI_MODE = 1 or C_SPI_MODE = 0) and
(C_SPI_MEMORY = 2 or C_SPI_MEMORY = 0)
)generate
-------------------
begin
-----
--------------------------------------------------
PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
qspi_cntrl_ps <= IDLE;
stop_clock_reg <= '0';
else
qspi_cntrl_ps <= qspi_cntrl_ns;
stop_clock_reg <= stop_clock;
end if;
end if;
end process PS_TO_NS_PROCESS;
-----------------------------
pr_state_data_receive <= '1' when qspi_cntrl_ps = DATA_RECEIVE else
'0';
pr_state_non_idle <= '1' when qspi_cntrl_ps /= IDLE else
'0';
pr_state_idle <= '1' when qspi_cntrl_ps = IDLE else
'0';
pr_state_cmd_ph <= '1' when qspi_cntrl_ps = CMD_SEND else
'0';
QSPI_CNTRL_PROCESS: process(
---------------------
--CMD_decoded ,
new_tr,
CMD_Mode_1 ,
CMD_Mode_0 ,
--CMD_Error ,
---------------------
Addr_Phase ,
Addr_Bit ,
Addr_Mode_1 ,
Addr_Mode_0 ,
---------------------
Data_Phase ,
Data_Dir ,
Data_Mode_1 ,
Data_Mode_0 ,
---------------------
addr_cnt ,
---------------------
SR_5_Tx_Empty ,SPIXfer_done_int_pulse,
stop_clock_reg,
no_slave_selected ,
---------------------
qspi_cntrl_ps ,
---------------------
wrap_around ,
transfer_start ,
Quad_Phase ,
wrap_ack_1
)is
-----
begin
-----
mode_1 <= '0';
mode_0 <= '0';
--------------
IO0_T_control <= '1';
IO1_T_control <= '1';
--------------
stop_clock <= '0';
--------------
rst_wrap_around <= '0';
--------------
case qspi_cntrl_ps is
when IDLE => if((SR_5_Tx_Empty = '0') and -- this will be used specially in case of WRAP transactions
(transfer_start = '1')and
(new_tr = '1')
)then
IO0_T_control <= CMD_Mode_0;
IO3_T_control <= not Quad_Phase;--
qspi_cntrl_ns <= CMD_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
stop_clock <= '1';
------------------------------------------------
when CMD_SEND => mode_1 <= CMD_Mode_1;
mode_0 <= CMD_Mode_0;
IO0_T_control <= CMD_Mode_1;
--if(SPIXfer_done_int_pulse_d2 = '1')then
if(SPIXfer_done_int_pulse = '1')then
if(Addr_Phase='1')then
qspi_cntrl_ns <= ADDR_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
else
qspi_cntrl_ns <= CMD_SEND;
end if;
------------------------------------------------
when ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0);
--stop_clock <= SR_5_Tx_Empty;
if(((SR_5_Tx_Empty='1') and
(Data_Phase='0')) or (wrap_ack_1 = '1')
)then
if (no_slave_selected = '1') or (wrap_ack_1 = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
if(
(addr_cnt = "011") and -- 24 bit address
(Addr_Bit='0') and (Data_Phase='1')
)then
if((Data_Dir='1'))then
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= Data_Mode_1;
IO1_T_control <= not(Data_Mode_0);
qspi_cntrl_ns <= DATA_SEND; -- o/p
else
IO0_T_control <= '1';
IO1_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
end if;
elsif(
(addr_cnt = "100") and -- 32 bit
(Addr_Bit = '1') and (Data_Phase='1')
) then
--if((Data_Dir='1'))then
-- qspi_cntrl_ns <= DATA_SEND; -- o/p
--else
IO0_T_control <= '1';
IO1_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
--end if;
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
end if;
-- ------------------------------------------------
when TEMP_ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);-- (Addr_Mode_1) or(not Addr_Mode_0);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= ADDR_SEND;
end if;
when DATA_SEND => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= Data_Mode_1;
IO1_T_control <= not(Data_Mode_0);
--stop_clock <= SR_5_Tx_Empty;
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
------------------------------------------------
when TEMP_DATA_SEND =>
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= Data_Mode_1;
IO1_T_control <= not(Data_Mode_0);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_SEND;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_SEND;
end if;
when DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1') or (wrap_ack_1 = '1')then
rst_wrap_around <= wrap_ack_1;
if(no_slave_selected = '1') or (wrap_ack_1 = '1')then
stop_clock <= wrap_ack_1;
qspi_cntrl_ns <= IDLE;
else
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
when TEMP_DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
-- coverage off
when others => qspi_cntrl_ns <= IDLE;
------------------------------------------------
-- coverage on
end case;
-------------------------------
end process QSPI_CNTRL_PROCESS;
-------------------------------
pr_state_addr_ph <= '1' when qspi_cntrl_ps = ADDR_SEND else
'0';
QSPI_ADDR_CNTR_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(pr_state_addr_ph = '0') then
addr_cnt <= (others => '0');
elsif(pr_state_addr_ph = '1')then
addr_cnt <= addr_cnt + SPIXfer_done_int_pulse;
end if;
end if;
end process QSPI_ADDR_CNTR_PROCESS;
-----------------------------------
end generate XIP_STD_DUAL_MODE_NM_MEM_GEN;
--------------------------------
--------------------------------------------------
XIP_STD_DUAL_MODE_SP_MEM_GEN: if ((C_SPI_MODE = 1 or C_SPI_MODE = 0) and
(C_SPI_MEMORY = 3 or C_SPI_MEMORY = 0)
)generate
-------------------
begin
-----
--------------------------------------------------
PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
qspi_cntrl_ps <= IDLE;
stop_clock_reg <= '0';
else
qspi_cntrl_ps <= qspi_cntrl_ns;
stop_clock_reg <= stop_clock;
end if;
end if;
end process PS_TO_NS_PROCESS;
-----------------------------
pr_state_data_receive <= '1' when qspi_cntrl_ps = DATA_RECEIVE else
'0';
pr_state_non_idle <= '1' when qspi_cntrl_ps /= IDLE else
'0';
pr_state_idle <= '1' when qspi_cntrl_ps = IDLE else
'0';
pr_state_cmd_ph <= '1' when qspi_cntrl_ps = CMD_SEND else
'0';
QSPI_CNTRL_PROCESS: process(
---------------------
--CMD_decoded ,
new_tr,
CMD_Mode_1 ,
CMD_Mode_0 ,
--CMD_Error ,
---------------------
Addr_Phase ,
Addr_Bit ,
Addr_Mode_1 ,
Addr_Mode_0 ,
---------------------
Data_Phase ,
Data_Dir ,
Data_Mode_1 ,
Data_Mode_0 ,
---------------------
addr_cnt ,
---------------------
SR_5_Tx_Empty ,SPIXfer_done_int_pulse,
stop_clock_reg,
no_slave_selected ,
---------------------
qspi_cntrl_ps ,
---------------------
wrap_around ,
transfer_start ,
wrap_ack_1
)is
-----
begin
-----
mode_1 <= '0';
mode_0 <= '0';
--------------
IO0_T_control <= '1';
IO1_T_control <= '1';
--------------
stop_clock <= '0';
--------------
rst_wrap_around <= '0';
--------------
case qspi_cntrl_ps is
when IDLE => if((SR_5_Tx_Empty = '0') and -- this will be used specially in case of WRAP transactions
(transfer_start = '1')and
(new_tr = '1')
)then
IO0_T_control <= CMD_Mode_0;
IO3_T_control <= not Quad_Phase;--
qspi_cntrl_ns <= CMD_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
stop_clock <= '1';
------------------------------------------------
when CMD_SEND => mode_1 <= CMD_Mode_1;
mode_0 <= CMD_Mode_0;
IO0_T_control <= CMD_Mode_1;
--if(SPIXfer_done_int_pulse_d2 = '1')then
if(SPIXfer_done_int_pulse = '1')then
if(Addr_Phase='1')then
qspi_cntrl_ns <= ADDR_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
else
qspi_cntrl_ns <= CMD_SEND;
end if;
------------------------------------------------
when ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0);
--stop_clock <= SR_5_Tx_Empty;
if(((SR_5_Tx_Empty='1') and
(Data_Phase='0')) or (wrap_ack_1 = '1')
)then
if (no_slave_selected = '1') or (wrap_ack_1 = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
if(
(addr_cnt = "011") and -- 24 bit address
(Addr_Bit='0') and (Data_Phase='1')
)then
if((Data_Dir='1'))then
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= Data_Mode_1;
IO1_T_control <= not(Data_Mode_0);
qspi_cntrl_ns <= DATA_SEND; -- o/p
else
IO0_T_control <= '1';
IO1_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
end if;
elsif(
(addr_cnt = "100") and -- 32 bit
(Addr_Bit = '1') and (Data_Phase='1')
) then
--if((Data_Dir='1'))then
-- qspi_cntrl_ns <= DATA_SEND; -- o/p
--else
IO0_T_control <= '1';
IO1_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
--end if;
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
end if;
-- ------------------------------------------------
when TEMP_ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);-- (Addr_Mode_1) or(not Addr_Mode_0);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= ADDR_SEND;
end if;
when DATA_SEND => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= Data_Mode_1;
IO1_T_control <= not(Data_Mode_0);
--stop_clock <= SR_5_Tx_Empty;
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
------------------------------------------------
when TEMP_DATA_SEND =>
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= Data_Mode_1;
IO1_T_control <= not(Data_Mode_0);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_SEND;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_SEND;
end if;
when DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1') or (wrap_ack_1 = '1')then
rst_wrap_around <= wrap_ack_1;
if(no_slave_selected = '1') or (wrap_ack_1 = '1')then
stop_clock <= wrap_ack_1;
qspi_cntrl_ns <= IDLE;
else
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
when TEMP_DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
-- coverage off
when others => qspi_cntrl_ns <= IDLE;
------------------------------------------------
-- coverage on
end case;
-------------------------------
end process QSPI_CNTRL_PROCESS;
-------------------------------
pr_state_addr_ph <= '1' when qspi_cntrl_ps = ADDR_SEND else
'0';
QSPI_ADDR_CNTR_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(pr_state_addr_ph = '0') then
addr_cnt <= (others => '0');
elsif(pr_state_addr_ph = '1')then
addr_cnt <= addr_cnt + SPIXfer_done_int_pulse;
end if;
end if;
end process QSPI_ADDR_CNTR_PROCESS;
-----------------------------------
end generate XIP_STD_DUAL_MODE_SP_MEM_GEN;
--------------------------------------------------
XIP_QUAD_MODE_WB_MEM_GEN: if (
C_SPI_MODE = 2 and
C_SPI_MEMORY = 1
)
generate
-------------------
begin
-----
--------------------------------------------------
PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
qspi_cntrl_ps <= IDLE;
stop_clock_reg <= '0';
else
qspi_cntrl_ps <= qspi_cntrl_ns;
stop_clock_reg <= stop_clock;
end if;
end if;
end process PS_TO_NS_PROCESS;
-----------------------------
pr_state_data_receive <= '1' when qspi_cntrl_ps = DATA_RECEIVE else
'0';
pr_state_non_idle <= '1' when qspi_cntrl_ps /= IDLE else
'0';
pr_state_idle <= '1' when qspi_cntrl_ps = IDLE else
'0';
pr_state_cmd_ph <= '1' when qspi_cntrl_ps = CMD_SEND else
'0';
QSPI_CNTRL_PROCESS: process(
---------------------
new_tr,
CMD_Mode_1 ,
CMD_Mode_0 ,
---------------------
Addr_Phase ,
Addr_Bit ,
Addr_Mode_1 ,
Addr_Mode_0 ,
---------------------
Data_Phase ,
Data_Dir ,
Data_Mode_1 ,
Data_Mode_0 ,
---------------------
addr_cnt ,
Quad_Phase ,
---------------------
SR_5_Tx_Empty ,
SPIXfer_done_int_pulse,
stop_clock_reg,
---------------------
qspi_cntrl_ps ,
no_slave_selected ,
---------------------
wrap_around ,
transfer_start ,
wrap_ack_1 ,
wb_hpm_done ,
hpm_under_process_d1
)is
-----
begin
-----
mode_1 <= '0';
mode_0 <= '0';
--------------
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
--------------
stop_clock <= '0';
--------------
rst_wrap_around <= '0';
--------------
case qspi_cntrl_ps is
when IDLE => if(--(CMD_decoded = '1') and
(SR_5_Tx_Empty = '0') and -- this will be used specially in case of WRAP transactions
(transfer_start = '1')and
(new_tr = '1')
--(CMD_Error = '0') -- proceed only when there is no command error
)then
IO0_T_control <= CMD_Mode_0;
IO3_T_control <= not Quad_Phase;--
qspi_cntrl_ns <= CMD_SEND;
else
qspi_cntrl_ns <= IDLE; -- CMD_DECODE;
end if;
stop_clock <= '1';
------------------------------------------------
when CMD_SEND => mode_1 <= CMD_Mode_1;
mode_0 <= CMD_Mode_0;
IO0_T_control <= CMD_Mode_0;
IO3_T_control <= not Quad_Phase;--
--if(SPIXfer_done_int_pulse_d2 = '1')then
if(SPIXfer_done_int_pulse = '1')then
if(hpm_under_process_d1 = '1')then
qspi_cntrl_ns <= HPM_DUMMY;
elsif(Addr_Phase='1')then
qspi_cntrl_ns <= ADDR_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
else
qspi_cntrl_ns <= CMD_SEND;
end if;
------------------------------------------------
when HPM_DUMMY => IO0_T_control <= CMD_Mode_0;
IO1_T_control <= (CMD_Mode_1) or (not CMD_Mode_0);
if(SR_5_Tx_Empty='1') then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= HPM_DUMMY;
end if;
------------------------------------------------
when ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);
IO2_T_control <= (not Addr_Mode_1);
IO3_T_control <= (not Addr_Mode_1);
--stop_clock <= SR_5_Tx_Empty;
if((SR_5_Tx_Empty='1') and
(Data_Phase='0')
)then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
if(
(addr_cnt = "011") and -- 24 bit address
(Addr_Bit='0') and(Data_Phase='1')
)then
if((Data_Dir='1'))then
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0'; -- data output
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);-- active only
IO3_T_control <= not (Data_Mode_1);-- active only
qspi_cntrl_ns <= DATA_SEND; -- o/p
else
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
end if;
-- -- coverage off
-- -- below piece of code is for 32-bit address check, and left for future use
-- elsif(
-- (addr_cnt = "100") and -- 32 bit
-- (Addr_Bit = '1') and (Data_Phase='1')
-- )then
-- if((Data_Dir='1'))then
-- qspi_cntrl_ns <= DATA_SEND; -- o/p
-- else
-- qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
-- end if;
-- -- coverage on
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
end if;
------------------------------------------------
when TEMP_ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);
IO2_T_control <= (not Addr_Mode_1);
IO3_T_control <= (not Addr_Mode_1);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= ADDR_SEND;
end if;
-----------------------------------------------------------------------
when DATA_SEND => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0'; -- data output active only in Dual mode
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);-- active only in quad mode
IO3_T_control <= not (Data_Mode_1);-- active only in quad mode
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1')then
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
qspi_cntrl_ns <= DATA_SEND;
end if;
------------------------------------------------
when TEMP_DATA_SEND => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0'; -- data output active only in Dual mode
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);-- active only in quad mode
IO3_T_control <= not (Data_Mode_1);-- active only in quad mode
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_SEND;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_SEND;
end if;
when DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1')or (wrap_ack_1 = '1')then
rst_wrap_around <= wrap_ack_1;
if(no_slave_selected = '1')or (wrap_ack_1 = '1')then
stop_clock <= wrap_ack_1;
qspi_cntrl_ns <= IDLE;
else
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
when TEMP_DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
-- coverage off
when others => qspi_cntrl_ns <= IDLE;
------------------------------------------------
-- coverage on
end case;
-------------------------------
end process QSPI_CNTRL_PROCESS;
-------------------------------
pr_state_addr_ph <= '1' when qspi_cntrl_ps = ADDR_SEND else
'0';
QSPI_ADDR_CNTR_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(pr_state_addr_ph = '0') then
addr_cnt <= (others => '0');
elsif(pr_state_addr_ph = '1')then
--addr_cnt <= addr_cnt + SPIXfer_done_int_pulse_d2;
addr_cnt <= addr_cnt + SPIXfer_done_int_pulse;
end if;
end if;
end process QSPI_ADDR_CNTR_PROCESS;
-----------------------------------
------------------------------------------
end generate XIP_QUAD_MODE_WB_MEM_GEN;
------------------------------------------
--------------------------------------------------
XIP_QUAD_MODE_NM_MEM_GEN: if C_SPI_MODE = 2 and C_SPI_MEMORY = 2 generate
-------------------
begin
-----
--------------------------------------------------
PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
qspi_cntrl_ps <= IDLE;
stop_clock_reg <= '0';
else
qspi_cntrl_ps <= qspi_cntrl_ns;
stop_clock_reg <= stop_clock;
end if;
end if;
end process PS_TO_NS_PROCESS;
-----------------------------
pr_state_data_receive <= '1' when qspi_cntrl_ps = DATA_RECEIVE else
'0';
pr_state_non_idle <= '1' when qspi_cntrl_ps /= IDLE else
'0';
pr_state_idle <= '1' when qspi_cntrl_ps = IDLE else
'0';
pr_state_cmd_ph <= '1' when qspi_cntrl_ps = CMD_SEND else
'0';
QSPI_CNTRL_PROCESS: process(
---------------------
--CMD_decoded ,
new_tr,
CMD_Mode_1 ,
CMD_Mode_0 ,
--CMD_Error ,
---------------------
Addr_Phase ,
Addr_Bit ,
Addr_Mode_1 ,
Addr_Mode_0 ,
---------------------
Data_Phase ,
Data_Dir ,
Data_Mode_1 ,
Data_Mode_0 ,
---------------------
addr_cnt ,
Quad_Phase ,
---------------------
SR_5_Tx_Empty ,
--SPIXfer_done_int_pulse_d2,
SPIXfer_done_int_pulse,
stop_clock_reg,
no_slave_selected ,
---------------------
qspi_cntrl_ps ,
---------------------
wrap_around ,
transfer_start_d1 ,
transfer_start ,
wrap_ack_1
)is
-----
begin
-----
mode_1 <= '0';
mode_0 <= '0';
--------------
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
-------------
stop_clock <= '0';
-------------
rst_wrap_around <= '0';
-------------
case qspi_cntrl_ps is
when IDLE => if(--(CMD_decoded = '1') and
(SR_5_Tx_Empty = '0') and -- this will be used specially in case of WRAP transactions
(transfer_start = '1')and
(new_tr = '1')
--(CMD_Error = '0') -- proceed only when there is no command error
)then
IO0_T_control <= CMD_Mode_0;
IO3_T_control <= not Quad_Phase;
qspi_cntrl_ns <= CMD_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
stop_clock <= '1';
------------------------------------------------
when CMD_SEND => mode_1 <= CMD_Mode_1;
mode_0 <= CMD_Mode_0;
IO0_T_control <= CMD_Mode_0;
IO3_T_control <= not Quad_Phase;-- this is due to sending '1' on DQ3 line during command phase for Quad instructions only.
--if(SPIXfer_done_int_pulse_d2 = '1')then
if(SPIXfer_done_int_pulse = '1')then
if(Addr_Phase='1')then
qspi_cntrl_ns <= ADDR_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
else
qspi_cntrl_ns <= CMD_SEND;
end if;
------------------------------------------------
when ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);
IO2_T_control <= (not Addr_Mode_1);
IO3_T_control <= (not Addr_Mode_1);
--stop_clock <= SR_5_Tx_Empty;
if((SR_5_Tx_Empty='1') and
(Data_Phase='0')
)then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
if(
(addr_cnt = "011") and -- 24 bit address
(Addr_Bit='0') and
(Data_Phase='1')
)then
if((Data_Dir='1'))then
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0';
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);
IO3_T_control <= not (Data_Mode_1);
qspi_cntrl_ns <= DATA_SEND; -- o/p
else
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
end if;
elsif(
(addr_cnt = "100") and -- 32 bit
(Addr_Bit = '1') and
(Data_Phase='1')
) then
--if((Data_Dir='1'))then
-- qspi_cntrl_ns <= DATA_SEND; -- o/p
--else
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
--end if;
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
end if;
-- ------------------------------------------------
when TEMP_ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);
IO2_T_control <= (not Addr_Mode_1);
IO3_T_control <= (not Addr_Mode_1);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= ADDR_SEND;
end if;
when DATA_SEND => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0';
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);
IO3_T_control <= not (Data_Mode_1);
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1')then
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
qspi_cntrl_ns <= DATA_SEND;
end if;
------------------------------------------------
when TEMP_DATA_SEND=> mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0';
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);
IO3_T_control <= not (Data_Mode_1);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_SEND;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_SEND;
end if;
when DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1') or (wrap_ack_1 = '1')then
rst_wrap_around <= wrap_ack_1;
--if(no_slave_selected = '1') or (wrap_around = '1')then
stop_clock <= wrap_ack_1 or SR_5_Tx_Empty;
qspi_cntrl_ns <= IDLE;
--else
-- stop_clock <= SR_5_Tx_Empty;
-- qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
--end if;
else
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
when TEMP_DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= stop_clock_reg;
--if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
--else
-- stop_clock <= '0';
-- qspi_cntrl_ns <= DATA_RECEIVE;
--end if;
------------------------------------------------
-- coverage off
when others => qspi_cntrl_ns <= IDLE; -- CMD_DECODE;
------------------------------------------------
-- coverage on
end case;
-------------------------------
end process QSPI_CNTRL_PROCESS;
-------------------------------
pr_state_addr_ph <= '1' when qspi_cntrl_ps = ADDR_SEND else
'0';
QSPI_ADDR_CNTR_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(pr_state_addr_ph = '0') then
addr_cnt <= (others => '0');
elsif(pr_state_addr_ph = '1')then
--addr_cnt <= addr_cnt + SPIXfer_done_int_pulse_d2;
addr_cnt <= addr_cnt + SPIXfer_done_int_pulse;
end if;
end if;
end process QSPI_ADDR_CNTR_PROCESS;
-----------------------------------
end generate XIP_QUAD_MODE_NM_MEM_GEN;
---------------------------------------
XIP_QUAD_MODE_SP_MEM_GEN: if C_SPI_MODE = 2 and C_SPI_MEMORY = 3 generate
-------------------
begin
-----
--------------------------------------------------
PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
qspi_cntrl_ps <= IDLE;
stop_clock_reg <= '0';
else
qspi_cntrl_ps <= qspi_cntrl_ns;
stop_clock_reg <= stop_clock;
end if;
end if;
end process PS_TO_NS_PROCESS;
-----------------------------
pr_state_data_receive <= '1' when qspi_cntrl_ps = DATA_RECEIVE else
'0';
pr_state_non_idle <= '1' when qspi_cntrl_ps /= IDLE else
'0';
pr_state_idle <= '1' when qspi_cntrl_ps = IDLE else
'0';
pr_state_cmd_ph <= '1' when qspi_cntrl_ps = CMD_SEND else
'0';
QSPI_CNTRL_PROCESS: process(
---------------------
--CMD_decoded ,
new_tr,
CMD_Mode_1 ,
CMD_Mode_0 ,
--CMD_Error ,
---------------------
Addr_Phase ,
Addr_Bit ,
Addr_Mode_1 ,
Addr_Mode_0 ,
---------------------
Data_Phase ,
Data_Dir ,
Data_Mode_1 ,
Data_Mode_0 ,
---------------------
addr_cnt ,
Quad_Phase ,
---------------------
SR_5_Tx_Empty ,
--SPIXfer_done_int_pulse_d2,
SPIXfer_done_int_pulse,
stop_clock_reg,
no_slave_selected ,
---------------------
qspi_cntrl_ps ,
---------------------
wrap_around ,
transfer_start_d1 ,
transfer_start ,
wrap_ack_1
)is
-----
begin
-----
mode_1 <= '0';
mode_0 <= '0';
--------------
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
-------------
stop_clock <= '0';
-------------
rst_wrap_around <= '0';
-------------
case qspi_cntrl_ps is
when IDLE => if(--(CMD_decoded = '1') and
(SR_5_Tx_Empty = '0') and -- this will be used specially in case of WRAP transactions
(transfer_start = '1')and
(new_tr = '1')
--(CMD_Error = '0') -- proceed only when there is no command error
)then
IO0_T_control <= CMD_Mode_0;
IO3_T_control <= not Quad_Phase;
qspi_cntrl_ns <= CMD_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
stop_clock <= '1';
------------------------------------------------
when CMD_SEND => mode_1 <= CMD_Mode_1;
mode_0 <= CMD_Mode_0;
IO0_T_control <= CMD_Mode_0;
IO3_T_control <= not Quad_Phase;-- this is due to sending '1' on DQ3 line during command phase for Quad instructions only.
--if(SPIXfer_done_int_pulse_d2 = '1')then
if(SPIXfer_done_int_pulse = '1')then
if(Addr_Phase='1')then
qspi_cntrl_ns <= ADDR_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
else
qspi_cntrl_ns <= CMD_SEND;
end if;
------------------------------------------------
when ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);
IO2_T_control <= (not Addr_Mode_1);
IO3_T_control <= (not Addr_Mode_1);
--stop_clock <= SR_5_Tx_Empty;
if((SR_5_Tx_Empty='1') and
(Data_Phase='0')
)then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
if(
(addr_cnt = "011") and -- 24 bit address
(Addr_Bit='0') and
(Data_Phase='1')
)then
if((Data_Dir='1'))then
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0';
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);
IO3_T_control <= not (Data_Mode_1);
qspi_cntrl_ns <= DATA_SEND; -- o/p
else
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
end if;
elsif(
(addr_cnt = "100") and -- 32 bit
(Addr_Bit = '1') and
(Data_Phase='1')
) then
--if((Data_Dir='1'))then
-- qspi_cntrl_ns <= DATA_SEND; -- o/p
--else
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
--end if;
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
end if;
-- ------------------------------------------------
when TEMP_ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);
IO2_T_control <= (not Addr_Mode_1);
IO3_T_control <= (not Addr_Mode_1);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= ADDR_SEND;
end if;
when DATA_SEND => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0';
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);
IO3_T_control <= not (Data_Mode_1);
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1')then
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
qspi_cntrl_ns <= DATA_SEND;
end if;
------------------------------------------------
when TEMP_DATA_SEND=> mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0';
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);
IO3_T_control <= not (Data_Mode_1);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_SEND;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_SEND;
end if;
when DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1') or (wrap_ack_1 = '1')then
rst_wrap_around <= wrap_ack_1;
--if(no_slave_selected = '1') or (wrap_around = '1')then
stop_clock <= wrap_ack_1 or SR_5_Tx_Empty;
qspi_cntrl_ns <= IDLE;
--else
-- stop_clock <= SR_5_Tx_Empty;
-- qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
--end if;
else
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
when TEMP_DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= stop_clock_reg;
--if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
--else
-- stop_clock <= '0';
-- qspi_cntrl_ns <= DATA_RECEIVE;
--end if;
------------------------------------------------
-- coverage off
when others => qspi_cntrl_ns <= IDLE; -- CMD_DECODE;
------------------------------------------------
-- coverage on
end case;
-------------------------------
end process QSPI_CNTRL_PROCESS;
-------------------------------
pr_state_addr_ph <= '1' when qspi_cntrl_ps = ADDR_SEND else
'0';
QSPI_ADDR_CNTR_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(pr_state_addr_ph = '0') then
addr_cnt <= (others => '0');
elsif(pr_state_addr_ph = '1')then
--addr_cnt <= addr_cnt + SPIXfer_done_int_pulse_d2;
addr_cnt <= addr_cnt + SPIXfer_done_int_pulse;
end if;
end if;
end process QSPI_ADDR_CNTR_PROCESS;
-----------------------------------
end generate XIP_QUAD_MODE_SP_MEM_GEN;
---------------------------------------
IO0_O <= Serial_Dout_0;
IO1_O <= Serial_Dout_1;
IO2_O <= Serial_Dout_2;
IO3_O <= Serial_Dout_3;
--SCK_O <= SCK_O_reg;
--SS_O <= SS_to_spi_clk;
--* -------------------------------------------------------------------------------
--* -- MASTER_TRIST_EN_PROCESS : If not master make tristate enabled
--* ----------------------------
SS_tri_state_en_control <= '0' when
(
-- (SR_5_Tx_Empty_d1 = '0') and -- Length counter is not exited
(transfer_start = '1') and
(wrap_ack = '0') and -- no wrap around
--(MODF_strobe_int ='0') -- no mode fault -- 9/7/2013
(SPISEL_sync = '1') -- 9/7/2013
)
else
'1';
--QSPI_SS_T: tri-state register for SS,ideal state-deactive
QSPI_SS_T: component FD
generic map
(
INIT => '1'
)
port map
(
Q => SS_T,
C => EXT_SPI_CLK,
D => SS_tri_state_en_control
);
--QSPI_SCK_T : Tri-state register for SCK_T, ideal state-deactive
SCK_tri_state_en_control <= '0' when
(
-- (SR_5_Tx_Empty = '0') and -- Length counter is not exited
(transfer_start = '1') and -- 4/14/2013
(wrap_ack = '0') and -- no wrap around-- (pr_state_non_idle = '1') and -- CR#619275 - this is commented to operate the mode 3 with SW flow
--(MODF_strobe_int ='0') -- no mode fault -- 9/7/2013
(SPISEL_sync = '1') -- 9/7/2013
) else
'1';
QSPI_SCK_T: component FD
generic map
(
INIT => '1'
)
port map
(
Q => SCK_T,
C => EXT_SPI_CLK,
D => SCK_tri_state_en_control
);
IO0_tri_state_en_control <= '0' when
(
(IO0_T_control = '0') and
--(MODF_strobe_int = '0')-- no mode fault-- 9/7/2013
(SPISEL_sync = '1') -- 9/7/2013
) else
'1';
--QSPI_IO0_T: tri-state register for MOSI, ideal state-deactive
QSPI_IO0_T: component FD
generic map
(
INIT => '1'
)
port map
(
Q => IO0_T, -- MOSI_T,
C => EXT_SPI_CLK,
D => IO0_tri_state_en_control -- master_tri_state_en_control
);
IO1_tri_state_en_control <= '0' when
(
(IO1_T_control = '0') and
--(MODF_strobe_int = '0')-- no mode fault-- 9/7/2013
(SPISEL_sync = '1') -- 9/7/2013
) else
'1';
--QSPI_IO0_T: tri-state register for MISO, ideal state-deactive
QSPI_IO1_T: component FD
generic map
(
INIT => '1'
)
port map
(
Q => IO1_T, -- MISO_T,
C => EXT_SPI_CLK,
D => IO1_tri_state_en_control
);
-------------------------------------------------------------------------------
QSPI_NO_MODE_2_T_CONTROL: if C_SPI_MODE = 1 or C_SPI_MODE = 0 generate
----------------------
begin
-----
--------------------------------------
IO2_tri_state_en_control <= '1';
IO3_tri_state_en_control <= '1';
IO2_T <= '1';
IO3_T <= '1';
--------------------------------------
end generate QSPI_NO_MODE_2_T_CONTROL;
--------------------------------------
-------------------------------------------------------------------------------
QSPI_MODE_2_T_CONTROL: if C_SPI_MODE = 2 generate
----------------------
begin
-----
--------------------------------------
IO2_tri_state_en_control <= '0' when
(
(IO2_T_control = '0') and
--(MODF_strobe_int = '0')-- no mode fault -- 9/7/2013
(SPISEL_sync = '1') -- 9/7/2013
) else
'1';
--QSPI_IO0_T: tri-state register for MOSI, ideal state-deactive
QSPI_IO2_T: component FD
generic map
(
INIT => '1'
)
port map
(
Q => IO2_T, -- MOSI_T,
C => EXT_SPI_CLK,
D => IO2_tri_state_en_control -- master_tri_state_en_control
);
--------------------------------------
IO3_tri_state_en_control <= '0' when
(
(IO3_T_control = '0') and
--(MODF_strobe_int = '0')-- no mode fault-- 9/7/2013
(SPISEL_sync = '1') -- 9/7/2013
) else
'1';
--QSPI_IO0_T: tri-state register for MISO, ideal state-deactive
QSPI_IO3_T: component FD
generic map
(
INIT => '1'
)
port map
(
Q => IO3_T, -- MISO_T,
C => EXT_SPI_CLK,
D => IO3_tri_state_en_control
);
--------------------------------------
end generate QSPI_MODE_2_T_CONTROL;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- QSPI_SPISEL: first synchronize the incoming signal, this is required is slave
--------------- mode of the core.
QSPI_SPISEL: component FD
generic map
(
INIT => '1' -- default '1' to make the device in default master mode
)
port map
(
Q => SPISEL_sync,
C => EXT_SPI_CLK,
D => SPISEL
);
-- SPISEL_DELAY_1CLK_PROCESS_P : Detect active SCK edge in slave mode
-----------------------------
SPISEL_DELAY_1CLK_PROCESS_P: process(EXT_SPI_CLK)
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
spisel_d1 <= '1';
else
spisel_d1 <= SPISEL_sync;
end if;
end if;
end process SPISEL_DELAY_1CLK_PROCESS_P;
------------------------------------------------
-- MODF_STROBE_PROCESS : Strobe MODF signal when master is addressed as slave
------------------------
MODF_STROBE_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if((Rst_to_spi = RESET_ACTIVE) or (SPISEL_sync = '1')) then
MODF_strobe <= '0';
MODF_strobe_int <= '0';
Allow_MODF_Strobe <= '1';
elsif(
(SPISEL_sync = '0') and
(Allow_MODF_Strobe = '1')
) then
MODF_strobe <= '1';
MODF_strobe_int <= '1';
Allow_MODF_Strobe <= '0';
else
MODF_strobe <= '0';
MODF_strobe_int <= '0';
end if;
end if;
end process MODF_STROBE_PROCESS;
SS_O_24_BIT_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
-----
begin
-----
-------------------------------------------------------------------------------
-- SELECT_OUT_PROCESS : This process sets SS active-low, one-hot encoded select
-- bit. Changing SS is premitted during a transfer by
-- hardware, but is to be prevented by software. In Auto
-- mode SS_O reflects value of Slave_Select_Reg only
-- when transfer is in progress, otherwise is SS_O is held
-- high
-----------------------
SELECT_OUT_PROCESS: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
SS_O <= (others => '1');
elsif(wrap_ack_1 = '1') or (store_last_b4_wrap = '1') or (SR_5_Tx_Empty ='1') then
SS_O <= (others => '1');
elsif(hpm_under_process_d1 = '1') then
for i in (C_NUM_SS_BITS-1) downto 0 loop
SS_O(i) <= (SS_to_spi_clk(C_NUM_SS_BITS-1-i));
end loop;
elsif(store_last_b4_wrap = '0') then
for i in (C_NUM_SS_BITS-1) downto 0 loop
SS_O(i) <= not(SS_to_spi_clk(C_NUM_SS_BITS-1-i));
end loop;
end if;
end if;
end process SELECT_OUT_PROCESS;
----------------------------
end generate SS_O_24_BIT_ADDR_GEN;
----------------------------------
SS_O_32_BIT_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
-----
begin
-----
-------------------------------------------------------------------------------
-- SELECT_OUT_PROCESS : This process sets SS active-low, one-hot encoded select
-- bit. Changing SS is premitted during a transfer by
-- hardware, but is to be prevented by software. In Auto
-- mode SS_O reflects value of Slave_Select_Reg only
-- when transfer is in progress, otherwise is SS_O is held
-- high
-----------------------
SELECT_OUT_PROCESS: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
SS_O <= (others => '1');
elsif(wrap_ack_1 = '1') or (store_last_b4_wrap = '1') or (transfer_start = '0' and SR_5_Tx_Empty_d1='1') then
SS_O <= (others => '1');
elsif(hpm_under_process = '1') or (wr_en_under_process = '1') then
for i in (C_NUM_SS_BITS-1) downto 0 loop
SS_O(i) <= (SS_to_spi_clk(C_NUM_SS_BITS-1-i));
end loop;
elsif(store_last_b4_wrap = '0') then
for i in (C_NUM_SS_BITS-1) downto 0 loop
SS_O(i) <= not(SS_to_spi_clk(C_NUM_SS_BITS-1-i));
end loop;
end if;
end if;
end process SELECT_OUT_PROCESS;
----------------------------
end generate SS_O_32_BIT_ADDR_GEN;
----------------------------------
no_slave_selected <= and_reduce(SS_to_spi_clk((C_NUM_SS_BITS-1) downto 0));
-------------------------------------------------------------------------------
SCK_O_NQ_4_NO_STARTUP_USED: if (C_USE_STARTUP = 0) generate
----------------
attribute IOB : string;
attribute IOB of SCK_O_NE_4_FDRE_INST : label is "true";
signal slave_mode : std_logic;
----------------
begin
-----
-------------------------------------------------------------------------------
-- SCK_O_SELECT_PROCESS : Select the idle state (CPOL bit) when not transfering
-- data else select the clock for slave device
-------------------------
SCK_O_NQ_4_SELECT_PROCESS: process(--Mst_N_Slv ,-- in master mode
sck_o_int ,-- value driven on sck_int
CPOL_to_spi_clk ,-- CPOL mode thr SPICR
transfer_start ,
transfer_start_d1 ,
Count(COUNT_WIDTH),
pr_state_non_idle -- State machine is in Non-idle state
)is
begin
if((transfer_start = '1') and
--(transfer_start_d1 = '1') and
--(Count(COUNT_WIDTH) = '0')and
(pr_state_non_idle = '1')
) then
sck_o_in <= sck_o_int;
else
sck_o_in <= CPOL_to_spi_clk;
end if;
end process SCK_O_NQ_4_SELECT_PROCESS;
---------------------------------
slave_mode <= '0'; -- create the reset condition by inverting the mst_n_slv signal. 1 - master mode, 0 - slave mode.
-- FDRE: Single Data Rate D Flip-Flop with Synchronous Reset and
-- Clock Enable (posedge clk). during slave mode no clock should be generated from the core.
SCK_O_NE_4_FDRE_INST : component FDRE
generic map (
INIT => '0'
) -- Initial value of register (0 or 1)
port map
(
Q => SCK_O_reg, -- Data output
C => EXT_SPI_CLK, -- Clock input
CE => '1', -- Clock enable input
R => Rst_to_spi, -- Synchronous reset input
D => sck_o_in -- Data input
);
end generate SCK_O_NQ_4_NO_STARTUP_USED;
-------------------------------
SCK_O_NQ_4_STARTUP_USED: if (C_USE_STARTUP = 1) generate
-------------
begin
-----
-------------------------------------------------------------------------------
-- SCK_O_SELECT_PROCESS : Select the idle state (CPOL bit) when not transfering
-- data else select the clock for slave device
-------------------------
SCK_O_NQ_4_SELECT_PROCESS: process(sck_o_int ,
CPOL_to_spi_clk ,
transfer_start ,
transfer_start_d1 ,
Count(COUNT_WIDTH)
)is
begin
if((transfer_start = '1') -- and
--(transfer_start_d1 = '1') --and
--(Count(COUNT_WIDTH) = '0')
) then
sck_o_in <= sck_o_int;
else
sck_o_in <= CPOL_to_spi_clk;
end if;
end process SCK_O_NQ_4_SELECT_PROCESS;
---------------------------------
---------------------------------------------------------------------------
-- SCK_O_FINAL_PROCESS : Register the final SCK_O_reg
------------------------
SCK_O_NQ_4_FINAL_PROCESS: process(EXT_SPI_CLK)
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
--If Soft_Reset_op or slave Mode.Prevents SCK_O_reg to be generated in slave
if((Rst_to_spi = RESET_ACTIVE)
) then
SCK_O_reg <= '0';
elsif((pr_state_non_idle='0')-- or -- dont allow sck to go out when
--(Mst_N_Slv = '0')
)then -- SM is in IDLE state or core in slave mode
SCK_O_reg <= '0';
else
SCK_O_reg <= sck_o_in;
end if;
end if;
end process SCK_O_NQ_4_FINAL_PROCESS;
-------------------------------------
end generate SCK_O_NQ_4_STARTUP_USED;
-------------------------------------
--end generate RATIO_NOT_EQUAL_4_GENERATE;
end generate RATIO_OF_2_GENERATE;
end architecture imp;
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- axi_qspi_xip_if.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_qspi_xip_if.vhd
-- Version: v3.0
-- Description: This is the top-level design file for the AXI Quad SPI core
-- in XIP mode.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_arith.all;
-- use ieee.std_logic_signed.all;
use ieee.std_logic_misc.all;
-- library unsigned is used for overloading of "=" which allows integer to
-- be compared to std_logic_vector
use ieee.std_logic_unsigned.all;
library axi_lite_ipif_v3_0_4;
use axi_lite_ipif_v3_0_4.axi_lite_ipif;
use axi_lite_ipif_v3_0_4.ipif_pkg.all;
library lib_fifo_v1_0_5;
use lib_fifo_v1_0_5.async_fifo_fg;
library lib_cdc_v1_0_2;
use lib_cdc_v1_0_2.cdc_sync;
library axi_quad_spi_v3_2_8;
use axi_quad_spi_v3_2_8.all;
library unisim;
use unisim.vcomponents.FDRE;
use unisim.vcomponents.FD;
use unisim.vcomponents.FDR;
-------------------------------------------------------------------------------
entity axi_qspi_xip_if is
generic(
-- General Parameters
C_FAMILY : string := "virtex7";
Async_Clk : integer := 0;
C_SUB_FAMILY : string := "virtex7";
-------------------------
C_SPI_MEM_ADDR_BITS : integer ; -- default is 24 bit, options are 24 or 32 bits
-------------------------
-- C_AXI4_CLK_PS : integer := 10000;--AXI clock period
-- C_EXT_SPI_CLK_PS : integer := 10000;--ext clock period
C_XIP_FIFO_DEPTH : integer := 64;-- Fixed value for XIP mode.
C_SCK_RATIO : integer := 16;--default in legacy mode
C_NUM_SS_BITS : integer range 1 to 32:= 1;
C_NUM_TRANSFER_BITS : integer := 8; -- Fixed 8 bit for XIP mode
-------------------------
C_SPI_MODE : integer range 0 to 2 := 0; -- used for differentiating
-- Standard, Dual or Quad mode
-- in Ports as well as internal
-- functionality
C_USE_STARTUP : integer range 0 to 1 := 1; --
C_SPI_MEMORY : integer range 0 to 3 := 1; -- 0 - mixed mode,
-- 1 - winbond,
-- 2 - numonyx
-- 3 - spansion
-- used to differentiate
-- internal look up table
-- for commands.
-------------------------
-- AXI4 Lite Interface Parameters
--*C_S_AXI_ADDR_WIDTH : integer range 32 to 32 := 32;
C_S_AXI_ADDR_WIDTH : integer range 7 to 7 := 7;
C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
-------------------------
--*C_BASEADDR : std_logic_vector := x"FFFFFFFF";
--*C_HIGHADDR : std_logic_vector := x"00000000";
-------------------------
-- AXI4 Full Interface Parameters
--*C_S_AXI4_ADDR_WIDTH : integer range 32 to 32 := 32;
C_S_AXI4_ADDR_WIDTH : integer ;-- range 32 to 32 := 32;
C_S_AXI4_DATA_WIDTH : integer range 32 to 32 := 32;
C_S_AXI4_ID_WIDTH : integer range 1 to 16 := 4;
-------------------------
--*C_AXI4_BASEADDR : std_logic_vector := x"FFFFFFFF";
--*C_AXI4_HIGHADDR : std_logic_vector := x"00000000";
-------------------------
C_XIP_FULL_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_0100_0000", -- IP user0 base address
X"0000_0000_01FF_FFFF" -- IP user0 high address
);
C_XIP_FULL_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
2,
1 -- User0 CE Number
)
);
port(
-- external async clock for SPI interface logic
EXT_SPI_CLK : in std_logic;
S_AXI4_ACLK : in std_logic;
Rst_to_spi : in std_logic;
S_AXI4_ARESET : in std_logic;
-------------------------------
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
------------------------------------
-- AXI Write Address Channel Signals
------------------------------------
S_AXI4_AWID : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_AWADDR : in std_logic_vector((C_SPI_MEM_ADDR_BITS-1) downto 0);
S_AXI4_AWLEN : in std_logic_vector(7 downto 0);
S_AXI4_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI4_AWBURST : in std_logic_vector(1 downto 0);
S_AXI4_AWLOCK : in std_logic; -- not supported in design
S_AXI4_AWCACHE : in std_logic_vector(3 downto 0);-- not supported in design
S_AXI4_AWPROT : in std_logic_vector(2 downto 0);-- not supported in design
S_AXI4_AWVALID : in std_logic;
S_AXI4_AWREADY : out std_logic;
---------------------------------------
-- AXI4 Full Write Data Channel Signals
---------------------------------------
S_AXI4_WDATA : in std_logic_vector((C_S_AXI4_DATA_WIDTH-1)downto 0);
S_AXI4_WSTRB : in std_logic_vector(((C_S_AXI4_DATA_WIDTH/8)-1) downto 0);
S_AXI4_WLAST : in std_logic;
S_AXI4_WVALID : in std_logic;
S_AXI4_WREADY : out std_logic;
-------------------------------------------
-- AXI4 Full Write Response Channel Signals
-------------------------------------------
S_AXI4_BID : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_BRESP : out std_logic_vector(1 downto 0);
S_AXI4_BVALID : out std_logic;
S_AXI4_BREADY : in std_logic;
-----------------------------------
-- AXI Read Address Channel Signals
-----------------------------------
S_AXI4_ARID : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_ARADDR : in std_logic_vector((C_SPI_MEM_ADDR_BITS-1) downto 0);
S_AXI4_ARLEN : in std_logic_vector(7 downto 0);
S_AXI4_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI4_ARBURST : in std_logic_vector(1 downto 0);
S_AXI4_ARLOCK : in std_logic; -- not supported in design
S_AXI4_ARCACHE : in std_logic_vector(3 downto 0);-- not supported in design
S_AXI4_ARPROT : in std_logic_vector(2 downto 0);-- not supported in design
S_AXI4_ARVALID : in std_logic;
S_AXI4_ARREADY : out std_logic;
--------------------------------
-- AXI Read Data Channel Signals
--------------------------------
S_AXI4_RID : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_RDATA : out std_logic_vector((C_S_AXI4_DATA_WIDTH-1) downto 0);
S_AXI4_RRESP : out std_logic_vector(1 downto 0);
S_AXI4_RLAST : out std_logic;
S_AXI4_RVALID : out std_logic;
S_AXI4_RREADY : in std_logic;
--------------------------------
XIPSR_CPHA_CPOL_ERR : in std_logic;
TO_XIPSR_trans_error : out std_logic;
--------------------------------
TO_XIPSR_mst_modf_err : out std_logic;
TO_XIPSR_axi_rx_full : out std_logic;
TO_XIPSR_axi_rx_empty : out std_logic;
XIPCR_1_CPOL : in std_logic;
XIPCR_0_CPHA : in std_logic;
-------------------------------
--*SPI port interface * --
-------------------------------
IO0_I : in std_logic; -- MOSI signal in standard SPI
IO0_O : out std_logic;
IO0_T : out std_logic;
-------------------------------
IO1_I : in std_logic; -- MISO signal in standard SPI
IO1_O : out std_logic;
IO1_T : out std_logic;
-----------------
-- quad mode pins
-----------------
IO2_I : in std_logic;
IO2_O : out std_logic;
IO2_T : out std_logic;
---------------
IO3_I : in std_logic;
IO3_O : out std_logic;
IO3_T : out std_logic;
---------------------------------
-- common pins
----------------
SPISEL : in std_logic;
-----
SCK_I : in std_logic;
SCK_O_reg : out std_logic;
SCK_T : out std_logic;
-----
SS_I : in std_logic_vector((C_NUM_SS_BITS-1) downto 0);
SS_O : out std_logic_vector((C_NUM_SS_BITS-1) downto 0);
SS_T : out std_logic
---------------------------------
);
end entity axi_qspi_xip_if;
--------------------------------------------------------------------------------
architecture imp of axi_qspi_xip_if is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
constant NEW_LOGIC : integer := 0; -- 3/29/2013
constant ACTIVE_LOW_RESET : std_logic := '0';
constant CMD_BITS_LENGTH : integer:= 8; -- 3/29/2013
-----
-- code coverage -- function assign_addr_bits (logic_info : integer) return integer is
-- code coverage -- variable addr_width_24 : integer:= 24;
-- code coverage -- variable addr_width_32 : integer:= 32;
-- code coverage -- begin
-- code coverage -- if logic_info = 0 then -- old logic for 24 bit addressing
-- code coverage -- return addr_width_24;
-- code coverage -- else
-- code coverage -- return addr_width_32;
-- code coverage -- end if;
-- code coverage -- end function assign_addr_bits;
signal nm_wr_en_CMD : std_logic_vector(7 downto 0);
signal nm_4byte_addr_en_CMD : std_logic_vector(7 downto 0);
type NM_WR_EN_STATE_TYPE is
(NM_WR_EN_IDLE, -- decode command can be combined here later
NM_WR_EN,
NM_WR_EN_DONE
);
signal nm_wr_en_cntrl_ps : NM_WR_EN_STATE_TYPE;
signal nm_wr_en_cntrl_ns : NM_WR_EN_STATE_TYPE;
signal wr_en_under_process : std_logic;
signal wr_en_under_process_d1 : std_logic;
signal load_wr_en, wr_en_done_reg : std_logic;
signal wr_en_done_d1, wr_en_done_d2 : std_logic;
signal wr_en_done : std_logic;
signal data_loaded, cmd_sent : std_logic;
type NM_32_BIT_WR_EN_STATE_TYPE is
(NM_32_BIT_IDLE, -- decode command can be combined here later
NM_32_BIT_EN,
NM_32_BIT_EN_DONE
);
signal nm_sm_4_byte_addr_ps : NM_32_BIT_WR_EN_STATE_TYPE;
signal nm_sm_4_byte_addr_ns : NM_32_BIT_WR_EN_STATE_TYPE;
signal four_byte_en_under_process : std_logic;
signal four_byte_addr_under_process_d1 : std_logic;
signal load_4_byte_addr_en, four_byte_en_done, four_byte_en_done_reg : std_logic;
-----
-- constant declaration
constant FAST_READ : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0):="00001011"; -- 0B
constant FAST_READ_DUAL_IO : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0):="00111011"; -- 3B
constant FAST_READ_QUAD_IO : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0):="10111011"; -- BB
constant C_RD_COUNT_WIDTH_INT : integer := clog2(C_XIP_FIFO_DEPTH);
constant C_WR_COUNT_WIDTH_INT : integer := clog2(C_XIP_FIFO_DEPTH);
constant RX_FIFO_CNTR_WIDTH : integer := clog2(C_XIP_FIFO_DEPTH);
constant XIP_MIN_SIZE : std_logic_vector(31 downto 0):= X"00ffffff";-- 24 bit address
--constant XIP_ADDR_BITS : integer := 24;
constant XIP_ADDR_BITS : integer := C_SPI_MEM_ADDR_BITS; -- assign_addr_bits(NEW_LOGIC);
constant RESET_ACTIVE : std_logic := '1';
constant COUNT_WIDTH : INTEGER := log2(C_NUM_TRANSFER_BITS)+1;
constant ACTIVE_HIGH_RESET : std_logic := '1';
constant ZERO_RX_FIFO_CNT : std_logic_vector(RX_FIFO_CNTR_WIDTH-1 downto 0) := (others => '0');
signal rx_fifo_count: std_logic_vector(RX_FIFO_CNTR_WIDTH-1 downto 0);
constant ALL_1 : std_logic_vector(0 to RX_FIFO_CNTR_WIDTH-1)
:= (others => '0');
signal updown_cnt_en_rx,down_cnt_en_rx : std_logic;
type AXI_IF_STATE_TYPE is
(
IDLE, -- decode command can be combined here later
RD_BURST
);
signal xip_sm_ps: AXI_IF_STATE_TYPE;
signal xip_sm_ns: AXI_IF_STATE_TYPE;
type STATE_TYPE is
(IDLE, -- decode command can be combined here later
CMD_SEND,
HPM_DUMMY,
ADDR_SEND,
TEMP_ADDR_SEND,
--DUMMY_SEND,
DATA_SEND,
TEMP_DATA_SEND,
DATA_RECEIVE,
TEMP_DATA_RECEIVE
);
signal qspi_cntrl_ns : STATE_TYPE;
signal qspi_cntrl_ps : STATE_TYPE;
type WB_STATE_TYPE is
(WB_IDLE, -- decode command can be combined here later
WB_WR_HPM,
WB_DONE
);
signal wb_cntrl_ns : WB_STATE_TYPE;
signal wb_cntrl_ps : WB_STATE_TYPE;
signal valid_decode : std_logic;
signal s_axi_arready_cmb : std_logic;
signal temp_i : std_logic;
signal SS_frm_axi : std_logic_vector(C_NUM_SS_BITS-1 downto 0);
signal SS_frm_axi_int : std_logic_vector(C_NUM_SS_BITS-1 downto 0);
signal SS_frm_axi_reg : std_logic_vector(C_NUM_SS_BITS-1 downto 0);
signal type_of_burst : std_logic; --_vector(1 downto 0);
signal axi_length : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);
signal size_length : std_logic_vector(1 downto 0);
signal S_AXI4_RID_reg : std_logic_vector(C_S_AXI4_ID_WIDTH-1 downto 0);
signal XIP_ADDR : std_logic_vector(XIP_ADDR_BITS-1 downto 0);
signal one_byte_transfer : std_logic;
signal two_byte_transfer : std_logic;
signal four_byte_transfer: std_logic;
signal dtr_length : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);
signal write_length : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);
signal s_axi_rvalid_i : std_logic;
signal dtr_cntr_empty : std_logic;
signal last_bt_one_data_cmb : std_logic;
signal last_data_cmb : std_logic;
signal last_data_acked : std_logic;
signal last_data : std_logic;
signal rd_error_int : std_logic;
signal Data_From_Rx_FIFO : std_logic_vector(C_S_AXI4_DATA_WIDTH-1 downto 0);
signal S_AXI4_RRESP_i : std_logic_vector(1 downto 0);
signal S_AXI4_RDATA_i : std_logic_vector(C_S_AXI4_DATA_WIDTH-1 downto 0);
-- signal s_axi_rvalid_i : std_logic;
signal s_axi_rvalid_cmb : std_logic;
signal xip_pr_state_idle : std_logic;
signal pr_state_idle : std_logic;
signal rready_i : std_logic;
signal wrap_around_to_axi_clk : std_logic;
signal spiXfer_done_to_axi_1 : std_logic;
signal Rx_FIFO_Empty : std_logic;
signal IO0_T_cntrl_axi : std_logic;
signal IO1_T_cntrl_axi : std_logic;
signal IO2_T_cntrl_axi : std_logic;
signal IO3_T_cntrl_axi : std_logic;
signal SCK_T_cntrl_axi : std_logic;
signal load_axi_data_frm_axi : std_logic;
--signal Transmit_addr_int : std_logic_vector(23 downto 0); -- 3/30/2013
signal Transmit_addr_int : std_logic_vector(XIP_ADDR_BITS-1 downto 0); -- 3/30/2013
signal Rx_FIFO_rd_ack : std_logic;
signal Data_To_Rx_FIFO : std_logic_vector(C_S_AXI4_DATA_WIDTH-1 downto 0);
signal store_date_in_drr_fifo : std_logic;
--signal Rx_FIFO_Empty : std_logic;
signal Rx_FIFO_almost_Full : std_logic;
signal Rx_FIFO_almost_Empty : std_logic;
--signal pr_state_idle : std_logic;
signal spiXfer_done_frm_spi_clk: std_logic;
signal mst_modf_err_frm_spi_clk: std_logic;
signal wrap_around_frm_spi_clk : std_logic;
signal one_byte_xfer_frm_axi_clk : std_logic;
signal two_byte_xfer_frm_axi_clk : std_logic;
signal four_byte_xfer_frm_axi_clk : std_logic;
signal load_axi_data_frm_axi_clk : std_logic;
--signal Transmit_Addr_frm_axi_clk : std_logic_vector(23 downto 0); -- 3/30/2013
signal Transmit_Addr_frm_axi_clk : std_logic_vector(XIP_ADDR_BITS-1 downto 0);-- 3/30/2013
signal CPOL_frm_axi_clk : std_logic;
signal CPHA_frm_axi_clk : std_logic;
signal SS_frm_axi_clk : std_logic_vector(C_NUM_SS_BITS-1 downto 0);
signal type_of_burst_frm_axi_clk : std_logic; -- _vector(1 downto 0);
signal type_of_burst_frm_axi : std_logic; -- _vector(1 downto 0);
signal axi_length_frm_axi_clk : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);
signal dtr_length_frm_axi_clk : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);
signal load_axi_data_to_spi_clk : std_logic;
--signal Transmit_Addr_to_spi_clk : std_logic_vector(23 downto 0); -- 3/30/2013
signal Transmit_Addr_to_spi_clk : std_logic_vector(XIP_ADDR_BITS-1 downto 0); -- 3/30/2013
signal last_7_addr_bits : std_logic_vector(7 downto 0);
signal CPOL_to_spi_clk : std_logic;
signal CPHA_to_spi_clk : std_logic;
signal SS_to_spi_clk : std_logic_vector(C_NUM_SS_BITS-1 downto 0);
signal type_of_burst_to_spi : std_logic;
signal type_of_burst_to_spi_clk : std_logic;
signal axi_length_to_spi_clk : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);
signal dtr_length_to_spi_clk : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);
--signal wrap_around_to_axi_clk : std_logic;
signal spi_addr : std_logic_vector(31 downto 0);
signal spi_addr_i : std_logic_vector(XIP_ADDR_BITS-1 downto 0); -- (23 downto 0);
signal spi_addr_int : std_logic_vector(XIP_ADDR_BITS-1 downto 0); -- (23 downto 0);
signal spi_addr_wrap : std_logic_vector(XIP_ADDR_BITS-1 downto 0); -- (23 downto 0);
signal spi_addr_wrap_1 : std_logic_vector(XIP_ADDR_BITS-1 downto 0); -- (23 downto 0);
--signal Transmit_Addr_to_spi_clk : std_logic_vector(23 downto 0);
signal load_wrap_addr : std_logic;
signal wrap_two : std_logic;
signal wrap_four : std_logic;
signal wrap_eight : std_logic;
signal wrap_sixteen : std_logic;
signal SPIXfer_done_int : std_logic;
signal size_length_cntr : std_logic_vector(1 downto 0);
signal size_length_cntr_fixed : std_logic_vector(1 downto 0);
signal length_cntr : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);
signal cmd_addr_sent : std_logic;
signal SR_5_Tx_Empty, SR_5_Tx_Empty_d1, SR_5_Tx_Empty_d2 : std_logic;
signal wrap_around : std_logic;
signal rst_wrap_around : std_logic;
--signal pr_state_idle : std_logic;
signal one_byte_xfer_to_spi_clk : std_logic;
signal two_byte_xfer_to_spi_clk : std_logic;
signal four_byte_xfer_to_spi_clk : std_logic;
--signal store_date_in_drr_fifo : std_logic;
signal Data_To_Rx_FIFO_int : std_logic_vector(C_S_AXI4_DATA_WIDTH-1 downto 0);
signal SPIXfer_done_int_pulse_d2 : std_logic;
signal receive_Data_int : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);
--signal Data_To_Rx_FIFO : std_logic_vector(7 downto 0);
--signal load_axi_data_to_spi_clk : std_logic;
signal Tx_Data_d1 : std_logic_vector(31 downto 0);
signal Tx_Data_d2 : std_logic_vector(39 downto 0);
signal internal_count : std_logic_vector(3 downto 0);
signal SPI_cmd : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);
signal Transmit_Data : std_logic_vector(0 to C_NUM_TRANSFER_BITS-1);
signal Data_Dir : std_logic;
signal Data_Mode_1 : std_logic;
signal Data_Mode_0 : std_logic;
signal Data_Phase : std_logic;
signal Quad_Phase : std_logic;
signal Addr_Mode_1 : std_logic;
signal Addr_Mode_0 : std_logic;
signal Addr_Bit : std_logic;
signal Addr_Phase : std_logic;
signal CMD_Mode_1 : std_logic;
signal CMD_Mode_0 : std_logic;
--signal cmd_addr_cntr : std_logic_vector(2 downto 0);
--signal cmd_addr_sent : std_logic;
signal transfer_start : std_logic;
signal last_bt_one_data : std_logic;
--signal SPIXfer_done_int : std_logic;
signal actual_SPIXfer_done_int : std_logic;
signal transfer_start_d1 : std_logic;
signal transfer_start_d2 : std_logic;
signal transfer_start_d3 : std_logic;
signal transfer_start_pulse : std_logic;
signal SPIXfer_done_int_d1 : std_logic;
signal SPIXfer_done_int_pulse : std_logic;
signal SPIXfer_done_int_pulse_d1 : std_logic;
--signal SPIXfer_done_int_pulse_d2 : std_logic;
signal SPIXfer_done_int_pulse_d3 : std_logic;
--signal SPIXfer_done_int : std_logic;
signal mode_1 : std_logic;
signal mode_0 : std_logic;
signal Count : std_logic_vector(COUNT_WIDTH downto 0);
--signal receive_Data_int : std_logic_vector(7 downto 0);
signal rx_shft_reg_mode_0011 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal Sync_Set : std_logic;
signal Sync_Reset : std_logic;
signal sck_o_int : std_logic;
signal sck_d1 : std_logic;
signal sck_d2 : std_logic;
signal sck_rising_edge : std_logic;
signal Shift_Reg : std_logic_vector(0 to C_NUM_TRANSFER_BITS-1);
signal Serial_Dout_0 : std_logic;
signal Serial_Dout_1 : std_logic;
signal Serial_Dout_2 : std_logic;
signal Serial_Dout_3 : std_logic;
signal pr_state_cmd_ph : std_logic;
--signal qspi_cntrl_ps : std_logic;
signal stop_clock : std_logic;
signal stop_clock_reg : std_logic;
signal pr_state_data_receive : std_logic;
signal pr_state_non_idle : std_logic;
--signal pr_state_idle : std_logic;
--signal pr_state_cmd_ph : std_logic;
--signal SPIXfer_done_int_pulse : std_logic;
signal no_slave_selected : std_logic;
--signal rst_wrap_around : std_logic;
signal IO0_T_control : std_logic;
signal IO1_T_control : std_logic;
signal IO2_T_control : std_logic;
signal IO3_T_control : std_logic;
signal addr_cnt : std_logic_vector(2 downto 0);
signal addr_cnt1 : std_logic_vector(1 downto 0);
signal pr_state_addr_ph : std_logic;
signal SS_tri_state_en_control : std_logic;
signal SCK_tri_state_en_control : std_logic;
signal IO0_tri_state_en_control : std_logic;
signal IO1_tri_state_en_control : std_logic;
signal IO2_tri_state_en_control : std_logic;
signal IO3_tri_state_en_control : std_logic;
signal IO0_T_cntrl_spi : std_logic;
signal MODF_strobe_int : std_logic;
signal SPISEL_sync : std_logic;
signal spisel_d1 : std_logic;
signal MODF_strobe : std_logic;
signal Allow_MODF_Strobe : std_logic;
signal sck_o_in : std_logic;
--signal SCK_O_reg : std_logic;
signal slave_mode : std_logic;
--signal pr_state_non_idle : std_logic;
signal mst_modf_err_to_axi_clk : std_logic;
signal mst_modf_err_to_axi4_clk : std_logic;
signal Rx_FIFO_Full_to_axi4_clk : std_logic;
signal Rx_FIFO_Full_to_axi_clk : std_logic;
signal Rx_FIFO_Full : std_logic;
signal Rx_FIFO_Full_org : std_logic;
signal Rx_FIFO_Empty_Synced_in_SPI_domain : std_logic;
signal Rx_FIFO_Empty_Synced_in_AXI_domain : std_logic;
signal one_byte_xfer : std_logic;
signal two_byte_xfer : std_logic;
signal four_byte_xfer : std_logic;
signal XIP_trans_error : std_logic;
signal XIP_trans_cdc_to_error : std_logic;
signal load_cmd : std_logic;
signal load_cmd_to_spi_clk : std_logic;
--signal load_axi_data_frm_axi_clk : std_logic;
signal load_cmd_frm_axi_clk : std_logic;
signal axi_len_two : std_logic;
signal axi_len_four : std_logic;
signal axi_len_eight : std_logic;
signal axi_len_sixteen : std_logic;
signal reset_inversion : std_logic;
signal new_tr : std_logic;
signal SR_5_Tx_Empty_int : std_logic;
signal only_last_count : std_logic;
signal rx_fifo_cntr_rst, rx_fifo_not_empty : std_logic;
signal store_date_in_drr_fifo_d1 : std_logic;
signal store_date_in_drr_fifo_d2 : std_logic;
signal store_date_in_drr_fifo_d3 : std_logic;
signal xip_ns_state_idle : std_logic;
signal wrap_around_d1 : std_logic;
signal wrap_ack : std_logic;
signal wrap_ack_1 : std_logic;
signal wrap_around_d2 : std_logic;
signal wrap_around_d3 : std_logic;
signal start_after_wrap : std_logic;
signal store_last_b4_wrap : std_logic;
signal wrp_addr_len_16_siz_32 : std_logic;
signal wrp_addr_len_8_siz_32 : std_logic;
signal wrp_addr_len_4_siz_32 : std_logic;
signal wrp_addr_len_2_siz_32 : std_logic;
signal wrp_addr_len_16_siz_16 : std_logic;
signal wrp_addr_len_8_siz_16 : std_logic;
signal wrp_addr_len_4_siz_16 : std_logic;
signal wrp_addr_len_2_siz_16, start_after_wrap_d1 : std_logic;
signal SS_O_1 : std_logic_vector((C_NUM_SS_BITS-1) downto 0);
signal WB_wr_en_CMD : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);-- (7 downto 0);
signal WB_wr_sr_CMD : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);-- (7 downto 0);
signal WB_wr_sr_DATA : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);-- (7 downto 0);
signal WB_wr_hpm_CMD : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);-- (7 downto 0);
signal wb_wr_en_done : std_logic;
signal wb_wr_sr_done : std_logic;
signal wb_wr_sr_data_done : std_logic;
signal wb_wr_hpm_done : std_logic;
signal load_wr_en_cmd : std_logic;
signal load_wr_sr_cmd : std_logic;
signal load_wr_sr_d0 : std_logic;
signal load_wr_sr_d1 : std_logic;
signal load_rd_sr : std_logic;
signal load_wr_hpm : std_logic;
signal wb_hpm_done : std_logic;
signal wb_hpm_done_reg : std_logic;
signal dis_sr_5_empty_reg : std_logic;
signal dis_sr_5_empty : std_logic;
signal wb_hpm_done_frm_spi,wb_hpm_done_frm_spi_clk,wb_hpm_done_to_axi : std_logic;
signal hpm_under_process : std_logic;
signal hpm_under_process_d1 : std_logic;
signal s_axi_rlast_cmb : std_logic;
signal store_date_in_drr_fifo_en : std_logic;
signal XIP_trans_error_cmb, XIP_trans_error_d1, XIP_trans_error_d2, XIP_trans_error_d3 : std_logic;
signal axi4_tr_over_d1, axi4_tr_over_d2 : std_logic;
signal arready_d1, arready_d2, arready_d3 : std_logic;
signal XIPSR_CPHA_CPOL_ERR_d1, XIPSR_CPHA_CPOL_ERR_d2 : std_logic;
signal axi4_tr_over_d3 : std_logic;
signal last_data_acked_int_2 : std_logic;
signal XIP_trans_error_int_2 : std_logic;
signal s_axi_arready_int_2 : std_logic;
-- signal XIP_trans_error_cmb : std_logic;
-- signal axi4_tr_over_d1, axi4_tr_over_d2 : std_logic;
-- signal arready_d1, arready_d2, arready_d3 : std_logic;
-- signal XIPSR_CPHA_CPOL_ERR_d1, XIPSR_CPHA_CPOL_ERR_d2 : std_logic;
-- signal axi4_tr_over_d3 : std_logic;
-- signal last_data_acked_int_2 : std_logic;
-- signal XIP_trans_error_int_2 : std_logic;
-- signal s_axi_arready_int_2 : std_logic;
signal Rx_FIFO_Empty_d1, Rx_FIFO_Empty_d2 : std_logic;
signal XIPSR_CPHA_CPOL_ERR_4 : std_logic;
--signal mst_modf_err_to_axi4clk: std_logic;
signal xip_done : std_logic;
signal en_xip : std_logic;
signal new_tr_at_axi4 : std_logic;
signal axi4_tr_over : std_logic;
signal fifo_ren :std_logic;
--attribute ASYNC_REG : string;
--attribute ASYNC_REG of XIP_TRANS_ERROR_AXI2AXI4_CDC : label is "TRUE";
--attribute ASYNC_REG of Rx_FIFO_Empty_AXI42AXI : label is "TRUE";
--attribute ASYNC_REG of CPHA_CPOL_ERR_AXI2AXI4_CDC : label is "TRUE";
--attribute ASYNC_REG of ARREADY_PULSE_AXI42AXI_CDC: label is "TRUE";
--attribute ASYNC_REG of AXI4_TR_OVER_AXI42AXI_CDC : label is "TRUE";
constant LOGIC_CHANGE : integer range 0 to 1 := 1;
constant MTBF_STAGES_AXI2S : integer range 0 to 6 := 3 ;
constant MTBF_STAGES_S2AXI : integer range 0 to 6 := 4 ;
constant MTBF_STAGES_AXI2AXILITE : integer range 0 to 6 := 4 ;
-----
begin
-----
S_AXI4_WREADY <= '0';
S_AXI4_BID <= (others => '0');
S_AXI4_BRESP <= (others => '0');
S_AXI4_BVALID <= '0';
S_AXI4_AWREADY<= '0';
RX_FIFO_EMPTY_SYNC_AXI4_2_AXI_CDC : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1, -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => 2
)
port map (
prmry_aclk => S_AXI4_ACLK ,
prmry_resetn => '0',
prmry_in => Rx_FIFO_Empty,
scndry_aclk => S_AXI_ACLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => '0' ,
scndry_out => Rx_FIFO_Empty_Synced_in_AXI_domain
);
RX_FIFO_EMPTY_SYNC_AXI_2_SPI_CDC : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1, -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => 2
)
port map (
prmry_aclk => S_AXI4_ACLK ,
prmry_resetn => '0',
prmry_in => Rx_FIFO_Empty,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => '0' ,
scndry_out => Rx_FIFO_Empty_Synced_in_SPI_domain
);
Rx_FIFO_Full <= Rx_FIFO_Full_org and not Rx_FIFO_Empty_Synced_in_SPI_domain;
valid_decode <= S_AXI4_ARVALID and xip_pr_state_idle;
reset_inversion <= not S_AXI4_ARESET;
-- address decoder and CS generation in AXI interface
I_DECODER : entity axi_quad_spi_v3_2_8.qspi_address_decoder
generic map
(
C_BUS_AWIDTH => XIP_ADDR_BITS, -- C_S_AXI4_ADDR_WIDTH,
C_S_AXI4_MIN_SIZE => XIP_MIN_SIZE,
C_ARD_ADDR_RANGE_ARRAY=> C_XIP_FULL_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_XIP_FULL_ARD_NUM_CE_ARRAY,
C_FAMILY => "nofamily"
)
port map
(
Bus_clk => S_AXI4_ACLK, -- in std_logic;
Bus_rst => reset_inversion, -- in std_logic;
Address_In_Erly => S_AXI4_ARADDR(XIP_ADDR_BITS-1 downto 0), -- in std_logic_vector(0 to C_BUS_AWIDTH-1);
Address_Valid_Erly => s_axi_arready_cmb, -- in std_logic;
Bus_RNW => valid_decode, -- in std_logic;
Bus_RNW_Erly => valid_decode, -- in std_logic;
CS_CE_ld_enable => s_axi_arready_cmb, -- in std_logic;
Clear_CS_CE_Reg => temp_i, -- in std_logic;
RW_CE_ld_enable => s_axi_arready_cmb, -- in std_logic;
CS_for_gaps => open, -- out std_logic;
-- Decode output signals
CS_Out => SS_frm_axi,
RdCE_Out => open,
WrCE_Out => open
);
-------------------------------------------------
STORE_AXI_ARBURST_P: process (S_AXI4_ACLK) is
begin
if (S_AXI4_ACLK'event and S_AXI4_ACLK='1') then
if (S_AXI4_ARESET = ACTIVE_HIGH_RESET) then -- S_AXI4_ARESET is already inverted and made active high
type_of_burst <= '0';-- "01"; -- default is INCR burst
elsif(s_axi_arready_cmb = '1')then
type_of_burst <= S_AXI4_ARBURST(1) ;
end if;
end if;
end process STORE_AXI_ARBURST_P;
-----------------------
S_AXI4_ARREADY_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
S_AXI4_ARREADY <= '0';
else
S_AXI4_ARREADY <= s_axi_arready_cmb;
end if;
end if;
end process S_AXI4_ARREADY_P;
-- S_AXI4_ARREADY <= s_axi_arready_cmb;
STORE_AXI_LENGTH_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
axi_length <= (others => '0');
elsif(s_axi_arready_cmb = '1')then
axi_length <= S_AXI4_ARLEN;
end if;
end if;
end process STORE_AXI_LENGTH_P;
---------------------------------------------------
STORE_AXI_SIZE_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
size_length <= (others => '0');
elsif(s_axi_arready_cmb = '1')then
size_length <= S_AXI4_ARSIZE(1 downto 0);
end if;
end if;
end process STORE_AXI_SIZE_P;
-------------------------------------------------------------------------------
REG_RID_P: process (S_AXI4_ACLK) is
begin
if (S_AXI4_ACLK'event and S_AXI4_ACLK='1') then
if (S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
S_AXI4_RID_reg <= (others=> '0');
elsif(s_axi_arready_cmb = '1')then
S_AXI4_RID_reg <= S_AXI4_ARID ;
end if;
end if;
end process REG_RID_P;
----------------------
S_AXI4_RID <= S_AXI4_ARID when (s_axi_arready_cmb = '1') else S_AXI4_RID_reg; --kar S_AXI4_RID_reg
-----------------------------
OLD_LOGIC_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
STORE_AXI_ADDR_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
XIP_ADDR <= (others => '0');
elsif(s_axi_arready_cmb = '1')then
XIP_ADDR <= S_AXI4_ARADDR(23 downto 0);-- support for 24 bit address
end if;
end if;
end process STORE_AXI_ADDR_P;
end generate OLD_LOGIC_GEN;
---------------------------
NEW_LOGIC_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
STORE_AXI_ADDR_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
XIP_ADDR <= (others => '0');
elsif(s_axi_arready_cmb = '1')then
XIP_ADDR <= S_AXI4_ARADDR(C_SPI_MEM_ADDR_BITS-1 downto 0);-- support for 24 or 32 bit address
end if;
end if;
end process STORE_AXI_ADDR_P;
end generate NEW_LOGIC_GEN;
---------------------------
------------------------------------------------------------------------------
ONE_BYTE_XFER_P:process(S_AXI4_ACLK) is
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
one_byte_xfer <= '0';
elsif(s_axi_arready_cmb = '1')then
one_byte_xfer <= not(or_reduce(S_AXI4_ARSIZE(1 downto 0)));
end if;
end if;
end process ONE_BYTE_XFER_P;
TWO_BYTE_XFER_P:process(S_AXI4_ACLK) is
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
two_byte_xfer <= '0';
elsif(s_axi_arready_cmb = '1')then
two_byte_xfer <= S_AXI4_ARSIZE(0);
end if;
end if;
end process TWO_BYTE_XFER_P;
FOUR_BYTE_XFER_P:process(S_AXI4_ACLK) is
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
four_byte_xfer <= '0';
elsif(s_axi_arready_cmb = '1')then
four_byte_xfer <= S_AXI4_ARSIZE(1);
end if;
end if;
end process FOUR_BYTE_XFER_P;
---------------------------------------------------------------------------------
STORE_DTR_LENGTH_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
dtr_length <= (others => '0');
elsif(s_axi_arready_cmb = '1')then
dtr_length <= S_AXI4_ARLEN;-- + "00000001";
-- elsif(S_AXI4_RREADY = '1' and s_axi_rvalid_i = '1') then
--elsif(Rx_FIFO_rd_ack = '1') then
elsif(fifo_ren = '1') then
dtr_length <= dtr_length - '1';
end if;
end if;
end process STORE_DTR_LENGTH_P;
-----------------------------------------------------
STORE_WRITE_LENGTH_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then -- if(xip_sm_ps = IDLE)then
write_length <= (others => '0');
elsif(s_axi_arready_cmb = '1')then
write_length <= S_AXI4_ARLEN + "00000001";
elsif(spiXfer_done_to_axi_1 = '1')then
write_length <= write_length - '1';
end if;
end if;
end process STORE_WRITE_LENGTH_P;
-----------------------------------------------------
--dtr_cntr_empty <= or_Reduce(dtr_length);
-----------------------------------------------------
last_bt_one_data_cmb <= not(or_reduce(dtr_length(C_NUM_TRANSFER_BITS-1 downto 1))) and
dtr_length(0) and
S_AXI4_RREADY;
last_data_cmb <= not(or_reduce(dtr_length(C_NUM_TRANSFER_BITS-1 downto 0)));
RX_FIFO_FULL_CNTR_I : entity axi_quad_spi_v3_2_8.counter_f
generic map(
C_NUM_BITS => RX_FIFO_CNTR_WIDTH,
C_FAMILY => "nofamily"
)
port map(
Clk => S_AXI4_ACLK, -- in
Rst => S_AXI4_ARESET, -- '0', -- in
-- coverage off
Load_In => ALL_1, -- in
-- coverage on
Count_Enable => updown_cnt_en_rx, -- in
----------------
Count_Load => s_axi_arready_cmb,-- in
----------------
Count_Down => down_cnt_en_rx, -- in
Count_Out => rx_fifo_count, -- out std_logic_vector
Carry_Out => open -- out
);
updown_cnt_en_rx <= s_axi_arready_cmb or
spiXfer_done_to_axi_1 or
(down_cnt_en_rx); -- this is to make the counter enable for decreasing.
down_cnt_en_rx <= S_AXI4_RREADY and s_axi_rvalid_i;
only_last_count <= not(or_reduce(rx_fifo_count(RX_FIFO_CNTR_WIDTH-1 downto 0))) and
last_data_cmb;
rx_fifo_not_empty <= or_reduce(rx_fifo_count(RX_FIFO_CNTR_WIDTH-1 downto 0));
LAST_DATA_ACKED_P: process (S_AXI4_ACLK) is
-----------------
begin
-----
if (S_AXI4_ACLK'event and S_AXI4_ACLK='1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
last_data_acked <= '0';
else
if(S_AXI4_RREADY = '1' and last_data_acked = '1') then -- AXI Ready and Rlast active
last_data_acked <= '0';
elsif(S_AXI4_RREADY = '0' and last_data_acked = '1')then-- AXI not Ready and Rlast active, then hold the RLAST signal
last_data_acked <= '1';
else
last_data_acked <=(last_data_cmb and
Rx_FIFO_rd_ack);
end if;
end if;
end if;
end process LAST_DATA_ACKED_P;
------------------------------
S_AXI4_RLAST <= '1' when (last_data_cmb='1' and S_AXI4_ARESET /= ACTIVE_HIGH_RESET ) else '0';--last_data_acked;
--------------------------------
S_AXI4_RDATA_RESP_P : process (S_AXI4_ACLK) is
begin
if S_AXI4_ACLK'event and S_AXI4_ACLK = '1' then
if (S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
S_AXI4_RRESP_i <= (others => '0');
--karS_AXI4_RDATA_i <= (others => '0');
else-- if(S_AXI4_RREADY = '1' )then -- and (Rx_FIFO_Empty = '0')then
S_AXI4_RRESP_i <= --(rd_error_int or mst_modf_err_to_axi_clk) & '0';
(mst_modf_err_to_axi4_clk) & '0';
--karS_AXI4_RDATA_i <= Data_From_Rx_FIFO;
end if;
end if;
end process S_AXI4_RDATA_RESP_P;
--------------------------------
S_AXI4_RRESP <= (mst_modf_err_to_axi4_clk) & '0';--S_AXI4_RRESP_i;
S_AXI4_RDATA <= Data_From_Rx_FIFO;--S_AXI4_RDATA_i;
-------------------------------
-----------------------------
-- S_AXI_RVALID_I_P : below process generates the RVALID response on read channel
----------------------
--karS_AXI_RVALID_I_P : process (S_AXI4_ACLK) is
--kar begin
--kar if S_AXI4_ACLK'event and S_AXI4_ACLK = '1' then
--kar if (S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
--kar s_axi_rvalid_i <= '0';
--kar elsif(S_AXI4_RREADY = '1' and (s_axi_rvalid_i = '1')) then -- and (s_axi_rvalid_i = '1') then -- AXI Ready and Rlast active
--kar s_axi_rvalid_i <= '0';--not(Rx_FIFO_Empty);--Rx_FIFO_rd_ack; -- '0';
--kar elsif(S_AXI4_RREADY = '1' and (s_axi_rvalid_i = '0')) then -- and (s_axi_rvalid_i = '1') then -- AXI Ready and Rlast active
--kar s_axi_rvalid_i <= not(Rx_FIFO_Empty);--Rx_FIFO_rd_ack; -- '0';
--kar elsif(S_AXI4_RREADY = '0') and (s_axi_rvalid_i = '1') then
--kar s_axi_rvalid_i <= s_axi_rvalid_i;
--kar else
--kar s_axi_rvalid_i <= not(Rx_FIFO_Empty);--Rx_FIFO_rd_ack;
--kar end if;
--kar end if;
--karend process S_AXI_RVALID_I_P;
-----------------------------
--karS_AXI_RVALID_I_P : process (S_AXI4_ACLK) is
--kar begin
--kar if S_AXI4_ACLK'event and S_AXI4_ACLK = '1' then
--kar if (S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
--kar s_axi_rvalid_i <= '0';
--kar else
--kar s_axi_rvalid_i <= not(Rx_FIFO_Empty);
--kar end if;
--kar end if;
--kar end process S_AXI_RVALID_I_P;
s_axi_rvalid_i <= not(Rx_FIFO_Empty);
S_AXI4_RVALID <= s_axi_rvalid_i;
fifo_ren <= S_AXI4_RREADY and s_axi_rvalid_i;
-- -----------------------------
--fifo_non_empty <= not(Rx_FIFO_Empty);
-----------------------------
-- REN_Generation : below process generates the Fifo_Ren
----------------------
--karREN_Generation : process (S_AXI4_ACLK) is
--kar begin
--kar if S_AXI4_ACLK'event and S_AXI4_ACLK = '1' then
--kar if (S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
--kar fifo_ren <= '0';
--kar elsif(S_AXI4_RREADY = '1' and (s_axi_rvalid_i = '1')) then
--kar fifo_ren <= '1';
--kar else
--kar fifo_ren <= '0';--Rx_FIFO_rd_ack;
--kar end if;
--kar end if;
--karend process REN_Generation;
-----------------------------
xip_pr_state_idle <= '1' when xip_sm_ps = IDLE else '0';
xip_ns_state_idle <= '1' when xip_sm_ns = IDLE else '0';
rready_i <= S_AXI4_RREADY and not last_data_cmb;
------------------------------------------------------------------------------
XIP_trans_error_cmb <= not(or_reduce(S_AXI4_ARBURST)) and (S_AXI4_ARVALID);
-- XIP_TR_ERROR_PULSE_STRETCH_1: single pulse for AXI4 transaction error
LOGIC_GENERATION_FDR : if (Async_Clk = 0) generate
attribute ASYNC_REG : string;
attribute ASYNC_REG of XIP_TRANS_ERROR_AXI2AXI4_CDC : label is "TRUE";
--attribute ASYNC_REG of Rx_FIFO_Empty_AXI42AXI : label is "TRUE";
attribute ASYNC_REG of CPHA_CPOL_ERR_AXI2AXI4_CDC : label is "TRUE";
attribute ASYNC_REG of ARREADY_PULSE_AXI42AXI_CDC: label is "TRUE";
attribute ASYNC_REG of AXI4_TR_OVER_AXI42AXI_CDC : label is "TRUE";
begin
XIP_TR_ERROR_PULSE_STRETCH_1: process(S_AXI4_ACLK)is
begin
if(S_AXI4_ACLK'event and S_AXI4_ACLK= '1') then
if(S_AXI4_ARESET = '1') then
XIP_trans_error_int_2 <= '0';
else
XIP_trans_error_int_2 <= XIP_trans_error_cmb xor
XIP_trans_error_int_2;
end if;
end if;
end process XIP_TR_ERROR_PULSE_STRETCH_1;
-------------------------------------
XIP_TRANS_ERROR_AXI2AXI4_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => XIP_trans_error_d1,
C => S_AXI_ACLK,
D => XIP_trans_error_int_2,
R => S_AXI_ARESETN
);
XIP_TRANS_ERROR_AXI2AXI4_1: component FDR
generic map(INIT => '0'
)port map (
Q => XIP_trans_error_d2,
C => S_AXI_ACLK,
D => XIP_trans_error_d1,
R => S_AXI_ARESETN
);
XIP_TRANS_ERROR_AXI2AXI4_2: component FDR
generic map(INIT => '0'
)port map (
Q => XIP_trans_error_d3,
C => S_AXI_ACLK,
D => XIP_trans_error_d2,
R => S_AXI_ARESETN
);
XIP_trans_error <= XIP_trans_error_d2 xor XIP_trans_error_d3;
------------------------------------------------------------------------------
--mst_modf_err_to_axi <= mst_modf_err_d2;
-- TO XIP Status Register
-- LAST_DATA_PULSE_STRETCH_1: single pulse for AXI4 transaction completion
LAST_DATA_PULSE_STRETCH_1: process(S_AXI4_ACLK)is
begin
if(S_AXI4_ACLK'event and S_AXI4_ACLK= '1') then
if(S_AXI4_ARESET = '1') then
last_data_acked_int_2 <= '0';
else
last_data_acked_int_2 <= last_data_acked xor
last_data_acked_int_2;
end if;
end if;
end process LAST_DATA_PULSE_STRETCH_1;
-------------------------------------
AXI4_TR_OVER_AXI42AXI_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => axi4_tr_over_d1,
C => S_AXI_ACLK,
D => last_data_acked_int_2,
R => S_AXI_ARESETN
);
AXI4_TR_OVER_AXI42AXI_1: component FDR
generic map(INIT => '0'
)port map (
Q => axi4_tr_over_d2,
C => S_AXI_ACLK,
D => axi4_tr_over_d1,
R => S_AXI_ARESETN
);
AXI4_TR_OVER_AXI42AXI_2: component FDR
generic map(INIT => '0'
)port map (
Q => axi4_tr_over_d3,
C => S_AXI_ACLK,
D => axi4_tr_over_d2,
R => S_AXI_ARESETN
);
axi4_tr_over <= axi4_tr_over_d2 xor axi4_tr_over_d3;
-------------------------------------------------------------
-- ARREADY_PULSE_STRETCH_1: single pulse for AXI4 transaction acceptance
ARREADY_PULSE_STRETCH_1: process(S_AXI4_ACLK)is
begin
if(S_AXI4_ACLK'event and S_AXI4_ACLK= '1') then
if(S_AXI4_ARESET = '1') then
s_axi_arready_int_2 <= '0';
else
s_axi_arready_int_2 <= s_axi_arready_cmb xor
s_axi_arready_int_2;
end if;
end if;
end process ARREADY_PULSE_STRETCH_1;
-------------------------------------
ARREADY_PULSE_AXI42AXI_CDC: component FDR
generic map(INIT => '1'
)port map (
Q => arready_d1,
C => S_AXI_ACLK,
D => s_axi_arready_int_2,
R => S_AXI_ARESETN
);
ARREADY_PULSE_AXI42AXI_2: component FDR
generic map(INIT => '1'
)port map (
Q => arready_d2,
C => S_AXI_ACLK,
D => arready_d1,
R => S_AXI_ARESETN
);
ARREADY_PULSE_AXI42AXI_3: component FDR -- 2/21/2012
generic map(INIT => '1'
)port map (
Q => arready_d3,
C => S_AXI_ACLK,
D => arready_d2,
R => S_AXI_ARESETN
);
new_tr_at_axi4 <= arready_d2 xor arready_d3;
-------------------------------------
------------------------------------------------------------------------------
-- CPHA_CPOL_ERR_AXI2AXI4_CDC: CDC flop at cross clock boundary
CPHA_CPOL_ERR_AXI2AXI4_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => XIPSR_CPHA_CPOL_ERR_d1,
C => S_AXI4_ACLK,
D => XIPSR_CPHA_CPOL_ERR,
R => S_AXI4_ARESET
);
CPHA_CPOL_ERR_AXI2AXI4_1: component FDR
generic map(INIT => '0'
)port map (
Q => XIPSR_CPHA_CPOL_ERR_d2,
C => S_AXI4_ACLK,
D => XIPSR_CPHA_CPOL_ERR_d1,
R => S_AXI4_ARESET
);
XIPSR_CPHA_CPOL_ERR_4 <= XIPSR_CPHA_CPOL_ERR_d2;
-------------------------------------------------------------------------------
end generate LOGIC_GENERATION_FDR;
LOGIC_GENERATION_CDC : if (Async_Clk = 1) generate
--=================================================================================
XIP_TR_ERROR_PULSE_STRETCH_1_P: process(S_AXI4_ACLK)is
begin
if(S_AXI4_ACLK'event and S_AXI4_ACLK= '1') then
if(S_AXI4_ARESET = '1') then
XIP_trans_error_int_2 <= '0';
else
XIP_trans_error_int_2 <= XIP_trans_error_cmb xor
XIP_trans_error_int_2;
end if;
end if;
end process XIP_TR_ERROR_PULSE_STRETCH_1_P;
XIP_TRANS_ERROR_AXI42AXI: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2AXILITE
)
port map (
prmry_aclk => S_AXI4_ACLK ,
prmry_resetn => S_AXI_ARESETN ,
prmry_in => XIP_trans_error_int_2 ,
scndry_aclk => S_AXI_ACLK ,
prmry_vect_in => (others => '0') ,
scndry_resetn => S_AXI_ARESETN ,
scndry_out => XIP_trans_error_d2
);
XIP_TR_ERROR_PULSE_STRETCH_1: process(S_AXI_ACLK)is
begin
if(S_AXI_ACLK'event and S_AXI_ACLK= '1') then
XIP_trans_error_d3 <= XIP_trans_error_d2 ;
end if;
end process XIP_TR_ERROR_PULSE_STRETCH_1;
XIP_trans_cdc_to_error <= XIP_trans_error_d2 xor XIP_trans_error_d3;
XIP_trans_error <= XIP_trans_cdc_to_error;
--=================================================================================
LAST_DATA_PULSE_STRETCH_1_CDC: process(S_AXI4_ACLK)is
begin
if(S_AXI4_ACLK'event and S_AXI4_ACLK= '1') then
if(S_AXI4_ARESET = '1') then
last_data_acked_int_2 <= '0';
--axi4_tr_over_d1 <= '0';
else
last_data_acked_int_2 <= last_data_acked xor
last_data_acked_int_2;
--axi4_tr_over_d1 <= last_data_acked_int_2;
end if;
end if;
end process LAST_DATA_PULSE_STRETCH_1_CDC;
AXI4_TR_OVER_AXI42AXI: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 1 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2AXILITE
)
port map (
prmry_aclk => S_AXI4_ACLK ,
prmry_resetn => S_AXI4_ARESET ,
prmry_in => last_data_acked_int_2 ,
scndry_aclk => S_AXI_ACLK ,
prmry_vect_in => (others => '0') ,
scndry_resetn => S_AXI_ARESETN ,
scndry_out => axi4_tr_over_d2
);
LAST_DATA_PULSE_STRETCH_1: process(S_AXI_ACLK)is
begin
if(S_AXI_ACLK'event and S_AXI_ACLK= '1') then
axi4_tr_over_d3 <= axi4_tr_over_d2 ;
-- end if;
end if;
end process LAST_DATA_PULSE_STRETCH_1;
axi4_tr_over <= axi4_tr_over_d2 xor axi4_tr_over_d3;
--=================================================================================
ARREADY_PULSE_STRETCH_1_CDC: process(S_AXI4_ACLK)is
begin
if(S_AXI4_ACLK'event and S_AXI4_ACLK= '1') then
if(S_AXI4_ARESET = '1') then
s_axi_arready_int_2 <= '1';
--arready_d1 <= '0';
else
s_axi_arready_int_2 <= s_axi_arready_cmb xor
s_axi_arready_int_2;
--arready_d1 <= s_axi_arready_int_2;
end if;
end if;
end process ARREADY_PULSE_STRETCH_1_CDC;
ARREADY_PULSE_AXI42AXI: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 1 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2AXILITE
)
port map (
prmry_aclk => S_AXI4_ACLK ,
prmry_resetn => S_AXI4_ARESET ,
prmry_in => s_axi_arready_int_2 ,
scndry_aclk => S_AXI_ACLK ,
prmry_vect_in => (others => '0') ,
scndry_resetn => S_AXI_ARESETN ,
scndry_out => arready_d2
);
ARREADY_PULSE_STRETCH_1: process(S_AXI_ACLK)is
begin
if(S_AXI_ACLK'event and S_AXI_ACLK= '1') then
arready_d3 <= arready_d2;
-- end if;
end if;
end process ARREADY_PULSE_STRETCH_1;
new_tr_at_axi4 <= arready_d2 xor arready_d3;
--==================================================================================
CPHA_CPOL_ERR_AXI2AXI4: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2AXILITE
)
port map (
prmry_aclk => S_AXI_ACLK ,
prmry_resetn => S_AXI_ARESETN ,
prmry_in => XIPSR_CPHA_CPOL_ERR ,
scndry_aclk => S_AXI4_ACLK ,
prmry_vect_in => (others => '0') ,
scndry_resetn => S_AXI4_ARESET ,
scndry_out => XIPSR_CPHA_CPOL_ERR_4
);
--==================================================================================
end generate LOGIC_GENERATION_CDC;
TO_XIPSR_axi_rx_empty <= Rx_FIFO_Empty_Synced_in_AXI_domain;
--XIPSR_RX_EMPTY_P: process(S_AXI_ACLK)is
--begin
-- if(S_AXI_ACLK'event and S_AXI_ACLK = '1')then
-- if(S_AXI_ARESETN = ACTIVE_HIGH_RESET) then
-- TO_XIPSR_axi_rx_empty <= '1';
-- elsif(axi4_tr_over = '1')then
-- TO_XIPSR_axi_rx_empty <= '1';
-- elsif(new_tr_at_axi4 = '1')then
-- TO_XIPSR_axi_rx_empty <= '0';
-- end if;
-- end if;
--end process XIPSR_RX_EMPTY_P;
-------------------------------------
TO_XIPSR_trans_error <= XIP_trans_error;
TO_XIPSR_mst_modf_err <= mst_modf_err_to_axi_clk;
TO_XIPSR_axi_rx_full <= Rx_FIFO_Full_to_axi_clk;
-- XIP_PS_TO_NS_PROCESS: stores the next state memory
XIP_PS_TO_NS_PROCESS: process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
xip_sm_ps <= IDLE;
else
xip_sm_ps <= xip_sm_ns;
end if;
end if;
end process XIP_PS_TO_NS_PROCESS;
-----------------------------
-- XIP_SM_P: below state machine is AXI interface state machine and controls the
-- acceptance of new transaction as well as monitors data transaction
XIP_SM_P:process(
xip_sm_ps ,
S_AXI4_ARVALID ,
S_AXI4_RREADY ,
S_AXI4_ARBURST ,
XIP_trans_error_cmb ,
mst_modf_err_to_axi4_clk,
Rx_FIFO_Full_to_Axi4_clk,
XIPSR_CPHA_CPOL_ERR_4 ,
Rx_FIFO_Empty ,
wb_hpm_done_to_axi ,
spiXfer_done_to_axi_1 ,
last_data_cmb ,
Rx_FIFO_rd_ack ,--,
last_data_acked
--wrap_around_to_axi_clk ,
--last_bt_one_data_cmb ,
--Rx_FIFO_Empty ,
--only_last_count ,
--rx_fifo_not_empty ,
--rx_fifo_count ,
)is
begin
-----
s_axi_arready_cmb <= '0';
load_axi_data_frm_axi <= '0';
load_cmd <= '0';
s_axi_rlast_cmb <= '0';
s_axi_rvalid_cmb <= '0';
last_data <= '0';
--IO0_T_cntrl_axi <= '1';
--IO1_T_cntrl_axi <= '1';
--IO2_T_cntrl_axi <= '1';
--IO3_T_cntrl_axi <= '1';
--SCK_T_cntrl_axi <= '1';
temp_i <= '0';
case xip_sm_ps is
when IDLE => --if(XIP_cmd_error = '0') then
if(S_AXI4_ARVALID = '1') and
(XIP_trans_error_cmb = '0') and
(mst_modf_err_to_axi4_clk = '0') and
(Rx_FIFO_Full_to_axi4_clk = '0') and
(XIPSR_CPHA_CPOL_ERR_4 = '0') and
(Rx_FIFO_Empty = '1') and
(wb_hpm_done_to_axi = '1')
then
s_axi_arready_cmb <= S_AXI4_ARVALID;
load_axi_data_frm_axi <= S_AXI4_ARVALID;
load_cmd <= S_AXI4_ARVALID;
xip_sm_ns <= RD_BURST;
else
xip_sm_ns <= IDLE;
end if;
when RD_BURST =>
--if(last_data_cmb = '1') and (Rx_FIFO_rd_ack = '1') then--(rx_fifo_count = "000001") then
if (last_data_acked = '1') then
if(S_AXI4_RREADY = '1') then
temp_i <= '1';
xip_sm_ns <= IDLE;
else
xip_sm_ns <= RD_BURST;
end if;
else
xip_sm_ns <= RD_BURST;
end if;
-- coverage off
when others => xip_sm_ns <= IDLE;
-- coverage on
end case;
end process XIP_SM_P;
----------------------
-- AXI_24_BIT_ADDR_STORE_GEN: stores 24 bit axi address
AXI_24_BIT_ADDR_STORE_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
LOAD_TRANSMIT_ADDR_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
Transmit_addr_int <= (others => '0');
elsif(load_axi_data_frm_axi = '1') then
Transmit_addr_int <= S_AXI4_ARADDR(23 downto 0);-- & XIPCR_7_0_CMD;
end if;
end if;
end process LOAD_TRANSMIT_ADDR_P;
end generate AXI_24_BIT_ADDR_STORE_GEN;
-----------------------------------------
-- AXI_32_BIT_ADDR_STORE_GEN: stores 32 bit axi address
AXI_32_BIT_ADDR_STORE_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate -- 3/30/2013 updated for 32 or 24 bit addressing modes
begin
LOAD_TRANSMIT_ADDR_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
Transmit_addr_int <= (others => '0');
elsif(load_axi_data_frm_axi = '1') then
Transmit_addr_int <= S_AXI4_ARADDR(C_SPI_MEM_ADDR_BITS-1 downto 0);-- & XIPCR_7_0_CMD;
end if;
end if;
end process LOAD_TRANSMIT_ADDR_P;
end generate AXI_32_BIT_ADDR_STORE_GEN;
-----------------------------------------
-- 24/32-bit --
-- AXI Clk domain -- __________________ SPI clk domain
--Dout --|AXI clk |-- Din
--Rd_en --| |-- Wr_en
--Rd_clk --| |-- Wr_clk
--| |--
--Rx_FIFO_Empty --| Rx FIFO |-- Rx_FIFO_Full_org
--Rx_FIFO_almost_Empty --| |-- Rx_FIFO_almost_Full
--Rx_FIFO_occ_Reversed --| |--
--Rx_FIFO_rd_ack --| |--
--| |--
--| |--
--| |--
--|__________________|--
-------------------------------------------------------------------------------
XIP_RECEIVE_FIFO_II: entity lib_fifo_v1_0_5.async_fifo_fg
generic map(
-- 3/30/2013 starts
C_PRELOAD_LATENCY => 0 ,-- this is newly added and async_fifo_fg is referred from proc common v4_0
C_PRELOAD_REGS => 1 ,-- this is newly added and async_fifo_fg is referred from proc common v4_0
-- 3/30/2013 ends
-- variables
C_ALLOW_2N_DEPTH => 1 , -- : Integer := 0; -- New paramter to leverage FIFO Gen 2**N depth
C_FAMILY => C_FAMILY , -- : String := "virtex5"; -- new for FIFO Gen
C_DATA_WIDTH => C_S_AXI4_DATA_WIDTH , -- : integer := 16;
C_FIFO_DEPTH => C_XIP_FIFO_DEPTH , -- : integer := 256;
C_RD_COUNT_WIDTH => C_RD_COUNT_WIDTH_INT, -- : integer := 3 ;
C_WR_COUNT_WIDTH => C_WR_COUNT_WIDTH_INT, -- : integer := 3 ;
C_HAS_ALMOST_EMPTY => 1 , -- : integer := 1 ;
C_HAS_ALMOST_FULL => 1 , -- : integer := 1 ;
C_HAS_RD_ACK => 1 , -- : integer := 0 ;
C_HAS_RD_COUNT => 1 , -- : integer := 1 ;
C_HAS_WR_ACK => 1 , -- : integer := 0 ;
C_HAS_WR_COUNT => 1 , -- : integer := 1 ;
-- constants
C_HAS_RD_ERR => 0 , -- : integer := 0 ;
C_HAS_WR_ERR => 0 , -- : integer := 0 ;
C_RD_ACK_LOW => 0 , -- : integer := 0 ;
C_RD_ERR_LOW => 0 , -- : integer := 0 ;
C_WR_ACK_LOW => 0 , -- : integer := 0 ;
C_WR_ERR_LOW => 0 , -- : integer := 0
C_ENABLE_RLOCS => 0 , -- : integer := 0 ; -- not supported in FG
C_USE_BLOCKMEM => 0 -- : integer := 1 ; -- 0 = distributed RAM, 1 = BRAM
)
port map(
Dout => Data_From_Rx_FIFO , -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
Rd_en => fifo_ren , --S_AXI4_RREADY , -- : in std_logic := '0';
Rd_clk => S_AXI4_ACLK , -- : in std_logic := '1';
Rd_ack => Rx_FIFO_rd_ack , -- : out std_logic;
------
Din => Data_To_Rx_FIFO , -- : in std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0');
Wr_en => store_date_in_drr_fifo_en , --SPIXfer_done_Rx_Wr_en, -- , -- : in std_logic := '1';
Wr_clk => EXT_SPI_CLK , -- : in std_logic := '1';
Wr_ack => open, -- Rx_FIFO_wr_ack_open, -- : out std_logic;
------
Full => Rx_FIFO_Full_org, --Rx_FIFO_Full, -- : out std_logic;
Empty => Rx_FIFO_Empty , -- : out std_logic;
Almost_full => Rx_FIFO_almost_Full , -- : out std_logic;
Almost_empty => Rx_FIFO_almost_Empty , -- : out std_logic;
Rd_count => open , -- : out std_logic_vector(C_RD_COUNT_WIDTH-1 downto 0);
------
Ainit => Rst_to_spi ,--reset_RcFIFO_ptr_int, -- reset_RcFIFO_ptr_to_spi_clk ,--Rx_FIFO_ptr_RST , -- : in std_logic := '1';
Wr_count => open , -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
Rd_err => rd_error_int , -- : out std_logic;
Wr_err => open -- : out std_logic
);
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- from SPI clock
spiXfer_done_frm_spi_clk <= store_date_in_drr_fifo_en; --spiXfer_done_int;
mst_modf_err_frm_spi_clk <= not SPISEL_sync; -- 9/7/2013 -- MODF_strobe; -- 9/7/2013
--wrap_around_frm_spi_clk <= wrap_around;
wb_hpm_done_frm_spi_clk <= wb_hpm_done;
-- from AXI clocks
--size_length_frm_axi_clk <= size_length;
one_byte_xfer_frm_axi_clk <= one_byte_xfer;
two_byte_xfer_frm_axi_clk <= two_byte_xfer;
four_byte_xfer_frm_axi_clk <= four_byte_xfer;
load_axi_data_frm_axi_clk <= load_axi_data_frm_Axi;-- 1 bit
Transmit_Addr_frm_axi_clk <= Transmit_addr_int; -- 24 bit
load_cmd_frm_axi_clk <= load_cmd;
CPOL_frm_axi_clk <= XIPCR_1_CPOL; -- 1 bit
CPHA_frm_axi_clk <= XIPCR_0_CPHA; -- 1 bit
SS_frm_axi_clk <= SS_frm_axi; -- _reg; -- based upon C_NUM_SS_BITS
type_of_burst_frm_axi_clk <= type_of_burst; -- 1 bit signal take MSB only to differentiate WRAP and INCR burst
axi_length_frm_axi_clk <= axi_length; -- 8 bit used for WRAP transfer
dtr_length_frm_axi_clk <= dtr_length; -- 8 bit used for internbal counter
XIP_CLK_DOMAIN_SIGNALS:entity axi_quad_spi_v3_2_8.xip_cross_clk_sync
generic map(
C_S_AXI4_DATA_WIDTH => C_S_AXI4_DATA_WIDTH ,
Async_Clk => Async_Clk ,
C_NUM_SS_BITS => C_NUM_SS_BITS ,
C_SPI_MEM_ADDR_BITS => XIP_ADDR_BITS
)
port map(
EXT_SPI_CLK => EXT_SPI_CLK ,
S_AXI4_ACLK => S_AXI4_ACLK ,
S_AXI4_ARESET => S_AXI4_ARESET ,
S_AXI_ACLK => S_AXI_ACLK ,
S_AXI_ARESETN => S_AXI_ARESETN ,
Rst_from_axi_cdc_to_spi => Rst_to_spi ,
----------------------------
spiXfer_done_cdc_from_spi => spiXfer_done_frm_spi_clk ,
spiXfer_done_cdc_to_axi_1 => spiXfer_done_to_axi_1 ,
----------------------------
mst_modf_err_cdc_from_spi => mst_modf_err_frm_spi_clk ,
mst_modf_err_cdc_to_axi => mst_modf_err_to_axi_clk ,
mst_modf_err_cdc_to_axi4 => mst_modf_err_to_axi4_clk ,
----------------------------
one_byte_xfer_cdc_from_axi => one_byte_xfer_frm_axi_clk ,
one_byte_xfer_cdc_to_spi => one_byte_xfer_to_spi_clk ,
----------------------------
two_byte_xfer_cdc_from_axi => two_byte_xfer_frm_axi_clk ,
two_byte_xfer_cdc_to_spi => two_byte_xfer_to_spi_clk ,
----------------------------
four_byte_xfer_cdc_from_axi => four_byte_xfer_frm_axi_clk ,
four_byte_xfer_cdc_to_spi => four_byte_xfer_to_spi_clk ,
----------------------------
load_axi_data_cdc_from_axi => load_axi_data_frm_axi_clk ,
load_axi_data_cdc_to_spi => load_axi_data_to_spi_clk ,
----------------------------
Transmit_Addr_cdc_from_axi => Transmit_Addr_frm_axi_clk ,
Transmit_Addr_cdc_to_spi => Transmit_Addr_to_spi_clk ,
----------------------------
load_cmd_cdc_from_axi => load_cmd_frm_axi_clk ,
load_cmd_cdc_to_spi => load_cmd_to_spi_clk ,
----------------------------
CPOL_cdc_from_axi => CPOL_frm_axi_clk ,
CPOL_cdc_to_spi => CPOL_to_spi_clk ,
----------------------------
CPHA_cdc_from_axi => CPHA_frm_axi_clk ,
CPHA_cdc_to_spi => CPHA_to_spi_clk ,
------------------------------
SS_cdc_from_axi => SS_frm_axi_clk ,
SS_cdc_to_spi => SS_to_spi_clk ,
----------------------------
type_of_burst_cdc_from_axi => type_of_burst_frm_axi_clk ,
type_of_burst_cdc_to_spi => type_of_burst_to_spi_clk ,
----------------------------
axi_length_cdc_from_axi => axi_length_frm_axi_clk ,
axi_length_cdc_to_spi => axi_length_to_spi_clk ,
----------------------------
dtr_length_cdc_from_axi => dtr_length_frm_axi_clk ,
dtr_length_cdc_to_spi => dtr_length_to_spi_clk , --,
----------------------------
Rx_FIFO_Full_cdc_from_spi => Rx_FIFO_Full ,
Rx_FIFO_Full_cdc_to_axi => Rx_FIFO_Full_to_axi_clk ,
Rx_FIFO_Full_cdc_to_axi4 => Rx_FIFO_Full_to_axi4_clk ,
----------------------------
wb_hpm_done_cdc_from_spi => wb_hpm_done_frm_spi_clk ,
wb_hpm_done_cdc_to_axi => wb_hpm_done_to_axi
);
-------------------------------------------------------------------------------
-- STORE_NEW_TR_P: This process is used in INCR and WRAP to check for any new transaction from AXI
STORE_NEW_TR_32_BIT_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-----
-------------------------------------
STORE_NEW_TR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
new_tr <= '0';
elsif( (load_axi_data_to_spi_clk = '1')
or (load_wr_hpm = '1') -- needed for enabling 32 bit addressing mode
or (load_wr_en = '1') -- needed for write enabling before enabling the 32 bit addressing mode
) then
new_tr <= '1';
elsif(SR_5_Tx_Empty_int = '1') then --(wrap_around = '0' and qspi_cntrl_ns = IDLE)then
new_tr <= '0';
end if;
end if;
end process STORE_NEW_TR_P;
-------------------------------------
end generate STORE_NEW_TR_32_BIT_ADDR_GEN;
---------------------------------------------
STORE_NEW_TR_24_BIT_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-----
-------------------------------------
STORE_NEW_TR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
new_tr <= '0';
elsif( (load_axi_data_to_spi_clk = '1')
or (load_wr_hpm = '1')
-- or (load_wr_en = '1')
) then
new_tr <= '1';
elsif(SR_5_Tx_Empty_int = '1') then --(wrap_around = '0' and qspi_cntrl_ns = IDLE)then
new_tr <= '0';
end if;
end if;
end process STORE_NEW_TR_P;
-------------------------------------
end generate STORE_NEW_TR_24_BIT_ADDR_GEN;
-------------------------------------------------------------------------------
-- STORE_INITAL_ADDR_P: The address frm AXI should be stored in the SPI environment
-- as the address generation logic will work in this domain.
STORE_24_BIT_SPI_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-----
-------------------------------------
STORE_INITAL_ADDR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
spi_addr <= (others => '0');
elsif(load_axi_data_to_spi_clk = '1')then
spi_addr <= "00000000" & Transmit_Addr_to_spi_clk;-- (31 downto 8);
elsif(load_wrap_addr = '1')then -- and (type_of_burst_to_spi = '1') then
spi_addr <= "00000000" & spi_addr_wrap;
end if;
end if;
end process STORE_INITAL_ADDR_P;
-------------------------------------
end generate STORE_24_BIT_SPI_ADDR_GEN;
-----------------------------------------
STORE_32_BIT_SPI_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate -- 3/30/2013
begin
-----
----------------------------------
STORE_INITAL_ADDR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
spi_addr <= (others => '0');
elsif(load_axi_data_to_spi_clk = '1')then
spi_addr <= Transmit_Addr_to_spi_clk;-- (31 downto 0);
elsif(load_wrap_addr = '1')then -- and (type_of_burst_to_spi = '1') then
spi_addr <= spi_addr_wrap;
end if;
end if;
end process STORE_INITAL_ADDR_P;
----------------------------------
end generate STORE_32_BIT_SPI_ADDR_GEN;
---------------------------------------
-------------------------------------------------------------------------------
-- below signals will store the length of AXI transaction in the SPI domain
axi_len_two <= not(or_Reduce(axi_length_to_spi_clk(3 downto 1))) and
axi_length_to_spi_clk(0);
axi_len_four <= not(or_Reduce(axi_length_to_spi_clk(3 downto 2))) and
and_reduce(axi_length_to_spi_clk(1 downto 0));
axi_len_eight <= not(axi_length_to_spi_clk(3)) and
and_Reduce(axi_length_to_spi_clk(2 downto 0));
axi_len_sixteen <= and_reduce(axi_length_to_spi_clk(3 downto 0));
-------------------------------------------------------------------------------
-- below signals store the WRAP information in SPI domain
wrap_two <= '1' when (type_of_burst_to_spi_clk = '1' and
axi_len_two = '1')
else
'0';
wrap_four <= '1' when (type_of_burst_to_spi_clk = '1' and
axi_len_four = '1')
else
'0';
wrap_eight <= '1' when (type_of_burst_to_spi_clk = '1' and
axi_len_eight = '1')
else
'0';
wrap_sixteen <= '1' when (type_of_burst_to_spi_clk = '1' and
axi_len_sixteen = '1')
else
'0';
-------------------------------------------------------------------------------
-- SPI_ADDRESS_REG: This process stores the initial address coming from the AXI in
-- two registers. one register will store this address till the
-- transaction ends, while other will be updated based upon type of
-- transaction as well as at the end of each SPI transfer. this is
-- used for internal use only.
SPI_24_BIT_ADDRESS_REG_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-----
SPI_ADDRESS_REG : process(EXT_SPI_CLK) is
--variable xfer : std_logic_vector(2 downto 0);
begin
-- xfer := four_byte_xfer_to_spi_clk & two_byte_xfer_to_spi_clk & one_byte_xfer_to_spi_clk;
if (EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if (Rst_to_spi = RESET_ACTIVE) then
spi_addr_i <= (others => '0');
spi_addr_int <= (others => '0');
else
if (load_cmd_to_spi_clk = '1') then
spi_addr_i <= Transmit_Addr_to_spi_clk(23 downto 0);
spi_addr_int <= Transmit_Addr_to_spi_clk(23 downto 0);
-- below is address generation for the WRAP mode
elsif (type_of_burst_to_spi_clk = '1') and
(SPIXfer_done_int_pulse_d2 = '1') and
(cmd_addr_sent = '1') then
spi_addr_int(23 downto 0) <= spi_addr_int(23 downto 0) + '1';
case size_length_cntr is
when "00" => -- 8-bit access
if(wrap_two = '1') then
spi_addr_i(23 downto 1) <= spi_addr_i(23 downto 1);
spi_addr_i(0) <= not (spi_addr_i(0));
elsif(wrap_four = '1') then -- the byte address increment will take 2 address bits
spi_addr_i(23 downto 2) <= spi_addr_i(23 downto 2);
spi_addr_i(1 downto 0) <= spi_addr_i(1 downto 0) + "01";
elsif(wrap_eight = '1') then -- the byte address increment will take 3 address bits
spi_addr_i(23 downto 3) <= spi_addr_i(23 downto 3);
spi_addr_i(2 downto 0) <= spi_addr_i(2 downto 0) + "001";
elsif(wrap_sixteen = '1') then -- the byte address increment will take 4 address bits for 16's wrap
spi_addr_i(23 downto 4) <= spi_addr_i(23 downto 4);
spi_addr_i(3 downto 0) <= spi_addr_i(3 downto 0) + "0001";
else
spi_addr_i <= spi_addr_i + "0001";
end if;
when "01" => -- 16-bit access
if(wrap_two = '1') then
spi_addr_i(23 downto 2) <= spi_addr_i(23 downto 2);
spi_addr_i(1 downto 0) <= spi_addr_i(1 downto 0) + "10";
elsif(wrap_four = '1') then
spi_addr_i(23 downto 3) <= spi_addr_i(23 downto 3);
spi_addr_i(2 downto 0) <= spi_addr_i(2 downto 0) + "010";
elsif(wrap_eight = '1') then
spi_addr_i(23 downto 4) <= spi_addr_i(23 downto 4);
spi_addr_i(3 downto 0) <= spi_addr_i(3 downto 0) + "0010";
elsif(wrap_sixteen = '1') then
spi_addr_i(23 downto 5) <= spi_addr_i(23 downto 5);
spi_addr_i(4 downto 0) <= spi_addr_i(4 downto 0) + "00010";
else
spi_addr_i <= spi_addr_i + "0010";
end if;
when "10" => -- 32-bit access
if(wrap_two = '1') then
spi_addr_i(23 downto 3) <= spi_addr_i(23 downto 3);
spi_addr_i(2 downto 0) <=spi_addr_i(2 downto 0) + "100";
elsif(wrap_four = '1') then
spi_addr_i(23 downto 4) <= spi_addr_i(23 downto 4);
spi_addr_i(3 downto 0) <=spi_addr_i(3 downto 0) + "0100";
elsif(wrap_eight = '1') then
spi_addr_i(23 downto 5) <= spi_addr_i(23 downto 5);
spi_addr_i(4 downto 0) <=spi_addr_i(4 downto 0) + "00100";
elsif(wrap_sixteen = '1') then
spi_addr_i(23 downto 6) <= spi_addr_i(23 downto 6);
spi_addr_i(5 downto 0) <=spi_addr_i(5 downto 0) + "000100";
else
spi_addr_i <= spi_addr_i + "0100";
end if;
-- coverage off
when others =>
spi_addr_i <= spi_addr_i;
-- coverage on
end case;
-- below is address generation for the INCR mode
elsif (type_of_burst_to_spi_clk = '0') and
(SPIXfer_done_int_pulse_d2 = '1') and
(cmd_addr_sent = '1') then
spi_addr_i(23 downto 0) <= spi_addr_i(23 downto 0) + '1';
end if;
end if;
end if;
end process SPI_ADDRESS_REG;
----------------------------------
end generate SPI_24_BIT_ADDRESS_REG_GEN;
----------------------------------------
SPI_32_BIT_ADDRESS_REG_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-----
SPI_ADDRESS_REG : process(EXT_SPI_CLK) is
--variable xfer : std_logic_vector(2 downto 0);
begin
-- xfer := four_byte_xfer_to_spi_clk & two_byte_xfer_to_spi_clk & one_byte_xfer_to_spi_clk;
if (EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if (Rst_to_spi = RESET_ACTIVE) then
spi_addr_i <= (others => '0');
spi_addr_int <= (others => '0');
else
if (load_cmd_to_spi_clk = '1') then
spi_addr_i <= Transmit_Addr_to_spi_clk(31 downto 0);
spi_addr_int <= Transmit_Addr_to_spi_clk(31 downto 0);
-- below is address generation for the WRAP mode
elsif (type_of_burst_to_spi_clk = '1') and
(SPIXfer_done_int_pulse_d2 = '1') and
(cmd_addr_sent = '1') then
spi_addr_int(31 downto 0) <= spi_addr_int(31 downto 0) + '1';
case size_length_cntr is
when "00" => -- 8-bit access
if(wrap_two = '1') then
spi_addr_i(31 downto 1) <= spi_addr_i(31 downto 1);
spi_addr_i(0) <= not (spi_addr_i(0));
elsif(wrap_four = '1') then -- the byte address increment will take 2 address bits
spi_addr_i(31 downto 2) <= spi_addr_i(31 downto 2);
spi_addr_i(1 downto 0) <= spi_addr_i(1 downto 0) + "01";
elsif(wrap_eight = '1') then -- the byte address increment will take 3 address bits
spi_addr_i(31 downto 3) <= spi_addr_i(31 downto 3);
spi_addr_i(2 downto 0) <= spi_addr_i(2 downto 0) + "001";
elsif(wrap_sixteen = '1') then -- the byte address increment will take 4 address bits for 16's wrap
spi_addr_i(31 downto 4) <= spi_addr_i(31 downto 4);
spi_addr_i(3 downto 0) <= spi_addr_i(3 downto 0) + "0001";
else
spi_addr_i <= spi_addr_i + "0001";
end if;
when "01" => -- 16-bit access
if(wrap_two = '1') then
spi_addr_i(31 downto 2) <= spi_addr_i(31 downto 2);
spi_addr_i(1 downto 0) <= spi_addr_i(1 downto 0) + "10";
elsif(wrap_four = '1') then
spi_addr_i(31 downto 3) <= spi_addr_i(31 downto 3);
spi_addr_i(2 downto 0) <= spi_addr_i(2 downto 0) + "010";
elsif(wrap_eight = '1') then
spi_addr_i(31 downto 4) <= spi_addr_i(31 downto 4);
spi_addr_i(3 downto 0) <= spi_addr_i(3 downto 0) + "0010";
elsif(wrap_sixteen = '1') then
spi_addr_i(31 downto 5) <= spi_addr_i(31 downto 5);
spi_addr_i(4 downto 0) <= spi_addr_i(4 downto 0) + "00010";
else
spi_addr_i <= spi_addr_i + "0010";
end if;
when "10" => -- 32-bit access
if(wrap_two = '1') then
spi_addr_i(31 downto 3) <= spi_addr_i(31 downto 3);
spi_addr_i(2 downto 0) <=spi_addr_i(2 downto 0) + "100";
elsif(wrap_four = '1') then
spi_addr_i(31 downto 4) <= spi_addr_i(31 downto 4);
spi_addr_i(3 downto 0) <=spi_addr_i(3 downto 0) + "0100";
elsif(wrap_eight = '1') then
spi_addr_i(31 downto 5) <= spi_addr_i(31 downto 5);
spi_addr_i(4 downto 0) <=spi_addr_i(4 downto 0) + "00100";
elsif(wrap_sixteen = '1') then
spi_addr_i(31 downto 6) <= spi_addr_i(31 downto 6);
spi_addr_i(5 downto 0) <=spi_addr_i(5 downto 0) + "000100";
else
spi_addr_i <= spi_addr_i + "0100";
end if;
-- coverage off
when others =>
spi_addr_i <= spi_addr_i;
-- coverage on
end case;
-- below is address generation for the INCR mode
elsif (type_of_burst_to_spi_clk = '0') and
(SPIXfer_done_int_pulse_d2 = '1') and
(cmd_addr_sent = '1') then
spi_addr_i(31 downto 0) <= spi_addr_i(31 downto 0) + '1';
end if;
end if;
end if;
end process SPI_ADDRESS_REG;
end generate SPI_32_BIT_ADDRESS_REG_GEN;
----------------------------------------
-- SPI_WRAP_ADDR_REG: this is separate process used for WRAP address generation
SPI_24_WRAP_ADDR_REG_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
SPI_WRAP_ADDR_REG : process(EXT_SPI_CLK) is
--variable xfer : std_logic_vector(2 downto 0);
begin
-- xfer := four_byte_xfer_to_spi_clk & two_byte_xfer_to_spi_clk & one_byte_xfer_to_spi_clk;
if (EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if (Rst_to_spi = RESET_ACTIVE) then
spi_addr_wrap <= (others => '0');
else
if (load_cmd_to_spi_clk = '1') then
spi_addr_wrap <= Transmit_Addr_to_spi_clk(23 downto 0);
elsif(wrap_ack_1 = '1') then
spi_addr_wrap <= spi_addr_wrap_1;
-- below is address generation for the WRAP mode
elsif (type_of_burst_to_spi_clk = '1') and
(store_date_in_drr_fifo = '1') and
(cmd_addr_sent = '1') then
case size_length_cntr_fixed is
when "00" => -- 8-bit access
if(wrap_two = '1') then
spi_addr_wrap(23 downto 1) <= spi_addr_wrap(23 downto 1);
spi_addr_wrap(0) <= not (spi_addr_wrap(0));
elsif(wrap_four = '1') then -- the byte address increment will take 2 address bits
spi_addr_wrap(23 downto 2) <= spi_addr_wrap(23 downto 2);
spi_addr_wrap(1 downto 0) <= spi_addr_wrap(1 downto 0) + "01";
elsif(wrap_eight = '1') then -- the byte address increment will take 3 address bits
spi_addr_wrap(23 downto 3) <= spi_addr_wrap(23 downto 3);
spi_addr_wrap(2 downto 0) <= spi_addr_wrap(2 downto 0) + "001";
elsif(wrap_sixteen = '1') then -- the byte address increment will take 4 address bits for 16's wrap
spi_addr_wrap(23 downto 4) <= spi_addr_wrap(23 downto 4);
spi_addr_wrap(3 downto 0) <= spi_addr_wrap(3 downto 0) + "0001";
else
spi_addr_wrap <= spi_addr_wrap + "0001";
end if;
when "01" => -- 16-bit access
if(wrap_two = '1') then
spi_addr_wrap(23 downto 2) <= spi_addr_wrap(23 downto 2);
spi_addr_wrap(1 downto 0) <= spi_addr_wrap(1 downto 0) + "10";
elsif(wrap_four = '1') then
spi_addr_wrap(23 downto 3) <= spi_addr_wrap(23 downto 3);
spi_addr_wrap(2 downto 0) <= spi_addr_wrap(2 downto 0) + "010";
elsif(wrap_eight = '1') then
spi_addr_wrap(23 downto 4) <= spi_addr_wrap(23 downto 4);
spi_addr_wrap(3 downto 0) <= spi_addr_wrap(3 downto 0) + "0010";
elsif(wrap_sixteen = '1') then
spi_addr_wrap(23 downto 5) <= spi_addr_wrap(23 downto 5);
spi_addr_wrap(4 downto 0) <= spi_addr_wrap(4 downto 0) + "00010";
else
spi_addr_wrap <= spi_addr_wrap + "0010";
end if;
when "10" => -- 32-bit access
if(wrap_two = '1') then
spi_addr_wrap(23 downto 3) <= spi_addr_wrap(23 downto 3);
spi_addr_wrap(2 downto 0) <=spi_addr_wrap(2 downto 0) + "100";
elsif(wrap_four = '1') then
spi_addr_wrap(23 downto 4) <= spi_addr_wrap(23 downto 4);
spi_addr_wrap(3 downto 0) <=spi_addr_wrap(3 downto 0) + "0100";
elsif(wrap_eight = '1') then
spi_addr_wrap(23 downto 5) <= spi_addr_wrap(23 downto 5);
spi_addr_wrap(4 downto 0) <=spi_addr_wrap(4 downto 0) + "00100";
elsif(wrap_sixteen = '1') then
spi_addr_wrap(23 downto 6) <= spi_addr_wrap(23 downto 6);
spi_addr_wrap(5 downto 0) <=spi_addr_wrap(5 downto 0) + "000100";
else
spi_addr_wrap <= spi_addr_wrap + "0100";
end if;
-- coverage off
when others =>
spi_addr_wrap <= spi_addr_wrap;
-- coverage on
end case;
end if;
end if;
end if;
end process SPI_WRAP_ADDR_REG;
end generate SPI_24_WRAP_ADDR_REG_GEN;
--------------------------------------
SPI_32_WRAP_ADDR_REG_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
SPI_WRAP_ADDR_REG : process(EXT_SPI_CLK) is
--variable xfer : std_logic_vector(2 downto 0);
begin
-- xfer := four_byte_xfer_to_spi_clk & two_byte_xfer_to_spi_clk & one_byte_xfer_to_spi_clk;
if (EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if (Rst_to_spi = RESET_ACTIVE) then
spi_addr_wrap <= (others => '0');
else
if (load_cmd_to_spi_clk = '1') then
spi_addr_wrap <= Transmit_Addr_to_spi_clk(31 downto 0);
elsif(wrap_ack_1 = '1') then
spi_addr_wrap <= spi_addr_wrap_1;
-- below is address generation for the WRAP mode
elsif (type_of_burst_to_spi_clk = '1') and
(store_date_in_drr_fifo = '1') and
(cmd_addr_sent = '1') then
case size_length_cntr_fixed is
when "00" => -- 8-bit access
if(wrap_two = '1') then
spi_addr_wrap(31 downto 1) <= spi_addr_wrap(31 downto 1);
spi_addr_wrap(0) <= not (spi_addr_wrap(0));
elsif(wrap_four = '1') then -- the byte address increment will take 2 address bits
spi_addr_wrap(31 downto 2) <= spi_addr_wrap(31 downto 2);
spi_addr_wrap(1 downto 0) <= spi_addr_wrap(1 downto 0) + "01";
elsif(wrap_eight = '1') then -- the byte address increment will take 3 address bits
spi_addr_wrap(31 downto 3) <= spi_addr_wrap(31 downto 3);
spi_addr_wrap(2 downto 0) <= spi_addr_wrap(2 downto 0) + "001";
elsif(wrap_sixteen = '1') then -- the byte address increment will take 4 address bits for 16's wrap
spi_addr_wrap(31 downto 4) <= spi_addr_wrap(31 downto 4);
spi_addr_wrap(3 downto 0) <= spi_addr_wrap(3 downto 0) + "0001";
else
spi_addr_wrap <= spi_addr_wrap + "0001";
end if;
when "01" => -- 16-bit access
if(wrap_two = '1') then
spi_addr_wrap(31 downto 2) <= spi_addr_wrap(31 downto 2);
spi_addr_wrap(1 downto 0) <= spi_addr_wrap(1 downto 0) + "10";
elsif(wrap_four = '1') then
spi_addr_wrap(31 downto 3) <= spi_addr_wrap(31 downto 3);
spi_addr_wrap(2 downto 0) <= spi_addr_wrap(2 downto 0) + "010";
elsif(wrap_eight = '1') then
spi_addr_wrap(31 downto 4) <= spi_addr_wrap(31 downto 4);
spi_addr_wrap(3 downto 0) <= spi_addr_wrap(3 downto 0) + "0010";
elsif(wrap_sixteen = '1') then
spi_addr_wrap(31 downto 5) <= spi_addr_wrap(31 downto 5);
spi_addr_wrap(4 downto 0) <= spi_addr_wrap(4 downto 0) + "00010";
else
spi_addr_wrap <= spi_addr_wrap + "0010";
end if;
when "10" => -- 32-bit access
if(wrap_two = '1') then
spi_addr_wrap(31 downto 3) <= spi_addr_wrap(31 downto 3);
spi_addr_wrap(2 downto 0) <=spi_addr_wrap(2 downto 0) + "100";
elsif(wrap_four = '1') then
spi_addr_wrap(31 downto 4) <= spi_addr_wrap(31 downto 4);
spi_addr_wrap(3 downto 0) <=spi_addr_wrap(3 downto 0) + "0100";
elsif(wrap_eight = '1') then
spi_addr_wrap(31 downto 5) <= spi_addr_wrap(31 downto 5);
spi_addr_wrap(4 downto 0) <=spi_addr_wrap(4 downto 0) + "00100";
elsif(wrap_sixteen = '1') then
spi_addr_wrap(31 downto 6) <= spi_addr_wrap(31 downto 6);
spi_addr_wrap(5 downto 0) <=spi_addr_wrap(5 downto 0) + "000100";
else
spi_addr_wrap <= spi_addr_wrap + "0100";
end if;
-- coverage off
when others =>
spi_addr_wrap <= spi_addr_wrap;
-- coverage on
end case;
end if;
end if;
end if;
end process SPI_WRAP_ADDR_REG;
----------------------------------
end generate SPI_32_WRAP_ADDR_REG_GEN;
--------------------------------------
-------------------------------------------------------------------------------
-- SPI_WRAP_ADDR_REG: this is separate process used for WRAP address generation
LOAD_SPI_WRAP_ADDR_REG : process(EXT_SPI_CLK) is
begin
-----
if (EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if (Rst_to_spi = RESET_ACTIVE) then
spi_addr_wrap_1 <= (others => '0');
else
if (wrap_around = '1') then
-- below is address generation for the WRAP mode
case size_length_cntr_fixed is
when "00" => -- 8-bit access
if(wrap_two = '1') then
spi_addr_wrap_1 <= spi_addr_wrap + '1';
elsif(wrap_four = '1') then -- the byte address increment will take 2 address bits
spi_addr_wrap_1 <= spi_addr_wrap + "01";
elsif(wrap_eight = '1') then -- the byte address increment will take 3 address bits
spi_addr_wrap_1 <= spi_addr_wrap + "001";
elsif(wrap_sixteen = '1') then -- the byte address increment will take 4 address bits for 16's wrap
spi_addr_wrap_1 <= spi_addr_wrap + "0001";
else
spi_addr_wrap_1 <= spi_addr_wrap + "0001";
end if;
when "01" => -- 16-bit access
if(wrap_two = '1') then
spi_addr_wrap_1 <= spi_addr_wrap + "10";
elsif(wrap_four = '1') then
spi_addr_wrap_1 <= spi_addr_wrap + "010";
elsif(wrap_eight = '1') then
spi_addr_wrap_1 <= spi_addr_wrap + "0010";
elsif(wrap_sixteen = '1') then
spi_addr_wrap_1 <= spi_addr_wrap + "00010";
else
spi_addr_wrap_1 <= spi_addr_wrap + "0010";
end if;
when "10" => -- 32-bit access
if(wrap_two = '1') then
spi_addr_wrap_1 <=spi_addr_wrap + "100";
elsif(wrap_four = '1') then
spi_addr_wrap_1 <=spi_addr_wrap + "0100";
elsif(wrap_eight = '1') then
spi_addr_wrap_1 <=spi_addr_wrap + "00100";
elsif(wrap_sixteen = '1') then
spi_addr_wrap_1 <=spi_addr_wrap + "000100";
else
spi_addr_wrap_1 <=spi_addr_wrap + "0100";
end if;
-- coverage off
when others =>
spi_addr_wrap_1 <= spi_addr_wrap;
-- coverage on
end case;
end if;
end if;
end if;
end process LOAD_SPI_WRAP_ADDR_REG;
-------------------------------------------------------------------------------
-- WRAP_AROUND_GEN_P : WRAP boundary detection logic
WRAP_AROUND_GEN_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if( (Rst_to_spi = '1')
or(rst_wrap_around = '1')
) then
wrap_around <= '0';
elsif(type_of_burst_to_spi_clk = '1')then
case size_length_cntr_fixed is
when "00" => -- byte transfer
if(wrap_two = '1') and
(spi_addr_wrap(1) = '1') and
(store_date_in_drr_fifo = '1')then -- then
wrap_around <= --spi_addr_wrap(1) and
not SR_5_Tx_Empty;
elsif(wrap_four = '1') and
(spi_addr_wrap(1 downto 0) = "11") and
(store_date_in_drr_fifo = '1')then -- then -- the byte address increment will take 2 address bits
wrap_around <= --and_reduce(spi_addr_wrap(1 downto 0)) and
not SR_5_Tx_Empty;
elsif(wrap_eight = '1') and
(spi_addr_wrap(2 downto 0) = "111") and
(store_date_in_drr_fifo = '1')then -- then -- the byte address increment will take 3 address bits
wrap_around <= --and_reduce(spi_addr_wrap(2 downto 0)) and
not SR_5_Tx_Empty;
elsif(wrap_sixteen = '1') and
(spi_addr_wrap(3 downto 0) = "1111") and
(store_date_in_drr_fifo = '1')then -- the byte address increment will take 4 address bits for 16's wrap
wrap_around <= --and_reduce(spi_addr_wrap(3 downto 0)) and
not SR_5_Tx_Empty;
else
wrap_around <= '0';
end if;
when "01" => -- 16-bit access
if(wrap_two = '1') then -- and (spi_addr_wrap(1 downto 0) = "10") and (store_date_in_drr_fifo = '1')then
wrap_around <= not SR_5_Tx_Empty and
store_date_in_drr_fifo and
wrp_addr_len_2_siz_16;
elsif(wrap_four = '1') then -- and (spi_addr_wrap(2 downto 0) = "110") and (store_date_in_drr_fifo = '1')then
wrap_around <= not SR_5_Tx_Empty and
store_date_in_drr_fifo and
wrp_addr_len_4_siz_16;
elsif(wrap_eight = '1') then -- and (spi_addr_wrap(3 downto 0) = "1110") and (store_date_in_drr_fifo = '1')then
wrap_around <= not SR_5_Tx_Empty and
store_date_in_drr_fifo and
wrp_addr_len_8_siz_16;
elsif(wrap_sixteen = '1') then -- and (spi_addr_wrap(4 downto 0) = "11110") and (store_date_in_drr_fifo = '1') then
wrap_around <= not SR_5_Tx_Empty and
store_date_in_drr_fifo and
wrp_addr_len_16_siz_16;
else
wrap_around <= '0';
end if;
when "10" => -- 32-bit access
if(wrap_two = '1') then -- and (spi_addr_wrap(2 downto 0) = "100") and (store_date_in_drr_fifo = '1') then
wrap_around <= not SR_5_Tx_Empty and
store_date_in_drr_fifo and
wrp_addr_len_2_siz_32;
elsif(wrap_four = '1') then -- and (spi_addr_wrap(3 downto 0) = "1100") and (store_date_in_drr_fifo = '1') then
wrap_around <= not SR_5_Tx_Empty and
store_date_in_drr_fifo and
wrp_addr_len_4_siz_32;
elsif(wrap_eight = '1') then -- and (spi_addr_wrap(4 downto 0) = "11100") and (store_date_in_drr_fifo = '1') then
wrap_around <= not SR_5_Tx_Empty and
store_date_in_drr_fifo and
wrp_addr_len_8_siz_32;
elsif(wrap_sixteen = '1') then --and (spi_addr_wrap(5 downto 0) = "111100") and (store_date_in_drr_fifo = '1') then
wrap_around <= not SR_5_Tx_Empty and
store_date_in_drr_fifo and
wrp_addr_len_16_siz_32;
else
wrap_around <= '0';
end if;
-- coverage off
when others => wrap_around <= wrap_around;
-- coverage on
end case;
end if;
end if;
end process WRAP_AROUND_GEN_P;
-------------------------------------------------------------------------------
load_wrap_addr <= wrap_around;
wrp_addr_len_16_siz_32 <= '1' when (spi_addr_wrap(5 downto 0) = "111100") else '0';
wrp_addr_len_8_siz_32 <= '1' when (spi_addr_wrap(4 downto 0) = "11100") else '0';
wrp_addr_len_4_siz_32 <= '1' when (spi_addr_wrap(3 downto 0) = "1100") else '0';
wrp_addr_len_2_siz_32 <= '1' when (spi_addr_wrap(2 downto 0) = "100") else '0';
-----------------------------------------------------------------------------------
wrp_addr_len_16_siz_16 <= '1' when (spi_addr_wrap(4 downto 0) = "11110") else '0';
wrp_addr_len_8_siz_16 <= '1' when (spi_addr_wrap(3 downto 0) = "1110") else '0';
wrp_addr_len_4_siz_16 <= '1' when (spi_addr_wrap(2 downto 0) = "110") else '0';
wrp_addr_len_2_siz_16 <= '1' when (spi_addr_wrap(1 downto 0) = "10") else '0';
-----------------------------------------------------------------------------------
-- LEN_CNTR_P: This is data length counter. this counter will start decrementing
-- only when the first 4 bytes are transferred from SPI.
LEN_CNTR_24_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-----
LEN_CNTR_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
length_cntr <= (others => '0');
elsif(load_wr_hpm='1') then
length_cntr <= "00000011";
elsif(load_cmd_to_spi_clk = '1')then
length_cntr <= dtr_length_to_spi_clk;
elsif((SPIXfer_done_int = '1') and
(((size_length_cntr = "00") and
(cmd_addr_sent = '1')
)or
(hpm_under_process_d1 = '1'))
)then
length_cntr <= length_cntr - "00000001";
end if;
end if;
end process LEN_CNTR_P;
-----------------------
end generate LEN_CNTR_24_BIT_GEN;
---------------------------------
LEN_CNTR_32_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-----
LEN_CNTR_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
length_cntr <= (others => '0');
elsif(load_wr_hpm='1') then
length_cntr <= "00000000";
elsif(load_cmd_to_spi_clk = '1')then
length_cntr <= dtr_length_to_spi_clk;
elsif((SPIXfer_done_int = '1') and
(((size_length_cntr = "00") and
(cmd_addr_sent = '1')
)or
(hpm_under_process_d1 = '1') or (wr_en_under_process_d1 = '1'))
)then
length_cntr <= length_cntr - "00000001";
end if;
end if;
end process LEN_CNTR_P;
-----------------------
end generate LEN_CNTR_32_BIT_GEN;
---------------------------------
-------------------------------------------------------------------------------
SR_5_TX_EMPTY_32_BIT_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
SR_5_Tx_Empty_int<= (not(or_reduce(length_cntr)) and
store_date_in_drr_fifo and
cmd_addr_sent)
or
(-- (hpm_under_process_d1 or wr_en_under_process_d1) and
(hpm_under_process or wr_en_under_process) and
not(or_reduce(length_cntr)) and
SPIXfer_done_int_pulse);
-- LEN_CNTR_P: This is data length counter. this counter will start decrementing
-- only when the first 4 bytesfor 24 bit addressing and 5 bytes for 32 bit addressing mode are transferred from SPI.
SR_5_TX_EMPTY_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
SR_5_Tx_Empty <= '1';
elsif(load_cmd_to_spi_clk = '1') or (load_wr_hpm = '1') or (load_wr_en = '1') then
SR_5_Tx_Empty <= '0';
elsif(SR_5_Tx_Empty_int = '1')then
SR_5_Tx_Empty <= '1';
end if;
end if;
end process SR_5_TX_EMPTY_P;
end generate SR_5_TX_EMPTY_32_BIT_ADDR_GEN;
-------------------------------------------------------------------------------
SR_5_TX_EMPTY_24_BIT_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
SR_5_Tx_Empty_int<= (not(or_reduce(length_cntr)) and
store_date_in_drr_fifo and
cmd_addr_sent)
or
(-- (hpm_under_process_d1 or wr_en_under_process_d1) and
(hpm_under_process
--or wr_en_under_process
)
and
not(
or_reduce(length_cntr))
and
SPIXfer_done_int_pulse
);
-- LEN_CNTR_P: This is data length counter. this counter will start decrementing
-- only when the first 4 bytesfor 24 bit addressing and 5 bytes for 32 bit addressing mode are transferred from SPI.
SR_5_TX_EMPTY_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
SR_5_Tx_Empty <= '1';
elsif(load_cmd_to_spi_clk = '1') or (load_wr_hpm = '1')
--or (load_wr_en = '1')
then
SR_5_Tx_Empty <= '0';
elsif(SR_5_Tx_Empty_int = '1')then
SR_5_Tx_Empty <= '1';
end if;
end if;
end process SR_5_TX_EMPTY_P;
end generate SR_5_TX_EMPTY_24_BIT_ADDR_GEN;
-------------------------------------------
DELAY_FIFO_EMPTY_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
SR_5_Tx_Empty_d1 <= '1';
SR_5_Tx_Empty_d2 <= '1';
else
SR_5_Tx_Empty_d1 <= SR_5_Tx_Empty;
SR_5_Tx_Empty_d2 <= SR_5_Tx_Empty_d1;
end if;
end if;
end process DELAY_FIFO_EMPTY_P;
-------------------------------------------------------------------------------
last_bt_one_data <= not(or_reduce(length_cntr(7 downto 1))) and length_cntr(0);
-------------------------------------------------------------------------------
SIZE_CNTR_LD_SPI_CLK_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
size_length_cntr_fixed <= (others => '0');
size_length_cntr <= (others => '0');
elsif(
(pr_state_idle = '1') or ((SPIXfer_done_int = '1') and
(size_length_cntr = "00"))
)then
--if(one_byte_xfer_to_spi_clk = '1' )then
-- size_length_cntr_fixed <= "00";
-- size_length_cntr <= "00"; -- 1 byte
--els
if(two_byte_xfer_to_spi_clk = '1')then
size_length_cntr_fixed <= "01";
size_length_cntr <= "01"; -- half word
elsif(four_byte_xfer_to_spi_clk = '1') then
size_length_cntr_fixed <= "10";
size_length_cntr <= "11"; -- word
else
size_length_cntr_fixed <= "00";
size_length_cntr <= "00"; -- other and one_byte_xfer_to_spi_clk = '1' is merged here
end if;
elsif(SPIXfer_done_int = '1') and
(one_byte_xfer_to_spi_clk = '0')and
(cmd_addr_sent = '1') then -- (size_length_cntr /= "00") then
size_length_cntr <= size_length_cntr - "01";
end if;
end if;
end process SIZE_CNTR_LD_SPI_CLK_P;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
store_date_in_drr_fifo <= not(or_reduce(size_length_cntr)) and
SPIXfer_done_int and
cmd_addr_sent;
-------------------------------------------------------------------------------
STORE_STROBE_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
store_date_in_drr_fifo_d1 <= '0';
store_date_in_drr_fifo_d2 <= '0';
store_date_in_drr_fifo_d3 <= '0';
else
store_date_in_drr_fifo_d1 <= store_date_in_drr_fifo;
store_date_in_drr_fifo_d2 <= store_date_in_drr_fifo_d1;
store_date_in_drr_fifo_d3 <= store_date_in_drr_fifo_d2;
end if;
end if;
end process STORE_STROBE_SPI_CLK_P;
-------------------------------------------------------------------------------
MD_12_WR_EN_TO_FIFO_GEN: if C_SPI_MODE = 1 or C_SPI_MODE = 2 generate
begin
-----
--------------------------------------------------------------------
WB_FIFO_WR_EN_GEN: if C_SPI_MEMORY = 1 generate
begin
-----
store_date_in_drr_fifo_en <= store_date_in_drr_fifo_d3;
end generate WB_FIFO_WR_EN_GEN;
--------------------------------------------------------------------
NM_FIFO_WR_EN_GEN: if C_SPI_MEMORY = 2 generate
begin
-----
STORE_DATA_24_BIT_ADDRESS_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
store_date_in_drr_fifo_en <= store_date_in_drr_fifo_d3;
end generate STORE_DATA_24_BIT_ADDRESS_GEN;
-------------------------------------------
STORE_DATA_32_BIT_ADDRESS_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
store_date_in_drr_fifo_en <= store_date_in_drr_fifo_d3;
end generate STORE_DATA_32_BIT_ADDRESS_GEN;
-------------------------------------------
end generate NM_FIFO_WR_EN_GEN;
--------------------------------------------------------------------
SP_FIFO_WR_EN_GEN: if C_SPI_MEMORY = 3 generate
begin
-----
STORE_DATA_24_BIT_ADDRESS_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
store_date_in_drr_fifo_en <= store_date_in_drr_fifo_d3;
end generate STORE_DATA_24_BIT_ADDRESS_GEN;
-------------------------------------------
STORE_DATA_32_BIT_ADDRESS_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
store_date_in_drr_fifo_en <= store_date_in_drr_fifo_d3;
end generate STORE_DATA_32_BIT_ADDRESS_GEN;
-------------------------------------------
end generate SP_FIFO_WR_EN_GEN;
--------------------------------------------------------------------
end generate MD_12_WR_EN_TO_FIFO_GEN;
MD_0_WR_EN_TO_FIFO_GEN: if C_SPI_MODE = 0 generate
begin
-----
WB_FIFO_WR_EN_GEN: if C_SPI_MEMORY = 1 generate
begin
-----
store_date_in_drr_fifo_en <= store_date_in_drr_fifo;
end generate WB_FIFO_WR_EN_GEN;
NM_FIFO_WR_EN_GEN: if C_SPI_MEMORY = 2 generate
begin
-----
store_date_in_drr_fifo_en <= store_date_in_drr_fifo;
end generate NM_FIFO_WR_EN_GEN;
SP_FIFO_WR_EN_GEN: if C_SPI_MEMORY = 3 generate
begin
-----
store_date_in_drr_fifo_en <= store_date_in_drr_fifo;
end generate SP_FIFO_WR_EN_GEN;
end generate MD_0_WR_EN_TO_FIFO_GEN;
-------------------------------------------------------------------------------
SHIFT_TX_REG_24_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
SHIFT_TX_REG_SPI_CLK_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1')then
Tx_Data_d1 <= (others => '0');
elsif(load_wr_hpm = '1') then
Tx_Data_d1(31 downto 24) <= WB_wr_hpm_CMD;
Tx_Data_d1(23 downto 0) <= (others => '0');
elsif(load_axi_data_to_spi_clk = '1')then
Tx_Data_d1 <= SPI_cmd & Transmit_Addr_to_spi_clk; -- & SPI_cmd;-- (31 downto 8);
elsif(wrap_around = '1') then
Tx_Data_d1 <= SPI_cmd & spi_addr_wrap;--spi_addr_i & SPI_cmd;
elsif(SPIXfer_done_int = '1')then
Tx_Data_d1 <= --"11111111" & -- Tx_Data_d1(7 downto 0) &
-- --Tx_Data_d1(31 downto 8);
-- Tx_Data_d1(31 downto 8);
Tx_Data_d1(23 downto 0) & "11111111";
end if;
end if;
end process SHIFT_TX_REG_SPI_CLK_P;
Transmit_Data <= Tx_Data_d1(31 downto 24);
end generate SHIFT_TX_REG_24_BIT_GEN;
-------------------------------------------------------
SHIFT_TX_REG_32_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
SHIFT_TX_REG_SPI_CLK_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1')then
Tx_Data_d1 <= (others => '0');
--last_7_addr_bits <= (others => '0');
elsif(load_wr_en = '1') then
Tx_Data_d1(31 downto 24) <= "00000110"; ---nm_wr_en_CMD;
Tx_Data_d1(23 downto 0) <= (others => '0');
elsif(load_wr_hpm = '1')then
Tx_Data_d1(31 downto 24) <= "10110111"; ---nm_4byte_addr_en_CMD;
Tx_Data_d1(23 downto 0) <= (others => '0');
elsif(load_axi_data_to_spi_clk = '1')then
Tx_Data_d1 <= SPI_cmd & Transmit_Addr_to_spi_clk(31 downto 8); -- & SPI_cmd;-- (31 downto 8);
last_7_addr_bits <= Transmit_Addr_to_spi_clk(7 downto 0);
-- internal_count <= (others => '0');
elsif(wrap_around = '1') then
Tx_Data_d1 <= SPI_cmd & spi_addr_wrap(31 downto 8);--spi_addr_i & SPI_cmd;
last_7_addr_bits <= spi_addr_wrap(7 downto 0);
elsif(SPIXfer_done_int = '1') then -- and internal_count < "0101")then
Tx_Data_d1 <= --"11111111" & -- Tx_Data_d1(7 downto 0) &
-- --Tx_Data_d1(31 downto 8);
-- Tx_Data_d1(31 downto 8);
Tx_Data_d1(23 downto 0) & -- Transmit_Addr_to_spi_clk(7 downto 0);
-- spi_addr_wrap(7 downto 0);
last_7_addr_bits(7 downto 0);
-- internal_count <= internal_count + "0001";
--elsif(SPIXfer_done_int = '1' and internal_count = "0101") then
-- Tx_Data_d1 <= (others => '1');
end if;
end if;
end process SHIFT_TX_REG_SPI_CLK_P;
Transmit_Data <= Tx_Data_d1(31 downto 24);
-- STORE_INFO_P:process(EXT_SPI_CLK)is
-- -----
-- begin
-- -----
-- if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
-- if(Rst_to_spi = '1')then
-- data_loaded <= '0';
-- cmd_sent <= '0';
-- elsif(load_axi_data_to_spi_clk = '1' or wrap_around = '1) then
-- data_loaded <= '1';
-- elsif(data_loaded = '1' and SPIXfer_done_int = '1') then
-- cmd_sent <= '1';
-- end if;
-- end if;
-- end process STORE_INFO_P;
end generate SHIFT_TX_REG_32_BIT_GEN;
-------------------------------------------------------
-- Transmit_Data <= Tx_Data_d1(31 downto 24);
-------------------------------------------------------
-------------------------------------------------------------------------------
STD_MODE_CONTROL_GEN: if C_SPI_MODE = 0 generate
-----
begin
-----
WB_MEM_STD_MD_GEN: if C_SPI_MODE = 0 and C_SPI_MEMORY = 1 generate
-----------
signal cmd_addr_cntr : std_logic_vector(2 downto 0);
signal hw_wd_cntr : std_logic_vector(1 downto 0);
-----
begin
-----
wb_hpm_done <= '1';
load_wr_en <= '0';-- 4/12/2013 applicable only for Numonyx memories
---- Std mode command = 0x0B - Fast Read
SPI_cmd <= "00001011"; -- FAST_READ
-- |<---- cmd error
-- WB 000 000 0100 0<-cmd error
-- NM 000 000 0100 0
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
---------------------------
-- CMD_ADDR_CNTR_P: in each SPI transaction, the first 5 transactions are of
-- CMD, A0, A1, A2 and dummy. Total 5 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 5 bytes are transferred.
-- below counter is for that purpose only. This is applicable only for Winbond memory.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or (wrap_around = '1') then
cmd_addr_cntr <= "000";
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1')then
cmd_addr_cntr <= "000";
cmd_addr_sent <= wrap_around;
elsif(SPIXfer_done_int = '1')then
if(cmd_addr_cntr = "101")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
----------------------------
-- TWO_BIT_CNTR_P: This is specifically used for HW data storage
TWO_BIT_CNTR_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') or (wrap_around = '1') then
hw_wd_cntr <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1')then
hw_wd_cntr <= hw_wd_cntr + "01";
end if;
end if;
end process TWO_BIT_CNTR_P;
----------------------------------------------
STORE_RX_DATA_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') then
Data_To_Rx_FIFO_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1') then
if(one_byte_xfer_to_spi_clk = '1') then
case spi_addr_i(1 downto 0) is
when "00" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 8) &
receive_Data_int;
when "01" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 16)&
receive_Data_int &
Data_To_Rx_FIFO_int(7 downto 0);
when "10" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 24)&
receive_Data_int &
Data_To_Rx_FIFO_int(15 downto 0);
when "11" =>
Data_To_Rx_FIFO_int <= receive_Data_int &
Data_To_Rx_FIFO_int(23 downto 0);
when others => null;
end case;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '0') then -- adjustment for half word
if(spi_addr_i(1) = '0') then
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);-- & receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= receive_Data_int & Data_To_Rx_FIFO_int(15 downto 8);-- & receive_Data_int;
else
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);-- & receive_Data_int;
Data_To_Rx_FIFO_int(31 downto 16)<= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 24);-- & receive_Data_int;
end if;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '1') then -- adjustment for half word
if(hw_wd_cntr = "00") then -- fill in D0
Data_To_Rx_FIFO_int(31 downto 8) <= Data_To_Rx_FIFO_int(31 downto 8);
Data_To_Rx_FIFO_int(7 downto 0) <= receive_Data_int;
elsif(hw_wd_cntr = "01")then -- fill in D1
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);
Data_To_Rx_FIFO_int(15 downto 8) <= receive_Data_int;
Data_To_Rx_FIFO_int(7 downto 0) <= Data_To_Rx_FIFO_int(7 downto 0);
elsif(hw_wd_cntr = "10")then -- fill in D2
Data_To_Rx_FIFO_int(31 downto 24) <= Data_To_Rx_FIFO_int(31 downto 24);
Data_To_Rx_FIFO_int(23 downto 16) <= receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);
else
Data_To_Rx_FIFO_int(31 downto 24) <= receive_Data_int;
Data_To_Rx_FIFO_int(23 downto 0) <= Data_To_Rx_FIFO_int(23 downto 0);
end if;
else -- adjustment for complete word
--Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(23 downto 0) & receive_Data_int;
Data_To_Rx_FIFO_int <= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 8);
end if;
end if;
end if;
end process STORE_RX_DATA_SPI_CLK_P;
----------------------------
Data_To_Rx_FIFO <= Data_To_Rx_FIFO_int;
---------------------------------------
RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
receive_Data_int <= (others => '0');
elsif(SPIXfer_done_int_pulse = '1') then
receive_Data_int <= rx_shft_reg_mode_0011;
elsif(SPIXfer_done_int_pulse_d1 = '1') and (cmd_addr_sent = '1')then
receive_Data_int <= receive_Data_int
((C_NUM_TRANSFER_BITS-2) downto 0) &
IO1_I ; --MISO_I;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS;
-----------------------------------------
end generate WB_MEM_STD_MD_GEN;
------------------------
--------------------------------------------------------------------------
NM_MEM_STD_MD_GEN: if C_SPI_MODE = 0 and C_SPI_MEMORY = 2 generate
signal cmd_addr_cntr : std_logic_vector(2 downto 0);
signal hw_wd_cntr : std_logic_vector(1 downto 0);
-----
begin
-----
---- Std mode command = 0x0B - Fast Read
STD_SPI_CMD_NM_24_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
SPI_cmd <= "00001011";-- FAST_READ - 0x0Bh
-- |<---- cmd error
-- NM 000 000 0100 0
four_byte_en_done <= '1';
wb_hpm_done <= '1';
DRIVE_CONTROL_SIG_P: process(EXT_SPI_CLK, wb_hpm_done, wr_en_done_reg ) is -- wb_hpm_done, wr_en_done_reg) is
variable temp: std_logic_vector(1 downto 0);
begin
temp := wb_hpm_done & wr_en_done_reg;
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
--case wb_hpm_done is
-- -- when "00"|"01" => -- write enable is under process
-- when '0' => -- write enable and/or Enable 4 byte addressing is under process
-- Data_Dir <= '0';
-- Data_Mode_1 <= '0';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '0';
-- --------------------
-- Quad_Phase <= '0';-- permanent '0'
-- --------------------
-- Addr_Mode_1 <= '0';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '0';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
-- -- when "01" => -- Enable 4 byte addressing is under process
-- -- Data_Dir <= '0';
-- -- Data_Mode_1 <= '0';
-- -- Data_Mode_0 <= '0';
-- -- Data_Phase <= '0';
-- -- --------------------
-- -- Quad_Phase <= '0';-- permanent '0'
-- -- --------------------
-- -- Addr_Mode_1 <= '0';
-- -- Addr_Mode_0 <= '0';
-- -- Addr_Bit <= '0';
-- -- Addr_Phase <= '0';
-- -- --------------------
-- -- CMD_Mode_1 <= '0';
-- -- CMD_Mode_0 <= '0';
-- -- when "10" => -- write enable is done and enable 4 byte addressing is also done
-- when '1' => -- write enable and enable 4 byte addressing is also done
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- -- coverage off
-- when others =>
-- Data_Dir <= '0';
-- Data_Mode_1 <= '0';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '0';
-- --------------------
-- Quad_Phase <= '0';-- permanent '0'
-- --------------------
-- Addr_Mode_1 <= '0';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '0';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
-- -- coverage on
--end case;
end if;
end process DRIVE_CONTROL_SIG_P;
---------------------------------------------------------------------
end generate STD_SPI_CMD_NM_24_BIT_GEN;
STD_SPI_CMD_NM_32_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
SPI_cmd <= "00001100";-- FAST_READ_4Byte - 0x0Ch
-- |<---- cmd error
-- NM 000 000 0100 0
--end generate STD_SPI_CMD_NM_32_BIT_GEN;
--NM_EN_32_ADDR_MD_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
--begin
-----
nm_wr_en_CMD <= "00000110"; -- 0x06 h Write Enable
nm_4byte_addr_en_CMD <= "10110111"; -- 0xB7 h Enable 4 Byte Addressing Mode
----------------------------------------------------
NM_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
nm_wr_en_cntrl_ps <= NM_WR_EN_IDLE;
wr_en_under_process_d1 <= '0';
wr_en_done_reg <= '0';
else
nm_wr_en_cntrl_ps <= nm_wr_en_cntrl_ns;
wr_en_under_process_d1 <= wr_en_under_process;
wr_en_done_reg <= wr_en_done;
end if;
end if;
end process NM_PS_TO_NS_PROCESS;
----------------------------------
--
NM_WR_EN_CNTRL_PROCESS: process(
nm_wr_en_cntrl_ps ,
--SPIXfer_done_int_pulse,
--SPIXfer_done_int ,
Rst_to_spi ,
SR_5_Tx_Empty ,
wr_en_done_reg
) is
-----
begin
-----
--load_wr_en_cmd <= '0';
--load_wr_sr_cmd <= '0';
--load_wr_sr_d0 <= '0';
--load_wr_sr_d1 <= '0';
load_wr_en <= '0';
wr_en_done <= '0';
wr_en_under_process <= '0';
case nm_wr_en_cntrl_ps is
when NM_WR_EN_IDLE => --load_wr_en_cmd <= '1';
load_wr_en <= '1';
wr_en_under_process <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN;
when NM_WR_EN => if (SR_5_Tx_Empty = '1')then
--wr_en_done <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN_DONE;
else
--wr_en_under_process <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN;
end if;
wr_en_done <= SR_5_Tx_Empty;
wr_en_under_process <= not SR_5_Tx_Empty;
when NM_WR_EN_DONE => if (Rst_to_spi = '1') then
nm_wr_en_cntrl_ns <= NM_WR_EN_IDLE;
else
nm_wr_en_cntrl_ns <= NM_WR_EN_DONE;
end if;
wr_en_done <= wr_en_done_reg;
end case;
end process NM_WR_EN_CNTRL_PROCESS;
----------------------------------------------------
NM_4_BYTE_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
nm_sm_4_byte_addr_ps <= NM_32_BIT_IDLE;
--four_byte_addr_under_process_d1 <= '0';
hpm_under_process_d1 <= '0';
wr_en_done_d1 <= '0';
wr_en_done_d2 <= '0';
wb_hpm_done_reg <= '0';
else
nm_sm_4_byte_addr_ps <= nm_sm_4_byte_addr_ns;
hpm_under_process_d1 <= hpm_under_process;
--four_byte_en_done_reg <= four_byte_en_done;
wr_en_done_d1 <= wr_en_done_reg; -- wr_en_done;
wr_en_done_d2 <= wr_en_done_d1;
wb_hpm_done_reg <= wb_hpm_done;
end if;
end if;
end process NM_4_BYTE_PS_TO_NS_PROCESS;
----------------------------------
--
NM_4_BYTE_ADDR_EN_PROCESS: process(
nm_sm_4_byte_addr_ps ,
Rst_to_spi ,
SR_5_Tx_Empty ,
wr_en_done_d2 ,
wb_hpm_done_reg
) is
-----
begin
-----
-- load_4_byte_addr_en <= '0';
load_wr_hpm <= '0';
wb_hpm_done <= '0';
hpm_under_process <= '0';
four_byte_en_done <= '0';
four_byte_en_under_process <= '0';
case nm_sm_4_byte_addr_ps is
when NM_32_BIT_IDLE => if (wr_en_done_d2 = '1') then
--load_wr_hpm <= '1';
--hpm_under_process <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN;
else
nm_sm_4_byte_addr_ns <= NM_32_BIT_IDLE;
end if;
load_wr_hpm <= wr_en_done_d2;
hpm_under_process <= wr_en_done_d2;
when NM_32_BIT_EN => if (SR_5_Tx_Empty = '1') then
-- wb_hpm_done <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN_DONE;
else
-- hpm_under_process <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN;
end if;
wb_hpm_done <= SR_5_Tx_Empty;
hpm_under_process <= not(SR_5_Tx_Empty);
when NM_32_BIT_EN_DONE => if(Rst_to_spi = '1')then
nm_sm_4_byte_addr_ns <= NM_32_BIT_IDLE;
else
-- if (SR_5_Tx_Empty = '1')then
-- --four_byte_en_done <= '1';
-- wb_hpm_done <= '1';
-- else
-- -- four_byte_en_under_process <= '1';
-- hpm_under_process <= '1';
-- end if;
-- four_byte_en_done <= four_byte_en_done_reg;
-- wb_hpm_done <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN_DONE;
end if;
wb_hpm_done <= wb_hpm_done_reg;
end case;
end process NM_4_BYTE_ADDR_EN_PROCESS;
--------------------------------------
DRIVE_CONTROL_SIG_P: process(EXT_SPI_CLK, wb_hpm_done, wr_en_done_reg) is -- wb_hpm_done, wr_en_done_reg) is
variable temp: std_logic_vector(1 downto 0);
begin
temp := wb_hpm_done & wr_en_done_reg;
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
case wb_hpm_done is
-- when "00"|"01" => -- write enable is under process
when '0' => -- write enable and/or Enable 4 byte addressing is under process
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- when "01" => -- Enable 4 byte addressing is under process
-- Data_Dir <= '0';
-- Data_Mode_1 <= '0';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '0';
-- --------------------
-- Quad_Phase <= '0';-- permanent '0'
-- --------------------
-- Addr_Mode_1 <= '0';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '0';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
-- when "10" => -- write enable is done and enable 4 byte addressing is also done
when '1' => -- write enable and enable 4 byte addressing is also done
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '1';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '1';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage off
when others =>
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage on
end case;
end if;
end process DRIVE_CONTROL_SIG_P;
---------------------------------------------------------------------
--end generate NM_EN_32_ADDR_MD_GEN;
end generate STD_SPI_CMD_NM_32_BIT_GEN;
---------------------------------------
-- wb_hpm_done <= four_byte_en_done;
--Data_Dir <= '0';
--Data_Mode_1 <= '0';
--Data_Mode_0 <= '0';
--Data_Phase <= '0';
----------------------
--Quad_Phase <= '0';-- permanent '0'
----------------------
--Addr_Mode_1 <= '0';
--Addr_Mode_0 <= '0';
--Addr_Bit <= '0';
--Addr_Phase <= '1';
----------------------
--CMD_Mode_1 <= '0';
--CMD_Mode_0 <= '0';
---------------------------
-----
RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
receive_Data_int <= (others => '0');
-- elsif(SPIXfer_done_int = '1') and (cmd_addr_cntr = "110")then
elsif(SPIXfer_done_int_pulse = '1') then
receive_Data_int <= rx_shft_reg_mode_0011;
elsif(SPIXfer_done_int_pulse_d1 = '1') and (cmd_addr_sent = '1')then
receive_Data_int <= receive_Data_int
((C_NUM_TRANSFER_BITS-2) downto 0) &
IO1_I ; --MISO_I;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS;
CMD_ADDR_24_BIT_CNTR_GEN : if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-- CMD_ADDR_CNTR_P: in each SPI transaction, the first 5 transactions are of
-- CMD, A0, A1, A2 and dummy. Total 5 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 5 bytes are transferred.
-- below counter is for that purpose only. Tihs is for 24 bit addressing mode only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or (wrap_around = '1') then
cmd_addr_cntr <= "000";
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1') then -- and store_date_in_drr_fifo_d3 = '1')then
cmd_addr_cntr <= "000";
cmd_addr_sent <= wrap_around;
elsif(SPIXfer_done_int = '1')then
if(cmd_addr_cntr = "101")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
----------------------------
end generate CMD_ADDR_24_BIT_CNTR_GEN;
--------------------------------------
CMD_ADDR_32_BIT_CNTR_GEN : if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-- * -- -----
-- * -- RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-- * -- -----
-- * -- begin
-- * -- -----
-- * -- if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
-- * -- if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
-- * -- receive_Data_int <= (others => '0');
-- * -- elsif(SPIXfer_done_int_pulse_d1 = '1') and (cmd_addr_sent = '1') then -- and (cmd_addr_cntr = "111")then
-- * -- receive_Data_int <= rx_shft_reg_mode_0011;
-- * -- end if;
-- * -- end if;
-- * -- end process RECEIVE_DATA_STROBE_PROCESS;
-- CMD_ADDR_CNTR_P: in each SPI transaction, the first 6 transactions are of
-- CMD, A0, A1, A2, A3 and dummy. Total 6 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 6 bytes are transferred.
-- below counter is for that purpose only. This is for 32 bit addressing mode only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or (wrap_around = '1') then
cmd_addr_cntr <= "000";
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1' and store_date_in_drr_fifo_d3 = '1')then
cmd_addr_cntr <= "000";
cmd_addr_sent <= wrap_around;
elsif(SPIXfer_done_int = '1' and wb_hpm_done = '1')then
if(cmd_addr_cntr = "110")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
----------------------------
end generate CMD_ADDR_32_BIT_CNTR_GEN;
--------------------------------------
-- TWO_BIT_CNTR_P: This is specifically used for HW data storage
TWO_BIT_CNTR_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') or (wrap_around = '1') then
hw_wd_cntr <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1')then
hw_wd_cntr <= hw_wd_cntr + "01";
end if;
end if;
end process TWO_BIT_CNTR_P;
----------------------------------------------
STORE_RX_DATA_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') then
Data_To_Rx_FIFO_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1') then
if(one_byte_xfer_to_spi_clk = '1') then
case spi_addr_i(1 downto 0) is
when "00" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 8) &
receive_Data_int;
when "01" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 16)&
receive_Data_int &
Data_To_Rx_FIFO_int(7 downto 0);
when "10" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 24)&
receive_Data_int &
Data_To_Rx_FIFO_int(15 downto 0);
when "11" =>
Data_To_Rx_FIFO_int <= receive_Data_int &
Data_To_Rx_FIFO_int(23 downto 0);
when others => null;
end case;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '0') then -- adjustment for half word
if(spi_addr_i(1) = '0') then
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);-- & receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= receive_Data_int & Data_To_Rx_FIFO_int(15 downto 8);-- & receive_Data_int;
else
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);-- & receive_Data_int;
Data_To_Rx_FIFO_int(31 downto 16)<= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 24);-- & receive_Data_int;
end if;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '1') then -- adjustment for half word
if(hw_wd_cntr = "00") then -- fill in D0
Data_To_Rx_FIFO_int(31 downto 8) <= Data_To_Rx_FIFO_int(31 downto 8);
Data_To_Rx_FIFO_int(7 downto 0) <= receive_Data_int;
elsif(hw_wd_cntr = "01")then -- fill in D1
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);
Data_To_Rx_FIFO_int(15 downto 8) <= receive_Data_int;
Data_To_Rx_FIFO_int(7 downto 0) <= Data_To_Rx_FIFO_int(7 downto 0);
elsif(hw_wd_cntr = "10")then -- fill in D2
Data_To_Rx_FIFO_int(31 downto 24) <= Data_To_Rx_FIFO_int(31 downto 24);
Data_To_Rx_FIFO_int(23 downto 16) <= receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);
else
Data_To_Rx_FIFO_int(31 downto 24) <= receive_Data_int;
Data_To_Rx_FIFO_int(23 downto 0) <= Data_To_Rx_FIFO_int(23 downto 0);
end if;
else -- adjustment for complete word
--Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(23 downto 0) & receive_Data_int;
Data_To_Rx_FIFO_int <= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 8);
end if;
end if;
end if;
end process STORE_RX_DATA_SPI_CLK_P;
----------------------------
Data_To_Rx_FIFO <= Data_To_Rx_FIFO_int;
---------------------------------------
end generate NM_MEM_STD_MD_GEN;
------------------------
SP_MEM_STD_MD_GEN: if C_SPI_MODE = 0 and C_SPI_MEMORY = 3 generate
signal cmd_addr_cntr : std_logic_vector(2 downto 0);
signal hw_wd_cntr : std_logic_vector(1 downto 0);
-----
begin
-----
---- Std mode command = 0x0B - Fast Read
STD_SPI_CMD_SP_24_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
SPI_cmd <= "00001011";-- FAST_READ - 0x0Bh
-- |<---- cmd error
-- NM 000 000 0100 0
four_byte_en_done <= '1';
wb_hpm_done <= '1';
DRIVE_CONTROL_SIG_P: process(EXT_SPI_CLK) is -- wb_hpm_done, wr_en_done_reg) is
variable temp: std_logic_vector(1 downto 0);
begin
temp := wb_hpm_done & wr_en_done_reg;
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
--case wb_hpm_done is
-- -- when "00"|"01" => -- write enable is under process
-- when '0' => -- write enable and/or Enable 4 byte addressing is under process
-- Data_Dir <= '0';
-- Data_Mode_1 <= '0';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '0';
-- --------------------
-- Quad_Phase <= '0';-- permanent '0'
-- --------------------
-- Addr_Mode_1 <= '0';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '0';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
-- -- when "01" => -- Enable 4 byte addressing is under process
-- -- Data_Dir <= '0';
-- -- Data_Mode_1 <= '0';
-- -- Data_Mode_0 <= '0';
-- -- Data_Phase <= '0';
-- -- --------------------
-- -- Quad_Phase <= '0';-- permanent '0'
-- -- --------------------
-- -- Addr_Mode_1 <= '0';
-- -- Addr_Mode_0 <= '0';
-- -- Addr_Bit <= '0';
-- -- Addr_Phase <= '0';
-- -- --------------------
-- -- CMD_Mode_1 <= '0';
-- -- CMD_Mode_0 <= '0';
-- -- when "10" => -- write enable is done and enable 4 byte addressing is also done
-- when '1' => -- write enable and enable 4 byte addressing is also done
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- -- coverage off
-- when others =>
-- Data_Dir <= '0';
-- Data_Mode_1 <= '0';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '0';
-- --------------------
-- Quad_Phase <= '0';-- permanent '0'
-- --------------------
-- Addr_Mode_1 <= '0';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '0';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
-- -- coverage on
--end case;
end if;
end process DRIVE_CONTROL_SIG_P;
---------------------------------------------------------------------
end generate STD_SPI_CMD_SP_24_BIT_GEN;
STD_SPI_CMD_SP_32_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
SPI_cmd <= "00001100";-- FAST_READ_4Byte - 0x0Ch
-- |<---- cmd error
-- NM 000 000 0100 0
--end generate STD_SPI_CMD_NM_32_BIT_GEN;
--NM_EN_32_ADDR_MD_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
--begin
-----
nm_wr_en_CMD <= "00000110"; -- 0x06 h Write Enable
nm_4byte_addr_en_CMD <= "10110111"; -- 0xB7 h Enable 4 Byte Addressing Mode
----------------------------------------------------
SP_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
nm_wr_en_cntrl_ps <= NM_WR_EN_IDLE;
wr_en_under_process_d1 <= '0';
wr_en_done_reg <= '0';
else
nm_wr_en_cntrl_ps <= nm_wr_en_cntrl_ns;
wr_en_under_process_d1 <= wr_en_under_process;
wr_en_done_reg <= wr_en_done;
end if;
end if;
end process SP_PS_TO_NS_PROCESS;
----------------------------------
--
SP_WR_EN_CNTRL_PROCESS: process(
nm_wr_en_cntrl_ps ,
--SPIXfer_done_int_pulse,
--SPIXfer_done_int ,
Rst_to_spi ,
SR_5_Tx_Empty ,
wr_en_done_reg
) is
-----
begin
-----
--load_wr_en_cmd <= '0';
--load_wr_sr_cmd <= '0';
--load_wr_sr_d0 <= '0';
--load_wr_sr_d1 <= '0';
load_wr_en <= '0';
wr_en_done <= '0';
wr_en_under_process <= '0';
case nm_wr_en_cntrl_ps is
when NM_WR_EN_IDLE => --load_wr_en_cmd <= '1';
load_wr_en <= '1';
wr_en_under_process <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN;
when NM_WR_EN => if (SR_5_Tx_Empty = '1')then
--wr_en_done <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN_DONE;
else
--wr_en_under_process <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN;
end if;
wr_en_done <= SR_5_Tx_Empty;
wr_en_under_process <= not SR_5_Tx_Empty;
when NM_WR_EN_DONE => if (Rst_to_spi = '1') then
nm_wr_en_cntrl_ns <= NM_WR_EN_IDLE;
else
nm_wr_en_cntrl_ns <= NM_WR_EN_DONE;
end if;
wr_en_done <= wr_en_done_reg;
end case;
end process SP_WR_EN_CNTRL_PROCESS;
----------------------------------------------------
SP_4_BYTE_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
nm_sm_4_byte_addr_ps <= NM_32_BIT_IDLE;
--four_byte_addr_under_process_d1 <= '0';
hpm_under_process_d1 <= '0';
wr_en_done_d1 <= '0';
wr_en_done_d2 <= '0';
wb_hpm_done_reg <= '0';
else
nm_sm_4_byte_addr_ps <= nm_sm_4_byte_addr_ns;
hpm_under_process_d1 <= hpm_under_process;
--four_byte_en_done_reg <= four_byte_en_done;
wr_en_done_d1 <= wr_en_done_reg; -- wr_en_done;
wr_en_done_d2 <= wr_en_done_d1;
wb_hpm_done_reg <= wb_hpm_done;
end if;
end if;
end process SP_4_BYTE_PS_TO_NS_PROCESS;
----------------------------------
--
SP_4_BYTE_ADDR_EN_PROCESS: process(
nm_sm_4_byte_addr_ps ,
Rst_to_spi ,
SR_5_Tx_Empty ,
wr_en_done_d2 ,
wb_hpm_done_reg
) is
-----
begin
-----
-- load_4_byte_addr_en <= '0';
load_wr_hpm <= '0';
wb_hpm_done <= '0';
hpm_under_process <= '0';
four_byte_en_done <= '0';
four_byte_en_under_process <= '0';
case nm_sm_4_byte_addr_ps is
when NM_32_BIT_IDLE => if (wr_en_done_d2 = '1') then
--load_wr_hpm <= '1';
--hpm_under_process <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN;
else
nm_sm_4_byte_addr_ns <= NM_32_BIT_IDLE;
end if;
load_wr_hpm <= wr_en_done_d2;
hpm_under_process <= wr_en_done_d2;
when NM_32_BIT_EN => if (SR_5_Tx_Empty = '1') then
-- wb_hpm_done <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN_DONE;
else
-- hpm_under_process <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN;
end if;
wb_hpm_done <= SR_5_Tx_Empty;
hpm_under_process <= not(SR_5_Tx_Empty);
when NM_32_BIT_EN_DONE => if(Rst_to_spi = '1')then
nm_sm_4_byte_addr_ns <= NM_32_BIT_IDLE;
else
-- if (SR_5_Tx_Empty = '1')then
-- --four_byte_en_done <= '1';
-- wb_hpm_done <= '1';
-- else
-- -- four_byte_en_under_process <= '1';
-- hpm_under_process <= '1';
-- end if;
-- four_byte_en_done <= four_byte_en_done_reg;
-- wb_hpm_done <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN_DONE;
end if;
wb_hpm_done <= wb_hpm_done_reg;
end case;
end process SP_4_BYTE_ADDR_EN_PROCESS;
--------------------------------------
DRIVE_CONTROL_SIG_P: process(EXT_SPI_CLK) is -- wb_hpm_done, wr_en_done_reg) is
variable temp: std_logic_vector(1 downto 0);
begin
temp := wb_hpm_done & wr_en_done_reg;
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
case wb_hpm_done is
-- when "00"|"01" => -- write enable is under process
when '0' => -- write enable and/or Enable 4 byte addressing is under process
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- when "01" => -- Enable 4 byte addressing is under process
-- Data_Dir <= '0';
-- Data_Mode_1 <= '0';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '0';
-- --------------------
-- Quad_Phase <= '0';-- permanent '0'
-- --------------------
-- Addr_Mode_1 <= '0';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '0';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
-- when "10" => -- write enable is done and enable 4 byte addressing is also done
when '1' => -- write enable and enable 4 byte addressing is also done
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '1';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '1';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage off
when others =>
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage on
end case;
end if;
end process DRIVE_CONTROL_SIG_P;
---------------------------------------------------------------------
--end generate NM_EN_32_ADDR_MD_GEN;
end generate STD_SPI_CMD_SP_32_BIT_GEN;
---------------------------------------
-- wb_hpm_done <= four_byte_en_done;
--Data_Dir <= '0';
--Data_Mode_1 <= '0';
--Data_Mode_0 <= '0';
--Data_Phase <= '0';
----------------------
--Quad_Phase <= '0';-- permanent '0'
----------------------
--Addr_Mode_1 <= '0';
--Addr_Mode_0 <= '0';
--Addr_Bit <= '0';
--Addr_Phase <= '1';
----------------------
--CMD_Mode_1 <= '0';
--CMD_Mode_0 <= '0';
---------------------------
-----
RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
receive_Data_int <= (others => '0');
-- elsif(SPIXfer_done_int = '1') and (cmd_addr_cntr = "110")then
elsif(SPIXfer_done_int_pulse = '1') then
receive_Data_int <= rx_shft_reg_mode_0011;
elsif(SPIXfer_done_int_pulse_d1 = '1') and (cmd_addr_sent = '1')then
receive_Data_int <= receive_Data_int
((C_NUM_TRANSFER_BITS-2) downto 0) &
IO1_I ; --MISO_I;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS;
CMD_ADDR_24_BIT_CNTR_GEN : if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-- CMD_ADDR_CNTR_P: in each SPI transaction, the first 5 transactions are of
-- CMD, A0, A1, A2 and dummy. Total 5 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 5 bytes are transferred.
-- below counter is for that purpose only. Tihs is for 24 bit addressing mode only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or (wrap_around = '1') then
cmd_addr_cntr <= "000";
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1') then -- and store_date_in_drr_fifo_d3 = '1')then
cmd_addr_cntr <= "000";
cmd_addr_sent <= wrap_around;
elsif(SPIXfer_done_int = '1')then
if(cmd_addr_cntr = "101")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
----------------------------
end generate CMD_ADDR_24_BIT_CNTR_GEN;
--------------------------------------
CMD_ADDR_32_BIT_CNTR_GEN : if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-- * -- -----
-- * -- RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-- * -- -----
-- * -- begin
-- * -- -----
-- * -- if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
-- * -- if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
-- * -- receive_Data_int <= (others => '0');
-- * -- elsif(SPIXfer_done_int_pulse_d1 = '1') and (cmd_addr_sent = '1') then -- and (cmd_addr_cntr = "111")then
-- * -- receive_Data_int <= rx_shft_reg_mode_0011;
-- * -- end if;
-- * -- end if;
-- * -- end process RECEIVE_DATA_STROBE_PROCESS;
-- CMD_ADDR_CNTR_P: in each SPI transaction, the first 6 transactions are of
-- CMD, A0, A1, A2, A3 and dummy. Total 6 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 6 bytes are transferred.
-- below counter is for that purpose only. This is for 32 bit addressing mode only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or (wrap_around = '1') then
cmd_addr_cntr <= "000";
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1' and store_date_in_drr_fifo_d3 = '1')then
cmd_addr_cntr <= "000";
cmd_addr_sent <= wrap_around;
elsif(SPIXfer_done_int = '1' and wb_hpm_done = '1')then
if(cmd_addr_cntr = "110")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
----------------------------
end generate CMD_ADDR_32_BIT_CNTR_GEN;
--------------------------------------
-- TWO_BIT_CNTR_P: This is specifically used for HW data storage
TWO_BIT_CNTR_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') or (wrap_around = '1') then
hw_wd_cntr <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1')then
hw_wd_cntr <= hw_wd_cntr + "01";
end if;
end if;
end process TWO_BIT_CNTR_P;
----------------------------------------------
STORE_RX_DATA_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') then
Data_To_Rx_FIFO_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1') then
if(one_byte_xfer_to_spi_clk = '1') then
case spi_addr_i(1 downto 0) is
when "00" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 8) &
receive_Data_int;
when "01" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 16)&
receive_Data_int &
Data_To_Rx_FIFO_int(7 downto 0);
when "10" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 24)&
receive_Data_int &
Data_To_Rx_FIFO_int(15 downto 0);
when "11" =>
Data_To_Rx_FIFO_int <= receive_Data_int &
Data_To_Rx_FIFO_int(23 downto 0);
when others => null;
end case;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '0') then -- adjustment for half word
if(spi_addr_i(1) = '0') then
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);-- & receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= receive_Data_int & Data_To_Rx_FIFO_int(15 downto 8);-- & receive_Data_int;
else
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);-- & receive_Data_int;
Data_To_Rx_FIFO_int(31 downto 16)<= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 24);-- & receive_Data_int;
end if;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '1') then -- adjustment for half word
if(hw_wd_cntr = "00") then -- fill in D0
Data_To_Rx_FIFO_int(31 downto 8) <= Data_To_Rx_FIFO_int(31 downto 8);
Data_To_Rx_FIFO_int(7 downto 0) <= receive_Data_int;
elsif(hw_wd_cntr = "01")then -- fill in D1
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);
Data_To_Rx_FIFO_int(15 downto 8) <= receive_Data_int;
Data_To_Rx_FIFO_int(7 downto 0) <= Data_To_Rx_FIFO_int(7 downto 0);
elsif(hw_wd_cntr = "10")then -- fill in D2
Data_To_Rx_FIFO_int(31 downto 24) <= Data_To_Rx_FIFO_int(31 downto 24);
Data_To_Rx_FIFO_int(23 downto 16) <= receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);
else
Data_To_Rx_FIFO_int(31 downto 24) <= receive_Data_int;
Data_To_Rx_FIFO_int(23 downto 0) <= Data_To_Rx_FIFO_int(23 downto 0);
end if;
else -- adjustment for complete word
--Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(23 downto 0) & receive_Data_int;
Data_To_Rx_FIFO_int <= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 8);
end if;
end if;
end if;
end process STORE_RX_DATA_SPI_CLK_P;
----------------------------
Data_To_Rx_FIFO <= Data_To_Rx_FIFO_int;
---------------------------------------
end generate SP_MEM_STD_MD_GEN;
end generate STD_MODE_CONTROL_GEN;
-------------------------------------------------------------------------------
DUAL_MODE_CONTROL_GEN: if C_SPI_MODE = 1 generate
signal cmd_addr_cntr : std_logic_vector(2 downto 0);-----
signal hw_wd_cntr : std_logic_vector(1 downto 0);
begin
-----
WB_MEM_DUAL_MD_GEN: if C_SPI_MEMORY = 1 generate
-----
begin
-----
wb_wr_hpm_CMD <= "10100011"; -- 0xA3 h HPM mode
--
----------------------------------------------------
WB_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
wb_cntrl_ps <= WB_IDLE;
hpm_under_process_d1 <= '0';
else
wb_cntrl_ps <= wb_cntrl_ns;
hpm_under_process_d1 <= hpm_under_process;
end if;
end if;
end process WB_PS_TO_NS_PROCESS;
----------------------------------
--
WB_DUAL_CNTRL_PROCESS: process(
wb_cntrl_ps ,
SPIXfer_done_int_pulse,
SPIXfer_done_int ,
Rst_to_spi ,
SR_5_Tx_Empty
) is
-----
begin
-----
load_wr_en_cmd <= '0';
load_wr_sr_cmd <= '0';
load_wr_sr_d0 <= '0';
load_wr_sr_d1 <= '0';
load_wr_hpm <= '0';
wb_hpm_done <= '0';
hpm_under_process <= '0';
case wb_cntrl_ps is
when WB_IDLE => --load_wr_en_cmd <= '1';
load_wr_hpm <= '1';
hpm_under_process <= '1';
wb_cntrl_ns <= WB_WR_HPM;
when WB_WR_HPM => if (SR_5_Tx_Empty = '1')then
wb_hpm_done <= '1';
wb_cntrl_ns <= WB_DONE;
else
hpm_under_process <= '1';
wb_cntrl_ns <= WB_WR_HPM;
end if;
when WB_DONE => if (Rst_to_spi = '1') then
wb_cntrl_ns <= WB_IDLE;
else
wb_hpm_done <= '1';
wb_cntrl_ns <= WB_DONE;
end if;
end case;
end process WB_DUAL_CNTRL_PROCESS;
---- Dual mode command = 0x3B - DOFR
--SPI_cmd <= "00111011";
SPI_cmd <= "10111011"; -- 0xBB - DIOFR
-- WB 0011 000 100 0
-- NM 0011 000 100 0<-cmd error
-- NM 0011 010 100 0<-cmd error -- For 0xbbh DIOFR
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '1';
Data_Phase <= '1';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '1'; -- <- '0' for DOFR, '1' for DIOFR
Addr_Bit <= '0';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
---------------------------------------------------------------------
--RECEIVE_DATA_WB_GEN: if C_SPI_MEMORY = 1 and C_SPI_MODE /=0 generate
--begin
-----
RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
receive_Data_int <= (others => '0');
elsif(SPIXfer_done_int_pulse = '1') then
receive_Data_int <= rx_shft_reg_mode_0011;
elsif(SPIXfer_done_int_pulse_d1 = '1') and (cmd_addr_sent = '1')then
receive_Data_int <= receive_Data_int
((C_NUM_TRANSFER_BITS-3) downto 0) &
IO1_I & -- MISO_I - MSB first
IO0_I ; -- MOSI_I
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS;
--end generate RECEIVE_DATA_WB_GEN;
---------------------------------------------------------------------
-- CMD_ADDR_CNTR_P: in each SPI transaction, the firs 4 transactions are of
-- CMD, A0, A1, A2. Total 4 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 4 bytes are transferred.
-- below counter is for that purpose only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or (store_last_b4_wrap = '1') then
cmd_addr_cntr <= "000";--(others => '1');
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1')then
cmd_addr_cntr <= "000";
cmd_addr_sent <= store_last_b4_wrap;
elsif(SPIXfer_done_int_pulse_d2 = '1')then
if(cmd_addr_cntr = "100")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
----------------------------
TWO_BIT_CNTR_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') or (store_last_b4_wrap = '1') then
hw_wd_cntr <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1')then
hw_wd_cntr <= hw_wd_cntr + "01";
end if;
end if;
end process TWO_BIT_CNTR_P;
----------------------------------------------
STORE_RX_DATA_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') then
Data_To_Rx_FIFO_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1') then
if(one_byte_xfer_to_spi_clk = '1') then
case spi_addr_i(1 downto 0) is
when "00" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 8) &
receive_Data_int;
when "01" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 16)&
receive_Data_int &
Data_To_Rx_FIFO_int(7 downto 0);
when "10" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 24)&
receive_Data_int &
Data_To_Rx_FIFO_int(15 downto 0);
when "11" =>
Data_To_Rx_FIFO_int <= receive_Data_int &
Data_To_Rx_FIFO_int(23 downto 0);
when others => null;
end case;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '0') then -- adjustment for half word
if(spi_addr_i(1) = '0') then
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);-- & receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= receive_Data_int & Data_To_Rx_FIFO_int(15 downto 8);-- & receive_Data_int;
else
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);-- & receive_Data_int;
Data_To_Rx_FIFO_int(31 downto 16)<= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 24);-- & receive_Data_int;
end if;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '1') then -- adjustment for half word
if(hw_wd_cntr = "00") then -- fill in D0
Data_To_Rx_FIFO_int(31 downto 8) <= Data_To_Rx_FIFO_int(31 downto 8);
Data_To_Rx_FIFO_int(7 downto 0) <= receive_Data_int;
elsif(hw_wd_cntr = "01")then -- fill in D1
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);
Data_To_Rx_FIFO_int(15 downto 8) <= receive_Data_int;
Data_To_Rx_FIFO_int(7 downto 0) <= Data_To_Rx_FIFO_int(7 downto 0);
elsif(hw_wd_cntr = "10")then -- fill in D2
Data_To_Rx_FIFO_int(31 downto 24) <= Data_To_Rx_FIFO_int(31 downto 24);
Data_To_Rx_FIFO_int(23 downto 16) <= receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);
else
Data_To_Rx_FIFO_int(31 downto 24) <= receive_Data_int;
Data_To_Rx_FIFO_int(23 downto 0) <= Data_To_Rx_FIFO_int(23 downto 0);
end if;
else -- adjustment for complete word
--Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(23 downto 0) & receive_Data_int;
Data_To_Rx_FIFO_int <= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 8);
end if;
end if;
end if;
end process STORE_RX_DATA_SPI_CLK_P;
----------------------------
Data_To_Rx_FIFO <= Data_To_Rx_FIFO_int;
---------------------------------------
end generate WB_MEM_DUAL_MD_GEN;
---------------=============-------------------------------------------
NM_MEM_DUAL_MD_GEN: if C_SPI_MEMORY = 2 generate
-----
begin
-----
--wb_hpm_done <= '1';
---- Dual mode command = 0x3B - DOFR
--SPI_cmd <= "00111011";
--------------------------------------------------------
DUAL_SPI_CMD_NM_24_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
-----
begin
-----
---------------------------
SPI_cmd <= "10111011"; -- 0xBB - DIOFR
wb_hpm_done <= '1';
---------------------------
Data_Dir <= '0';-- for BB
Data_Mode_1 <= '0';
Data_Mode_0 <= '1';
Data_Phase <= '1';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '1';
Addr_Bit <= '0';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
---------------------------
end generate DUAL_SPI_CMD_NM_24_GEN;
------------------------------------
DUAL_SPI_CMD_NM_32_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
-----
begin
-----
SPI_cmd <= "10111100"; -- 0xBCh - DIOFR_4Byte
end generate DUAL_SPI_CMD_NM_32_GEN;
------------------------------------
NM_EN_32_ADDR_MD_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-----
nm_wr_en_CMD <= "00000110"; -- 0x06 h Write Enable
nm_4byte_addr_en_CMD <= "10110111"; -- 0xB7 h Enable 4 Byte Addressing Mode
----------------------------------------------------
NM_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
nm_wr_en_cntrl_ps <= NM_WR_EN_IDLE;
wr_en_under_process_d1 <= '0';
wr_en_done_reg <= '0';
else
nm_wr_en_cntrl_ps <= nm_wr_en_cntrl_ns;
wr_en_under_process_d1 <= wr_en_under_process;
wr_en_done_reg <= wr_en_done;
end if;
end if;
end process NM_PS_TO_NS_PROCESS;
----------------------------------
--
NM_WR_EN_CNTRL_PROCESS: process(
nm_wr_en_cntrl_ps ,
--SPIXfer_done_int_pulse,
--SPIXfer_done_int ,
Rst_to_spi ,
SR_5_Tx_Empty ,
wr_en_done_reg
) is
-----
begin
-----
--load_wr_en_cmd <= '0';
--load_wr_sr_cmd <= '0';
--load_wr_sr_d0 <= '0';
--load_wr_sr_d1 <= '0';
load_wr_en <= '0';
wr_en_done <= '0';
wr_en_under_process <= '0';
case nm_wr_en_cntrl_ps is
when NM_WR_EN_IDLE => --load_wr_en_cmd <= '1';
load_wr_en <= '1';
wr_en_under_process <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN;
when NM_WR_EN => if (SR_5_Tx_Empty = '1')then
--wr_en_done <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN_DONE;
else
--wr_en_under_process <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN;
end if;
wr_en_done <= SR_5_Tx_Empty;
wr_en_under_process <= not SR_5_Tx_Empty;
when NM_WR_EN_DONE => if (Rst_to_spi = '1') then
nm_wr_en_cntrl_ns <= NM_WR_EN_IDLE;
else
nm_wr_en_cntrl_ns <= NM_WR_EN_DONE;
end if;
wr_en_done <= wr_en_done_reg;
end case;
end process NM_WR_EN_CNTRL_PROCESS;
----------------------------------------------------
NM_4_BYTE_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
nm_sm_4_byte_addr_ps <= NM_32_BIT_IDLE;
--four_byte_addr_under_process_d1 <= '0';
hpm_under_process_d1 <= '0';
wr_en_done_d1 <= '0';
wr_en_done_d2 <= '0';
wb_hpm_done_reg <= '0';
else
nm_sm_4_byte_addr_ps <= nm_sm_4_byte_addr_ns;
hpm_under_process_d1 <= hpm_under_process;
--four_byte_en_done_reg <= four_byte_en_done;
wr_en_done_d1 <= wr_en_done_reg; -- wr_en_done;
wr_en_done_d2 <= wr_en_done_d1;
wb_hpm_done_reg <= wb_hpm_done;
end if;
end if;
end process NM_4_BYTE_PS_TO_NS_PROCESS;
----------------------------------
--
NM_4_BYTE_ADDR_EN_PROCESS: process(
nm_sm_4_byte_addr_ps ,
Rst_to_spi ,
SR_5_Tx_Empty ,
wr_en_done_d2 ,
wb_hpm_done_reg
) is
-----
begin
-----
-- load_4_byte_addr_en <= '0';
load_wr_hpm <= '0';
wb_hpm_done <= '0';
hpm_under_process <= '0';
four_byte_en_done <= '0';
four_byte_en_under_process <= '0';
case nm_sm_4_byte_addr_ps is
when NM_32_BIT_IDLE => if (wr_en_done_d2 = '1') then
--load_wr_hpm <= '1';
--hpm_under_process <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN;
else
nm_sm_4_byte_addr_ns <= NM_32_BIT_IDLE;
end if;
load_wr_hpm <= wr_en_done_d2;
hpm_under_process <= wr_en_done_d2;
when NM_32_BIT_EN => if (SR_5_Tx_Empty = '1') then
-- wb_hpm_done <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN_DONE;
else
-- hpm_under_process <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN;
end if;
wb_hpm_done <= SR_5_Tx_Empty;
hpm_under_process <= not(SR_5_Tx_Empty);
when NM_32_BIT_EN_DONE => if(Rst_to_spi = '1')then
nm_sm_4_byte_addr_ns <= NM_32_BIT_IDLE;
else
-- if (SR_5_Tx_Empty = '1')then
-- --four_byte_en_done <= '1';
-- wb_hpm_done <= '1';
-- else
-- -- four_byte_en_under_process <= '1';
-- hpm_under_process <= '1';
-- end if;
-- four_byte_en_done <= four_byte_en_done_reg;
-- wb_hpm_done <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN_DONE;
end if;
wb_hpm_done <= wb_hpm_done_reg;
end case;
end process NM_4_BYTE_ADDR_EN_PROCESS;
--------------------------------------
DRIVE_CONTROL_SIG_P: process(EXT_SPI_CLK, wb_hpm_done, wr_en_done_reg) is -- wb_hpm_done, wr_en_done_reg) is
variable temp: std_logic_vector(1 downto 0);
begin
temp := wb_hpm_done & wr_en_done_reg;
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
case wb_hpm_done is
-- when "00"|"01" => -- write enable is under process
when '0' => -- write enable and/or Enable 4 byte addressing is under process
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- when "01" => -- Enable 4 byte addressing is under process
-- Data_Dir <= '0';
-- Data_Mode_1 <= '0';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '0';
-- --------------------
-- Quad_Phase <= '0';-- permanent '0'
-- --------------------
-- Addr_Mode_1 <= '0';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '0';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
-- when "10" => -- write enable is done and enable 4 byte addressing is also done
when '1' => -- write enable and enable 4 byte addressing is also done
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '1';
Data_Phase <= '1';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '1';
Addr_Bit <= '1';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage off
when others =>
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage on
end case;
end if;
end process DRIVE_CONTROL_SIG_P;
end generate NM_EN_32_ADDR_MD_GEN;
--------------------------------------
-- -- WB 0011 000 100 0
-- -- NM 0011 000 100 0<-cmd error
-- -- NM 0011 010 100 0<-cmd error -- For 0xbbh DIOFR
-- 0011 011 100 0
-- Data_Dir <= '0';<-- for BB -- '0';<-- for BC
-- Data_Mode_1 <= '0'; -- '0';
-- Data_Mode_0 <= '1'; -- '1';
-- Data_Phase <= '1'; -- '1';
-- -------------------- --
-- Quad_Phase <= '0';-- permanent '0' -- '0';
-- -------------------- --
-- Addr_Mode_1 <= '0'; -- '0';
-- Addr_Mode_0 <= '1'; -- '1';
-- Addr_Bit <= '0'; -- '1';
-- Addr_Phase <= '1'; -- '1';
-- -------------------- --
-- CMD_Mode_1 <= '0'; -- '0'
-- CMD_Mode_0 <= '0'; -- '0';
---------------------------------------------------------------------
-- RECEIVE_DATA_STROBE_PROCESS : Strobe data from shift register to receive
-- data register
--------------------------------
-- For a SCK ratio of 2 the Done needs to be delayed by an extra cycle
-- due to the serial input being captured on the falling edge of the PLB
-- clock. this is purely required for dealing with the real SPI slave memories.
--RECEIVE_DATA_NM_GEN: if C_SPI_MEMORY = 2 and C_SPI_MODE /=0 generate
--begin
-----
RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
receive_Data_int <= (others => '0');
elsif(SPIXfer_done_int_pulse = '1') then
receive_Data_int <= rx_shft_reg_mode_0011;
elsif(SPIXfer_done_int_pulse_d1 = '1') then
receive_Data_int <= receive_Data_int
((C_NUM_TRANSFER_BITS-3) downto 0) &
IO1_I & -- MISO_I - MSB first
IO0_I ; -- MOSI_I
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS;
--end generate RECEIVE_DATA_NM_GEN;
-----------------------------------------------------------------------------
CMD_ADDR_NM_24_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-- CMD_ADDR_CNTR_P: in each SPI transaction, the firs 4 transactions are of
-- CMD, A0, A1, A2. Total 4 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 4 bytes are transferred.
-- below counter is for that purpose only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or (store_last_b4_wrap = '1') then
cmd_addr_cntr <= "000";--(others => '1');
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1')then
cmd_addr_cntr <= "000";
cmd_addr_sent <= store_last_b4_wrap;
elsif(SPIXfer_done_int_pulse_d2 = '1')then
if(cmd_addr_cntr = "101")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
----------------------------
end generate CMD_ADDR_NM_24_BIT_GEN;
------------------------------------
CMD_ADDR_NM_32_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-- CMD_ADDR_CNTR_P: in each SPI transaction, the firs 5 transactions are of
-- CMD, A0, A1, A2, A3. Total 5 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 5 bytes are transferred.
-- below counter is for that purpose only. This is 4 byte addessing mode of NM memory.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or (store_last_b4_wrap = '1') then
cmd_addr_cntr <= "000";--(others => '1');
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1')then
cmd_addr_cntr <= "000";
cmd_addr_sent <= store_last_b4_wrap;
elsif(SPIXfer_done_int_pulse_d2 = '1')then
if(cmd_addr_cntr = "111")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
----------------------------
end generate CMD_ADDR_NM_32_BIT_GEN;
------------------------------------
TWO_BIT_CNTR_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') or (store_last_b4_wrap = '1') then
hw_wd_cntr <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1')then
hw_wd_cntr <= hw_wd_cntr + "01";
end if;
end if;
end process TWO_BIT_CNTR_P;
----------------------------------------------
STORE_RX_DATA_32_BIT_ADDR: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-----
STORE_RX_DATA_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') then
Data_To_Rx_FIFO_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d3 = '1') and (cmd_addr_sent = '1') then
if(one_byte_xfer_to_spi_clk = '1') then
case spi_addr_i(1 downto 0) is
when "00" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 8) &
receive_Data_int;
when "01" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 16)&
receive_Data_int &
Data_To_Rx_FIFO_int(7 downto 0);
when "10" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 24)&
receive_Data_int &
Data_To_Rx_FIFO_int(15 downto 0);
when "11" =>
Data_To_Rx_FIFO_int <= receive_Data_int &
Data_To_Rx_FIFO_int(23 downto 0);
when others => null;
end case;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '0') then -- adjustment for half word
if(spi_addr_i(1) = '0') then
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);-- & receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= receive_Data_int & Data_To_Rx_FIFO_int(15 downto 8);-- & receive_Data_int;
else
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);-- & receive_Data_int;
Data_To_Rx_FIFO_int(31 downto 16)<= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 24);-- & receive_Data_int;
end if;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '1') then -- adjustment for half word
if(hw_wd_cntr = "00") then -- fill in D0
Data_To_Rx_FIFO_int(31 downto 8) <= Data_To_Rx_FIFO_int(31 downto 8);
Data_To_Rx_FIFO_int(7 downto 0) <= receive_Data_int;
elsif(hw_wd_cntr = "01")then -- fill in D1
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);
Data_To_Rx_FIFO_int(15 downto 8) <= receive_Data_int;
Data_To_Rx_FIFO_int(7 downto 0) <= Data_To_Rx_FIFO_int(7 downto 0);
elsif(hw_wd_cntr = "10")then -- fill in D2
Data_To_Rx_FIFO_int(31 downto 24) <= Data_To_Rx_FIFO_int(31 downto 24);
Data_To_Rx_FIFO_int(23 downto 16) <= receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);
else
Data_To_Rx_FIFO_int(31 downto 24) <= receive_Data_int;
Data_To_Rx_FIFO_int(23 downto 0) <= Data_To_Rx_FIFO_int(23 downto 0);
end if;
else -- adjustment for complete word
--Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(23 downto 0) & receive_Data_int;
Data_To_Rx_FIFO_int <= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 8);
end if;
end if;
end if;
end process STORE_RX_DATA_SPI_CLK_P;
end generate STORE_RX_DATA_32_BIT_ADDR;
STORE_RX_DATA_24_BIT_ADDR: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-----
STORE_RX_DATA_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') then
Data_To_Rx_FIFO_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1') then
if(one_byte_xfer_to_spi_clk = '1') then
case spi_addr_i(1 downto 0) is
when "00" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 8) &
receive_Data_int;
when "01" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 16)&
receive_Data_int &
Data_To_Rx_FIFO_int(7 downto 0);
when "10" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 24)&
receive_Data_int &
Data_To_Rx_FIFO_int(15 downto 0);
when "11" =>
Data_To_Rx_FIFO_int <= receive_Data_int &
Data_To_Rx_FIFO_int(23 downto 0);
when others => null;
end case;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '0') then -- adjustment for half word
if(spi_addr_i(1) = '0') then
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);-- & receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= receive_Data_int & Data_To_Rx_FIFO_int(15 downto 8);-- & receive_Data_int;
else
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);-- & receive_Data_int;
Data_To_Rx_FIFO_int(31 downto 16)<= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 24);-- & receive_Data_int;
end if;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '1') then -- adjustment for half word
if(hw_wd_cntr = "00") then -- fill in D0
Data_To_Rx_FIFO_int(31 downto 8) <= Data_To_Rx_FIFO_int(31 downto 8);
Data_To_Rx_FIFO_int(7 downto 0) <= receive_Data_int;
elsif(hw_wd_cntr = "01")then -- fill in D1
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);
Data_To_Rx_FIFO_int(15 downto 8) <= receive_Data_int;
Data_To_Rx_FIFO_int(7 downto 0) <= Data_To_Rx_FIFO_int(7 downto 0);
elsif(hw_wd_cntr = "10")then -- fill in D2
Data_To_Rx_FIFO_int(31 downto 24) <= Data_To_Rx_FIFO_int(31 downto 24);
Data_To_Rx_FIFO_int(23 downto 16) <= receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);
else
Data_To_Rx_FIFO_int(31 downto 24) <= receive_Data_int;
Data_To_Rx_FIFO_int(23 downto 0) <= Data_To_Rx_FIFO_int(23 downto 0);
end if;
else -- adjustment for complete word
--Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(23 downto 0) & receive_Data_int;
Data_To_Rx_FIFO_int <= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 8);
end if;
end if;
end if;
end process STORE_RX_DATA_SPI_CLK_P;
end generate STORE_RX_DATA_24_BIT_ADDR;
----------------------------
Data_To_Rx_FIFO <= Data_To_Rx_FIFO_int;
---------------------------------------
end generate NM_MEM_DUAL_MD_GEN;
SP_MEM_DUAL_MD_GEN: if C_SPI_MEMORY = 3 generate
-----
begin
-----
--wb_hpm_done <= '1';
---- Dual mode command = 0x3B - DOFR
--SPI_cmd <= "00111011";
--------------------------------------------------------
DUAL_SPI_CMD_NM_24_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
-----
begin
-----
---------------------------
SPI_cmd <= "10111011"; -- 0xBB - DIOFR
wb_hpm_done <= '1';
---------------------------
Data_Dir <= '0';-- for BB
Data_Mode_1 <= '0';
Data_Mode_0 <= '1';
Data_Phase <= '1';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '1';
Addr_Bit <= '0';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
---------------------------
end generate DUAL_SPI_CMD_NM_24_GEN;
------------------------------------
DUAL_SPI_CMD_NM_32_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
-----
begin
-----
SPI_cmd <= "10111100"; -- 0xBCh - DIOFR_4Byte
end generate DUAL_SPI_CMD_NM_32_GEN;
------------------------------------
NM_EN_32_ADDR_MD_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-----
nm_wr_en_CMD <= "00000110"; -- 0x06 h Write Enable
nm_4byte_addr_en_CMD <= "10110111"; -- 0xB7 h Enable 4 Byte Addressing Mode
----------------------------------------------------
NM_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
nm_wr_en_cntrl_ps <= NM_WR_EN_IDLE;
wr_en_under_process_d1 <= '0';
wr_en_done_reg <= '0';
else
nm_wr_en_cntrl_ps <= nm_wr_en_cntrl_ns;
wr_en_under_process_d1 <= wr_en_under_process;
wr_en_done_reg <= wr_en_done;
end if;
end if;
end process NM_PS_TO_NS_PROCESS;
----------------------------------
--
NM_WR_EN_CNTRL_PROCESS: process(
nm_wr_en_cntrl_ps ,
--SPIXfer_done_int_pulse,
--SPIXfer_done_int ,
Rst_to_spi ,
SR_5_Tx_Empty ,
wr_en_done_reg
) is
-----
begin
-----
--load_wr_en_cmd <= '0';
--load_wr_sr_cmd <= '0';
--load_wr_sr_d0 <= '0';
--load_wr_sr_d1 <= '0';
load_wr_en <= '0';
wr_en_done <= '0';
wr_en_under_process <= '0';
case nm_wr_en_cntrl_ps is
when NM_WR_EN_IDLE => --load_wr_en_cmd <= '1';
load_wr_en <= '1';
wr_en_under_process <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN;
when NM_WR_EN => if (SR_5_Tx_Empty = '1')then
--wr_en_done <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN_DONE;
else
--wr_en_under_process <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN;
end if;
wr_en_done <= SR_5_Tx_Empty;
wr_en_under_process <= not SR_5_Tx_Empty;
when NM_WR_EN_DONE => if (Rst_to_spi = '1') then
nm_wr_en_cntrl_ns <= NM_WR_EN_IDLE;
else
nm_wr_en_cntrl_ns <= NM_WR_EN_DONE;
end if;
wr_en_done <= wr_en_done_reg;
end case;
end process NM_WR_EN_CNTRL_PROCESS;
----------------------------------------------------
NM_4_BYTE_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
nm_sm_4_byte_addr_ps <= NM_32_BIT_IDLE;
--four_byte_addr_under_process_d1 <= '0';
hpm_under_process_d1 <= '0';
wr_en_done_d1 <= '0';
wr_en_done_d2 <= '0';
wb_hpm_done_reg <= '0';
else
nm_sm_4_byte_addr_ps <= nm_sm_4_byte_addr_ns;
hpm_under_process_d1 <= hpm_under_process;
--four_byte_en_done_reg <= four_byte_en_done;
wr_en_done_d1 <= wr_en_done_reg; -- wr_en_done;
wr_en_done_d2 <= wr_en_done_d1;
wb_hpm_done_reg <= wb_hpm_done;
end if;
end if;
end process NM_4_BYTE_PS_TO_NS_PROCESS;
----------------------------------
--
NM_4_BYTE_ADDR_EN_PROCESS: process(
nm_sm_4_byte_addr_ps ,
Rst_to_spi ,
SR_5_Tx_Empty ,
wr_en_done_d2 ,
wb_hpm_done_reg
) is
-----
begin
-----
-- load_4_byte_addr_en <= '0';
load_wr_hpm <= '0';
wb_hpm_done <= '0';
hpm_under_process <= '0';
four_byte_en_done <= '0';
four_byte_en_under_process <= '0';
case nm_sm_4_byte_addr_ps is
when NM_32_BIT_IDLE => if (wr_en_done_d2 = '1') then
--load_wr_hpm <= '1';
--hpm_under_process <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN;
else
nm_sm_4_byte_addr_ns <= NM_32_BIT_IDLE;
end if;
load_wr_hpm <= wr_en_done_d2;
hpm_under_process <= wr_en_done_d2;
when NM_32_BIT_EN => if (SR_5_Tx_Empty = '1') then
-- wb_hpm_done <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN_DONE;
else
-- hpm_under_process <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN;
end if;
wb_hpm_done <= SR_5_Tx_Empty;
hpm_under_process <= not(SR_5_Tx_Empty);
when NM_32_BIT_EN_DONE => if(Rst_to_spi = '1')then
nm_sm_4_byte_addr_ns <= NM_32_BIT_IDLE;
else
-- if (SR_5_Tx_Empty = '1')then
-- --four_byte_en_done <= '1';
-- wb_hpm_done <= '1';
-- else
-- -- four_byte_en_under_process <= '1';
-- hpm_under_process <= '1';
-- end if;
-- four_byte_en_done <= four_byte_en_done_reg;
-- wb_hpm_done <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN_DONE;
end if;
wb_hpm_done <= wb_hpm_done_reg;
end case;
end process NM_4_BYTE_ADDR_EN_PROCESS;
--------------------------------------
DRIVE_CONTROL_SIG_P: process(EXT_SPI_CLK) is -- wb_hpm_done, wr_en_done_reg) is
variable temp: std_logic_vector(1 downto 0);
begin
temp := wb_hpm_done & wr_en_done_reg;
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
case wb_hpm_done is
-- when "00"|"01" => -- write enable is under process
when '0' => -- write enable and/or Enable 4 byte addressing is under process
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- when "01" => -- Enable 4 byte addressing is under process
-- Data_Dir <= '0';
-- Data_Mode_1 <= '0';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '0';
-- --------------------
-- Quad_Phase <= '0';-- permanent '0'
-- --------------------
-- Addr_Mode_1 <= '0';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '0';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
-- when "10" => -- write enable is done and enable 4 byte addressing is also done
when '1' => -- write enable and enable 4 byte addressing is also done
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '1';
Data_Phase <= '1';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '1';
Addr_Bit <= '1';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage off
when others =>
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage on
end case;
end if;
end process DRIVE_CONTROL_SIG_P;
end generate NM_EN_32_ADDR_MD_GEN;
--------------------------------------
-- -- WB 0011 000 100 0
-- -- NM 0011 000 100 0<-cmd error
-- -- NM 0011 010 100 0<-cmd error -- For 0xbbh DIOFR
-- 0011 011 100 0
-- Data_Dir <= '0';<-- for BB -- '0';<-- for BC
-- Data_Mode_1 <= '0'; -- '0';
-- Data_Mode_0 <= '1'; -- '1';
-- Data_Phase <= '1'; -- '1';
-- -------------------- --
-- Quad_Phase <= '0';-- permanent '0' -- '0';
-- -------------------- --
-- Addr_Mode_1 <= '0'; -- '0';
-- Addr_Mode_0 <= '1'; -- '1';
-- Addr_Bit <= '0'; -- '1';
-- Addr_Phase <= '1'; -- '1';
-- -------------------- --
-- CMD_Mode_1 <= '0'; -- '0'
-- CMD_Mode_0 <= '0'; -- '0';
---------------------------------------------------------------------
-- RECEIVE_DATA_STROBE_PROCESS : Strobe data from shift register to receive
-- data register
--------------------------------
-- For a SCK ratio of 2 the Done needs to be delayed by an extra cycle
-- due to the serial input being captured on the falling edge of the PLB
-- clock. this is purely required for dealing with the real SPI slave memories.
--RECEIVE_DATA_NM_GEN: if C_SPI_MEMORY = 2 and C_SPI_MODE /=0 generate
--begin
-----
RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
receive_Data_int <= (others => '0');
elsif(SPIXfer_done_int_pulse = '1') then
receive_Data_int <= rx_shft_reg_mode_0011;
elsif(SPIXfer_done_int_pulse_d1 = '1') then
receive_Data_int <= receive_Data_int
((C_NUM_TRANSFER_BITS-3) downto 0) &
IO1_I & -- MISO_I - MSB first
IO0_I ; -- MOSI_I
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS;
--end generate RECEIVE_DATA_NM_GEN;
-----------------------------------------------------------------------------
CMD_ADDR_NM_24_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-- CMD_ADDR_CNTR_P: in each SPI transaction, the firs 4 transactions are of
-- CMD, A0, A1, A2. Total 4 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 4 bytes are transferred.
-- below counter is for that purpose only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or (store_last_b4_wrap = '1') then
cmd_addr_cntr <= "000";--(others => '1');
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1')then
cmd_addr_cntr <= "000";
cmd_addr_sent <= store_last_b4_wrap;
elsif(SPIXfer_done_int_pulse_d2 = '1')then
if(cmd_addr_cntr = "100")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
----------------------------
end generate CMD_ADDR_NM_24_BIT_GEN;
------------------------------------
CMD_ADDR_NM_32_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-- CMD_ADDR_CNTR_P: in each SPI transaction, the firs 5 transactions are of
-- CMD, A0, A1, A2, A3. Total 5 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 5 bytes are transferred.
-- below counter is for that purpose only. This is 4 byte addessing mode of NM memory.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or (store_last_b4_wrap = '1') then
cmd_addr_cntr <= "000";--(others => '1');
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1')then
cmd_addr_cntr <= "000";
cmd_addr_sent <= store_last_b4_wrap;
elsif(SPIXfer_done_int_pulse_d2 = '1')then
if(cmd_addr_cntr = "110")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
----------------------------
end generate CMD_ADDR_NM_32_BIT_GEN;
------------------------------------
TWO_BIT_CNTR_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') or (store_last_b4_wrap = '1') then
hw_wd_cntr <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1')then
hw_wd_cntr <= hw_wd_cntr + "01";
end if;
end if;
end process TWO_BIT_CNTR_P;
----------------------------------------------
STORE_RX_DATA_32_BIT_ADDR: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-----
STORE_RX_DATA_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') then
Data_To_Rx_FIFO_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d3 = '1') and (cmd_addr_sent = '1') then
if(one_byte_xfer_to_spi_clk = '1') then
case spi_addr_i(1 downto 0) is
when "00" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 8) &
receive_Data_int;
when "01" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 16)&
receive_Data_int &
Data_To_Rx_FIFO_int(7 downto 0);
when "10" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 24)&
receive_Data_int &
Data_To_Rx_FIFO_int(15 downto 0);
when "11" =>
Data_To_Rx_FIFO_int <= receive_Data_int &
Data_To_Rx_FIFO_int(23 downto 0);
when others => null;
end case;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '0') then -- adjustment for half word
if(spi_addr_i(1) = '0') then
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);-- & receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= receive_Data_int & Data_To_Rx_FIFO_int(15 downto 8);-- & receive_Data_int;
else
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);-- & receive_Data_int;
Data_To_Rx_FIFO_int(31 downto 16)<= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 24);-- & receive_Data_int;
end if;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '1') then -- adjustment for half word
if(hw_wd_cntr = "00") then -- fill in D0
Data_To_Rx_FIFO_int(31 downto 8) <= Data_To_Rx_FIFO_int(31 downto 8);
Data_To_Rx_FIFO_int(7 downto 0) <= receive_Data_int;
elsif(hw_wd_cntr = "01")then -- fill in D1
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);
Data_To_Rx_FIFO_int(15 downto 8) <= receive_Data_int;
Data_To_Rx_FIFO_int(7 downto 0) <= Data_To_Rx_FIFO_int(7 downto 0);
elsif(hw_wd_cntr = "10")then -- fill in D2
Data_To_Rx_FIFO_int(31 downto 24) <= Data_To_Rx_FIFO_int(31 downto 24);
Data_To_Rx_FIFO_int(23 downto 16) <= receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);
else
Data_To_Rx_FIFO_int(31 downto 24) <= receive_Data_int;
Data_To_Rx_FIFO_int(23 downto 0) <= Data_To_Rx_FIFO_int(23 downto 0);
end if;
else -- adjustment for complete word
--Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(23 downto 0) & receive_Data_int;
Data_To_Rx_FIFO_int <= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 8);
end if;
end if;
end if;
end process STORE_RX_DATA_SPI_CLK_P;
end generate STORE_RX_DATA_32_BIT_ADDR;
STORE_RX_DATA_24_BIT_ADDR: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-----
STORE_RX_DATA_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') then
Data_To_Rx_FIFO_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1') then
if(one_byte_xfer_to_spi_clk = '1') then
case spi_addr_i(1 downto 0) is
when "00" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 8) &
receive_Data_int;
when "01" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 16)&
receive_Data_int &
Data_To_Rx_FIFO_int(7 downto 0);
when "10" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 24)&
receive_Data_int &
Data_To_Rx_FIFO_int(15 downto 0);
when "11" =>
Data_To_Rx_FIFO_int <= receive_Data_int &
Data_To_Rx_FIFO_int(23 downto 0);
when others => null;
end case;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '0') then -- adjustment for half word
if(spi_addr_i(1) = '0') then
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);-- & receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= receive_Data_int & Data_To_Rx_FIFO_int(15 downto 8);-- & receive_Data_int;
else
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);-- & receive_Data_int;
Data_To_Rx_FIFO_int(31 downto 16)<= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 24);-- & receive_Data_int;
end if;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '1') then -- adjustment for half word
if(hw_wd_cntr = "00") then -- fill in D0
Data_To_Rx_FIFO_int(31 downto 8) <= Data_To_Rx_FIFO_int(31 downto 8);
Data_To_Rx_FIFO_int(7 downto 0) <= receive_Data_int;
elsif(hw_wd_cntr = "01")then -- fill in D1
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);
Data_To_Rx_FIFO_int(15 downto 8) <= receive_Data_int;
Data_To_Rx_FIFO_int(7 downto 0) <= Data_To_Rx_FIFO_int(7 downto 0);
elsif(hw_wd_cntr = "10")then -- fill in D2
Data_To_Rx_FIFO_int(31 downto 24) <= Data_To_Rx_FIFO_int(31 downto 24);
Data_To_Rx_FIFO_int(23 downto 16) <= receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);
else
Data_To_Rx_FIFO_int(31 downto 24) <= receive_Data_int;
Data_To_Rx_FIFO_int(23 downto 0) <= Data_To_Rx_FIFO_int(23 downto 0);
end if;
else -- adjustment for complete word
--Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(23 downto 0) & receive_Data_int;
Data_To_Rx_FIFO_int <= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 8);
end if;
end if;
end if;
end process STORE_RX_DATA_SPI_CLK_P;
end generate STORE_RX_DATA_24_BIT_ADDR;
----------------------------
Data_To_Rx_FIFO <= Data_To_Rx_FIFO_int;
---------------------------------------
end generate SP_MEM_DUAL_MD_GEN;
end generate DUAL_MODE_CONTROL_GEN;
QUAD_MODE_CONTROL_GEN: if C_SPI_MODE = 2 generate
-----
begin
-----
-- WB 0011 0101 00 0<-cmd error
-- NM 001100101 00 0<-cmd error
WB_MEM_QUAD_MD_GEN:if C_SPI_MEMORY = 1 generate
signal cmd_addr_cntr : std_logic_vector(2 downto 0);
signal hw_wd_cntr : std_logic_vector(1 downto 0);
-----
begin
-----
wb_wr_hpm_CMD <= "10100011"; -- 0xA3 h HPM mode
--
----------------------------------------------------
WB_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
wb_cntrl_ps <= WB_IDLE;
hpm_under_process_d1 <= '0';
else
wb_cntrl_ps <= wb_cntrl_ns;
hpm_under_process_d1 <= hpm_under_process;
end if;
end if;
end process WB_PS_TO_NS_PROCESS;
----------------------------------
--
WB_DUAL_CNTRL_PROCESS: process(
wb_cntrl_ps ,
SPIXfer_done_int_pulse,
SPIXfer_done_int ,
Rst_to_spi ,
SR_5_Tx_Empty
) is
-----
begin
-----
load_wr_en_cmd <= '0';
load_wr_sr_cmd <= '0';
load_wr_sr_d0 <= '0';
load_wr_sr_d1 <= '0';
load_wr_hpm <= '0';
wb_hpm_done <= '0';
hpm_under_process <= '0';
case wb_cntrl_ps is
when WB_IDLE => load_wr_hpm <= '1';
hpm_under_process <= '1';
wb_cntrl_ns <= WB_WR_HPM;
when WB_WR_HPM => if (SR_5_Tx_Empty = '1')then
wb_hpm_done <= '1';
wb_cntrl_ns <= WB_DONE;
else
hpm_under_process <= '1';
wb_cntrl_ns <= WB_WR_HPM;
end if;
when WB_DONE => if (Rst_to_spi = '1') then
wb_cntrl_ns <= WB_IDLE;
else
wb_hpm_done <= '1';
wb_cntrl_ns <= WB_DONE;
end if;
end case;
end process WB_DUAL_CNTRL_PROCESS;
---- Quad mode command = 0x6B - QOFR Read
-- SPI_cmd <= "01101011";
-- 0101 000 100 0
---- Quad mode command = 0xEB - QIOFR Read
SPI_cmd <= "11101011";
-- 0101 100 100 0 -- QUAD_IO_FAST_RD
Data_Dir <= '0';
Data_Mode_1 <= '1';
Data_Mode_0 <= '0';
Data_Phase <= '1';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '1';-- '0' for QOFR and '1' for QIOFR
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
---------------------------------------------------------------------
--RECEIVE_DATA_WB_GEN: if C_SPI_MEMORY = 1 and C_SPI_MODE /=0 generate
--begin
-----
RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
receive_Data_int <= (others => '0');
elsif(SPIXfer_done_int_pulse = '1') then
receive_Data_int <= rx_shft_reg_mode_0011;
elsif(SPIXfer_done_int_pulse_d1 = '1') and (cmd_addr_sent = '1')then
receive_Data_int <= receive_Data_int
((C_NUM_TRANSFER_BITS-5) downto 0) &
IO3_I & -- MSB first
IO2_I &
IO1_I &
IO0_I ;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS;
--end generate RECEIVE_DATA_WB_GEN;
---------------------------------------------------------------------
-- CMD_ADDR_CNTR_P: in each SPI transaction, the firs 4 transactions are of
-- CMD, A0, A1, A2. Total 4 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 4 bytes are transferred.
-- below counter is for that purpose only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or (load_axi_data_to_spi_clk = '1') then
cmd_addr_cntr <= "000";--(others => '1');
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1')then
cmd_addr_cntr <= "000";
cmd_addr_sent <= store_last_b4_wrap;
elsif(SPIXfer_done_int_pulse_d2 = '1')then
if(cmd_addr_cntr = "110")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
----------------------------
TWO_BIT_CNTR_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') or (start_after_wrap = '1') then
hw_wd_cntr <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1')then
hw_wd_cntr <= hw_wd_cntr + "01";
end if;
end if;
end process TWO_BIT_CNTR_P;
STORE_RX_DATA_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') then
Data_To_Rx_FIFO_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1') then
if(one_byte_xfer_to_spi_clk = '1') then
case spi_addr_i(1 downto 0) is
when "00" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 8) &
receive_Data_int;
when "01" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 16)&
receive_Data_int &
Data_To_Rx_FIFO_int(7 downto 0);
when "10" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 24)&
receive_Data_int &
Data_To_Rx_FIFO_int(15 downto 0);
when "11" =>
Data_To_Rx_FIFO_int <= receive_Data_int &
Data_To_Rx_FIFO_int(23 downto 0);
when others => null;
end case;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '0') then -- adjustment for half word
if(spi_addr_i(1) = '0') then
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);-- & receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= receive_Data_int & Data_To_Rx_FIFO_int(15 downto 8);-- & receive_Data_int;
else
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);-- & receive_Data_int;
Data_To_Rx_FIFO_int(31 downto 16)<= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 24);-- & receive_Data_int;
end if;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '1') then -- adjustment for half word
if(hw_wd_cntr = "00") then -- fill in D0
Data_To_Rx_FIFO_int(31 downto 8) <= Data_To_Rx_FIFO_int(31 downto 8);
Data_To_Rx_FIFO_int(7 downto 0) <= receive_Data_int;
elsif(hw_wd_cntr = "01")then -- fill in D1
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);
Data_To_Rx_FIFO_int(15 downto 8) <= receive_Data_int;
Data_To_Rx_FIFO_int(7 downto 0) <= Data_To_Rx_FIFO_int(7 downto 0);
elsif(hw_wd_cntr = "10")then -- fill in D2
Data_To_Rx_FIFO_int(31 downto 24) <= Data_To_Rx_FIFO_int(31 downto 24);
Data_To_Rx_FIFO_int(23 downto 16) <= receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);
else
Data_To_Rx_FIFO_int(31 downto 24) <= receive_Data_int;
Data_To_Rx_FIFO_int(23 downto 0) <= Data_To_Rx_FIFO_int(23 downto 0);
end if;
else -- adjustment for complete word
--Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(23 downto 0) & receive_Data_int;
Data_To_Rx_FIFO_int <= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 8);
end if;
end if;
end if;
end process STORE_RX_DATA_SPI_CLK_P;
----------------------------
Data_To_Rx_FIFO <= Data_To_Rx_FIFO_int;
---------------------------------------
----------------------------
end generate WB_MEM_QUAD_MD_GEN;
-- NM 0011 0 0101 00 0<-cmd error
NM_MEM_QUAD_MD_GEN:if C_SPI_MEMORY = 2 generate
signal cmd_addr_cntr : std_logic_vector(3 downto 0);
signal hw_wd_cntr : std_logic_vector(1 downto 0);
begin
-----
--wb_hpm_done <= '1';
---- Quad mode command = 0x6B - QOFR Read - 0xEBh
--SPI_cmd <= -- "01101011";
-- 0101 1 000100 0
QUAD_SPI_CMD_NM_24_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
SPI_cmd <= "11101011"; -- QIOFR
-- 0101 1 100100 0
wb_hpm_done <= '1';
DRIVE_CONTROL_SIG_P: process(EXT_SPI_CLK, wb_hpm_done, wr_en_done_reg) is -- wb_hpm_done, wr_en_done_reg) is
variable temp: std_logic_vector(1 downto 0);
begin
temp := wb_hpm_done & wr_en_done_reg;
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
case wb_hpm_done is
-- when "00"|"01" => -- write enable is under process
when '0' => -- write enable and/or Enable 4 byte addressing is under process
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- when "01" => -- Enable 4 byte addressing is under process
-- Data_Dir <= '0';
-- Data_Mode_1 <= '0';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '0';
-- --------------------
-- Quad_Phase <= '0';-- permanent '0'
-- --------------------
-- Addr_Mode_1 <= '0';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '0';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
-- when "10" => -- write enable is done and enable 4 byte addressing is also done
when '1' => -- write enable and enable 4 byte addressing is also done
Data_Dir <= '0';
Data_Mode_1 <= '1';
Data_Mode_0 <= '0';
Data_Phase <= '1';
--------------------
Quad_Phase <= '1';-- permanent '0'
--------------------
Addr_Mode_1 <= '1';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage off
when others =>
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage on
end case;
end if;
end process DRIVE_CONTROL_SIG_P;
--------------------------------
end generate QUAD_SPI_CMD_NM_24_GEN;
QUAD_SPI_CMD_NM_32_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
SPI_cmd <= "11101100"; -- QIOFR_4Byte 0xECh
-- 0101 1 100100 0
end generate QUAD_SPI_CMD_NM_32_GEN;
NM_EN_32_ADDR_MD_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-----
nm_wr_en_CMD <= "00000110"; -- 0x06 h Write Enable
nm_4byte_addr_en_CMD <= "10110111"; -- 0xB7 h Enable 4 Byte Addressing Mode
----------------------------------------------------
NM_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
nm_wr_en_cntrl_ps <= NM_WR_EN_IDLE;
wr_en_under_process_d1 <= '0';
wr_en_done_reg <= '0';
else
nm_wr_en_cntrl_ps <= nm_wr_en_cntrl_ns;
wr_en_under_process_d1 <= wr_en_under_process;
wr_en_done_reg <= wr_en_done;
end if;
end if;
end process NM_PS_TO_NS_PROCESS;
----------------------------------
--
NM_WR_EN_CNTRL_PROCESS: process(
nm_wr_en_cntrl_ps ,
--SPIXfer_done_int_pulse,
--SPIXfer_done_int ,
Rst_to_spi ,
SR_5_Tx_Empty ,
wr_en_done_reg
) is
-----
begin
-----
--load_wr_en_cmd <= '0';
--load_wr_sr_cmd <= '0';
--load_wr_sr_d0 <= '0';
--load_wr_sr_d1 <= '0';
load_wr_en <= '0';
wr_en_done <= '0';
wr_en_under_process <= '0';
case nm_wr_en_cntrl_ps is
when NM_WR_EN_IDLE => --load_wr_en_cmd <= '1';
load_wr_en <= '1';
wr_en_under_process <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN;
when NM_WR_EN => if (SR_5_Tx_Empty = '1')then
--wr_en_done <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN_DONE;
else
--wr_en_under_process <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN;
end if;
wr_en_done <= SR_5_Tx_Empty;
wr_en_under_process <= not SR_5_Tx_Empty;
when NM_WR_EN_DONE => if (Rst_to_spi = '1') then
nm_wr_en_cntrl_ns <= NM_WR_EN_IDLE;
else
nm_wr_en_cntrl_ns <= NM_WR_EN_DONE;
end if;
wr_en_done <= wr_en_done_reg;
end case;
end process NM_WR_EN_CNTRL_PROCESS;
----------------------------------------------------
NM_4_BYTE_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
nm_sm_4_byte_addr_ps <= NM_32_BIT_IDLE;
--four_byte_addr_under_process_d1 <= '0';
hpm_under_process_d1 <= '0';
wr_en_done_d1 <= '0';
wr_en_done_d2 <= '0';
wb_hpm_done_reg <= '0';
else
nm_sm_4_byte_addr_ps <= nm_sm_4_byte_addr_ns;
hpm_under_process_d1 <= hpm_under_process;
--four_byte_en_done_reg <= four_byte_en_done;
wr_en_done_d1 <= wr_en_done_reg; -- wr_en_done;
wr_en_done_d2 <= wr_en_done_d1;
wb_hpm_done_reg <= wb_hpm_done;
end if;
end if;
end process NM_4_BYTE_PS_TO_NS_PROCESS;
----------------------------------
--
NM_4_BYTE_ADDR_EN_PROCESS: process(
nm_sm_4_byte_addr_ps ,
Rst_to_spi ,
SR_5_Tx_Empty ,
wr_en_done_d2 ,
wb_hpm_done_reg
) is
-----
begin
-----
-- load_4_byte_addr_en <= '0';
load_wr_hpm <= '0';
wb_hpm_done <= '0';
hpm_under_process <= '0';
four_byte_en_done <= '0';
four_byte_en_under_process <= '0';
case nm_sm_4_byte_addr_ps is
when NM_32_BIT_IDLE => if (wr_en_done_d2 = '1') then
--load_wr_hpm <= '1';
--hpm_under_process <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN;
else
nm_sm_4_byte_addr_ns <= NM_32_BIT_IDLE;
end if;
load_wr_hpm <= wr_en_done_d2;
hpm_under_process <= wr_en_done_d2;
when NM_32_BIT_EN => if (SR_5_Tx_Empty = '1') then
-- wb_hpm_done <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN_DONE;
else
-- hpm_under_process <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN;
end if;
wb_hpm_done <= SR_5_Tx_Empty;
hpm_under_process <= not(SR_5_Tx_Empty);
when NM_32_BIT_EN_DONE => if(Rst_to_spi = '1')then
nm_sm_4_byte_addr_ns <= NM_32_BIT_IDLE;
else
-- if (SR_5_Tx_Empty = '1')then
-- --four_byte_en_done <= '1';
-- wb_hpm_done <= '1';
-- else
-- -- four_byte_en_under_process <= '1';
-- hpm_under_process <= '1';
-- end if;
-- four_byte_en_done <= four_byte_en_done_reg;
-- wb_hpm_done <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN_DONE;
end if;
wb_hpm_done <= wb_hpm_done_reg;
end case;
end process NM_4_BYTE_ADDR_EN_PROCESS;
--------------------------------------
DRIVE_CONTROL_SIG_P: process(EXT_SPI_CLK, wb_hpm_done, wr_en_done_reg) is -- wb_hpm_done, wr_en_done_reg) is
variable temp: std_logic_vector(1 downto 0);
begin
temp := wb_hpm_done & wr_en_done_reg;
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
case wb_hpm_done is
-- when "00"|"01" => -- write enable is under process
when '0' => -- write enable and/or Enable 4 byte addressing is under process
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- when "01" => -- Enable 4 byte addressing is under process
-- Data_Dir <= '0';
-- Data_Mode_1 <= '0';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '0';
-- --------------------
-- Quad_Phase <= '0';-- permanent '0'
-- --------------------
-- Addr_Mode_1 <= '0';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '0';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
-- when "10" => -- write enable is done and enable 4 byte addressing is also done
when '1' => -- write enable and enable 4 byte addressing is also done
Data_Dir <= '0';
Data_Mode_1 <= '1';
Data_Mode_0 <= '0';
Data_Phase <= '1';
--------------------
Quad_Phase <= '1';-- permanent '0'
--------------------
Addr_Mode_1 <= '1';
Addr_Mode_0 <= '0';
Addr_Bit <= '1';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage off
when others =>
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage on
end case;
end if;
end process DRIVE_CONTROL_SIG_P;
--------------------------------
end generate NM_EN_32_ADDR_MD_GEN;
-------------------------------------
-- Data_Dir <= '0';
-- Data_Mode_1 <= '1';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '1';
-- --------------------
-- Quad_Phase <= '1';-- for NM this is 0
-- --------------------
-- Addr_Mode_1 <= '1';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '1';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
---------------------------------------------------------------------
-- RECEIVE_DATA_STROBE_PROCESS : Strobe data from shift register to receive
-- data register
--------------------------------
-- For a SCK ratio of 2 the Done needs to be delayed by an extra cycle
-- due to the serial input being captured on the falling edge of the PLB
-- clock. this is purely required for dealing with the real SPI slave memories.
--RECEIVE_DATA_NM_GEN: if C_SPI_MEMORY = 2 and C_SPI_MODE /=0 generate
--begin
-----
RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
receive_Data_int <= (others => '0');
elsif(SPIXfer_done_int_pulse = '1') then
receive_Data_int <= rx_shft_reg_mode_0011;
elsif(SPIXfer_done_int_pulse_d1 = '1') then
receive_Data_int <= receive_Data_int
((C_NUM_TRANSFER_BITS-5) downto 0) &
IO3_I & -- MSB first
IO2_I &
IO1_I &
IO0_I ;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS;
--end generate RECEIVE_DATA_NM_GEN;
-----------------------------------------------------------------------------
CMD_ADDR_NM_24_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-- CMD_ADDR_CNTR_P: in each SPI transaction, the firs 5 transactions are of
-- CMD, A0, A1, A2. Total 4 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 4 bytes are transferred.
-- below counter is for that purpose only. This is for 24 bit addressing of NM memories only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or
(load_axi_data_to_spi_clk = '1') or
(store_last_b4_wrap = '1') then
cmd_addr_cntr <= "0000";--(others => '1');
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1')then
cmd_addr_cntr <= "0000";
cmd_addr_sent <= store_last_b4_wrap;
elsif(SPIXfer_done_int_pulse_d2 = '1')then
if(cmd_addr_cntr = "1000")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "0001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
end generate CMD_ADDR_NM_24_BIT_GEN;
------------------------------------
CMD_ADDR_NM_32_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-- CMD_ADDR_CNTR_P: in each SPI transaction, the firs 6 transactions are of
-- CMD, A0, A1, A2, A3. Total 5 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 5 bytes are transferred.
-- below counter is for that purpose only. This is for 32 bit addressing of NM memories only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or
(load_axi_data_to_spi_clk = '1') or
(store_last_b4_wrap = '1') then
cmd_addr_cntr <= "0000";--(others => '1');
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1')then
cmd_addr_cntr <= "0000";
cmd_addr_sent <= store_last_b4_wrap;
elsif(SPIXfer_done_int_pulse_d2 = '1')then
if(cmd_addr_cntr = "1001")then -- note the differene in counter value
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "0001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
end generate CMD_ADDR_NM_32_BIT_GEN;
------------------------------------
TWO_BIT_CNTR_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') or (start_after_wrap = '1') then
hw_wd_cntr <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1')then
hw_wd_cntr <= hw_wd_cntr + "01";
end if;
end if;
end process TWO_BIT_CNTR_P;
---------------------------
STORE_RX_DATA_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') then
Data_To_Rx_FIFO_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1') then
if(one_byte_xfer_to_spi_clk = '1') then
case spi_addr_i(1 downto 0) is
when "00" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 8) &
receive_Data_int;
when "01" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 16)&
receive_Data_int &
Data_To_Rx_FIFO_int(7 downto 0);
when "10" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 24)&
receive_Data_int &
Data_To_Rx_FIFO_int(15 downto 0);
when "11" =>
Data_To_Rx_FIFO_int <= receive_Data_int &
Data_To_Rx_FIFO_int(23 downto 0);
when others => null;
end case;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '0') then -- adjustment for half word
if(spi_addr_i(1) = '0') then
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);-- & receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= receive_Data_int & Data_To_Rx_FIFO_int(15 downto 8);-- & receive_Data_int;
else
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);-- & receive_Data_int;
Data_To_Rx_FIFO_int(31 downto 16)<= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 24);-- & receive_Data_int;
end if;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '1') then -- adjustment for half word
if(hw_wd_cntr = "00") then -- fill in D0
Data_To_Rx_FIFO_int(31 downto 8) <= Data_To_Rx_FIFO_int(31 downto 8);
Data_To_Rx_FIFO_int(7 downto 0) <= receive_Data_int;
elsif(hw_wd_cntr = "01")then -- fill in D1
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);
Data_To_Rx_FIFO_int(15 downto 8) <= receive_Data_int;
Data_To_Rx_FIFO_int(7 downto 0) <= Data_To_Rx_FIFO_int(7 downto 0);
elsif(hw_wd_cntr = "10")then -- fill in D2
Data_To_Rx_FIFO_int(31 downto 24) <= Data_To_Rx_FIFO_int(31 downto 24);
Data_To_Rx_FIFO_int(23 downto 16) <= receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);
else
Data_To_Rx_FIFO_int(31 downto 24) <= receive_Data_int;
Data_To_Rx_FIFO_int(23 downto 0) <= Data_To_Rx_FIFO_int(23 downto 0);
end if;
else -- adjustment for complete word
--Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(23 downto 0) & receive_Data_int;
Data_To_Rx_FIFO_int <= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 8);
end if;
end if;
end if;
end process STORE_RX_DATA_SPI_CLK_P;
----------------------------
Data_To_Rx_FIFO <= Data_To_Rx_FIFO_int;
---------------------------------------
--------------------------------
end generate NM_MEM_QUAD_MD_GEN;
--------------------------------
SP_MEM_QUAD_MD_GEN:if C_SPI_MEMORY = 3 generate
signal cmd_addr_cntr : std_logic_vector(3 downto 0);
signal hw_wd_cntr : std_logic_vector(1 downto 0);
begin
-----
--wb_hpm_done <= '1';
---- Quad mode command = 0x6B - QOFR Read - 0xEBh
--SPI_cmd <= -- "01101011";
-- 0101 1 000100 0
QUAD_SPI_CMD_NM_24_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
SPI_cmd <= "11101011"; -- QIOFR
-- 0101 1 100100 0
wb_hpm_done <= '1';
DRIVE_CONTROL_SIG_P: process(EXT_SPI_CLK) is -- wb_hpm_done, wr_en_done_reg) is
variable temp: std_logic_vector(1 downto 0);
begin
temp := wb_hpm_done & wr_en_done_reg;
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
case wb_hpm_done is
-- when "00"|"01" => -- write enable is under process
when '0' => -- write enable and/or Enable 4 byte addressing is under process
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- when "01" => -- Enable 4 byte addressing is under process
-- Data_Dir <= '0';
-- Data_Mode_1 <= '0';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '0';
-- --------------------
-- Quad_Phase <= '0';-- permanent '0'
-- --------------------
-- Addr_Mode_1 <= '0';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '0';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
-- when "10" => -- write enable is done and enable 4 byte addressing is also done
when '1' => -- write enable and enable 4 byte addressing is also done
Data_Dir <= '0';
Data_Mode_1 <= '1';
Data_Mode_0 <= '0';
Data_Phase <= '1';
--------------------
Quad_Phase <= '1';-- permanent '0'
--------------------
Addr_Mode_1 <= '1';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage off
when others =>
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage on
end case;
end if;
end process DRIVE_CONTROL_SIG_P;
--------------------------------
end generate QUAD_SPI_CMD_NM_24_GEN;
QUAD_SPI_CMD_NM_32_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
SPI_cmd <= "11101100"; -- QIOFR_4Byte 0xECh
-- 0101 1 100100 0
end generate QUAD_SPI_CMD_NM_32_GEN;
NM_EN_32_ADDR_MD_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-----
nm_wr_en_CMD <= "00000110"; -- 0x06 h Write Enable
nm_4byte_addr_en_CMD <= "10110111"; -- 0xB7 h Enable 4 Byte Addressing Mode
----------------------------------------------------
NM_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
nm_wr_en_cntrl_ps <= NM_WR_EN_IDLE;
wr_en_under_process_d1 <= '0';
wr_en_done_reg <= '0';
else
nm_wr_en_cntrl_ps <= nm_wr_en_cntrl_ns;
wr_en_under_process_d1 <= wr_en_under_process;
wr_en_done_reg <= wr_en_done;
end if;
end if;
end process NM_PS_TO_NS_PROCESS;
----------------------------------
--
NM_WR_EN_CNTRL_PROCESS: process(
nm_wr_en_cntrl_ps ,
--SPIXfer_done_int_pulse,
--SPIXfer_done_int ,
Rst_to_spi ,
SR_5_Tx_Empty ,
wr_en_done_reg
) is
-----
begin
-----
--load_wr_en_cmd <= '0';
--load_wr_sr_cmd <= '0';
--load_wr_sr_d0 <= '0';
--load_wr_sr_d1 <= '0';
load_wr_en <= '0';
wr_en_done <= '0';
wr_en_under_process <= '0';
case nm_wr_en_cntrl_ps is
when NM_WR_EN_IDLE => --load_wr_en_cmd <= '1';
load_wr_en <= '1';
wr_en_under_process <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN;
when NM_WR_EN => if (SR_5_Tx_Empty = '1')then
--wr_en_done <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN_DONE;
else
--wr_en_under_process <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN;
end if;
wr_en_done <= SR_5_Tx_Empty;
wr_en_under_process <= not SR_5_Tx_Empty;
when NM_WR_EN_DONE => if (Rst_to_spi = '1') then
nm_wr_en_cntrl_ns <= NM_WR_EN_IDLE;
else
nm_wr_en_cntrl_ns <= NM_WR_EN_DONE;
end if;
wr_en_done <= wr_en_done_reg;
end case;
end process NM_WR_EN_CNTRL_PROCESS;
----------------------------------------------------
NM_4_BYTE_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
nm_sm_4_byte_addr_ps <= NM_32_BIT_IDLE;
--four_byte_addr_under_process_d1 <= '0';
hpm_under_process_d1 <= '0';
wr_en_done_d1 <= '0';
wr_en_done_d2 <= '0';
wb_hpm_done_reg <= '0';
else
nm_sm_4_byte_addr_ps <= nm_sm_4_byte_addr_ns;
hpm_under_process_d1 <= hpm_under_process;
--four_byte_en_done_reg <= four_byte_en_done;
wr_en_done_d1 <= wr_en_done_reg; -- wr_en_done;
wr_en_done_d2 <= wr_en_done_d1;
wb_hpm_done_reg <= wb_hpm_done;
end if;
end if;
end process NM_4_BYTE_PS_TO_NS_PROCESS;
----------------------------------
--
NM_4_BYTE_ADDR_EN_PROCESS: process(
nm_sm_4_byte_addr_ps ,
Rst_to_spi ,
SR_5_Tx_Empty ,
wr_en_done_d2 ,
wb_hpm_done_reg
) is
-----
begin
-----
-- load_4_byte_addr_en <= '0';
load_wr_hpm <= '0';
wb_hpm_done <= '0';
hpm_under_process <= '0';
four_byte_en_done <= '0';
four_byte_en_under_process <= '0';
case nm_sm_4_byte_addr_ps is
when NM_32_BIT_IDLE => if (wr_en_done_d2 = '1') then
--load_wr_hpm <= '1';
--hpm_under_process <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN;
else
nm_sm_4_byte_addr_ns <= NM_32_BIT_IDLE;
end if;
load_wr_hpm <= wr_en_done_d2;
hpm_under_process <= wr_en_done_d2;
when NM_32_BIT_EN => if (SR_5_Tx_Empty = '1') then
-- wb_hpm_done <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN_DONE;
else
-- hpm_under_process <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN;
end if;
wb_hpm_done <= SR_5_Tx_Empty;
hpm_under_process <= not(SR_5_Tx_Empty);
when NM_32_BIT_EN_DONE => if(Rst_to_spi = '1')then
nm_sm_4_byte_addr_ns <= NM_32_BIT_IDLE;
else
-- if (SR_5_Tx_Empty = '1')then
-- --four_byte_en_done <= '1';
-- wb_hpm_done <= '1';
-- else
-- -- four_byte_en_under_process <= '1';
-- hpm_under_process <= '1';
-- end if;
-- four_byte_en_done <= four_byte_en_done_reg;
-- wb_hpm_done <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN_DONE;
end if;
wb_hpm_done <= wb_hpm_done_reg;
end case;
end process NM_4_BYTE_ADDR_EN_PROCESS;
--------------------------------------
DRIVE_CONTROL_SIG_P: process(EXT_SPI_CLK) is -- wb_hpm_done, wr_en_done_reg) is
variable temp: std_logic_vector(1 downto 0);
begin
temp := wb_hpm_done & wr_en_done_reg;
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
case wb_hpm_done is
-- when "00"|"01" => -- write enable is under process
when '0' => -- write enable and/or Enable 4 byte addressing is under process
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- when "01" => -- Enable 4 byte addressing is under process
-- Data_Dir <= '0';
-- Data_Mode_1 <= '0';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '0';
-- --------------------
-- Quad_Phase <= '0';-- permanent '0'
-- --------------------
-- Addr_Mode_1 <= '0';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '0';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
-- when "10" => -- write enable is done and enable 4 byte addressing is also done
when '1' => -- write enable and enable 4 byte addressing is also done
Data_Dir <= '0';
Data_Mode_1 <= '1';
Data_Mode_0 <= '0';
Data_Phase <= '1';
--------------------
Quad_Phase <= '1';-- permanent '0'
--------------------
Addr_Mode_1 <= '1';
Addr_Mode_0 <= '0';
Addr_Bit <= '1';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage off
when others =>
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage on
end case;
end if;
end process DRIVE_CONTROL_SIG_P;
--------------------------------
end generate NM_EN_32_ADDR_MD_GEN;
-------------------------------------
-- Data_Dir <= '0';
-- Data_Mode_1 <= '1';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '1';
-- --------------------
-- Quad_Phase <= '1';-- for NM this is 0
-- --------------------
-- Addr_Mode_1 <= '1';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '1';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
---------------------------------------------------------------------
-- RECEIVE_DATA_STROBE_PROCESS : Strobe data from shift register to receive
-- data register
--------------------------------
-- For a SCK ratio of 2 the Done needs to be delayed by an extra cycle
-- due to the serial input being captured on the falling edge of the PLB
-- clock. this is purely required for dealing with the real SPI slave memories.
--RECEIVE_DATA_NM_GEN: if C_SPI_MEMORY = 2 and C_SPI_MODE /=0 generate
--begin
-----
RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
receive_Data_int <= (others => '0');
elsif(SPIXfer_done_int_pulse = '1') then
receive_Data_int <= rx_shft_reg_mode_0011;
elsif(SPIXfer_done_int_pulse_d1 = '1') then
receive_Data_int <= receive_Data_int
((C_NUM_TRANSFER_BITS-5) downto 0) &
IO3_I & -- MSB first
IO2_I &
IO1_I &
IO0_I ;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS;
--end generate RECEIVE_DATA_NM_GEN;
-----------------------------------------------------------------------------
CMD_ADDR_NM_24_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-- CMD_ADDR_CNTR_P: in each SPI transaction, the firs 5 transactions are of
-- CMD, A0, A1, A2. Total 4 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 4 bytes are transferred.
-- below counter is for that purpose only. This is for 24 bit addressing of NM memories only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or
(load_axi_data_to_spi_clk = '1') or
(store_last_b4_wrap = '1') then
cmd_addr_cntr <= "0000";--(others => '1');
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1')then
cmd_addr_cntr <= "0000";
cmd_addr_sent <= store_last_b4_wrap;
elsif(SPIXfer_done_int_pulse_d2 = '1')then
if(cmd_addr_cntr = "0110")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "0001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
end generate CMD_ADDR_NM_24_BIT_GEN;
------------------------------------
CMD_ADDR_NM_32_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-- CMD_ADDR_CNTR_P: in each SPI transaction, the firs 6 transactions are of
-- CMD, A0, A1, A2, A3. Total 5 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 5 bytes are transferred.
-- below counter is for that purpose only. This is for 32 bit addressing of NM memories only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or
(load_axi_data_to_spi_clk = '1') or
(store_last_b4_wrap = '1') then
cmd_addr_cntr <= "0000";--(others => '1');
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1')then
cmd_addr_cntr <= "0000";
cmd_addr_sent <= store_last_b4_wrap;
elsif(SPIXfer_done_int_pulse_d2 = '1')then
if(cmd_addr_cntr = "0111")then -- note the differene in counter value
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "0001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
end generate CMD_ADDR_NM_32_BIT_GEN;
------------------------------------
TWO_BIT_CNTR_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') or (start_after_wrap = '1') then
hw_wd_cntr <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1')then
hw_wd_cntr <= hw_wd_cntr + "01";
end if;
end if;
end process TWO_BIT_CNTR_P;
---------------------------
STORE_RX_DATA_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') then
Data_To_Rx_FIFO_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1') then
if(one_byte_xfer_to_spi_clk = '1') then
case spi_addr_i(1 downto 0) is
when "00" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 8) &
receive_Data_int;
when "01" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 16)&
receive_Data_int &
Data_To_Rx_FIFO_int(7 downto 0);
when "10" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 24)&
receive_Data_int &
Data_To_Rx_FIFO_int(15 downto 0);
when "11" =>
Data_To_Rx_FIFO_int <= receive_Data_int &
Data_To_Rx_FIFO_int(23 downto 0);
when others => null;
end case;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '0') then -- adjustment for half word
if(spi_addr_i(1) = '0') then
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);-- & receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= receive_Data_int & Data_To_Rx_FIFO_int(15 downto 8);-- & receive_Data_int;
else
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);-- & receive_Data_int;
Data_To_Rx_FIFO_int(31 downto 16)<= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 24);-- & receive_Data_int;
end if;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '1') then -- adjustment for half word
if(hw_wd_cntr = "00") then -- fill in D0
Data_To_Rx_FIFO_int(31 downto 8) <= Data_To_Rx_FIFO_int(31 downto 8);
Data_To_Rx_FIFO_int(7 downto 0) <= receive_Data_int;
elsif(hw_wd_cntr = "01")then -- fill in D1
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);
Data_To_Rx_FIFO_int(15 downto 8) <= receive_Data_int;
Data_To_Rx_FIFO_int(7 downto 0) <= Data_To_Rx_FIFO_int(7 downto 0);
elsif(hw_wd_cntr = "10")then -- fill in D2
Data_To_Rx_FIFO_int(31 downto 24) <= Data_To_Rx_FIFO_int(31 downto 24);
Data_To_Rx_FIFO_int(23 downto 16) <= receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);
else
Data_To_Rx_FIFO_int(31 downto 24) <= receive_Data_int;
Data_To_Rx_FIFO_int(23 downto 0) <= Data_To_Rx_FIFO_int(23 downto 0);
end if;
else -- adjustment for complete word
--Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(23 downto 0) & receive_Data_int;
Data_To_Rx_FIFO_int <= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 8);
end if;
end if;
end if;
end process STORE_RX_DATA_SPI_CLK_P;
----------------------------
Data_To_Rx_FIFO <= Data_To_Rx_FIFO_int;
---------------------------------------
--------------------------------
end generate SP_MEM_QUAD_MD_GEN;
end generate QUAD_MODE_CONTROL_GEN;
WRAP_DELAY_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) or (load_axi_data_to_spi_clk = '1') then
wrap_around_d1 <= '0';
wrap_around_d2 <= '0';
wrap_around_d3 <= '0';
--wrap_around_d4 <= '0';
else
wrap_around_d1 <= wrap_around;
wrap_around_d2 <= wrap_around_d1;
wrap_around_d3 <= wrap_around_d2;
--wrap_around_d4 <= wrap_around_d3;
end if;
end if;
end process WRAP_DELAY_P;
wrap_ack <= (not wrap_around_d2) and wrap_around_d1;
wrap_ack_1 <= (not wrap_around_d3) and wrap_around_d2;
start_after_wrap <= wrap_around_d2 and (not wrap_around_d1) and not SR_5_Tx_Empty;
store_last_b4_wrap <= wrap_around_d3 and (not wrap_around_d2);
--xsfer_start_aftr_wrap <= wrap_around_d4 and (not wrap_around_d3);
DELAY_START_AFTR_WRAP:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
start_after_wrap_d1 <= '0';
else
start_after_wrap_d1 <= start_after_wrap;
end if;
end if;
end process DELAY_START_AFTR_WRAP;
----------------------------------
TRANSFER_START_24_BIT_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-----
TRANSFER_START_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
transfer_start <= '0';
elsif(wrap_around = '1') then -- and (actual_SPIXfer_done_int = '1')then
transfer_start <= '0';
elsif(hpm_under_process_d1 = '1' and wb_hpm_done = '1')-- or
--(wr_en_under_process_d1 = '1' and wr_en_done = '1')
then
transfer_start <= '0';
elsif (load_axi_data_to_spi_clk = '1')
or (start_after_wrap_d1 = '1')
or (load_wr_hpm = '1')
--or (load_wr_en = '1')
then
transfer_start <= '1';
elsif(SR_5_Tx_Empty_int = '1') then
transfer_start <= '0';
end if;
end if;
end process TRANSFER_START_P;
end generate TRANSFER_START_24_BIT_ADDR_GEN;
TRANSFER_START_32_BIT_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-----
TRANSFER_START_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
transfer_start <= '0';
elsif(wrap_around = '1') then -- and (actual_SPIXfer_done_int = '1')then
transfer_start <= '0';
elsif(hpm_under_process_d1 = '1' and wb_hpm_done = '1') or
(wr_en_under_process_d1 = '1' and wr_en_done = '1')then
transfer_start <= '0';
elsif(load_axi_data_to_spi_clk = '1') or
(start_after_wrap_d1 = '1') or
(load_wr_hpm = '1') or
(load_wr_en = '1') then
transfer_start <= '1';
elsif(SR_5_Tx_Empty_int = '1') then
transfer_start <= '0';
end if;
end if;
end process TRANSFER_START_P;
end generate TRANSFER_START_32_BIT_ADDR_GEN;
-------------------------------------------------------------------------------
-- TRANSFER_START_1CLK_PROCESS : Delay transfer start by 1 clock cycle
--------------------------------
TRANSFER_START_1CLK_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) or (load_axi_data_to_spi_clk = '1') then
transfer_start_d1 <= '0';
transfer_start_d2 <= '0';
transfer_start_d3 <= '0';
else
transfer_start_d1 <= transfer_start;
transfer_start_d2 <= transfer_start_d1;
transfer_start_d3 <= transfer_start_d2;
end if;
end if;
end process TRANSFER_START_1CLK_PROCESS;
transfer_start_pulse <= --transfer_start and (not transfer_start_d1);
--transfer_start_d2 and (not transfer_start_d3);
transfer_start and (not(transfer_start_d1));
-------------------------------------------------------------------------------
-- TRANSFER_DONE_1CLK_PROCESS : Delay SPI transfer done signal by 1 clock cycle
-------------------------------
TRANSFER_DONE_1CLK_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) or (load_axi_data_to_spi_clk = '1') then
SPIXfer_done_int_d1 <= '0';
else
SPIXfer_done_int_d1 <= SPIXfer_done_int;
end if;
end if;
end process TRANSFER_DONE_1CLK_PROCESS;
--
-- transfer done pulse generating logic
SPIXfer_done_int_pulse <= SPIXfer_done_int and (not(SPIXfer_done_int_d1));
-------------------------------------------------------------------------------
-- TRANSFER_DONE_PULSE_DLY_PROCESS : Delay SPI transfer done pulse by 1 and 2
-- clock cycles
------------------------------------
-- Delay the Done pulse by a further cycle. This is used as the output Rx
-- data strobe when C_SCK_RATIO = 2
TRANSFER_DONE_PULSE_DLY_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) or (load_axi_data_to_spi_clk = '1') then
SPIXfer_done_int_pulse_d1 <= '0';
SPIXfer_done_int_pulse_d2 <= '0';
SPIXfer_done_int_pulse_d3 <= '0';
else
SPIXfer_done_int_pulse_d1 <= SPIXfer_done_int_pulse;
SPIXfer_done_int_pulse_d2 <= SPIXfer_done_int_pulse_d1;
SPIXfer_done_int_pulse_d3 <= SPIXfer_done_int_pulse_d2;
end if;
end if;
end process TRANSFER_DONE_PULSE_DLY_PROCESS;
--------------------------------------------
-------------------------------------------------------------------------------
-- RX_DATA_GEN1: Only for C_SCK_RATIO = 2 mode.
----------------
-- RX_DATA_SCK_RATIO_2_GEN1 : if C_SCK_RATIO = 2 generate
-----
-- begin
-----
-------------------------------------------------------------------------------
-- TRANSFER_DONE_PROCESS : Generate SPI transfer done signal. This will stop the SPI clock.
--------------------------
TRANSFER_DONE_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
SPIXfer_done_int <= '0';
elsif(transfer_start_pulse = '1') then
SPIXfer_done_int <= '0';
else
if(mode_1 = '1' and mode_0 = '0')then
SPIXfer_done_int <= Count(1) and
not(Count(0));
elsif(mode_1 = '0' and mode_0 = '1')then
SPIXfer_done_int <= not(Count(0)) and
Count(2) and
Count(1);
else
SPIXfer_done_int <= --Count(COUNT_WIDTH);
Count(COUNT_WIDTH-1) and
Count(COUNT_WIDTH-2) and
Count(COUNT_WIDTH-3) and
not Count(COUNT_WIDTH-4);
end if;
end if;
end if;
end process TRANSFER_DONE_PROCESS;
-- -- RECEIVE_DATA_STROBE_PROCESS : Strobe data from shift register to receive
-- -- data register
-- --------------------------------
-- -- For a SCK ratio of 2 the Done needs to be delayed by an extra cycle
-- -- due to the serial input being captured on the falling edge of the PLB
-- -- clock. this is purely required for dealing with the real SPI slave memories.
-- RECEIVE_DATA_NM_GEN: if C_SPI_MEMORY = 2 and C_SPI_MODE /=0 generate
-- begin
-- -----
-- RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-- -----
-- begin
-- -----
-- if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
-- if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
-- receive_Data_int <= (others => '0');
-- elsif(SPIXfer_done_int_pulse_d1 = '1') then -- and (cmd_addr_sent = '1')then
-- receive_Data_int <= rx_shft_reg_mode_0011;
-- end if;
-- end if;
-- end process RECEIVE_DATA_STROBE_PROCESS;
-- end generate RECEIVE_DATA_NM_GEN;
-- -----------------------------------------------------------------------------
-- -----------------------------------------------------------------------------
-- RECEIVE_DATA_WB_GEN: if C_SPI_MEMORY = 1 and C_SPI_MODE /=0 generate
-- begin
-- -----
-- RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-- -----
-- begin
-- -----
-- if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
-- if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
-- receive_Data_int <= (others => '0');
-- elsif(SPIXfer_done_int_pulse_d1 = '1') and (cmd_addr_sent = '1')then
-- receive_Data_int <= rx_shft_reg_mode_0011;
-- end if;
-- end if;
-- end process RECEIVE_DATA_STROBE_PROCESS;
-- end generate RECEIVE_DATA_WB_GEN;
-----------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- RATIO_OF_2_GENERATE : Logic to be used when C_SCK_RATIO is equal to 2
------------------------
RATIO_OF_2_GENERATE: if(C_SCK_RATIO = 2) generate
--------------------
---------------attribute IOB : string;
---------------attribute IOB of QSPI_SCK_T : label is "true";
begin
-----
-------------------------------------------------------------------------------
-- SCK_CYCLE_COUNT_PROCESS : Counts number of trigger pulses provided. Used for
-- controlling the number of bits to be transfered
-- based on generic C_NUM_TRANSFER_BITS
----------------------------
RATIO_2_SCK_CYCLE_COUNT_PROCESS: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) or (transfer_start = '0') or (store_last_b4_wrap = '1') then -- (wrap_ack_1 = '1')then
Count <= (others => '0');
elsif(SPIXfer_done_int = '1')then
Count <= (others => '0');
elsif((Count(COUNT_WIDTH) = '0') and
((CPOL_to_spi_clk and CPHA_to_spi_clk) = '0')) then
Count <= Count + 1;
elsif(transfer_start_d2 = '1') and (Count(COUNT_WIDTH) = '0') then
Count <= Count + 1;
end if;
end if;
end process RATIO_2_SCK_CYCLE_COUNT_PROCESS;
------------------------------------
SCK_SET_RESET_32_BIT_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-------------------------------------------------------------------------------
-- SCK_SET_GEN_PROCESS : Generate SET control for SCK_O_reg
------------------------
SCK_SET_GEN_PROCESS: process(CPOL_to_spi_clk,
CPHA_to_spi_clk,
SPIXfer_done_int,
transfer_start_pulse,--,
load_axi_data_to_spi_clk,
wrap_ack_1,
load_wr_hpm,
load_wr_en
) is
-----
begin
-----
if(SPIXfer_done_int = '1')or(load_axi_data_to_spi_clk = '1') or (load_wr_hpm = '1') or (load_wr_en = '1')then
Sync_Set <= (CPOL_to_spi_clk xor CPHA_to_spi_clk);
else
Sync_Set <= '0';
end if;
end process SCK_SET_GEN_PROCESS;
-------------------------------------------------------------------------------
-- SCK_RESET_GEN_PROCESS : Generate SET control for SCK_O_reg
--------------------------
SCK_RESET_GEN_PROCESS: process(CPOL_to_spi_clk,
CPHA_to_spi_clk,
transfer_start_pulse,
SPIXfer_done_int,
load_axi_data_to_spi_clk,
load_wr_hpm,
load_wr_en
)is
-----
begin
-----
if(SPIXfer_done_int = '1')or(load_axi_data_to_spi_clk = '1')or(load_wr_hpm = '1') or (load_wr_en = '1') then
Sync_Reset <= not(CPOL_to_spi_clk xor CPHA_to_spi_clk);
else
Sync_Reset <= '0';
end if;
end process SCK_RESET_GEN_PROCESS;
end generate SCK_SET_RESET_32_BIT_ADDR_GEN;
-------------------------------------------
SCK_SET_RESET_24_BIT_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-------------------------------------------------------------------------------
-- SCK_SET_GEN_PROCESS : Generate SET control for SCK_O_reg
------------------------
SCK_SET_GEN_PROCESS: process(CPOL_to_spi_clk,
CPHA_to_spi_clk,
SPIXfer_done_int,
transfer_start_pulse,--,
load_axi_data_to_spi_clk,
wrap_ack_1,
load_wr_hpm--,
--load_wr_en
) is
-----
begin
-----
if(SPIXfer_done_int = '1')or(load_axi_data_to_spi_clk = '1') or (load_wr_hpm = '1')
--or (load_wr_en = '1')
then
Sync_Set <= (CPOL_to_spi_clk xor CPHA_to_spi_clk);
else
Sync_Set <= '0';
end if;
end process SCK_SET_GEN_PROCESS;
-------------------------------------------------------------------------------
-- SCK_RESET_GEN_PROCESS : Generate SET control for SCK_O_reg
--------------------------
SCK_RESET_GEN_PROCESS: process(CPOL_to_spi_clk,
CPHA_to_spi_clk,
transfer_start_pulse,
SPIXfer_done_int,
load_axi_data_to_spi_clk,
load_wr_hpm--,
--load_wr_en
)is
-----
begin
-----
if(SPIXfer_done_int = '1')or(load_axi_data_to_spi_clk = '1')or(load_wr_hpm = '1')
--or (load_wr_en = '1')
then
Sync_Reset <= not(CPOL_to_spi_clk xor CPHA_to_spi_clk);
else
Sync_Reset <= '0';
end if;
end process SCK_RESET_GEN_PROCESS;
end generate SCK_SET_RESET_24_BIT_ADDR_GEN;
-------------------------------------------
-------------------------------------------------------------------------------
-- SCK_SET_RESET_PROCESS : Sync set/reset toggle flip flop controlled by
-- transfer_start signal
--------------------------
RATIO_2_SCK_SET_RESET_PROCESS: process(EXT_SPI_CLK)
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if((Rst_to_spi = RESET_ACTIVE) or (Sync_Reset = '1') or
(new_tr = '0') or (wrap_ack_1 = '1')) then
sck_o_int <= '0';
elsif(Sync_Set = '1') then
sck_o_int <= '1';
elsif (transfer_start = '1') then
sck_o_int <= (not sck_o_int);
end if;
end if;
end process RATIO_2_SCK_SET_RESET_PROCESS;
----------------------------------
-- DELAY_CLK: Delay the internal clock for a cycle to generate internal enable
-- -- signal for data register.
-------------
RATIO_2_DELAY_CLK: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if (Rst_to_spi = RESET_ACTIVE)then
sck_d1 <= '0';
sck_d2 <= '0';
else
sck_d1 <= sck_o_int;
sck_d2 <= sck_d1;
end if;
end if;
end process RATIO_2_DELAY_CLK;
------------------------------------
-- Rising egde pulse
sck_rising_edge <= sck_d2 and (not sck_d1);
-- CAPT_RX_FE_MODE_00_11: The below logic is to capture data for SPI mode of
--------------------------- 00 and 11.
-- Generate a falling edge pulse from the serial clock. Use this to
-- capture the incoming serial data into a shift register.
RATIO_2_CAPT_RX_FE_MODE_00_11 : process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then -- SPIXfer_done_int_pulse_d2
if (Rst_to_spi = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
rx_shft_reg_mode_0011 <= (others => '0');
elsif((sck_d2='0') and --(sck_rising_edge = '1') and
(Data_Dir='0') -- data direction = 0 is read mode
)then
-------
if(mode_1 = '0' and mode_0 = '0')then -- for Standard transfer
rx_shft_reg_mode_0011 <= rx_shft_reg_mode_0011
(1 to (C_NUM_TRANSFER_BITS-1)) &
IO1_I ; --MISO_I;
elsif(mode_1 = '0' and mode_0 = '1')then -- for Dual transfer
rx_shft_reg_mode_0011 <= rx_shft_reg_mode_0011
(2 to (C_NUM_TRANSFER_BITS-1)) &
IO1_I & -- MISO_I - MSB first
IO0_I ; -- MOSI_I
elsif(mode_1 = '1' and mode_0 = '0')then -- for Quad transfer
rx_shft_reg_mode_0011 <= rx_shft_reg_mode_0011
(4 to (C_NUM_TRANSFER_BITS-1)) &
IO3_I & -- MSB first
IO2_I &
IO1_I &
IO0_I ;
end if;
-------
else
rx_shft_reg_mode_0011<= rx_shft_reg_mode_0011;
end if;
end if;
end process RATIO_2_CAPT_RX_FE_MODE_00_11;
----------------------------------
QSPI_NM_MEM_DATA_CAP_GEN: if (C_SPI_MODE = 0 and (C_SPI_MEMORY = 0 or
C_SPI_MEMORY = 2))
or
(
( C_SPI_MODE = 1
or
C_SPI_MODE = 2
)
and
C_SPI_MEMORY = 2
)generate
--------------------------------------
begin
-----
-------------------------------------------------------------------------------
-- CAPTURE_AND_SHIFT_PROCESS : This logic essentially controls the entire
-- capture and shift operation for serial data in
------------------------------ master SPI mode only
RATIO_2_CAPTURE_AND_SHIFT_PROCESS: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
Shift_Reg(0 to C_NUM_TRANSFER_BITS -1) <= (others => '0');
Serial_Dout_0 <= '0';-- default values of the IO0_O
Serial_Dout_1 <= '0';
Serial_Dout_2 <= '0';
Serial_Dout_3 <= '0';
elsif(transfer_start = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1') then --
--if(Load_tx_data_to_shift_reg_int = '1') then
Shift_Reg <= Transmit_Data;
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Transmit_Data(0);
Serial_Dout_3 <= Quad_Phase;--pr_state_cmd_ph and Quad_Phase;-- this is to make the DQ3 bit 1 in quad command transfer mode.
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Transmit_Data(0); -- msb to IO1_O
Serial_Dout_0 <= Transmit_Data(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Transmit_Data(0); -- msb to IO3_O
Serial_Dout_2 <= Transmit_Data(1);
Serial_Dout_1 <= Transmit_Data(2);
Serial_Dout_0 <= Transmit_Data(3);
end if;
elsif(
(Count(0) = '0')
)then -- Shift Data on even
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Shift_Reg(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Shift_Reg(0); -- msb to IO1_O
Serial_Dout_0 <= Shift_Reg(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Shift_Reg(0); -- msb to IO3_O
Serial_Dout_2 <= Shift_Reg(1);
Serial_Dout_1 <= Shift_Reg(2);
Serial_Dout_0 <= Shift_Reg(3);
end if;
elsif(
(Count(0) = '1') --and
) then -- Capture Data on odd
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Shift_Reg <= Shift_Reg
(1 to C_NUM_TRANSFER_BITS -1) &
IO1_I ;-- MISO_I;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Shift_Reg <= Shift_Reg
(2 to C_NUM_TRANSFER_BITS -1) &
IO1_I &
IO0_I ;
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Shift_Reg <= Shift_Reg
(4 to C_NUM_TRANSFER_BITS -1) &
IO3_I &
IO2_I &
IO1_I &
IO0_I ;
end if;
end if;
end if;
end if;
end process RATIO_2_CAPTURE_AND_SHIFT_PROCESS;
----------------------------------------------
end generate QSPI_NM_MEM_DATA_CAP_GEN;
----------------------------------
QSPI_SP_MEM_DATA_CAP_GEN: if (C_SPI_MODE = 0 and (C_SPI_MEMORY = 0 or
C_SPI_MEMORY = 3))
or
(
( C_SPI_MODE = 1
or
C_SPI_MODE = 2
)
and
C_SPI_MEMORY = 3
)generate
--------------------------------------
begin
-----
-------------------------------------------------------------------------------
-- CAPTURE_AND_SHIFT_PROCESS : This logic essentially controls the entire
-- capture and shift operation for serial data in
------------------------------ master SPI mode only
RATIO_2_CAPTURE_AND_SHIFT_PROCESS: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
Shift_Reg(0 to C_NUM_TRANSFER_BITS -1) <= (others => '0');
Serial_Dout_0 <= '0';-- default values of the IO0_O
Serial_Dout_1 <= '0';
Serial_Dout_2 <= '0';
Serial_Dout_3 <= '0';
elsif(transfer_start = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1') then --
--if(Load_tx_data_to_shift_reg_int = '1') then
Shift_Reg <= Transmit_Data;
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Transmit_Data(0);
Serial_Dout_3 <= Quad_Phase;--pr_state_cmd_ph and Quad_Phase;-- this is to make the DQ3 bit 1 in quad command transfer mode.
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Transmit_Data(0); -- msb to IO1_O
Serial_Dout_0 <= Transmit_Data(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Transmit_Data(0); -- msb to IO3_O
Serial_Dout_2 <= Transmit_Data(1);
Serial_Dout_1 <= Transmit_Data(2);
Serial_Dout_0 <= Transmit_Data(3);
end if;
elsif(
(Count(0) = '0')
)then -- Shift Data on even
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Shift_Reg(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Shift_Reg(0); -- msb to IO1_O
Serial_Dout_0 <= Shift_Reg(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Shift_Reg(0); -- msb to IO3_O
Serial_Dout_2 <= Shift_Reg(1);
Serial_Dout_1 <= Shift_Reg(2);
Serial_Dout_0 <= Shift_Reg(3);
end if;
elsif(
(Count(0) = '1') --and
) then -- Capture Data on odd
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Shift_Reg <= Shift_Reg
(1 to C_NUM_TRANSFER_BITS -1) &
IO1_I ;-- MISO_I;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Shift_Reg <= Shift_Reg
(2 to C_NUM_TRANSFER_BITS -1) &
IO1_I &
IO0_I ;
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Shift_Reg <= Shift_Reg
(4 to C_NUM_TRANSFER_BITS -1) &
IO3_I &
IO2_I &
IO1_I &
IO0_I ;
end if;
end if;
end if;
end if;
end process RATIO_2_CAPTURE_AND_SHIFT_PROCESS;
----------------------------------------------
end generate QSPI_SP_MEM_DATA_CAP_GEN;
----------------------------------
QSPI_WINBOND_MEM_DATA_CAP_GEN: if (
(C_SPI_MODE = 0 and (C_SPI_MEMORY = 0 or
C_SPI_MEMORY = 1))
or
(
( C_SPI_MODE = 1
or
C_SPI_MODE = 2
)
and
C_SPI_MEMORY = 1
)) generate
-----------------------------------------
begin
-----
-------------------------------------------------------------------------------
-- CAPTURE_AND_SHIFT_PROCESS : This logic essentially controls the entire
-- capture and shift operation for serial data in
------------------------------ master SPI mode only
RATIO_2_CAPTURE_AND_SHIFT_PROCESS: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
Shift_Reg(0 to C_NUM_TRANSFER_BITS -1) <= (others => '0');
Serial_Dout_0 <= '0';-- default values of the IO0_O
Serial_Dout_1 <= '0';
Serial_Dout_2 <= '0';
Serial_Dout_3 <= '0';
elsif(transfer_start = '1') then
--if(Load_tx_data_to_shift_reg_int = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1') then --
Shift_Reg <= Transmit_Data;
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Transmit_Data(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;-- this is to make the DQ3 bit 1 in quad command transfer mode.
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Transmit_Data(0); -- msb to IO1_O
Serial_Dout_0 <= Transmit_Data(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Transmit_Data(0); -- msb to IO3_O
Serial_Dout_2 <= Transmit_Data(1);
Serial_Dout_1 <= Transmit_Data(2);
Serial_Dout_0 <= Transmit_Data(3);
end if;
elsif(
(Count(0) = '0') --and
)then -- Shift Data on even
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Shift_Reg(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Shift_Reg(0); -- msb to IO1_O
Serial_Dout_0 <= Shift_Reg(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Shift_Reg(0); -- msb to IO3_O
Serial_Dout_2 <= Shift_Reg(1);
Serial_Dout_1 <= Shift_Reg(2);
Serial_Dout_0 <= Shift_Reg(3);
end if;
elsif(
(Count(0) = '1') --and
) then -- Capture Data on odd
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Shift_Reg <= Shift_Reg
(1 to C_NUM_TRANSFER_BITS -1) &
IO1_I;-- MISO_I;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Shift_Reg <= Shift_Reg
(2 to C_NUM_TRANSFER_BITS -1) &
IO1_I &
IO0_I ;
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Shift_Reg <= Shift_Reg
(4 to C_NUM_TRANSFER_BITS -1) &
IO3_I &
IO2_I &
IO1_I &
IO0_I ;
end if;
end if;
end if;
end if;
end process RATIO_2_CAPTURE_AND_SHIFT_PROCESS;
----------------------------------------------
end generate QSPI_WINBOND_MEM_DATA_CAP_GEN;
------------------------------------------------------
--------------------------------
XIP_STD_DUAL_MODE_WB_MEM_GEN: if (
(C_SPI_MODE = 0 or C_SPI_MODE = 1) and
(
(C_SPI_MEMORY = 1 or C_SPI_MEMORY = 0)
)
)generate
--------------------------------
begin
-----
--------------------------------------------------
PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
qspi_cntrl_ps <= IDLE;
stop_clock_reg <= '0';
else
qspi_cntrl_ps <= qspi_cntrl_ns;
stop_clock_reg <= stop_clock;
end if;
end if;
end process PS_TO_NS_PROCESS;
-----------------------------
pr_state_data_receive <= '1' when qspi_cntrl_ps = DATA_RECEIVE else
'0';
pr_state_non_idle <= '1' when qspi_cntrl_ps /= IDLE else
'0';
pr_state_idle <= '1' when qspi_cntrl_ps = IDLE else
'0';
pr_state_cmd_ph <= '1' when qspi_cntrl_ps = CMD_SEND else
'0';
QSPI_CNTRL_PROCESS: process(
---------------------
new_tr ,
CMD_Mode_1 ,
CMD_Mode_0 ,
---------------------
Addr_Phase ,
Addr_Bit ,
Addr_Mode_1 ,
Addr_Mode_0 ,
---------------------
Data_Phase ,
Data_Dir ,
Data_Mode_1 ,
Data_Mode_0 ,
---------------------
addr_cnt ,
Quad_Phase ,
---------------------
SR_5_Tx_Empty ,
SPIXfer_done_int_pulse,
stop_clock_reg,
---------------------
qspi_cntrl_ps ,
no_slave_selected ,
---------------------
wrap_around ,
transfer_start ,
wrap_ack_1 ,
wb_hpm_done ,
hpm_under_process_d1
)is
-----
begin
-----
mode_1 <= '0';
mode_0 <= '0';
--------------
IO0_T_control <= '1';
IO1_T_control <= '1';
-------------
stop_clock <= '0';
-------------
rst_wrap_around <= '0';
-------------
case qspi_cntrl_ps is
when IDLE => if((SR_5_Tx_Empty = '0') and -- this will be used specially in case of WRAP transactions
(transfer_start = '1')and
(new_tr = '1')
)then
IO0_T_control <= CMD_Mode_0;
IO3_T_control <= not Quad_Phase;--
qspi_cntrl_ns <= CMD_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
stop_clock <= '1';
------------------------------------------------
when CMD_SEND => mode_1 <= CMD_Mode_1;
mode_0 <= CMD_Mode_0;
IO0_T_control <= CMD_Mode_0;
IO1_T_control <= (CMD_Mode_1) or (not CMD_Mode_0);
if(SPIXfer_done_int_pulse = '1')then
if(hpm_under_process_d1 = '1')then
qspi_cntrl_ns <= HPM_DUMMY;
elsif(Addr_Phase='1')then
qspi_cntrl_ns <= ADDR_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
else
qspi_cntrl_ns <= CMD_SEND;
end if;
------------------------------------------------
when HPM_DUMMY => IO0_T_control <= CMD_Mode_0;
IO1_T_control <= (CMD_Mode_1) or (not CMD_Mode_0);
if(SR_5_Tx_Empty='1') then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= HPM_DUMMY;
end if;
------------------------------------------------
when ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);-- (Addr_Mode_1) or(not Addr_Mode_0);
--stop_clock <= not SR_5_Tx_Empty;
if((SR_5_Tx_Empty='1') and
(Data_Phase='0')
) or (wrap_ack_1 = '1') then
if (no_slave_selected = '1') or (wrap_ack_1 = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
if(
(addr_cnt = "011") and -- 24 bit address
(Addr_Bit='0') and (Data_Phase='1')
)then
IO0_T_control <= '1';
IO1_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
end if;
------------------------------------------------
when TEMP_ADDR_SEND =>
mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);-- (Addr_Mode_1) or(not Addr_Mode_0);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= ADDR_SEND;
end if;
when DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
if(SR_5_Tx_Empty='1') or (wrap_ack_1 = '1')then
rst_wrap_around <= '1';
if(no_slave_selected = '1') or
(wrap_around = '1')then
qspi_cntrl_ns <= IDLE;
stop_clock <= wrap_ack_1;
else
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
when TEMP_DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
-- coverage off
when others => qspi_cntrl_ns <= IDLE;
------------------------------------------------
-- coverage on
end case;
-------------------------------
end process QSPI_CNTRL_PROCESS;
-------------------------------
pr_state_addr_ph <= '1' when (qspi_cntrl_ps = ADDR_SEND) else
'0';
QSPI_ADDR_CNTR_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(pr_state_addr_ph = '0') then
addr_cnt <= (others => '0');
elsif(pr_state_addr_ph = '1')then
addr_cnt <= addr_cnt + SPIXfer_done_int_pulse;
end if;
end if;
end process QSPI_ADDR_CNTR_PROCESS;
-----------------------------------
end generate XIP_STD_DUAL_MODE_WB_MEM_GEN;
------------------------------------------
--------------------------------------------------
XIP_STD_DUAL_MODE_NM_MEM_GEN: if ((C_SPI_MODE = 1 or C_SPI_MODE = 0) and
(C_SPI_MEMORY = 2 or C_SPI_MEMORY = 0)
)generate
-------------------
begin
-----
--------------------------------------------------
PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
qspi_cntrl_ps <= IDLE;
stop_clock_reg <= '0';
else
qspi_cntrl_ps <= qspi_cntrl_ns;
stop_clock_reg <= stop_clock;
end if;
end if;
end process PS_TO_NS_PROCESS;
-----------------------------
pr_state_data_receive <= '1' when qspi_cntrl_ps = DATA_RECEIVE else
'0';
pr_state_non_idle <= '1' when qspi_cntrl_ps /= IDLE else
'0';
pr_state_idle <= '1' when qspi_cntrl_ps = IDLE else
'0';
pr_state_cmd_ph <= '1' when qspi_cntrl_ps = CMD_SEND else
'0';
QSPI_CNTRL_PROCESS: process(
---------------------
--CMD_decoded ,
new_tr,
CMD_Mode_1 ,
CMD_Mode_0 ,
--CMD_Error ,
---------------------
Addr_Phase ,
Addr_Bit ,
Addr_Mode_1 ,
Addr_Mode_0 ,
---------------------
Data_Phase ,
Data_Dir ,
Data_Mode_1 ,
Data_Mode_0 ,
---------------------
addr_cnt ,
---------------------
SR_5_Tx_Empty ,SPIXfer_done_int_pulse,
stop_clock_reg,
no_slave_selected ,
---------------------
qspi_cntrl_ps ,
---------------------
wrap_around ,
transfer_start ,
Quad_Phase ,
wrap_ack_1
)is
-----
begin
-----
mode_1 <= '0';
mode_0 <= '0';
--------------
IO0_T_control <= '1';
IO1_T_control <= '1';
--------------
stop_clock <= '0';
--------------
rst_wrap_around <= '0';
--------------
case qspi_cntrl_ps is
when IDLE => if((SR_5_Tx_Empty = '0') and -- this will be used specially in case of WRAP transactions
(transfer_start = '1')and
(new_tr = '1')
)then
IO0_T_control <= CMD_Mode_0;
IO3_T_control <= not Quad_Phase;--
qspi_cntrl_ns <= CMD_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
stop_clock <= '1';
------------------------------------------------
when CMD_SEND => mode_1 <= CMD_Mode_1;
mode_0 <= CMD_Mode_0;
IO0_T_control <= CMD_Mode_1;
--if(SPIXfer_done_int_pulse_d2 = '1')then
if(SPIXfer_done_int_pulse = '1')then
if(Addr_Phase='1')then
qspi_cntrl_ns <= ADDR_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
else
qspi_cntrl_ns <= CMD_SEND;
end if;
------------------------------------------------
when ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0);
--stop_clock <= SR_5_Tx_Empty;
if(((SR_5_Tx_Empty='1') and
(Data_Phase='0')) or (wrap_ack_1 = '1')
)then
if (no_slave_selected = '1') or (wrap_ack_1 = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
if(
(addr_cnt = "011") and -- 24 bit address
(Addr_Bit='0') and (Data_Phase='1')
)then
if((Data_Dir='1'))then
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= Data_Mode_1;
IO1_T_control <= not(Data_Mode_0);
qspi_cntrl_ns <= DATA_SEND; -- o/p
else
IO0_T_control <= '1';
IO1_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
end if;
elsif(
(addr_cnt = "100") and -- 32 bit
(Addr_Bit = '1') and (Data_Phase='1')
) then
--if((Data_Dir='1'))then
-- qspi_cntrl_ns <= DATA_SEND; -- o/p
--else
IO0_T_control <= '1';
IO1_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
--end if;
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
end if;
-- ------------------------------------------------
when TEMP_ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);-- (Addr_Mode_1) or(not Addr_Mode_0);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= ADDR_SEND;
end if;
when DATA_SEND => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= Data_Mode_1;
IO1_T_control <= not(Data_Mode_0);
--stop_clock <= SR_5_Tx_Empty;
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
------------------------------------------------
when TEMP_DATA_SEND =>
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= Data_Mode_1;
IO1_T_control <= not(Data_Mode_0);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_SEND;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_SEND;
end if;
when DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1') or (wrap_ack_1 = '1')then
rst_wrap_around <= wrap_ack_1;
if(no_slave_selected = '1') or (wrap_ack_1 = '1')then
stop_clock <= wrap_ack_1;
qspi_cntrl_ns <= IDLE;
else
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
when TEMP_DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
-- coverage off
when others => qspi_cntrl_ns <= IDLE;
------------------------------------------------
-- coverage on
end case;
-------------------------------
end process QSPI_CNTRL_PROCESS;
-------------------------------
pr_state_addr_ph <= '1' when qspi_cntrl_ps = ADDR_SEND else
'0';
QSPI_ADDR_CNTR_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(pr_state_addr_ph = '0') then
addr_cnt <= (others => '0');
elsif(pr_state_addr_ph = '1')then
addr_cnt <= addr_cnt + SPIXfer_done_int_pulse;
end if;
end if;
end process QSPI_ADDR_CNTR_PROCESS;
-----------------------------------
end generate XIP_STD_DUAL_MODE_NM_MEM_GEN;
--------------------------------
--------------------------------------------------
XIP_STD_DUAL_MODE_SP_MEM_GEN: if ((C_SPI_MODE = 1 or C_SPI_MODE = 0) and
(C_SPI_MEMORY = 3 or C_SPI_MEMORY = 0)
)generate
-------------------
begin
-----
--------------------------------------------------
PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
qspi_cntrl_ps <= IDLE;
stop_clock_reg <= '0';
else
qspi_cntrl_ps <= qspi_cntrl_ns;
stop_clock_reg <= stop_clock;
end if;
end if;
end process PS_TO_NS_PROCESS;
-----------------------------
pr_state_data_receive <= '1' when qspi_cntrl_ps = DATA_RECEIVE else
'0';
pr_state_non_idle <= '1' when qspi_cntrl_ps /= IDLE else
'0';
pr_state_idle <= '1' when qspi_cntrl_ps = IDLE else
'0';
pr_state_cmd_ph <= '1' when qspi_cntrl_ps = CMD_SEND else
'0';
QSPI_CNTRL_PROCESS: process(
---------------------
--CMD_decoded ,
new_tr,
CMD_Mode_1 ,
CMD_Mode_0 ,
--CMD_Error ,
---------------------
Addr_Phase ,
Addr_Bit ,
Addr_Mode_1 ,
Addr_Mode_0 ,
---------------------
Data_Phase ,
Data_Dir ,
Data_Mode_1 ,
Data_Mode_0 ,
---------------------
addr_cnt ,
---------------------
SR_5_Tx_Empty ,SPIXfer_done_int_pulse,
stop_clock_reg,
no_slave_selected ,
---------------------
qspi_cntrl_ps ,
---------------------
wrap_around ,
transfer_start ,
wrap_ack_1
)is
-----
begin
-----
mode_1 <= '0';
mode_0 <= '0';
--------------
IO0_T_control <= '1';
IO1_T_control <= '1';
--------------
stop_clock <= '0';
--------------
rst_wrap_around <= '0';
--------------
case qspi_cntrl_ps is
when IDLE => if((SR_5_Tx_Empty = '0') and -- this will be used specially in case of WRAP transactions
(transfer_start = '1')and
(new_tr = '1')
)then
IO0_T_control <= CMD_Mode_0;
IO3_T_control <= not Quad_Phase;--
qspi_cntrl_ns <= CMD_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
stop_clock <= '1';
------------------------------------------------
when CMD_SEND => mode_1 <= CMD_Mode_1;
mode_0 <= CMD_Mode_0;
IO0_T_control <= CMD_Mode_1;
--if(SPIXfer_done_int_pulse_d2 = '1')then
if(SPIXfer_done_int_pulse = '1')then
if(Addr_Phase='1')then
qspi_cntrl_ns <= ADDR_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
else
qspi_cntrl_ns <= CMD_SEND;
end if;
------------------------------------------------
when ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0);
--stop_clock <= SR_5_Tx_Empty;
if(((SR_5_Tx_Empty='1') and
(Data_Phase='0')) or (wrap_ack_1 = '1')
)then
if (no_slave_selected = '1') or (wrap_ack_1 = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
if(
(addr_cnt = "011") and -- 24 bit address
(Addr_Bit='0') and (Data_Phase='1')
)then
if((Data_Dir='1'))then
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= Data_Mode_1;
IO1_T_control <= not(Data_Mode_0);
qspi_cntrl_ns <= DATA_SEND; -- o/p
else
IO0_T_control <= '1';
IO1_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
end if;
elsif(
(addr_cnt = "100") and -- 32 bit
(Addr_Bit = '1') and (Data_Phase='1')
) then
--if((Data_Dir='1'))then
-- qspi_cntrl_ns <= DATA_SEND; -- o/p
--else
IO0_T_control <= '1';
IO1_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
--end if;
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
end if;
-- ------------------------------------------------
when TEMP_ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);-- (Addr_Mode_1) or(not Addr_Mode_0);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= ADDR_SEND;
end if;
when DATA_SEND => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= Data_Mode_1;
IO1_T_control <= not(Data_Mode_0);
--stop_clock <= SR_5_Tx_Empty;
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
------------------------------------------------
when TEMP_DATA_SEND =>
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= Data_Mode_1;
IO1_T_control <= not(Data_Mode_0);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_SEND;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_SEND;
end if;
when DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1') or (wrap_ack_1 = '1')then
rst_wrap_around <= wrap_ack_1;
if(no_slave_selected = '1') or (wrap_ack_1 = '1')then
stop_clock <= wrap_ack_1;
qspi_cntrl_ns <= IDLE;
else
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
when TEMP_DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
-- coverage off
when others => qspi_cntrl_ns <= IDLE;
------------------------------------------------
-- coverage on
end case;
-------------------------------
end process QSPI_CNTRL_PROCESS;
-------------------------------
pr_state_addr_ph <= '1' when qspi_cntrl_ps = ADDR_SEND else
'0';
QSPI_ADDR_CNTR_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(pr_state_addr_ph = '0') then
addr_cnt <= (others => '0');
elsif(pr_state_addr_ph = '1')then
addr_cnt <= addr_cnt + SPIXfer_done_int_pulse;
end if;
end if;
end process QSPI_ADDR_CNTR_PROCESS;
-----------------------------------
end generate XIP_STD_DUAL_MODE_SP_MEM_GEN;
--------------------------------------------------
XIP_QUAD_MODE_WB_MEM_GEN: if (
C_SPI_MODE = 2 and
C_SPI_MEMORY = 1
)
generate
-------------------
begin
-----
--------------------------------------------------
PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
qspi_cntrl_ps <= IDLE;
stop_clock_reg <= '0';
else
qspi_cntrl_ps <= qspi_cntrl_ns;
stop_clock_reg <= stop_clock;
end if;
end if;
end process PS_TO_NS_PROCESS;
-----------------------------
pr_state_data_receive <= '1' when qspi_cntrl_ps = DATA_RECEIVE else
'0';
pr_state_non_idle <= '1' when qspi_cntrl_ps /= IDLE else
'0';
pr_state_idle <= '1' when qspi_cntrl_ps = IDLE else
'0';
pr_state_cmd_ph <= '1' when qspi_cntrl_ps = CMD_SEND else
'0';
QSPI_CNTRL_PROCESS: process(
---------------------
new_tr,
CMD_Mode_1 ,
CMD_Mode_0 ,
---------------------
Addr_Phase ,
Addr_Bit ,
Addr_Mode_1 ,
Addr_Mode_0 ,
---------------------
Data_Phase ,
Data_Dir ,
Data_Mode_1 ,
Data_Mode_0 ,
---------------------
addr_cnt ,
Quad_Phase ,
---------------------
SR_5_Tx_Empty ,
SPIXfer_done_int_pulse,
stop_clock_reg,
---------------------
qspi_cntrl_ps ,
no_slave_selected ,
---------------------
wrap_around ,
transfer_start ,
wrap_ack_1 ,
wb_hpm_done ,
hpm_under_process_d1
)is
-----
begin
-----
mode_1 <= '0';
mode_0 <= '0';
--------------
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
--------------
stop_clock <= '0';
--------------
rst_wrap_around <= '0';
--------------
case qspi_cntrl_ps is
when IDLE => if(--(CMD_decoded = '1') and
(SR_5_Tx_Empty = '0') and -- this will be used specially in case of WRAP transactions
(transfer_start = '1')and
(new_tr = '1')
--(CMD_Error = '0') -- proceed only when there is no command error
)then
IO0_T_control <= CMD_Mode_0;
IO3_T_control <= not Quad_Phase;--
qspi_cntrl_ns <= CMD_SEND;
else
qspi_cntrl_ns <= IDLE; -- CMD_DECODE;
end if;
stop_clock <= '1';
------------------------------------------------
when CMD_SEND => mode_1 <= CMD_Mode_1;
mode_0 <= CMD_Mode_0;
IO0_T_control <= CMD_Mode_0;
IO3_T_control <= not Quad_Phase;--
--if(SPIXfer_done_int_pulse_d2 = '1')then
if(SPIXfer_done_int_pulse = '1')then
if(hpm_under_process_d1 = '1')then
qspi_cntrl_ns <= HPM_DUMMY;
elsif(Addr_Phase='1')then
qspi_cntrl_ns <= ADDR_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
else
qspi_cntrl_ns <= CMD_SEND;
end if;
------------------------------------------------
when HPM_DUMMY => IO0_T_control <= CMD_Mode_0;
IO1_T_control <= (CMD_Mode_1) or (not CMD_Mode_0);
if(SR_5_Tx_Empty='1') then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= HPM_DUMMY;
end if;
------------------------------------------------
when ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);
IO2_T_control <= (not Addr_Mode_1);
IO3_T_control <= (not Addr_Mode_1);
--stop_clock <= SR_5_Tx_Empty;
if((SR_5_Tx_Empty='1') and
(Data_Phase='0')
)then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
if(
(addr_cnt = "011") and -- 24 bit address
(Addr_Bit='0') and(Data_Phase='1')
)then
if((Data_Dir='1'))then
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0'; -- data output
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);-- active only
IO3_T_control <= not (Data_Mode_1);-- active only
qspi_cntrl_ns <= DATA_SEND; -- o/p
else
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
end if;
-- -- coverage off
-- -- below piece of code is for 32-bit address check, and left for future use
-- elsif(
-- (addr_cnt = "100") and -- 32 bit
-- (Addr_Bit = '1') and (Data_Phase='1')
-- )then
-- if((Data_Dir='1'))then
-- qspi_cntrl_ns <= DATA_SEND; -- o/p
-- else
-- qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
-- end if;
-- -- coverage on
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
end if;
------------------------------------------------
when TEMP_ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);
IO2_T_control <= (not Addr_Mode_1);
IO3_T_control <= (not Addr_Mode_1);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= ADDR_SEND;
end if;
-----------------------------------------------------------------------
when DATA_SEND => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0'; -- data output active only in Dual mode
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);-- active only in quad mode
IO3_T_control <= not (Data_Mode_1);-- active only in quad mode
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1')then
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
qspi_cntrl_ns <= DATA_SEND;
end if;
------------------------------------------------
when TEMP_DATA_SEND => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0'; -- data output active only in Dual mode
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);-- active only in quad mode
IO3_T_control <= not (Data_Mode_1);-- active only in quad mode
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_SEND;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_SEND;
end if;
when DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1')or (wrap_ack_1 = '1')then
rst_wrap_around <= wrap_ack_1;
if(no_slave_selected = '1')or (wrap_ack_1 = '1')then
stop_clock <= wrap_ack_1;
qspi_cntrl_ns <= IDLE;
else
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
when TEMP_DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
-- coverage off
when others => qspi_cntrl_ns <= IDLE;
------------------------------------------------
-- coverage on
end case;
-------------------------------
end process QSPI_CNTRL_PROCESS;
-------------------------------
pr_state_addr_ph <= '1' when qspi_cntrl_ps = ADDR_SEND else
'0';
QSPI_ADDR_CNTR_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(pr_state_addr_ph = '0') then
addr_cnt <= (others => '0');
elsif(pr_state_addr_ph = '1')then
--addr_cnt <= addr_cnt + SPIXfer_done_int_pulse_d2;
addr_cnt <= addr_cnt + SPIXfer_done_int_pulse;
end if;
end if;
end process QSPI_ADDR_CNTR_PROCESS;
-----------------------------------
------------------------------------------
end generate XIP_QUAD_MODE_WB_MEM_GEN;
------------------------------------------
--------------------------------------------------
XIP_QUAD_MODE_NM_MEM_GEN: if C_SPI_MODE = 2 and C_SPI_MEMORY = 2 generate
-------------------
begin
-----
--------------------------------------------------
PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
qspi_cntrl_ps <= IDLE;
stop_clock_reg <= '0';
else
qspi_cntrl_ps <= qspi_cntrl_ns;
stop_clock_reg <= stop_clock;
end if;
end if;
end process PS_TO_NS_PROCESS;
-----------------------------
pr_state_data_receive <= '1' when qspi_cntrl_ps = DATA_RECEIVE else
'0';
pr_state_non_idle <= '1' when qspi_cntrl_ps /= IDLE else
'0';
pr_state_idle <= '1' when qspi_cntrl_ps = IDLE else
'0';
pr_state_cmd_ph <= '1' when qspi_cntrl_ps = CMD_SEND else
'0';
QSPI_CNTRL_PROCESS: process(
---------------------
--CMD_decoded ,
new_tr,
CMD_Mode_1 ,
CMD_Mode_0 ,
--CMD_Error ,
---------------------
Addr_Phase ,
Addr_Bit ,
Addr_Mode_1 ,
Addr_Mode_0 ,
---------------------
Data_Phase ,
Data_Dir ,
Data_Mode_1 ,
Data_Mode_0 ,
---------------------
addr_cnt ,
Quad_Phase ,
---------------------
SR_5_Tx_Empty ,
--SPIXfer_done_int_pulse_d2,
SPIXfer_done_int_pulse,
stop_clock_reg,
no_slave_selected ,
---------------------
qspi_cntrl_ps ,
---------------------
wrap_around ,
transfer_start_d1 ,
transfer_start ,
wrap_ack_1
)is
-----
begin
-----
mode_1 <= '0';
mode_0 <= '0';
--------------
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
-------------
stop_clock <= '0';
-------------
rst_wrap_around <= '0';
-------------
case qspi_cntrl_ps is
when IDLE => if(--(CMD_decoded = '1') and
(SR_5_Tx_Empty = '0') and -- this will be used specially in case of WRAP transactions
(transfer_start = '1')and
(new_tr = '1')
--(CMD_Error = '0') -- proceed only when there is no command error
)then
IO0_T_control <= CMD_Mode_0;
IO3_T_control <= not Quad_Phase;
qspi_cntrl_ns <= CMD_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
stop_clock <= '1';
------------------------------------------------
when CMD_SEND => mode_1 <= CMD_Mode_1;
mode_0 <= CMD_Mode_0;
IO0_T_control <= CMD_Mode_0;
IO3_T_control <= not Quad_Phase;-- this is due to sending '1' on DQ3 line during command phase for Quad instructions only.
--if(SPIXfer_done_int_pulse_d2 = '1')then
if(SPIXfer_done_int_pulse = '1')then
if(Addr_Phase='1')then
qspi_cntrl_ns <= ADDR_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
else
qspi_cntrl_ns <= CMD_SEND;
end if;
------------------------------------------------
when ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);
IO2_T_control <= (not Addr_Mode_1);
IO3_T_control <= (not Addr_Mode_1);
--stop_clock <= SR_5_Tx_Empty;
if((SR_5_Tx_Empty='1') and
(Data_Phase='0')
)then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
if(
(addr_cnt = "011") and -- 24 bit address
(Addr_Bit='0') and
(Data_Phase='1')
)then
if((Data_Dir='1'))then
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0';
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);
IO3_T_control <= not (Data_Mode_1);
qspi_cntrl_ns <= DATA_SEND; -- o/p
else
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
end if;
elsif(
(addr_cnt = "100") and -- 32 bit
(Addr_Bit = '1') and
(Data_Phase='1')
) then
--if((Data_Dir='1'))then
-- qspi_cntrl_ns <= DATA_SEND; -- o/p
--else
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
--end if;
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
end if;
-- ------------------------------------------------
when TEMP_ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);
IO2_T_control <= (not Addr_Mode_1);
IO3_T_control <= (not Addr_Mode_1);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= ADDR_SEND;
end if;
when DATA_SEND => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0';
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);
IO3_T_control <= not (Data_Mode_1);
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1')then
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
qspi_cntrl_ns <= DATA_SEND;
end if;
------------------------------------------------
when TEMP_DATA_SEND=> mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0';
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);
IO3_T_control <= not (Data_Mode_1);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_SEND;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_SEND;
end if;
when DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1') or (wrap_ack_1 = '1')then
rst_wrap_around <= wrap_ack_1;
--if(no_slave_selected = '1') or (wrap_around = '1')then
stop_clock <= wrap_ack_1 or SR_5_Tx_Empty;
qspi_cntrl_ns <= IDLE;
--else
-- stop_clock <= SR_5_Tx_Empty;
-- qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
--end if;
else
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
when TEMP_DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= stop_clock_reg;
--if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
--else
-- stop_clock <= '0';
-- qspi_cntrl_ns <= DATA_RECEIVE;
--end if;
------------------------------------------------
-- coverage off
when others => qspi_cntrl_ns <= IDLE; -- CMD_DECODE;
------------------------------------------------
-- coverage on
end case;
-------------------------------
end process QSPI_CNTRL_PROCESS;
-------------------------------
pr_state_addr_ph <= '1' when qspi_cntrl_ps = ADDR_SEND else
'0';
QSPI_ADDR_CNTR_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(pr_state_addr_ph = '0') then
addr_cnt <= (others => '0');
elsif(pr_state_addr_ph = '1')then
--addr_cnt <= addr_cnt + SPIXfer_done_int_pulse_d2;
addr_cnt <= addr_cnt + SPIXfer_done_int_pulse;
end if;
end if;
end process QSPI_ADDR_CNTR_PROCESS;
-----------------------------------
end generate XIP_QUAD_MODE_NM_MEM_GEN;
---------------------------------------
XIP_QUAD_MODE_SP_MEM_GEN: if C_SPI_MODE = 2 and C_SPI_MEMORY = 3 generate
-------------------
begin
-----
--------------------------------------------------
PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
qspi_cntrl_ps <= IDLE;
stop_clock_reg <= '0';
else
qspi_cntrl_ps <= qspi_cntrl_ns;
stop_clock_reg <= stop_clock;
end if;
end if;
end process PS_TO_NS_PROCESS;
-----------------------------
pr_state_data_receive <= '1' when qspi_cntrl_ps = DATA_RECEIVE else
'0';
pr_state_non_idle <= '1' when qspi_cntrl_ps /= IDLE else
'0';
pr_state_idle <= '1' when qspi_cntrl_ps = IDLE else
'0';
pr_state_cmd_ph <= '1' when qspi_cntrl_ps = CMD_SEND else
'0';
QSPI_CNTRL_PROCESS: process(
---------------------
--CMD_decoded ,
new_tr,
CMD_Mode_1 ,
CMD_Mode_0 ,
--CMD_Error ,
---------------------
Addr_Phase ,
Addr_Bit ,
Addr_Mode_1 ,
Addr_Mode_0 ,
---------------------
Data_Phase ,
Data_Dir ,
Data_Mode_1 ,
Data_Mode_0 ,
---------------------
addr_cnt ,
Quad_Phase ,
---------------------
SR_5_Tx_Empty ,
--SPIXfer_done_int_pulse_d2,
SPIXfer_done_int_pulse,
stop_clock_reg,
no_slave_selected ,
---------------------
qspi_cntrl_ps ,
---------------------
wrap_around ,
transfer_start_d1 ,
transfer_start ,
wrap_ack_1
)is
-----
begin
-----
mode_1 <= '0';
mode_0 <= '0';
--------------
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
-------------
stop_clock <= '0';
-------------
rst_wrap_around <= '0';
-------------
case qspi_cntrl_ps is
when IDLE => if(--(CMD_decoded = '1') and
(SR_5_Tx_Empty = '0') and -- this will be used specially in case of WRAP transactions
(transfer_start = '1')and
(new_tr = '1')
--(CMD_Error = '0') -- proceed only when there is no command error
)then
IO0_T_control <= CMD_Mode_0;
IO3_T_control <= not Quad_Phase;
qspi_cntrl_ns <= CMD_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
stop_clock <= '1';
------------------------------------------------
when CMD_SEND => mode_1 <= CMD_Mode_1;
mode_0 <= CMD_Mode_0;
IO0_T_control <= CMD_Mode_0;
IO3_T_control <= not Quad_Phase;-- this is due to sending '1' on DQ3 line during command phase for Quad instructions only.
--if(SPIXfer_done_int_pulse_d2 = '1')then
if(SPIXfer_done_int_pulse = '1')then
if(Addr_Phase='1')then
qspi_cntrl_ns <= ADDR_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
else
qspi_cntrl_ns <= CMD_SEND;
end if;
------------------------------------------------
when ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);
IO2_T_control <= (not Addr_Mode_1);
IO3_T_control <= (not Addr_Mode_1);
--stop_clock <= SR_5_Tx_Empty;
if((SR_5_Tx_Empty='1') and
(Data_Phase='0')
)then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
if(
(addr_cnt = "011") and -- 24 bit address
(Addr_Bit='0') and
(Data_Phase='1')
)then
if((Data_Dir='1'))then
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0';
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);
IO3_T_control <= not (Data_Mode_1);
qspi_cntrl_ns <= DATA_SEND; -- o/p
else
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
end if;
elsif(
(addr_cnt = "100") and -- 32 bit
(Addr_Bit = '1') and
(Data_Phase='1')
) then
--if((Data_Dir='1'))then
-- qspi_cntrl_ns <= DATA_SEND; -- o/p
--else
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
--end if;
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
end if;
-- ------------------------------------------------
when TEMP_ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);
IO2_T_control <= (not Addr_Mode_1);
IO3_T_control <= (not Addr_Mode_1);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= ADDR_SEND;
end if;
when DATA_SEND => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0';
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);
IO3_T_control <= not (Data_Mode_1);
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1')then
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
qspi_cntrl_ns <= DATA_SEND;
end if;
------------------------------------------------
when TEMP_DATA_SEND=> mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0';
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);
IO3_T_control <= not (Data_Mode_1);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_SEND;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_SEND;
end if;
when DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1') or (wrap_ack_1 = '1')then
rst_wrap_around <= wrap_ack_1;
--if(no_slave_selected = '1') or (wrap_around = '1')then
stop_clock <= wrap_ack_1 or SR_5_Tx_Empty;
qspi_cntrl_ns <= IDLE;
--else
-- stop_clock <= SR_5_Tx_Empty;
-- qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
--end if;
else
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
when TEMP_DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= stop_clock_reg;
--if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
--else
-- stop_clock <= '0';
-- qspi_cntrl_ns <= DATA_RECEIVE;
--end if;
------------------------------------------------
-- coverage off
when others => qspi_cntrl_ns <= IDLE; -- CMD_DECODE;
------------------------------------------------
-- coverage on
end case;
-------------------------------
end process QSPI_CNTRL_PROCESS;
-------------------------------
pr_state_addr_ph <= '1' when qspi_cntrl_ps = ADDR_SEND else
'0';
QSPI_ADDR_CNTR_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(pr_state_addr_ph = '0') then
addr_cnt <= (others => '0');
elsif(pr_state_addr_ph = '1')then
--addr_cnt <= addr_cnt + SPIXfer_done_int_pulse_d2;
addr_cnt <= addr_cnt + SPIXfer_done_int_pulse;
end if;
end if;
end process QSPI_ADDR_CNTR_PROCESS;
-----------------------------------
end generate XIP_QUAD_MODE_SP_MEM_GEN;
---------------------------------------
IO0_O <= Serial_Dout_0;
IO1_O <= Serial_Dout_1;
IO2_O <= Serial_Dout_2;
IO3_O <= Serial_Dout_3;
--SCK_O <= SCK_O_reg;
--SS_O <= SS_to_spi_clk;
--* -------------------------------------------------------------------------------
--* -- MASTER_TRIST_EN_PROCESS : If not master make tristate enabled
--* ----------------------------
SS_tri_state_en_control <= '0' when
(
-- (SR_5_Tx_Empty_d1 = '0') and -- Length counter is not exited
(transfer_start = '1') and
(wrap_ack = '0') and -- no wrap around
--(MODF_strobe_int ='0') -- no mode fault -- 9/7/2013
(SPISEL_sync = '1') -- 9/7/2013
)
else
'1';
--QSPI_SS_T: tri-state register for SS,ideal state-deactive
QSPI_SS_T: component FD
generic map
(
INIT => '1'
)
port map
(
Q => SS_T,
C => EXT_SPI_CLK,
D => SS_tri_state_en_control
);
--QSPI_SCK_T : Tri-state register for SCK_T, ideal state-deactive
SCK_tri_state_en_control <= '0' when
(
-- (SR_5_Tx_Empty = '0') and -- Length counter is not exited
(transfer_start = '1') and -- 4/14/2013
(wrap_ack = '0') and -- no wrap around-- (pr_state_non_idle = '1') and -- CR#619275 - this is commented to operate the mode 3 with SW flow
--(MODF_strobe_int ='0') -- no mode fault -- 9/7/2013
(SPISEL_sync = '1') -- 9/7/2013
) else
'1';
QSPI_SCK_T: component FD
generic map
(
INIT => '1'
)
port map
(
Q => SCK_T,
C => EXT_SPI_CLK,
D => SCK_tri_state_en_control
);
IO0_tri_state_en_control <= '0' when
(
(IO0_T_control = '0') and
--(MODF_strobe_int = '0')-- no mode fault-- 9/7/2013
(SPISEL_sync = '1') -- 9/7/2013
) else
'1';
--QSPI_IO0_T: tri-state register for MOSI, ideal state-deactive
QSPI_IO0_T: component FD
generic map
(
INIT => '1'
)
port map
(
Q => IO0_T, -- MOSI_T,
C => EXT_SPI_CLK,
D => IO0_tri_state_en_control -- master_tri_state_en_control
);
IO1_tri_state_en_control <= '0' when
(
(IO1_T_control = '0') and
--(MODF_strobe_int = '0')-- no mode fault-- 9/7/2013
(SPISEL_sync = '1') -- 9/7/2013
) else
'1';
--QSPI_IO0_T: tri-state register for MISO, ideal state-deactive
QSPI_IO1_T: component FD
generic map
(
INIT => '1'
)
port map
(
Q => IO1_T, -- MISO_T,
C => EXT_SPI_CLK,
D => IO1_tri_state_en_control
);
-------------------------------------------------------------------------------
QSPI_NO_MODE_2_T_CONTROL: if C_SPI_MODE = 1 or C_SPI_MODE = 0 generate
----------------------
begin
-----
--------------------------------------
IO2_tri_state_en_control <= '1';
IO3_tri_state_en_control <= '1';
IO2_T <= '1';
IO3_T <= '1';
--------------------------------------
end generate QSPI_NO_MODE_2_T_CONTROL;
--------------------------------------
-------------------------------------------------------------------------------
QSPI_MODE_2_T_CONTROL: if C_SPI_MODE = 2 generate
----------------------
begin
-----
--------------------------------------
IO2_tri_state_en_control <= '0' when
(
(IO2_T_control = '0') and
--(MODF_strobe_int = '0')-- no mode fault -- 9/7/2013
(SPISEL_sync = '1') -- 9/7/2013
) else
'1';
--QSPI_IO0_T: tri-state register for MOSI, ideal state-deactive
QSPI_IO2_T: component FD
generic map
(
INIT => '1'
)
port map
(
Q => IO2_T, -- MOSI_T,
C => EXT_SPI_CLK,
D => IO2_tri_state_en_control -- master_tri_state_en_control
);
--------------------------------------
IO3_tri_state_en_control <= '0' when
(
(IO3_T_control = '0') and
--(MODF_strobe_int = '0')-- no mode fault-- 9/7/2013
(SPISEL_sync = '1') -- 9/7/2013
) else
'1';
--QSPI_IO0_T: tri-state register for MISO, ideal state-deactive
QSPI_IO3_T: component FD
generic map
(
INIT => '1'
)
port map
(
Q => IO3_T, -- MISO_T,
C => EXT_SPI_CLK,
D => IO3_tri_state_en_control
);
--------------------------------------
end generate QSPI_MODE_2_T_CONTROL;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- QSPI_SPISEL: first synchronize the incoming signal, this is required is slave
--------------- mode of the core.
QSPI_SPISEL: component FD
generic map
(
INIT => '1' -- default '1' to make the device in default master mode
)
port map
(
Q => SPISEL_sync,
C => EXT_SPI_CLK,
D => SPISEL
);
-- SPISEL_DELAY_1CLK_PROCESS_P : Detect active SCK edge in slave mode
-----------------------------
SPISEL_DELAY_1CLK_PROCESS_P: process(EXT_SPI_CLK)
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
spisel_d1 <= '1';
else
spisel_d1 <= SPISEL_sync;
end if;
end if;
end process SPISEL_DELAY_1CLK_PROCESS_P;
------------------------------------------------
-- MODF_STROBE_PROCESS : Strobe MODF signal when master is addressed as slave
------------------------
MODF_STROBE_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if((Rst_to_spi = RESET_ACTIVE) or (SPISEL_sync = '1')) then
MODF_strobe <= '0';
MODF_strobe_int <= '0';
Allow_MODF_Strobe <= '1';
elsif(
(SPISEL_sync = '0') and
(Allow_MODF_Strobe = '1')
) then
MODF_strobe <= '1';
MODF_strobe_int <= '1';
Allow_MODF_Strobe <= '0';
else
MODF_strobe <= '0';
MODF_strobe_int <= '0';
end if;
end if;
end process MODF_STROBE_PROCESS;
SS_O_24_BIT_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
-----
begin
-----
-------------------------------------------------------------------------------
-- SELECT_OUT_PROCESS : This process sets SS active-low, one-hot encoded select
-- bit. Changing SS is premitted during a transfer by
-- hardware, but is to be prevented by software. In Auto
-- mode SS_O reflects value of Slave_Select_Reg only
-- when transfer is in progress, otherwise is SS_O is held
-- high
-----------------------
SELECT_OUT_PROCESS: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
SS_O <= (others => '1');
elsif(wrap_ack_1 = '1') or (store_last_b4_wrap = '1') or (SR_5_Tx_Empty ='1') then
SS_O <= (others => '1');
elsif(hpm_under_process_d1 = '1') then
for i in (C_NUM_SS_BITS-1) downto 0 loop
SS_O(i) <= (SS_to_spi_clk(C_NUM_SS_BITS-1-i));
end loop;
elsif(store_last_b4_wrap = '0') then
for i in (C_NUM_SS_BITS-1) downto 0 loop
SS_O(i) <= not(SS_to_spi_clk(C_NUM_SS_BITS-1-i));
end loop;
end if;
end if;
end process SELECT_OUT_PROCESS;
----------------------------
end generate SS_O_24_BIT_ADDR_GEN;
----------------------------------
SS_O_32_BIT_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
-----
begin
-----
-------------------------------------------------------------------------------
-- SELECT_OUT_PROCESS : This process sets SS active-low, one-hot encoded select
-- bit. Changing SS is premitted during a transfer by
-- hardware, but is to be prevented by software. In Auto
-- mode SS_O reflects value of Slave_Select_Reg only
-- when transfer is in progress, otherwise is SS_O is held
-- high
-----------------------
SELECT_OUT_PROCESS: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
SS_O <= (others => '1');
elsif(wrap_ack_1 = '1') or (store_last_b4_wrap = '1') or (transfer_start = '0' and SR_5_Tx_Empty_d1='1') then
SS_O <= (others => '1');
elsif(hpm_under_process = '1') or (wr_en_under_process = '1') then
for i in (C_NUM_SS_BITS-1) downto 0 loop
SS_O(i) <= (SS_to_spi_clk(C_NUM_SS_BITS-1-i));
end loop;
elsif(store_last_b4_wrap = '0') then
for i in (C_NUM_SS_BITS-1) downto 0 loop
SS_O(i) <= not(SS_to_spi_clk(C_NUM_SS_BITS-1-i));
end loop;
end if;
end if;
end process SELECT_OUT_PROCESS;
----------------------------
end generate SS_O_32_BIT_ADDR_GEN;
----------------------------------
no_slave_selected <= and_reduce(SS_to_spi_clk((C_NUM_SS_BITS-1) downto 0));
-------------------------------------------------------------------------------
SCK_O_NQ_4_NO_STARTUP_USED: if (C_USE_STARTUP = 0) generate
----------------
attribute IOB : string;
attribute IOB of SCK_O_NE_4_FDRE_INST : label is "true";
signal slave_mode : std_logic;
----------------
begin
-----
-------------------------------------------------------------------------------
-- SCK_O_SELECT_PROCESS : Select the idle state (CPOL bit) when not transfering
-- data else select the clock for slave device
-------------------------
SCK_O_NQ_4_SELECT_PROCESS: process(--Mst_N_Slv ,-- in master mode
sck_o_int ,-- value driven on sck_int
CPOL_to_spi_clk ,-- CPOL mode thr SPICR
transfer_start ,
transfer_start_d1 ,
Count(COUNT_WIDTH),
pr_state_non_idle -- State machine is in Non-idle state
)is
begin
if((transfer_start = '1') and
--(transfer_start_d1 = '1') and
--(Count(COUNT_WIDTH) = '0')and
(pr_state_non_idle = '1')
) then
sck_o_in <= sck_o_int;
else
sck_o_in <= CPOL_to_spi_clk;
end if;
end process SCK_O_NQ_4_SELECT_PROCESS;
---------------------------------
slave_mode <= '0'; -- create the reset condition by inverting the mst_n_slv signal. 1 - master mode, 0 - slave mode.
-- FDRE: Single Data Rate D Flip-Flop with Synchronous Reset and
-- Clock Enable (posedge clk). during slave mode no clock should be generated from the core.
SCK_O_NE_4_FDRE_INST : component FDRE
generic map (
INIT => '0'
) -- Initial value of register (0 or 1)
port map
(
Q => SCK_O_reg, -- Data output
C => EXT_SPI_CLK, -- Clock input
CE => '1', -- Clock enable input
R => Rst_to_spi, -- Synchronous reset input
D => sck_o_in -- Data input
);
end generate SCK_O_NQ_4_NO_STARTUP_USED;
-------------------------------
SCK_O_NQ_4_STARTUP_USED: if (C_USE_STARTUP = 1) generate
-------------
begin
-----
-------------------------------------------------------------------------------
-- SCK_O_SELECT_PROCESS : Select the idle state (CPOL bit) when not transfering
-- data else select the clock for slave device
-------------------------
SCK_O_NQ_4_SELECT_PROCESS: process(sck_o_int ,
CPOL_to_spi_clk ,
transfer_start ,
transfer_start_d1 ,
Count(COUNT_WIDTH)
)is
begin
if((transfer_start = '1') -- and
--(transfer_start_d1 = '1') --and
--(Count(COUNT_WIDTH) = '0')
) then
sck_o_in <= sck_o_int;
else
sck_o_in <= CPOL_to_spi_clk;
end if;
end process SCK_O_NQ_4_SELECT_PROCESS;
---------------------------------
---------------------------------------------------------------------------
-- SCK_O_FINAL_PROCESS : Register the final SCK_O_reg
------------------------
SCK_O_NQ_4_FINAL_PROCESS: process(EXT_SPI_CLK)
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
--If Soft_Reset_op or slave Mode.Prevents SCK_O_reg to be generated in slave
if((Rst_to_spi = RESET_ACTIVE)
) then
SCK_O_reg <= '0';
elsif((pr_state_non_idle='0')-- or -- dont allow sck to go out when
--(Mst_N_Slv = '0')
)then -- SM is in IDLE state or core in slave mode
SCK_O_reg <= '0';
else
SCK_O_reg <= sck_o_in;
end if;
end if;
end process SCK_O_NQ_4_FINAL_PROCESS;
-------------------------------------
end generate SCK_O_NQ_4_STARTUP_USED;
-------------------------------------
--end generate RATIO_NOT_EQUAL_4_GENERATE;
end generate RATIO_OF_2_GENERATE;
end architecture imp;
-------------------------------------------------------------------------------
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ent is
generic(n : natural := 2);
port(A : in std_logic_vector(n - 1 downto 0);
B : in std_logic_vector(n - 1 downto 0);
carry : out std_logic;
sum : out std_logic_vector(n - 1 downto 0));
end ent;
architecture beh of ent is
signal result : std_logic_vector(n downto 0);
begin
result <= ('0' & A) + ('0' & B);
sum <= result(n - 1 downto 0);
carry <= result;
end beh;
|
-- file: modules/player_pack.vhd
-- authors: Alexandre Medeiros and Gabriel Lopes
--
-- A Flappy bird implementation in VHDL for a Digital Circuits course at
-- Unicamp.
library ieee ;
use ieee.std_logic_1164.all ;
package player is
-- Calculate current speed based on internal register for speed, gravity value
-- and jump signal.
component calculate_speed
generic (
V_RES : natural -- Vertical Resolution
) ;
port (
jump : in std_logic ;
gravity : in integer range 0 to V_RES - 1 ;
speed : out integer range - V_RES to V_RES - 1 ;
clock : in std_logic ;
enable : in std_logic ;
reset : in std_logic
) ;
end component ;
-- Calculate current position based on internal register for position and
-- current speed value.
component calculate_position
generic (
V_RES : natural -- Vertical Resolution
) ;
port (
jump : in std_logic ;
gravity : in integer range 0 to V_RES - 1 ;
position : out integer range 0 to V_RES - 1 ;
clock : in std_logic ;
enable : in std_logic ;
reset : in std_logic
) ;
end component ;
end player ;
|
------------------------------------------------------------------------------
-- Computation clock generation unit; clock gating of main clock; clock enabled
-- if run cycle counter is not NULL
--
-- Project :
-- File : cclkgating.vhd
-- Author : Rolf Enzler <enzler@ife.ee.ethz.ch>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2002/06/26
-- Last changed: $LastChangedDate: 2004-10-05 17:10:36 +0200 (Tue, 05 Oct 2004) $
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity CClkGating is
port (
EnxEI : in std_logic;
MClockxCI : in std_logic;
CClockxCO : out std_logic);
end CClkGating;
architecture simple of CClkGating is
begin -- simple
CClockxCO <= MClockxCI and EnxEI;
end simple;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc891.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c10s02b00x00p02n02i00891ent IS
END c10s02b00x00p02n02i00891ent;
ARCHITECTURE c10s02b00x00p02n02i00891arch OF c10s02b00x00p02n02i00891ent IS
type rec_typ is RECORD
-- immediate scope
r,g,b : real;
end record;
BEGIN
TESTING: PROCESS
-- extended scope
variable electron_gun : rec_typ := ( 0.25, 0.5, 1.0 );
BEGIN
assert NOT( electron_gun.r = 0.25 and
electron_gun.g = 0.5 and
electron_gun.b = 1.0 )
report "***PASSED TEST: c10s02b00x00p02n02i00891"
severity NOTE;
assert ( electron_gun.r = 0.25 and
electron_gun.g = 0.5 and
electron_gun.b = 1.0 )
report "***FAILED TEST: c10s02b00x00p02n02i00891 - The scope of the declaration that occurs immediately within a record type declaration extends beyond the immediate scope"
severity ERROR;
wait;
END PROCESS TESTING;
END c10s02b00x00p02n02i00891arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc891.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c10s02b00x00p02n02i00891ent IS
END c10s02b00x00p02n02i00891ent;
ARCHITECTURE c10s02b00x00p02n02i00891arch OF c10s02b00x00p02n02i00891ent IS
type rec_typ is RECORD
-- immediate scope
r,g,b : real;
end record;
BEGIN
TESTING: PROCESS
-- extended scope
variable electron_gun : rec_typ := ( 0.25, 0.5, 1.0 );
BEGIN
assert NOT( electron_gun.r = 0.25 and
electron_gun.g = 0.5 and
electron_gun.b = 1.0 )
report "***PASSED TEST: c10s02b00x00p02n02i00891"
severity NOTE;
assert ( electron_gun.r = 0.25 and
electron_gun.g = 0.5 and
electron_gun.b = 1.0 )
report "***FAILED TEST: c10s02b00x00p02n02i00891 - The scope of the declaration that occurs immediately within a record type declaration extends beyond the immediate scope"
severity ERROR;
wait;
END PROCESS TESTING;
END c10s02b00x00p02n02i00891arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc891.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c10s02b00x00p02n02i00891ent IS
END c10s02b00x00p02n02i00891ent;
ARCHITECTURE c10s02b00x00p02n02i00891arch OF c10s02b00x00p02n02i00891ent IS
type rec_typ is RECORD
-- immediate scope
r,g,b : real;
end record;
BEGIN
TESTING: PROCESS
-- extended scope
variable electron_gun : rec_typ := ( 0.25, 0.5, 1.0 );
BEGIN
assert NOT( electron_gun.r = 0.25 and
electron_gun.g = 0.5 and
electron_gun.b = 1.0 )
report "***PASSED TEST: c10s02b00x00p02n02i00891"
severity NOTE;
assert ( electron_gun.r = 0.25 and
electron_gun.g = 0.5 and
electron_gun.b = 1.0 )
report "***FAILED TEST: c10s02b00x00p02n02i00891 - The scope of the declaration that occurs immediately within a record type declaration extends beyond the immediate scope"
severity ERROR;
wait;
END PROCESS TESTING;
END c10s02b00x00p02n02i00891arch;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pcitb_monitor
-- File: pcitb_monitor.vhd
-- Author:
-- Description: PCI Monitor.
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.pt_pkg.all;
library grlib;
use grlib.stdlib.xorv;
entity pt_pci_monitor is
generic (dbglevel : integer := 1);
port (pciin : in pci_type);
end pt_pci_monitor;
architecture tb of pt_pci_monitor is
constant T_O : integer := 9;
type pci_array_type is array(0 to 2) of pci_type;
type reg_type is record
pci : pci_array_type;
frame_deass : boolean;
m_wait_data_phase : boolean;
t_wait_data_phase : boolean;
stop_asserted : boolean;
device_sel : boolean;
first : boolean;
current_master : integer;
master_cnt : integer;
irdy_cnt : integer;
trdy_cnt : integer;
end record;
signal r,rin : reg_type;
signal init_done : boolean := false;
begin
init : process
begin
if init_done = false then
wait until pciin.syst.rst = '0';
wait until pciin.syst.rst = '1';
init_done <= true;
else
wait until pciin.syst.rst = '0';
init_done <= false;
end if;
end process;
comb : process(pciin)
variable i : integer;
variable v : reg_type;
begin
v := r;
v.pci(0) := pciin; v.pci(1) := r.pci(0); v.pci(2) := r.pci(1);
if r.pci(0).ifc.frame = 'H' then v.frame_deass := false;
elsif (r.pci(0).ifc.frame and not r.pci(1).ifc.frame) = '1' then v.frame_deass := true; end if;
if ((r.pci(0).ifc.trdy and r.pci(0).ifc.stop) or r.pci(0).ifc.irdy) = '0' then v.m_wait_data_phase := false;
elsif r.pci(0).ifc.irdy = '0' then v.m_wait_data_phase := true; end if;
if ((r.pci(0).ifc.trdy and r.pci(0).ifc.stop) or r.pci(0).ifc.irdy) = '0' then v.t_wait_data_phase := false;
elsif (r.pci(0).ifc.trdy and r.pci(0).ifc.stop) = '0' then v.t_wait_data_phase := true; end if;
if r.pci(0).ifc.frame = '0' and r.pci(1).ifc.frame = 'H' then
for i in 0 to 20 loop
if r.pci(0).arb.gnt(i) = '0' then v.current_master := i; end if;
end loop;
end if;
if (r.pci(0).ifc.frame and r.pci(0).ifc.irdy) = '0' then
if (r.pci(0).ifc.trdy and r.pci(0).ifc.stop) = '1' then
v.master_cnt := r.master_cnt+1;
else v.master_cnt := 0; end if;
else v.master_cnt := 0; end if;
if (r.pci(0).ifc.irdy and not r.pci(0).ifc.frame) = '1' then
v.irdy_cnt := r.irdy_cnt+1;
else v.irdy_cnt := 0; end if;
if ((r.pci(0).ifc.trdy and r.pci(0).ifc.stop) and not (r.pci(0).ifc.frame and r.pci(0).ifc.irdy)) = '1' then
v.trdy_cnt := r.trdy_cnt+1;
else v.trdy_cnt := 0; end if;
if r.pci(0).ifc.devsel = '0' then v.device_sel := true;
elsif (to_x01(r.pci(1).ifc.devsel) and not (r.pci(0).ifc.frame and r.pci(0).ifc.irdy)) = '1' then v.device_sel := false; end if;
if r.pci(0).ifc.stop = '0' then v.stop_asserted := true;
elsif r.pci(0).ifc.frame = '0' then v.stop_asserted := false; end if;
if (r.pci(1).ifc.frame = 'H' and r.pci(0).ifc.frame = '0') then v.first := true;
elsif (r.pci(0).ifc.trdy and r.pci(0).ifc.stop) = '0' then v.first := false; end if;
rin <= v;
end process;
clkprc : process(pciin.syst)
begin
if rising_edge(pciin.syst.clk) then
r <= rin;
if init_done then
if (r.pci(0).ifc.frame = '0' and r.frame_deass = true) then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: FRAME# was reasserted during the same transaction.");
end if;
end if;
if (r.pci(0).ifc.frame and r.pci(0).ifc.irdy and not r.pci(1).ifc.frame) = '1' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: FRAME# was deasserted without IRDY# asserted.");
end if;
end if;
if (r.m_wait_data_phase and r.device_sel) then
if (r.pci(0).ifc.frame /= r.pci(1).ifc.frame) or (r.pci(0).ifc.irdy /= r.pci(1).ifc.irdy) then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Current master changed IRDY# or FRAME# before current data phase was completed.");
end if;
end if;
end if;
if ((r.pci(1).ifc.irdy and r.pci(1).ifc.frame and not r.pci(2).ifc.irdy) = '1' and r.stop_asserted = true) then
if not ((r.pci(1).arb.req(r.current_master) and (r.pci(0).arb.req(r.current_master) or r.pci(2).arb.req(r.current_master))) = '1') then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Current master at slot %d did not release its REQ# when the bus returned to idle state.",r.current_master);
end if;
end if;
end if;
if (r.pci(0).ifc.stop and not r.pci(1).ifc.stop and not r.pci(0).ifc.frame) = '1' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Target did not keep STOP# asserted until FRAME# was deasserted.");
end if;
end if;
if (r.pci(0).ifc.frame and r.pci(1).ifc.frame and not r.pci(0).ifc.stop and not r.pci(1).ifc.stop) = '1' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Target did not release STOP# after FRAME# was deasserted.");
end if;
end if;
if r.t_wait_data_phase = true then
if (r.pci(0).ifc.devsel /= r.pci(1).ifc.devsel) or (r.pci(0).ifc.trdy /= r.pci(1).ifc.trdy) or (r.pci(0).ifc.stop /= r.pci(1).ifc.stop) then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Current target changed DEVSEL#, STOP# or TRDY# before current data phase was completed.");
end if;
end if;
end if;
if (r.pci(0).ifc.frame and r.pci(0).ifc.stop and not r.pci(1).ifc.frame and not r.pci(1).ifc.stop) = '1' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Target did not keep STOP# asserted until the last data phase.");
end if;
end if;
if (r.pci(2).ifc.frame and not (r.pci(2).ifc.trdy and r.pci(2).ifc.stop)) = '1' then
if r.pci(1).ifc.irdy = '0' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Master kept IRDY# asserted after last data phase.");
end if;
end if;
if r.pci(1).ifc.trdy = '0' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Target kept TRDY# asserted after last data phase.");
end if;
end if;
if r.pci(1).ifc.stop = '0' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Target kept STOP# asserted after last data phase.");
end if;
end if;
if r.pci(1).ifc.frame /= 'H' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Master did not tri-state FRAME# after turn-around cycle.");
end if;
end if;
if r.pci(0).ifc.irdy /= 'H' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Master did not tri-state IRDY# after turn-around cycle.");
end if;
end if;
if r.pci(0).ifc.trdy /= 'H' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Target did not tri-state TRDY# after turn-around cycle.");
end if;
end if;
if r.pci(0).ifc.stop /= 'H' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Target did not tri-state STOP# after turn-around cycle.");
end if;
end if;
end if;
if (r.master_cnt > 16 and r.first = true) then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Target did not complete its initial data phase in 16 clkc.");
end if;
end if;
if r.irdy_cnt > 8 then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Master did not complete its initial data phase in 8 clkc.");
end if;
end if;
if (r.trdy_cnt > 8 and r.device_sel = true and r.first = false) then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Target did not complete a data phase in 8 clkc.");
end if;
end if;
if not r.device_sel then
if (r.pci(0).ifc.irdy and not r.pci(1).ifc.irdy) = '1' then
if dbglevel > 0 then
assert false
report "**"
severity note;
printf("PCI_MONITOR: Master abort detected.");
end if;
end if;
end if;
if ((r.pci(1).ifc.irdy = 'H' and r.pci(1).ifc.frame = '0')
or (r.pci(1).ifc.irdy or r.pci(1).ifc.trdy) = '0') then
if r.pci(0).ad.par = 'Z' then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Current Master/Target is not generating parity during a data phase.");
end if;
elsif r.pci(0).ad.par /= xorv(r.pci(1).ad.ad & r.pci(1).ad.cbe) then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: Parity error detected.");
end if;
end if;
end if;
end if;
end if;
end process;
adchk : process(pciin.ad)
begin
if init_done then
-- for i in 0 to 31 loop
-- if pciin.ad.ad(i) = 'X' then
-- if dbglevel > 0 then
-- assert false
-- report " **"
-- severity warning;
-- printf("PCI_MONITOR: AD lines have multiple drivers.");
-- end if;
-- end if;
-- end loop;
for i in 0 to 3 loop
if pciin.ad.cbe(i) = 'X' then
if dbglevel > 0 then
assert false
report " **"
severity warning;
printf("PCI_MONITOR: CBE# lines have multiple drivers.");
end if;
end if;
end loop;
-- if pciin.ad.par = 'X' then
-- if dbglevel > 0 then
-- assert false
-- report " **"
-- severity warning;
-- printf("PCI_MONITOR: PAR line has multiple drivers.");
-- end if;
-- end if;
end if;
end process;
ifcchk : process(pciin.ifc)
begin
if init_done then
if pciin.ifc.frame = 'X' then
if dbglevel > 0 then
assert false
report " **"
severity warning;
printf("PCI_MONITOR: FRAME# line has multiple drivers.");
end if;
end if;
if pciin.ifc.irdy = 'X' then
if dbglevel > 0 then
assert false
report " **"
severity warning;
printf("PCI_MONITOR: IRDY# line has multiple drivers.");
end if;
end if;
if pciin.ifc.trdy = 'X' then
if dbglevel > 0 then
assert false
report " **"
severity warning;
printf("PCI_MONITOR: TRDY# line has multiple drivers.");
end if;
end if;
if pciin.ifc.stop = 'X' then
if dbglevel > 0 then
assert false
report " **"
severity warning;
printf("PCI_MONITOR: STOP# line has multiple drivers.");
end if;
end if;
if pciin.ifc.devsel = 'X' then
if dbglevel > 0 then
assert false
report " **"
severity warning;
printf("PCI_MONITOR: DEVSEL# line has multiple drivers.");
end if;
end if;
end if;
end process;
arbchk : process(pciin.arb)
variable gnt_set : boolean;
begin
gnt_set := false;
if init_done then
for i in 0 to 20 loop
if pciin.arb.gnt(i) = '0' then
if gnt_set then
if dbglevel > 0 then
assert false
report "***PCI ERROR***"
severity warning;
printf("PCI_MONITOR: GNT# is asserted for more than one PCI master.");
end if;
else gnt_set := true; end if;
end if;
end loop;
end if;
end process;
end;
-- pragma translate_on
|
-------------------------------------------------------------------------------
-- Title : UART
-- Project : fpga_logic_analyzer
-------------------------------------------------------------------------------
-- File : UART.vhd
-- Created : 2016-02-22
-- Last update: 2016-03-28
-- Standard : VHDL'08
-------------------------------------------------------------------------------
-- Description: This is the UART the sump comms module will use. It is capable
-- of taking an input baud rate and clock frequency to run a baud clock using a
-- clock divider. It transmits data when the transmit data (data_out)changes and
-- recieves data when it recieves a low signal on the rx line.
-------------------------------------------------------------------------------
-- Copyright (c) 2016 Ashton Johnson, Paul Henny, Ian Swepston, David Hurt
-------------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-02-22 1.0 ian Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity uart_comms is
generic (baud_rate : positive := 115_200;
clock_freq : positive := 100_000_000); -- Make sure we keep integer division here
port(clk : in std_logic; -- clock
rst : in std_logic; -- reset logic
rx_get_more_data : in std_logic; -- stop bit found for stream in
rx_data_ready : out std_logic; -- stream out ready
rx : in std_logic; -- recieve line
data_in : in std_logic_vector(7 downto 0) := (others => '0'); -- data to be transmitted
tx_data_ready : in std_logic; -- stream out stop bit sent
tx_data_sent : out std_logic; -- ready for rx
tx : out std_logic; -- transmit line
data_out : out std_logic_vector(7 downto 0));
--state : out integer;
-- baud16 : out std_logic); -- data recieved from rx line
begin --added comment
assert(clock_freq mod baud_rate = 0) report ("Non Integer Division") severity(error);
end entity uart_comms;
architecture pass_through of uart_comms is
type states is (Init, Wait_State, Get_Data, Send_Data, Data_Ready, Send_Complete);
signal rx_current_state, rx_next_state, tx_current_state, tx_next_state : states;
signal rx_counter, tx_counter : integer range 0 to 255 := 0;
signal trans_data : std_logic_vector(7 downto 0) := (others => '0');
signal data_out_sig : std_logic_vector(7 downto 0) := (others => '0');
signal baud_clock, baud_clock_x16 : std_logic := '0';
signal baud_counter, baud_counter_x16 : integer range 0 to 1024 := 0;
signal sampling_counter, zero_counter : integer range 0 to 16 := 0;
signal baud_reset, baud_reset_last : std_logic := '0';
constant baud_total : integer := (clock_freq/baud_rate)/2;
constant baud_total_x16 : integer := (clock_freq/baud_rate)/16/2;
begin
-- Create baud clock
baud_clocking : process (clk)
begin
if(clk = '1' and clk'event) then
if (baud_counter < baud_total - 1) then
baud_counter <= baud_counter + 1;
else
baud_counter <= 0;
baud_clock <= not baud_clock;
end if;
end if;
end process baud_clocking;
baud_clocking_x16 : process (clk)
begin
if (clk = '1' and clk'event) then
baud_reset_last <= baud_reset;
if(baud_reset = '1' and baud_reset_last = '0') then
baud_counter_x16 <= 0;
baud_clock_x16 <= '0';
elsif (baud_counter_x16 < ((baud_total_x16) - 1)) then
baud_counter_x16 <= baud_counter_x16 + 1;
else
baud_counter_x16 <= 0;
baud_clock_x16 <= not baud_clock_x16;
end if;
end if;
end process baud_clocking_x16;
-- baud16 <= baud_clock_x16;
-- State transition logic for RX
rx_moore : process (baud_clock_x16)
begin
if rst = '1' then
rx_next_state <= Init;
elsif baud_clock_x16 = '1' and baud_clock_x16'event then
baud_reset <= '0';
rx_data_ready <= '0';
case rx_current_state is
when Init =>
rx_next_state <= Wait_State;
baud_reset <= '1';
sampling_counter <= 0;
rx_counter <= 0;
zero_counter <= 0;
when Wait_State =>
rx_next_state <= Wait_State;
if rx = '0' then
zero_counter <= zero_counter + 1;
else
zero_counter <= 0;
end if;
if zero_counter > 9 then
rx_next_state <= Get_Data;
baud_reset <= '1';
sampling_counter <= 0;
rx_counter <= 0;
zero_counter <= 0;
end if;
when Get_Data =>
rx_next_state <= Get_Data;
if sampling_counter < 15 then
sampling_counter <= sampling_counter + 1;
else
sampling_counter <= 0;
if rx_counter < 8 then
rx_counter <= rx_counter + 1;
data_out_sig <= rx & data_out_sig(7 downto 1); -- shift right
else
rx_counter <= 0;
rx_next_state <= Data_Ready;
end if;
end if;
when Data_Ready =>
rx_next_state <= Data_Ready;
data_out <= data_out_sig;
rx_data_ready <= '1';
if rx_get_more_data <= '1' then
rx_next_state <= Wait_State;
end if;
when others => null;
end case;
end if;
rx_current_state <= rx_next_state;
end process rx_moore;
-- State transition logic for TX
tx_moore : process (baud_clock)
begin
if rst = '1' then
tx_next_state <= Init;
elsif baud_clock = '1' and baud_clock'event then
tx <= '1';
tx_data_sent <= '0';
case tx_current_state is
when Init =>
tx_next_state <= Wait_State;
tx_data_sent <= '0';
trans_data <= data_in;
tx_counter <= 0;
when Wait_State =>
tx_next_state <= Wait_State;
if tx_data_ready = '1' then
tx_next_state <= Send_Data;
trans_data <= data_in;
tx_counter <= 0;
tx <= '0';
end if;
when Send_Data =>
tx_next_state <= Send_Data;
if tx_counter < 8 then -- transmit 8 bits
tx <= trans_data(tx_counter);
tx_counter <= tx_counter + 1;
else -- transmit high end bit
tx <= '1';
tx_next_state <= Send_Complete;
end if;
when Send_Complete =>
tx_next_state <= Wait_State;
tx_data_sent <= '1';
when others => null;
end case;
end if;
tx_current_state <= tx_next_state;
end process tx_moore;
end architecture pass_through;
|
--
-- Clock divider (clock enable generator)
--
-- Author: Sebastian Witt
-- Date: 27.01.2008
-- Version: 1.1
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
entity slib_clock_div is
generic (
RATIO : integer := 4 -- Clock divider ratio
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CE : in std_logic; -- Clock enable input
Q : out std_logic -- New clock enable output
);
end slib_clock_div;
architecture rtl of slib_clock_div is
-- Signals
signal iQ : std_logic; -- Internal Q
signal iCounter : integer range 0 to RATIO-1; -- Counter
begin
-- Main process
CD_PROC: process (RST, CLK)
begin
if (RST = '1') then
iCounter <= 0;
iQ <= '0';
elsif (CLK'event and CLK='1') then
iQ <= '0';
if (CE = '1') then
if (iCounter = (RATIO-1)) then
iQ <= '1';
iCounter <= 0;
else
iCounter <= iCounter + 1;
end if;
end if;
end if;
end process;
-- Output signals
Q <= iQ;
end rtl;
|
--
-- Clock divider (clock enable generator)
--
-- Author: Sebastian Witt
-- Date: 27.01.2008
-- Version: 1.1
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
entity slib_clock_div is
generic (
RATIO : integer := 4 -- Clock divider ratio
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CE : in std_logic; -- Clock enable input
Q : out std_logic -- New clock enable output
);
end slib_clock_div;
architecture rtl of slib_clock_div is
-- Signals
signal iQ : std_logic; -- Internal Q
signal iCounter : integer range 0 to RATIO-1; -- Counter
begin
-- Main process
CD_PROC: process (RST, CLK)
begin
if (RST = '1') then
iCounter <= 0;
iQ <= '0';
elsif (CLK'event and CLK='1') then
iQ <= '0';
if (CE = '1') then
if (iCounter = (RATIO-1)) then
iQ <= '1';
iCounter <= 0;
else
iCounter <= iCounter + 1;
end if;
end if;
end if;
end process;
-- Output signals
Q <= iQ;
end rtl;
|
--
-- Clock divider (clock enable generator)
--
-- Author: Sebastian Witt
-- Date: 27.01.2008
-- Version: 1.1
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
entity slib_clock_div is
generic (
RATIO : integer := 4 -- Clock divider ratio
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CE : in std_logic; -- Clock enable input
Q : out std_logic -- New clock enable output
);
end slib_clock_div;
architecture rtl of slib_clock_div is
-- Signals
signal iQ : std_logic; -- Internal Q
signal iCounter : integer range 0 to RATIO-1; -- Counter
begin
-- Main process
CD_PROC: process (RST, CLK)
begin
if (RST = '1') then
iCounter <= 0;
iQ <= '0';
elsif (CLK'event and CLK='1') then
iQ <= '0';
if (CE = '1') then
if (iCounter = (RATIO-1)) then
iQ <= '1';
iCounter <= 0;
else
iCounter <= iCounter + 1;
end if;
end if;
end if;
end process;
-- Output signals
Q <= iQ;
end rtl;
|
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - sergeykhbr@gmail.com
--! @brief Clock phase offset generator (90 deg) for Kintex7 FPGA.
------------------------------------------------------------------------------
--! Standard library
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity clkp90_kintex7 is
generic (
freq : integer := 125000
);
port (
--! Active High
i_rst : in std_logic;
i_clk : in std_logic;
o_clk : out std_logic;
o_clkp90 : out std_logic;
o_clk2x : out std_logic;
o_lock : out std_logic
);
end clkp90_kintex7;
architecture rtl of clkp90_kintex7 is
constant clk_mul : integer := 8;
constant clk_div : integer := 8;
constant period : real := 1000000.0/real(freq);
constant clkio_div : integer := freq*clk_mul/200000;
signal CLKFBOUT : std_logic;
signal CLKFBIN : std_logic;
signal clk_nobuf : std_logic;
signal clk90_nobuf : std_logic;
signal clkio_nobuf : std_logic;
begin
CLKFBIN <= CLKFBOUT;
PLLE2_ADV_inst : PLLE2_ADV generic map (
BANDWIDTH => "OPTIMIZED", -- OPTIMIZED, HIGH, LOW
CLKFBOUT_MULT => clk_mul, -- Multiply value for all CLKOUT, (2-64)
CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB, (-360.000-360.000).
-- CLKIN_PERIOD: Input clock period in nS to ps resolution (i.e. 33.333 is 30 MHz).
CLKIN1_PERIOD => period,
CLKIN2_PERIOD => 0.0,
-- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for CLKOUT (1-128)
CLKOUT0_DIVIDE => clk_div,
CLKOUT1_DIVIDE => clk_div,
CLKOUT2_DIVIDE => clkio_div,
CLKOUT3_DIVIDE => 1,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
-- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for CLKOUT outputs (0.001-0.999).
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT2_DUTY_CYCLE => 0.5,
CLKOUT3_DUTY_CYCLE => 0.5,
CLKOUT4_DUTY_CYCLE => 0.5,
CLKOUT5_DUTY_CYCLE => 0.5,
-- CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for CLKOUT outputs (-360.000-360.000).
CLKOUT0_PHASE => 0.0,
CLKOUT1_PHASE => 90.0,
CLKOUT2_PHASE => 0.0,
CLKOUT3_PHASE => 0.0,
CLKOUT4_PHASE => 0.0,
CLKOUT5_PHASE => 0.0,
COMPENSATION => "ZHOLD", -- ZHOLD, BUF_IN, EXTERNAL, INTERNAL
DIVCLK_DIVIDE => 1, -- Master division value (1-56)
-- REF_JITTER: Reference input jitter in UI (0.000-0.999).
REF_JITTER1 => 0.0,
REF_JITTER2 => 0.0,
STARTUP_WAIT => "TRUE" -- Delay DONE until PLL Locks, ("TRUE"/"FALSE")
) port map (
-- Clock Outputs: 1-bit (each) output: User configurable clock outputs
CLKOUT0 => clk_nobuf,
CLKOUT1 => clk90_nobuf,
CLKOUT2 => clkio_nobuf,
CLKOUT3 => OPEN,
CLKOUT4 => OPEN,
CLKOUT5 => OPEN,
-- DRP Ports: 16-bit (each) output: Dynamic reconfigration ports
DO => OPEN,
DRDY => OPEN,
-- Feedback Clocks: 1-bit (each) output: Clock feedback ports
CLKFBOUT => CLKFBOUT,
-- Status Ports: 1-bit (each) output: PLL status ports
LOCKED => o_lock,
-- Clock Inputs: 1-bit (each) input: Clock inputs
CLKIN1 => i_clk,
CLKIN2 => '0',
-- Con trol Ports: 1-bit (each) input: PLL control ports
CLKINSEL => '1',
PWRDWN => '0',
RST => i_rst,
-- DRP Ports: 7-bit (each) input: Dynamic reconfigration ports
DADDR => "0000000",
DCLK => '0',
DEN => '0',
DI => "0000000000000000",
DWE => '0',
-- Feedback Clocks: 1-bit (each) input: Clock feedback ports
CLKFBIN => CLKFBIN
);
bufgclk0 : BUFG port map (I => clk_nobuf, O => o_clk);
bufgclk90 : BUFG port map (I => clk90_nobuf, O => o_clkp90);
bufgclkio : BUFG port map (I => clkio_nobuf, O => o_clk2x);
end;
|
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - sergeykhbr@gmail.com
--! @brief Clock phase offset generator (90 deg) for Kintex7 FPGA.
------------------------------------------------------------------------------
--! Standard library
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity clkp90_kintex7 is
generic (
freq : integer := 125000
);
port (
--! Active High
i_rst : in std_logic;
i_clk : in std_logic;
o_clk : out std_logic;
o_clkp90 : out std_logic;
o_clk2x : out std_logic;
o_lock : out std_logic
);
end clkp90_kintex7;
architecture rtl of clkp90_kintex7 is
constant clk_mul : integer := 8;
constant clk_div : integer := 8;
constant period : real := 1000000.0/real(freq);
constant clkio_div : integer := freq*clk_mul/200000;
signal CLKFBOUT : std_logic;
signal CLKFBIN : std_logic;
signal clk_nobuf : std_logic;
signal clk90_nobuf : std_logic;
signal clkio_nobuf : std_logic;
begin
CLKFBIN <= CLKFBOUT;
PLLE2_ADV_inst : PLLE2_ADV generic map (
BANDWIDTH => "OPTIMIZED", -- OPTIMIZED, HIGH, LOW
CLKFBOUT_MULT => clk_mul, -- Multiply value for all CLKOUT, (2-64)
CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB, (-360.000-360.000).
-- CLKIN_PERIOD: Input clock period in nS to ps resolution (i.e. 33.333 is 30 MHz).
CLKIN1_PERIOD => period,
CLKIN2_PERIOD => 0.0,
-- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for CLKOUT (1-128)
CLKOUT0_DIVIDE => clk_div,
CLKOUT1_DIVIDE => clk_div,
CLKOUT2_DIVIDE => clkio_div,
CLKOUT3_DIVIDE => 1,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
-- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for CLKOUT outputs (0.001-0.999).
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT2_DUTY_CYCLE => 0.5,
CLKOUT3_DUTY_CYCLE => 0.5,
CLKOUT4_DUTY_CYCLE => 0.5,
CLKOUT5_DUTY_CYCLE => 0.5,
-- CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for CLKOUT outputs (-360.000-360.000).
CLKOUT0_PHASE => 0.0,
CLKOUT1_PHASE => 90.0,
CLKOUT2_PHASE => 0.0,
CLKOUT3_PHASE => 0.0,
CLKOUT4_PHASE => 0.0,
CLKOUT5_PHASE => 0.0,
COMPENSATION => "ZHOLD", -- ZHOLD, BUF_IN, EXTERNAL, INTERNAL
DIVCLK_DIVIDE => 1, -- Master division value (1-56)
-- REF_JITTER: Reference input jitter in UI (0.000-0.999).
REF_JITTER1 => 0.0,
REF_JITTER2 => 0.0,
STARTUP_WAIT => "TRUE" -- Delay DONE until PLL Locks, ("TRUE"/"FALSE")
) port map (
-- Clock Outputs: 1-bit (each) output: User configurable clock outputs
CLKOUT0 => clk_nobuf,
CLKOUT1 => clk90_nobuf,
CLKOUT2 => clkio_nobuf,
CLKOUT3 => OPEN,
CLKOUT4 => OPEN,
CLKOUT5 => OPEN,
-- DRP Ports: 16-bit (each) output: Dynamic reconfigration ports
DO => OPEN,
DRDY => OPEN,
-- Feedback Clocks: 1-bit (each) output: Clock feedback ports
CLKFBOUT => CLKFBOUT,
-- Status Ports: 1-bit (each) output: PLL status ports
LOCKED => o_lock,
-- Clock Inputs: 1-bit (each) input: Clock inputs
CLKIN1 => i_clk,
CLKIN2 => '0',
-- Con trol Ports: 1-bit (each) input: PLL control ports
CLKINSEL => '1',
PWRDWN => '0',
RST => i_rst,
-- DRP Ports: 7-bit (each) input: Dynamic reconfigration ports
DADDR => "0000000",
DCLK => '0',
DEN => '0',
DI => "0000000000000000",
DWE => '0',
-- Feedback Clocks: 1-bit (each) input: Clock feedback ports
CLKFBIN => CLKFBIN
);
bufgclk0 : BUFG port map (I => clk_nobuf, O => o_clk);
bufgclk90 : BUFG port map (I => clk90_nobuf, O => o_clkp90);
bufgclkio : BUFG port map (I => clkio_nobuf, O => o_clk2x);
end;
|
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - sergeykhbr@gmail.com
--! @brief Clock phase offset generator (90 deg) for Kintex7 FPGA.
------------------------------------------------------------------------------
--! Standard library
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity clkp90_kintex7 is
generic (
freq : integer := 125000
);
port (
--! Active High
i_rst : in std_logic;
i_clk : in std_logic;
o_clk : out std_logic;
o_clkp90 : out std_logic;
o_clk2x : out std_logic;
o_lock : out std_logic
);
end clkp90_kintex7;
architecture rtl of clkp90_kintex7 is
constant clk_mul : integer := 8;
constant clk_div : integer := 8;
constant period : real := 1000000.0/real(freq);
constant clkio_div : integer := freq*clk_mul/200000;
signal CLKFBOUT : std_logic;
signal CLKFBIN : std_logic;
signal clk_nobuf : std_logic;
signal clk90_nobuf : std_logic;
signal clkio_nobuf : std_logic;
begin
CLKFBIN <= CLKFBOUT;
PLLE2_ADV_inst : PLLE2_ADV generic map (
BANDWIDTH => "OPTIMIZED", -- OPTIMIZED, HIGH, LOW
CLKFBOUT_MULT => clk_mul, -- Multiply value for all CLKOUT, (2-64)
CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB, (-360.000-360.000).
-- CLKIN_PERIOD: Input clock period in nS to ps resolution (i.e. 33.333 is 30 MHz).
CLKIN1_PERIOD => period,
CLKIN2_PERIOD => 0.0,
-- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for CLKOUT (1-128)
CLKOUT0_DIVIDE => clk_div,
CLKOUT1_DIVIDE => clk_div,
CLKOUT2_DIVIDE => clkio_div,
CLKOUT3_DIVIDE => 1,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
-- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for CLKOUT outputs (0.001-0.999).
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT2_DUTY_CYCLE => 0.5,
CLKOUT3_DUTY_CYCLE => 0.5,
CLKOUT4_DUTY_CYCLE => 0.5,
CLKOUT5_DUTY_CYCLE => 0.5,
-- CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for CLKOUT outputs (-360.000-360.000).
CLKOUT0_PHASE => 0.0,
CLKOUT1_PHASE => 90.0,
CLKOUT2_PHASE => 0.0,
CLKOUT3_PHASE => 0.0,
CLKOUT4_PHASE => 0.0,
CLKOUT5_PHASE => 0.0,
COMPENSATION => "ZHOLD", -- ZHOLD, BUF_IN, EXTERNAL, INTERNAL
DIVCLK_DIVIDE => 1, -- Master division value (1-56)
-- REF_JITTER: Reference input jitter in UI (0.000-0.999).
REF_JITTER1 => 0.0,
REF_JITTER2 => 0.0,
STARTUP_WAIT => "TRUE" -- Delay DONE until PLL Locks, ("TRUE"/"FALSE")
) port map (
-- Clock Outputs: 1-bit (each) output: User configurable clock outputs
CLKOUT0 => clk_nobuf,
CLKOUT1 => clk90_nobuf,
CLKOUT2 => clkio_nobuf,
CLKOUT3 => OPEN,
CLKOUT4 => OPEN,
CLKOUT5 => OPEN,
-- DRP Ports: 16-bit (each) output: Dynamic reconfigration ports
DO => OPEN,
DRDY => OPEN,
-- Feedback Clocks: 1-bit (each) output: Clock feedback ports
CLKFBOUT => CLKFBOUT,
-- Status Ports: 1-bit (each) output: PLL status ports
LOCKED => o_lock,
-- Clock Inputs: 1-bit (each) input: Clock inputs
CLKIN1 => i_clk,
CLKIN2 => '0',
-- Con trol Ports: 1-bit (each) input: PLL control ports
CLKINSEL => '1',
PWRDWN => '0',
RST => i_rst,
-- DRP Ports: 7-bit (each) input: Dynamic reconfigration ports
DADDR => "0000000",
DCLK => '0',
DEN => '0',
DI => "0000000000000000",
DWE => '0',
-- Feedback Clocks: 1-bit (each) input: Clock feedback ports
CLKFBIN => CLKFBIN
);
bufgclk0 : BUFG port map (I => clk_nobuf, O => o_clk);
bufgclk90 : BUFG port map (I => clk90_nobuf, O => o_clkp90);
bufgclkio : BUFG port map (I => clkio_nobuf, O => o_clk2x);
end;
|
--------------------------------------------------------------------------------
-- FILE: tbDiv
-- DESC: Testbench for Divider
--
-- Author:
-- Create: 2015-09-10
-- Update: 2015-09-10
-- Status: UNTESTED
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.Consts.all;
--------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------
entity tbDiv is
end tbDiv;
--------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------
architecture behav of tbDiv is
constant N: integer :=32;
constant S: integer :=10;
signal clk: std_logic := '0';
signal rst: std_logic := '1';
signal en: std_logic:='0';
signal ia: std_logic_vector(N-1 downto 0):=x"00000000";
signal ib: std_logic_vector(N-1 downto 0):=x"00000000";
signal oy: std_logic_vector(N-1 downto 0):=x"00000000";
component Div is
generic (
DATA_SIZE : integer := C_SYS_DATA_SIZE;
STAGE : integer := C_DIV_STAGE
);
port (
rst: in std_logic;
clk: in std_logic;
en: in std_logic:='0';
a : in std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0'); -- Data A
b : in std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0'); -- Data B
o : out std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0') -- Data Out
);
end component;
begin
DIV0: Div
generic map (N, S)
port map (rst, clk, en, ia, ib, oy);
-- Clock generator
PCLOCK : process(clk)
begin
clk <= not(clk) after 0.5 ns;
end process;
-- Reset test
rst <= '0', '1' after 2 ns;
en <= '0', '1' after 3 ns, '0' after 15 ns;
ia<=x"00000000", x"ff05070e" after 1 ns;
ib<=x"00000001", x"244398fe" after 1 ns;
end behav;
configuration tb_div_cfg of tbDiv is
for behav
end for;
end tb_div_cfg;
|
architecture RTL of FIFO is
begin
process
begin
loop
end loop;
-- Violations below
loop
end loop;
end process;
end;
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "WhiteNoise"
-- Project :
-------------------------------------------------------------------------------
-- File : WhiteNoise_tb.vhd
-- Author : <fxst@FXST-PC>
-- Company :
-- Created : 2017-12-12
-- Last update: 2017-12-12
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2017
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2017-12-12 1.0 fxst Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.Global.all;
-------------------------------------------------------------------------------
entity WhiteNoise_tb is
end entity WhiteNoise_tb;
-------------------------------------------------------------------------------
architecture bhv of WhiteNoise_tb is
constant strobe_time : time := 1 sec/real(44117);
-- component generics
constant data_width_g : natural := 24;
constant lfsr_length_g : natural := 24;
-- component ports
signal csi_clk : std_logic := '1';
signal rsi_reset_n : std_logic;
signal coe_sample_strobe : std_logic;
signal avs_s0_write : std_logic;
signal avs_s0_writedata : std_logic_vector(31 downto 0);
signal aso_data : std_logic_vector(data_width_g-1 downto 0);
signal aso_valid : std_logic;
begin -- architecture bhv
-- component instantiation
DUT: entity work.WhiteNoise
generic map (
data_width_g => data_width_g,
lfsr_length_g => lfsr_length_g)
port map (
csi_clk => csi_clk,
rsi_reset_n => rsi_reset_n,
coe_sample_strobe => coe_sample_strobe,
avs_s0_write => avs_s0_write,
avs_s0_writedata => avs_s0_writedata,
aso_data => aso_data,
aso_valid => aso_valid);
-- clock generation
csi_clk <= not csi_clk after 10 ns;
-- sample strobe generation
sample_strobe : process is
begin -- process
wait for strobe_time;
wait until rising_edge(csi_clk);
coe_sample_strobe <= '1';
wait until rising_edge(csi_clk);
coe_sample_strobe <= '0';
end process;
-- waveform generation
WaveGen_Proc: process
begin
rsi_reset_n <= '0' after 0 ns,
'1' after 40 ns;
avs_s0_write <= '0';
avs_s0_writedata <= (others => '-');
wait for 100 ns;
-- enable
avs_s0_write <= '1';
avs_s0_writedata(0) <= '1';
wait until rising_edge(csi_clk);
avs_s0_write <= '0';
avs_s0_writedata(0) <= '-';
wait for 50000 ns;
-- disable
avs_s0_write <= '1';
avs_s0_writedata(0) <= '0';
wait until rising_edge(csi_clk);
avs_s0_write <= '0';
avs_s0_writedata(0) <= '-';
wait for 50000 ns;
-- enable
avs_s0_write <= '1';
avs_s0_writedata(0) <= '1';
wait until rising_edge(csi_clk);
avs_s0_write <= '0';
avs_s0_writedata(0) <= '-';
wait;
end process WaveGen_Proc;
end architecture bhv;
|
------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2013 Aeroflex Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.ddrpkg.all;
--pragma translate_off
use gaisler.sim.all;
library unisim;
use unisim.BUFG;
use unisim.PLLE2_ADV;
use unisim.STARTUPE2;
--pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
library testgrouppolito;
use testgrouppolito.dprc_pkg.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
SIM_BYPASS_INIT_CAL : string := "OFF";
SIMULATION : string := "FALSE";
USE_MIG_INTERFACE_MODEL : boolean := false
);
port (
sys_clk_i : in std_ulogic;
-- onBoard DDR2
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_ulogic;
ddr2_cas_n : out std_ulogic;
ddr2_we_n : out std_ulogic;
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0);
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
-- SPI
QspiCSn : out std_ulogic;
QspiDB : inout std_logic_vector(3 downto 0);
--pragma translate_off
QspiClk : out std_ulogic;
--pragma translate_on
-- 7 segment display
--seg : out std_logic_vector(6 downto 0);
--an : out std_logic_vector(7 downto 0);
-- LEDs
Led : out std_logic_vector(15 downto 0);
-- Switches
sw : in std_logic_vector(15 downto 0);
-- Buttons
btnCpuResetn : in std_ulogic;
btn : in std_logic_vector(4 downto 0);
-- VGA Connector
--vgaRed : out std_logic_vector(2 downto 0);
--vgaGreen : out std_logic_vector(2 downto 0);
--vgaBlue : out std_logic_vector(2 downto 1);
--Hsync : out std_ulogic;
--Vsync : out std_ulogic;
-- 12 pin connectors
--ja : inout std_logic_vector(7 downto 0);
--jb : inout std_logic_vector(7 downto 0);
--jc : inout std_logic_vector(7 downto 0);
--jd : inout std_logic_vector(7 downto 0);
-- SMSC ethernet PHY
eth_rstn : out std_ulogic;
eth_crsdv : in std_ulogic;
eth_refclk : out std_ulogic;
eth_txd : out std_logic_vector(1 downto 0);
eth_txen : out std_ulogic;
eth_rxd : in std_logic_vector(1 downto 0);
eth_rxerr : in std_ulogic;
eth_mdc : out std_ulogic;
eth_mdio : inout std_logic;
-- Pic USB-HID interface
--~ PS2KeyboardData : inout std_logic;
--~ PS2KeyboardClk : inout std_logic;
--~ PS2MouseData : inout std_logic;
--~ PS2MouseClk : inout std_logic;
--~ PicGpio : out std_logic_vector(1 downto 0);
-- USB-RS232 interface
uart_txd_in : in std_logic;
uart_rxd_out : out std_logic);
end;
architecture rtl of leon3mp is
component PLLE2_ADV
generic (
BANDWIDTH : string := "OPTIMIZED";
CLKFBOUT_MULT : integer := 5;
CLKFBOUT_PHASE : real := 0.0;
CLKIN1_PERIOD : real := 0.0;
CLKIN2_PERIOD : real := 0.0;
CLKOUT0_DIVIDE : integer := 1;
CLKOUT0_DUTY_CYCLE : real := 0.5;
CLKOUT0_PHASE : real := 0.0;
CLKOUT1_DIVIDE : integer := 1;
CLKOUT1_DUTY_CYCLE : real := 0.5;
CLKOUT1_PHASE : real := 0.0;
CLKOUT2_DIVIDE : integer := 1;
CLKOUT2_DUTY_CYCLE : real := 0.5;
CLKOUT2_PHASE : real := 0.0;
CLKOUT3_DIVIDE : integer := 1;
CLKOUT3_DUTY_CYCLE : real := 0.5;
CLKOUT3_PHASE : real := 0.0;
CLKOUT4_DIVIDE : integer := 1;
CLKOUT4_DUTY_CYCLE : real := 0.5;
CLKOUT4_PHASE : real := 0.0;
CLKOUT5_DIVIDE : integer := 1;
CLKOUT5_DUTY_CYCLE : real := 0.5;
CLKOUT5_PHASE : real := 0.0;
COMPENSATION : string := "ZHOLD";
DIVCLK_DIVIDE : integer := 1;
REF_JITTER1 : real := 0.0;
REF_JITTER2 : real := 0.0;
STARTUP_WAIT : string := "FALSE"
);
port (
CLKFBOUT : out std_ulogic := '0';
CLKOUT0 : out std_ulogic := '0';
CLKOUT1 : out std_ulogic := '0';
CLKOUT2 : out std_ulogic := '0';
CLKOUT3 : out std_ulogic := '0';
CLKOUT4 : out std_ulogic := '0';
CLKOUT5 : out std_ulogic := '0';
DO : out std_logic_vector (15 downto 0);
DRDY : out std_ulogic := '0';
LOCKED : out std_ulogic := '0';
CLKFBIN : in std_ulogic;
CLKIN1 : in std_ulogic;
CLKIN2 : in std_ulogic;
CLKINSEL : in std_ulogic;
DADDR : in std_logic_vector(6 downto 0);
DCLK : in std_ulogic;
DEN : in std_ulogic;
DI : in std_logic_vector(15 downto 0);
DWE : in std_ulogic;
PWRDWN : in std_ulogic;
RST : in std_ulogic
);
end component;
component STARTUPE2
generic (
PROG_USR : string := "FALSE";
SIM_CCLK_FREQ : real := 0.0
);
port (
CFGCLK : out std_ulogic;
CFGMCLK : out std_ulogic;
EOS : out std_ulogic;
PREQ : out std_ulogic;
CLK : in std_ulogic;
GSR : in std_ulogic;
GTS : in std_ulogic;
KEYCLEARB : in std_ulogic;
PACK : in std_ulogic;
USRCCLKO : in std_ulogic;
USRCCLKTS : in std_ulogic;
USRDONEO : in std_ulogic;
USRDONETS : in std_ulogic
);
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
component ahb2mig_7series_ddr2_dq16_ad13_ba3
generic(
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
SIM_BYPASS_INIT_CAL : string := "OFF";
SIMULATION : string := "FALSE";
USE_MIG_INTERFACE_MODEL : boolean := false);
port(
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0);
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_reset_n : out std_logic;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
calib_done : out std_logic;
rst_n_syn : in std_logic;
rst_n_async : in std_logic;
clk_amba : in std_logic;
sys_clk_i : in std_logic;
clk_ref_i : in std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic);
end component ;
-- pragma translate_off
component ahbram_sim
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := DEFMEMTECH;
kbytes : integer := 1;
pipe : integer := 0;
maccsz : integer := AHBDW;
fname : string := "ram.dat"
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end component ;
-- pragma translate_on
signal CLKFBOUT : std_logic;
signal CLKFBIN : std_logic;
signal eth_pll_rst : std_logic;
signal eth_clk_nobuf : std_logic;
signal eth_clk90_nobuf : std_logic;
signal eth_clk : std_logic;
signal eth_clk90 : std_logic;
signal vcc : std_logic;
signal gnd : std_logic;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal cgi : clkgen_in_type;
signal cgo, cgo1 : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ndsuact : std_ulogic;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal gpti : gptimer_in_type;
signal spii : spi_in_type;
signal spio : spi_out_type;
signal spmi : spimctrl_in_type;
signal spmo : spimctrl_out_type;
signal clkm : std_ulogic
-- pragma translate_off
:= '0'
-- pragma translate_on
;
signal clkm2x, clk200, clkfb, pllrst, rstn, clkml : std_ulogic;
signal tck, tms, tdi, tdo : std_ulogic;
signal rstraw : std_logic;
signal btnCpuReset : std_logic;
signal lock, lock0 : std_logic;
signal clkinmig : std_logic;
signal ddr0_clkv : std_logic_vector(2 downto 0);
signal ddr0_clkbv : std_logic_vector(2 downto 0);
signal ddr0_cke : std_logic_vector(1 downto 0);
signal ddr0_csb : std_logic_vector(1 downto 0);
signal ddr0_odt : std_logic_vector(1 downto 0);
signal ddr0_addr : std_logic_vector(13 downto 0);
signal ddr0_clk_fb : std_logic;
signal clkref, calib_done, migrstn : std_logic;
-- RS232 APB Uart
signal rxd1 : std_logic;
signal txd1 : std_logic;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of lock : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_keep of clkm : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute keep of lock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
constant BOARD_FREQ : integer := 100000; -- CLK input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
----------------------------------------------------------------------
--- FIR component declaration --------------------------------------
----------------------------------------------------------------------
component fir_ahb_dma_apb is
generic (
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
technology : integer := virtex4);
port (
clk : in std_logic;
rstn : in std_logic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbin : in ahb_mst_in_type;
ahbout : out ahb_mst_out_type;
rm_reset: in std_logic
);
end component;
signal rm_reset : std_logic_vector(31 downto 0);
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1';
gnd <= '0';
led(15 downto 6) <= (others =>'0'); -- unused leds off
btnCpuReset<= not btnCpuResetn;
cgi.pllctrl <= "00";
cgi.pllrst <= rstraw;
pllrst <= not cgi.pllrst;
rst0 : rstgen generic map (acthigh => 1)
port map (btnCpuReset, clkm, lock, rstn, rstraw);
lock <= calib_done when CFG_MIG_7SERIES = 1 else cgo.clklock and lock0;
led(4) <= lock;
led(5) <= lock0;
rst1 : rstgen -- reset generator
generic map (acthigh => 1)
port map (btnCpuReset, clkm, lock, migrstn, open);
-- clock generator
clkgen_gen: if (CFG_MIG_7SERIES = 0) generate
clkgen0 : clkgen
generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (sys_clk_i, gnd, clkm, open, clkm2x, open, open, cgi, cgo, open, open, open);
end generate;
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_PRC*2,
nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
-- LEON3 processor
leon3gen : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR,
CFG_NCPU-1, CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
led(3) <= not dbgo(0).error;
led(2) <= not dsuo.active;
-- LEON3 Debug Support Unit
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#, ahbpf => CFG_AHBPF,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
--dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsui.enable <= '1';
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
-- Debug UART
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (uart_txd_in, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (uart_rxd_out, duo.txd);
led(0) <= not dui.rxd;
led(1) <= not duo.txd;
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd);
end generate;
----------------------------------------------------------------------
--- DDR2 Memory controller ------------------------------------------
----------------------------------------------------------------------
ddr2gen: if (CFG_DDR2SP = 1) and (CFG_MIG_7SERIES = 0) generate
ddrc : ddr2spa generic map (fabtech => fabtech, memtech => memtech,
hindex => 5, haddr => 16#400#, hmask => 16#F80#, ioaddr => 1, rstdel => 200, -- iomask generic default value
MHz => CPU_FREQ/1000, TRFC => CFG_DDR2SP_TRFC, clkmul => 12,
clkdiv => 6, col => CFG_DDR2SP_COL, Mbyte => CFG_DDR2SP_SIZE,
pwron => CFG_DDR2SP_INIT, ddrbits => CFG_DDR2SP_DATAWIDTH, raspipe => 0,
ahbfreq => CPU_FREQ/1000, readdly => 0, rskew => 0, oepol => 0,
ddelayb0 => CFG_DDR2SP_DELAY0, ddelayb1 => CFG_DDR2SP_DELAY1,
ddelayb2 => CFG_DDR2SP_DELAY2, ddelayb3 => CFG_DDR2SP_DELAY3,
ddelayb4 => CFG_DDR2SP_DELAY4, ddelayb5 => CFG_DDR2SP_DELAY5,
ddelayb6 => CFG_DDR2SP_DELAY6, ddelayb7 => CFG_DDR2SP_DELAY7, -- cbdelayb0-3 generics not used in non-ft mode
numidelctrl => 1, norefclk => 1, -- dqsse, ahbbits, bigmem, nclk, scantest and octen default
nosync => CFG_DDR2SP_NOSYNC, eightbanks => 1, odten => 3, dqsgating => 0,
burstlen => 8, ft => CFG_DDR2SP_FTEN, ftbits => CFG_DDR2SP_FTWIDTH)
port map (
btnCpuResetn, rstn, clkm, clkm, clkm, lock0, clkml, clkml, ahbsi, ahbso(5),
ddr0_clkv, ddr0_clkbv, ddr0_clk_fb, ddr0_clk_fb,
ddr0_cke, ddr0_csb, ddr2_we_n, ddr2_ras_n, ddr2_cas_n,
ddr2_dm, ddr2_dqs_p, ddr2_dqs_n, ddr0_addr, ddr2_ba, ddr2_dq, ddr0_odt,open);
ddr2_addr <= ddr0_addr(12 downto 0);
ddr2_cke <= ddr0_cke(0 downto 0);
ddr2_cs_n <= ddr0_csb(0 downto 0);
ddr2_ck_p(0) <= ddr0_clkv(0);
ddr2_ck_n(0) <= ddr0_clkbv(0);
ddr2_odt <= ddr0_odt(0 downto 0);
end generate;
noddr2 : if (CFG_DDR2SP = 0) and (CFG_MIG_7SERIES = 0) generate lock0 <= '1'; end generate;
mig_gen : if (CFG_DDR2SP = 0) and (CFG_MIG_7SERIES = 1) generate
gen_mig : if (USE_MIG_INTERFACE_MODEL /= true) generate
ddrc : ahb2mig_7series_ddr2_dq16_ad13_ba3 generic map(
hindex => 5, haddr => 16#400#, hmask => 16#F80#, pindex => 5, paddr => 5,
SIM_BYPASS_INIT_CAL => SIM_BYPASS_INIT_CAL, SIMULATION => SIMULATION, USE_MIG_INTERFACE_MODEL => USE_MIG_INTERFACE_MODEL)
port map(
ddr2_dq => ddr2_dq,
ddr2_dqs_p => ddr2_dqs_p,
ddr2_dqs_n => ddr2_dqs_n,
ddr2_addr => ddr2_addr,
ddr2_ba => ddr2_ba,
ddr2_ras_n => ddr2_ras_n,
ddr2_cas_n => ddr2_cas_n,
ddr2_we_n => ddr2_we_n,
ddr2_reset_n => open,
ddr2_ck_p => ddr2_ck_p,
ddr2_ck_n => ddr2_ck_n,
ddr2_cke => ddr2_cke,
ddr2_cs_n => ddr2_cs_n,
ddr2_dm => ddr2_dm,
ddr2_odt => ddr2_odt,
ahbsi => ahbsi,
ahbso => ahbso(5),
apbi => apbi,
apbo => apbo(5),
calib_done => calib_done,
rst_n_syn => migrstn,
rst_n_async => cgo1.clklock,--rstraw,
clk_amba => clkm,
sys_clk_i => clkinmig,
clk_ref_i => clkref,
ui_clk => clkm, -- 70 MHz clk , DDR at 280 MHz (560 Mbps)
ui_clk_sync_rst => open);
clkgenmigref0 : clkgen
generic map (clktech, 16, 8, 0,CFG_CLK_NOFB, 0, 0, 0, 100000)
port map (sys_clk_i, sys_clk_i, clkref, open, open, open, open, cgi, cgo, open, open, open);
clkgenmigin : clkgen
generic map (clktech, 14, 20, 0,CFG_CLK_NOFB, 0, 0, 0, 100000)
port map (sys_clk_i, sys_clk_i, clkinmig, open, open, open, open, cgi, cgo1, open, open, open);
end generate gen_mig;
gen_mig_model : if (USE_MIG_INTERFACE_MODEL = true) generate
-- pragma translate_off
mig_ahbram : ahbram_sim
generic map (
hindex => 5,
haddr => 16#400#,
hmask => 16#F80#,
tech => 0,
kbytes => 1000,
pipe => 0,
maccsz => AHBDW,
fname => "ram.srec"
)
port map(
rst => rstn,
clk => clkm,
ahbsi => ahbsi,
ahbso => ahbso(5)
);
ddr2_dq <= (others => 'Z');
ddr2_dqs_p <= (others => 'Z');
ddr2_dqs_n <= (others => 'Z');
ddr2_addr <= (others => '0');
ddr2_ba <= (others => '0');
ddr2_ras_n <= '0';
ddr2_cas_n <= '0';
ddr2_we_n <= '0';
ddr2_ck_p <= (others => '0');
ddr2_ck_n <= (others => '0');
ddr2_cke <= (others => '0');
ddr2_cs_n <= (others => '0');
ddr2_dm <= (others => '0');
ddr2_odt <= (others => '0');
--calib_done : out std_logic;
calib_done <= '1';
--ui_clk : out std_logic;
clkm <= not clkm after 13.333 ns;
--ui_clk_sync_rst : out std_logic
-- n/a
-- pragma translate_on
end generate gen_mig_model; end generate;
----------------------------------------------------------------------
--- SPI Memory controller -------------------------------------------
----------------------------------------------------------------------
spi_gen: if CFG_SPIMCTRL = 1 generate
-- OPTIONALY set the offset generic (only affect reads).
-- The first 4MB are used for loading the FPGA.
-- For dual ouptut: readcmd => 16#3B#, dualoutput => 1
spimctrl1 : spimctrl
generic map (hindex => 7, hirq => 7, faddr => 16#000#, fmask => 16#ff0#,
ioaddr => 16#700#, iomask => 16#fff#, spliten => CFG_SPLIT,
sdcard => CFG_SPIMCTRL_SDCARD, readcmd => CFG_SPIMCTRL_READCMD, dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => CFG_SPIMCTRL_DUALOUTPUT, scaler => CFG_SPIMCTRL_SCALER, altscaler => CFG_SPIMCTRL_ASCALER)
port map (rstn, clkm, ahbsi, ahbso(7), spmi, spmo);
QspiDB(3) <= '1'; QspiDB(2) <= '1';
-- spi_bdr : iopad generic map (tech => padtech)
-- port map (QspiDB(0), spmo.mosi, spmo.mosioen, spmi.mosi);
spi_mosi_pad : outpad generic map (tech => padtech)
port map (QspiDB(0), spmo.mosi);
spi_miso_pad : inpad generic map (tech => padtech)
port map (QspiDB(1), spmi.miso);
spi_slvsel0_pad : outpad generic map (tech => padtech)
port map (QspiCSn, spmo.csn);
-- MACRO for assigning the SPI output clock
spicclk: STARTUPE2
port map (--CFGCLK => open, CFGMCLK => open, EOS => open, PREQ => open,
CLK => '0', GSR => '0', GTS => '0', KEYCLEARB => '0', PACK => '0',
USRCCLKO => spmo.sck, USRCCLKTS => '0', USRDONEO => '1', USRDONETS => '0' );
--pragma translate_off
QspiClk <= spmo.sck;
--pragma translate_on
end generate;
nospi: if CFG_SPIMCTRL = 0 generate
ahbso(7) <= ahbs_none;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
-- APB Bridge
apb0 : apbctrl
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
-- Interrupt controller
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
-- Time Unit
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW,
ntimers => CFG_GPT_NTIM, nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop;
gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1;
u1i.ctsn <= '0';
u1i.extclk <= '0';
txd1 <= u1o.txd;
-- serrx_pad : inpad generic map (tech => padtech) port map (dsurx, rxd1);
-- sertx_pad : outpad generic map (tech => padtech) port map (dsutx, txd1);
-- led(0) <= not rxd1;
-- led(1) <= not txd1;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm
generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 15, paddr => 15, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 1,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G, rmii => 1)
port map(rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
apbi => apbi, apbo => apbo(15), ethi => ethi, etho => etho);
eth_rstn<=rstn;
end generate;
etxc_pad : outpad generic map (tech => padtech)
port map (eth_refclk, eth_clk);
ethpads : if (CFG_GRETH = 1) generate
emdio_pad : iopad generic map (tech => padtech)
port map (eth_mdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
ethi.rmii_clk<=eth_clk90;
erxd_pad : inpadv generic map (tech => padtech, width => 2) --8
port map (eth_rxd, ethi.rxd(1 downto 0));
erxer_pad : inpad generic map (tech => padtech)
port map (eth_rxerr, ethi.rx_er);
erxcr_pad : inpad generic map (tech => padtech)
port map (eth_crsdv, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 2)
port map (eth_txd, etho.txd(1 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (eth_txen, etho.tx_en);
emdc_pad : outpad generic map (tech => padtech)
port map (eth_mdc, etho.mdc);
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram
generic map (hindex => 3, haddr => CFG_AHBRADDR, tech => CFG_MEMTECH,
kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- DYNAMIC PARTIAL RECONFIGURATION ---------------------------------
-----------------------------------------------------------------------
prc : if CFG_PRC = 1 generate
p1 : dprc generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH, pindex => 14, paddr => 14, clk_sel => 1,
technology => CFG_FABTECH, crc_en => CFG_CRC_EN, words_block => CFG_WORDS_BLOCK, fifo_dcm_inst => CFG_DCM_FIFO, fifo_depth => CFG_DPR_FIFO)
port map(rstn => rstn, clkm => clkm, clkraw => '0', clk100 => sys_clk_i, ahbmi => ahbmi, ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH),
apbi => apbi, apbo => apbo(14), rm_reset => rm_reset);
--------------------------------------------------------------------
-- FIR component instantiation (for dprc demo) -------------------
--------------------------------------------------------------------
fir_ex : FIR_AHB_DMA_APB
generic map (hindex=>CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_PRC, pindex=>13, paddr=>13,
pmask=>16#fff#, technology =>CFG_FABTECH)
port map (rstn=>rstn, clk=>clkm, apbi=>apbi, apbo=>apbo(13), ahbin=>ahbmi,
ahbout=>ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_PRC), rm_reset => rm_reset(0));
end generate;
-----------------------------------------------------------------------
-- Test report module, only used for simulation ----------------------
-----------------------------------------------------------------------
--pragma translate_off
test0 : ahbrep generic map (hindex => 4, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(4));
--pragma translate_on
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_PRC*2+1) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Demonstration design for Digilent NEXYS 4 DDR board",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
-----------------------------------------------------------------------
--- Ethernet Clock Generation ---------------------------------------
-----------------------------------------------------------------------
ethclk : if CFG_GRETH = 1 generate
-- 50 MHz clock for output
bufgclk0 : BUFG port map (I => eth_clk_nobuf, O => eth_clk);
-- 50 MHz with +90 deg phase for Rx GRETH
bufgclk45 : BUFG port map (I => eth_clk90_nobuf, O => eth_clk90);
CLKFBIN <= CLKFBOUT;
eth_pll_rst <= not cgi.pllrst;
PLLE2_ADV_inst : PLLE2_ADV generic map (
BANDWIDTH => "OPTIMIZED", -- OPTIMIZED, HIGH, LOW
CLKFBOUT_MULT => 8, -- Multiply value for all CLKOUT, (2-64)
CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB, (-360.000-360.000).
-- CLKIN_PERIOD: Input clock period in nS to ps resolution (i.e. 33.333 is 30 MHz).
CLKIN1_PERIOD => 1000000.0/real(100000.0),
CLKIN2_PERIOD => 0.0,
-- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for CLKOUT (1-128)
CLKOUT0_DIVIDE => 16,
CLKOUT1_DIVIDE => 16,
CLKOUT2_DIVIDE => 1,
CLKOUT3_DIVIDE => 1,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
-- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for CLKOUT outputs (0.001-0.999).
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT2_DUTY_CYCLE => 0.5,
CLKOUT3_DUTY_CYCLE => 0.5,
CLKOUT4_DUTY_CYCLE => 0.5,
CLKOUT5_DUTY_CYCLE => 0.5,
-- CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for CLKOUT outputs (-360.000-360.000).
CLKOUT0_PHASE => 0.0,
CLKOUT1_PHASE => 90.0,
CLKOUT2_PHASE => 0.0,
CLKOUT3_PHASE => 0.0,
CLKOUT4_PHASE => 0.0,
CLKOUT5_PHASE => 0.0,
COMPENSATION => "ZHOLD", -- ZHOLD, BUF_IN, EXTERNAL, INTERNAL
DIVCLK_DIVIDE => 1, -- Master division value (1-56)
-- REF_JITTER: Reference input jitter in UI (0.000-0.999).
REF_JITTER1 => 0.0,
REF_JITTER2 => 0.0,
STARTUP_WAIT => "TRUE" -- Delay DONE until PLL Locks, ("TRUE"/"FALSE")
)
port map (
-- Clock Outputs: 1-bit (each) output: User configurable clock outputs
CLKOUT0 => eth_clk_nobuf,
CLKOUT1 => eth_clk90_nobuf,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
-- DRP Ports: 16-bit (each) output: Dynamic reconfigration ports
DO => open,
DRDY => open,
-- Feedback Clocks: 1-bit (each) output: Clock feedback ports
CLKFBOUT => CLKFBOUT,
-- Status Ports: 1-bit (each) output: PLL status ports
LOCKED => open,
-- Clock Inputs: 1-bit (each) input: Clock inputs
CLKIN1 => sys_clk_i,
CLKIN2 => '0',
-- Con trol Ports: 1-bit (each) input: PLL control ports
CLKINSEL => '1',
PWRDWN => '0',
RST => eth_pll_rst,
-- DRP Ports: 7-bit (each) input: Dynamic reconfigration ports
DADDR => "0000000",
DCLK => '0',
DEN => '0',
DI => "0000000000000000",
DWE => '0',
-- Feedback Clocks: 1-bit (each) input: Clock feedback ports
CLKFBIN => CLKFBIN
);
end generate;
end rtl;
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity planet_hot is
port(
clock: in std_logic;
input: in std_logic_vector(6 downto 0);
output: out std_logic_vector(18 downto 0)
);
end planet_hot;
architecture behaviour of planet_hot is
constant st0: std_logic_vector(47 downto 0) := "100000000000000000000000000000000000000000000000";
constant st1: std_logic_vector(47 downto 0) := "010000000000000000000000000000000000000000000000";
constant st2: std_logic_vector(47 downto 0) := "001000000000000000000000000000000000000000000000";
constant st3: std_logic_vector(47 downto 0) := "000100000000000000000000000000000000000000000000";
constant st4: std_logic_vector(47 downto 0) := "000010000000000000000000000000000000000000000000";
constant st42: std_logic_vector(47 downto 0) := "000001000000000000000000000000000000000000000000";
constant st5: std_logic_vector(47 downto 0) := "000000100000000000000000000000000000000000000000";
constant st6: std_logic_vector(47 downto 0) := "000000010000000000000000000000000000000000000000";
constant st7: std_logic_vector(47 downto 0) := "000000001000000000000000000000000000000000000000";
constant st41: std_logic_vector(47 downto 0) := "000000000100000000000000000000000000000000000000";
constant st38: std_logic_vector(47 downto 0) := "000000000010000000000000000000000000000000000000";
constant st8: std_logic_vector(47 downto 0) := "000000000001000000000000000000000000000000000000";
constant st10: std_logic_vector(47 downto 0) := "000000000000100000000000000000000000000000000000";
constant st9: std_logic_vector(47 downto 0) := "000000000000010000000000000000000000000000000000";
constant st11: std_logic_vector(47 downto 0) := "000000000000001000000000000000000000000000000000";
constant st12: std_logic_vector(47 downto 0) := "000000000000000100000000000000000000000000000000";
constant st13: std_logic_vector(47 downto 0) := "000000000000000010000000000000000000000000000000";
constant st14: std_logic_vector(47 downto 0) := "000000000000000001000000000000000000000000000000";
constant st15: std_logic_vector(47 downto 0) := "000000000000000000100000000000000000000000000000";
constant st16: std_logic_vector(47 downto 0) := "000000000000000000010000000000000000000000000000";
constant st17: std_logic_vector(47 downto 0) := "000000000000000000001000000000000000000000000000";
constant st18: std_logic_vector(47 downto 0) := "000000000000000000000100000000000000000000000000";
constant st19: std_logic_vector(47 downto 0) := "000000000000000000000010000000000000000000000000";
constant st46: std_logic_vector(47 downto 0) := "000000000000000000000001000000000000000000000000";
constant st24: std_logic_vector(47 downto 0) := "000000000000000000000000100000000000000000000000";
constant st20: std_logic_vector(47 downto 0) := "000000000000000000000000010000000000000000000000";
constant st25: std_logic_vector(47 downto 0) := "000000000000000000000000001000000000000000000000";
constant st21: std_logic_vector(47 downto 0) := "000000000000000000000000000100000000000000000000";
constant st22: std_logic_vector(47 downto 0) := "000000000000000000000000000010000000000000000000";
constant st23: std_logic_vector(47 downto 0) := "000000000000000000000000000001000000000000000000";
constant st26: std_logic_vector(47 downto 0) := "000000000000000000000000000000100000000000000000";
constant st28: std_logic_vector(47 downto 0) := "000000000000000000000000000000010000000000000000";
constant st30: std_logic_vector(47 downto 0) := "000000000000000000000000000000001000000000000000";
constant st27: std_logic_vector(47 downto 0) := "000000000000000000000000000000000100000000000000";
constant st29: std_logic_vector(47 downto 0) := "000000000000000000000000000000000010000000000000";
constant st31: std_logic_vector(47 downto 0) := "000000000000000000000000000000000001000000000000";
constant st32: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000100000000000";
constant st33: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000010000000000";
constant st35: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000001000000000";
constant st34: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000100000000";
constant st36: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000010000000";
constant st37: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000001000000";
constant st39: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000100000";
constant st40: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000010000";
constant st43: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000001000";
constant st44: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000100";
constant st45: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000010";
constant st47: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000001";
signal current_state, next_state: std_logic_vector(47 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "------------------------------------------------"; output <= "-------------------";
case current_state is
when st0 =>
if std_match(input, "-------") then next_state <= st1; output <= "001011101000000---0";
end if;
when st1 =>
if std_match(input, "----01-") then next_state <= st1; output <= "--------0000000---0";
elsif std_match(input, "----10-") then next_state <= st1; output <= "--------0100000---1";
elsif std_match(input, "----00-") then next_state <= st1; output <= "1000----1000000---1";
elsif std_match(input, "----11-") then next_state <= st2; output <= "1000111110011001000";
end if;
when st2 =>
if std_match(input, "------0") then next_state <= st3; output <= "1010010010000000000";
elsif std_match(input, "---0---") then next_state <= st3; output <= "1010010010000000000";
elsif std_match(input, "---1--1") then next_state <= st0; output <= "1010----1010010---1";
end if;
when st3 =>
if std_match(input, "11-----") then next_state <= st4; output <= "001111101000000-010";
elsif std_match(input, "10-----") then next_state <= st4; output <= "0011111110000000-10";
elsif std_match(input, "0-0-01-") then next_state <= st4; output <= "--------000010000-0";
elsif std_match(input, "0-0-10-") then next_state <= st4; output <= "--------010010000-1";
elsif std_match(input, "0-0-11-") then next_state <= st42; output <= "011011011000100---0";
elsif std_match(input, "0-0-00-") then next_state <= st4; output <= "0110----100000000-1";
elsif std_match(input, "0-1-01-") then next_state <= st4; output <= "--------00011000000";
elsif std_match(input, "0-1-10-") then next_state <= st4; output <= "--------01011000001";
elsif std_match(input, "0-1-11-") then next_state <= st42; output <= "011011011001100--00";
elsif std_match(input, "0-1-00-") then next_state <= st4; output <= "0110----10010000001";
end if;
when st4 =>
if std_match(input, "-------") then next_state <= st5; output <= "1010010010000000000";
end if;
when st5 =>
if std_match(input, "--0----") then next_state <= st6; output <= "1000011110000000001";
elsif std_match(input, "--1----") then next_state <= st6; output <= "1000011110010000001";
end if;
when st6 =>
if std_match(input, "-1----0") then next_state <= st7; output <= "101001001000000-000";
elsif std_match(input, "-110--1") then next_state <= st7; output <= "101001001000000-000";
elsif std_match(input, "-10---1") then next_state <= st41; output <= "101001001000000--00";
elsif std_match(input, "-111--1") then next_state <= st38; output <= "101001001000000--00";
elsif std_match(input, "-0-----") then next_state <= st7; output <= "1010010010000000-00";
end if;
when st7 =>
if std_match(input, "--1----") then next_state <= st8; output <= "0001101010010000000";
elsif std_match(input, "--0----") then next_state <= st8; output <= "0001101010000000000";
end if;
when st8 =>
if std_match(input, "--0----") then next_state <= st10; output <= "1010010010000000000";
elsif std_match(input, "--1----") then next_state <= st9; output <= "1010010010000000000";
end if;
when st9 =>
if std_match(input, "-11----") then next_state <= st11; output <= "001011101001000-000";
elsif std_match(input, "-01----") then next_state <= st11; output <= "0010111110010000-00";
elsif std_match(input, "-10----") then next_state <= st11; output <= "001011101000000-000";
elsif std_match(input, "-00----") then next_state <= st11; output <= "0010111110000000-00";
end if;
when st10 =>
if std_match(input, "--1----") then next_state <= st12; output <= "0010----10010000001";
elsif std_match(input, "--0----") then next_state <= st12; output <= "0010----10000000001";
end if;
when st11 =>
if std_match(input, "-------") then next_state <= st13; output <= "1010010010000000000";
end if;
when st12 =>
if std_match(input, "-------") then next_state <= st14; output <= "1010010010000000000";
end if;
when st13 =>
if std_match(input, "-11----") then next_state <= st15; output <= "010110011001000-000";
elsif std_match(input, "-10----") then next_state <= st15; output <= "010110011000000-000";
elsif std_match(input, "-01----") then next_state <= st15; output <= "0101100010010000-00";
elsif std_match(input, "-00----") then next_state <= st15; output <= "0101100010000000-00";
end if;
when st14 =>
if std_match(input, "--1----") then next_state <= st15; output <= "0101----10010000001";
elsif std_match(input, "--0----") then next_state <= st15; output <= "0101----10000000001";
end if;
when st15 =>
if std_match(input, "-------") then next_state <= st16; output <= "1010010010000000000";
end if;
when st16 =>
if std_match(input, "--1----") then next_state <= st17; output <= "0110010110010000001";
elsif std_match(input, "--0----") then next_state <= st17; output <= "0110010110000000001";
end if;
when st17 =>
if std_match(input, "---0---") then next_state <= st18; output <= "1010010010000000000";
elsif std_match(input, "01-1---") then next_state <= st19; output <= "101001001000001-0-0";
elsif std_match(input, "00-1--0") then next_state <= st19; output <= "1010010010000010--0";
elsif std_match(input, "00-1--1") then next_state <= st46; output <= "101001001000000---0";
elsif std_match(input, "11-1---") then next_state <= st24; output <= "101001001000001-000";
elsif std_match(input, "10-1--0") then next_state <= st24; output <= "1010010010000010-00";
elsif std_match(input, "10-1--1") then next_state <= st18; output <= "1010010010000000-00";
end if;
when st18 =>
if std_match(input, "--1----") then next_state <= st2; output <= "1000111110010000000";
elsif std_match(input, "0-0----") then next_state <= st2; output <= "1000----10000000001";
elsif std_match(input, "1-0----") then next_state <= st2; output <= "1000111110000000000";
end if;
when st19 =>
if std_match(input, "-10----") then next_state <= st20; output <= "100101001000000-0-0";
elsif std_match(input, "-00----") then next_state <= st20; output <= "1001010110000000--0";
elsif std_match(input, "--1----") then next_state <= st25; output <= "100011111001000--00";
end if;
when st20 =>
if std_match(input, "-10----") then next_state <= st19; output <= "101001001000000-0-0";
elsif std_match(input, "-11----") then next_state <= st21; output <= "101001001000000-0-0";
elsif std_match(input, "-01----") then next_state <= st19; output <= "1010010010000000--0";
elsif std_match(input, "-00----") then next_state <= st21; output <= "1010010010000000--0";
end if;
when st21 =>
if std_match(input, "-10----") then next_state <= st22; output <= "001111111000000-0-0";
elsif std_match(input, "-11----") then next_state <= st23; output <= "001111111001000--00";
elsif std_match(input, "-00----") then next_state <= st22; output <= "0011111010000000--0";
elsif std_match(input, "-01----") then next_state <= st23; output <= "001111101001000--00";
end if;
when st22 =>
if std_match(input, "-------") then next_state <= st19; output <= "10100100100000000-0";
end if;
when st23 =>
if std_match(input, "-------") then next_state <= st24; output <= "101001001000000--00";
end if;
when st24 =>
if std_match(input, "-------") then next_state <= st25; output <= "100011111000000--00";
end if;
when st25 =>
if std_match(input, "---0--0") then next_state <= st26; output <= "101001001000000---0";
elsif std_match(input, "---1--0") then next_state <= st28; output <= "101001001000010--00";
elsif std_match(input, "------1") then next_state <= st30; output <= "101001001000000--10";
end if;
when st26 =>
if std_match(input, "--0-01-") then next_state <= st27; output <= "--------0000100---0";
elsif std_match(input, "--0-10-") then next_state <= st27; output <= "--------0100100---1";
elsif std_match(input, "--0-00-") then next_state <= st27; output <= "0110----1000000---1";
elsif std_match(input, "--0-11-") then next_state <= st42; output <= "011011011000100---0";
elsif std_match(input, "--1----") then next_state <= st25; output <= "100011111001000--00";
end if;
when st27 =>
if std_match(input, "-------") then next_state <= st26; output <= "101001001000000---0";
end if;
when st28 =>
if std_match(input, "-------") then next_state <= st29; output <= "011001011000000--01";
end if;
when st29 =>
if std_match(input, "---1---") then next_state <= st26; output <= "101001001000000---0";
elsif std_match(input, "--10---") then next_state <= st3; output <= "1010010010000001000";
elsif std_match(input, "--00---") then next_state <= st3; output <= "1010010010000000100";
end if;
when st30 =>
if std_match(input, "-------") then next_state <= st31; output <= "100001111000000---1";
end if;
when st31 =>
if std_match(input, "---0---") then next_state <= st26; output <= "101001001000000---0";
elsif std_match(input, "---1---") then next_state <= st32; output <= "101001001000000---0";
end if;
when st32 =>
if std_match(input, "--0----") then next_state <= st33; output <= "100101011000000---0";
elsif std_match(input, "--1----") then next_state <= st35; output <= "011011011001000--00";
end if;
when st33 =>
if std_match(input, "--10---") then next_state <= st32; output <= "101001001000000---0";
elsif std_match(input, "--0----") then next_state <= st34; output <= "101001001000000---0";
elsif std_match(input, "---1---") then next_state <= st34; output <= "101001001000000---0";
end if;
when st34 =>
if std_match(input, "--1----") then next_state <= st35; output <= "011011011001000--00";
elsif std_match(input, "--0----") then next_state <= st35; output <= "011011011000000---0";
end if;
when st35 =>
if std_match(input, "-------") then next_state <= st36; output <= "101001001000000--00";
end if;
when st36 =>
if std_match(input, "--0----") then next_state <= st37; output <= "011011101000000--00";
elsif std_match(input, "--1----") then next_state <= st37; output <= "011011101001000--00";
end if;
when st37 =>
if std_match(input, "-------") then next_state <= st9; output <= "1010010010000000100";
end if;
when st38 =>
if std_match(input, "--0-01-") then next_state <= st39; output <= "--------0000100---0";
elsif std_match(input, "--0-10-") then next_state <= st39; output <= "--------0100100---1";
elsif std_match(input, "--0-11-") then next_state <= st42; output <= "011011011000100---0";
elsif std_match(input, "--0-00-") then next_state <= st39; output <= "0110----1000000---1";
elsif std_match(input, "--1----") then next_state <= st40; output <= "100011111001000--00";
end if;
when st39 =>
if std_match(input, "-------") then next_state <= st38; output <= "101001001000000---0";
end if;
when st40 =>
if std_match(input, "-------") then next_state <= st41; output <= "101001001000000--10";
end if;
when st41 =>
if std_match(input, "-------") then next_state <= st42; output <= "011011011000000---0";
end if;
when st42 =>
if std_match(input, "-------") then next_state <= st43; output <= "101001001000000--00";
end if;
when st43 =>
if std_match(input, "--0----") then next_state <= st44; output <= "011011101000000--00";
elsif std_match(input, "--1----") then next_state <= st44; output <= "011011101001000--00";
end if;
when st44 =>
if std_match(input, "-------") then next_state <= st45; output <= "101001001000000--00";
end if;
when st45 =>
if std_match(input, "--0----") then next_state <= st6; output <= "0111001110000000100";
elsif std_match(input, "--1----") then next_state <= st6; output <= "0111001110010000100";
end if;
when st46 =>
if std_match(input, "--0----") then next_state <= st47; output <= "1000----1000000---1";
elsif std_match(input, "--1----") then next_state <= st0; output <= "100011111011010---0";
end if;
when st47 =>
if std_match(input, "-------") then next_state <= st46; output <= "101001001000000---0";
end if;
when others => next_state <= "------------------------------------------------"; output <= "-------------------";
end case;
end process;
end behaviour;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Steven Vanden Branden
--
-- Create Date: 15:23:25 03/13/2013
-- Design Name:
-- Module Name: Control - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
--! Use standard library
library IEEE;
--! use logic elements
use IEEE.STD_LOGIC_1164.ALL;
--! sends out control signals depending on the instruction first 6 bits (FUNCT field) and the instructions 26-31 bits(?)
entity Control is
Port ( Instruction : in STD_LOGIC_VECTOR (31 downto 26); --! last 6 bits of instruction (?)
Instruction_funct : in STD_LOGIC_VECTOR (5 downto 0); --! first 6 bits of instruction (FUNCT field)
RegDst : out STD_LOGIC; --! Register Destination selector
ALUSrc : out STD_LOGIC; --! ALU input Source selector
MemtoReg : out STD_LOGIC; --! write to register from memory
RegWrite : out STD_LOGIC; --! Write to register from ALU output
MemRead : out STD_LOGIC; --! read from memory
MemWrite : out STD_LOGIC; --! write to memory
Branch : out STD_LOGIC; --! branch if equal
Branch_ne : out STD_LOGIC; --! branch if not equal
ALUop : out STD_LOGIC_VECTOR (1 downto 0)); --! input for ALU_Control
end Control;
--! @brief This is the controller that sets the control variables
--! @details depending on function field sets (RegDst,ALUSrc,MemtoReg,RegWrite,MemRead,Branch,ALUop):
--! @details 000000:(1,0,0,1,0,0,0,0,10) --> R-type instruction
--! @details 100011:(0,1,1,1,1,0,0,0,00) --> load word instruction
--! @details 101011:(0,1,0,0,0,1,0,0,00) --> save word instruction
--! @details 000100:(0,0,0,0,0,0,1/0,0/1,01)--> branch equal/branch not equal instruction
architecture Behavioral of Control is
begin
Control_out: process(Instruction,Instruction_funct)
begin
case Instruction is
when "000000" => --R-format instruction
RegDst<= '1';
ALUSrc<= '0';
MemtoReg<= '0';
RegWrite<= '1';
MemRead<='0';
MemWrite<='0';
Branch<='0';
Branch_ne<='0';
ALUop<="10";
when "000100" => -- branch on equal
RegDst <= '0';
ALUSrc <= '0';
MemtoReg <= '0';
RegWrite <= '0';
MemRead <= '0';
MemWrite <= '0';
Branch <= '1';
Branch_ne<= '0';
ALUop <= "01";
when "000101" => -- branch on not equal
RegDst <= '0';
ALUSrc <= '0';
MemtoReg <= '0';
RegWrite <= '0';
MemRead <= '0';
MemWrite <= '0';
Branch <= '0';
Branch_ne<= '1';
ALUop <= "01";
when "001000" => -- add immediate
RegDst<= '0';
ALUSrc<= '1';
MemtoReg<= '0';
RegWrite<= '1';
MemRead<='0';
MemWrite<='0';
Branch<='0';
Branch_ne<='0';
when "101011" => -- store word
RegDst<= '0';
ALUSrc<= '1';
MemtoReg<= '0';
RegWrite<= '0';
MemRead<='0';
MemWrite<='1';
Branch<='0';
Branch_ne<='0';
ALUop <= "00";
when "100011" => -- load word
RegDst<= '0';
ALUSrc<= '1';
MemtoReg<= '1';
RegWrite<= '1';
MemRead<='1';
MemWrite<='0';
Branch<='0';
Branch_ne<='0';
ALUop <= "00";
when others => --error
RegDst <= '0';
ALUSrc <= '0';
MemtoReg <= '0';
RegWrite <= '0';
MemRead <= '0';
MemWrite <= '0';
Branch <= '0';
Branch_ne<='0';
ALUop <= "00";
end case;
end process Control_out;
end Behavioral;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:54:34 05/24/2011
-- Design Name:
-- Module Name: /home/xiadz/prog/fpga/oscilloscope/test_reader.vhd
-- Project Name: oscilloscope
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: reader
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY test_reader IS
END test_reader;
ARCHITECTURE behavior OF test_reader IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT reader
PORT(
nrst : IN std_logic;
clk108 : IN std_logic;
input_red : IN std_logic;
input_green : IN std_logic;
input_blue : IN std_logic;
is_reading_active : IN std_logic;
time_resolution : IN integer range 0 to 15;
overflow_indicator : OUT std_logic;
flush_and_return_to_zero : OUT std_logic;
write_enable : OUT std_logic;
red_value : OUT std_logic;
green_value : OUT std_logic;
blue_value : OUT std_logic
);
END COMPONENT;
--Inputs
signal nrst : std_logic := '0';
signal clk108 : std_logic := '0';
signal input_red : std_logic := '0';
signal input_green : std_logic := '0';
signal input_blue : std_logic := '0';
signal is_reading_active : std_logic := '0';
signal time_resolution : integer range 0 to 15 := 0;
--Outputs
signal overflow_indicator : std_logic;
signal flush_and_return_to_zero : std_logic;
signal write_enable : std_logic;
signal red_value : std_logic;
signal green_value : std_logic;
signal blue_value : std_logic;
-- Clock period definitions
constant clk108_period : time := 10 ns;
signal was_there_an_overflow : std_logic := '0';
signal please_reset_overflow : std_logic := '0';
signal currently_doing_nothing : std_logic := '0';
signal write_enable_count_between_flushes : natural := 0;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: reader PORT MAP (
nrst => nrst,
clk108 => clk108,
input_red => input_red,
input_green => input_green,
input_blue => input_blue,
is_reading_active => is_reading_active,
time_resolution => time_resolution,
overflow_indicator => overflow_indicator,
flush_and_return_to_zero => flush_and_return_to_zero,
write_enable => write_enable,
red_value => red_value,
green_value => green_value,
blue_value => blue_value
);
-- Clock process definitions
clk108_process :process
begin
clk108 <= '0';
wait for clk108_period/2;
clk108 <= '1';
wait for clk108_period/2;
end process;
simulate_trigger : process (nrst, clk108) is
begin
if nrst = '0' then
is_reading_active <= '1';
elsif rising_edge (clk108) then
if please_reset_overflow = '1' then
was_there_an_overflow <= '0';
is_reading_active <= '1';
time_resolution <= (time_resolution + 1) mod 16;
elsif was_there_an_overflow = '0' then
if overflow_indicator = '1' then
was_there_an_overflow <= '1';
is_reading_active <= '0';
end if;
end if;
end if;
end process;
restart_was_there_an_overflow: process is
begin
while true loop
if was_there_an_overflow = '1' then
wait for clk108_period * 25;
currently_doing_nothing <= '1';
wait for clk108_period;
currently_doing_nothing <= '0';
wait for clk108_period * 25;
please_reset_overflow <= '1';
end if;
wait for clk108_period;
please_reset_overflow <= '0';
end loop;
end process;
write_enable_counter: process (nrst, clk108) is
begin
if nrst = '0' then
write_enable_count_between_flushes <= 0;
elsif rising_edge (clk108) then
if currently_doing_nothing = '1' then
assert write_enable_count_between_flushes = 14 * 1280 report "Improper number of write_enable ones.";
write_enable_count_between_flushes <= 0;
elsif write_enable = '1' then
write_enable_count_between_flushes <= write_enable_count_between_flushes + 1;
end if;
end if;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
nrst <= '0';
wait for 100 ns;
nrst <= '1';
wait for clk108_period*10;
-- insert stimulus here
wait;
end process;
END;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2545.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b05x00p14n01i02545ent IS
END c07s03b05x00p14n01i02545ent;
ARCHITECTURE c07s03b05x00p14n01i02545arch OF c07s03b05x00p14n01i02545ent IS
BEGIN
TESTING: PROCESS
type X1 is range 1.0 to 100.0 ;
type X2 is range 1.0 to 100.0 ;
type I1 is range 1 to 1000000;
type I2 is range 1 to 10000000 ;
variable RE1 : X1 ;
variable RE2 : X2 ;
variable IN1 : I1 ;
variable IN2 : I2 ;
BEGIN
RE1 := RE2 - RE1; -- Failure_here
-- ERROR: TYPE CONVERSION CANNOT OCCUR ON AN OPERAND OF ANY TYPE BUT
-- UNIVERSAL INTEGER OR UNIVERSAL REAL.
assert FALSE
report "***FAILED TEST: c07s03b05x00p14n01i02545 - Type conversion can only occur on operand of universal real or integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b05x00p14n01i02545arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2545.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b05x00p14n01i02545ent IS
END c07s03b05x00p14n01i02545ent;
ARCHITECTURE c07s03b05x00p14n01i02545arch OF c07s03b05x00p14n01i02545ent IS
BEGIN
TESTING: PROCESS
type X1 is range 1.0 to 100.0 ;
type X2 is range 1.0 to 100.0 ;
type I1 is range 1 to 1000000;
type I2 is range 1 to 10000000 ;
variable RE1 : X1 ;
variable RE2 : X2 ;
variable IN1 : I1 ;
variable IN2 : I2 ;
BEGIN
RE1 := RE2 - RE1; -- Failure_here
-- ERROR: TYPE CONVERSION CANNOT OCCUR ON AN OPERAND OF ANY TYPE BUT
-- UNIVERSAL INTEGER OR UNIVERSAL REAL.
assert FALSE
report "***FAILED TEST: c07s03b05x00p14n01i02545 - Type conversion can only occur on operand of universal real or integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b05x00p14n01i02545arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2545.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b05x00p14n01i02545ent IS
END c07s03b05x00p14n01i02545ent;
ARCHITECTURE c07s03b05x00p14n01i02545arch OF c07s03b05x00p14n01i02545ent IS
BEGIN
TESTING: PROCESS
type X1 is range 1.0 to 100.0 ;
type X2 is range 1.0 to 100.0 ;
type I1 is range 1 to 1000000;
type I2 is range 1 to 10000000 ;
variable RE1 : X1 ;
variable RE2 : X2 ;
variable IN1 : I1 ;
variable IN2 : I2 ;
BEGIN
RE1 := RE2 - RE1; -- Failure_here
-- ERROR: TYPE CONVERSION CANNOT OCCUR ON AN OPERAND OF ANY TYPE BUT
-- UNIVERSAL INTEGER OR UNIVERSAL REAL.
assert FALSE
report "***FAILED TEST: c07s03b05x00p14n01i02545 - Type conversion can only occur on operand of universal real or integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b05x00p14n01i02545arch;
|
architecture RTL of FIFO is
procedure proc1 is begin end procedure PROC1;
PROCEDURE PROC1 IS BEGIN END PROCEDURE PROC1;
function func1 return integer is begin end function Func1;
begin
end architecture RTL;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1512.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s09b00x00p02n01i01512ent IS
END c08s09b00x00p02n01i01512ent;
ARCHITECTURE c08s09b00x00p02n01i01512arch OF c08s09b00x00p02n01i01512ent IS
BEGIN
TESTING: PROCESS
variable counter : integer := 0;
BEGIN
for i in 1 to 10 loop
counter := counter + 1;
end loop;
assert NOT( counter = 10 )
report "***PASSED TEST: c08s09b00x00p02n01i01512"
severity NOTE;
assert ( counter = 10 )
report "***FAILED TEST: c08s09b00x00p02n01i01512 - In loop statement, the reserved word loop must be followed by a sequence of statements, and the reserved words end loop"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s09b00x00p02n01i01512arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1512.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s09b00x00p02n01i01512ent IS
END c08s09b00x00p02n01i01512ent;
ARCHITECTURE c08s09b00x00p02n01i01512arch OF c08s09b00x00p02n01i01512ent IS
BEGIN
TESTING: PROCESS
variable counter : integer := 0;
BEGIN
for i in 1 to 10 loop
counter := counter + 1;
end loop;
assert NOT( counter = 10 )
report "***PASSED TEST: c08s09b00x00p02n01i01512"
severity NOTE;
assert ( counter = 10 )
report "***FAILED TEST: c08s09b00x00p02n01i01512 - In loop statement, the reserved word loop must be followed by a sequence of statements, and the reserved words end loop"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s09b00x00p02n01i01512arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1512.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s09b00x00p02n01i01512ent IS
END c08s09b00x00p02n01i01512ent;
ARCHITECTURE c08s09b00x00p02n01i01512arch OF c08s09b00x00p02n01i01512ent IS
BEGIN
TESTING: PROCESS
variable counter : integer := 0;
BEGIN
for i in 1 to 10 loop
counter := counter + 1;
end loop;
assert NOT( counter = 10 )
report "***PASSED TEST: c08s09b00x00p02n01i01512"
severity NOTE;
assert ( counter = 10 )
report "***FAILED TEST: c08s09b00x00p02n01i01512 - In loop statement, the reserved word loop must be followed by a sequence of statements, and the reserved words end loop"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s09b00x00p02n01i01512arch;
|
--
-- Wrapper of gtx example
--
-- Author:
-- * Rodrigo A. Melo, rmelo@inti.gob.ar
--
-- Copyright (c) 2017 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Wrapper is
port (
gtxclk_i : in std_logic;
sysclk_i : in std_logic;
rst_i : in std_logic;
--
rxp_i : in std_logic;
rxn_i : in std_logic;
txp_o : out std_logic;
txn_o : out std_logic;
--
loopback_i: in std_logic;
rx_data_o : out std_logic_vector(39 downto 0);
tx_data_i : in std_logic_vector(39 downto 0);
ready_o : out std_logic
);
end entity Wrapper;
architecture Structural of Wrapper is
signal rx_fsm_reset, tx_fsm_reset : std_logic;
signal rxresetdone, txresetdone : std_logic;
signal txoutclk, txusrclk : std_logic;
signal loopback : std_logic_vector(2 downto 0);
signal qplloutclk, qplloutrefclk : std_logic;
signal qplllock, qpllrefclklost : std_logic;
signal qpllreset : std_logic;
begin
loopback <= '0' & loopback_i & '0';
ready_o <= rxresetdone and txresetdone and rx_fsm_reset and tx_fsm_reset;
gbt1_i : entity work.gbt1
port map (
sysclk_in => sysclk_i,
soft_reset_tx_in => '0',
soft_reset_rx_in => '0',
dont_reset_on_data_error_in => '0',
gt0_tx_fsm_reset_done_out => tx_fsm_reset,
gt0_rx_fsm_reset_done_out => rx_fsm_reset,
gt0_data_valid_in => '0',
---------------------------- Channel - DRP Ports --------------------------
gt0_drpaddr_in => "000000000",
gt0_drpclk_in => sysclk_i,
gt0_drpdi_in => "0000000000000000",
gt0_drpdo_out => open,
gt0_drpen_in => '0',
gt0_drprdy_out => open,
gt0_drpwe_in => '0',
--------------------------- Digital Monitor Ports --------------------------
gt0_dmonitorout_out => open,
------------------------------- Loopback Ports -----------------------------
gt0_loopback_in => loopback,
--------------------- RX Initialization and Reset Ports --------------------
gt0_eyescanreset_in => '0',
gt0_rxuserrdy_in => '0',
-------------------------- RX Margin Analysis Ports ------------------------
gt0_eyescandataerror_out => open,
gt0_eyescantrigger_in => '0',
------------------ Receive Ports - FPGA RX Interface Ports -----------------
gt0_rxusrclk_in => txusrclk,
gt0_rxusrclk2_in => txusrclk,
------------------ Receive Ports - FPGA RX interface Ports -----------------
gt0_rxdata_out => rx_data_o,
--------------------------- Receive Ports - RX AFE -------------------------
gt0_gtxrxp_in => rxp_i,
------------------------ Receive Ports - RX AFE Ports ----------------------
gt0_gtxrxn_in => rxn_i,
--------------------- Receive Ports - RX Equalizer Ports -------------------
gt0_rxdfelpmreset_in => '0',
gt0_rxmonitorout_out => open,
gt0_rxmonitorsel_in => "00",
--------------- Receive Ports - RX Fabric Output Control Ports -------------
gt0_rxoutclkfabric_out => open,
------------- Receive Ports - RX Initialization and Reset Ports ------------
gt0_gtrxreset_in => '0',
gt0_rxpmareset_in => '0',
-------------- Receive Ports -RX Initialization and Reset Ports ------------
gt0_rxresetdone_out => rxresetdone,
--------------------- TX Initialization and Reset Ports --------------------
gt0_gttxreset_in => '0',
gt0_txuserrdy_in => '0',
------------------ Transmit Ports - FPGA TX Interface Ports ----------------
gt0_txusrclk_in => txusrclk,
gt0_txusrclk2_in => txusrclk,
------------------ Transmit Ports - TX Data Path interface -----------------
gt0_txdata_in => tx_data_i,
---------------- Transmit Ports - TX Driver and OOB signaling --------------
gt0_gtxtxn_out => txn_o,
gt0_gtxtxp_out => txp_o,
----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
gt0_txoutclk_out => txoutclk,
gt0_txoutclkfabric_out => open,
gt0_txoutclkpcs_out => open,
------------- Transmit Ports - TX Initialization and Reset Ports -----------
gt0_txresetdone_out => txresetdone,
--
gt0_qplllock_in => qplllock,
gt0_qpllrefclklost_in => qpllrefclklost,
gt0_qpllreset_out => qpllreset,
gt0_qplloutclk_in => qplloutclk,
gt0_qplloutrefclk_in => qplloutrefclk
);
txoutclk_i : BUFG
port map (I => txoutclk, O => txusrclk);
gtxe2_common_i : GTXE2_COMMON
generic map (
-- Simulation attributes
SIM_RESET_SPEEDUP => ("TRUE"),
SIM_QPLLREFCLK_SEL => "111", -- "010"
SIM_VERSION => ("4.0"),
------------------COMMON BLOCK Attributes---------------
BIAS_CFG => (x"0000040000001000"),
COMMON_CFG => (x"00000000"),
QPLL_CFG => (x"0680181"),
QPLL_CLKOUT_CFG => ("0000"),
QPLL_COARSE_FREQ_OVRD => ("010000"),
QPLL_COARSE_FREQ_OVRD_EN => ('0'),
QPLL_CP => ("0000011111"),
QPLL_CP_MONITOR_EN => ('0'),
QPLL_DMONITOR_SEL => ('0'),
QPLL_FBDIV => ("0101110000"),
QPLL_FBDIV_MONITOR_EN => ('0'),
QPLL_FBDIV_RATIO => ('1'),
QPLL_INIT_CFG => (x"000006"),
QPLL_LOCK_CFG => (x"21E8"),
QPLL_LPF => ("1111"),
QPLL_REFCLK_DIV => (2)
)
port map (
------------- Common Block - Dynamic Reconfiguration Port (DRP) -----------
DRPADDR => "00000000",
DRPCLK => '0',
DRPDI => "0000000000000000",
DRPDO => open,
DRPEN => '0',
DRPRDY => open,
DRPWE => '0',
---------------------- Common Block - Ref Clock Ports ---------------------
GTGREFCLK => gtxclk_i,
GTNORTHREFCLK0 => '0',
GTNORTHREFCLK1 => '0',
GTREFCLK0 => '0',
GTREFCLK1 => '0',
GTSOUTHREFCLK0 => '0',
GTSOUTHREFCLK1 => '0',
------------------------- Common Block - QPLL Ports -----------------------
QPLLDMONITOR => open,
----------------------- Common Block - Clocking Ports ----------------------
QPLLOUTCLK => qplloutclk,
QPLLOUTREFCLK => qplloutrefclk,
REFCLKOUTMONITOR => open,
------------------------- Common Block - QPLL Ports ------------------------
QPLLFBCLKLOST => open,
QPLLLOCK => qplllock,
QPLLLOCKDETCLK => sysclk_i,
QPLLLOCKEN => '1',
QPLLOUTRESET => '0',
QPLLPD => '0',
QPLLREFCLKLOST => qpllrefclklost,
QPLLREFCLKSEL => "111", -- "010"
QPLLRESET => qpllreset,
QPLLRSVD1 => "0000000000000000",
QPLLRSVD2 => "11111",
--------------------------------- QPLL Ports -------------------------------
BGBYPASSB => '1',
BGMONITORENB => '1',
BGPDB => '1',
BGRCALOVRD => "11111",
PMARSVD => "00000000",
RCALENB => '1'
);
end architecture Structural;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2168.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p22n01i02168ent IS
END c07s02b04x00p22n01i02168ent;
ARCHITECTURE c07s02b04x00p22n01i02168arch OF c07s02b04x00p22n01i02168ent IS
TYPE severity_level_v is array (integer range <>) of severity_level;
SUBTYPE severity_level_2 is severity_level_v (1 to 2);
BEGIN
TESTING: PROCESS
variable result : severity_level_2;
variable l_operand : severity_level := NOTE ;
variable r_operand : severity_level := FAILURE ;
BEGIN
--
-- The element is treated as an implicit single element array !
--
result := l_operand & r_operand;
wait for 5 ns;
assert NOT(( result = (NOTE,FAILURE)) and (result(1) = NOTE))
report "***PASSED TEST: c07s02b04x00p22n01i02168"
severity NOTE;
assert (( result = (NOTE,FAILURE)) and (result(1) = NOTE))
report "***FAILED TEST: c07s02b04x00p22n01i02168 - Concatenation of element and element failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p22n01i02168arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2168.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p22n01i02168ent IS
END c07s02b04x00p22n01i02168ent;
ARCHITECTURE c07s02b04x00p22n01i02168arch OF c07s02b04x00p22n01i02168ent IS
TYPE severity_level_v is array (integer range <>) of severity_level;
SUBTYPE severity_level_2 is severity_level_v (1 to 2);
BEGIN
TESTING: PROCESS
variable result : severity_level_2;
variable l_operand : severity_level := NOTE ;
variable r_operand : severity_level := FAILURE ;
BEGIN
--
-- The element is treated as an implicit single element array !
--
result := l_operand & r_operand;
wait for 5 ns;
assert NOT(( result = (NOTE,FAILURE)) and (result(1) = NOTE))
report "***PASSED TEST: c07s02b04x00p22n01i02168"
severity NOTE;
assert (( result = (NOTE,FAILURE)) and (result(1) = NOTE))
report "***FAILED TEST: c07s02b04x00p22n01i02168 - Concatenation of element and element failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p22n01i02168arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2168.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p22n01i02168ent IS
END c07s02b04x00p22n01i02168ent;
ARCHITECTURE c07s02b04x00p22n01i02168arch OF c07s02b04x00p22n01i02168ent IS
TYPE severity_level_v is array (integer range <>) of severity_level;
SUBTYPE severity_level_2 is severity_level_v (1 to 2);
BEGIN
TESTING: PROCESS
variable result : severity_level_2;
variable l_operand : severity_level := NOTE ;
variable r_operand : severity_level := FAILURE ;
BEGIN
--
-- The element is treated as an implicit single element array !
--
result := l_operand & r_operand;
wait for 5 ns;
assert NOT(( result = (NOTE,FAILURE)) and (result(1) = NOTE))
report "***PASSED TEST: c07s02b04x00p22n01i02168"
severity NOTE;
assert (( result = (NOTE,FAILURE)) and (result(1) = NOTE))
report "***FAILED TEST: c07s02b04x00p22n01i02168 - Concatenation of element and element failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p22n01i02168arch;
|
-- Original source:
-- Mike Field
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
--
-- VGA configuration parameters
--
-------------------------------------------
-- CONFIG #1: 640x480 @ 60Hz
-- Clock: 25MHz
-- ----------------------------------------
-- Name Description Cycles
-- ----------------------------------------
-- H_S Horizontal sync pulse 800
-- H_DISP Horizontal display 640
-- H_FP Horizontal front porch 16
-- H_PW Horizontal pulse width 96
-- H_BP Horizontal back porch 48
-- V_S Vertical sync pulse 521
-- V_DISP Vertical display 480
-- V_FP Vertical front porch 10
-- V_PW Vertical pulse width 2
-- V_BP Vertical back porch 29
-- ----------------------------------------
--
-------------------------------------------
-- CONFIG #2: 800x600 @ 72Hz
-- Clock: 50MHz
-- ----------------------------------------
-- Name Description Cycles
-- ----------------------------------------
-- H_S Horizontal sync pulse 1040
-- H_DISP Horizontal display 800
-- H_FP Horizontal front porch 56
-- H_PW Horizontal pulse width 120
-- H_BP Horizontal back porch 64
-- V_S Vertical sync pulse 666
-- V_DISP Vertical display 600
-- V_FP Vertical front porch 37
-- V_PW Vertical pulse width 6
-- V_BP Vertical back porch 23
-- ----------------------------------------
entity vga_controller is
generic (
-- horizontal timing
-- sync pulse
H_S : integer := 800;
-- display
H_DISP : integer := 640;
-- front porch
H_FP : integer := 16;
-- pulse width
H_PW : integer := 96;
-- back porch
H_BP : integer := 48;
-- vertical timing
-- sync pulse
V_S : integer := 521;
-- display
V_DISP : integer := 480;
-- front porch
V_FP : integer := 10;
-- pulse width
V_PW : integer := 2;
-- back porch
V_BP : integer := 29
);
port (
clk : in std_logic; -- assuming a clock of 25MHz
rst : in std_logic; -- reset (synchronous)
hs : out std_logic; -- Horizontal sync pulse. Active low
vs : out std_logic; -- Vertical sync pulse. Active low
blank : out std_logic; -- Blanking interval indicator. Active low.
-- Color to monitor should be black when active
-- (ie, AND this signal with your color signals).
hpix : out std_logic_vector(9 downto 0); -- horizontal coordinate
vpix : out std_logic_vector(9 downto 0) -- vertical coordinate
);
end vga_controller;
architecture behavioral of vga_controller is
--
-- Constants
constant hVisible : natural := H_DISP;
constant hSyncStart : natural := H_DISP+H_FP;
constant hSyncEnd : natural := H_DISP+H_FP+H_PW;
constant hTotalCount : natural := H_DISP+H_FP+H_PW+H_BP;
constant vVisible : natural := V_DISP;
constant vSyncStart : natural := V_DISP+V_FP;
constant vSyncEnd : natural := V_DISP+V_FP+V_PW;
constant vTotalCount : natural := V_DISP+V_FP+V_PW+V_BP;
--
-- Signals
signal nextHsync : std_logic;
signal nextVsync : std_logic;
signal vCounter : unsigned(10 downto 0) := (others => '0');
signal hCounter : unsigned(11 downto 0) := (others => '0');
--
begin
process (clk)
begin
if rising_edge(clk) then
hs <= nextHsync;
vs <= nextVsync;
hpix <= std_logic_vector(hCounter(9 downto 0));
vpix <= std_logic_vector(vCounter(9 downto 0));
--
if ((hCounter < hVisible) and (vCounter < vVisible)) then
blank <= '1';
else
blank <= '0';
end if;
--
if (hCounter /= hTotalCount-1) then
hcounter <= hcounter + 1;
else
hcounter <= (others => '0');
if (vCounter = vTotalCount-1) then
vCounter <= (others => '0');
else
vCounter <= vCounter + 1;
end if;
end if;
--
if ((hcounter >= hSyncStart) and (hcounter < hSyncEnd)) then
nextHsync <= '0';
else
nextHsync <= '1';
end if;
--
if ((vcounter >= vSyncStart) and (vcounter < vSyncEnd)) then
nextVsync <= '1';
else
nextVsync <= '0';
end if;
end if;
end process;
end behavioral;
|
library IEEE;
use IEEE.Std_Logic_1164.all;
entity LAB6 is
port (SW: in std_logic_vector(9 downto 0);
HEX0: out std_logic_vector(6 downto 0);
LEDR: out std_logic_vector(9 downto 0)
);
end LAB6;
architecture lab_stru of LAB6 is
signal F, F1, F2, F3, F4: std_logic_vector(3 downto 0);
component C1
port (A: in std_logic_vector(3 downto 0);
B: in std_logic_vector(3 downto 0);
F: out std_logic_vector(3 downto 0)
);
end component;
component C2
port (A: in std_logic_vector(3 downto 0);
B: in std_logic_vector(3 downto 0);
F: out std_logic_vector(3 downto 0)
);
end component;
component C3
port (A: in std_logic_vector(3 downto 0);
B: in std_logic_vector(3 downto 0);
F: out std_logic_vector(3 downto 0)
);
end component;
component C4
port (A: in std_logic_vector(3 downto 0);
F: out std_logic_vector(3 downto 0)
);
end component;
component mux4x1
port (w, x, y, z: in std_logic_vector(3 downto 0);
s: in std_logic_vector(1 downto 0);
m: out std_logic_vector(3 downto 0)
);
end component;
component decod7seg
port (C: in std_logic_vector(3 downto 0);
F: out std_logic_vector(6 downto 0)
);
end component;
begin
L1: C1 port map(SW(3 downto 0), SW(7 downto 4), F1);
L2: C2 port map(SW(3 downto 0), SW(7 downto 4), F2);
L3: C3 port map(SW(3 downto 0), SW(7 downto 4), F3);
L4: C4 port map(SW(3 downto 0), F4);
L5: mux4x1 port map(F1, F2, F3, F4, SW(9 downto 8), F);
L6: decod7seg port map(F, HEX0);
LEDR <= "000000" & F;
end lab_stru;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: can_oc
-- File: can_oc.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB interface for the OpenCores CAN MAC
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.can.all;
entity can_rd is
generic (
slvndx : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#FF0#;
irq : integer := 0;
memtech : integer := DEFMEMTECH;
syncrst : integer := 0;
dmap : integer := 0);
port (
resetn : in std_logic;
clk : in std_logic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
can_rxi : in std_logic_vector(1 downto 0);
can_txo : out std_logic_vector(1 downto 0)
);
end;
architecture rtl of can_rd is
constant ncores : integer := 1;
constant sepirq : integer := 0;
constant REVISION : amba_version_type := ncores-1;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_CANAHB, 0, REVISION, irq),
4 => ahb_iobar(ioaddr, iomask), others => zero32);
type ahbregs is record
hsel : std_ulogic;
hwrite : std_ulogic;
hwrite2 : std_ulogic;
htrans : std_logic_vector(1 downto 0);
haddr : std_logic_vector(10 downto 0);
hwdata : std_logic_vector(7 downto 0);
herr : std_ulogic;
hready : std_ulogic;
ws : std_logic_vector(1 downto 0);
irqi : std_logic_vector(ncores-1 downto 0);
irqo : std_logic_vector(ncores-1 downto 0);
muxsel : std_logic;
writemux : std_logic;
end record;
subtype cdata is std_logic_vector(7 downto 0);
type cdataarr is array (0 to 7) of cdata;
signal data_out : cdataarr;
signal reset : std_logic;
signal irqo : std_logic_vector(ncores-1 downto 0);
signal addr : std_logic_vector(7 downto 0);
signal vcc, gnd : std_ulogic;
signal r, rin : ahbregs;
signal can_lrxi, can_ltxo : std_logic;
begin
gnd <= '0'; vcc <= '1'; reset <= not resetn;
comb : process(ahbsi, r, resetn, data_out, irqo)
variable v : ahbregs;
variable hresp : std_logic_vector(1 downto 0);
variable dataout : std_logic_vector(7 downto 0);
variable irqvec : std_logic_vector(NAHBIRQ-1 downto 0);
variable vmuxreg : std_logic;
variable hwdata : std_logic_vector(31 downto 0);
begin
v := r;
hwdata := ahbreadword(ahbsi.hwdata, r.haddr(4 downto 2));
if (r.hsel = '1' ) and (r.ws /= "11") then v.ws := r.ws + 1; end if;
if ahbsi.hready = '1' then
v.hsel := ahbsi.hsel(slvndx);
v.haddr := ahbsi.haddr(10 downto 0);
v.htrans := ahbsi.htrans;
v.hwrite := ahbsi.hwrite;
v.herr := orv(ahbsi.hsize) and ahbsi.hwrite;
v.ws := "00";
end if;
v.hready := (r.hsel and r.ws(1) and not r.ws(0)) or not resetn
or (ahbsi.hready and not ahbsi.htrans(1));
vmuxreg := not r.haddr(7) and r.haddr(6);
--v.hwrite2 := r.hwrite and r.hsel and r.htrans(1) and r.ws(1)
-- and not r.ws(0) and not r.herr;
v.hwrite2 := r.hwrite and r.hsel and r.htrans(1) and r.ws(1)
and not r.ws(0) and not r.herr and not vmuxreg;
v.writemux := r.hwrite and r.hsel and r.htrans(1) and r.ws(1)
and not r.ws(0) and vmuxreg;
if (r.herr and r.ws(1)) = '1' then hresp := HRESP_ERROR;
else hresp := HRESP_OKAY; end if;
case r.haddr(1 downto 0) is
when "00" => v.hwdata := hwdata(31 downto 24);
when "01" => v.hwdata := hwdata(23 downto 16);
when "10" => v.hwdata := hwdata(15 downto 8);
when others => v.hwdata := hwdata(7 downto 0);
end case;
--dataout := data_out(0);
if r.haddr(7 downto 6) = "01" then
dataout := (others => r.muxsel);
if r.writemux = '1' then
v.muxsel := r.hwdata(0);
end if;
else
dataout := data_out(0);
end if;
-- Interrupt goes to low when appeard and is normal high
-- but the irq controller from leon is active high and the interrupt should appear only
-- for 1 Clk cycle,
v.irqi := irqo; v.irqo:= (r.irqi and not irqo);
irqvec := (others => '0');
if sepirq = 1 then irqvec(ncores-1+irq downto irq) := r.irqo;
else irqvec(irq) := orv(r.irqo); end if;
ahbso.hirq <= irqvec;
ahbso.hrdata <= ahbdrivedata(dataout);
ahbso.hresp <= hresp; rin <= v;
end process;
-- Double mapping of registers [byte (offset 0), word (offset 0x80)]
dmap0 : if dmap = 0 generate
addr <= r.haddr(7 downto 0);
end generate;
dmap1 : if dmap = 1 generate
addr <= "000"&r.haddr(6 downto 2) when r.haddr(7) = '1' else
r.haddr(7 downto 0);
end generate;
reg : process(clk)
begin if clk'event and clk = '1' then r <= rin; end if; end process;
cmod : can_mod generic map (memtech, syncrst)
--port map (reset, clk, r.hsel, r.hwrite2, r.haddr(7 downto 0), r.hwdata,
port map (reset, clk, r.hsel, r.hwrite2, addr, r.hwdata,
data_out(0), irqo(0), can_lrxi, can_ltxo, ahbsi.testen);
cmux : canmux port map (r.muxsel, can_lrxi, can_ltxo, can_rxi, can_txo);
ahbso.hconfig <= hconfig;
ahbso.hindex <= slvndx;
ahbso.hsplit <= (others => '0');
ahbso.hready <= r.hready;
-- pragma translate_off
bootmsg : report_version
generic map (
"can_oc" & tost(slvndx) &
": SJA1000 Compatible CAN MAC, revision " & tost(REVISION) &
", irq " & tost(irq));
-- pragma translate_on
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1976.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p03n01i01976ent IS
END c07s02b01x00p03n01i01976ent;
ARCHITECTURE c07s02b01x00p03n01i01976arch OF c07s02b01x00p03n01i01976ent IS
signal s : integer := 0;
function temp(s:integer) return boolean is
begin
assert FALSE
report "***FAILED TEST: c07s02b01x00p03n01i01976 - The right operand is evaluated only if the value of the left operand is not sufficient to determine the result of the operation."
severity ERROR;
return true;
end;
BEGIN
TESTING: PROCESS
variable x : boolean := false;
BEGIN
if x and (temp(s)) then
NULL;
end if;
wait for 1 ns;
assert FALSE
report "***PASSED TEST: c07s02b01x00p03n01i01976 - This test needs manual check, only when the FAILED TEST assertion do not appear then the test is passed."
severity NOTE;
wait;
END PROCESS TESTING;
END c07s02b01x00p03n01i01976arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1976.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p03n01i01976ent IS
END c07s02b01x00p03n01i01976ent;
ARCHITECTURE c07s02b01x00p03n01i01976arch OF c07s02b01x00p03n01i01976ent IS
signal s : integer := 0;
function temp(s:integer) return boolean is
begin
assert FALSE
report "***FAILED TEST: c07s02b01x00p03n01i01976 - The right operand is evaluated only if the value of the left operand is not sufficient to determine the result of the operation."
severity ERROR;
return true;
end;
BEGIN
TESTING: PROCESS
variable x : boolean := false;
BEGIN
if x and (temp(s)) then
NULL;
end if;
wait for 1 ns;
assert FALSE
report "***PASSED TEST: c07s02b01x00p03n01i01976 - This test needs manual check, only when the FAILED TEST assertion do not appear then the test is passed."
severity NOTE;
wait;
END PROCESS TESTING;
END c07s02b01x00p03n01i01976arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1976.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p03n01i01976ent IS
END c07s02b01x00p03n01i01976ent;
ARCHITECTURE c07s02b01x00p03n01i01976arch OF c07s02b01x00p03n01i01976ent IS
signal s : integer := 0;
function temp(s:integer) return boolean is
begin
assert FALSE
report "***FAILED TEST: c07s02b01x00p03n01i01976 - The right operand is evaluated only if the value of the left operand is not sufficient to determine the result of the operation."
severity ERROR;
return true;
end;
BEGIN
TESTING: PROCESS
variable x : boolean := false;
BEGIN
if x and (temp(s)) then
NULL;
end if;
wait for 1 ns;
assert FALSE
report "***PASSED TEST: c07s02b01x00p03n01i01976 - This test needs manual check, only when the FAILED TEST assertion do not appear then the test is passed."
severity NOTE;
wait;
END PROCESS TESTING;
END c07s02b01x00p03n01i01976arch;
|
----------------------------------------------------------------------------------------------------
-- ENTITY - GF(2^M) Interleaved Multiplier
-- Computes the polynomial multiplication a*b mod F IN GF(2**M) (LSB first)
--
-- Ports:
-- clk_i - Clock
-- rst_i - Reset flag
-- enable_i - Enable computation
-- a_i - First input value
-- b_i - Seccond input value
-- z_o - Output value
-- ready_o - Ready flag after computation
--
-- Example:
-- (x^2+x+1)*(x^2+1) = x^4+x^3+x+1
-- 1 1 1 * 1 0 1 = 11011 (bit-shift and XOR, shifts 2*M-2 bits)
--
-- BIT-SHIFT and XOR:
-- 11100 <- [1] 0 1 shift 2 bits
-- 111 <- 1 0 [1] shift 0 bits
-- 11011 <- XOR result
--
-- -> Result has more then M bits, so we've to reduce it by irreducible polynomial like 1011
-- 11011
-- 1011 <- shift 1 bits (degree 4 - degree 3)
-- 1101 <- shift 0 bits (degree 3 - degree 3)
-- 1011
-- 110
--
-- Based on:
-- http://arithmetic-circuits.org/finite-field/vhdl_Models/chapter10_codes/VHDL/K-163/interleaved_mult.vhd
--
-- Autor: Lennart Bublies (inf100434)
-- Date: 22.06.2017
----------------------------------------------------------------------------------------------------
-----------------------------------
-- GF(2^M) interleaved MSB-first multipication data path
-----------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
USE work.tld_ecdsa_package.all;
ENTITY e_gf2m_interleaved_data_path IS
GENERIC (
MODULO : std_logic_vector(M-1 DOWNTO 0)
);
PORT (
-- Clock and reset signals
clk_i: IN std_logic;
rst_i: IN std_logic;
-- Input signals
a_i: IN std_logic_vector(M-1 DOWNTO 0);
b_i: IN std_logic_vector(M-1 DOWNTO 0);
-- Load input, shift right and ???
inic_i: IN std_logic;
shiftr_i: IN std_logic;
cec_i: IN std_logic;
-- Output signals
z_o: OUT std_logic_vector(M-1 DOWNTO 0)
);
END e_gf2m_interleaved_data_path;
ARCHITECTURE rtl OF e_gf2m_interleaved_data_path IS
-- Internal signals
SIGNAL aa, bb, cc: std_logic_vector(M-1 DOWNTO 0);
SIGNAL new_a, new_c: std_logic_vector(M-1 DOWNTO 0);
BEGIN
-- Register and multiplexer
register_a: PROCESS(clk_i, rst_i)
BEGIN
IF rst_i = '1' THEN
aa <= (OTHERS => '0');
ELSIF clk_i'event and clk_i = '1' THEN
IF inic_i = '1' THEN
-- Load register a
aa <= a_i;
ELSE
-- Override register a with ???
aa <= new_a;
END IF;
END IF;
END PROCESS register_a;
shift_register_b: PROCESS(clk_i, rst_i)
BEGIN
IF rst_i = '1' THEN
bb <= (OTHERS => '0');
ELSIF clk_i'event and clk_i = '1' THEN
IF inic_i = '1' THEN
-- Load register b
bb <= b_i;
END IF;
IF shiftr_i = '1' THEN
-- Shift input of register b
bb <= '0' & bb(M-1 DOWNTO 1);
END IF;
END IF;
END PROCESS shift_register_b;
register_c: PROCESS(inic_i, clk_i, rst_i)
BEGIN
IF inic_i = '1' or rst_i = '1' THEN
cc <= (OTHERS => '0');
ELSIF clk_i'event and clk_i = '1' THEN
IF cec_i = '1' THEN
-- Set output register
cc <= new_c;
END IF;
END IF;
END PROCESS register_c;
-- Calculate next value for register a and c
new_a(0) <= aa(M-1) and MODULO(0);
new_a_calc: FOR i IN 1 TO M-1 GENERATE
new_a(i) <= aa(i-1) xor (aa(M-1) and MODULO(i));
END GENERATE;
new_c_calc: FOR i IN 0 TO M-1 GENERATE
new_c(i) <= cc(i) xor (aa(i) and bb(0));
END GENERATE;
-- Set output
z_o <= cc;
END rtl;
-----------------------------------
-- GF(2^M) interleaved multiplication
-----------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.tld_ecdsa_package.all;
ENTITY e_gf2m_interleaved_multiplier IS
GENERIC (
MODULO : std_logic_vector(M-1 DOWNTO 0) := ONE(M-1 DOWNTO 0)
);
PORT (
-- Clock, reset, enable
clk_i: IN std_logic;
rst_i: IN std_logic;
enable_i: IN std_logic;
-- Input signals
a_i: IN std_logic_vector (M-1 DOWNTO 0);
b_i: IN std_logic_vector (M-1 DOWNTO 0);
-- Output signals
z_o: OUT std_logic_vector (M-1 DOWNTO 0);
ready_o: OUT std_logic
);
END e_gf2m_interleaved_multiplier;
ARCHITECTURE rtl OF e_gf2m_interleaved_multiplier IS
-- Import entity e_gf2m_interleaved_data_path
COMPONENT e_gf2m_interleaved_data_path IS
GENERIC (
MODULO : std_logic_vector(M-1 DOWNTO 0)
);
PORT(
clk_i: IN std_logic;
rst_i: IN std_logic;
a_i: IN std_logic_vector(M-1 DOWNTO 0);
b_i: IN std_logic_vector(M-1 DOWNTO 0);
inic_i: IN std_logic;
shiftr_i: IN std_logic;
cec_i: IN std_logic;
z_o: OUT std_logic_vector(M-1 DOWNTO 0)
);
END COMPONENT;
SIGNAL inic, shiftr, cec: std_logic;
SIGNAL count: natural RANGE 0 TO M;
-- Define all available states
type states IS RANGE 0 TO 3;
SIGNAL current_state: states;
BEGIN
-- Instantiate interleaved data path
-- Used to computes the polynomial multiplication mod F in one step
data_path: e_gf2m_interleaved_data_path GENERIC MAP (
MODULO => MODULO
) PORT MAP (
clk_i => clk_i,
rst_i => rst_i,
a_i => a_i,
b_i => b_i,
inic_i => inic,
shiftr_i => shiftr,
cec_i => cec,
z_o => z_o
);
-- Clock signals
counter: PROCESS(rst_i, clk_i)
BEGIN
IF rst_i = '1' THEN
count <= 0;
ELSIF clk_i' event and clk_i = '1' THEN
-- Shift until all input bits are proceeds
IF inic = '1' THEN
count <= 0;
ELSIF shiftr = '1' THEN
count <= count+1;
END IF;
END IF;
END PROCESS counter;
-- State machine
control_unit: PROCESS(clk_i, rst_i, current_state)
BEGIN
-- Handle current state
-- 0,1 : Default state
-- 2 : Load input arguments (initialize registers)
-- 3 : Shift and add
CASE current_state IS
WHEN 0 TO 1 => inic <= '0'; shiftr <= '0'; cec <= '0'; ready_o <= '1';
WHEN 2 => inic <= '1'; shiftr <= '0'; cec <= '0'; ready_o <= '0';
WHEN 3 => inic <= '0'; shiftr <= '1'; cec <= '1'; ready_o <= '0';
END CASE;
IF rst_i = '1' THEN
-- Reset state if reset is high
current_state <= 0;
ELSIF clk_i'event and clk_i = '1' THEN
-- Set next state
CASE current_state IS
WHEN 0 =>
IF enable_i = '0' THEN
current_state <= 1;
END IF;
WHEN 1 =>
IF enable_i = '1' THEN
current_state <= 2;
END IF;
WHEN 2 =>
current_state <= 3;
WHEN 3 =>
IF count = M-1 THEN
current_state <= 0;
END IF;
END CASE;
END IF;
END PROCESS control_unit;
END rtl; |
-- Vhdl test bench created from schematic C:\Users\fafik\Dropbox\infa\git\ethernet\ethernet4b\CU_test1.sch - Sat Aug 30 21:25:04 2014
--
-- Notes:
-- 1) This testbench template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the unit under test.
-- Xilinx recommends that these types always be used for the top-level
-- I/O of a design in order to guarantee that the testbench will bind
-- correctly to the timing (post-route) simulation model.
-- 2) To use this template as your testbench, change the filename to any
-- name of your choice with the extension .vhd, and use the "Source->Add"
-- menu in Project Navigator to import the testbench. Then
-- edit the user defined section below, adding code to generate the
-- stimulus for your design.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY UNISIM;
USE UNISIM.Vcomponents.ALL;
ENTITY CU_test1_CU_test1_sch_tb IS
END CU_test1_CU_test1_sch_tb;
ARCHITECTURE behavioral OF CU_test1_CU_test1_sch_tb IS
COMPONENT CU_test1
PORT( clk : IN STD_LOGIC;
E_RX_D : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
E_RX_CLK : IN STD_LOGIC;
E_RX_DV : IN STD_LOGIC;
full : OUT STD_LOGIC;
test : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
REST : IN STD_LOGIC);
END COMPONENT;
SIGNAL clk : STD_LOGIC;
SIGNAL E_RX_D : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL E_RX_CLK : STD_LOGIC;
SIGNAL E_RX_DV : STD_LOGIC;
SIGNAL full : STD_LOGIC;
SIGNAL test : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL REST : STD_LOGIC;
BEGIN
UUT: CU_test1 PORT MAP(
clk => clk,
E_RX_D => E_RX_D,
E_RX_CLK => E_RX_CLK,
E_RX_DV => E_RX_DV,
full => full,
test => test,
REST => REST
);
process
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end process;
process
begin
E_RX_CLK <= '0';
wait for 10 ns;
E_RX_CLK <= '1';
wait for 10 ns;
end process;
E_RX_DV <= '0', '1' after 50 ns, '0' after 650 ns;
E_RX_D <= x"0",
x"1" after 50 ns,
x"2" after 70 ns,
x"3" after 90 ns,
x"4" after 110 ns,
x"5" after 130 ns,
x"6" after 150 ns,
x"7" after 170 ns,
x"8" after 190 ns,
x"9" after 210 ns,
x"a" after 230 ns,
x"b" after 250 ns,
x"c" after 270 ns,
x"d" after 290 ns,
x"e" after 310 ns,
x"f" after 330 ns,
x"0" after 350 ns,
x"1" after 370 ns,
x"2" after 390 ns,
x"3" after 410 ns,
x"4" after 430 ns,
x"5" after 450 ns,
x"6" after 470 ns,
x"7" after 490 ns,
x"8" after 510 ns,
x"9" after 530 ns,
x"a" after 550 ns,
x"b" after 570 ns,
x"c" after 590 ns,
x"d" after 610 ns,
x"e" after 630 ns;
END;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cover1 is
port (clk, rst: std_logic;
cnt : out unsigned(3 downto 0));
end cover1;
architecture behav of cover1 is
signal val : unsigned (3 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
val <= (others => '0');
else
val <= val + 1;
end if;
end if;
end process;
cnt <= val;
--psl default clock is rising_edge(clk);
--psl cover {val = 10};
end behav;
|
-------------------------------------------------------------------------------
-- --
-- Module : BRAM_S72_S72.vhd Last Update: --
-- --
-- Project : Parameterizable LocalLink FIFO --
-- --
-- Description : BRAM Macro with Dual Port, two data widths (64 and 64) --
-- made for LL_FIFO. --
-- --
-- Designer : Wen Ying Wei, Davy Huang --
-- --
-- Company : Xilinx, Inc. --
-- --
-- Disclaimer : THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY --
-- WHATSOEVER and XILinX SPECifICALLY DISCLAIMS ANY --
-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS For --
-- A PARTICULAR PURPOSE, or AGAinST inFRinGEMENT. --
-- THEY ARE ONLY inTENDED TO BE USED BY XILinX --
-- CUSTOMERS, and WITHin XILinX DEVICES. --
-- --
-- Copyright (c) 2003 Xilinx, Inc. --
-- All rights reserved --
-- --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity BRAM_S72_S72 is
port (ADDRA : in std_logic_vector (8 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
DIA : in std_logic_vector (63 downto 0);
DIPA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (63 downto 0);
DIPB : in std_logic_vector (7 downto 0);
WEA : in std_logic;
WEB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
ENA : in std_logic;
ENB : in std_logic;
DOA : out std_logic_vector (63 downto 0);
DOPA : out std_logic_vector(7 downto 0);
DOB : out std_logic_vector (63 downto 0);
DOPB : out std_logic_vector(7 downto 0));
end entity BRAM_S72_S72;
architecture BRAM_S72_S72_arch of BRAM_S72_S72 is
component RAMB16_S36_S36
port (
ADDRA: in std_logic_vector(8 downto 0);
ADDRB: in std_logic_vector(8 downto 0);
DIA: in std_logic_vector(31 downto 0);
DIPA: in std_logic_vector(3 downto 0);
DIB: in std_logic_vector(31 downto 0);
DIPB: in std_logic_vector(3 downto 0);
WEA: in std_logic;
WEB: in std_logic;
CLKA: in std_logic;
CLKB: in std_logic;
SSRA: in std_logic;
SSRB: in std_logic;
ENA: in std_logic;
ENB: in std_logic;
DOA: out std_logic_vector(31 downto 0);
DOPA: out std_logic_vector(3 downto 0);
DOB: out std_logic_vector(31 downto 0);
DOPB: out std_logic_vector(3 downto 0));
END component;
signal doa1 : std_logic_vector (31 downto 0);
signal dob1 : std_logic_vector (31 downto 0);
signal doa2 : std_logic_vector (31 downto 0);
signal dob2 : std_logic_vector (31 downto 0);
signal dia1 : std_logic_vector (31 downto 0);
signal dib1 : std_logic_vector (31 downto 0);
signal dia2 : std_logic_vector (31 downto 0);
signal dib2 : std_logic_vector (31 downto 0);
signal dipa1: std_logic_vector(3 downto 0);
signal dipa2: std_logic_vector(3 downto 0);
signal dipb1: std_logic_vector(3 downto 0);
signal dipb2: std_logic_vector(3 downto 0);
signal dopa1: std_logic_vector(3 downto 0);
signal dopa2: std_logic_vector(3 downto 0);
signal dopb1: std_logic_vector(3 downto 0);
signal dopb2: std_logic_vector(3 downto 0);
begin
dia1(15 downto 0) <= DIA(15 downto 0);
dia2(15 downto 0) <= DIA(31 downto 16);
dia1(31 downto 16) <= DIA(47 downto 32);
dia2(31 downto 16) <= DIA(63 downto 48);
dib1 <= DIB(31 downto 0);
dib2 <= DIB(63 downto 32);
DOA(31 downto 0) <= doa1;
DOA(63 downto 32) <= doa2;
DOB(31 downto 0) <= dob1;
DOB(63 downto 32) <= dob2;
dipa1 <= dipa(3 downto 0);
dipa2 <= dipa(7 downto 4);
dopa(3 downto 0) <= dopa1;
dopa(7 downto 4) <= dopa2;
dipb1 <= dipb(3 downto 0);
dipb2 <= dipb(7 downto 4);
dopb(3 downto 0) <= dopb1;
dopb(7 downto 4) <= dopb2;
bram1: RAMB16_S36_S36
port map (
ADDRA => addra(8 downto 0),
ADDRB => addrb(8 downto 0),
DIA => dia1,
DIPA => dipa1,
DIB => dib1,
DIPB => dipb1,
WEA => wea,
WEB => web,
CLKA => clka,
CLKB => clkb,
SSRA => ssra,
SSRB => ssrb,
ENA => ena,
ENB => enb,
DOA => doa1,
DOPA => dopa1,
DOB => dob1,
DOPB => dopb1);
bram2: RAMB16_S36_S36
port map (
ADDRA => addra(8 downto 0),
ADDRB => addrb(8 downto 0),
DIA => dia2,
DIPA => dipa2,
DIB => dib2,
DIPB => dipb2,
WEA => wea,
WEB => web,
CLKA => clka,
CLKB => clkb,
SSRA => ssra,
SSRB => ssrb,
ENA => ena,
ENB => enb,
DOA => doa2,
DOPA => dopa2,
DOB => dob2,
DOPB => dopb2);
end BRAM_S72_S72_arch;
|
--------------------------------------------------------------------------------
-- Company: Lehrstuhl Integrierte Systeme - TUM
-- Engineer: Johannes Zeppenfeld
--
-- Project Name: LIS-IPIF
-- Module Name: lipif_slv_write
-- Architectures: lipif_slv_write_rtl
-- Description:
--
-- Dependencies:
--
-- Revision:
-- 11.4.2006 - File Created
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library lisipif_master_v1_00_c;
use lisipif_master_v1_00_c.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity lipif_mst_write is
generic (
C_NUM_WIDTH : integer := 5;
C_EN_SRL16 : boolean := true;
C_EN_FAST_ABORT : boolean := false
);
port (
clk : in std_logic;
reset : in std_logic;
-- Control Signals to/from Arbiter
xfer_rdy_o : out std_logic;
xfer_init_i : in std_logic;
xfer_ack_i : in std_logic;
xfer_rearb_i : in std_logic;
xfer_retry_o : out std_logic;
xfer_abort_o : out std_logic;
-- LIS-IPIC Transfer Signals
M_wrNum_i : in std_logic_vector(C_NUM_WIDTH-1 downto 0);
M_wrRearb_o : out std_logic;
M_wrAbort_i : in std_logic;
M_wrError_o : out std_logic;
M_wrData_i : in std_logic_vector(63 downto 0);
M_wrRdy_o : out std_logic;
M_wrAck_o : out std_logic;
M_wrComp_o : out std_logic;
-- PLB Signals
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic;
M_wrBurst : out std_logic;
M_wrDBus : out std_logic_vector(0 to 63)
);
end lipif_mst_write;
architecture lipif_mst_write_rtl of lipif_mst_write is
signal prim_valid : std_logic;
signal prim_ack : std_logic;
signal prim_num : std_logic_vector(C_NUM_WIDTH-1 downto 0);
signal prim_num_n : std_logic_vector(C_NUM_WIDTH-1 downto 0);
signal prim_comp : std_logic;
signal prim_last : std_logic;
signal prim_last_n : std_logic;
-- Transfer termination requests from IP/PLB
signal mst_term : std_logic;
signal mst_term_r : std_logic; -- Track until transfer complete
signal plb_term : std_logic;
signal data_num : std_logic_vector(C_NUM_WIDTH-1 downto 0);
signal data_num_n : std_logic_vector(C_NUM_WIDTH-1 downto 0);
signal data_done : std_logic;
signal data_req : std_logic;
signal data_rdy : std_logic;
signal data_flush : std_logic;
begin
-- Signals to load new data into data buffer
data_done <= '1' when (data_num=0) else '0';
data_req <= data_rdy and (not data_done or xfer_init_i);
M_wrRdy_o <= data_req;
-- Flush data buffer if transfer aborted prematurely
data_flush <= reset or (prim_comp and not prim_last);
-- Pipelining not possible due to the inability of inserting a
-- latency after a slave-initiated transfer termination.
xfer_rdy_o <= not prim_valid;
-- Pass rearbitration signal to IP
M_wrRearb_o <= xfer_rearb_i and not prim_ack;
-- Control signals to arbiter (Affect arbiter only!)
xfer_retry_o <= xfer_rearb_i and not prim_ack;
xfer_abort_o <= mst_term and prim_valid and not prim_ack;
-- Next IP data count, subtraction and ce occur below
data_num_n <= M_wrNum_i when (xfer_init_i='1') else data_num;
-- Assert prim_comp to complete transfer:
-- * with last d-ack of transfer
-- * with next d-ack when plb_term or mst_term are asserted
-- * with mst_term when primary transfer not acknowledged
process(PLB_MWrDAck, prim_last, plb_term, mst_term, prim_ack) begin
if(PLB_MWrDAck='1') then
prim_comp <= prim_last or plb_term or mst_term;
else
prim_comp <= mst_term and not prim_ack;
end if;
end process;
-- Generate PLB remaining transfer counter signals (M_wrBurst, prim_num, prim_last)
-- TIMING(18%) M_wrBurst is a register, so no problem
-- TODO: When C_EN_FAST_ABORT, M_wrBurst must respond with M_wrAbort
prim_num_n <= M_wrNum_i when(xfer_init_i='1') else prim_num - 1;
prim_last_n <= '1' when (prim_num_n(C_NUM_WIDTH-1 downto 1)=0) else '0';
process(clk) begin
if(clk='1' and clk'event) then
if(reset='1') then
M_wrBurst <= '0';
prim_last <= '0';
prim_num <= (others=>'0');
else
-- Burst must go low in response to PLB/IP abort
if(PLB_MWrBTerm='1' or M_wrAbort_i='1') then
M_wrBurst <= '0';
-- Update burst signal at start of transfer, or with each data ack
elsif(xfer_init_i='1' or PLB_MWrDAck='1') then
M_wrBurst <= not prim_last_n;
end if;
-- Update transfer counter at start of transfer, or with each data ack
if(xfer_init_i='1' or PLB_MWrDAck='1') then
prim_last <= prim_last_n;
prim_num <= prim_num_n;
end if;
end if;
end if;
end process;
-- Latch IP termination request until completion of transfer
process(clk) begin
if(clk='1' and clk'event) then
if(reset='1') then
mst_term_r <= '0';
else
if(prim_comp='1') then
mst_term_r <= '0';
elsif(M_wrAbort_i='1') then
mst_term_r <= '1';
end if;
end if;
end if;
end process;
-- When not C_EN_FAST_ABORT, assert terminate signal immediately only if rearbitrating
-- TODO: Remove resulting combinatorial dependance of M_abort on M_wrAbort_i
NEN_FAST_ABORT: if(not C_EN_FAST_ABORT) generate
mst_term <= M_wrAbort_i when(xfer_rearb_i='1') else mst_term_r;
end generate NEN_FAST_ABORT;
-- When C_EN_FAST_ABORT, always pass M_wrAbort_i through
EN_FAST_ABORT: if(C_EN_FAST_ABORT) generate
mst_term <= '1' when(mst_term_r='1') else M_wrAbort_i;
end generate EN_FAST_ABORT;
-- Various registers
process(clk) begin
if(clk='1' and clk'event) then
if(reset='1') then
prim_valid <= '0';
prim_ack <= '0';
data_num <= (others=>'0');
M_wrError_o <= '0';
M_wrComp_o <= '0';
M_wrAck_o <= '0';
plb_term <= '0';
else
-- Primary transfer valid
if(xfer_init_i='1') then
prim_valid <= '1';
elsif(prim_comp='1') then
prim_valid <= '0';
end if;
-- Primary transfer acknowledged by slave
if(xfer_ack_i='1') then
prim_ack <= '1';
elsif(prim_comp='1') then
prim_ack <= '0';
end if;
-- Remaining IP required data count
if(prim_comp='1') then
data_num <= (others=>'0');
elsif(data_req='1') then
data_num <= data_num_n - 1;
else
data_num <= data_num_n;
end if;
-- Error occurred if transfer completes before all data was transferred,
-- or if transfer was never acknowledged
M_wrError_o <= prim_comp and (not prim_last or (not prim_ack and not xfer_ack_i));
-- IPIC's complete signal is pipeliner's complete signal delayed
M_wrComp_o <= prim_comp;
-- Data acknowledge to IP
M_wrAck_o <= PLB_MWrDAck;
-- Previous termination request by slave
if(prim_comp='1') then
plb_term <= '0';
elsif(PLB_MWrBTerm='1') then
plb_term <= '1';
end if;
end if;
end if;
end process;
-- Instantiate data buffer
pipebuf_0: entity lisipif_master_v1_00_c.lipif_mst_pipebuf
generic map (
C_DATA_WIDTH => 64,
-- Since SRL outputs are slow (>3ns after clk), must use registers
-- to meet PLB timings.
C_EN_SRL16 => false
)
port map (
clk => clk,
reset => data_flush,
-- Previous (input) stage I/O
prevReq_i => data_req,
prevRdy_o => data_rdy,
prevData_i => M_wrData_i,
-- Next (output) stage I/O
nextReq_o => open,
nextRdy_i => PLB_MWrDAck,
nextData_o => M_wrDBus
);
end lipif_mst_write_rtl;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: logan
-- File: logan.vhd
-- Author: Kristoffer Carlsson, Gaisler Research
-- Description: On-chip logic analyzer IP core
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
entity logan is
generic (
dbits : integer range 0 to 256 := 32; -- Number of traced signals
depth : integer range 256 to 16384 := 1024; -- Depth of trace buffer
trigl : integer range 1 to 63 := 1; -- Number of trigger levels
usereg : integer range 0 to 1 := 1; -- Use input register
usequal : integer range 0 to 1 := 0; -- Use qualifer bit
usediv : integer range 0 to 1 := 1; -- Enable/disable div counter
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#F00#;
memtech : integer := DEFMEMTECH);
port (
rstn : in std_logic; -- Synchronous reset
clk : in std_logic; -- System clock
tclk : in std_logic; -- Trace clock
apbi : in apb_slv_in_type; -- APB in record
apbo : out apb_slv_out_type; -- APB out record
signals : in std_logic_vector(dbits - 1 downto 0)); -- Traced signals
end logan;
architecture rtl of logan is
constant REVISION : amba_version_type := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_LOGAN, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
constant abits: integer := 8 + log2x(depth/256 - 1);
constant az : std_logic_vector(abits-1 downto 0) := (others => '0');
constant dz : std_logic_vector(dbits-1 downto 0) := (others => '0');
type trig_cfg_type is record
pattern : std_logic_vector(dbits-1 downto 0); -- Pattern to trig on
mask : std_logic_vector(dbits-1 downto 0); -- trigger mask
count : std_logic_vector(5 downto 0); -- match counter
eq : std_ulogic; -- Trig on match or no match?
end record;
type trig_cfg_arr is array (0 to trigl-1) of trig_cfg_type;
type reg_type is record
armed : std_ulogic;
trig_demet : std_ulogic;
trigged : std_ulogic;
fin_demet : std_ulogic;
finished : std_ulogic;
qualifier : std_logic_vector(7 downto 0);
qual_val : std_ulogic;
divcount : std_logic_vector(15 downto 0);
counter : std_logic_vector(abits-1 downto 0);
page : std_logic_vector(3 downto 0);
trig_conf : trig_cfg_arr;
end record;
type trace_reg_type is record
armed : std_ulogic;
arm_demet : std_ulogic;
trigged : std_ulogic;
finished : std_ulogic;
sample : std_ulogic;
divcounter : std_logic_vector(15 downto 0);
match_count : std_logic_vector(5 downto 0);
counter : std_logic_vector(abits-1 downto 0);
curr_tl : integer range 0 to trigl-1;
w_addr : std_logic_vector(abits-1 downto 0);
end record;
signal r_addr : std_logic_vector(13 downto 0);
signal bufout : std_logic_vector(255 downto 0);
signal r_en : std_ulogic;
signal r, rin : reg_type;
signal tr, trin : trace_reg_type;
signal sigreg : std_logic_vector(dbits-1 downto 0);
signal sigold : std_logic_vector(dbits-1 downto 0);
begin
bufout(255 downto dbits) <= (others => '0');
-- Combinatorial process for AMBA clock domain
comb1: process(rstn, apbi, r, tr, bufout)
variable v : reg_type;
variable rdata : std_logic_vector(31 downto 0);
variable tl : integer range 0 to trigl-1;
variable pattern, mask : std_logic_vector(255 downto 0);
begin
v := r;
rdata := (others => '0'); tl := 0;
pattern := (others => '0'); mask := (others => '0');
-- Two stage synch
v.trig_demet := tr.trigged;
v.trigged := r.trig_demet;
v.fin_demet := tr.finished;
v.finished := r.fin_demet;
if r.finished = '1' then
v.armed := '0';
end if;
r_en <= '0';
-- Read/Write --
if apbi.psel(pindex) = '1' then
-- Write
if apbi.pwrite = '1' and apbi.penable = '1' then
-- Only conf area writeable
if apbi.paddr(15) = '0' then
-- pattern/mask
if apbi.paddr(14 downto 13) = "11" then
tl := conv_integer(apbi.paddr(11 downto 6));
pattern(dbits-1 downto 0) := v.trig_conf(tl).pattern;
mask(dbits-1 downto 0) := v.trig_conf(tl).mask;
case apbi.paddr(5 downto 2) is
when "0000" => pattern(31 downto 0) := apbi.pwdata;
when "0001" => pattern(63 downto 32) := apbi.pwdata;
when "0010" => pattern(95 downto 64) := apbi.pwdata;
when "0011" => pattern(127 downto 96) := apbi.pwdata;
when "0100" => pattern(159 downto 128) := apbi.pwdata;
when "0101" => pattern(191 downto 160) := apbi.pwdata;
when "0110" => pattern(223 downto 192) := apbi.pwdata;
when "0111" => pattern(255 downto 224) := apbi.pwdata;
when "1000" => mask(31 downto 0) := apbi.pwdata;
when "1001" => mask(63 downto 32) := apbi.pwdata;
when "1010" => mask(95 downto 64) := apbi.pwdata;
when "1011" => mask(127 downto 96) := apbi.pwdata;
when "1100" => mask(159 downto 128) := apbi.pwdata;
when "1101" => mask(191 downto 160) := apbi.pwdata;
when "1110" => mask(223 downto 192) := apbi.pwdata;
when "1111" => mask(255 downto 224) := apbi.pwdata;
when others => null;
end case;
-- write back updated pattern/mask
v.trig_conf(tl).pattern := pattern(dbits-1 downto 0);
v.trig_conf(tl).mask := mask(dbits-1 downto 0);
-- count/eq
elsif apbi.paddr(14 downto 13) = "01" then
tl := conv_integer(apbi.paddr(7 downto 2));
v.trig_conf(tl).count := apbi.pwdata(6 downto 1);
v.trig_conf(tl).eq := apbi.pwdata(0);
-- arm/reset
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00000" then
v.armed := apbi.pwdata(0);
-- Page reg
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00010" then
v.page := apbi.pwdata(3 downto 0);
-- Trigger counter
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00011" then
v.counter := apbi.pwdata(abits-1 downto 0);
-- div count
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00100" then
v.divcount := apbi.pwdata(15 downto 0);
-- qualifier bit
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00101" then
v.qualifier := apbi.pwdata(7 downto 0);
v.qual_val := apbi.pwdata(8);
end if;
end if;
-- end write
-- Read
else
-- Read config/status area
if apbi.paddr(15) = '0' then
-- pattern/mask
if apbi.paddr(14 downto 13) = "11" then
tl := conv_integer(apbi.paddr(11 downto 6));
pattern(dbits-1 downto 0) := v.trig_conf(tl).pattern;
mask(dbits-1 downto 0) := v.trig_conf(tl).mask;
case apbi.paddr(5 downto 2) is
when "0000" => rdata := pattern(31 downto 0);
when "0001" => rdata := pattern(63 downto 32);
when "0010" => rdata := pattern(95 downto 64);
when "0011" => rdata := pattern(127 downto 96);
when "0100" => rdata := pattern(159 downto 128);
when "0101" => rdata := pattern(191 downto 160);
when "0110" => rdata := pattern(223 downto 192);
when "0111" => rdata := pattern(255 downto 224);
when "1000" => rdata := mask(31 downto 0);
when "1001" => rdata := mask(63 downto 32);
when "1010" => rdata := mask(95 downto 64);
when "1011" => rdata := mask(127 downto 96);
when "1100" => rdata := mask(159 downto 128);
when "1101" => rdata := mask(191 downto 160);
when "1110" => rdata := mask(223 downto 192);
when "1111" => rdata := mask(255 downto 224);
when others => rdata := (others => '0');
end case;
-- count/eq
elsif apbi.paddr(14 downto 13) = "01" then
tl := conv_integer(apbi.paddr(7 downto 2));
rdata(6 downto 1) := v.trig_conf(tl).count;
rdata(0) := v.trig_conf(tl).eq;
-- status
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00000" then
rdata := conv_std_logic_vector(usereg,1) & conv_std_logic_vector(usequal,1) &
r.armed & r.trigged &
conv_std_logic_vector(dbits,8)&
conv_std_logic_vector(depth-1,14)&
conv_std_logic_vector(trigl,6);
-- trace buffer index
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00001" then
rdata(abits-1 downto 0) := tr.w_addr(abits-1 downto 0);
-- page reg
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00010" then
rdata(3 downto 0) := r.page;
-- trigger counter
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00011" then
rdata(abits-1 downto 0) := r.counter;
-- divcount
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00100" then
rdata(15 downto 0) := r.divcount;
-- qualifier
elsif apbi.paddr(14 downto 13)&apbi.paddr(4 downto 2) = "00101" then
rdata(7 downto 0) := r.qualifier;
rdata(8) := r.qual_val;
end if;
-- Read from trace buffer
else
-- address always r.page & apbi.paddr(14 downto 5)
r_en <= '1';
-- Select word from pattern
case apbi.paddr(4 downto 2) is
when "000" => rdata := bufout(31 downto 0);
when "001" => rdata := bufout(63 downto 32);
when "010" => rdata := bufout(95 downto 64);
when "011" => rdata := bufout(127 downto 96);
when "100" => rdata := bufout(159 downto 128);
when "101" => rdata := bufout(191 downto 160);
when "110" => rdata := bufout(223 downto 192);
when "111" => rdata := bufout(255 downto 224);
when others => rdata := (others => '0');
end case;
end if;
end if; -- end read
end if;
if rstn = '0' then
v.armed := '0'; v.trigged := '0'; v.finished := '0'; v.trig_demet := '0'; v.fin_demet := '0';
v.counter := (others => '0');
v.divcount := X"0001";
v.qualifier := (others => '0');
v.qual_val := '0';
v.page := (others => '0');
end if;
apbo.prdata <= rdata;
rin <= v;
end process;
-- Combinatorial process for trace clock domain
comb2 : process (rstn, tr, r, sigreg)
variable v : trace_reg_type;
begin
v := tr;
v.sample := '0';
if tr.armed = '0' then
v.trigged := '0'; v.counter := (others => '0'); v.curr_tl := 0;
end if;
-- Synch arm signal
v.arm_demet := r.armed;
v.armed := tr.arm_demet;
if tr.finished = '1' then
v.finished := tr.armed;
end if;
-- Trigger --
if tr.armed = '1' and tr.finished = '0' then
if usediv = 1 then
if tr.divcounter = X"0000" then
v.divcounter := r.divcount-1;
if usequal = 0 or sigreg(conv_integer(r.qualifier)) = r.qual_val then
v.sample := '1';
end if;
else
v.divcounter := v.divcounter - 1;
end if;
else
v.sample := '1';
end if;
if tr.sample = '1' then v.w_addr := tr.w_addr + 1; end if;
if tr.trigged = '1' and tr.sample = '1' then
if tr.counter = r.counter then
v.trigged := '0';
v.sample := '0';
v.finished := '1';
v.counter := (others => '0');
else v.counter := tr.counter + 1; end if;
else
-- match?
if ((sigreg xor r.trig_conf(tr.curr_tl).pattern) and r.trig_conf(tr.curr_tl).mask) = dz then
-- trig on equal
if r.trig_conf(tr.curr_tl).eq = '1' then
if tr.match_count /= r.trig_conf(tr.curr_tl).count then
v.match_count := tr.match_count + 1;
else
-- final match?
if tr.curr_tl = trigl-1 then
v.trigged := '1';
else
v.curr_tl := tr.curr_tl + 1;
end if;
end if;
end if;
else -- not a match
-- trig on inequal
if r.trig_conf(tr.curr_tl).eq = '0' then
if tr.match_count /= r.trig_conf(tr.curr_tl).count then
v.match_count := tr.match_count + 1;
else
-- final match?
if tr.curr_tl = trigl-1 then
v.trigged := '1';
else
v.curr_tl := tr.curr_tl + 1;
end if;
end if;
end if;
end if;
end if;
end if;
-- end trigger
if rstn = '0' then
v.armed := '0'; v.trigged := '0'; v.sample := '0'; v.finished := '0'; v.arm_demet := '0';
v.curr_tl := 0;
v.counter := (others => '0');
v.divcounter := (others => '0');
v.match_count := (others => '0');
v.w_addr := (others => '0');
end if;
trin <= v;
end process;
-- clk traced signals through register to minimize fan out
inreg: if usereg = 1 generate
process (tclk)
begin
if rising_edge(tclk) then
sigold <= sigreg;
sigreg <= signals;
end if;
end process;
end generate;
noinreg: if usereg = 0 generate
sigreg <= signals;
sigold <= signals;
end generate;
-- Update registers
reg: process(clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process;
treg: process(tclk)
begin
if rising_edge(tclk) then tr <= trin; end if;
end process;
r_addr <= r.page & apbi.paddr(14 downto 5);
trace_buf : syncram_2p
generic map (tech => memtech, abits => abits, dbits => dbits)
port map (clk, r_en, r_addr(abits-1 downto 0), bufout(dbits-1 downto 0), -- read
tclk, tr.sample, tr.w_addr, sigold); -- write
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
apbo.pirq <= (others => '0');
end architecture;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
-- Patrick Lehmann
--
-- Module: UART Wrapper with Embedded FIFOs and Optional Flow Control
--
-- Description:
-- ------------------------------------
-- Small FIFOs are included in this module, if larger or asynchronous
-- transmit / receive FIFOs are required, then they must be connected
-- externally.
--
-- old comments:
-- UART BAUD rate generator
-- bclk = bit clock is rising
-- bclk_x8 = bit clock times 8 is rising
--
--
-- License:
-- ============================================================================
-- Copyright 2008-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
library PoC;
use PoC.vectors.all;
use PoC.physical.all;
use PoC.components.all;
use PoC.uart.all;
entity uart_fifo is
generic (
-- Communication Parameters
CLOCK_FREQ : FREQ;
BAUDRATE : BAUD;
-- Buffer Dimensioning
TX_MIN_DEPTH : positive := 16;
TX_ESTATE_BITS : natural := 0;
RX_MIN_DEPTH : positive := 16;
RX_FSTATE_BITS : natural := 0;
-- Flow Control
FLOWCONTROL : T_IO_UART_FLOWCONTROL_KIND := UART_FLOWCONTROL_NONE;
SWFC_XON_CHAR : std_logic_vector(7 downto 0) := x"11"; -- ^Q
SWFC_XON_TRIGGER : real := 0.0625;
SWFC_XOFF_CHAR : std_logic_vector(7 downto 0) := x"13"; -- ^S
SWFC_XOFF_TRIGGER : real := 0.75
);
port (
Clock : in std_logic;
Reset : in std_logic;
-- FIFO interface
TX_put : in STD_LOGIC;
TX_Data : in STD_LOGIC_VECTOR(7 downto 0);
TX_Full : out STD_LOGIC;
TX_EmptyState : out STD_LOGIC_VECTOR(TX_ESTATE_BITS - 1 downto 0);
RX_Valid : out STD_LOGIC;
RX_Data : out STD_LOGIC_VECTOR(7 downto 0);
RX_got : in STD_LOGIC;
RX_FullState : out STD_LOGIC_VECTOR(RX_FSTATE_BITS - 1 downto 0);
RX_Overflow : out std_logic;
-- External pins
UART_TX : out std_logic;
UART_RX : in std_logic
);
end entity;
architecture rtl of uart_fifo is
signal FC_TX_Strobe : STD_LOGIC;
signal FC_TX_Data : T_SLV_8;
signal FC_TX_got : STD_LOGIC;
signal FC_RX_put : STD_LOGIC;
signal FC_RX_Data : T_SLV_8;
signal TXFIFO_Valid : STD_LOGIC;
signal TXFIFO_Data : T_SLV_8;
signal RXFIFO_Full : STD_LOGIC;
signal TXUART_Full : STD_LOGIC;
signal RXUART_Strobe : STD_LOGIC;
signal RXUART_Data : T_SLV_8;
signal BitClock : STD_LOGIC;
signal BitClock_x8 : STD_LOGIC;
signal UART_RX_sync : STD_LOGIC;
begin
assert FALSE report "uart_fifo: BAUDRATE=: " & to_string(BAUDRATE, 3) severity NOTE;
-- ===========================================================================
-- Transmit and Receive FIFOs
-- ===========================================================================
TXFIFO : entity PoC.fifo_cc_got
generic map (
D_BITS => 8, -- Data Width
MIN_DEPTH => TX_MIN_DEPTH, -- Minimum FIFO Depth
DATA_REG => TRUE, -- Store Data Content in Registers
STATE_REG => FALSE, -- Registered Full/Empty Indicators
OUTPUT_REG => FALSE, -- Registered FIFO Output
ESTATE_WR_BITS => TX_ESTATE_BITS, -- Empty State Bits
FSTATE_RD_BITS => 0 -- Full State Bits
)
port map (
rst => Reset,
clk => Clock,
put => TX_put,
din => TX_Data,
full => TX_Full,
estate_wr => TX_EmptyState,
valid => TXFIFO_Valid,
dout => TXFIFO_Data,
got => FC_TX_got,
fstate_rd => open
);
RXFIFO : entity PoC.fifo_cc_got
generic map (
D_BITS => 8, -- Data Width
MIN_DEPTH => RX_MIN_DEPTH, -- Minimum FIFO Depth
DATA_REG => TRUE, -- Store Data Content in Registers
STATE_REG => FALSE, -- Registered Full/Empty Indicators
OUTPUT_REG => FALSE, -- Registered FIFO Output
ESTATE_WR_BITS => 0, -- Empty State Bits
FSTATE_RD_BITS => RX_FSTATE_BITS -- Full State Bits
)
port map (
rst => Reset,
clk => Clock,
put => FC_RX_put,
din => FC_RX_Data,
full => RXFIFO_Full,
estate_wr => open,
valid => RX_Valid,
dout => RX_Data,
got => RX_got,
fstate_rd => RX_FullState
);
genNOFC : if (FLOWCONTROL = UART_FLOWCONTROL_NONE) generate
signal Overflow_r : std_logic := '0';
begin
FC_TX_Strobe <= TXFIFO_Valid and not TXUART_Full;
FC_TX_Data <= TXFIFO_Data;
FC_TX_got <= FC_TX_Strobe;
FC_RX_put <= RXUART_Strobe;
FC_RX_Data <= RXUART_Data;
Overflow_r <= ffrs(q => Overflow_r, rst => Reset, set => (RXUART_Strobe and RXFIFO_Full)) when rising_edge(Clock);
RX_Overflow <= Overflow_r;
end generate;
-- ===========================================================================
-- Software Flow Control
-- ===========================================================================
genSWFC : if (FLOWCONTROL = UART_FLOWCONTROL_XON_XOFF) generate
constant XON : std_logic_vector(7 downto 0) := x"11"; -- ^Q
constant XOFF : std_logic_vector(7 downto 0) := x"13"; -- ^S
constant XON_TRIG : integer := integer(SWFC_XON_TRIGGER * real(2**RX_FSTATE_BITS));
constant XOFF_TRIG : integer := integer(SWFC_XOFF_TRIGGER * real(2**RX_FSTATE_BITS));
signal send_xoff : std_logic;
signal send_xon : std_logic;
signal set_xoff_transmitted : std_logic;
signal clr_xoff_transmitted : std_logic;
signal discard_user : std_logic;
signal set_overflow : std_logic;
-- registers
signal xoff_transmitted : std_logic;
begin
-- -- send XOFF only once when fill state goes above trigger level
-- send_xoff <= (not xoff_transmitted) when (rf_fs >= XOFF_TRIG) else '0';
-- set_xoff_transmitted <= tx_rdy when (rf_fs >= XOFF_TRIG) else '0';
--
-- -- send XON only once when receive FIFO is almost empty
-- send_xon <= xoff_transmitted when (rf_fs = XON_TRIG) else '0';
-- clr_xoff_transmitted <= tx_rdy when (rf_fs = XON_TRIG) else '0';
--
-- -- discard any user supplied XON/XOFF
-- discard_user <= '1' when (tf_dout = SWFC_XON_CHAR) or (tf_dout = SWFC_XOFF_CHAR) else '0';
--
-- -- tx / tf control
-- tx_din <= SWFC_XOFF_CHAR when (send_xoff = '1') else
-- SWFC_XON_CHAR when (send_xon = '1') else
-- tf_dout;
--
-- tx_stb <= send_xoff or send_xon or (tf_valid and (not discard_user));
-- tf_got <= (send_xoff nor send_xon) and
-- tf_valid and tx_rdy; -- always check tf_valid
--
-- -- rx / rf control
-- rf_put <= (not rf_full) and rx_dos; -- always check rf_full
-- rf_din <= rx_dout;
--
-- set_overflow <= rf_full and rx_dos;
--
-- -- registers
-- process (Clock)
-- begin -- process
-- if rising_edge(Clock) then
-- if (rst or set_xoff_transmitted) = '1' then
-- -- send a XON after reset
-- xoff_transmitted <= '1';
-- elsif clr_xoff_transmitted = '1' then
-- xoff_transmitted <= '0';
-- end if;
--
-- if rst = '1' then
-- overflow <= '0';
-- elsif set_overflow = '1' then
-- overflow <= '1';
-- end if;
-- end if;
-- end process;
end generate;
-- ===========================================================================
-- Hardware Flow Control
-- ===========================================================================
genHWFC1 : if (FLOWCONTROL = UART_FLOWCONTROL_RTS_CTS) generate
begin
end generate;
-- ===========================================================================
-- Hardware Flow Control
-- ===========================================================================
genHWFC2 : if (FLOWCONTROL = UART_FLOWCONTROL_RTR_CTS) generate
begin
end generate;
-- ===========================================================================
-- BitClock, Transmitter, Receiver
-- ===========================================================================
genNoSync : if (ADD_INPUT_SYNCHRONIZERS = FALSE) generate
UART_RX_sync <= UART_RX;
end generate;
genSync: if (ADD_INPUT_SYNCHRONIZERS = TRUE) generate
sync_i : entity PoC.sync_Bits
port map (
Clock => Clock, -- Clock to be synchronized to
Input(0) => UART_RX, -- Data to be synchronized
Output(0) => UART_RX_sync -- synchronised data
);
end generate;
-- ===========================================================================
-- BitClock, Transmitter, Receiver
-- ===========================================================================
bclk : entity PoC.uart_bclk
generic map (
CLOCK_FREQ => CLOCK_FREQ,
BAUDRATE => BAUDRATE
)
port map (
clk => Clock,
rst => Reset,
bclk => BitClock,
bclk_x8 => BitClock_x8
);
TX : entity PoC.uart_tx
port map (
clk => Clock,
rst => Reset,
bclk => BitClock,
tx => UART_TX
di => FC_TX_Data,
put => FC_TX_Strobe,
ful => TXUART_Full
);
RX : entity PoC.uart_rx
port map (
clk => Clock,
rst => Reset,
bclk_x8 => BitClock_x8,
rx => UART_RX_sync,
do => RXUART_Data,
stb => RXUART_Strobe
);
end architecture;
|
architecture RTL of FIFO is
begin
process
begin
loop
end loop;
-- Violations below
loop end loop;
end process;
end;
|
---------------------------------------------------------------------------------------------------
--
-- Title : dma_config
-- Design : ring bus
-- Author : Zhao Ming
-- Company : a4a881d4
--
---------------------------------------------------------------------------------------------------
--
-- File : dma_config.vhd
-- Generated : 2013/9/10
-- From :
-- By :
--
---------------------------------------------------------------------------------------------------
--
-- Description : dma reg config
--
-- Rev: 3.1
--
---------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package dma_config is
-- DMA reg
constant reg_RESET : std_logic_vector( 3 downto 0 ) := "0000";
constant reg_START : std_logic_vector( 3 downto 0 ) := "1111";
constant reg_DADDR : std_logic_vector( 3 downto 0 ) := "0001";
constant reg_SADDR : std_logic_vector( 3 downto 0 ) := "0010";
constant reg_LEN : std_logic_vector( 3 downto 0 ) := "0011";
-- BUS reg
constant reg_BADDR : std_logic_vector( 3 downto 0 ) := "0100";
constant reg_BID : std_logic_vector( 3 downto 0 ) := "0101";
--
constant reg_BUSY : std_logic_vector( 3 downto 0 ) := "0000";
constant max_payload : natural := 32;
component DMANP
generic(
Bwidth : natural := 128;
SAwidth : natural := 16;
DAwidth : natural := 32;
Lwidth : natural := 16
);
port(
-- system signal
clk : in STD_LOGIC;
rst : in STD_LOGIC;
-- Tx interface
header: out std_logic_vector(Bwidth-1 downto 0);
Req : out std_logic;
laddr : out std_logic_vector(SAwidth-1 downto 0);
busy : in std_logic;
tx_sop : in std_logic;
-- CPU bus
CS : in std_logic;
wr : in std_logic;
rd : in std_logic;
addr : in std_logic_vector( 3 downto 0 );
Din : in std_logic_vector( 7 downto 0 );
Dout : out std_logic_vector( 7 downto 0 );
cpuClk : in std_logic;
-- Priority
en : in std_logic
);
end component;
end dma_config;
|
---------------------------------------------------------------------------------------------------
--
-- Title : dma_config
-- Design : ring bus
-- Author : Zhao Ming
-- Company : a4a881d4
--
---------------------------------------------------------------------------------------------------
--
-- File : dma_config.vhd
-- Generated : 2013/9/10
-- From :
-- By :
--
---------------------------------------------------------------------------------------------------
--
-- Description : dma reg config
--
-- Rev: 3.1
--
---------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package dma_config is
-- DMA reg
constant reg_RESET : std_logic_vector( 3 downto 0 ) := "0000";
constant reg_START : std_logic_vector( 3 downto 0 ) := "1111";
constant reg_DADDR : std_logic_vector( 3 downto 0 ) := "0001";
constant reg_SADDR : std_logic_vector( 3 downto 0 ) := "0010";
constant reg_LEN : std_logic_vector( 3 downto 0 ) := "0011";
-- BUS reg
constant reg_BADDR : std_logic_vector( 3 downto 0 ) := "0100";
constant reg_BID : std_logic_vector( 3 downto 0 ) := "0101";
--
constant reg_BUSY : std_logic_vector( 3 downto 0 ) := "0000";
constant max_payload : natural := 32;
component DMANP
generic(
Bwidth : natural := 128;
SAwidth : natural := 16;
DAwidth : natural := 32;
Lwidth : natural := 16
);
port(
-- system signal
clk : in STD_LOGIC;
rst : in STD_LOGIC;
-- Tx interface
header: out std_logic_vector(Bwidth-1 downto 0);
Req : out std_logic;
laddr : out std_logic_vector(SAwidth-1 downto 0);
busy : in std_logic;
tx_sop : in std_logic;
-- CPU bus
CS : in std_logic;
wr : in std_logic;
rd : in std_logic;
addr : in std_logic_vector( 3 downto 0 );
Din : in std_logic_vector( 7 downto 0 );
Dout : out std_logic_vector( 7 downto 0 );
cpuClk : in std_logic;
-- Priority
en : in std_logic
);
end component;
end dma_config;
|
library verilog;
use verilog.vl_types.all;
entity BFM_MAIN is
generic(
OPMODE : integer := 0;
VECTFILE : string := "test.vec";
MAX_INSTRUCTIONS: integer := 16384;
MAX_STACK : integer := 1024;
MAX_MEMTEST : integer := 65536;
TPD : integer := 1;
DEBUGLEVEL : integer := -1;
CON_SPULSE : integer := 0;
ARGVALUE0 : integer := 0;
ARGVALUE1 : integer := 0;
ARGVALUE2 : integer := 0;
ARGVALUE3 : integer := 0;
ARGVALUE4 : integer := 0;
ARGVALUE5 : integer := 0;
ARGVALUE6 : integer := 0;
ARGVALUE7 : integer := 0;
ARGVALUE8 : integer := 0;
ARGVALUE9 : integer := 0;
ARGVALUE10 : integer := 0;
ARGVALUE11 : integer := 0;
ARGVALUE12 : integer := 0;
ARGVALUE13 : integer := 0;
ARGVALUE14 : integer := 0;
ARGVALUE15 : integer := 0;
ARGVALUE16 : integer := 0;
ARGVALUE17 : integer := 0;
ARGVALUE18 : integer := 0;
ARGVALUE19 : integer := 0;
ARGVALUE20 : integer := 0;
ARGVALUE21 : integer := 0;
ARGVALUE22 : integer := 0;
ARGVALUE23 : integer := 0;
ARGVALUE24 : integer := 0;
ARGVALUE25 : integer := 0;
ARGVALUE26 : integer := 0;
ARGVALUE27 : integer := 0;
ARGVALUE28 : integer := 0;
ARGVALUE29 : integer := 0;
ARGVALUE30 : integer := 0;
ARGVALUE31 : integer := 0;
ARGVALUE32 : integer := 0;
ARGVALUE33 : integer := 0;
ARGVALUE34 : integer := 0;
ARGVALUE35 : integer := 0;
ARGVALUE36 : integer := 0;
ARGVALUE37 : integer := 0;
ARGVALUE38 : integer := 0;
ARGVALUE39 : integer := 0;
ARGVALUE40 : integer := 0;
ARGVALUE41 : integer := 0;
ARGVALUE42 : integer := 0;
ARGVALUE43 : integer := 0;
ARGVALUE44 : integer := 0;
ARGVALUE45 : integer := 0;
ARGVALUE46 : integer := 0;
ARGVALUE47 : integer := 0;
ARGVALUE48 : integer := 0;
ARGVALUE49 : integer := 0;
ARGVALUE50 : integer := 0;
ARGVALUE51 : integer := 0;
ARGVALUE52 : integer := 0;
ARGVALUE53 : integer := 0;
ARGVALUE54 : integer := 0;
ARGVALUE55 : integer := 0;
ARGVALUE56 : integer := 0;
ARGVALUE57 : integer := 0;
ARGVALUE58 : integer := 0;
ARGVALUE59 : integer := 0;
ARGVALUE60 : integer := 0;
ARGVALUE61 : integer := 0;
ARGVALUE62 : integer := 0;
ARGVALUE63 : integer := 0;
ARGVALUE64 : integer := 0;
ARGVALUE65 : integer := 0;
ARGVALUE66 : integer := 0;
ARGVALUE67 : integer := 0;
ARGVALUE68 : integer := 0;
ARGVALUE69 : integer := 0;
ARGVALUE70 : integer := 0;
ARGVALUE71 : integer := 0;
ARGVALUE72 : integer := 0;
ARGVALUE73 : integer := 0;
ARGVALUE74 : integer := 0;
ARGVALUE75 : integer := 0;
ARGVALUE76 : integer := 0;
ARGVALUE77 : integer := 0;
ARGVALUE78 : integer := 0;
ARGVALUE79 : integer := 0;
ARGVALUE80 : integer := 0;
ARGVALUE81 : integer := 0;
ARGVALUE82 : integer := 0;
ARGVALUE83 : integer := 0;
ARGVALUE84 : integer := 0;
ARGVALUE85 : integer := 0;
ARGVALUE86 : integer := 0;
ARGVALUE87 : integer := 0;
ARGVALUE88 : integer := 0;
ARGVALUE89 : integer := 0;
ARGVALUE90 : integer := 0;
ARGVALUE91 : integer := 0;
ARGVALUE92 : integer := 0;
ARGVALUE93 : integer := 0;
ARGVALUE94 : integer := 0;
ARGVALUE95 : integer := 0;
ARGVALUE96 : integer := 0;
ARGVALUE97 : integer := 0;
ARGVALUE98 : integer := 0;
ARGVALUE99 : integer := 0;
BFMA1lI1 : vl_logic_vector(31 downto 0) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0);
BFMA1Ol1 : vl_logic_vector(255 downto 0) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0);
BFMA1Il1 : vl_notype;
BFMA1Ol10 : vl_logic_vector(2 downto 0) := (Hi0, Hi0, Hi0);
BFMA1Il10 : vl_logic_vector(2 downto 0) := (Hi0, Hi0, Hi1);
BFMA1ll10 : vl_logic_vector(2 downto 0) := (Hi0, Hi1, Hi0);
BFMA1O010 : vl_logic_vector(2 downto 0) := (Hi0, Hi1, Hi1);
BFMA1I010 : vl_logic_vector(2 downto 0) := (Hi1, Hi0, Hi0);
BFMA1l010 : vl_logic_vector(2 downto 0) := (Hi1, Hi0, Hi1)
);
port(
SYSCLK : in vl_logic;
SYSRSTN : in vl_logic;
PCLK : out vl_logic;
HCLK : out vl_logic;
HRESETN : out vl_logic;
HADDR : out vl_logic_vector(31 downto 0);
HBURST : out vl_logic_vector(2 downto 0);
HMASTLOCK : out vl_logic;
HPROT : out vl_logic_vector(3 downto 0);
HSIZE : out vl_logic_vector(2 downto 0);
HTRANS : out vl_logic_vector(1 downto 0);
HWRITE : out vl_logic;
HWDATA : out vl_logic_vector(31 downto 0);
HRDATA : in vl_logic_vector(31 downto 0);
HREADY : in vl_logic;
HRESP : in vl_logic;
HSEL : out vl_logic_vector(15 downto 0);
INTERRUPT : in vl_logic_vector(255 downto 0);
GP_OUT : out vl_logic_vector(31 downto 0);
GP_IN : in vl_logic_vector(31 downto 0);
EXT_WR : out vl_logic;
EXT_RD : out vl_logic;
EXT_ADDR : out vl_logic_vector(31 downto 0);
EXT_DATA : inout vl_logic_vector(31 downto 0);
EXT_WAIT : in vl_logic;
CON_ADDR : in vl_logic_vector(15 downto 0);
CON_DATA : inout vl_logic_vector(31 downto 0);
CON_RD : in vl_logic;
CON_WR : in vl_logic;
CON_BUSY : out vl_logic;
INSTR_OUT : out vl_logic_vector(31 downto 0);
INSTR_IN : in vl_logic_vector(31 downto 0);
FINISHED : out vl_logic;
FAILED : out vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of OPMODE : constant is 1;
attribute mti_svvh_generic_type of VECTFILE : constant is 1;
attribute mti_svvh_generic_type of MAX_INSTRUCTIONS : constant is 1;
attribute mti_svvh_generic_type of MAX_STACK : constant is 1;
attribute mti_svvh_generic_type of MAX_MEMTEST : constant is 1;
attribute mti_svvh_generic_type of TPD : constant is 1;
attribute mti_svvh_generic_type of DEBUGLEVEL : constant is 1;
attribute mti_svvh_generic_type of CON_SPULSE : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE0 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE1 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE2 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE3 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE4 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE5 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE6 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE7 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE8 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE9 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE10 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE11 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE12 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE13 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE14 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE15 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE16 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE17 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE18 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE19 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE20 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE21 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE22 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE23 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE24 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE25 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE26 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE27 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE28 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE29 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE30 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE31 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE32 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE33 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE34 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE35 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE36 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE37 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE38 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE39 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE40 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE41 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE42 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE43 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE44 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE45 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE46 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE47 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE48 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE49 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE50 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE51 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE52 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE53 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE54 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE55 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE56 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE57 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE58 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE59 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE60 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE61 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE62 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE63 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE64 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE65 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE66 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE67 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE68 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE69 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE70 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE71 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE72 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE73 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE74 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE75 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE76 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE77 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE78 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE79 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE80 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE81 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE82 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE83 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE84 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE85 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE86 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE87 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE88 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE89 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE90 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE91 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE92 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE93 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE94 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE95 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE96 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE97 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE98 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE99 : constant is 1;
attribute mti_svvh_generic_type of BFMA1lI1 : constant is 2;
attribute mti_svvh_generic_type of BFMA1Ol1 : constant is 2;
attribute mti_svvh_generic_type of BFMA1Il1 : constant is 3;
attribute mti_svvh_generic_type of BFMA1Ol10 : constant is 2;
attribute mti_svvh_generic_type of BFMA1Il10 : constant is 2;
attribute mti_svvh_generic_type of BFMA1ll10 : constant is 2;
attribute mti_svvh_generic_type of BFMA1O010 : constant is 2;
attribute mti_svvh_generic_type of BFMA1I010 : constant is 2;
attribute mti_svvh_generic_type of BFMA1l010 : constant is 2;
end BFM_MAIN;
|
library verilog;
use verilog.vl_types.all;
entity BFM_MAIN is
generic(
OPMODE : integer := 0;
VECTFILE : string := "test.vec";
MAX_INSTRUCTIONS: integer := 16384;
MAX_STACK : integer := 1024;
MAX_MEMTEST : integer := 65536;
TPD : integer := 1;
DEBUGLEVEL : integer := -1;
CON_SPULSE : integer := 0;
ARGVALUE0 : integer := 0;
ARGVALUE1 : integer := 0;
ARGVALUE2 : integer := 0;
ARGVALUE3 : integer := 0;
ARGVALUE4 : integer := 0;
ARGVALUE5 : integer := 0;
ARGVALUE6 : integer := 0;
ARGVALUE7 : integer := 0;
ARGVALUE8 : integer := 0;
ARGVALUE9 : integer := 0;
ARGVALUE10 : integer := 0;
ARGVALUE11 : integer := 0;
ARGVALUE12 : integer := 0;
ARGVALUE13 : integer := 0;
ARGVALUE14 : integer := 0;
ARGVALUE15 : integer := 0;
ARGVALUE16 : integer := 0;
ARGVALUE17 : integer := 0;
ARGVALUE18 : integer := 0;
ARGVALUE19 : integer := 0;
ARGVALUE20 : integer := 0;
ARGVALUE21 : integer := 0;
ARGVALUE22 : integer := 0;
ARGVALUE23 : integer := 0;
ARGVALUE24 : integer := 0;
ARGVALUE25 : integer := 0;
ARGVALUE26 : integer := 0;
ARGVALUE27 : integer := 0;
ARGVALUE28 : integer := 0;
ARGVALUE29 : integer := 0;
ARGVALUE30 : integer := 0;
ARGVALUE31 : integer := 0;
ARGVALUE32 : integer := 0;
ARGVALUE33 : integer := 0;
ARGVALUE34 : integer := 0;
ARGVALUE35 : integer := 0;
ARGVALUE36 : integer := 0;
ARGVALUE37 : integer := 0;
ARGVALUE38 : integer := 0;
ARGVALUE39 : integer := 0;
ARGVALUE40 : integer := 0;
ARGVALUE41 : integer := 0;
ARGVALUE42 : integer := 0;
ARGVALUE43 : integer := 0;
ARGVALUE44 : integer := 0;
ARGVALUE45 : integer := 0;
ARGVALUE46 : integer := 0;
ARGVALUE47 : integer := 0;
ARGVALUE48 : integer := 0;
ARGVALUE49 : integer := 0;
ARGVALUE50 : integer := 0;
ARGVALUE51 : integer := 0;
ARGVALUE52 : integer := 0;
ARGVALUE53 : integer := 0;
ARGVALUE54 : integer := 0;
ARGVALUE55 : integer := 0;
ARGVALUE56 : integer := 0;
ARGVALUE57 : integer := 0;
ARGVALUE58 : integer := 0;
ARGVALUE59 : integer := 0;
ARGVALUE60 : integer := 0;
ARGVALUE61 : integer := 0;
ARGVALUE62 : integer := 0;
ARGVALUE63 : integer := 0;
ARGVALUE64 : integer := 0;
ARGVALUE65 : integer := 0;
ARGVALUE66 : integer := 0;
ARGVALUE67 : integer := 0;
ARGVALUE68 : integer := 0;
ARGVALUE69 : integer := 0;
ARGVALUE70 : integer := 0;
ARGVALUE71 : integer := 0;
ARGVALUE72 : integer := 0;
ARGVALUE73 : integer := 0;
ARGVALUE74 : integer := 0;
ARGVALUE75 : integer := 0;
ARGVALUE76 : integer := 0;
ARGVALUE77 : integer := 0;
ARGVALUE78 : integer := 0;
ARGVALUE79 : integer := 0;
ARGVALUE80 : integer := 0;
ARGVALUE81 : integer := 0;
ARGVALUE82 : integer := 0;
ARGVALUE83 : integer := 0;
ARGVALUE84 : integer := 0;
ARGVALUE85 : integer := 0;
ARGVALUE86 : integer := 0;
ARGVALUE87 : integer := 0;
ARGVALUE88 : integer := 0;
ARGVALUE89 : integer := 0;
ARGVALUE90 : integer := 0;
ARGVALUE91 : integer := 0;
ARGVALUE92 : integer := 0;
ARGVALUE93 : integer := 0;
ARGVALUE94 : integer := 0;
ARGVALUE95 : integer := 0;
ARGVALUE96 : integer := 0;
ARGVALUE97 : integer := 0;
ARGVALUE98 : integer := 0;
ARGVALUE99 : integer := 0;
BFMA1lI1 : vl_logic_vector(31 downto 0) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0);
BFMA1Ol1 : vl_logic_vector(255 downto 0) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0);
BFMA1Il1 : vl_notype;
BFMA1Ol10 : vl_logic_vector(2 downto 0) := (Hi0, Hi0, Hi0);
BFMA1Il10 : vl_logic_vector(2 downto 0) := (Hi0, Hi0, Hi1);
BFMA1ll10 : vl_logic_vector(2 downto 0) := (Hi0, Hi1, Hi0);
BFMA1O010 : vl_logic_vector(2 downto 0) := (Hi0, Hi1, Hi1);
BFMA1I010 : vl_logic_vector(2 downto 0) := (Hi1, Hi0, Hi0);
BFMA1l010 : vl_logic_vector(2 downto 0) := (Hi1, Hi0, Hi1)
);
port(
SYSCLK : in vl_logic;
SYSRSTN : in vl_logic;
PCLK : out vl_logic;
HCLK : out vl_logic;
HRESETN : out vl_logic;
HADDR : out vl_logic_vector(31 downto 0);
HBURST : out vl_logic_vector(2 downto 0);
HMASTLOCK : out vl_logic;
HPROT : out vl_logic_vector(3 downto 0);
HSIZE : out vl_logic_vector(2 downto 0);
HTRANS : out vl_logic_vector(1 downto 0);
HWRITE : out vl_logic;
HWDATA : out vl_logic_vector(31 downto 0);
HRDATA : in vl_logic_vector(31 downto 0);
HREADY : in vl_logic;
HRESP : in vl_logic;
HSEL : out vl_logic_vector(15 downto 0);
INTERRUPT : in vl_logic_vector(255 downto 0);
GP_OUT : out vl_logic_vector(31 downto 0);
GP_IN : in vl_logic_vector(31 downto 0);
EXT_WR : out vl_logic;
EXT_RD : out vl_logic;
EXT_ADDR : out vl_logic_vector(31 downto 0);
EXT_DATA : inout vl_logic_vector(31 downto 0);
EXT_WAIT : in vl_logic;
CON_ADDR : in vl_logic_vector(15 downto 0);
CON_DATA : inout vl_logic_vector(31 downto 0);
CON_RD : in vl_logic;
CON_WR : in vl_logic;
CON_BUSY : out vl_logic;
INSTR_OUT : out vl_logic_vector(31 downto 0);
INSTR_IN : in vl_logic_vector(31 downto 0);
FINISHED : out vl_logic;
FAILED : out vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of OPMODE : constant is 1;
attribute mti_svvh_generic_type of VECTFILE : constant is 1;
attribute mti_svvh_generic_type of MAX_INSTRUCTIONS : constant is 1;
attribute mti_svvh_generic_type of MAX_STACK : constant is 1;
attribute mti_svvh_generic_type of MAX_MEMTEST : constant is 1;
attribute mti_svvh_generic_type of TPD : constant is 1;
attribute mti_svvh_generic_type of DEBUGLEVEL : constant is 1;
attribute mti_svvh_generic_type of CON_SPULSE : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE0 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE1 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE2 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE3 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE4 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE5 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE6 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE7 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE8 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE9 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE10 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE11 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE12 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE13 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE14 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE15 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE16 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE17 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE18 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE19 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE20 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE21 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE22 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE23 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE24 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE25 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE26 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE27 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE28 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE29 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE30 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE31 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE32 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE33 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE34 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE35 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE36 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE37 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE38 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE39 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE40 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE41 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE42 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE43 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE44 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE45 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE46 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE47 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE48 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE49 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE50 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE51 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE52 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE53 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE54 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE55 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE56 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE57 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE58 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE59 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE60 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE61 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE62 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE63 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE64 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE65 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE66 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE67 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE68 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE69 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE70 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE71 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE72 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE73 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE74 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE75 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE76 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE77 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE78 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE79 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE80 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE81 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE82 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE83 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE84 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE85 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE86 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE87 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE88 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE89 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE90 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE91 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE92 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE93 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE94 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE95 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE96 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE97 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE98 : constant is 1;
attribute mti_svvh_generic_type of ARGVALUE99 : constant is 1;
attribute mti_svvh_generic_type of BFMA1lI1 : constant is 2;
attribute mti_svvh_generic_type of BFMA1Ol1 : constant is 2;
attribute mti_svvh_generic_type of BFMA1Il1 : constant is 3;
attribute mti_svvh_generic_type of BFMA1Ol10 : constant is 2;
attribute mti_svvh_generic_type of BFMA1Il10 : constant is 2;
attribute mti_svvh_generic_type of BFMA1ll10 : constant is 2;
attribute mti_svvh_generic_type of BFMA1O010 : constant is 2;
attribute mti_svvh_generic_type of BFMA1I010 : constant is 2;
attribute mti_svvh_generic_type of BFMA1l010 : constant is 2;
end BFM_MAIN;
|
entity ENTITY1 is
port (
I_PORT1 : in std_logic;
I_PORT2 : in std_logic;
O_PORT3 : out std_logic;
O_PORT4 : out std_logic
);
end entity;
|
-- The Potato Processor - A simple processor for FPGAs
-- (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net>
-- Report bugs and issues on <https://github.com/skordal/potato/issues>
library ieee;
use ieee.std_logic_1164.all;
use work.pp_types.all;
use work.pp_utilities.all;
--! @brief The Potato Processor.
--! This file provides a Wishbone-compatible interface to the Potato processor.
entity pp_potato is
generic(
PROCESSOR_ID : std_logic_vector(31 downto 0) := x"00000000"; --! Processor ID.
RESET_ADDRESS : std_logic_vector(31 downto 0) := x"00000000"; --! Address of the first instruction to execute.
MTIME_DIVIDER : positive := 5; --! Divider for the clock driving the MTIME counter.
ICACHE_ENABLE : boolean := true; --! Whether to enable the instruction cache.
ICACHE_LINE_SIZE : natural := 4; --! Number of words per instruction cache line.
ICACHE_NUM_LINES : natural := 128 --! Number of cache lines in the instruction cache.
);
port(
clk : in std_logic;
reset : in std_logic;
-- Interrupts:
irq : in std_logic_vector(7 downto 0);
-- Test interface:
test_context_out : out test_context;
-- Wishbone interface:
wb_adr_out : out std_logic_vector(31 downto 0);
wb_sel_out : out std_logic_vector( 3 downto 0);
wb_cyc_out : out std_logic;
wb_stb_out : out std_logic;
wb_we_out : out std_logic;
wb_dat_out : out std_logic_vector(31 downto 0);
wb_dat_in : in std_logic_vector(31 downto 0);
wb_ack_in : in std_logic
);
end entity pp_potato;
architecture behaviour of pp_potato is
-- Instruction memory signals:
signal imem_address : std_logic_vector(31 downto 0);
signal imem_data : std_logic_vector(31 downto 0);
signal imem_req, imem_ack : std_logic;
-- Data memory signals:
signal dmem_address : std_logic_vector(31 downto 0);
signal dmem_data_in : std_logic_vector(31 downto 0);
signal dmem_data_out : std_logic_vector(31 downto 0);
signal dmem_data_size : std_logic_vector( 1 downto 0);
signal dmem_read_req : std_logic;
signal dmem_read_ack : std_logic;
signal dmem_write_req : std_logic;
signal dmem_write_ack : std_logic;
-- Wishbone signals:
signal icache_inputs, dmem_if_inputs : wishbone_master_inputs;
signal icache_outputs, dmem_if_outputs : wishbone_master_outputs;
-- Arbiter signals:
signal m1_inputs, m2_inputs : wishbone_master_inputs;
signal m1_outputs, m2_outputs : wishbone_master_outputs;
begin
processor: entity work.pp_core
generic map(
PROCESSOR_ID => PROCESSOR_ID,
RESET_ADDRESS => RESET_ADDRESS
) port map(
clk => clk,
reset => reset,
imem_address => imem_address,
imem_data_in => imem_data,
imem_req => imem_req,
imem_ack => imem_ack,
dmem_address => dmem_address,
dmem_data_in => dmem_data_in,
dmem_data_out => dmem_data_out,
dmem_data_size => dmem_data_size,
dmem_read_req => dmem_read_req,
dmem_read_ack => dmem_read_ack,
dmem_write_req => dmem_write_req,
dmem_write_ack => dmem_write_ack,
test_context_out => test_context_out,
irq => irq
);
icache_enabled: if ICACHE_ENABLE
generate
icache: entity work.pp_icache
generic map(
LINE_SIZE => ICACHE_LINE_SIZE,
NUM_LINES => ICACHE_NUM_LINES
) port map(
clk => clk,
reset => reset,
mem_address_in => imem_address,
mem_data_out => imem_data,
mem_read_req => imem_req,
mem_read_ack => imem_ack,
wb_inputs => icache_inputs,
wb_outputs => icache_outputs
);
icache_inputs <= m1_inputs;
m1_outputs <= icache_outputs;
dmem_if_inputs <= m2_inputs;
m2_outputs <= dmem_if_outputs;
end generate icache_enabled;
icache_disabled: if not ICACHE_ENABLE
generate
imem_if: entity work.pp_wb_adapter
port map(
clk => clk,
reset => reset,
mem_address => imem_address,
mem_data_in => (others => '0'),
mem_data_out => imem_data,
mem_data_size => (others => '0'),
mem_read_req => imem_req,
mem_read_ack => imem_ack,
mem_write_req => '0',
mem_write_ack => open,
wb_inputs => icache_inputs,
wb_outputs => icache_outputs
);
dmem_if_inputs <= m1_inputs;
m1_outputs <= dmem_if_outputs;
icache_inputs <= m2_inputs;
m2_outputs <= icache_outputs;
end generate icache_disabled;
dmem_if: entity work.pp_wb_adapter
port map(
clk => clk,
reset => reset,
mem_address => dmem_address,
mem_data_in => dmem_data_out,
mem_data_out => dmem_data_in,
mem_data_size => dmem_data_size,
mem_read_req => dmem_read_req,
mem_read_ack => dmem_read_ack,
mem_write_req => dmem_write_req,
mem_write_ack => dmem_write_ack,
wb_inputs => dmem_if_inputs,
wb_outputs => dmem_if_outputs
);
arbiter: entity work.pp_wb_arbiter
port map(
clk => clk,
reset => reset,
m1_inputs => m1_inputs,
m1_outputs => m1_outputs,
m2_inputs => m2_inputs,
m2_outputs => m2_outputs,
wb_adr_out => wb_adr_out,
wb_sel_out => wb_sel_out,
wb_cyc_out => wb_cyc_out,
wb_stb_out => wb_stb_out,
wb_we_out => wb_we_out,
wb_dat_out => wb_dat_out,
wb_dat_in => wb_dat_in,
wb_ack_in => wb_ack_in
);
end architecture behaviour;
|
entity tb_enot is
end tb_enot;
architecture behav of tb_enot is
signal i : bit;
signal x : boolean;
signal o : bit;
begin
dut: entity work.enot
port map (i, x, o);
process
begin
i <= '0';
x <= false;
wait for 1 ns;
assert o = '0' severity failure;
i <= '1';
x <= false;
wait for 1 ns;
assert o = '1' severity failure;
i <= '1';
x <= True;
wait for 1 ns;
assert o = '0' severity failure;
wait;
end process;
end behav;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library work;
use work.genram_pkg.all;
package memory_loader_pkg is
subtype t_meminit_array is t_generic_ram_init;
function f_hexchar_to_slv (c : character) return std_logic_vector;
function f_hexstring_to_slv (s : string; n_digits : integer) return std_logic_vector;
function f_get_token(s : string; n : integer) return string;
function f_load_mem_from_file
(file_name : string;
mem_size : integer;
mem_width : integer;
fail_if_notfound : boolean)
return t_meminit_array;
end memory_loader_pkg;
package body memory_loader_pkg is
function f_hexchar_to_slv (c : character) return std_logic_vector is
variable t : std_logic_vector(3 downto 0);
begin
case c is
when '0' => t := x"0";
when '1' => t := x"1";
when '2' => t := x"2";
when '3' => t := x"3";
when '4' => t := x"4";
when '5' => t := x"5";
when '6' => t := x"6";
when '7' => t := x"7";
when '8' => t := x"8";
when '9' => t := x"9";
when 'a' => t := x"a";
when 'A' => t := x"a";
when 'b' => t := x"b";
when 'B' => t := x"b";
when 'c' => t := x"c";
when 'C' => t := x"c";
when 'd' => t := x"d";
when 'D' => t := x"d";
when 'e' => t := x"e";
when 'E' => t := x"e";
when 'f' => t := x"f";
when 'F' => t := x"f";
when others =>
report "f_hexchar_to_slv(): unrecognized character '" &c&" in hex text string" severity failure;
end case;
return t;
end f_hexchar_to_slv;
function f_hexstring_to_slv (s : string; n_digits : integer) return std_logic_vector is
variable tmp : std_logic_vector(255 downto 0) := (others => '0');
begin
if s'length > tmp'length then
report "f_hexstring_to_slv(): string length exceeds the limit" severity failure;
end if;
for i in 0 to s'length-1 loop
tmp(4 * (s'length - i) - 1 downto 4 * (s'length - 1 - i)) := f_hexchar_to_slv(s(i+1));
end loop; -- i
return tmp(n_digits * 4 - 1 downto 0);
end f_hexstring_to_slv;
function f_get_token(s : string; n : integer) return string is
variable cur_pos : integer;
variable tmp : string (1 to 128);
variable cur_token : integer;
variable tmp_pos : integer;
begin
cur_pos := 1;
cur_token := 1;
tmp_pos := 1;
loop
if(cur_pos >= s'length) then
return "";
end if;
while cur_pos <= s'length and (s(cur_pos) = ' ' or s(cur_pos) = character'val(9) or s(cur_pos) = character'val(0)) loop
cur_pos := cur_pos + 1;
end loop;
if(cur_pos >= s'length) then
return "";
end if;
while(cur_pos <= s'length and s(cur_pos) /= ' ' and s(cur_pos) /= character'val(9) and s(cur_pos) /= character'val(0)) loop
if(cur_token = n) then
tmp(tmp_pos) := s(cur_pos);
tmp_pos := tmp_pos + 1;
end if;
cur_pos := cur_pos + 1;
end loop;
if(cur_token = n) then
return tmp(1 to tmp_pos-1);
end if;
cur_token := cur_token + 1;
if(cur_pos >= s'length) then
return "";
end if;
end loop;
return "";
end f_get_token;
function f_load_mem_from_file
(file_name : string;
mem_size : integer;
mem_width : integer;
fail_if_notfound : boolean)
return t_meminit_array is
file f_in : text;
variable l : line;
variable ls : string(1 to 128);
variable cmd : string(1 to 128);
variable line_len : integer;
variable status : file_open_status;
variable mem : t_meminit_array(0 to mem_size-1, mem_width-1 downto 0);
variable i : integer;
variable c : character;
variable good : boolean;
variable addr : integer;
variable data_tmp : unsigned(mem_width-1 downto 0);
variable data_int : integer;
begin
if(file_name = "" or file_name = "none") then
mem := (others => (others => '0'));
return mem;
end if;
file_open(status, f_in, file_name, read_mode);
if(status /= open_ok) then
if(fail_if_notfound) then
report "f_load_mem_from_file(): can't open file '"&file_name&"'" severity failure;
else
report "f_load_mem_from_file(): can't open file '"&file_name&"'" severity warning;
end if;
end if;
while true loop
i := 0;
while (i < 4096) loop
-- stupid ISE restricts the loop length
readline(f_in, l);
line_len := 0;
loop
read(l, ls(line_len+1), good);
exit when good = false;
line_len := line_len + 1;
end loop;
if(line_len /= 0 and f_get_token(ls, 1) = "write") then
addr := to_integer(unsigned(f_hexstring_to_slv(f_get_token(ls, 2), 8)));
data_tmp := resize(unsigned(f_hexstring_to_slv(f_get_token(ls, 3), 8)), mem_width);
data_int := to_integer(data_tmp);
-- report "addr: " & integer'image(addr) & " data: " & integer'image(data_int);
for i in 0 to mem_width-1 loop
mem(addr, i) := std_logic(data_tmp(i));
end loop; -- i in 0 to mem_width-1
-- report "addr: " & integer'image(addr) & " data: " & integer'image(data_int);
end if;
if endfile(f_in) then
file_close(f_in);
return mem;
end if;
i := i+1;
end loop;
end loop;
return mem;
end f_load_mem_from_file;
end memory_loader_pkg;
|
architecture RTL of FIFO is
begin
process
begin
if (a = '1') then
b <= '0';
end if;
-- Violations below
if (a = '1') then
b <= '0';
end if;
if (a = '1') then
b <= '0';
end if;
end process;
end architecture RTL;
|
architecture RTL of FIFO is
begin
process
begin
if (a = '1') then
b <= '0';
end if;
-- Violations below
if (a = '1') then
b <= '0';
end if;
if (a = '1') then
b <= '0';
end if;
end process;
end architecture RTL;
|
-- megafunction wizard: %Altera PLL v14.0%
-- GENERATION: XML
-- adc_pll.vhd
-- Generated using ACDS version 14.0 200 at 2015.06.18.16:00:31
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity adc_pll is
port (
refclk : in std_logic := '0'; -- refclk.clk
rst : in std_logic := '0'; -- reset.reset
outclk_0 : out std_logic; -- outclk0.clk
outclk_1 : out std_logic -- outclk1.clk
);
end entity adc_pll;
architecture rtl of adc_pll is
component adc_pll_0002 is
port (
refclk : in std_logic := 'X'; -- clk
rst : in std_logic := 'X'; -- reset
outclk_0 : out std_logic; -- clk
outclk_1 : out std_logic; -- clk
locked : out std_logic -- export
);
end component adc_pll_0002;
begin
adc_pll_inst : component adc_pll_0002
port map (
refclk => refclk, -- refclk.clk
rst => rst, -- reset.reset
outclk_0 => outclk_0, -- outclk0.clk
outclk_1 => outclk_1, -- outclk1.clk
locked => open -- (terminated)
);
end architecture rtl; -- of adc_pll
-- Retrieval info: <?xml version="1.0"?>
--<!--
-- Generated by Altera MegaWizard Launcher Utility version 1.0
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- ************************************************************
-- Copyright (C) 1991-2015 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
---->
-- Retrieval info: <instance entity-name="altera_pll" version="14.0" >
-- Retrieval info: <generic name="debug_print_output" value="false" />
-- Retrieval info: <generic name="debug_use_rbc_taf_method" value="false" />
-- Retrieval info: <generic name="device_family" value="Cyclone V" />
-- Retrieval info: <generic name="device" value="Unknown" />
-- Retrieval info: <generic name="gui_device_speed_grade" value="8" />
-- Retrieval info: <generic name="gui_pll_mode" value="Integer-N PLL" />
-- Retrieval info: <generic name="gui_reference_clock_frequency" value="240.0" />
-- Retrieval info: <generic name="gui_channel_spacing" value="0.0" />
-- Retrieval info: <generic name="gui_operation_mode" value="normal" />
-- Retrieval info: <generic name="gui_feedback_clock" value="Global Clock" />
-- Retrieval info: <generic name="gui_fractional_cout" value="32" />
-- Retrieval info: <generic name="gui_dsm_out_sel" value="1st_order" />
-- Retrieval info: <generic name="gui_use_locked" value="false" />
-- Retrieval info: <generic name="gui_en_adv_params" value="false" />
-- Retrieval info: <generic name="gui_number_of_clocks" value="2" />
-- Retrieval info: <generic name="gui_multiply_factor" value="1" />
-- Retrieval info: <generic name="gui_frac_multiply_factor" value="1" />
-- Retrieval info: <generic name="gui_divide_factor_n" value="1" />
-- Retrieval info: <generic name="gui_cascade_counter0" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency0" value="60.0" />
-- Retrieval info: <generic name="gui_divide_factor_c0" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units0" value="degrees" />
-- Retrieval info: <generic name="gui_phase_shift0" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg0" value="50.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift0" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle0" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter1" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency1" value="60.0" />
-- Retrieval info: <generic name="gui_divide_factor_c1" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units1" value="degrees" />
-- Retrieval info: <generic name="gui_phase_shift1" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg1" value="50.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift1" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle1" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter2" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency2" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c2" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units2" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift2" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg2" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift2" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle2" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter3" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency3" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c3" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency3" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units3" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift3" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg3" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift3" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle3" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter4" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency4" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c4" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency4" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units4" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift4" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg4" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift4" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle4" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter5" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency5" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c5" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency5" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units5" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift5" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg5" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift5" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle5" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter6" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency6" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c6" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency6" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units6" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift6" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg6" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift6" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle6" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter7" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency7" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c7" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency7" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units7" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift7" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg7" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift7" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle7" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter8" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency8" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c8" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency8" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units8" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift8" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg8" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift8" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle8" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter9" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency9" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c9" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency9" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units9" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift9" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg9" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift9" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle9" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter10" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency10" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c10" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency10" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units10" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift10" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg10" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift10" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle10" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter11" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency11" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c11" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency11" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units11" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift11" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg11" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift11" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle11" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter12" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency12" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c12" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency12" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units12" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift12" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg12" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift12" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle12" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter13" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency13" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c13" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency13" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units13" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift13" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg13" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift13" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle13" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter14" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency14" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c14" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency14" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units14" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift14" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg14" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift14" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle14" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter15" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency15" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c15" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency15" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units15" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift15" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg15" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift15" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle15" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter16" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency16" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c16" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency16" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units16" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift16" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg16" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift16" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle16" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter17" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency17" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c17" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency17" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units17" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift17" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg17" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift17" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle17" value="50" />
-- Retrieval info: <generic name="gui_pll_auto_reset" value="Off" />
-- Retrieval info: <generic name="gui_pll_bandwidth_preset" value="Auto" />
-- Retrieval info: <generic name="gui_en_reconf" value="false" />
-- Retrieval info: <generic name="gui_en_dps_ports" value="false" />
-- Retrieval info: <generic name="gui_en_phout_ports" value="false" />
-- Retrieval info: <generic name="gui_phout_division" value="1" />
-- Retrieval info: <generic name="gui_en_lvds_ports" value="false" />
-- Retrieval info: <generic name="gui_mif_generate" value="false" />
-- Retrieval info: <generic name="gui_enable_mif_dps" value="false" />
-- Retrieval info: <generic name="gui_dps_cntr" value="C0" />
-- Retrieval info: <generic name="gui_dps_num" value="1" />
-- Retrieval info: <generic name="gui_dps_dir" value="Positive" />
-- Retrieval info: <generic name="gui_refclk_switch" value="false" />
-- Retrieval info: <generic name="gui_refclk1_frequency" value="100.0" />
-- Retrieval info: <generic name="gui_switchover_mode" value="Automatic Switchover" />
-- Retrieval info: <generic name="gui_switchover_delay" value="0" />
-- Retrieval info: <generic name="gui_active_clk" value="false" />
-- Retrieval info: <generic name="gui_clk_bad" value="false" />
-- Retrieval info: <generic name="gui_enable_cascade_out" value="false" />
-- Retrieval info: <generic name="gui_cascade_outclk_index" value="0" />
-- Retrieval info: <generic name="gui_enable_cascade_in" value="false" />
-- Retrieval info: <generic name="gui_pll_cascading_mode" value="Create an adjpllin signal to connect with an upstream PLL" />
-- Retrieval info: <generic name="AUTO_REFCLK_CLOCK_RATE" value="-1" />
-- Retrieval info: </instance>
-- IPFS_FILES : adc_pll.vho
-- RELATED_FILES: adc_pll.vhd, adc_pll_0002.v
|
architecture RTL of FIFO is
signal sig1, sig3, sig4 : std_logic;
signal sig2 : std_logic;
-- Violations below
signal sig1 : std_logic;
signal sig2, sig3, sig4 : std_logic;
begin
end architecture RTL;
|
library verilog;
use verilog.vl_types.all;
entity altera_avalon_dc_fifo is
generic(
SYMBOLS_PER_BEAT: integer := 1;
BITS_PER_SYMBOL : integer := 8;
FIFO_DEPTH : integer := 16;
CHANNEL_WIDTH : integer := 0;
ERROR_WIDTH : integer := 0;
USE_PACKETS : integer := 0;
USE_IN_FILL_LEVEL: integer := 0;
USE_OUT_FILL_LEVEL: integer := 0;
WR_SYNC_DEPTH : integer := 2;
RD_SYNC_DEPTH : integer := 2;
STREAM_ALMOST_FULL: integer := 0;
STREAM_ALMOST_EMPTY: integer := 0;
BACKPRESSURE_DURING_RESET: integer := 0;
LOOKAHEAD_POINTERS: integer := 0;
PIPELINE_POINTERS: integer := 0;
USE_SPACE_AVAIL_IF: integer := 0
);
port(
in_clk : in vl_logic;
in_reset_n : in vl_logic;
out_clk : in vl_logic;
out_reset_n : in vl_logic;
in_data : in vl_logic_vector;
in_valid : in vl_logic;
in_ready : out vl_logic;
in_startofpacket: in vl_logic;
in_endofpacket : in vl_logic;
in_empty : in vl_logic_vector;
in_error : in vl_logic_vector;
in_channel : in vl_logic_vector;
out_data : out vl_logic_vector;
out_valid : out vl_logic;
out_ready : in vl_logic;
out_startofpacket: out vl_logic;
out_endofpacket : out vl_logic;
out_empty : out vl_logic_vector;
out_error : out vl_logic_vector;
out_channel : out vl_logic_vector;
in_csr_address : in vl_logic;
in_csr_write : in vl_logic;
in_csr_read : in vl_logic;
in_csr_readdata : out vl_logic_vector(31 downto 0);
in_csr_writedata: in vl_logic_vector(31 downto 0);
out_csr_address : in vl_logic;
out_csr_write : in vl_logic;
out_csr_read : in vl_logic;
out_csr_readdata: out vl_logic_vector(31 downto 0);
out_csr_writedata: in vl_logic_vector(31 downto 0);
almost_full_valid: out vl_logic;
almost_full_data: out vl_logic;
almost_empty_valid: out vl_logic;
almost_empty_data: out vl_logic;
space_avail_data: out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of SYMBOLS_PER_BEAT : constant is 1;
attribute mti_svvh_generic_type of BITS_PER_SYMBOL : constant is 1;
attribute mti_svvh_generic_type of FIFO_DEPTH : constant is 1;
attribute mti_svvh_generic_type of CHANNEL_WIDTH : constant is 1;
attribute mti_svvh_generic_type of ERROR_WIDTH : constant is 1;
attribute mti_svvh_generic_type of USE_PACKETS : constant is 1;
attribute mti_svvh_generic_type of USE_IN_FILL_LEVEL : constant is 1;
attribute mti_svvh_generic_type of USE_OUT_FILL_LEVEL : constant is 1;
attribute mti_svvh_generic_type of WR_SYNC_DEPTH : constant is 1;
attribute mti_svvh_generic_type of RD_SYNC_DEPTH : constant is 1;
attribute mti_svvh_generic_type of STREAM_ALMOST_FULL : constant is 1;
attribute mti_svvh_generic_type of STREAM_ALMOST_EMPTY : constant is 1;
attribute mti_svvh_generic_type of BACKPRESSURE_DURING_RESET : constant is 1;
attribute mti_svvh_generic_type of LOOKAHEAD_POINTERS : constant is 1;
attribute mti_svvh_generic_type of PIPELINE_POINTERS : constant is 1;
attribute mti_svvh_generic_type of USE_SPACE_AVAIL_IF : constant is 1;
end altera_avalon_dc_fifo;
|
library verilog;
use verilog.vl_types.all;
entity altera_avalon_dc_fifo is
generic(
SYMBOLS_PER_BEAT: integer := 1;
BITS_PER_SYMBOL : integer := 8;
FIFO_DEPTH : integer := 16;
CHANNEL_WIDTH : integer := 0;
ERROR_WIDTH : integer := 0;
USE_PACKETS : integer := 0;
USE_IN_FILL_LEVEL: integer := 0;
USE_OUT_FILL_LEVEL: integer := 0;
WR_SYNC_DEPTH : integer := 2;
RD_SYNC_DEPTH : integer := 2;
STREAM_ALMOST_FULL: integer := 0;
STREAM_ALMOST_EMPTY: integer := 0;
BACKPRESSURE_DURING_RESET: integer := 0;
LOOKAHEAD_POINTERS: integer := 0;
PIPELINE_POINTERS: integer := 0;
USE_SPACE_AVAIL_IF: integer := 0
);
port(
in_clk : in vl_logic;
in_reset_n : in vl_logic;
out_clk : in vl_logic;
out_reset_n : in vl_logic;
in_data : in vl_logic_vector;
in_valid : in vl_logic;
in_ready : out vl_logic;
in_startofpacket: in vl_logic;
in_endofpacket : in vl_logic;
in_empty : in vl_logic_vector;
in_error : in vl_logic_vector;
in_channel : in vl_logic_vector;
out_data : out vl_logic_vector;
out_valid : out vl_logic;
out_ready : in vl_logic;
out_startofpacket: out vl_logic;
out_endofpacket : out vl_logic;
out_empty : out vl_logic_vector;
out_error : out vl_logic_vector;
out_channel : out vl_logic_vector;
in_csr_address : in vl_logic;
in_csr_write : in vl_logic;
in_csr_read : in vl_logic;
in_csr_readdata : out vl_logic_vector(31 downto 0);
in_csr_writedata: in vl_logic_vector(31 downto 0);
out_csr_address : in vl_logic;
out_csr_write : in vl_logic;
out_csr_read : in vl_logic;
out_csr_readdata: out vl_logic_vector(31 downto 0);
out_csr_writedata: in vl_logic_vector(31 downto 0);
almost_full_valid: out vl_logic;
almost_full_data: out vl_logic;
almost_empty_valid: out vl_logic;
almost_empty_data: out vl_logic;
space_avail_data: out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of SYMBOLS_PER_BEAT : constant is 1;
attribute mti_svvh_generic_type of BITS_PER_SYMBOL : constant is 1;
attribute mti_svvh_generic_type of FIFO_DEPTH : constant is 1;
attribute mti_svvh_generic_type of CHANNEL_WIDTH : constant is 1;
attribute mti_svvh_generic_type of ERROR_WIDTH : constant is 1;
attribute mti_svvh_generic_type of USE_PACKETS : constant is 1;
attribute mti_svvh_generic_type of USE_IN_FILL_LEVEL : constant is 1;
attribute mti_svvh_generic_type of USE_OUT_FILL_LEVEL : constant is 1;
attribute mti_svvh_generic_type of WR_SYNC_DEPTH : constant is 1;
attribute mti_svvh_generic_type of RD_SYNC_DEPTH : constant is 1;
attribute mti_svvh_generic_type of STREAM_ALMOST_FULL : constant is 1;
attribute mti_svvh_generic_type of STREAM_ALMOST_EMPTY : constant is 1;
attribute mti_svvh_generic_type of BACKPRESSURE_DURING_RESET : constant is 1;
attribute mti_svvh_generic_type of LOOKAHEAD_POINTERS : constant is 1;
attribute mti_svvh_generic_type of PIPELINE_POINTERS : constant is 1;
attribute mti_svvh_generic_type of USE_SPACE_AVAIL_IF : constant is 1;
end altera_avalon_dc_fifo;
|
----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: process_node - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.math_real.all;
use work.lloyds_algorithm_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity process_node is
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
u_in : in node_data_type;
centre_positions_in : in data_type;
rdy : out std_logic;
final_index_out : out centre_index_type;
sum_sq_out : out coord_type_ext;
u_out : out node_data_type
);
end process_node;
architecture Behavioral of process_node is
component closest_to_point_top
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
u_in : in node_data_type;
point : in data_type;
point_list_d : in data_type; -- assume FIFO interface !!!
min_point : out data_type;
min_index : out centre_index_type;
min_distance : out coord_type_ext;
u_out : out node_data_type;
rdy : out std_logic
);
end component;
-- closest centre
signal closest_centre : data_type;
signal closest_index : centre_index_type;
signal closest_distance : coord_type_ext;
signal u_out_delayed : node_data_type;
signal closest_rdy : std_logic;
-- write back
signal tmp_final_index : centre_index_type;
begin
closest_to_point_inst : closest_to_point_top
port map (
clk => clk,
sclr => sclr,
nd => nd,
u_in => u_in,
point => u_in.position,
point_list_d => centre_positions_in,
min_point => closest_centre,
min_index => closest_index,
min_distance => closest_distance,
u_out => u_out_delayed,
rdy => closest_rdy
);
rdy <= closest_rdy;
final_index_out <= closest_index;
sum_sq_out <= closest_distance;
u_out <= u_out_delayed;
end Behavioral;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-------------------------------------------------------------------------------
-- This file is part of the Queens@TUD solver suite
-- for enumerating and counting the solutions of an N-Queens Puzzle.
--
-- Copyright (C) 2008-2015
-- Thomas B. Preusser <thomas.preusser@utexas.edu>
-------------------------------------------------------------------------------
-- This design is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Affero General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Affero General Public License for more details.
--
-- You should have received a copy of the GNU Affero General Public License
-- along with this design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity unframe is
generic (
SENTINEL : std_logic_vector(7 downto 0); -- Start Byte
PAY_LEN : positive
);
port (
clk : in std_logic;
rst : in std_logic;
rx_dat : in std_logic_vector(7 downto 0);
rx_vld : in std_logic;
rx_got : out std_logic;
odat : out std_logic_vector(7 downto 0);
oeof : out std_logic;
oful : in std_logic;
oput : out std_logic;
ocommit : out std_logic;
orollback : out std_logic
);
end unframe;
library IEEE;
use IEEE.numeric_std.all;
library PoC;
use PoC.utils.all;
architecture rtl of unframe is
-- CRC Table for 0x1D5 (CRC-8)
type tFCS is array(0 to 255) of std_logic_vector(7 downto 0);
constant FCS : tFCS := (
x"00", x"D5", x"7F", x"AA", x"FE", x"2B", x"81", x"54",
x"29", x"FC", x"56", x"83", x"D7", x"02", x"A8", x"7D",
x"52", x"87", x"2D", x"F8", x"AC", x"79", x"D3", x"06",
x"7B", x"AE", x"04", x"D1", x"85", x"50", x"FA", x"2F",
x"A4", x"71", x"DB", x"0E", x"5A", x"8F", x"25", x"F0",
x"8D", x"58", x"F2", x"27", x"73", x"A6", x"0C", x"D9",
x"F6", x"23", x"89", x"5C", x"08", x"DD", x"77", x"A2",
x"DF", x"0A", x"A0", x"75", x"21", x"F4", x"5E", x"8B",
x"9D", x"48", x"E2", x"37", x"63", x"B6", x"1C", x"C9",
x"B4", x"61", x"CB", x"1E", x"4A", x"9F", x"35", x"E0",
x"CF", x"1A", x"B0", x"65", x"31", x"E4", x"4E", x"9B",
x"E6", x"33", x"99", x"4C", x"18", x"CD", x"67", x"B2",
x"39", x"EC", x"46", x"93", x"C7", x"12", x"B8", x"6D",
x"10", x"C5", x"6F", x"BA", x"EE", x"3B", x"91", x"44",
x"6B", x"BE", x"14", x"C1", x"95", x"40", x"EA", x"3F",
x"42", x"97", x"3D", x"E8", x"BC", x"69", x"C3", x"16",
x"EF", x"3A", x"90", x"45", x"11", x"C4", x"6E", x"BB",
x"C6", x"13", x"B9", x"6C", x"38", x"ED", x"47", x"92",
x"BD", x"68", x"C2", x"17", x"43", x"96", x"3C", x"E9",
x"94", x"41", x"EB", x"3E", x"6A", x"BF", x"15", x"C0",
x"4B", x"9E", x"34", x"E1", x"B5", x"60", x"CA", x"1F",
x"62", x"B7", x"1D", x"C8", x"9C", x"49", x"E3", x"36",
x"19", x"CC", x"66", x"B3", x"E7", x"32", x"98", x"4D",
x"30", x"E5", x"4F", x"9A", x"CE", x"1B", x"B1", x"64",
x"72", x"A7", x"0D", x"D8", x"8C", x"59", x"F3", x"26",
x"5B", x"8E", x"24", x"F1", x"A5", x"70", x"DA", x"0F",
x"20", x"F5", x"5F", x"8A", x"DE", x"0B", x"A1", x"74",
x"09", x"DC", x"76", x"A3", x"F7", x"22", x"88", x"5D",
x"D6", x"03", x"A9", x"7C", x"28", x"FD", x"57", x"82",
x"FF", x"2A", x"80", x"55", x"01", x"D4", x"7E", x"AB",
x"84", x"51", x"FB", x"2E", x"7A", x"AF", x"05", x"D0",
x"AD", x"78", x"D2", x"07", x"53", x"86", x"2C", x"F9"
);
-- State Machine
type tState is (Idle, Load, CheckCRC);
signal State : tState := Idle;
signal NextState : tState;
signal CRC : std_logic_vector(7 downto 0) := (others => '-');
signal Start : std_logic;
signal Append : std_logic;
signal Last : std_logic;
signal CRC_next : std_logic_vector(7 downto 0);
begin
-- State
CRC_next <= FCS(to_integer(unsigned(CRC xor rx_dat)));
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
State <= Idle;
CRC <= (others => '-');
else
State <= NextState;
if Start = '1' then
CRC <= FCS(255);
elsif Append = '1' then
CRC <= CRC_next;
end if;
end if;
end if;
end process;
process(State, rx_vld, rx_dat, oful, Last, CRC)
begin
NextState <= State;
Start <= '0';
Append <= '0';
odat <= (others => '-');
oeof <= Last;
oput <= '0';
ocommit <= '0';
orollback <= '0';
rx_got <= '0';
if rx_vld = '1' then
case State is
when Idle =>
rx_got <= '1';
if rx_dat = SENTINEL then
Start <= '1';
NextState <= Load;
end if;
when Load =>
if oful = '0' then
odat <= rx_dat;
oput <= '1';
rx_got <= '1';
Append <= '1';
if Last = '1' then
NextState <= CheckCRC;
end if;
end if;
when CheckCRC =>
if rx_dat = CRC then
ocommit <= '1';
else
orollback <= '1';
end if;
NextState <= Idle;
end case;
end if;
end process;
-- Payload Counter
genPayEq1: if PAY_LEN = 1 generate
Last <= '1';
end generate genPayEq1;
genPayGt1: if PAY_LEN > 1 generate
signal Cnt : unsigned(log2ceil(PAY_LEN-1) downto 0) := (others => '-');
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
Cnt <= (others => '-');
else
if Start = '1' then
Cnt <= to_unsigned(PAY_LEN-2, Cnt'length);
elsif Append = '1' then
Cnt <= Cnt - 1;
end if;
end if;
end if;
end process;
Last <= Cnt(Cnt'left);
end generate genPayGt1;
end rtl;
|
library verilog;
use verilog.vl_types.all;
entity FourBitMultiplier_vlg_vec_tst is
end FourBitMultiplier_vlg_vec_tst;
|
--------------------------------------------------------------------------------
-- Author: Parham Alvani (parham.alvani@gmail.com)
--
-- Create Date: 04-03-2016
-- Module Name: p4-5.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity counter is
generic (N : natural := 4);
port (clk : in std_logic;
d : out std_logic_vector(N - 1 downto 0));
end entity counter;
architecture structural of counter is
component t_flipflop is
port( t, clk : in std_logic;
q, q_bar : out std_logic);
end component;
signal C : std_logic_vector(N - 1 downto 0);
signal B : std_logic_vector(N - 1 downto 0) := (others => '0');
for all:t_flipflop use entity work.t_flipflop;
begin
C(0) <= '1';
c0: t_flipflop port map ('1', clk, B(0), open);
cs: for I in 1 to N - 1 generate
C(I) <= C(I - 1) and B(I - 1);
cI: t_flipflop port map (C(I), clk, B(I), open);
end generate;
Bs: for I in 0 to N - 1 generate
d(I) <= B(I);
end generate;
end architecture structural;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01:53:54 06/02/2011
-- Design Name:
-- Module Name: sha256_ch - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity sha256_ch is
Port ( x : in STD_LOGIC_VECTOR (31 downto 0);
y : in STD_LOGIC_VECTOR (31 downto 0);
z : in STD_LOGIC_VECTOR (31 downto 0);
q : out STD_LOGIC_VECTOR (31 downto 0));
end sha256_ch;
architecture Behavioral of sha256_ch is
begin
q <= z xor (x and (y xor z));
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01:53:54 06/02/2011
-- Design Name:
-- Module Name: sha256_ch - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity sha256_ch is
Port ( x : in STD_LOGIC_VECTOR (31 downto 0);
y : in STD_LOGIC_VECTOR (31 downto 0);
z : in STD_LOGIC_VECTOR (31 downto 0);
q : out STD_LOGIC_VECTOR (31 downto 0));
end sha256_ch;
architecture Behavioral of sha256_ch is
begin
q <= z xor (x and (y xor z));
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01:53:54 06/02/2011
-- Design Name:
-- Module Name: sha256_ch - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity sha256_ch is
Port ( x : in STD_LOGIC_VECTOR (31 downto 0);
y : in STD_LOGIC_VECTOR (31 downto 0);
z : in STD_LOGIC_VECTOR (31 downto 0);
q : out STD_LOGIC_VECTOR (31 downto 0));
end sha256_ch;
architecture Behavioral of sha256_ch is
begin
q <= z xor (x and (y xor z));
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01:53:54 06/02/2011
-- Design Name:
-- Module Name: sha256_ch - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity sha256_ch is
Port ( x : in STD_LOGIC_VECTOR (31 downto 0);
y : in STD_LOGIC_VECTOR (31 downto 0);
z : in STD_LOGIC_VECTOR (31 downto 0);
q : out STD_LOGIC_VECTOR (31 downto 0));
end sha256_ch;
architecture Behavioral of sha256_ch is
begin
q <= z xor (x and (y xor z));
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fetch2decode_reg is
port(
clk, rst : in std_logic;
noop : in std_logic;
data_in : in std_logic_vector(15 downto 0);
data_out : out std_logic_vector(15 downto 0));
end fetch2decode_reg;
architecture mixed of fetch2decode_reg is
begin
process(clk, rst)
begin
if (rst = '1') then
data_out <= X"0000";
elsif rising_edge(clk) then
if (noop = '1') then
data_out <= X"0000";
else
data_out <= data_in;
end if;
end if;
end process;
end mixed;
|
-- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the
-- Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-- ----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.dspalu_pac.all;
-------------------------------------------------------------------------------
entity bench_dspalu is
end bench_dspalu;
--=----------------------------------------------------------------------------
architecture archi_bench_dspalu of bench_dspalu is
-----------------------------------------------------------------------------
-- @constants definition
-----------------------------------------------------------------------------
constant sig_width : integer := 16;
constant acc_width : integer := 40;
--=--------------------------------------------------------------------------
--
-- @component declarations
--
-----------------------------------------------------------------------------
component clock_gen
generic (
tpw : time;
tps : time
);
port (
clk : out std_logic;
reset : out std_logic
);
end component;
component dspalu_acc
generic (
sig_width : integer ;
acc_width : integer
);
port (
a1 : in std_logic_vector((sig_width - 1) downto 0);
b1 : in std_logic_vector((sig_width - 1) downto 0);
a2 : in std_logic_vector((sig_width - 1) downto 0);
b2 : in std_logic_vector((sig_width - 1) downto 0);
clk : in std_logic;
clr_acc : in std_logic;
acc_mode1 : in std_logic_vector((acc_mode_width - 1) downto 0);
acc_mode2 : in std_logic_vector((acc_mode_width - 1) downto 0);
alu_select : in std_logic_vector((alu_select_width - 1) downto 0);
cmp_mode : in std_logic_vector((cmp_mode_width - 1) downto 0);
cmp_pol : in std_logic;
cmp_store : in std_logic;
chain_acc : in std_logic;
result1 : out std_logic_vector((sig_width - 1) downto 0);
result_acc1 : out std_logic_vector((acc_width - 1) downto 0);
result2 : out std_logic_vector((sig_width - 1) downto 0);
result_acc2 : out std_logic_vector((acc_width - 1) downto 0);
result_sum : out std_logic_vector((2*sig_width - 1) downto 0);
cmp_reg : out std_logic_vector((acc_width - 1) downto 0);
cmp_greater : out std_logic;
cmp_out : out std_logic
);
end component;
--=--------------------------------------------------------------------------
-- @signals definition
-----------------------------------------------------------------------------
signal s_reset : std_logic;
signal s_a1 : std_logic_vector((sig_width - 1) downto 0);
signal s_b1 : std_logic_vector((sig_width - 1) downto 0);
signal s_a2 : std_logic_vector((sig_width - 1) downto 0);
signal s_b2 : std_logic_vector((sig_width - 1) downto 0);
signal s_clk : std_logic;
signal s_clr_acc : std_logic;
signal s_acc_mode1 : std_logic_vector((acc_mode_width - 1) downto 0); -- t_acc_mode;
signal s_acc_mode2 : std_logic_vector((acc_mode_width - 1) downto 0); -- t_acc_mode;
signal s_alu_select : std_logic_vector((alu_select_width - 1) downto 0); -- t_alu_select;
signal s_result1 : std_logic_vector((sig_width - 1) downto 0);
signal s_result_acc1 : std_logic_vector((acc_width - 1) downto 0);
signal s_result2 : std_logic_vector((sig_width - 1) downto 0);
signal s_result_acc2 : std_logic_vector((acc_width - 1) downto 0);
signal s_cmp_mode : std_logic_vector((cmp_mode_width - 1) downto 0);
signal s_cmp_pol : std_logic;
signal s_cmp_store : std_logic;
signal s_chain_acc : std_logic;
signal s_cmp_reg : std_logic_vector((acc_width - 1) downto 0);
signal s_cmp_greater : std_logic;
signal s_cmp_out : std_logic;
signal s_result_sum : std_logic_vector((2*sig_width - 1) downto 0);
begin -- archs_bench_dspalu
-----------------------------------------------------------------------------
--
-- @instantiations
--
-----------------------------------------------------------------------------
clock_gen_1 : clock_gen
generic map (
tpw => 5 ns,
tps => 0 ns)
port map (
clk => s_clk,
reset => s_reset);
dspalu_acc_1 : dspalu_acc
generic map (
sig_width => sig_width,
acc_width => acc_width)
port map (
a1 => s_a1,
b1 => s_b1,
a2 => s_a2,
b2 => s_b2,
clk => s_clk,
clr_acc => s_clr_acc,
acc_mode1 => s_acc_mode1,
acc_mode2 => s_acc_mode2,
alu_select => s_alu_select,
cmp_mode => s_cmp_mode,
cmp_pol => s_cmp_pol,
cmp_store => s_cmp_store,
chain_acc => s_chain_acc,
result1 => s_result1,
result_acc1 => s_result_acc1,
result2 => s_result2,
result_acc2 => s_result_acc2,
result_sum => s_result_sum,
cmp_reg => s_cmp_reg,
cmp_greater => s_cmp_greater,
cmp_out => s_cmp_out);
--=---------------------------------------------------------------------------
--=---------------------------------------------------------------------------
--
-- @concurrent signal assignments
--
-----------------------------------------------------------------------------
s_a1 <= "0010000100000000", "0000000000000010" after 501 ns;
s_b1 <= "1111111111111011", "0000000000000011" after 501 ns;
s_a2 <= "0000000000000100";
s_b2 <= "1111111111111110";
s_clr_acc <= not s_reset;
s_acc_mode1 <= acc_add, acc_store after 201 ns, acc_sub after 301 ns, acc_sumstore after 401 ns,
acc_store after 501 ns, acc_sub after 701 ns, acc_add after 901 ns;
s_acc_mode2 <= acc_add, acc_store after 501 ns, acc_sub after 701 ns, acc_add after 901 ns;
s_alu_select <= alu_mul, alu_cmul after 501 ns;
end archi_bench_dspalu;
--------------------------------------------------------------------------------
-- Simulation parameters
-->SIMSTOPTIME=1000ns
-->SIMSAVFILE=dspalu.sav
-------------------------------------------------------------------------------
|
-- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the
-- Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-- ----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.dspalu_pac.all;
-------------------------------------------------------------------------------
entity bench_dspalu is
end bench_dspalu;
--=----------------------------------------------------------------------------
architecture archi_bench_dspalu of bench_dspalu is
-----------------------------------------------------------------------------
-- @constants definition
-----------------------------------------------------------------------------
constant sig_width : integer := 16;
constant acc_width : integer := 40;
--=--------------------------------------------------------------------------
--
-- @component declarations
--
-----------------------------------------------------------------------------
component clock_gen
generic (
tpw : time;
tps : time
);
port (
clk : out std_logic;
reset : out std_logic
);
end component;
component dspalu_acc
generic (
sig_width : integer ;
acc_width : integer
);
port (
a1 : in std_logic_vector((sig_width - 1) downto 0);
b1 : in std_logic_vector((sig_width - 1) downto 0);
a2 : in std_logic_vector((sig_width - 1) downto 0);
b2 : in std_logic_vector((sig_width - 1) downto 0);
clk : in std_logic;
clr_acc : in std_logic;
acc_mode1 : in std_logic_vector((acc_mode_width - 1) downto 0);
acc_mode2 : in std_logic_vector((acc_mode_width - 1) downto 0);
alu_select : in std_logic_vector((alu_select_width - 1) downto 0);
cmp_mode : in std_logic_vector((cmp_mode_width - 1) downto 0);
cmp_pol : in std_logic;
cmp_store : in std_logic;
chain_acc : in std_logic;
result1 : out std_logic_vector((sig_width - 1) downto 0);
result_acc1 : out std_logic_vector((acc_width - 1) downto 0);
result2 : out std_logic_vector((sig_width - 1) downto 0);
result_acc2 : out std_logic_vector((acc_width - 1) downto 0);
result_sum : out std_logic_vector((2*sig_width - 1) downto 0);
cmp_reg : out std_logic_vector((acc_width - 1) downto 0);
cmp_greater : out std_logic;
cmp_out : out std_logic
);
end component;
--=--------------------------------------------------------------------------
-- @signals definition
-----------------------------------------------------------------------------
signal s_reset : std_logic;
signal s_a1 : std_logic_vector((sig_width - 1) downto 0);
signal s_b1 : std_logic_vector((sig_width - 1) downto 0);
signal s_a2 : std_logic_vector((sig_width - 1) downto 0);
signal s_b2 : std_logic_vector((sig_width - 1) downto 0);
signal s_clk : std_logic;
signal s_clr_acc : std_logic;
signal s_acc_mode1 : std_logic_vector((acc_mode_width - 1) downto 0); -- t_acc_mode;
signal s_acc_mode2 : std_logic_vector((acc_mode_width - 1) downto 0); -- t_acc_mode;
signal s_alu_select : std_logic_vector((alu_select_width - 1) downto 0); -- t_alu_select;
signal s_result1 : std_logic_vector((sig_width - 1) downto 0);
signal s_result_acc1 : std_logic_vector((acc_width - 1) downto 0);
signal s_result2 : std_logic_vector((sig_width - 1) downto 0);
signal s_result_acc2 : std_logic_vector((acc_width - 1) downto 0);
signal s_cmp_mode : std_logic_vector((cmp_mode_width - 1) downto 0);
signal s_cmp_pol : std_logic;
signal s_cmp_store : std_logic;
signal s_chain_acc : std_logic;
signal s_cmp_reg : std_logic_vector((acc_width - 1) downto 0);
signal s_cmp_greater : std_logic;
signal s_cmp_out : std_logic;
signal s_result_sum : std_logic_vector((2*sig_width - 1) downto 0);
begin -- archs_bench_dspalu
-----------------------------------------------------------------------------
--
-- @instantiations
--
-----------------------------------------------------------------------------
clock_gen_1 : clock_gen
generic map (
tpw => 5 ns,
tps => 0 ns)
port map (
clk => s_clk,
reset => s_reset);
dspalu_acc_1 : dspalu_acc
generic map (
sig_width => sig_width,
acc_width => acc_width)
port map (
a1 => s_a1,
b1 => s_b1,
a2 => s_a2,
b2 => s_b2,
clk => s_clk,
clr_acc => s_clr_acc,
acc_mode1 => s_acc_mode1,
acc_mode2 => s_acc_mode2,
alu_select => s_alu_select,
cmp_mode => s_cmp_mode,
cmp_pol => s_cmp_pol,
cmp_store => s_cmp_store,
chain_acc => s_chain_acc,
result1 => s_result1,
result_acc1 => s_result_acc1,
result2 => s_result2,
result_acc2 => s_result_acc2,
result_sum => s_result_sum,
cmp_reg => s_cmp_reg,
cmp_greater => s_cmp_greater,
cmp_out => s_cmp_out);
--=---------------------------------------------------------------------------
--=---------------------------------------------------------------------------
--
-- @concurrent signal assignments
--
-----------------------------------------------------------------------------
s_a1 <= "0010000100000000", "0000000000000010" after 501 ns;
s_b1 <= "1111111111111011", "0000000000000011" after 501 ns;
s_a2 <= "0000000000000100";
s_b2 <= "1111111111111110";
s_clr_acc <= not s_reset;
s_acc_mode1 <= acc_add, acc_store after 201 ns, acc_sub after 301 ns, acc_sumstore after 401 ns,
acc_store after 501 ns, acc_sub after 701 ns, acc_add after 901 ns;
s_acc_mode2 <= acc_add, acc_store after 501 ns, acc_sub after 701 ns, acc_add after 901 ns;
s_alu_select <= alu_mul, alu_cmul after 501 ns;
end archi_bench_dspalu;
--------------------------------------------------------------------------------
-- Simulation parameters
-->SIMSTOPTIME=1000ns
-->SIMSAVFILE=dspalu.sav
-------------------------------------------------------------------------------
|
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`protect end_protected
|
library ieee;
use ieee.std_logic_1164.all;
entity TbdAudioCodecAvalon is
port(
-- Clock
Clock_50 : in std_logic;
-- KEYs
KEY : in std_logic_vector(0 downto 0);
-- Audio
AUD_ADCDAT : in std_logic;
AUD_ADCLRCK : in std_logic;
AUD_BCLK : in std_logic;
AUD_DACDAT : out std_logic;
AUD_DACLRCK : in std_logic;
AUD_XCK : out std_logic;
-- I2C for Audio and Video-In
FPGA_I2C_SCLK : out std_logic;
FPGA_I2C_SDAT : inout std_logic
);
end entity TbdAudioCodecAvalon;
|
-- NEED RESULT: ARCH00575: Can declare entities with same name as entities declared in a use'd pkg passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00575
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 10.4 (1)
--
-- DESIGN UNIT ORDERING:
--
-- PKG00574_575
-- PKG00574_575/BODY
-- ENT00575_Test_Bench(ARCH00575_Test_Bench)
--
-- REVISION HISTORY:
--
-- 19-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
package PKG00574_575 is
type T1 is (one, two, three, four) ;
type T2 is (one, two, three, four) ;
type T3 is (one, two, three, four) ;
type T4 is (one, two, three, four) ;
subtype S1 is INTEGER;
subtype S2 is INTEGER;
subtype S3 is INTEGER;
subtype S4 is INTEGER;
function F1 return REAL ;
function F2 return REAL ;
function F3 return REAL ;
function F4 return REAL ;
end PKG00574_575 ;
package body PKG00574_575 is
function F1 return REAL is begin
return 0.0; end;
function F2 return REAL is begin
return 0.0; end;
function F3 return REAL is begin
return 0.0; end;
function F4 return REAL is begin
return 0.0; end;
end PKG00574_575 ;
use WORK.STANDARD_TYPES.all ;
entity ENT00575_Test_Bench is
use WORK.PKG00574_575; use PKG00574_575.all;
end ENT00575_Test_Bench ;
architecture ARCH00575_Test_Bench of ENT00575_Test_Bench is begin
L_X_1 : block
type T1 is record -- should be able to define new type T1
TE : BOOLEAN;
end record;
subtype T2 is REAL range 0.0 to 256.0; -- ditto for subtype called T2
attribute T3 : PKG00574_575.T3 ; -- ditto for attribute calle
signal T4 : PKG00574_575.T1; -- ditto for object called T
type S1 is record -- should be able to define new type S1
SE : BOOLEAN;
end record;
subtype S2 is REAL range 0.0 to 256.0; -- ditto for subtype called S2
attribute S3 : PKG00574_575.T3 ; -- ditto for attribute calle
signal S4 : PKG00574_575.T1; -- ditto for object called
type F1 is record -- should be able to define new type F1
FE : BOOLEAN;
end record;
subtype F2 is REAL range 0.0 to 256.0; -- ditto for subtype called F2
attribute F3 : PKG00574_575.T3 ; -- ditto for attribute calle
signal F4 : PKG00574_575.T1; -- ditto for object called F
begin
process
variable T1 : PKG00574_575.T1; -- ditto for object called
variable F1 : PKG00574_575.T1; -- ditto for object called
variable S1 : PKG00574_575.T1; -- ditto for object called
begin
test_report ( "ARCH00575" ,
"Can declare entities with same name as entities "&
"declared in a use'd pkg" ,
True ) ;
wait ;
end process;
end block;
end ARCH00575_Test_Bench ;
|
-- Copyright (c) 2015 CERN
-- @author Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- 'wait on' & 'wait until' test
library ieee;
use ieee.std_logic_1164.all;
entity vhdl_wait is
port(a : in std_logic_vector(1 downto 0);
b : out std_logic_vector(1 downto 0));
end vhdl_wait;
architecture test of vhdl_wait is
begin
process begin
report "final wait test";
wait;
end process;
process begin
wait on a(0);
report "wait 1 completed";
-- acknowledge wait 1
b(0) <= '1';
end process;
process begin
wait until(a(1) = '1' and a(1)'event);
report "wait 2 completed";
-- acknowledge wait 2
b(1) <= '1';
end process;
end test;
|
-- Copyright (c) 2015 CERN
-- @author Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- 'wait on' & 'wait until' test
library ieee;
use ieee.std_logic_1164.all;
entity vhdl_wait is
port(a : in std_logic_vector(1 downto 0);
b : out std_logic_vector(1 downto 0));
end vhdl_wait;
architecture test of vhdl_wait is
begin
process begin
report "final wait test";
wait;
end process;
process begin
wait on a(0);
report "wait 1 completed";
-- acknowledge wait 1
b(0) <= '1';
end process;
process begin
wait until(a(1) = '1' and a(1)'event);
report "wait 2 completed";
-- acknowledge wait 2
b(1) <= '1';
end process;
end test;
|
--================================================================================================================================
-- Copyright (c) 2020 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the Apache License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@bitvis.no>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO
-- THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--================================================================================================================================
---------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
---------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
use work.support_pkg.all;
library bitvis_vip_sbi;
context bitvis_vip_sbi.vvc_context;
architecture SBI of hvvc_to_vvc_bridge is
begin
p_executor : process
constant c_data_words_width : natural := hvvc_to_bridge.data_words(hvvc_to_bridge.data_words'low)'length;
variable v_cmd_idx : integer;
variable v_sbi_received_data : bitvis_vip_sbi.vvc_cmd_pkg.t_vvc_result;
variable v_dut_address : unsigned(GC_DUT_IF_FIELD_CONFIG(GC_DUT_IF_FIELD_CONFIG'low)(GC_DUT_IF_FIELD_CONFIG(GC_DUT_IF_FIELD_CONFIG'low)'high).dut_address'range);
variable v_dut_address_increment : integer;
variable v_dut_data_width : positive;
variable v_num_transfers : integer;
variable v_data_slv : std_logic_vector(GC_MAX_NUM_WORDS*c_data_words_width-1 downto 0);
variable v_dut_if_field_pos_is_first : boolean;
variable v_dut_if_field_pos_is_last : boolean;
variable v_disabled_msg_id_int_wait : boolean;
variable v_disabled_msg_id_exe_wait : boolean;
--UVVM: temporary fix for HVVC, remove 2 lines below in v3.0
variable v_disabled_msg_id_int : boolean;
variable v_disabled_msg_id_exe : boolean;
-- Converts a t_slv_array to a std_logic_vector (word endianness is LOWER_WORD_RIGHT)
function convert_slv_array_to_slv(
constant slv_array : t_slv_array
) return std_logic_vector is
constant c_num_words : integer := slv_array'length;
constant c_word_len : integer := slv_array(slv_array'low)'length;
variable v_slv : std_logic_vector(c_num_words*c_word_len-1 downto 0);
begin
for word_idx in 0 to c_num_words-1 loop
v_slv(c_word_len*(word_idx+1)-1 downto c_word_len*word_idx) := slv_array(word_idx);
end loop;
return v_slv;
end function;
-- Converts a std_logic_vector to a t_slv_array (word endianness is LOWER_WORD_RIGHT)
function convert_slv_to_slv_array(
constant slv : std_logic_vector;
constant word_len : integer
) return t_slv_array is
constant c_num_words : integer := slv'length/word_len;
variable v_slv_array : t_slv_array(0 to c_num_words-1)(word_len-1 downto 0);
begin
for word_idx in 0 to c_num_words-1 loop
v_slv_array(word_idx) := slv(word_len*(word_idx+1)-1 downto word_len*word_idx);
end loop;
return v_slv_array;
end function;
-- Disables a previously enabled msg_id in the VVC's shared config
impure function disable_sbi_vvc_msg_id(
constant instance_idx : integer;
constant msg_id : t_msg_id
) return boolean is
variable v_disable_id : boolean := false;
begin
if shared_sbi_vvc_config(instance_idx).msg_id_panel(msg_id) = ENABLED then
shared_sbi_vvc_config(instance_idx).msg_id_panel(msg_id) := DISABLED;
v_disable_id := true;
end if;
return v_disable_id;
end function;
begin
loop
-- Await cmd from the HVVC
wait until hvvc_to_bridge.trigger = true;
-- Check the field position in the packet
v_dut_if_field_pos_is_first := hvvc_to_bridge.dut_if_field_pos = FIRST or hvvc_to_bridge.dut_if_field_pos = FIRST_AND_LAST;
v_dut_if_field_pos_is_last := hvvc_to_bridge.dut_if_field_pos = LAST or hvvc_to_bridge.dut_if_field_pos = FIRST_AND_LAST;
if v_dut_if_field_pos_is_first then
log(ID_NEW_HVVC_CMD_SEQ, "VVC is busy while executing an HVVC command", "SBI_VVC," & to_string(GC_INSTANCE_IDX), shared_sbi_vvc_config(GC_INSTANCE_IDX).msg_id_panel);
-- Disable the interpreter and executor waiting logs during the HVVC command
v_disabled_msg_id_int_wait := disable_sbi_vvc_msg_id(GC_INSTANCE_IDX, ID_CMD_INTERPRETER_WAIT);
v_disabled_msg_id_exe_wait := disable_sbi_vvc_msg_id(GC_INSTANCE_IDX, ID_CMD_EXECUTOR_WAIT);
--UVVM: temporary fix for HVVC, remove 2 lines below in v3.0
v_disabled_msg_id_int := disable_sbi_vvc_msg_id(GC_INSTANCE_IDX, ID_CMD_INTERPRETER);
v_disabled_msg_id_exe := disable_sbi_vvc_msg_id(GC_INSTANCE_IDX, ID_CMD_EXECUTOR);
end if;
-- Get the next DUT address from the config to write the data
get_dut_address_config(GC_DUT_IF_FIELD_CONFIG, hvvc_to_bridge, v_dut_address, v_dut_address_increment);
-- Get the next DUT data width from the config
get_data_width_config(GC_DUT_IF_FIELD_CONFIG, hvvc_to_bridge, v_dut_data_width);
-- Calculate number of transfers
v_num_transfers := (hvvc_to_bridge.num_data_words*c_data_words_width)/v_dut_data_width;
-- Extra transfer if data bits remainder
if ((hvvc_to_bridge.num_data_words*c_data_words_width) rem v_dut_data_width) /= 0 then
v_num_transfers := v_num_transfers+1;
end if;
-- Execute command
case hvvc_to_bridge.operation is
when TRANSMIT =>
--UVVM: temporary fix for HVVC, remove line below in v3.0
shared_sbi_vvc_config(GC_INSTANCE_IDX).parent_msg_id_panel := hvvc_to_bridge.msg_id_panel;
-- Convert from t_slv_array to std_logic_vector (word endianness is LOWER_WORD_RIGHT)
v_data_slv(hvvc_to_bridge.num_data_words*c_data_words_width-1 downto 0) := convert_slv_array_to_slv(hvvc_to_bridge.data_words(0 to hvvc_to_bridge.num_data_words-1));
-- Loop through transfers
for i in 0 to v_num_transfers-1 loop
sbi_write(SBI_VVCT, GC_INSTANCE_IDX, v_dut_address, v_data_slv(v_dut_data_width*(i+1)-1 downto v_dut_data_width*i),
"HVVC: Write data via SBI.", GC_SCOPE, hvvc_to_bridge.msg_id_panel);
-- Enable the executor waiting log after receiving its last command
if v_disabled_msg_id_exe_wait and v_dut_if_field_pos_is_last and i = v_num_transfers-1 then
shared_sbi_vvc_config(GC_INSTANCE_IDX).msg_id_panel(ID_CMD_EXECUTOR_WAIT) := ENABLED;
end if;
v_cmd_idx := get_last_received_cmd_idx(SBI_VVCT, GC_INSTANCE_IDX, NA, GC_SCOPE);
await_completion(SBI_VVCT, GC_INSTANCE_IDX, v_cmd_idx, GC_MAX_NUM_WORDS*GC_PHY_MAX_ACCESS_TIME, "HVVC: Wait for write to finish.", GC_SCOPE, hvvc_to_bridge.msg_id_panel);
v_dut_address := v_dut_address + v_dut_address_increment;
end loop;
when RECEIVE =>
--UVVM: temporary fix for HVVC, remove line below in v3.0
shared_sbi_vvc_config(GC_INSTANCE_IDX).parent_msg_id_panel := hvvc_to_bridge.msg_id_panel;
-- Loop through transfers
for i in 0 to v_num_transfers-1 loop
sbi_read(SBI_VVCT, GC_INSTANCE_IDX, v_dut_address, "HVVC: Read data via SBI.", GC_SCOPE, hvvc_to_bridge.msg_id_panel);
-- Enable the executor waiting log after receiving its last command
if v_disabled_msg_id_exe_wait and v_dut_if_field_pos_is_last and i = v_num_transfers-1 then
shared_sbi_vvc_config(GC_INSTANCE_IDX).msg_id_panel(ID_CMD_EXECUTOR_WAIT) := ENABLED;
end if;
v_cmd_idx := get_last_received_cmd_idx(SBI_VVCT, GC_INSTANCE_IDX, NA, GC_SCOPE);
await_completion(SBI_VVCT, GC_INSTANCE_IDX, v_cmd_idx, GC_MAX_NUM_WORDS*GC_PHY_MAX_ACCESS_TIME, "HVVC: Wait for read to finish.", GC_SCOPE, hvvc_to_bridge.msg_id_panel);
fetch_result(SBI_VVCT, GC_INSTANCE_IDX, v_cmd_idx, v_sbi_received_data, "HVVC: Fetching received data.", TB_ERROR, GC_SCOPE, hvvc_to_bridge.msg_id_panel);
v_data_slv(v_dut_data_width*(i+1)-1 downto v_dut_data_width*i) := v_sbi_received_data(v_dut_data_width-1 downto 0);
v_dut_address := v_dut_address + v_dut_address_increment;
end loop;
-- Convert from std_logic_vector to t_slv_array (word endianness is LOWER_WORD_RIGHT)
bridge_to_hvvc.data_words(0 to hvvc_to_bridge.num_data_words-1) <= convert_slv_to_slv_array(v_data_slv(hvvc_to_bridge.num_data_words*c_data_words_width-1 downto 0), c_data_words_width);
when others =>
alert(TB_ERROR, "Unsupported operation");
end case;
-- Enable the interpreter waiting log after receiving its last command
if v_disabled_msg_id_int_wait and v_dut_if_field_pos_is_last then
shared_sbi_vvc_config(GC_INSTANCE_IDX).msg_id_panel(ID_CMD_INTERPRETER_WAIT) := ENABLED;
end if;
--UVVM: temporary fix for HVVC, remove 4 lines below in v3.0
if v_dut_if_field_pos_is_last then
shared_sbi_vvc_config(GC_INSTANCE_IDX).msg_id_panel(ID_CMD_INTERPRETER) := ENABLED when v_disabled_msg_id_int;
shared_sbi_vvc_config(GC_INSTANCE_IDX).msg_id_panel(ID_CMD_EXECUTOR) := ENABLED when v_disabled_msg_id_exe;
end if;
gen_pulse(bridge_to_hvvc.trigger, 0 ns, "Pulsing bridge_to_hvvc trigger", GC_SCOPE, ID_NEVER);
end loop;
end process;
end architecture SBI; |
library ieee;
use ieee.std_logic_1164.all;
entity test_stencil_buffer is
end test_stencil_buffer;
architecture behavioural of test_stencil_buffer is
component stencil_buffer is
generic (
addr_bits : natural
);
port (
clock : in std_logic;
advance: in std_logic;
input : in std_logic_vector;
tl : out std_logic_vector;
tc : out std_logic_vector;
tr : out std_logic_vector;
ml : out std_logic_vector;
mc : out std_logic_vector;
mr : out std_logic_vector;
bl : out std_logic_vector;
bc : out std_logic_vector;
br : out std_logic_vector
);
end component stencil_buffer;
signal period: time := 10 ns;
signal clock : std_logic := '0';
signal finished : std_logic := '0';
signal advance : std_logic := '0';
signal input : std_logic_vector(7 downto 0);
signal tl : std_logic_vector(7 downto 0);
signal tc : std_logic_vector(7 downto 0);
signal tr : std_logic_vector(7 downto 0);
signal ml : std_logic_vector(7 downto 0);
signal mc : std_logic_vector(7 downto 0);
signal mr : std_logic_vector(7 downto 0);
signal bl : std_logic_vector(7 downto 0);
signal bc : std_logic_vector(7 downto 0);
signal br : std_logic_vector(7 downto 0);
begin
clock <= not clock after period/2 when finished='0';
BUFF: stencil_buffer generic map (addr_bits => 4) -- 16 places; large enough for a 3x3 stencil
port map (clock, advance, input,
tl, tc, tr,
ml, mc, mr,
bl, bc, br);
process
begin
-- Fill test
advance <= '1';
input <= "11001100";
wait for 9 * period;
assert tl = "11001100" report "tl should be filled" severity error;
assert tc = "11001100" report "tc should be filled" severity error;
assert tr = "11001100" report "tr should be filled" severity error;
assert ml = "11001100" report "ml should be filled" severity error;
assert mc = "11001100" report "mc should be filled" severity error;
assert mr = "11001100" report "mr should be filled" severity error;
assert bl = "11001100" report "bl should be filled" severity error;
assert bc = "11001100" report "bc should be filled" severity error;
assert br = "11001100" report "br should be filled" severity error;
-- Order test
input <= "00000000"; wait for period;
input <= "00000001"; wait for period;
input <= "00000010"; wait for period;
input <= "00000011"; wait for period;
input <= "00000100"; wait for period;
input <= "00000101"; wait for period;
input <= "00000110"; wait for period;
input <= "00000111"; wait for period;
input <= "00001000"; wait for period;
assert tl = "00000000" report "tl should contain the correct value" severity error;
assert tc = "00000001" report "tc should contain the correct value" severity error;
assert tr = "00000010" report "tr should contain the correct value" severity error;
assert ml = "00000011" report "ml should contain the correct value" severity error;
assert mc = "00000100" report "mc should contain the correct value" severity error;
assert mr = "00000101" report "mr should contain the correct value" severity error;
assert bl = "00000110" report "bl should contain the correct value" severity error;
assert bc = "00000111" report "bc should contain the correct value" severity error;
assert br = "00001000" report "br should contain the correct value" severity error;
-- Scroll test
input <= "00001001"; wait for period;
input <= "00001010"; wait for period;
input <= "00001011"; wait for period;
assert tl = "00000011" report "tl should contain the correct value" severity error;
assert tc = "00000100" report "tc should contain the correct value" severity error;
assert tr = "00000101" report "tr should contain the correct value" severity error;
assert ml = "00000110" report "ml should contain the correct value" severity error;
assert mc = "00000111" report "mc should contain the correct value" severity error;
assert mr = "00001000" report "mr should contain the correct value" severity error;
assert bl = "00001001" report "bl should contain the correct value" severity error;
assert bc = "00001010" report "bc should contain the correct value" severity error;
assert br = "00001011" report "br should contain the correct value" severity error;
wait for 30 * period;
finished <= '1';
wait;
end process;
end behavioural;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTXTOD.VHD ***
--*** ***
--*** Function: Cast Internal Single to IEEE754 ***
--*** Double ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castxtod IS
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
mantissa : positive := 32;
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_castxtod;
ARCHITECTURE rtl OF hcc_castxtod IS
signal yvector : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal yvectorsat, yvectorzip : STD_LOGIC;
component hcc_castxtoy IS
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
mantissa : positive := 32
);
PORT (
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_castytod
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
corein: hcc_castxtoy
GENERIC MAP (target=>1,mantissa=>mantissa)
PORT MAP (aa=>aa,aasat=>aasat,aazip=>aazip,
cc=>yvector,ccsat=>yvectorsat,cczip=>yvectorzip);
coreout: hcc_castytod
GENERIC MAP (roundconvert=>roundconvert,normspeed=>normspeed,
doublespeed=>doublespeed,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>yvector,aasat=>yvectorsat,aazip=>yvectorzip,
cc=>cc);
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTXTOD.VHD ***
--*** ***
--*** Function: Cast Internal Single to IEEE754 ***
--*** Double ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castxtod IS
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
mantissa : positive := 32;
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_castxtod;
ARCHITECTURE rtl OF hcc_castxtod IS
signal yvector : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal yvectorsat, yvectorzip : STD_LOGIC;
component hcc_castxtoy IS
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
mantissa : positive := 32
);
PORT (
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_castytod
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
corein: hcc_castxtoy
GENERIC MAP (target=>1,mantissa=>mantissa)
PORT MAP (aa=>aa,aasat=>aasat,aazip=>aazip,
cc=>yvector,ccsat=>yvectorsat,cczip=>yvectorzip);
coreout: hcc_castytod
GENERIC MAP (roundconvert=>roundconvert,normspeed=>normspeed,
doublespeed=>doublespeed,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>yvector,aasat=>yvectorsat,aazip=>yvectorzip,
cc=>cc);
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTXTOD.VHD ***
--*** ***
--*** Function: Cast Internal Single to IEEE754 ***
--*** Double ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castxtod IS
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
mantissa : positive := 32;
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_castxtod;
ARCHITECTURE rtl OF hcc_castxtod IS
signal yvector : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal yvectorsat, yvectorzip : STD_LOGIC;
component hcc_castxtoy IS
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
mantissa : positive := 32
);
PORT (
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_castytod
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
corein: hcc_castxtoy
GENERIC MAP (target=>1,mantissa=>mantissa)
PORT MAP (aa=>aa,aasat=>aasat,aazip=>aazip,
cc=>yvector,ccsat=>yvectorsat,cczip=>yvectorzip);
coreout: hcc_castytod
GENERIC MAP (roundconvert=>roundconvert,normspeed=>normspeed,
doublespeed=>doublespeed,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>yvector,aasat=>yvectorsat,aazip=>yvectorzip,
cc=>cc);
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTXTOD.VHD ***
--*** ***
--*** Function: Cast Internal Single to IEEE754 ***
--*** Double ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castxtod IS
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
mantissa : positive := 32;
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_castxtod;
ARCHITECTURE rtl OF hcc_castxtod IS
signal yvector : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal yvectorsat, yvectorzip : STD_LOGIC;
component hcc_castxtoy IS
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
mantissa : positive := 32
);
PORT (
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_castytod
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
corein: hcc_castxtoy
GENERIC MAP (target=>1,mantissa=>mantissa)
PORT MAP (aa=>aa,aasat=>aasat,aazip=>aazip,
cc=>yvector,ccsat=>yvectorsat,cczip=>yvectorzip);
coreout: hcc_castytod
GENERIC MAP (roundconvert=>roundconvert,normspeed=>normspeed,
doublespeed=>doublespeed,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>yvector,aasat=>yvectorsat,aazip=>yvectorzip,
cc=>cc);
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTXTOD.VHD ***
--*** ***
--*** Function: Cast Internal Single to IEEE754 ***
--*** Double ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castxtod IS
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
mantissa : positive := 32;
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_castxtod;
ARCHITECTURE rtl OF hcc_castxtod IS
signal yvector : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal yvectorsat, yvectorzip : STD_LOGIC;
component hcc_castxtoy IS
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
mantissa : positive := 32
);
PORT (
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_castytod
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
corein: hcc_castxtoy
GENERIC MAP (target=>1,mantissa=>mantissa)
PORT MAP (aa=>aa,aasat=>aasat,aazip=>aazip,
cc=>yvector,ccsat=>yvectorsat,cczip=>yvectorzip);
coreout: hcc_castytod
GENERIC MAP (roundconvert=>roundconvert,normspeed=>normspeed,
doublespeed=>doublespeed,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>yvector,aasat=>yvectorsat,aazip=>yvectorzip,
cc=>cc);
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTXTOD.VHD ***
--*** ***
--*** Function: Cast Internal Single to IEEE754 ***
--*** Double ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castxtod IS
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
mantissa : positive := 32;
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_castxtod;
ARCHITECTURE rtl OF hcc_castxtod IS
signal yvector : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal yvectorsat, yvectorzip : STD_LOGIC;
component hcc_castxtoy IS
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
mantissa : positive := 32
);
PORT (
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_castytod
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
corein: hcc_castxtoy
GENERIC MAP (target=>1,mantissa=>mantissa)
PORT MAP (aa=>aa,aasat=>aasat,aazip=>aazip,
cc=>yvector,ccsat=>yvectorsat,cczip=>yvectorzip);
coreout: hcc_castytod
GENERIC MAP (roundconvert=>roundconvert,normspeed=>normspeed,
doublespeed=>doublespeed,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>yvector,aasat=>yvectorsat,aazip=>yvectorzip,
cc=>cc);
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTXTOD.VHD ***
--*** ***
--*** Function: Cast Internal Single to IEEE754 ***
--*** Double ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castxtod IS
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
mantissa : positive := 32;
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_castxtod;
ARCHITECTURE rtl OF hcc_castxtod IS
signal yvector : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal yvectorsat, yvectorzip : STD_LOGIC;
component hcc_castxtoy IS
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
mantissa : positive := 32
);
PORT (
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_castytod
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
corein: hcc_castxtoy
GENERIC MAP (target=>1,mantissa=>mantissa)
PORT MAP (aa=>aa,aasat=>aasat,aazip=>aazip,
cc=>yvector,ccsat=>yvectorsat,cczip=>yvectorzip);
coreout: hcc_castytod
GENERIC MAP (roundconvert=>roundconvert,normspeed=>normspeed,
doublespeed=>doublespeed,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>yvector,aasat=>yvectorsat,aazip=>yvectorzip,
cc=>cc);
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTXTOD.VHD ***
--*** ***
--*** Function: Cast Internal Single to IEEE754 ***
--*** Double ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castxtod IS
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
mantissa : positive := 32;
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_castxtod;
ARCHITECTURE rtl OF hcc_castxtod IS
signal yvector : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal yvectorsat, yvectorzip : STD_LOGIC;
component hcc_castxtoy IS
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
mantissa : positive := 32
);
PORT (
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_castytod
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
corein: hcc_castxtoy
GENERIC MAP (target=>1,mantissa=>mantissa)
PORT MAP (aa=>aa,aasat=>aasat,aazip=>aazip,
cc=>yvector,ccsat=>yvectorsat,cczip=>yvectorzip);
coreout: hcc_castytod
GENERIC MAP (roundconvert=>roundconvert,normspeed=>normspeed,
doublespeed=>doublespeed,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>yvector,aasat=>yvectorsat,aazip=>yvectorzip,
cc=>cc);
END rtl;
|
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