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LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTXTOD.VHD ***
--*** ***
--*** Function: Cast Internal Single to IEEE754 ***
--*** Double ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castxtod IS
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
mantissa : positive := 32;
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_castxtod;
ARCHITECTURE rtl OF hcc_castxtod IS
signal yvector : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal yvectorsat, yvectorzip : STD_LOGIC;
component hcc_castxtoy IS
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
mantissa : positive := 32
);
PORT (
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_castytod
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
corein: hcc_castxtoy
GENERIC MAP (target=>1,mantissa=>mantissa)
PORT MAP (aa=>aa,aasat=>aasat,aazip=>aazip,
cc=>yvector,ccsat=>yvectorsat,cczip=>yvectorzip);
coreout: hcc_castytod
GENERIC MAP (roundconvert=>roundconvert,normspeed=>normspeed,
doublespeed=>doublespeed,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>yvector,aasat=>yvectorsat,aazip=>yvectorzip,
cc=>cc);
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTXTOD.VHD ***
--*** ***
--*** Function: Cast Internal Single to IEEE754 ***
--*** Double ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castxtod IS
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
mantissa : positive := 32;
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_castxtod;
ARCHITECTURE rtl OF hcc_castxtod IS
signal yvector : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal yvectorsat, yvectorzip : STD_LOGIC;
component hcc_castxtoy IS
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
mantissa : positive := 32
);
PORT (
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_castytod
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
corein: hcc_castxtoy
GENERIC MAP (target=>1,mantissa=>mantissa)
PORT MAP (aa=>aa,aasat=>aasat,aazip=>aazip,
cc=>yvector,ccsat=>yvectorsat,cczip=>yvectorzip);
coreout: hcc_castytod
GENERIC MAP (roundconvert=>roundconvert,normspeed=>normspeed,
doublespeed=>doublespeed,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>yvector,aasat=>yvectorsat,aazip=>yvectorzip,
cc=>cc);
END rtl;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Thomas B. Preusser
--
-- Module: Computes XOR masks for stream scrambling from an LFSR generator.
--
-- Description:
-- ------------------------------------
-- The LFSR computation is unrolled to generate an arbitrary number of mask
-- bits in parallel. The mask are output in little endian. The generated bit
-- sequence is independent from the chosen output width.
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
entity comm_scramble is
generic (
GEN : bit_vector; -- Generator Polynomial (little endian)
BITS : positive -- Width of Mask Bits to be computed in parallel
);
port (
clk : in std_logic; -- Clock
set : in std_logic; -- Set LFSR to provided Value
din : in std_logic_vector(GEN'length-2 downto 0);
step : in std_logic; -- Compute a Mask Output
mask : out std_logic_vector(BITS-1 downto 0)
);
end comm_scramble;
architecture rtl of comm_scramble is
-----------------------------------------------------------------------------
-- Normalizes a generator representation:
-- - into a 'downto 0' index range and
-- - truncating it just below the most significant and so hidden '1'.
function normalize(G : bit_vector) return bit_vector is
variable GN : bit_vector(G'length-1 downto 0);
begin
GN := G;
for i in GN'left downto 1 loop
if GN(i) = '1' then
return GN(i-1 downto 0);
end if;
end loop;
report "Cannot use absolute constant as generator."
severity failure;
end normalize;
-- Normalized Generator
constant GN : bit_vector := normalize(GEN);
-- LFSR Value
signal lfsr : std_logic_vector(GN'range);
begin
process(clk)
-- Intermediate LFSR Values for single-bit Steps
variable v : std_logic_vector(lfsr'range);
begin
if rising_edge(clk) then
if set = '1' then
lfsr <= din(lfsr'range);
elsif step = '1' then
v := lfsr;
for i in 0 to BITS-1 loop
mask(i) <= v(v'left);
v := (v(v'left-1 downto 0) & '0') xor
(to_stdlogicvector(GN) and (GN'range => v(v'left)));
end loop;
lfsr <= v;
end if;
end if;
end process;
end rtl;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Thomas B. Preusser
--
-- Module: Computes XOR masks for stream scrambling from an LFSR generator.
--
-- Description:
-- ------------------------------------
-- The LFSR computation is unrolled to generate an arbitrary number of mask
-- bits in parallel. The mask are output in little endian. The generated bit
-- sequence is independent from the chosen output width.
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
entity comm_scramble is
generic (
GEN : bit_vector; -- Generator Polynomial (little endian)
BITS : positive -- Width of Mask Bits to be computed in parallel
);
port (
clk : in std_logic; -- Clock
set : in std_logic; -- Set LFSR to provided Value
din : in std_logic_vector(GEN'length-2 downto 0);
step : in std_logic; -- Compute a Mask Output
mask : out std_logic_vector(BITS-1 downto 0)
);
end comm_scramble;
architecture rtl of comm_scramble is
-----------------------------------------------------------------------------
-- Normalizes a generator representation:
-- - into a 'downto 0' index range and
-- - truncating it just below the most significant and so hidden '1'.
function normalize(G : bit_vector) return bit_vector is
variable GN : bit_vector(G'length-1 downto 0);
begin
GN := G;
for i in GN'left downto 1 loop
if GN(i) = '1' then
return GN(i-1 downto 0);
end if;
end loop;
report "Cannot use absolute constant as generator."
severity failure;
end normalize;
-- Normalized Generator
constant GN : bit_vector := normalize(GEN);
-- LFSR Value
signal lfsr : std_logic_vector(GN'range);
begin
process(clk)
-- Intermediate LFSR Values for single-bit Steps
variable v : std_logic_vector(lfsr'range);
begin
if rising_edge(clk) then
if set = '1' then
lfsr <= din(lfsr'range);
elsif step = '1' then
v := lfsr;
for i in 0 to BITS-1 loop
mask(i) <= v(v'left);
v := (v(v'left-1 downto 0) & '0') xor
(to_stdlogicvector(GN) and (GN'range => v(v'left)));
end loop;
lfsr <= v;
end if;
end if;
end process;
end rtl;
|
LIBRARY IEEE; -- These lines informs the compiler that the library IEEE is used
USE IEEE.std_logic_1164.all; -- contains the definition for the std_logic type plus some useful conversion functions
USE IEEE.std_logic_signed.all; --math operations for signed std_logic
ENTITY counter_up_down_4bit IS
PORT(up, clk, reset: IN STD_LOGIC;
out1: OUT STD_LOGIC;
out2: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END counter_up_down_4bit;
ARCHITECTURE behave OF counter_up_down_4bit IS
SIGNAL count : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS (clk, reset)
BEGIN
IF reset='0' THEN --asynchronous active low reset
count<=(OTHERS=>'0');
ELSIF rising_edge(clk) THEN
CASE up IS
WHEN '1'=>
count<=count+1;
WHEN OTHERS=>
count<=count-1;
END CASE;
IF ((count=15 AND up='1') OR (count=0 AND up='0')) THEN
out1<='1';
ELSE
out1<='0';
END IF;
out2<=count;
END IF;
END PROCESS;
END behave; -- Arch_counter_sig
|
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-15 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : CNE_01600_good.vhd
-- File Creation date : 2015-04-15
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Identification of package element: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.pkg_HBK.all;
entity CNE_01600_good is
port (
i_Clock : in std_logic; -- Global clock signal
i_Reset_n : in std_logic; -- Global reset signal
i_Raz : in std_logic; -- Reset counting and load length
i_Enable : in std_logic; -- Enable the counter
i_Length : in std_logic_vector(pkg_Width downto 0); -- How much the module should count (Value expected - 1)
o_Done : out std_logic -- Counter output
);
end CNE_01600_good;
architecture Behavioral of CNE_01600_good is
signal Count : signed(pkg_Width downto 0); -- Counting signal
signal Length : signed(pkg_Width downto 0); -- How much the module should count
signal Done : std_logic; -- Counter output
begin
P_Count:process(i_Reset_n, i_Clock)
begin
if (i_Reset_n='0') then
Count <= (others => '0');
Length <= (others => '0');
Done <= '0';
elsif (rising_edge(i_Clock)) then
if (i_Raz='1') then
-- Reset the counting
Length <= signed(i_Length);
Count <= (others => '0');
elsif (i_Enable='1' and Done='0') then
-- Counter activated and not finished
Count <= Count + 1;
end if;
if (Count>=Length) then -- Compared elements are of the same type and dimension
-- Counter finished
Done <= '1';
else
Done <= '0';
end if;
end if;
end process;
o_Done <= Done;
end Behavioral; |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:39:36 11/01/2015
-- Design Name:
-- Module Name: clock_divider_V2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity clock_divider_V2 is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
clk_out : out STD_LOGIC);
end clock_divider_V2;
architecture Behavioral of clock_divider_V2 is
-- Components --
component downcounter is
Generic ( period: integer:= 4;
WIDTH: integer:= 3);
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
enable : in STD_LOGIC;
zero : out STD_LOGIC;
value: out STD_LOGIC_VECTOR(WIDTH-1 downto 0));
end component;
-- Internal Signals --
signal kilohertz: STD_LOGIC;
signal hundredhertz: STD_LOGIC;
signal tenhertz: STD_LOGIC;
signal onehertz: STD_LOGIC;
signal counter_value : STD_LOGIC_VECTOR( 3 downto 0 );
signal i_clk_out : std_logic;
begin
kiloHzClock: downcounter
generic map(
period => (39-1),
WIDTH => 15
)
port map (
clk => clk,
reset => reset,
enable => '1',
zero => kilohertz,
value => open
);
hundredHzClock: downcounter
generic map(
period => (10-1),
WIDTH => 4
)
port map (
clk => clk,
reset => reset,
enable => kilohertz,
zero => hundredhertz,
value => counter_value
);
tenHzClock: downcounter
generic map(
period => (10-1),
WIDTH => 4
)
port map (
clk => clk,
reset => reset,
enable => hundredhertz,
zero => tenhertz,
value => open
);
oneHZClock: downcounter
generic map(
period => (10-1),
WIDTH => 4
)
port map (
clk => clk,
reset => reset,
enable => tenhertz,
zero => onehertz,
value => open
);
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
i_clk_out <= '1';
elsif (counter_value = "1000") then -- switch polarity every half period
i_clk_out <= '0';
else
i_clk_out <= '1';
end if;
end if;
end process;
clk_out <= i_clk_out;
end Behavioral;
|
-- *******************************************************************
-- Copyright 2008 Ray Salemi
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ********************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity tinyalu is
port(
A : in unsigned ( 7 downto 0 );
B : in unsigned ( 7 downto 0 );
clk : in std_logic;
op : in std_logic_vector ( 2 downto 0 );
reset_n : in std_logic;
start : in std_logic;
done : out std_logic;
result : out unsigned ( 15 downto 0 )
);
-- Declarations
end tinyalu;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
library work;
architecture rtl of tinyalu is
-- Architecture declarations
-- Internal signal declarations
signal done_aax : std_logic;
signal done_mult : std_logic;
signal result_aax : unsigned(15 downto 0);
signal result_mult : unsigned(15 downto 0);
signal start_single : std_logic; -- Start signal for single cycle ops
signal start_mult : std_logic; -- start signal for multiply
-- Implicit buffer signal declarations
signal done_internal : std_logic;
-- Component Declarations
-- pragma synthesis_off
component alu_firewall
port (
A : in unsigned ( 7 downto 0 );
B : in unsigned ( 7 downto 0 );
clk : in std_logic;
done : in std_logic;
op : in std_logic_vector ( 2 downto 0 );
reset_n : in std_logic;
start : in std_logic
);
end component;
-- pragma synthesis_on
component single_cycle
port (
A : in unsigned ( 7 downto 0 );
B : in unsigned ( 7 downto 0 );
clk : in std_logic;
op : in std_logic_vector ( 2 downto 0 );
reset_n : in std_logic;
start : in std_logic;
done_aax : out std_logic;
result_aax : out unsigned (15 downto 0)
);
end component;
component three_cycle
port (
A : in unsigned ( 7 downto 0 );
B : in unsigned ( 7 downto 0 );
clk : in std_logic;
reset_n : in std_logic;
start : in std_logic;
done_mult : out std_logic;
result_mult : out unsigned (15 downto 0)
);
end component;
-- Optional embedded configurations
-- pragma synthesis_off
for all : alu_firewall use entity work.alu_firewall;
for all : single_cycle use entity work.single_cycle;
for all : three_cycle use entity work.three_cycle;
-- pragma synthesis_on
begin
-- purpose: This block shunts the start signal to the correct block.
-- The multiply only sees the start signal when op(2) is '1'
-- type : combinational
-- inputs : op(2),start
-- outputs: start_mult, start_single
start_demux: process (op(2),start)
begin -- process start_demux
case op(2) is
when '0' =>
start_single <= start;
start_mult <= '0';
when '1' =>
start_single <= '0';
start_mult <= start;
when others => null;
end case;
end process start_demux;
result_mux : process(result_aax, result_mult, op)
begin
case op(2) is
when '0' => result <= result_aax;
when '1' => result <= result_mult;
when others => result <= (others => 'X');
end case;
end process result_mux;
done_mux : process(done_aax, done_mult, op)
begin
case op(2) is
when '0' => done_internal <= done_aax;
when '1' => done_internal <= done_mult;
when others => done_internal <= 'X';
end case;
end process done_mux;
-- Instance port mappings.
-- pragma synthesis_off
firewall : alu_firewall
port map (
A => A,
B => B,
clk => clk,
done => done_internal,
op => op,
reset_n => reset_n,
start => start);
-- pragma synthesis_on
add_and_xor : single_cycle
port map (
A => A,
B => B,
clk => clk,
op => op,
reset_n => reset_n,
start => start_single,
done_aax => done_aax,
result_aax => result_aax
);
mult : three_cycle
port map (
A => A,
B => B,
clk => clk,
reset_n => reset_n,
start => start_mult,
done_mult => done_mult,
result_mult => result_mult
);
-- Implicit buffered output assignments
done <= done_internal;
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dual_port_ram is
generic (
DATA_WIDTH : natural := 1;
ADDRESS_WIDTH : natural := 18
);
port (
clock: in std_logic;
write_enable : in std_logic;
address_A : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
address_B : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
data_A : in std_logic_vector(DATA_WIDTH-1 downto 0);
data_B : out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end entity dual_port_ram;
architecture dual_port_ram_arq of dual_port_ram is
attribute ram_style : string;
constant memo_size : natural := 2**ADDRESS_WIDTH;
subtype memo_i is integer range 0 to memo_size-1;
subtype t_word is std_logic_vector(DATA_WIDTH-1 downto 0);
type memo is array(0 to (memo_size-1)) of t_word;
signal RAM : memo := (others => (others => '0'));
attribute ram_style of ram: signal is "block";
-- DEBUG
---type memo_aux is array(0 to (memo_size-1)) of std_logic;
---signal RAM_aux : memo_aux := (others => '0');
signal address_A_int : memo_i := 0;---integer := 0;
signal address_B_int : memo_i := 0;---integer := 0;
begin
--DEBUG
---ram_test: for i in 0 to memo_size-1 generate
--- RAM_aux(i) <= RAM(i)(0);
---end generate;
address_A_int <= to_integer(unsigned(address_A));
address_B_int <= to_integer(unsigned(address_B));
process(clock)
begin
if rising_edge(clock) then
if write_enable = '1' then
RAM(address_A_int) <= data_A;
end if;
data_B <= RAM(address_B_int);
end if;
end process;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- Author: R. Azevedo Santos (rodrigo4zevedo@gmail.com)
-- Co-Author: Joao Lucas Magalini Zago
--
-- VHDL Implementation of (7,5) Reed Solomon
-- Course: Information Theory - 2014 - Ohio Northern University
entity SymbolAdder is
Port ( a : in std_logic_vector(2 downto 0);
b : in std_logic_vector(2 downto 0);
c : out std_logic_vector(2 downto 0));
end SymbolAdder;
architecture Behavioral of SymbolAdder is
begin
c(0) <= a(0) xor b(0);
c(1) <= a(1) xor b(1);
c(2) <= a(2) xor b(2);
end Behavioral;
|
architecture RTL of FIFO is
end architecture RTL;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Design Name:
-- Module Name: dsDMA_Transact - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision 1.30 - DMA engine divided into 2 modules: calculation and FSM. 26.07.2007
--
-- Revision 1.20 - DMA engine shared out. 12.02.2007
--
-- Revision 1.10 - x4 timing constraints met. 02.02.2007
--
-- Revision 1.04 - Timing improved. 17.01.2007
--
-- Revision 1.02 - FIFO added. 20.12.2006
--
-- Revision 1.00 - first release. 14.12.2006
--
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library work;
use work.abb64Package.all;
use work.genram_pkg.all;
entity dsDMA_Transact is
port (
-- downstream DMA Channel Buffer
MRd_dsp_Req : out std_logic;
MRd_dsp_RE : in std_logic;
MRd_dsp_Qout : out std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
-- Downstream reset from MWr channel
dsDMA_Channel_Rst : in std_logic;
-- Downstream Registers from MWr Channel
DMA_ds_PA : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_HA : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_BDA : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_Length : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_Control : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
dsDMA_BDA_eq_Null : in std_logic;
-- Calculation in advance, for better timing
dsHA_is_64b : in std_logic;
dsBDA_is_64b : in std_logic;
-- Calculation in advance, for better timing
dsLeng_Hi19b_True : in std_logic;
dsLeng_Lo7b_True : in std_logic;
-- from Cpl/D channel
dsDMA_dex_Tag : in std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- Downstream Control Signals from MWr Channel
dsDMA_Start : in std_logic; -- out of 1st dex
dsDMA_Stop : in std_logic; -- out of 1st dex
-- Downstream Control Signals from CplD Channel
dsDMA_Start2 : in std_logic; -- out of consecutive dex
dsDMA_Stop2 : in std_logic; -- out of consecutive dex
-- Downstream DMA Acknowledge to the start command
DMA_Cmd_Ack : out std_logic;
-- Downstream Handshake Signals with CplD Channel for Busy/Done
Tag_Map_Clear : in std_logic_vector(C_TAG_MAP_WIDTH-1 downto 0);
FC_pop : in std_logic;
-- Downstream tRAM port A write request
tRAM_weB : out std_logic;
tRAM_AddrB : out std_logic_vector(C_TAGRAM_AWIDTH-1 downto 0);
tRAM_dinB : out std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
-- To Interrupt module
DMA_Done : out std_logic;
DMA_TimeOut : out std_logic;
DMA_Busy : out std_logic;
-- To Tx Port
DMA_ds_Status : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Additional
cfg_dcommand : in std_logic_vector(C_CFG_COMMAND_DWIDTH-1 downto 0);
-- Common ports
user_clk : in std_logic
);
end entity dsDMA_Transact;
architecture Behavioral of dsDMA_Transact is
signal FC_push : std_logic;
signal FC_counter : std_logic_vector(C_TAGRAM_AWIDTH-1 downto 0);
signal dsFC_stop : std_logic;
signal dsFC_stop_128B : std_logic;
signal dsFC_stop_256B : std_logic;
signal dsFC_stop_512B : std_logic;
signal dsFC_stop_1024B : std_logic;
signal dsFC_stop_2048B : std_logic;
signal dsFC_stop_4096B : std_logic;
-- Reset
signal Local_Reset_i : std_logic;
signal Local_Reset_n_i : std_logic;
signal cfg_MRS : std_logic_vector(C_CFG_MRS_BIT_TOP-C_CFG_MRS_BIT_BOT downto 0);
-- Tag RAM port B write
signal tRAM_dinB_i : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
signal tRAM_AddrB_i : std_logic_vector(C_TAGRAM_AWIDTH-1 downto 0);
signal tRAM_weB_i : std_logic;
-- DMA calculation
component DMA_Calculate
port(
-- Downstream Registers from MWr Channel
DMA_PA : in std_logic_vector(C_DBUS_WIDTH-1 downto 0); -- EP (local)
DMA_HA : in std_logic_vector(C_DBUS_WIDTH-1 downto 0); -- Host (remote)
DMA_BDA : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_Length : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_Control : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Calculation in advance, for better timing
HA_is_64b : in std_logic;
BDA_is_64b : in std_logic;
-- Calculation in advance, for better timing
Leng_Hi19b_True : in std_logic;
Leng_Lo7b_True : in std_logic;
-- Parameters fed to DMA_FSM
DMA_PA_Loaded : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_PA_Var : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_HA_Var : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_BDA_fsm : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
BDA_is_64b_fsm : out std_logic;
-- Only for downstream channel
DMA_PA_Snout : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_BAR_Number : out std_logic_vector(C_TAGBAR_BIT_TOP-C_TAGBAR_BIT_BOT downto 0);
--
DMA_Snout_Length : out std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
DMA_Body_Length : out std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
DMA_Tail_Length : out std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0);
-- Engine control signals
DMA_Start : in std_logic;
DMA_Start2 : in std_logic; -- out of consecutive dex
-- Control signals to FSM
No_More_Bodies : out std_logic;
ThereIs_Snout : out std_logic;
ThereIs_Body : out std_logic;
ThereIs_Tail : out std_logic;
ThereIs_Dex : out std_logic;
HA64bit : out std_logic;
Addr_Inc : out std_logic;
-- FSM indicators
State_Is_LoadParam : in std_logic;
State_Is_Snout : in std_logic;
State_Is_Body : in std_logic;
-- State_Is_Tail : IN std_logic;
-- Additional
Param_Max_Cfg : in std_logic_vector(2 downto 0);
-- Common ports
dma_clk : in std_logic;
dma_reset : in std_logic
);
end component;
signal dsDMA_PA_Loaded : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal dsDMA_PA_Var : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal dsDMA_HA_Var : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal dsDMA_BDA_fsm : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal dsBDA_is_64b_fsm : std_logic;
signal dsDMA_PA_snout : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal dsDMA_BAR_Number : std_logic_vector(C_TAGBAR_BIT_TOP-C_TAGBAR_BIT_BOT downto 0);
signal dsDMA_Snout_Length : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
signal dsDMA_Body_Length : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
signal dsDMA_Tail_Length : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0);
signal dsNo_More_Bodies : std_logic;
signal dsThereIs_Snout : std_logic;
signal dsThereIs_Body : std_logic;
signal dsThereIs_Tail : std_logic;
signal dsThereIs_Dex : std_logic;
signal dsHA64bit : std_logic;
signal ds_AInc : std_logic;
-- DMA state machine
component DMA_FSM
port(
-- Fixed information for 1st header of TLP: MRd/MWr
TLP_Has_Payload : in std_logic;
TLP_Hdr_is_4DW : in std_logic;
DMA_Addr_Inc : in std_logic;
DMA_BAR_Number : in std_logic_vector(C_TAGBAR_BIT_TOP-C_TAGBAR_BIT_BOT downto 0);
-- FSM control signals
DMA_Start : in std_logic;
DMA_Start2 : in std_logic;
DMA_Stop : in std_logic;
DMA_Stop2 : in std_logic;
No_More_Bodies : in std_logic;
ThereIs_Snout : in std_logic;
ThereIs_Body : in std_logic;
ThereIs_Tail : in std_logic;
ThereIs_Dex : in std_logic;
-- Parameters to be written into ChBuf
DMA_PA_Loaded : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_PA_Var : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_HA_Var : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_BDA_fsm : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
BDA_is_64b_fsm : in std_logic;
DMA_Snout_Length : in std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
DMA_Body_Length : in std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
DMA_Tail_Length : in std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0);
-- Busy/Done conditions
Done_Condition_1 : in std_logic;
Done_Condition_2 : in std_logic;
Done_Condition_3 : in std_logic;
Done_Condition_4 : in std_logic;
Done_Condition_5 : in std_logic;
-- Channel buffer write
us_MWr_Param_Vec : in std_logic_vector(6-1 downto 0);
ChBuf_aFull : in std_logic;
ChBuf_WrEn : out std_logic;
ChBuf_WrDin : out std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
-- FSM indicators
State_Is_LoadParam : out std_logic;
State_Is_Snout : out std_logic;
State_Is_Body : out std_logic;
State_Is_Tail : out std_logic;
DMA_Cmd_Ack : out std_logic;
-- To Tx Port
ChBuf_ValidRd : in std_logic;
BDA_nAligned : out std_logic;
DMA_TimeOut : out std_logic;
DMA_Busy : out std_logic;
DMA_Done : out std_logic;
-- DMA_Done_Rise : OUT std_logic;
-- Tags
Pkt_Tag : in std_logic_vector(C_TAG_WIDTH-1 downto 0);
Dex_Tag : in std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- Common ports
dma_clk : in std_logic;
dma_reset : in std_logic
);
end component;
signal Tag_DMA_dsp : std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- FSM state indicators
signal dsState_Is_LoadParam : std_logic;
signal dsState_Is_Snout : std_logic;
signal dsState_Is_Body : std_logic;
signal dsState_Is_Tail : std_logic;
signal dsChBuf_ValidRd : std_logic;
signal dsBDA_nAligned : std_logic;
signal dsDMA_TimeOut_i : std_logic;
signal dsDMA_Busy_i : std_logic;
signal dsDMA_Done_i : std_logic;
signal DMA_Status_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
---------------------------------------------------------------
-- Done state identification uses 2^C_TAGRAM_AWIDTH bits, 2 stages logic
signal Tag_Map_Bits : std_logic_vector(C_TAG_MAP_WIDTH-1 downto 0);
signal Tag_Map_filling : std_logic_vector(C_SUB_TAG_MAP_WIDTH-1 downto 0);
signal All_CplD_have_come : std_logic;
-- Built-in single-port fifo as downstream DMA channel buffer
-- 128-bit wide, for 64-bit address
component sfifo_15x128
port (
clk : in std_logic;
rst : in std_logic;
prog_full : out std_logic;
-- wr_clk : IN std_logic;
wr_en : in std_logic;
din : in std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
full : out std_logic;
-- rd_clk : IN std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
prog_empty : out std_logic;
empty : out std_logic
);
end component;
-- Signal with DMA_downstream channel FIFO
signal MRd_dsp_din : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
signal MRd_dsp_dout : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
signal MRd_dsp_re_i : std_logic;
signal MRd_dsp_we : std_logic;
signal MRd_dsp_empty_i : std_logic;
signal MRd_dsp_full : std_logic;
signal MRd_dsp_prog_Full : std_logic;
signal MRd_dsp_prog_Full_r1 : std_logic;
signal MRd_dsp_re_r1 : std_logic;
signal MRd_dsp_empty_r1 : std_logic;
-- Request for output arbitration
signal MRd_dsp_Req_i : std_logic;
begin
-- DMA done signal
DMA_Done <= dsDMA_Done_i;
DMA_TimeOut <= dsDMA_TimeOut_i;
DMA_Busy <= dsDMA_Busy_i;
-- connecting FIFO's signals
MRd_dsp_Qout <= MRd_dsp_dout;
MRd_dsp_re_i <= MRd_dsp_RE;
MRd_dsp_Req <= MRd_dsp_Req_i;
-- tag RAM write request signals
tRAM_weB <= tRAM_weB_i;
tRAM_AddrB <= tRAM_AddrB_i;
tRAM_dinB <= tRAM_dinB_i;
-- positive local reset
Local_Reset_i <= dsDMA_Channel_Rst;
Local_Reset_n_i <= not(Local_Reset_i);
-- Max Read Request Size bits
cfg_MRS <= cfg_dcommand(C_CFG_MRS_BIT_TOP downto C_CFG_MRS_BIT_BOT);
-- Kernel Engine
ds_DMA_Calculation :
DMA_Calculate
port map(
DMA_PA => DMA_ds_PA ,
DMA_HA => DMA_ds_HA ,
DMA_BDA => DMA_ds_BDA ,
DMA_Length => DMA_ds_Length ,
DMA_Control => DMA_ds_Control ,
HA_is_64b => dsHA_is_64b ,
BDA_is_64b => dsBDA_is_64b ,
Leng_Hi19b_True => dsLeng_Hi19b_True ,
Leng_Lo7b_True => dsLeng_Lo7b_True ,
DMA_PA_Loaded => dsDMA_PA_Loaded ,
DMA_PA_Var => dsDMA_PA_Var ,
DMA_HA_Var => dsDMA_HA_Var ,
DMA_BDA_fsm => dsDMA_BDA_fsm ,
BDA_is_64b_fsm => dsBDA_is_64b_fsm ,
-- Only for downstream channel
DMA_PA_Snout => dsDMA_PA_snout ,
DMA_BAR_Number => dsDMA_BAR_Number ,
-- Lengths
DMA_Snout_Length => dsDMA_Snout_Length ,
DMA_Body_Length => dsDMA_Body_Length ,
DMA_Tail_Length => dsDMA_Tail_Length ,
-- Control signals to FSM
No_More_Bodies => dsNo_More_Bodies ,
ThereIs_Snout => dsThereIs_Snout ,
ThereIs_Body => dsThereIs_Body ,
ThereIs_Tail => dsThereIs_Tail ,
ThereIs_Dex => dsThereIs_Dex ,
HA64bit => dsHA64bit ,
Addr_Inc => ds_AInc ,
DMA_Start => dsDMA_Start ,
DMA_Start2 => dsDMA_Start2 ,
State_Is_LoadParam => dsState_Is_LoadParam ,
State_Is_Snout => dsState_Is_Snout ,
State_Is_Body => dsState_Is_Body ,
-- State_Is_Tail => dsState_Is_Tail ,
Param_Max_Cfg => cfg_MRS ,
dma_clk => user_clk ,
dma_reset => Local_Reset_i
);
-- Kernel FSM
ds_DMA_StateMachine :
DMA_FSM
port map(
TLP_Has_Payload => '0' ,
TLP_Hdr_is_4DW => dsHA64bit ,
DMA_Addr_Inc => '0' , -- of any value
DMA_BAR_Number => dsDMA_BAR_Number ,
DMA_Start => dsDMA_Start ,
DMA_Start2 => dsDMA_Start2 ,
DMA_Stop => dsDMA_Stop ,
DMA_Stop2 => dsDMA_Stop2 ,
-- Control signals to FSM
No_More_Bodies => dsNo_More_Bodies ,
ThereIs_Snout => dsThereIs_Snout ,
ThereIs_Body => dsThereIs_Body ,
ThereIs_Tail => dsThereIs_Tail ,
ThereIs_Dex => dsThereIs_Dex ,
DMA_PA_Loaded => dsDMA_PA_Loaded ,
DMA_PA_Var => dsDMA_PA_Var ,
DMA_HA_Var => dsDMA_HA_Var ,
DMA_BDA_fsm => dsDMA_BDA_fsm ,
BDA_is_64b_fsm => dsBDA_is_64b_fsm ,
DMA_Snout_Length => dsDMA_Snout_Length ,
DMA_Body_Length => dsDMA_Body_Length ,
DMA_Tail_Length => dsDMA_Tail_Length ,
ChBuf_ValidRd => dsChBuf_ValidRd,
BDA_nAligned => dsBDA_nAligned ,
DMA_TimeOut => dsDMA_TimeOut_i,
DMA_Busy => dsDMA_Busy_i ,
DMA_Done => dsDMA_Done_i ,
-- DMA_Done_Rise => open ,
Pkt_Tag => Tag_DMA_dsp ,
Dex_Tag => dsDMA_dex_Tag ,
Done_Condition_1 => '1' ,
Done_Condition_2 => MRd_dsp_empty_r1 ,
Done_Condition_3 => '1' ,
Done_Condition_4 => '1' ,
Done_Condition_5 => All_CplD_have_come ,
us_MWr_Param_Vec => "000000" ,
ChBuf_aFull => MRd_dsp_prog_Full_r1 ,
ChBuf_WrEn => MRd_dsp_we ,
ChBuf_WrDin => MRd_dsp_din ,
State_Is_LoadParam => dsState_Is_LoadParam ,
State_Is_Snout => dsState_Is_Snout ,
State_Is_Body => dsState_Is_Body ,
State_Is_Tail => dsState_Is_Tail ,
DMA_Cmd_Ack => DMA_Cmd_Ack ,
dma_clk => user_clk ,
dma_reset => Local_Reset_i
);
dsChBuf_ValidRd <= MRd_dsp_RE; -- MRd_dsp_re_i and not MRd_dsp_empty_i;
-- -------------------------------------------------
--
DMA_ds_Status <= DMA_Status_i;
--
-- Synchronous output: DMA_Status
--
DS_DMA_Status_Concat :
process (user_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
DMA_Status_i <= (others => '0');
elsif user_clk'event and user_clk = '1' then
DMA_Status_i <= (
CINT_BIT_DMA_STAT_NALIGN => dsBDA_nAligned,
CINT_BIT_DMA_STAT_TIMEOUT => dsDMA_TimeOut_i,
CINT_BIT_DMA_STAT_BDANULL => dsDMA_BDA_eq_Null,
CINT_BIT_DMA_STAT_BUSY => dsDMA_Busy_i,
CINT_BIT_DMA_STAT_DONE => dsDMA_Done_i,
others => '0'
);
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous reg: tRAM_weB
-- tRAM_AddrB
-- tRAM_dinB
--
FSM_dsDMA_tRAM_PortB :
process (user_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
tRAM_weB_i <= '0';
tRAM_AddrB_i <= (others => '1');
tRAM_dinB_i <= (others => '0');
elsif user_clk'event and user_clk = '1' then
tRAM_AddrB_i <= Tag_DMA_dsp(C_TAGRAM_AWIDTH-1 downto 0);
tRAM_weB_i <= dsState_Is_Snout
or dsState_Is_Body
or dsState_Is_Tail;
if dsState_Is_Snout = '1' then
tRAM_dinB_i <=
ds_AInc -- DMA_ds_Control(CINT_BIT_DMA_CTRL_AINC)
& dsDMA_BAR_Number -- (C_TAGBAR_BIT_TOP-C_TAGBAR_BIT_BOT downto 0)
& dsDMA_PA_snout(C_TAGBAR_BIT_BOT-1 downto 2)&"00";
elsif dsState_Is_Body = '1' then
tRAM_dinB_i <=
ds_AInc -- DMA_ds_Control(CINT_BIT_DMA_CTRL_AINC)
& dsDMA_BAR_Number -- (C_TAGBAR_BIT_TOP-C_TAGBAR_BIT_BOT downto 0)
& dsDMA_PA_Var(C_TAGBAR_BIT_BOT-1 downto 2) &"00";
elsif dsState_Is_Tail = '1' then
tRAM_dinB_i <=
ds_AInc -- DMA_ds_Control(CINT_BIT_DMA_CTRL_AINC)
& dsDMA_BAR_Number -- (C_TAGBAR_BIT_TOP-C_TAGBAR_BIT_BOT downto 0)
& dsDMA_PA_Var(C_TAGBAR_BIT_BOT-1 downto 2) &"00";
else
tRAM_dinB_i <= (others => '0');
end if;
end if;
end process;
-- ------------------------------------------
-- Loop: Tag_Map
--
Sync_Tag_set_reset_Bits :
process (user_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
Tag_Map_Bits <= (others => '0');
elsif user_clk'event and user_clk = '1' then
for j in 0 to C_TAG_MAP_WIDTH-1 loop
if tRAM_AddrB_i = CONV_STD_LOGIC_VECTOR(j, C_TAGRAM_AWIDTH) and tRAM_weB_i = '1' then
Tag_Map_Bits(j) <= '1';
elsif Tag_Map_Clear(j) = '1' then
Tag_Map_Bits(j) <= '0';
else
Tag_Map_Bits(j) <= Tag_Map_Bits(j);
end if;
end loop;
end if;
end process;
-- ------------------------------------------
-- Determination: All_CplD_have_come
--
Sync_Reg_All_CplD_have_come :
process (user_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
Tag_Map_filling <= (others => '0');
All_CplD_have_come <= '0';
elsif user_clk'event and user_clk = '1' then
for k in 0 to C_SUB_TAG_MAP_WIDTH-1 loop
if Tag_Map_Bits((C_TAG_MAP_WIDTH/C_SUB_TAG_MAP_WIDTH)*(k+1)-1 downto (C_TAG_MAP_WIDTH/C_SUB_TAG_MAP_WIDTH)*k)
= C_ALL_ZEROS((C_TAG_MAP_WIDTH/C_SUB_TAG_MAP_WIDTH)*(k+1)-1 downto (C_TAG_MAP_WIDTH/C_SUB_TAG_MAP_WIDTH)*k)
then
Tag_Map_filling(k) <= '1';
else
Tag_Map_filling(k) <= '0';
end if;
end loop;
-- final signal : All_CplD_have_come
if Tag_Map_filling = C_ALL_ONES(C_SUB_TAG_MAP_WIDTH-1 downto 0) then
All_CplD_have_come <= '1';
else
All_CplD_have_come <= '0';
end if;
end if;
end process;
-- ------------------------------------------
-- Synchronous Output: Tag_DMA_dsp
--
FSM_dsDMA_Tag_DMA_dsp :
process (user_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
Tag_DMA_dsp <= (others => '0');
elsif user_clk'event and user_clk = '1' then
if dsState_Is_Snout = '1'
or dsState_Is_Body = '1'
or dsState_Is_Tail = '1'
then
Tag_DMA_dsp <= '0' & dsDMA_BAR_Number(CINT_FIFO_SPACE_BAR/2)
& (Tag_DMA_dsp(C_TAGRAM_AWIDTH-1 downto 0)
+ CONV_STD_LOGIC_VECTOR(1, C_TAGRAM_AWIDTH));
else
Tag_DMA_dsp <= '0' & dsDMA_BAR_Number(CINT_FIFO_SPACE_BAR/2)
& Tag_DMA_dsp(C_TAGRAM_AWIDTH-1 downto 0);
end if;
end if;
end process;
-- -------------------------------------------------
-- ds MRd TLP Buffer
-- -------------------------------------------------
DMA_DSP_Buffer :
generic_sync_fifo
generic map (
g_data_width => 128,
g_size => 16,
g_show_ahead => false,
g_with_empty => true,
g_with_full => false,
g_with_almost_empty => true,
g_with_almost_full => true,
g_with_count => false,
g_almost_empty_threshold => 3,
g_almost_full_threshold => 13)
port map (
rst_n_i => Local_Reset_n_i,
clk_i => user_clk,
d_i => MRd_dsp_din,
we_i => MRd_dsp_we,
q_o => MRd_dsp_dout,
rd_i => MRd_dsp_re_i,
empty_o => MRd_dsp_empty_i,
full_o => MRd_dsp_full,
almost_empty_o => open,
almost_full_o => MRd_dsp_prog_Full,
count_o => open);
-- ---------------------------------------------
-- Delay of Empty and prog_Full
--
Synch_Delay_empty_and_full :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
MRd_dsp_re_r1 <= MRd_dsp_re_i;
MRd_dsp_empty_r1 <= MRd_dsp_empty_i;
MRd_dsp_prog_Full_r1 <= MRd_dsp_prog_Full;
MRd_dsp_Req_i <= not MRd_dsp_empty_i
and not dsDMA_Stop
and not dsDMA_Stop2
and not dsFC_stop;
end if;
end process;
-- ------------------------------------------
-- Synchronous: FC_push
--
Synch_Calc_FC_push :
process (user_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
FC_push <= '0';
elsif user_clk'event and user_clk = '1' then
FC_push <= MRd_dsp_re_r1 and not MRd_dsp_empty_r1
and not MRd_dsp_dout(C_CHBUF_TAG_BIT_TOP);
end if;
end process;
-- ------------------------------------------
-- Synchronous: FC_counter
--
Synch_Calc_FC_counter :
process (user_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
FC_counter <= (others => '0');
elsif user_clk'event and user_clk = '1' then
if FC_push = '1' and FC_pop = '0' then
FC_counter <= FC_counter + '1';
elsif FC_push = '0' and FC_pop = '1' then
FC_counter <= FC_counter - '1';
else
FC_counter <= FC_counter;
end if;
end if;
end process;
-- ------------------------------------------
-- Synchronous: dsFC_stop
--
Synch_Calc_dsFC_stop :
process (user_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
dsFC_stop_128B <= '1';
dsFC_stop_256B <= '1';
dsFC_stop_512B <= '1';
dsFC_stop_1024B <= '1';
dsFC_stop_2048B <= '1';
dsFC_stop_4096B <= '1';
elsif user_clk'event and user_clk = '1' then
if FC_counter(C_TAGRAM_AWIDTH-1 downto 0) /= C_ALL_ZEROS(C_TAGRAM_AWIDTH-1 downto 0) then
dsFC_stop_4096B <= '1';
else
dsFC_stop_4096B <= '0';
end if;
if FC_counter(C_TAGRAM_AWIDTH-1 downto 0) /= C_ALL_ZEROS(C_TAGRAM_AWIDTH-1 downto 0) then
dsFC_stop_2048B <= '1';
else
dsFC_stop_2048B <= '0';
end if;
if FC_counter(C_TAGRAM_AWIDTH-1 downto 1) /= C_ALL_ZEROS(C_TAGRAM_AWIDTH-1 downto 1) then
dsFC_stop_1024B <= '1';
else
dsFC_stop_1024B <= '0';
end if;
if FC_counter(C_TAGRAM_AWIDTH-1 downto 2) /= C_ALL_ZEROS(C_TAGRAM_AWIDTH-1 downto 2) then
dsFC_stop_512B <= '1';
else
dsFC_stop_512B <= '0';
end if;
if FC_counter(C_TAGRAM_AWIDTH-1 downto 3) /= C_ALL_ZEROS(C_TAGRAM_AWIDTH-1 downto 3) then
dsFC_stop_256B <= '1';
else
dsFC_stop_256B <= '0';
end if;
if FC_counter(C_TAGRAM_AWIDTH-1 downto 4) /= C_ALL_ZEROS(C_TAGRAM_AWIDTH-1 downto 4) then
dsFC_stop_128B <= '1';
else
dsFC_stop_128B <= '0';
end if;
end if;
end process;
-- ------------------------------------------
-- Configuration pamameters: cfg_MRS
--
Syn_Config_Param_cfg_MRS :
process (user_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then -- 0x0080 Bytes
dsFC_stop <= '1';
elsif user_clk'event and user_clk = '1' then
case cfg_MRS is
when "000" => -- 0x0080 Bytes
dsFC_stop <= dsFC_stop_128B;
when "001" => -- 0x0100 Bytes
dsFC_stop <= dsFC_stop_256B;
when "010" => -- 0x0200 Bytes
dsFC_stop <= dsFC_stop_512B;
when "011" => -- 0x0400 Bytes
dsFC_stop <= dsFC_stop_1024B;
when "100" => -- 0x0800 Bytes
dsFC_stop <= dsFC_stop_2048B;
when "101" => -- 0x1000 Bytes
dsFC_stop <= dsFC_stop_4096B;
when others => -- as 0x0080 Bytes
dsFC_stop <= dsFC_stop_128B;
end case;
end if;
end process;
end architecture Behavioral;
|
--
-- Project: Aurora Module Generator version 2.4
--
-- Date: $Date: 2005/11/16 00:32:43 $
-- Tag: $Name: i+IP+98818 $
-- File: $RCSfile: global_logic_vhd.ejava,v $
-- Rev: $Revision: 1.1.2.5 $
--
-- Company: Xilinx
-- Contributors: R. K. Awalt, B. L. Woodard, N. Gulstone
--
-- Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
-- INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
-- PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-- ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-- APPLICATION OR STANDARD, XILINX IS MAKING NO
-- REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-- FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
-- RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
-- REQUIRE FOR YOUR IMPLEMENTATION. XILINX
-- EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
-- RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
-- INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-- FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
-- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE.
--
-- (c) Copyright 2004 Xilinx, Inc.
-- All rights reserved.
--
--
-- GLOBAL_LOGIC
--
-- Author: Nigel Gulstone
-- Xilinx - Embedded Networking System Engineering Group
--
-- VHDL Translation: Brian Woodard
-- Xilinx - Garden Valley Design Team
--
-- Description: The GLOBAL_LOGIC module handles channel bonding, channel
-- verification, channel error manangement and idle generation.
--
-- This module supports 1 2-byte lane designs
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity GLOBAL_LOGIC is
generic (
EXTEND_WATCHDOGS : boolean := FALSE
);
port (
-- MGT Interface
CH_BOND_DONE : in std_logic;
EN_CHAN_SYNC : out std_logic;
-- Aurora Lane Interface
LANE_UP : in std_logic;
SOFT_ERROR : in std_logic;
HARD_ERROR : in std_logic;
CHANNEL_BOND_LOAD : in std_logic;
GOT_A : in std_logic_vector(0 to 1);
GOT_V : in std_logic;
GEN_A : out std_logic;
GEN_K : out std_logic_vector(0 to 1);
GEN_R : out std_logic_vector(0 to 1);
GEN_V : out std_logic_vector(0 to 1);
RESET_LANES : out std_logic;
-- System Interface
USER_CLK : in std_logic;
RESET : in std_logic;
POWER_DOWN : in std_logic;
CHANNEL_UP : out std_logic;
START_RX : out std_logic;
CHANNEL_SOFT_ERROR : out std_logic;
CHANNEL_HARD_ERROR : out std_logic
);
end GLOBAL_LOGIC;
architecture MAPPED of GLOBAL_LOGIC is
-- External Register Declarations --
signal EN_CHAN_SYNC_Buffer : std_logic;
signal GEN_A_Buffer : std_logic;
signal GEN_K_Buffer : std_logic_vector(0 to 1);
signal GEN_R_Buffer : std_logic_vector(0 to 1);
signal GEN_V_Buffer : std_logic_vector(0 to 1);
signal RESET_LANES_Buffer : std_logic;
signal CHANNEL_UP_Buffer : std_logic;
signal START_RX_Buffer : std_logic;
signal CHANNEL_SOFT_ERROR_Buffer : std_logic;
signal CHANNEL_HARD_ERROR_Buffer : std_logic;
-- Wire Declarations --
signal gen_ver_i : std_logic;
signal reset_channel_i : std_logic;
signal did_ver_i : std_logic;
-- Component Declarations --
component CHANNEL_INIT_SM
generic (
EXTEND_WATCHDOGS : boolean := FALSE
);
port (
-- MGT Interface
CH_BOND_DONE : in std_logic;
EN_CHAN_SYNC : out std_logic;
-- Aurora Lane Interface
CHANNEL_BOND_LOAD : in std_logic;
GOT_A : in std_logic_vector(0 to 1);
GOT_V : in std_logic;
RESET_LANES : out std_logic;
-- System Interface
USER_CLK : in std_logic;
RESET : in std_logic;
CHANNEL_UP : out std_logic;
START_RX : out std_logic;
-- Idle and Verification Sequence Generator Interface
DID_VER : in std_logic;
GEN_VER : out std_logic;
-- Channel Init State Machine Interface
RESET_CHANNEL : in std_logic
);
end component;
component IDLE_AND_VER_GEN
port (
-- Channel Init SM Interface
GEN_VER : in std_logic;
DID_VER : out std_logic;
-- Aurora Lane Interface
GEN_A : out std_logic;
GEN_K : out std_logic_vector(0 to 1);
GEN_R : out std_logic_vector(0 to 1);
GEN_V : out std_logic_vector(0 to 1);
-- System Interface
RESET : in std_logic;
USER_CLK : in std_logic
);
end component;
component CHANNEL_ERROR_DETECT
port (
-- Aurora Lane Interface
SOFT_ERROR : in std_logic;
HARD_ERROR : in std_logic;
LANE_UP : in std_logic;
-- System Interface
USER_CLK : in std_logic;
POWER_DOWN : in std_logic;
CHANNEL_SOFT_ERROR : out std_logic;
CHANNEL_HARD_ERROR : out std_logic;
-- Channel Init SM Interface
RESET_CHANNEL : out std_logic
);
end component;
begin
EN_CHAN_SYNC <= EN_CHAN_SYNC_Buffer;
GEN_A <= GEN_A_Buffer;
GEN_K <= GEN_K_Buffer;
GEN_R <= GEN_R_Buffer;
GEN_V <= GEN_V_Buffer;
RESET_LANES <= RESET_LANES_Buffer;
CHANNEL_UP <= CHANNEL_UP_Buffer;
START_RX <= START_RX_Buffer;
CHANNEL_SOFT_ERROR <= CHANNEL_SOFT_ERROR_Buffer;
CHANNEL_HARD_ERROR <= CHANNEL_HARD_ERROR_Buffer;
-- Main Body of Code --
-- State Machine for channel bonding and verification.
channel_init_sm_i : CHANNEL_INIT_SM
generic map (
EXTEND_WATCHDOGS => EXTEND_WATCHDOGS
)
port map (
-- MGT Interface
CH_BOND_DONE => CH_BOND_DONE,
EN_CHAN_SYNC => EN_CHAN_SYNC_Buffer,
-- Aurora Lane Interface
CHANNEL_BOND_LOAD => CHANNEL_BOND_LOAD,
GOT_A => GOT_A,
GOT_V => GOT_V,
RESET_LANES => RESET_LANES_Buffer,
-- System Interface
USER_CLK => USER_CLK,
RESET => RESET,
START_RX => START_RX_Buffer,
CHANNEL_UP => CHANNEL_UP_Buffer,
-- Idle and Verification Sequence Generator Interface
DID_VER => did_ver_i,
GEN_VER => gen_ver_i,
-- Channel Error Management Module Interface
RESET_CHANNEL => reset_channel_i
);
-- Idle and verification sequence generator module.
idle_and_ver_gen_i : IDLE_AND_VER_GEN
port map (
-- Channel Init SM Interface
GEN_VER => gen_ver_i,
DID_VER => did_ver_i,
-- Aurora Lane Interface
GEN_A => GEN_A_Buffer,
GEN_K => GEN_K_Buffer,
GEN_R => GEN_R_Buffer,
GEN_V => GEN_V_Buffer,
-- System Interface
RESET => RESET,
USER_CLK => USER_CLK
);
-- Channel Error Management module.
channel_error_detect_i : CHANNEL_ERROR_DETECT
port map (
-- Aurora Lane Interface
SOFT_ERROR => SOFT_ERROR,
HARD_ERROR => HARD_ERROR,
LANE_UP => LANE_UP,
-- System Interface
USER_CLK => USER_CLK,
POWER_DOWN => POWER_DOWN,
CHANNEL_SOFT_ERROR => CHANNEL_SOFT_ERROR_Buffer,
CHANNEL_HARD_ERROR => CHANNEL_HARD_ERROR_Buffer,
-- Channel Init State Machine Interface
RESET_CHANNEL => reset_channel_i
);
end MAPPED;
|
--
-- Project: Aurora Module Generator version 2.4
--
-- Date: $Date: 2005/11/16 00:32:43 $
-- Tag: $Name: i+IP+98818 $
-- File: $RCSfile: global_logic_vhd.ejava,v $
-- Rev: $Revision: 1.1.2.5 $
--
-- Company: Xilinx
-- Contributors: R. K. Awalt, B. L. Woodard, N. Gulstone
--
-- Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
-- INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
-- PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-- ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-- APPLICATION OR STANDARD, XILINX IS MAKING NO
-- REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-- FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
-- RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
-- REQUIRE FOR YOUR IMPLEMENTATION. XILINX
-- EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
-- RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
-- INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-- FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
-- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE.
--
-- (c) Copyright 2004 Xilinx, Inc.
-- All rights reserved.
--
--
-- GLOBAL_LOGIC
--
-- Author: Nigel Gulstone
-- Xilinx - Embedded Networking System Engineering Group
--
-- VHDL Translation: Brian Woodard
-- Xilinx - Garden Valley Design Team
--
-- Description: The GLOBAL_LOGIC module handles channel bonding, channel
-- verification, channel error manangement and idle generation.
--
-- This module supports 1 2-byte lane designs
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity GLOBAL_LOGIC is
generic (
EXTEND_WATCHDOGS : boolean := FALSE
);
port (
-- MGT Interface
CH_BOND_DONE : in std_logic;
EN_CHAN_SYNC : out std_logic;
-- Aurora Lane Interface
LANE_UP : in std_logic;
SOFT_ERROR : in std_logic;
HARD_ERROR : in std_logic;
CHANNEL_BOND_LOAD : in std_logic;
GOT_A : in std_logic_vector(0 to 1);
GOT_V : in std_logic;
GEN_A : out std_logic;
GEN_K : out std_logic_vector(0 to 1);
GEN_R : out std_logic_vector(0 to 1);
GEN_V : out std_logic_vector(0 to 1);
RESET_LANES : out std_logic;
-- System Interface
USER_CLK : in std_logic;
RESET : in std_logic;
POWER_DOWN : in std_logic;
CHANNEL_UP : out std_logic;
START_RX : out std_logic;
CHANNEL_SOFT_ERROR : out std_logic;
CHANNEL_HARD_ERROR : out std_logic
);
end GLOBAL_LOGIC;
architecture MAPPED of GLOBAL_LOGIC is
-- External Register Declarations --
signal EN_CHAN_SYNC_Buffer : std_logic;
signal GEN_A_Buffer : std_logic;
signal GEN_K_Buffer : std_logic_vector(0 to 1);
signal GEN_R_Buffer : std_logic_vector(0 to 1);
signal GEN_V_Buffer : std_logic_vector(0 to 1);
signal RESET_LANES_Buffer : std_logic;
signal CHANNEL_UP_Buffer : std_logic;
signal START_RX_Buffer : std_logic;
signal CHANNEL_SOFT_ERROR_Buffer : std_logic;
signal CHANNEL_HARD_ERROR_Buffer : std_logic;
-- Wire Declarations --
signal gen_ver_i : std_logic;
signal reset_channel_i : std_logic;
signal did_ver_i : std_logic;
-- Component Declarations --
component CHANNEL_INIT_SM
generic (
EXTEND_WATCHDOGS : boolean := FALSE
);
port (
-- MGT Interface
CH_BOND_DONE : in std_logic;
EN_CHAN_SYNC : out std_logic;
-- Aurora Lane Interface
CHANNEL_BOND_LOAD : in std_logic;
GOT_A : in std_logic_vector(0 to 1);
GOT_V : in std_logic;
RESET_LANES : out std_logic;
-- System Interface
USER_CLK : in std_logic;
RESET : in std_logic;
CHANNEL_UP : out std_logic;
START_RX : out std_logic;
-- Idle and Verification Sequence Generator Interface
DID_VER : in std_logic;
GEN_VER : out std_logic;
-- Channel Init State Machine Interface
RESET_CHANNEL : in std_logic
);
end component;
component IDLE_AND_VER_GEN
port (
-- Channel Init SM Interface
GEN_VER : in std_logic;
DID_VER : out std_logic;
-- Aurora Lane Interface
GEN_A : out std_logic;
GEN_K : out std_logic_vector(0 to 1);
GEN_R : out std_logic_vector(0 to 1);
GEN_V : out std_logic_vector(0 to 1);
-- System Interface
RESET : in std_logic;
USER_CLK : in std_logic
);
end component;
component CHANNEL_ERROR_DETECT
port (
-- Aurora Lane Interface
SOFT_ERROR : in std_logic;
HARD_ERROR : in std_logic;
LANE_UP : in std_logic;
-- System Interface
USER_CLK : in std_logic;
POWER_DOWN : in std_logic;
CHANNEL_SOFT_ERROR : out std_logic;
CHANNEL_HARD_ERROR : out std_logic;
-- Channel Init SM Interface
RESET_CHANNEL : out std_logic
);
end component;
begin
EN_CHAN_SYNC <= EN_CHAN_SYNC_Buffer;
GEN_A <= GEN_A_Buffer;
GEN_K <= GEN_K_Buffer;
GEN_R <= GEN_R_Buffer;
GEN_V <= GEN_V_Buffer;
RESET_LANES <= RESET_LANES_Buffer;
CHANNEL_UP <= CHANNEL_UP_Buffer;
START_RX <= START_RX_Buffer;
CHANNEL_SOFT_ERROR <= CHANNEL_SOFT_ERROR_Buffer;
CHANNEL_HARD_ERROR <= CHANNEL_HARD_ERROR_Buffer;
-- Main Body of Code --
-- State Machine for channel bonding and verification.
channel_init_sm_i : CHANNEL_INIT_SM
generic map (
EXTEND_WATCHDOGS => EXTEND_WATCHDOGS
)
port map (
-- MGT Interface
CH_BOND_DONE => CH_BOND_DONE,
EN_CHAN_SYNC => EN_CHAN_SYNC_Buffer,
-- Aurora Lane Interface
CHANNEL_BOND_LOAD => CHANNEL_BOND_LOAD,
GOT_A => GOT_A,
GOT_V => GOT_V,
RESET_LANES => RESET_LANES_Buffer,
-- System Interface
USER_CLK => USER_CLK,
RESET => RESET,
START_RX => START_RX_Buffer,
CHANNEL_UP => CHANNEL_UP_Buffer,
-- Idle and Verification Sequence Generator Interface
DID_VER => did_ver_i,
GEN_VER => gen_ver_i,
-- Channel Error Management Module Interface
RESET_CHANNEL => reset_channel_i
);
-- Idle and verification sequence generator module.
idle_and_ver_gen_i : IDLE_AND_VER_GEN
port map (
-- Channel Init SM Interface
GEN_VER => gen_ver_i,
DID_VER => did_ver_i,
-- Aurora Lane Interface
GEN_A => GEN_A_Buffer,
GEN_K => GEN_K_Buffer,
GEN_R => GEN_R_Buffer,
GEN_V => GEN_V_Buffer,
-- System Interface
RESET => RESET,
USER_CLK => USER_CLK
);
-- Channel Error Management module.
channel_error_detect_i : CHANNEL_ERROR_DETECT
port map (
-- Aurora Lane Interface
SOFT_ERROR => SOFT_ERROR,
HARD_ERROR => HARD_ERROR,
LANE_UP => LANE_UP,
-- System Interface
USER_CLK => USER_CLK,
POWER_DOWN => POWER_DOWN,
CHANNEL_SOFT_ERROR => CHANNEL_SOFT_ERROR_Buffer,
CHANNEL_HARD_ERROR => CHANNEL_HARD_ERROR_Buffer,
-- Channel Init State Machine Interface
RESET_CHANNEL => reset_channel_i
);
end MAPPED;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity memory_matrix is
generic(ROWS: integer := 350; COLUMNS: integer := 350; CLK_DELAY_COUNT: integer := 9);
port(
x_write: in std_logic_vector(9 downto 0) := (others => '0');
y_write: in std_logic_vector(9 downto 0) := (others => '0');
write_data: in std_logic_vector(0 downto 0) := (others => '0');
write_enable: in std_logic := '0';
clk: in std_logic := '0';
enable: in std_logic := '0';
reset: in std_logic := '0';
x_read: in std_logic_vector(9 downto 0) := (others => '0');
y_read: in std_logic_vector(9 downto 0) := (others => '0');
read_data : out std_logic_vector(0 downto 0) := (others => '0')
);
end memory_matrix;
architecture memory_matrix_arq of memory_matrix is
constant MAX_ROWS : integer := 350;
constant MAX_COLUMNS : integer := 350;
constant RAM_SIZE : integer := 16384;
constant RAM_SIZE_1 : integer := 2 * RAM_SIZE;
constant RAM_SIZE_2 : integer := 3 * RAM_SIZE;
constant RAM_SIZE_3 : integer := 4 * RAM_SIZE;
constant RAM_SIZE_4 : integer := 5 * RAM_SIZE;
constant RAM_SIZE_5 : integer := 6 * RAM_SIZE;
constant RAM_SIZE_6 : integer := 7 * RAM_SIZE;
constant RAM_SIZE_7 : integer := 8 * RAM_SIZE;
constant default_ram_mask : unsigned(7 downto 0) := "00000001";
signal write_address : std_logic_vector(13 downto 0) := (others => '0');
signal read_address : std_logic_vector(13 downto 0) := (others => '0');
signal ram_write_mask : std_logic_vector(7 downto 0) := (others => '0');
signal ram_read_mask : std_logic_vector(7 downto 0) := (others => '0');
signal data : std_logic_vector(0 downto 0) := (others => '0');
signal rb : integer := 0;
component dual_port_ram is
port (
data_in : in std_logic_vector (0 downto 0) := (others => '0');
write_address : in std_logic_vector (13 downto 0) := (others => '0');
write_enable : in std_logic := '0';
ram_write_mask : in std_logic_vector(7 downto 0) := (others => '0');
enable : in std_logic := '0';
clk : in std_logic := '0';
reset : in std_logic := '0';
ram_read_mask : in std_logic_vector(7 downto 0) := (others => '0');
read_address : in std_logic_vector(13 downto 0) := (others => '0');
data_out : out std_logic_vector (0 downto 0) := (others => '0')
);
end component;
begin
dual_port_ram_0 : dual_port_ram
port map(
data_in => write_data,
write_address => write_address,
write_enable => write_enable,
ram_write_mask => ram_write_mask,
enable => enable,
reset => reset,
clk => clk,
ram_read_mask => ram_read_mask,
read_address => read_address,
data_out => data
);
write_process : process(enable, reset, write_enable, write_data, x_write, y_write)
variable x_write_int : integer := 0;
variable y_write_int : integer := 0;
variable tmp_write_ram : integer := 0;
variable write_bit_position : integer := 0;
variable write_pos_in_ram : integer := 0;
begin
x_write_int := to_integer(unsigned(x_write));
y_write_int := to_integer(unsigned(y_write));
--report "MATRIX-W " & integer'image(x_write_int) & " : " & integer'image(y_write_int) & "=>" & std_logic'image(write_data(0));
if(x_write_int <= COLUMNS and y_write_int <= ROWS) then
write_bit_position := x_write_int + y_write_int * ROWS;
case (write_bit_position) is
when 0 to RAM_SIZE-1 => tmp_write_ram := 0;
when RAM_SIZE to RAM_SIZE_1-1 => tmp_write_ram := 1;
when RAM_SIZE_1 to RAM_SIZE_2-1 => tmp_write_ram := 2;
when RAM_SIZE_2 to RAM_SIZE_3-1 => tmp_write_ram := 3;
when RAM_SIZE_3 to RAM_SIZE_4-1 => tmp_write_ram := 4;
when RAM_SIZE_4 to RAM_SIZE_5-1 => tmp_write_ram := 5;
when RAM_SIZE_5 to RAM_SIZE_6-1 => tmp_write_ram := 6;
when RAM_SIZE_6 to RAM_SIZE_7-1 => tmp_write_ram := 7;
when others => tmp_write_ram := 0;
end case;
write_pos_in_ram := write_bit_position - (tmp_write_ram * RAM_SIZE);
write_address <= std_logic_vector(to_unsigned(write_pos_in_ram, 14));
ram_write_mask <= std_logic_vector(shift_left(default_ram_mask, tmp_write_ram));
end if;
end process;
read_process : process(enable, reset, x_read, y_read, data)
variable x_read_int : integer := 0;
variable y_read_int : integer := 0;
variable tmp_read_ram : integer := 0;
variable read_bit_position : integer := 0;
variable read_pos_in_ram : integer := 0;
begin
x_read_int := to_integer(unsigned(x_read));
y_read_int := to_integer(unsigned(y_read));
--if(data(0) = '1') then
-- report "MATRIX-R " & integer'image(x_read_int) & " : " & integer'image(y_read_int) & "=>" & std_logic'image(data(0));
--end if;
if(ROWS > MAX_ROWS) then
report "MAX ROWS is: " & integer'image(MAX_ROWS) severity failure;
end if;
if(COLUMNS > MAX_COLUMNS) then
report "MAX COLUMNS is: " & integer'image(MAX_COLUMNS) severity failure;
end if;
if(x_read_int >= COLUMNS or y_read_int >= ROWS) then
read_data <= "0";
else
read_bit_position := x_read_int + y_read_int * COLUMNS;
rb <= read_bit_position;
case (read_bit_position) is
when 0 to RAM_SIZE-1 => tmp_read_ram := 0;
when RAM_SIZE to RAM_SIZE_1-1 => tmp_read_ram := 1;
when RAM_SIZE_1 to RAM_SIZE_2-1 => tmp_read_ram := 2;
when RAM_SIZE_2 to RAM_SIZE_3-1 => tmp_read_ram := 3;
when RAM_SIZE_3 to RAM_SIZE_4-1 => tmp_read_ram := 4;
when RAM_SIZE_4 to RAM_SIZE_5-1 => tmp_read_ram := 5;
when RAM_SIZE_5 to RAM_SIZE_6-1 => tmp_read_ram := 6;
when RAM_SIZE_6 to RAM_SIZE_7-1 => tmp_read_ram := 7;
when others => tmp_read_ram := 0;
end case;
read_pos_in_ram := read_bit_position - (tmp_read_ram * RAM_SIZE);
read_address <= std_logic_vector(to_unsigned(read_pos_in_ram, 14));
ram_read_mask <= std_logic_vector(shift_left(default_ram_mask, tmp_read_ram));
read_data <= data;
end if;
end process;
end architecture; |
LIBRARY ieee;
use IEEE.std_logic_1164.all;
use work.iface.all;
use work.amba.all;
package ddmlib is
component ddm
port (
rst : in std_logic;
clk : in clk_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ddmi : in ddm_in_type;
ddmo : out ddm_out_type
);
end component;
end;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
------------------------------------------------------------
-- This file is automatically generated!
-- Here are the parameters:
-- network size x: 2
-- network size y: 2
-- Data width: 32
-- Parity: False
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE ieee.numeric_std.ALL;
use work.component_pack.all;
entity network_2x2_with_PE is
generic (DATA_WIDTH: integer := 32;
DATA_WIDTH_LV: integer := 11;
memory_type : string :=
"TRI_PORT_X"
-- "DUAL_PORT_"
-- "ALTERA_LPM"
-- "XILINX_16X"
);
port (reset: in std_logic;
clk: in std_logic;
-- IJTAG network for fault injection and checker status monitoring
TCK : in std_logic;
RST : in std_logic;
SEL : in std_logic;
SI : in std_logic;
SE : in std_logic;
UE : in std_logic;
CE : in std_logic;
SO : out std_logic;
toF : out std_logic;
toC : out std_logic;
-- GPIO for Node 0
GPIO_out: out std_logic_vector(15 downto 0);
GPIO_in: in std_logic_vector(21 downto 0);
-- UART for all Plasmas
uart_write_0 : out std_logic;
uart_read_0 : in std_logic;
uart_write_1 : out std_logic;
uart_read_1 : in std_logic;
uart_write_2 : out std_logic;
uart_read_2 : in std_logic;
uart_write_3 : out std_logic;
uart_read_3 : in std_logic;
-- Monitor connections
temperature_control : out std_logic_vector(2 downto 0);
iddt_control : out std_logic_vector(2 downto 0);
slack_control : out std_logic_vector(2 downto 0);
slack_data : in std_logic_vector(31 downto 0);
voltage_control : out std_logic_vector(2 downto 0);
voltage_data : in std_logic_vector(31 downto 0)
);
end network_2x2_with_PE;
architecture behavior of network_2x2_with_PE is
constant RAMDataSize : positive := 32;
constant RAMAddrSize : positive := 12;
constant path : string(1 to 12) := "Testbenches/"; --uncomment this if you are SIMULATING in MODELSIM, or if you're synthesizing.
-- constant path : string(positive range <>) := "/home/tsotne/ownCloud/git/Bonfire_sim/Bonfire/RTL/Chip_Designs/IMMORTAL_Chip_2017/Testbenches/"; --used only for Vivado similation. Tsotnes PC.
component immortal_sensor_IJTAG_interface is
Port ( -- Scan Interface client --------------
TCK : in std_logic;
RST : in std_logic;
SEL : in std_logic;
SI : in std_logic;
SE : in std_logic;
UE : in std_logic;
CE : in std_logic;
SO : out std_logic;
toF : out std_logic;
toC : out std_logic;
-- Monitor connections
temperature_control : out std_logic_vector(2 downto 0);
temperature_data : in std_logic_vector(12 downto 0);
iddt_control : out std_logic_vector(2 downto 0);
iddt_data : in std_logic_vector(12 downto 0);
slack_control : out std_logic_vector(2 downto 0);
slack_data : in std_logic_vector(31 downto 0);
voltage_control : out std_logic_vector(2 downto 0);
voltage_data : in std_logic_vector(31 downto 0));
end component;
component SIB_mux_pre_FCX_SELgate is
Port ( -- Scan Interface client --------------
SI : in STD_LOGIC; -- ScanInPort
CE : in STD_LOGIC; -- CaptureEnPort
SE : in STD_LOGIC; -- ShiftEnPort
UE : in STD_LOGIC; -- UpdateEnPort
SEL : in STD_LOGIC; -- SelectPort
RST : in STD_LOGIC; -- ResetPort
TCK : in STD_LOGIC; -- TCKPort
SO : out STD_LOGIC; -- ScanOutPort
toF : out STD_LOGIC; -- To F flag of the upper hierarchical level
toC : out STD_LOGIC; -- To C flag of the upper hierarchical level
-- Scan Interface host ----------------
fromSO : in STD_LOGIC; -- ScanInPort
toCE : out STD_LOGIC; -- ToCaptureEnPort
toSE : out STD_LOGIC; -- ToShiftEnPort
toUE : out STD_LOGIC; -- ToUpdateEnPort
toSEL : out STD_LOGIC; -- ToSelectPort
toRST : out STD_LOGIC; -- ToResetPort
toTCK : out STD_LOGIC; -- ToTCKPort
toSI : out STD_LOGIC; -- ScanOutPort
fromF : in STD_LOGIC; -- From an OR of all F flags in the underlying network segment
fromC : in STD_LOGIC); -- From an AND of all C flags in the underlying network segment
end component;
component RAMAccessInstrument is
Generic ( DataSize : positive := 8;
AddressSize : positive := 8);
Port ( -- Scan Interface scan_client ----------
SI : in std_logic; -- ScanInPort
SO : out std_logic; -- ScanOutPort
SEL : in std_logic; -- SelectPort
----------------------------------------
SE : in std_logic; -- ShiftEnPort
CE : in std_logic; -- CaptureEnPort
UE : in std_logic; -- UpdateEnPort
RST : in std_logic; -- ResetPort
TCK : in std_logic; -- TCKPort
MEM_SIB_SEL : out std_logic;
-- RAM interface
RAM_data_read : in std_logic_vector (DataSize-1 downto 0);
RAM_data_write : out std_logic_vector (DataSize-1 downto 0);
RAM_address_out : out std_logic_vector (AddressSize-1 downto 0);
RAM_write_enable : out std_logic);
end component;
-- Monitor signals
signal temperature_data : std_logic_vector(12 downto 0);
signal iddt_data : std_logic_vector(12 downto 0);
-- Declaring network component
-- Declaring NoC_Node component (with Plasma, RAM, NI and UART)
-- generating bulk signals...
signal RX_L_0, TX_L_0: std_logic_vector (31 downto 0);
signal credit_counter_out_0: std_logic_vector (1 downto 0);
signal credit_out_L_0, credit_in_L_0, valid_in_L_0, valid_out_L_0: std_logic;
signal RX_L_1, TX_L_1: std_logic_vector (31 downto 0);
signal credit_counter_out_1: std_logic_vector (1 downto 0);
signal credit_out_L_1, credit_in_L_1, valid_in_L_1, valid_out_L_1: std_logic;
signal RX_L_2, TX_L_2: std_logic_vector (31 downto 0);
signal credit_counter_out_2: std_logic_vector (1 downto 0);
signal credit_out_L_2, credit_in_L_2, valid_in_L_2, valid_out_L_2: std_logic;
signal RX_L_3, TX_L_3: std_logic_vector (31 downto 0);
signal credit_counter_out_3: std_logic_vector (1 downto 0);
signal credit_out_L_3, credit_in_L_3, valid_in_L_3, valid_out_L_3: std_logic;
-- NI testing signals
--------------
--signal Rxy_reconf: std_logic_vector (7 downto 0) := "01111101";
--signal Reconfig: std_logic := '0';
--------------
signal not_reset: std_logic;
signal link_faults_0, link_faults_1, link_faults_2, link_faults_3 : std_logic_vector(4 downto 0);
signal turn_faults_0, turn_faults_1, turn_faults_2, turn_faults_3 : std_logic_vector(19 downto 0);
signal Rxy_reconf_PE_0, Rxy_reconf_PE_1,Rxy_reconf_PE_2, Rxy_reconf_PE_3 : std_logic_vector(7 downto 0);
signal Cx_reconf_PE_0, Cx_reconf_PE_1, Cx_reconf_PE_2, Cx_reconf_PE_3 : std_logic_vector(3 downto 0);
signal Reconfig_command_0, Reconfig_command_1, Reconfig_command_2, Reconfig_command_3 : std_logic;
signal GPIO_out_FF_in, GPIO_out_FF : std_logic_vector(15 downto 0);
signal UART_0_W_in, UART_0_W_out, UART_0_R_in, UART_0_R_out : std_logic;
signal UART_1_W_in, UART_1_W_out, UART_1_R_in, UART_1_R_out : std_logic;
signal UART_2_W_in, UART_2_W_out, UART_2_R_in, UART_2_R_out : std_logic;
signal UART_3_W_in, UART_3_W_out, UART_3_R_in, UART_3_R_out : std_logic;
-- IJTAG-related signals
signal SO_NoC , SO_sensors , SO_RAM : std_logic;
signal toF_NoC, toF_sensors, toF_RAM : std_logic;
signal toC_NoC, toC_sensors, toC_RAM : std_logic;
signal SIB_RAM_toSI, SIB_RAM_toTCK, SIB_RAM_toRST, SIB_RAM_toSEL, SIB_RAM_toUE, SIB_RAM_toSE, SIB_RAM_toCE : std_logic;
signal RAM0_SO, RAM1_SO, RAM2_SO, RAM3_SO : std_logic;
signal RAM0_write_enable, RAM1_write_enable, RAM2_write_enable, RAM3_write_enable : std_logic;
signal RAM0_address, RAM1_address, RAM2_address, RAM3_address : std_logic_vector(RAMAddrSize-1 downto 0);
signal IJTAG_ram_0_select : std_logic;
signal IJTAG_ram_0_clk : std_logic;
signal IJTAG_ram_0_reset : std_logic;
signal IJTAG_ram_0_enable : std_logic;
signal IJTAG_ram_0_write_byte_enable : std_logic_vector(3 downto 0);
signal IJTAG_ram_0_address : std_logic_vector(31 downto 2);
signal IJTAG_ram_0_data_write : std_logic_vector(31 downto 0);
signal IJTAG_ram_0_data_read : std_logic_vector(31 downto 0);
signal IJTAG_ram_1_select : std_logic;
signal IJTAG_ram_1_clk : std_logic;
signal IJTAG_ram_1_reset : std_logic;
signal IJTAG_ram_1_enable : std_logic;
signal IJTAG_ram_1_write_byte_enable : std_logic_vector(3 downto 0);
signal IJTAG_ram_1_address : std_logic_vector(31 downto 2);
signal IJTAG_ram_1_data_write : std_logic_vector(31 downto 0);
signal IJTAG_ram_1_data_read : std_logic_vector(31 downto 0);
signal IJTAG_ram_2_select : std_logic;
signal IJTAG_ram_2_clk : std_logic;
signal IJTAG_ram_2_reset : std_logic;
signal IJTAG_ram_2_enable : std_logic;
signal IJTAG_ram_2_write_byte_enable : std_logic_vector(3 downto 0);
signal IJTAG_ram_2_address : std_logic_vector(31 downto 2);
signal IJTAG_ram_2_data_write : std_logic_vector(31 downto 0);
signal IJTAG_ram_2_data_read : std_logic_vector(31 downto 0);
signal IJTAG_ram_3_select : std_logic;
signal IJTAG_ram_3_clk : std_logic;
signal IJTAG_ram_3_reset : std_logic;
signal IJTAG_ram_3_enable : std_logic;
signal IJTAG_ram_3_write_byte_enable : std_logic_vector(3 downto 0);
signal IJTAG_ram_3_address : std_logic_vector(31 downto 2);
signal IJTAG_ram_3_data_write : std_logic_vector(31 downto 0);
signal IJTAG_ram_3_data_read : std_logic_vector(31 downto 0);
begin
-- instantiating the network
NoC: network_2x2 generic map (DATA_WIDTH => 32, DATA_WIDTH_LV => 11)
port map (reset, clk,
RX_L_0, credit_out_L_0, valid_out_L_0, credit_in_L_0, valid_in_L_0, TX_L_0,
RX_L_1, credit_out_L_1, valid_out_L_1, credit_in_L_1, valid_in_L_1, TX_L_1,
RX_L_2, credit_out_L_2, valid_out_L_2, credit_in_L_2, valid_in_L_2, TX_L_2,
RX_L_3, credit_out_L_3, valid_out_L_3, credit_in_L_3, valid_in_L_3, TX_L_3,
link_faults_0, turn_faults_0, Rxy_reconf_PE_0, Cx_reconf_PE_0, Reconfig_command_0,
link_faults_1, turn_faults_1, Rxy_reconf_PE_1, Cx_reconf_PE_1, Reconfig_command_1,
link_faults_2, turn_faults_2, Rxy_reconf_PE_2, Cx_reconf_PE_2, Reconfig_command_2,
link_faults_3, turn_faults_3, Rxy_reconf_PE_3, Cx_reconf_PE_3, Reconfig_command_3,
TCK, RST, SEL, SO_sensors, SE, UE, CE, SO_NoC, toF_NoC, toC_NoC
);
process (not_reset, clk)
begin
if not_reset = '1' then
GPIO_out_FF <= (others => '0');
UART_0_W_out <= '0';
UART_1_W_out <= '0';
UART_2_W_out <= '0';
UART_3_W_out <= '0';
UART_0_R_out <= '0';
UART_1_R_out <= '0';
UART_2_R_out <= '0';
UART_3_R_out <= '0';
elsif clk'event and clk = '1' then
GPIO_out_FF <= GPIO_out_FF_in;
UART_0_W_out <= UART_0_W_in;
UART_1_W_out <= UART_1_W_in;
UART_2_W_out <= UART_2_W_in;
UART_3_W_out <= UART_3_W_in;
UART_0_R_out <= UART_0_R_in;
UART_1_R_out <= UART_1_R_in;
UART_2_R_out <= UART_2_R_in;
UART_3_R_out <= UART_3_R_in;
end if;
end process;
GPIO_out <= GPIO_out_FF;
uart_write_0 <= UART_0_W_out;
uart_write_1 <= UART_1_W_out;
uart_write_2 <= UART_2_W_out;
uart_write_3 <= UART_3_W_out;
UART_0_R_in <= uart_read_0;
UART_1_R_in <= uart_read_1;
UART_2_R_in <= uart_read_2;
UART_3_R_in <= uart_read_3;
not_reset <= not reset;
-- instantiating and connecting the PEs
PE_0: NoC_Node
generic map( current_address => 0,
stim_file => path & "code_0.txt",
log_file => path & "output_0.txt",
memory_type => memory_type)
port map( not_reset, clk,
uart_read => UART_0_R_out,
uart_write => UART_0_W_in,
credit_in => credit_out_L_0,
valid_out => valid_in_L_0,
TX => RX_L_0,
credit_out => credit_in_L_0,
valid_in => valid_out_L_0,
RX => TX_L_0,
link_faults => link_faults_0,
turn_faults => turn_faults_0,
Rxy_reconf_PE => Rxy_reconf_PE_0,
Cx_reconf_PE => Cx_reconf_PE_0,
Reconfig_command => Reconfig_command_0,
GPIO_out => GPIO_out_FF_in,
GPIO_in => GPIO_in,
IJTAG_select => IJTAG_ram_0_select,
IJTAG_clk => IJTAG_ram_0_clk,
IJTAG_reset => IJTAG_ram_0_reset,
IJTAG_enable => IJTAG_ram_0_enable,
IJTAG_write_byte_enable => IJTAG_ram_0_write_byte_enable,
IJTAG_address => IJTAG_ram_0_address,
IJTAG_data_write => IJTAG_ram_0_data_write,
IJTAG_data_read => IJTAG_ram_0_data_read
);
PE_1: NoC_Node
generic map( current_address => 1,
stim_file => path & "code_1.txt",
log_file => path & "output_1.txt",
memory_type => memory_type)
port map( not_reset, clk,
uart_read => UART_1_R_out,
uart_write => UART_1_W_in,
credit_in => credit_out_L_1,
valid_out => valid_in_L_1,
TX => RX_L_1,
credit_out => credit_in_L_1,
valid_in => valid_out_L_1,
RX => TX_L_1,
link_faults => link_faults_1,
turn_faults => turn_faults_1,
Rxy_reconf_PE => Rxy_reconf_PE_1,
Cx_reconf_PE => Cx_reconf_PE_1,
Reconfig_command => Reconfig_command_1,
GPIO_out => open,
GPIO_in => (others => '0'),
IJTAG_select => IJTAG_ram_1_select,
IJTAG_clk => IJTAG_ram_1_clk,
IJTAG_reset => IJTAG_ram_1_reset,
IJTAG_enable => IJTAG_ram_1_enable,
IJTAG_write_byte_enable => IJTAG_ram_1_write_byte_enable,
IJTAG_address => IJTAG_ram_1_address,
IJTAG_data_write => IJTAG_ram_1_data_write,
IJTAG_data_read => IJTAG_ram_1_data_read
);
PE_2: NoC_Node
generic map( current_address => 2,
stim_file => path & "code_2.txt",
log_file => path & "output_2.txt",
memory_type => memory_type)
port map( not_reset, clk,
uart_read => UART_2_R_out,
uart_write => UART_2_W_in,
credit_in => credit_out_L_2,
valid_out => valid_in_L_2,
TX => RX_L_2,
credit_out => credit_in_L_2,
valid_in => valid_out_L_2,
RX => TX_L_2,
link_faults => link_faults_2,
turn_faults => turn_faults_2,
Rxy_reconf_PE => Rxy_reconf_PE_2,
Cx_reconf_PE => Cx_reconf_PE_2,
Reconfig_command => Reconfig_command_2,
GPIO_out => open,
GPIO_in => (others => '0'),
IJTAG_select => IJTAG_ram_2_select,
IJTAG_clk => IJTAG_ram_2_clk,
IJTAG_reset => IJTAG_ram_2_reset,
IJTAG_enable => IJTAG_ram_2_enable,
IJTAG_write_byte_enable => IJTAG_ram_2_write_byte_enable,
IJTAG_address => IJTAG_ram_2_address,
IJTAG_data_write => IJTAG_ram_2_data_write,
IJTAG_data_read => IJTAG_ram_2_data_read
);
PE_3: NoC_Node
generic map( current_address => 3,
stim_file => path & "code_3.txt",
log_file => path & "output_3.txt",
memory_type => memory_type)
port map( not_reset, clk,
uart_read => UART_3_R_out,
uart_write => UART_3_W_in,
credit_in => credit_out_L_3,
valid_out => valid_in_L_3,
TX => RX_L_3,
credit_out => credit_in_L_3,
valid_in => valid_out_L_3,
RX => TX_L_3,
link_faults => link_faults_3,
turn_faults => turn_faults_3,
Rxy_reconf_PE => Rxy_reconf_PE_3,
Cx_reconf_PE => Cx_reconf_PE_3,
Reconfig_command => Reconfig_command_3,
GPIO_out => open,
GPIO_in => (others => '0'),
IJTAG_select => IJTAG_ram_3_select,
IJTAG_clk => IJTAG_ram_3_clk,
IJTAG_reset => IJTAG_ram_3_reset,
IJTAG_enable => IJTAG_ram_3_enable,
IJTAG_write_byte_enable => IJTAG_ram_3_write_byte_enable,
IJTAG_address => IJTAG_ram_3_address,
IJTAG_data_write => IJTAG_ram_3_data_write,
IJTAG_data_read => IJTAG_ram_3_data_read
);
-------------------------------------------
------- IJTAG stuff -----------------------
-------------------------------------------
-- Organization of IJTAG network (top level):
-- .----------. .-----------. .----------.
-- SI ----| sib_ram |---| sib_sens |---| sib_noc |-- SO
-- '----------' '-----------' '----------'
-- | |_________________________________________________.
-- | |
-- | .-----------. .-----------. .-----------. .-----------. |
-- '-| sib_ram_0 |-| sib_ram_1 |-| sib_ram_2 |-| sib_ram_3 |-'
-- '-----------' '-----------' '-----------' '-----------'
toF <= toF_NoC or toF_sensors;
toC <= toC_NoC and toC_sensors;
SO <= SO_NoC;
IJTAG_ram_0_enable <= '1';
IJTAG_ram_1_enable <= '1';
IJTAG_ram_2_enable <= '1';
IJTAG_ram_3_enable <= '1';
IJTAG_ram_0_clk <= TCK;
IJTAG_ram_1_clk <= TCK;
IJTAG_ram_2_clk <= TCK;
IJTAG_ram_3_clk <= TCK;
IJTAG_ram_0_reset <= RST;
IJTAG_ram_1_reset <= RST;
IJTAG_ram_2_reset <= RST;
IJTAG_ram_3_reset <= RST;
-- RAM Access SIB
SIB_RAM : SIB_mux_pre_FCX_SELgate
port map ( -- Scan Interface client --------------
SI => SI,
CE => CE,
SE => SE,
UE => UE,
SEL => SEL,
RST => RST,
TCK => TCK,
SO => SO_RAM,
toF => toF_RAM,
toC => toC_RAM,
-- Scan Interface host ----------------
fromSO => RAM3_SO,
toCE => SIB_RAM_toCE,
toSE => SIB_RAM_toSE,
toUE => SIB_RAM_toUE,
toSEL => SIB_RAM_toSEL,
toRST => SIB_RAM_toRST,
toTCK => SIB_RAM_toTCK,
toSI => SIB_RAM_toSI,
fromF => '0',
fromC => '1'
);
-- RAM Access instruments
RAM_instr0 : RAMAccessInstrument
generic map ( DataSize => RAMDataSize,
AddressSize => RAMAddrSize)
port map ( SI => SIB_RAM_toSI,
SO => RAM0_SO,
SEL => SIB_RAM_toSEL,
SE => SIB_RAM_toSE,
CE => SIB_RAM_toCE,
UE => SIB_RAM_toUE,
RST => SIB_RAM_toRST,
TCK => SIB_RAM_toTCK,
MEM_SIB_SEL => IJTAG_ram_0_select,
RAM_data_read => IJTAG_ram_0_data_read,
RAM_data_write => IJTAG_ram_0_data_write,
RAM_address_out => RAM0_address,
RAM_write_enable => RAM0_write_enable);
IJTAG_ram_0_write_byte_enable <= (others => RAM0_write_enable);
IJTAG_ram_0_address <= "000000000000000000" & RAM0_address;
RAM_instr1 : RAMAccessInstrument
generic map ( DataSize => RAMDataSize,
AddressSize => RAMAddrSize)
port map ( SI => RAM0_SO,
SO => RAM1_SO,
SEL => SIB_RAM_toSEL,
SE => SIB_RAM_toSE,
CE => SIB_RAM_toCE,
UE => SIB_RAM_toUE,
RST => SIB_RAM_toRST,
TCK => SIB_RAM_toTCK,
MEM_SIB_SEL => IJTAG_ram_1_select,
RAM_data_read => IJTAG_ram_1_data_read,
RAM_data_write => IJTAG_ram_1_data_write,
RAM_address_out => RAM1_address,
RAM_write_enable => RAM1_write_enable);
IJTAG_ram_1_write_byte_enable <= (others => RAM1_write_enable);
IJTAG_ram_1_address <= "000000000000000000" & RAM1_address;
RAM_instr2 : RAMAccessInstrument
generic map ( DataSize => RAMDataSize,
AddressSize => RAMAddrSize)
port map ( SI => RAM1_SO,
SO => RAM2_SO,
SEL => SIB_RAM_toSEL,
SE => SIB_RAM_toSE,
CE => SIB_RAM_toCE,
UE => SIB_RAM_toUE,
RST => SIB_RAM_toRST,
TCK => SIB_RAM_toTCK,
MEM_SIB_SEL => IJTAG_ram_2_select,
RAM_data_read => IJTAG_ram_2_data_read,
RAM_data_write => IJTAG_ram_2_data_write,
RAM_address_out => RAM2_address,
RAM_write_enable => RAM2_write_enable);
IJTAG_ram_2_write_byte_enable <= (others => RAM2_write_enable);
IJTAG_ram_2_address <= "000000000000000000" & RAM2_address;
RAM_instr3 : RAMAccessInstrument
generic map ( DataSize => RAMDataSize,
AddressSize => RAMAddrSize)
port map ( SI => RAM2_SO,
SO => RAM3_SO,
SEL => SIB_RAM_toSEL,
SE => SIB_RAM_toSE,
CE => SIB_RAM_toCE,
UE => SIB_RAM_toUE,
RST => SIB_RAM_toRST,
TCK => SIB_RAM_toTCK,
MEM_SIB_SEL => IJTAG_ram_3_select,
RAM_data_read => IJTAG_ram_3_data_read,
RAM_data_write => IJTAG_ram_3_data_write,
RAM_address_out => RAM3_address,
RAM_write_enable => RAM3_write_enable);
IJTAG_ram_3_write_byte_enable <= (others => RAM3_write_enable);
IJTAG_ram_3_address <= "000000000000000000" & RAM3_address;
-- IMMORTAL sensors interface
immortal_sensors: immortal_sensor_IJTAG_interface
port map (
TCK => TCK,
RST => RST,
SEL => SEL,
SI => SO_RAM,
SE => SE,
UE => UE,
CE => CE,
SO => SO_sensors,
toF => toF_sensors,
toC => toC_sensors,
temperature_control => temperature_control,
temperature_data => temperature_data,
iddt_control => iddt_control,
iddt_data => iddt_data,
slack_control => slack_control,
slack_data => slack_data,
voltage_control => voltage_control,
voltage_data => voltage_data
);
temperature_data <= (others => '0');
iddt_data <= (others => '0');
end;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
------------------------------------------------------------
-- This file is automatically generated!
-- Here are the parameters:
-- network size x: 2
-- network size y: 2
-- Data width: 32
-- Parity: False
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE ieee.numeric_std.ALL;
use work.component_pack.all;
entity network_2x2_with_PE is
generic (DATA_WIDTH: integer := 32;
DATA_WIDTH_LV: integer := 11;
memory_type : string :=
"TRI_PORT_X"
-- "DUAL_PORT_"
-- "ALTERA_LPM"
-- "XILINX_16X"
);
port (reset: in std_logic;
clk: in std_logic;
-- IJTAG network for fault injection and checker status monitoring
TCK : in std_logic;
RST : in std_logic;
SEL : in std_logic;
SI : in std_logic;
SE : in std_logic;
UE : in std_logic;
CE : in std_logic;
SO : out std_logic;
toF : out std_logic;
toC : out std_logic;
-- GPIO for Node 0
GPIO_out: out std_logic_vector(15 downto 0);
GPIO_in: in std_logic_vector(21 downto 0);
-- UART for all Plasmas
uart_write_0 : out std_logic;
uart_read_0 : in std_logic;
uart_write_1 : out std_logic;
uart_read_1 : in std_logic;
uart_write_2 : out std_logic;
uart_read_2 : in std_logic;
uart_write_3 : out std_logic;
uart_read_3 : in std_logic;
-- Monitor connections
temperature_control : out std_logic_vector(2 downto 0);
iddt_control : out std_logic_vector(2 downto 0);
slack_control : out std_logic_vector(2 downto 0);
slack_data : in std_logic_vector(31 downto 0);
voltage_control : out std_logic_vector(2 downto 0);
voltage_data : in std_logic_vector(31 downto 0)
);
end network_2x2_with_PE;
architecture behavior of network_2x2_with_PE is
constant RAMDataSize : positive := 32;
constant RAMAddrSize : positive := 12;
constant path : string(1 to 12) := "Testbenches/"; --uncomment this if you are SIMULATING in MODELSIM, or if you're synthesizing.
-- constant path : string(positive range <>) := "/home/tsotne/ownCloud/git/Bonfire_sim/Bonfire/RTL/Chip_Designs/IMMORTAL_Chip_2017/Testbenches/"; --used only for Vivado similation. Tsotnes PC.
component immortal_sensor_IJTAG_interface is
Port ( -- Scan Interface client --------------
TCK : in std_logic;
RST : in std_logic;
SEL : in std_logic;
SI : in std_logic;
SE : in std_logic;
UE : in std_logic;
CE : in std_logic;
SO : out std_logic;
toF : out std_logic;
toC : out std_logic;
-- Monitor connections
temperature_control : out std_logic_vector(2 downto 0);
temperature_data : in std_logic_vector(12 downto 0);
iddt_control : out std_logic_vector(2 downto 0);
iddt_data : in std_logic_vector(12 downto 0);
slack_control : out std_logic_vector(2 downto 0);
slack_data : in std_logic_vector(31 downto 0);
voltage_control : out std_logic_vector(2 downto 0);
voltage_data : in std_logic_vector(31 downto 0));
end component;
component SIB_mux_pre_FCX_SELgate is
Port ( -- Scan Interface client --------------
SI : in STD_LOGIC; -- ScanInPort
CE : in STD_LOGIC; -- CaptureEnPort
SE : in STD_LOGIC; -- ShiftEnPort
UE : in STD_LOGIC; -- UpdateEnPort
SEL : in STD_LOGIC; -- SelectPort
RST : in STD_LOGIC; -- ResetPort
TCK : in STD_LOGIC; -- TCKPort
SO : out STD_LOGIC; -- ScanOutPort
toF : out STD_LOGIC; -- To F flag of the upper hierarchical level
toC : out STD_LOGIC; -- To C flag of the upper hierarchical level
-- Scan Interface host ----------------
fromSO : in STD_LOGIC; -- ScanInPort
toCE : out STD_LOGIC; -- ToCaptureEnPort
toSE : out STD_LOGIC; -- ToShiftEnPort
toUE : out STD_LOGIC; -- ToUpdateEnPort
toSEL : out STD_LOGIC; -- ToSelectPort
toRST : out STD_LOGIC; -- ToResetPort
toTCK : out STD_LOGIC; -- ToTCKPort
toSI : out STD_LOGIC; -- ScanOutPort
fromF : in STD_LOGIC; -- From an OR of all F flags in the underlying network segment
fromC : in STD_LOGIC); -- From an AND of all C flags in the underlying network segment
end component;
component RAMAccessInstrument is
Generic ( DataSize : positive := 8;
AddressSize : positive := 8);
Port ( -- Scan Interface scan_client ----------
SI : in std_logic; -- ScanInPort
SO : out std_logic; -- ScanOutPort
SEL : in std_logic; -- SelectPort
----------------------------------------
SE : in std_logic; -- ShiftEnPort
CE : in std_logic; -- CaptureEnPort
UE : in std_logic; -- UpdateEnPort
RST : in std_logic; -- ResetPort
TCK : in std_logic; -- TCKPort
MEM_SIB_SEL : out std_logic;
-- RAM interface
RAM_data_read : in std_logic_vector (DataSize-1 downto 0);
RAM_data_write : out std_logic_vector (DataSize-1 downto 0);
RAM_address_out : out std_logic_vector (AddressSize-1 downto 0);
RAM_write_enable : out std_logic);
end component;
-- Monitor signals
signal temperature_data : std_logic_vector(12 downto 0);
signal iddt_data : std_logic_vector(12 downto 0);
-- Declaring network component
-- Declaring NoC_Node component (with Plasma, RAM, NI and UART)
-- generating bulk signals...
signal RX_L_0, TX_L_0: std_logic_vector (31 downto 0);
signal credit_counter_out_0: std_logic_vector (1 downto 0);
signal credit_out_L_0, credit_in_L_0, valid_in_L_0, valid_out_L_0: std_logic;
signal RX_L_1, TX_L_1: std_logic_vector (31 downto 0);
signal credit_counter_out_1: std_logic_vector (1 downto 0);
signal credit_out_L_1, credit_in_L_1, valid_in_L_1, valid_out_L_1: std_logic;
signal RX_L_2, TX_L_2: std_logic_vector (31 downto 0);
signal credit_counter_out_2: std_logic_vector (1 downto 0);
signal credit_out_L_2, credit_in_L_2, valid_in_L_2, valid_out_L_2: std_logic;
signal RX_L_3, TX_L_3: std_logic_vector (31 downto 0);
signal credit_counter_out_3: std_logic_vector (1 downto 0);
signal credit_out_L_3, credit_in_L_3, valid_in_L_3, valid_out_L_3: std_logic;
-- NI testing signals
--------------
--signal Rxy_reconf: std_logic_vector (7 downto 0) := "01111101";
--signal Reconfig: std_logic := '0';
--------------
signal not_reset: std_logic;
signal link_faults_0, link_faults_1, link_faults_2, link_faults_3 : std_logic_vector(4 downto 0);
signal turn_faults_0, turn_faults_1, turn_faults_2, turn_faults_3 : std_logic_vector(19 downto 0);
signal Rxy_reconf_PE_0, Rxy_reconf_PE_1,Rxy_reconf_PE_2, Rxy_reconf_PE_3 : std_logic_vector(7 downto 0);
signal Cx_reconf_PE_0, Cx_reconf_PE_1, Cx_reconf_PE_2, Cx_reconf_PE_3 : std_logic_vector(3 downto 0);
signal Reconfig_command_0, Reconfig_command_1, Reconfig_command_2, Reconfig_command_3 : std_logic;
signal GPIO_out_FF_in, GPIO_out_FF : std_logic_vector(15 downto 0);
signal UART_0_W_in, UART_0_W_out, UART_0_R_in, UART_0_R_out : std_logic;
signal UART_1_W_in, UART_1_W_out, UART_1_R_in, UART_1_R_out : std_logic;
signal UART_2_W_in, UART_2_W_out, UART_2_R_in, UART_2_R_out : std_logic;
signal UART_3_W_in, UART_3_W_out, UART_3_R_in, UART_3_R_out : std_logic;
-- IJTAG-related signals
signal SO_NoC , SO_sensors , SO_RAM : std_logic;
signal toF_NoC, toF_sensors, toF_RAM : std_logic;
signal toC_NoC, toC_sensors, toC_RAM : std_logic;
signal SIB_RAM_toSI, SIB_RAM_toTCK, SIB_RAM_toRST, SIB_RAM_toSEL, SIB_RAM_toUE, SIB_RAM_toSE, SIB_RAM_toCE : std_logic;
signal RAM0_SO, RAM1_SO, RAM2_SO, RAM3_SO : std_logic;
signal RAM0_write_enable, RAM1_write_enable, RAM2_write_enable, RAM3_write_enable : std_logic;
signal RAM0_address, RAM1_address, RAM2_address, RAM3_address : std_logic_vector(RAMAddrSize-1 downto 0);
signal IJTAG_ram_0_select : std_logic;
signal IJTAG_ram_0_clk : std_logic;
signal IJTAG_ram_0_reset : std_logic;
signal IJTAG_ram_0_enable : std_logic;
signal IJTAG_ram_0_write_byte_enable : std_logic_vector(3 downto 0);
signal IJTAG_ram_0_address : std_logic_vector(31 downto 2);
signal IJTAG_ram_0_data_write : std_logic_vector(31 downto 0);
signal IJTAG_ram_0_data_read : std_logic_vector(31 downto 0);
signal IJTAG_ram_1_select : std_logic;
signal IJTAG_ram_1_clk : std_logic;
signal IJTAG_ram_1_reset : std_logic;
signal IJTAG_ram_1_enable : std_logic;
signal IJTAG_ram_1_write_byte_enable : std_logic_vector(3 downto 0);
signal IJTAG_ram_1_address : std_logic_vector(31 downto 2);
signal IJTAG_ram_1_data_write : std_logic_vector(31 downto 0);
signal IJTAG_ram_1_data_read : std_logic_vector(31 downto 0);
signal IJTAG_ram_2_select : std_logic;
signal IJTAG_ram_2_clk : std_logic;
signal IJTAG_ram_2_reset : std_logic;
signal IJTAG_ram_2_enable : std_logic;
signal IJTAG_ram_2_write_byte_enable : std_logic_vector(3 downto 0);
signal IJTAG_ram_2_address : std_logic_vector(31 downto 2);
signal IJTAG_ram_2_data_write : std_logic_vector(31 downto 0);
signal IJTAG_ram_2_data_read : std_logic_vector(31 downto 0);
signal IJTAG_ram_3_select : std_logic;
signal IJTAG_ram_3_clk : std_logic;
signal IJTAG_ram_3_reset : std_logic;
signal IJTAG_ram_3_enable : std_logic;
signal IJTAG_ram_3_write_byte_enable : std_logic_vector(3 downto 0);
signal IJTAG_ram_3_address : std_logic_vector(31 downto 2);
signal IJTAG_ram_3_data_write : std_logic_vector(31 downto 0);
signal IJTAG_ram_3_data_read : std_logic_vector(31 downto 0);
begin
-- instantiating the network
NoC: network_2x2 generic map (DATA_WIDTH => 32, DATA_WIDTH_LV => 11)
port map (reset, clk,
RX_L_0, credit_out_L_0, valid_out_L_0, credit_in_L_0, valid_in_L_0, TX_L_0,
RX_L_1, credit_out_L_1, valid_out_L_1, credit_in_L_1, valid_in_L_1, TX_L_1,
RX_L_2, credit_out_L_2, valid_out_L_2, credit_in_L_2, valid_in_L_2, TX_L_2,
RX_L_3, credit_out_L_3, valid_out_L_3, credit_in_L_3, valid_in_L_3, TX_L_3,
link_faults_0, turn_faults_0, Rxy_reconf_PE_0, Cx_reconf_PE_0, Reconfig_command_0,
link_faults_1, turn_faults_1, Rxy_reconf_PE_1, Cx_reconf_PE_1, Reconfig_command_1,
link_faults_2, turn_faults_2, Rxy_reconf_PE_2, Cx_reconf_PE_2, Reconfig_command_2,
link_faults_3, turn_faults_3, Rxy_reconf_PE_3, Cx_reconf_PE_3, Reconfig_command_3,
TCK, RST, SEL, SO_sensors, SE, UE, CE, SO_NoC, toF_NoC, toC_NoC
);
process (not_reset, clk)
begin
if not_reset = '1' then
GPIO_out_FF <= (others => '0');
UART_0_W_out <= '0';
UART_1_W_out <= '0';
UART_2_W_out <= '0';
UART_3_W_out <= '0';
UART_0_R_out <= '0';
UART_1_R_out <= '0';
UART_2_R_out <= '0';
UART_3_R_out <= '0';
elsif clk'event and clk = '1' then
GPIO_out_FF <= GPIO_out_FF_in;
UART_0_W_out <= UART_0_W_in;
UART_1_W_out <= UART_1_W_in;
UART_2_W_out <= UART_2_W_in;
UART_3_W_out <= UART_3_W_in;
UART_0_R_out <= UART_0_R_in;
UART_1_R_out <= UART_1_R_in;
UART_2_R_out <= UART_2_R_in;
UART_3_R_out <= UART_3_R_in;
end if;
end process;
GPIO_out <= GPIO_out_FF;
uart_write_0 <= UART_0_W_out;
uart_write_1 <= UART_1_W_out;
uart_write_2 <= UART_2_W_out;
uart_write_3 <= UART_3_W_out;
UART_0_R_in <= uart_read_0;
UART_1_R_in <= uart_read_1;
UART_2_R_in <= uart_read_2;
UART_3_R_in <= uart_read_3;
not_reset <= not reset;
-- instantiating and connecting the PEs
PE_0: NoC_Node
generic map( current_address => 0,
stim_file => path & "code_0.txt",
log_file => path & "output_0.txt",
memory_type => memory_type)
port map( not_reset, clk,
uart_read => UART_0_R_out,
uart_write => UART_0_W_in,
credit_in => credit_out_L_0,
valid_out => valid_in_L_0,
TX => RX_L_0,
credit_out => credit_in_L_0,
valid_in => valid_out_L_0,
RX => TX_L_0,
link_faults => link_faults_0,
turn_faults => turn_faults_0,
Rxy_reconf_PE => Rxy_reconf_PE_0,
Cx_reconf_PE => Cx_reconf_PE_0,
Reconfig_command => Reconfig_command_0,
GPIO_out => GPIO_out_FF_in,
GPIO_in => GPIO_in,
IJTAG_select => IJTAG_ram_0_select,
IJTAG_clk => IJTAG_ram_0_clk,
IJTAG_reset => IJTAG_ram_0_reset,
IJTAG_enable => IJTAG_ram_0_enable,
IJTAG_write_byte_enable => IJTAG_ram_0_write_byte_enable,
IJTAG_address => IJTAG_ram_0_address,
IJTAG_data_write => IJTAG_ram_0_data_write,
IJTAG_data_read => IJTAG_ram_0_data_read
);
PE_1: NoC_Node
generic map( current_address => 1,
stim_file => path & "code_1.txt",
log_file => path & "output_1.txt",
memory_type => memory_type)
port map( not_reset, clk,
uart_read => UART_1_R_out,
uart_write => UART_1_W_in,
credit_in => credit_out_L_1,
valid_out => valid_in_L_1,
TX => RX_L_1,
credit_out => credit_in_L_1,
valid_in => valid_out_L_1,
RX => TX_L_1,
link_faults => link_faults_1,
turn_faults => turn_faults_1,
Rxy_reconf_PE => Rxy_reconf_PE_1,
Cx_reconf_PE => Cx_reconf_PE_1,
Reconfig_command => Reconfig_command_1,
GPIO_out => open,
GPIO_in => (others => '0'),
IJTAG_select => IJTAG_ram_1_select,
IJTAG_clk => IJTAG_ram_1_clk,
IJTAG_reset => IJTAG_ram_1_reset,
IJTAG_enable => IJTAG_ram_1_enable,
IJTAG_write_byte_enable => IJTAG_ram_1_write_byte_enable,
IJTAG_address => IJTAG_ram_1_address,
IJTAG_data_write => IJTAG_ram_1_data_write,
IJTAG_data_read => IJTAG_ram_1_data_read
);
PE_2: NoC_Node
generic map( current_address => 2,
stim_file => path & "code_2.txt",
log_file => path & "output_2.txt",
memory_type => memory_type)
port map( not_reset, clk,
uart_read => UART_2_R_out,
uart_write => UART_2_W_in,
credit_in => credit_out_L_2,
valid_out => valid_in_L_2,
TX => RX_L_2,
credit_out => credit_in_L_2,
valid_in => valid_out_L_2,
RX => TX_L_2,
link_faults => link_faults_2,
turn_faults => turn_faults_2,
Rxy_reconf_PE => Rxy_reconf_PE_2,
Cx_reconf_PE => Cx_reconf_PE_2,
Reconfig_command => Reconfig_command_2,
GPIO_out => open,
GPIO_in => (others => '0'),
IJTAG_select => IJTAG_ram_2_select,
IJTAG_clk => IJTAG_ram_2_clk,
IJTAG_reset => IJTAG_ram_2_reset,
IJTAG_enable => IJTAG_ram_2_enable,
IJTAG_write_byte_enable => IJTAG_ram_2_write_byte_enable,
IJTAG_address => IJTAG_ram_2_address,
IJTAG_data_write => IJTAG_ram_2_data_write,
IJTAG_data_read => IJTAG_ram_2_data_read
);
PE_3: NoC_Node
generic map( current_address => 3,
stim_file => path & "code_3.txt",
log_file => path & "output_3.txt",
memory_type => memory_type)
port map( not_reset, clk,
uart_read => UART_3_R_out,
uart_write => UART_3_W_in,
credit_in => credit_out_L_3,
valid_out => valid_in_L_3,
TX => RX_L_3,
credit_out => credit_in_L_3,
valid_in => valid_out_L_3,
RX => TX_L_3,
link_faults => link_faults_3,
turn_faults => turn_faults_3,
Rxy_reconf_PE => Rxy_reconf_PE_3,
Cx_reconf_PE => Cx_reconf_PE_3,
Reconfig_command => Reconfig_command_3,
GPIO_out => open,
GPIO_in => (others => '0'),
IJTAG_select => IJTAG_ram_3_select,
IJTAG_clk => IJTAG_ram_3_clk,
IJTAG_reset => IJTAG_ram_3_reset,
IJTAG_enable => IJTAG_ram_3_enable,
IJTAG_write_byte_enable => IJTAG_ram_3_write_byte_enable,
IJTAG_address => IJTAG_ram_3_address,
IJTAG_data_write => IJTAG_ram_3_data_write,
IJTAG_data_read => IJTAG_ram_3_data_read
);
-------------------------------------------
------- IJTAG stuff -----------------------
-------------------------------------------
-- Organization of IJTAG network (top level):
-- .----------. .-----------. .----------.
-- SI ----| sib_ram |---| sib_sens |---| sib_noc |-- SO
-- '----------' '-----------' '----------'
-- | |_________________________________________________.
-- | |
-- | .-----------. .-----------. .-----------. .-----------. |
-- '-| sib_ram_0 |-| sib_ram_1 |-| sib_ram_2 |-| sib_ram_3 |-'
-- '-----------' '-----------' '-----------' '-----------'
toF <= toF_NoC or toF_sensors;
toC <= toC_NoC and toC_sensors;
SO <= SO_NoC;
IJTAG_ram_0_enable <= '1';
IJTAG_ram_1_enable <= '1';
IJTAG_ram_2_enable <= '1';
IJTAG_ram_3_enable <= '1';
IJTAG_ram_0_clk <= TCK;
IJTAG_ram_1_clk <= TCK;
IJTAG_ram_2_clk <= TCK;
IJTAG_ram_3_clk <= TCK;
IJTAG_ram_0_reset <= RST;
IJTAG_ram_1_reset <= RST;
IJTAG_ram_2_reset <= RST;
IJTAG_ram_3_reset <= RST;
-- RAM Access SIB
SIB_RAM : SIB_mux_pre_FCX_SELgate
port map ( -- Scan Interface client --------------
SI => SI,
CE => CE,
SE => SE,
UE => UE,
SEL => SEL,
RST => RST,
TCK => TCK,
SO => SO_RAM,
toF => toF_RAM,
toC => toC_RAM,
-- Scan Interface host ----------------
fromSO => RAM3_SO,
toCE => SIB_RAM_toCE,
toSE => SIB_RAM_toSE,
toUE => SIB_RAM_toUE,
toSEL => SIB_RAM_toSEL,
toRST => SIB_RAM_toRST,
toTCK => SIB_RAM_toTCK,
toSI => SIB_RAM_toSI,
fromF => '0',
fromC => '1'
);
-- RAM Access instruments
RAM_instr0 : RAMAccessInstrument
generic map ( DataSize => RAMDataSize,
AddressSize => RAMAddrSize)
port map ( SI => SIB_RAM_toSI,
SO => RAM0_SO,
SEL => SIB_RAM_toSEL,
SE => SIB_RAM_toSE,
CE => SIB_RAM_toCE,
UE => SIB_RAM_toUE,
RST => SIB_RAM_toRST,
TCK => SIB_RAM_toTCK,
MEM_SIB_SEL => IJTAG_ram_0_select,
RAM_data_read => IJTAG_ram_0_data_read,
RAM_data_write => IJTAG_ram_0_data_write,
RAM_address_out => RAM0_address,
RAM_write_enable => RAM0_write_enable);
IJTAG_ram_0_write_byte_enable <= (others => RAM0_write_enable);
IJTAG_ram_0_address <= "000000000000000000" & RAM0_address;
RAM_instr1 : RAMAccessInstrument
generic map ( DataSize => RAMDataSize,
AddressSize => RAMAddrSize)
port map ( SI => RAM0_SO,
SO => RAM1_SO,
SEL => SIB_RAM_toSEL,
SE => SIB_RAM_toSE,
CE => SIB_RAM_toCE,
UE => SIB_RAM_toUE,
RST => SIB_RAM_toRST,
TCK => SIB_RAM_toTCK,
MEM_SIB_SEL => IJTAG_ram_1_select,
RAM_data_read => IJTAG_ram_1_data_read,
RAM_data_write => IJTAG_ram_1_data_write,
RAM_address_out => RAM1_address,
RAM_write_enable => RAM1_write_enable);
IJTAG_ram_1_write_byte_enable <= (others => RAM1_write_enable);
IJTAG_ram_1_address <= "000000000000000000" & RAM1_address;
RAM_instr2 : RAMAccessInstrument
generic map ( DataSize => RAMDataSize,
AddressSize => RAMAddrSize)
port map ( SI => RAM1_SO,
SO => RAM2_SO,
SEL => SIB_RAM_toSEL,
SE => SIB_RAM_toSE,
CE => SIB_RAM_toCE,
UE => SIB_RAM_toUE,
RST => SIB_RAM_toRST,
TCK => SIB_RAM_toTCK,
MEM_SIB_SEL => IJTAG_ram_2_select,
RAM_data_read => IJTAG_ram_2_data_read,
RAM_data_write => IJTAG_ram_2_data_write,
RAM_address_out => RAM2_address,
RAM_write_enable => RAM2_write_enable);
IJTAG_ram_2_write_byte_enable <= (others => RAM2_write_enable);
IJTAG_ram_2_address <= "000000000000000000" & RAM2_address;
RAM_instr3 : RAMAccessInstrument
generic map ( DataSize => RAMDataSize,
AddressSize => RAMAddrSize)
port map ( SI => RAM2_SO,
SO => RAM3_SO,
SEL => SIB_RAM_toSEL,
SE => SIB_RAM_toSE,
CE => SIB_RAM_toCE,
UE => SIB_RAM_toUE,
RST => SIB_RAM_toRST,
TCK => SIB_RAM_toTCK,
MEM_SIB_SEL => IJTAG_ram_3_select,
RAM_data_read => IJTAG_ram_3_data_read,
RAM_data_write => IJTAG_ram_3_data_write,
RAM_address_out => RAM3_address,
RAM_write_enable => RAM3_write_enable);
IJTAG_ram_3_write_byte_enable <= (others => RAM3_write_enable);
IJTAG_ram_3_address <= "000000000000000000" & RAM3_address;
-- IMMORTAL sensors interface
immortal_sensors: immortal_sensor_IJTAG_interface
port map (
TCK => TCK,
RST => RST,
SEL => SEL,
SI => SO_RAM,
SE => SE,
UE => UE,
CE => CE,
SO => SO_sensors,
toF => toF_sensors,
toC => toC_sensors,
temperature_control => temperature_control,
temperature_data => temperature_data,
iddt_control => iddt_control,
iddt_data => iddt_data,
slack_control => slack_control,
slack_data => slack_data,
voltage_control => voltage_control,
voltage_data => voltage_data
);
temperature_data <= (others => '0');
iddt_data <= (others => '0');
end;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
------------------------------------------------------------
-- This file is automatically generated!
-- Here are the parameters:
-- network size x: 2
-- network size y: 2
-- Data width: 32
-- Parity: False
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE ieee.numeric_std.ALL;
use work.component_pack.all;
entity network_2x2_with_PE is
generic (DATA_WIDTH: integer := 32;
DATA_WIDTH_LV: integer := 11;
memory_type : string :=
"TRI_PORT_X"
-- "DUAL_PORT_"
-- "ALTERA_LPM"
-- "XILINX_16X"
);
port (reset: in std_logic;
clk: in std_logic;
-- IJTAG network for fault injection and checker status monitoring
TCK : in std_logic;
RST : in std_logic;
SEL : in std_logic;
SI : in std_logic;
SE : in std_logic;
UE : in std_logic;
CE : in std_logic;
SO : out std_logic;
toF : out std_logic;
toC : out std_logic;
-- GPIO for Node 0
GPIO_out: out std_logic_vector(15 downto 0);
GPIO_in: in std_logic_vector(21 downto 0);
-- UART for all Plasmas
uart_write_0 : out std_logic;
uart_read_0 : in std_logic;
uart_write_1 : out std_logic;
uart_read_1 : in std_logic;
uart_write_2 : out std_logic;
uart_read_2 : in std_logic;
uart_write_3 : out std_logic;
uart_read_3 : in std_logic;
-- Monitor connections
temperature_control : out std_logic_vector(2 downto 0);
iddt_control : out std_logic_vector(2 downto 0);
slack_control : out std_logic_vector(2 downto 0);
slack_data : in std_logic_vector(31 downto 0);
voltage_control : out std_logic_vector(2 downto 0);
voltage_data : in std_logic_vector(31 downto 0)
);
end network_2x2_with_PE;
architecture behavior of network_2x2_with_PE is
constant RAMDataSize : positive := 32;
constant RAMAddrSize : positive := 12;
constant path : string(1 to 12) := "Testbenches/"; --uncomment this if you are SIMULATING in MODELSIM, or if you're synthesizing.
-- constant path : string(positive range <>) := "/home/tsotne/ownCloud/git/Bonfire_sim/Bonfire/RTL/Chip_Designs/IMMORTAL_Chip_2017/Testbenches/"; --used only for Vivado similation. Tsotnes PC.
component immortal_sensor_IJTAG_interface is
Port ( -- Scan Interface client --------------
TCK : in std_logic;
RST : in std_logic;
SEL : in std_logic;
SI : in std_logic;
SE : in std_logic;
UE : in std_logic;
CE : in std_logic;
SO : out std_logic;
toF : out std_logic;
toC : out std_logic;
-- Monitor connections
temperature_control : out std_logic_vector(2 downto 0);
temperature_data : in std_logic_vector(12 downto 0);
iddt_control : out std_logic_vector(2 downto 0);
iddt_data : in std_logic_vector(12 downto 0);
slack_control : out std_logic_vector(2 downto 0);
slack_data : in std_logic_vector(31 downto 0);
voltage_control : out std_logic_vector(2 downto 0);
voltage_data : in std_logic_vector(31 downto 0));
end component;
component SIB_mux_pre_FCX_SELgate is
Port ( -- Scan Interface client --------------
SI : in STD_LOGIC; -- ScanInPort
CE : in STD_LOGIC; -- CaptureEnPort
SE : in STD_LOGIC; -- ShiftEnPort
UE : in STD_LOGIC; -- UpdateEnPort
SEL : in STD_LOGIC; -- SelectPort
RST : in STD_LOGIC; -- ResetPort
TCK : in STD_LOGIC; -- TCKPort
SO : out STD_LOGIC; -- ScanOutPort
toF : out STD_LOGIC; -- To F flag of the upper hierarchical level
toC : out STD_LOGIC; -- To C flag of the upper hierarchical level
-- Scan Interface host ----------------
fromSO : in STD_LOGIC; -- ScanInPort
toCE : out STD_LOGIC; -- ToCaptureEnPort
toSE : out STD_LOGIC; -- ToShiftEnPort
toUE : out STD_LOGIC; -- ToUpdateEnPort
toSEL : out STD_LOGIC; -- ToSelectPort
toRST : out STD_LOGIC; -- ToResetPort
toTCK : out STD_LOGIC; -- ToTCKPort
toSI : out STD_LOGIC; -- ScanOutPort
fromF : in STD_LOGIC; -- From an OR of all F flags in the underlying network segment
fromC : in STD_LOGIC); -- From an AND of all C flags in the underlying network segment
end component;
component RAMAccessInstrument is
Generic ( DataSize : positive := 8;
AddressSize : positive := 8);
Port ( -- Scan Interface scan_client ----------
SI : in std_logic; -- ScanInPort
SO : out std_logic; -- ScanOutPort
SEL : in std_logic; -- SelectPort
----------------------------------------
SE : in std_logic; -- ShiftEnPort
CE : in std_logic; -- CaptureEnPort
UE : in std_logic; -- UpdateEnPort
RST : in std_logic; -- ResetPort
TCK : in std_logic; -- TCKPort
MEM_SIB_SEL : out std_logic;
-- RAM interface
RAM_data_read : in std_logic_vector (DataSize-1 downto 0);
RAM_data_write : out std_logic_vector (DataSize-1 downto 0);
RAM_address_out : out std_logic_vector (AddressSize-1 downto 0);
RAM_write_enable : out std_logic);
end component;
-- Monitor signals
signal temperature_data : std_logic_vector(12 downto 0);
signal iddt_data : std_logic_vector(12 downto 0);
-- Declaring network component
-- Declaring NoC_Node component (with Plasma, RAM, NI and UART)
-- generating bulk signals...
signal RX_L_0, TX_L_0: std_logic_vector (31 downto 0);
signal credit_counter_out_0: std_logic_vector (1 downto 0);
signal credit_out_L_0, credit_in_L_0, valid_in_L_0, valid_out_L_0: std_logic;
signal RX_L_1, TX_L_1: std_logic_vector (31 downto 0);
signal credit_counter_out_1: std_logic_vector (1 downto 0);
signal credit_out_L_1, credit_in_L_1, valid_in_L_1, valid_out_L_1: std_logic;
signal RX_L_2, TX_L_2: std_logic_vector (31 downto 0);
signal credit_counter_out_2: std_logic_vector (1 downto 0);
signal credit_out_L_2, credit_in_L_2, valid_in_L_2, valid_out_L_2: std_logic;
signal RX_L_3, TX_L_3: std_logic_vector (31 downto 0);
signal credit_counter_out_3: std_logic_vector (1 downto 0);
signal credit_out_L_3, credit_in_L_3, valid_in_L_3, valid_out_L_3: std_logic;
-- NI testing signals
--------------
--signal Rxy_reconf: std_logic_vector (7 downto 0) := "01111101";
--signal Reconfig: std_logic := '0';
--------------
signal not_reset: std_logic;
signal link_faults_0, link_faults_1, link_faults_2, link_faults_3 : std_logic_vector(4 downto 0);
signal turn_faults_0, turn_faults_1, turn_faults_2, turn_faults_3 : std_logic_vector(19 downto 0);
signal Rxy_reconf_PE_0, Rxy_reconf_PE_1,Rxy_reconf_PE_2, Rxy_reconf_PE_3 : std_logic_vector(7 downto 0);
signal Cx_reconf_PE_0, Cx_reconf_PE_1, Cx_reconf_PE_2, Cx_reconf_PE_3 : std_logic_vector(3 downto 0);
signal Reconfig_command_0, Reconfig_command_1, Reconfig_command_2, Reconfig_command_3 : std_logic;
signal GPIO_out_FF_in, GPIO_out_FF : std_logic_vector(15 downto 0);
signal UART_0_W_in, UART_0_W_out, UART_0_R_in, UART_0_R_out : std_logic;
signal UART_1_W_in, UART_1_W_out, UART_1_R_in, UART_1_R_out : std_logic;
signal UART_2_W_in, UART_2_W_out, UART_2_R_in, UART_2_R_out : std_logic;
signal UART_3_W_in, UART_3_W_out, UART_3_R_in, UART_3_R_out : std_logic;
-- IJTAG-related signals
signal SO_NoC , SO_sensors , SO_RAM : std_logic;
signal toF_NoC, toF_sensors, toF_RAM : std_logic;
signal toC_NoC, toC_sensors, toC_RAM : std_logic;
signal SIB_RAM_toSI, SIB_RAM_toTCK, SIB_RAM_toRST, SIB_RAM_toSEL, SIB_RAM_toUE, SIB_RAM_toSE, SIB_RAM_toCE : std_logic;
signal RAM0_SO, RAM1_SO, RAM2_SO, RAM3_SO : std_logic;
signal RAM0_write_enable, RAM1_write_enable, RAM2_write_enable, RAM3_write_enable : std_logic;
signal RAM0_address, RAM1_address, RAM2_address, RAM3_address : std_logic_vector(RAMAddrSize-1 downto 0);
signal IJTAG_ram_0_select : std_logic;
signal IJTAG_ram_0_clk : std_logic;
signal IJTAG_ram_0_reset : std_logic;
signal IJTAG_ram_0_enable : std_logic;
signal IJTAG_ram_0_write_byte_enable : std_logic_vector(3 downto 0);
signal IJTAG_ram_0_address : std_logic_vector(31 downto 2);
signal IJTAG_ram_0_data_write : std_logic_vector(31 downto 0);
signal IJTAG_ram_0_data_read : std_logic_vector(31 downto 0);
signal IJTAG_ram_1_select : std_logic;
signal IJTAG_ram_1_clk : std_logic;
signal IJTAG_ram_1_reset : std_logic;
signal IJTAG_ram_1_enable : std_logic;
signal IJTAG_ram_1_write_byte_enable : std_logic_vector(3 downto 0);
signal IJTAG_ram_1_address : std_logic_vector(31 downto 2);
signal IJTAG_ram_1_data_write : std_logic_vector(31 downto 0);
signal IJTAG_ram_1_data_read : std_logic_vector(31 downto 0);
signal IJTAG_ram_2_select : std_logic;
signal IJTAG_ram_2_clk : std_logic;
signal IJTAG_ram_2_reset : std_logic;
signal IJTAG_ram_2_enable : std_logic;
signal IJTAG_ram_2_write_byte_enable : std_logic_vector(3 downto 0);
signal IJTAG_ram_2_address : std_logic_vector(31 downto 2);
signal IJTAG_ram_2_data_write : std_logic_vector(31 downto 0);
signal IJTAG_ram_2_data_read : std_logic_vector(31 downto 0);
signal IJTAG_ram_3_select : std_logic;
signal IJTAG_ram_3_clk : std_logic;
signal IJTAG_ram_3_reset : std_logic;
signal IJTAG_ram_3_enable : std_logic;
signal IJTAG_ram_3_write_byte_enable : std_logic_vector(3 downto 0);
signal IJTAG_ram_3_address : std_logic_vector(31 downto 2);
signal IJTAG_ram_3_data_write : std_logic_vector(31 downto 0);
signal IJTAG_ram_3_data_read : std_logic_vector(31 downto 0);
begin
-- instantiating the network
NoC: network_2x2 generic map (DATA_WIDTH => 32, DATA_WIDTH_LV => 11)
port map (reset, clk,
RX_L_0, credit_out_L_0, valid_out_L_0, credit_in_L_0, valid_in_L_0, TX_L_0,
RX_L_1, credit_out_L_1, valid_out_L_1, credit_in_L_1, valid_in_L_1, TX_L_1,
RX_L_2, credit_out_L_2, valid_out_L_2, credit_in_L_2, valid_in_L_2, TX_L_2,
RX_L_3, credit_out_L_3, valid_out_L_3, credit_in_L_3, valid_in_L_3, TX_L_3,
link_faults_0, turn_faults_0, Rxy_reconf_PE_0, Cx_reconf_PE_0, Reconfig_command_0,
link_faults_1, turn_faults_1, Rxy_reconf_PE_1, Cx_reconf_PE_1, Reconfig_command_1,
link_faults_2, turn_faults_2, Rxy_reconf_PE_2, Cx_reconf_PE_2, Reconfig_command_2,
link_faults_3, turn_faults_3, Rxy_reconf_PE_3, Cx_reconf_PE_3, Reconfig_command_3,
TCK, RST, SEL, SO_sensors, SE, UE, CE, SO_NoC, toF_NoC, toC_NoC
);
process (not_reset, clk)
begin
if not_reset = '1' then
GPIO_out_FF <= (others => '0');
UART_0_W_out <= '0';
UART_1_W_out <= '0';
UART_2_W_out <= '0';
UART_3_W_out <= '0';
UART_0_R_out <= '0';
UART_1_R_out <= '0';
UART_2_R_out <= '0';
UART_3_R_out <= '0';
elsif clk'event and clk = '1' then
GPIO_out_FF <= GPIO_out_FF_in;
UART_0_W_out <= UART_0_W_in;
UART_1_W_out <= UART_1_W_in;
UART_2_W_out <= UART_2_W_in;
UART_3_W_out <= UART_3_W_in;
UART_0_R_out <= UART_0_R_in;
UART_1_R_out <= UART_1_R_in;
UART_2_R_out <= UART_2_R_in;
UART_3_R_out <= UART_3_R_in;
end if;
end process;
GPIO_out <= GPIO_out_FF;
uart_write_0 <= UART_0_W_out;
uart_write_1 <= UART_1_W_out;
uart_write_2 <= UART_2_W_out;
uart_write_3 <= UART_3_W_out;
UART_0_R_in <= uart_read_0;
UART_1_R_in <= uart_read_1;
UART_2_R_in <= uart_read_2;
UART_3_R_in <= uart_read_3;
not_reset <= not reset;
-- instantiating and connecting the PEs
PE_0: NoC_Node
generic map( current_address => 0,
stim_file => path & "code_0.txt",
log_file => path & "output_0.txt",
memory_type => memory_type)
port map( not_reset, clk,
uart_read => UART_0_R_out,
uart_write => UART_0_W_in,
credit_in => credit_out_L_0,
valid_out => valid_in_L_0,
TX => RX_L_0,
credit_out => credit_in_L_0,
valid_in => valid_out_L_0,
RX => TX_L_0,
link_faults => link_faults_0,
turn_faults => turn_faults_0,
Rxy_reconf_PE => Rxy_reconf_PE_0,
Cx_reconf_PE => Cx_reconf_PE_0,
Reconfig_command => Reconfig_command_0,
GPIO_out => GPIO_out_FF_in,
GPIO_in => GPIO_in,
IJTAG_select => IJTAG_ram_0_select,
IJTAG_clk => IJTAG_ram_0_clk,
IJTAG_reset => IJTAG_ram_0_reset,
IJTAG_enable => IJTAG_ram_0_enable,
IJTAG_write_byte_enable => IJTAG_ram_0_write_byte_enable,
IJTAG_address => IJTAG_ram_0_address,
IJTAG_data_write => IJTAG_ram_0_data_write,
IJTAG_data_read => IJTAG_ram_0_data_read
);
PE_1: NoC_Node
generic map( current_address => 1,
stim_file => path & "code_1.txt",
log_file => path & "output_1.txt",
memory_type => memory_type)
port map( not_reset, clk,
uart_read => UART_1_R_out,
uart_write => UART_1_W_in,
credit_in => credit_out_L_1,
valid_out => valid_in_L_1,
TX => RX_L_1,
credit_out => credit_in_L_1,
valid_in => valid_out_L_1,
RX => TX_L_1,
link_faults => link_faults_1,
turn_faults => turn_faults_1,
Rxy_reconf_PE => Rxy_reconf_PE_1,
Cx_reconf_PE => Cx_reconf_PE_1,
Reconfig_command => Reconfig_command_1,
GPIO_out => open,
GPIO_in => (others => '0'),
IJTAG_select => IJTAG_ram_1_select,
IJTAG_clk => IJTAG_ram_1_clk,
IJTAG_reset => IJTAG_ram_1_reset,
IJTAG_enable => IJTAG_ram_1_enable,
IJTAG_write_byte_enable => IJTAG_ram_1_write_byte_enable,
IJTAG_address => IJTAG_ram_1_address,
IJTAG_data_write => IJTAG_ram_1_data_write,
IJTAG_data_read => IJTAG_ram_1_data_read
);
PE_2: NoC_Node
generic map( current_address => 2,
stim_file => path & "code_2.txt",
log_file => path & "output_2.txt",
memory_type => memory_type)
port map( not_reset, clk,
uart_read => UART_2_R_out,
uart_write => UART_2_W_in,
credit_in => credit_out_L_2,
valid_out => valid_in_L_2,
TX => RX_L_2,
credit_out => credit_in_L_2,
valid_in => valid_out_L_2,
RX => TX_L_2,
link_faults => link_faults_2,
turn_faults => turn_faults_2,
Rxy_reconf_PE => Rxy_reconf_PE_2,
Cx_reconf_PE => Cx_reconf_PE_2,
Reconfig_command => Reconfig_command_2,
GPIO_out => open,
GPIO_in => (others => '0'),
IJTAG_select => IJTAG_ram_2_select,
IJTAG_clk => IJTAG_ram_2_clk,
IJTAG_reset => IJTAG_ram_2_reset,
IJTAG_enable => IJTAG_ram_2_enable,
IJTAG_write_byte_enable => IJTAG_ram_2_write_byte_enable,
IJTAG_address => IJTAG_ram_2_address,
IJTAG_data_write => IJTAG_ram_2_data_write,
IJTAG_data_read => IJTAG_ram_2_data_read
);
PE_3: NoC_Node
generic map( current_address => 3,
stim_file => path & "code_3.txt",
log_file => path & "output_3.txt",
memory_type => memory_type)
port map( not_reset, clk,
uart_read => UART_3_R_out,
uart_write => UART_3_W_in,
credit_in => credit_out_L_3,
valid_out => valid_in_L_3,
TX => RX_L_3,
credit_out => credit_in_L_3,
valid_in => valid_out_L_3,
RX => TX_L_3,
link_faults => link_faults_3,
turn_faults => turn_faults_3,
Rxy_reconf_PE => Rxy_reconf_PE_3,
Cx_reconf_PE => Cx_reconf_PE_3,
Reconfig_command => Reconfig_command_3,
GPIO_out => open,
GPIO_in => (others => '0'),
IJTAG_select => IJTAG_ram_3_select,
IJTAG_clk => IJTAG_ram_3_clk,
IJTAG_reset => IJTAG_ram_3_reset,
IJTAG_enable => IJTAG_ram_3_enable,
IJTAG_write_byte_enable => IJTAG_ram_3_write_byte_enable,
IJTAG_address => IJTAG_ram_3_address,
IJTAG_data_write => IJTAG_ram_3_data_write,
IJTAG_data_read => IJTAG_ram_3_data_read
);
-------------------------------------------
------- IJTAG stuff -----------------------
-------------------------------------------
-- Organization of IJTAG network (top level):
-- .----------. .-----------. .----------.
-- SI ----| sib_ram |---| sib_sens |---| sib_noc |-- SO
-- '----------' '-----------' '----------'
-- | |_________________________________________________.
-- | |
-- | .-----------. .-----------. .-----------. .-----------. |
-- '-| sib_ram_0 |-| sib_ram_1 |-| sib_ram_2 |-| sib_ram_3 |-'
-- '-----------' '-----------' '-----------' '-----------'
toF <= toF_NoC or toF_sensors;
toC <= toC_NoC and toC_sensors;
SO <= SO_NoC;
IJTAG_ram_0_enable <= '1';
IJTAG_ram_1_enable <= '1';
IJTAG_ram_2_enable <= '1';
IJTAG_ram_3_enable <= '1';
IJTAG_ram_0_clk <= TCK;
IJTAG_ram_1_clk <= TCK;
IJTAG_ram_2_clk <= TCK;
IJTAG_ram_3_clk <= TCK;
IJTAG_ram_0_reset <= RST;
IJTAG_ram_1_reset <= RST;
IJTAG_ram_2_reset <= RST;
IJTAG_ram_3_reset <= RST;
-- RAM Access SIB
SIB_RAM : SIB_mux_pre_FCX_SELgate
port map ( -- Scan Interface client --------------
SI => SI,
CE => CE,
SE => SE,
UE => UE,
SEL => SEL,
RST => RST,
TCK => TCK,
SO => SO_RAM,
toF => toF_RAM,
toC => toC_RAM,
-- Scan Interface host ----------------
fromSO => RAM3_SO,
toCE => SIB_RAM_toCE,
toSE => SIB_RAM_toSE,
toUE => SIB_RAM_toUE,
toSEL => SIB_RAM_toSEL,
toRST => SIB_RAM_toRST,
toTCK => SIB_RAM_toTCK,
toSI => SIB_RAM_toSI,
fromF => '0',
fromC => '1'
);
-- RAM Access instruments
RAM_instr0 : RAMAccessInstrument
generic map ( DataSize => RAMDataSize,
AddressSize => RAMAddrSize)
port map ( SI => SIB_RAM_toSI,
SO => RAM0_SO,
SEL => SIB_RAM_toSEL,
SE => SIB_RAM_toSE,
CE => SIB_RAM_toCE,
UE => SIB_RAM_toUE,
RST => SIB_RAM_toRST,
TCK => SIB_RAM_toTCK,
MEM_SIB_SEL => IJTAG_ram_0_select,
RAM_data_read => IJTAG_ram_0_data_read,
RAM_data_write => IJTAG_ram_0_data_write,
RAM_address_out => RAM0_address,
RAM_write_enable => RAM0_write_enable);
IJTAG_ram_0_write_byte_enable <= (others => RAM0_write_enable);
IJTAG_ram_0_address <= "000000000000000000" & RAM0_address;
RAM_instr1 : RAMAccessInstrument
generic map ( DataSize => RAMDataSize,
AddressSize => RAMAddrSize)
port map ( SI => RAM0_SO,
SO => RAM1_SO,
SEL => SIB_RAM_toSEL,
SE => SIB_RAM_toSE,
CE => SIB_RAM_toCE,
UE => SIB_RAM_toUE,
RST => SIB_RAM_toRST,
TCK => SIB_RAM_toTCK,
MEM_SIB_SEL => IJTAG_ram_1_select,
RAM_data_read => IJTAG_ram_1_data_read,
RAM_data_write => IJTAG_ram_1_data_write,
RAM_address_out => RAM1_address,
RAM_write_enable => RAM1_write_enable);
IJTAG_ram_1_write_byte_enable <= (others => RAM1_write_enable);
IJTAG_ram_1_address <= "000000000000000000" & RAM1_address;
RAM_instr2 : RAMAccessInstrument
generic map ( DataSize => RAMDataSize,
AddressSize => RAMAddrSize)
port map ( SI => RAM1_SO,
SO => RAM2_SO,
SEL => SIB_RAM_toSEL,
SE => SIB_RAM_toSE,
CE => SIB_RAM_toCE,
UE => SIB_RAM_toUE,
RST => SIB_RAM_toRST,
TCK => SIB_RAM_toTCK,
MEM_SIB_SEL => IJTAG_ram_2_select,
RAM_data_read => IJTAG_ram_2_data_read,
RAM_data_write => IJTAG_ram_2_data_write,
RAM_address_out => RAM2_address,
RAM_write_enable => RAM2_write_enable);
IJTAG_ram_2_write_byte_enable <= (others => RAM2_write_enable);
IJTAG_ram_2_address <= "000000000000000000" & RAM2_address;
RAM_instr3 : RAMAccessInstrument
generic map ( DataSize => RAMDataSize,
AddressSize => RAMAddrSize)
port map ( SI => RAM2_SO,
SO => RAM3_SO,
SEL => SIB_RAM_toSEL,
SE => SIB_RAM_toSE,
CE => SIB_RAM_toCE,
UE => SIB_RAM_toUE,
RST => SIB_RAM_toRST,
TCK => SIB_RAM_toTCK,
MEM_SIB_SEL => IJTAG_ram_3_select,
RAM_data_read => IJTAG_ram_3_data_read,
RAM_data_write => IJTAG_ram_3_data_write,
RAM_address_out => RAM3_address,
RAM_write_enable => RAM3_write_enable);
IJTAG_ram_3_write_byte_enable <= (others => RAM3_write_enable);
IJTAG_ram_3_address <= "000000000000000000" & RAM3_address;
-- IMMORTAL sensors interface
immortal_sensors: immortal_sensor_IJTAG_interface
port map (
TCK => TCK,
RST => RST,
SEL => SEL,
SI => SO_RAM,
SE => SE,
UE => UE,
CE => CE,
SO => SO_sensors,
toF => toF_sensors,
toC => toC_sensors,
temperature_control => temperature_control,
temperature_data => temperature_data,
iddt_control => iddt_control,
iddt_data => iddt_data,
slack_control => slack_control,
slack_data => slack_data,
voltage_control => voltage_control,
voltage_data => voltage_data
);
temperature_data <= (others => '0');
iddt_data <= (others => '0');
end;
|
--This should pass
context c1 is
end context c1;
--These should fail
context c1 is
end context c1;
context
c1
is
end
context -- Some comment
c1;
-- Comment
context c1 is
end -- Some comment
context c1; -- Some other comment
-- other comments
context c1 -- Yet another commet
-- Some comment
is
end
-- Comment again
context
c1; -- Comment
-- Comment
-- Comment
-- Test with missing end context keyword
context c1 is
end;
context c1 is
end context;
context c1 is
end context c1;
|
library ieee;
use ieee.std_logic_1164.all;
entity fifo is
generic(
width : integer;
depth : integer
);
port(
clk : in std_logic;
rst : in std_logic;
input : in std_logic_vector(width-1 downto 0);
input_stb : in std_logic;
input_ack : out std_logic;
output : out std_logic_vector(width-1 downto 0);
output_stb : out std_logic;
output_ack : in std_logic
);
end entity fifo;
architecture rtl of fifo is
signal s_output_stb, s_input_ack, full, empty, read, write : std_logic;
signal a_out, a_in : integer range 0 to depth - 1 := 0;
type memory_type is array (0 to depth - 1) of std_logic_vector(width -1 downto 0);
signal memory : memory_type;
begin
process
begin
wait until rising_edge(clk);
if write = '1' then
memory(a_in) <= input;
end if;
if read = '1' then
output <= memory(a_out);
end if;
end process;
process
begin
wait until rising_edge(clk);
s_output_stb <= '0';
if read = '1' then
--data is available on clock following read
s_output_stb <= '1';
if a_out = (depth - 1) then
a_out <= 0;
else
a_out <= a_out + 1;
end if;
end if;
--if data has not been read, extend strobe
if s_output_stb = '1' and output_ack = '0' then
s_output_stb <= '1';
end if;
if write = '1' then
if a_in = (depth - 1) then
a_in <= 0;
else
a_in <= a_in + 1;
end if;
end if;
if rst = '1' then
a_out <= 0;
a_in <= 0;
s_output_stb <= '0';
end if;
end process;
full <= '1' when (a_out-1) = a_in else
'1' when (a_out = 0) and (a_in = depth - 1) else
'0';
empty <= '1' when a_out = a_in else '0';
s_input_ack <= not full;
output_stb <= s_output_stb;
input_ack <= s_input_ack;
write <= s_input_ack and input_stb;
read <= ((not s_output_stb) or output_ack) and (not empty);
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
entity fifo is
generic(
width : integer;
depth : integer
);
port(
clk : in std_logic;
rst : in std_logic;
input : in std_logic_vector(width-1 downto 0);
input_stb : in std_logic;
input_ack : out std_logic;
output : out std_logic_vector(width-1 downto 0);
output_stb : out std_logic;
output_ack : in std_logic
);
end entity fifo;
architecture rtl of fifo is
signal s_output_stb, s_input_ack, full, empty, read, write : std_logic;
signal a_out, a_in : integer range 0 to depth - 1 := 0;
type memory_type is array (0 to depth - 1) of std_logic_vector(width -1 downto 0);
signal memory : memory_type;
begin
process
begin
wait until rising_edge(clk);
if write = '1' then
memory(a_in) <= input;
end if;
if read = '1' then
output <= memory(a_out);
end if;
end process;
process
begin
wait until rising_edge(clk);
s_output_stb <= '0';
if read = '1' then
--data is available on clock following read
s_output_stb <= '1';
if a_out = (depth - 1) then
a_out <= 0;
else
a_out <= a_out + 1;
end if;
end if;
--if data has not been read, extend strobe
if s_output_stb = '1' and output_ack = '0' then
s_output_stb <= '1';
end if;
if write = '1' then
if a_in = (depth - 1) then
a_in <= 0;
else
a_in <= a_in + 1;
end if;
end if;
if rst = '1' then
a_out <= 0;
a_in <= 0;
s_output_stb <= '0';
end if;
end process;
full <= '1' when (a_out-1) = a_in else
'1' when (a_out = 0) and (a_in = depth - 1) else
'0';
empty <= '1' when a_out = a_in else '0';
s_input_ack <= not full;
output_stb <= s_output_stb;
input_ack <= s_input_ack;
write <= s_input_ack and input_stb;
read <= ((not s_output_stb) or output_ack) and (not empty);
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
entity fifo is
generic(
width : integer;
depth : integer
);
port(
clk : in std_logic;
rst : in std_logic;
input : in std_logic_vector(width-1 downto 0);
input_stb : in std_logic;
input_ack : out std_logic;
output : out std_logic_vector(width-1 downto 0);
output_stb : out std_logic;
output_ack : in std_logic
);
end entity fifo;
architecture rtl of fifo is
signal s_output_stb, s_input_ack, full, empty, read, write : std_logic;
signal a_out, a_in : integer range 0 to depth - 1 := 0;
type memory_type is array (0 to depth - 1) of std_logic_vector(width -1 downto 0);
signal memory : memory_type;
begin
process
begin
wait until rising_edge(clk);
if write = '1' then
memory(a_in) <= input;
end if;
if read = '1' then
output <= memory(a_out);
end if;
end process;
process
begin
wait until rising_edge(clk);
s_output_stb <= '0';
if read = '1' then
--data is available on clock following read
s_output_stb <= '1';
if a_out = (depth - 1) then
a_out <= 0;
else
a_out <= a_out + 1;
end if;
end if;
--if data has not been read, extend strobe
if s_output_stb = '1' and output_ack = '0' then
s_output_stb <= '1';
end if;
if write = '1' then
if a_in = (depth - 1) then
a_in <= 0;
else
a_in <= a_in + 1;
end if;
end if;
if rst = '1' then
a_out <= 0;
a_in <= 0;
s_output_stb <= '0';
end if;
end process;
full <= '1' when (a_out-1) = a_in else
'1' when (a_out = 0) and (a_in = depth - 1) else
'0';
empty <= '1' when a_out = a_in else '0';
s_input_ack <= not full;
output_stb <= s_output_stb;
input_ack <= s_input_ack;
write <= s_input_ack and input_stb;
read <= ((not s_output_stb) or output_ack) and (not empty);
end rtl;
|
entity FIFO is
port (
I_WR_EN : in std_logic;
I_DATA : out std_logic_vector(31 downto 0);
I_RD_EN : in std_logic;
O_DATA : out std_logic_vector(31 downto 0)
);
end entity FIFO;
entity FIFO is
port (
I_WR_EN : in std_logic;
I_DATA : out std_logic_vector(31 downto 0);
I_RD_EN : in std_logic;
O_DATA : out std_logic_vector(31 downto 0))
;
end entity FIFO;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_01 is
end entity inline_01;
----------------------------------------------------------------
architecture test of inline_01 is
type MVL4_ulogic is ('X', '0', '1', 'Z'); -- unresolved logic type
-- code from book:
type small_int is range 1 to 4;
type small_array is array (small_int range <>) of -- . . . ;
-- not in book
MVL4_ulogic;
-- end not in book
-- end of code from book
type table is array (MVL4_ulogic, MVL4_ulogic) of MVL4_ulogic;
constant resolution_table : table :=
-- 'X' '0' '1' 'Z'
-- ------------------
( ( 'X', 'X', 'X', 'X' ), -- 'X'
( 'X', '0', 'X', '0' ), -- '0'
( 'X', 'X', '1', '1' ), -- '1'
( 'X', '0', '1', 'Z' ) ); -- 'Z'
function resolve_MVL4 ( contribution : small_array ) return MVL4_ulogic is
variable result : MVL4_ulogic := 'Z';
begin
for index in contribution'range loop
result := resolution_table(result, contribution(index));
end loop;
return result;
end function resolve_MVL4;
subtype MVL4_logic is resolve_MVL4 MVL4_ulogic;
signal s : MVL4_logic;
begin
driver_1 : s <= 'Z';
driver_2 : s <= 'Z';
driver_3 : s <= 'Z';
driver_4 : s <= 'Z';
driver_5 : s <= 'Z';
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_01 is
end entity inline_01;
----------------------------------------------------------------
architecture test of inline_01 is
type MVL4_ulogic is ('X', '0', '1', 'Z'); -- unresolved logic type
-- code from book:
type small_int is range 1 to 4;
type small_array is array (small_int range <>) of -- . . . ;
-- not in book
MVL4_ulogic;
-- end not in book
-- end of code from book
type table is array (MVL4_ulogic, MVL4_ulogic) of MVL4_ulogic;
constant resolution_table : table :=
-- 'X' '0' '1' 'Z'
-- ------------------
( ( 'X', 'X', 'X', 'X' ), -- 'X'
( 'X', '0', 'X', '0' ), -- '0'
( 'X', 'X', '1', '1' ), -- '1'
( 'X', '0', '1', 'Z' ) ); -- 'Z'
function resolve_MVL4 ( contribution : small_array ) return MVL4_ulogic is
variable result : MVL4_ulogic := 'Z';
begin
for index in contribution'range loop
result := resolution_table(result, contribution(index));
end loop;
return result;
end function resolve_MVL4;
subtype MVL4_logic is resolve_MVL4 MVL4_ulogic;
signal s : MVL4_logic;
begin
driver_1 : s <= 'Z';
driver_2 : s <= 'Z';
driver_3 : s <= 'Z';
driver_4 : s <= 'Z';
driver_5 : s <= 'Z';
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_01 is
end entity inline_01;
----------------------------------------------------------------
architecture test of inline_01 is
type MVL4_ulogic is ('X', '0', '1', 'Z'); -- unresolved logic type
-- code from book:
type small_int is range 1 to 4;
type small_array is array (small_int range <>) of -- . . . ;
-- not in book
MVL4_ulogic;
-- end not in book
-- end of code from book
type table is array (MVL4_ulogic, MVL4_ulogic) of MVL4_ulogic;
constant resolution_table : table :=
-- 'X' '0' '1' 'Z'
-- ------------------
( ( 'X', 'X', 'X', 'X' ), -- 'X'
( 'X', '0', 'X', '0' ), -- '0'
( 'X', 'X', '1', '1' ), -- '1'
( 'X', '0', '1', 'Z' ) ); -- 'Z'
function resolve_MVL4 ( contribution : small_array ) return MVL4_ulogic is
variable result : MVL4_ulogic := 'Z';
begin
for index in contribution'range loop
result := resolution_table(result, contribution(index));
end loop;
return result;
end function resolve_MVL4;
subtype MVL4_logic is resolve_MVL4 MVL4_ulogic;
signal s : MVL4_logic;
begin
driver_1 : s <= 'Z';
driver_2 : s <= 'Z';
driver_3 : s <= 'Z';
driver_4 : s <= 'Z';
driver_5 : s <= 'Z';
end architecture test;
|
library verilog;
use verilog.vl_types.all;
entity Multiple_Cycles_CPU is
port(
Clk : in vl_logic;
PC_in : out vl_logic_vector(31 downto 0);
PC_out : out vl_logic_vector(31 downto 0);
Mem_addr_in : out vl_logic_vector(31 downto 0);
Mem_data_out : out vl_logic_vector(31 downto 0);
IR_out : out vl_logic_vector(31 downto 0);
AddrReg_out : out vl_logic_vector(31 downto 0);
Mem_data_shift : out vl_logic_vector(31 downto 0);
Reg_data_shift : out vl_logic_vector(31 downto 0);
Shift_out : out vl_logic_vector(31 downto 0);
A_in : out vl_logic_vector(31 downto 0);
B_in : out vl_logic_vector(31 downto 0);
ALU_out : out vl_logic_vector(31 downto 0);
ALUShift_out : out vl_logic_vector(31 downto 0);
Rs_out : out vl_logic_vector(31 downto 0);
Rt_out : out vl_logic_vector(31 downto 0);
Rd_in : out vl_logic_vector(31 downto 0);
Rt_addr : out vl_logic_vector(4 downto 0);
Rd_addr : out vl_logic_vector(4 downto 0);
Rs_addr : out vl_logic_vector(4 downto 0);
condition : out vl_logic_vector(2 downto 0);
ALU_SrcB : out vl_logic_vector(2 downto 0);
ALU_op : out vl_logic_vector(3 downto 0);
Rd_write_byte_en: out vl_logic_vector(3 downto 0);
Mem_byte_write : out vl_logic_vector(3 downto 0);
RegDst : out vl_logic_vector(1 downto 0);
MemtoReg : out vl_logic_vector(1 downto 0);
PC_source : out vl_logic_vector(1 downto 0);
Shift_op : out vl_logic_vector(1 downto 0);
ALU_SrcA : out vl_logic;
Ex_top : out vl_logic;
Shift_amountSrc : out vl_logic;
ALUShift_Sel : out vl_logic;
PC_write_cond : out vl_logic;
PC_write_en : out vl_logic;
IorD : out vl_logic;
IR_write_en : out vl_logic;
Addreg_write_en : out vl_logic;
Zero : out vl_logic;
Less : out vl_logic;
Overflow : out vl_logic;
PC_write : out vl_logic;
state : out vl_logic_vector(3 downto 0);
RegDt0 : out vl_logic
);
end Multiple_Cycles_CPU;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (lin64) Build 1756540 Mon Jan 23 19:11:19 MST 2017
-- Date : Sun Mar 26 22:18:09 2017
-- Host : andrewandrepowell2-desktop running 64-bit Ubuntu 16.04 LTS
-- Command : write_vhdl -force -mode synth_stub -rename_top mig_wrap_auto_cc_0 -prefix
-- mig_wrap_auto_cc_0_ mig_wrap_auto_cc_0_stub.vhdl
-- Design : mig_wrap_auto_cc_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a100tcsg324-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mig_wrap_auto_cc_0 is
Port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_aclk : in STD_LOGIC;
m_axi_aresetn : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end mig_wrap_auto_cc_0;
architecture stub of mig_wrap_auto_cc_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "s_axi_aclk,s_axi_aresetn,s_axi_awid[3:0],s_axi_awaddr[31:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awregion[3:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[3:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[3:0],s_axi_araddr[31:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arregion[3:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[3:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_aclk,m_axi_aresetn,m_axi_awid[3:0],m_axi_awaddr[31:0],m_axi_awlen[7:0],m_axi_awsize[2:0],m_axi_awburst[1:0],m_axi_awlock[0:0],m_axi_awcache[3:0],m_axi_awprot[2:0],m_axi_awregion[3:0],m_axi_awqos[3:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wlast,m_axi_wvalid,m_axi_wready,m_axi_bid[3:0],m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_arid[3:0],m_axi_araddr[31:0],m_axi_arlen[7:0],m_axi_arsize[2:0],m_axi_arburst[1:0],m_axi_arlock[0:0],m_axi_arcache[3:0],m_axi_arprot[2:0],m_axi_arregion[3:0],m_axi_arqos[3:0],m_axi_arvalid,m_axi_arready,m_axi_rid[3:0],m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rlast,m_axi_rvalid,m_axi_rready";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "axi_clock_converter_v2_1_10_axi_clock_converter,Vivado 2016.4";
begin
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: dmactrl
-- File: dmactrl.vhd
-- Author: Alf Vaerneus - Gaisler Research
-- Modified: Nils-Johan Wessman - Gaisler Research
-- Description: Simple DMA controller
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.pci.all;
entity dmactrl is
generic (
hindex : integer := 0;
slvindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
blength : integer := 4
);
port (
rst : in std_logic;
clk : in std_logic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbsi0 : in ahb_slv_in_type;
ahbso0 : out ahb_slv_out_type;
ahbsi1 : out ahb_slv_in_type;
ahbso1 : in ahb_slv_out_type
);
end;
architecture rtl of dmactrl is
constant BURST_LENGTH : integer := blength;
constant REVISION : integer := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_DMACTRL, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
type state_type is(idle, read1, read2, read3, read4, read5, write1, write2, writeb, write3, write4, turn);
type rbuf_type is array (0 to 2) of std_logic_vector(31 downto 0);
type dmactrl_reg_type is record
state : state_type;
addr0 : std_logic_vector(31 downto 2);
addr1 : std_logic_vector(31 downto 2);
hmbsel : std_logic_vector(0 to NAHBAMR-1);
htrans : std_logic_vector(1 downto 0);
rbuf : rbuf_type;
write : std_logic;
start_req : std_logic;
start : std_logic;
ready : std_logic;
err : std_logic;
first0 : std_logic;
first1 : std_logic;
no_ws : std_logic; -- no wait states
blimit : std_logic; -- 1k limit
dmao_start: std_logic;
dmao_ready: std_logic; -- sets if ready responce in read4, not set two_in_buf if retry on second access in buf
two_in_buf: std_logic; -- two words in rbuf to be stored
burstl_p : std_logic_vector(BURST_LENGTH - 1 downto 0); -- pci access counter
burstl_a : std_logic_vector(BURST_LENGTH - 1 downto 0); -- amba access counter
ahb0_htrans : std_logic_vector(1 downto 0);
ahb0_hresp : std_logic_vector(1 downto 0);
ahb0_hready : std_logic;
ahb0_retry : std_logic;
ahb0_hsel : std_logic;
start_del : std_logic;
end record;
signal r,rin : dmactrl_reg_type;
signal dmai : pci_ahb_dma_in_type;
signal dmao : pci_ahb_dma_out_type;
begin
comb : process(rst,r,dmao,apbi,ahbsi0,ahbso1)
variable v : dmactrl_reg_type;
variable vdmai : pci_ahb_dma_in_type;
variable pdata : std_logic_vector(31 downto 0);
variable slvbusy : ahb_slv_out_type;
variable dma_done, pci_done : std_logic;
variable bufloc : integer range 0 to 2;
begin
slvbusy := ahbso1; v := r;
vdmai.burst := '1'; vdmai.address := r.addr0 & "00";
vdmai.write := not r.write; vdmai.start := '0'; vdmai.size := "10";
vdmai.wdata := r.rbuf(0); pdata := (others => '0');
vdmai.busy := '0'; vdmai.irq := '0';
bufloc := 0;
v.start_del := r.start;
--slvbusy.hready := '1'; slvbusy.hindex := hindex; --slvbusy.hresp := "00";
--v.ahb0_htrans := ahbsi0.htrans; v.ahb0_retry := '0';
--v.ahb0_hsel := ahbsi0.hsel(slvindex); v.ahb0_hready := ahbsi0.hready;
v.ahb0_hready := '1'; v.ahb0_hresp := HRESP_OKAY; v.ahb0_retry := '0';
slvbusy.hready := r.ahb0_hready; slvbusy.hresp := r.ahb0_hresp;
-- AMBA busy response when dma is running
--if r.ahb0_retry = '1' then slvbusy.hresp := "10";
--else slvbusy.hresp := "00"; end if;
if r.ahb0_retry = '1' then v.ahb0_hresp := HRESP_RETRY; end if;
--if r.ahb0_htrans = "10" and (r.start = '1') and r.ahb0_hsel = '1' and r.ahb0_hready = '1' then
-- slvbusy.hready := '0';
-- slvbusy.hresp := "10";
-- v.ahb0_retry := '1';
--end if;
if ahbsi0.htrans = "10" and (r.start = '1') and ahbsi0.hsel(slvindex) = '1' and ahbsi0.hready = '1' then
v.ahb0_hready := '0';
v.ahb0_hresp := HRESP_RETRY;
v.ahb0_retry := '1';
end if;
-- Done signals
if (r.burstl_a(BURST_LENGTH - 1 downto 1) = zero32(BURST_LENGTH - 1 downto 1)) then -- AMBA access done
dma_done := '1'; else dma_done := '0'; end if;
if (r.burstl_p(BURST_LENGTH - 1 downto 1) = zero32(BURST_LENGTH - 1 downto 1)) then -- PCI access done
pci_done := '1'; else pci_done := '0'; end if;
-- APB interface
if (apbi.psel(pindex) and apbi.penable) = '1' then
case apbi.paddr(4 downto 2) is
when "000" =>
if apbi.pwrite = '1' then
v.start_req := apbi.pwdata(0);
v.write := apbi.pwdata(1);
v.ready := r.ready and not apbi.pwdata(2);
v.err := r.err and not apbi.pwdata(3);
v.hmbsel := apbi.pwdata(7 downto 4);
end if;
pdata := zero32(31 downto 8) & r.hmbsel & r.err & r.ready & r.write & r.start_req;
when "001" =>
if apbi.pwrite = '1' then v.addr0 := apbi.pwdata(31 downto 2); end if;
pdata := r.addr0 & "00";
when "010" =>
if apbi.pwrite = '1' then v.addr1 := apbi.pwdata(31 downto 2); end if;
pdata := r.addr1 & "00";
when "011" =>
if apbi.pwrite = '1' then
v.burstl_p := apbi.pwdata(BURST_LENGTH - 1 downto 0);
v.burstl_a := apbi.pwdata(BURST_LENGTH - 1 downto 0);
end if;
pdata := zero32(31 downto BURST_LENGTH) & r.burstl_p;
when others =>
end case;
end if;
-- can't start dma until AMBA slave is idle
if r.start_req = '1' and (ahbsi0.hready = '1' and (ahbsi0.htrans = "00" or ahbsi0.hsel(slvindex) = '0')) then
v.start := '1';
end if;
case r.state is
when idle =>
v.htrans := "00";
v.first0 := '1'; v.first1 := '1';
v.no_ws := '0'; v.dmao_start := '0'; v.blimit := '0';
if r.start = '1' then
if r.write = '0' then v.state := read1;
else v.state := write1; end if;
end if;
when read1 => -- Start PCI read
bufloc := 0;
v.htrans := "10";
if ahbso1.hready = '1' and ahbso1.hresp = HRESP_OKAY then
if r.htrans(1) = '1' then
if pci_done = '1' then
v.htrans := "00";
v.state := read5;
else
v.htrans := "11";
v.state := read2;
end if;
end if;
elsif ahbso1.hready = '0' then
v.htrans := "11";
else
v.htrans := "00";
end if;
when read2 => -- fill rbuf (3 words)
if r.first1 = '1' then bufloc := 1; -- store 3 words
else bufloc := 2; end if;
if ahbso1.hready = '1' and ahbso1.hresp = HRESP_OKAY then
--if r.htrans = "11" then
if r.htrans(1) = '1' then
v.first1 := '0';
if pci_done = '1' then
v.htrans := "00";
v.state := read5;
elsif r.first1 = '0' then
v.htrans := "01";
v.state := read3;
v.first0 := '1';
end if;
end if;
elsif ahbso1.hready = '0' and ahbso1.hresp = HRESP_RETRY then
v.htrans := "00";
else
if ahbso1.hresp = HRESP_RETRY then
v.htrans := "10";
else
v.htrans := "11";
end if;
end if;
when read3 => -- write to AMBA and read from PCI
vdmai.start := '1';
bufloc := 1;
if (dmao.ready and dmao.start) = '1' then bufloc := 1; v.no_ws := '1'; -- no wait state on AMBA ?
else
bufloc := 2;
if dmao.active = '1' then v.no_ws := '0'; end if;
end if;
if dmao.active = '0' then v.blimit := '1';
else v.blimit := '0'; end if;
if dmao.ready = '1' then
v.first0 := '0';
v.htrans := "11";
else
v.htrans := "01";
end if;
if r.htrans(1) = '1' and ahbso1.hready = '1' and ahbso1.hresp = HRESP_OKAY and pci_done = '1' then
v.state := read5;
v.htrans := "00";
elsif r.htrans(1) = '1' and ahbso1.hready = '0' and ahbso1.hresp = HRESP_RETRY then
if dmao.active = '0' then v.two_in_buf := '1'; end if; -- two words in rbuf to store
v.state := read4;
v.htrans := "01";
if bufloc = 2 then v.dmao_ready := '0'; end if;
end if;
when read4 => -- PCI retry
bufloc := 1;
--if dmao.ready = '1' then v.two_in_buf := '0'; end if;
if dmao.ready = '1' then v.two_in_buf := '0'; v.dmao_ready := '1'; end if;
if dmao.retry = '1' and r.dmao_ready = '0' then v.two_in_buf := '1'; end if; -- two words in rbuf if retry/split
if dmao.retry = '1' then v.dmao_start := '0'; end if; -- retry last word
if dmao.start = '1' and r.two_in_buf = '0' then v.dmao_start := '1'; end if;
if r.no_ws = '1' and r.dmao_start = '1' then vdmai.start := '0';
elsif dmao.start = '1' and r.two_in_buf = '0' then v.no_ws := '1'; vdmai.start := '0';
else vdmai.start := '1'; end if;
--if dmao.ready = '1' and r.no_ws = '1' and r.two_in_buf = '0' then -- handle change of waitstates (sdram refresh)
if (dmao.ready = '1' or (dmao.active = '0' and r.dmao_start = '1')) and r.no_ws = '1' and r.two_in_buf = '0' then
v.first0 := '1';
v.first1 := '1';
v.no_ws := '0';
v.dmao_start := '0';
v.state := read1;
end if;
when read5 => -- PCI read done
if dmao.start = '1' then v.first0 := '0'; -- first amba access
elsif dmao.active = '0' then v.first0 := '1'; end if; -- 1k limit
if dma_done = '0' or (r.first0 = '1' and dmao.start = '0') then vdmai.start := '1'; end if;
if (dmao.ready and dmao.start) = '1' then bufloc := 1; v.no_ws := '1'; -- no wait state on AMBA ?
else bufloc := 2; end if;
if dmao.ready = '1' and dma_done = '1' then
v.state := turn;
end if;
when write1 => -- Read first from AMBA
bufloc := 0;
v.first1 := '1'; v.no_ws := '0';
if dmao.start = '1' then v.first0 := '0'; -- first amba access
elsif dmao.active = '0' then v.first0 := '1'; end if; -- 1k limit
if dma_done = '1' and (r.first0 = '0' or dmao.start = '1') then vdmai.start := '0';
else vdmai.start := '1'; end if;
if dmao.ready = '1' then
if dma_done = '1' then v.state := write4;
else v.state := write2; end if;
v.htrans := "10"; -- start access to PCI
end if;
when write2 => -- Read from AMBA and write to PCI
bufloc := 0;
if (dmao.ready and dmao.start) = '1' then v.no_ws := '1'; end if; -- no wait state on AMBA ?
if dmao.start = '1' then v.first0 := '0'; -- first amba access
elsif dmao.active = '0' then v.first0 := '1'; end if; -- 1k limit
if dmao.ready = '1' then -- Data ready write to PCI
v.htrans := "11";
if dma_done = '1' then
v.state := write4;
end if;
else v.htrans := "01"; end if;
if ahbso1.hready = '0' then
vdmai.start := '0';
if v.no_ws = '1' then bufloc := 1; end if;
if dmao.active = '0' then v.state := writeb; -- AMBA 1k limit
else v.state := write3; v.dmao_ready := '1'; end if; -- assume ready responce, change later of retry/split
elsif dma_done = '0' or (r.first0 = '1' and dmao.start = '0') then
vdmai.start := '1';
end if;
when writeb => -- AMBA 1k limit and PCI retry
bufloc := 1;
if dmao.active = '1' then vdmai.start := '0';
else vdmai.start := '1'; end if;
if dmao.ready = '1' then v.state := write3; v.dmao_ready := '1'; end if;
when write3 => -- Retry from PCI
bufloc := 1;
--if ahbso1.hready = '1' then v.htrans := "10"; -- wait for AMBA access to be done before retry
--if (ahbso1.hready and (dmao.ready or not dmao.active)) = '1' then v.htrans := "10";
if (ahbso1.hready and (dmao.ready or (not dmao.active and r.dmao_ready))) = '1' then v.htrans := "10"; -- handle retry (don't start until ready)
else v.htrans := "01"; end if;
-- handle retry/split (restart access)
if dmao.retry = '1' then v.dmao_ready := '0';
elsif dmao.ready = '1' then v.dmao_ready := '1'; end if;
if r.dmao_ready = '0' and dmao.active = '0' then vdmai.start := '1';
else vdmai.start := '0'; end if;
if r.htrans(1) = '1' and ahbso1.hready = '1' and ahbso1.hresp = HRESP_OKAY then
if pci_done = '1' then
v.htrans := "00";
v.state := turn;
elsif dma_done = '1' and r.burstl_a(0) = '0' then
v.htrans := "01";
v.state := write4;
else
v.htrans := "11";
v.first0 := '1';
v.state := write2;
end if;
end if;
when write4 => -- Done read AMBA
v.htrans := "11";
if pci_done = '1' and ahbso1.hready = '1' and r.htrans(1) = '1' then
v.htrans := "00";
v.state := turn;
elsif ahbso1.hready = '0' then
v.state := write3;
v.htrans := "01";
v.dmao_ready := '1';
end if;
when turn =>
v.htrans := "00";
-- can't switch off dma until AMBA slave is idle
if (ahbsi0.hsel(slvindex) = '0' and r.ahb0_retry = '0' and ahbsi0.hready = '1')
or (ahbsi0.htrans = "00" and ahbsi0.hready = '1') or r.ahb0_retry = '1' then
v.ready := '1'; v.first1 := '1'; v.start_req := '0';
v.start := '0'; v.state := idle;
end if;
end case;
if ((r.htrans(1) and ahbso1.hready) = '1' and ahbso1.hresp = HRESP_OKAY) then -- PCI access done
v.burstl_p := r.burstl_p - '1'; -- dec counter
v.addr1 := r.addr1 + '1'; -- inc address (PCI)
if (r.write = '0' or r.state = write4 or r.state = write3) then
if r.state /= read1 and r.state /= read2 and (v.no_ws = '1' or r.state = write3) and v.blimit = '0' then
v.rbuf(0) := r.rbuf(1); -- dont update if wait states
v.rbuf(1) := r.rbuf(2); --
end if;
if r.write = '0' then v.rbuf(bufloc) := ahbreadword(ahbso1.hrdata); end if; -- PCI to AMBA
end if; -- if wait states store in buf(2) else
end if; -- in buf(1). Frist word in buf(0)
if dmao.ready = '1' then -- AMBA access done
v.burstl_a := r.burstl_a - '1'; -- dec counter
v.addr0 := r.addr0 + 1; -- inc address (AMBA master)
if r.write = '1' then
if r.state /= write3 and bufloc = 0 then -- dont update if retry from PCI
v.rbuf(0) := r.rbuf(1);
v.rbuf(1) := r.rbuf(2);
end if;
v.rbuf(bufloc) := dmao.rdata; -- AMBA to PCI
elsif r.write = '0' and (r.first0 = '1' or v.state = read4 or r.state = read5 or (v.no_ws = '0' or r.blimit = '1')) then
v.rbuf(0) := r.rbuf(1); -- update when data is written if wait states or PCI retry or PCI done
v.rbuf(1) := r.rbuf(2);
end if;
end if;
--if (ahbso1.hresp = HRESP_ERROR or (dmao.mexc or dmao.retry) = '1') then
if (ahbso1.hresp = HRESP_ERROR or dmao.mexc = '1') then
v.err := '1'; v.state := turn; v.htrans := HTRANS_IDLE;
end if;
--cancel dma
if r.start = '1' and r.start_req = '0' then
v.state := turn;
end if;
if rst = '0' then
v.state := idle;
v.start := '0';
v.start_req := '0';
v.write := '0';
v.err := '0';
v.ready := '0';
v.first1 := '1';
v.two_in_buf := '0';
v.hmbsel := (others => '0');
v.addr1 := (others => '0');
end if;
if r.start = '1' then
ahbsi1.hsel <= (others => '1');
ahbsi1.hmbsel(0 to 3) <= r.hmbsel;
ahbsi1.hsize <= "010";
ahbsi1.hwrite <= r.write;
ahbsi1.htrans <= v.htrans;
-- ahbsi1.haddr <= r.addr1 & "00";
ahbsi1.haddr <= v.addr1 & "00";
ahbsi1.hburst <= "001";
ahbsi1.hwdata <= ahbdrivedata(r.rbuf(0));
ahbsi1.hready <= ahbso1.hready;
ahbsi1.hmaster <= conv_std_logic_vector(hindex,4);
ahbso0 <= slvbusy;
else
ahbsi1.hsel <= ahbsi0.hsel;
ahbsi1.hmbsel(0 to 3) <= ahbsi0.hmbsel(0 to 3);
ahbsi1.hsize <= ahbsi0.hsize;
ahbsi1.hwrite <= ahbsi0.hwrite;
ahbsi1.htrans <= ahbsi0.htrans;
ahbsi1.haddr <= ahbsi0.haddr;
ahbsi1.hburst <= ahbsi0.hburst;
ahbsi1.hwdata <= ahbsi0.hwdata;
ahbsi1.hready <= ahbsi0.hready;
ahbsi1.hmaster <= ahbsi0.hmaster;
ahbso0 <= ahbso1;
if r.ahb0_hresp = HRESP_RETRY then
ahbso0.hready <= r.ahb0_hready; ahbso0.hresp <= r.ahb0_hresp;
end if;
v.state := idle;
end if;
dmai <= vdmai;
rin <= v;
apbo.pconfig <= pconfig;
apbo.prdata <= pdata;
apbo.pirq <= (others => '0');
apbo.pirq(pirq) <= v.ready and not r.ready;
apbo.pindex <= pindex;
ahbsi1.hirq <= (others => '0');
ahbsi1.hprot <= (others => '0');
ahbsi1.hmastlock <= '0';
ahbsi1.testen <= '0';
ahbsi1.testrst <= '0';
ahbsi1.scanen <= '0';
ahbsi1.testoen <= '0';
ahbsi1.testin <= ahbsi0.testin;
end process;
cpur : process (clk)
begin
if rising_edge (clk) then
r <= rin;
end if;
end process;
ahbmst0 : pciahbmst generic map (hindex => hindex, devid => GAISLER_DMACTRL, incaddr => 1)
port map (rst, clk, dmai, dmao, ahbmi, ahbmo);
-- pragma translate_off
bootmsg : report_version
generic map ("dmactrl" & tost(pindex) &
": 32-bit DMA controller & AHB/AHB bridge rev " & tost(REVISION));
-- pragma translate_on
end;
|
library ieee;
use ieee.std_logic_1164.all;
entity top is
port (
clock : in std_logic;
reset : in std_logic;
start : in std_logic;
stdout_rdy : out std_logic;
stdout_ack : in std_logic;
stdin_ack : in std_logic;
stdout_data : out std_logic_vector(7 downto 0);
stdin_data : in std_logic_vector(7 downto 0);
stdin_rdy : out std_logic
);
end top;
architecture augh of top is
-- Declaration of components
component cmp_869 is
port (
eq : out std_logic;
in1 : in std_logic_vector(7 downto 0);
in0 : in std_logic_vector(7 downto 0)
);
end component;
component cmp_978 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_979 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_847 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_855 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_852 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component mul_213 is
port (
output : out std_logic_vector(40 downto 0);
in_b : in std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0)
);
end component;
component mul_216 is
port (
output : out std_logic_vector(40 downto 0);
in_b : in std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0)
);
end component;
component mul_214 is
port (
output : out std_logic_vector(40 downto 0);
in_b : in std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0)
);
end component;
component cmp_846 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_848 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_849 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component p_jinfo_comps_info_id is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(1 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(1 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
wa0_en : in std_logic
);
end component;
component p_jinfo_comps_info_h_samp_factor is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(1 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(1 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
wa0_en : in std_logic
);
end component;
component p_jinfo_comps_info_quant_tbl_no is
port (
wa0_data : in std_logic_vector(1 downto 0);
wa0_addr : in std_logic_vector(1 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(1 downto 0);
ra0_data : out std_logic_vector(1 downto 0);
wa0_en : in std_logic
);
end component;
component p_jinfo_comps_info_dc_tbl_no is
port (
wa0_data : in std_logic;
wa0_addr : in std_logic_vector(1 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(1 downto 0);
ra0_data : out std_logic;
wa0_en : in std_logic
);
end component;
component p_jinfo_quant_tbl_quantval is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(7 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(7 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component p_jinfo_dc_xhuff_tbl_bits is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(6 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(6 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component p_jinfo_dc_xhuff_tbl_huffval is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(9 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(9 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component p_jinfo_ac_xhuff_tbl_bits is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(6 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(6 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component p_jinfo_ac_xhuff_tbl_huffval is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(9 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(9 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component p_jinfo_dc_dhuff_tbl_ml is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic;
clk : in std_logic;
ra0_addr : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component p_jinfo_dc_dhuff_tbl_maxcode is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(6 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(6 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component p_jinfo_dc_dhuff_tbl_mincode is
port (
wa0_data : in std_logic_vector(8 downto 0);
wa0_addr : in std_logic_vector(6 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(6 downto 0);
ra0_data : out std_logic_vector(8 downto 0);
wa0_en : in std_logic
);
end component;
component p_jinfo_dc_dhuff_tbl_valptr is
port (
wa0_data : in std_logic_vector(8 downto 0);
wa0_addr : in std_logic_vector(6 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(6 downto 0);
ra0_data : out std_logic_vector(8 downto 0);
wa0_en : in std_logic
);
end component;
component p_jinfo_ac_dhuff_tbl_ml is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic;
clk : in std_logic;
ra0_addr : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component p_jinfo_ac_dhuff_tbl_maxcode is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(6 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(6 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component p_jinfo_ac_dhuff_tbl_mincode is
port (
wa0_data : in std_logic_vector(8 downto 0);
wa0_addr : in std_logic_vector(6 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(6 downto 0);
ra0_data : out std_logic_vector(8 downto 0);
wa0_en : in std_logic
);
end component;
component p_jinfo_ac_dhuff_tbl_valptr is
port (
wa0_data : in std_logic_vector(8 downto 0);
wa0_addr : in std_logic_vector(6 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(6 downto 0);
ra0_data : out std_logic_vector(8 downto 0);
wa0_en : in std_logic
);
end component;
component outdata_comp_vpos is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(1 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(1 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component outdata_comp_hpos is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(1 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(1 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component outdata_comp_buf is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(14 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(14 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
wa0_en : in std_logic
);
end component;
component izigzag_index is
port (
clk : in std_logic;
ra0_addr : in std_logic_vector(5 downto 0);
ra0_data : out std_logic_vector(5 downto 0)
);
end component;
component jpegfilebuf is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(12 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(12 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
wa0_en : in std_logic
);
end component;
component huffbuff is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(7 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(7 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component idctbuff is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(8 downto 0);
clk : in std_logic;
ra2_data : out std_logic_vector(31 downto 0);
ra2_addr : in std_logic_vector(8 downto 0);
ra1_data : out std_logic_vector(31 downto 0);
ra1_addr : in std_logic_vector(8 downto 0);
ra0_addr : in std_logic_vector(8 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component quantbuff is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(5 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(5 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component extend_mask is
port (
clk : in std_logic;
ra0_addr : in std_logic_vector(4 downto 0);
ra0_data : out std_logic_vector(20 downto 0)
);
end component;
component bit_set_mask is
port (
clk : in std_logic;
ra0_addr : in std_logic_vector(4 downto 0);
ra0_data : out std_logic_vector(31 downto 0)
);
end component;
component lmask is
port (
clk : in std_logic;
ra0_addr : in std_logic_vector(4 downto 0);
ra0_data : out std_logic_vector(31 downto 0)
);
end component;
component huff_make_dhuff_tb_ac_huffsize is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(8 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(8 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component huff_make_dhuff_tb_ac_huffcode is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(8 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(8 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component huff_make_dhuff_tb_dc_huffsize is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(8 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(8 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component huff_make_dhuff_tb_dc_huffcode is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(8 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(8 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component rgb_buf is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(9 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(9 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
wa0_en : in std_logic
);
end component;
component zigzag_index is
port (
clk : in std_logic;
ra0_addr : in std_logic_vector(5 downto 0);
ra0_data : out std_logic_vector(5 downto 0)
);
end component;
component shr_212 is
port (
output : out std_logic_vector(31 downto 0);
input : in std_logic_vector(31 downto 0);
shift : in std_logic_vector(5 downto 0);
padding : in std_logic
);
end component;
component mul_209 is
port (
output : out std_logic_vector(40 downto 0);
in_b : in std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0)
);
end component;
component mul_210 is
port (
output : out std_logic_vector(40 downto 0);
in_b : in std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0)
);
end component;
component shl_211 is
port (
output : out std_logic_vector(31 downto 0);
input : in std_logic_vector(31 downto 0);
shift : in std_logic_vector(5 downto 0);
padding : in std_logic
);
end component;
component sub_206 is
port (
gt : out std_logic;
output : out std_logic_vector(40 downto 0);
sign : in std_logic;
in_b : in std_logic_vector(40 downto 0);
in_a : in std_logic_vector(40 downto 0)
);
end component;
component sub_207 is
port (
ge : out std_logic;
le : out std_logic;
output : out std_logic_vector(40 downto 0);
sign : in std_logic;
in_b : in std_logic_vector(40 downto 0);
in_a : in std_logic_vector(40 downto 0)
);
end component;
component sub_208 is
port (
ge : out std_logic;
output : out std_logic_vector(40 downto 0);
sign : in std_logic;
in_b : in std_logic_vector(40 downto 0);
in_a : in std_logic_vector(40 downto 0)
);
end component;
component sub_205 is
port (
gt : out std_logic;
ge : out std_logic;
lt : out std_logic;
le : out std_logic;
output : out std_logic_vector(40 downto 0);
sign : in std_logic;
in_b : in std_logic_vector(40 downto 0);
in_a : in std_logic_vector(40 downto 0)
);
end component;
component add_202 is
port (
output : out std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0)
);
end component;
component add_203 is
port (
output : out std_logic_vector(38 downto 0);
in_b : in std_logic_vector(38 downto 0);
in_a : in std_logic_vector(38 downto 0)
);
end component;
component add_204 is
port (
output : out std_logic_vector(24 downto 0);
in_b : in std_logic_vector(24 downto 0);
in_a : in std_logic_vector(24 downto 0)
);
end component;
component add_201 is
port (
output : out std_logic_vector(38 downto 0);
in_b : in std_logic_vector(38 downto 0);
in_a : in std_logic_vector(38 downto 0)
);
end component;
component add_200 is
port (
output : out std_logic_vector(38 downto 0);
in_b : in std_logic_vector(38 downto 0);
in_a : in std_logic_vector(38 downto 0)
);
end component;
component cmp_775 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_779 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_780 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_787 is
port (
eq : out std_logic;
in1 : in std_logic;
in0 : in std_logic
);
end component;
component cmp_788 is
port (
eq : out std_logic;
in1 : in std_logic_vector(2 downto 0);
in0 : in std_logic_vector(2 downto 0)
);
end component;
component cmp_790 is
port (
ne : out std_logic;
in1 : in std_logic_vector(3 downto 0);
in0 : in std_logic_vector(3 downto 0)
);
end component;
component cmp_792 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_793 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_794 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_791 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_804 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_800 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_799 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_865 is
port (
ne : out std_logic;
in1 : in std_logic_vector(2 downto 0);
in0 : in std_logic_vector(2 downto 0)
);
end component;
component cmp_882 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_885 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_887 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component mul_215 is
port (
output : out std_logic_vector(40 downto 0);
in_b : in std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0)
);
end component;
component cmp_850 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_851 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_861 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_871 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_873 is
port (
eq : out std_logic;
in1 : in std_logic_vector(7 downto 0);
in0 : in std_logic_vector(7 downto 0)
);
end component;
component cmp_879 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_880 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component sub_217 is
port (
ge : out std_logic;
output : out std_logic_vector(40 downto 0);
sign : in std_logic;
in_b : in std_logic_vector(40 downto 0);
in_a : in std_logic_vector(40 downto 0)
);
end component;
component cmp_863 is
port (
ne : out std_logic;
in1 : in std_logic_vector(2 downto 0);
in0 : in std_logic_vector(2 downto 0)
);
end component;
component cmp_868 is
port (
eq : out std_logic;
in1 : in std_logic_vector(23 downto 0);
in0 : in std_logic_vector(23 downto 0)
);
end component;
component cmp_877 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_878 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component sub_218 is
port (
le : out std_logic;
output : out std_logic_vector(40 downto 0);
sign : in std_logic;
in_b : in std_logic_vector(40 downto 0);
in_a : in std_logic_vector(40 downto 0)
);
end component;
component sub_220 is
port (
gt : out std_logic;
output : out std_logic_vector(40 downto 0);
sign : in std_logic;
in_b : in std_logic_vector(40 downto 0);
in_a : in std_logic_vector(40 downto 0)
);
end component;
component sub_221 is
port (
gt : out std_logic;
output : out std_logic_vector(40 downto 0);
sign : in std_logic;
in_b : in std_logic_vector(40 downto 0);
in_a : in std_logic_vector(40 downto 0)
);
end component;
component mul_222 is
port (
output : out std_logic_vector(40 downto 0);
in_b : in std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0)
);
end component;
component sub_219 is
port (
le : out std_logic;
output : out std_logic_vector(40 downto 0);
sign : in std_logic;
in_b : in std_logic_vector(40 downto 0);
in_a : in std_logic_vector(40 downto 0)
);
end component;
component cmp_962 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_975 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component fsm_224 is
port (
clock : in std_logic;
reset : in std_logic;
out40 : out std_logic;
in2 : in std_logic;
in11 : in std_logic;
out146 : out std_logic;
out148 : out std_logic;
out150 : out std_logic;
out152 : out std_logic;
in12 : in std_logic;
out153 : out std_logic;
out154 : out std_logic;
in13 : in std_logic;
out156 : out std_logic;
out157 : out std_logic;
out160 : out std_logic;
out162 : out std_logic;
out165 : out std_logic;
out170 : out std_logic;
out171 : out std_logic;
out173 : out std_logic;
out175 : out std_logic;
out177 : out std_logic;
out180 : out std_logic;
out184 : out std_logic;
in14 : in std_logic;
out186 : out std_logic;
out189 : out std_logic;
out191 : out std_logic;
out192 : out std_logic;
out193 : out std_logic;
out197 : out std_logic;
out199 : out std_logic;
out201 : out std_logic;
out202 : out std_logic;
out205 : out std_logic;
out207 : out std_logic;
out208 : out std_logic;
out209 : out std_logic;
out210 : out std_logic;
out212 : out std_logic;
out213 : out std_logic;
in15 : in std_logic;
out221 : out std_logic;
out222 : out std_logic;
out224 : out std_logic;
out225 : out std_logic;
out228 : out std_logic;
out229 : out std_logic;
out230 : out std_logic;
out231 : out std_logic;
out99 : out std_logic;
in6 : in std_logic;
out92 : out std_logic;
out232 : out std_logic;
in16 : in std_logic;
out234 : out std_logic;
out236 : out std_logic;
out239 : out std_logic;
out240 : out std_logic;
out241 : out std_logic;
out245 : out std_logic;
out246 : out std_logic;
out247 : out std_logic;
out251 : out std_logic;
out252 : out std_logic;
out253 : out std_logic;
out255 : out std_logic;
out256 : out std_logic;
out258 : out std_logic;
out259 : out std_logic;
in17 : in std_logic;
out263 : out std_logic;
out264 : out std_logic;
out266 : out std_logic;
in18 : in std_logic;
out267 : out std_logic;
out268 : out std_logic;
out270 : out std_logic;
out273 : out std_logic;
out275 : out std_logic;
out276 : out std_logic;
in19 : in std_logic;
out279 : out std_logic;
in20 : in std_logic;
out281 : out std_logic;
out282 : out std_logic;
in21 : in std_logic;
out283 : out std_logic;
out286 : out std_logic;
out289 : out std_logic;
out296 : out std_logic;
out297 : out std_logic;
out299 : out std_logic;
out300 : out std_logic;
out304 : out std_logic;
out305 : out std_logic;
in22 : in std_logic;
out306 : out std_logic;
out310 : out std_logic;
out311 : out std_logic;
out313 : out std_logic;
out314 : out std_logic;
in23 : in std_logic;
out316 : out std_logic;
out317 : out std_logic;
out320 : out std_logic;
out322 : out std_logic;
out324 : out std_logic;
out325 : out std_logic;
out326 : out std_logic;
out328 : out std_logic;
out332 : out std_logic;
out333 : out std_logic;
out334 : out std_logic;
out335 : out std_logic;
out338 : out std_logic;
out339 : out std_logic;
out341 : out std_logic;
out342 : out std_logic;
out344 : out std_logic;
out93 : out std_logic;
out98 : out std_logic;
out85 : out std_logic;
out87 : out std_logic;
out88 : out std_logic;
out80 : out std_logic;
out82 : out std_logic;
out83 : out std_logic;
out84 : out std_logic;
in5 : in std_logic;
out77 : out std_logic;
out78 : out std_logic;
out71 : out std_logic;
out72 : out std_logic;
in4 : in std_logic;
out65 : out std_logic;
out67 : out std_logic;
out60 : out std_logic;
out64 : out std_logic;
in3 : in std_logic;
out59 : out std_logic;
out53 : out std_logic;
out55 : out std_logic;
out49 : out std_logic;
out44 : out std_logic;
out104 : out std_logic;
out107 : out std_logic;
out111 : out std_logic;
out112 : out std_logic;
out114 : out std_logic;
in7 : in std_logic;
out117 : out std_logic;
out119 : out std_logic;
out122 : out std_logic;
in8 : in std_logic;
out128 : out std_logic;
in9 : in std_logic;
out129 : out std_logic;
out130 : out std_logic;
out133 : out std_logic;
out134 : out std_logic;
out136 : out std_logic;
out137 : out std_logic;
in10 : in std_logic;
out139 : out std_logic;
out143 : out std_logic;
out144 : out std_logic;
out32 : out std_logic;
out35 : out std_logic;
out27 : out std_logic;
out25 : out std_logic;
out26 : out std_logic;
in1 : in std_logic;
out15 : out std_logic;
out16 : out std_logic;
out11 : out std_logic;
out13 : out std_logic;
out14 : out std_logic;
out7 : out std_logic;
out1 : out std_logic;
out2 : out std_logic;
out3 : out std_logic;
out4 : out std_logic;
in0 : in std_logic;
in24 : in std_logic;
out346 : out std_logic;
out347 : out std_logic;
out348 : out std_logic;
out349 : out std_logic;
in25 : in std_logic;
out350 : out std_logic;
out351 : out std_logic;
out355 : out std_logic;
out356 : out std_logic;
out357 : out std_logic;
out358 : out std_logic;
out360 : out std_logic;
out362 : out std_logic;
out363 : out std_logic;
out364 : out std_logic;
out365 : out std_logic;
out366 : out std_logic;
out370 : out std_logic;
out371 : out std_logic;
out372 : out std_logic;
out373 : out std_logic;
out375 : out std_logic;
in26 : in std_logic;
out376 : out std_logic;
out378 : out std_logic;
out379 : out std_logic;
out381 : out std_logic;
out382 : out std_logic;
in27 : in std_logic;
out384 : out std_logic;
in28 : in std_logic;
out391 : out std_logic;
out395 : out std_logic;
out396 : out std_logic;
out401 : out std_logic;
out402 : out std_logic;
out403 : out std_logic;
out404 : out std_logic;
out405 : out std_logic;
out407 : out std_logic;
out408 : out std_logic;
out409 : out std_logic;
out410 : out std_logic;
in29 : in std_logic;
out412 : out std_logic;
out414 : out std_logic;
out415 : out std_logic;
out417 : out std_logic;
out418 : out std_logic;
out419 : out std_logic;
out420 : out std_logic;
out422 : out std_logic;
out424 : out std_logic;
out425 : out std_logic;
out426 : out std_logic;
in30 : in std_logic;
out428 : out std_logic;
out429 : out std_logic;
out432 : out std_logic;
out433 : out std_logic;
out434 : out std_logic;
out437 : out std_logic;
out440 : out std_logic;
out441 : out std_logic;
in31 : in std_logic;
out443 : out std_logic;
in32 : in std_logic;
out445 : out std_logic;
out447 : out std_logic;
out448 : out std_logic;
out450 : out std_logic;
in33 : in std_logic;
out453 : out std_logic;
out455 : out std_logic;
out458 : out std_logic;
in34 : in std_logic;
out462 : out std_logic;
out464 : out std_logic;
out467 : out std_logic;
out468 : out std_logic;
out472 : out std_logic;
in35 : in std_logic;
out478 : out std_logic;
out479 : out std_logic;
out480 : out std_logic;
out487 : out std_logic;
out488 : out std_logic;
in36 : in std_logic;
out491 : out std_logic;
out496 : out std_logic;
out497 : out std_logic;
out498 : out std_logic;
out500 : out std_logic;
out504 : out std_logic;
out505 : out std_logic;
in37 : in std_logic;
out506 : out std_logic;
out508 : out std_logic;
in38 : in std_logic;
out510 : out std_logic;
out513 : out std_logic;
out514 : out std_logic;
out515 : out std_logic;
out517 : out std_logic;
out519 : out std_logic;
in39 : in std_logic;
out523 : out std_logic;
out526 : out std_logic;
out527 : out std_logic;
out528 : out std_logic;
out530 : out std_logic;
out531 : out std_logic;
out533 : out std_logic;
out534 : out std_logic;
out537 : out std_logic;
out538 : out std_logic;
out549 : out std_logic;
out558 : out std_logic;
out559 : out std_logic;
out561 : out std_logic;
in40 : in std_logic;
out566 : out std_logic;
out567 : out std_logic;
out568 : out std_logic;
out569 : out std_logic;
out570 : out std_logic;
out572 : out std_logic;
out574 : out std_logic;
out575 : out std_logic;
out577 : out std_logic;
in41 : in std_logic;
out578 : out std_logic;
out581 : out std_logic;
out589 : out std_logic;
out590 : out std_logic;
out595 : out std_logic;
out597 : out std_logic;
out599 : out std_logic;
out601 : out std_logic;
out602 : out std_logic;
out607 : out std_logic;
out610 : out std_logic;
out612 : out std_logic;
in42 : in std_logic;
out614 : out std_logic;
out621 : out std_logic;
out628 : out std_logic;
out635 : out std_logic;
out636 : out std_logic;
out638 : out std_logic;
out640 : out std_logic;
out643 : out std_logic;
out646 : out std_logic;
out649 : out std_logic;
out651 : out std_logic;
out656 : out std_logic;
in43 : in std_logic;
out658 : out std_logic;
out659 : out std_logic;
out661 : out std_logic;
out663 : out std_logic;
out664 : out std_logic;
in44 : in std_logic;
out667 : out std_logic;
out668 : out std_logic;
out670 : out std_logic;
out672 : out std_logic;
out674 : out std_logic;
in45 : in std_logic;
out679 : out std_logic;
out681 : out std_logic;
out683 : out std_logic;
out686 : out std_logic;
out688 : out std_logic;
out690 : out std_logic;
out692 : out std_logic;
out694 : out std_logic;
out696 : out std_logic;
out697 : out std_logic;
out698 : out std_logic;
out699 : out std_logic;
out700 : out std_logic;
out703 : out std_logic;
out704 : out std_logic;
out706 : out std_logic;
out708 : out std_logic;
out710 : out std_logic;
out712 : out std_logic;
out715 : out std_logic;
out718 : out std_logic;
in46 : in std_logic;
out722 : out std_logic;
out724 : out std_logic;
out726 : out std_logic;
out728 : out std_logic;
out731 : out std_logic;
out733 : out std_logic;
out734 : out std_logic;
out737 : out std_logic;
out739 : out std_logic;
out740 : out std_logic;
out743 : out std_logic;
out745 : out std_logic;
out746 : out std_logic;
in47 : in std_logic;
out749 : out std_logic;
out753 : out std_logic;
out755 : out std_logic;
out759 : out std_logic;
in48 : in std_logic;
out762 : out std_logic;
out764 : out std_logic;
out765 : out std_logic;
out767 : out std_logic;
out768 : out std_logic;
in49 : in std_logic;
out772 : out std_logic;
in50 : in std_logic;
out775 : out std_logic;
out776 : out std_logic;
out778 : out std_logic;
out783 : out std_logic;
out784 : out std_logic;
out787 : out std_logic;
out791 : out std_logic;
in51 : in std_logic;
out794 : out std_logic;
out795 : out std_logic;
in52 : in std_logic;
out799 : out std_logic;
out802 : out std_logic;
out806 : out std_logic;
out809 : out std_logic;
out812 : out std_logic;
out815 : out std_logic;
out826 : out std_logic;
out828 : out std_logic;
in53 : in std_logic;
in54 : in std_logic;
out843 : out std_logic;
out848 : out std_logic;
out852 : out std_logic;
in55 : in std_logic;
out855 : out std_logic;
out858 : out std_logic;
in56 : in std_logic;
out860 : out std_logic;
out861 : out std_logic;
out863 : out std_logic;
out866 : out std_logic;
out872 : out std_logic;
in57 : in std_logic;
out874 : out std_logic;
out876 : out std_logic;
out879 : out std_logic;
out882 : out std_logic;
out886 : out std_logic;
out887 : out std_logic;
in58 : in std_logic;
out888 : out std_logic;
out892 : out std_logic;
out894 : out std_logic;
out895 : out std_logic;
out896 : out std_logic;
out901 : out std_logic;
out902 : out std_logic;
out903 : out std_logic;
out905 : out std_logic;
out907 : out std_logic;
out918 : out std_logic;
out920 : out std_logic;
out921 : out std_logic;
out923 : out std_logic;
out925 : out std_logic;
out928 : out std_logic;
out929 : out std_logic;
out931 : out std_logic;
out933 : out std_logic;
out936 : out std_logic;
out937 : out std_logic;
out938 : out std_logic;
out939 : out std_logic;
out942 : out std_logic;
out943 : out std_logic;
out944 : out std_logic;
out947 : out std_logic;
out948 : out std_logic;
out949 : out std_logic;
out951 : out std_logic;
in59 : in std_logic;
out952 : out std_logic;
out953 : out std_logic;
out955 : out std_logic;
out956 : out std_logic;
out957 : out std_logic;
out958 : out std_logic;
in60 : in std_logic;
in61 : in std_logic;
out962 : out std_logic;
out963 : out std_logic;
out972 : out std_logic;
out973 : out std_logic;
out974 : out std_logic;
in62 : in std_logic;
out978 : out std_logic;
out979 : out std_logic;
out981 : out std_logic;
out982 : out std_logic;
out985 : out std_logic;
out986 : out std_logic;
out989 : out std_logic;
in63 : in std_logic;
in64 : in std_logic;
in65 : in std_logic;
in66 : in std_logic;
in67 : in std_logic;
in68 : in std_logic;
in69 : in std_logic;
in70 : in std_logic;
in71 : in std_logic;
in72 : in std_logic;
in73 : in std_logic;
in74 : in std_logic;
in75 : in std_logic;
in76 : in std_logic;
in77 : in std_logic;
in78 : in std_logic;
out990 : out std_logic;
out991 : out std_logic;
out993 : out std_logic;
out994 : out std_logic;
out996 : out std_logic;
out997 : out std_logic;
out998 : out std_logic;
out999 : out std_logic;
out1000 : out std_logic;
out1002 : out std_logic;
out1003 : out std_logic;
out1005 : out std_logic;
out1006 : out std_logic;
out1007 : out std_logic;
out1009 : out std_logic;
out1011 : out std_logic;
out1012 : out std_logic;
out1013 : out std_logic;
out1014 : out std_logic;
out1015 : out std_logic;
out1016 : out std_logic;
out1018 : out std_logic;
out1019 : out std_logic;
out1021 : out std_logic;
out1022 : out std_logic;
out1024 : out std_logic;
out1026 : out std_logic;
out1027 : out std_logic;
out1029 : out std_logic;
out1030 : out std_logic;
out1032 : out std_logic;
out1033 : out std_logic;
out1035 : out std_logic;
out1036 : out std_logic;
out1037 : out std_logic;
out1057 : out std_logic;
out1068 : out std_logic;
out1069 : out std_logic;
out1070 : out std_logic;
out1072 : out std_logic;
out1073 : out std_logic;
out1075 : out std_logic;
out1078 : out std_logic;
out1080 : out std_logic;
out1082 : out std_logic;
out1083 : out std_logic;
out1084 : out std_logic;
out1085 : out std_logic;
out1088 : out std_logic;
out1089 : out std_logic;
out1091 : out std_logic;
out1092 : out std_logic;
out1094 : out std_logic;
out1096 : out std_logic;
out1098 : out std_logic;
out1101 : out std_logic;
out1104 : out std_logic;
out1107 : out std_logic;
out1109 : out std_logic;
out1111 : out std_logic;
out1114 : out std_logic;
out1119 : out std_logic;
out1121 : out std_logic;
out1125 : out std_logic;
out1126 : out std_logic;
out1128 : out std_logic;
out1131 : out std_logic;
out1134 : out std_logic;
out1137 : out std_logic;
out1139 : out std_logic;
out1141 : out std_logic;
out1145 : out std_logic;
out1146 : out std_logic;
out1147 : out std_logic;
out1150 : out std_logic;
out1151 : out std_logic;
out1152 : out std_logic;
out1155 : out std_logic;
out1158 : out std_logic;
out1160 : out std_logic;
out1164 : out std_logic;
out1166 : out std_logic;
out1169 : out std_logic;
out1171 : out std_logic;
out1174 : out std_logic;
out1175 : out std_logic;
out1176 : out std_logic;
out1180 : out std_logic;
out1181 : out std_logic;
out1182 : out std_logic;
out1185 : out std_logic;
out1186 : out std_logic;
out1187 : out std_logic;
out1190 : out std_logic;
out1213 : out std_logic;
out1215 : out std_logic;
out1217 : out std_logic;
out1220 : out std_logic;
out1221 : out std_logic;
out1223 : out std_logic;
out1228 : out std_logic;
out1229 : out std_logic;
out1231 : out std_logic;
out1235 : out std_logic;
out1236 : out std_logic;
out1240 : out std_logic;
out1243 : out std_logic;
out1250 : out std_logic;
out1252 : out std_logic;
out1253 : out std_logic;
out1258 : out std_logic;
out1262 : out std_logic;
out1266 : out std_logic;
out1269 : out std_logic;
out1275 : out std_logic;
out1278 : out std_logic;
out1279 : out std_logic;
out1284 : out std_logic;
out1286 : out std_logic;
out1287 : out std_logic;
out1289 : out std_logic;
out1290 : out std_logic;
out1292 : out std_logic;
out1293 : out std_logic;
out1295 : out std_logic;
out1298 : out std_logic;
out1301 : out std_logic;
out1302 : out std_logic;
out1303 : out std_logic;
out1308 : out std_logic;
out1309 : out std_logic;
out1311 : out std_logic;
out1318 : out std_logic;
out1319 : out std_logic;
out1320 : out std_logic;
out1323 : out std_logic;
out1324 : out std_logic;
out1326 : out std_logic;
out1327 : out std_logic;
out1329 : out std_logic;
out1337 : out std_logic;
out1339 : out std_logic;
out1340 : out std_logic;
out1341 : out std_logic;
out1344 : out std_logic;
out1346 : out std_logic;
out1349 : out std_logic;
out1353 : out std_logic;
out1356 : out std_logic;
out1362 : out std_logic;
out1363 : out std_logic;
out1364 : out std_logic;
out1365 : out std_logic;
out1366 : out std_logic;
out1368 : out std_logic;
out1370 : out std_logic;
out1375 : out std_logic;
out1378 : out std_logic;
out1381 : out std_logic;
out1383 : out std_logic;
out1387 : out std_logic
);
end component;
component muxb_784 is
port (
in_sel : in std_logic;
out_data : out std_logic_vector(31 downto 0);
in_data0 : in std_logic_vector(31 downto 0);
in_data1 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_964 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_972 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_973 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_974 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_985 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_971 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_977 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
-- Declaration of signals
signal sig_clock : std_logic;
signal sig_reset : std_logic;
signal augh_test_159 : std_logic;
signal augh_test_6 : std_logic;
signal augh_test_9 : std_logic;
signal augh_test_10 : std_logic;
signal augh_test_26 : std_logic;
signal augh_test_49 : std_logic;
signal augh_test_52 : std_logic;
signal augh_test_53 : std_logic;
signal augh_test_62 : std_logic;
signal augh_test_67 : std_logic;
signal augh_test_72 : std_logic;
signal augh_test_77 : std_logic;
signal augh_test_83 : std_logic;
signal augh_test_89 : std_logic;
signal augh_test_90 : std_logic;
signal augh_test_94 : std_logic;
signal augh_test_99 : std_logic;
signal augh_test_100 : std_logic;
signal augh_test_101 : std_logic;
signal augh_test_102 : std_logic;
signal augh_test_103 : std_logic;
signal augh_test_104 : std_logic;
signal augh_test_105 : std_logic;
signal augh_test_106 : std_logic;
signal augh_test_107 : std_logic;
signal augh_test_108 : std_logic;
signal augh_test_109 : std_logic;
signal augh_test_111 : std_logic;
signal augh_test_113 : std_logic;
signal augh_test_114 : std_logic;
signal augh_test_115 : std_logic;
signal augh_test_118 : std_logic;
signal augh_test_119 : std_logic;
signal augh_test_120 : std_logic;
signal augh_test_122 : std_logic;
signal augh_test_123 : std_logic;
signal augh_test_124 : std_logic;
signal augh_test_125 : std_logic;
signal augh_test_126 : std_logic;
signal augh_test_127 : std_logic;
signal augh_test_128 : std_logic;
signal augh_test_130 : std_logic;
signal augh_test_131 : std_logic;
signal augh_test_132 : std_logic;
signal augh_test_133 : std_logic;
signal augh_test_134 : std_logic;
signal augh_test_136 : std_logic;
signal augh_test_138 : std_logic;
signal augh_test_142 : std_logic;
signal augh_test_144 : std_logic;
signal augh_test_148 : std_logic;
signal augh_test_150 : std_logic;
signal augh_test_151 : std_logic;
signal augh_test_152 : std_logic;
signal augh_test_154 : std_logic;
signal augh_test_155 : std_logic;
signal augh_test_157 : std_logic;
signal augh_test_158 : std_logic;
signal augh_test_165 : std_logic;
signal augh_test_166 : std_logic;
signal augh_test_167 : std_logic;
signal augh_test_168 : std_logic;
signal sig_start : std_logic;
signal augh_test_171 : std_logic;
signal augh_test_178 : std_logic;
signal augh_test_179 : std_logic;
signal augh_test_180 : std_logic;
signal augh_test_182 : std_logic;
signal augh_test_183 : std_logic;
signal augh_test_184 : std_logic;
signal augh_test_186 : std_logic;
signal augh_test_187 : std_logic;
signal augh_test_188 : std_logic;
signal augh_test_189 : std_logic;
signal augh_test_194 : std_logic;
signal augh_test_196 : std_logic;
signal augh_test_197 : std_logic;
signal sig_990 : std_logic;
signal sig_991 : std_logic;
signal sig_992 : std_logic_vector(31 downto 0);
signal sig_993 : std_logic;
signal sig_994 : std_logic;
signal sig_995 : std_logic;
signal sig_996 : std_logic;
signal sig_997 : std_logic;
signal sig_998 : std_logic;
signal sig_999 : std_logic;
signal sig_1000 : std_logic;
signal sig_1001 : std_logic;
signal sig_1002 : std_logic;
signal sig_1003 : std_logic;
signal sig_1004 : std_logic;
signal sig_1005 : std_logic;
signal sig_1006 : std_logic;
signal sig_1007 : std_logic;
signal sig_1008 : std_logic;
signal sig_1009 : std_logic;
signal sig_1010 : std_logic;
signal sig_1011 : std_logic;
signal sig_1012 : std_logic;
signal sig_1013 : std_logic;
signal sig_1014 : std_logic;
signal sig_1015 : std_logic;
signal sig_1016 : std_logic;
signal sig_1017 : std_logic;
signal sig_1018 : std_logic;
signal sig_1019 : std_logic;
signal sig_1020 : std_logic;
signal sig_1021 : std_logic;
signal sig_1022 : std_logic;
signal sig_1023 : std_logic;
signal sig_1024 : std_logic;
signal sig_1025 : std_logic;
signal sig_1026 : std_logic;
signal sig_1027 : std_logic;
signal sig_1028 : std_logic;
signal sig_1029 : std_logic;
signal sig_1030 : std_logic;
signal sig_1031 : std_logic;
signal sig_1032 : std_logic;
signal sig_1033 : std_logic;
signal sig_1034 : std_logic;
signal sig_1035 : std_logic;
signal sig_1036 : std_logic;
signal sig_1037 : std_logic;
signal sig_1038 : std_logic;
signal sig_1039 : std_logic;
signal sig_1040 : std_logic;
signal sig_1041 : std_logic;
signal sig_1042 : std_logic;
signal sig_1043 : std_logic;
signal sig_1044 : std_logic;
signal sig_1045 : std_logic;
signal sig_1046 : std_logic;
signal sig_1047 : std_logic;
signal sig_1048 : std_logic;
signal sig_1049 : std_logic;
signal sig_1050 : std_logic;
signal sig_1051 : std_logic;
signal sig_1052 : std_logic;
signal sig_1053 : std_logic;
signal sig_1054 : std_logic;
signal sig_1055 : std_logic;
signal sig_1056 : std_logic;
signal sig_1057 : std_logic;
signal sig_1058 : std_logic;
signal sig_1059 : std_logic;
signal sig_1060 : std_logic;
signal sig_1061 : std_logic;
signal sig_1062 : std_logic;
signal sig_1063 : std_logic;
signal sig_1064 : std_logic;
signal sig_1065 : std_logic;
signal sig_1066 : std_logic;
signal sig_1067 : std_logic;
signal sig_1068 : std_logic;
signal sig_1069 : std_logic;
signal sig_1070 : std_logic;
signal sig_1071 : std_logic;
signal sig_1072 : std_logic;
signal sig_1073 : std_logic;
signal sig_1074 : std_logic;
signal sig_1075 : std_logic;
signal sig_1076 : std_logic;
signal sig_1077 : std_logic;
signal sig_1078 : std_logic;
signal sig_1079 : std_logic;
signal sig_1080 : std_logic;
signal sig_1081 : std_logic;
signal sig_1082 : std_logic;
signal sig_1083 : std_logic;
signal sig_1084 : std_logic;
signal sig_1085 : std_logic;
signal sig_1086 : std_logic;
signal sig_1087 : std_logic;
signal sig_1088 : std_logic;
signal sig_1089 : std_logic;
signal sig_1090 : std_logic;
signal sig_1091 : std_logic;
signal sig_1092 : std_logic;
signal sig_1093 : std_logic;
signal sig_1094 : std_logic;
signal sig_1095 : std_logic;
signal sig_1096 : std_logic;
signal sig_1097 : std_logic;
signal sig_1098 : std_logic;
signal sig_1099 : std_logic;
signal sig_1100 : std_logic;
signal sig_1101 : std_logic;
signal sig_1102 : std_logic;
signal sig_1103 : std_logic;
signal sig_1104 : std_logic;
signal sig_1105 : std_logic;
signal sig_1106 : std_logic;
signal sig_1107 : std_logic;
signal sig_1108 : std_logic;
signal sig_1109 : std_logic;
signal sig_1110 : std_logic;
signal sig_1111 : std_logic;
signal sig_1112 : std_logic;
signal sig_1113 : std_logic;
signal sig_1114 : std_logic;
signal sig_1115 : std_logic;
signal sig_1116 : std_logic;
signal sig_1117 : std_logic;
signal sig_1118 : std_logic;
signal sig_1119 : std_logic;
signal sig_1120 : std_logic;
signal sig_1121 : std_logic;
signal sig_1122 : std_logic;
signal sig_1123 : std_logic;
signal sig_1124 : std_logic;
signal sig_1125 : std_logic;
signal sig_1126 : std_logic;
signal sig_1127 : std_logic;
signal sig_1128 : std_logic;
signal sig_1129 : std_logic;
signal sig_1130 : std_logic;
signal sig_1131 : std_logic;
signal sig_1132 : std_logic;
signal sig_1133 : std_logic;
signal sig_1134 : std_logic;
signal sig_1135 : std_logic;
signal sig_1136 : std_logic;
signal sig_1137 : std_logic;
signal sig_1138 : std_logic;
signal sig_1139 : std_logic;
signal sig_1140 : std_logic;
signal sig_1141 : std_logic;
signal sig_1142 : std_logic;
signal sig_1143 : std_logic;
signal sig_1144 : std_logic;
signal sig_1145 : std_logic;
signal sig_1146 : std_logic;
signal sig_1147 : std_logic;
signal sig_1148 : std_logic;
signal sig_1149 : std_logic;
signal sig_1150 : std_logic;
signal sig_1151 : std_logic;
signal sig_1152 : std_logic;
signal sig_1153 : std_logic;
signal sig_1154 : std_logic;
signal sig_1155 : std_logic;
signal sig_1156 : std_logic;
signal sig_1157 : std_logic;
signal sig_1158 : std_logic;
signal sig_1159 : std_logic;
signal sig_1160 : std_logic;
signal sig_1161 : std_logic;
signal sig_1162 : std_logic;
signal sig_1163 : std_logic;
signal sig_1164 : std_logic;
signal sig_1165 : std_logic;
signal sig_1166 : std_logic;
signal sig_1167 : std_logic;
signal sig_1168 : std_logic;
signal sig_1169 : std_logic;
signal sig_1170 : std_logic;
signal sig_1171 : std_logic;
signal sig_1172 : std_logic;
signal sig_1173 : std_logic;
signal sig_1174 : std_logic;
signal sig_1175 : std_logic;
signal sig_1176 : std_logic;
signal sig_1177 : std_logic;
signal sig_1178 : std_logic;
signal sig_1179 : std_logic;
signal sig_1180 : std_logic;
signal sig_1181 : std_logic;
signal sig_1182 : std_logic;
signal sig_1183 : std_logic;
signal sig_1184 : std_logic;
signal sig_1185 : std_logic;
signal sig_1186 : std_logic;
signal sig_1187 : std_logic;
signal sig_1188 : std_logic;
signal sig_1189 : std_logic;
signal sig_1190 : std_logic;
signal sig_1191 : std_logic;
signal sig_1192 : std_logic;
signal sig_1193 : std_logic;
signal sig_1194 : std_logic;
signal sig_1195 : std_logic;
signal sig_1196 : std_logic;
signal sig_1197 : std_logic;
signal sig_1198 : std_logic;
signal sig_1199 : std_logic;
signal sig_1200 : std_logic;
signal sig_1201 : std_logic;
signal sig_1202 : std_logic;
signal sig_1203 : std_logic;
signal sig_1204 : std_logic;
signal sig_1205 : std_logic;
signal sig_1206 : std_logic;
signal sig_1207 : std_logic;
signal sig_1208 : std_logic;
signal sig_1209 : std_logic;
signal sig_1210 : std_logic;
signal sig_1211 : std_logic;
signal sig_1212 : std_logic;
signal sig_1213 : std_logic;
signal sig_1214 : std_logic;
signal sig_1215 : std_logic;
signal sig_1216 : std_logic;
signal sig_1217 : std_logic;
signal sig_1218 : std_logic;
signal sig_1219 : std_logic;
signal sig_1220 : std_logic;
signal sig_1221 : std_logic;
signal sig_1222 : std_logic;
signal sig_1223 : std_logic;
signal sig_1224 : std_logic;
signal sig_1225 : std_logic;
signal sig_1226 : std_logic;
signal sig_1227 : std_logic;
signal sig_1228 : std_logic;
signal sig_1229 : std_logic;
signal sig_1230 : std_logic;
signal sig_1231 : std_logic;
signal sig_1232 : std_logic;
signal sig_1233 : std_logic;
signal sig_1234 : std_logic;
signal sig_1235 : std_logic;
signal sig_1236 : std_logic;
signal sig_1237 : std_logic;
signal sig_1238 : std_logic;
signal sig_1239 : std_logic;
signal sig_1240 : std_logic;
signal sig_1241 : std_logic;
signal sig_1242 : std_logic;
signal sig_1243 : std_logic;
signal sig_1244 : std_logic;
signal sig_1245 : std_logic;
signal sig_1246 : std_logic;
signal sig_1247 : std_logic;
signal sig_1248 : std_logic;
signal sig_1249 : std_logic;
signal sig_1250 : std_logic;
signal sig_1251 : std_logic;
signal sig_1252 : std_logic;
signal sig_1253 : std_logic;
signal sig_1254 : std_logic;
signal sig_1255 : std_logic;
signal sig_1256 : std_logic;
signal sig_1257 : std_logic;
signal sig_1258 : std_logic;
signal sig_1259 : std_logic;
signal sig_1260 : std_logic;
signal sig_1261 : std_logic;
signal sig_1262 : std_logic;
signal sig_1263 : std_logic;
signal sig_1264 : std_logic;
signal sig_1265 : std_logic;
signal sig_1266 : std_logic;
signal sig_1267 : std_logic;
signal sig_1268 : std_logic;
signal sig_1269 : std_logic;
signal sig_1270 : std_logic;
signal sig_1271 : std_logic;
signal sig_1272 : std_logic;
signal sig_1273 : std_logic;
signal sig_1274 : std_logic;
signal sig_1275 : std_logic;
signal sig_1276 : std_logic;
signal sig_1277 : std_logic;
signal sig_1278 : std_logic;
signal sig_1279 : std_logic;
signal sig_1280 : std_logic;
signal sig_1281 : std_logic;
signal sig_1282 : std_logic;
signal sig_1283 : std_logic;
signal sig_1284 : std_logic;
signal sig_1285 : std_logic;
signal sig_1286 : std_logic;
signal sig_1287 : std_logic;
signal sig_1288 : std_logic;
signal sig_1289 : std_logic;
signal sig_1290 : std_logic;
signal sig_1291 : std_logic;
signal sig_1292 : std_logic;
signal sig_1293 : std_logic;
signal sig_1294 : std_logic;
signal sig_1295 : std_logic;
signal sig_1296 : std_logic;
signal sig_1297 : std_logic;
signal sig_1298 : std_logic;
signal sig_1299 : std_logic;
signal sig_1300 : std_logic;
signal sig_1301 : std_logic;
signal sig_1302 : std_logic;
signal sig_1303 : std_logic;
signal sig_1304 : std_logic;
signal sig_1305 : std_logic;
signal sig_1306 : std_logic;
signal sig_1307 : std_logic;
signal sig_1308 : std_logic;
signal sig_1309 : std_logic;
signal sig_1310 : std_logic;
signal sig_1311 : std_logic;
signal sig_1312 : std_logic;
signal sig_1313 : std_logic;
signal sig_1314 : std_logic;
signal sig_1315 : std_logic;
signal sig_1316 : std_logic;
signal sig_1317 : std_logic;
signal sig_1318 : std_logic;
signal sig_1319 : std_logic;
signal sig_1320 : std_logic;
signal sig_1321 : std_logic;
signal sig_1322 : std_logic;
signal sig_1323 : std_logic;
signal sig_1324 : std_logic;
signal sig_1325 : std_logic;
signal sig_1326 : std_logic;
signal sig_1327 : std_logic;
signal sig_1328 : std_logic;
signal sig_1329 : std_logic;
signal sig_1330 : std_logic;
signal sig_1331 : std_logic;
signal sig_1332 : std_logic;
signal sig_1333 : std_logic;
signal sig_1334 : std_logic;
signal sig_1335 : std_logic;
signal sig_1336 : std_logic;
signal sig_1337 : std_logic;
signal sig_1338 : std_logic;
signal sig_1339 : std_logic;
signal sig_1340 : std_logic;
signal sig_1341 : std_logic;
signal sig_1342 : std_logic;
signal sig_1343 : std_logic;
signal sig_1344 : std_logic;
signal sig_1345 : std_logic;
signal sig_1346 : std_logic;
signal sig_1347 : std_logic;
signal sig_1348 : std_logic;
signal sig_1349 : std_logic;
signal sig_1350 : std_logic;
signal sig_1351 : std_logic;
signal sig_1352 : std_logic;
signal sig_1353 : std_logic;
signal sig_1354 : std_logic;
signal sig_1355 : std_logic;
signal sig_1356 : std_logic;
signal sig_1357 : std_logic;
signal sig_1358 : std_logic;
signal sig_1359 : std_logic;
signal sig_1360 : std_logic;
signal sig_1361 : std_logic;
signal sig_1362 : std_logic;
signal sig_1363 : std_logic;
signal sig_1364 : std_logic;
signal sig_1365 : std_logic;
signal sig_1366 : std_logic;
signal sig_1367 : std_logic;
signal sig_1368 : std_logic;
signal sig_1369 : std_logic;
signal sig_1370 : std_logic;
signal sig_1371 : std_logic;
signal sig_1372 : std_logic;
signal sig_1373 : std_logic;
signal sig_1374 : std_logic;
signal sig_1375 : std_logic;
signal sig_1376 : std_logic;
signal sig_1377 : std_logic;
signal sig_1378 : std_logic;
signal sig_1379 : std_logic;
signal sig_1380 : std_logic;
signal sig_1381 : std_logic;
signal sig_1382 : std_logic;
signal sig_1383 : std_logic;
signal sig_1384 : std_logic;
signal sig_1385 : std_logic;
signal sig_1386 : std_logic;
signal sig_1387 : std_logic;
signal sig_1388 : std_logic;
signal sig_1389 : std_logic;
signal sig_1390 : std_logic;
signal sig_1391 : std_logic;
signal sig_1392 : std_logic;
signal sig_1393 : std_logic;
signal sig_1394 : std_logic;
signal sig_1395 : std_logic;
signal sig_1396 : std_logic;
signal sig_1397 : std_logic;
signal sig_1398 : std_logic;
signal sig_1399 : std_logic;
signal sig_1400 : std_logic;
signal sig_1401 : std_logic;
signal sig_1402 : std_logic;
signal sig_1403 : std_logic;
signal sig_1404 : std_logic;
signal sig_1405 : std_logic;
signal sig_1406 : std_logic;
signal sig_1407 : std_logic;
signal sig_1408 : std_logic;
signal sig_1409 : std_logic;
signal sig_1410 : std_logic;
signal sig_1411 : std_logic;
signal sig_1412 : std_logic;
signal sig_1413 : std_logic;
signal sig_1414 : std_logic;
signal sig_1415 : std_logic;
signal sig_1416 : std_logic;
signal sig_1417 : std_logic;
signal sig_1418 : std_logic;
signal sig_1419 : std_logic;
signal sig_1420 : std_logic;
signal sig_1421 : std_logic;
signal sig_1422 : std_logic;
signal sig_1423 : std_logic;
signal sig_1424 : std_logic;
signal sig_1425 : std_logic;
signal sig_1426 : std_logic;
signal sig_1427 : std_logic;
signal sig_1428 : std_logic;
signal sig_1429 : std_logic;
signal sig_1430 : std_logic;
signal sig_1431 : std_logic;
signal sig_1432 : std_logic;
signal sig_1433 : std_logic;
signal sig_1434 : std_logic;
signal sig_1435 : std_logic;
signal sig_1436 : std_logic;
signal sig_1437 : std_logic;
signal sig_1438 : std_logic;
signal sig_1439 : std_logic;
signal sig_1440 : std_logic;
signal sig_1441 : std_logic;
signal sig_1442 : std_logic;
signal sig_1443 : std_logic;
signal sig_1444 : std_logic;
signal sig_1445 : std_logic;
signal sig_1446 : std_logic;
signal sig_1447 : std_logic;
signal sig_1448 : std_logic;
signal sig_1449 : std_logic;
signal sig_1450 : std_logic;
signal sig_1451 : std_logic;
signal sig_1452 : std_logic;
signal sig_1453 : std_logic;
signal sig_1454 : std_logic;
signal sig_1455 : std_logic;
signal sig_1456 : std_logic;
signal sig_1457 : std_logic;
signal sig_1458 : std_logic;
signal sig_1459 : std_logic;
signal sig_1460 : std_logic;
signal sig_1461 : std_logic;
signal sig_1462 : std_logic;
signal sig_1463 : std_logic;
signal sig_1464 : std_logic;
signal sig_1465 : std_logic;
signal sig_1466 : std_logic;
signal sig_1467 : std_logic;
signal sig_1468 : std_logic;
signal sig_1469 : std_logic;
signal sig_1470 : std_logic;
signal sig_1471 : std_logic;
signal sig_1472 : std_logic;
signal sig_1473 : std_logic;
signal sig_1474 : std_logic;
signal sig_1475 : std_logic;
signal sig_1476 : std_logic;
signal sig_1477 : std_logic;
signal sig_1478 : std_logic;
signal sig_1479 : std_logic;
signal sig_1480 : std_logic;
signal sig_1481 : std_logic;
signal sig_1482 : std_logic;
signal sig_1483 : std_logic;
signal sig_1484 : std_logic;
signal sig_1485 : std_logic;
signal sig_1486 : std_logic;
signal sig_1487 : std_logic;
signal sig_1488 : std_logic;
signal sig_1489 : std_logic;
signal sig_1490 : std_logic;
signal sig_1491 : std_logic;
signal sig_1492 : std_logic;
signal sig_1493 : std_logic;
signal sig_1494 : std_logic;
signal sig_1495 : std_logic;
signal sig_1496 : std_logic;
signal sig_1497 : std_logic;
signal sig_1498 : std_logic;
signal sig_1499 : std_logic;
signal sig_1500 : std_logic;
signal sig_1501 : std_logic;
signal sig_1502 : std_logic;
signal sig_1503 : std_logic;
signal sig_1504 : std_logic;
signal sig_1505 : std_logic;
signal sig_1506 : std_logic;
signal sig_1507 : std_logic;
signal sig_1508 : std_logic;
signal sig_1509 : std_logic;
signal sig_1510 : std_logic;
signal sig_1511 : std_logic;
signal sig_1512 : std_logic;
signal sig_1513 : std_logic;
signal sig_1514 : std_logic;
signal sig_1515 : std_logic;
signal sig_1516 : std_logic;
signal sig_1517 : std_logic;
signal sig_1518 : std_logic;
signal sig_1519 : std_logic;
signal sig_1520 : std_logic;
signal sig_1521 : std_logic;
signal sig_1522 : std_logic;
signal sig_1523 : std_logic;
signal sig_1524 : std_logic;
signal sig_1525 : std_logic;
signal sig_1526 : std_logic;
signal sig_1527 : std_logic;
signal sig_1528 : std_logic;
signal sig_1529 : std_logic;
signal sig_1530 : std_logic;
signal sig_1531 : std_logic;
signal sig_1532 : std_logic;
signal sig_1533 : std_logic;
signal sig_1534 : std_logic;
signal sig_1535 : std_logic;
signal sig_1536 : std_logic;
signal sig_1537 : std_logic;
signal sig_1538 : std_logic;
signal sig_1539 : std_logic;
signal sig_1540 : std_logic;
signal sig_1541 : std_logic;
signal sig_1542 : std_logic;
signal sig_1543 : std_logic;
signal sig_1544 : std_logic;
signal sig_1545 : std_logic;
signal sig_1546 : std_logic;
signal sig_1547 : std_logic;
signal sig_1548 : std_logic;
signal sig_1549 : std_logic;
signal sig_1550 : std_logic;
signal sig_1551 : std_logic;
signal sig_1552 : std_logic;
signal sig_1553 : std_logic;
signal sig_1554 : std_logic;
signal sig_1555 : std_logic;
signal sig_1556 : std_logic;
signal sig_1557 : std_logic;
signal sig_1558 : std_logic;
signal sig_1559 : std_logic;
signal sig_1560 : std_logic;
signal sig_1561 : std_logic;
signal sig_1562 : std_logic;
signal sig_1563 : std_logic;
signal sig_1564 : std_logic;
signal sig_1565 : std_logic;
signal sig_1566 : std_logic;
signal sig_1567 : std_logic;
signal sig_1568 : std_logic;
signal sig_1569 : std_logic;
signal sig_1570 : std_logic;
signal sig_1571 : std_logic;
signal sig_1572 : std_logic;
signal sig_1573 : std_logic;
signal sig_1574 : std_logic;
signal sig_1575 : std_logic;
signal sig_1576 : std_logic;
signal sig_1577 : std_logic;
signal sig_1578 : std_logic;
signal sig_1579 : std_logic;
signal sig_1580 : std_logic;
signal sig_1581 : std_logic;
signal sig_1582 : std_logic;
signal sig_1583 : std_logic;
signal sig_1584 : std_logic;
signal sig_1585 : std_logic_vector(40 downto 0);
signal sig_1586 : std_logic;
signal sig_1587 : std_logic_vector(40 downto 0);
signal sig_1588 : std_logic_vector(40 downto 0);
signal sig_1589 : std_logic;
signal sig_1590 : std_logic_vector(40 downto 0);
signal sig_1591 : std_logic;
signal sig_1592 : std_logic_vector(40 downto 0);
signal sig_1593 : std_logic;
signal sig_1594 : std_logic;
signal sig_1595 : std_logic;
signal sig_1596 : std_logic_vector(40 downto 0);
signal sig_1597 : std_logic;
signal sig_1598 : std_logic;
signal sig_1599 : std_logic;
signal sig_1600 : std_logic_vector(40 downto 0);
signal sig_1601 : std_logic;
signal sig_1602 : std_logic;
signal sig_1603 : std_logic;
signal sig_1604 : std_logic;
signal sig_1605 : std_logic;
signal sig_1606 : std_logic;
signal sig_1607 : std_logic;
signal sig_1608 : std_logic;
signal sig_1609 : std_logic_vector(38 downto 0);
signal sig_1610 : std_logic_vector(38 downto 0);
signal sig_1611 : std_logic_vector(24 downto 0);
signal sig_1612 : std_logic_vector(38 downto 0);
signal sig_1613 : std_logic_vector(31 downto 0);
signal sig_1614 : std_logic_vector(40 downto 0);
signal sig_1615 : std_logic;
signal sig_1616 : std_logic;
signal sig_1617 : std_logic;
signal sig_1618 : std_logic;
signal sig_1619 : std_logic_vector(40 downto 0);
signal sig_1620 : std_logic;
signal sig_1621 : std_logic_vector(40 downto 0);
signal sig_1622 : std_logic;
signal sig_1623 : std_logic;
signal sig_1624 : std_logic_vector(40 downto 0);
signal sig_1625 : std_logic;
signal sig_1626 : std_logic_vector(31 downto 0);
signal sig_1627 : std_logic_vector(40 downto 0);
signal sig_1628 : std_logic_vector(40 downto 0);
signal sig_1629 : std_logic_vector(31 downto 0);
signal sig_1630 : std_logic_vector(5 downto 0);
signal sig_1631 : std_logic_vector(7 downto 0);
signal sig_1632 : std_logic_vector(31 downto 0);
signal sig_1633 : std_logic_vector(31 downto 0);
signal sig_1634 : std_logic_vector(31 downto 0);
signal sig_1635 : std_logic_vector(31 downto 0);
signal sig_1636 : std_logic_vector(31 downto 0);
signal sig_1637 : std_logic_vector(31 downto 0);
signal sig_1638 : std_logic_vector(20 downto 0);
signal sig_1639 : std_logic_vector(31 downto 0);
signal sig_1640 : std_logic_vector(31 downto 0);
signal sig_1641 : std_logic_vector(31 downto 0);
signal sig_1642 : std_logic_vector(31 downto 0);
signal sig_1643 : std_logic_vector(31 downto 0);
signal sig_1644 : std_logic_vector(7 downto 0);
signal sig_1645 : std_logic_vector(5 downto 0);
signal sig_1646 : std_logic_vector(7 downto 0);
signal sig_1647 : std_logic_vector(31 downto 0);
signal sig_1648 : std_logic_vector(31 downto 0);
signal sig_1649 : std_logic_vector(8 downto 0);
signal sig_1650 : std_logic_vector(8 downto 0);
signal sig_1651 : std_logic_vector(31 downto 0);
signal sig_1652 : std_logic_vector(31 downto 0);
signal sig_1653 : std_logic_vector(8 downto 0);
signal sig_1654 : std_logic_vector(8 downto 0);
signal sig_1655 : std_logic_vector(31 downto 0);
signal sig_1656 : std_logic_vector(31 downto 0);
signal sig_1657 : std_logic_vector(31 downto 0);
signal sig_1658 : std_logic_vector(31 downto 0);
signal sig_1659 : std_logic_vector(31 downto 0);
signal sig_1660 : std_logic_vector(31 downto 0);
signal sig_1661 : std_logic_vector(31 downto 0);
signal sig_1662 : std_logic;
signal sig_1663 : std_logic_vector(1 downto 0);
signal sig_1664 : std_logic_vector(7 downto 0);
signal sig_1665 : std_logic_vector(7 downto 0);
signal sig_1666 : std_logic_vector(40 downto 0);
signal sig_1667 : std_logic_vector(40 downto 0);
signal sig_1668 : std_logic_vector(40 downto 0);
signal sig_1669 : std_logic;
signal sig_1670 : std_logic;
signal sig_1671 : std_logic_vector(31 downto 0);
signal sig_1672 : std_logic_vector(31 downto 0);
signal sig_1673 : std_logic_vector(40 downto 0);
signal sig_1674 : std_logic_vector(40 downto 0);
signal sig_1675 : std_logic_vector(40 downto 0);
signal sig_1676 : std_logic_vector(40 downto 0);
signal sig_1677 : std_logic_vector(31 downto 0);
signal sig_1678 : std_logic_vector(31 downto 0);
signal sig_1679 : std_logic_vector(40 downto 0);
signal sig_1680 : std_logic_vector(31 downto 0);
signal sig_1681 : std_logic_vector(31 downto 0);
signal sig_1682 : std_logic_vector(31 downto 0);
signal sig_1683 : std_logic_vector(31 downto 0);
signal sig_1684 : std_logic_vector(31 downto 0);
signal sig_1685 : std_logic_vector(31 downto 0);
signal sig_1686 : std_logic_vector(31 downto 0);
signal sig_1687 : std_logic_vector(31 downto 0);
signal sig_1688 : std_logic_vector(24 downto 0);
signal sig_1689 : std_logic_vector(40 downto 0);
signal sig_1690 : std_logic_vector(31 downto 0);
signal sig_1691 : std_logic_vector(9 downto 0);
signal sig_1692 : std_logic_vector(8 downto 0);
signal sig_1693 : std_logic_vector(14 downto 0);
signal sig_1694 : std_logic_vector(14 downto 0);
signal sig_1695 : std_logic_vector(6 downto 0);
signal sig_1696 : std_logic_vector(6 downto 0);
signal sig_1697 : std_logic_vector(6 downto 0);
signal sig_1698 : std_logic_vector(6 downto 0);
signal sig_1699 : std_logic_vector(6 downto 0);
signal sig_1700 : std_logic_vector(6 downto 0);
signal sig_1701 : std_logic_vector(6 downto 0);
signal sig_1702 : std_logic_vector(6 downto 0);
signal sig_1703 : std_logic_vector(9 downto 0);
signal sig_1704 : std_logic_vector(6 downto 0);
signal sig_1705 : std_logic_vector(9 downto 0);
signal sig_1706 : std_logic_vector(6 downto 0);
signal sig_1707 : std_logic_vector(7 downto 0);
signal sig_1708 : std_logic_vector(31 downto 0);
signal sig_1709 : std_logic_vector(31 downto 0);
signal sig_1710 : std_logic_vector(31 downto 0);
signal sig_1711 : std_logic_vector(31 downto 0);
signal sig_1712 : std_logic_vector(31 downto 0);
signal sig_1713 : std_logic_vector(31 downto 0);
signal sig_1714 : std_logic_vector(31 downto 0);
signal sig_1715 : std_logic_vector(31 downto 0);
signal sig_1716 : std_logic_vector(31 downto 0);
-- Other inlined components
signal mux_967 : std_logic_vector(31 downto 0);
signal and_976 : std_logic;
signal and_982 : std_logic_vector(31 downto 0);
signal and_983 : std_logic_vector(27 downto 0);
signal and_984 : std_logic_vector(31 downto 0);
signal mux_689 : std_logic_vector(31 downto 0);
signal mux_690 : std_logic_vector(6 downto 0);
signal mux_691 : std_logic_vector(6 downto 0);
signal and_853 : std_logic_vector(31 downto 0);
signal izigzagmatrix_i : std_logic_vector(31 downto 0) := (others => '0');
signal mux_233 : std_logic_vector(31 downto 0);
signal izigzagmatrix_out_idx : std_logic_vector(31 downto 0) := (others => '0');
signal iquantize_qidx : std_logic_vector(1 downto 0) := (others => '0');
signal write8_u8 : std_logic_vector(7 downto 0) := (others => '0');
signal p_jinfo_image_height : std_logic_vector(15 downto 0) := (others => '0');
signal p_jinfo_image_width : std_logic_vector(15 downto 0) := (others => '0');
signal mux_671 : std_logic_vector(31 downto 0);
signal p_jinfo_num_components : std_logic_vector(7 downto 0) := (others => '0');
signal p_jinfo_smp_fact : std_logic_vector(1 downto 0) := (others => '0');
signal mux_665 : std_logic_vector(1 downto 0);
signal mux_663 : std_logic_vector(31 downto 0);
signal mux_664 : std_logic_vector(1 downto 0);
signal mux_659 : std_logic_vector(31 downto 0);
signal mux_660 : std_logic_vector(1 downto 0);
signal mux_661 : std_logic_vector(1 downto 0);
signal mux_652 : std_logic_vector(12 downto 0);
signal mux_648 : std_logic_vector(31 downto 0);
signal mux_633 : std_logic_vector(31 downto 0);
signal mux_622 : std_logic_vector(31 downto 0);
signal mux_614 : std_logic_vector(31 downto 0);
signal mux_616 : std_logic_vector(31 downto 0);
signal p_jinfo_mcuwidth : std_logic_vector(31 downto 0) := (others => '0');
signal mux_602 : std_logic_vector(31 downto 0);
signal p_jinfo_mcuheight : std_logic_vector(31 downto 0) := (others => '0');
signal mux_600 : std_logic_vector(31 downto 0);
signal p_jinfo_nummcu : std_logic_vector(31 downto 0) := (others => '0');
signal i_jinfo_jpeg_data : std_logic_vector(31 downto 0) := (others => '0');
signal mux_593 : std_logic_vector(31 downto 0);
signal curhuffreadbuf_idx : std_logic_vector(31 downto 0) := (others => '0');
signal mux_587 : std_logic_vector(31 downto 0);
signal outdata_image_width : std_logic_vector(7 downto 0) := (others => '0');
signal mux_585 : std_logic_vector(15 downto 0);
signal outdata_image_height : std_logic_vector(7 downto 0) := (others => '0');
signal mux_580 : std_logic_vector(7 downto 0);
signal mux_569 : std_logic_vector(7 downto 0);
signal mux_567 : std_logic_vector(31 downto 0);
signal mux_568 : std_logic_vector(7 downto 0);
signal mux_563 : std_logic_vector(8 downto 0);
signal mux_565 : std_logic_vector(8 downto 0);
signal mux_561 : std_logic_vector(31 downto 0);
signal mux_562 : std_logic_vector(8 downto 0);
signal mux_557 : std_logic_vector(31 downto 0);
signal mux_558 : std_logic_vector(5 downto 0);
signal mux_559 : std_logic_vector(5 downto 0);
signal mux_555 : std_logic_vector(31 downto 0);
signal mux_551 : std_logic_vector(31 downto 0);
signal mux_553 : std_logic_vector(31 downto 0);
signal mux_549 : std_logic_vector(31 downto 0);
signal mux_545 : std_logic_vector(31 downto 0);
signal mux_547 : std_logic_vector(31 downto 0);
signal mux_543 : std_logic_vector(31 downto 0);
signal mux_731 : std_logic_vector(7 downto 0);
signal mux_727 : std_logic_vector(6 downto 0);
signal mux_723 : std_logic_vector(9 downto 0);
signal mux_719 : std_logic_vector(6 downto 0);
signal mux_539 : std_logic_vector(31 downto 0);
signal mux_541 : std_logic_vector(31 downto 0);
signal mux_537 : std_logic_vector(31 downto 0);
signal mux_533 : std_logic_vector(31 downto 0);
signal mux_535 : std_logic_vector(31 downto 0);
signal mux_715 : std_logic_vector(9 downto 0);
signal mux_711 : std_logic;
signal mux_705 : std_logic_vector(31 downto 0);
signal mux_706 : std_logic_vector(6 downto 0);
signal mux_707 : std_logic_vector(6 downto 0);
signal mux_531 : std_logic_vector(31 downto 0);
signal mux_529 : std_logic_vector(31 downto 0);
signal mux_695 : std_logic;
signal mux_524 : std_logic_vector(4 downto 0);
signal mux_521 : std_logic_vector(31 downto 0);
signal readbuf_idx : std_logic_vector(31 downto 0) := (others => '0');
signal read_byte : std_logic_vector(7 downto 0) := (others => '0');
signal read_word : std_logic_vector(15 downto 0) := (others => '0');
signal read_word_c : std_logic_vector(7 downto 0) := (others => '0');
signal mux_519 : std_logic_vector(31 downto 0);
signal mux_517 : std_logic_vector(7 downto 0);
signal next_marker : std_logic_vector(7 downto 0) := (others => '0');
signal next_marker_c : std_logic_vector(7 downto 0) := (others => '0');
signal get_sof_ci : std_logic_vector(31 downto 0) := (others => '0');
signal mux_507 : std_logic_vector(31 downto 0);
signal mux_505 : std_logic_vector(31 downto 0);
signal get_sof_i_comp_info_id : std_logic_vector(1 downto 0) := (others => '0');
signal mux_501 : std_logic_vector(31 downto 0);
signal get_sof_i_comp_info_h_samp_factor : std_logic_vector(1 downto 0) := (others => '0');
signal get_sof_i_comp_info_quant_tbl_no : std_logic_vector(1 downto 0) := (others => '0');
signal mux_492 : std_logic_vector(31 downto 0);
signal mux_488 : std_logic_vector(31 downto 0);
signal mux_490 : std_logic_vector(31 downto 0);
signal get_sos_num_comp : std_logic_vector(7 downto 0) := (others => '0');
signal mux_486 : std_logic_vector(31 downto 0);
signal get_sos_i : std_logic_vector(31 downto 0) := (others => '0');
signal mux_482 : std_logic_vector(31 downto 0);
signal mux_484 : std_logic_vector(31 downto 0);
signal get_sos_c : std_logic := '0';
signal mux_480 : std_logic_vector(31 downto 0);
signal get_sos_cc : std_logic_vector(7 downto 0) := (others => '0');
signal mux_476 : std_logic_vector(31 downto 0);
signal mux_478 : std_logic_vector(8 downto 0);
signal get_sos_ci : std_logic_vector(31 downto 0) := (others => '0');
signal get_sos_j : std_logic_vector(31 downto 0) := (others => '0');
signal get_sos_i_comp_info_dc_tbl_no : std_logic_vector(1 downto 0) := (others => '0');
signal get_dht_length : std_logic_vector(31 downto 0) := (others => '0');
signal get_dht_index : std_logic := '0';
signal mux_459 : std_logic_vector(31 downto 0);
signal get_dht_i : std_logic_vector(31 downto 0) := (others => '0');
signal mux_455 : std_logic_vector(31 downto 0);
signal mux_457 : std_logic_vector(31 downto 0);
signal get_dht_count : std_logic_vector(31 downto 0) := (others => '0');
signal mux_453 : std_logic_vector(31 downto 0);
signal mux_449 : std_logic_vector(31 downto 0);
signal mux_451 : std_logic_vector(31 downto 0);
signal get_dht_is_ac : std_logic := '0';
signal get_dqt_length : std_logic_vector(31 downto 0) := (others => '0');
signal mux_447 : std_logic_vector(31 downto 0);
signal get_dqt_prec : std_logic_vector(3 downto 0) := (others => '0');
signal mux_443 : std_logic_vector(31 downto 0);
signal mux_445 : std_logic_vector(8 downto 0);
signal get_dqt_num : std_logic_vector(1 downto 0) := (others => '0');
signal get_dqt_i : std_logic_vector(31 downto 0) := (others => '0');
signal get_dqt_tmp : std_logic_vector(15 downto 0) := (others => '0');
signal read_markers_unread_marker : std_logic_vector(7 downto 0) := (others => '0');
signal read_markers_sow_soi : std_logic := '0';
signal mux_430 : std_logic_vector(31 downto 0);
signal mux_422 : std_logic_vector(31 downto 0);
signal mux_424 : std_logic_vector(31 downto 0);
signal chenidct_i : std_logic_vector(31 downto 0) := (others => '0');
signal mux_416 : std_logic_vector(31 downto 0);
signal chenidct_aidx : std_logic_vector(31 downto 0) := (others => '0');
signal chenidct_a0 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_410 : std_logic_vector(31 downto 0);
signal chenidct_a1 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_408 : std_logic_vector(31 downto 0);
signal chenidct_a2 : std_logic_vector(31 downto 0) := (others => '0');
signal chenidct_a3 : std_logic_vector(31 downto 0) := (others => '0');
signal chenidct_b0 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_398 : std_logic_vector(31 downto 0);
signal mux_400 : std_logic_vector(31 downto 0);
signal chenidct_b1 : std_logic_vector(31 downto 0) := (others => '0');
signal chenidct_b2 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_392 : std_logic_vector(31 downto 0);
signal mux_394 : std_logic_vector(31 downto 0);
signal chenidct_b3 : std_logic_vector(31 downto 0) := (others => '0');
signal chenidct_c0 : std_logic_vector(31 downto 0) := (others => '0');
signal chenidct_c1 : std_logic_vector(31 downto 0) := (others => '0');
signal chenidct_c2 : std_logic_vector(31 downto 0) := (others => '0');
signal chenidct_c3 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_378 : std_logic_vector(7 downto 0);
signal mux_379 : std_logic_vector(9 downto 0);
signal mux_375 : std_logic_vector(1 downto 0);
signal mux_373 : std_logic_vector(1 downto 0);
signal current_read_byte : std_logic_vector(31 downto 0) := (others => '0');
signal mux_365 : std_logic_vector(31 downto 0);
signal mux_367 : std_logic_vector(31 downto 0);
signal read_position : std_logic_vector(31 downto 0) := "11111111111111111111111111111111";
signal pgetc : std_logic_vector(7 downto 0) := (others => '0');
signal pgetc_temp : std_logic_vector(7 downto 0) := (others => '0');
signal buf_getb : std_logic := '0';
signal buf_getv : std_logic_vector(31 downto 0) := (others => '0');
signal buf_getv_n : std_logic_vector(31 downto 0) := (others => '0');
signal mux_363 : std_logic_vector(31 downto 0);
signal buf_getv_p : std_logic_vector(31 downto 0) := (others => '0');
signal mux_359 : std_logic_vector(31 downto 0);
signal mux_361 : std_logic_vector(31 downto 0);
signal buf_getv_rv : std_logic_vector(31 downto 0) := (others => '0');
signal huff_make_dhuff_tb_ac : std_logic_vector(31 downto 0) := (others => '0');
signal huff_make_dhuff_tb_ac_tbl_no : std_logic := '0';
signal huff_make_dhuff_tb_ac_p_dhtbl_ml : std_logic_vector(31 downto 0) := (others => '0');
signal huff_make_dhuff_tb_ac_i_c0 : std_logic_vector(31 downto 0) := (others => '0');
signal huff_make_dhuff_tb_ac_j : std_logic_vector(31 downto 0) := (others => '0');
signal mux_347 : std_logic_vector(31 downto 0);
signal huff_make_dhuff_tb_ac_p : std_logic_vector(31 downto 0) := (others => '0');
signal mux_345 : std_logic_vector(31 downto 0);
signal huff_make_dhuff_tb_ac_code : std_logic_vector(31 downto 0) := (others => '0');
signal mux_341 : std_logic_vector(2 downto 0);
signal mux_343 : std_logic_vector(1 downto 0);
signal huff_make_dhuff_tb_ac_size : std_logic_vector(31 downto 0) := (others => '0');
signal mux_339 : std_logic_vector(2 downto 0);
signal huff_make_dhuff_tb_ac_l : std_logic_vector(31 downto 0) := (others => '0');
signal mux_335 : std_logic_vector(31 downto 0);
signal mux_337 : std_logic_vector(2 downto 0);
signal mux_333 : std_logic_vector(31 downto 0);
signal mux_331 : std_logic_vector(31 downto 0);
signal huff_make_dhuff_tb_dc : std_logic_vector(31 downto 0) := (others => '0');
signal huff_make_dhuff_tb_dc_tbl_no : std_logic := '0';
signal huff_make_dhuff_tb_dc_p_dhtbl_ml : std_logic_vector(31 downto 0) := (others => '0');
signal mux_323 : std_logic_vector(5 downto 0);
signal huff_make_dhuff_tb_dc_i_c0 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_320 : std_logic_vector(31 downto 0);
signal mux_322 : std_logic_vector(31 downto 0);
signal huff_make_dhuff_tb_dc_j : std_logic_vector(31 downto 0) := (others => '0');
signal mux_317 : std_logic_vector(1 downto 0);
signal huff_make_dhuff_tb_dc_p : std_logic_vector(31 downto 0) := (others => '0');
signal mux_314 : std_logic_vector(31 downto 0);
signal mux_315 : std_logic_vector(31 downto 0);
signal mux_316 : std_logic_vector(31 downto 0);
signal huff_make_dhuff_tb_dc_code : std_logic_vector(31 downto 0) := (others => '0');
signal mux_313 : std_logic_vector(8 downto 0);
signal huff_make_dhuff_tb_dc_size : std_logic_vector(31 downto 0) := (others => '0');
signal mux_308 : std_logic_vector(2 downto 0);
signal huff_make_dhuff_tb_dc_l : std_logic_vector(31 downto 0) := (others => '0');
signal mux_306 : std_logic_vector(40 downto 0);
signal mux_307 : std_logic_vector(40 downto 0);
signal mux_302 : std_logic_vector(40 downto 0);
signal mux_303 : std_logic_vector(40 downto 0);
signal decodehuffman_ac : std_logic_vector(31 downto 0) := (others => '0');
signal decodehuffman_ac_tbl_no : std_logic := '0';
signal mux_294 : std_logic_vector(1 downto 0);
signal decodehuffman_ac_dhuff_ml : std_logic_vector(5 downto 0) := (others => '0');
signal mux_290 : std_logic_vector(40 downto 0);
signal mux_291 : std_logic_vector(40 downto 0);
signal mux_292 : std_logic_vector(31 downto 0);
signal decodehuffman_ac_code : std_logic_vector(31 downto 0) := (others => '0');
signal decodehuffman_ac_l : std_logic_vector(31 downto 0) := (others => '0');
signal mux_286 : std_logic_vector(31 downto 0);
signal decodehuffman_ac_p : std_logic_vector(8 downto 0) := (others => '0');
signal decodehuffman_dc : std_logic_vector(31 downto 0) := (others => '0');
signal decodehuffman_dc_tbl_no : std_logic := '0';
signal decodehuffman_dc_dhuff_ml : std_logic_vector(5 downto 0) := (others => '0');
signal mux_275 : std_logic_vector(31 downto 0);
signal decodehuffman_dc_code : std_logic_vector(31 downto 0) := (others => '0');
signal mux_272 : std_logic_vector(38 downto 0);
signal mux_274 : std_logic_vector(31 downto 0);
signal decodehuffman_dc_l : std_logic_vector(31 downto 0) := (others => '0');
signal mux_271 : std_logic_vector(38 downto 0);
signal decodehuffman_dc_p : std_logic_vector(8 downto 0) := (others => '0');
signal decodehuffmcu_bufdim1 : std_logic_vector(1 downto 0) := (others => '0');
signal mux_266 : std_logic_vector(38 downto 0);
signal mux_265 : std_logic_vector(38 downto 0);
signal decodehuffmcu_s : std_logic_vector(31 downto 0) := (others => '0');
signal mux_260 : std_logic_vector(38 downto 0);
signal mux_261 : std_logic_vector(38 downto 0);
signal mux_262 : std_logic_vector(31 downto 0);
signal decodehuffmcu_diff : std_logic_vector(31 downto 0) := (others => '0');
signal mux_257 : std_logic_vector(31 downto 0);
signal decodehuffmcu_tbl_no : std_logic := '0';
signal decodehuffmcu_i : std_logic_vector(31 downto 0) := (others => '0');
signal decodehuffmcu_k : std_logic_vector(31 downto 0) := (others => '0');
signal decodehuffmcu_n : std_logic_vector(27 downto 0) := (others => '0');
signal writeoneblock_outidx : std_logic_vector(1 downto 0) := (others => '0');
signal writeoneblock_indim1 : std_logic_vector(1 downto 0) := (others => '0');
signal writeoneblock_width : std_logic_vector(31 downto 0) := (others => '0');
signal writeoneblock_height : std_logic_vector(31 downto 0) := (others => '0');
signal writeoneblock_voffs : std_logic_vector(31 downto 0) := (others => '0');
signal writeoneblock_hoffs : std_logic_vector(31 downto 0) := (others => '0');
signal writeoneblock_i : std_logic_vector(31 downto 0) := (others => '0');
signal writeoneblock_e : std_logic_vector(31 downto 0) := (others => '0');
signal writeoneblock_inidx : std_logic_vector(31 downto 0) := (others => '0');
signal writeoneblock_diff : std_logic_vector(12 downto 0) := (others => '0');
signal writeblock_i : std_logic_vector(1 downto 0) := (others => '0');
signal write4blocks_i : std_logic_vector(1 downto 0) := (others => '0');
signal write4blocks_voffs : std_logic_vector(31 downto 0) := (others => '0');
signal write4blocks_hoffs : std_logic_vector(31 downto 0) := (others => '0');
signal yuvtorgb_p : std_logic_vector(1 downto 0) := (others => '0');
signal yuvtorgb_yidx : std_logic_vector(2 downto 0) := (others => '0');
signal yuvtorgb_uidx : std_logic_vector(2 downto 0) := (others => '0');
signal yuvtorgb_vidx : std_logic_vector(2 downto 0) := (others => '0');
signal yuvtorgb_r : std_logic_vector(31 downto 0) := (others => '0');
signal yuvtorgb_g : std_logic_vector(31 downto 0) := (others => '0');
signal yuvtorgb_b : std_logic_vector(31 downto 0) := (others => '0');
signal yuvtorgb_y : std_logic_vector(23 downto 0) := (others => '0');
signal yuvtorgb_u : std_logic_vector(30 downto 0) := (others => '0');
signal yuvtorgb_v : std_logic_vector(31 downto 0) := (others => '0');
signal yuvtorgb_i : std_logic_vector(31 downto 0) := (others => '0');
signal decode_block_comp_no : std_logic_vector(1 downto 0) := (others => '0');
signal decode_block_out_buf_idx : std_logic_vector(2 downto 0) := (others => '0');
signal decode_block_in_buf_idx : std_logic_vector(1 downto 0) := (others => '0');
signal decode_start_i : std_logic_vector(31 downto 0) := (others => '0');
signal decode_start_currentmcu : std_logic_vector(31 downto 0) := (others => '0');
signal nand_786 : std_logic;
signal or_845 : std_logic_vector(31 downto 0);
signal or_854 : std_logic_vector(31 downto 0);
signal or_866 : std_logic_vector(31 downto 0);
signal jpeg2bmp_main_i : std_logic_vector(31 downto 0) := (others => '0');
signal jpeg2bmp_main_j : std_logic_vector(31 downto 0) := (others => '0');
signal read8_ret0_195 : std_logic_vector(7 downto 0) := (others => '0');
signal and_785 : std_logic;
signal and_801 : std_logic_vector(31 downto 0);
signal mux_761 : std_logic_vector(8 downto 0);
signal mux_782 : std_logic_vector(31 downto 0);
signal or_802 : std_logic_vector(23 downto 0);
signal and_803 : std_logic_vector(31 downto 0);
signal mux_822 : std_logic_vector(31 downto 0);
signal mux_823 : std_logic_vector(31 downto 0);
signal mux_776 : std_logic_vector(31 downto 0);
signal mux_820 : std_logic_vector(31 downto 0);
signal mux_824 : std_logic_vector(31 downto 0);
signal mux_825 : std_logic_vector(31 downto 0);
signal mux_760 : std_logic_vector(31 downto 0);
signal and_789 : std_logic;
signal mux_759 : std_logic_vector(5 downto 0);
signal mux_768 : std_logic_vector(31 downto 0);
signal mux_757 : std_logic_vector(7 downto 0);
signal mux_773 : std_logic_vector(7 downto 0);
signal mux_762 : std_logic_vector(31 downto 0);
signal mux_766 : std_logic_vector(31 downto 0);
signal mux_781 : std_logic_vector(31 downto 0);
signal mux_797 : std_logic_vector(31 downto 0);
signal mux_821 : std_logic_vector(31 downto 0);
signal mux_826 : std_logic_vector(31 downto 0);
signal mux_778 : std_logic_vector(31 downto 0);
signal mux_827 : std_logic_vector(31 downto 0);
signal mux_815 : std_logic_vector(31 downto 0);
signal mux_798 : std_logic_vector(31 downto 0);
signal mux_816 : std_logic_vector(31 downto 0);
signal mux_817 : std_logic_vector(31 downto 0);
signal mux_777 : std_logic_vector(31 downto 0);
signal mux_819 : std_logic_vector(31 downto 0);
signal mux_783 : std_logic_vector(31 downto 0);
signal mux_795 : std_logic_vector(31 downto 0);
signal mux_796 : std_logic_vector(31 downto 0);
signal mux_805 : std_logic_vector(31 downto 0);
signal mux_806 : std_logic_vector(31 downto 0);
signal mux_807 : std_logic_vector(31 downto 0);
signal mux_808 : std_logic_vector(31 downto 0);
signal mux_809 : std_logic_vector(31 downto 0);
signal mux_810 : std_logic_vector(31 downto 0);
signal mux_811 : std_logic_vector(31 downto 0);
signal mux_812 : std_logic_vector(31 downto 0);
signal mux_813 : std_logic_vector(31 downto 0);
signal mux_814 : std_logic_vector(31 downto 0);
signal mux_818 : std_logic_vector(31 downto 0);
signal mux_828 : std_logic_vector(31 downto 0);
signal mux_829 : std_logic_vector(31 downto 0);
signal mux_830 : std_logic_vector(31 downto 0);
signal mux_831 : std_logic_vector(31 downto 0);
signal mux_832 : std_logic_vector(31 downto 0);
signal mux_836 : std_logic_vector(31 downto 0);
signal mux_837 : std_logic_vector(31 downto 0);
signal mux_839 : std_logic_vector(31 downto 0);
signal mux_840 : std_logic_vector(31 downto 0);
signal mux_841 : std_logic_vector(31 downto 0);
signal mux_842 : std_logic_vector(31 downto 0);
signal mux_843 : std_logic_vector(31 downto 0);
signal mux_856 : std_logic_vector(31 downto 0);
signal and_864 : std_logic;
signal mux_870 : std_logic_vector(31 downto 0);
signal mux_872 : std_logic_vector(1 downto 0);
signal mux_875 : std_logic_vector(31 downto 0);
signal mux_891 : std_logic_vector(31 downto 0);
signal mux_892 : std_logic_vector(31 downto 0);
signal mux_893 : std_logic_vector(31 downto 0);
signal mux_894 : std_logic_vector(31 downto 0);
signal mux_895 : std_logic_vector(31 downto 0);
signal mux_896 : std_logic_vector(31 downto 0);
signal mux_897 : std_logic_vector(31 downto 0);
signal mux_898 : std_logic_vector(31 downto 0);
signal mux_899 : std_logic_vector(31 downto 0);
signal mux_900 : std_logic_vector(31 downto 0);
signal mux_901 : std_logic_vector(31 downto 0);
signal mux_902 : std_logic_vector(31 downto 0);
signal mux_903 : std_logic_vector(31 downto 0);
signal mux_904 : std_logic_vector(31 downto 0);
signal mux_905 : std_logic_vector(31 downto 0);
signal mux_906 : std_logic_vector(31 downto 0);
signal mux_907 : std_logic_vector(31 downto 0);
signal mux_908 : std_logic_vector(31 downto 0);
signal mux_917 : std_logic_vector(31 downto 0);
signal mux_918 : std_logic_vector(31 downto 0);
signal mux_924 : std_logic_vector(31 downto 0);
signal mux_925 : std_logic_vector(31 downto 0);
signal mux_928 : std_logic_vector(31 downto 0);
signal mux_929 : std_logic_vector(31 downto 0);
signal mux_931 : std_logic_vector(31 downto 0);
signal mux_932 : std_logic_vector(31 downto 0);
signal mux_934 : std_logic_vector(31 downto 0);
signal mux_935 : std_logic_vector(31 downto 0);
signal mux_936 : std_logic_vector(31 downto 0);
signal mux_937 : std_logic_vector(31 downto 0);
signal mux_938 : std_logic_vector(31 downto 0);
signal mux_939 : std_logic_vector(31 downto 0);
signal mux_941 : std_logic_vector(31 downto 0);
signal mux_944 : std_logic_vector(31 downto 0);
signal mux_945 : std_logic_vector(31 downto 0);
signal mux_946 : std_logic_vector(31 downto 0);
signal mux_833 : std_logic_vector(31 downto 0);
signal mux_834 : std_logic_vector(31 downto 0);
signal mux_835 : std_logic_vector(31 downto 0);
signal mux_838 : std_logic_vector(31 downto 0);
signal mux_844 : std_logic_vector(31 downto 0);
signal mux_857 : std_logic_vector(31 downto 0);
signal mux_858 : std_logic_vector(31 downto 0);
signal mux_859 : std_logic_vector(31 downto 0);
signal mux_874 : std_logic_vector(31 downto 0);
signal mux_888 : std_logic_vector(31 downto 0);
signal mux_889 : std_logic_vector(31 downto 0);
signal mux_913 : std_logic_vector(31 downto 0);
signal mux_914 : std_logic_vector(31 downto 0);
signal mux_915 : std_logic_vector(31 downto 0);
signal mux_916 : std_logic_vector(31 downto 0);
signal mux_933 : std_logic_vector(31 downto 0);
signal mux_940 : std_logic_vector(31 downto 0);
signal mux_942 : std_logic_vector(31 downto 0);
signal and_867 : std_logic;
signal mux_909 : std_logic_vector(31 downto 0);
signal mux_910 : std_logic_vector(31 downto 0);
signal mux_911 : std_logic_vector(31 downto 0);
signal mux_920 : std_logic_vector(31 downto 0);
signal mux_921 : std_logic_vector(31 downto 0);
signal mux_926 : std_logic_vector(31 downto 0);
signal mux_927 : std_logic_vector(31 downto 0);
signal mux_943 : std_logic_vector(31 downto 0);
signal mux_886 : std_logic;
signal mux_922 : std_logic_vector(31 downto 0);
signal mux_923 : std_logic_vector(31 downto 0);
signal mux_930 : std_logic_vector(31 downto 0);
signal mux_987 : std_logic_vector(31 downto 0);
signal and_860 : std_logic_vector(31 downto 0);
signal and_881 : std_logic_vector(31 downto 0);
signal and_884 : std_logic_vector(31 downto 0);
signal mux_890 : std_logic_vector(31 downto 0);
signal mux_912 : std_logic_vector(31 downto 0);
signal mux_919 : std_logic_vector(31 downto 0);
signal mux_948 : std_logic_vector(31 downto 0);
signal mux_949 : std_logic_vector(31 downto 0);
signal mux_950 : std_logic_vector(31 downto 0);
signal and_862 : std_logic;
signal mux_953 : std_logic_vector(31 downto 0);
signal mux_954 : std_logic_vector(31 downto 0);
signal mux_955 : std_logic_vector(31 downto 0);
signal mux_951 : std_logic_vector(31 downto 0);
signal mux_952 : std_logic_vector(31 downto 0);
signal mux_959 : std_logic_vector(31 downto 0);
signal mux_960 : std_logic_vector(31 downto 0);
signal mux_961 : std_logic_vector(31 downto 0);
signal mux_965 : std_logic_vector(31 downto 0);
signal mux_966 : std_logic_vector(31 downto 0);
signal and_876 : std_logic_vector(7 downto 0);
signal mux_956 : std_logic_vector(31 downto 0);
signal mux_957 : std_logic_vector(31 downto 0);
signal mux_947 : std_logic_vector(31 downto 0);
signal mux_968 : std_logic_vector(31 downto 0);
signal mux_969 : std_logic_vector(31 downto 0);
signal mux_970 : std_logic_vector(31 downto 0);
signal mux_980 : std_logic_vector(31 downto 0);
signal mux_981 : std_logic_vector(31 downto 0);
signal mux_958 : std_logic_vector(31 downto 0);
signal and_963 : std_logic;
signal mux_986 : std_logic_vector(31 downto 0);
signal mux_988 : std_logic_vector(31 downto 0);
signal mux_989 : std_logic_vector(31 downto 0);
-- This utility function is used for inlining MUX behaviour
-- Little utility function to ease concatenation of an std_logic
-- and explicitely return an std_logic_vector
function repeat(N: natural; B: std_logic) return std_logic_vector is
variable result: std_logic_vector(N-1 downto 0);
begin
result := (others => B);
return result;
end;
begin
-- Instantiation of components
cmp_869_i : cmp_869 port map (
eq => sig_1670,
in1 => sig_1665,
in0 => get_sos_cc
);
cmp_978_i : cmp_978 port map (
ne => augh_test_132,
in1 => sig_1633,
in0 => huff_make_dhuff_tb_dc_size
);
cmp_979_i : cmp_979 port map (
ne => augh_test_124,
in1 => sig_1635,
in0 => huff_make_dhuff_tb_ac_size
);
cmp_847_i : cmp_847 port map (
eq => augh_test_100,
in1 => sig_1716,
in0 => "00000000000000000000000011000000"
);
cmp_855_i : cmp_855 port map (
ne => sig_1669,
in1 => sig_1715,
in0 => "00000000000000000000000000000000"
);
cmp_852_i : cmp_852 port map (
eq => augh_test_94,
in1 => sig_1714,
in0 => "00000000000000000000000000000000"
);
mul_213_i : mul_213 port map (
output => sig_1668,
in_b => "00000000000000000000000000110001",
in_a => chenidct_b3
);
mul_216_i : mul_216 port map (
output => sig_1667,
in_b => sig_1713,
in_a => mux_762
);
mul_214_i : mul_214 port map (
output => sig_1666,
in_b => sig_1712,
in_a => mux_760
);
cmp_846_i : cmp_846 port map (
eq => augh_test_99,
in1 => sig_1711,
in0 => "00000000000000000000000011011000"
);
cmp_848_i : cmp_848 port map (
eq => augh_test_101,
in1 => sig_1710,
in0 => "00000000000000000000000011011010"
);
cmp_849_i : cmp_849 port map (
eq => augh_test_102,
in1 => sig_1709,
in0 => "00000000000000000000000011000100"
);
p_jinfo_comps_info_id_i : p_jinfo_comps_info_id port map (
wa0_data => read_byte,
wa0_addr => get_sof_i_comp_info_id,
clk => sig_clock,
ra0_addr => get_sos_ci(1 downto 0),
ra0_data => sig_1665,
wa0_en => sig_1213
);
p_jinfo_comps_info_h_samp_factor_i : p_jinfo_comps_info_h_samp_factor port map (
wa0_data => and_876,
wa0_addr => get_sof_i_comp_info_h_samp_factor,
clk => sig_clock,
ra0_addr => "00",
ra0_data => sig_1664,
wa0_en => sig_1214
);
p_jinfo_comps_info_quant_tbl_no_i : p_jinfo_comps_info_quant_tbl_no port map (
wa0_data => read_byte(1 downto 0),
wa0_addr => get_sof_i_comp_info_quant_tbl_no,
clk => sig_clock,
ra0_addr => decode_block_comp_no,
ra0_data => sig_1663,
wa0_en => sig_1212
);
p_jinfo_comps_info_dc_tbl_no_i : p_jinfo_comps_info_dc_tbl_no port map (
wa0_data => get_sos_c,
wa0_addr => get_sos_i_comp_info_dc_tbl_no,
clk => sig_clock,
ra0_addr => decode_block_comp_no,
ra0_data => sig_1662,
wa0_en => sig_1252
);
p_jinfo_quant_tbl_quantval_i : p_jinfo_quant_tbl_quantval port map (
wa0_data => sig_1708,
wa0_addr => sig_1707,
clk => sig_clock,
ra0_addr => mux_731,
ra0_data => sig_1661,
wa0_en => sig_1334
);
p_jinfo_dc_xhuff_tbl_bits_i : p_jinfo_dc_xhuff_tbl_bits port map (
wa0_data => mux_782,
wa0_addr => sig_1706,
clk => sig_clock,
ra0_addr => mux_727,
ra0_data => sig_1660,
wa0_en => sig_1457
);
p_jinfo_dc_xhuff_tbl_huffval_i : p_jinfo_dc_xhuff_tbl_huffval port map (
wa0_data => mux_778,
wa0_addr => sig_1705,
clk => sig_clock,
ra0_addr => mux_723,
ra0_data => sig_1659,
wa0_en => sig_1540
);
p_jinfo_ac_xhuff_tbl_bits_i : p_jinfo_ac_xhuff_tbl_bits port map (
wa0_data => mux_783,
wa0_addr => sig_1704,
clk => sig_clock,
ra0_addr => mux_719,
ra0_data => sig_1658,
wa0_en => sig_1457
);
p_jinfo_ac_xhuff_tbl_huffval_i : p_jinfo_ac_xhuff_tbl_huffval port map (
wa0_data => mux_781,
wa0_addr => sig_1703,
clk => sig_clock,
ra0_addr => mux_715,
ra0_data => sig_1657,
wa0_en => sig_1540
);
p_jinfo_dc_dhuff_tbl_ml_i : p_jinfo_dc_dhuff_tbl_ml port map (
wa0_data => huff_make_dhuff_tb_dc,
wa0_addr => sig_1188,
clk => sig_clock,
ra0_addr => mux_711,
ra0_data => sig_1656,
wa0_en => sig_1190
);
p_jinfo_dc_dhuff_tbl_maxcode_i : p_jinfo_dc_dhuff_tbl_maxcode port map (
wa0_data => mux_705,
wa0_addr => mux_706,
clk => sig_clock,
ra0_addr => mux_707,
ra0_data => sig_1655,
wa0_en => sig_1560
);
p_jinfo_dc_dhuff_tbl_mincode_i : p_jinfo_dc_dhuff_tbl_mincode port map (
wa0_data => sig_1632(8 downto 0),
wa0_addr => sig_1702,
clk => sig_clock,
ra0_addr => sig_1701,
ra0_data => sig_1654,
wa0_en => sig_1039
);
p_jinfo_dc_dhuff_tbl_valptr_i : p_jinfo_dc_dhuff_tbl_valptr port map (
wa0_data => huff_make_dhuff_tb_dc_p(8 downto 0),
wa0_addr => sig_1700,
clk => sig_clock,
ra0_addr => sig_1699,
ra0_data => sig_1653,
wa0_en => sig_1039
);
p_jinfo_ac_dhuff_tbl_ml_i : p_jinfo_ac_dhuff_tbl_ml port map (
wa0_data => huff_make_dhuff_tb_ac,
wa0_addr => sig_1183,
clk => sig_clock,
ra0_addr => mux_695,
ra0_data => sig_1652,
wa0_en => sig_1185
);
p_jinfo_ac_dhuff_tbl_maxcode_i : p_jinfo_ac_dhuff_tbl_maxcode port map (
wa0_data => mux_689,
wa0_addr => mux_690,
clk => sig_clock,
ra0_addr => mux_691,
ra0_data => sig_1651,
wa0_en => sig_1522
);
p_jinfo_ac_dhuff_tbl_mincode_i : p_jinfo_ac_dhuff_tbl_mincode port map (
wa0_data => sig_1634(8 downto 0),
wa0_addr => sig_1698,
clk => sig_clock,
ra0_addr => sig_1697,
ra0_data => sig_1650,
wa0_en => sig_1549
);
p_jinfo_ac_dhuff_tbl_valptr_i : p_jinfo_ac_dhuff_tbl_valptr port map (
wa0_data => huff_make_dhuff_tb_ac_p(8 downto 0),
wa0_addr => sig_1696,
clk => sig_clock,
ra0_addr => sig_1695,
ra0_data => sig_1649,
wa0_en => sig_1549
);
outdata_comp_vpos_i : outdata_comp_vpos port map (
wa0_data => mux_663,
wa0_addr => mux_664,
clk => sig_clock,
ra0_addr => mux_665,
ra0_data => sig_1648,
wa0_en => sig_1295
);
outdata_comp_hpos_i : outdata_comp_hpos port map (
wa0_data => mux_659,
wa0_addr => mux_660,
clk => sig_clock,
ra0_addr => mux_661,
ra0_data => sig_1647,
wa0_en => sig_1295
);
outdata_comp_buf_i : outdata_comp_buf port map (
wa0_data => sig_1631,
wa0_addr => sig_1694,
clk => sig_clock,
ra0_addr => sig_1693,
ra0_data => sig_1646,
wa0_en => sig_1013
);
izigzag_index_i : izigzag_index port map (
clk => sig_clock,
ra0_addr => get_dqt_i(5 downto 0),
ra0_data => sig_1645
);
jpegfilebuf_i : jpegfilebuf port map (
wa0_data => read8_ret0_195,
wa0_addr => jpeg2bmp_main_i(12 downto 0),
clk => sig_clock,
ra0_addr => mux_652,
ra0_data => sig_1644,
wa0_en => sig_1041
);
huffbuff_i : huffbuff port map (
wa0_data => mux_567,
wa0_addr => mux_568,
clk => sig_clock,
ra0_addr => mux_569,
ra0_data => sig_1643,
wa0_en => sig_1428
);
idctbuff_i : idctbuff port map (
wa0_data => mux_561,
wa0_addr => mux_562,
clk => sig_clock,
ra2_data => sig_1642,
ra2_addr => mux_563,
ra1_data => sig_1641,
ra1_addr => sig_1692,
ra0_addr => mux_565,
ra0_data => sig_1640,
wa0_en => sig_1474
);
quantbuff_i : quantbuff port map (
wa0_data => mux_557,
wa0_addr => mux_558,
clk => sig_clock,
ra0_addr => mux_559,
ra0_data => sig_1639,
wa0_en => sig_1431
);
extend_mask_i : extend_mask port map (
clk => sig_clock,
ra0_addr => decodehuffmcu_s(4 downto 0),
ra0_data => sig_1638
);
bit_set_mask_i : bit_set_mask port map (
clk => sig_clock,
ra0_addr => mux_524,
ra0_data => sig_1637
);
lmask_i : lmask port map (
clk => sig_clock,
ra0_addr => buf_getv_n(4 downto 0),
ra0_data => sig_1636
);
huff_make_dhuff_tb_ac_huffsize_i : huff_make_dhuff_tb_ac_huffsize port map (
wa0_data => mux_476,
wa0_addr => huff_make_dhuff_tb_ac_p(8 downto 0),
clk => sig_clock,
ra0_addr => mux_478,
ra0_data => sig_1635,
wa0_en => sig_1501
);
huff_make_dhuff_tb_ac_huffcode_i : huff_make_dhuff_tb_ac_huffcode port map (
wa0_data => huff_make_dhuff_tb_ac_code,
wa0_addr => huff_make_dhuff_tb_ac_p(8 downto 0),
clk => sig_clock,
ra0_addr => huff_make_dhuff_tb_ac_p(8 downto 0),
ra0_data => sig_1634,
wa0_en => sig_1024
);
huff_make_dhuff_tb_dc_huffsize_i : huff_make_dhuff_tb_dc_huffsize port map (
wa0_data => mux_443,
wa0_addr => huff_make_dhuff_tb_dc_p(8 downto 0),
clk => sig_clock,
ra0_addr => mux_445,
ra0_data => sig_1633,
wa0_en => sig_1530
);
huff_make_dhuff_tb_dc_huffcode_i : huff_make_dhuff_tb_dc_huffcode port map (
wa0_data => huff_make_dhuff_tb_dc_code,
wa0_addr => huff_make_dhuff_tb_dc_p(8 downto 0),
clk => sig_clock,
ra0_addr => huff_make_dhuff_tb_dc_p(8 downto 0),
ra0_data => sig_1632,
wa0_en => sig_1036
);
rgb_buf_i : rgb_buf port map (
wa0_data => mux_378,
wa0_addr => mux_379,
clk => sig_clock,
ra0_addr => sig_1691,
ra0_data => sig_1631,
wa0_en => sig_1236
);
zigzag_index_i : zigzag_index port map (
clk => sig_clock,
ra0_addr => izigzagmatrix_i(5 downto 0),
ra0_data => sig_1630
);
shr_212_i : shr_212 port map (
output => sig_1629,
input => mux_322,
shift => mux_323,
padding => '0'
);
mul_209_i : mul_209 port map (
output => sig_1628,
in_b => mux_315,
in_a => mux_316
);
mul_210_i : mul_210 port map (
output => sig_1627,
in_b => sig_1690,
in_a => mux_314
);
shl_211_i : shl_211 port map (
output => sig_1626,
input => current_read_byte,
shift => buf_getv_p(5 downto 0),
padding => '0'
);
sub_206_i : sub_206 port map (
gt => sig_1625,
output => sig_1624,
sign => '1',
in_b => mux_306,
in_a => mux_307
);
sub_207_i : sub_207 port map (
ge => sig_1623,
le => sig_1622,
output => sig_1621,
sign => '1',
in_b => mux_302,
in_a => mux_303
);
sub_208_i : sub_208 port map (
ge => sig_1620,
output => sig_1619,
sign => '1',
in_b => "00000000000000000000000000000000000000000",
in_a => sig_1689
);
sub_205_i : sub_205 port map (
gt => sig_1618,
ge => sig_1617,
lt => sig_1616,
le => sig_1615,
output => sig_1614,
sign => '1',
in_b => mux_290,
in_a => mux_291
);
add_202_i : add_202 port map (
output => sig_1613,
in_b => mux_274,
in_a => mux_275
);
add_203_i : add_203 port map (
output => sig_1612,
in_b => mux_271,
in_a => mux_272
);
add_204_i : add_204 port map (
output => sig_1611,
in_b => "0000000000000000000000001",
in_a => sig_1688
);
add_201_i : add_201 port map (
output => sig_1610,
in_b => mux_265,
in_a => mux_266
);
add_200_i : add_200 port map (
output => sig_1609,
in_b => mux_260,
in_a => mux_261
);
cmp_775_i : cmp_775 port map (
eq => augh_test_158,
in1 => sig_1687,
in0 => "00000000000000000000000000001111"
);
cmp_779_i : cmp_779 port map (
eq => sig_1608,
in1 => sig_1686,
in0 => "00000000000000000000000000000000"
);
cmp_780_i : cmp_780 port map (
ne => sig_1607,
in1 => sig_1685,
in0 => "00000000000000000000000000000000"
);
cmp_787_i : cmp_787 port map (
eq => sig_1606,
in1 => '0',
in0 => sig_1610(0)
);
cmp_788_i : cmp_788 port map (
eq => sig_1605,
in1 => "000",
in0 => sig_1642(2 downto 0)
);
cmp_790_i : cmp_790 port map (
ne => sig_1604,
in1 => sig_1624(3 downto 0),
in0 => "0000"
);
cmp_792_i : cmp_792 port map (
eq => augh_test_134,
in1 => sig_1660,
in0 => "00000000000000000000000000000000"
);
cmp_793_i : cmp_793 port map (
eq => augh_test_131,
in1 => sig_1633,
in0 => "00000000000000000000000000000000"
);
cmp_794_i : cmp_794 port map (
eq => augh_test_126,
in1 => sig_1658,
in0 => "00000000000000000000000000000000"
);
cmp_791_i : cmp_791 port map (
ne => augh_test_148,
in1 => decodehuffman_dc,
in0 => "00000000000000000000000000000000"
);
cmp_804_i : cmp_804 port map (
ne => augh_test_113,
in1 => and_803,
in0 => "00000000000000000000000000000000"
);
cmp_800_i : cmp_800 port map (
eq => augh_test_118,
in1 => buf_getv_p,
in0 => "00000000000000000000000000000000"
);
cmp_799_i : cmp_799 port map (
eq => augh_test_123,
in1 => sig_1635,
in0 => "00000000000000000000000000000000"
);
cmp_865_i : cmp_865 port map (
ne => sig_1603,
in1 => sig_1624(2 downto 0),
in0 => "000"
);
cmp_882_i : cmp_882 port map (
eq => augh_test_157,
in1 => and_881,
in0 => "00000000000000000000000000000000"
);
cmp_885_i : cmp_885 port map (
ne => sig_1602,
in1 => and_884,
in0 => "00000000000000000000000000000000"
);
cmp_887_i : cmp_887 port map (
eq => sig_1601,
in1 => and_884,
in0 => "00000000000000000000000000000000"
);
mul_215_i : mul_215 port map (
output => sig_1600,
in_b => "00000000000000000000000111011001",
in_a => chenidct_b2
);
cmp_850_i : cmp_850 port map (
eq => augh_test_103,
in1 => sig_1684,
in0 => "00000000000000000000000011011011"
);
cmp_851_i : cmp_851 port map (
eq => augh_test_104,
in1 => sig_1683,
in0 => "00000000000000000000000011011001"
);
cmp_861_i : cmp_861 port map (
eq => augh_test_150,
in1 => and_860,
in0 => "00000000000000000000000000000000"
);
cmp_871_i : cmp_871 port map (
eq => sig_1599,
in1 => sig_1682,
in0 => "00000000000000000000000000000000"
);
cmp_873_i : cmp_873 port map (
eq => sig_1598,
in1 => sig_1664,
in0 => "00000010"
);
cmp_879_i : cmp_879 port map (
ne => augh_test_6,
in1 => sig_1681,
in0 => "00000000000000000000000011111111"
);
cmp_880_i : cmp_880 port map (
eq => augh_test_9,
in1 => sig_1680,
in0 => "00000000000000000000000011111111"
);
sub_217_i : sub_217 port map (
ge => sig_1597,
output => sig_1596,
sign => '1',
in_b => "00000000000000000000000000000000000000000",
in_a => sig_1679
);
cmp_863_i : cmp_863 port map (
ne => sig_1595,
in1 => sig_1614(2 downto 0),
in0 => "000"
);
cmp_868_i : cmp_868 port map (
eq => sig_1594,
in1 => "000000000000000000000000",
in0 => "000000000000000000000000"
);
cmp_877_i : cmp_877 port map (
ne => augh_test_109,
in1 => sig_1678,
in0 => "00000000000000000000000000000000"
);
cmp_878_i : cmp_878 port map (
ne => augh_test_10,
in1 => sig_1677,
in0 => "00000000000000000000000000000000"
);
sub_218_i : sub_218 port map (
le => sig_1593,
output => sig_1592,
sign => '1',
in_b => "00000000000000000000000000000000011111111",
in_a => sig_1676
);
sub_220_i : sub_220 port map (
gt => sig_1591,
output => sig_1590,
sign => '1',
in_b => "00000000000000000000000000000000011111111",
in_a => sig_1675
);
sub_221_i : sub_221 port map (
gt => sig_1589,
output => sig_1588,
sign => '1',
in_b => "00000000000000000000000000000000011111111",
in_a => sig_1674
);
mul_222_i : mul_222 port map (
output => sig_1587,
in_b => "00000000000000000000000010110101",
in_a => mux_233
);
sub_219_i : sub_219 port map (
le => sig_1586,
output => sig_1585,
sign => '1',
in_b => "00000000000000000000000000000000011111111",
in_a => sig_1673
);
cmp_962_i : cmp_962 port map (
ne => augh_test_62,
in1 => get_sos_j,
in0 => "11111111111111111111111111111111"
);
cmp_975_i : cmp_975 port map (
ne => augh_test_154,
in1 => decodehuffmcu_s,
in0 => "00000000000000000000000000000000"
);
fsm_224_i : fsm_224 port map (
clock => sig_clock,
reset => sig_reset,
out40 => sig_1584,
in2 => augh_test_152,
in11 => augh_test_131,
out146 => sig_1583,
out148 => sig_1582,
out150 => sig_1581,
out152 => sig_1580,
in12 => augh_test_128,
out153 => sig_1579,
out154 => sig_1578,
in13 => augh_test_127,
out156 => sig_1577,
out157 => sig_1576,
out160 => sig_1575,
out162 => sig_1574,
out165 => sig_1573,
out170 => sig_1572,
out171 => sig_1571,
out173 => sig_1570,
out175 => sig_1569,
out177 => sig_1568,
out180 => sig_1567,
out184 => sig_1566,
in14 => augh_test_126,
out186 => sig_1565,
out189 => sig_1564,
out191 => sig_1563,
out192 => sig_1562,
out193 => sig_1561,
out197 => sig_1560,
out199 => sig_1559,
out201 => sig_1558,
out202 => sig_1557,
out205 => sig_1556,
out207 => sig_1555,
out208 => sig_1554,
out209 => sig_1553,
out210 => sig_1552,
out212 => sig_1551,
out213 => sig_1550,
in15 => augh_test_125,
out221 => sig_1549,
out222 => sig_1548,
out224 => sig_1547,
out225 => sig_1546,
out228 => sig_1545,
out229 => sig_1544,
out230 => sig_1543,
out231 => sig_1542,
out99 => sig_1541,
in6 => augh_test_142,
out92 => sig_1540,
out232 => sig_1539,
in16 => augh_test_123,
out234 => sig_1538,
out236 => sig_1537,
out239 => sig_1536,
out240 => sig_1535,
out241 => sig_1534,
out245 => sig_1533,
out246 => sig_1532,
out247 => sig_1531,
out251 => sig_1530,
out252 => sig_1529,
out253 => sig_1528,
out255 => sig_1527,
out256 => sig_1526,
out258 => sig_1525,
out259 => sig_1524,
in17 => augh_test_120,
out263 => sig_1523,
out264 => sig_1522,
out266 => sig_1521,
in18 => augh_test_119,
out267 => sig_1520,
out268 => sig_1519,
out270 => sig_1518,
out273 => sig_1517,
out275 => sig_1516,
out276 => sig_1515,
in19 => augh_test_118,
out279 => sig_1514,
in20 => augh_test_115,
out281 => sig_1513,
out282 => sig_1512,
in21 => augh_test_114,
out283 => sig_1511,
out286 => sig_1510,
out289 => sig_1509,
out296 => sig_1508,
out297 => sig_1507,
out299 => sig_1506,
out300 => sig_1505,
out304 => sig_1504,
out305 => sig_1503,
in22 => augh_test_113,
out306 => sig_1502,
out310 => sig_1501,
out311 => sig_1500,
out313 => sig_1499,
out314 => sig_1498,
in23 => augh_test_111,
out316 => sig_1497,
out317 => sig_1496,
out320 => sig_1495,
out322 => sig_1494,
out324 => sig_1493,
out325 => sig_1492,
out326 => sig_1491,
out328 => sig_1490,
out332 => sig_1489,
out333 => sig_1488,
out334 => sig_1487,
out335 => sig_1486,
out338 => sig_1485,
out339 => sig_1484,
out341 => sig_1483,
out342 => sig_1482,
out344 => sig_1481,
out93 => sig_1480,
out98 => sig_1479,
out85 => sig_1478,
out87 => sig_1477,
out88 => sig_1476,
out80 => sig_1475,
out82 => sig_1474,
out83 => sig_1473,
out84 => sig_1472,
in5 => augh_test_144,
out77 => sig_1471,
out78 => sig_1470,
out71 => sig_1469,
out72 => sig_1468,
in4 => augh_test_148,
out65 => sig_1467,
out67 => sig_1466,
out60 => sig_1465,
out64 => sig_1464,
in3 => augh_test_151,
out59 => sig_1463,
out53 => sig_1462,
out55 => sig_1461,
out49 => sig_1460,
out44 => sig_1459,
out104 => sig_1458,
out107 => sig_1457,
out111 => sig_1456,
out112 => sig_1455,
out114 => sig_1454,
in7 => augh_test_138,
out117 => sig_1453,
out119 => sig_1452,
out122 => sig_1451,
in8 => augh_test_136,
out128 => sig_1450,
in9 => augh_test_134,
out129 => sig_1449,
out130 => sig_1448,
out133 => sig_1447,
out134 => sig_1446,
out136 => sig_1445,
out137 => sig_1444,
in10 => augh_test_133,
out139 => sig_1443,
out143 => sig_1442,
out144 => sig_1441,
out32 => sig_1440,
out35 => sig_1439,
out27 => sig_1438,
out25 => sig_1437,
out26 => sig_1436,
in1 => augh_test_158,
out15 => sig_1435,
out16 => sig_1434,
out11 => sig_1433,
out13 => sig_1432,
out14 => sig_1431,
out7 => sig_1430,
out1 => sig_1429,
out2 => sig_1428,
out3 => sig_1427,
out4 => sig_1426,
in0 => augh_test_159,
in24 => augh_test_107,
out346 => sig_1425,
out347 => sig_1424,
out348 => sig_1423,
out349 => sig_1422,
in25 => augh_test_106,
out350 => sig_1421,
out351 => sig_1420,
out355 => sig_1419,
out356 => sig_1418,
out357 => sig_1417,
out358 => sig_1416,
out360 => sig_1415,
out362 => sig_1414,
out363 => sig_1413,
out364 => sig_1412,
out365 => sig_1411,
out366 => sig_1410,
out370 => sig_1409,
out371 => sig_1408,
out372 => sig_1407,
out373 => sig_1406,
out375 => sig_1405,
in26 => augh_test_105,
out376 => sig_1404,
out378 => sig_1403,
out379 => sig_1402,
out381 => sig_1401,
out382 => sig_1400,
in27 => augh_test_99,
out384 => sig_1399,
in28 => augh_test_100,
out391 => sig_1398,
out395 => sig_1397,
out396 => sig_1396,
out401 => sig_1395,
out402 => sig_1394,
out403 => sig_1393,
out404 => sig_1392,
out405 => sig_1391,
out407 => sig_1390,
out408 => sig_1389,
out409 => sig_1388,
out410 => sig_1387,
in29 => augh_test_101,
out412 => sig_1386,
out414 => sig_1385,
out415 => sig_1384,
out417 => sig_1383,
out418 => sig_1382,
out419 => sig_1381,
out420 => sig_1380,
out422 => sig_1379,
out424 => sig_1378,
out425 => sig_1377,
out426 => sig_1376,
in30 => augh_test_102,
out428 => sig_1375,
out429 => sig_1374,
out432 => sig_1373,
out433 => sig_1372,
out434 => sig_1371,
out437 => sig_1370,
out440 => sig_1369,
out441 => sig_1368,
in31 => augh_test_103,
out443 => sig_1367,
in32 => augh_test_104,
out445 => sig_1366,
out447 => sig_1365,
out448 => sig_1364,
out450 => sig_1363,
in33 => augh_test_94,
out453 => sig_1362,
out455 => sig_1361,
out458 => sig_1360,
in34 => augh_test_90,
out462 => sig_1359,
out464 => sig_1358,
out467 => sig_1357,
out468 => sig_1356,
out472 => sig_1355,
in35 => augh_test_89,
out478 => sig_1354,
out479 => sig_1353,
out480 => sig_1352,
out487 => sig_1351,
out488 => sig_1350,
in36 => augh_test_83,
out491 => sig_1349,
out496 => sig_1348,
out497 => sig_1347,
out498 => sig_1346,
out500 => sig_1345,
out504 => sig_1344,
out505 => sig_1343,
in37 => augh_test_150,
out506 => sig_1342,
out508 => sig_1341,
in38 => augh_test_77,
out510 => sig_1340,
out513 => sig_1339,
out514 => sig_1338,
out515 => sig_1337,
out517 => sig_1336,
out519 => sig_1335,
in39 => augh_test_72,
out523 => sig_1334,
out526 => sig_1333,
out527 => sig_1332,
out528 => sig_1331,
out530 => sig_1330,
out531 => sig_1329,
out533 => sig_1328,
out534 => sig_1327,
out537 => sig_1326,
out538 => sig_1325,
out549 => sig_1324,
out558 => sig_1323,
out559 => sig_1322,
out561 => sig_1321,
in40 => augh_test_67,
out566 => sig_1320,
out567 => sig_1319,
out568 => sig_1318,
out569 => sig_1317,
out570 => sig_1316,
out572 => sig_1315,
out574 => sig_1314,
out575 => sig_1313,
out577 => sig_1312,
in41 => augh_test_52,
out578 => sig_1311,
out581 => sig_1310,
out589 => sig_1309,
out590 => sig_1308,
out595 => sig_1307,
out597 => sig_1306,
out599 => sig_1305,
out601 => sig_1304,
out602 => sig_1303,
out607 => sig_1302,
out610 => sig_1301,
out612 => sig_1300,
in42 => augh_test_53,
out614 => sig_1299,
out621 => sig_1298,
out628 => sig_1297,
out635 => sig_1296,
out636 => sig_1295,
out638 => sig_1294,
out640 => sig_1293,
out643 => sig_1292,
out646 => sig_1291,
out649 => sig_1290,
out651 => sig_1289,
out656 => sig_1288,
in43 => augh_test_49,
out658 => sig_1287,
out659 => sig_1286,
out661 => sig_1285,
out663 => sig_1284,
out664 => sig_1283,
in44 => augh_test_109,
out667 => sig_1282,
out668 => sig_1281,
out670 => sig_1280,
out672 => sig_1279,
out674 => sig_1278,
in45 => augh_test_26,
out679 => sig_1277,
out681 => sig_1276,
out683 => sig_1275,
out686 => sig_1274,
out688 => sig_1273,
out690 => sig_1272,
out692 => sig_1271,
out694 => sig_1270,
out696 => sig_1269,
out697 => sig_1268,
out698 => sig_1267,
out699 => sig_1266,
out700 => sig_1265,
out703 => sig_1264,
out704 => sig_1263,
out706 => sig_1262,
out708 => sig_1261,
out710 => sig_1260,
out712 => sig_1259,
out715 => sig_1258,
out718 => sig_1257,
in46 => augh_test_10,
out722 => sig_1256,
out724 => sig_1255,
out726 => sig_1254,
out728 => sig_1253,
out731 => sig_1252,
out733 => sig_1251,
out734 => sig_1250,
out737 => sig_1249,
out739 => sig_1248,
out740 => sig_1247,
out743 => sig_1246,
out745 => sig_1245,
out746 => sig_1244,
in47 => augh_test_6,
out749 => sig_1243,
out753 => sig_1242,
out755 => sig_1241,
out759 => sig_1240,
in48 => augh_test_9,
out762 => sig_1239,
out764 => sig_1238,
out765 => sig_1237,
out767 => sig_1236,
out768 => sig_1235,
in49 => augh_test_157,
out772 => sig_1234,
in50 => stdout_ack,
out775 => sig_1233,
out776 => sig_1232,
out778 => sig_1231,
out783 => sig_1230,
out784 => sig_1229,
out787 => sig_1228,
out791 => sig_1227,
in51 => stdin_ack,
out794 => sig_1226,
out795 => sig_1225,
in52 => augh_test_62,
out799 => sig_1224,
out802 => sig_1223,
out806 => sig_1222,
out809 => sig_1221,
out812 => sig_1220,
out815 => sig_1219,
out826 => sig_1218,
out828 => sig_1217,
in53 => augh_test_122,
in54 => augh_test_197,
out843 => sig_1216,
out848 => sig_1215,
out852 => sig_1214,
in55 => augh_test_196,
out855 => sig_1213,
out858 => sig_1212,
in56 => augh_test_189,
out860 => sig_1211,
out861 => sig_1210,
out863 => sig_1209,
out866 => sig_1208,
out872 => sig_1207,
in57 => augh_test_188,
out874 => sig_1206,
out876 => sig_1205,
out879 => sig_1204,
out882 => sig_1203,
out886 => sig_1202,
out887 => sig_1201,
in58 => augh_test_187,
out888 => sig_1200,
out892 => sig_1199,
out894 => sig_1198,
out895 => sig_1197,
out896 => sig_1196,
out901 => sig_1195,
out902 => sig_1194,
out903 => sig_1193,
out905 => sig_1192,
out907 => sig_1191,
out918 => sig_1190,
out920 => sig_1189,
out921 => sig_1188,
out923 => sig_1187,
out925 => sig_1186,
out928 => sig_1185,
out929 => sig_1184,
out931 => sig_1183,
out933 => sig_1182,
out936 => stdout_rdy,
out937 => sig_1181,
out938 => sig_1180,
out939 => sig_1179,
out942 => sig_1178,
out943 => sig_1177,
out944 => sig_1176,
out947 => sig_1175,
out948 => sig_1174,
out949 => sig_1173,
out951 => sig_1172,
in59 => augh_test_186,
out952 => sig_1171,
out953 => sig_1170,
out955 => sig_1169,
out956 => sig_1168,
out957 => sig_1167,
out958 => sig_1166,
in60 => augh_test_184,
in61 => augh_test_183,
out962 => sig_1165,
out963 => sig_1164,
out972 => sig_1163,
out973 => sig_1162,
out974 => sig_1161,
in62 => augh_test_182,
out978 => sig_1160,
out979 => sig_1159,
out981 => sig_1158,
out982 => sig_1157,
out985 => sig_1156,
out986 => sig_1155,
out989 => sig_1154,
in63 => augh_test_180,
in64 => augh_test_179,
in65 => augh_test_178,
in66 => augh_test_194,
in67 => augh_test_154,
in68 => augh_test_130,
in69 => augh_test_132,
in70 => augh_test_124,
in71 => augh_test_171,
in72 => augh_test_168,
in73 => augh_test_167,
in74 => augh_test_166,
in75 => augh_test_165,
in76 => augh_test_108,
in77 => sig_start,
in78 => augh_test_155,
out990 => sig_1153,
out991 => sig_1152,
out993 => sig_1151,
out994 => sig_1150,
out996 => sig_1149,
out997 => sig_1148,
out998 => sig_1147,
out999 => sig_1146,
out1000 => sig_1145,
out1002 => sig_1144,
out1003 => sig_1143,
out1005 => sig_1142,
out1006 => sig_1141,
out1007 => sig_1140,
out1009 => sig_1139,
out1011 => sig_1138,
out1012 => sig_1137,
out1013 => sig_1136,
out1014 => sig_1135,
out1015 => sig_1134,
out1016 => sig_1133,
out1018 => sig_1132,
out1019 => sig_1131,
out1021 => sig_1130,
out1022 => sig_1129,
out1024 => sig_1128,
out1026 => sig_1127,
out1027 => sig_1126,
out1029 => sig_1125,
out1030 => sig_1124,
out1032 => sig_1123,
out1033 => sig_1122,
out1035 => sig_1121,
out1036 => sig_1120,
out1037 => sig_1119,
out1057 => sig_1118,
out1068 => sig_1117,
out1069 => sig_1116,
out1070 => sig_1115,
out1072 => sig_1114,
out1073 => sig_1113,
out1075 => sig_1112,
out1078 => sig_1111,
out1080 => sig_1110,
out1082 => sig_1109,
out1083 => sig_1108,
out1084 => sig_1107,
out1085 => sig_1106,
out1088 => sig_1105,
out1089 => sig_1104,
out1091 => sig_1103,
out1092 => sig_1102,
out1094 => sig_1101,
out1096 => sig_1100,
out1098 => sig_1099,
out1101 => sig_1098,
out1104 => sig_1097,
out1107 => sig_1096,
out1109 => sig_1095,
out1111 => sig_1094,
out1114 => sig_1093,
out1119 => sig_1092,
out1121 => sig_1091,
out1125 => sig_1090,
out1126 => sig_1089,
out1128 => sig_1088,
out1131 => sig_1087,
out1134 => sig_1086,
out1137 => sig_1085,
out1139 => sig_1084,
out1141 => sig_1083,
out1145 => sig_1082,
out1146 => sig_1081,
out1147 => sig_1080,
out1150 => sig_1079,
out1151 => sig_1078,
out1152 => sig_1077,
out1155 => sig_1076,
out1158 => sig_1075,
out1160 => sig_1074,
out1164 => sig_1073,
out1166 => sig_1072,
out1169 => sig_1071,
out1171 => sig_1070,
out1174 => sig_1069,
out1175 => sig_1068,
out1176 => sig_1067,
out1180 => sig_1066,
out1181 => sig_1065,
out1182 => sig_1064,
out1185 => sig_1063,
out1186 => sig_1062,
out1187 => sig_1061,
out1190 => sig_1060,
out1213 => sig_1059,
out1215 => sig_1058,
out1217 => sig_1057,
out1220 => sig_1056,
out1221 => sig_1055,
out1223 => sig_1054,
out1228 => sig_1053,
out1229 => sig_1052,
out1231 => sig_1051,
out1235 => sig_1050,
out1236 => sig_1049,
out1240 => sig_1048,
out1243 => sig_1047,
out1250 => sig_1046,
out1252 => sig_1045,
out1253 => sig_1044,
out1258 => sig_1043,
out1262 => sig_1042,
out1266 => sig_1041,
out1269 => sig_1040,
out1275 => sig_1039,
out1278 => sig_1038,
out1279 => sig_1037,
out1284 => sig_1036,
out1286 => sig_1035,
out1287 => sig_1034,
out1289 => sig_1033,
out1290 => sig_1032,
out1292 => sig_1031,
out1293 => sig_1030,
out1295 => sig_1029,
out1298 => sig_1028,
out1301 => sig_1027,
out1302 => sig_1026,
out1303 => sig_1025,
out1308 => sig_1024,
out1309 => sig_1023,
out1311 => sig_1022,
out1318 => sig_1021,
out1319 => sig_1020,
out1320 => sig_1019,
out1323 => sig_1018,
out1324 => sig_1017,
out1326 => sig_1016,
out1327 => sig_1015,
out1329 => sig_1014,
out1337 => sig_1013,
out1339 => sig_1012,
out1340 => sig_1011,
out1341 => sig_1010,
out1344 => sig_1009,
out1346 => sig_1008,
out1349 => sig_1007,
out1353 => sig_1006,
out1356 => sig_1005,
out1362 => sig_1004,
out1363 => sig_1003,
out1364 => sig_1002,
out1365 => sig_1001,
out1366 => sig_1000,
out1368 => sig_999,
out1370 => sig_998,
out1375 => sig_997,
out1378 => sig_996,
out1381 => sig_995,
out1383 => sig_994,
out1387 => sig_993
);
muxb_784_i : muxb_784 port map (
in_sel => sig_1616,
out_data => sig_992,
in_data0 => sig_1609(31 downto 0),
in_data1 => sig_1613
);
cmp_964_i : cmp_964 port map (
eq => sig_991,
in1 => sig_1635,
in0 => huff_make_dhuff_tb_ac_size
);
cmp_972_i : cmp_972 port map (
ne => augh_test_196,
in1 => jpeg2bmp_main_i,
in0 => "00000000000000000000000000000010"
);
cmp_973_i : cmp_973 port map (
eq => augh_test_180,
in1 => sig_1672,
in0 => "00000000000000000000000000000000"
);
cmp_974_i : cmp_974 port map (
ne => augh_test_194,
in1 => jpeg2bmp_main_i,
in0 => "00000000000000000001010001010110"
);
cmp_985_i : cmp_985 port map (
eq => augh_test_108,
in1 => sig_1671,
in0 => "00000000000000000000000011111111"
);
cmp_971_i : cmp_971 port map (
ne => augh_test_197,
in1 => jpeg2bmp_main_j,
in0 => "00000000000000000001010010111101"
);
cmp_977_i : cmp_977 port map (
eq => sig_990,
in1 => sig_1633,
in0 => huff_make_dhuff_tb_dc_size
);
-- Behaviour of component 'mux_967' model 'mux'
mux_967 <=
(repeat(32, sig_1620) and mux_968);
-- Behaviour of component 'and_976' model 'and'
and_976 <=
sig_1615 and
sig_990;
-- Behaviour of component 'and_982' model 'and'
and_982 <=
"00000000000000000000000000001111" and
decodehuffman_ac;
-- Behaviour of component 'and_983' model 'and'
and_983 <=
"0000000000000000000000001111" and
decodehuffman_ac(31 downto 4);
-- Behaviour of component 'and_984' model 'and'
and_984 <=
sig_1636 and
buf_getv_rv;
-- Behaviour of component 'mux_689' model 'mux'
mux_689 <=
(repeat(32, sig_1034) and sig_1634) or
(repeat(32, sig_1520) and "11111111111111111111111111111111") or
(repeat(32, sig_1523) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_690' model 'mux'
mux_690 <=
(repeat(7, sig_1519) and huff_make_dhuff_tb_ac_tbl_no & huff_make_dhuff_tb_ac_l(5 downto 0)) or
(repeat(7, sig_1523) and huff_make_dhuff_tb_ac_tbl_no & huff_make_dhuff_tb_ac_p_dhtbl_ml(5 downto 0));
-- Behaviour of component 'mux_691' model 'mux'
mux_691 <=
(repeat(7, sig_1523) and huff_make_dhuff_tb_ac_tbl_no & huff_make_dhuff_tb_ac_p_dhtbl_ml(5 downto 0)) or
(repeat(7, sig_1568) and decodehuffman_ac_tbl_no & decodehuffman_ac_l(5 downto 0)) or
(repeat(7, sig_1570) and decodehuffman_ac_tbl_no & decodehuffman_ac_dhuff_ml);
-- Behaviour of component 'and_853' model 'and'
and_853 <=
sig_1636 and
sig_1629;
-- Behaviour of component 'mux_233' model 'mux'
mux_233 <=
(repeat(32, sig_1118) and sig_1609(31 downto 0)) or
(repeat(32, sig_1324) and sig_1624(31 downto 0));
-- Behaviour of component 'mux_671' model 'mux'
mux_671 <=
(repeat(32, sig_1183) and i_jinfo_jpeg_data) or
(repeat(32, sig_1441) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_665' model 'mux'
mux_665 <=
(repeat(2, sig_1162) and write4blocks_i) or
(repeat(2, sig_1196) and decode_start_i(1 downto 0)) or
(repeat(2, sig_1296) and writeblock_i);
-- Behaviour of component 'mux_663' model 'mux'
mux_663 <=
(repeat(32, sig_1163) and sig_1609(30 downto 0) & sig_1648(0)) or
(repeat(32, sig_1161) and mux_896) or
(repeat(32, sig_1215) and mux_874) or
(repeat(32, sig_1297) and sig_1609(31 downto 0));
-- Behaviour of component 'mux_664' model 'mux'
mux_664 <=
(repeat(2, sig_1043) and decode_start_i(1 downto 0)) or
(repeat(2, sig_1162) and write4blocks_i) or
(repeat(2, sig_1296) and writeblock_i);
-- Behaviour of component 'mux_659' model 'mux'
mux_659 <=
(repeat(32, sig_1163) and sig_1610(30 downto 0) & sig_1647(0)) or
(repeat(32, sig_1161) and mux_897) or
(repeat(32, sig_1215) and mux_875) or
(repeat(32, sig_1297) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_660' model 'mux'
mux_660 <=
(repeat(2, sig_1043) and decode_start_i(1 downto 0)) or
(repeat(2, sig_1162) and write4blocks_i) or
(repeat(2, sig_1296) and writeblock_i);
-- Behaviour of component 'mux_661' model 'mux'
mux_661 <=
(repeat(2, sig_1162) and write4blocks_i) or
(repeat(2, sig_1196) and decode_start_i(1 downto 0)) or
(repeat(2, sig_1296) and writeblock_i);
-- Behaviour of component 'mux_652' model 'mux'
mux_652 <=
(repeat(13, sig_1247) and readbuf_idx(12 downto 0)) or
(repeat(13, sig_1441) and curhuffreadbuf_idx(12 downto 0));
-- Behaviour of component 'mux_648' model 'mux'
mux_648 <=
(repeat(32, sig_1247) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_633' model 'mux'
mux_633 <=
(repeat(32, sig_1211) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_622' model 'mux'
mux_622 <=
(repeat(32, sig_1251) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_614' model 'mux'
mux_614 <=
(repeat(32, sig_1269) and "00000000000000000000000000000011") or
(repeat(32, sig_1287) and sig_1614(31 downto 0));
-- Behaviour of component 'mux_616' model 'mux'
mux_616 <=
(repeat(32, sig_1254) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_602' model 'mux'
mux_602 <=
(repeat(32, sig_1198) and "00000000000000000000000000000001") or
(repeat(32, sig_1479) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_600' model 'mux'
mux_600 <=
(repeat(32, sig_1458) and sig_1609(31 downto 0));
-- Behaviour of component 'mux_593' model 'mux'
mux_593 <=
(repeat(32, sig_1240) and mux_870) or
(repeat(32, sig_1317) and sig_1614(31 downto 0));
-- Behaviour of component 'mux_587' model 'mux'
mux_587 <=
(repeat(32, sig_1335) and sig_1609(31 downto 0));
-- Behaviour of component 'mux_585' model 'mux'
mux_585 <=
(repeat(16, sig_1337) and read_word) or
(repeat(16, sig_1339) and "00000000" & read_byte);
-- Behaviour of component 'mux_580' model 'mux'
mux_580 <=
(repeat(8, sig_1346) and read_byte) or
(repeat(8, sig_1348) and next_marker);
-- Behaviour of component 'mux_569' model 'mux'
mux_569 <=
(repeat(8, sig_1027) and decodehuffmcu_bufdim1 & "000000") or
(repeat(8, sig_1268) and decodehuffmcu_bufdim1 & decodehuffmcu_k(5 downto 0)) or
(repeat(8, sig_1436) and decode_block_in_buf_idx & sig_1630);
-- Behaviour of component 'mux_567' model 'mux'
mux_567 <=
(repeat(32, sig_1257) and sig_1610(31 downto 0)) or
(repeat(32, sig_1000) and decodehuffmcu_diff) or
(repeat(32, sig_1202) and buf_getv) or
(repeat(32, sig_1267) and or_866);
-- Behaviour of component 'mux_568' model 'mux'
mux_568 <=
(repeat(8, sig_1266) and decodehuffmcu_bufdim1 & decodehuffmcu_k(5 downto 0)) or
(repeat(8, sig_1000) and decodehuffmcu_bufdim1 & "000000") or
(repeat(8, sig_1443) and decodehuffmcu_bufdim1 & decodehuffmcu_i(5 downto 0)) or
(repeat(8, sig_1429) and decode_start_i(1 downto 0) & "000000");
-- Behaviour of component 'mux_563' model 'mux'
mux_563 <=
(repeat(9, sig_1555) and decode_block_out_buf_idx & "011000") or
(repeat(9, sig_1408) and decode_block_out_buf_idx & "001010") or
(repeat(9, sig_1407) and decode_block_out_buf_idx & "101010") or
(repeat(9, sig_1405) and decode_block_out_buf_idx & "010100") or
(repeat(9, sig_1403) and decode_block_out_buf_idx & "110101") or
(repeat(9, sig_1401) and decode_block_out_buf_idx & "111000") or
(repeat(9, sig_1510) and decode_block_out_buf_idx & "101000") or
(repeat(9, sig_1389) and decode_block_out_buf_idx & "011001") or
(repeat(9, sig_1388) and decode_block_out_buf_idx & "100110") or
(repeat(9, sig_1384) and decode_block_out_buf_idx & "111010") or
(repeat(9, sig_1382) and decode_block_out_buf_idx & "111011") or
(repeat(9, sig_1381) and decode_block_out_buf_idx & "111100") or
(repeat(9, sig_1377) and decode_block_out_buf_idx & "000100") or
(repeat(9, sig_1375) and decode_block_out_buf_idx & "100100") or
(repeat(9, sig_1372) and decode_block_out_buf_idx & "010010") or
(repeat(9, sig_1512) and decode_block_out_buf_idx & "000001") or
(repeat(9, sig_1515) and decode_block_out_buf_idx & "011110") or
(repeat(9, sig_1517) and decode_block_out_buf_idx & "011100") or
(repeat(9, sig_1418) and decode_block_out_buf_idx & "111101") or
(repeat(9, sig_1417) and decode_block_out_buf_idx & "100010") or
(repeat(9, sig_1415) and decode_block_out_buf_idx & "010111") or
(repeat(9, sig_1414) and decode_block_out_buf_idx & chenidct_aidx(5 downto 0)) or
(repeat(9, sig_1451) and decode_block_out_buf_idx & chenidct_i(5 downto 0)) or
(repeat(9, sig_1469) and decode_block_out_buf_idx & "010000") or
(repeat(9, sig_1370) and decode_block_out_buf_idx & "000111") or
(repeat(9, sig_1368) and decode_block_out_buf_idx & "001100") or
(repeat(9, sig_1366) and decode_block_out_buf_idx & "111111") or
(repeat(9, sig_1365) and decode_block_out_buf_idx & "101100") or
(repeat(9, sig_1362) and decode_block_out_buf_idx & "110010") or
(repeat(9, sig_1331) and decode_block_out_buf_idx & "000101") or
(repeat(9, sig_1330) and decode_block_out_buf_idx & "010001") or
(repeat(9, sig_1328) and decode_block_out_buf_idx & "001111") or
(repeat(9, sig_1326) and decode_block_out_buf_idx & "100111") or
(repeat(9, sig_1299) and yuvtorgb_yidx & yuvtorgb_i(5 downto 0)) or
(repeat(9, sig_1281) and decode_block_out_buf_idx & "011101") or
(repeat(9, sig_1279) and decode_block_out_buf_idx & "101110") or
(repeat(9, sig_1278) and decode_block_out_buf_idx & "110110") or
(repeat(9, sig_1265) and decode_block_out_buf_idx & "001110") or
(repeat(9, sig_1261) and decode_block_out_buf_idx & "001001") or
(repeat(9, sig_1238) and decode_block_out_buf_idx & "010110") or
(repeat(9, sig_1232) and decode_block_out_buf_idx & "001011") or
(repeat(9, sig_1177) and decode_block_out_buf_idx & "111110") or
(repeat(9, sig_1174) and decode_block_out_buf_idx & "100001") or
(repeat(9, sig_1171) and decode_block_out_buf_idx & "011111") or
(repeat(9, sig_1159) and decode_block_out_buf_idx & "000000") or
(repeat(9, sig_1157) and decode_block_out_buf_idx & "100000") or
(repeat(9, sig_1153) and decode_block_out_buf_idx & "000010") or
(repeat(9, sig_1151) and decode_block_out_buf_idx & "010101") or
(repeat(9, sig_1146) and decode_block_out_buf_idx & "101001") or
(repeat(9, sig_1144) and decode_block_out_buf_idx & "110111") or
(repeat(9, sig_1141) and decode_block_out_buf_idx & "001000") or
(repeat(9, sig_1137) and decode_block_out_buf_idx & "101011") or
(repeat(9, sig_1134) and decode_block_out_buf_idx & "111001") or
(repeat(9, sig_1132) and decode_block_out_buf_idx & "000110") or
(repeat(9, sig_1130) and decode_block_out_buf_idx & "011010") or
(repeat(9, sig_1126) and decode_block_out_buf_idx & "100101") or
(repeat(9, sig_1124) and decode_block_out_buf_idx & "011011") or
(repeat(9, sig_1122) and decode_block_out_buf_idx & "000011") or
(repeat(9, sig_1120) and decode_block_out_buf_idx & "100011") or
(repeat(9, sig_1116) and decode_block_out_buf_idx & "001101") or
(repeat(9, sig_1114) and decode_block_out_buf_idx & "101101") or
(repeat(9, sig_1108) and decode_block_out_buf_idx & "110011") or
(repeat(9, sig_1107) and decode_block_out_buf_idx & "010011") or
(repeat(9, sig_1104) and decode_block_out_buf_idx & "110100") or
(repeat(9, sig_1102) and decode_block_out_buf_idx & "110000") or
(repeat(9, sig_1096) and decode_block_out_buf_idx & "101111") or
(repeat(9, sig_1095) and decode_block_out_buf_idx & "110001") or
(repeat(9, sig_1088) and decode_block_out_buf_idx & chenidct_i(2 downto 0) & "000");
-- Behaviour of component 'mux_565' model 'mux'
mux_565 <=
(repeat(9, sig_1088) and decode_block_out_buf_idx & chenidct_i(2 downto 0) & "001") or
(repeat(9, sig_1299) and yuvtorgb_vidx & yuvtorgb_i(5 downto 0));
-- Behaviour of component 'mux_561' model 'mux'
mux_561 <=
(repeat(32, sig_1556) and sig_1610(24 downto 0) & sig_1642(6 downto 0)) or
(repeat(32, sig_1400) and mux_817) or
(repeat(32, sig_1399) and mux_819) or
(repeat(32, sig_1395) and sig_1609(31 downto 0)) or
(repeat(32, sig_1392) and sig_1614(31 downto 0)) or
(repeat(32, sig_1390) and mux_821) or
(repeat(32, sig_1416) and mux_807) or
(repeat(32, sig_1387) and mux_823) or
(repeat(32, sig_1386) and mux_825) or
(repeat(32, sig_1385) and mux_827) or
(repeat(32, sig_1383) and mux_829) or
(repeat(32, sig_1380) and mux_831) or
(repeat(32, sig_1379) and mux_833) or
(repeat(32, sig_1378) and mux_835) or
(repeat(32, sig_1374) and mux_837) or
(repeat(32, sig_1419) and mux_805) or
(repeat(32, sig_1513) and mux_797) or
(repeat(32, sig_1516) and mux_795) or
(repeat(32, sig_1409) and mux_809) or
(repeat(32, sig_1406) and mux_811) or
(repeat(32, sig_1404) and mux_813) or
(repeat(32, sig_1402) and mux_815) or
(repeat(32, sig_1451) and sig_992) or
(repeat(32, sig_1475) and mux_776) or
(repeat(32, sig_1373) and mux_839) or
(repeat(32, sig_1369) and mux_841) or
(repeat(32, sig_1364) and mux_843) or
(repeat(32, sig_1329) and mux_856) or
(repeat(32, sig_1327) and mux_858) or
(repeat(32, sig_1263) and sig_1610(31 downto 0)) or
(repeat(32, sig_1176) and mux_888) or
(repeat(32, sig_1175) and mux_890) or
(repeat(32, sig_1173) and mux_892) or
(repeat(32, sig_1172) and mux_894) or
(repeat(32, sig_1160) and mux_898) or
(repeat(32, sig_1158) and mux_900) or
(repeat(32, sig_1154) and mux_902) or
(repeat(32, sig_1152) and mux_904) or
(repeat(32, sig_1150) and mux_906) or
(repeat(32, sig_1149) and mux_908) or
(repeat(32, sig_1148) and mux_910) or
(repeat(32, sig_1147) and mux_912) or
(repeat(32, sig_1145) and mux_914) or
(repeat(32, sig_1143) and mux_916) or
(repeat(32, sig_1142) and mux_918) or
(repeat(32, sig_1140) and mux_920) or
(repeat(32, sig_1139) and mux_922) or
(repeat(32, sig_1138) and mux_924) or
(repeat(32, sig_1136) and mux_926) or
(repeat(32, sig_1135) and mux_928) or
(repeat(32, sig_1133) and mux_930) or
(repeat(32, sig_1131) and mux_932) or
(repeat(32, sig_1129) and mux_934) or
(repeat(32, sig_1128) and mux_936) or
(repeat(32, sig_1127) and mux_938) or
(repeat(32, sig_1125) and mux_940) or
(repeat(32, sig_1123) and mux_942) or
(repeat(32, sig_1121) and mux_944) or
(repeat(32, sig_1119) and mux_946) or
(repeat(32, sig_1117) and mux_948) or
(repeat(32, sig_1115) and mux_950) or
(repeat(32, sig_1113) and mux_952) or
(repeat(32, sig_1109) and mux_954) or
(repeat(32, sig_1106) and mux_956) or
(repeat(32, sig_1105) and mux_958) or
(repeat(32, sig_1103) and mux_960) or
(repeat(32, sig_1031) and mux_980) or
(repeat(32, sig_1003) and mux_986) or
(repeat(32, sig_1002) and mux_988);
-- Behaviour of component 'mux_562' model 'mux'
mux_562 <=
(repeat(9, sig_1555) and decode_block_out_buf_idx & "011000") or
(repeat(9, sig_1407) and decode_block_out_buf_idx & "101010") or
(repeat(9, sig_1405) and decode_block_out_buf_idx & "010100") or
(repeat(9, sig_1403) and decode_block_out_buf_idx & "110101") or
(repeat(9, sig_1401) and decode_block_out_buf_idx & "111000") or
(repeat(9, sig_1391) and decode_block_out_buf_idx & chenidct_aidx(5 downto 0)) or
(repeat(9, sig_1510) and decode_block_out_buf_idx & "101000") or
(repeat(9, sig_1389) and decode_block_out_buf_idx & "011001") or
(repeat(9, sig_1388) and decode_block_out_buf_idx & "100110") or
(repeat(9, sig_1384) and decode_block_out_buf_idx & "111010") or
(repeat(9, sig_1382) and decode_block_out_buf_idx & "111011") or
(repeat(9, sig_1381) and decode_block_out_buf_idx & "111100") or
(repeat(9, sig_1377) and decode_block_out_buf_idx & "000100") or
(repeat(9, sig_1375) and decode_block_out_buf_idx & "100100") or
(repeat(9, sig_1372) and decode_block_out_buf_idx & "010010") or
(repeat(9, sig_1512) and decode_block_out_buf_idx & "000001") or
(repeat(9, sig_1515) and decode_block_out_buf_idx & "011110") or
(repeat(9, sig_1517) and decode_block_out_buf_idx & "011100") or
(repeat(9, sig_1418) and decode_block_out_buf_idx & "111101") or
(repeat(9, sig_1417) and decode_block_out_buf_idx & "100010") or
(repeat(9, sig_1415) and decode_block_out_buf_idx & "010111") or
(repeat(9, sig_1408) and decode_block_out_buf_idx & "001010") or
(repeat(9, sig_1450) and decode_block_out_buf_idx & chenidct_i(5 downto 0)) or
(repeat(9, sig_1469) and decode_block_out_buf_idx & "010000") or
(repeat(9, sig_1370) and decode_block_out_buf_idx & "000111") or
(repeat(9, sig_1368) and decode_block_out_buf_idx & "001100") or
(repeat(9, sig_1366) and decode_block_out_buf_idx & "111111") or
(repeat(9, sig_1365) and decode_block_out_buf_idx & "101100") or
(repeat(9, sig_1362) and decode_block_out_buf_idx & "110010") or
(repeat(9, sig_1331) and decode_block_out_buf_idx & "000101") or
(repeat(9, sig_1330) and decode_block_out_buf_idx & "010001") or
(repeat(9, sig_1328) and decode_block_out_buf_idx & "001111") or
(repeat(9, sig_1326) and decode_block_out_buf_idx & "100111") or
(repeat(9, sig_1281) and decode_block_out_buf_idx & "011101") or
(repeat(9, sig_1279) and decode_block_out_buf_idx & "101110") or
(repeat(9, sig_1278) and decode_block_out_buf_idx & "110110") or
(repeat(9, sig_1265) and decode_block_out_buf_idx & "001110") or
(repeat(9, sig_1261) and decode_block_out_buf_idx & "001001") or
(repeat(9, sig_1238) and decode_block_out_buf_idx & "010110") or
(repeat(9, sig_1232) and decode_block_out_buf_idx & "001011") or
(repeat(9, sig_1177) and decode_block_out_buf_idx & "111110") or
(repeat(9, sig_1174) and decode_block_out_buf_idx & "100001") or
(repeat(9, sig_1171) and decode_block_out_buf_idx & "011111") or
(repeat(9, sig_1159) and decode_block_out_buf_idx & "000000") or
(repeat(9, sig_1157) and decode_block_out_buf_idx & "100000") or
(repeat(9, sig_1153) and decode_block_out_buf_idx & "000010") or
(repeat(9, sig_1151) and decode_block_out_buf_idx & "010101") or
(repeat(9, sig_1146) and decode_block_out_buf_idx & "101001") or
(repeat(9, sig_1144) and decode_block_out_buf_idx & "110111") or
(repeat(9, sig_1141) and decode_block_out_buf_idx & "001000") or
(repeat(9, sig_1137) and decode_block_out_buf_idx & "101011") or
(repeat(9, sig_1134) and decode_block_out_buf_idx & "111001") or
(repeat(9, sig_1132) and decode_block_out_buf_idx & "000110") or
(repeat(9, sig_1130) and decode_block_out_buf_idx & "011010") or
(repeat(9, sig_1126) and decode_block_out_buf_idx & "100101") or
(repeat(9, sig_1124) and decode_block_out_buf_idx & "011011") or
(repeat(9, sig_1122) and decode_block_out_buf_idx & "000011") or
(repeat(9, sig_1120) and decode_block_out_buf_idx & "100011") or
(repeat(9, sig_1116) and decode_block_out_buf_idx & "001101") or
(repeat(9, sig_1114) and decode_block_out_buf_idx & "101101") or
(repeat(9, sig_1108) and decode_block_out_buf_idx & "110011") or
(repeat(9, sig_1107) and decode_block_out_buf_idx & "010011") or
(repeat(9, sig_1104) and decode_block_out_buf_idx & "110100") or
(repeat(9, sig_1102) and decode_block_out_buf_idx & "110000") or
(repeat(9, sig_1096) and decode_block_out_buf_idx & "101111") or
(repeat(9, sig_1095) and decode_block_out_buf_idx & "110001") or
(repeat(9, sig_1087) and decode_block_out_buf_idx & chenidct_i(2 downto 0) & "000") or
(repeat(9, sig_1083) and decode_block_out_buf_idx & chenidct_i(2 downto 0) & "001");
-- Behaviour of component 'mux_557' model 'mux'
mux_557 <=
(repeat(32, sig_1436) and sig_1643) or
(repeat(32, sig_1433) and sig_1628(31 downto 0));
-- Behaviour of component 'mux_558' model 'mux'
mux_558 <=
(repeat(6, sig_1564) and "000101") or
(repeat(6, sig_1321) and "110001") or
(repeat(6, sig_1320) and "000110") or
(repeat(6, sig_1315) and "010101") or
(repeat(6, sig_1311) and "011111") or
(repeat(6, sig_1301) and "100101") or
(repeat(6, sig_1367) and "111010") or
(repeat(6, sig_1293) and "100111") or
(repeat(6, sig_1277) and "000010") or
(repeat(6, sig_1276) and "111001") or
(repeat(6, sig_1275) and "010001") or
(repeat(6, sig_1270) and "110000") or
(repeat(6, sig_1260) and "101001") or
(repeat(6, sig_1259) and "111100") or
(repeat(6, sig_1258) and "011000") or
(repeat(6, sig_1371) and "110111") or
(repeat(6, sig_1410) and "011001") or
(repeat(6, sig_1508) and "001101") or
(repeat(6, sig_1361) and "101100") or
(repeat(6, sig_1359) and "001000") or
(repeat(6, sig_1358) and "101011") or
(repeat(6, sig_1436) and izigzagmatrix_out_idx(5 downto 0)) or
(repeat(6, sig_1432) and "010010") or
(repeat(6, sig_1256) and "010110") or
(repeat(6, sig_1255) and "000011") or
(repeat(6, sig_1246) and "100011") or
(repeat(6, sig_1239) and "100001") or
(repeat(6, sig_1235) and "100100") or
(repeat(6, sig_1231) and "100110") or
(repeat(6, sig_1230) and "100000") or
(repeat(6, sig_1228) and "110101") or
(repeat(6, sig_1227) and "101101") or
(repeat(6, sig_1226) and "011110") or
(repeat(6, sig_1225) and "000100") or
(repeat(6, sig_1223) and "000111") or
(repeat(6, sig_1222) and "110110") or
(repeat(6, sig_1221) and "011101") or
(repeat(6, sig_1220) and "101110") or
(repeat(6, sig_1166) and "001110") or
(repeat(6, sig_1164) and "110100") or
(repeat(6, sig_1156) and "010100") or
(repeat(6, sig_1155) and "101010") or
(repeat(6, sig_1099) and "011010") or
(repeat(6, sig_1098) and "101111") or
(repeat(6, sig_1097) and "010011") or
(repeat(6, sig_1094) and "010111") or
(repeat(6, sig_1093) and "111000") or
(repeat(6, sig_1092) and "011100") or
(repeat(6, sig_1091) and "000001") or
(repeat(6, sig_1090) and "001001") or
(repeat(6, sig_1086) and "001011") or
(repeat(6, sig_1085) and "110010") or
(repeat(6, sig_1084) and "010000") or
(repeat(6, sig_1079) and "001111") or
(repeat(6, sig_1076) and "001010") or
(repeat(6, sig_1075) and "110011") or
(repeat(6, sig_1074) and "111111") or
(repeat(6, sig_1071) and "011011") or
(repeat(6, sig_1063) and "001100") or
(repeat(6, sig_1054) and "101000") or
(repeat(6, sig_1050) and "100010") or
(repeat(6, sig_1028) and "111101") or
(repeat(6, sig_1022) and "111110") or
(repeat(6, sig_1007) and "111011");
-- Behaviour of component 'mux_559' model 'mux'
mux_559 <=
(repeat(6, sig_1581) and chenidct_i(5 downto 0)) or
(repeat(6, sig_1358) and "101011") or
(repeat(6, sig_1321) and "110001") or
(repeat(6, sig_1320) and "000110") or
(repeat(6, sig_1315) and "010101") or
(repeat(6, sig_1311) and "011111") or
(repeat(6, sig_1371) and "110111") or
(repeat(6, sig_1301) and "100101") or
(repeat(6, sig_1293) and "100111") or
(repeat(6, sig_1277) and "000010") or
(repeat(6, sig_1276) and "111001") or
(repeat(6, sig_1275) and "010001") or
(repeat(6, sig_1270) and "110000") or
(repeat(6, sig_1260) and "101001") or
(repeat(6, sig_1259) and "111100") or
(repeat(6, sig_1410) and "011001") or
(repeat(6, sig_1508) and "001101") or
(repeat(6, sig_1564) and "000101") or
(repeat(6, sig_1367) and "111010") or
(repeat(6, sig_1361) and "101100") or
(repeat(6, sig_1359) and "001000") or
(repeat(6, sig_1473) and chenidct_aidx(5 downto 0)) or
(repeat(6, sig_1432) and "010010") or
(repeat(6, sig_1258) and "011000") or
(repeat(6, sig_1256) and "010110") or
(repeat(6, sig_1255) and "000011") or
(repeat(6, sig_1246) and "100011") or
(repeat(6, sig_1239) and "100001") or
(repeat(6, sig_1235) and "100100") or
(repeat(6, sig_1231) and "100110") or
(repeat(6, sig_1230) and "100000") or
(repeat(6, sig_1228) and "110101") or
(repeat(6, sig_1227) and "101101") or
(repeat(6, sig_1226) and "011110") or
(repeat(6, sig_1225) and "000100") or
(repeat(6, sig_1223) and "000111") or
(repeat(6, sig_1222) and "110110") or
(repeat(6, sig_1221) and "011101") or
(repeat(6, sig_1220) and "101110") or
(repeat(6, sig_1166) and "001110") or
(repeat(6, sig_1164) and "110100") or
(repeat(6, sig_1156) and "010100") or
(repeat(6, sig_1155) and "101010") or
(repeat(6, sig_1099) and "011010") or
(repeat(6, sig_1098) and "101111") or
(repeat(6, sig_1097) and "010011") or
(repeat(6, sig_1094) and "010111") or
(repeat(6, sig_1093) and "111000") or
(repeat(6, sig_1092) and "011100") or
(repeat(6, sig_1091) and "000001") or
(repeat(6, sig_1090) and "001001") or
(repeat(6, sig_1086) and "001011") or
(repeat(6, sig_1085) and "110010") or
(repeat(6, sig_1084) and "010000") or
(repeat(6, sig_1079) and "001111") or
(repeat(6, sig_1076) and "001010") or
(repeat(6, sig_1075) and "110011") or
(repeat(6, sig_1074) and "111111") or
(repeat(6, sig_1071) and "011011") or
(repeat(6, sig_1063) and "001100") or
(repeat(6, sig_1054) and "101000") or
(repeat(6, sig_1050) and "100010") or
(repeat(6, sig_1028) and "111101") or
(repeat(6, sig_1022) and "111110") or
(repeat(6, sig_1007) and "111011");
-- Behaviour of component 'mux_555' model 'mux'
mux_555 <=
(repeat(32, sig_1396) and sig_1613) or
(repeat(32, sig_1449) and sig_1612(31 downto 0));
-- Behaviour of component 'mux_551' model 'mux'
mux_551 <=
(repeat(32, sig_1118) and sig_1587(39 downto 8)) or
(repeat(32, sig_1088) and sig_1640) or
(repeat(32, sig_1332) and sig_1639(29 downto 0) & "00") or
(repeat(32, sig_1463) and sig_1609(31 downto 0));
-- Behaviour of component 'mux_553' model 'mux'
mux_553 <=
(repeat(32, sig_1411) and sig_1610(31 downto 0)) or
(repeat(32, sig_1111) and sig_1609(28 downto 0) & chenidct_aidx(2 downto 0)) or
(repeat(32, sig_1262) and sig_1609(31 downto 0)) or
(repeat(32, sig_1582) and sig_1610(28 downto 0) & chenidct_i(2 downto 0)) or
(repeat(32, sig_1477) and sig_1610(28 downto 0) & chenidct_aidx(2 downto 0));
-- Behaviour of component 'mux_549' model 'mux'
mux_549 <=
(repeat(32, sig_1323) and sig_1639(29 downto 0) & "00") or
(repeat(32, sig_1274) and sig_1642) or
(repeat(32, sig_1324) and sig_1587(39 downto 8)) or
(repeat(32, sig_1463) and sig_1614(31 downto 0));
-- Behaviour of component 'mux_545' model 'mux'
mux_545 <=
(repeat(32, sig_1118) and sig_1612(38 downto 7)) or
(repeat(32, sig_1040) and sig_1639(29 downto 0) & "00") or
(repeat(32, sig_1351) and sig_1642) or
(repeat(32, sig_1463) and sig_1613);
-- Behaviour of component 'mux_547' model 'mux'
mux_547 <=
(repeat(32, sig_1349) and sig_1614(40 downto 9)) or
(repeat(32, sig_1001) and sig_1639(29 downto 0) & "00") or
(repeat(32, sig_1413) and sig_1642) or
(repeat(32, sig_1463) and sig_1624(31 downto 0));
-- Behaviour of component 'mux_543' model 'mux'
mux_543 <=
(repeat(32, sig_1088) and sig_1642) or
(repeat(32, sig_1581) and sig_1639(29 downto 0) & "00") or
(repeat(32, sig_1463) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_731' model 'mux'
mux_731 <=
(repeat(8, sig_1508) and iquantize_qidx & "001101") or
(repeat(8, sig_1320) and iquantize_qidx & "000110") or
(repeat(8, sig_1315) and iquantize_qidx & "010101") or
(repeat(8, sig_1311) and iquantize_qidx & "011111") or
(repeat(8, sig_1301) and iquantize_qidx & "100101") or
(repeat(8, sig_1293) and iquantize_qidx & "100111") or
(repeat(8, sig_1361) and iquantize_qidx & "101100") or
(repeat(8, sig_1277) and iquantize_qidx & "000010") or
(repeat(8, sig_1276) and iquantize_qidx & "111001") or
(repeat(8, sig_1275) and iquantize_qidx & "010001") or
(repeat(8, sig_1270) and iquantize_qidx & "110000") or
(repeat(8, sig_1260) and iquantize_qidx & "101001") or
(repeat(8, sig_1259) and iquantize_qidx & "111100") or
(repeat(8, sig_1258) and iquantize_qidx & "011000") or
(repeat(8, sig_1256) and iquantize_qidx & "010110") or
(repeat(8, sig_1367) and iquantize_qidx & "111010") or
(repeat(8, sig_1371) and iquantize_qidx & "110111") or
(repeat(8, sig_1410) and iquantize_qidx & "011001") or
(repeat(8, sig_1360) and iquantize_qidx & "000000") or
(repeat(8, sig_1359) and iquantize_qidx & "001000") or
(repeat(8, sig_1358) and iquantize_qidx & "101011") or
(repeat(8, sig_1321) and iquantize_qidx & "110001") or
(repeat(8, sig_1564) and iquantize_qidx & "000101") or
(repeat(8, sig_1432) and iquantize_qidx & "010010") or
(repeat(8, sig_1255) and iquantize_qidx & "000011") or
(repeat(8, sig_1246) and iquantize_qidx & "100011") or
(repeat(8, sig_1239) and iquantize_qidx & "100001") or
(repeat(8, sig_1235) and iquantize_qidx & "100100") or
(repeat(8, sig_1231) and iquantize_qidx & "100110") or
(repeat(8, sig_1230) and iquantize_qidx & "100000") or
(repeat(8, sig_1228) and iquantize_qidx & "110101") or
(repeat(8, sig_1227) and iquantize_qidx & "101101") or
(repeat(8, sig_1226) and iquantize_qidx & "011110") or
(repeat(8, sig_1225) and iquantize_qidx & "000100") or
(repeat(8, sig_1223) and iquantize_qidx & "000111") or
(repeat(8, sig_1222) and iquantize_qidx & "110110") or
(repeat(8, sig_1221) and iquantize_qidx & "011101") or
(repeat(8, sig_1220) and iquantize_qidx & "101110") or
(repeat(8, sig_1166) and iquantize_qidx & "001110") or
(repeat(8, sig_1164) and iquantize_qidx & "110100") or
(repeat(8, sig_1156) and iquantize_qidx & "010100") or
(repeat(8, sig_1155) and iquantize_qidx & "101010") or
(repeat(8, sig_1099) and iquantize_qidx & "011010") or
(repeat(8, sig_1098) and iquantize_qidx & "101111") or
(repeat(8, sig_1097) and iquantize_qidx & "010011") or
(repeat(8, sig_1094) and iquantize_qidx & "010111") or
(repeat(8, sig_1093) and iquantize_qidx & "111000") or
(repeat(8, sig_1092) and iquantize_qidx & "011100") or
(repeat(8, sig_1091) and iquantize_qidx & "000001") or
(repeat(8, sig_1090) and iquantize_qidx & "001001") or
(repeat(8, sig_1086) and iquantize_qidx & "001011") or
(repeat(8, sig_1085) and iquantize_qidx & "110010") or
(repeat(8, sig_1084) and iquantize_qidx & "010000") or
(repeat(8, sig_1079) and iquantize_qidx & "001111") or
(repeat(8, sig_1076) and iquantize_qidx & "001010") or
(repeat(8, sig_1075) and iquantize_qidx & "110011") or
(repeat(8, sig_1074) and iquantize_qidx & "111111") or
(repeat(8, sig_1071) and iquantize_qidx & "011011") or
(repeat(8, sig_1063) and iquantize_qidx & "001100") or
(repeat(8, sig_1054) and iquantize_qidx & "101000") or
(repeat(8, sig_1050) and iquantize_qidx & "100010") or
(repeat(8, sig_1028) and iquantize_qidx & "111101") or
(repeat(8, sig_1022) and iquantize_qidx & "111110") or
(repeat(8, sig_1007) and iquantize_qidx & "111011");
-- Behaviour of component 'mux_727' model 'mux'
mux_727 <=
(repeat(7, sig_1534) and huff_make_dhuff_tb_dc_tbl_no & huff_make_dhuff_tb_dc_i_c0(5 downto 0)) or
(repeat(7, sig_1552) and huff_make_dhuff_tb_dc_tbl_no & huff_make_dhuff_tb_dc_l(5 downto 0)) or
(repeat(7, sig_1458) and get_dht_index & get_dht_i(5 downto 0));
-- Behaviour of component 'mux_723' model 'mux'
mux_723 <=
(repeat(10, sig_1304) and decodehuffman_dc_tbl_no & decodehuffman_dc_p) or
(repeat(10, sig_1480) and get_dht_index & get_dht_i(8 downto 0));
-- Behaviour of component 'mux_719' model 'mux'
mux_719 <=
(repeat(7, sig_1505) and huff_make_dhuff_tb_ac_tbl_no & huff_make_dhuff_tb_ac_i_c0(5 downto 0)) or
(repeat(7, sig_1547) and huff_make_dhuff_tb_ac_tbl_no & huff_make_dhuff_tb_ac_l(5 downto 0)) or
(repeat(7, sig_1458) and get_dht_index & get_dht_i(5 downto 0));
-- Behaviour of component 'mux_539' model 'mux'
mux_539 <=
(repeat(32, sig_1118) and sig_1624(31 downto 0)) or
(repeat(32, sig_1354) and sig_1642) or
(repeat(32, sig_1472) and sig_1639(29 downto 0) & "00");
-- Behaviour of component 'mux_541' model 'mux'
mux_541 <=
(repeat(32, sig_999) and sig_1639(29 downto 0) & "00") or
(repeat(32, sig_1118) and sig_1613) or
(repeat(32, sig_1357) and sig_1642);
-- Behaviour of component 'mux_537' model 'mux'
mux_537 <=
(repeat(32, sig_1285) and sig_1642) or
(repeat(32, sig_1325) and sig_1639(29 downto 0) & "00") or
(repeat(32, sig_1463) and sig_1621(31 downto 0));
-- Behaviour of component 'mux_533' model 'mux'
mux_533 <=
(repeat(32, sig_1324) and sig_1614(40 downto 9)) or
(repeat(32, sig_1395) and sig_1627(39 downto 8));
-- Behaviour of component 'mux_535' model 'mux'
mux_535 <=
(repeat(32, sig_1118) and sig_1614(40 downto 9)) or
(repeat(32, sig_1463) and sig_1609(31 downto 0));
-- Behaviour of component 'mux_715' model 'mux'
mux_715 <=
(repeat(10, sig_1284) and decodehuffman_ac_tbl_no & decodehuffman_ac_p) or
(repeat(10, sig_1480) and get_dht_index & get_dht_i(8 downto 0));
-- Behaviour of component 'mux_711' model 'mux'
mux_711 <=
(sig_1170 and decodehuffmcu_tbl_no) or
(sig_1189 and '1');
-- Behaviour of component 'mux_705' model 'mux'
mux_705 <=
(repeat(32, sig_1271) and sig_1632) or
(repeat(32, sig_1554) and "11111111111111111111111111111111") or
(repeat(32, sig_1561) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_706' model 'mux'
mux_706 <=
(repeat(7, sig_1553) and huff_make_dhuff_tb_dc_tbl_no & huff_make_dhuff_tb_dc_l(5 downto 0)) or
(repeat(7, sig_1561) and huff_make_dhuff_tb_dc_tbl_no & huff_make_dhuff_tb_dc_p_dhtbl_ml(5 downto 0));
-- Behaviour of component 'mux_707' model 'mux'
mux_707 <=
(repeat(7, sig_1561) and huff_make_dhuff_tb_dc_tbl_no & huff_make_dhuff_tb_dc_p_dhtbl_ml(5 downto 0)) or
(repeat(7, sig_1575) and decodehuffman_dc_tbl_no & decodehuffman_dc_l(5 downto 0)) or
(repeat(7, sig_1577) and decodehuffman_dc_tbl_no & decodehuffman_dc_dhuff_ml);
-- Behaviour of component 'mux_531' model 'mux'
mux_531 <=
(repeat(32, sig_1324) and sig_1609(38 downto 7)) or
(repeat(32, sig_1395) and sig_1628(39 downto 8));
-- Behaviour of component 'mux_529' model 'mux'
mux_529 <=
(repeat(32, sig_1118) and sig_1610(38 downto 7)) or
(repeat(32, sig_1463) and sig_1613);
-- Behaviour of component 'mux_695' model 'mux'
mux_695 <=
(sig_1184 and '1') or
(sig_1453 and decodehuffmcu_tbl_no);
-- Behaviour of component 'mux_524' model 'mux'
mux_524 <=
(repeat(5, sig_1310) and decodehuffmcu_s(4 downto 0)) or
(repeat(5, sig_1482) and read_position(4 downto 0));
-- Behaviour of component 'mux_521' model 'mux'
mux_521 <=
(repeat(32, sig_1422) and "000000000000000000000000" & pgetc) or
(repeat(32, sig_1493) and or_802 & pgetc);
-- Behaviour of component 'mux_519' model 'mux'
mux_519 <=
(repeat(32, sig_1484) and sig_1614(31 downto 0)) or
(repeat(32, sig_1355) and sig_1624(31 downto 0)) or
(repeat(32, sig_1421) and "00000000000000000000000000000111") or
(repeat(32, sig_1493) and sig_1610(28 downto 0) & read_position(2 downto 0)) or
(repeat(32, sig_1497) and "11111111111111111111111111111111");
-- Behaviour of component 'mux_517' model 'mux'
mux_517 <=
(repeat(8, sig_1423) and "11111111") or
(repeat(8, sig_1425) and pgetc_temp);
-- Behaviour of component 'mux_507' model 'mux'
mux_507 <=
(repeat(32, sig_1008) and and_984) or
(repeat(32, sig_1345) and and_853) or
(repeat(32, sig_1497) and and_801);
-- Behaviour of component 'mux_505' model 'mux'
mux_505 <=
(repeat(32, sig_1167) and sig_1614(31 downto 0)) or
(repeat(32, sig_1197) and decodehuffmcu_s) or
(repeat(32, sig_1201) and decodehuffman_dc);
-- Behaviour of component 'mux_501' model 'mux'
mux_501 <=
(repeat(32, sig_1355) and or_845) or
(repeat(32, sig_1489) and sig_1626);
-- Behaviour of component 'mux_492' model 'mux'
mux_492 <=
(repeat(32, sig_1186) and sig_1652) or
(repeat(32, sig_1514) and "00000000000000000000000000000001") or
(repeat(32, sig_1544) and huff_make_dhuff_tb_ac_l);
-- Behaviour of component 'mux_488' model 'mux'
mux_488 <=
(repeat(32, sig_1499) and sig_1609(31 downto 0)) or
(repeat(32, sig_1504) and "00000000000000000000000000000001");
-- Behaviour of component 'mux_490' model 'mux'
mux_490 <=
(repeat(32, sig_1498) and "00000000000000000000000000000001") or
(repeat(32, sig_1507) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_486' model 'mux'
mux_486 <=
(repeat(32, sig_1500) and sig_1610(31 downto 0)) or
(repeat(32, sig_1544) and sig_1609(31 downto 0));
-- Behaviour of component 'mux_482' model 'mux'
mux_482 <=
(repeat(32, sig_1283) and sig_1610(31 downto 0)) or
(repeat(32, sig_1558) and sig_1635);
-- Behaviour of component 'mux_484' model 'mux'
mux_484 <=
(repeat(32, sig_1023) and sig_1609(31 downto 0)) or
(repeat(32, sig_1283) and huff_make_dhuff_tb_ac_code(30 downto 0) & '0');
-- Behaviour of component 'mux_480' model 'mux'
mux_480 <=
(repeat(32, sig_1514) and "00000000000000000000000000000001") or
(repeat(32, sig_1525) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_476' model 'mux'
mux_476 <=
(repeat(32, sig_1499) and huff_make_dhuff_tb_ac_i_c0);
-- Behaviour of component 'mux_478' model 'mux'
mux_478 <=
(repeat(9, sig_1511) and huff_make_dhuff_tb_ac_p(8 downto 0));
-- Behaviour of component 'mux_459' model 'mux'
mux_459 <=
(repeat(32, sig_1038) and huff_make_dhuff_tb_dc_l) or
(repeat(32, sig_1305) and sig_1656) or
(repeat(32, sig_1542) and "00000000000000000000000000000001");
-- Behaviour of component 'mux_455' model 'mux'
mux_455 <=
(repeat(32, sig_1527) and sig_1609(31 downto 0)) or
(repeat(32, sig_1533) and "00000000000000000000000000000001");
-- Behaviour of component 'mux_457' model 'mux'
mux_457 <=
(repeat(32, sig_1526) and "00000000000000000000000000000001") or
(repeat(32, sig_1536) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_453' model 'mux'
mux_453 <=
(repeat(32, sig_1038) and sig_1609(31 downto 0)) or
(repeat(32, sig_1528) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_449' model 'mux'
mux_449 <=
(repeat(32, sig_1033) and sig_1633) or
(repeat(32, sig_1068) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_451' model 'mux'
mux_451 <=
(repeat(32, sig_1035) and sig_1609(31 downto 0)) or
(repeat(32, sig_1068) and huff_make_dhuff_tb_dc_code(30 downto 0) & '0');
-- Behaviour of component 'mux_447' model 'mux'
mux_447 <=
(repeat(32, sig_1542) and "00000000000000000000000000000001") or
(repeat(32, sig_1563) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_443' model 'mux'
mux_443 <=
(repeat(32, sig_1527) and huff_make_dhuff_tb_dc_i_c0);
-- Behaviour of component 'mux_445' model 'mux'
mux_445 <=
(repeat(9, sig_1537) and huff_make_dhuff_tb_dc_p(8 downto 0));
-- Behaviour of component 'mux_430' model 'mux'
mux_430 <=
(repeat(32, sig_1284) and sig_1657);
-- Behaviour of component 'mux_422' model 'mux'
mux_422 <=
(repeat(32, sig_1565) and "00000000000000000000000000000001") or
(repeat(32, sig_1567) and sig_1609(31 downto 0));
-- Behaviour of component 'mux_424' model 'mux'
mux_424 <=
(repeat(32, sig_1565) and "0000000000000000000000000000000" & buf_getb) or
(repeat(32, sig_1567) and sig_1610(30 downto 0) & buf_getb);
-- Behaviour of component 'mux_416' model 'mux'
mux_416 <=
(repeat(32, sig_1304) and sig_1659);
-- Behaviour of component 'mux_410' model 'mux'
mux_410 <=
(repeat(32, sig_1571) and "0000000000000000000000000000000" & buf_getb) or
(repeat(32, sig_1574) and sig_1610(30 downto 0) & buf_getb);
-- Behaviour of component 'mux_408' model 'mux'
mux_408 <=
(repeat(32, sig_1571) and "00000000000000000000000000000001") or
(repeat(32, sig_1574) and sig_1609(31 downto 0));
-- Behaviour of component 'mux_398' model 'mux'
mux_398 <=
(repeat(32, sig_1026) and sig_1610(31 downto 0)) or
(repeat(32, sig_1341) and buf_getv) or
(repeat(32, sig_1344) and or_854);
-- Behaviour of component 'mux_400' model 'mux'
mux_400 <=
(repeat(32, sig_1030) and and_982) or
(repeat(32, sig_1342) and sig_1614(31 downto 0)) or
(repeat(32, sig_1579) and decodehuffman_dc);
-- Behaviour of component 'mux_392' model 'mux'
mux_392 <=
(repeat(32, sig_1454) and "00000000000000000000000000000001") or
(repeat(32, sig_1466) and sig_1610(31 downto 0)) or
(repeat(32, sig_1464) and sig_1610(27 downto 0) & decodehuffmcu_k(3 downto 0));
-- Behaviour of component 'mux_394' model 'mux'
mux_394 <=
(repeat(32, sig_1443) and sig_1610(31 downto 0)) or
(repeat(32, sig_1445) and "00000000000000000000000000000001");
-- Behaviour of component 'mux_378' model 'mux'
mux_378 <=
(repeat(8, sig_1070) and yuvtorgb_r(7 downto 0)) or
(repeat(8, sig_1234) and yuvtorgb_b(7 downto 0)) or
(repeat(8, sig_1237) and yuvtorgb_g(7 downto 0));
-- Behaviour of component 'mux_379' model 'mux'
mux_379 <=
(repeat(10, sig_1070) and yuvtorgb_p & "00" & yuvtorgb_i(5 downto 0)) or
(repeat(10, sig_1234) and yuvtorgb_p & "10" & yuvtorgb_i(5 downto 0)) or
(repeat(10, sig_1237) and yuvtorgb_p & "01" & yuvtorgb_i(5 downto 0));
-- Behaviour of component 'mux_375' model 'mux'
mux_375 <=
(repeat(2, sig_1020) and write4blocks_i) or
(repeat(2, sig_1196) and decode_start_i(1 downto 0));
-- Behaviour of component 'mux_373' model 'mux'
mux_373 <=
(repeat(2, sig_1005) and "10") or
(repeat(2, sig_1004) and "11") or
(repeat(2, sig_1019) and "01");
-- Behaviour of component 'mux_365' model 'mux'
mux_365 <=
(repeat(32, sig_1005) and sig_1614(31 downto 0)) or
(repeat(32, sig_1021) and sig_1610(28 downto 0) & write4blocks_hoffs(2 downto 0)) or
(repeat(32, sig_1196) and sig_1647(28 downto 0) & "000");
-- Behaviour of component 'mux_367' model 'mux'
mux_367 <=
(repeat(32, sig_1005) and sig_1610(28 downto 0) & write4blocks_voffs(2 downto 0)) or
(repeat(32, sig_1021) and write4blocks_voffs) or
(repeat(32, sig_1196) and sig_1648(28 downto 0) & "000");
-- Behaviour of component 'mux_363' model 'mux'
mux_363 <=
(repeat(32, sig_1018) and sig_1610(31 downto 0)) or
(repeat(32, sig_1065) and writeoneblock_voffs);
-- Behaviour of component 'mux_359' model 'mux'
mux_359 <=
(repeat(32, sig_1012) and sig_1609(31 downto 0));
-- Behaviour of component 'mux_361' model 'mux'
mux_361 <=
(repeat(32, sig_1017) and sig_1610(31 downto 0)) or
(repeat(32, sig_1081) and writeoneblock_hoffs);
-- Behaviour of component 'mux_347' model 'mux'
mux_347 <=
(repeat(32, sig_1005) and sig_1610(28 downto 0) & write4blocks_voffs(2 downto 0)) or
(repeat(32, sig_1194) and sig_1648(28 downto 0) & "000");
-- Behaviour of component 'mux_345' model 'mux'
mux_345 <=
(repeat(32, sig_1005) and sig_1614(31 downto 0)) or
(repeat(32, sig_1021) and sig_1610(28 downto 0) & write4blocks_hoffs(2 downto 0)) or
(repeat(32, sig_1194) and sig_1647(28 downto 0) & "000");
-- Behaviour of component 'mux_341' model 'mux'
mux_341 <=
(repeat(3, sig_993) and decode_start_i(2 downto 0));
-- Behaviour of component 'mux_343' model 'mux'
mux_343 <=
(repeat(2, sig_993) and decode_start_i(1 downto 0));
-- Behaviour of component 'mux_339' model 'mux'
mux_339 <=
(repeat(3, sig_993) and "100") or
(repeat(3, sig_997) and "001");
-- Behaviour of component 'mux_335' model 'mux'
mux_335 <=
(repeat(32, sig_1060) and mux_965) or
(repeat(32, sig_1217) and sig_1611(24) & sig_1611(24) & sig_1611(24) & sig_1611(24) & sig_1611(24) & sig_1611(24) & sig_1611(24) & sig_1611(24) & sig_1611(24 downto 1));
-- Behaviour of component 'mux_337' model 'mux'
mux_337 <=
(repeat(3, sig_993) and "101") or
(repeat(3, sig_997) and "010");
-- Behaviour of component 'mux_333' model 'mux'
mux_333 <=
(repeat(32, sig_1060) and mux_969) or
(repeat(32, sig_1217) and sig_1610(24) & sig_1610(24) & sig_1610(24) & sig_1610(24) & sig_1610(24) & sig_1610(24) & sig_1610(24) & sig_1610(24) & sig_1610(24 downto 1));
-- Behaviour of component 'mux_331' model 'mux'
mux_331 <=
(repeat(32, sig_1060) and mux_967) or
(repeat(32, sig_1217) and sig_1613(24) & sig_1613(24) & sig_1613(24) & sig_1613(24) & sig_1613(24) & sig_1613(24) & sig_1613(24) & sig_1613(24) & sig_1613(24 downto 1));
-- Behaviour of component 'mux_323' model 'mux'
mux_323 <=
(repeat(6, sig_1345) and buf_getv_p(5 downto 0)) or
(repeat(6, sig_1355) and sig_1614(5 downto 0));
-- Behaviour of component 'mux_320' model 'mux'
mux_320 <=
(repeat(32, sig_1234) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_322' model 'mux'
mux_322 <=
(repeat(32, sig_1345) and current_read_byte) or
(repeat(32, sig_1355) and "000000000000000000000000" & pgetc);
-- Behaviour of component 'mux_317' model 'mux'
mux_317 <=
(repeat(2, sig_995) and "01") or
(repeat(2, sig_994) and "10") or
(repeat(2, sig_1045) and decode_start_i(1 downto 0));
-- Behaviour of component 'mux_314' model 'mux'
mux_314 <=
(repeat(32, sig_1324) and chenidct_a2) or
(repeat(32, sig_1118) and chenidct_a3) or
(repeat(32, sig_1217) and yuvtorgb_v(30) & yuvtorgb_v(30 downto 0)) or
(repeat(32, sig_1349) and chenidct_b3) or
(repeat(32, sig_1395) and sig_1614(31 downto 0));
-- Behaviour of component 'mux_315' model 'mux'
mux_315 <=
(repeat(32, sig_1349) and "00000000000000000000000000110001") or
(repeat(32, sig_1101) and p_jinfo_mcuwidth) or
(repeat(32, sig_1118) and "00000000000000000000000000011001") or
(repeat(32, sig_1217) and "00000000000000000000000000001011") or
(repeat(32, sig_1324) and "00000000000000000000000011010101") or
(repeat(32, sig_1081) and writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12 downto 0)) or
(repeat(32, sig_1395) and "00000000000000000000000010110101") or
(repeat(32, sig_1433) and sig_1661);
-- Behaviour of component 'mux_316' model 'mux'
mux_316 <=
(repeat(32, sig_1349) and chenidct_b2) or
(repeat(32, sig_1101) and p_jinfo_mcuheight) or
(repeat(32, sig_1118) and chenidct_a0) or
(repeat(32, sig_1217) and yuvtorgb_u(28) & yuvtorgb_u(28) & yuvtorgb_u(28) & yuvtorgb_u(28 downto 0)) or
(repeat(32, sig_1324) and chenidct_a1) or
(repeat(32, sig_1081) and writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12 downto 0)) or
(repeat(32, sig_1395) and sig_1610(31 downto 0)) or
(repeat(32, sig_1433) and sig_1639);
-- Behaviour of component 'mux_313' model 'mux'
mux_313 <=
(repeat(9, sig_1324) and "001000111") or
(repeat(9, sig_1118) and "011111011") or
(repeat(9, sig_1217) and "001011011") or
(repeat(9, sig_1349) and "111011001") or
(repeat(9, sig_1395) and "010110101");
-- Behaviour of component 'mux_308' model 'mux'
mux_308 <=
(repeat(3, sig_994) and "101") or
(repeat(3, sig_995) and "100") or
(repeat(3, sig_1046) and decode_start_i(2 downto 0));
-- Behaviour of component 'mux_306' model 'mux'
mux_306 <=
(repeat(41, sig_1451) and "00000000000000000000000000000000000001000") or
(repeat(41, sig_1299) and "00000000000000000000000000000000010000000") or
(repeat(41, sig_1308) and "00000000000000000000000000000000000000001") or
(repeat(41, sig_1324) and chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1) or
(repeat(41, sig_1355) and buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p) or
(repeat(41, sig_1217) and sig_1627(30) & sig_1627(30) & sig_1627(30) & sig_1627(30) & sig_1627(30) & sig_1627(30) & sig_1627(30) & sig_1627(30) & sig_1627(30) & sig_1627(30 downto 0) & '0') or
(repeat(41, sig_1161) and "00000000000000000000000000000000000000010") or
(repeat(41, sig_1118) and chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2) or
(repeat(41, sig_1470) and "00000000000000000000000000000000011111111") or
(repeat(41, sig_1463) and chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2);
-- Behaviour of component 'mux_307' model 'mux'
mux_307 <=
(repeat(41, sig_1355) and "00000000000000000000000000000000000000111") or
(repeat(41, sig_1217) and sig_1614(31) & sig_1614(31) & sig_1614(31) & sig_1614(31) & sig_1614(31) & sig_1614(31) & sig_1614(31) & sig_1614(31) & sig_1614(31) & sig_1614(31 downto 0)) or
(repeat(41, sig_1299) and sig_1641(30) & sig_1641(30) & sig_1641(30) & sig_1641(30) & sig_1641(30) & sig_1641(30) & sig_1641(30) & sig_1641(30) & sig_1641(30) & sig_1641(30) & sig_1641(30 downto 0)) or
(repeat(41, sig_1309) and p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width) or
(repeat(41, sig_1324) and chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0) or
(repeat(41, sig_1216) and sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648) or
(repeat(41, sig_1118) and chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1) or
(repeat(41, sig_1060) and yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r) or
(repeat(41, sig_1468) and sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642) or
(repeat(41, sig_1463) and chenidct_c3(31) & chenidct_c3(31) & chenidct_c3(31) & chenidct_c3(31) & chenidct_c3(31) & chenidct_c3(31) & chenidct_c3(31) & chenidct_c3(31) & chenidct_c3(31) & chenidct_c3);
-- Behaviour of component 'mux_302' model 'mux'
mux_302 <=
(repeat(41, sig_1216) and p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth) or
(repeat(41, sig_1470) and "00000000000000000000000000000000011111111") or
(repeat(41, sig_1463) and chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3);
-- Behaviour of component 'mux_303' model 'mux'
mux_303 <=
(repeat(41, sig_1216) and sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647) or
(repeat(41, sig_1060) and yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r) or
(repeat(41, sig_1471) and sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642) or
(repeat(41, sig_1463) and chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0);
-- Behaviour of component 'mux_294' model 'mux'
mux_294 <=
(repeat(2, sig_995) and "01") or
(repeat(2, sig_994) and "10") or
(repeat(2, sig_1045) and decode_start_i(1 downto 0));
-- Behaviour of component 'mux_290' model 'mux'
mux_290 <=
(repeat(41, sig_1395) and chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1) or
(repeat(41, sig_1376) and "00000000000000000000000000000000000000111") or
(repeat(41, sig_1363) and chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2) or
(repeat(41, sig_1355) and buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5 downto 0)) or
(repeat(41, sig_1349) and sig_1627) or
(repeat(41, sig_1534) and sig_1660(31) & sig_1660(31) & sig_1660(31) & sig_1660(31) & sig_1660(31) & sig_1660(31) & sig_1660(31) & sig_1660(31) & sig_1660(31) & sig_1660) or
(repeat(41, sig_1324) and sig_1667(38 downto 0) & "00") or
(repeat(41, sig_1318) and "00000000000000000000000000000000000000010") or
(repeat(41, sig_1313) and get_dht_count(31) & get_dht_count(31) & get_dht_count(31) & get_dht_count(31) & get_dht_count(31) & get_dht_count(31) & get_dht_count(31) & get_dht_count(31) & get_dht_count(31) & get_dht_count) or
(repeat(41, sig_1300) and "00000000000000000000000000000000000010001") or
(repeat(41, sig_1299) and "00000000000000000000000000000000010000000") or
(repeat(41, sig_1292) and sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654) or
(repeat(41, sig_1289) and sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650) or
(repeat(41, sig_1280) and chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0) or
(repeat(41, sig_1550) and "00000000000000000000000000000000000010000") or
(repeat(41, sig_1569) and sig_1651(31) & sig_1651(31) & sig_1651(31) & sig_1651(31) & sig_1651(31) & sig_1651(31) & sig_1651(31) & sig_1651(31) & sig_1651(31) & sig_1651) or
(repeat(41, sig_1576) and sig_1655(31) & sig_1655(31) & sig_1655(31) & sig_1655(31) & sig_1655(31) & sig_1655(31) & sig_1655(31) & sig_1655(31) & sig_1655(31) & sig_1655) or
(repeat(41, sig_1505) and sig_1658(31) & sig_1658(31) & sig_1658(31) & sig_1658(31) & sig_1658(31) & sig_1658(31) & sig_1658(31) & sig_1658(31) & sig_1658(31) & sig_1658) or
(repeat(41, sig_1491) and "00000000000000000000000000000000000001000") or
(repeat(41, sig_1486) and "00000000000000000000000000000000000010111") or
(repeat(41, sig_1485) and "00000000000000000000000000000000000000001") or
(repeat(41, sig_1440) and chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1) or
(repeat(41, sig_1434) and "00000000000000000000000000000000000111111") or
(repeat(41, sig_1244) and "000000000000000000000000000000000" & p_jinfo_num_components) or
(repeat(41, sig_1241) and "000000000000000000000000000000000" & get_sos_num_comp) or
(repeat(41, sig_1240) and "00000000000000000000000000000000001000000") or
(repeat(41, sig_1229) and chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3) or
(repeat(41, sig_1217) and sig_1628(28) & sig_1628(28) & sig_1628(28) & sig_1628(28) & sig_1628(28) & sig_1628(28) & sig_1628(28) & sig_1628(28) & sig_1628(28) & sig_1628(28 downto 0) & "000") or
(repeat(41, sig_1216) and p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth) or
(repeat(41, sig_1165) and buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p) or
(repeat(41, sig_1118) and sig_1627(39 downto 0) & '0') or
(repeat(41, sig_1089) and "00000000000000000000000000000000001000001") or
(repeat(41, sig_1077) and "00000000000000000000000000000000100000000") or
(repeat(41, sig_1049) and "00000000000000000000000000000000000000011") or
(repeat(41, sig_1048) and p_jinfo_nummcu(31) & p_jinfo_nummcu(31) & p_jinfo_nummcu(31) & p_jinfo_nummcu(31) & p_jinfo_nummcu(31) & p_jinfo_nummcu(31) & p_jinfo_nummcu(31) & p_jinfo_nummcu(31) & p_jinfo_nummcu(31) & p_jinfo_nummcu) or
(repeat(41, sig_1032) and read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position) or
(repeat(41, sig_1015) and writeoneblock_width(31) & writeoneblock_width(31) & writeoneblock_width(31) & writeoneblock_width(31) & writeoneblock_width(31) & writeoneblock_width(31) & writeoneblock_width(31) & writeoneblock_width(31) & writeoneblock_width(31) & writeoneblock_width) or
(repeat(41, sig_1014) and sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28 downto 0) & writeoneblock_hoffs(2 downto 0)) or
(repeat(41, sig_1010) and writeoneblock_height(31) & writeoneblock_height(31) & writeoneblock_height(31) & writeoneblock_height(31) & writeoneblock_height(31) & writeoneblock_height(31) & writeoneblock_height(31) & writeoneblock_height(31) & writeoneblock_height(31) & writeoneblock_height) or
(repeat(41, sig_1009) and sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28 downto 0) & writeoneblock_voffs(2 downto 0));
-- Behaviour of component 'mux_291' model 'mux'
mux_291 <=
(repeat(41, sig_1468) and sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642) or
(repeat(41, sig_1505) and huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j) or
(repeat(41, sig_1502) and huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0) or
(repeat(41, sig_1492) and buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p) or
(repeat(41, sig_1487) and read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position) or
(repeat(41, sig_1420) and chenidct_i(31) & chenidct_i(31) & chenidct_i(31) & chenidct_i(31) & chenidct_i(31) & chenidct_i(31) & chenidct_i(31) & chenidct_i(31) & chenidct_i(31) & chenidct_i) or
(repeat(41, sig_1569) and decodehuffman_ac_code(31) & decodehuffman_ac_code(31) & decodehuffman_ac_code(31) & decodehuffman_ac_code(31) & decodehuffman_ac_code(31) & decodehuffman_ac_code(31) & decodehuffman_ac_code(31) & decodehuffman_ac_code(31) & decodehuffman_ac_code(31) & decodehuffman_ac_code) or
(repeat(41, sig_1395) and chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2) or
(repeat(41, sig_1393) and chenidct_b2(31) & chenidct_b2(31) & chenidct_b2(31) & chenidct_b2(31) & chenidct_b2(31) & chenidct_b2(31) & chenidct_b2(31) & chenidct_b2(31) & chenidct_b2(31) & chenidct_b2) or
(repeat(41, sig_1363) and chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1) or
(repeat(41, sig_1355) and "00000000000000000000000000000000000001000") or
(repeat(41, sig_1349) and sig_1628(38 downto 0) & "00") or
(repeat(41, sig_1342) and decodehuffmcu_s(31) & decodehuffmcu_s(31) & decodehuffmcu_s(31) & decodehuffmcu_s(31) & decodehuffmcu_s(31) & decodehuffmcu_s(31) & decodehuffmcu_s(31) & decodehuffmcu_s(31) & decodehuffmcu_s(31) & decodehuffmcu_s) or
(repeat(41, sig_1336) and get_dqt_i(31) & get_dqt_i(31) & get_dqt_i(31) & get_dqt_i(31) & get_dqt_i(31) & get_dqt_i(31) & get_dqt_i(31) & get_dqt_i(31) & get_dqt_i(31) & get_dqt_i) or
(repeat(41, sig_1324) and sig_1666(39 downto 0) & '0') or
(repeat(41, sig_1576) and decodehuffman_dc_code(31) & decodehuffman_dc_code(31) & decodehuffman_dc_code(31) & decodehuffman_dc_code(31) & decodehuffman_dc_code(31) & decodehuffman_dc_code(31) & decodehuffman_dc_code(31) & decodehuffman_dc_code(31) & decodehuffman_dc_code(31) & decodehuffman_dc_code) or
(repeat(41, sig_1446) and decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i) or
(repeat(41, sig_1455) and decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k) or
(repeat(41, sig_1551) and huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l) or
(repeat(41, sig_1534) and huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j) or
(repeat(41, sig_1531) and huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0) or
(repeat(41, sig_1518) and huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l) or
(repeat(41, sig_1463) and chenidct_c0(31) & chenidct_c0(31) & chenidct_c0(31) & chenidct_c0(31) & chenidct_c0(31) & chenidct_c0(31) & chenidct_c0(31) & chenidct_c0(31) & chenidct_c0(31) & chenidct_c0) or
(repeat(41, sig_1435) and izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i) or
(repeat(41, sig_1322) and get_dqt_length(31) & get_dqt_length(31) & get_dqt_length(31) & get_dqt_length(31) & get_dqt_length(31) & get_dqt_length(31) & get_dqt_length(31) & get_dqt_length(31) & get_dqt_length(31) & get_dqt_length) or
(repeat(41, sig_1319) and read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word) or
(repeat(41, sig_1314) and get_dht_length(31) & get_dht_length(31) & get_dht_length(31) & get_dht_length(31) & get_dht_length(31) & get_dht_length(31) & get_dht_length(31) & get_dht_length(31) & get_dht_length(31) & get_dht_length) or
(repeat(41, sig_1309) and p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height) or
(repeat(41, sig_1303) and get_dht_i(31) & get_dht_i(31) & get_dht_i(31) & get_dht_i(31) & get_dht_i(31) & get_dht_i(31) & get_dht_i(31) & get_dht_i(31) & get_dht_i(31) & get_dht_i) or
(repeat(41, sig_1299) and sig_1640(31) & sig_1640(31) & sig_1640(31) & sig_1640(31) & sig_1640(31) & sig_1640(31) & sig_1640(31) & sig_1640(31) & sig_1640(31) & sig_1640) or
(repeat(41, sig_1291) and sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8 downto 0)) or
(repeat(41, sig_1287) and get_sos_j(31) & get_sos_j(31) & get_sos_j(31) & get_sos_j(31) & get_sos_j(31) & get_sos_j(31) & get_sos_j(31) & get_sos_j(31) & get_sos_j(31) & get_sos_j) or
(repeat(41, sig_1280) and chenidct_b3(31) & chenidct_b3(31) & chenidct_b3(31) & chenidct_b3(31) & chenidct_b3(31) & chenidct_b3(31) & chenidct_b3(31) & chenidct_b3(31) & chenidct_b3(31) & chenidct_b3) or
(repeat(41, sig_1245) and get_sos_ci(31) & get_sos_ci(31) & get_sos_ci(31) & get_sos_ci(31) & get_sos_ci(31) & get_sos_ci(31) & get_sos_ci(31) & get_sos_ci(31) & get_sos_ci(31) & get_sos_ci) or
(repeat(41, sig_1241) and get_sos_i(31) & get_sos_i(31) & get_sos_i(31) & get_sos_i(31) & get_sos_i(31) & get_sos_i(31) & get_sos_i(31) & get_sos_i(31) & get_sos_i(31) & get_sos_i) or
(repeat(41, sig_1229) and chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0) or
(repeat(41, sig_1217) and yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y & "00000000") or
(repeat(41, sig_1216) and sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647) or
(repeat(41, sig_1209) and get_sof_ci(31) & get_sof_ci(31) & get_sof_ci(31) & get_sof_ci(31) & get_sof_ci(31) & get_sof_ci(31) & get_sof_ci(31) & get_sof_ci(31) & get_sof_ci(31) & get_sof_ci) or
(repeat(41, sig_1168) and buf_getv_n(31) & buf_getv_n(31) & buf_getv_n(31) & buf_getv_n(31) & buf_getv_n(31) & buf_getv_n(31) & buf_getv_n(31) & buf_getv_n(31) & buf_getv_n(31) & buf_getv_n) or
(repeat(41, sig_1118) and sig_1628(37) & sig_1628(37 downto 0) & "00") or
(repeat(41, sig_1078) and huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p) or
(repeat(41, sig_1060) and yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r) or
(repeat(41, sig_1051) and decode_start_i(31) & decode_start_i(31) & decode_start_i(31) & decode_start_i(31) & decode_start_i(31) & decode_start_i(31) & decode_start_i(31) & decode_start_i(31) & decode_start_i(31) & decode_start_i) or
(repeat(41, sig_1048) and decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu) or
(repeat(41, sig_1037) and huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p) or
(repeat(41, sig_1025) and yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i) or
(repeat(41, sig_1016) and writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e) or
(repeat(41, sig_1011) and writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i) or
(repeat(41, sig_1005) and write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs);
-- Behaviour of component 'mux_292' model 'mux'
mux_292 <=
(repeat(32, sig_1294) and sig_1613) or
(repeat(32, sig_1427) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_286' model 'mux'
mux_286 <=
(repeat(32, sig_1047) and sig_1610(31 downto 0)) or
(repeat(32, sig_1052) and sig_1610(29 downto 0) & decode_start_currentmcu(1 downto 0));
-- Behaviour of component 'mux_275' model 'mux'
mux_275 <=
(repeat(32, sig_1396) and chenidct_i) or
(repeat(32, sig_1118) and chenidct_a1) or
(repeat(32, sig_1217) and sig_1609(23) & sig_1609(23) & sig_1609(23) & sig_1609(23) & sig_1609(23) & sig_1609(23) & sig_1609(23) & sig_1609(23 downto 0) & sig_1666(6)) or
(repeat(32, sig_1294) and decode_start_i) or
(repeat(32, sig_1309) and sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16 downto 3)) or
(repeat(32, sig_1451) and sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31 downto 4)) or
(repeat(32, sig_1463) and chenidct_c3);
-- Behaviour of component 'mux_272' model 'mux'
mux_272 <=
(repeat(39, sig_1217) and yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y) or
(repeat(39, sig_1118) and sig_1600(40 downto 2)) or
(repeat(39, sig_1309) and sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16 downto 0)) or
(repeat(39, sig_1449) and chenidct_i(31) & chenidct_i(31) & chenidct_i(31) & chenidct_i(31) & chenidct_i(31) & chenidct_i(31) & chenidct_i(31) & chenidct_i);
-- Behaviour of component 'mux_274' model 'mux'
mux_274 <=
(repeat(32, sig_1397) and "00000000000000000000000000000001") or
(repeat(32, sig_1118) and chenidct_a2) or
(repeat(32, sig_1309) and "0000000000000000000000000000000" & and_864) or
(repeat(32, sig_1451) and "0000000000000000000000000000000" & and_789) or
(repeat(32, sig_1463) and chenidct_c2);
-- Behaviour of component 'mux_271' model 'mux'
mux_271 <=
(repeat(39, sig_1118) and sig_1668(38 downto 0)) or
(repeat(39, sig_1217) and sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31 downto 8)) or
(repeat(39, sig_1448) and "000000000000000000000000000000000000001");
-- Behaviour of component 'mux_266' model 'mux'
mux_266 <=
(repeat(39, sig_1463) and chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0) or
(repeat(39, sig_1574) and decodehuffman_dc_code(30) & decodehuffman_dc_code(30) & decodehuffman_dc_code(30) & decodehuffman_dc_code(30) & decodehuffman_dc_code(30) & decodehuffman_dc_code(30) & decodehuffman_dc_code(30) & decodehuffman_dc_code(30) & decodehuffman_dc_code(30 downto 0)) or
(repeat(39, sig_1567) and decodehuffman_ac_code(30) & decodehuffman_ac_code(30) & decodehuffman_ac_code(30) & decodehuffman_ac_code(30) & decodehuffman_ac_code(30) & decodehuffman_ac_code(30) & decodehuffman_ac_code(30) & decodehuffman_ac_code(30) & decodehuffman_ac_code(30 downto 0)) or
(repeat(39, sig_1563) and huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l) or
(repeat(39, sig_1561) and sig_1655(31) & sig_1655(31) & sig_1655(31) & sig_1655(31) & sig_1655(31) & sig_1655(31) & sig_1655(31) & sig_1655) or
(repeat(39, sig_1556) and sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31 downto 7)) or
(repeat(39, sig_1479) and get_dht_i(31) & get_dht_i(31) & get_dht_i(31) & get_dht_i(31) & get_dht_i(31) & get_dht_i(31) & get_dht_i(31) & get_dht_i) or
(repeat(39, sig_1548) and huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p) or
(repeat(39, sig_1536) and huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0) or
(repeat(39, sig_1529) and huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p) or
(repeat(39, sig_1525) and huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l) or
(repeat(39, sig_1523) and sig_1651(31) & sig_1651(31) & sig_1651(31) & sig_1651(31) & sig_1651(31) & sig_1651(31) & sig_1651(31) & sig_1651) or
(repeat(39, sig_1507) and huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0) or
(repeat(39, sig_1493) and read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31 downto 3)) or
(repeat(39, sig_1412) and "0000000" & chenidct_aidx) or
(repeat(39, sig_1477) and "0000000000" & chenidct_aidx(31 downto 3)) or
(repeat(39, sig_1466) and decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k) or
(repeat(39, sig_1464) and decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31 downto 4)) or
(repeat(39, sig_1451) and sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31 downto 3)) or
(repeat(39, sig_1443) and decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i) or
(repeat(39, sig_1441) and "0000000" & curhuffreadbuf_idx) or
(repeat(39, sig_1582) and "0000000000" & chenidct_i(31 downto 3)) or
(repeat(39, sig_1436) and izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i) or
(repeat(39, sig_1427) and decode_start_i(31) & decode_start_i(31) & decode_start_i(31) & decode_start_i(31) & decode_start_i(31) & decode_start_i(31) & decode_start_i(31) & decode_start_i) or
(repeat(39, sig_1395) and chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1) or
(repeat(39, sig_1350) and "0000000" & chenidct_i(28 downto 0) & "001") or
(repeat(39, sig_1335) and get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num) or
(repeat(39, sig_1309) and sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16 downto 3)) or
(repeat(39, sig_1297) and sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647) or
(repeat(39, sig_1292) and sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653) or
(repeat(39, sig_1289) and sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649) or
(repeat(39, sig_1283) and huff_make_dhuff_tb_ac_size(31) & huff_make_dhuff_tb_ac_size(31) & huff_make_dhuff_tb_ac_size(31) & huff_make_dhuff_tb_ac_size(31) & huff_make_dhuff_tb_ac_size(31) & huff_make_dhuff_tb_ac_size(31) & huff_make_dhuff_tb_ac_size(31) & huff_make_dhuff_tb_ac_size) or
(repeat(39, sig_1264) and chenidct_b2(31) & chenidct_b2(31) & chenidct_b2(31) & chenidct_b2(31) & chenidct_b2(31) & chenidct_b2(31) & chenidct_b2(31) & chenidct_b2) or
(repeat(39, sig_1257) and sig_1643(31) & sig_1643(31) & sig_1643(31) & sig_1643(31) & sig_1643(31) & sig_1643(31) & sig_1643(31) & sig_1643) or
(repeat(39, sig_1254) and get_sos_ci(31) & get_sos_ci(31) & get_sos_ci(31) & get_sos_ci(31) & get_sos_ci(31) & get_sos_ci(31) & get_sos_ci(31) & get_sos_ci) or
(repeat(39, sig_1251) and get_sos_i(31) & get_sos_i(31) & get_sos_i(31) & get_sos_i(31) & get_sos_i(31) & get_sos_i(31) & get_sos_i(31) & get_sos_i) or
(repeat(39, sig_1247) and "0000000" & readbuf_idx) or
(repeat(39, sig_1234) and yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i) or
(repeat(39, sig_1217) and sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31 downto 7)) or
(repeat(39, sig_1211) and get_sof_ci(31) & get_sof_ci(31) & get_sof_ci(31) & get_sof_ci(31) & get_sof_ci(31) & get_sof_ci(31) & get_sof_ci(31) & get_sof_ci) or
(repeat(39, sig_1163) and sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31 downto 1)) or
(repeat(39, sig_1118) and sig_1666(39 downto 1)) or
(repeat(39, sig_1112) and chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1) or
(repeat(39, sig_1110) and chenidct_b3(31) & chenidct_b3(31) & chenidct_b3(31) & chenidct_b3(31) & chenidct_b3(31) & chenidct_b3(31) & chenidct_b3(31) & chenidct_b3) or
(repeat(39, sig_1073) and "0000000000000000000000000000000000000" & sig_1663) or
(repeat(39, sig_1068) and huff_make_dhuff_tb_dc_size(31) & huff_make_dhuff_tb_dc_size(31) & huff_make_dhuff_tb_dc_size(31) & huff_make_dhuff_tb_dc_size(31) & huff_make_dhuff_tb_dc_size(31) & huff_make_dhuff_tb_dc_size(31) & huff_make_dhuff_tb_dc_size(31) & huff_make_dhuff_tb_dc_size) or
(repeat(39, sig_1059) and "0000000" & jpeg2bmp_main_j) or
(repeat(39, sig_1056) and "0000000" & jpeg2bmp_main_i) or
(repeat(39, sig_1052) and decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31 downto 2)) or
(repeat(39, sig_1047) and decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu) or
(repeat(39, sig_1026) and decodehuffmcu_diff(31) & decodehuffmcu_diff(31) & decodehuffmcu_diff(31) & decodehuffmcu_diff(31) & decodehuffmcu_diff(31) & decodehuffmcu_diff(31) & decodehuffmcu_diff(31) & decodehuffmcu_diff) or
(repeat(39, sig_1021) and write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31 downto 3)) or
(repeat(39, sig_1018) and writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i) or
(repeat(39, sig_1017) and writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e) or
(repeat(39, sig_1014) and writeoneblock_hoffs(31) & writeoneblock_hoffs(31) & writeoneblock_hoffs(31) & writeoneblock_hoffs(31) & writeoneblock_hoffs(31) & writeoneblock_hoffs(31) & writeoneblock_hoffs(31) & writeoneblock_hoffs(31) & writeoneblock_hoffs(31) & writeoneblock_hoffs(31) & writeoneblock_hoffs(31 downto 3)) or
(repeat(39, sig_1012) and writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff) or
(repeat(39, sig_1009) and writeoneblock_voffs(31) & writeoneblock_voffs(31) & writeoneblock_voffs(31) & writeoneblock_voffs(31) & writeoneblock_voffs(31) & writeoneblock_voffs(31) & writeoneblock_voffs(31) & writeoneblock_voffs(31) & writeoneblock_voffs(31) & writeoneblock_voffs(31) & writeoneblock_voffs(31 downto 3)) or
(repeat(39, sig_1005) and write4blocks_voffs(31) & write4blocks_voffs(31) & write4blocks_voffs(31) & write4blocks_voffs(31) & write4blocks_voffs(31) & write4blocks_voffs(31) & write4blocks_voffs(31) & write4blocks_voffs(31) & write4blocks_voffs(31) & write4blocks_voffs(31) & write4blocks_voffs(31 downto 3));
-- Behaviour of component 'mux_265' model 'mux'
mux_265 <=
(repeat(39, sig_1112) and chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2) or
(repeat(39, sig_1110) and chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0) or
(repeat(39, sig_1027) and sig_1643(31) & sig_1643(31) & sig_1643(31) & sig_1643(31) & sig_1643(31) & sig_1643(31) & sig_1643(31) & sig_1643) or
(repeat(39, sig_1012) and writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12 downto 0)) or
(repeat(39, sig_1006) and "00000000000" & decodehuffmcu_n) or
(repeat(39, sig_1309) and "00000000000000000000000000000000000000" & and_862) or
(repeat(39, sig_1395) and chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2) or
(repeat(39, sig_1546) and "111111111111111111111111111111111111111") or
(repeat(39, sig_1556) and "000000000000000000000000000000000000001") or
(repeat(39, sig_1292) and decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8 downto 0)) or
(repeat(39, sig_1289) and decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8 downto 0)) or
(repeat(39, sig_1264) and chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1) or
(repeat(39, sig_1118) and sig_1667(37) & sig_1667(37 downto 0)) or
(repeat(39, sig_1463) and chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3) or
(repeat(39, sig_1426) and "000000000000000000000000000000000000001");
-- Behaviour of component 'mux_260' model 'mux'
mux_260 <=
(repeat(39, sig_1458) and "0000000000000000000000000000000" & read_byte) or
(repeat(39, sig_1324) and sig_1627(38 downto 0)) or
(repeat(39, sig_1395) and chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3) or
(repeat(39, sig_1544) and sig_1658(31) & sig_1658(31) & sig_1658(31) & sig_1658(31) & sig_1658(31) & sig_1658(31) & sig_1658(31) & sig_1658) or
(repeat(39, sig_1451) and "00000000000000000000000000000000000000" & and_785) or
(repeat(39, sig_1217) and sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30 downto 7)) or
(repeat(39, sig_1118) and chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1) or
(repeat(39, sig_1038) and sig_1660(31) & sig_1660(31) & sig_1660(31) & sig_1660(31) & sig_1660(31) & sig_1660(31) & sig_1660(31) & sig_1660) or
(repeat(39, sig_1463) and chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1) or
(repeat(39, sig_1438) and "000000000000000000000000000000000000001");
-- Behaviour of component 'mux_261' model 'mux'
mux_261 <=
(repeat(39, sig_1458) and get_dht_count(31) & get_dht_count(31) & get_dht_count(31) & get_dht_count(31) & get_dht_count(31) & get_dht_count(31) & get_dht_count(31) & get_dht_count) or
(repeat(39, sig_1324) and sig_1628(39 downto 1)) or
(repeat(39, sig_1309) and sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16 downto 0)) or
(repeat(39, sig_1297) and sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648) or
(repeat(39, sig_1262) and "0000000" & chenidct_aidx) or
(repeat(39, sig_1217) and yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y) or
(repeat(39, sig_1546) and sig_1610(31) & sig_1610(31) & sig_1610(31) & sig_1610(31) & sig_1610(31) & sig_1610(31) & sig_1610(31) & sig_1610(31 downto 0)) or
(repeat(39, sig_1163) and sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31 downto 1)) or
(repeat(39, sig_1111) and "0000000000" & chenidct_aidx(31 downto 3)) or
(repeat(39, sig_1035) and huff_make_dhuff_tb_dc_code(31) & huff_make_dhuff_tb_dc_code(31) & huff_make_dhuff_tb_dc_code(31) & huff_make_dhuff_tb_dc_code(31) & huff_make_dhuff_tb_dc_code(31) & huff_make_dhuff_tb_dc_code(31) & huff_make_dhuff_tb_dc_code(31) & huff_make_dhuff_tb_dc_code) or
(repeat(39, sig_1023) and huff_make_dhuff_tb_ac_code(31) & huff_make_dhuff_tb_ac_code(31) & huff_make_dhuff_tb_ac_code(31) & huff_make_dhuff_tb_ac_code(31) & huff_make_dhuff_tb_ac_code(31) & huff_make_dhuff_tb_ac_code(31) & huff_make_dhuff_tb_ac_code(31) & huff_make_dhuff_tb_ac_code) or
(repeat(39, sig_1012) and "0000000" & writeoneblock_inidx) or
(repeat(39, sig_1567) and decodehuffman_ac_l(31) & decodehuffman_ac_l(31) & decodehuffman_ac_l(31) & decodehuffman_ac_l(31) & decodehuffman_ac_l(31) & decodehuffman_ac_l(31) & decodehuffman_ac_l(31) & decodehuffman_ac_l) or
(repeat(39, sig_1574) and decodehuffman_dc_l(31) & decodehuffman_dc_l(31) & decodehuffman_dc_l(31) & decodehuffman_dc_l(31) & decodehuffman_dc_l(31) & decodehuffman_dc_l(31) & decodehuffman_dc_l(31) & decodehuffman_dc_l) or
(repeat(39, sig_1451) and sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28 downto 1)) or
(repeat(39, sig_1527) and huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j) or
(repeat(39, sig_1499) and huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j) or
(repeat(39, sig_1398) and chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0) or
(repeat(39, sig_1335) and get_dqt_i(31) & get_dqt_i(31) & get_dqt_i(31) & get_dqt_i(31) & get_dqt_i(31) & get_dqt_i(31) & get_dqt_i(31) & get_dqt_i) or
(repeat(39, sig_1463) and chenidct_c0(31) & chenidct_c0(31) & chenidct_c0(31) & chenidct_c0(31) & chenidct_c0(31) & chenidct_c0(31) & chenidct_c0(31) & chenidct_c0) or
(repeat(39, sig_1436) and izigzagmatrix_out_idx(31) & izigzagmatrix_out_idx(31) & izigzagmatrix_out_idx(31) & izigzagmatrix_out_idx(31) & izigzagmatrix_out_idx(31) & izigzagmatrix_out_idx(31) & izigzagmatrix_out_idx(31) & izigzagmatrix_out_idx);
-- Behaviour of component 'mux_262' model 'mux'
mux_262 <=
(repeat(32, sig_1056) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_257' model 'mux'
mux_257 <=
(repeat(32, sig_1059) and sig_1610(31 downto 0));
-- Behaviour of component 'nand_786' model 'nand'
nand_786 <= not (
sig_1605 and
sig_1606
);
-- Behaviour of component 'or_845' model 'or'
or_845 <=
sig_1629 or
buf_getv_rv;
-- Behaviour of component 'or_854' model 'or'
or_854 <=
sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638 or
buf_getv;
-- Behaviour of component 'or_866' model 'or'
or_866 <=
sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638 or
sig_1643;
-- Behaviour of component 'and_785' model 'and'
and_785 <=
nand_786 and
sig_1610(28);
-- Behaviour of component 'and_801' model 'and'
and_801 <=
sig_1636 and
current_read_byte;
-- Behaviour of component 'mux_761' model 'mux'
mux_761 <=
(repeat(9, sig_1118) and "000011001") or
(repeat(9, sig_1217) and "101100111") or
(repeat(9, sig_1324) and "001000111");
-- Behaviour of component 'mux_782' model 'mux'
mux_782 <=
(repeat(32, sig_1607) and sig_1660) or
(repeat(32, sig_1608) and "000000000000000000000000" & read_byte);
-- Behaviour of component 'or_802' model 'or'
or_802 <=
current_read_byte(23 downto 0) or
"000000000000000000000000";
-- Behaviour of component 'and_803' model 'and'
and_803 <=
sig_1637 and
current_read_byte;
-- Behaviour of component 'mux_822' model 'mux'
mux_822 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_823' model 'mux'
mux_823 <=
(repeat(32, sig_1617) and mux_824);
-- Behaviour of component 'mux_776' model 'mux'
mux_776 <=
(repeat(32, sig_1617) and mux_777);
-- Behaviour of component 'mux_820' model 'mux'
mux_820 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_824' model 'mux'
mux_824 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_825' model 'mux'
mux_825 <=
(repeat(32, sig_1617) and mux_826);
-- Behaviour of component 'mux_760' model 'mux'
mux_760 <=
(repeat(32, sig_1118) and chenidct_a0) or
(repeat(32, sig_1217) and yuvtorgb_u(30) & yuvtorgb_u) or
(repeat(32, sig_1324) and chenidct_a2);
-- Behaviour of component 'and_789' model 'and'
and_789 <=
sig_1604 and
sig_1624(31);
-- Behaviour of component 'mux_759' model 'mux'
mux_759 <=
(repeat(6, sig_1118) and "111011") or
(repeat(6, sig_1217) and "100011") or
(repeat(6, sig_1324) and "010101");
-- Behaviour of component 'mux_768' model 'mux'
mux_768 <=
(repeat(32, sig_1436) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_757' model 'mux'
mux_757 <=
(repeat(8, sig_1057) and sig_1646) or
(repeat(8, sig_1062) and outdata_image_height);
-- Behaviour of component 'mux_773' model 'mux'
mux_773 <=
(repeat(8, sig_1179) and outdata_image_height) or
(repeat(8, sig_1180) and outdata_image_width) or
(repeat(8, sig_1181) and write8_u8);
-- Behaviour of component 'mux_762' model 'mux'
mux_762 <=
(repeat(32, sig_1118) and chenidct_a3) or
(repeat(32, sig_1217) and yuvtorgb_v) or
(repeat(32, sig_1324) and chenidct_a1);
-- Behaviour of component 'mux_766' model 'mux'
mux_766 <=
(repeat(32, sig_1436) and sig_1609(31 downto 0));
-- Behaviour of component 'mux_781' model 'mux'
mux_781 <=
(repeat(32, sig_1608) and sig_1657) or
(repeat(32, sig_1607) and "000000000000000000000000" & read_byte);
-- Behaviour of component 'mux_797' model 'mux'
mux_797 <=
(repeat(32, sig_1617) and mux_798);
-- Behaviour of component 'mux_821' model 'mux'
mux_821 <=
(repeat(32, sig_1617) and mux_822);
-- Behaviour of component 'mux_826' model 'mux'
mux_826 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_778' model 'mux'
mux_778 <=
(repeat(32, sig_1607) and sig_1659) or
(repeat(32, sig_1608) and "000000000000000000000000" & read_byte);
-- Behaviour of component 'mux_827' model 'mux'
mux_827 <=
(repeat(32, sig_1617) and mux_828);
-- Behaviour of component 'mux_815' model 'mux'
mux_815 <=
(repeat(32, sig_1617) and mux_816);
-- Behaviour of component 'mux_798' model 'mux'
mux_798 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_816' model 'mux'
mux_816 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_817' model 'mux'
mux_817 <=
(repeat(32, sig_1617) and mux_818);
-- Behaviour of component 'mux_777' model 'mux'
mux_777 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_819' model 'mux'
mux_819 <=
(repeat(32, sig_1617) and mux_820);
-- Behaviour of component 'mux_783' model 'mux'
mux_783 <=
(repeat(32, sig_1608) and sig_1658) or
(repeat(32, sig_1607) and "000000000000000000000000" & read_byte);
-- Behaviour of component 'mux_795' model 'mux'
mux_795 <=
(repeat(32, sig_1617) and mux_796);
-- Behaviour of component 'mux_796' model 'mux'
mux_796 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_805' model 'mux'
mux_805 <=
(repeat(32, sig_1617) and mux_806);
-- Behaviour of component 'mux_806' model 'mux'
mux_806 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_807' model 'mux'
mux_807 <=
(repeat(32, sig_1617) and mux_808);
-- Behaviour of component 'mux_808' model 'mux'
mux_808 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_809' model 'mux'
mux_809 <=
(repeat(32, sig_1617) and mux_810);
-- Behaviour of component 'mux_810' model 'mux'
mux_810 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_811' model 'mux'
mux_811 <=
(repeat(32, sig_1617) and mux_812);
-- Behaviour of component 'mux_812' model 'mux'
mux_812 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_813' model 'mux'
mux_813 <=
(repeat(32, sig_1617) and mux_814);
-- Behaviour of component 'mux_814' model 'mux'
mux_814 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_818' model 'mux'
mux_818 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_828' model 'mux'
mux_828 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_829' model 'mux'
mux_829 <=
(repeat(32, sig_1617) and mux_830);
-- Behaviour of component 'mux_830' model 'mux'
mux_830 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_831' model 'mux'
mux_831 <=
(repeat(32, sig_1617) and mux_832);
-- Behaviour of component 'mux_832' model 'mux'
mux_832 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_836' model 'mux'
mux_836 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_837' model 'mux'
mux_837 <=
(repeat(32, sig_1617) and mux_838);
-- Behaviour of component 'mux_839' model 'mux'
mux_839 <=
(repeat(32, sig_1617) and mux_840);
-- Behaviour of component 'mux_840' model 'mux'
mux_840 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_841' model 'mux'
mux_841 <=
(repeat(32, sig_1617) and mux_842);
-- Behaviour of component 'mux_842' model 'mux'
mux_842 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_843' model 'mux'
mux_843 <=
(repeat(32, sig_1617) and mux_844);
-- Behaviour of component 'mux_856' model 'mux'
mux_856 <=
(repeat(32, sig_1617) and mux_857);
-- Behaviour of component 'and_864' model 'and'
and_864 <=
sig_1603 and
sig_1624(16);
-- Behaviour of component 'mux_870' model 'mux'
mux_870 <=
(repeat(32, sig_1599) and get_dqt_length) or
(repeat(32, sig_1669) and sig_1614(31 downto 0));
-- Behaviour of component 'mux_872' model 'mux'
mux_872 <=
(repeat(2, sig_1598) and "10");
-- Behaviour of component 'mux_875' model 'mux'
mux_875 <=
(repeat(32, sig_1616) and sig_1647);
-- Behaviour of component 'mux_891' model 'mux'
mux_891 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_892' model 'mux'
mux_892 <=
(repeat(32, sig_1617) and mux_893);
-- Behaviour of component 'mux_893' model 'mux'
mux_893 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_894' model 'mux'
mux_894 <=
(repeat(32, sig_1617) and mux_895);
-- Behaviour of component 'mux_895' model 'mux'
mux_895 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_896' model 'mux'
mux_896 <=
(repeat(32, sig_1623) and sig_1648) or
(repeat(32, sig_1616) and sig_1624(31 downto 0));
-- Behaviour of component 'mux_897' model 'mux'
mux_897 <=
(repeat(32, sig_1616) and sig_1647);
-- Behaviour of component 'mux_898' model 'mux'
mux_898 <=
(repeat(32, sig_1617) and mux_899);
-- Behaviour of component 'mux_899' model 'mux'
mux_899 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_900' model 'mux'
mux_900 <=
(repeat(32, sig_1617) and mux_901);
-- Behaviour of component 'mux_901' model 'mux'
mux_901 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_902' model 'mux'
mux_902 <=
(repeat(32, sig_1617) and mux_903);
-- Behaviour of component 'mux_903' model 'mux'
mux_903 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_904' model 'mux'
mux_904 <=
(repeat(32, sig_1617) and mux_905);
-- Behaviour of component 'mux_905' model 'mux'
mux_905 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_906' model 'mux'
mux_906 <=
(repeat(32, sig_1617) and mux_907);
-- Behaviour of component 'mux_907' model 'mux'
mux_907 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_908' model 'mux'
mux_908 <=
(repeat(32, sig_1617) and mux_909);
-- Behaviour of component 'mux_917' model 'mux'
mux_917 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_918' model 'mux'
mux_918 <=
(repeat(32, sig_1617) and mux_919);
-- Behaviour of component 'mux_924' model 'mux'
mux_924 <=
(repeat(32, sig_1617) and mux_925);
-- Behaviour of component 'mux_925' model 'mux'
mux_925 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_928' model 'mux'
mux_928 <=
(repeat(32, sig_1617) and mux_929);
-- Behaviour of component 'mux_929' model 'mux'
mux_929 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_931' model 'mux'
mux_931 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_932' model 'mux'
mux_932 <=
(repeat(32, sig_1617) and mux_933);
-- Behaviour of component 'mux_934' model 'mux'
mux_934 <=
(repeat(32, sig_1617) and mux_935);
-- Behaviour of component 'mux_935' model 'mux'
mux_935 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_936' model 'mux'
mux_936 <=
(repeat(32, sig_1617) and mux_937);
-- Behaviour of component 'mux_937' model 'mux'
mux_937 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_938' model 'mux'
mux_938 <=
(repeat(32, sig_1617) and mux_939);
-- Behaviour of component 'mux_939' model 'mux'
mux_939 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_941' model 'mux'
mux_941 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_944' model 'mux'
mux_944 <=
(repeat(32, sig_1617) and mux_945);
-- Behaviour of component 'mux_945' model 'mux'
mux_945 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_946' model 'mux'
mux_946 <=
(repeat(32, sig_1617) and mux_947);
-- Behaviour of component 'mux_833' model 'mux'
mux_833 <=
(repeat(32, sig_1617) and mux_834);
-- Behaviour of component 'mux_834' model 'mux'
mux_834 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_835' model 'mux'
mux_835 <=
(repeat(32, sig_1617) and mux_836);
-- Behaviour of component 'mux_838' model 'mux'
mux_838 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_844' model 'mux'
mux_844 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_857' model 'mux'
mux_857 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_858' model 'mux'
mux_858 <=
(repeat(32, sig_1617) and mux_859);
-- Behaviour of component 'mux_859' model 'mux'
mux_859 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_874' model 'mux'
mux_874 <=
(repeat(32, sig_1623) and sig_1648) or
(repeat(32, sig_1616) and sig_1624(31 downto 0));
-- Behaviour of component 'mux_888' model 'mux'
mux_888 <=
(repeat(32, sig_1617) and mux_889);
-- Behaviour of component 'mux_889' model 'mux'
mux_889 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_913' model 'mux'
mux_913 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_914' model 'mux'
mux_914 <=
(repeat(32, sig_1617) and mux_915);
-- Behaviour of component 'mux_915' model 'mux'
mux_915 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_916' model 'mux'
mux_916 <=
(repeat(32, sig_1617) and mux_917);
-- Behaviour of component 'mux_933' model 'mux'
mux_933 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_940' model 'mux'
mux_940 <=
(repeat(32, sig_1617) and mux_941);
-- Behaviour of component 'mux_942' model 'mux'
mux_942 <=
(repeat(32, sig_1617) and mux_943);
-- Behaviour of component 'and_867' model 'and'
and_867 <=
sig_1670 and
sig_1594;
-- Behaviour of component 'mux_909' model 'mux'
mux_909 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_910' model 'mux'
mux_910 <=
(repeat(32, sig_1617) and mux_911);
-- Behaviour of component 'mux_911' model 'mux'
mux_911 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_920' model 'mux'
mux_920 <=
(repeat(32, sig_1617) and mux_921);
-- Behaviour of component 'mux_921' model 'mux'
mux_921 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_926' model 'mux'
mux_926 <=
(repeat(32, sig_1617) and mux_927);
-- Behaviour of component 'mux_927' model 'mux'
mux_927 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_943' model 'mux'
mux_943 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_886' model 'mux'
mux_886 <=
(sig_1601 and read_byte(0)) or
(sig_1602 and read_byte(0));
-- Behaviour of component 'mux_922' model 'mux'
mux_922 <=
(repeat(32, sig_1617) and mux_923);
-- Behaviour of component 'mux_923' model 'mux'
mux_923 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_930' model 'mux'
mux_930 <=
(repeat(32, sig_1617) and mux_931);
-- Behaviour of component 'mux_987' model 'mux'
mux_987 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'and_860' model 'and'
and_860 <=
sig_1637 and
buf_getv;
-- Behaviour of component 'and_881' model 'and'
and_881 <=
sig_1637 and
sig_1643;
-- Behaviour of component 'and_884' model 'and'
and_884 <=
"00000000000000000000000000010000" and
"000000000000000000000000" & read_byte;
-- Behaviour of component 'mux_890' model 'mux'
mux_890 <=
(repeat(32, sig_1617) and mux_891);
-- Behaviour of component 'mux_912' model 'mux'
mux_912 <=
(repeat(32, sig_1617) and mux_913);
-- Behaviour of component 'mux_919' model 'mux'
mux_919 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_948' model 'mux'
mux_948 <=
(repeat(32, sig_1617) and mux_949);
-- Behaviour of component 'mux_949' model 'mux'
mux_949 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_950' model 'mux'
mux_950 <=
(repeat(32, sig_1617) and mux_951);
-- Behaviour of component 'and_862' model 'and'
and_862 <=
sig_1595 and
sig_1614(16);
-- Behaviour of component 'mux_953' model 'mux'
mux_953 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_954' model 'mux'
mux_954 <=
(repeat(32, sig_1617) and mux_955);
-- Behaviour of component 'mux_955' model 'mux'
mux_955 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_951' model 'mux'
mux_951 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_952' model 'mux'
mux_952 <=
(repeat(32, sig_1617) and mux_953);
-- Behaviour of component 'mux_959' model 'mux'
mux_959 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_960' model 'mux'
mux_960 <=
(repeat(32, sig_1617) and mux_961);
-- Behaviour of component 'mux_961' model 'mux'
mux_961 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_965' model 'mux'
mux_965 <=
(repeat(32, sig_1617) and mux_966);
-- Behaviour of component 'mux_966' model 'mux'
mux_966 <=
(repeat(32, sig_1622) and yuvtorgb_r) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'and_876' model 'and'
and_876 <=
"00001111" and
"0000" & read_byte(7 downto 4);
-- Behaviour of component 'mux_956' model 'mux'
mux_956 <=
(repeat(32, sig_1617) and mux_957);
-- Behaviour of component 'mux_957' model 'mux'
mux_957 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_947' model 'mux'
mux_947 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_968' model 'mux'
mux_968 <=
(repeat(32, sig_1593) and yuvtorgb_b) or
(repeat(32, sig_1591) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_969' model 'mux'
mux_969 <=
(repeat(32, sig_1597) and mux_970);
-- Behaviour of component 'mux_970' model 'mux'
mux_970 <=
(repeat(32, sig_1586) and yuvtorgb_g) or
(repeat(32, sig_1589) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_980' model 'mux'
mux_980 <=
(repeat(32, sig_1617) and mux_981);
-- Behaviour of component 'mux_981' model 'mux'
mux_981 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_958' model 'mux'
mux_958 <=
(repeat(32, sig_1617) and mux_959);
-- Behaviour of component 'and_963' model 'and'
and_963 <=
sig_1615 and
sig_991;
-- Behaviour of component 'mux_986' model 'mux'
mux_986 <=
(repeat(32, sig_1617) and mux_987);
-- Behaviour of component 'mux_988' model 'mux'
mux_988 <=
(repeat(32, sig_1617) and mux_989);
-- Behaviour of component 'mux_989' model 'mux'
mux_989 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of all components of model 'reg'
-- Registers with clock = sig_clock and no reset
process(sig_clock)
begin
if rising_edge(sig_clock) then
if sig_1437 = '1' then
izigzagmatrix_i <= mux_768;
end if;
if sig_1437 = '1' then
izigzagmatrix_out_idx <= mux_766;
end if;
if sig_1072 = '1' then
iquantize_qidx <= sig_1610(1 downto 0);
end if;
if sig_1061 = '1' then
write8_u8 <= mux_757;
end if;
if sig_1206 = '1' then
p_jinfo_image_height <= read_word;
end if;
if sig_1207 = '1' then
p_jinfo_image_width <= read_word;
end if;
if sig_1204 = '1' then
p_jinfo_num_components <= read_byte;
end if;
if sig_1219 = '1' then
p_jinfo_smp_fact <= mux_872;
end if;
if sig_1307 = '1' then
p_jinfo_mcuwidth <= sig_1612(17) & sig_1612(17) & sig_1612(17) & sig_1612(17) & sig_1612(17) & sig_1612(17) & sig_1612(17) & sig_1612(17) & sig_1612(17) & sig_1612(17) & sig_1612(17) & sig_1612(17) & sig_1612(17) & sig_1612(17) & sig_1612(17 downto 0);
end if;
if sig_1307 = '1' then
p_jinfo_mcuheight <= sig_1609(17) & sig_1609(17) & sig_1609(17) & sig_1609(17) & sig_1609(17) & sig_1609(17) & sig_1609(17) & sig_1609(17) & sig_1609(17) & sig_1609(17) & sig_1609(17) & sig_1609(17) & sig_1609(17) & sig_1609(17) & sig_1609(17 downto 0);
end if;
if sig_1100 = '1' then
p_jinfo_nummcu <= sig_1628(31 downto 0);
end if;
if sig_1273 = '1' then
i_jinfo_jpeg_data <= readbuf_idx;
end if;
if sig_1583 = '1' then
curhuffreadbuf_idx <= mux_671;
end if;
if sig_1042 = '1' then
outdata_image_width <= p_jinfo_image_width(7 downto 0);
end if;
if sig_1042 = '1' then
outdata_image_height <= p_jinfo_image_height(7 downto 0);
end if;
if sig_1340 = '1' then
readbuf_idx <= mux_648;
end if;
if sig_1053 = '1' then
read_byte <= sig_1644;
end if;
if sig_1249 = '1' then
read_word <= read_word_c & sig_1644;
end if;
if sig_1248 = '1' then
read_word_c <= sig_1644;
end if;
if sig_1205 = '1' then
next_marker <= next_marker_c;
end if;
if sig_1203 = '1' then
next_marker_c <= read_byte;
end if;
if sig_1210 = '1' then
get_sof_ci <= mux_633;
end if;
if sig_1208 = '1' then
get_sof_i_comp_info_id <= get_sof_ci(1 downto 0);
end if;
if sig_1208 = '1' then
get_sof_i_comp_info_h_samp_factor <= get_sof_ci(1 downto 0);
end if;
if sig_1208 = '1' then
get_sof_i_comp_info_quant_tbl_no <= get_sof_ci(1 downto 0);
end if;
if sig_1224 = '1' then
get_sos_num_comp <= read_byte;
end if;
if sig_1250 = '1' then
get_sos_i <= mux_622;
end if;
if sig_1272 = '1' then
get_sos_c <= read_byte(4);
end if;
if sig_1242 = '1' then
get_sos_cc <= read_byte;
end if;
if sig_1253 = '1' then
get_sos_ci <= mux_616;
end if;
if sig_1286 = '1' then
get_sos_j <= mux_614;
end if;
if sig_1243 = '1' then
get_sos_i_comp_info_dc_tbl_no <= get_sos_ci(1 downto 0);
end if;
if sig_1312 = '1' then
get_dht_length <= sig_1614(31 downto 0);
end if;
if sig_1199 = '1' then
get_dht_index <= mux_886;
end if;
if sig_1541 = '1' then
get_dht_i <= mux_602;
end if;
if sig_1456 = '1' then
get_dht_count <= mux_600;
end if;
if sig_1199 = '1' then
get_dht_is_ac <= sig_1602;
end if;
if sig_1316 = '1' then
get_dqt_length <= mux_593;
end if;
if sig_1302 = '1' then
get_dqt_prec <= read_byte(7 downto 4);
end if;
if sig_1302 = '1' then
get_dqt_num <= read_byte(1 downto 0);
end if;
if sig_1333 = '1' then
get_dqt_i <= mux_587;
end if;
if sig_1338 = '1' then
get_dqt_tmp <= mux_585;
end if;
if sig_1347 = '1' then
read_markers_unread_marker <= mux_580;
end if;
if sig_1352 = '1' then
read_markers_sow_soi <= sig_1353;
end if;
if sig_1447 = '1' then
chenidct_i <= mux_555;
end if;
if sig_1476 = '1' then
chenidct_aidx <= mux_553;
end if;
if sig_1462 = '1' then
chenidct_a0 <= mux_551;
end if;
if sig_1439 = '1' then
chenidct_a1 <= mux_549;
end if;
if sig_1584 = '1' then
chenidct_a2 <= mux_547;
end if;
if sig_1465 = '1' then
chenidct_a3 <= mux_545;
end if;
if sig_1459 = '1' then
chenidct_b0 <= mux_543;
end if;
if sig_1356 = '1' then
chenidct_b1 <= mux_541;
end if;
if sig_1478 = '1' then
chenidct_b2 <= mux_539;
end if;
if sig_1460 = '1' then
chenidct_b3 <= mux_537;
end if;
if sig_1461 = '1' then
chenidct_c0 <= mux_535;
end if;
if sig_1394 = '1' then
chenidct_c1 <= mux_533;
end if;
if sig_1394 = '1' then
chenidct_c2 <= mux_531;
end if;
if sig_1461 = '1' then
chenidct_c3 <= mux_529;
end if;
if sig_1494 = '1' then
current_read_byte <= mux_521;
end if;
if sig_1424 = '1' then
pgetc <= mux_517;
end if;
if sig_1442 = '1' then
pgetc_temp <= sig_1644;
end if;
if sig_1483 = '1' then
buf_getb <= sig_1481;
end if;
if sig_1495 = '1' then
buf_getv <= mux_507;
end if;
if sig_1200 = '1' then
buf_getv_n <= mux_505;
end if;
if sig_1490 = '1' then
buf_getv_p <= sig_1614(31 downto 0);
end if;
if sig_1488 = '1' then
buf_getv_rv <= mux_501;
end if;
if sig_1521 = '1' then
huff_make_dhuff_tb_ac <= huff_make_dhuff_tb_ac_p_dhtbl_ml;
end if;
if sig_1187 = '1' then
huff_make_dhuff_tb_ac_tbl_no <= sig_1184;
end if;
if sig_1543 = '1' then
huff_make_dhuff_tb_ac_p_dhtbl_ml <= mux_492;
end if;
if sig_1506 = '1' then
huff_make_dhuff_tb_ac_i_c0 <= mux_490;
end if;
if sig_1503 = '1' then
huff_make_dhuff_tb_ac_j <= mux_488;
end if;
if sig_1545 = '1' then
huff_make_dhuff_tb_ac_p <= mux_486;
end if;
if sig_1282 = '1' then
huff_make_dhuff_tb_ac_code <= mux_484;
end if;
if sig_1557 = '1' then
huff_make_dhuff_tb_ac_size <= mux_482;
end if;
if sig_1524 = '1' then
huff_make_dhuff_tb_ac_l <= mux_480;
end if;
if sig_1559 = '1' then
huff_make_dhuff_tb_dc <= huff_make_dhuff_tb_dc_p_dhtbl_ml;
end if;
if sig_1306 = '1' then
huff_make_dhuff_tb_dc_tbl_no <= sig_1189;
end if;
if sig_1539 = '1' then
huff_make_dhuff_tb_dc_p_dhtbl_ml <= mux_459;
end if;
if sig_1535 = '1' then
huff_make_dhuff_tb_dc_i_c0 <= mux_457;
end if;
if sig_1532 = '1' then
huff_make_dhuff_tb_dc_j <= mux_455;
end if;
if sig_1538 = '1' then
huff_make_dhuff_tb_dc_p <= mux_453;
end if;
if sig_1067 = '1' then
huff_make_dhuff_tb_dc_code <= mux_451;
end if;
if sig_1069 = '1' then
huff_make_dhuff_tb_dc_size <= mux_449;
end if;
if sig_1562 = '1' then
huff_make_dhuff_tb_dc_l <= mux_447;
end if;
if sig_1572 = '1' then
decodehuffman_ac <= mux_430;
end if;
if sig_1452 = '1' then
decodehuffman_ac_tbl_no <= decodehuffmcu_tbl_no;
end if;
if sig_1452 = '1' then
decodehuffman_ac_dhuff_ml <= sig_1652(5 downto 0);
end if;
if sig_1566 = '1' then
decodehuffman_ac_code <= mux_424;
end if;
if sig_1566 = '1' then
decodehuffman_ac_l <= mux_422;
end if;
if sig_1288 = '1' then
decodehuffman_ac_p <= sig_1614(8 downto 0);
end if;
if sig_1580 = '1' then
decodehuffman_dc <= mux_416;
end if;
if sig_1509 = '1' then
decodehuffman_dc_tbl_no <= sig_1662;
end if;
if sig_1169 = '1' then
decodehuffman_dc_dhuff_ml <= sig_1656(5 downto 0);
end if;
if sig_1573 = '1' then
decodehuffman_dc_code <= mux_410;
end if;
if sig_1573 = '1' then
decodehuffman_dc_l <= mux_408;
end if;
if sig_1290 = '1' then
decodehuffman_dc_p <= sig_1614(8 downto 0);
end if;
if sig_1509 = '1' then
decodehuffmcu_bufdim1 <= decode_block_in_buf_idx;
end if;
if sig_1578 = '1' then
decodehuffmcu_s <= mux_400;
end if;
if sig_1343 = '1' then
decodehuffmcu_diff <= mux_398;
end if;
if sig_1509 = '1' then
decodehuffmcu_tbl_no <= sig_1662;
end if;
if sig_1444 = '1' then
decodehuffmcu_i <= mux_394;
end if;
if sig_1467 = '1' then
decodehuffmcu_k <= mux_392;
end if;
if sig_1029 = '1' then
decodehuffmcu_n <= and_983;
end if;
if sig_1195 = '1' then
writeoneblock_outidx <= mux_375;
end if;
if sig_1195 = '1' then
writeoneblock_indim1 <= mux_373;
end if;
if sig_1195 = '1' then
writeoneblock_width <= p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width;
end if;
if sig_1195 = '1' then
writeoneblock_height <= p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height;
end if;
if sig_1195 = '1' then
writeoneblock_voffs <= mux_367;
end if;
if sig_1195 = '1' then
writeoneblock_hoffs <= mux_365;
end if;
if sig_1064 = '1' then
writeoneblock_i <= mux_363;
end if;
if sig_1080 = '1' then
writeoneblock_e <= mux_361;
end if;
if sig_1066 = '1' then
writeoneblock_inidx <= mux_359;
end if;
if sig_1082 = '1' then
writeoneblock_diff <= sig_1628(12 downto 0);
end if;
if sig_996 = '1' then
writeblock_i <= decode_start_i(1 downto 0);
end if;
if sig_1191 = '1' then
write4blocks_i <= decode_start_i(1 downto 0);
end if;
if sig_1193 = '1' then
write4blocks_voffs <= mux_347;
end if;
if sig_1192 = '1' then
write4blocks_hoffs <= mux_345;
end if;
if sig_998 = '1' then
yuvtorgb_p <= mux_343;
end if;
if sig_998 = '1' then
yuvtorgb_yidx <= mux_341;
end if;
if sig_998 = '1' then
yuvtorgb_uidx <= mux_339;
end if;
if sig_998 = '1' then
yuvtorgb_vidx <= mux_337;
end if;
if sig_1218 = '1' then
yuvtorgb_r <= mux_335;
end if;
if sig_1218 = '1' then
yuvtorgb_g <= mux_333;
end if;
if sig_1218 = '1' then
yuvtorgb_b <= mux_331;
end if;
if sig_1298 = '1' then
yuvtorgb_y <= sig_1642(23 downto 0);
end if;
if sig_1298 = '1' then
yuvtorgb_u <= sig_1624(30 downto 0);
end if;
if sig_1298 = '1' then
yuvtorgb_v <= sig_1614(31 downto 0);
end if;
if sig_1233 = '1' then
yuvtorgb_i <= mux_320;
end if;
if sig_1044 = '1' then
decode_block_comp_no <= mux_317;
end if;
if sig_1044 = '1' then
decode_block_out_buf_idx <= mux_308;
end if;
if sig_1044 = '1' then
decode_block_in_buf_idx <= mux_294;
end if;
if sig_1430 = '1' then
decode_start_i <= mux_292;
end if;
if sig_1182 = '1' then
decode_start_currentmcu <= mux_286;
end if;
if sig_1055 = '1' then
jpeg2bmp_main_i <= mux_262;
end if;
if sig_1058 = '1' then
jpeg2bmp_main_j <= mux_257;
end if;
if sig_1178 = '1' then
read8_ret0_195 <= stdin_data;
end if;
end if;
end process;
-- Registers with clock = sig_clock and reset = sig_reset active '1'
process(sig_clock, sig_reset)
begin
if sig_reset = '1' then
read_position <= "11111111111111111111111111111111";
else
if rising_edge(sig_clock) then
if sig_1496 = '1' then
read_position <= mux_519;
end if;
end if;
end if;
end process;
-- Remaining signal assignments
-- Those who are not assigned by component instantiation
sig_clock <= clock;
sig_reset <= reset;
augh_test_159 <= sig_1615;
augh_test_26 <= sig_1616;
augh_test_49 <= sig_1616;
augh_test_52 <= sig_1616;
augh_test_53 <= and_867;
augh_test_67 <= sig_1618;
augh_test_72 <= sig_1615;
augh_test_77 <= sig_1616;
augh_test_83 <= sig_1618;
augh_test_89 <= sig_1615;
augh_test_90 <= sig_1669;
augh_test_105 <= sig_1615;
augh_test_106 <= sig_1615;
augh_test_107 <= sig_1615;
augh_test_111 <= sig_1616;
augh_test_114 <= sig_1618;
augh_test_115 <= sig_1618;
augh_test_119 <= sig_1615;
augh_test_120 <= sig_1615;
augh_test_122 <= and_963;
augh_test_125 <= sig_1615;
augh_test_127 <= sig_1615;
augh_test_128 <= sig_1615;
augh_test_130 <= and_976;
augh_test_133 <= sig_1615;
augh_test_136 <= sig_1618;
augh_test_138 <= sig_1616;
augh_test_142 <= sig_1618;
augh_test_144 <= sig_1616;
augh_test_151 <= sig_1615;
augh_test_152 <= sig_1615;
augh_test_155 <= sig_1618;
augh_test_165 <= sig_1616;
augh_test_166 <= sig_1616;
augh_test_167 <= sig_1616;
augh_test_168 <= sig_1616;
sig_start <= start;
augh_test_171 <= sig_1615;
augh_test_178 <= sig_1615;
augh_test_179 <= sig_1615;
augh_test_182 <= sig_1616;
augh_test_183 <= sig_1615;
augh_test_184 <= sig_1615;
augh_test_186 <= sig_1616;
augh_test_187 <= sig_1615;
augh_test_188 <= sig_1615;
augh_test_189 <= sig_1615;
sig_1671 <= "000000000000000000000000" & pgetc_temp;
sig_1672 <= "000000000000000000000000000000" & p_jinfo_smp_fact;
sig_1673 <= yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g;
sig_1674 <= yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g;
sig_1675 <= yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b;
sig_1676 <= yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b;
sig_1677 <= "000000000000000000000000" & next_marker_c;
sig_1678 <= "000000000000000000000000" & pgetc_temp;
sig_1679 <= yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g;
sig_1680 <= "000000000000000000000000" & read_byte;
sig_1681 <= "000000000000000000000000" & next_marker_c;
sig_1682 <= "0000000000000000000000000000" & get_dqt_prec;
sig_1683 <= "000000000000000000000000" & read_markers_unread_marker;
sig_1684 <= "000000000000000000000000" & read_markers_unread_marker;
sig_1685 <= "0000000000000000000000000000000" & get_dht_is_ac;
sig_1686 <= "0000000000000000000000000000000" & get_dht_is_ac;
sig_1687 <= "0000" & decodehuffmcu_n;
sig_1688 <= sig_1612(23 downto 0) & sig_1667(7);
sig_1689 <= yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b;
sig_1690 <= "00000000000000000000000" & mux_313;
sig_1691 <= writeoneblock_indim1 & writeoneblock_outidx & writeoneblock_inidx(5 downto 0);
sig_1692 <= yuvtorgb_uidx & yuvtorgb_i(5 downto 0);
sig_1693 <= jpeg2bmp_main_i(1 downto 0) & jpeg2bmp_main_j(12 downto 0);
sig_1694 <= writeoneblock_outidx & sig_1610(12 downto 0);
sig_1695 <= decodehuffman_ac_tbl_no & decodehuffman_ac_l(5 downto 0);
sig_1696 <= huff_make_dhuff_tb_ac_tbl_no & huff_make_dhuff_tb_ac_l(5 downto 0);
sig_1697 <= decodehuffman_ac_tbl_no & decodehuffman_ac_l(5 downto 0);
sig_1698 <= huff_make_dhuff_tb_ac_tbl_no & huff_make_dhuff_tb_ac_l(5 downto 0);
sig_1699 <= decodehuffman_dc_tbl_no & decodehuffman_dc_l(5 downto 0);
sig_1700 <= huff_make_dhuff_tb_dc_tbl_no & huff_make_dhuff_tb_dc_l(5 downto 0);
sig_1701 <= decodehuffman_dc_tbl_no & decodehuffman_dc_l(5 downto 0);
sig_1702 <= huff_make_dhuff_tb_dc_tbl_no & huff_make_dhuff_tb_dc_l(5 downto 0);
sig_1703 <= get_dht_index & get_dht_i(8 downto 0);
sig_1704 <= get_dht_index & get_dht_i(5 downto 0);
sig_1705 <= get_dht_index & get_dht_i(8 downto 0);
sig_1706 <= get_dht_index & get_dht_i(5 downto 0);
sig_1707 <= sig_1610(1 downto 0) & sig_1645;
sig_1708 <= "0000000000000000" & get_dqt_tmp;
sig_1709 <= "000000000000000000000000" & read_markers_unread_marker;
sig_1710 <= "000000000000000000000000" & read_markers_unread_marker;
sig_1711 <= "000000000000000000000000" & read_markers_unread_marker;
sig_1712 <= "00000000000000000000000011" & mux_759;
sig_1713 <= "00000000000000000000000" & mux_761;
sig_1714 <= "0000000000000000000000000000000" & read_markers_sow_soi;
sig_1715 <= "0000000000000000000000000000" & get_dqt_prec;
sig_1716 <= "000000000000000000000000" & read_markers_unread_marker;
-- Remaining top-level ports assignments
-- Those who are not assigned by component instantiation
stdout_data <= mux_773;
stdin_rdy <= sig_1178;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity top is
port (
clock : in std_logic;
reset : in std_logic;
start : in std_logic;
stdout_rdy : out std_logic;
stdout_ack : in std_logic;
stdin_ack : in std_logic;
stdout_data : out std_logic_vector(7 downto 0);
stdin_data : in std_logic_vector(7 downto 0);
stdin_rdy : out std_logic
);
end top;
architecture augh of top is
-- Declaration of components
component cmp_869 is
port (
eq : out std_logic;
in1 : in std_logic_vector(7 downto 0);
in0 : in std_logic_vector(7 downto 0)
);
end component;
component cmp_978 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_979 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_847 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_855 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_852 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component mul_213 is
port (
output : out std_logic_vector(40 downto 0);
in_b : in std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0)
);
end component;
component mul_216 is
port (
output : out std_logic_vector(40 downto 0);
in_b : in std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0)
);
end component;
component mul_214 is
port (
output : out std_logic_vector(40 downto 0);
in_b : in std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0)
);
end component;
component cmp_846 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_848 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_849 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component p_jinfo_comps_info_id is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(1 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(1 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
wa0_en : in std_logic
);
end component;
component p_jinfo_comps_info_h_samp_factor is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(1 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(1 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
wa0_en : in std_logic
);
end component;
component p_jinfo_comps_info_quant_tbl_no is
port (
wa0_data : in std_logic_vector(1 downto 0);
wa0_addr : in std_logic_vector(1 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(1 downto 0);
ra0_data : out std_logic_vector(1 downto 0);
wa0_en : in std_logic
);
end component;
component p_jinfo_comps_info_dc_tbl_no is
port (
wa0_data : in std_logic;
wa0_addr : in std_logic_vector(1 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(1 downto 0);
ra0_data : out std_logic;
wa0_en : in std_logic
);
end component;
component p_jinfo_quant_tbl_quantval is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(7 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(7 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component p_jinfo_dc_xhuff_tbl_bits is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(6 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(6 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component p_jinfo_dc_xhuff_tbl_huffval is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(9 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(9 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component p_jinfo_ac_xhuff_tbl_bits is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(6 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(6 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component p_jinfo_ac_xhuff_tbl_huffval is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(9 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(9 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component p_jinfo_dc_dhuff_tbl_ml is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic;
clk : in std_logic;
ra0_addr : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component p_jinfo_dc_dhuff_tbl_maxcode is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(6 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(6 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component p_jinfo_dc_dhuff_tbl_mincode is
port (
wa0_data : in std_logic_vector(8 downto 0);
wa0_addr : in std_logic_vector(6 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(6 downto 0);
ra0_data : out std_logic_vector(8 downto 0);
wa0_en : in std_logic
);
end component;
component p_jinfo_dc_dhuff_tbl_valptr is
port (
wa0_data : in std_logic_vector(8 downto 0);
wa0_addr : in std_logic_vector(6 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(6 downto 0);
ra0_data : out std_logic_vector(8 downto 0);
wa0_en : in std_logic
);
end component;
component p_jinfo_ac_dhuff_tbl_ml is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic;
clk : in std_logic;
ra0_addr : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component p_jinfo_ac_dhuff_tbl_maxcode is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(6 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(6 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component p_jinfo_ac_dhuff_tbl_mincode is
port (
wa0_data : in std_logic_vector(8 downto 0);
wa0_addr : in std_logic_vector(6 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(6 downto 0);
ra0_data : out std_logic_vector(8 downto 0);
wa0_en : in std_logic
);
end component;
component p_jinfo_ac_dhuff_tbl_valptr is
port (
wa0_data : in std_logic_vector(8 downto 0);
wa0_addr : in std_logic_vector(6 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(6 downto 0);
ra0_data : out std_logic_vector(8 downto 0);
wa0_en : in std_logic
);
end component;
component outdata_comp_vpos is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(1 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(1 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component outdata_comp_hpos is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(1 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(1 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component outdata_comp_buf is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(14 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(14 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
wa0_en : in std_logic
);
end component;
component izigzag_index is
port (
clk : in std_logic;
ra0_addr : in std_logic_vector(5 downto 0);
ra0_data : out std_logic_vector(5 downto 0)
);
end component;
component jpegfilebuf is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(12 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(12 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
wa0_en : in std_logic
);
end component;
component huffbuff is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(7 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(7 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component idctbuff is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(8 downto 0);
clk : in std_logic;
ra2_data : out std_logic_vector(31 downto 0);
ra2_addr : in std_logic_vector(8 downto 0);
ra1_data : out std_logic_vector(31 downto 0);
ra1_addr : in std_logic_vector(8 downto 0);
ra0_addr : in std_logic_vector(8 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component quantbuff is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(5 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(5 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component extend_mask is
port (
clk : in std_logic;
ra0_addr : in std_logic_vector(4 downto 0);
ra0_data : out std_logic_vector(20 downto 0)
);
end component;
component bit_set_mask is
port (
clk : in std_logic;
ra0_addr : in std_logic_vector(4 downto 0);
ra0_data : out std_logic_vector(31 downto 0)
);
end component;
component lmask is
port (
clk : in std_logic;
ra0_addr : in std_logic_vector(4 downto 0);
ra0_data : out std_logic_vector(31 downto 0)
);
end component;
component huff_make_dhuff_tb_ac_huffsize is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(8 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(8 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component huff_make_dhuff_tb_ac_huffcode is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(8 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(8 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component huff_make_dhuff_tb_dc_huffsize is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(8 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(8 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component huff_make_dhuff_tb_dc_huffcode is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(8 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(8 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component rgb_buf is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(9 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(9 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
wa0_en : in std_logic
);
end component;
component zigzag_index is
port (
clk : in std_logic;
ra0_addr : in std_logic_vector(5 downto 0);
ra0_data : out std_logic_vector(5 downto 0)
);
end component;
component shr_212 is
port (
output : out std_logic_vector(31 downto 0);
input : in std_logic_vector(31 downto 0);
shift : in std_logic_vector(5 downto 0);
padding : in std_logic
);
end component;
component mul_209 is
port (
output : out std_logic_vector(40 downto 0);
in_b : in std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0)
);
end component;
component mul_210 is
port (
output : out std_logic_vector(40 downto 0);
in_b : in std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0)
);
end component;
component shl_211 is
port (
output : out std_logic_vector(31 downto 0);
input : in std_logic_vector(31 downto 0);
shift : in std_logic_vector(5 downto 0);
padding : in std_logic
);
end component;
component sub_206 is
port (
gt : out std_logic;
output : out std_logic_vector(40 downto 0);
sign : in std_logic;
in_b : in std_logic_vector(40 downto 0);
in_a : in std_logic_vector(40 downto 0)
);
end component;
component sub_207 is
port (
ge : out std_logic;
le : out std_logic;
output : out std_logic_vector(40 downto 0);
sign : in std_logic;
in_b : in std_logic_vector(40 downto 0);
in_a : in std_logic_vector(40 downto 0)
);
end component;
component sub_208 is
port (
ge : out std_logic;
output : out std_logic_vector(40 downto 0);
sign : in std_logic;
in_b : in std_logic_vector(40 downto 0);
in_a : in std_logic_vector(40 downto 0)
);
end component;
component sub_205 is
port (
gt : out std_logic;
ge : out std_logic;
lt : out std_logic;
le : out std_logic;
output : out std_logic_vector(40 downto 0);
sign : in std_logic;
in_b : in std_logic_vector(40 downto 0);
in_a : in std_logic_vector(40 downto 0)
);
end component;
component add_202 is
port (
output : out std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0)
);
end component;
component add_203 is
port (
output : out std_logic_vector(38 downto 0);
in_b : in std_logic_vector(38 downto 0);
in_a : in std_logic_vector(38 downto 0)
);
end component;
component add_204 is
port (
output : out std_logic_vector(24 downto 0);
in_b : in std_logic_vector(24 downto 0);
in_a : in std_logic_vector(24 downto 0)
);
end component;
component add_201 is
port (
output : out std_logic_vector(38 downto 0);
in_b : in std_logic_vector(38 downto 0);
in_a : in std_logic_vector(38 downto 0)
);
end component;
component add_200 is
port (
output : out std_logic_vector(38 downto 0);
in_b : in std_logic_vector(38 downto 0);
in_a : in std_logic_vector(38 downto 0)
);
end component;
component cmp_775 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_779 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_780 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_787 is
port (
eq : out std_logic;
in1 : in std_logic;
in0 : in std_logic
);
end component;
component cmp_788 is
port (
eq : out std_logic;
in1 : in std_logic_vector(2 downto 0);
in0 : in std_logic_vector(2 downto 0)
);
end component;
component cmp_790 is
port (
ne : out std_logic;
in1 : in std_logic_vector(3 downto 0);
in0 : in std_logic_vector(3 downto 0)
);
end component;
component cmp_792 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_793 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_794 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_791 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_804 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_800 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_799 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_865 is
port (
ne : out std_logic;
in1 : in std_logic_vector(2 downto 0);
in0 : in std_logic_vector(2 downto 0)
);
end component;
component cmp_882 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_885 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_887 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component mul_215 is
port (
output : out std_logic_vector(40 downto 0);
in_b : in std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0)
);
end component;
component cmp_850 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_851 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_861 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_871 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_873 is
port (
eq : out std_logic;
in1 : in std_logic_vector(7 downto 0);
in0 : in std_logic_vector(7 downto 0)
);
end component;
component cmp_879 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_880 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component sub_217 is
port (
ge : out std_logic;
output : out std_logic_vector(40 downto 0);
sign : in std_logic;
in_b : in std_logic_vector(40 downto 0);
in_a : in std_logic_vector(40 downto 0)
);
end component;
component cmp_863 is
port (
ne : out std_logic;
in1 : in std_logic_vector(2 downto 0);
in0 : in std_logic_vector(2 downto 0)
);
end component;
component cmp_868 is
port (
eq : out std_logic;
in1 : in std_logic_vector(23 downto 0);
in0 : in std_logic_vector(23 downto 0)
);
end component;
component cmp_877 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_878 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component sub_218 is
port (
le : out std_logic;
output : out std_logic_vector(40 downto 0);
sign : in std_logic;
in_b : in std_logic_vector(40 downto 0);
in_a : in std_logic_vector(40 downto 0)
);
end component;
component sub_220 is
port (
gt : out std_logic;
output : out std_logic_vector(40 downto 0);
sign : in std_logic;
in_b : in std_logic_vector(40 downto 0);
in_a : in std_logic_vector(40 downto 0)
);
end component;
component sub_221 is
port (
gt : out std_logic;
output : out std_logic_vector(40 downto 0);
sign : in std_logic;
in_b : in std_logic_vector(40 downto 0);
in_a : in std_logic_vector(40 downto 0)
);
end component;
component mul_222 is
port (
output : out std_logic_vector(40 downto 0);
in_b : in std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0)
);
end component;
component sub_219 is
port (
le : out std_logic;
output : out std_logic_vector(40 downto 0);
sign : in std_logic;
in_b : in std_logic_vector(40 downto 0);
in_a : in std_logic_vector(40 downto 0)
);
end component;
component cmp_962 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_975 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component fsm_224 is
port (
clock : in std_logic;
reset : in std_logic;
out40 : out std_logic;
in2 : in std_logic;
in11 : in std_logic;
out146 : out std_logic;
out148 : out std_logic;
out150 : out std_logic;
out152 : out std_logic;
in12 : in std_logic;
out153 : out std_logic;
out154 : out std_logic;
in13 : in std_logic;
out156 : out std_logic;
out157 : out std_logic;
out160 : out std_logic;
out162 : out std_logic;
out165 : out std_logic;
out170 : out std_logic;
out171 : out std_logic;
out173 : out std_logic;
out175 : out std_logic;
out177 : out std_logic;
out180 : out std_logic;
out184 : out std_logic;
in14 : in std_logic;
out186 : out std_logic;
out189 : out std_logic;
out191 : out std_logic;
out192 : out std_logic;
out193 : out std_logic;
out197 : out std_logic;
out199 : out std_logic;
out201 : out std_logic;
out202 : out std_logic;
out205 : out std_logic;
out207 : out std_logic;
out208 : out std_logic;
out209 : out std_logic;
out210 : out std_logic;
out212 : out std_logic;
out213 : out std_logic;
in15 : in std_logic;
out221 : out std_logic;
out222 : out std_logic;
out224 : out std_logic;
out225 : out std_logic;
out228 : out std_logic;
out229 : out std_logic;
out230 : out std_logic;
out231 : out std_logic;
out99 : out std_logic;
in6 : in std_logic;
out92 : out std_logic;
out232 : out std_logic;
in16 : in std_logic;
out234 : out std_logic;
out236 : out std_logic;
out239 : out std_logic;
out240 : out std_logic;
out241 : out std_logic;
out245 : out std_logic;
out246 : out std_logic;
out247 : out std_logic;
out251 : out std_logic;
out252 : out std_logic;
out253 : out std_logic;
out255 : out std_logic;
out256 : out std_logic;
out258 : out std_logic;
out259 : out std_logic;
in17 : in std_logic;
out263 : out std_logic;
out264 : out std_logic;
out266 : out std_logic;
in18 : in std_logic;
out267 : out std_logic;
out268 : out std_logic;
out270 : out std_logic;
out273 : out std_logic;
out275 : out std_logic;
out276 : out std_logic;
in19 : in std_logic;
out279 : out std_logic;
in20 : in std_logic;
out281 : out std_logic;
out282 : out std_logic;
in21 : in std_logic;
out283 : out std_logic;
out286 : out std_logic;
out289 : out std_logic;
out296 : out std_logic;
out297 : out std_logic;
out299 : out std_logic;
out300 : out std_logic;
out304 : out std_logic;
out305 : out std_logic;
in22 : in std_logic;
out306 : out std_logic;
out310 : out std_logic;
out311 : out std_logic;
out313 : out std_logic;
out314 : out std_logic;
in23 : in std_logic;
out316 : out std_logic;
out317 : out std_logic;
out320 : out std_logic;
out322 : out std_logic;
out324 : out std_logic;
out325 : out std_logic;
out326 : out std_logic;
out328 : out std_logic;
out332 : out std_logic;
out333 : out std_logic;
out334 : out std_logic;
out335 : out std_logic;
out338 : out std_logic;
out339 : out std_logic;
out341 : out std_logic;
out342 : out std_logic;
out344 : out std_logic;
out93 : out std_logic;
out98 : out std_logic;
out85 : out std_logic;
out87 : out std_logic;
out88 : out std_logic;
out80 : out std_logic;
out82 : out std_logic;
out83 : out std_logic;
out84 : out std_logic;
in5 : in std_logic;
out77 : out std_logic;
out78 : out std_logic;
out71 : out std_logic;
out72 : out std_logic;
in4 : in std_logic;
out65 : out std_logic;
out67 : out std_logic;
out60 : out std_logic;
out64 : out std_logic;
in3 : in std_logic;
out59 : out std_logic;
out53 : out std_logic;
out55 : out std_logic;
out49 : out std_logic;
out44 : out std_logic;
out104 : out std_logic;
out107 : out std_logic;
out111 : out std_logic;
out112 : out std_logic;
out114 : out std_logic;
in7 : in std_logic;
out117 : out std_logic;
out119 : out std_logic;
out122 : out std_logic;
in8 : in std_logic;
out128 : out std_logic;
in9 : in std_logic;
out129 : out std_logic;
out130 : out std_logic;
out133 : out std_logic;
out134 : out std_logic;
out136 : out std_logic;
out137 : out std_logic;
in10 : in std_logic;
out139 : out std_logic;
out143 : out std_logic;
out144 : out std_logic;
out32 : out std_logic;
out35 : out std_logic;
out27 : out std_logic;
out25 : out std_logic;
out26 : out std_logic;
in1 : in std_logic;
out15 : out std_logic;
out16 : out std_logic;
out11 : out std_logic;
out13 : out std_logic;
out14 : out std_logic;
out7 : out std_logic;
out1 : out std_logic;
out2 : out std_logic;
out3 : out std_logic;
out4 : out std_logic;
in0 : in std_logic;
in24 : in std_logic;
out346 : out std_logic;
out347 : out std_logic;
out348 : out std_logic;
out349 : out std_logic;
in25 : in std_logic;
out350 : out std_logic;
out351 : out std_logic;
out355 : out std_logic;
out356 : out std_logic;
out357 : out std_logic;
out358 : out std_logic;
out360 : out std_logic;
out362 : out std_logic;
out363 : out std_logic;
out364 : out std_logic;
out365 : out std_logic;
out366 : out std_logic;
out370 : out std_logic;
out371 : out std_logic;
out372 : out std_logic;
out373 : out std_logic;
out375 : out std_logic;
in26 : in std_logic;
out376 : out std_logic;
out378 : out std_logic;
out379 : out std_logic;
out381 : out std_logic;
out382 : out std_logic;
in27 : in std_logic;
out384 : out std_logic;
in28 : in std_logic;
out391 : out std_logic;
out395 : out std_logic;
out396 : out std_logic;
out401 : out std_logic;
out402 : out std_logic;
out403 : out std_logic;
out404 : out std_logic;
out405 : out std_logic;
out407 : out std_logic;
out408 : out std_logic;
out409 : out std_logic;
out410 : out std_logic;
in29 : in std_logic;
out412 : out std_logic;
out414 : out std_logic;
out415 : out std_logic;
out417 : out std_logic;
out418 : out std_logic;
out419 : out std_logic;
out420 : out std_logic;
out422 : out std_logic;
out424 : out std_logic;
out425 : out std_logic;
out426 : out std_logic;
in30 : in std_logic;
out428 : out std_logic;
out429 : out std_logic;
out432 : out std_logic;
out433 : out std_logic;
out434 : out std_logic;
out437 : out std_logic;
out440 : out std_logic;
out441 : out std_logic;
in31 : in std_logic;
out443 : out std_logic;
in32 : in std_logic;
out445 : out std_logic;
out447 : out std_logic;
out448 : out std_logic;
out450 : out std_logic;
in33 : in std_logic;
out453 : out std_logic;
out455 : out std_logic;
out458 : out std_logic;
in34 : in std_logic;
out462 : out std_logic;
out464 : out std_logic;
out467 : out std_logic;
out468 : out std_logic;
out472 : out std_logic;
in35 : in std_logic;
out478 : out std_logic;
out479 : out std_logic;
out480 : out std_logic;
out487 : out std_logic;
out488 : out std_logic;
in36 : in std_logic;
out491 : out std_logic;
out496 : out std_logic;
out497 : out std_logic;
out498 : out std_logic;
out500 : out std_logic;
out504 : out std_logic;
out505 : out std_logic;
in37 : in std_logic;
out506 : out std_logic;
out508 : out std_logic;
in38 : in std_logic;
out510 : out std_logic;
out513 : out std_logic;
out514 : out std_logic;
out515 : out std_logic;
out517 : out std_logic;
out519 : out std_logic;
in39 : in std_logic;
out523 : out std_logic;
out526 : out std_logic;
out527 : out std_logic;
out528 : out std_logic;
out530 : out std_logic;
out531 : out std_logic;
out533 : out std_logic;
out534 : out std_logic;
out537 : out std_logic;
out538 : out std_logic;
out549 : out std_logic;
out558 : out std_logic;
out559 : out std_logic;
out561 : out std_logic;
in40 : in std_logic;
out566 : out std_logic;
out567 : out std_logic;
out568 : out std_logic;
out569 : out std_logic;
out570 : out std_logic;
out572 : out std_logic;
out574 : out std_logic;
out575 : out std_logic;
out577 : out std_logic;
in41 : in std_logic;
out578 : out std_logic;
out581 : out std_logic;
out589 : out std_logic;
out590 : out std_logic;
out595 : out std_logic;
out597 : out std_logic;
out599 : out std_logic;
out601 : out std_logic;
out602 : out std_logic;
out607 : out std_logic;
out610 : out std_logic;
out612 : out std_logic;
in42 : in std_logic;
out614 : out std_logic;
out621 : out std_logic;
out628 : out std_logic;
out635 : out std_logic;
out636 : out std_logic;
out638 : out std_logic;
out640 : out std_logic;
out643 : out std_logic;
out646 : out std_logic;
out649 : out std_logic;
out651 : out std_logic;
out656 : out std_logic;
in43 : in std_logic;
out658 : out std_logic;
out659 : out std_logic;
out661 : out std_logic;
out663 : out std_logic;
out664 : out std_logic;
in44 : in std_logic;
out667 : out std_logic;
out668 : out std_logic;
out670 : out std_logic;
out672 : out std_logic;
out674 : out std_logic;
in45 : in std_logic;
out679 : out std_logic;
out681 : out std_logic;
out683 : out std_logic;
out686 : out std_logic;
out688 : out std_logic;
out690 : out std_logic;
out692 : out std_logic;
out694 : out std_logic;
out696 : out std_logic;
out697 : out std_logic;
out698 : out std_logic;
out699 : out std_logic;
out700 : out std_logic;
out703 : out std_logic;
out704 : out std_logic;
out706 : out std_logic;
out708 : out std_logic;
out710 : out std_logic;
out712 : out std_logic;
out715 : out std_logic;
out718 : out std_logic;
in46 : in std_logic;
out722 : out std_logic;
out724 : out std_logic;
out726 : out std_logic;
out728 : out std_logic;
out731 : out std_logic;
out733 : out std_logic;
out734 : out std_logic;
out737 : out std_logic;
out739 : out std_logic;
out740 : out std_logic;
out743 : out std_logic;
out745 : out std_logic;
out746 : out std_logic;
in47 : in std_logic;
out749 : out std_logic;
out753 : out std_logic;
out755 : out std_logic;
out759 : out std_logic;
in48 : in std_logic;
out762 : out std_logic;
out764 : out std_logic;
out765 : out std_logic;
out767 : out std_logic;
out768 : out std_logic;
in49 : in std_logic;
out772 : out std_logic;
in50 : in std_logic;
out775 : out std_logic;
out776 : out std_logic;
out778 : out std_logic;
out783 : out std_logic;
out784 : out std_logic;
out787 : out std_logic;
out791 : out std_logic;
in51 : in std_logic;
out794 : out std_logic;
out795 : out std_logic;
in52 : in std_logic;
out799 : out std_logic;
out802 : out std_logic;
out806 : out std_logic;
out809 : out std_logic;
out812 : out std_logic;
out815 : out std_logic;
out826 : out std_logic;
out828 : out std_logic;
in53 : in std_logic;
in54 : in std_logic;
out843 : out std_logic;
out848 : out std_logic;
out852 : out std_logic;
in55 : in std_logic;
out855 : out std_logic;
out858 : out std_logic;
in56 : in std_logic;
out860 : out std_logic;
out861 : out std_logic;
out863 : out std_logic;
out866 : out std_logic;
out872 : out std_logic;
in57 : in std_logic;
out874 : out std_logic;
out876 : out std_logic;
out879 : out std_logic;
out882 : out std_logic;
out886 : out std_logic;
out887 : out std_logic;
in58 : in std_logic;
out888 : out std_logic;
out892 : out std_logic;
out894 : out std_logic;
out895 : out std_logic;
out896 : out std_logic;
out901 : out std_logic;
out902 : out std_logic;
out903 : out std_logic;
out905 : out std_logic;
out907 : out std_logic;
out918 : out std_logic;
out920 : out std_logic;
out921 : out std_logic;
out923 : out std_logic;
out925 : out std_logic;
out928 : out std_logic;
out929 : out std_logic;
out931 : out std_logic;
out933 : out std_logic;
out936 : out std_logic;
out937 : out std_logic;
out938 : out std_logic;
out939 : out std_logic;
out942 : out std_logic;
out943 : out std_logic;
out944 : out std_logic;
out947 : out std_logic;
out948 : out std_logic;
out949 : out std_logic;
out951 : out std_logic;
in59 : in std_logic;
out952 : out std_logic;
out953 : out std_logic;
out955 : out std_logic;
out956 : out std_logic;
out957 : out std_logic;
out958 : out std_logic;
in60 : in std_logic;
in61 : in std_logic;
out962 : out std_logic;
out963 : out std_logic;
out972 : out std_logic;
out973 : out std_logic;
out974 : out std_logic;
in62 : in std_logic;
out978 : out std_logic;
out979 : out std_logic;
out981 : out std_logic;
out982 : out std_logic;
out985 : out std_logic;
out986 : out std_logic;
out989 : out std_logic;
in63 : in std_logic;
in64 : in std_logic;
in65 : in std_logic;
in66 : in std_logic;
in67 : in std_logic;
in68 : in std_logic;
in69 : in std_logic;
in70 : in std_logic;
in71 : in std_logic;
in72 : in std_logic;
in73 : in std_logic;
in74 : in std_logic;
in75 : in std_logic;
in76 : in std_logic;
in77 : in std_logic;
in78 : in std_logic;
out990 : out std_logic;
out991 : out std_logic;
out993 : out std_logic;
out994 : out std_logic;
out996 : out std_logic;
out997 : out std_logic;
out998 : out std_logic;
out999 : out std_logic;
out1000 : out std_logic;
out1002 : out std_logic;
out1003 : out std_logic;
out1005 : out std_logic;
out1006 : out std_logic;
out1007 : out std_logic;
out1009 : out std_logic;
out1011 : out std_logic;
out1012 : out std_logic;
out1013 : out std_logic;
out1014 : out std_logic;
out1015 : out std_logic;
out1016 : out std_logic;
out1018 : out std_logic;
out1019 : out std_logic;
out1021 : out std_logic;
out1022 : out std_logic;
out1024 : out std_logic;
out1026 : out std_logic;
out1027 : out std_logic;
out1029 : out std_logic;
out1030 : out std_logic;
out1032 : out std_logic;
out1033 : out std_logic;
out1035 : out std_logic;
out1036 : out std_logic;
out1037 : out std_logic;
out1057 : out std_logic;
out1068 : out std_logic;
out1069 : out std_logic;
out1070 : out std_logic;
out1072 : out std_logic;
out1073 : out std_logic;
out1075 : out std_logic;
out1078 : out std_logic;
out1080 : out std_logic;
out1082 : out std_logic;
out1083 : out std_logic;
out1084 : out std_logic;
out1085 : out std_logic;
out1088 : out std_logic;
out1089 : out std_logic;
out1091 : out std_logic;
out1092 : out std_logic;
out1094 : out std_logic;
out1096 : out std_logic;
out1098 : out std_logic;
out1101 : out std_logic;
out1104 : out std_logic;
out1107 : out std_logic;
out1109 : out std_logic;
out1111 : out std_logic;
out1114 : out std_logic;
out1119 : out std_logic;
out1121 : out std_logic;
out1125 : out std_logic;
out1126 : out std_logic;
out1128 : out std_logic;
out1131 : out std_logic;
out1134 : out std_logic;
out1137 : out std_logic;
out1139 : out std_logic;
out1141 : out std_logic;
out1145 : out std_logic;
out1146 : out std_logic;
out1147 : out std_logic;
out1150 : out std_logic;
out1151 : out std_logic;
out1152 : out std_logic;
out1155 : out std_logic;
out1158 : out std_logic;
out1160 : out std_logic;
out1164 : out std_logic;
out1166 : out std_logic;
out1169 : out std_logic;
out1171 : out std_logic;
out1174 : out std_logic;
out1175 : out std_logic;
out1176 : out std_logic;
out1180 : out std_logic;
out1181 : out std_logic;
out1182 : out std_logic;
out1185 : out std_logic;
out1186 : out std_logic;
out1187 : out std_logic;
out1190 : out std_logic;
out1213 : out std_logic;
out1215 : out std_logic;
out1217 : out std_logic;
out1220 : out std_logic;
out1221 : out std_logic;
out1223 : out std_logic;
out1228 : out std_logic;
out1229 : out std_logic;
out1231 : out std_logic;
out1235 : out std_logic;
out1236 : out std_logic;
out1240 : out std_logic;
out1243 : out std_logic;
out1250 : out std_logic;
out1252 : out std_logic;
out1253 : out std_logic;
out1258 : out std_logic;
out1262 : out std_logic;
out1266 : out std_logic;
out1269 : out std_logic;
out1275 : out std_logic;
out1278 : out std_logic;
out1279 : out std_logic;
out1284 : out std_logic;
out1286 : out std_logic;
out1287 : out std_logic;
out1289 : out std_logic;
out1290 : out std_logic;
out1292 : out std_logic;
out1293 : out std_logic;
out1295 : out std_logic;
out1298 : out std_logic;
out1301 : out std_logic;
out1302 : out std_logic;
out1303 : out std_logic;
out1308 : out std_logic;
out1309 : out std_logic;
out1311 : out std_logic;
out1318 : out std_logic;
out1319 : out std_logic;
out1320 : out std_logic;
out1323 : out std_logic;
out1324 : out std_logic;
out1326 : out std_logic;
out1327 : out std_logic;
out1329 : out std_logic;
out1337 : out std_logic;
out1339 : out std_logic;
out1340 : out std_logic;
out1341 : out std_logic;
out1344 : out std_logic;
out1346 : out std_logic;
out1349 : out std_logic;
out1353 : out std_logic;
out1356 : out std_logic;
out1362 : out std_logic;
out1363 : out std_logic;
out1364 : out std_logic;
out1365 : out std_logic;
out1366 : out std_logic;
out1368 : out std_logic;
out1370 : out std_logic;
out1375 : out std_logic;
out1378 : out std_logic;
out1381 : out std_logic;
out1383 : out std_logic;
out1387 : out std_logic
);
end component;
component muxb_784 is
port (
in_sel : in std_logic;
out_data : out std_logic_vector(31 downto 0);
in_data0 : in std_logic_vector(31 downto 0);
in_data1 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_964 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_972 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_973 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_974 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_985 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_971 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_977 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
-- Declaration of signals
signal sig_clock : std_logic;
signal sig_reset : std_logic;
signal augh_test_159 : std_logic;
signal augh_test_6 : std_logic;
signal augh_test_9 : std_logic;
signal augh_test_10 : std_logic;
signal augh_test_26 : std_logic;
signal augh_test_49 : std_logic;
signal augh_test_52 : std_logic;
signal augh_test_53 : std_logic;
signal augh_test_62 : std_logic;
signal augh_test_67 : std_logic;
signal augh_test_72 : std_logic;
signal augh_test_77 : std_logic;
signal augh_test_83 : std_logic;
signal augh_test_89 : std_logic;
signal augh_test_90 : std_logic;
signal augh_test_94 : std_logic;
signal augh_test_99 : std_logic;
signal augh_test_100 : std_logic;
signal augh_test_101 : std_logic;
signal augh_test_102 : std_logic;
signal augh_test_103 : std_logic;
signal augh_test_104 : std_logic;
signal augh_test_105 : std_logic;
signal augh_test_106 : std_logic;
signal augh_test_107 : std_logic;
signal augh_test_108 : std_logic;
signal augh_test_109 : std_logic;
signal augh_test_111 : std_logic;
signal augh_test_113 : std_logic;
signal augh_test_114 : std_logic;
signal augh_test_115 : std_logic;
signal augh_test_118 : std_logic;
signal augh_test_119 : std_logic;
signal augh_test_120 : std_logic;
signal augh_test_122 : std_logic;
signal augh_test_123 : std_logic;
signal augh_test_124 : std_logic;
signal augh_test_125 : std_logic;
signal augh_test_126 : std_logic;
signal augh_test_127 : std_logic;
signal augh_test_128 : std_logic;
signal augh_test_130 : std_logic;
signal augh_test_131 : std_logic;
signal augh_test_132 : std_logic;
signal augh_test_133 : std_logic;
signal augh_test_134 : std_logic;
signal augh_test_136 : std_logic;
signal augh_test_138 : std_logic;
signal augh_test_142 : std_logic;
signal augh_test_144 : std_logic;
signal augh_test_148 : std_logic;
signal augh_test_150 : std_logic;
signal augh_test_151 : std_logic;
signal augh_test_152 : std_logic;
signal augh_test_154 : std_logic;
signal augh_test_155 : std_logic;
signal augh_test_157 : std_logic;
signal augh_test_158 : std_logic;
signal augh_test_165 : std_logic;
signal augh_test_166 : std_logic;
signal augh_test_167 : std_logic;
signal augh_test_168 : std_logic;
signal sig_start : std_logic;
signal augh_test_171 : std_logic;
signal augh_test_178 : std_logic;
signal augh_test_179 : std_logic;
signal augh_test_180 : std_logic;
signal augh_test_182 : std_logic;
signal augh_test_183 : std_logic;
signal augh_test_184 : std_logic;
signal augh_test_186 : std_logic;
signal augh_test_187 : std_logic;
signal augh_test_188 : std_logic;
signal augh_test_189 : std_logic;
signal augh_test_194 : std_logic;
signal augh_test_196 : std_logic;
signal augh_test_197 : std_logic;
signal sig_990 : std_logic;
signal sig_991 : std_logic;
signal sig_992 : std_logic_vector(31 downto 0);
signal sig_993 : std_logic;
signal sig_994 : std_logic;
signal sig_995 : std_logic;
signal sig_996 : std_logic;
signal sig_997 : std_logic;
signal sig_998 : std_logic;
signal sig_999 : std_logic;
signal sig_1000 : std_logic;
signal sig_1001 : std_logic;
signal sig_1002 : std_logic;
signal sig_1003 : std_logic;
signal sig_1004 : std_logic;
signal sig_1005 : std_logic;
signal sig_1006 : std_logic;
signal sig_1007 : std_logic;
signal sig_1008 : std_logic;
signal sig_1009 : std_logic;
signal sig_1010 : std_logic;
signal sig_1011 : std_logic;
signal sig_1012 : std_logic;
signal sig_1013 : std_logic;
signal sig_1014 : std_logic;
signal sig_1015 : std_logic;
signal sig_1016 : std_logic;
signal sig_1017 : std_logic;
signal sig_1018 : std_logic;
signal sig_1019 : std_logic;
signal sig_1020 : std_logic;
signal sig_1021 : std_logic;
signal sig_1022 : std_logic;
signal sig_1023 : std_logic;
signal sig_1024 : std_logic;
signal sig_1025 : std_logic;
signal sig_1026 : std_logic;
signal sig_1027 : std_logic;
signal sig_1028 : std_logic;
signal sig_1029 : std_logic;
signal sig_1030 : std_logic;
signal sig_1031 : std_logic;
signal sig_1032 : std_logic;
signal sig_1033 : std_logic;
signal sig_1034 : std_logic;
signal sig_1035 : std_logic;
signal sig_1036 : std_logic;
signal sig_1037 : std_logic;
signal sig_1038 : std_logic;
signal sig_1039 : std_logic;
signal sig_1040 : std_logic;
signal sig_1041 : std_logic;
signal sig_1042 : std_logic;
signal sig_1043 : std_logic;
signal sig_1044 : std_logic;
signal sig_1045 : std_logic;
signal sig_1046 : std_logic;
signal sig_1047 : std_logic;
signal sig_1048 : std_logic;
signal sig_1049 : std_logic;
signal sig_1050 : std_logic;
signal sig_1051 : std_logic;
signal sig_1052 : std_logic;
signal sig_1053 : std_logic;
signal sig_1054 : std_logic;
signal sig_1055 : std_logic;
signal sig_1056 : std_logic;
signal sig_1057 : std_logic;
signal sig_1058 : std_logic;
signal sig_1059 : std_logic;
signal sig_1060 : std_logic;
signal sig_1061 : std_logic;
signal sig_1062 : std_logic;
signal sig_1063 : std_logic;
signal sig_1064 : std_logic;
signal sig_1065 : std_logic;
signal sig_1066 : std_logic;
signal sig_1067 : std_logic;
signal sig_1068 : std_logic;
signal sig_1069 : std_logic;
signal sig_1070 : std_logic;
signal sig_1071 : std_logic;
signal sig_1072 : std_logic;
signal sig_1073 : std_logic;
signal sig_1074 : std_logic;
signal sig_1075 : std_logic;
signal sig_1076 : std_logic;
signal sig_1077 : std_logic;
signal sig_1078 : std_logic;
signal sig_1079 : std_logic;
signal sig_1080 : std_logic;
signal sig_1081 : std_logic;
signal sig_1082 : std_logic;
signal sig_1083 : std_logic;
signal sig_1084 : std_logic;
signal sig_1085 : std_logic;
signal sig_1086 : std_logic;
signal sig_1087 : std_logic;
signal sig_1088 : std_logic;
signal sig_1089 : std_logic;
signal sig_1090 : std_logic;
signal sig_1091 : std_logic;
signal sig_1092 : std_logic;
signal sig_1093 : std_logic;
signal sig_1094 : std_logic;
signal sig_1095 : std_logic;
signal sig_1096 : std_logic;
signal sig_1097 : std_logic;
signal sig_1098 : std_logic;
signal sig_1099 : std_logic;
signal sig_1100 : std_logic;
signal sig_1101 : std_logic;
signal sig_1102 : std_logic;
signal sig_1103 : std_logic;
signal sig_1104 : std_logic;
signal sig_1105 : std_logic;
signal sig_1106 : std_logic;
signal sig_1107 : std_logic;
signal sig_1108 : std_logic;
signal sig_1109 : std_logic;
signal sig_1110 : std_logic;
signal sig_1111 : std_logic;
signal sig_1112 : std_logic;
signal sig_1113 : std_logic;
signal sig_1114 : std_logic;
signal sig_1115 : std_logic;
signal sig_1116 : std_logic;
signal sig_1117 : std_logic;
signal sig_1118 : std_logic;
signal sig_1119 : std_logic;
signal sig_1120 : std_logic;
signal sig_1121 : std_logic;
signal sig_1122 : std_logic;
signal sig_1123 : std_logic;
signal sig_1124 : std_logic;
signal sig_1125 : std_logic;
signal sig_1126 : std_logic;
signal sig_1127 : std_logic;
signal sig_1128 : std_logic;
signal sig_1129 : std_logic;
signal sig_1130 : std_logic;
signal sig_1131 : std_logic;
signal sig_1132 : std_logic;
signal sig_1133 : std_logic;
signal sig_1134 : std_logic;
signal sig_1135 : std_logic;
signal sig_1136 : std_logic;
signal sig_1137 : std_logic;
signal sig_1138 : std_logic;
signal sig_1139 : std_logic;
signal sig_1140 : std_logic;
signal sig_1141 : std_logic;
signal sig_1142 : std_logic;
signal sig_1143 : std_logic;
signal sig_1144 : std_logic;
signal sig_1145 : std_logic;
signal sig_1146 : std_logic;
signal sig_1147 : std_logic;
signal sig_1148 : std_logic;
signal sig_1149 : std_logic;
signal sig_1150 : std_logic;
signal sig_1151 : std_logic;
signal sig_1152 : std_logic;
signal sig_1153 : std_logic;
signal sig_1154 : std_logic;
signal sig_1155 : std_logic;
signal sig_1156 : std_logic;
signal sig_1157 : std_logic;
signal sig_1158 : std_logic;
signal sig_1159 : std_logic;
signal sig_1160 : std_logic;
signal sig_1161 : std_logic;
signal sig_1162 : std_logic;
signal sig_1163 : std_logic;
signal sig_1164 : std_logic;
signal sig_1165 : std_logic;
signal sig_1166 : std_logic;
signal sig_1167 : std_logic;
signal sig_1168 : std_logic;
signal sig_1169 : std_logic;
signal sig_1170 : std_logic;
signal sig_1171 : std_logic;
signal sig_1172 : std_logic;
signal sig_1173 : std_logic;
signal sig_1174 : std_logic;
signal sig_1175 : std_logic;
signal sig_1176 : std_logic;
signal sig_1177 : std_logic;
signal sig_1178 : std_logic;
signal sig_1179 : std_logic;
signal sig_1180 : std_logic;
signal sig_1181 : std_logic;
signal sig_1182 : std_logic;
signal sig_1183 : std_logic;
signal sig_1184 : std_logic;
signal sig_1185 : std_logic;
signal sig_1186 : std_logic;
signal sig_1187 : std_logic;
signal sig_1188 : std_logic;
signal sig_1189 : std_logic;
signal sig_1190 : std_logic;
signal sig_1191 : std_logic;
signal sig_1192 : std_logic;
signal sig_1193 : std_logic;
signal sig_1194 : std_logic;
signal sig_1195 : std_logic;
signal sig_1196 : std_logic;
signal sig_1197 : std_logic;
signal sig_1198 : std_logic;
signal sig_1199 : std_logic;
signal sig_1200 : std_logic;
signal sig_1201 : std_logic;
signal sig_1202 : std_logic;
signal sig_1203 : std_logic;
signal sig_1204 : std_logic;
signal sig_1205 : std_logic;
signal sig_1206 : std_logic;
signal sig_1207 : std_logic;
signal sig_1208 : std_logic;
signal sig_1209 : std_logic;
signal sig_1210 : std_logic;
signal sig_1211 : std_logic;
signal sig_1212 : std_logic;
signal sig_1213 : std_logic;
signal sig_1214 : std_logic;
signal sig_1215 : std_logic;
signal sig_1216 : std_logic;
signal sig_1217 : std_logic;
signal sig_1218 : std_logic;
signal sig_1219 : std_logic;
signal sig_1220 : std_logic;
signal sig_1221 : std_logic;
signal sig_1222 : std_logic;
signal sig_1223 : std_logic;
signal sig_1224 : std_logic;
signal sig_1225 : std_logic;
signal sig_1226 : std_logic;
signal sig_1227 : std_logic;
signal sig_1228 : std_logic;
signal sig_1229 : std_logic;
signal sig_1230 : std_logic;
signal sig_1231 : std_logic;
signal sig_1232 : std_logic;
signal sig_1233 : std_logic;
signal sig_1234 : std_logic;
signal sig_1235 : std_logic;
signal sig_1236 : std_logic;
signal sig_1237 : std_logic;
signal sig_1238 : std_logic;
signal sig_1239 : std_logic;
signal sig_1240 : std_logic;
signal sig_1241 : std_logic;
signal sig_1242 : std_logic;
signal sig_1243 : std_logic;
signal sig_1244 : std_logic;
signal sig_1245 : std_logic;
signal sig_1246 : std_logic;
signal sig_1247 : std_logic;
signal sig_1248 : std_logic;
signal sig_1249 : std_logic;
signal sig_1250 : std_logic;
signal sig_1251 : std_logic;
signal sig_1252 : std_logic;
signal sig_1253 : std_logic;
signal sig_1254 : std_logic;
signal sig_1255 : std_logic;
signal sig_1256 : std_logic;
signal sig_1257 : std_logic;
signal sig_1258 : std_logic;
signal sig_1259 : std_logic;
signal sig_1260 : std_logic;
signal sig_1261 : std_logic;
signal sig_1262 : std_logic;
signal sig_1263 : std_logic;
signal sig_1264 : std_logic;
signal sig_1265 : std_logic;
signal sig_1266 : std_logic;
signal sig_1267 : std_logic;
signal sig_1268 : std_logic;
signal sig_1269 : std_logic;
signal sig_1270 : std_logic;
signal sig_1271 : std_logic;
signal sig_1272 : std_logic;
signal sig_1273 : std_logic;
signal sig_1274 : std_logic;
signal sig_1275 : std_logic;
signal sig_1276 : std_logic;
signal sig_1277 : std_logic;
signal sig_1278 : std_logic;
signal sig_1279 : std_logic;
signal sig_1280 : std_logic;
signal sig_1281 : std_logic;
signal sig_1282 : std_logic;
signal sig_1283 : std_logic;
signal sig_1284 : std_logic;
signal sig_1285 : std_logic;
signal sig_1286 : std_logic;
signal sig_1287 : std_logic;
signal sig_1288 : std_logic;
signal sig_1289 : std_logic;
signal sig_1290 : std_logic;
signal sig_1291 : std_logic;
signal sig_1292 : std_logic;
signal sig_1293 : std_logic;
signal sig_1294 : std_logic;
signal sig_1295 : std_logic;
signal sig_1296 : std_logic;
signal sig_1297 : std_logic;
signal sig_1298 : std_logic;
signal sig_1299 : std_logic;
signal sig_1300 : std_logic;
signal sig_1301 : std_logic;
signal sig_1302 : std_logic;
signal sig_1303 : std_logic;
signal sig_1304 : std_logic;
signal sig_1305 : std_logic;
signal sig_1306 : std_logic;
signal sig_1307 : std_logic;
signal sig_1308 : std_logic;
signal sig_1309 : std_logic;
signal sig_1310 : std_logic;
signal sig_1311 : std_logic;
signal sig_1312 : std_logic;
signal sig_1313 : std_logic;
signal sig_1314 : std_logic;
signal sig_1315 : std_logic;
signal sig_1316 : std_logic;
signal sig_1317 : std_logic;
signal sig_1318 : std_logic;
signal sig_1319 : std_logic;
signal sig_1320 : std_logic;
signal sig_1321 : std_logic;
signal sig_1322 : std_logic;
signal sig_1323 : std_logic;
signal sig_1324 : std_logic;
signal sig_1325 : std_logic;
signal sig_1326 : std_logic;
signal sig_1327 : std_logic;
signal sig_1328 : std_logic;
signal sig_1329 : std_logic;
signal sig_1330 : std_logic;
signal sig_1331 : std_logic;
signal sig_1332 : std_logic;
signal sig_1333 : std_logic;
signal sig_1334 : std_logic;
signal sig_1335 : std_logic;
signal sig_1336 : std_logic;
signal sig_1337 : std_logic;
signal sig_1338 : std_logic;
signal sig_1339 : std_logic;
signal sig_1340 : std_logic;
signal sig_1341 : std_logic;
signal sig_1342 : std_logic;
signal sig_1343 : std_logic;
signal sig_1344 : std_logic;
signal sig_1345 : std_logic;
signal sig_1346 : std_logic;
signal sig_1347 : std_logic;
signal sig_1348 : std_logic;
signal sig_1349 : std_logic;
signal sig_1350 : std_logic;
signal sig_1351 : std_logic;
signal sig_1352 : std_logic;
signal sig_1353 : std_logic;
signal sig_1354 : std_logic;
signal sig_1355 : std_logic;
signal sig_1356 : std_logic;
signal sig_1357 : std_logic;
signal sig_1358 : std_logic;
signal sig_1359 : std_logic;
signal sig_1360 : std_logic;
signal sig_1361 : std_logic;
signal sig_1362 : std_logic;
signal sig_1363 : std_logic;
signal sig_1364 : std_logic;
signal sig_1365 : std_logic;
signal sig_1366 : std_logic;
signal sig_1367 : std_logic;
signal sig_1368 : std_logic;
signal sig_1369 : std_logic;
signal sig_1370 : std_logic;
signal sig_1371 : std_logic;
signal sig_1372 : std_logic;
signal sig_1373 : std_logic;
signal sig_1374 : std_logic;
signal sig_1375 : std_logic;
signal sig_1376 : std_logic;
signal sig_1377 : std_logic;
signal sig_1378 : std_logic;
signal sig_1379 : std_logic;
signal sig_1380 : std_logic;
signal sig_1381 : std_logic;
signal sig_1382 : std_logic;
signal sig_1383 : std_logic;
signal sig_1384 : std_logic;
signal sig_1385 : std_logic;
signal sig_1386 : std_logic;
signal sig_1387 : std_logic;
signal sig_1388 : std_logic;
signal sig_1389 : std_logic;
signal sig_1390 : std_logic;
signal sig_1391 : std_logic;
signal sig_1392 : std_logic;
signal sig_1393 : std_logic;
signal sig_1394 : std_logic;
signal sig_1395 : std_logic;
signal sig_1396 : std_logic;
signal sig_1397 : std_logic;
signal sig_1398 : std_logic;
signal sig_1399 : std_logic;
signal sig_1400 : std_logic;
signal sig_1401 : std_logic;
signal sig_1402 : std_logic;
signal sig_1403 : std_logic;
signal sig_1404 : std_logic;
signal sig_1405 : std_logic;
signal sig_1406 : std_logic;
signal sig_1407 : std_logic;
signal sig_1408 : std_logic;
signal sig_1409 : std_logic;
signal sig_1410 : std_logic;
signal sig_1411 : std_logic;
signal sig_1412 : std_logic;
signal sig_1413 : std_logic;
signal sig_1414 : std_logic;
signal sig_1415 : std_logic;
signal sig_1416 : std_logic;
signal sig_1417 : std_logic;
signal sig_1418 : std_logic;
signal sig_1419 : std_logic;
signal sig_1420 : std_logic;
signal sig_1421 : std_logic;
signal sig_1422 : std_logic;
signal sig_1423 : std_logic;
signal sig_1424 : std_logic;
signal sig_1425 : std_logic;
signal sig_1426 : std_logic;
signal sig_1427 : std_logic;
signal sig_1428 : std_logic;
signal sig_1429 : std_logic;
signal sig_1430 : std_logic;
signal sig_1431 : std_logic;
signal sig_1432 : std_logic;
signal sig_1433 : std_logic;
signal sig_1434 : std_logic;
signal sig_1435 : std_logic;
signal sig_1436 : std_logic;
signal sig_1437 : std_logic;
signal sig_1438 : std_logic;
signal sig_1439 : std_logic;
signal sig_1440 : std_logic;
signal sig_1441 : std_logic;
signal sig_1442 : std_logic;
signal sig_1443 : std_logic;
signal sig_1444 : std_logic;
signal sig_1445 : std_logic;
signal sig_1446 : std_logic;
signal sig_1447 : std_logic;
signal sig_1448 : std_logic;
signal sig_1449 : std_logic;
signal sig_1450 : std_logic;
signal sig_1451 : std_logic;
signal sig_1452 : std_logic;
signal sig_1453 : std_logic;
signal sig_1454 : std_logic;
signal sig_1455 : std_logic;
signal sig_1456 : std_logic;
signal sig_1457 : std_logic;
signal sig_1458 : std_logic;
signal sig_1459 : std_logic;
signal sig_1460 : std_logic;
signal sig_1461 : std_logic;
signal sig_1462 : std_logic;
signal sig_1463 : std_logic;
signal sig_1464 : std_logic;
signal sig_1465 : std_logic;
signal sig_1466 : std_logic;
signal sig_1467 : std_logic;
signal sig_1468 : std_logic;
signal sig_1469 : std_logic;
signal sig_1470 : std_logic;
signal sig_1471 : std_logic;
signal sig_1472 : std_logic;
signal sig_1473 : std_logic;
signal sig_1474 : std_logic;
signal sig_1475 : std_logic;
signal sig_1476 : std_logic;
signal sig_1477 : std_logic;
signal sig_1478 : std_logic;
signal sig_1479 : std_logic;
signal sig_1480 : std_logic;
signal sig_1481 : std_logic;
signal sig_1482 : std_logic;
signal sig_1483 : std_logic;
signal sig_1484 : std_logic;
signal sig_1485 : std_logic;
signal sig_1486 : std_logic;
signal sig_1487 : std_logic;
signal sig_1488 : std_logic;
signal sig_1489 : std_logic;
signal sig_1490 : std_logic;
signal sig_1491 : std_logic;
signal sig_1492 : std_logic;
signal sig_1493 : std_logic;
signal sig_1494 : std_logic;
signal sig_1495 : std_logic;
signal sig_1496 : std_logic;
signal sig_1497 : std_logic;
signal sig_1498 : std_logic;
signal sig_1499 : std_logic;
signal sig_1500 : std_logic;
signal sig_1501 : std_logic;
signal sig_1502 : std_logic;
signal sig_1503 : std_logic;
signal sig_1504 : std_logic;
signal sig_1505 : std_logic;
signal sig_1506 : std_logic;
signal sig_1507 : std_logic;
signal sig_1508 : std_logic;
signal sig_1509 : std_logic;
signal sig_1510 : std_logic;
signal sig_1511 : std_logic;
signal sig_1512 : std_logic;
signal sig_1513 : std_logic;
signal sig_1514 : std_logic;
signal sig_1515 : std_logic;
signal sig_1516 : std_logic;
signal sig_1517 : std_logic;
signal sig_1518 : std_logic;
signal sig_1519 : std_logic;
signal sig_1520 : std_logic;
signal sig_1521 : std_logic;
signal sig_1522 : std_logic;
signal sig_1523 : std_logic;
signal sig_1524 : std_logic;
signal sig_1525 : std_logic;
signal sig_1526 : std_logic;
signal sig_1527 : std_logic;
signal sig_1528 : std_logic;
signal sig_1529 : std_logic;
signal sig_1530 : std_logic;
signal sig_1531 : std_logic;
signal sig_1532 : std_logic;
signal sig_1533 : std_logic;
signal sig_1534 : std_logic;
signal sig_1535 : std_logic;
signal sig_1536 : std_logic;
signal sig_1537 : std_logic;
signal sig_1538 : std_logic;
signal sig_1539 : std_logic;
signal sig_1540 : std_logic;
signal sig_1541 : std_logic;
signal sig_1542 : std_logic;
signal sig_1543 : std_logic;
signal sig_1544 : std_logic;
signal sig_1545 : std_logic;
signal sig_1546 : std_logic;
signal sig_1547 : std_logic;
signal sig_1548 : std_logic;
signal sig_1549 : std_logic;
signal sig_1550 : std_logic;
signal sig_1551 : std_logic;
signal sig_1552 : std_logic;
signal sig_1553 : std_logic;
signal sig_1554 : std_logic;
signal sig_1555 : std_logic;
signal sig_1556 : std_logic;
signal sig_1557 : std_logic;
signal sig_1558 : std_logic;
signal sig_1559 : std_logic;
signal sig_1560 : std_logic;
signal sig_1561 : std_logic;
signal sig_1562 : std_logic;
signal sig_1563 : std_logic;
signal sig_1564 : std_logic;
signal sig_1565 : std_logic;
signal sig_1566 : std_logic;
signal sig_1567 : std_logic;
signal sig_1568 : std_logic;
signal sig_1569 : std_logic;
signal sig_1570 : std_logic;
signal sig_1571 : std_logic;
signal sig_1572 : std_logic;
signal sig_1573 : std_logic;
signal sig_1574 : std_logic;
signal sig_1575 : std_logic;
signal sig_1576 : std_logic;
signal sig_1577 : std_logic;
signal sig_1578 : std_logic;
signal sig_1579 : std_logic;
signal sig_1580 : std_logic;
signal sig_1581 : std_logic;
signal sig_1582 : std_logic;
signal sig_1583 : std_logic;
signal sig_1584 : std_logic;
signal sig_1585 : std_logic_vector(40 downto 0);
signal sig_1586 : std_logic;
signal sig_1587 : std_logic_vector(40 downto 0);
signal sig_1588 : std_logic_vector(40 downto 0);
signal sig_1589 : std_logic;
signal sig_1590 : std_logic_vector(40 downto 0);
signal sig_1591 : std_logic;
signal sig_1592 : std_logic_vector(40 downto 0);
signal sig_1593 : std_logic;
signal sig_1594 : std_logic;
signal sig_1595 : std_logic;
signal sig_1596 : std_logic_vector(40 downto 0);
signal sig_1597 : std_logic;
signal sig_1598 : std_logic;
signal sig_1599 : std_logic;
signal sig_1600 : std_logic_vector(40 downto 0);
signal sig_1601 : std_logic;
signal sig_1602 : std_logic;
signal sig_1603 : std_logic;
signal sig_1604 : std_logic;
signal sig_1605 : std_logic;
signal sig_1606 : std_logic;
signal sig_1607 : std_logic;
signal sig_1608 : std_logic;
signal sig_1609 : std_logic_vector(38 downto 0);
signal sig_1610 : std_logic_vector(38 downto 0);
signal sig_1611 : std_logic_vector(24 downto 0);
signal sig_1612 : std_logic_vector(38 downto 0);
signal sig_1613 : std_logic_vector(31 downto 0);
signal sig_1614 : std_logic_vector(40 downto 0);
signal sig_1615 : std_logic;
signal sig_1616 : std_logic;
signal sig_1617 : std_logic;
signal sig_1618 : std_logic;
signal sig_1619 : std_logic_vector(40 downto 0);
signal sig_1620 : std_logic;
signal sig_1621 : std_logic_vector(40 downto 0);
signal sig_1622 : std_logic;
signal sig_1623 : std_logic;
signal sig_1624 : std_logic_vector(40 downto 0);
signal sig_1625 : std_logic;
signal sig_1626 : std_logic_vector(31 downto 0);
signal sig_1627 : std_logic_vector(40 downto 0);
signal sig_1628 : std_logic_vector(40 downto 0);
signal sig_1629 : std_logic_vector(31 downto 0);
signal sig_1630 : std_logic_vector(5 downto 0);
signal sig_1631 : std_logic_vector(7 downto 0);
signal sig_1632 : std_logic_vector(31 downto 0);
signal sig_1633 : std_logic_vector(31 downto 0);
signal sig_1634 : std_logic_vector(31 downto 0);
signal sig_1635 : std_logic_vector(31 downto 0);
signal sig_1636 : std_logic_vector(31 downto 0);
signal sig_1637 : std_logic_vector(31 downto 0);
signal sig_1638 : std_logic_vector(20 downto 0);
signal sig_1639 : std_logic_vector(31 downto 0);
signal sig_1640 : std_logic_vector(31 downto 0);
signal sig_1641 : std_logic_vector(31 downto 0);
signal sig_1642 : std_logic_vector(31 downto 0);
signal sig_1643 : std_logic_vector(31 downto 0);
signal sig_1644 : std_logic_vector(7 downto 0);
signal sig_1645 : std_logic_vector(5 downto 0);
signal sig_1646 : std_logic_vector(7 downto 0);
signal sig_1647 : std_logic_vector(31 downto 0);
signal sig_1648 : std_logic_vector(31 downto 0);
signal sig_1649 : std_logic_vector(8 downto 0);
signal sig_1650 : std_logic_vector(8 downto 0);
signal sig_1651 : std_logic_vector(31 downto 0);
signal sig_1652 : std_logic_vector(31 downto 0);
signal sig_1653 : std_logic_vector(8 downto 0);
signal sig_1654 : std_logic_vector(8 downto 0);
signal sig_1655 : std_logic_vector(31 downto 0);
signal sig_1656 : std_logic_vector(31 downto 0);
signal sig_1657 : std_logic_vector(31 downto 0);
signal sig_1658 : std_logic_vector(31 downto 0);
signal sig_1659 : std_logic_vector(31 downto 0);
signal sig_1660 : std_logic_vector(31 downto 0);
signal sig_1661 : std_logic_vector(31 downto 0);
signal sig_1662 : std_logic;
signal sig_1663 : std_logic_vector(1 downto 0);
signal sig_1664 : std_logic_vector(7 downto 0);
signal sig_1665 : std_logic_vector(7 downto 0);
signal sig_1666 : std_logic_vector(40 downto 0);
signal sig_1667 : std_logic_vector(40 downto 0);
signal sig_1668 : std_logic_vector(40 downto 0);
signal sig_1669 : std_logic;
signal sig_1670 : std_logic;
signal sig_1671 : std_logic_vector(31 downto 0);
signal sig_1672 : std_logic_vector(31 downto 0);
signal sig_1673 : std_logic_vector(40 downto 0);
signal sig_1674 : std_logic_vector(40 downto 0);
signal sig_1675 : std_logic_vector(40 downto 0);
signal sig_1676 : std_logic_vector(40 downto 0);
signal sig_1677 : std_logic_vector(31 downto 0);
signal sig_1678 : std_logic_vector(31 downto 0);
signal sig_1679 : std_logic_vector(40 downto 0);
signal sig_1680 : std_logic_vector(31 downto 0);
signal sig_1681 : std_logic_vector(31 downto 0);
signal sig_1682 : std_logic_vector(31 downto 0);
signal sig_1683 : std_logic_vector(31 downto 0);
signal sig_1684 : std_logic_vector(31 downto 0);
signal sig_1685 : std_logic_vector(31 downto 0);
signal sig_1686 : std_logic_vector(31 downto 0);
signal sig_1687 : std_logic_vector(31 downto 0);
signal sig_1688 : std_logic_vector(24 downto 0);
signal sig_1689 : std_logic_vector(40 downto 0);
signal sig_1690 : std_logic_vector(31 downto 0);
signal sig_1691 : std_logic_vector(9 downto 0);
signal sig_1692 : std_logic_vector(8 downto 0);
signal sig_1693 : std_logic_vector(14 downto 0);
signal sig_1694 : std_logic_vector(14 downto 0);
signal sig_1695 : std_logic_vector(6 downto 0);
signal sig_1696 : std_logic_vector(6 downto 0);
signal sig_1697 : std_logic_vector(6 downto 0);
signal sig_1698 : std_logic_vector(6 downto 0);
signal sig_1699 : std_logic_vector(6 downto 0);
signal sig_1700 : std_logic_vector(6 downto 0);
signal sig_1701 : std_logic_vector(6 downto 0);
signal sig_1702 : std_logic_vector(6 downto 0);
signal sig_1703 : std_logic_vector(9 downto 0);
signal sig_1704 : std_logic_vector(6 downto 0);
signal sig_1705 : std_logic_vector(9 downto 0);
signal sig_1706 : std_logic_vector(6 downto 0);
signal sig_1707 : std_logic_vector(7 downto 0);
signal sig_1708 : std_logic_vector(31 downto 0);
signal sig_1709 : std_logic_vector(31 downto 0);
signal sig_1710 : std_logic_vector(31 downto 0);
signal sig_1711 : std_logic_vector(31 downto 0);
signal sig_1712 : std_logic_vector(31 downto 0);
signal sig_1713 : std_logic_vector(31 downto 0);
signal sig_1714 : std_logic_vector(31 downto 0);
signal sig_1715 : std_logic_vector(31 downto 0);
signal sig_1716 : std_logic_vector(31 downto 0);
-- Other inlined components
signal mux_967 : std_logic_vector(31 downto 0);
signal and_976 : std_logic;
signal and_982 : std_logic_vector(31 downto 0);
signal and_983 : std_logic_vector(27 downto 0);
signal and_984 : std_logic_vector(31 downto 0);
signal mux_689 : std_logic_vector(31 downto 0);
signal mux_690 : std_logic_vector(6 downto 0);
signal mux_691 : std_logic_vector(6 downto 0);
signal and_853 : std_logic_vector(31 downto 0);
signal izigzagmatrix_i : std_logic_vector(31 downto 0) := (others => '0');
signal mux_233 : std_logic_vector(31 downto 0);
signal izigzagmatrix_out_idx : std_logic_vector(31 downto 0) := (others => '0');
signal iquantize_qidx : std_logic_vector(1 downto 0) := (others => '0');
signal write8_u8 : std_logic_vector(7 downto 0) := (others => '0');
signal p_jinfo_image_height : std_logic_vector(15 downto 0) := (others => '0');
signal p_jinfo_image_width : std_logic_vector(15 downto 0) := (others => '0');
signal mux_671 : std_logic_vector(31 downto 0);
signal p_jinfo_num_components : std_logic_vector(7 downto 0) := (others => '0');
signal p_jinfo_smp_fact : std_logic_vector(1 downto 0) := (others => '0');
signal mux_665 : std_logic_vector(1 downto 0);
signal mux_663 : std_logic_vector(31 downto 0);
signal mux_664 : std_logic_vector(1 downto 0);
signal mux_659 : std_logic_vector(31 downto 0);
signal mux_660 : std_logic_vector(1 downto 0);
signal mux_661 : std_logic_vector(1 downto 0);
signal mux_652 : std_logic_vector(12 downto 0);
signal mux_648 : std_logic_vector(31 downto 0);
signal mux_633 : std_logic_vector(31 downto 0);
signal mux_622 : std_logic_vector(31 downto 0);
signal mux_614 : std_logic_vector(31 downto 0);
signal mux_616 : std_logic_vector(31 downto 0);
signal p_jinfo_mcuwidth : std_logic_vector(31 downto 0) := (others => '0');
signal mux_602 : std_logic_vector(31 downto 0);
signal p_jinfo_mcuheight : std_logic_vector(31 downto 0) := (others => '0');
signal mux_600 : std_logic_vector(31 downto 0);
signal p_jinfo_nummcu : std_logic_vector(31 downto 0) := (others => '0');
signal i_jinfo_jpeg_data : std_logic_vector(31 downto 0) := (others => '0');
signal mux_593 : std_logic_vector(31 downto 0);
signal curhuffreadbuf_idx : std_logic_vector(31 downto 0) := (others => '0');
signal mux_587 : std_logic_vector(31 downto 0);
signal outdata_image_width : std_logic_vector(7 downto 0) := (others => '0');
signal mux_585 : std_logic_vector(15 downto 0);
signal outdata_image_height : std_logic_vector(7 downto 0) := (others => '0');
signal mux_580 : std_logic_vector(7 downto 0);
signal mux_569 : std_logic_vector(7 downto 0);
signal mux_567 : std_logic_vector(31 downto 0);
signal mux_568 : std_logic_vector(7 downto 0);
signal mux_563 : std_logic_vector(8 downto 0);
signal mux_565 : std_logic_vector(8 downto 0);
signal mux_561 : std_logic_vector(31 downto 0);
signal mux_562 : std_logic_vector(8 downto 0);
signal mux_557 : std_logic_vector(31 downto 0);
signal mux_558 : std_logic_vector(5 downto 0);
signal mux_559 : std_logic_vector(5 downto 0);
signal mux_555 : std_logic_vector(31 downto 0);
signal mux_551 : std_logic_vector(31 downto 0);
signal mux_553 : std_logic_vector(31 downto 0);
signal mux_549 : std_logic_vector(31 downto 0);
signal mux_545 : std_logic_vector(31 downto 0);
signal mux_547 : std_logic_vector(31 downto 0);
signal mux_543 : std_logic_vector(31 downto 0);
signal mux_731 : std_logic_vector(7 downto 0);
signal mux_727 : std_logic_vector(6 downto 0);
signal mux_723 : std_logic_vector(9 downto 0);
signal mux_719 : std_logic_vector(6 downto 0);
signal mux_539 : std_logic_vector(31 downto 0);
signal mux_541 : std_logic_vector(31 downto 0);
signal mux_537 : std_logic_vector(31 downto 0);
signal mux_533 : std_logic_vector(31 downto 0);
signal mux_535 : std_logic_vector(31 downto 0);
signal mux_715 : std_logic_vector(9 downto 0);
signal mux_711 : std_logic;
signal mux_705 : std_logic_vector(31 downto 0);
signal mux_706 : std_logic_vector(6 downto 0);
signal mux_707 : std_logic_vector(6 downto 0);
signal mux_531 : std_logic_vector(31 downto 0);
signal mux_529 : std_logic_vector(31 downto 0);
signal mux_695 : std_logic;
signal mux_524 : std_logic_vector(4 downto 0);
signal mux_521 : std_logic_vector(31 downto 0);
signal readbuf_idx : std_logic_vector(31 downto 0) := (others => '0');
signal read_byte : std_logic_vector(7 downto 0) := (others => '0');
signal read_word : std_logic_vector(15 downto 0) := (others => '0');
signal read_word_c : std_logic_vector(7 downto 0) := (others => '0');
signal mux_519 : std_logic_vector(31 downto 0);
signal mux_517 : std_logic_vector(7 downto 0);
signal next_marker : std_logic_vector(7 downto 0) := (others => '0');
signal next_marker_c : std_logic_vector(7 downto 0) := (others => '0');
signal get_sof_ci : std_logic_vector(31 downto 0) := (others => '0');
signal mux_507 : std_logic_vector(31 downto 0);
signal mux_505 : std_logic_vector(31 downto 0);
signal get_sof_i_comp_info_id : std_logic_vector(1 downto 0) := (others => '0');
signal mux_501 : std_logic_vector(31 downto 0);
signal get_sof_i_comp_info_h_samp_factor : std_logic_vector(1 downto 0) := (others => '0');
signal get_sof_i_comp_info_quant_tbl_no : std_logic_vector(1 downto 0) := (others => '0');
signal mux_492 : std_logic_vector(31 downto 0);
signal mux_488 : std_logic_vector(31 downto 0);
signal mux_490 : std_logic_vector(31 downto 0);
signal get_sos_num_comp : std_logic_vector(7 downto 0) := (others => '0');
signal mux_486 : std_logic_vector(31 downto 0);
signal get_sos_i : std_logic_vector(31 downto 0) := (others => '0');
signal mux_482 : std_logic_vector(31 downto 0);
signal mux_484 : std_logic_vector(31 downto 0);
signal get_sos_c : std_logic := '0';
signal mux_480 : std_logic_vector(31 downto 0);
signal get_sos_cc : std_logic_vector(7 downto 0) := (others => '0');
signal mux_476 : std_logic_vector(31 downto 0);
signal mux_478 : std_logic_vector(8 downto 0);
signal get_sos_ci : std_logic_vector(31 downto 0) := (others => '0');
signal get_sos_j : std_logic_vector(31 downto 0) := (others => '0');
signal get_sos_i_comp_info_dc_tbl_no : std_logic_vector(1 downto 0) := (others => '0');
signal get_dht_length : std_logic_vector(31 downto 0) := (others => '0');
signal get_dht_index : std_logic := '0';
signal mux_459 : std_logic_vector(31 downto 0);
signal get_dht_i : std_logic_vector(31 downto 0) := (others => '0');
signal mux_455 : std_logic_vector(31 downto 0);
signal mux_457 : std_logic_vector(31 downto 0);
signal get_dht_count : std_logic_vector(31 downto 0) := (others => '0');
signal mux_453 : std_logic_vector(31 downto 0);
signal mux_449 : std_logic_vector(31 downto 0);
signal mux_451 : std_logic_vector(31 downto 0);
signal get_dht_is_ac : std_logic := '0';
signal get_dqt_length : std_logic_vector(31 downto 0) := (others => '0');
signal mux_447 : std_logic_vector(31 downto 0);
signal get_dqt_prec : std_logic_vector(3 downto 0) := (others => '0');
signal mux_443 : std_logic_vector(31 downto 0);
signal mux_445 : std_logic_vector(8 downto 0);
signal get_dqt_num : std_logic_vector(1 downto 0) := (others => '0');
signal get_dqt_i : std_logic_vector(31 downto 0) := (others => '0');
signal get_dqt_tmp : std_logic_vector(15 downto 0) := (others => '0');
signal read_markers_unread_marker : std_logic_vector(7 downto 0) := (others => '0');
signal read_markers_sow_soi : std_logic := '0';
signal mux_430 : std_logic_vector(31 downto 0);
signal mux_422 : std_logic_vector(31 downto 0);
signal mux_424 : std_logic_vector(31 downto 0);
signal chenidct_i : std_logic_vector(31 downto 0) := (others => '0');
signal mux_416 : std_logic_vector(31 downto 0);
signal chenidct_aidx : std_logic_vector(31 downto 0) := (others => '0');
signal chenidct_a0 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_410 : std_logic_vector(31 downto 0);
signal chenidct_a1 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_408 : std_logic_vector(31 downto 0);
signal chenidct_a2 : std_logic_vector(31 downto 0) := (others => '0');
signal chenidct_a3 : std_logic_vector(31 downto 0) := (others => '0');
signal chenidct_b0 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_398 : std_logic_vector(31 downto 0);
signal mux_400 : std_logic_vector(31 downto 0);
signal chenidct_b1 : std_logic_vector(31 downto 0) := (others => '0');
signal chenidct_b2 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_392 : std_logic_vector(31 downto 0);
signal mux_394 : std_logic_vector(31 downto 0);
signal chenidct_b3 : std_logic_vector(31 downto 0) := (others => '0');
signal chenidct_c0 : std_logic_vector(31 downto 0) := (others => '0');
signal chenidct_c1 : std_logic_vector(31 downto 0) := (others => '0');
signal chenidct_c2 : std_logic_vector(31 downto 0) := (others => '0');
signal chenidct_c3 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_378 : std_logic_vector(7 downto 0);
signal mux_379 : std_logic_vector(9 downto 0);
signal mux_375 : std_logic_vector(1 downto 0);
signal mux_373 : std_logic_vector(1 downto 0);
signal current_read_byte : std_logic_vector(31 downto 0) := (others => '0');
signal mux_365 : std_logic_vector(31 downto 0);
signal mux_367 : std_logic_vector(31 downto 0);
signal read_position : std_logic_vector(31 downto 0) := "11111111111111111111111111111111";
signal pgetc : std_logic_vector(7 downto 0) := (others => '0');
signal pgetc_temp : std_logic_vector(7 downto 0) := (others => '0');
signal buf_getb : std_logic := '0';
signal buf_getv : std_logic_vector(31 downto 0) := (others => '0');
signal buf_getv_n : std_logic_vector(31 downto 0) := (others => '0');
signal mux_363 : std_logic_vector(31 downto 0);
signal buf_getv_p : std_logic_vector(31 downto 0) := (others => '0');
signal mux_359 : std_logic_vector(31 downto 0);
signal mux_361 : std_logic_vector(31 downto 0);
signal buf_getv_rv : std_logic_vector(31 downto 0) := (others => '0');
signal huff_make_dhuff_tb_ac : std_logic_vector(31 downto 0) := (others => '0');
signal huff_make_dhuff_tb_ac_tbl_no : std_logic := '0';
signal huff_make_dhuff_tb_ac_p_dhtbl_ml : std_logic_vector(31 downto 0) := (others => '0');
signal huff_make_dhuff_tb_ac_i_c0 : std_logic_vector(31 downto 0) := (others => '0');
signal huff_make_dhuff_tb_ac_j : std_logic_vector(31 downto 0) := (others => '0');
signal mux_347 : std_logic_vector(31 downto 0);
signal huff_make_dhuff_tb_ac_p : std_logic_vector(31 downto 0) := (others => '0');
signal mux_345 : std_logic_vector(31 downto 0);
signal huff_make_dhuff_tb_ac_code : std_logic_vector(31 downto 0) := (others => '0');
signal mux_341 : std_logic_vector(2 downto 0);
signal mux_343 : std_logic_vector(1 downto 0);
signal huff_make_dhuff_tb_ac_size : std_logic_vector(31 downto 0) := (others => '0');
signal mux_339 : std_logic_vector(2 downto 0);
signal huff_make_dhuff_tb_ac_l : std_logic_vector(31 downto 0) := (others => '0');
signal mux_335 : std_logic_vector(31 downto 0);
signal mux_337 : std_logic_vector(2 downto 0);
signal mux_333 : std_logic_vector(31 downto 0);
signal mux_331 : std_logic_vector(31 downto 0);
signal huff_make_dhuff_tb_dc : std_logic_vector(31 downto 0) := (others => '0');
signal huff_make_dhuff_tb_dc_tbl_no : std_logic := '0';
signal huff_make_dhuff_tb_dc_p_dhtbl_ml : std_logic_vector(31 downto 0) := (others => '0');
signal mux_323 : std_logic_vector(5 downto 0);
signal huff_make_dhuff_tb_dc_i_c0 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_320 : std_logic_vector(31 downto 0);
signal mux_322 : std_logic_vector(31 downto 0);
signal huff_make_dhuff_tb_dc_j : std_logic_vector(31 downto 0) := (others => '0');
signal mux_317 : std_logic_vector(1 downto 0);
signal huff_make_dhuff_tb_dc_p : std_logic_vector(31 downto 0) := (others => '0');
signal mux_314 : std_logic_vector(31 downto 0);
signal mux_315 : std_logic_vector(31 downto 0);
signal mux_316 : std_logic_vector(31 downto 0);
signal huff_make_dhuff_tb_dc_code : std_logic_vector(31 downto 0) := (others => '0');
signal mux_313 : std_logic_vector(8 downto 0);
signal huff_make_dhuff_tb_dc_size : std_logic_vector(31 downto 0) := (others => '0');
signal mux_308 : std_logic_vector(2 downto 0);
signal huff_make_dhuff_tb_dc_l : std_logic_vector(31 downto 0) := (others => '0');
signal mux_306 : std_logic_vector(40 downto 0);
signal mux_307 : std_logic_vector(40 downto 0);
signal mux_302 : std_logic_vector(40 downto 0);
signal mux_303 : std_logic_vector(40 downto 0);
signal decodehuffman_ac : std_logic_vector(31 downto 0) := (others => '0');
signal decodehuffman_ac_tbl_no : std_logic := '0';
signal mux_294 : std_logic_vector(1 downto 0);
signal decodehuffman_ac_dhuff_ml : std_logic_vector(5 downto 0) := (others => '0');
signal mux_290 : std_logic_vector(40 downto 0);
signal mux_291 : std_logic_vector(40 downto 0);
signal mux_292 : std_logic_vector(31 downto 0);
signal decodehuffman_ac_code : std_logic_vector(31 downto 0) := (others => '0');
signal decodehuffman_ac_l : std_logic_vector(31 downto 0) := (others => '0');
signal mux_286 : std_logic_vector(31 downto 0);
signal decodehuffman_ac_p : std_logic_vector(8 downto 0) := (others => '0');
signal decodehuffman_dc : std_logic_vector(31 downto 0) := (others => '0');
signal decodehuffman_dc_tbl_no : std_logic := '0';
signal decodehuffman_dc_dhuff_ml : std_logic_vector(5 downto 0) := (others => '0');
signal mux_275 : std_logic_vector(31 downto 0);
signal decodehuffman_dc_code : std_logic_vector(31 downto 0) := (others => '0');
signal mux_272 : std_logic_vector(38 downto 0);
signal mux_274 : std_logic_vector(31 downto 0);
signal decodehuffman_dc_l : std_logic_vector(31 downto 0) := (others => '0');
signal mux_271 : std_logic_vector(38 downto 0);
signal decodehuffman_dc_p : std_logic_vector(8 downto 0) := (others => '0');
signal decodehuffmcu_bufdim1 : std_logic_vector(1 downto 0) := (others => '0');
signal mux_266 : std_logic_vector(38 downto 0);
signal mux_265 : std_logic_vector(38 downto 0);
signal decodehuffmcu_s : std_logic_vector(31 downto 0) := (others => '0');
signal mux_260 : std_logic_vector(38 downto 0);
signal mux_261 : std_logic_vector(38 downto 0);
signal mux_262 : std_logic_vector(31 downto 0);
signal decodehuffmcu_diff : std_logic_vector(31 downto 0) := (others => '0');
signal mux_257 : std_logic_vector(31 downto 0);
signal decodehuffmcu_tbl_no : std_logic := '0';
signal decodehuffmcu_i : std_logic_vector(31 downto 0) := (others => '0');
signal decodehuffmcu_k : std_logic_vector(31 downto 0) := (others => '0');
signal decodehuffmcu_n : std_logic_vector(27 downto 0) := (others => '0');
signal writeoneblock_outidx : std_logic_vector(1 downto 0) := (others => '0');
signal writeoneblock_indim1 : std_logic_vector(1 downto 0) := (others => '0');
signal writeoneblock_width : std_logic_vector(31 downto 0) := (others => '0');
signal writeoneblock_height : std_logic_vector(31 downto 0) := (others => '0');
signal writeoneblock_voffs : std_logic_vector(31 downto 0) := (others => '0');
signal writeoneblock_hoffs : std_logic_vector(31 downto 0) := (others => '0');
signal writeoneblock_i : std_logic_vector(31 downto 0) := (others => '0');
signal writeoneblock_e : std_logic_vector(31 downto 0) := (others => '0');
signal writeoneblock_inidx : std_logic_vector(31 downto 0) := (others => '0');
signal writeoneblock_diff : std_logic_vector(12 downto 0) := (others => '0');
signal writeblock_i : std_logic_vector(1 downto 0) := (others => '0');
signal write4blocks_i : std_logic_vector(1 downto 0) := (others => '0');
signal write4blocks_voffs : std_logic_vector(31 downto 0) := (others => '0');
signal write4blocks_hoffs : std_logic_vector(31 downto 0) := (others => '0');
signal yuvtorgb_p : std_logic_vector(1 downto 0) := (others => '0');
signal yuvtorgb_yidx : std_logic_vector(2 downto 0) := (others => '0');
signal yuvtorgb_uidx : std_logic_vector(2 downto 0) := (others => '0');
signal yuvtorgb_vidx : std_logic_vector(2 downto 0) := (others => '0');
signal yuvtorgb_r : std_logic_vector(31 downto 0) := (others => '0');
signal yuvtorgb_g : std_logic_vector(31 downto 0) := (others => '0');
signal yuvtorgb_b : std_logic_vector(31 downto 0) := (others => '0');
signal yuvtorgb_y : std_logic_vector(23 downto 0) := (others => '0');
signal yuvtorgb_u : std_logic_vector(30 downto 0) := (others => '0');
signal yuvtorgb_v : std_logic_vector(31 downto 0) := (others => '0');
signal yuvtorgb_i : std_logic_vector(31 downto 0) := (others => '0');
signal decode_block_comp_no : std_logic_vector(1 downto 0) := (others => '0');
signal decode_block_out_buf_idx : std_logic_vector(2 downto 0) := (others => '0');
signal decode_block_in_buf_idx : std_logic_vector(1 downto 0) := (others => '0');
signal decode_start_i : std_logic_vector(31 downto 0) := (others => '0');
signal decode_start_currentmcu : std_logic_vector(31 downto 0) := (others => '0');
signal nand_786 : std_logic;
signal or_845 : std_logic_vector(31 downto 0);
signal or_854 : std_logic_vector(31 downto 0);
signal or_866 : std_logic_vector(31 downto 0);
signal jpeg2bmp_main_i : std_logic_vector(31 downto 0) := (others => '0');
signal jpeg2bmp_main_j : std_logic_vector(31 downto 0) := (others => '0');
signal read8_ret0_195 : std_logic_vector(7 downto 0) := (others => '0');
signal and_785 : std_logic;
signal and_801 : std_logic_vector(31 downto 0);
signal mux_761 : std_logic_vector(8 downto 0);
signal mux_782 : std_logic_vector(31 downto 0);
signal or_802 : std_logic_vector(23 downto 0);
signal and_803 : std_logic_vector(31 downto 0);
signal mux_822 : std_logic_vector(31 downto 0);
signal mux_823 : std_logic_vector(31 downto 0);
signal mux_776 : std_logic_vector(31 downto 0);
signal mux_820 : std_logic_vector(31 downto 0);
signal mux_824 : std_logic_vector(31 downto 0);
signal mux_825 : std_logic_vector(31 downto 0);
signal mux_760 : std_logic_vector(31 downto 0);
signal and_789 : std_logic;
signal mux_759 : std_logic_vector(5 downto 0);
signal mux_768 : std_logic_vector(31 downto 0);
signal mux_757 : std_logic_vector(7 downto 0);
signal mux_773 : std_logic_vector(7 downto 0);
signal mux_762 : std_logic_vector(31 downto 0);
signal mux_766 : std_logic_vector(31 downto 0);
signal mux_781 : std_logic_vector(31 downto 0);
signal mux_797 : std_logic_vector(31 downto 0);
signal mux_821 : std_logic_vector(31 downto 0);
signal mux_826 : std_logic_vector(31 downto 0);
signal mux_778 : std_logic_vector(31 downto 0);
signal mux_827 : std_logic_vector(31 downto 0);
signal mux_815 : std_logic_vector(31 downto 0);
signal mux_798 : std_logic_vector(31 downto 0);
signal mux_816 : std_logic_vector(31 downto 0);
signal mux_817 : std_logic_vector(31 downto 0);
signal mux_777 : std_logic_vector(31 downto 0);
signal mux_819 : std_logic_vector(31 downto 0);
signal mux_783 : std_logic_vector(31 downto 0);
signal mux_795 : std_logic_vector(31 downto 0);
signal mux_796 : std_logic_vector(31 downto 0);
signal mux_805 : std_logic_vector(31 downto 0);
signal mux_806 : std_logic_vector(31 downto 0);
signal mux_807 : std_logic_vector(31 downto 0);
signal mux_808 : std_logic_vector(31 downto 0);
signal mux_809 : std_logic_vector(31 downto 0);
signal mux_810 : std_logic_vector(31 downto 0);
signal mux_811 : std_logic_vector(31 downto 0);
signal mux_812 : std_logic_vector(31 downto 0);
signal mux_813 : std_logic_vector(31 downto 0);
signal mux_814 : std_logic_vector(31 downto 0);
signal mux_818 : std_logic_vector(31 downto 0);
signal mux_828 : std_logic_vector(31 downto 0);
signal mux_829 : std_logic_vector(31 downto 0);
signal mux_830 : std_logic_vector(31 downto 0);
signal mux_831 : std_logic_vector(31 downto 0);
signal mux_832 : std_logic_vector(31 downto 0);
signal mux_836 : std_logic_vector(31 downto 0);
signal mux_837 : std_logic_vector(31 downto 0);
signal mux_839 : std_logic_vector(31 downto 0);
signal mux_840 : std_logic_vector(31 downto 0);
signal mux_841 : std_logic_vector(31 downto 0);
signal mux_842 : std_logic_vector(31 downto 0);
signal mux_843 : std_logic_vector(31 downto 0);
signal mux_856 : std_logic_vector(31 downto 0);
signal and_864 : std_logic;
signal mux_870 : std_logic_vector(31 downto 0);
signal mux_872 : std_logic_vector(1 downto 0);
signal mux_875 : std_logic_vector(31 downto 0);
signal mux_891 : std_logic_vector(31 downto 0);
signal mux_892 : std_logic_vector(31 downto 0);
signal mux_893 : std_logic_vector(31 downto 0);
signal mux_894 : std_logic_vector(31 downto 0);
signal mux_895 : std_logic_vector(31 downto 0);
signal mux_896 : std_logic_vector(31 downto 0);
signal mux_897 : std_logic_vector(31 downto 0);
signal mux_898 : std_logic_vector(31 downto 0);
signal mux_899 : std_logic_vector(31 downto 0);
signal mux_900 : std_logic_vector(31 downto 0);
signal mux_901 : std_logic_vector(31 downto 0);
signal mux_902 : std_logic_vector(31 downto 0);
signal mux_903 : std_logic_vector(31 downto 0);
signal mux_904 : std_logic_vector(31 downto 0);
signal mux_905 : std_logic_vector(31 downto 0);
signal mux_906 : std_logic_vector(31 downto 0);
signal mux_907 : std_logic_vector(31 downto 0);
signal mux_908 : std_logic_vector(31 downto 0);
signal mux_917 : std_logic_vector(31 downto 0);
signal mux_918 : std_logic_vector(31 downto 0);
signal mux_924 : std_logic_vector(31 downto 0);
signal mux_925 : std_logic_vector(31 downto 0);
signal mux_928 : std_logic_vector(31 downto 0);
signal mux_929 : std_logic_vector(31 downto 0);
signal mux_931 : std_logic_vector(31 downto 0);
signal mux_932 : std_logic_vector(31 downto 0);
signal mux_934 : std_logic_vector(31 downto 0);
signal mux_935 : std_logic_vector(31 downto 0);
signal mux_936 : std_logic_vector(31 downto 0);
signal mux_937 : std_logic_vector(31 downto 0);
signal mux_938 : std_logic_vector(31 downto 0);
signal mux_939 : std_logic_vector(31 downto 0);
signal mux_941 : std_logic_vector(31 downto 0);
signal mux_944 : std_logic_vector(31 downto 0);
signal mux_945 : std_logic_vector(31 downto 0);
signal mux_946 : std_logic_vector(31 downto 0);
signal mux_833 : std_logic_vector(31 downto 0);
signal mux_834 : std_logic_vector(31 downto 0);
signal mux_835 : std_logic_vector(31 downto 0);
signal mux_838 : std_logic_vector(31 downto 0);
signal mux_844 : std_logic_vector(31 downto 0);
signal mux_857 : std_logic_vector(31 downto 0);
signal mux_858 : std_logic_vector(31 downto 0);
signal mux_859 : std_logic_vector(31 downto 0);
signal mux_874 : std_logic_vector(31 downto 0);
signal mux_888 : std_logic_vector(31 downto 0);
signal mux_889 : std_logic_vector(31 downto 0);
signal mux_913 : std_logic_vector(31 downto 0);
signal mux_914 : std_logic_vector(31 downto 0);
signal mux_915 : std_logic_vector(31 downto 0);
signal mux_916 : std_logic_vector(31 downto 0);
signal mux_933 : std_logic_vector(31 downto 0);
signal mux_940 : std_logic_vector(31 downto 0);
signal mux_942 : std_logic_vector(31 downto 0);
signal and_867 : std_logic;
signal mux_909 : std_logic_vector(31 downto 0);
signal mux_910 : std_logic_vector(31 downto 0);
signal mux_911 : std_logic_vector(31 downto 0);
signal mux_920 : std_logic_vector(31 downto 0);
signal mux_921 : std_logic_vector(31 downto 0);
signal mux_926 : std_logic_vector(31 downto 0);
signal mux_927 : std_logic_vector(31 downto 0);
signal mux_943 : std_logic_vector(31 downto 0);
signal mux_886 : std_logic;
signal mux_922 : std_logic_vector(31 downto 0);
signal mux_923 : std_logic_vector(31 downto 0);
signal mux_930 : std_logic_vector(31 downto 0);
signal mux_987 : std_logic_vector(31 downto 0);
signal and_860 : std_logic_vector(31 downto 0);
signal and_881 : std_logic_vector(31 downto 0);
signal and_884 : std_logic_vector(31 downto 0);
signal mux_890 : std_logic_vector(31 downto 0);
signal mux_912 : std_logic_vector(31 downto 0);
signal mux_919 : std_logic_vector(31 downto 0);
signal mux_948 : std_logic_vector(31 downto 0);
signal mux_949 : std_logic_vector(31 downto 0);
signal mux_950 : std_logic_vector(31 downto 0);
signal and_862 : std_logic;
signal mux_953 : std_logic_vector(31 downto 0);
signal mux_954 : std_logic_vector(31 downto 0);
signal mux_955 : std_logic_vector(31 downto 0);
signal mux_951 : std_logic_vector(31 downto 0);
signal mux_952 : std_logic_vector(31 downto 0);
signal mux_959 : std_logic_vector(31 downto 0);
signal mux_960 : std_logic_vector(31 downto 0);
signal mux_961 : std_logic_vector(31 downto 0);
signal mux_965 : std_logic_vector(31 downto 0);
signal mux_966 : std_logic_vector(31 downto 0);
signal and_876 : std_logic_vector(7 downto 0);
signal mux_956 : std_logic_vector(31 downto 0);
signal mux_957 : std_logic_vector(31 downto 0);
signal mux_947 : std_logic_vector(31 downto 0);
signal mux_968 : std_logic_vector(31 downto 0);
signal mux_969 : std_logic_vector(31 downto 0);
signal mux_970 : std_logic_vector(31 downto 0);
signal mux_980 : std_logic_vector(31 downto 0);
signal mux_981 : std_logic_vector(31 downto 0);
signal mux_958 : std_logic_vector(31 downto 0);
signal and_963 : std_logic;
signal mux_986 : std_logic_vector(31 downto 0);
signal mux_988 : std_logic_vector(31 downto 0);
signal mux_989 : std_logic_vector(31 downto 0);
-- This utility function is used for inlining MUX behaviour
-- Little utility function to ease concatenation of an std_logic
-- and explicitely return an std_logic_vector
function repeat(N: natural; B: std_logic) return std_logic_vector is
variable result: std_logic_vector(N-1 downto 0);
begin
result := (others => B);
return result;
end;
begin
-- Instantiation of components
cmp_869_i : cmp_869 port map (
eq => sig_1670,
in1 => sig_1665,
in0 => get_sos_cc
);
cmp_978_i : cmp_978 port map (
ne => augh_test_132,
in1 => sig_1633,
in0 => huff_make_dhuff_tb_dc_size
);
cmp_979_i : cmp_979 port map (
ne => augh_test_124,
in1 => sig_1635,
in0 => huff_make_dhuff_tb_ac_size
);
cmp_847_i : cmp_847 port map (
eq => augh_test_100,
in1 => sig_1716,
in0 => "00000000000000000000000011000000"
);
cmp_855_i : cmp_855 port map (
ne => sig_1669,
in1 => sig_1715,
in0 => "00000000000000000000000000000000"
);
cmp_852_i : cmp_852 port map (
eq => augh_test_94,
in1 => sig_1714,
in0 => "00000000000000000000000000000000"
);
mul_213_i : mul_213 port map (
output => sig_1668,
in_b => "00000000000000000000000000110001",
in_a => chenidct_b3
);
mul_216_i : mul_216 port map (
output => sig_1667,
in_b => sig_1713,
in_a => mux_762
);
mul_214_i : mul_214 port map (
output => sig_1666,
in_b => sig_1712,
in_a => mux_760
);
cmp_846_i : cmp_846 port map (
eq => augh_test_99,
in1 => sig_1711,
in0 => "00000000000000000000000011011000"
);
cmp_848_i : cmp_848 port map (
eq => augh_test_101,
in1 => sig_1710,
in0 => "00000000000000000000000011011010"
);
cmp_849_i : cmp_849 port map (
eq => augh_test_102,
in1 => sig_1709,
in0 => "00000000000000000000000011000100"
);
p_jinfo_comps_info_id_i : p_jinfo_comps_info_id port map (
wa0_data => read_byte,
wa0_addr => get_sof_i_comp_info_id,
clk => sig_clock,
ra0_addr => get_sos_ci(1 downto 0),
ra0_data => sig_1665,
wa0_en => sig_1213
);
p_jinfo_comps_info_h_samp_factor_i : p_jinfo_comps_info_h_samp_factor port map (
wa0_data => and_876,
wa0_addr => get_sof_i_comp_info_h_samp_factor,
clk => sig_clock,
ra0_addr => "00",
ra0_data => sig_1664,
wa0_en => sig_1214
);
p_jinfo_comps_info_quant_tbl_no_i : p_jinfo_comps_info_quant_tbl_no port map (
wa0_data => read_byte(1 downto 0),
wa0_addr => get_sof_i_comp_info_quant_tbl_no,
clk => sig_clock,
ra0_addr => decode_block_comp_no,
ra0_data => sig_1663,
wa0_en => sig_1212
);
p_jinfo_comps_info_dc_tbl_no_i : p_jinfo_comps_info_dc_tbl_no port map (
wa0_data => get_sos_c,
wa0_addr => get_sos_i_comp_info_dc_tbl_no,
clk => sig_clock,
ra0_addr => decode_block_comp_no,
ra0_data => sig_1662,
wa0_en => sig_1252
);
p_jinfo_quant_tbl_quantval_i : p_jinfo_quant_tbl_quantval port map (
wa0_data => sig_1708,
wa0_addr => sig_1707,
clk => sig_clock,
ra0_addr => mux_731,
ra0_data => sig_1661,
wa0_en => sig_1334
);
p_jinfo_dc_xhuff_tbl_bits_i : p_jinfo_dc_xhuff_tbl_bits port map (
wa0_data => mux_782,
wa0_addr => sig_1706,
clk => sig_clock,
ra0_addr => mux_727,
ra0_data => sig_1660,
wa0_en => sig_1457
);
p_jinfo_dc_xhuff_tbl_huffval_i : p_jinfo_dc_xhuff_tbl_huffval port map (
wa0_data => mux_778,
wa0_addr => sig_1705,
clk => sig_clock,
ra0_addr => mux_723,
ra0_data => sig_1659,
wa0_en => sig_1540
);
p_jinfo_ac_xhuff_tbl_bits_i : p_jinfo_ac_xhuff_tbl_bits port map (
wa0_data => mux_783,
wa0_addr => sig_1704,
clk => sig_clock,
ra0_addr => mux_719,
ra0_data => sig_1658,
wa0_en => sig_1457
);
p_jinfo_ac_xhuff_tbl_huffval_i : p_jinfo_ac_xhuff_tbl_huffval port map (
wa0_data => mux_781,
wa0_addr => sig_1703,
clk => sig_clock,
ra0_addr => mux_715,
ra0_data => sig_1657,
wa0_en => sig_1540
);
p_jinfo_dc_dhuff_tbl_ml_i : p_jinfo_dc_dhuff_tbl_ml port map (
wa0_data => huff_make_dhuff_tb_dc,
wa0_addr => sig_1188,
clk => sig_clock,
ra0_addr => mux_711,
ra0_data => sig_1656,
wa0_en => sig_1190
);
p_jinfo_dc_dhuff_tbl_maxcode_i : p_jinfo_dc_dhuff_tbl_maxcode port map (
wa0_data => mux_705,
wa0_addr => mux_706,
clk => sig_clock,
ra0_addr => mux_707,
ra0_data => sig_1655,
wa0_en => sig_1560
);
p_jinfo_dc_dhuff_tbl_mincode_i : p_jinfo_dc_dhuff_tbl_mincode port map (
wa0_data => sig_1632(8 downto 0),
wa0_addr => sig_1702,
clk => sig_clock,
ra0_addr => sig_1701,
ra0_data => sig_1654,
wa0_en => sig_1039
);
p_jinfo_dc_dhuff_tbl_valptr_i : p_jinfo_dc_dhuff_tbl_valptr port map (
wa0_data => huff_make_dhuff_tb_dc_p(8 downto 0),
wa0_addr => sig_1700,
clk => sig_clock,
ra0_addr => sig_1699,
ra0_data => sig_1653,
wa0_en => sig_1039
);
p_jinfo_ac_dhuff_tbl_ml_i : p_jinfo_ac_dhuff_tbl_ml port map (
wa0_data => huff_make_dhuff_tb_ac,
wa0_addr => sig_1183,
clk => sig_clock,
ra0_addr => mux_695,
ra0_data => sig_1652,
wa0_en => sig_1185
);
p_jinfo_ac_dhuff_tbl_maxcode_i : p_jinfo_ac_dhuff_tbl_maxcode port map (
wa0_data => mux_689,
wa0_addr => mux_690,
clk => sig_clock,
ra0_addr => mux_691,
ra0_data => sig_1651,
wa0_en => sig_1522
);
p_jinfo_ac_dhuff_tbl_mincode_i : p_jinfo_ac_dhuff_tbl_mincode port map (
wa0_data => sig_1634(8 downto 0),
wa0_addr => sig_1698,
clk => sig_clock,
ra0_addr => sig_1697,
ra0_data => sig_1650,
wa0_en => sig_1549
);
p_jinfo_ac_dhuff_tbl_valptr_i : p_jinfo_ac_dhuff_tbl_valptr port map (
wa0_data => huff_make_dhuff_tb_ac_p(8 downto 0),
wa0_addr => sig_1696,
clk => sig_clock,
ra0_addr => sig_1695,
ra0_data => sig_1649,
wa0_en => sig_1549
);
outdata_comp_vpos_i : outdata_comp_vpos port map (
wa0_data => mux_663,
wa0_addr => mux_664,
clk => sig_clock,
ra0_addr => mux_665,
ra0_data => sig_1648,
wa0_en => sig_1295
);
outdata_comp_hpos_i : outdata_comp_hpos port map (
wa0_data => mux_659,
wa0_addr => mux_660,
clk => sig_clock,
ra0_addr => mux_661,
ra0_data => sig_1647,
wa0_en => sig_1295
);
outdata_comp_buf_i : outdata_comp_buf port map (
wa0_data => sig_1631,
wa0_addr => sig_1694,
clk => sig_clock,
ra0_addr => sig_1693,
ra0_data => sig_1646,
wa0_en => sig_1013
);
izigzag_index_i : izigzag_index port map (
clk => sig_clock,
ra0_addr => get_dqt_i(5 downto 0),
ra0_data => sig_1645
);
jpegfilebuf_i : jpegfilebuf port map (
wa0_data => read8_ret0_195,
wa0_addr => jpeg2bmp_main_i(12 downto 0),
clk => sig_clock,
ra0_addr => mux_652,
ra0_data => sig_1644,
wa0_en => sig_1041
);
huffbuff_i : huffbuff port map (
wa0_data => mux_567,
wa0_addr => mux_568,
clk => sig_clock,
ra0_addr => mux_569,
ra0_data => sig_1643,
wa0_en => sig_1428
);
idctbuff_i : idctbuff port map (
wa0_data => mux_561,
wa0_addr => mux_562,
clk => sig_clock,
ra2_data => sig_1642,
ra2_addr => mux_563,
ra1_data => sig_1641,
ra1_addr => sig_1692,
ra0_addr => mux_565,
ra0_data => sig_1640,
wa0_en => sig_1474
);
quantbuff_i : quantbuff port map (
wa0_data => mux_557,
wa0_addr => mux_558,
clk => sig_clock,
ra0_addr => mux_559,
ra0_data => sig_1639,
wa0_en => sig_1431
);
extend_mask_i : extend_mask port map (
clk => sig_clock,
ra0_addr => decodehuffmcu_s(4 downto 0),
ra0_data => sig_1638
);
bit_set_mask_i : bit_set_mask port map (
clk => sig_clock,
ra0_addr => mux_524,
ra0_data => sig_1637
);
lmask_i : lmask port map (
clk => sig_clock,
ra0_addr => buf_getv_n(4 downto 0),
ra0_data => sig_1636
);
huff_make_dhuff_tb_ac_huffsize_i : huff_make_dhuff_tb_ac_huffsize port map (
wa0_data => mux_476,
wa0_addr => huff_make_dhuff_tb_ac_p(8 downto 0),
clk => sig_clock,
ra0_addr => mux_478,
ra0_data => sig_1635,
wa0_en => sig_1501
);
huff_make_dhuff_tb_ac_huffcode_i : huff_make_dhuff_tb_ac_huffcode port map (
wa0_data => huff_make_dhuff_tb_ac_code,
wa0_addr => huff_make_dhuff_tb_ac_p(8 downto 0),
clk => sig_clock,
ra0_addr => huff_make_dhuff_tb_ac_p(8 downto 0),
ra0_data => sig_1634,
wa0_en => sig_1024
);
huff_make_dhuff_tb_dc_huffsize_i : huff_make_dhuff_tb_dc_huffsize port map (
wa0_data => mux_443,
wa0_addr => huff_make_dhuff_tb_dc_p(8 downto 0),
clk => sig_clock,
ra0_addr => mux_445,
ra0_data => sig_1633,
wa0_en => sig_1530
);
huff_make_dhuff_tb_dc_huffcode_i : huff_make_dhuff_tb_dc_huffcode port map (
wa0_data => huff_make_dhuff_tb_dc_code,
wa0_addr => huff_make_dhuff_tb_dc_p(8 downto 0),
clk => sig_clock,
ra0_addr => huff_make_dhuff_tb_dc_p(8 downto 0),
ra0_data => sig_1632,
wa0_en => sig_1036
);
rgb_buf_i : rgb_buf port map (
wa0_data => mux_378,
wa0_addr => mux_379,
clk => sig_clock,
ra0_addr => sig_1691,
ra0_data => sig_1631,
wa0_en => sig_1236
);
zigzag_index_i : zigzag_index port map (
clk => sig_clock,
ra0_addr => izigzagmatrix_i(5 downto 0),
ra0_data => sig_1630
);
shr_212_i : shr_212 port map (
output => sig_1629,
input => mux_322,
shift => mux_323,
padding => '0'
);
mul_209_i : mul_209 port map (
output => sig_1628,
in_b => mux_315,
in_a => mux_316
);
mul_210_i : mul_210 port map (
output => sig_1627,
in_b => sig_1690,
in_a => mux_314
);
shl_211_i : shl_211 port map (
output => sig_1626,
input => current_read_byte,
shift => buf_getv_p(5 downto 0),
padding => '0'
);
sub_206_i : sub_206 port map (
gt => sig_1625,
output => sig_1624,
sign => '1',
in_b => mux_306,
in_a => mux_307
);
sub_207_i : sub_207 port map (
ge => sig_1623,
le => sig_1622,
output => sig_1621,
sign => '1',
in_b => mux_302,
in_a => mux_303
);
sub_208_i : sub_208 port map (
ge => sig_1620,
output => sig_1619,
sign => '1',
in_b => "00000000000000000000000000000000000000000",
in_a => sig_1689
);
sub_205_i : sub_205 port map (
gt => sig_1618,
ge => sig_1617,
lt => sig_1616,
le => sig_1615,
output => sig_1614,
sign => '1',
in_b => mux_290,
in_a => mux_291
);
add_202_i : add_202 port map (
output => sig_1613,
in_b => mux_274,
in_a => mux_275
);
add_203_i : add_203 port map (
output => sig_1612,
in_b => mux_271,
in_a => mux_272
);
add_204_i : add_204 port map (
output => sig_1611,
in_b => "0000000000000000000000001",
in_a => sig_1688
);
add_201_i : add_201 port map (
output => sig_1610,
in_b => mux_265,
in_a => mux_266
);
add_200_i : add_200 port map (
output => sig_1609,
in_b => mux_260,
in_a => mux_261
);
cmp_775_i : cmp_775 port map (
eq => augh_test_158,
in1 => sig_1687,
in0 => "00000000000000000000000000001111"
);
cmp_779_i : cmp_779 port map (
eq => sig_1608,
in1 => sig_1686,
in0 => "00000000000000000000000000000000"
);
cmp_780_i : cmp_780 port map (
ne => sig_1607,
in1 => sig_1685,
in0 => "00000000000000000000000000000000"
);
cmp_787_i : cmp_787 port map (
eq => sig_1606,
in1 => '0',
in0 => sig_1610(0)
);
cmp_788_i : cmp_788 port map (
eq => sig_1605,
in1 => "000",
in0 => sig_1642(2 downto 0)
);
cmp_790_i : cmp_790 port map (
ne => sig_1604,
in1 => sig_1624(3 downto 0),
in0 => "0000"
);
cmp_792_i : cmp_792 port map (
eq => augh_test_134,
in1 => sig_1660,
in0 => "00000000000000000000000000000000"
);
cmp_793_i : cmp_793 port map (
eq => augh_test_131,
in1 => sig_1633,
in0 => "00000000000000000000000000000000"
);
cmp_794_i : cmp_794 port map (
eq => augh_test_126,
in1 => sig_1658,
in0 => "00000000000000000000000000000000"
);
cmp_791_i : cmp_791 port map (
ne => augh_test_148,
in1 => decodehuffman_dc,
in0 => "00000000000000000000000000000000"
);
cmp_804_i : cmp_804 port map (
ne => augh_test_113,
in1 => and_803,
in0 => "00000000000000000000000000000000"
);
cmp_800_i : cmp_800 port map (
eq => augh_test_118,
in1 => buf_getv_p,
in0 => "00000000000000000000000000000000"
);
cmp_799_i : cmp_799 port map (
eq => augh_test_123,
in1 => sig_1635,
in0 => "00000000000000000000000000000000"
);
cmp_865_i : cmp_865 port map (
ne => sig_1603,
in1 => sig_1624(2 downto 0),
in0 => "000"
);
cmp_882_i : cmp_882 port map (
eq => augh_test_157,
in1 => and_881,
in0 => "00000000000000000000000000000000"
);
cmp_885_i : cmp_885 port map (
ne => sig_1602,
in1 => and_884,
in0 => "00000000000000000000000000000000"
);
cmp_887_i : cmp_887 port map (
eq => sig_1601,
in1 => and_884,
in0 => "00000000000000000000000000000000"
);
mul_215_i : mul_215 port map (
output => sig_1600,
in_b => "00000000000000000000000111011001",
in_a => chenidct_b2
);
cmp_850_i : cmp_850 port map (
eq => augh_test_103,
in1 => sig_1684,
in0 => "00000000000000000000000011011011"
);
cmp_851_i : cmp_851 port map (
eq => augh_test_104,
in1 => sig_1683,
in0 => "00000000000000000000000011011001"
);
cmp_861_i : cmp_861 port map (
eq => augh_test_150,
in1 => and_860,
in0 => "00000000000000000000000000000000"
);
cmp_871_i : cmp_871 port map (
eq => sig_1599,
in1 => sig_1682,
in0 => "00000000000000000000000000000000"
);
cmp_873_i : cmp_873 port map (
eq => sig_1598,
in1 => sig_1664,
in0 => "00000010"
);
cmp_879_i : cmp_879 port map (
ne => augh_test_6,
in1 => sig_1681,
in0 => "00000000000000000000000011111111"
);
cmp_880_i : cmp_880 port map (
eq => augh_test_9,
in1 => sig_1680,
in0 => "00000000000000000000000011111111"
);
sub_217_i : sub_217 port map (
ge => sig_1597,
output => sig_1596,
sign => '1',
in_b => "00000000000000000000000000000000000000000",
in_a => sig_1679
);
cmp_863_i : cmp_863 port map (
ne => sig_1595,
in1 => sig_1614(2 downto 0),
in0 => "000"
);
cmp_868_i : cmp_868 port map (
eq => sig_1594,
in1 => "000000000000000000000000",
in0 => "000000000000000000000000"
);
cmp_877_i : cmp_877 port map (
ne => augh_test_109,
in1 => sig_1678,
in0 => "00000000000000000000000000000000"
);
cmp_878_i : cmp_878 port map (
ne => augh_test_10,
in1 => sig_1677,
in0 => "00000000000000000000000000000000"
);
sub_218_i : sub_218 port map (
le => sig_1593,
output => sig_1592,
sign => '1',
in_b => "00000000000000000000000000000000011111111",
in_a => sig_1676
);
sub_220_i : sub_220 port map (
gt => sig_1591,
output => sig_1590,
sign => '1',
in_b => "00000000000000000000000000000000011111111",
in_a => sig_1675
);
sub_221_i : sub_221 port map (
gt => sig_1589,
output => sig_1588,
sign => '1',
in_b => "00000000000000000000000000000000011111111",
in_a => sig_1674
);
mul_222_i : mul_222 port map (
output => sig_1587,
in_b => "00000000000000000000000010110101",
in_a => mux_233
);
sub_219_i : sub_219 port map (
le => sig_1586,
output => sig_1585,
sign => '1',
in_b => "00000000000000000000000000000000011111111",
in_a => sig_1673
);
cmp_962_i : cmp_962 port map (
ne => augh_test_62,
in1 => get_sos_j,
in0 => "11111111111111111111111111111111"
);
cmp_975_i : cmp_975 port map (
ne => augh_test_154,
in1 => decodehuffmcu_s,
in0 => "00000000000000000000000000000000"
);
fsm_224_i : fsm_224 port map (
clock => sig_clock,
reset => sig_reset,
out40 => sig_1584,
in2 => augh_test_152,
in11 => augh_test_131,
out146 => sig_1583,
out148 => sig_1582,
out150 => sig_1581,
out152 => sig_1580,
in12 => augh_test_128,
out153 => sig_1579,
out154 => sig_1578,
in13 => augh_test_127,
out156 => sig_1577,
out157 => sig_1576,
out160 => sig_1575,
out162 => sig_1574,
out165 => sig_1573,
out170 => sig_1572,
out171 => sig_1571,
out173 => sig_1570,
out175 => sig_1569,
out177 => sig_1568,
out180 => sig_1567,
out184 => sig_1566,
in14 => augh_test_126,
out186 => sig_1565,
out189 => sig_1564,
out191 => sig_1563,
out192 => sig_1562,
out193 => sig_1561,
out197 => sig_1560,
out199 => sig_1559,
out201 => sig_1558,
out202 => sig_1557,
out205 => sig_1556,
out207 => sig_1555,
out208 => sig_1554,
out209 => sig_1553,
out210 => sig_1552,
out212 => sig_1551,
out213 => sig_1550,
in15 => augh_test_125,
out221 => sig_1549,
out222 => sig_1548,
out224 => sig_1547,
out225 => sig_1546,
out228 => sig_1545,
out229 => sig_1544,
out230 => sig_1543,
out231 => sig_1542,
out99 => sig_1541,
in6 => augh_test_142,
out92 => sig_1540,
out232 => sig_1539,
in16 => augh_test_123,
out234 => sig_1538,
out236 => sig_1537,
out239 => sig_1536,
out240 => sig_1535,
out241 => sig_1534,
out245 => sig_1533,
out246 => sig_1532,
out247 => sig_1531,
out251 => sig_1530,
out252 => sig_1529,
out253 => sig_1528,
out255 => sig_1527,
out256 => sig_1526,
out258 => sig_1525,
out259 => sig_1524,
in17 => augh_test_120,
out263 => sig_1523,
out264 => sig_1522,
out266 => sig_1521,
in18 => augh_test_119,
out267 => sig_1520,
out268 => sig_1519,
out270 => sig_1518,
out273 => sig_1517,
out275 => sig_1516,
out276 => sig_1515,
in19 => augh_test_118,
out279 => sig_1514,
in20 => augh_test_115,
out281 => sig_1513,
out282 => sig_1512,
in21 => augh_test_114,
out283 => sig_1511,
out286 => sig_1510,
out289 => sig_1509,
out296 => sig_1508,
out297 => sig_1507,
out299 => sig_1506,
out300 => sig_1505,
out304 => sig_1504,
out305 => sig_1503,
in22 => augh_test_113,
out306 => sig_1502,
out310 => sig_1501,
out311 => sig_1500,
out313 => sig_1499,
out314 => sig_1498,
in23 => augh_test_111,
out316 => sig_1497,
out317 => sig_1496,
out320 => sig_1495,
out322 => sig_1494,
out324 => sig_1493,
out325 => sig_1492,
out326 => sig_1491,
out328 => sig_1490,
out332 => sig_1489,
out333 => sig_1488,
out334 => sig_1487,
out335 => sig_1486,
out338 => sig_1485,
out339 => sig_1484,
out341 => sig_1483,
out342 => sig_1482,
out344 => sig_1481,
out93 => sig_1480,
out98 => sig_1479,
out85 => sig_1478,
out87 => sig_1477,
out88 => sig_1476,
out80 => sig_1475,
out82 => sig_1474,
out83 => sig_1473,
out84 => sig_1472,
in5 => augh_test_144,
out77 => sig_1471,
out78 => sig_1470,
out71 => sig_1469,
out72 => sig_1468,
in4 => augh_test_148,
out65 => sig_1467,
out67 => sig_1466,
out60 => sig_1465,
out64 => sig_1464,
in3 => augh_test_151,
out59 => sig_1463,
out53 => sig_1462,
out55 => sig_1461,
out49 => sig_1460,
out44 => sig_1459,
out104 => sig_1458,
out107 => sig_1457,
out111 => sig_1456,
out112 => sig_1455,
out114 => sig_1454,
in7 => augh_test_138,
out117 => sig_1453,
out119 => sig_1452,
out122 => sig_1451,
in8 => augh_test_136,
out128 => sig_1450,
in9 => augh_test_134,
out129 => sig_1449,
out130 => sig_1448,
out133 => sig_1447,
out134 => sig_1446,
out136 => sig_1445,
out137 => sig_1444,
in10 => augh_test_133,
out139 => sig_1443,
out143 => sig_1442,
out144 => sig_1441,
out32 => sig_1440,
out35 => sig_1439,
out27 => sig_1438,
out25 => sig_1437,
out26 => sig_1436,
in1 => augh_test_158,
out15 => sig_1435,
out16 => sig_1434,
out11 => sig_1433,
out13 => sig_1432,
out14 => sig_1431,
out7 => sig_1430,
out1 => sig_1429,
out2 => sig_1428,
out3 => sig_1427,
out4 => sig_1426,
in0 => augh_test_159,
in24 => augh_test_107,
out346 => sig_1425,
out347 => sig_1424,
out348 => sig_1423,
out349 => sig_1422,
in25 => augh_test_106,
out350 => sig_1421,
out351 => sig_1420,
out355 => sig_1419,
out356 => sig_1418,
out357 => sig_1417,
out358 => sig_1416,
out360 => sig_1415,
out362 => sig_1414,
out363 => sig_1413,
out364 => sig_1412,
out365 => sig_1411,
out366 => sig_1410,
out370 => sig_1409,
out371 => sig_1408,
out372 => sig_1407,
out373 => sig_1406,
out375 => sig_1405,
in26 => augh_test_105,
out376 => sig_1404,
out378 => sig_1403,
out379 => sig_1402,
out381 => sig_1401,
out382 => sig_1400,
in27 => augh_test_99,
out384 => sig_1399,
in28 => augh_test_100,
out391 => sig_1398,
out395 => sig_1397,
out396 => sig_1396,
out401 => sig_1395,
out402 => sig_1394,
out403 => sig_1393,
out404 => sig_1392,
out405 => sig_1391,
out407 => sig_1390,
out408 => sig_1389,
out409 => sig_1388,
out410 => sig_1387,
in29 => augh_test_101,
out412 => sig_1386,
out414 => sig_1385,
out415 => sig_1384,
out417 => sig_1383,
out418 => sig_1382,
out419 => sig_1381,
out420 => sig_1380,
out422 => sig_1379,
out424 => sig_1378,
out425 => sig_1377,
out426 => sig_1376,
in30 => augh_test_102,
out428 => sig_1375,
out429 => sig_1374,
out432 => sig_1373,
out433 => sig_1372,
out434 => sig_1371,
out437 => sig_1370,
out440 => sig_1369,
out441 => sig_1368,
in31 => augh_test_103,
out443 => sig_1367,
in32 => augh_test_104,
out445 => sig_1366,
out447 => sig_1365,
out448 => sig_1364,
out450 => sig_1363,
in33 => augh_test_94,
out453 => sig_1362,
out455 => sig_1361,
out458 => sig_1360,
in34 => augh_test_90,
out462 => sig_1359,
out464 => sig_1358,
out467 => sig_1357,
out468 => sig_1356,
out472 => sig_1355,
in35 => augh_test_89,
out478 => sig_1354,
out479 => sig_1353,
out480 => sig_1352,
out487 => sig_1351,
out488 => sig_1350,
in36 => augh_test_83,
out491 => sig_1349,
out496 => sig_1348,
out497 => sig_1347,
out498 => sig_1346,
out500 => sig_1345,
out504 => sig_1344,
out505 => sig_1343,
in37 => augh_test_150,
out506 => sig_1342,
out508 => sig_1341,
in38 => augh_test_77,
out510 => sig_1340,
out513 => sig_1339,
out514 => sig_1338,
out515 => sig_1337,
out517 => sig_1336,
out519 => sig_1335,
in39 => augh_test_72,
out523 => sig_1334,
out526 => sig_1333,
out527 => sig_1332,
out528 => sig_1331,
out530 => sig_1330,
out531 => sig_1329,
out533 => sig_1328,
out534 => sig_1327,
out537 => sig_1326,
out538 => sig_1325,
out549 => sig_1324,
out558 => sig_1323,
out559 => sig_1322,
out561 => sig_1321,
in40 => augh_test_67,
out566 => sig_1320,
out567 => sig_1319,
out568 => sig_1318,
out569 => sig_1317,
out570 => sig_1316,
out572 => sig_1315,
out574 => sig_1314,
out575 => sig_1313,
out577 => sig_1312,
in41 => augh_test_52,
out578 => sig_1311,
out581 => sig_1310,
out589 => sig_1309,
out590 => sig_1308,
out595 => sig_1307,
out597 => sig_1306,
out599 => sig_1305,
out601 => sig_1304,
out602 => sig_1303,
out607 => sig_1302,
out610 => sig_1301,
out612 => sig_1300,
in42 => augh_test_53,
out614 => sig_1299,
out621 => sig_1298,
out628 => sig_1297,
out635 => sig_1296,
out636 => sig_1295,
out638 => sig_1294,
out640 => sig_1293,
out643 => sig_1292,
out646 => sig_1291,
out649 => sig_1290,
out651 => sig_1289,
out656 => sig_1288,
in43 => augh_test_49,
out658 => sig_1287,
out659 => sig_1286,
out661 => sig_1285,
out663 => sig_1284,
out664 => sig_1283,
in44 => augh_test_109,
out667 => sig_1282,
out668 => sig_1281,
out670 => sig_1280,
out672 => sig_1279,
out674 => sig_1278,
in45 => augh_test_26,
out679 => sig_1277,
out681 => sig_1276,
out683 => sig_1275,
out686 => sig_1274,
out688 => sig_1273,
out690 => sig_1272,
out692 => sig_1271,
out694 => sig_1270,
out696 => sig_1269,
out697 => sig_1268,
out698 => sig_1267,
out699 => sig_1266,
out700 => sig_1265,
out703 => sig_1264,
out704 => sig_1263,
out706 => sig_1262,
out708 => sig_1261,
out710 => sig_1260,
out712 => sig_1259,
out715 => sig_1258,
out718 => sig_1257,
in46 => augh_test_10,
out722 => sig_1256,
out724 => sig_1255,
out726 => sig_1254,
out728 => sig_1253,
out731 => sig_1252,
out733 => sig_1251,
out734 => sig_1250,
out737 => sig_1249,
out739 => sig_1248,
out740 => sig_1247,
out743 => sig_1246,
out745 => sig_1245,
out746 => sig_1244,
in47 => augh_test_6,
out749 => sig_1243,
out753 => sig_1242,
out755 => sig_1241,
out759 => sig_1240,
in48 => augh_test_9,
out762 => sig_1239,
out764 => sig_1238,
out765 => sig_1237,
out767 => sig_1236,
out768 => sig_1235,
in49 => augh_test_157,
out772 => sig_1234,
in50 => stdout_ack,
out775 => sig_1233,
out776 => sig_1232,
out778 => sig_1231,
out783 => sig_1230,
out784 => sig_1229,
out787 => sig_1228,
out791 => sig_1227,
in51 => stdin_ack,
out794 => sig_1226,
out795 => sig_1225,
in52 => augh_test_62,
out799 => sig_1224,
out802 => sig_1223,
out806 => sig_1222,
out809 => sig_1221,
out812 => sig_1220,
out815 => sig_1219,
out826 => sig_1218,
out828 => sig_1217,
in53 => augh_test_122,
in54 => augh_test_197,
out843 => sig_1216,
out848 => sig_1215,
out852 => sig_1214,
in55 => augh_test_196,
out855 => sig_1213,
out858 => sig_1212,
in56 => augh_test_189,
out860 => sig_1211,
out861 => sig_1210,
out863 => sig_1209,
out866 => sig_1208,
out872 => sig_1207,
in57 => augh_test_188,
out874 => sig_1206,
out876 => sig_1205,
out879 => sig_1204,
out882 => sig_1203,
out886 => sig_1202,
out887 => sig_1201,
in58 => augh_test_187,
out888 => sig_1200,
out892 => sig_1199,
out894 => sig_1198,
out895 => sig_1197,
out896 => sig_1196,
out901 => sig_1195,
out902 => sig_1194,
out903 => sig_1193,
out905 => sig_1192,
out907 => sig_1191,
out918 => sig_1190,
out920 => sig_1189,
out921 => sig_1188,
out923 => sig_1187,
out925 => sig_1186,
out928 => sig_1185,
out929 => sig_1184,
out931 => sig_1183,
out933 => sig_1182,
out936 => stdout_rdy,
out937 => sig_1181,
out938 => sig_1180,
out939 => sig_1179,
out942 => sig_1178,
out943 => sig_1177,
out944 => sig_1176,
out947 => sig_1175,
out948 => sig_1174,
out949 => sig_1173,
out951 => sig_1172,
in59 => augh_test_186,
out952 => sig_1171,
out953 => sig_1170,
out955 => sig_1169,
out956 => sig_1168,
out957 => sig_1167,
out958 => sig_1166,
in60 => augh_test_184,
in61 => augh_test_183,
out962 => sig_1165,
out963 => sig_1164,
out972 => sig_1163,
out973 => sig_1162,
out974 => sig_1161,
in62 => augh_test_182,
out978 => sig_1160,
out979 => sig_1159,
out981 => sig_1158,
out982 => sig_1157,
out985 => sig_1156,
out986 => sig_1155,
out989 => sig_1154,
in63 => augh_test_180,
in64 => augh_test_179,
in65 => augh_test_178,
in66 => augh_test_194,
in67 => augh_test_154,
in68 => augh_test_130,
in69 => augh_test_132,
in70 => augh_test_124,
in71 => augh_test_171,
in72 => augh_test_168,
in73 => augh_test_167,
in74 => augh_test_166,
in75 => augh_test_165,
in76 => augh_test_108,
in77 => sig_start,
in78 => augh_test_155,
out990 => sig_1153,
out991 => sig_1152,
out993 => sig_1151,
out994 => sig_1150,
out996 => sig_1149,
out997 => sig_1148,
out998 => sig_1147,
out999 => sig_1146,
out1000 => sig_1145,
out1002 => sig_1144,
out1003 => sig_1143,
out1005 => sig_1142,
out1006 => sig_1141,
out1007 => sig_1140,
out1009 => sig_1139,
out1011 => sig_1138,
out1012 => sig_1137,
out1013 => sig_1136,
out1014 => sig_1135,
out1015 => sig_1134,
out1016 => sig_1133,
out1018 => sig_1132,
out1019 => sig_1131,
out1021 => sig_1130,
out1022 => sig_1129,
out1024 => sig_1128,
out1026 => sig_1127,
out1027 => sig_1126,
out1029 => sig_1125,
out1030 => sig_1124,
out1032 => sig_1123,
out1033 => sig_1122,
out1035 => sig_1121,
out1036 => sig_1120,
out1037 => sig_1119,
out1057 => sig_1118,
out1068 => sig_1117,
out1069 => sig_1116,
out1070 => sig_1115,
out1072 => sig_1114,
out1073 => sig_1113,
out1075 => sig_1112,
out1078 => sig_1111,
out1080 => sig_1110,
out1082 => sig_1109,
out1083 => sig_1108,
out1084 => sig_1107,
out1085 => sig_1106,
out1088 => sig_1105,
out1089 => sig_1104,
out1091 => sig_1103,
out1092 => sig_1102,
out1094 => sig_1101,
out1096 => sig_1100,
out1098 => sig_1099,
out1101 => sig_1098,
out1104 => sig_1097,
out1107 => sig_1096,
out1109 => sig_1095,
out1111 => sig_1094,
out1114 => sig_1093,
out1119 => sig_1092,
out1121 => sig_1091,
out1125 => sig_1090,
out1126 => sig_1089,
out1128 => sig_1088,
out1131 => sig_1087,
out1134 => sig_1086,
out1137 => sig_1085,
out1139 => sig_1084,
out1141 => sig_1083,
out1145 => sig_1082,
out1146 => sig_1081,
out1147 => sig_1080,
out1150 => sig_1079,
out1151 => sig_1078,
out1152 => sig_1077,
out1155 => sig_1076,
out1158 => sig_1075,
out1160 => sig_1074,
out1164 => sig_1073,
out1166 => sig_1072,
out1169 => sig_1071,
out1171 => sig_1070,
out1174 => sig_1069,
out1175 => sig_1068,
out1176 => sig_1067,
out1180 => sig_1066,
out1181 => sig_1065,
out1182 => sig_1064,
out1185 => sig_1063,
out1186 => sig_1062,
out1187 => sig_1061,
out1190 => sig_1060,
out1213 => sig_1059,
out1215 => sig_1058,
out1217 => sig_1057,
out1220 => sig_1056,
out1221 => sig_1055,
out1223 => sig_1054,
out1228 => sig_1053,
out1229 => sig_1052,
out1231 => sig_1051,
out1235 => sig_1050,
out1236 => sig_1049,
out1240 => sig_1048,
out1243 => sig_1047,
out1250 => sig_1046,
out1252 => sig_1045,
out1253 => sig_1044,
out1258 => sig_1043,
out1262 => sig_1042,
out1266 => sig_1041,
out1269 => sig_1040,
out1275 => sig_1039,
out1278 => sig_1038,
out1279 => sig_1037,
out1284 => sig_1036,
out1286 => sig_1035,
out1287 => sig_1034,
out1289 => sig_1033,
out1290 => sig_1032,
out1292 => sig_1031,
out1293 => sig_1030,
out1295 => sig_1029,
out1298 => sig_1028,
out1301 => sig_1027,
out1302 => sig_1026,
out1303 => sig_1025,
out1308 => sig_1024,
out1309 => sig_1023,
out1311 => sig_1022,
out1318 => sig_1021,
out1319 => sig_1020,
out1320 => sig_1019,
out1323 => sig_1018,
out1324 => sig_1017,
out1326 => sig_1016,
out1327 => sig_1015,
out1329 => sig_1014,
out1337 => sig_1013,
out1339 => sig_1012,
out1340 => sig_1011,
out1341 => sig_1010,
out1344 => sig_1009,
out1346 => sig_1008,
out1349 => sig_1007,
out1353 => sig_1006,
out1356 => sig_1005,
out1362 => sig_1004,
out1363 => sig_1003,
out1364 => sig_1002,
out1365 => sig_1001,
out1366 => sig_1000,
out1368 => sig_999,
out1370 => sig_998,
out1375 => sig_997,
out1378 => sig_996,
out1381 => sig_995,
out1383 => sig_994,
out1387 => sig_993
);
muxb_784_i : muxb_784 port map (
in_sel => sig_1616,
out_data => sig_992,
in_data0 => sig_1609(31 downto 0),
in_data1 => sig_1613
);
cmp_964_i : cmp_964 port map (
eq => sig_991,
in1 => sig_1635,
in0 => huff_make_dhuff_tb_ac_size
);
cmp_972_i : cmp_972 port map (
ne => augh_test_196,
in1 => jpeg2bmp_main_i,
in0 => "00000000000000000000000000000010"
);
cmp_973_i : cmp_973 port map (
eq => augh_test_180,
in1 => sig_1672,
in0 => "00000000000000000000000000000000"
);
cmp_974_i : cmp_974 port map (
ne => augh_test_194,
in1 => jpeg2bmp_main_i,
in0 => "00000000000000000001010001010110"
);
cmp_985_i : cmp_985 port map (
eq => augh_test_108,
in1 => sig_1671,
in0 => "00000000000000000000000011111111"
);
cmp_971_i : cmp_971 port map (
ne => augh_test_197,
in1 => jpeg2bmp_main_j,
in0 => "00000000000000000001010010111101"
);
cmp_977_i : cmp_977 port map (
eq => sig_990,
in1 => sig_1633,
in0 => huff_make_dhuff_tb_dc_size
);
-- Behaviour of component 'mux_967' model 'mux'
mux_967 <=
(repeat(32, sig_1620) and mux_968);
-- Behaviour of component 'and_976' model 'and'
and_976 <=
sig_1615 and
sig_990;
-- Behaviour of component 'and_982' model 'and'
and_982 <=
"00000000000000000000000000001111" and
decodehuffman_ac;
-- Behaviour of component 'and_983' model 'and'
and_983 <=
"0000000000000000000000001111" and
decodehuffman_ac(31 downto 4);
-- Behaviour of component 'and_984' model 'and'
and_984 <=
sig_1636 and
buf_getv_rv;
-- Behaviour of component 'mux_689' model 'mux'
mux_689 <=
(repeat(32, sig_1034) and sig_1634) or
(repeat(32, sig_1520) and "11111111111111111111111111111111") or
(repeat(32, sig_1523) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_690' model 'mux'
mux_690 <=
(repeat(7, sig_1519) and huff_make_dhuff_tb_ac_tbl_no & huff_make_dhuff_tb_ac_l(5 downto 0)) or
(repeat(7, sig_1523) and huff_make_dhuff_tb_ac_tbl_no & huff_make_dhuff_tb_ac_p_dhtbl_ml(5 downto 0));
-- Behaviour of component 'mux_691' model 'mux'
mux_691 <=
(repeat(7, sig_1523) and huff_make_dhuff_tb_ac_tbl_no & huff_make_dhuff_tb_ac_p_dhtbl_ml(5 downto 0)) or
(repeat(7, sig_1568) and decodehuffman_ac_tbl_no & decodehuffman_ac_l(5 downto 0)) or
(repeat(7, sig_1570) and decodehuffman_ac_tbl_no & decodehuffman_ac_dhuff_ml);
-- Behaviour of component 'and_853' model 'and'
and_853 <=
sig_1636 and
sig_1629;
-- Behaviour of component 'mux_233' model 'mux'
mux_233 <=
(repeat(32, sig_1118) and sig_1609(31 downto 0)) or
(repeat(32, sig_1324) and sig_1624(31 downto 0));
-- Behaviour of component 'mux_671' model 'mux'
mux_671 <=
(repeat(32, sig_1183) and i_jinfo_jpeg_data) or
(repeat(32, sig_1441) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_665' model 'mux'
mux_665 <=
(repeat(2, sig_1162) and write4blocks_i) or
(repeat(2, sig_1196) and decode_start_i(1 downto 0)) or
(repeat(2, sig_1296) and writeblock_i);
-- Behaviour of component 'mux_663' model 'mux'
mux_663 <=
(repeat(32, sig_1163) and sig_1609(30 downto 0) & sig_1648(0)) or
(repeat(32, sig_1161) and mux_896) or
(repeat(32, sig_1215) and mux_874) or
(repeat(32, sig_1297) and sig_1609(31 downto 0));
-- Behaviour of component 'mux_664' model 'mux'
mux_664 <=
(repeat(2, sig_1043) and decode_start_i(1 downto 0)) or
(repeat(2, sig_1162) and write4blocks_i) or
(repeat(2, sig_1296) and writeblock_i);
-- Behaviour of component 'mux_659' model 'mux'
mux_659 <=
(repeat(32, sig_1163) and sig_1610(30 downto 0) & sig_1647(0)) or
(repeat(32, sig_1161) and mux_897) or
(repeat(32, sig_1215) and mux_875) or
(repeat(32, sig_1297) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_660' model 'mux'
mux_660 <=
(repeat(2, sig_1043) and decode_start_i(1 downto 0)) or
(repeat(2, sig_1162) and write4blocks_i) or
(repeat(2, sig_1296) and writeblock_i);
-- Behaviour of component 'mux_661' model 'mux'
mux_661 <=
(repeat(2, sig_1162) and write4blocks_i) or
(repeat(2, sig_1196) and decode_start_i(1 downto 0)) or
(repeat(2, sig_1296) and writeblock_i);
-- Behaviour of component 'mux_652' model 'mux'
mux_652 <=
(repeat(13, sig_1247) and readbuf_idx(12 downto 0)) or
(repeat(13, sig_1441) and curhuffreadbuf_idx(12 downto 0));
-- Behaviour of component 'mux_648' model 'mux'
mux_648 <=
(repeat(32, sig_1247) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_633' model 'mux'
mux_633 <=
(repeat(32, sig_1211) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_622' model 'mux'
mux_622 <=
(repeat(32, sig_1251) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_614' model 'mux'
mux_614 <=
(repeat(32, sig_1269) and "00000000000000000000000000000011") or
(repeat(32, sig_1287) and sig_1614(31 downto 0));
-- Behaviour of component 'mux_616' model 'mux'
mux_616 <=
(repeat(32, sig_1254) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_602' model 'mux'
mux_602 <=
(repeat(32, sig_1198) and "00000000000000000000000000000001") or
(repeat(32, sig_1479) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_600' model 'mux'
mux_600 <=
(repeat(32, sig_1458) and sig_1609(31 downto 0));
-- Behaviour of component 'mux_593' model 'mux'
mux_593 <=
(repeat(32, sig_1240) and mux_870) or
(repeat(32, sig_1317) and sig_1614(31 downto 0));
-- Behaviour of component 'mux_587' model 'mux'
mux_587 <=
(repeat(32, sig_1335) and sig_1609(31 downto 0));
-- Behaviour of component 'mux_585' model 'mux'
mux_585 <=
(repeat(16, sig_1337) and read_word) or
(repeat(16, sig_1339) and "00000000" & read_byte);
-- Behaviour of component 'mux_580' model 'mux'
mux_580 <=
(repeat(8, sig_1346) and read_byte) or
(repeat(8, sig_1348) and next_marker);
-- Behaviour of component 'mux_569' model 'mux'
mux_569 <=
(repeat(8, sig_1027) and decodehuffmcu_bufdim1 & "000000") or
(repeat(8, sig_1268) and decodehuffmcu_bufdim1 & decodehuffmcu_k(5 downto 0)) or
(repeat(8, sig_1436) and decode_block_in_buf_idx & sig_1630);
-- Behaviour of component 'mux_567' model 'mux'
mux_567 <=
(repeat(32, sig_1257) and sig_1610(31 downto 0)) or
(repeat(32, sig_1000) and decodehuffmcu_diff) or
(repeat(32, sig_1202) and buf_getv) or
(repeat(32, sig_1267) and or_866);
-- Behaviour of component 'mux_568' model 'mux'
mux_568 <=
(repeat(8, sig_1266) and decodehuffmcu_bufdim1 & decodehuffmcu_k(5 downto 0)) or
(repeat(8, sig_1000) and decodehuffmcu_bufdim1 & "000000") or
(repeat(8, sig_1443) and decodehuffmcu_bufdim1 & decodehuffmcu_i(5 downto 0)) or
(repeat(8, sig_1429) and decode_start_i(1 downto 0) & "000000");
-- Behaviour of component 'mux_563' model 'mux'
mux_563 <=
(repeat(9, sig_1555) and decode_block_out_buf_idx & "011000") or
(repeat(9, sig_1408) and decode_block_out_buf_idx & "001010") or
(repeat(9, sig_1407) and decode_block_out_buf_idx & "101010") or
(repeat(9, sig_1405) and decode_block_out_buf_idx & "010100") or
(repeat(9, sig_1403) and decode_block_out_buf_idx & "110101") or
(repeat(9, sig_1401) and decode_block_out_buf_idx & "111000") or
(repeat(9, sig_1510) and decode_block_out_buf_idx & "101000") or
(repeat(9, sig_1389) and decode_block_out_buf_idx & "011001") or
(repeat(9, sig_1388) and decode_block_out_buf_idx & "100110") or
(repeat(9, sig_1384) and decode_block_out_buf_idx & "111010") or
(repeat(9, sig_1382) and decode_block_out_buf_idx & "111011") or
(repeat(9, sig_1381) and decode_block_out_buf_idx & "111100") or
(repeat(9, sig_1377) and decode_block_out_buf_idx & "000100") or
(repeat(9, sig_1375) and decode_block_out_buf_idx & "100100") or
(repeat(9, sig_1372) and decode_block_out_buf_idx & "010010") or
(repeat(9, sig_1512) and decode_block_out_buf_idx & "000001") or
(repeat(9, sig_1515) and decode_block_out_buf_idx & "011110") or
(repeat(9, sig_1517) and decode_block_out_buf_idx & "011100") or
(repeat(9, sig_1418) and decode_block_out_buf_idx & "111101") or
(repeat(9, sig_1417) and decode_block_out_buf_idx & "100010") or
(repeat(9, sig_1415) and decode_block_out_buf_idx & "010111") or
(repeat(9, sig_1414) and decode_block_out_buf_idx & chenidct_aidx(5 downto 0)) or
(repeat(9, sig_1451) and decode_block_out_buf_idx & chenidct_i(5 downto 0)) or
(repeat(9, sig_1469) and decode_block_out_buf_idx & "010000") or
(repeat(9, sig_1370) and decode_block_out_buf_idx & "000111") or
(repeat(9, sig_1368) and decode_block_out_buf_idx & "001100") or
(repeat(9, sig_1366) and decode_block_out_buf_idx & "111111") or
(repeat(9, sig_1365) and decode_block_out_buf_idx & "101100") or
(repeat(9, sig_1362) and decode_block_out_buf_idx & "110010") or
(repeat(9, sig_1331) and decode_block_out_buf_idx & "000101") or
(repeat(9, sig_1330) and decode_block_out_buf_idx & "010001") or
(repeat(9, sig_1328) and decode_block_out_buf_idx & "001111") or
(repeat(9, sig_1326) and decode_block_out_buf_idx & "100111") or
(repeat(9, sig_1299) and yuvtorgb_yidx & yuvtorgb_i(5 downto 0)) or
(repeat(9, sig_1281) and decode_block_out_buf_idx & "011101") or
(repeat(9, sig_1279) and decode_block_out_buf_idx & "101110") or
(repeat(9, sig_1278) and decode_block_out_buf_idx & "110110") or
(repeat(9, sig_1265) and decode_block_out_buf_idx & "001110") or
(repeat(9, sig_1261) and decode_block_out_buf_idx & "001001") or
(repeat(9, sig_1238) and decode_block_out_buf_idx & "010110") or
(repeat(9, sig_1232) and decode_block_out_buf_idx & "001011") or
(repeat(9, sig_1177) and decode_block_out_buf_idx & "111110") or
(repeat(9, sig_1174) and decode_block_out_buf_idx & "100001") or
(repeat(9, sig_1171) and decode_block_out_buf_idx & "011111") or
(repeat(9, sig_1159) and decode_block_out_buf_idx & "000000") or
(repeat(9, sig_1157) and decode_block_out_buf_idx & "100000") or
(repeat(9, sig_1153) and decode_block_out_buf_idx & "000010") or
(repeat(9, sig_1151) and decode_block_out_buf_idx & "010101") or
(repeat(9, sig_1146) and decode_block_out_buf_idx & "101001") or
(repeat(9, sig_1144) and decode_block_out_buf_idx & "110111") or
(repeat(9, sig_1141) and decode_block_out_buf_idx & "001000") or
(repeat(9, sig_1137) and decode_block_out_buf_idx & "101011") or
(repeat(9, sig_1134) and decode_block_out_buf_idx & "111001") or
(repeat(9, sig_1132) and decode_block_out_buf_idx & "000110") or
(repeat(9, sig_1130) and decode_block_out_buf_idx & "011010") or
(repeat(9, sig_1126) and decode_block_out_buf_idx & "100101") or
(repeat(9, sig_1124) and decode_block_out_buf_idx & "011011") or
(repeat(9, sig_1122) and decode_block_out_buf_idx & "000011") or
(repeat(9, sig_1120) and decode_block_out_buf_idx & "100011") or
(repeat(9, sig_1116) and decode_block_out_buf_idx & "001101") or
(repeat(9, sig_1114) and decode_block_out_buf_idx & "101101") or
(repeat(9, sig_1108) and decode_block_out_buf_idx & "110011") or
(repeat(9, sig_1107) and decode_block_out_buf_idx & "010011") or
(repeat(9, sig_1104) and decode_block_out_buf_idx & "110100") or
(repeat(9, sig_1102) and decode_block_out_buf_idx & "110000") or
(repeat(9, sig_1096) and decode_block_out_buf_idx & "101111") or
(repeat(9, sig_1095) and decode_block_out_buf_idx & "110001") or
(repeat(9, sig_1088) and decode_block_out_buf_idx & chenidct_i(2 downto 0) & "000");
-- Behaviour of component 'mux_565' model 'mux'
mux_565 <=
(repeat(9, sig_1088) and decode_block_out_buf_idx & chenidct_i(2 downto 0) & "001") or
(repeat(9, sig_1299) and yuvtorgb_vidx & yuvtorgb_i(5 downto 0));
-- Behaviour of component 'mux_561' model 'mux'
mux_561 <=
(repeat(32, sig_1556) and sig_1610(24 downto 0) & sig_1642(6 downto 0)) or
(repeat(32, sig_1400) and mux_817) or
(repeat(32, sig_1399) and mux_819) or
(repeat(32, sig_1395) and sig_1609(31 downto 0)) or
(repeat(32, sig_1392) and sig_1614(31 downto 0)) or
(repeat(32, sig_1390) and mux_821) or
(repeat(32, sig_1416) and mux_807) or
(repeat(32, sig_1387) and mux_823) or
(repeat(32, sig_1386) and mux_825) or
(repeat(32, sig_1385) and mux_827) or
(repeat(32, sig_1383) and mux_829) or
(repeat(32, sig_1380) and mux_831) or
(repeat(32, sig_1379) and mux_833) or
(repeat(32, sig_1378) and mux_835) or
(repeat(32, sig_1374) and mux_837) or
(repeat(32, sig_1419) and mux_805) or
(repeat(32, sig_1513) and mux_797) or
(repeat(32, sig_1516) and mux_795) or
(repeat(32, sig_1409) and mux_809) or
(repeat(32, sig_1406) and mux_811) or
(repeat(32, sig_1404) and mux_813) or
(repeat(32, sig_1402) and mux_815) or
(repeat(32, sig_1451) and sig_992) or
(repeat(32, sig_1475) and mux_776) or
(repeat(32, sig_1373) and mux_839) or
(repeat(32, sig_1369) and mux_841) or
(repeat(32, sig_1364) and mux_843) or
(repeat(32, sig_1329) and mux_856) or
(repeat(32, sig_1327) and mux_858) or
(repeat(32, sig_1263) and sig_1610(31 downto 0)) or
(repeat(32, sig_1176) and mux_888) or
(repeat(32, sig_1175) and mux_890) or
(repeat(32, sig_1173) and mux_892) or
(repeat(32, sig_1172) and mux_894) or
(repeat(32, sig_1160) and mux_898) or
(repeat(32, sig_1158) and mux_900) or
(repeat(32, sig_1154) and mux_902) or
(repeat(32, sig_1152) and mux_904) or
(repeat(32, sig_1150) and mux_906) or
(repeat(32, sig_1149) and mux_908) or
(repeat(32, sig_1148) and mux_910) or
(repeat(32, sig_1147) and mux_912) or
(repeat(32, sig_1145) and mux_914) or
(repeat(32, sig_1143) and mux_916) or
(repeat(32, sig_1142) and mux_918) or
(repeat(32, sig_1140) and mux_920) or
(repeat(32, sig_1139) and mux_922) or
(repeat(32, sig_1138) and mux_924) or
(repeat(32, sig_1136) and mux_926) or
(repeat(32, sig_1135) and mux_928) or
(repeat(32, sig_1133) and mux_930) or
(repeat(32, sig_1131) and mux_932) or
(repeat(32, sig_1129) and mux_934) or
(repeat(32, sig_1128) and mux_936) or
(repeat(32, sig_1127) and mux_938) or
(repeat(32, sig_1125) and mux_940) or
(repeat(32, sig_1123) and mux_942) or
(repeat(32, sig_1121) and mux_944) or
(repeat(32, sig_1119) and mux_946) or
(repeat(32, sig_1117) and mux_948) or
(repeat(32, sig_1115) and mux_950) or
(repeat(32, sig_1113) and mux_952) or
(repeat(32, sig_1109) and mux_954) or
(repeat(32, sig_1106) and mux_956) or
(repeat(32, sig_1105) and mux_958) or
(repeat(32, sig_1103) and mux_960) or
(repeat(32, sig_1031) and mux_980) or
(repeat(32, sig_1003) and mux_986) or
(repeat(32, sig_1002) and mux_988);
-- Behaviour of component 'mux_562' model 'mux'
mux_562 <=
(repeat(9, sig_1555) and decode_block_out_buf_idx & "011000") or
(repeat(9, sig_1407) and decode_block_out_buf_idx & "101010") or
(repeat(9, sig_1405) and decode_block_out_buf_idx & "010100") or
(repeat(9, sig_1403) and decode_block_out_buf_idx & "110101") or
(repeat(9, sig_1401) and decode_block_out_buf_idx & "111000") or
(repeat(9, sig_1391) and decode_block_out_buf_idx & chenidct_aidx(5 downto 0)) or
(repeat(9, sig_1510) and decode_block_out_buf_idx & "101000") or
(repeat(9, sig_1389) and decode_block_out_buf_idx & "011001") or
(repeat(9, sig_1388) and decode_block_out_buf_idx & "100110") or
(repeat(9, sig_1384) and decode_block_out_buf_idx & "111010") or
(repeat(9, sig_1382) and decode_block_out_buf_idx & "111011") or
(repeat(9, sig_1381) and decode_block_out_buf_idx & "111100") or
(repeat(9, sig_1377) and decode_block_out_buf_idx & "000100") or
(repeat(9, sig_1375) and decode_block_out_buf_idx & "100100") or
(repeat(9, sig_1372) and decode_block_out_buf_idx & "010010") or
(repeat(9, sig_1512) and decode_block_out_buf_idx & "000001") or
(repeat(9, sig_1515) and decode_block_out_buf_idx & "011110") or
(repeat(9, sig_1517) and decode_block_out_buf_idx & "011100") or
(repeat(9, sig_1418) and decode_block_out_buf_idx & "111101") or
(repeat(9, sig_1417) and decode_block_out_buf_idx & "100010") or
(repeat(9, sig_1415) and decode_block_out_buf_idx & "010111") or
(repeat(9, sig_1408) and decode_block_out_buf_idx & "001010") or
(repeat(9, sig_1450) and decode_block_out_buf_idx & chenidct_i(5 downto 0)) or
(repeat(9, sig_1469) and decode_block_out_buf_idx & "010000") or
(repeat(9, sig_1370) and decode_block_out_buf_idx & "000111") or
(repeat(9, sig_1368) and decode_block_out_buf_idx & "001100") or
(repeat(9, sig_1366) and decode_block_out_buf_idx & "111111") or
(repeat(9, sig_1365) and decode_block_out_buf_idx & "101100") or
(repeat(9, sig_1362) and decode_block_out_buf_idx & "110010") or
(repeat(9, sig_1331) and decode_block_out_buf_idx & "000101") or
(repeat(9, sig_1330) and decode_block_out_buf_idx & "010001") or
(repeat(9, sig_1328) and decode_block_out_buf_idx & "001111") or
(repeat(9, sig_1326) and decode_block_out_buf_idx & "100111") or
(repeat(9, sig_1281) and decode_block_out_buf_idx & "011101") or
(repeat(9, sig_1279) and decode_block_out_buf_idx & "101110") or
(repeat(9, sig_1278) and decode_block_out_buf_idx & "110110") or
(repeat(9, sig_1265) and decode_block_out_buf_idx & "001110") or
(repeat(9, sig_1261) and decode_block_out_buf_idx & "001001") or
(repeat(9, sig_1238) and decode_block_out_buf_idx & "010110") or
(repeat(9, sig_1232) and decode_block_out_buf_idx & "001011") or
(repeat(9, sig_1177) and decode_block_out_buf_idx & "111110") or
(repeat(9, sig_1174) and decode_block_out_buf_idx & "100001") or
(repeat(9, sig_1171) and decode_block_out_buf_idx & "011111") or
(repeat(9, sig_1159) and decode_block_out_buf_idx & "000000") or
(repeat(9, sig_1157) and decode_block_out_buf_idx & "100000") or
(repeat(9, sig_1153) and decode_block_out_buf_idx & "000010") or
(repeat(9, sig_1151) and decode_block_out_buf_idx & "010101") or
(repeat(9, sig_1146) and decode_block_out_buf_idx & "101001") or
(repeat(9, sig_1144) and decode_block_out_buf_idx & "110111") or
(repeat(9, sig_1141) and decode_block_out_buf_idx & "001000") or
(repeat(9, sig_1137) and decode_block_out_buf_idx & "101011") or
(repeat(9, sig_1134) and decode_block_out_buf_idx & "111001") or
(repeat(9, sig_1132) and decode_block_out_buf_idx & "000110") or
(repeat(9, sig_1130) and decode_block_out_buf_idx & "011010") or
(repeat(9, sig_1126) and decode_block_out_buf_idx & "100101") or
(repeat(9, sig_1124) and decode_block_out_buf_idx & "011011") or
(repeat(9, sig_1122) and decode_block_out_buf_idx & "000011") or
(repeat(9, sig_1120) and decode_block_out_buf_idx & "100011") or
(repeat(9, sig_1116) and decode_block_out_buf_idx & "001101") or
(repeat(9, sig_1114) and decode_block_out_buf_idx & "101101") or
(repeat(9, sig_1108) and decode_block_out_buf_idx & "110011") or
(repeat(9, sig_1107) and decode_block_out_buf_idx & "010011") or
(repeat(9, sig_1104) and decode_block_out_buf_idx & "110100") or
(repeat(9, sig_1102) and decode_block_out_buf_idx & "110000") or
(repeat(9, sig_1096) and decode_block_out_buf_idx & "101111") or
(repeat(9, sig_1095) and decode_block_out_buf_idx & "110001") or
(repeat(9, sig_1087) and decode_block_out_buf_idx & chenidct_i(2 downto 0) & "000") or
(repeat(9, sig_1083) and decode_block_out_buf_idx & chenidct_i(2 downto 0) & "001");
-- Behaviour of component 'mux_557' model 'mux'
mux_557 <=
(repeat(32, sig_1436) and sig_1643) or
(repeat(32, sig_1433) and sig_1628(31 downto 0));
-- Behaviour of component 'mux_558' model 'mux'
mux_558 <=
(repeat(6, sig_1564) and "000101") or
(repeat(6, sig_1321) and "110001") or
(repeat(6, sig_1320) and "000110") or
(repeat(6, sig_1315) and "010101") or
(repeat(6, sig_1311) and "011111") or
(repeat(6, sig_1301) and "100101") or
(repeat(6, sig_1367) and "111010") or
(repeat(6, sig_1293) and "100111") or
(repeat(6, sig_1277) and "000010") or
(repeat(6, sig_1276) and "111001") or
(repeat(6, sig_1275) and "010001") or
(repeat(6, sig_1270) and "110000") or
(repeat(6, sig_1260) and "101001") or
(repeat(6, sig_1259) and "111100") or
(repeat(6, sig_1258) and "011000") or
(repeat(6, sig_1371) and "110111") or
(repeat(6, sig_1410) and "011001") or
(repeat(6, sig_1508) and "001101") or
(repeat(6, sig_1361) and "101100") or
(repeat(6, sig_1359) and "001000") or
(repeat(6, sig_1358) and "101011") or
(repeat(6, sig_1436) and izigzagmatrix_out_idx(5 downto 0)) or
(repeat(6, sig_1432) and "010010") or
(repeat(6, sig_1256) and "010110") or
(repeat(6, sig_1255) and "000011") or
(repeat(6, sig_1246) and "100011") or
(repeat(6, sig_1239) and "100001") or
(repeat(6, sig_1235) and "100100") or
(repeat(6, sig_1231) and "100110") or
(repeat(6, sig_1230) and "100000") or
(repeat(6, sig_1228) and "110101") or
(repeat(6, sig_1227) and "101101") or
(repeat(6, sig_1226) and "011110") or
(repeat(6, sig_1225) and "000100") or
(repeat(6, sig_1223) and "000111") or
(repeat(6, sig_1222) and "110110") or
(repeat(6, sig_1221) and "011101") or
(repeat(6, sig_1220) and "101110") or
(repeat(6, sig_1166) and "001110") or
(repeat(6, sig_1164) and "110100") or
(repeat(6, sig_1156) and "010100") or
(repeat(6, sig_1155) and "101010") or
(repeat(6, sig_1099) and "011010") or
(repeat(6, sig_1098) and "101111") or
(repeat(6, sig_1097) and "010011") or
(repeat(6, sig_1094) and "010111") or
(repeat(6, sig_1093) and "111000") or
(repeat(6, sig_1092) and "011100") or
(repeat(6, sig_1091) and "000001") or
(repeat(6, sig_1090) and "001001") or
(repeat(6, sig_1086) and "001011") or
(repeat(6, sig_1085) and "110010") or
(repeat(6, sig_1084) and "010000") or
(repeat(6, sig_1079) and "001111") or
(repeat(6, sig_1076) and "001010") or
(repeat(6, sig_1075) and "110011") or
(repeat(6, sig_1074) and "111111") or
(repeat(6, sig_1071) and "011011") or
(repeat(6, sig_1063) and "001100") or
(repeat(6, sig_1054) and "101000") or
(repeat(6, sig_1050) and "100010") or
(repeat(6, sig_1028) and "111101") or
(repeat(6, sig_1022) and "111110") or
(repeat(6, sig_1007) and "111011");
-- Behaviour of component 'mux_559' model 'mux'
mux_559 <=
(repeat(6, sig_1581) and chenidct_i(5 downto 0)) or
(repeat(6, sig_1358) and "101011") or
(repeat(6, sig_1321) and "110001") or
(repeat(6, sig_1320) and "000110") or
(repeat(6, sig_1315) and "010101") or
(repeat(6, sig_1311) and "011111") or
(repeat(6, sig_1371) and "110111") or
(repeat(6, sig_1301) and "100101") or
(repeat(6, sig_1293) and "100111") or
(repeat(6, sig_1277) and "000010") or
(repeat(6, sig_1276) and "111001") or
(repeat(6, sig_1275) and "010001") or
(repeat(6, sig_1270) and "110000") or
(repeat(6, sig_1260) and "101001") or
(repeat(6, sig_1259) and "111100") or
(repeat(6, sig_1410) and "011001") or
(repeat(6, sig_1508) and "001101") or
(repeat(6, sig_1564) and "000101") or
(repeat(6, sig_1367) and "111010") or
(repeat(6, sig_1361) and "101100") or
(repeat(6, sig_1359) and "001000") or
(repeat(6, sig_1473) and chenidct_aidx(5 downto 0)) or
(repeat(6, sig_1432) and "010010") or
(repeat(6, sig_1258) and "011000") or
(repeat(6, sig_1256) and "010110") or
(repeat(6, sig_1255) and "000011") or
(repeat(6, sig_1246) and "100011") or
(repeat(6, sig_1239) and "100001") or
(repeat(6, sig_1235) and "100100") or
(repeat(6, sig_1231) and "100110") or
(repeat(6, sig_1230) and "100000") or
(repeat(6, sig_1228) and "110101") or
(repeat(6, sig_1227) and "101101") or
(repeat(6, sig_1226) and "011110") or
(repeat(6, sig_1225) and "000100") or
(repeat(6, sig_1223) and "000111") or
(repeat(6, sig_1222) and "110110") or
(repeat(6, sig_1221) and "011101") or
(repeat(6, sig_1220) and "101110") or
(repeat(6, sig_1166) and "001110") or
(repeat(6, sig_1164) and "110100") or
(repeat(6, sig_1156) and "010100") or
(repeat(6, sig_1155) and "101010") or
(repeat(6, sig_1099) and "011010") or
(repeat(6, sig_1098) and "101111") or
(repeat(6, sig_1097) and "010011") or
(repeat(6, sig_1094) and "010111") or
(repeat(6, sig_1093) and "111000") or
(repeat(6, sig_1092) and "011100") or
(repeat(6, sig_1091) and "000001") or
(repeat(6, sig_1090) and "001001") or
(repeat(6, sig_1086) and "001011") or
(repeat(6, sig_1085) and "110010") or
(repeat(6, sig_1084) and "010000") or
(repeat(6, sig_1079) and "001111") or
(repeat(6, sig_1076) and "001010") or
(repeat(6, sig_1075) and "110011") or
(repeat(6, sig_1074) and "111111") or
(repeat(6, sig_1071) and "011011") or
(repeat(6, sig_1063) and "001100") or
(repeat(6, sig_1054) and "101000") or
(repeat(6, sig_1050) and "100010") or
(repeat(6, sig_1028) and "111101") or
(repeat(6, sig_1022) and "111110") or
(repeat(6, sig_1007) and "111011");
-- Behaviour of component 'mux_555' model 'mux'
mux_555 <=
(repeat(32, sig_1396) and sig_1613) or
(repeat(32, sig_1449) and sig_1612(31 downto 0));
-- Behaviour of component 'mux_551' model 'mux'
mux_551 <=
(repeat(32, sig_1118) and sig_1587(39 downto 8)) or
(repeat(32, sig_1088) and sig_1640) or
(repeat(32, sig_1332) and sig_1639(29 downto 0) & "00") or
(repeat(32, sig_1463) and sig_1609(31 downto 0));
-- Behaviour of component 'mux_553' model 'mux'
mux_553 <=
(repeat(32, sig_1411) and sig_1610(31 downto 0)) or
(repeat(32, sig_1111) and sig_1609(28 downto 0) & chenidct_aidx(2 downto 0)) or
(repeat(32, sig_1262) and sig_1609(31 downto 0)) or
(repeat(32, sig_1582) and sig_1610(28 downto 0) & chenidct_i(2 downto 0)) or
(repeat(32, sig_1477) and sig_1610(28 downto 0) & chenidct_aidx(2 downto 0));
-- Behaviour of component 'mux_549' model 'mux'
mux_549 <=
(repeat(32, sig_1323) and sig_1639(29 downto 0) & "00") or
(repeat(32, sig_1274) and sig_1642) or
(repeat(32, sig_1324) and sig_1587(39 downto 8)) or
(repeat(32, sig_1463) and sig_1614(31 downto 0));
-- Behaviour of component 'mux_545' model 'mux'
mux_545 <=
(repeat(32, sig_1118) and sig_1612(38 downto 7)) or
(repeat(32, sig_1040) and sig_1639(29 downto 0) & "00") or
(repeat(32, sig_1351) and sig_1642) or
(repeat(32, sig_1463) and sig_1613);
-- Behaviour of component 'mux_547' model 'mux'
mux_547 <=
(repeat(32, sig_1349) and sig_1614(40 downto 9)) or
(repeat(32, sig_1001) and sig_1639(29 downto 0) & "00") or
(repeat(32, sig_1413) and sig_1642) or
(repeat(32, sig_1463) and sig_1624(31 downto 0));
-- Behaviour of component 'mux_543' model 'mux'
mux_543 <=
(repeat(32, sig_1088) and sig_1642) or
(repeat(32, sig_1581) and sig_1639(29 downto 0) & "00") or
(repeat(32, sig_1463) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_731' model 'mux'
mux_731 <=
(repeat(8, sig_1508) and iquantize_qidx & "001101") or
(repeat(8, sig_1320) and iquantize_qidx & "000110") or
(repeat(8, sig_1315) and iquantize_qidx & "010101") or
(repeat(8, sig_1311) and iquantize_qidx & "011111") or
(repeat(8, sig_1301) and iquantize_qidx & "100101") or
(repeat(8, sig_1293) and iquantize_qidx & "100111") or
(repeat(8, sig_1361) and iquantize_qidx & "101100") or
(repeat(8, sig_1277) and iquantize_qidx & "000010") or
(repeat(8, sig_1276) and iquantize_qidx & "111001") or
(repeat(8, sig_1275) and iquantize_qidx & "010001") or
(repeat(8, sig_1270) and iquantize_qidx & "110000") or
(repeat(8, sig_1260) and iquantize_qidx & "101001") or
(repeat(8, sig_1259) and iquantize_qidx & "111100") or
(repeat(8, sig_1258) and iquantize_qidx & "011000") or
(repeat(8, sig_1256) and iquantize_qidx & "010110") or
(repeat(8, sig_1367) and iquantize_qidx & "111010") or
(repeat(8, sig_1371) and iquantize_qidx & "110111") or
(repeat(8, sig_1410) and iquantize_qidx & "011001") or
(repeat(8, sig_1360) and iquantize_qidx & "000000") or
(repeat(8, sig_1359) and iquantize_qidx & "001000") or
(repeat(8, sig_1358) and iquantize_qidx & "101011") or
(repeat(8, sig_1321) and iquantize_qidx & "110001") or
(repeat(8, sig_1564) and iquantize_qidx & "000101") or
(repeat(8, sig_1432) and iquantize_qidx & "010010") or
(repeat(8, sig_1255) and iquantize_qidx & "000011") or
(repeat(8, sig_1246) and iquantize_qidx & "100011") or
(repeat(8, sig_1239) and iquantize_qidx & "100001") or
(repeat(8, sig_1235) and iquantize_qidx & "100100") or
(repeat(8, sig_1231) and iquantize_qidx & "100110") or
(repeat(8, sig_1230) and iquantize_qidx & "100000") or
(repeat(8, sig_1228) and iquantize_qidx & "110101") or
(repeat(8, sig_1227) and iquantize_qidx & "101101") or
(repeat(8, sig_1226) and iquantize_qidx & "011110") or
(repeat(8, sig_1225) and iquantize_qidx & "000100") or
(repeat(8, sig_1223) and iquantize_qidx & "000111") or
(repeat(8, sig_1222) and iquantize_qidx & "110110") or
(repeat(8, sig_1221) and iquantize_qidx & "011101") or
(repeat(8, sig_1220) and iquantize_qidx & "101110") or
(repeat(8, sig_1166) and iquantize_qidx & "001110") or
(repeat(8, sig_1164) and iquantize_qidx & "110100") or
(repeat(8, sig_1156) and iquantize_qidx & "010100") or
(repeat(8, sig_1155) and iquantize_qidx & "101010") or
(repeat(8, sig_1099) and iquantize_qidx & "011010") or
(repeat(8, sig_1098) and iquantize_qidx & "101111") or
(repeat(8, sig_1097) and iquantize_qidx & "010011") or
(repeat(8, sig_1094) and iquantize_qidx & "010111") or
(repeat(8, sig_1093) and iquantize_qidx & "111000") or
(repeat(8, sig_1092) and iquantize_qidx & "011100") or
(repeat(8, sig_1091) and iquantize_qidx & "000001") or
(repeat(8, sig_1090) and iquantize_qidx & "001001") or
(repeat(8, sig_1086) and iquantize_qidx & "001011") or
(repeat(8, sig_1085) and iquantize_qidx & "110010") or
(repeat(8, sig_1084) and iquantize_qidx & "010000") or
(repeat(8, sig_1079) and iquantize_qidx & "001111") or
(repeat(8, sig_1076) and iquantize_qidx & "001010") or
(repeat(8, sig_1075) and iquantize_qidx & "110011") or
(repeat(8, sig_1074) and iquantize_qidx & "111111") or
(repeat(8, sig_1071) and iquantize_qidx & "011011") or
(repeat(8, sig_1063) and iquantize_qidx & "001100") or
(repeat(8, sig_1054) and iquantize_qidx & "101000") or
(repeat(8, sig_1050) and iquantize_qidx & "100010") or
(repeat(8, sig_1028) and iquantize_qidx & "111101") or
(repeat(8, sig_1022) and iquantize_qidx & "111110") or
(repeat(8, sig_1007) and iquantize_qidx & "111011");
-- Behaviour of component 'mux_727' model 'mux'
mux_727 <=
(repeat(7, sig_1534) and huff_make_dhuff_tb_dc_tbl_no & huff_make_dhuff_tb_dc_i_c0(5 downto 0)) or
(repeat(7, sig_1552) and huff_make_dhuff_tb_dc_tbl_no & huff_make_dhuff_tb_dc_l(5 downto 0)) or
(repeat(7, sig_1458) and get_dht_index & get_dht_i(5 downto 0));
-- Behaviour of component 'mux_723' model 'mux'
mux_723 <=
(repeat(10, sig_1304) and decodehuffman_dc_tbl_no & decodehuffman_dc_p) or
(repeat(10, sig_1480) and get_dht_index & get_dht_i(8 downto 0));
-- Behaviour of component 'mux_719' model 'mux'
mux_719 <=
(repeat(7, sig_1505) and huff_make_dhuff_tb_ac_tbl_no & huff_make_dhuff_tb_ac_i_c0(5 downto 0)) or
(repeat(7, sig_1547) and huff_make_dhuff_tb_ac_tbl_no & huff_make_dhuff_tb_ac_l(5 downto 0)) or
(repeat(7, sig_1458) and get_dht_index & get_dht_i(5 downto 0));
-- Behaviour of component 'mux_539' model 'mux'
mux_539 <=
(repeat(32, sig_1118) and sig_1624(31 downto 0)) or
(repeat(32, sig_1354) and sig_1642) or
(repeat(32, sig_1472) and sig_1639(29 downto 0) & "00");
-- Behaviour of component 'mux_541' model 'mux'
mux_541 <=
(repeat(32, sig_999) and sig_1639(29 downto 0) & "00") or
(repeat(32, sig_1118) and sig_1613) or
(repeat(32, sig_1357) and sig_1642);
-- Behaviour of component 'mux_537' model 'mux'
mux_537 <=
(repeat(32, sig_1285) and sig_1642) or
(repeat(32, sig_1325) and sig_1639(29 downto 0) & "00") or
(repeat(32, sig_1463) and sig_1621(31 downto 0));
-- Behaviour of component 'mux_533' model 'mux'
mux_533 <=
(repeat(32, sig_1324) and sig_1614(40 downto 9)) or
(repeat(32, sig_1395) and sig_1627(39 downto 8));
-- Behaviour of component 'mux_535' model 'mux'
mux_535 <=
(repeat(32, sig_1118) and sig_1614(40 downto 9)) or
(repeat(32, sig_1463) and sig_1609(31 downto 0));
-- Behaviour of component 'mux_715' model 'mux'
mux_715 <=
(repeat(10, sig_1284) and decodehuffman_ac_tbl_no & decodehuffman_ac_p) or
(repeat(10, sig_1480) and get_dht_index & get_dht_i(8 downto 0));
-- Behaviour of component 'mux_711' model 'mux'
mux_711 <=
(sig_1170 and decodehuffmcu_tbl_no) or
(sig_1189 and '1');
-- Behaviour of component 'mux_705' model 'mux'
mux_705 <=
(repeat(32, sig_1271) and sig_1632) or
(repeat(32, sig_1554) and "11111111111111111111111111111111") or
(repeat(32, sig_1561) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_706' model 'mux'
mux_706 <=
(repeat(7, sig_1553) and huff_make_dhuff_tb_dc_tbl_no & huff_make_dhuff_tb_dc_l(5 downto 0)) or
(repeat(7, sig_1561) and huff_make_dhuff_tb_dc_tbl_no & huff_make_dhuff_tb_dc_p_dhtbl_ml(5 downto 0));
-- Behaviour of component 'mux_707' model 'mux'
mux_707 <=
(repeat(7, sig_1561) and huff_make_dhuff_tb_dc_tbl_no & huff_make_dhuff_tb_dc_p_dhtbl_ml(5 downto 0)) or
(repeat(7, sig_1575) and decodehuffman_dc_tbl_no & decodehuffman_dc_l(5 downto 0)) or
(repeat(7, sig_1577) and decodehuffman_dc_tbl_no & decodehuffman_dc_dhuff_ml);
-- Behaviour of component 'mux_531' model 'mux'
mux_531 <=
(repeat(32, sig_1324) and sig_1609(38 downto 7)) or
(repeat(32, sig_1395) and sig_1628(39 downto 8));
-- Behaviour of component 'mux_529' model 'mux'
mux_529 <=
(repeat(32, sig_1118) and sig_1610(38 downto 7)) or
(repeat(32, sig_1463) and sig_1613);
-- Behaviour of component 'mux_695' model 'mux'
mux_695 <=
(sig_1184 and '1') or
(sig_1453 and decodehuffmcu_tbl_no);
-- Behaviour of component 'mux_524' model 'mux'
mux_524 <=
(repeat(5, sig_1310) and decodehuffmcu_s(4 downto 0)) or
(repeat(5, sig_1482) and read_position(4 downto 0));
-- Behaviour of component 'mux_521' model 'mux'
mux_521 <=
(repeat(32, sig_1422) and "000000000000000000000000" & pgetc) or
(repeat(32, sig_1493) and or_802 & pgetc);
-- Behaviour of component 'mux_519' model 'mux'
mux_519 <=
(repeat(32, sig_1484) and sig_1614(31 downto 0)) or
(repeat(32, sig_1355) and sig_1624(31 downto 0)) or
(repeat(32, sig_1421) and "00000000000000000000000000000111") or
(repeat(32, sig_1493) and sig_1610(28 downto 0) & read_position(2 downto 0)) or
(repeat(32, sig_1497) and "11111111111111111111111111111111");
-- Behaviour of component 'mux_517' model 'mux'
mux_517 <=
(repeat(8, sig_1423) and "11111111") or
(repeat(8, sig_1425) and pgetc_temp);
-- Behaviour of component 'mux_507' model 'mux'
mux_507 <=
(repeat(32, sig_1008) and and_984) or
(repeat(32, sig_1345) and and_853) or
(repeat(32, sig_1497) and and_801);
-- Behaviour of component 'mux_505' model 'mux'
mux_505 <=
(repeat(32, sig_1167) and sig_1614(31 downto 0)) or
(repeat(32, sig_1197) and decodehuffmcu_s) or
(repeat(32, sig_1201) and decodehuffman_dc);
-- Behaviour of component 'mux_501' model 'mux'
mux_501 <=
(repeat(32, sig_1355) and or_845) or
(repeat(32, sig_1489) and sig_1626);
-- Behaviour of component 'mux_492' model 'mux'
mux_492 <=
(repeat(32, sig_1186) and sig_1652) or
(repeat(32, sig_1514) and "00000000000000000000000000000001") or
(repeat(32, sig_1544) and huff_make_dhuff_tb_ac_l);
-- Behaviour of component 'mux_488' model 'mux'
mux_488 <=
(repeat(32, sig_1499) and sig_1609(31 downto 0)) or
(repeat(32, sig_1504) and "00000000000000000000000000000001");
-- Behaviour of component 'mux_490' model 'mux'
mux_490 <=
(repeat(32, sig_1498) and "00000000000000000000000000000001") or
(repeat(32, sig_1507) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_486' model 'mux'
mux_486 <=
(repeat(32, sig_1500) and sig_1610(31 downto 0)) or
(repeat(32, sig_1544) and sig_1609(31 downto 0));
-- Behaviour of component 'mux_482' model 'mux'
mux_482 <=
(repeat(32, sig_1283) and sig_1610(31 downto 0)) or
(repeat(32, sig_1558) and sig_1635);
-- Behaviour of component 'mux_484' model 'mux'
mux_484 <=
(repeat(32, sig_1023) and sig_1609(31 downto 0)) or
(repeat(32, sig_1283) and huff_make_dhuff_tb_ac_code(30 downto 0) & '0');
-- Behaviour of component 'mux_480' model 'mux'
mux_480 <=
(repeat(32, sig_1514) and "00000000000000000000000000000001") or
(repeat(32, sig_1525) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_476' model 'mux'
mux_476 <=
(repeat(32, sig_1499) and huff_make_dhuff_tb_ac_i_c0);
-- Behaviour of component 'mux_478' model 'mux'
mux_478 <=
(repeat(9, sig_1511) and huff_make_dhuff_tb_ac_p(8 downto 0));
-- Behaviour of component 'mux_459' model 'mux'
mux_459 <=
(repeat(32, sig_1038) and huff_make_dhuff_tb_dc_l) or
(repeat(32, sig_1305) and sig_1656) or
(repeat(32, sig_1542) and "00000000000000000000000000000001");
-- Behaviour of component 'mux_455' model 'mux'
mux_455 <=
(repeat(32, sig_1527) and sig_1609(31 downto 0)) or
(repeat(32, sig_1533) and "00000000000000000000000000000001");
-- Behaviour of component 'mux_457' model 'mux'
mux_457 <=
(repeat(32, sig_1526) and "00000000000000000000000000000001") or
(repeat(32, sig_1536) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_453' model 'mux'
mux_453 <=
(repeat(32, sig_1038) and sig_1609(31 downto 0)) or
(repeat(32, sig_1528) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_449' model 'mux'
mux_449 <=
(repeat(32, sig_1033) and sig_1633) or
(repeat(32, sig_1068) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_451' model 'mux'
mux_451 <=
(repeat(32, sig_1035) and sig_1609(31 downto 0)) or
(repeat(32, sig_1068) and huff_make_dhuff_tb_dc_code(30 downto 0) & '0');
-- Behaviour of component 'mux_447' model 'mux'
mux_447 <=
(repeat(32, sig_1542) and "00000000000000000000000000000001") or
(repeat(32, sig_1563) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_443' model 'mux'
mux_443 <=
(repeat(32, sig_1527) and huff_make_dhuff_tb_dc_i_c0);
-- Behaviour of component 'mux_445' model 'mux'
mux_445 <=
(repeat(9, sig_1537) and huff_make_dhuff_tb_dc_p(8 downto 0));
-- Behaviour of component 'mux_430' model 'mux'
mux_430 <=
(repeat(32, sig_1284) and sig_1657);
-- Behaviour of component 'mux_422' model 'mux'
mux_422 <=
(repeat(32, sig_1565) and "00000000000000000000000000000001") or
(repeat(32, sig_1567) and sig_1609(31 downto 0));
-- Behaviour of component 'mux_424' model 'mux'
mux_424 <=
(repeat(32, sig_1565) and "0000000000000000000000000000000" & buf_getb) or
(repeat(32, sig_1567) and sig_1610(30 downto 0) & buf_getb);
-- Behaviour of component 'mux_416' model 'mux'
mux_416 <=
(repeat(32, sig_1304) and sig_1659);
-- Behaviour of component 'mux_410' model 'mux'
mux_410 <=
(repeat(32, sig_1571) and "0000000000000000000000000000000" & buf_getb) or
(repeat(32, sig_1574) and sig_1610(30 downto 0) & buf_getb);
-- Behaviour of component 'mux_408' model 'mux'
mux_408 <=
(repeat(32, sig_1571) and "00000000000000000000000000000001") or
(repeat(32, sig_1574) and sig_1609(31 downto 0));
-- Behaviour of component 'mux_398' model 'mux'
mux_398 <=
(repeat(32, sig_1026) and sig_1610(31 downto 0)) or
(repeat(32, sig_1341) and buf_getv) or
(repeat(32, sig_1344) and or_854);
-- Behaviour of component 'mux_400' model 'mux'
mux_400 <=
(repeat(32, sig_1030) and and_982) or
(repeat(32, sig_1342) and sig_1614(31 downto 0)) or
(repeat(32, sig_1579) and decodehuffman_dc);
-- Behaviour of component 'mux_392' model 'mux'
mux_392 <=
(repeat(32, sig_1454) and "00000000000000000000000000000001") or
(repeat(32, sig_1466) and sig_1610(31 downto 0)) or
(repeat(32, sig_1464) and sig_1610(27 downto 0) & decodehuffmcu_k(3 downto 0));
-- Behaviour of component 'mux_394' model 'mux'
mux_394 <=
(repeat(32, sig_1443) and sig_1610(31 downto 0)) or
(repeat(32, sig_1445) and "00000000000000000000000000000001");
-- Behaviour of component 'mux_378' model 'mux'
mux_378 <=
(repeat(8, sig_1070) and yuvtorgb_r(7 downto 0)) or
(repeat(8, sig_1234) and yuvtorgb_b(7 downto 0)) or
(repeat(8, sig_1237) and yuvtorgb_g(7 downto 0));
-- Behaviour of component 'mux_379' model 'mux'
mux_379 <=
(repeat(10, sig_1070) and yuvtorgb_p & "00" & yuvtorgb_i(5 downto 0)) or
(repeat(10, sig_1234) and yuvtorgb_p & "10" & yuvtorgb_i(5 downto 0)) or
(repeat(10, sig_1237) and yuvtorgb_p & "01" & yuvtorgb_i(5 downto 0));
-- Behaviour of component 'mux_375' model 'mux'
mux_375 <=
(repeat(2, sig_1020) and write4blocks_i) or
(repeat(2, sig_1196) and decode_start_i(1 downto 0));
-- Behaviour of component 'mux_373' model 'mux'
mux_373 <=
(repeat(2, sig_1005) and "10") or
(repeat(2, sig_1004) and "11") or
(repeat(2, sig_1019) and "01");
-- Behaviour of component 'mux_365' model 'mux'
mux_365 <=
(repeat(32, sig_1005) and sig_1614(31 downto 0)) or
(repeat(32, sig_1021) and sig_1610(28 downto 0) & write4blocks_hoffs(2 downto 0)) or
(repeat(32, sig_1196) and sig_1647(28 downto 0) & "000");
-- Behaviour of component 'mux_367' model 'mux'
mux_367 <=
(repeat(32, sig_1005) and sig_1610(28 downto 0) & write4blocks_voffs(2 downto 0)) or
(repeat(32, sig_1021) and write4blocks_voffs) or
(repeat(32, sig_1196) and sig_1648(28 downto 0) & "000");
-- Behaviour of component 'mux_363' model 'mux'
mux_363 <=
(repeat(32, sig_1018) and sig_1610(31 downto 0)) or
(repeat(32, sig_1065) and writeoneblock_voffs);
-- Behaviour of component 'mux_359' model 'mux'
mux_359 <=
(repeat(32, sig_1012) and sig_1609(31 downto 0));
-- Behaviour of component 'mux_361' model 'mux'
mux_361 <=
(repeat(32, sig_1017) and sig_1610(31 downto 0)) or
(repeat(32, sig_1081) and writeoneblock_hoffs);
-- Behaviour of component 'mux_347' model 'mux'
mux_347 <=
(repeat(32, sig_1005) and sig_1610(28 downto 0) & write4blocks_voffs(2 downto 0)) or
(repeat(32, sig_1194) and sig_1648(28 downto 0) & "000");
-- Behaviour of component 'mux_345' model 'mux'
mux_345 <=
(repeat(32, sig_1005) and sig_1614(31 downto 0)) or
(repeat(32, sig_1021) and sig_1610(28 downto 0) & write4blocks_hoffs(2 downto 0)) or
(repeat(32, sig_1194) and sig_1647(28 downto 0) & "000");
-- Behaviour of component 'mux_341' model 'mux'
mux_341 <=
(repeat(3, sig_993) and decode_start_i(2 downto 0));
-- Behaviour of component 'mux_343' model 'mux'
mux_343 <=
(repeat(2, sig_993) and decode_start_i(1 downto 0));
-- Behaviour of component 'mux_339' model 'mux'
mux_339 <=
(repeat(3, sig_993) and "100") or
(repeat(3, sig_997) and "001");
-- Behaviour of component 'mux_335' model 'mux'
mux_335 <=
(repeat(32, sig_1060) and mux_965) or
(repeat(32, sig_1217) and sig_1611(24) & sig_1611(24) & sig_1611(24) & sig_1611(24) & sig_1611(24) & sig_1611(24) & sig_1611(24) & sig_1611(24) & sig_1611(24 downto 1));
-- Behaviour of component 'mux_337' model 'mux'
mux_337 <=
(repeat(3, sig_993) and "101") or
(repeat(3, sig_997) and "010");
-- Behaviour of component 'mux_333' model 'mux'
mux_333 <=
(repeat(32, sig_1060) and mux_969) or
(repeat(32, sig_1217) and sig_1610(24) & sig_1610(24) & sig_1610(24) & sig_1610(24) & sig_1610(24) & sig_1610(24) & sig_1610(24) & sig_1610(24) & sig_1610(24 downto 1));
-- Behaviour of component 'mux_331' model 'mux'
mux_331 <=
(repeat(32, sig_1060) and mux_967) or
(repeat(32, sig_1217) and sig_1613(24) & sig_1613(24) & sig_1613(24) & sig_1613(24) & sig_1613(24) & sig_1613(24) & sig_1613(24) & sig_1613(24) & sig_1613(24 downto 1));
-- Behaviour of component 'mux_323' model 'mux'
mux_323 <=
(repeat(6, sig_1345) and buf_getv_p(5 downto 0)) or
(repeat(6, sig_1355) and sig_1614(5 downto 0));
-- Behaviour of component 'mux_320' model 'mux'
mux_320 <=
(repeat(32, sig_1234) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_322' model 'mux'
mux_322 <=
(repeat(32, sig_1345) and current_read_byte) or
(repeat(32, sig_1355) and "000000000000000000000000" & pgetc);
-- Behaviour of component 'mux_317' model 'mux'
mux_317 <=
(repeat(2, sig_995) and "01") or
(repeat(2, sig_994) and "10") or
(repeat(2, sig_1045) and decode_start_i(1 downto 0));
-- Behaviour of component 'mux_314' model 'mux'
mux_314 <=
(repeat(32, sig_1324) and chenidct_a2) or
(repeat(32, sig_1118) and chenidct_a3) or
(repeat(32, sig_1217) and yuvtorgb_v(30) & yuvtorgb_v(30 downto 0)) or
(repeat(32, sig_1349) and chenidct_b3) or
(repeat(32, sig_1395) and sig_1614(31 downto 0));
-- Behaviour of component 'mux_315' model 'mux'
mux_315 <=
(repeat(32, sig_1349) and "00000000000000000000000000110001") or
(repeat(32, sig_1101) and p_jinfo_mcuwidth) or
(repeat(32, sig_1118) and "00000000000000000000000000011001") or
(repeat(32, sig_1217) and "00000000000000000000000000001011") or
(repeat(32, sig_1324) and "00000000000000000000000011010101") or
(repeat(32, sig_1081) and writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12 downto 0)) or
(repeat(32, sig_1395) and "00000000000000000000000010110101") or
(repeat(32, sig_1433) and sig_1661);
-- Behaviour of component 'mux_316' model 'mux'
mux_316 <=
(repeat(32, sig_1349) and chenidct_b2) or
(repeat(32, sig_1101) and p_jinfo_mcuheight) or
(repeat(32, sig_1118) and chenidct_a0) or
(repeat(32, sig_1217) and yuvtorgb_u(28) & yuvtorgb_u(28) & yuvtorgb_u(28) & yuvtorgb_u(28 downto 0)) or
(repeat(32, sig_1324) and chenidct_a1) or
(repeat(32, sig_1081) and writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12 downto 0)) or
(repeat(32, sig_1395) and sig_1610(31 downto 0)) or
(repeat(32, sig_1433) and sig_1639);
-- Behaviour of component 'mux_313' model 'mux'
mux_313 <=
(repeat(9, sig_1324) and "001000111") or
(repeat(9, sig_1118) and "011111011") or
(repeat(9, sig_1217) and "001011011") or
(repeat(9, sig_1349) and "111011001") or
(repeat(9, sig_1395) and "010110101");
-- Behaviour of component 'mux_308' model 'mux'
mux_308 <=
(repeat(3, sig_994) and "101") or
(repeat(3, sig_995) and "100") or
(repeat(3, sig_1046) and decode_start_i(2 downto 0));
-- Behaviour of component 'mux_306' model 'mux'
mux_306 <=
(repeat(41, sig_1451) and "00000000000000000000000000000000000001000") or
(repeat(41, sig_1299) and "00000000000000000000000000000000010000000") or
(repeat(41, sig_1308) and "00000000000000000000000000000000000000001") or
(repeat(41, sig_1324) and chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1) or
(repeat(41, sig_1355) and buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p) or
(repeat(41, sig_1217) and sig_1627(30) & sig_1627(30) & sig_1627(30) & sig_1627(30) & sig_1627(30) & sig_1627(30) & sig_1627(30) & sig_1627(30) & sig_1627(30) & sig_1627(30 downto 0) & '0') or
(repeat(41, sig_1161) and "00000000000000000000000000000000000000010") or
(repeat(41, sig_1118) and chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2) or
(repeat(41, sig_1470) and "00000000000000000000000000000000011111111") or
(repeat(41, sig_1463) and chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2);
-- Behaviour of component 'mux_307' model 'mux'
mux_307 <=
(repeat(41, sig_1355) and "00000000000000000000000000000000000000111") or
(repeat(41, sig_1217) and sig_1614(31) & sig_1614(31) & sig_1614(31) & sig_1614(31) & sig_1614(31) & sig_1614(31) & sig_1614(31) & sig_1614(31) & sig_1614(31) & sig_1614(31 downto 0)) or
(repeat(41, sig_1299) and sig_1641(30) & sig_1641(30) & sig_1641(30) & sig_1641(30) & sig_1641(30) & sig_1641(30) & sig_1641(30) & sig_1641(30) & sig_1641(30) & sig_1641(30) & sig_1641(30 downto 0)) or
(repeat(41, sig_1309) and p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width) or
(repeat(41, sig_1324) and chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0) or
(repeat(41, sig_1216) and sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648) or
(repeat(41, sig_1118) and chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1) or
(repeat(41, sig_1060) and yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r) or
(repeat(41, sig_1468) and sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642) or
(repeat(41, sig_1463) and chenidct_c3(31) & chenidct_c3(31) & chenidct_c3(31) & chenidct_c3(31) & chenidct_c3(31) & chenidct_c3(31) & chenidct_c3(31) & chenidct_c3(31) & chenidct_c3(31) & chenidct_c3);
-- Behaviour of component 'mux_302' model 'mux'
mux_302 <=
(repeat(41, sig_1216) and p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth) or
(repeat(41, sig_1470) and "00000000000000000000000000000000011111111") or
(repeat(41, sig_1463) and chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3);
-- Behaviour of component 'mux_303' model 'mux'
mux_303 <=
(repeat(41, sig_1216) and sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647) or
(repeat(41, sig_1060) and yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r) or
(repeat(41, sig_1471) and sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642) or
(repeat(41, sig_1463) and chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0);
-- Behaviour of component 'mux_294' model 'mux'
mux_294 <=
(repeat(2, sig_995) and "01") or
(repeat(2, sig_994) and "10") or
(repeat(2, sig_1045) and decode_start_i(1 downto 0));
-- Behaviour of component 'mux_290' model 'mux'
mux_290 <=
(repeat(41, sig_1395) and chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1) or
(repeat(41, sig_1376) and "00000000000000000000000000000000000000111") or
(repeat(41, sig_1363) and chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2) or
(repeat(41, sig_1355) and buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5 downto 0)) or
(repeat(41, sig_1349) and sig_1627) or
(repeat(41, sig_1534) and sig_1660(31) & sig_1660(31) & sig_1660(31) & sig_1660(31) & sig_1660(31) & sig_1660(31) & sig_1660(31) & sig_1660(31) & sig_1660(31) & sig_1660) or
(repeat(41, sig_1324) and sig_1667(38 downto 0) & "00") or
(repeat(41, sig_1318) and "00000000000000000000000000000000000000010") or
(repeat(41, sig_1313) and get_dht_count(31) & get_dht_count(31) & get_dht_count(31) & get_dht_count(31) & get_dht_count(31) & get_dht_count(31) & get_dht_count(31) & get_dht_count(31) & get_dht_count(31) & get_dht_count) or
(repeat(41, sig_1300) and "00000000000000000000000000000000000010001") or
(repeat(41, sig_1299) and "00000000000000000000000000000000010000000") or
(repeat(41, sig_1292) and sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654) or
(repeat(41, sig_1289) and sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650) or
(repeat(41, sig_1280) and chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0) or
(repeat(41, sig_1550) and "00000000000000000000000000000000000010000") or
(repeat(41, sig_1569) and sig_1651(31) & sig_1651(31) & sig_1651(31) & sig_1651(31) & sig_1651(31) & sig_1651(31) & sig_1651(31) & sig_1651(31) & sig_1651(31) & sig_1651) or
(repeat(41, sig_1576) and sig_1655(31) & sig_1655(31) & sig_1655(31) & sig_1655(31) & sig_1655(31) & sig_1655(31) & sig_1655(31) & sig_1655(31) & sig_1655(31) & sig_1655) or
(repeat(41, sig_1505) and sig_1658(31) & sig_1658(31) & sig_1658(31) & sig_1658(31) & sig_1658(31) & sig_1658(31) & sig_1658(31) & sig_1658(31) & sig_1658(31) & sig_1658) or
(repeat(41, sig_1491) and "00000000000000000000000000000000000001000") or
(repeat(41, sig_1486) and "00000000000000000000000000000000000010111") or
(repeat(41, sig_1485) and "00000000000000000000000000000000000000001") or
(repeat(41, sig_1440) and chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1) or
(repeat(41, sig_1434) and "00000000000000000000000000000000000111111") or
(repeat(41, sig_1244) and "000000000000000000000000000000000" & p_jinfo_num_components) or
(repeat(41, sig_1241) and "000000000000000000000000000000000" & get_sos_num_comp) or
(repeat(41, sig_1240) and "00000000000000000000000000000000001000000") or
(repeat(41, sig_1229) and chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3) or
(repeat(41, sig_1217) and sig_1628(28) & sig_1628(28) & sig_1628(28) & sig_1628(28) & sig_1628(28) & sig_1628(28) & sig_1628(28) & sig_1628(28) & sig_1628(28) & sig_1628(28 downto 0) & "000") or
(repeat(41, sig_1216) and p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth) or
(repeat(41, sig_1165) and buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p) or
(repeat(41, sig_1118) and sig_1627(39 downto 0) & '0') or
(repeat(41, sig_1089) and "00000000000000000000000000000000001000001") or
(repeat(41, sig_1077) and "00000000000000000000000000000000100000000") or
(repeat(41, sig_1049) and "00000000000000000000000000000000000000011") or
(repeat(41, sig_1048) and p_jinfo_nummcu(31) & p_jinfo_nummcu(31) & p_jinfo_nummcu(31) & p_jinfo_nummcu(31) & p_jinfo_nummcu(31) & p_jinfo_nummcu(31) & p_jinfo_nummcu(31) & p_jinfo_nummcu(31) & p_jinfo_nummcu(31) & p_jinfo_nummcu) or
(repeat(41, sig_1032) and read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position) or
(repeat(41, sig_1015) and writeoneblock_width(31) & writeoneblock_width(31) & writeoneblock_width(31) & writeoneblock_width(31) & writeoneblock_width(31) & writeoneblock_width(31) & writeoneblock_width(31) & writeoneblock_width(31) & writeoneblock_width(31) & writeoneblock_width) or
(repeat(41, sig_1014) and sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28 downto 0) & writeoneblock_hoffs(2 downto 0)) or
(repeat(41, sig_1010) and writeoneblock_height(31) & writeoneblock_height(31) & writeoneblock_height(31) & writeoneblock_height(31) & writeoneblock_height(31) & writeoneblock_height(31) & writeoneblock_height(31) & writeoneblock_height(31) & writeoneblock_height(31) & writeoneblock_height) or
(repeat(41, sig_1009) and sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28 downto 0) & writeoneblock_voffs(2 downto 0));
-- Behaviour of component 'mux_291' model 'mux'
mux_291 <=
(repeat(41, sig_1468) and sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642) or
(repeat(41, sig_1505) and huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j) or
(repeat(41, sig_1502) and huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0) or
(repeat(41, sig_1492) and buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p) or
(repeat(41, sig_1487) and read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position) or
(repeat(41, sig_1420) and chenidct_i(31) & chenidct_i(31) & chenidct_i(31) & chenidct_i(31) & chenidct_i(31) & chenidct_i(31) & chenidct_i(31) & chenidct_i(31) & chenidct_i(31) & chenidct_i) or
(repeat(41, sig_1569) and decodehuffman_ac_code(31) & decodehuffman_ac_code(31) & decodehuffman_ac_code(31) & decodehuffman_ac_code(31) & decodehuffman_ac_code(31) & decodehuffman_ac_code(31) & decodehuffman_ac_code(31) & decodehuffman_ac_code(31) & decodehuffman_ac_code(31) & decodehuffman_ac_code) or
(repeat(41, sig_1395) and chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2) or
(repeat(41, sig_1393) and chenidct_b2(31) & chenidct_b2(31) & chenidct_b2(31) & chenidct_b2(31) & chenidct_b2(31) & chenidct_b2(31) & chenidct_b2(31) & chenidct_b2(31) & chenidct_b2(31) & chenidct_b2) or
(repeat(41, sig_1363) and chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1) or
(repeat(41, sig_1355) and "00000000000000000000000000000000000001000") or
(repeat(41, sig_1349) and sig_1628(38 downto 0) & "00") or
(repeat(41, sig_1342) and decodehuffmcu_s(31) & decodehuffmcu_s(31) & decodehuffmcu_s(31) & decodehuffmcu_s(31) & decodehuffmcu_s(31) & decodehuffmcu_s(31) & decodehuffmcu_s(31) & decodehuffmcu_s(31) & decodehuffmcu_s(31) & decodehuffmcu_s) or
(repeat(41, sig_1336) and get_dqt_i(31) & get_dqt_i(31) & get_dqt_i(31) & get_dqt_i(31) & get_dqt_i(31) & get_dqt_i(31) & get_dqt_i(31) & get_dqt_i(31) & get_dqt_i(31) & get_dqt_i) or
(repeat(41, sig_1324) and sig_1666(39 downto 0) & '0') or
(repeat(41, sig_1576) and decodehuffman_dc_code(31) & decodehuffman_dc_code(31) & decodehuffman_dc_code(31) & decodehuffman_dc_code(31) & decodehuffman_dc_code(31) & decodehuffman_dc_code(31) & decodehuffman_dc_code(31) & decodehuffman_dc_code(31) & decodehuffman_dc_code(31) & decodehuffman_dc_code) or
(repeat(41, sig_1446) and decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i) or
(repeat(41, sig_1455) and decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k) or
(repeat(41, sig_1551) and huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l) or
(repeat(41, sig_1534) and huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j) or
(repeat(41, sig_1531) and huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0) or
(repeat(41, sig_1518) and huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l) or
(repeat(41, sig_1463) and chenidct_c0(31) & chenidct_c0(31) & chenidct_c0(31) & chenidct_c0(31) & chenidct_c0(31) & chenidct_c0(31) & chenidct_c0(31) & chenidct_c0(31) & chenidct_c0(31) & chenidct_c0) or
(repeat(41, sig_1435) and izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i) or
(repeat(41, sig_1322) and get_dqt_length(31) & get_dqt_length(31) & get_dqt_length(31) & get_dqt_length(31) & get_dqt_length(31) & get_dqt_length(31) & get_dqt_length(31) & get_dqt_length(31) & get_dqt_length(31) & get_dqt_length) or
(repeat(41, sig_1319) and read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word) or
(repeat(41, sig_1314) and get_dht_length(31) & get_dht_length(31) & get_dht_length(31) & get_dht_length(31) & get_dht_length(31) & get_dht_length(31) & get_dht_length(31) & get_dht_length(31) & get_dht_length(31) & get_dht_length) or
(repeat(41, sig_1309) and p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height) or
(repeat(41, sig_1303) and get_dht_i(31) & get_dht_i(31) & get_dht_i(31) & get_dht_i(31) & get_dht_i(31) & get_dht_i(31) & get_dht_i(31) & get_dht_i(31) & get_dht_i(31) & get_dht_i) or
(repeat(41, sig_1299) and sig_1640(31) & sig_1640(31) & sig_1640(31) & sig_1640(31) & sig_1640(31) & sig_1640(31) & sig_1640(31) & sig_1640(31) & sig_1640(31) & sig_1640) or
(repeat(41, sig_1291) and sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8 downto 0)) or
(repeat(41, sig_1287) and get_sos_j(31) & get_sos_j(31) & get_sos_j(31) & get_sos_j(31) & get_sos_j(31) & get_sos_j(31) & get_sos_j(31) & get_sos_j(31) & get_sos_j(31) & get_sos_j) or
(repeat(41, sig_1280) and chenidct_b3(31) & chenidct_b3(31) & chenidct_b3(31) & chenidct_b3(31) & chenidct_b3(31) & chenidct_b3(31) & chenidct_b3(31) & chenidct_b3(31) & chenidct_b3(31) & chenidct_b3) or
(repeat(41, sig_1245) and get_sos_ci(31) & get_sos_ci(31) & get_sos_ci(31) & get_sos_ci(31) & get_sos_ci(31) & get_sos_ci(31) & get_sos_ci(31) & get_sos_ci(31) & get_sos_ci(31) & get_sos_ci) or
(repeat(41, sig_1241) and get_sos_i(31) & get_sos_i(31) & get_sos_i(31) & get_sos_i(31) & get_sos_i(31) & get_sos_i(31) & get_sos_i(31) & get_sos_i(31) & get_sos_i(31) & get_sos_i) or
(repeat(41, sig_1229) and chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0) or
(repeat(41, sig_1217) and yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y & "00000000") or
(repeat(41, sig_1216) and sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647) or
(repeat(41, sig_1209) and get_sof_ci(31) & get_sof_ci(31) & get_sof_ci(31) & get_sof_ci(31) & get_sof_ci(31) & get_sof_ci(31) & get_sof_ci(31) & get_sof_ci(31) & get_sof_ci(31) & get_sof_ci) or
(repeat(41, sig_1168) and buf_getv_n(31) & buf_getv_n(31) & buf_getv_n(31) & buf_getv_n(31) & buf_getv_n(31) & buf_getv_n(31) & buf_getv_n(31) & buf_getv_n(31) & buf_getv_n(31) & buf_getv_n) or
(repeat(41, sig_1118) and sig_1628(37) & sig_1628(37 downto 0) & "00") or
(repeat(41, sig_1078) and huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p) or
(repeat(41, sig_1060) and yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r) or
(repeat(41, sig_1051) and decode_start_i(31) & decode_start_i(31) & decode_start_i(31) & decode_start_i(31) & decode_start_i(31) & decode_start_i(31) & decode_start_i(31) & decode_start_i(31) & decode_start_i(31) & decode_start_i) or
(repeat(41, sig_1048) and decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu) or
(repeat(41, sig_1037) and huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p) or
(repeat(41, sig_1025) and yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i) or
(repeat(41, sig_1016) and writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e) or
(repeat(41, sig_1011) and writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i) or
(repeat(41, sig_1005) and write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs);
-- Behaviour of component 'mux_292' model 'mux'
mux_292 <=
(repeat(32, sig_1294) and sig_1613) or
(repeat(32, sig_1427) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_286' model 'mux'
mux_286 <=
(repeat(32, sig_1047) and sig_1610(31 downto 0)) or
(repeat(32, sig_1052) and sig_1610(29 downto 0) & decode_start_currentmcu(1 downto 0));
-- Behaviour of component 'mux_275' model 'mux'
mux_275 <=
(repeat(32, sig_1396) and chenidct_i) or
(repeat(32, sig_1118) and chenidct_a1) or
(repeat(32, sig_1217) and sig_1609(23) & sig_1609(23) & sig_1609(23) & sig_1609(23) & sig_1609(23) & sig_1609(23) & sig_1609(23) & sig_1609(23 downto 0) & sig_1666(6)) or
(repeat(32, sig_1294) and decode_start_i) or
(repeat(32, sig_1309) and sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16 downto 3)) or
(repeat(32, sig_1451) and sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31 downto 4)) or
(repeat(32, sig_1463) and chenidct_c3);
-- Behaviour of component 'mux_272' model 'mux'
mux_272 <=
(repeat(39, sig_1217) and yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y) or
(repeat(39, sig_1118) and sig_1600(40 downto 2)) or
(repeat(39, sig_1309) and sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16 downto 0)) or
(repeat(39, sig_1449) and chenidct_i(31) & chenidct_i(31) & chenidct_i(31) & chenidct_i(31) & chenidct_i(31) & chenidct_i(31) & chenidct_i(31) & chenidct_i);
-- Behaviour of component 'mux_274' model 'mux'
mux_274 <=
(repeat(32, sig_1397) and "00000000000000000000000000000001") or
(repeat(32, sig_1118) and chenidct_a2) or
(repeat(32, sig_1309) and "0000000000000000000000000000000" & and_864) or
(repeat(32, sig_1451) and "0000000000000000000000000000000" & and_789) or
(repeat(32, sig_1463) and chenidct_c2);
-- Behaviour of component 'mux_271' model 'mux'
mux_271 <=
(repeat(39, sig_1118) and sig_1668(38 downto 0)) or
(repeat(39, sig_1217) and sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31 downto 8)) or
(repeat(39, sig_1448) and "000000000000000000000000000000000000001");
-- Behaviour of component 'mux_266' model 'mux'
mux_266 <=
(repeat(39, sig_1463) and chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0) or
(repeat(39, sig_1574) and decodehuffman_dc_code(30) & decodehuffman_dc_code(30) & decodehuffman_dc_code(30) & decodehuffman_dc_code(30) & decodehuffman_dc_code(30) & decodehuffman_dc_code(30) & decodehuffman_dc_code(30) & decodehuffman_dc_code(30) & decodehuffman_dc_code(30 downto 0)) or
(repeat(39, sig_1567) and decodehuffman_ac_code(30) & decodehuffman_ac_code(30) & decodehuffman_ac_code(30) & decodehuffman_ac_code(30) & decodehuffman_ac_code(30) & decodehuffman_ac_code(30) & decodehuffman_ac_code(30) & decodehuffman_ac_code(30) & decodehuffman_ac_code(30 downto 0)) or
(repeat(39, sig_1563) and huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l) or
(repeat(39, sig_1561) and sig_1655(31) & sig_1655(31) & sig_1655(31) & sig_1655(31) & sig_1655(31) & sig_1655(31) & sig_1655(31) & sig_1655) or
(repeat(39, sig_1556) and sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31 downto 7)) or
(repeat(39, sig_1479) and get_dht_i(31) & get_dht_i(31) & get_dht_i(31) & get_dht_i(31) & get_dht_i(31) & get_dht_i(31) & get_dht_i(31) & get_dht_i) or
(repeat(39, sig_1548) and huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p) or
(repeat(39, sig_1536) and huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0) or
(repeat(39, sig_1529) and huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p) or
(repeat(39, sig_1525) and huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l) or
(repeat(39, sig_1523) and sig_1651(31) & sig_1651(31) & sig_1651(31) & sig_1651(31) & sig_1651(31) & sig_1651(31) & sig_1651(31) & sig_1651) or
(repeat(39, sig_1507) and huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0) or
(repeat(39, sig_1493) and read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31 downto 3)) or
(repeat(39, sig_1412) and "0000000" & chenidct_aidx) or
(repeat(39, sig_1477) and "0000000000" & chenidct_aidx(31 downto 3)) or
(repeat(39, sig_1466) and decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k) or
(repeat(39, sig_1464) and decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31 downto 4)) or
(repeat(39, sig_1451) and sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31 downto 3)) or
(repeat(39, sig_1443) and decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i) or
(repeat(39, sig_1441) and "0000000" & curhuffreadbuf_idx) or
(repeat(39, sig_1582) and "0000000000" & chenidct_i(31 downto 3)) or
(repeat(39, sig_1436) and izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i) or
(repeat(39, sig_1427) and decode_start_i(31) & decode_start_i(31) & decode_start_i(31) & decode_start_i(31) & decode_start_i(31) & decode_start_i(31) & decode_start_i(31) & decode_start_i) or
(repeat(39, sig_1395) and chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1) or
(repeat(39, sig_1350) and "0000000" & chenidct_i(28 downto 0) & "001") or
(repeat(39, sig_1335) and get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num) or
(repeat(39, sig_1309) and sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16 downto 3)) or
(repeat(39, sig_1297) and sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647) or
(repeat(39, sig_1292) and sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653) or
(repeat(39, sig_1289) and sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649) or
(repeat(39, sig_1283) and huff_make_dhuff_tb_ac_size(31) & huff_make_dhuff_tb_ac_size(31) & huff_make_dhuff_tb_ac_size(31) & huff_make_dhuff_tb_ac_size(31) & huff_make_dhuff_tb_ac_size(31) & huff_make_dhuff_tb_ac_size(31) & huff_make_dhuff_tb_ac_size(31) & huff_make_dhuff_tb_ac_size) or
(repeat(39, sig_1264) and chenidct_b2(31) & chenidct_b2(31) & chenidct_b2(31) & chenidct_b2(31) & chenidct_b2(31) & chenidct_b2(31) & chenidct_b2(31) & chenidct_b2) or
(repeat(39, sig_1257) and sig_1643(31) & sig_1643(31) & sig_1643(31) & sig_1643(31) & sig_1643(31) & sig_1643(31) & sig_1643(31) & sig_1643) or
(repeat(39, sig_1254) and get_sos_ci(31) & get_sos_ci(31) & get_sos_ci(31) & get_sos_ci(31) & get_sos_ci(31) & get_sos_ci(31) & get_sos_ci(31) & get_sos_ci) or
(repeat(39, sig_1251) and get_sos_i(31) & get_sos_i(31) & get_sos_i(31) & get_sos_i(31) & get_sos_i(31) & get_sos_i(31) & get_sos_i(31) & get_sos_i) or
(repeat(39, sig_1247) and "0000000" & readbuf_idx) or
(repeat(39, sig_1234) and yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i) or
(repeat(39, sig_1217) and sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31 downto 7)) or
(repeat(39, sig_1211) and get_sof_ci(31) & get_sof_ci(31) & get_sof_ci(31) & get_sof_ci(31) & get_sof_ci(31) & get_sof_ci(31) & get_sof_ci(31) & get_sof_ci) or
(repeat(39, sig_1163) and sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31 downto 1)) or
(repeat(39, sig_1118) and sig_1666(39 downto 1)) or
(repeat(39, sig_1112) and chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1) or
(repeat(39, sig_1110) and chenidct_b3(31) & chenidct_b3(31) & chenidct_b3(31) & chenidct_b3(31) & chenidct_b3(31) & chenidct_b3(31) & chenidct_b3(31) & chenidct_b3) or
(repeat(39, sig_1073) and "0000000000000000000000000000000000000" & sig_1663) or
(repeat(39, sig_1068) and huff_make_dhuff_tb_dc_size(31) & huff_make_dhuff_tb_dc_size(31) & huff_make_dhuff_tb_dc_size(31) & huff_make_dhuff_tb_dc_size(31) & huff_make_dhuff_tb_dc_size(31) & huff_make_dhuff_tb_dc_size(31) & huff_make_dhuff_tb_dc_size(31) & huff_make_dhuff_tb_dc_size) or
(repeat(39, sig_1059) and "0000000" & jpeg2bmp_main_j) or
(repeat(39, sig_1056) and "0000000" & jpeg2bmp_main_i) or
(repeat(39, sig_1052) and decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31 downto 2)) or
(repeat(39, sig_1047) and decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu) or
(repeat(39, sig_1026) and decodehuffmcu_diff(31) & decodehuffmcu_diff(31) & decodehuffmcu_diff(31) & decodehuffmcu_diff(31) & decodehuffmcu_diff(31) & decodehuffmcu_diff(31) & decodehuffmcu_diff(31) & decodehuffmcu_diff) or
(repeat(39, sig_1021) and write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31 downto 3)) or
(repeat(39, sig_1018) and writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i) or
(repeat(39, sig_1017) and writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e) or
(repeat(39, sig_1014) and writeoneblock_hoffs(31) & writeoneblock_hoffs(31) & writeoneblock_hoffs(31) & writeoneblock_hoffs(31) & writeoneblock_hoffs(31) & writeoneblock_hoffs(31) & writeoneblock_hoffs(31) & writeoneblock_hoffs(31) & writeoneblock_hoffs(31) & writeoneblock_hoffs(31) & writeoneblock_hoffs(31 downto 3)) or
(repeat(39, sig_1012) and writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff) or
(repeat(39, sig_1009) and writeoneblock_voffs(31) & writeoneblock_voffs(31) & writeoneblock_voffs(31) & writeoneblock_voffs(31) & writeoneblock_voffs(31) & writeoneblock_voffs(31) & writeoneblock_voffs(31) & writeoneblock_voffs(31) & writeoneblock_voffs(31) & writeoneblock_voffs(31) & writeoneblock_voffs(31 downto 3)) or
(repeat(39, sig_1005) and write4blocks_voffs(31) & write4blocks_voffs(31) & write4blocks_voffs(31) & write4blocks_voffs(31) & write4blocks_voffs(31) & write4blocks_voffs(31) & write4blocks_voffs(31) & write4blocks_voffs(31) & write4blocks_voffs(31) & write4blocks_voffs(31) & write4blocks_voffs(31 downto 3));
-- Behaviour of component 'mux_265' model 'mux'
mux_265 <=
(repeat(39, sig_1112) and chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2) or
(repeat(39, sig_1110) and chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0) or
(repeat(39, sig_1027) and sig_1643(31) & sig_1643(31) & sig_1643(31) & sig_1643(31) & sig_1643(31) & sig_1643(31) & sig_1643(31) & sig_1643) or
(repeat(39, sig_1012) and writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12 downto 0)) or
(repeat(39, sig_1006) and "00000000000" & decodehuffmcu_n) or
(repeat(39, sig_1309) and "00000000000000000000000000000000000000" & and_862) or
(repeat(39, sig_1395) and chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2) or
(repeat(39, sig_1546) and "111111111111111111111111111111111111111") or
(repeat(39, sig_1556) and "000000000000000000000000000000000000001") or
(repeat(39, sig_1292) and decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8 downto 0)) or
(repeat(39, sig_1289) and decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8 downto 0)) or
(repeat(39, sig_1264) and chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1) or
(repeat(39, sig_1118) and sig_1667(37) & sig_1667(37 downto 0)) or
(repeat(39, sig_1463) and chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3) or
(repeat(39, sig_1426) and "000000000000000000000000000000000000001");
-- Behaviour of component 'mux_260' model 'mux'
mux_260 <=
(repeat(39, sig_1458) and "0000000000000000000000000000000" & read_byte) or
(repeat(39, sig_1324) and sig_1627(38 downto 0)) or
(repeat(39, sig_1395) and chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3) or
(repeat(39, sig_1544) and sig_1658(31) & sig_1658(31) & sig_1658(31) & sig_1658(31) & sig_1658(31) & sig_1658(31) & sig_1658(31) & sig_1658) or
(repeat(39, sig_1451) and "00000000000000000000000000000000000000" & and_785) or
(repeat(39, sig_1217) and sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30 downto 7)) or
(repeat(39, sig_1118) and chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1) or
(repeat(39, sig_1038) and sig_1660(31) & sig_1660(31) & sig_1660(31) & sig_1660(31) & sig_1660(31) & sig_1660(31) & sig_1660(31) & sig_1660) or
(repeat(39, sig_1463) and chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1) or
(repeat(39, sig_1438) and "000000000000000000000000000000000000001");
-- Behaviour of component 'mux_261' model 'mux'
mux_261 <=
(repeat(39, sig_1458) and get_dht_count(31) & get_dht_count(31) & get_dht_count(31) & get_dht_count(31) & get_dht_count(31) & get_dht_count(31) & get_dht_count(31) & get_dht_count) or
(repeat(39, sig_1324) and sig_1628(39 downto 1)) or
(repeat(39, sig_1309) and sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16 downto 0)) or
(repeat(39, sig_1297) and sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648) or
(repeat(39, sig_1262) and "0000000" & chenidct_aidx) or
(repeat(39, sig_1217) and yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y) or
(repeat(39, sig_1546) and sig_1610(31) & sig_1610(31) & sig_1610(31) & sig_1610(31) & sig_1610(31) & sig_1610(31) & sig_1610(31) & sig_1610(31 downto 0)) or
(repeat(39, sig_1163) and sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31 downto 1)) or
(repeat(39, sig_1111) and "0000000000" & chenidct_aidx(31 downto 3)) or
(repeat(39, sig_1035) and huff_make_dhuff_tb_dc_code(31) & huff_make_dhuff_tb_dc_code(31) & huff_make_dhuff_tb_dc_code(31) & huff_make_dhuff_tb_dc_code(31) & huff_make_dhuff_tb_dc_code(31) & huff_make_dhuff_tb_dc_code(31) & huff_make_dhuff_tb_dc_code(31) & huff_make_dhuff_tb_dc_code) or
(repeat(39, sig_1023) and huff_make_dhuff_tb_ac_code(31) & huff_make_dhuff_tb_ac_code(31) & huff_make_dhuff_tb_ac_code(31) & huff_make_dhuff_tb_ac_code(31) & huff_make_dhuff_tb_ac_code(31) & huff_make_dhuff_tb_ac_code(31) & huff_make_dhuff_tb_ac_code(31) & huff_make_dhuff_tb_ac_code) or
(repeat(39, sig_1012) and "0000000" & writeoneblock_inidx) or
(repeat(39, sig_1567) and decodehuffman_ac_l(31) & decodehuffman_ac_l(31) & decodehuffman_ac_l(31) & decodehuffman_ac_l(31) & decodehuffman_ac_l(31) & decodehuffman_ac_l(31) & decodehuffman_ac_l(31) & decodehuffman_ac_l) or
(repeat(39, sig_1574) and decodehuffman_dc_l(31) & decodehuffman_dc_l(31) & decodehuffman_dc_l(31) & decodehuffman_dc_l(31) & decodehuffman_dc_l(31) & decodehuffman_dc_l(31) & decodehuffman_dc_l(31) & decodehuffman_dc_l) or
(repeat(39, sig_1451) and sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28 downto 1)) or
(repeat(39, sig_1527) and huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j) or
(repeat(39, sig_1499) and huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j) or
(repeat(39, sig_1398) and chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0) or
(repeat(39, sig_1335) and get_dqt_i(31) & get_dqt_i(31) & get_dqt_i(31) & get_dqt_i(31) & get_dqt_i(31) & get_dqt_i(31) & get_dqt_i(31) & get_dqt_i) or
(repeat(39, sig_1463) and chenidct_c0(31) & chenidct_c0(31) & chenidct_c0(31) & chenidct_c0(31) & chenidct_c0(31) & chenidct_c0(31) & chenidct_c0(31) & chenidct_c0) or
(repeat(39, sig_1436) and izigzagmatrix_out_idx(31) & izigzagmatrix_out_idx(31) & izigzagmatrix_out_idx(31) & izigzagmatrix_out_idx(31) & izigzagmatrix_out_idx(31) & izigzagmatrix_out_idx(31) & izigzagmatrix_out_idx(31) & izigzagmatrix_out_idx);
-- Behaviour of component 'mux_262' model 'mux'
mux_262 <=
(repeat(32, sig_1056) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_257' model 'mux'
mux_257 <=
(repeat(32, sig_1059) and sig_1610(31 downto 0));
-- Behaviour of component 'nand_786' model 'nand'
nand_786 <= not (
sig_1605 and
sig_1606
);
-- Behaviour of component 'or_845' model 'or'
or_845 <=
sig_1629 or
buf_getv_rv;
-- Behaviour of component 'or_854' model 'or'
or_854 <=
sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638 or
buf_getv;
-- Behaviour of component 'or_866' model 'or'
or_866 <=
sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638 or
sig_1643;
-- Behaviour of component 'and_785' model 'and'
and_785 <=
nand_786 and
sig_1610(28);
-- Behaviour of component 'and_801' model 'and'
and_801 <=
sig_1636 and
current_read_byte;
-- Behaviour of component 'mux_761' model 'mux'
mux_761 <=
(repeat(9, sig_1118) and "000011001") or
(repeat(9, sig_1217) and "101100111") or
(repeat(9, sig_1324) and "001000111");
-- Behaviour of component 'mux_782' model 'mux'
mux_782 <=
(repeat(32, sig_1607) and sig_1660) or
(repeat(32, sig_1608) and "000000000000000000000000" & read_byte);
-- Behaviour of component 'or_802' model 'or'
or_802 <=
current_read_byte(23 downto 0) or
"000000000000000000000000";
-- Behaviour of component 'and_803' model 'and'
and_803 <=
sig_1637 and
current_read_byte;
-- Behaviour of component 'mux_822' model 'mux'
mux_822 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_823' model 'mux'
mux_823 <=
(repeat(32, sig_1617) and mux_824);
-- Behaviour of component 'mux_776' model 'mux'
mux_776 <=
(repeat(32, sig_1617) and mux_777);
-- Behaviour of component 'mux_820' model 'mux'
mux_820 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_824' model 'mux'
mux_824 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_825' model 'mux'
mux_825 <=
(repeat(32, sig_1617) and mux_826);
-- Behaviour of component 'mux_760' model 'mux'
mux_760 <=
(repeat(32, sig_1118) and chenidct_a0) or
(repeat(32, sig_1217) and yuvtorgb_u(30) & yuvtorgb_u) or
(repeat(32, sig_1324) and chenidct_a2);
-- Behaviour of component 'and_789' model 'and'
and_789 <=
sig_1604 and
sig_1624(31);
-- Behaviour of component 'mux_759' model 'mux'
mux_759 <=
(repeat(6, sig_1118) and "111011") or
(repeat(6, sig_1217) and "100011") or
(repeat(6, sig_1324) and "010101");
-- Behaviour of component 'mux_768' model 'mux'
mux_768 <=
(repeat(32, sig_1436) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_757' model 'mux'
mux_757 <=
(repeat(8, sig_1057) and sig_1646) or
(repeat(8, sig_1062) and outdata_image_height);
-- Behaviour of component 'mux_773' model 'mux'
mux_773 <=
(repeat(8, sig_1179) and outdata_image_height) or
(repeat(8, sig_1180) and outdata_image_width) or
(repeat(8, sig_1181) and write8_u8);
-- Behaviour of component 'mux_762' model 'mux'
mux_762 <=
(repeat(32, sig_1118) and chenidct_a3) or
(repeat(32, sig_1217) and yuvtorgb_v) or
(repeat(32, sig_1324) and chenidct_a1);
-- Behaviour of component 'mux_766' model 'mux'
mux_766 <=
(repeat(32, sig_1436) and sig_1609(31 downto 0));
-- Behaviour of component 'mux_781' model 'mux'
mux_781 <=
(repeat(32, sig_1608) and sig_1657) or
(repeat(32, sig_1607) and "000000000000000000000000" & read_byte);
-- Behaviour of component 'mux_797' model 'mux'
mux_797 <=
(repeat(32, sig_1617) and mux_798);
-- Behaviour of component 'mux_821' model 'mux'
mux_821 <=
(repeat(32, sig_1617) and mux_822);
-- Behaviour of component 'mux_826' model 'mux'
mux_826 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_778' model 'mux'
mux_778 <=
(repeat(32, sig_1607) and sig_1659) or
(repeat(32, sig_1608) and "000000000000000000000000" & read_byte);
-- Behaviour of component 'mux_827' model 'mux'
mux_827 <=
(repeat(32, sig_1617) and mux_828);
-- Behaviour of component 'mux_815' model 'mux'
mux_815 <=
(repeat(32, sig_1617) and mux_816);
-- Behaviour of component 'mux_798' model 'mux'
mux_798 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_816' model 'mux'
mux_816 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_817' model 'mux'
mux_817 <=
(repeat(32, sig_1617) and mux_818);
-- Behaviour of component 'mux_777' model 'mux'
mux_777 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_819' model 'mux'
mux_819 <=
(repeat(32, sig_1617) and mux_820);
-- Behaviour of component 'mux_783' model 'mux'
mux_783 <=
(repeat(32, sig_1608) and sig_1658) or
(repeat(32, sig_1607) and "000000000000000000000000" & read_byte);
-- Behaviour of component 'mux_795' model 'mux'
mux_795 <=
(repeat(32, sig_1617) and mux_796);
-- Behaviour of component 'mux_796' model 'mux'
mux_796 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_805' model 'mux'
mux_805 <=
(repeat(32, sig_1617) and mux_806);
-- Behaviour of component 'mux_806' model 'mux'
mux_806 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_807' model 'mux'
mux_807 <=
(repeat(32, sig_1617) and mux_808);
-- Behaviour of component 'mux_808' model 'mux'
mux_808 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_809' model 'mux'
mux_809 <=
(repeat(32, sig_1617) and mux_810);
-- Behaviour of component 'mux_810' model 'mux'
mux_810 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_811' model 'mux'
mux_811 <=
(repeat(32, sig_1617) and mux_812);
-- Behaviour of component 'mux_812' model 'mux'
mux_812 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_813' model 'mux'
mux_813 <=
(repeat(32, sig_1617) and mux_814);
-- Behaviour of component 'mux_814' model 'mux'
mux_814 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_818' model 'mux'
mux_818 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_828' model 'mux'
mux_828 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_829' model 'mux'
mux_829 <=
(repeat(32, sig_1617) and mux_830);
-- Behaviour of component 'mux_830' model 'mux'
mux_830 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_831' model 'mux'
mux_831 <=
(repeat(32, sig_1617) and mux_832);
-- Behaviour of component 'mux_832' model 'mux'
mux_832 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_836' model 'mux'
mux_836 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_837' model 'mux'
mux_837 <=
(repeat(32, sig_1617) and mux_838);
-- Behaviour of component 'mux_839' model 'mux'
mux_839 <=
(repeat(32, sig_1617) and mux_840);
-- Behaviour of component 'mux_840' model 'mux'
mux_840 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_841' model 'mux'
mux_841 <=
(repeat(32, sig_1617) and mux_842);
-- Behaviour of component 'mux_842' model 'mux'
mux_842 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_843' model 'mux'
mux_843 <=
(repeat(32, sig_1617) and mux_844);
-- Behaviour of component 'mux_856' model 'mux'
mux_856 <=
(repeat(32, sig_1617) and mux_857);
-- Behaviour of component 'and_864' model 'and'
and_864 <=
sig_1603 and
sig_1624(16);
-- Behaviour of component 'mux_870' model 'mux'
mux_870 <=
(repeat(32, sig_1599) and get_dqt_length) or
(repeat(32, sig_1669) and sig_1614(31 downto 0));
-- Behaviour of component 'mux_872' model 'mux'
mux_872 <=
(repeat(2, sig_1598) and "10");
-- Behaviour of component 'mux_875' model 'mux'
mux_875 <=
(repeat(32, sig_1616) and sig_1647);
-- Behaviour of component 'mux_891' model 'mux'
mux_891 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_892' model 'mux'
mux_892 <=
(repeat(32, sig_1617) and mux_893);
-- Behaviour of component 'mux_893' model 'mux'
mux_893 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_894' model 'mux'
mux_894 <=
(repeat(32, sig_1617) and mux_895);
-- Behaviour of component 'mux_895' model 'mux'
mux_895 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_896' model 'mux'
mux_896 <=
(repeat(32, sig_1623) and sig_1648) or
(repeat(32, sig_1616) and sig_1624(31 downto 0));
-- Behaviour of component 'mux_897' model 'mux'
mux_897 <=
(repeat(32, sig_1616) and sig_1647);
-- Behaviour of component 'mux_898' model 'mux'
mux_898 <=
(repeat(32, sig_1617) and mux_899);
-- Behaviour of component 'mux_899' model 'mux'
mux_899 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_900' model 'mux'
mux_900 <=
(repeat(32, sig_1617) and mux_901);
-- Behaviour of component 'mux_901' model 'mux'
mux_901 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_902' model 'mux'
mux_902 <=
(repeat(32, sig_1617) and mux_903);
-- Behaviour of component 'mux_903' model 'mux'
mux_903 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_904' model 'mux'
mux_904 <=
(repeat(32, sig_1617) and mux_905);
-- Behaviour of component 'mux_905' model 'mux'
mux_905 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_906' model 'mux'
mux_906 <=
(repeat(32, sig_1617) and mux_907);
-- Behaviour of component 'mux_907' model 'mux'
mux_907 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_908' model 'mux'
mux_908 <=
(repeat(32, sig_1617) and mux_909);
-- Behaviour of component 'mux_917' model 'mux'
mux_917 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_918' model 'mux'
mux_918 <=
(repeat(32, sig_1617) and mux_919);
-- Behaviour of component 'mux_924' model 'mux'
mux_924 <=
(repeat(32, sig_1617) and mux_925);
-- Behaviour of component 'mux_925' model 'mux'
mux_925 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_928' model 'mux'
mux_928 <=
(repeat(32, sig_1617) and mux_929);
-- Behaviour of component 'mux_929' model 'mux'
mux_929 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_931' model 'mux'
mux_931 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_932' model 'mux'
mux_932 <=
(repeat(32, sig_1617) and mux_933);
-- Behaviour of component 'mux_934' model 'mux'
mux_934 <=
(repeat(32, sig_1617) and mux_935);
-- Behaviour of component 'mux_935' model 'mux'
mux_935 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_936' model 'mux'
mux_936 <=
(repeat(32, sig_1617) and mux_937);
-- Behaviour of component 'mux_937' model 'mux'
mux_937 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_938' model 'mux'
mux_938 <=
(repeat(32, sig_1617) and mux_939);
-- Behaviour of component 'mux_939' model 'mux'
mux_939 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_941' model 'mux'
mux_941 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_944' model 'mux'
mux_944 <=
(repeat(32, sig_1617) and mux_945);
-- Behaviour of component 'mux_945' model 'mux'
mux_945 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_946' model 'mux'
mux_946 <=
(repeat(32, sig_1617) and mux_947);
-- Behaviour of component 'mux_833' model 'mux'
mux_833 <=
(repeat(32, sig_1617) and mux_834);
-- Behaviour of component 'mux_834' model 'mux'
mux_834 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_835' model 'mux'
mux_835 <=
(repeat(32, sig_1617) and mux_836);
-- Behaviour of component 'mux_838' model 'mux'
mux_838 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_844' model 'mux'
mux_844 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_857' model 'mux'
mux_857 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_858' model 'mux'
mux_858 <=
(repeat(32, sig_1617) and mux_859);
-- Behaviour of component 'mux_859' model 'mux'
mux_859 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_874' model 'mux'
mux_874 <=
(repeat(32, sig_1623) and sig_1648) or
(repeat(32, sig_1616) and sig_1624(31 downto 0));
-- Behaviour of component 'mux_888' model 'mux'
mux_888 <=
(repeat(32, sig_1617) and mux_889);
-- Behaviour of component 'mux_889' model 'mux'
mux_889 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_913' model 'mux'
mux_913 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_914' model 'mux'
mux_914 <=
(repeat(32, sig_1617) and mux_915);
-- Behaviour of component 'mux_915' model 'mux'
mux_915 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_916' model 'mux'
mux_916 <=
(repeat(32, sig_1617) and mux_917);
-- Behaviour of component 'mux_933' model 'mux'
mux_933 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_940' model 'mux'
mux_940 <=
(repeat(32, sig_1617) and mux_941);
-- Behaviour of component 'mux_942' model 'mux'
mux_942 <=
(repeat(32, sig_1617) and mux_943);
-- Behaviour of component 'and_867' model 'and'
and_867 <=
sig_1670 and
sig_1594;
-- Behaviour of component 'mux_909' model 'mux'
mux_909 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_910' model 'mux'
mux_910 <=
(repeat(32, sig_1617) and mux_911);
-- Behaviour of component 'mux_911' model 'mux'
mux_911 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_920' model 'mux'
mux_920 <=
(repeat(32, sig_1617) and mux_921);
-- Behaviour of component 'mux_921' model 'mux'
mux_921 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_926' model 'mux'
mux_926 <=
(repeat(32, sig_1617) and mux_927);
-- Behaviour of component 'mux_927' model 'mux'
mux_927 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_943' model 'mux'
mux_943 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_886' model 'mux'
mux_886 <=
(sig_1601 and read_byte(0)) or
(sig_1602 and read_byte(0));
-- Behaviour of component 'mux_922' model 'mux'
mux_922 <=
(repeat(32, sig_1617) and mux_923);
-- Behaviour of component 'mux_923' model 'mux'
mux_923 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_930' model 'mux'
mux_930 <=
(repeat(32, sig_1617) and mux_931);
-- Behaviour of component 'mux_987' model 'mux'
mux_987 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'and_860' model 'and'
and_860 <=
sig_1637 and
buf_getv;
-- Behaviour of component 'and_881' model 'and'
and_881 <=
sig_1637 and
sig_1643;
-- Behaviour of component 'and_884' model 'and'
and_884 <=
"00000000000000000000000000010000" and
"000000000000000000000000" & read_byte;
-- Behaviour of component 'mux_890' model 'mux'
mux_890 <=
(repeat(32, sig_1617) and mux_891);
-- Behaviour of component 'mux_912' model 'mux'
mux_912 <=
(repeat(32, sig_1617) and mux_913);
-- Behaviour of component 'mux_919' model 'mux'
mux_919 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_948' model 'mux'
mux_948 <=
(repeat(32, sig_1617) and mux_949);
-- Behaviour of component 'mux_949' model 'mux'
mux_949 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_950' model 'mux'
mux_950 <=
(repeat(32, sig_1617) and mux_951);
-- Behaviour of component 'and_862' model 'and'
and_862 <=
sig_1595 and
sig_1614(16);
-- Behaviour of component 'mux_953' model 'mux'
mux_953 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_954' model 'mux'
mux_954 <=
(repeat(32, sig_1617) and mux_955);
-- Behaviour of component 'mux_955' model 'mux'
mux_955 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_951' model 'mux'
mux_951 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_952' model 'mux'
mux_952 <=
(repeat(32, sig_1617) and mux_953);
-- Behaviour of component 'mux_959' model 'mux'
mux_959 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_960' model 'mux'
mux_960 <=
(repeat(32, sig_1617) and mux_961);
-- Behaviour of component 'mux_961' model 'mux'
mux_961 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_965' model 'mux'
mux_965 <=
(repeat(32, sig_1617) and mux_966);
-- Behaviour of component 'mux_966' model 'mux'
mux_966 <=
(repeat(32, sig_1622) and yuvtorgb_r) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'and_876' model 'and'
and_876 <=
"00001111" and
"0000" & read_byte(7 downto 4);
-- Behaviour of component 'mux_956' model 'mux'
mux_956 <=
(repeat(32, sig_1617) and mux_957);
-- Behaviour of component 'mux_957' model 'mux'
mux_957 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_947' model 'mux'
mux_947 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_968' model 'mux'
mux_968 <=
(repeat(32, sig_1593) and yuvtorgb_b) or
(repeat(32, sig_1591) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_969' model 'mux'
mux_969 <=
(repeat(32, sig_1597) and mux_970);
-- Behaviour of component 'mux_970' model 'mux'
mux_970 <=
(repeat(32, sig_1586) and yuvtorgb_g) or
(repeat(32, sig_1589) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_980' model 'mux'
mux_980 <=
(repeat(32, sig_1617) and mux_981);
-- Behaviour of component 'mux_981' model 'mux'
mux_981 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_958' model 'mux'
mux_958 <=
(repeat(32, sig_1617) and mux_959);
-- Behaviour of component 'and_963' model 'and'
and_963 <=
sig_1615 and
sig_991;
-- Behaviour of component 'mux_986' model 'mux'
mux_986 <=
(repeat(32, sig_1617) and mux_987);
-- Behaviour of component 'mux_988' model 'mux'
mux_988 <=
(repeat(32, sig_1617) and mux_989);
-- Behaviour of component 'mux_989' model 'mux'
mux_989 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of all components of model 'reg'
-- Registers with clock = sig_clock and no reset
process(sig_clock)
begin
if rising_edge(sig_clock) then
if sig_1437 = '1' then
izigzagmatrix_i <= mux_768;
end if;
if sig_1437 = '1' then
izigzagmatrix_out_idx <= mux_766;
end if;
if sig_1072 = '1' then
iquantize_qidx <= sig_1610(1 downto 0);
end if;
if sig_1061 = '1' then
write8_u8 <= mux_757;
end if;
if sig_1206 = '1' then
p_jinfo_image_height <= read_word;
end if;
if sig_1207 = '1' then
p_jinfo_image_width <= read_word;
end if;
if sig_1204 = '1' then
p_jinfo_num_components <= read_byte;
end if;
if sig_1219 = '1' then
p_jinfo_smp_fact <= mux_872;
end if;
if sig_1307 = '1' then
p_jinfo_mcuwidth <= sig_1612(17) & sig_1612(17) & sig_1612(17) & sig_1612(17) & sig_1612(17) & sig_1612(17) & sig_1612(17) & sig_1612(17) & sig_1612(17) & sig_1612(17) & sig_1612(17) & sig_1612(17) & sig_1612(17) & sig_1612(17) & sig_1612(17 downto 0);
end if;
if sig_1307 = '1' then
p_jinfo_mcuheight <= sig_1609(17) & sig_1609(17) & sig_1609(17) & sig_1609(17) & sig_1609(17) & sig_1609(17) & sig_1609(17) & sig_1609(17) & sig_1609(17) & sig_1609(17) & sig_1609(17) & sig_1609(17) & sig_1609(17) & sig_1609(17) & sig_1609(17 downto 0);
end if;
if sig_1100 = '1' then
p_jinfo_nummcu <= sig_1628(31 downto 0);
end if;
if sig_1273 = '1' then
i_jinfo_jpeg_data <= readbuf_idx;
end if;
if sig_1583 = '1' then
curhuffreadbuf_idx <= mux_671;
end if;
if sig_1042 = '1' then
outdata_image_width <= p_jinfo_image_width(7 downto 0);
end if;
if sig_1042 = '1' then
outdata_image_height <= p_jinfo_image_height(7 downto 0);
end if;
if sig_1340 = '1' then
readbuf_idx <= mux_648;
end if;
if sig_1053 = '1' then
read_byte <= sig_1644;
end if;
if sig_1249 = '1' then
read_word <= read_word_c & sig_1644;
end if;
if sig_1248 = '1' then
read_word_c <= sig_1644;
end if;
if sig_1205 = '1' then
next_marker <= next_marker_c;
end if;
if sig_1203 = '1' then
next_marker_c <= read_byte;
end if;
if sig_1210 = '1' then
get_sof_ci <= mux_633;
end if;
if sig_1208 = '1' then
get_sof_i_comp_info_id <= get_sof_ci(1 downto 0);
end if;
if sig_1208 = '1' then
get_sof_i_comp_info_h_samp_factor <= get_sof_ci(1 downto 0);
end if;
if sig_1208 = '1' then
get_sof_i_comp_info_quant_tbl_no <= get_sof_ci(1 downto 0);
end if;
if sig_1224 = '1' then
get_sos_num_comp <= read_byte;
end if;
if sig_1250 = '1' then
get_sos_i <= mux_622;
end if;
if sig_1272 = '1' then
get_sos_c <= read_byte(4);
end if;
if sig_1242 = '1' then
get_sos_cc <= read_byte;
end if;
if sig_1253 = '1' then
get_sos_ci <= mux_616;
end if;
if sig_1286 = '1' then
get_sos_j <= mux_614;
end if;
if sig_1243 = '1' then
get_sos_i_comp_info_dc_tbl_no <= get_sos_ci(1 downto 0);
end if;
if sig_1312 = '1' then
get_dht_length <= sig_1614(31 downto 0);
end if;
if sig_1199 = '1' then
get_dht_index <= mux_886;
end if;
if sig_1541 = '1' then
get_dht_i <= mux_602;
end if;
if sig_1456 = '1' then
get_dht_count <= mux_600;
end if;
if sig_1199 = '1' then
get_dht_is_ac <= sig_1602;
end if;
if sig_1316 = '1' then
get_dqt_length <= mux_593;
end if;
if sig_1302 = '1' then
get_dqt_prec <= read_byte(7 downto 4);
end if;
if sig_1302 = '1' then
get_dqt_num <= read_byte(1 downto 0);
end if;
if sig_1333 = '1' then
get_dqt_i <= mux_587;
end if;
if sig_1338 = '1' then
get_dqt_tmp <= mux_585;
end if;
if sig_1347 = '1' then
read_markers_unread_marker <= mux_580;
end if;
if sig_1352 = '1' then
read_markers_sow_soi <= sig_1353;
end if;
if sig_1447 = '1' then
chenidct_i <= mux_555;
end if;
if sig_1476 = '1' then
chenidct_aidx <= mux_553;
end if;
if sig_1462 = '1' then
chenidct_a0 <= mux_551;
end if;
if sig_1439 = '1' then
chenidct_a1 <= mux_549;
end if;
if sig_1584 = '1' then
chenidct_a2 <= mux_547;
end if;
if sig_1465 = '1' then
chenidct_a3 <= mux_545;
end if;
if sig_1459 = '1' then
chenidct_b0 <= mux_543;
end if;
if sig_1356 = '1' then
chenidct_b1 <= mux_541;
end if;
if sig_1478 = '1' then
chenidct_b2 <= mux_539;
end if;
if sig_1460 = '1' then
chenidct_b3 <= mux_537;
end if;
if sig_1461 = '1' then
chenidct_c0 <= mux_535;
end if;
if sig_1394 = '1' then
chenidct_c1 <= mux_533;
end if;
if sig_1394 = '1' then
chenidct_c2 <= mux_531;
end if;
if sig_1461 = '1' then
chenidct_c3 <= mux_529;
end if;
if sig_1494 = '1' then
current_read_byte <= mux_521;
end if;
if sig_1424 = '1' then
pgetc <= mux_517;
end if;
if sig_1442 = '1' then
pgetc_temp <= sig_1644;
end if;
if sig_1483 = '1' then
buf_getb <= sig_1481;
end if;
if sig_1495 = '1' then
buf_getv <= mux_507;
end if;
if sig_1200 = '1' then
buf_getv_n <= mux_505;
end if;
if sig_1490 = '1' then
buf_getv_p <= sig_1614(31 downto 0);
end if;
if sig_1488 = '1' then
buf_getv_rv <= mux_501;
end if;
if sig_1521 = '1' then
huff_make_dhuff_tb_ac <= huff_make_dhuff_tb_ac_p_dhtbl_ml;
end if;
if sig_1187 = '1' then
huff_make_dhuff_tb_ac_tbl_no <= sig_1184;
end if;
if sig_1543 = '1' then
huff_make_dhuff_tb_ac_p_dhtbl_ml <= mux_492;
end if;
if sig_1506 = '1' then
huff_make_dhuff_tb_ac_i_c0 <= mux_490;
end if;
if sig_1503 = '1' then
huff_make_dhuff_tb_ac_j <= mux_488;
end if;
if sig_1545 = '1' then
huff_make_dhuff_tb_ac_p <= mux_486;
end if;
if sig_1282 = '1' then
huff_make_dhuff_tb_ac_code <= mux_484;
end if;
if sig_1557 = '1' then
huff_make_dhuff_tb_ac_size <= mux_482;
end if;
if sig_1524 = '1' then
huff_make_dhuff_tb_ac_l <= mux_480;
end if;
if sig_1559 = '1' then
huff_make_dhuff_tb_dc <= huff_make_dhuff_tb_dc_p_dhtbl_ml;
end if;
if sig_1306 = '1' then
huff_make_dhuff_tb_dc_tbl_no <= sig_1189;
end if;
if sig_1539 = '1' then
huff_make_dhuff_tb_dc_p_dhtbl_ml <= mux_459;
end if;
if sig_1535 = '1' then
huff_make_dhuff_tb_dc_i_c0 <= mux_457;
end if;
if sig_1532 = '1' then
huff_make_dhuff_tb_dc_j <= mux_455;
end if;
if sig_1538 = '1' then
huff_make_dhuff_tb_dc_p <= mux_453;
end if;
if sig_1067 = '1' then
huff_make_dhuff_tb_dc_code <= mux_451;
end if;
if sig_1069 = '1' then
huff_make_dhuff_tb_dc_size <= mux_449;
end if;
if sig_1562 = '1' then
huff_make_dhuff_tb_dc_l <= mux_447;
end if;
if sig_1572 = '1' then
decodehuffman_ac <= mux_430;
end if;
if sig_1452 = '1' then
decodehuffman_ac_tbl_no <= decodehuffmcu_tbl_no;
end if;
if sig_1452 = '1' then
decodehuffman_ac_dhuff_ml <= sig_1652(5 downto 0);
end if;
if sig_1566 = '1' then
decodehuffman_ac_code <= mux_424;
end if;
if sig_1566 = '1' then
decodehuffman_ac_l <= mux_422;
end if;
if sig_1288 = '1' then
decodehuffman_ac_p <= sig_1614(8 downto 0);
end if;
if sig_1580 = '1' then
decodehuffman_dc <= mux_416;
end if;
if sig_1509 = '1' then
decodehuffman_dc_tbl_no <= sig_1662;
end if;
if sig_1169 = '1' then
decodehuffman_dc_dhuff_ml <= sig_1656(5 downto 0);
end if;
if sig_1573 = '1' then
decodehuffman_dc_code <= mux_410;
end if;
if sig_1573 = '1' then
decodehuffman_dc_l <= mux_408;
end if;
if sig_1290 = '1' then
decodehuffman_dc_p <= sig_1614(8 downto 0);
end if;
if sig_1509 = '1' then
decodehuffmcu_bufdim1 <= decode_block_in_buf_idx;
end if;
if sig_1578 = '1' then
decodehuffmcu_s <= mux_400;
end if;
if sig_1343 = '1' then
decodehuffmcu_diff <= mux_398;
end if;
if sig_1509 = '1' then
decodehuffmcu_tbl_no <= sig_1662;
end if;
if sig_1444 = '1' then
decodehuffmcu_i <= mux_394;
end if;
if sig_1467 = '1' then
decodehuffmcu_k <= mux_392;
end if;
if sig_1029 = '1' then
decodehuffmcu_n <= and_983;
end if;
if sig_1195 = '1' then
writeoneblock_outidx <= mux_375;
end if;
if sig_1195 = '1' then
writeoneblock_indim1 <= mux_373;
end if;
if sig_1195 = '1' then
writeoneblock_width <= p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width;
end if;
if sig_1195 = '1' then
writeoneblock_height <= p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height;
end if;
if sig_1195 = '1' then
writeoneblock_voffs <= mux_367;
end if;
if sig_1195 = '1' then
writeoneblock_hoffs <= mux_365;
end if;
if sig_1064 = '1' then
writeoneblock_i <= mux_363;
end if;
if sig_1080 = '1' then
writeoneblock_e <= mux_361;
end if;
if sig_1066 = '1' then
writeoneblock_inidx <= mux_359;
end if;
if sig_1082 = '1' then
writeoneblock_diff <= sig_1628(12 downto 0);
end if;
if sig_996 = '1' then
writeblock_i <= decode_start_i(1 downto 0);
end if;
if sig_1191 = '1' then
write4blocks_i <= decode_start_i(1 downto 0);
end if;
if sig_1193 = '1' then
write4blocks_voffs <= mux_347;
end if;
if sig_1192 = '1' then
write4blocks_hoffs <= mux_345;
end if;
if sig_998 = '1' then
yuvtorgb_p <= mux_343;
end if;
if sig_998 = '1' then
yuvtorgb_yidx <= mux_341;
end if;
if sig_998 = '1' then
yuvtorgb_uidx <= mux_339;
end if;
if sig_998 = '1' then
yuvtorgb_vidx <= mux_337;
end if;
if sig_1218 = '1' then
yuvtorgb_r <= mux_335;
end if;
if sig_1218 = '1' then
yuvtorgb_g <= mux_333;
end if;
if sig_1218 = '1' then
yuvtorgb_b <= mux_331;
end if;
if sig_1298 = '1' then
yuvtorgb_y <= sig_1642(23 downto 0);
end if;
if sig_1298 = '1' then
yuvtorgb_u <= sig_1624(30 downto 0);
end if;
if sig_1298 = '1' then
yuvtorgb_v <= sig_1614(31 downto 0);
end if;
if sig_1233 = '1' then
yuvtorgb_i <= mux_320;
end if;
if sig_1044 = '1' then
decode_block_comp_no <= mux_317;
end if;
if sig_1044 = '1' then
decode_block_out_buf_idx <= mux_308;
end if;
if sig_1044 = '1' then
decode_block_in_buf_idx <= mux_294;
end if;
if sig_1430 = '1' then
decode_start_i <= mux_292;
end if;
if sig_1182 = '1' then
decode_start_currentmcu <= mux_286;
end if;
if sig_1055 = '1' then
jpeg2bmp_main_i <= mux_262;
end if;
if sig_1058 = '1' then
jpeg2bmp_main_j <= mux_257;
end if;
if sig_1178 = '1' then
read8_ret0_195 <= stdin_data;
end if;
end if;
end process;
-- Registers with clock = sig_clock and reset = sig_reset active '1'
process(sig_clock, sig_reset)
begin
if sig_reset = '1' then
read_position <= "11111111111111111111111111111111";
else
if rising_edge(sig_clock) then
if sig_1496 = '1' then
read_position <= mux_519;
end if;
end if;
end if;
end process;
-- Remaining signal assignments
-- Those who are not assigned by component instantiation
sig_clock <= clock;
sig_reset <= reset;
augh_test_159 <= sig_1615;
augh_test_26 <= sig_1616;
augh_test_49 <= sig_1616;
augh_test_52 <= sig_1616;
augh_test_53 <= and_867;
augh_test_67 <= sig_1618;
augh_test_72 <= sig_1615;
augh_test_77 <= sig_1616;
augh_test_83 <= sig_1618;
augh_test_89 <= sig_1615;
augh_test_90 <= sig_1669;
augh_test_105 <= sig_1615;
augh_test_106 <= sig_1615;
augh_test_107 <= sig_1615;
augh_test_111 <= sig_1616;
augh_test_114 <= sig_1618;
augh_test_115 <= sig_1618;
augh_test_119 <= sig_1615;
augh_test_120 <= sig_1615;
augh_test_122 <= and_963;
augh_test_125 <= sig_1615;
augh_test_127 <= sig_1615;
augh_test_128 <= sig_1615;
augh_test_130 <= and_976;
augh_test_133 <= sig_1615;
augh_test_136 <= sig_1618;
augh_test_138 <= sig_1616;
augh_test_142 <= sig_1618;
augh_test_144 <= sig_1616;
augh_test_151 <= sig_1615;
augh_test_152 <= sig_1615;
augh_test_155 <= sig_1618;
augh_test_165 <= sig_1616;
augh_test_166 <= sig_1616;
augh_test_167 <= sig_1616;
augh_test_168 <= sig_1616;
sig_start <= start;
augh_test_171 <= sig_1615;
augh_test_178 <= sig_1615;
augh_test_179 <= sig_1615;
augh_test_182 <= sig_1616;
augh_test_183 <= sig_1615;
augh_test_184 <= sig_1615;
augh_test_186 <= sig_1616;
augh_test_187 <= sig_1615;
augh_test_188 <= sig_1615;
augh_test_189 <= sig_1615;
sig_1671 <= "000000000000000000000000" & pgetc_temp;
sig_1672 <= "000000000000000000000000000000" & p_jinfo_smp_fact;
sig_1673 <= yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g;
sig_1674 <= yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g;
sig_1675 <= yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b;
sig_1676 <= yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b;
sig_1677 <= "000000000000000000000000" & next_marker_c;
sig_1678 <= "000000000000000000000000" & pgetc_temp;
sig_1679 <= yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g;
sig_1680 <= "000000000000000000000000" & read_byte;
sig_1681 <= "000000000000000000000000" & next_marker_c;
sig_1682 <= "0000000000000000000000000000" & get_dqt_prec;
sig_1683 <= "000000000000000000000000" & read_markers_unread_marker;
sig_1684 <= "000000000000000000000000" & read_markers_unread_marker;
sig_1685 <= "0000000000000000000000000000000" & get_dht_is_ac;
sig_1686 <= "0000000000000000000000000000000" & get_dht_is_ac;
sig_1687 <= "0000" & decodehuffmcu_n;
sig_1688 <= sig_1612(23 downto 0) & sig_1667(7);
sig_1689 <= yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b;
sig_1690 <= "00000000000000000000000" & mux_313;
sig_1691 <= writeoneblock_indim1 & writeoneblock_outidx & writeoneblock_inidx(5 downto 0);
sig_1692 <= yuvtorgb_uidx & yuvtorgb_i(5 downto 0);
sig_1693 <= jpeg2bmp_main_i(1 downto 0) & jpeg2bmp_main_j(12 downto 0);
sig_1694 <= writeoneblock_outidx & sig_1610(12 downto 0);
sig_1695 <= decodehuffman_ac_tbl_no & decodehuffman_ac_l(5 downto 0);
sig_1696 <= huff_make_dhuff_tb_ac_tbl_no & huff_make_dhuff_tb_ac_l(5 downto 0);
sig_1697 <= decodehuffman_ac_tbl_no & decodehuffman_ac_l(5 downto 0);
sig_1698 <= huff_make_dhuff_tb_ac_tbl_no & huff_make_dhuff_tb_ac_l(5 downto 0);
sig_1699 <= decodehuffman_dc_tbl_no & decodehuffman_dc_l(5 downto 0);
sig_1700 <= huff_make_dhuff_tb_dc_tbl_no & huff_make_dhuff_tb_dc_l(5 downto 0);
sig_1701 <= decodehuffman_dc_tbl_no & decodehuffman_dc_l(5 downto 0);
sig_1702 <= huff_make_dhuff_tb_dc_tbl_no & huff_make_dhuff_tb_dc_l(5 downto 0);
sig_1703 <= get_dht_index & get_dht_i(8 downto 0);
sig_1704 <= get_dht_index & get_dht_i(5 downto 0);
sig_1705 <= get_dht_index & get_dht_i(8 downto 0);
sig_1706 <= get_dht_index & get_dht_i(5 downto 0);
sig_1707 <= sig_1610(1 downto 0) & sig_1645;
sig_1708 <= "0000000000000000" & get_dqt_tmp;
sig_1709 <= "000000000000000000000000" & read_markers_unread_marker;
sig_1710 <= "000000000000000000000000" & read_markers_unread_marker;
sig_1711 <= "000000000000000000000000" & read_markers_unread_marker;
sig_1712 <= "00000000000000000000000011" & mux_759;
sig_1713 <= "00000000000000000000000" & mux_761;
sig_1714 <= "0000000000000000000000000000000" & read_markers_sow_soi;
sig_1715 <= "0000000000000000000000000000" & get_dqt_prec;
sig_1716 <= "000000000000000000000000" & read_markers_unread_marker;
-- Remaining top-level ports assignments
-- Those who are not assigned by component instantiation
stdout_data <= mux_773;
stdin_rdy <= sig_1178;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- this unit introduces 1 cycle delay between d and q
entity scrambler is
generic (
width : positive := 8
);
port (
clk : in std_logic;
clk_en : in std_logic;
rst : in std_logic;
sync : in std_logic;
d : in std_logic_vector(width-1 downto 0);
q : out std_logic_vector(width-1 downto 0)
);
end entity scrambler;
architecture rtl of scrambler is
signal prbs_rst : std_logic;
signal prbs : std_logic_vector(width-1 downto 0);
signal enable : std_logic;
signal invert : std_logic;
signal first_sync : std_logic;
signal cnt : unsigned(2 downto 0) := (others => '0');
begin
prbs15 : entity work.prbs
generic map(
n => 15,
width => width
)
port map (
clk => clk,
clk_en => clk_en,
rst => prbs_rst,
q => prbs,
def_val => "100101010000000"
);
prbs_rst <= rst or first_sync;
process
begin
wait until rising_edge(clk);
if rst = '1' then
cnt <= (others => '0');
elsif (clk_en = '1') and (sync = '1') then
cnt <= cnt + 1;
end if;
end process;
process
begin
wait until rising_edge(clk);
if rst = '1' then
q <= (others => '0');
elsif clk_en = '1' then
for i in 0 to width-1 loop
q(i) <= d(i) xor ((prbs(i) and enable) or invert);
end loop;
end if;
end process;
enable <= not sync;
first_sync <= sync when cnt = 0 else '0';
invert <= first_sync;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.counter_div_trig;
use work.dbgram;
entity dbgsnap is
port
( clk : in std_logic
; tr : in std_logic
;dbg_in : in std_logic_vector(15 downto 0)
);
end entity dbgsnap;
architecture syn of dbgsnap is
component dbgram IS
port
( address : in std_logic_vector (12 DOWNTO 0)
; clock : in std_logic := '1'
; data : in std_logic_vector (15 DOWNTO 0)
; wren : in std_logic
; q : OUT std_logic_vector (15 DOWNTO 0)
);
end component dbgram;
component counter_div_trig is
generic
( OFFSET : integer
; BIT_WIDTH : integer
);
port
( clk : in std_logic
; tr : in std_logic
; counter_out : out std_logic_vector((BIT_WIDTH - 1) downto 0)
);
end component counter_div_trig;
signal dbg_addr : std_logic_vector(12 downto 0) := (others => '0');
begin
inst_dbg_addr : counter_div_trig
generic map
( OFFSET => 0
, BIT_WIDTH => 13
)
port map
( clk => clk
, tr => tr
, counter_out => dbg_addr
);
inst_dbgram : dbgram
port map
( address => dbg_addr
, clock => clk
, data => dbg_in
, wren => '1'
-- , q =>
);
end architecture syn;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.counter_div_trig;
use work.dbgram;
entity dbgsnap is
port
( clk : in std_logic
; tr : in std_logic
;dbg_in : in std_logic_vector(15 downto 0)
);
end entity dbgsnap;
architecture syn of dbgsnap is
component dbgram IS
port
( address : in std_logic_vector (12 DOWNTO 0)
; clock : in std_logic := '1'
; data : in std_logic_vector (15 DOWNTO 0)
; wren : in std_logic
; q : OUT std_logic_vector (15 DOWNTO 0)
);
end component dbgram;
component counter_div_trig is
generic
( OFFSET : integer
; BIT_WIDTH : integer
);
port
( clk : in std_logic
; tr : in std_logic
; counter_out : out std_logic_vector((BIT_WIDTH - 1) downto 0)
);
end component counter_div_trig;
signal dbg_addr : std_logic_vector(12 downto 0) := (others => '0');
begin
inst_dbg_addr : counter_div_trig
generic map
( OFFSET => 0
, BIT_WIDTH => 13
)
port map
( clk => clk
, tr => tr
, counter_out => dbg_addr
);
inst_dbgram : dbgram
port map
( address => dbg_addr
, clock => clk
, data => dbg_in
, wren => '1'
-- , q =>
);
end architecture syn;
|
package issue247 is
subtype natural_down is natural range 10 downto 0;
type array_t is array (natural_down range <>) of boolean;
constant c : array_t(9 downto 5); -- ok
end package issue247;
|
package issue247 is
subtype natural_down is natural range 10 downto 0;
type array_t is array (natural_down range <>) of boolean;
constant c : array_t(9 downto 5); -- ok
end package issue247;
|
package issue247 is
subtype natural_down is natural range 10 downto 0;
type array_t is array (natural_down range <>) of boolean;
constant c : array_t(9 downto 5); -- ok
end package issue247;
|
package issue247 is
subtype natural_down is natural range 10 downto 0;
type array_t is array (natural_down range <>) of boolean;
constant c : array_t(9 downto 5); -- ok
end package issue247;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbmst_em
-- File: ahbmst_em.vhd
-- Author: Alf Vaerneus, Gaisler Research
-- Description: AMBA AHB Master emulator for simulation purposes only
------------------------------------------------------------------------------
-- pragma translate_off
library IEEE;
use IEEE.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.ambatest.all;
library std;
use std.textio.all;
entity ahbmst_em is
generic(
hindex : integer := 0;
timeoutc : integer := 100;
dbglevel : integer := 2
);
port(
rst : in std_logic;
clk : in std_logic;
-- AMBA signals
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
-- TB signals
tbi : in tb_in_type;
tbo : out tb_out_type
);
end;
architecture tb of ahbmst_em is
constant VERSION : integer := 1;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg (VENDOR_GAISLER, GAISLER_AHBMST_EM, 0, VERSION, 0),
others => zero32);
constant T_O : integer := timeoutc;
type state_type is(idle,active,done);
type reg_type is record
state : state_type;
current_word : integer;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
tocnt : integer;
running : std_logic;
longfile : std_logic;
active : std_logic;
grant : std_logic;
ahbmo : ahb_mst_out_type;
end record;
signal r,rin : reg_type;
signal fileahbmo : ahb_mst_out_type;
begin
tb : process(tbi,ahbmi,r,rst)
variable v : reg_type;
variable status : status_type;
variable ready : std_logic;
variable ahbm : ahb_mst_out_type;
variable newaddress : std_logic_vector(31 downto 0);
variable inc : std_logic_vector(3 downto 0);
begin
v := r; ahbm := AHB_IDLE; newaddress := r.address;
v.tocnt := 0; ready := '0'; inc := (others => '0');
ahbm.hconfig := hconfig;
if tbi.start = '1' then
if (r.running = '0' and r.state = idle) then
v.address := tbi.address;
status := OK;
v.running := '1';
end if;
case tbi.command is
when RD_SINGLE => ahbm := READ_SINGLE;
when RD_INCR => ahbm := READ_INCR;
when WR_SINGLE => ahbm := WRITE_SINGLE;
when WR_INCR => ahbm := WRITE_INCR;
when others =>
end case;
ahbm.hwdata := tbi.data;
end if;
inc(conv_integer(ahbm.hsize)) := '1';
if ((r.active and not ahbmi.hresp(1)) = '1') then
if ahbm.htrans = HTRANS_NONSEQ then
ahbm.htrans := HTRANS_SEQ; newaddress := newaddress+inc;
end if;
if ahbmi.hready = '1' then
v.address := r.address + inc; v.current_word := r.current_word+1;
end if;
if newaddress(9 downto 0) = "0000000000" then ahbm.htrans := HTRANS_NONSEQ; end if;
end if;
if v.current_word >= tbi.no_words then ahbm.htrans := HTRANS_IDLE; end if;
ahbm.haddr := newaddress;
if tbi.userfile then
if ahbmi.hresp(1) = '0' then
v.ahbmo := fileahbmo;
v.ahbmo.hwrite := ahbm.hwrite;
ahbm.haddr := fileahbmo.haddr;
if ahbmi.hready = '1' then v.data := fileahbmo.hwdata; end if;
ahbm.hwdata := r.data;
if r.longfile = '1' then
ahbm.htrans := fileahbmo.htrans;
ahbm.hburst := fileahbmo.hburst;
ahbm.hsize := fileahbmo.hsize;
ahbm.hprot := fileahbmo.hprot;
end if;
else ahbm := r.ahbmo; end if;
end if;
if ahbmi.hresp = HRESP_ERROR then status := ERR;
elsif r.tocnt = T_O then status := TIMEOUT; end if;
case r.state is
when idle =>
if r.running = '1' then
v.state := active;
end if;
when active =>
v.tocnt := r.tocnt + 1;
ahbm.hbusreq := r.running;
if (r.grant and ahbmi.hready) = '1' then v.tocnt := 0; end if;
if (v.current_word >= tbi.no_words and r.grant = '1' and tbi.userfile = false) then v.running := '0'; ahbm.hbusreq := '0'; end if;
if (status /= OK or ((ahbmi.hready and not r.running) = '1' and ahbmi.hresp = HRESP_OKAY)) then
v.state := done; ahbm.htrans := HTRANS_IDLE;
end if;
when done =>
v.running := '0'; ready := '1';
if tbi.start = '0' then
v.state := idle; v.longfile := '0';
v.current_word := 0;
end if;
when others =>
end case;
if ahbmi.hready = '1' then
v.grant := ahbmi.hgrant(hindex);
if ahbm.htrans /= HTRANS_IDLE then v.active := r.grant;
else v.active := '0'; end if;
end if;
ahbm.hindex := hindex;
if rst = '0' then
v.address := (others => '0');
v.state := idle;
v.running := '0';
v.current_word := 0;
v.tocnt := 0;
v.longfile := '0';
v.ahbmo := AHB_IDLE;
end if;
tbo.ready <= ready;
tbo.status <= status;
rin <= v;
ahbmo <= ahbm;
end process;
tbo.data <= ahbmi.hrdata when (ahbmi.hready and r.running) = '1';
cpur : process (clk)
file datafile_write,datafile_read :text;
variable L : line;
variable dataint : integer;
variable datahex : string(1 to 8);
variable count : integer;
begin
if rising_edge (clk) then
r <= rin;
if tbi.usewfile then
case r.state is
when idle =>
if r.running = '1' then
file_open(datafile_write,external_name => tbi.wfile(18 downto trimlen(tbi.wfile)), open_kind => write_mode);
count := 0;
end if;
when active =>
if ((r.active and ahbmi.hready) = '1' and ahbmi.hresp = HRESP_OKAY) then
if (tbi.userfile = false or count > 0) then
write(L,printhex(ahbmi.hrdata,32));
writeline(datafile_write,L);
end if;
count := count+1;
end if;
if rin.state = done then file_close(datafile_write); end if;
when done =>
when others =>
end case;
end if;
if tbi.userfile then
case r.state is
when idle =>
if r.running = '1' then
fileahbmo <= AHB_IDLE; fileahbmo.hwrite <= rin.ahbmo.hwrite;
file_open(datafile_read,external_name => tbi.rfile(18 downto trimlen(tbi.rfile)), open_kind => read_mode);
readline(datafile_read,L); read(L,dataint);
if dataint = 1 then r.longfile <= '1';
else r.longfile <= '0'; end if;
end if;
when active =>
if ((ahbmi.hgrant(hindex) and ahbmi.hready) = '1' and ahbmi.hresp = HRESP_OKAY) then
if not endfile(datafile_read) then
if r.longfile = '1' then
readline(datafile_read,L); -- Dummy read for header
readline(datafile_read,L); read(L,dataint);
fileahbmo.htrans <= conv_std_logic_vector(dataint,2);
readline(datafile_read,L); read(L,dataint);
fileahbmo.hburst <= conv_std_logic_vector(dataint,3);
readline(datafile_read,L); read(L,dataint);
fileahbmo.hsize <= conv_std_logic_vector(dataint,3);
readline(datafile_read,L); read(L,dataint);
fileahbmo.hprot <= conv_std_logic_vector(dataint,4);
readline(datafile_read,L); read(L,datahex);
fileahbmo.haddr <= conv_std_logic_vector(datahex,32);
readline(datafile_read,L); read(L,datahex);
fileahbmo.hwdata <= conv_std_logic_vector(datahex,32);
else
readline(datafile_read,L); -- Dummy read for header
readline(datafile_read,L); read(L,datahex);
fileahbmo.haddr <= conv_std_logic_vector(datahex,32);
readline(datafile_read,L); read(L,datahex);
fileahbmo.hwdata <= conv_std_logic_vector(datahex,32);
end if;
else r.running <= '0'; end if;
end if;
when done =>
if tbi.start = '0' then
file_close(datafile_read);
end if;
when others =>
end case;
end if;
end if;
end process;
bootmsg : report_version
generic map ("pcimst_em" & tost(hindex) &
": PCI Master Emulator rev " & tost(VERSION) &
" for simulation purpose only." &
" NOT syntheziseable.");
end;
-- pragma translate_on
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbmst_em
-- File: ahbmst_em.vhd
-- Author: Alf Vaerneus, Gaisler Research
-- Description: AMBA AHB Master emulator for simulation purposes only
------------------------------------------------------------------------------
-- pragma translate_off
library IEEE;
use IEEE.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.ambatest.all;
library std;
use std.textio.all;
entity ahbmst_em is
generic(
hindex : integer := 0;
timeoutc : integer := 100;
dbglevel : integer := 2
);
port(
rst : in std_logic;
clk : in std_logic;
-- AMBA signals
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
-- TB signals
tbi : in tb_in_type;
tbo : out tb_out_type
);
end;
architecture tb of ahbmst_em is
constant VERSION : integer := 1;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg (VENDOR_GAISLER, GAISLER_AHBMST_EM, 0, VERSION, 0),
others => zero32);
constant T_O : integer := timeoutc;
type state_type is(idle,active,done);
type reg_type is record
state : state_type;
current_word : integer;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
tocnt : integer;
running : std_logic;
longfile : std_logic;
active : std_logic;
grant : std_logic;
ahbmo : ahb_mst_out_type;
end record;
signal r,rin : reg_type;
signal fileahbmo : ahb_mst_out_type;
begin
tb : process(tbi,ahbmi,r,rst)
variable v : reg_type;
variable status : status_type;
variable ready : std_logic;
variable ahbm : ahb_mst_out_type;
variable newaddress : std_logic_vector(31 downto 0);
variable inc : std_logic_vector(3 downto 0);
begin
v := r; ahbm := AHB_IDLE; newaddress := r.address;
v.tocnt := 0; ready := '0'; inc := (others => '0');
ahbm.hconfig := hconfig;
if tbi.start = '1' then
if (r.running = '0' and r.state = idle) then
v.address := tbi.address;
status := OK;
v.running := '1';
end if;
case tbi.command is
when RD_SINGLE => ahbm := READ_SINGLE;
when RD_INCR => ahbm := READ_INCR;
when WR_SINGLE => ahbm := WRITE_SINGLE;
when WR_INCR => ahbm := WRITE_INCR;
when others =>
end case;
ahbm.hwdata := tbi.data;
end if;
inc(conv_integer(ahbm.hsize)) := '1';
if ((r.active and not ahbmi.hresp(1)) = '1') then
if ahbm.htrans = HTRANS_NONSEQ then
ahbm.htrans := HTRANS_SEQ; newaddress := newaddress+inc;
end if;
if ahbmi.hready = '1' then
v.address := r.address + inc; v.current_word := r.current_word+1;
end if;
if newaddress(9 downto 0) = "0000000000" then ahbm.htrans := HTRANS_NONSEQ; end if;
end if;
if v.current_word >= tbi.no_words then ahbm.htrans := HTRANS_IDLE; end if;
ahbm.haddr := newaddress;
if tbi.userfile then
if ahbmi.hresp(1) = '0' then
v.ahbmo := fileahbmo;
v.ahbmo.hwrite := ahbm.hwrite;
ahbm.haddr := fileahbmo.haddr;
if ahbmi.hready = '1' then v.data := fileahbmo.hwdata; end if;
ahbm.hwdata := r.data;
if r.longfile = '1' then
ahbm.htrans := fileahbmo.htrans;
ahbm.hburst := fileahbmo.hburst;
ahbm.hsize := fileahbmo.hsize;
ahbm.hprot := fileahbmo.hprot;
end if;
else ahbm := r.ahbmo; end if;
end if;
if ahbmi.hresp = HRESP_ERROR then status := ERR;
elsif r.tocnt = T_O then status := TIMEOUT; end if;
case r.state is
when idle =>
if r.running = '1' then
v.state := active;
end if;
when active =>
v.tocnt := r.tocnt + 1;
ahbm.hbusreq := r.running;
if (r.grant and ahbmi.hready) = '1' then v.tocnt := 0; end if;
if (v.current_word >= tbi.no_words and r.grant = '1' and tbi.userfile = false) then v.running := '0'; ahbm.hbusreq := '0'; end if;
if (status /= OK or ((ahbmi.hready and not r.running) = '1' and ahbmi.hresp = HRESP_OKAY)) then
v.state := done; ahbm.htrans := HTRANS_IDLE;
end if;
when done =>
v.running := '0'; ready := '1';
if tbi.start = '0' then
v.state := idle; v.longfile := '0';
v.current_word := 0;
end if;
when others =>
end case;
if ahbmi.hready = '1' then
v.grant := ahbmi.hgrant(hindex);
if ahbm.htrans /= HTRANS_IDLE then v.active := r.grant;
else v.active := '0'; end if;
end if;
ahbm.hindex := hindex;
if rst = '0' then
v.address := (others => '0');
v.state := idle;
v.running := '0';
v.current_word := 0;
v.tocnt := 0;
v.longfile := '0';
v.ahbmo := AHB_IDLE;
end if;
tbo.ready <= ready;
tbo.status <= status;
rin <= v;
ahbmo <= ahbm;
end process;
tbo.data <= ahbmi.hrdata when (ahbmi.hready and r.running) = '1';
cpur : process (clk)
file datafile_write,datafile_read :text;
variable L : line;
variable dataint : integer;
variable datahex : string(1 to 8);
variable count : integer;
begin
if rising_edge (clk) then
r <= rin;
if tbi.usewfile then
case r.state is
when idle =>
if r.running = '1' then
file_open(datafile_write,external_name => tbi.wfile(18 downto trimlen(tbi.wfile)), open_kind => write_mode);
count := 0;
end if;
when active =>
if ((r.active and ahbmi.hready) = '1' and ahbmi.hresp = HRESP_OKAY) then
if (tbi.userfile = false or count > 0) then
write(L,printhex(ahbmi.hrdata,32));
writeline(datafile_write,L);
end if;
count := count+1;
end if;
if rin.state = done then file_close(datafile_write); end if;
when done =>
when others =>
end case;
end if;
if tbi.userfile then
case r.state is
when idle =>
if r.running = '1' then
fileahbmo <= AHB_IDLE; fileahbmo.hwrite <= rin.ahbmo.hwrite;
file_open(datafile_read,external_name => tbi.rfile(18 downto trimlen(tbi.rfile)), open_kind => read_mode);
readline(datafile_read,L); read(L,dataint);
if dataint = 1 then r.longfile <= '1';
else r.longfile <= '0'; end if;
end if;
when active =>
if ((ahbmi.hgrant(hindex) and ahbmi.hready) = '1' and ahbmi.hresp = HRESP_OKAY) then
if not endfile(datafile_read) then
if r.longfile = '1' then
readline(datafile_read,L); -- Dummy read for header
readline(datafile_read,L); read(L,dataint);
fileahbmo.htrans <= conv_std_logic_vector(dataint,2);
readline(datafile_read,L); read(L,dataint);
fileahbmo.hburst <= conv_std_logic_vector(dataint,3);
readline(datafile_read,L); read(L,dataint);
fileahbmo.hsize <= conv_std_logic_vector(dataint,3);
readline(datafile_read,L); read(L,dataint);
fileahbmo.hprot <= conv_std_logic_vector(dataint,4);
readline(datafile_read,L); read(L,datahex);
fileahbmo.haddr <= conv_std_logic_vector(datahex,32);
readline(datafile_read,L); read(L,datahex);
fileahbmo.hwdata <= conv_std_logic_vector(datahex,32);
else
readline(datafile_read,L); -- Dummy read for header
readline(datafile_read,L); read(L,datahex);
fileahbmo.haddr <= conv_std_logic_vector(datahex,32);
readline(datafile_read,L); read(L,datahex);
fileahbmo.hwdata <= conv_std_logic_vector(datahex,32);
end if;
else r.running <= '0'; end if;
end if;
when done =>
if tbi.start = '0' then
file_close(datafile_read);
end if;
when others =>
end case;
end if;
end if;
end process;
bootmsg : report_version
generic map ("pcimst_em" & tost(hindex) &
": PCI Master Emulator rev " & tost(VERSION) &
" for simulation purpose only." &
" NOT syntheziseable.");
end;
-- pragma translate_on
|
-- Copyright (C) 2014 Roland Dobai
--
-- This file is part of ZyEHW.
--
-- ZyEHW is free software: you can redistribute it and/or modify it under the
-- terms of the GNU General Public License as published by the Free Software
-- Foundation, either version 3 of the License, or (at your option) any later
-- version.
--
-- ZyEHW is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ZyEHW. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.zyehw_pkg.all;
entity fitness_controler is
port (
clk: in std_logic;
pe_start: in std_logic;
fitness_wr: out std_logic;
fitness_en: out std_logic;
fitness_rst: out std_logic
);
end fitness_controler;
architecture behav_fitness_controler of fitness_controler is
component counter is
generic (
BITS: integer
);
port (
clk: in std_logic;
en: in std_logic;
rst: in std_logic;
count: out std_logic_vector(BITS-1 downto 0)
);
end component;
type state_t is (
wait_start,
wait_pe_array_delay,
process_row,
skip_to_next_row,
next_row,
complete_fitness,
write_fitness,
back_to_beginning
);
constant zero: std_logic:= '0';
constant fitness_delay: integer:= 4 - 1;
constant pe_delay: integer:= 2*columns-1;
constant pe_delay_bits: integer:= integer(ceil(log2(real(pe_delay))));
constant img_edge_bits: integer:= integer(ceil(log2(real(img_size))));
constant fitness_delay_bits: integer:=
integer(ceil(log2(real(fitness_delay))));
constant next_row_skip: integer:= img_kernel - 1;
constant int_columns: integer:= (img_size - 1) - next_row_skip;
constant skip_columns: integer:= (img_size - 1)
- 1; -- there is an increment in the next cycle too
constant int_rows: integer:= int_columns;
signal state: state_t:= wait_start;
signal next_state: state_t;
signal tmp_fitness_wr: std_logic;
signal tmp_fitness_en: std_logic;
signal tmp_fitness_rst: std_logic;
signal fitness_wr_reg: std_logic:= '0';
signal fitness_en_reg: std_logic:= '0';
signal fitness_rst_reg: std_logic:= '0';
signal pe_delay_count_en, pe_delay_count_rst: std_logic;
signal pe_delay_count: std_logic_vector(pe_delay_bits-1 downto 0);
signal column_count_en: std_logic;
signal column_count: std_logic_vector(img_edge_bits-1 downto 0);
signal row_count_en: std_logic;
signal row_count: std_logic_vector(img_edge_bits-1 downto 0);
signal fitness_delay_count_en, fitness_delay_count_rst: std_logic;
signal fitness_delay_count: std_logic_vector(fitness_delay_bits-1 downto
0);
begin
pe_delay_counter: counter
generic map (
BITS => pe_delay_bits
)
port map (
clk => clk,
en => pe_delay_count_en,
rst => pe_delay_count_rst,
count => pe_delay_count
);
column_counter: counter
generic map (
BITS => img_edge_bits
)
port map (
clk => clk,
en => column_count_en,
rst => zero,
count => column_count
);
row_counter: counter
generic map (
BITS => img_edge_bits
)
port map (
clk => clk,
en => row_count_en,
rst => zero,
count => row_count
);
fitness_delay_counter: counter
generic map (
BITS => fitness_delay_bits
)
port map (
clk => clk,
en => fitness_delay_count_en,
rst => fitness_delay_count_rst,
count => fitness_delay_count
);
next_state_p: process (state, pe_delay_count, column_count, row_count,
fitness_delay_count, pe_start)
begin
case state is
when wait_start =>
if pe_start = '1' then
next_state <= wait_pe_array_delay;
else
next_state <= wait_start;
end if;
when wait_pe_array_delay =>
if pe_delay_count = std_logic_vector(to_unsigned(pe_delay,
pe_delay_bits)) then
next_state <= process_row;
else
next_state <= wait_pe_array_delay;
end if;
when process_row =>
if column_count = std_logic_vector(to_unsigned(int_columns,
img_edge_bits)) then
next_state <= skip_to_next_row;
else
next_state <= process_row;
end if;
when skip_to_next_row =>
if column_count = std_logic_vector(to_unsigned(skip_columns,
img_edge_bits)) then
next_state <= next_row;
else
next_state <= skip_to_next_row;
end if;
when next_row =>
if row_count = std_logic_vector(to_unsigned(int_rows,
img_edge_bits)) then
next_state <= complete_fitness;
else
next_state <= process_row;
end if;
when complete_fitness =>
if fitness_delay_count =
std_logic_vector(to_unsigned(fitness_delay-1,
fitness_delay_bits)) then
next_state <= write_fitness;
else
next_state <= complete_fitness;
end if;
when write_fitness =>
next_state <= back_to_beginning;
when back_to_beginning =>
if row_count = std_logic_vector(to_unsigned(img_size-1,
img_edge_bits)) then
next_state <= wait_start;
else
next_state <= back_to_beginning;
end if;
end case;
end process;
output_p: process (state)
begin
tmp_fitness_wr <= '0';
tmp_fitness_en <= '0';
tmp_fitness_rst <= '0';
pe_delay_count_en <= '0';
pe_delay_count_rst <= '0';
column_count_en <= '0';
row_count_en <= '0';
fitness_delay_count_en <= '0';
fitness_delay_count_rst <= '0';
case state is
when wait_start =>
tmp_fitness_rst <= '1';
pe_delay_count_rst <= '1';
when wait_pe_array_delay =>
pe_delay_count_en <= '1';
when process_row =>
column_count_en <= '1';
tmp_fitness_en <= '1';
when skip_to_next_row =>
column_count_en <= '1';
when next_row =>
column_count_en <= '1';
row_count_en <= '1';
when complete_fitness =>
tmp_fitness_en <= '1';
fitness_delay_count_en <= '1';
when write_fitness =>
tmp_fitness_wr <= '1';
fitness_delay_count_rst <= '1';
when back_to_beginning =>
row_count_en <= '1';
end case;
end process;
process (clk)
begin
if clk'event and clk = '1' then
state <= next_state;
fitness_wr_reg <= tmp_fitness_wr;
fitness_en_reg <= tmp_fitness_en;
fitness_rst_reg <= tmp_fitness_rst;
end if;
end process;
fitness_wr <= fitness_wr_reg;
fitness_en <= fitness_en_reg;
fitness_rst <= fitness_rst_reg;
end behav_fitness_controler;
|
--!
--! \file mem_plb46.vhd
--!
--! Memory bus interface for the 64-bit PLB v34.
--!
--! \author Enno Luebbers <enno.luebbers@upb.de>
--! \date 08.12.2008
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
--
-- This file is part of ReconOS (http://www.reconos.de).
-- Copyright (c) 2006-2010 The ReconOS Project and contributors (see AUTHORS).
-- All rights reserved.
--
-- ReconOS is free software: you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- ReconOS is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ReconOS. If not, see <http://www.gnu.org/licenses/>.
--
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
-- Major Changes:
--
-- 08.12.2008 Enno Luebbers File created.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
library xps_osif_v2_01_a;
use xps_osif_v2_01_a.all;
entity mem_plb46 is
generic
(
-- Bus protocol parameters
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_PLB_AWIDTH : integer := 32;
C_PLB_DWIDTH : integer := 64;
--C_NUM_CE : integer := 2;
C_BURST_AWIDTH : integer := 13 -- 1024 x 64 Bit = 8192 Bytes = 2^13 Bytes
);
port
(
clk : in std_logic;
reset : in std_logic;
-- data interface ---------------------------
-- burst mem interface
o_burstAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_burstData : out std_logic_vector(0 to C_PLB_DWIDTH-1);
i_burstData : in std_logic_vector(0 to C_PLB_DWIDTH-1);
o_burstWE : out std_logic;
o_burstBE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1);
-- single word data input/output
i_singleData : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
-- osif2bus
o_singleData : out std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
-- bus2osif
-- control interface ------------------------
-- addresses for master transfers
i_localAddr : in std_logic_vector(0 to C_AWIDTH-1);
i_targetAddr : in std_logic_vector(0 to C_AWIDTH-1);
-- single word transfer requests
i_singleRdReq : in std_logic;
i_singleWrReq : in std_logic;
-- burst transfer requests
i_burstRdReq : in std_logic;
i_burstWrReq : in std_logic;
i_burstLen : in std_logic_vector(0 to 11); -- number of bytes to transfer (0..4096)
-- status outputs
o_busy : out std_logic;
o_rdDone : out std_logic;
o_wrDone : out std_logic;
-- PLBv34 bus interface -----------------------------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_MstError : in std_logic;
Bus2IP_MstLastAck : in std_logic;
Bus2IP_MstRdAck : in std_logic;
Bus2IP_MstWrAck : in std_logic;
Bus2IP_MstRetry : in std_logic;
Bus2IP_MstTimeOut : in std_logic;
Bus2IP_Mst_CmdAck : in std_logic;
Bus2IP_Mst_Cmplt : in std_logic;
Bus2IP_Mst_Error : in std_logic;
Bus2IP_Mst_Cmd_Timeout : in std_logic;
IP2Bus_Addr : out std_logic_vector(0 to C_AWIDTH-1);
IP2Bus_MstBE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1);
IP2Bus_MstBurst : out std_logic;
IP2Bus_MstBusReset : out std_logic;
IP2Bus_MstBusLock : out std_logic;
IP2Bus_MstNum : out std_logic_vector(0 to 11);
IP2Bus_MstRdReq : out std_logic;
IP2Bus_MstWrReq : out std_logic;
-- LocalLink Interface
Bus2IP_MstRd_d : in std_logic_vector(0 to C_PLB_DWIDTH-1);
Bus2IP_MstRd_rem : in std_logic_vector(0 to C_PLB_DWIDTH/8-1);
Bus2IP_MstRd_sof_n : in std_logic;
Bus2IP_MstRd_eof_n : in std_logic;
Bus2IP_MstRd_src_rdy_n : in std_logic;
Bus2IP_MstRd_src_dsc_n : in std_logic;
IP2Bus_MstRd_dst_rdy_n : out std_logic;
IP2Bus_MstRd_dst_dsc_n : out std_logic;
IP2Bus_MstWr_d : out std_logic_vector(0 to C_PLB_DWIDTH-1);
IP2Bus_MstWr_rem : out std_logic_vector(0 to C_PLB_DWIDTH/8-1);
IP2Bus_MstWr_sof_n : out std_logic;
IP2Bus_MstWr_eof_n : out std_logic;
IP2Bus_MstWr_src_rdy_n : out std_logic;
IP2Bus_MstWr_src_dsc_n : out std_logic;
Bus2IP_MstWr_dst_rdy_n : in std_logic;
Bus2IP_MstWr_dst_dsc_n : in std_logic
);
end entity mem_plb46;
architecture arch of mem_plb46 is
constant BYTES_PER_BEAT : integer := C_PLB_DWIDTH/8;
-- signals for master model command interface state machine
type CMD_CNTL_SM_TYPE is (CMD_IDLE, CMD_RUN, CMD_WAIT_FOR_DATA, CMD_DONE);
signal mst_cmd_sm_state : CMD_CNTL_SM_TYPE;
signal mst_cmd_sm_set_done : std_logic;
signal mst_cmd_sm_set_error : std_logic;
signal mst_cmd_sm_set_timeout : std_logic;
signal mst_cmd_sm_busy : std_logic;
signal mst_cmd_sm_clr_go : std_logic;
signal mst_cmd_sm_rd_req : std_logic;
signal mst_cmd_sm_wr_req : std_logic;
signal mst_cmd_sm_reset : std_logic;
signal mst_cmd_sm_bus_lock : std_logic;
signal mst_cmd_sm_ip2bus_addr : std_logic_vector(0 to C_PLB_AWIDTH-1);
signal mst_cmd_sm_ip2bus_be : std_logic_vector(0 to C_PLB_DWIDTH/8-1);
signal mst_cmd_sm_xfer_type : std_logic;
signal mst_cmd_sm_xfer_length : std_logic_vector(0 to 11);
signal mst_cmd_sm_start_rd_llink : std_logic;
signal mst_cmd_sm_start_wr_llink : std_logic;
-- signals for master model read locallink interface state machine
type RD_LLINK_SM_TYPE is (LLRD_IDLE, LLRD_GO);
signal mst_llrd_sm_state : RD_LLINK_SM_TYPE;
signal mst_llrd_sm_dst_rdy : std_logic;
-- signals for master model write locallink interface state machine
type WR_LLINK_SM_TYPE is (LLWR_IDLE, LLWR_SNGL_INIT, LLWR_SNGL, LLWR_BRST_INIT, LLWR_BRST, LLWR_BRST_LAST_BEAT);
signal mst_llwr_sm_state : WR_LLINK_SM_TYPE;
signal mst_llwr_sm_src_rdy : std_logic;
signal mst_llwr_sm_sof : std_logic;
signal mst_llwr_sm_eof : std_logic;
signal mst_llwr_byte_cnt : integer;
signal bram_offset : integer;
signal mst_fifo_valid_write_xfer : std_logic;
signal mst_fifo_valid_read_xfer : std_logic;
signal mst_fifo_valid_read_xfer_d1 : std_logic;
signal mst_xfer_length : std_logic_vector(0 to 11);
signal mst_cntl_rd_req : std_logic;
signal mst_cntl_wr_req : std_logic;
signal mst_cntl_bus_lock : std_logic;
signal mst_cntl_burst : std_logic;
signal mst_ip2bus_addr : std_logic_vector(0 to C_PLB_AWIDTH-1);
signal mst_ip2bus_be : std_logic_vector(0 to 7); -- FIXME: Hardcoded for 64 bit master
signal mst_go : std_logic;
signal xfer_cross_wrd_bndry : std_logic;
signal rolled_MstRd_d : std_logic_vector(0 to C_PLB_DWIDTH-1);
signal rolled_mst_ip2bus_be : std_logic_vector(0 to 7);
signal be_offset : integer range 0 to 7;
signal prefetch_data : std_logic_vector(0 to C_PLB_DWIDTH-1) ;
signal burstData_current : std_logic_vector(0 to C_PLB_DWIDTH-1) ;
signal prefetch_first : std_logic;
signal save_first : std_logic;
begin
-- get byte enable offset from target address
be_offset <= TO_INTEGER(ieee.numeric_std.unsigned(i_targetAddr(C_AWIDTH-3 to C_AWIDTH-1)));
mst_reg : process(Bus2IP_Clk, Bus2IP_Reset)
constant BE_32 : std_logic_vector := X"F0";
begin
if Bus2IP_Reset = '1' then
mst_xfer_length <= (others => '0');
mst_cntl_rd_req <= '0';
mst_cntl_wr_req <= '0';
mst_ip2bus_addr <= (others => '0');
mst_ip2bus_be <= (others => '0');
mst_cntl_burst <= '0';
xfer_cross_wrd_bndry <= '0';
mst_go <= '0';
elsif rising_edge(Bus2IP_Clk) then
if (i_burstRdReq = '1' or i_burstWrReq = '1') then -- if incoming burst request
mst_xfer_length <= i_burstLen(3 to 11) & "000"; -- burst length in bytes
mst_cntl_rd_req <= i_burstRdReq; -- read request
mst_cntl_wr_req <= i_burstWrReq; -- write request
mst_ip2bus_addr <= i_targetAddr; -- target address
mst_cntl_burst <= '1'; -- burst
xfer_cross_wrd_bndry <= '0'; -- bursts can't cross word boundary
mst_ip2bus_be <= X"00"; -- bursts do not look at BE
mst_go <= '1';
elsif (i_singleRdReq = '1' or i_singleWrReq = '1') then
mst_cntl_rd_req <= i_singleRdReq; -- read request
mst_cntl_wr_req <= i_singleWrReq; -- write request
mst_ip2bus_addr <= i_targetAddr; -- target address
mst_cntl_burst <= '0'; -- no burst
mst_ip2bus_be <= std_logic_vector(ieee.numeric_std.unsigned(BE_32) srl be_offset); -- calc byte enables from address
if be_offset > 4 then
-- 32 Bit transfer across 64 Bit boundary, we need to split this
xfer_cross_wrd_bndry <= '1';
end if;
mst_go <= '1';
elsif mst_cmd_sm_set_done = '1' and xfer_cross_wrd_bndry = '1' then -- if last transfer was a single word that crossed a 64bit boundary
xfer_cross_wrd_bndry <= '0'; -- repeat transfer with remaining data
mst_ip2bus_addr <= i_targetAddr + 8-be_offset; -- new target address
mst_ip2bus_be <= std_logic_vector(ieee.numeric_std.unsigned(BE_32) sll 8-be_offset); -- remaining byte enables
mst_go <= '1';
elsif mst_cmd_sm_clr_go = '1' then
mst_go <= '0';
end if;
end if;
end process;
-- command_decoder protocol to mst_* protocol conversion assignments
mst_cntl_bus_lock <= '0'; -- never lock the bus
-- user logic master command interface assignments
IP2Bus_MstRdReq <= mst_cmd_sm_rd_req;
IP2Bus_MstWrReq <= mst_cmd_sm_wr_req;
IP2Bus_Addr <= mst_cmd_sm_ip2bus_addr;
IP2Bus_MstBE <= mst_cmd_sm_ip2bus_be;
IP2Bus_MstBurst <= mst_cmd_sm_xfer_type;
IP2Bus_MstNum <= mst_cmd_sm_xfer_length;
IP2Bus_MstBusLock <= mst_cmd_sm_bus_lock;
IP2Bus_MstBusReset <= mst_cmd_sm_reset;
-- handshake output signals
o_busy <= mst_cmd_sm_busy or mst_go or i_singleRdReq or i_singleWrReq or i_burstRdReq or i_burstWrReq or mst_cmd_sm_set_done;
o_rdDone <= mst_cmd_sm_set_done and mst_cntl_rd_req and not xfer_cross_wrd_bndry;
o_wrDone <= mst_cmd_sm_set_done and mst_cntl_wr_req and not xfer_cross_wrd_bndry;
--implement master command interface state machine
MASTER_CMD_SM_PROC : process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Bus2IP_Reset = '1') then
-- reset condition
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_clr_go <= '0';
mst_cmd_sm_rd_req <= '0';
mst_cmd_sm_wr_req <= '0';
mst_cmd_sm_bus_lock <= '0';
mst_cmd_sm_reset <= '0';
mst_cmd_sm_ip2bus_addr <= (others => '0');
mst_cmd_sm_ip2bus_be <= (others => '0');
mst_cmd_sm_xfer_type <= '0';
mst_cmd_sm_xfer_length <= (others => '0');
mst_cmd_sm_set_done <= '0';
mst_cmd_sm_set_error <= '0';
mst_cmd_sm_set_timeout <= '0';
mst_cmd_sm_busy <= '0';
mst_cmd_sm_start_rd_llink <= '0';
mst_cmd_sm_start_wr_llink <= '0';
else
-- default condition
mst_cmd_sm_clr_go <= '0';
mst_cmd_sm_rd_req <= '0';
mst_cmd_sm_wr_req <= '0';
mst_cmd_sm_bus_lock <= '0';
mst_cmd_sm_reset <= '0';
mst_cmd_sm_ip2bus_addr <= (others => '0');
mst_cmd_sm_ip2bus_be <= (others => '0');
mst_cmd_sm_xfer_type <= '0';
mst_cmd_sm_xfer_length <= (others => '0');
mst_cmd_sm_set_done <= '0';
mst_cmd_sm_set_error <= '0';
mst_cmd_sm_set_timeout <= '0';
mst_cmd_sm_busy <= '1';
mst_cmd_sm_start_rd_llink <= '0';
mst_cmd_sm_start_wr_llink <= '0';
-- state transition
case mst_cmd_sm_state is
-- waiting for transfer
when CMD_IDLE =>
if (mst_go = '1') then -- new transfer initiated?
mst_cmd_sm_state <= CMD_RUN; -- go to RUN state
mst_cmd_sm_clr_go <= '1'; -- clear go register (REMOVEME)
if (mst_cntl_rd_req = '1') then -- read request?
mst_cmd_sm_start_rd_llink <= '1'; -- start ll read
elsif (mst_cntl_wr_req = '1') then -- write request?
mst_cmd_sm_start_wr_llink <= '1'; -- start ll write
end if;
else
mst_cmd_sm_state <= CMD_IDLE; -- otherwise, stay here and do nothing
mst_cmd_sm_busy <= '0';
end if;
-- transfer initiated
when CMD_RUN =>
if (Bus2IP_Mst_CmdAck = '1' and Bus2IP_Mst_Cmplt = '0') then -- command acknowledged and not completed?
mst_cmd_sm_state <= CMD_WAIT_FOR_DATA; -- go to WAIT_FOR_DATA state
elsif (Bus2IP_Mst_Cmplt = '1') then -- command completed?
mst_cmd_sm_state <= CMD_DONE; -- go to DONE state
if (Bus2IP_Mst_Cmd_Timeout = '1') then -- was it a timeout?
-- PLB address phase timeout
mst_cmd_sm_set_error <= '1'; -- set error and timeout flags
mst_cmd_sm_set_timeout <= '1';
elsif (Bus2IP_Mst_Error = '1') then -- was it an error
-- PLB data transfer error
mst_cmd_sm_set_error <= '1'; -- set only the error flag
end if;
else
mst_cmd_sm_state <= CMD_RUN; -- if it wasn't acknowledged or completed yet (i.e. new request)
mst_cmd_sm_rd_req <= mst_cntl_rd_req; -- set read and write request flags
mst_cmd_sm_wr_req <= mst_cntl_wr_req;
mst_cmd_sm_ip2bus_addr <= mst_ip2bus_addr; -- set target address
mst_cmd_sm_ip2bus_be <= mst_ip2bus_be; -- set byte enables
mst_cmd_sm_xfer_type <= mst_cntl_burst; -- set transfer type
mst_cmd_sm_xfer_length <= mst_xfer_length; -- set transfer length (in bytes?)
mst_cmd_sm_bus_lock <= mst_cntl_bus_lock; -- set bus lock (always 0?)
end if; -- and stay in RUN state (i.e. wait for acceptance/abort)
-- transfer request accepted, transfer in progress
when CMD_WAIT_FOR_DATA =>
if (Bus2IP_Mst_Cmplt = '1') then -- transfer completed?
mst_cmd_sm_state <= CMD_DONE; -- go to DONE state
else -- otherwise
mst_cmd_sm_state <= CMD_WAIT_FOR_DATA; -- stay here
end if;
-- transfer completed or aborted
when CMD_DONE =>
mst_cmd_sm_state <= CMD_IDLE; -- go to IDLE state
mst_cmd_sm_set_done <= '1'; -- signal that we're done
mst_cmd_sm_busy <= '0'; -- and not busy
-- default catchall
when others =>
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_busy <= '0';
end case;
end if;
end if;
end process MASTER_CMD_SM_PROC;
----------------------------------------------------
-- LOCAL LINK INTERFACE
----------------------------------------------------
-- user logic master read locallink interface assignments
IP2Bus_MstRd_dst_rdy_n <= not(mst_llrd_sm_dst_rdy);
IP2Bus_MstRd_dst_dsc_n <= '1'; -- do not throttle data
-- implement a simple state machine to enable the
-- read locallink interface to transfer data
LLINK_RD_SM_PROCESS : process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Bus2IP_Reset = '1') then
-- reset condition
mst_llrd_sm_state <= LLRD_IDLE;
mst_llrd_sm_dst_rdy <= '0'; -- not ready to read data
else
-- default condition
mst_llrd_sm_state <= LLRD_IDLE;
mst_llrd_sm_dst_rdy <= '0'; -- not ready to read data
-- state transition
case mst_llrd_sm_state is
when LLRD_IDLE =>
if (mst_cmd_sm_start_rd_llink = '1') then -- if we got start signal from master FSM
mst_llrd_sm_state <= LLRD_GO; -- go to GO state
else
mst_llrd_sm_state <= LLRD_IDLE; -- otherwise stay here and keep waiting
end if;
when LLRD_GO =>
-- done, end of packet
if (mst_llrd_sm_dst_rdy = '1' and -- if we are ready to receive
Bus2IP_MstRd_src_rdy_n = '0' and -- the sender is ready to send
Bus2IP_MstRd_eof_n = '0') then -- and the sender is done sending
mst_llrd_sm_state <= LLRD_IDLE; -- we're done
-- not done yet, continue receiving data
else -- otherwise
mst_llrd_sm_state <= LLRD_GO; -- stay in this state
mst_llrd_sm_dst_rdy <= '1'; -- and be ready to receive
end if;
-- default catchall
when others =>
mst_llrd_sm_state <= LLRD_IDLE;
end case;
end if;
else
null;
end if;
end process LLINK_RD_SM_PROCESS;
-- user logic master write locallink interface assignments
IP2Bus_MstWr_src_rdy_n <= not(mst_llwr_sm_src_rdy);
IP2Bus_MstWr_src_dsc_n <= '1'; -- do not throttle data
IP2Bus_MstWr_rem <= (others => '0'); -- no remainder mask
IP2Bus_MstWr_sof_n <= not(mst_llwr_sm_sof);
IP2Bus_MstWr_eof_n <= not(mst_llwr_sm_eof);
-- implement a simple state machine to enable the
-- write locallink interface to transfer data
LLINK_WR_SM_PROC : process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Bus2IP_Reset = '1') then
-- reset condition
mst_llwr_sm_state <= LLWR_IDLE;
mst_llwr_sm_src_rdy <= '0';
mst_llwr_sm_sof <= '0';
mst_llwr_sm_eof <= '0';
mst_llwr_byte_cnt <= 0;
else
-- default condition
mst_llwr_sm_state <= LLWR_IDLE;
mst_llwr_sm_src_rdy <= '0';
mst_llwr_sm_sof <= '0';
mst_llwr_sm_eof <= '0';
mst_llwr_byte_cnt <= 0;
-- state transition
case mst_llwr_sm_state is
-- wait for start of transfer
when LLWR_IDLE =>
if (mst_cmd_sm_start_wr_llink = '1' and mst_cntl_burst = '0') then -- single write request?
mst_llwr_sm_state <= LLWR_SNGL_INIT;
elsif (mst_cmd_sm_start_wr_llink = '1' and mst_cntl_burst = '1') then -- burst write request?
mst_llwr_sm_state <= LLWR_BRST_INIT;
else
mst_llwr_sm_state <= LLWR_IDLE;
end if;
-- init single transfer
when LLWR_SNGL_INIT =>
mst_llwr_sm_state <= LLWR_SNGL;
mst_llwr_sm_src_rdy <= '1'; -- ready to send
mst_llwr_sm_sof <= '1'; -- signal single transfer by asserting both SOF and EOF
mst_llwr_sm_eof <= '1';
-- do single transfer
when LLWR_SNGL =>
-- destination discontinue write
if (Bus2IP_MstWr_dst_dsc_n = '0' and Bus2IP_MstWr_dst_rdy_n = '0') then -- if discontinue from target
mst_llwr_sm_state <= LLWR_IDLE; -- reset back to IDLE state
mst_llwr_sm_src_rdy <= '0';
mst_llwr_sm_eof <= '0';
-- single data beat transfer complete
elsif (mst_fifo_valid_read_xfer = '1') then -- if local memory read has been completed
mst_llwr_sm_state <= LLWR_IDLE; -- go back to IDLE state
mst_llwr_sm_src_rdy <= '0';
mst_llwr_sm_sof <= '0';
mst_llwr_sm_eof <= '0';
-- wait on destination
else
mst_llwr_sm_state <= LLWR_SNGL; -- otherwise keep trying to transfer single word
mst_llwr_sm_src_rdy <= '1';
mst_llwr_sm_sof <= '1';
mst_llwr_sm_eof <= '1';
end if;
-- init burst transfer
when LLWR_BRST_INIT =>
mst_llwr_sm_state <= LLWR_BRST;
mst_llwr_sm_src_rdy <= '1';
mst_llwr_sm_sof <= '1';
mst_llwr_byte_cnt <= CONV_INTEGER(mst_xfer_length);
-- do burst transfer
when LLWR_BRST =>
if (mst_fifo_valid_read_xfer = '1') then -- if a word has been transferred (i.e. we are actively writing)
mst_llwr_sm_sof <= '0'; -- deassert SOF signal
else
mst_llwr_sm_sof <= mst_llwr_sm_sof;
end if;
-- destination discontinue write
if (Bus2IP_MstWr_dst_dsc_n = '0' and -- if discontinue from target
Bus2IP_MstWr_dst_rdy_n = '0') then
mst_llwr_sm_state <= LLWR_IDLE; -- reset to IDLE state
mst_llwr_sm_src_rdy <= '1'; -- and properly terminate transfer
mst_llwr_sm_eof <= '1';
-- last data beat write
elsif (mst_fifo_valid_read_xfer = '1' and -- if this was the second to last beat to transfer
(mst_llwr_byte_cnt-BYTES_PER_BEAT) <= BYTES_PER_BEAT) then
mst_llwr_sm_state <= LLWR_BRST_LAST_BEAT; -- go to LAST_BEAT state
mst_llwr_sm_src_rdy <= '1'; -- and signal termination of transfer
mst_llwr_sm_eof <= '1';
-- wait on destination
else
mst_llwr_sm_state <= LLWR_BRST; -- otherwise keep writing data
mst_llwr_sm_src_rdy <= '1';
-- decrement write transfer counter if it's a valid write
if (mst_fifo_valid_read_xfer = '1') then
mst_llwr_byte_cnt <= mst_llwr_byte_cnt - BYTES_PER_BEAT;
else
mst_llwr_byte_cnt <= mst_llwr_byte_cnt;
end if;
end if;
-- do last beat of write burst
when LLWR_BRST_LAST_BEAT =>
-- destination discontinue write
if (Bus2IP_MstWr_dst_dsc_n = '0' and -- if discontinue from target
Bus2IP_MstWr_dst_rdy_n = '0') then
mst_llwr_sm_state <= LLWR_IDLE; -- reset to IDLE state
mst_llwr_sm_src_rdy <= '0'; -- and mark ourselves as not ready (?)
-- last data beat done
elsif (mst_fifo_valid_read_xfer = '1') then -- if this transfer was successful
mst_llwr_sm_state <= LLWR_IDLE; -- reset to IDLE state
mst_llwr_sm_src_rdy <= '0';
-- wait on destination
else
mst_llwr_sm_state <= LLWR_BRST_LAST_BEAT; -- otherwise keep trying to send
mst_llwr_sm_src_rdy <= '1';
mst_llwr_sm_eof <= '1';
end if;
-- default catchall
when others =>
mst_llwr_sm_state <= LLWR_IDLE;
end case;
end if;
else
null;
end if;
end process LLINK_WR_SM_PROC;
-- determine whether a data beat was successfully written
mst_fifo_valid_write_xfer <= not(Bus2IP_MstRd_src_rdy_n) and mst_llrd_sm_dst_rdy;
mst_fifo_valid_read_xfer <= not(Bus2IP_MstWr_dst_rdy_n) and mst_llwr_sm_src_rdy;
-- connect burst ram
o_burstAddr <= i_localAddr(C_AWIDTH-C_BURST_AWIDTH to C_AWIDTH-1) + bram_offset;
o_burstData <= Bus2IP_MstRd_d;
o_burstWE <= mst_cntl_rd_req and mst_cntl_burst and mst_fifo_valid_write_xfer;
o_burstBE <= (others => '1');
-- delay read enable for edge detection and prefetch
mst_fifo_valid_read_xfer_d1 <= mst_fifo_valid_read_xfer when rising_edge(clk) else mst_fifo_valid_read_xfer_d1;
-- prefetch data from burst ram for contiguous writes
prefetch : process(clk, reset)
begin
if reset = '1' then
prefetch_data <= (others => '0');
elsif rising_edge(clk) then
if mst_fifo_valid_read_xfer_d1 = '1' or save_first = '1' then
prefetch_data <= i_burstData;
end if;
end if;
end process;
-- on the first beat of a back-to-back transfer, use the prefetched data, otherwise use the RAM output
burstData_current <= prefetch_data when mst_fifo_valid_read_xfer_d1 = '0' and mst_fifo_valid_read_xfer = '1' else i_burstData;
-- generate address signals for burst ram
burst_addr : process(clk, reset)
begin
if reset = '1' then
bram_offset <= 0;
save_first <= '0';
prefetch_first <= '0';
elsif rising_edge(clk) then
save_first <= '0';
if i_burstRdReq = '1' then -- new burst request
bram_offset <= 0;
elsif i_burstWrReq = '1' then -- new burst request
bram_offset <= 0;
prefetch_first <= '1';
elsif prefetch_first = '1' then
bram_offset <= bram_offset + BYTES_PER_BEAT;
prefetch_first <= '0';
save_first <= '1';
elsif mst_fifo_valid_write_xfer = '1' or mst_fifo_valid_read_xfer = '1' then
bram_offset <= bram_offset + BYTES_PER_BEAT;
end if;
end if;
end process;
-- multiplex burst ram and single data register to bus (possibly shifted)
IP2Bus_MstWr_d <= burstData_current when mst_cntl_burst = '1' else
std_logic_vector(ieee.numeric_std.unsigned(i_singleData & X"00000000") ror be_offset*8);
-- implement single data register
rolled_MstRd_d <= std_logic_vector(ieee.numeric_std.unsigned(Bus2IP_MstRd_d) rol be_offset*8);
rolled_mst_ip2bus_be <= std_logic_vector(ieee.numeric_std.unsigned(mst_ip2bus_be) rol be_offset);
single_reg : process(Bus2IP_Clk, Bus2IP_Reset, mst_ip2bus_be)
variable bit_enable : std_logic_vector(0 to C_DWIDTH-1);
variable assembled_data : std_logic_vector(0 to C_DWIDTH-1);
begin
for i in 0 to 3 loop
bit_enable(i*8 to i*8+7) := (others => rolled_mst_ip2bus_be(i));
end loop;
if Bus2IP_Reset = '1' then
assembled_data := (others => '0');
elsif rising_edge(Bus2IP_Clk) then
if (mst_cntl_rd_req = '1' and mst_cntl_burst = '0' and mst_fifo_valid_write_xfer = '1') then
assembled_data := (assembled_data and (not bit_enable)) or (rolled_MstRd_d(0 to C_DWIDTH-1) and bit_enable);
end if;
end if;
o_singleData <= assembled_data;
end process;
end arch;
|
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00125
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (2)
-- 8.3 (3)
-- 8.3 (5)
-- 8.3.1 (3)
--
-- DESIGN UNIT ORDERING:
--
-- PKG00125
-- PKG00125/BODY
-- E00000(ARCH00125)
-- ENT00125_Test_Bench(ARCH00125_Test_Bench)
--
-- REVISION HISTORY:
--
-- 07-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
package PKG00125 is
type r_st_rec1 is record
f1 : integer ;
f2 : st_rec1 ;
end record ;
function c_r_st_rec1_1 return r_st_rec1 ;
-- (c_integer_1, c_st_rec1_1) ;
function c_r_st_rec1_2 return r_st_rec1 ;
-- (c_integer_2, c_st_rec1_2) ;
--
type r_st_rec2 is record
f1 : integer ;
f2 : st_rec2 ;
end record ;
function c_r_st_rec2_1 return r_st_rec2 ;
-- (c_integer_1, c_st_rec2_1) ;
function c_r_st_rec2_2 return r_st_rec2 ;
-- (c_integer_2, c_st_rec2_2) ;
--
type r_st_rec3 is record
f1 : integer ;
f2 : st_rec3 ;
end record ;
function c_r_st_rec3_1 return r_st_rec3 ;
-- (c_integer_1, c_st_rec3_1) ;
function c_r_st_rec3_2 return r_st_rec3 ;
-- (c_integer_2, c_st_rec3_2) ;
--
--
end PKG00125 ;
--
package body PKG00125 is
function c_r_st_rec1_1 return r_st_rec1
is begin
return (c_integer_1, c_st_rec1_1) ;
end c_r_st_rec1_1 ;
--
function c_r_st_rec1_2 return r_st_rec1
is begin
return (c_integer_2, c_st_rec1_2) ;
end c_r_st_rec1_2 ;
--
--
function c_r_st_rec2_1 return r_st_rec2
is begin
return (c_integer_1, c_st_rec2_1) ;
end c_r_st_rec2_1 ;
--
function c_r_st_rec2_2 return r_st_rec2
is begin
return (c_integer_2, c_st_rec2_2) ;
end c_r_st_rec2_2 ;
--
--
function c_r_st_rec3_1 return r_st_rec3
is begin
return (c_integer_1, c_st_rec3_1) ;
end c_r_st_rec3_1 ;
--
function c_r_st_rec3_2 return r_st_rec3
is begin
return (c_integer_2, c_st_rec3_2) ;
end c_r_st_rec3_2 ;
--
--
--
end PKG00125 ;
--
use WORK.STANDARD_TYPES.all ;
use WORK.PKG00125.all ;
architecture ARCH00125 of E00000 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_r_st_rec1 : chk_sig_type := -1 ;
signal chk_r_st_rec2 : chk_sig_type := -1 ;
signal chk_r_st_rec3 : chk_sig_type := -1 ;
--
signal s_r_st_rec1 : r_st_rec1
:= c_r_st_rec1_1 ;
signal s_r_st_rec2 : r_st_rec2
:= c_r_st_rec2_1 ;
signal s_r_st_rec3 : r_st_rec3
:= c_r_st_rec3_1 ;
--
begin
PGEN_CHKP_1 :
process ( chk_r_st_rec1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions entirely completed",
chk_r_st_rec1 = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P1 :
process ( s_r_st_rec1 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_r_st_rec1.f2.f2 <= transport
c_r_st_rec1_2.f2.f2 after 10 ns,
c_r_st_rec1_1.f2.f2 after 20 ns ;
--
when 1
=> correct :=
s_r_st_rec1.f2.f2 =
c_r_st_rec1_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_rec1.f2.f2 =
c_r_st_rec1_1.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00125.P1" ,
"Multi transport transactions occurred on signal " &
"asg with selected name prefixed by a selected name on LHS",
correct ) ;
s_r_st_rec1.f2.f2 <= transport
c_r_st_rec1_2.f2.f2 after 10 ns ,
c_r_st_rec1_1.f2.f2 after 20 ns ,
c_r_st_rec1_2.f2.f2 after 30 ns ,
c_r_st_rec1_1.f2.f2 after 40 ns ;
--
when 3
=> correct :=
s_r_st_rec1.f2.f2 =
c_r_st_rec1_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_rec1.f2.f2 <= transport
c_r_st_rec1_1.f2.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_rec1.f2.f2 =
c_r_st_rec1_1.f2.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00125" ,
"One transport transaction occurred on signal " &
"asg with selected name prefixed by a selected name on LHS",
correct ) ;
test_report ( "ARCH00125" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by a selected name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00125" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by a selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_rec1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P1 ;
--
PGEN_CHKP_2 :
process ( chk_r_st_rec2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Transport transactions entirely completed",
chk_r_st_rec2 = 4 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
P2 :
process ( s_r_st_rec2 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_r_st_rec2.f2.f2 <= transport
c_r_st_rec2_2.f2.f2 after 10 ns,
c_r_st_rec2_1.f2.f2 after 20 ns ;
--
when 1
=> correct :=
s_r_st_rec2.f2.f2 =
c_r_st_rec2_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_rec2.f2.f2 =
c_r_st_rec2_1.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00125.P2" ,
"Multi transport transactions occurred on signal " &
"asg with selected name prefixed by a selected name on LHS",
correct ) ;
s_r_st_rec2.f2.f2 <= transport
c_r_st_rec2_2.f2.f2 after 10 ns ,
c_r_st_rec2_1.f2.f2 after 20 ns ,
c_r_st_rec2_2.f2.f2 after 30 ns ,
c_r_st_rec2_1.f2.f2 after 40 ns ;
--
when 3
=> correct :=
s_r_st_rec2.f2.f2 =
c_r_st_rec2_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_rec2.f2.f2 <= transport
c_r_st_rec2_1.f2.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_rec2.f2.f2 =
c_r_st_rec2_1.f2.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00125" ,
"One transport transaction occurred on signal " &
"asg with selected name prefixed by a selected name on LHS",
correct ) ;
test_report ( "ARCH00125" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by a selected name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00125" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by a selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_rec2 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P2 ;
--
PGEN_CHKP_3 :
process ( chk_r_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Transport transactions entirely completed",
chk_r_st_rec3 = 4 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
P3 :
process ( s_r_st_rec3 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_r_st_rec3.f2.f2 <= transport
c_r_st_rec3_2.f2.f2 after 10 ns,
c_r_st_rec3_1.f2.f2 after 20 ns ;
--
when 1
=> correct :=
s_r_st_rec3.f2.f2 =
c_r_st_rec3_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_rec3.f2.f2 =
c_r_st_rec3_1.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00125.P3" ,
"Multi transport transactions occurred on signal " &
"asg with selected name prefixed by a selected name on LHS",
correct ) ;
s_r_st_rec3.f2.f2 <= transport
c_r_st_rec3_2.f2.f2 after 10 ns ,
c_r_st_rec3_1.f2.f2 after 20 ns ,
c_r_st_rec3_2.f2.f2 after 30 ns ,
c_r_st_rec3_1.f2.f2 after 40 ns ;
--
when 3
=> correct :=
s_r_st_rec3.f2.f2 =
c_r_st_rec3_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_rec3.f2.f2 <= transport
c_r_st_rec3_1.f2.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_rec3.f2.f2 =
c_r_st_rec3_1.f2.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00125" ,
"One transport transaction occurred on signal " &
"asg with selected name prefixed by a selected name on LHS",
correct ) ;
test_report ( "ARCH00125" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by a selected name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00125" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by a selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_rec3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P3 ;
--
--
end ARCH00125 ;
--
entity ENT00125_Test_Bench is
end ENT00125_Test_Bench ;
--
architecture ARCH00125_Test_Bench of ENT00125_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00125 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00125_Test_Bench ;
|
-- test2 - clock divider controlled by quadrature decoder
-- Written in 2016 by <Ahmet Inan> <xdsopl@googlemail.com>
-- To the extent possible under law, the author(s) have dedicated all copyright and related and neighboring rights to this software to the public domain worldwide. This software is distributed without any warranty.
-- You should have received a copy of the CC0 Public Domain Dedication along with this software. If not, see <http://creativecommons.org/publicdomain/zero/1.0/>.
library ieee;
use ieee.std_logic_1164.all;
entity max10_10M08E144_eval_test2 is
generic (
NUM_LEDS : positive := 5
);
port (
clock : in std_logic;
reset_n : in std_logic;
rotary_n : in std_logic_vector (1 downto 0);
leds_n : out std_logic_vector (NUM_LEDS-1 downto 0);
dclock : out std_logic
);
end max10_10M08E144_eval_test2;
architecture rtl of max10_10M08E144_eval_test2 is
attribute chip_pin : string;
attribute chip_pin of clock : signal is "27";
attribute chip_pin of dclock : signal is "62";
attribute chip_pin of reset_n : signal is "121";
attribute chip_pin of rotary_n : signal is "70, 69"; -- need to enable weak pullup resistor
attribute chip_pin of leds_n : signal is "132, 134, 135, 140, 141";
signal reset : std_logic;
signal rotary : std_logic_vector (1 downto 0);
signal leds : std_logic_vector (NUM_LEDS-1 downto 0);
begin
reset <= not reset_n;
rotary <= not rotary_n;
leds_n <= not leds;
test2_inst : entity work.test2
generic map (NUM_LEDS)
port map (clock, reset, rotary, leds, dclock);
end rtl;
|
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`protect end_protected
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:08:29 11/26/2009
-- Design Name:
-- Module Name: E:/FPGA/Projects/Current Projects/Subsystems/FlashProgrammer/FlashProgrammer_TB.vhd
-- Project Name: FlashProgrammer
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: FlashProgrammer
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY FlashProgrammer_TB IS
END FlashProgrammer_TB;
ARCHITECTURE behavior OF FlashProgrammer_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT FlashProgrammer
PORT(
board_clk : IN std_logic;
start_button : IN std_logic;
flashSTS : IN std_logic;
flashWE : OUT std_logic;
flashOE : OUT std_logic;
flashCE : OUT std_logic;
flashADDR : OUT std_logic_vector(22 downto 0);
flashDATA : INOUT std_logic_vector(15 downto 0);
flashRP : OUT std_logic;
flashDATA_to_LEDs : OUT std_logic_vector(6 downto 0);
status_LED : OUT std_logic
);
END COMPONENT;
--Inputs
signal board_clk : std_logic := '0';
signal start_button : std_logic := '0';
signal flashSTS : std_logic := '0';
--BiDirs
signal flashDATA : std_logic_vector(15 downto 0);
--Outputs
signal flashWE : std_logic;
signal flashOE : std_logic;
signal flashCE : std_logic;
signal flashADDR : std_logic_vector(22 downto 0);
signal flashRP : std_logic;
signal flashDATA_to_LEDs : std_logic_vector(6 downto 0);
signal status_LED : std_logic;
-- Clock period definitions
constant board_clk_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: FlashProgrammer PORT MAP (
board_clk => board_clk,
start_button => start_button,
flashSTS => flashSTS,
flashWE => flashWE,
flashOE => flashOE,
flashCE => flashCE,
flashADDR => flashADDR,
flashDATA => flashDATA,
flashRP => flashRP,
flashDATA_to_LEDs => flashDATA_to_LEDs,
status_LED => status_LED
);
-- Clock process definitions
board_clk_process :process
begin
board_clk <= '0';
wait for board_clk_period/2;
board_clk <= '1';
wait for board_clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for 5000 ns;
start_button <= '1';
wait for 8000 ns;
start_button <= '0';
flashSTS <= '0';
wait for 4000 ns;
flashSTS <= '1';
wait;
end process;
END;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Package: Project specific configuration.
--
-- Description:
-- ------------------------------------
-- This is a template file.
--
-- TODO
--
-- USAGE:
-- 1) Copy this file into your project's source directory and rename it to
-- "my_project.vhdl".
-- 2) Add file to library "poc" in your synthesis tool.
-- 3) Change setup appropriately.
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library PoC;
package my_project is
-- Change these lines to setup configuration.
constant MY_PROJECT_DIR : string := ".";
constant MY_OPERATING_SYSTEM : string := "LINUX"; -- e.g. "WINDOWS", "LINUX"
end package;
package body my_project is
end package body;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Package: Project specific configuration.
--
-- Description:
-- ------------------------------------
-- This is a template file.
--
-- TODO
--
-- USAGE:
-- 1) Copy this file into your project's source directory and rename it to
-- "my_project.vhdl".
-- 2) Add file to library "poc" in your synthesis tool.
-- 3) Change setup appropriately.
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library PoC;
package my_project is
-- Change these lines to setup configuration.
constant MY_PROJECT_DIR : string := ".";
constant MY_OPERATING_SYSTEM : string := "LINUX"; -- e.g. "WINDOWS", "LINUX"
end package;
package body my_project is
end package body;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Package: Project specific configuration.
--
-- Description:
-- ------------------------------------
-- This is a template file.
--
-- TODO
--
-- USAGE:
-- 1) Copy this file into your project's source directory and rename it to
-- "my_project.vhdl".
-- 2) Add file to library "poc" in your synthesis tool.
-- 3) Change setup appropriately.
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library PoC;
package my_project is
-- Change these lines to setup configuration.
constant MY_PROJECT_DIR : string := ".";
constant MY_OPERATING_SYSTEM : string := "LINUX"; -- e.g. "WINDOWS", "LINUX"
end package;
package body my_project is
end package body;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Package: Project specific configuration.
--
-- Description:
-- ------------------------------------
-- This is a template file.
--
-- TODO
--
-- USAGE:
-- 1) Copy this file into your project's source directory and rename it to
-- "my_project.vhdl".
-- 2) Add file to library "poc" in your synthesis tool.
-- 3) Change setup appropriately.
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library PoC;
package my_project is
-- Change these lines to setup configuration.
constant MY_PROJECT_DIR : string := ".";
constant MY_OPERATING_SYSTEM : string := "LINUX"; -- e.g. "WINDOWS", "LINUX"
end package;
package body my_project is
end package body;
|
--
-- BananaCore - A processor written in VHDL
--
-- Created by Rogiel Sulzbach.
-- Copyright (c) 2014-2015 Rogiel Sulzbach. All rights reserved.
--
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.std_logic;
library BananaCore;
use BananaCore.Core.all;
use BananaCore.Memory.all;
use BananaCore.RegisterPackage.all;
-- The WriteIoInstructionExecutor entity
entity WriteIoInstructionExecutor is
port(
-- the processor main clock
clock: in BananaCore.Core.Clock;
-- enables the instruction
enable: in std_logic;
-- the first register to operate on (argument 0)
arg0_address: in RegisterAddress;
-- the first register to operate on (argument 1)
arg1_address: in RegisterAddress;
-- a bus indicating if the instruction is ready or not
instruction_ready: out std_logic;
------------------------------------------
-- MEMORY BUS
------------------------------------------
-- the address to read/write memory from/to
memory_address: out MemoryAddress;
-- the memory being read to
memory_data_read: in MemoryData;
-- the memory being written to
memory_data_write: out MemoryData;
-- the operation to perform on the memory
memory_operation: out MemoryOperation;
-- a flag indicating if a memory operation should be performed
memory_enable: out std_logic := '0';
-- a flag indicating if a memory operation has completed
memory_ready: in std_logic;
------------------------------------------
-- REGISTER BUS
------------------------------------------
-- the processor register address bus
register_address: out RegisterAddress;
-- the processor register data bus
register_data_read: in RegisterData;
-- the processor register data bus
register_data_write: out RegisterData;
-- the processor register operation signal
register_operation: out RegisterOperation;
-- the processor register enable signal
register_enable: out std_logic := '0';
-- a flag indicating if a register operation has completed
register_ready: in std_logic;
------------------------------------------
-- IO ports
------------------------------------------
-- io port: port1
port1: out IOPortData
);
end WriteIoInstructionExecutor;
architecture WriteIoInstructionExecutorImpl of WriteIoInstructionExecutor is
type state_type is (
fetch_arg0,
store_arg0,
execute,
complete
);
signal state: state_type := fetch_arg0;
signal arg0: RegisterData;
signal arg1: RegisterData;
signal result: RegisterData;
begin
process (clock) begin
if clock'event and clock = '1' then
if enable = '1' then
case state is
when fetch_arg0 =>
instruction_ready <= '0';
register_address <= arg0_address;
register_operation <= OP_REG_GET;
register_enable <= '1';
state <= store_arg0;
when store_arg0 =>
arg0 <= register_data_read;
state <= execute;
when execute =>
port1 <= arg0;
state <= complete;
when complete =>
instruction_ready <= '1';
state <= complete;
end case;
else
instruction_ready <= '0';
state <= fetch_arg0;
end if;
end if;
end process;
end WriteIoInstructionExecutorImpl;
|
-- Twofish_testbenches_secondary_circuits.vhd
-- Copyright (C) 2006 Spyros Ninos
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this library; see the file COPYING. If not, write to:
--
-- Free Software Foundation
-- 59 Temple Place - Suite 330
-- Boston, MA 02111-1307, USA.
--
-- description : this file contains all the secondary circuits that are needed for running the testbenches
--
--
-- reg128
--
library ieee;
use ieee.std_logic_1164.all;
entity reg128 is
port ( in_reg128 : in std_logic_vector(127 downto 0);
out_reg128 : out std_logic_vector(127 downto 0);
enable_reg128, reset_reg128,clk_reg128 : in std_logic
);
end reg128;
architecture reg128_arch of reg128 is
begin
clk_proc: process(clk_reg128, reset_reg128,enable_reg128)
variable internal_state : std_logic_vector(127 downto 0);
begin
if reset_reg128 = '1' then
internal_state := ( others => '0' );
elsif (clk_reg128'event and clk_reg128 = '1') then
if enable_reg128='1' then
internal_state := in_reg128;
else
internal_state := internal_state;
end if;
end if;
out_reg128 <= internal_state;
end process clk_proc;
end reg128_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- mux128
--
library ieee;
use ieee.std_logic_1164.all;
entity mux128 is
port ( in1_mux128, in2_mux128 : in std_logic_vector(127 downto 0);
selection_mux128 : in std_logic;
out_mux128 : out std_logic_vector(127 downto 0)
);
end mux128;
architecture mux128_arch of mux128 is
begin
with selection_mux128 select
out_mux128 <= in1_mux128 when '0',
in2_mux128 when others;
end mux128_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- demux128
--
library ieee;
use ieee.std_logic_1164.all;
entity demux128 is
port ( in_demux128 : in std_logic_vector(127 downto 0);
out1_demux128, out2_demux128 : out std_logic_vector(127 downto 0);
selection_demux128 : in std_logic
);
end demux128;
architecture demux128_arch of demux128 is
begin
demux_proc: process(in_demux128, selection_demux128)
begin
if selection_demux128 = '0' then
out1_demux128 <= in_demux128;
else
out2_demux128 <= in_demux128;
end if;
end process demux_proc;
end demux128_arch;
|
entity FIFO is
generic (
G_GEN1 : INTEGER;
G_GEN2 : STD_LOGIC;
G_GENA : t_user2;
G_GEN3 : STD_LOGIC_VECTOR(3 downto 0);
G_GEN4 : SIGNED(15 downto 0);
G_GEN5 : UNSIGNED(7 downto 0);
G_GEN6 : STD_ULOGIC;
G_GEN7 : t_user1
);
end entity FIFO;
-- Violation below
entity FIFO is
generic (
G_GEN1 : INTEGER;
G_GEN2 : STD_LOGIC;
G_GENA : T_USER2;
G_GEN3 : STD_LOGIC_VECTOR(3 downto 0);
G_GEN4 : SIGNED(15 downto 0);
G_GEN5 : UNSIGNED(7 downto 0);
G_GEN6 : STD_ULOGIC;
G_GEN7 : T_USER1
);
end entity FIFO;
|
-- Copyright (C) 1991-2009 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 9.0 Build 235 03/01/2009
----------------------------------------------------------------------------
-- ALtera Megafunction Component Declaration File
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package altera_mf_components is
type altera_mf_logic_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
component lcell
port (
a_in : in std_logic;
a_out : out std_logic);
end component;
component altcam
generic (
width : natural := 1;
widthad : natural := 1;
numwords : natural := 1;
lpm_file : string := "UNUSED";
lpm_filex : string := "UNUSED";
match_mode : string := "MULTIPLE";
output_reg : string := "UNREGISTERED";
output_aclr : string := "ON";
pattern_reg : string := "INCLOCK";
pattern_aclr : string := "ON";
wraddress_aclr : string := "ON";
wrx_reg : string := "INCLOCK";
wrx_aclr : string := "ON";
wrcontrol_aclr : string := "ON";
use_eab : string := "ON";
lpm_hint : string := "UNUSED";
lpm_type : string := "altcam" );
port (
pattern : in std_logic_vector(width-1 downto 0);
wrx : in std_logic_vector(width-1 downto 0) := (others => 'Z');
wrxused : in std_logic := '1';
wrdelete : in std_logic := '0';
wraddress : in std_logic_vector(widthad-1 downto 0);
wren : in std_logic;
inclock : in std_logic;
inclocken : in std_logic := '1';
inaclr : in std_logic := '0';
outclock : in std_logic := '0';
outclocken : in std_logic := '1';
outaclr : in std_logic := '0';
mstart : in std_logic := 'X';
mnext : in std_logic := '0';
maddress : out std_logic_vector(widthad-1 downto 0);
mbits : out std_logic_vector(numwords-1 downto 0);
mfound : out std_logic;
mcount : out std_logic_vector(widthad-1 downto 0);
rdbusy : out std_logic;
wrbusy : out std_logic );
end component;
component altclklock
generic (
inclock_period : natural := 10000; -- units in ps
inclock_settings : string := "UNUSED";
valid_lock_cycles : natural := 5;
invalid_lock_cycles : natural := 5;
valid_lock_multiplier : natural := 5;
invalid_lock_multiplier : natural := 5;
operation_mode : string := "NORMAL";
clock0_boost : natural := 1;
clock0_divide : natural := 1;
clock0_settings : string := "UNUSED";
clock0_time_delay : string := "0";
clock1_boost : natural := 1;
clock1_divide : natural := 1;
clock1_settings : string := "UNUSED";
clock1_time_delay : string := "0";
clock2_boost : natural := 1;
clock2_divide : natural := 1;
clock2_settings : string := "UNUSED";
clock2_time_delay : string := "0";
clock_ext_boost : natural := 1;
clock_ext_divide : natural := 1;
clock_ext_settings : string := "UNUSED";
clock_ext_time_delay : string := "0";
outclock_phase_shift : natural := 0; -- units in ps
intended_device_family : string := "APEX20KE" ;
lpm_hint : string := "UNUSED";
lpm_type : string := "altclklock" );
port(
inclock : in std_logic; -- required port, input reference clock
inclocken : in std_logic := '1'; -- PLL enable signal
fbin : in std_logic := '1'; -- feedback input for the PLL
clock0 : out std_logic; -- clock0 output
clock1 : out std_logic; -- clock1 output
clock2 : out std_logic; -- clock2 output
clock_ext : out std_logic; -- external clock output
locked : out std_logic ); -- PLL lock signal
end component;
component altlvds_rx
generic (
number_of_channels : natural; -- Required parameter
deserialization_factor : natural; -- Required parameter
registered_output : string := "ON";
inclock_period : natural := 10000; -- Required parameter
inclock_boost : natural := 0;
cds_mode : string := "UNUSED";
intended_device_family : string := "APEX20KE";
input_data_rate : natural := 0;
inclock_data_alignment : string := "EDGE_ALIGNED";
registered_data_align_input : string := "ON";
common_rx_tx_pll : string := "ON";
enable_dpa_mode : string := "OFF";
enable_dpa_pll_calibration : string := "OFF";
enable_dpa_calibration : string := "ON";
enable_dpa_fifo : string := "ON";
use_dpll_rawperror : string := "OFF";
use_coreclock_input : string := "OFF";
dpll_lock_count : natural := 0;
dpll_lock_window : natural := 0;
outclock_resource : string := "AUTO";
data_align_rollover : natural := 10;
lose_lock_on_one_change : string := "OFF";
reset_fifo_at_first_lock : string := "ON";
use_external_pll : string := "OFF";
implement_in_les : string := "OFF";
buffer_implementation : string := "RAM";
port_rx_data_align : string := "PORT_CONNECTIVITY";
port_rx_channel_data_align : string := "PORT_CONNECTIVITY";
pll_operation_mode : string := "NORMAL";
x_on_bitslip : string := "ON";
use_no_phase_shift : string := "ON";
rx_align_data_reg : string := "RISING_EDGE";
inclock_phase_shift : integer := 0;
enable_soft_cdr_mode : string := "OFF";
sim_dpa_output_clock_phase_shift : integer := 0;
sim_dpa_is_negative_ppm_drift : string := "OFF";
sim_dpa_net_ppm_variation : natural := 0;
enable_dpa_align_to_rising_edge_only : string := "OFF";
enable_dpa_initial_phase_selection : string := "OFF";
dpa_initial_phase_value :natural := 0;
pll_self_reset_on_loss_lock : string := "OFF";
lpm_hint : string := "UNUSED";
lpm_type : string := "altlvds_rx";
-- Specifies whether the source of the input clock is from the PLL
clk_src_is_pll : string := "off" );
-- PORT DECLARATION
port (
--INPUT PORT DECLARATION
rx_in : in std_logic_vector(number_of_channels-1 downto 0); --Required port
rx_inclock : in std_logic := '0';
rx_syncclock : in std_logic := '0';
rx_readclock : in std_logic := '0';
rx_enable : in std_logic := '0';
rx_deskew : in std_logic := '0';
rx_pll_enable : in std_logic := '1';
rx_data_align : in std_logic := 'Z';
rx_data_align_reset : in std_logic := '0';
rx_reset : in std_logic_vector(number_of_channels-1 downto 0):= (others => '0');
rx_dpll_reset : in std_logic_vector(number_of_channels-1 downto 0):= (others => '0');
rx_dpll_hold : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
rx_dpll_enable : in std_logic_vector(number_of_channels-1 downto 0) := (others => '1');
rx_fifo_reset : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
rx_channel_data_align : in std_logic_vector(number_of_channels-1 downto 0) := (others => 'Z');
rx_cda_reset : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
rx_coreclk : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
pll_areset : in std_logic := '0';
dpa_pll_recal : in std_logic := '0';
pll_phasedone : in std_logic := '1';
rx_dpa_lock_reset : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
-- OUTPUT PORT DECLARATION
rx_out : out std_logic_vector(deserialization_factor*number_of_channels -1 downto 0);
rx_outclock : out std_logic;
rx_locked : out std_logic;
rx_dpa_locked : out std_logic_vector(number_of_channels-1 downto 0);
rx_cda_max : out std_logic_vector(number_of_channels-1 downto 0);
rx_divfwdclk : out std_logic_vector(number_of_channels-1 downto 0);
dpa_pll_cal_busy : out std_logic;
pll_phasestep : out std_logic;
pll_phaseupdown : out std_logic;
pll_phasecounterselect: out std_logic_Vector(3 downto 0);
pll_scanclk : out std_logic
);
end component;
component altlvds_tx
generic (
-- Specifies the number of LVDS channels (required)
number_of_channels : natural;
-- Specifies the number of bits per channel (required)
deserialization_factor : natural := 4;
-- Indicates whether the tx_in[] and tx_outclock ports should be
-- registered. Choices for STRATIX are ON, OFF, TX_CLKIN or TX_CORECLK
registered_input : string := "ON";
-- "ON" means that sync_inclock is also used
-- (not used for Stratix and Stratix GX.)
multi_clock : string := "OFF";
-- Specifies the period of the input clock in ps (Required)
inclock_period : natural := 10000;
-- Specifies the period of the tx_outclock port as
-- [INCLOCK_PERIOD * OUTCLOCK_DIVIDE_BY]
outclock_divide_by : positive := 1;
-- The effective clock period used to sample output data
inclock_boost : natural := 0;
-- Aligns the Most Significant Bit(MSB) to the falling edge of the
-- clock instead of the rising edge (only for APEX II devices)
center_align_msb : string := "OFF";
-- Specifies the device family to be used
intended_device_family : string := "APEX20KE";
-- Specifies the data rate out of the PLL.
-- (required and only for Stratix and Stratix GX devices)
output_data_rate : natural := 0;
-- Specifies the alignment of the input data with respect to the
-- tx_inclock port. (required and only available for Stratix and
-- Stratix GX devices)
inclock_data_alignment : string := "EDGE_ALIGNED";
-- Specifies the alignment of the output data with respect to the
-- tx_outclock port. (required and only available for Stratix and
-- Stratix GX devices)
outclock_alignment : string := "EDGE_ALIGNED";
-- Specifies whether the compiler uses the same PLL for both the LVDS
-- receiver and the LVDS transmitter
common_rx_tx_pll : string := "ON";
outclock_resource : string := "AUTO";
use_external_pll : string := "OFF";
implement_in_les : STRING := "OFF";
preemphasis_setting : natural := 0;
vod_setting : natural := 0;
differential_drive : natural := 0;
outclock_multiply_by : natural := 1;
coreclock_divide_by : natural := 2;
outclock_duty_cycle : natural := 50;
inclock_phase_shift : integer := 0;
outclock_phase_shift : integer := 0;
use_no_phase_shift : string := "ON";
pll_self_reset_on_loss_lock : string := "OFF";
lpm_type : string := "altlvds_tx";
lpm_hint : string := "UNUSED";
-- Specifies whether the source of the input clock is from the PLL
clk_src_is_pll : string := "off" );
-- PORT DECLARATION
port (
-- INPUT PORT DECLARATION
-- Input data (required)
tx_in : in std_logic_vector(deserialization_factor*
number_of_channels -1 downto 0);
-- Input clock (required)
tx_inclock : in std_logic := '0';
tx_syncclock : in std_logic := '0';
tx_enable : in std_logic := '1';
-- Optional clock for input registers (Required if "multi_clock"
-- parameters is turned on)
sync_inclock : in std_logic := '0';
-- Enable control for the LVDS PLL
tx_pll_enable : in std_logic := '1';
-- Asynchronously resets all counters to initial values (only for
--Stratix and Stratix GX devices)
pll_areset : in std_logic := '0';
-- OUTPUT PORT DECLARATION
-- Serialized data signal(required)
tx_out : out std_logic_vector(number_of_channels-1 downto 0)
:= (others => '0');
-- External reference clock
tx_outclock : out std_logic;
-- Output clock used to feed non-peripheral logic.
-- Only available for Stratix, and Stratix GX devices only.
tx_coreclock : out std_logic;
-- Gives the status of the LVDS PLL
-- (when the PLL is locked, this signal is VCC. GND otherwise)
tx_locked : out std_logic
);
end component;
component altdpram
generic (
width : natural;
widthad : natural;
numwords : natural := 0;
lpm_file : string := "UNUSED";
lpm_hint : string := "USE_EAB=ON";
use_eab : string := "ON";
indata_reg : string := "INCLOCK";
indata_aclr : string := "ON";
wraddress_reg : string := "INCLOCK";
wraddress_aclr : string := "ON";
wrcontrol_reg : string := "INCLOCK";
wrcontrol_aclr : string := "ON";
rdaddress_reg : string := "OUTCLOCK";
rdaddress_aclr : string := "ON";
rdcontrol_reg : string := "OUTCLOCK";
rdcontrol_aclr : string := "ON";
outdata_reg : string := "UNREGISTERED";
outdata_aclr : string := "ON";
ram_block_type : string := "AUTO";
width_byteena : natural := 1;
byte_size : natural := 5;
read_during_write_mode_mixed_ports : string := "DONT_CARE";
intended_device_family : string := "APEX20KE";
lpm_type : string := "altdpram" );
port(
wren : in std_logic := '0';
data : in std_logic_vector(width-1 downto 0);
wraddress : in std_logic_vector(widthad-1 downto 0);
wraddressstall : in std_logic := '0';
inclock : in std_logic := '1';
inclocken : in std_logic := '1';
rden : in std_logic := '1';
rdaddress : in std_logic_vector(widthad-1 downto 0);
rdaddressstall : in std_logic := '0';
byteena : in std_logic_vector(width_byteena-1 downto 0) := (others => '1');
outclock : in std_logic := '1';
outclocken : in std_logic := '1';
aclr : in std_logic := '0';
q : out std_logic_vector(width-1 downto 0) );
end component;
component alt3pram
generic (
width : natural;
widthad : natural;
numwords : natural := 0;
lpm_file : string := "UNUSED";
lpm_hint : string := "USE_EAB=ON";
indata_reg : string := "UNREGISTERED";
indata_aclr : string := "OFF";
write_reg : string := "UNREGISTERED";
write_aclr : string := "OFF";
rdaddress_reg_a : string := "UNREGISTERED";
rdaddress_aclr_a : string := "OFF";
rdaddress_reg_b : string := "UNREGISTERED";
rdaddress_aclr_b : string := "OFF";
rdcontrol_reg_a : string := "UNREGISTERED";
rdcontrol_aclr_a : string := "OFF";
rdcontrol_reg_b : string := "UNREGISTERED";
rdcontrol_aclr_b : string := "OFF";
outdata_reg_a : string := "UNREGISTERED";
outdata_aclr_a : string := "OFF";
outdata_reg_b : string := "UNREGISTERED";
outdata_aclr_b : string := "OFF";
intended_device_family : string := "APEX20KE";
ram_block_type : string := "AUTO";
maximum_depth : integer := 0;
lpm_type : string := "alt3pram" );
port (
wren : in std_logic := '0';
data : in std_logic_vector(width-1 downto 0);
wraddress : in std_logic_vector(widthad-1 downto 0);
inclock : in std_logic := '0';
inclocken : in std_logic := '1';
rden_a : in std_logic := '1';
rden_b : in std_logic := '1';
rdaddress_a : in std_logic_vector(widthad-1 downto 0);
rdaddress_b : in std_logic_vector(widthad-1 downto 0);
outclock : in std_logic := '0';
outclocken : in std_logic := '1';
aclr : in std_logic := '0';
qa : out std_logic_vector(width-1 downto 0);
qb : out std_logic_vector(width-1 downto 0) );
end component;
component altqpram
generic (
operation_mode : string := "QUAD_PORT";
width_write_a : natural := 1;
widthad_write_a : natural := 1;
numwords_write_a : natural := 0; -- default = 2^widthad_write_a
indata_reg_a : string := "INCLOCK_A";
indata_aclr_a : string := "INACLR_A";
wrcontrol_wraddress_reg_a : string := "INCLOCK_A";
wrcontrol_aclr_a : string := "INACLR_A";
wraddress_aclr_a : string := "INACLR_A";
width_write_b : natural := 1; -- default = width_write_a
widthad_write_b : natural := 1; -- default = widthad_write_a
numwords_write_b : natural := 0; -- default = 2^widthad_write_b
indata_reg_b : string := "INCLOCK_B";
indata_aclr_b : string := "INACLR_B";
wrcontrol_wraddress_reg_b : string := "INCLOCK_B";
wrcontrol_aclr_b : string := "INACLR_B";
wraddress_aclr_b : string := "INACLR_B";
width_read_a : natural := 1;
widthad_read_a : natural := 1;
numwords_read_a : natural := 0; -- default = 2^widthad_read_a
rdcontrol_reg_a : string := "OUTCLOCK_A";
rdcontrol_aclr_a : string := "OUTACLR_A";
rdaddress_reg_a : string := "OUTCLOCK_A";
rdaddress_aclr_a : string := "OUTACLR_A";
outdata_reg_a : string := "UNREGISTERED";
outdata_aclr_a : string := "OUTACLR_A";
width_read_b : natural := 1; -- default = width_read_a
widthad_read_b : natural := 1; -- default = widthad_read_a
numwords_read_b : natural := 0; -- default = 2^widthad_read_b
rdcontrol_reg_b : string := "OUTCLOCK_B";
rdcontrol_aclr_b : string := "OUTACLR_B";
rdaddress_reg_b : string := "OUTCLOCK_B";
rdaddress_aclr_b : string := "OUTACLR_B";
outdata_reg_b : string := "UNREGISTERED";
outdata_aclr_b : string := "OUTACLR_B";
init_file : string := "UNUSED";
lpm_hint : string := "UNUSED";
lpm_type : string := "altqpram" );
port (
wren_a : in std_logic := '0';
wren_b : in std_logic := '0';
data_a : in std_logic_vector(width_write_a-1 downto 0) := (OTHERS => '0');
data_b : in std_logic_vector(width_write_b-1 downto 0) := (OTHERS => '0');
wraddress_a : in std_logic_vector(widthad_write_a-1 downto 0) := (OTHERS => '0');
wraddress_b : in std_logic_vector(widthad_write_b-1 downto 0) := (OTHERS => '0');
inclock_a : in std_logic := '0';
inclock_b : in std_logic := '0';
inclocken_a : in std_logic := '1';
inclocken_b : in std_logic := '1';
rden_a : in std_logic := '1';
rden_b : in std_logic := '1';
rdaddress_a : in std_logic_vector(widthad_read_a-1 downto 0) := (OTHERS => '0');
rdaddress_b : in std_logic_vector(widthad_read_b-1 downto 0) := (OTHERS => '0');
outclock_a : in std_logic := '0';
outclock_b : in std_logic := '0';
outclocken_a : in std_logic := '1';
outclocken_b : in std_logic := '1';
inaclr_a : in std_logic := '0';
inaclr_b : in std_logic := '0';
outaclr_a : in std_logic := '0';
outaclr_b : in std_logic := '0';
q_a : out std_logic_vector(width_read_a-1 downto 0);
q_b : out std_logic_vector(width_read_b-1 downto 0) );
end component;
component scfifo
generic (
lpm_width : natural;
lpm_widthu : natural;
lpm_numwords : natural;
lpm_showahead : string := "OFF";
lpm_hint : string := "USE_EAB=ON";
intended_device_family : string := "NON_STRATIX";
almost_full_value : natural := 0;
almost_empty_value : natural := 0;
overflow_checking : string := "ON";
underflow_checking : string := "ON";
allow_rwcycle_when_full : string := "OFF";
add_ram_output_register : string := "OFF";
use_eab : string := "ON";
lpm_type : string := "scfifo";
maximum_depth : natural := 0 );
port (
data : in std_logic_vector(lpm_width-1 downto 0);
clock : in std_logic;
wrreq : in std_logic;
rdreq : in std_logic;
aclr : in std_logic := '0';
sclr : in std_logic := '0';
full : out std_logic;
almost_full : out std_logic;
empty : out std_logic;
almost_empty : out std_logic;
q : out std_logic_vector(lpm_width-1 downto 0);
usedw : out std_logic_vector(lpm_widthu-1 downto 0) );
end component;
component dcfifo_mixed_widths
generic (
lpm_width : natural;
lpm_widthu : natural;
lpm_width_r : natural := 0;
lpm_widthu_r : natural := 0;
lpm_numwords : natural;
lpm_showahead : string := "OFF";
lpm_hint : string := "USE_EAB=ON";
overflow_checking : string := "ON";
underflow_checking : string := "ON";
delay_rdusedw : natural := 1;
delay_wrusedw : natural := 1;
rdsync_delaypipe : natural := 0;
wrsync_delaypipe : natural := 0;
use_eab : string := "ON";
add_ram_output_register : string := "OFF";
add_width : natural := 1;
clocks_are_synchronized : string := "FALSE";
ram_block_type : string := "AUTO";
add_usedw_msb_bit : string := "OFF";
write_aclr_synch : string := "OFF";
lpm_type : string := "dcfifo_mixed_widths";
intended_device_family : string := "NON_STRATIX" );
port (
data : in std_logic_vector(lpm_width-1 downto 0);
rdclk : in std_logic;
wrclk : in std_logic;
wrreq : in std_logic;
rdreq : in std_logic;
aclr : in std_logic := '0';
rdfull : out std_logic;
wrfull : out std_logic;
wrempty : out std_logic;
rdempty : out std_logic;
q : out std_logic_vector(lpm_width_r-1 downto 0);
rdusedw : out std_logic_vector(lpm_widthu_r-1 downto 0);
wrusedw : out std_logic_vector(lpm_widthu-1 downto 0) );
end component;
component dcfifo
generic (
lpm_width : natural;
lpm_widthu : natural;
lpm_numwords : natural;
lpm_showahead : string := "OFF";
lpm_hint : string := "USE_EAB=ON";
overflow_checking : string := "ON";
underflow_checking : string := "ON";
delay_rdusedw : natural := 1;
delay_wrusedw : natural := 1;
rdsync_delaypipe : natural := 0;
wrsync_delaypipe : natural := 0;
use_eab : string := "ON";
add_ram_output_register : string := "OFF";
add_width : natural := 1;
clocks_are_synchronized : string := "FALSE";
ram_block_type : string := "AUTO";
add_usedw_msb_bit : string := "OFF";
write_aclr_synch : string := "OFF";
lpm_type : string := "dcfifo";
intended_device_family : string := "NON_STRATIX" );
port (
data : in std_logic_vector(lpm_width-1 downto 0);
rdclk : in std_logic;
wrclk : in std_logic;
wrreq : in std_logic;
rdreq : in std_logic;
aclr : in std_logic := '0';
rdfull : out std_logic;
wrfull : out std_logic;
wrempty : out std_logic;
rdempty : out std_logic;
q : out std_logic_vector(lpm_width-1 downto 0);
rdusedw : out std_logic_vector(lpm_widthu-1 downto 0);
wrusedw : out std_logic_vector(lpm_widthu-1 downto 0) );
end component;
component altddio_in
generic (
width : positive; -- required parameter
invert_input_clocks : string := "OFF";
intended_device_family : string := "Stratix";
power_up_high : string := "OFF";
lpm_hint : string := "UNUSED";
lpm_type : string := "altddio_in" );
port (
datain : in std_logic_vector(width-1 downto 0);
inclock : in std_logic;
inclocken : in std_logic := '1';
aset : in std_logic := '0';
aclr : in std_logic := '0';
sset : in std_logic := '0';
sclr : in std_logic := '0';
dataout_h : out std_logic_vector(width-1 downto 0);
dataout_l : out std_logic_vector(width-1 downto 0) );
end component;
component altddio_out
generic (
width : positive; -- required parameter
power_up_high : string := "OFF";
oe_reg : string := "UNUSED";
extend_oe_disable : string := "UNUSED";
invert_output : string := "OFF";
intended_device_family : string := "Stratix";
lpm_hint : string := "UNUSED";
lpm_type : string := "altddio_out" );
port (
datain_h : in std_logic_vector(width-1 downto 0);
datain_l : in std_logic_vector(width-1 downto 0);
outclock : in std_logic;
outclocken : in std_logic := '1';
aset : in std_logic := '0';
aclr : in std_logic := '0';
sset : in std_logic := '0';
sclr : in std_logic := '0';
oe : in std_logic := '1';
dataout : out std_logic_vector(width-1 downto 0);
oe_out : out std_logic_vector(width-1 downto 0) );
end component;
component altddio_bidir
generic(
width : positive; -- required parameter
power_up_high : string := "OFF";
oe_reg : string := "UNUSED";
extend_oe_disable : string := "UNUSED";
implement_input_in_lcell : string := "UNUSED";
invert_output : string := "OFF";
intended_device_family : string := "Stratix";
lpm_hint : string := "UNUSED";
lpm_type : string := "altddio_bidir" );
port (
datain_h : in std_logic_vector(width-1 downto 0);
datain_l : in std_logic_vector(width-1 downto 0);
inclock : in std_logic := '0';
inclocken : in std_logic := '1';
outclock : in std_logic;
outclocken : in std_logic := '1';
aset : in std_logic := '0';
aclr : in std_logic := '0';
sset : in std_logic := '0';
sclr : in std_logic := '0';
oe : in std_logic := '1';
dataout_h : out std_logic_vector(width-1 downto 0);
dataout_l : out std_logic_vector(width-1 downto 0);
combout : out std_logic_vector(width-1 downto 0);
oe_out : out std_logic_vector(width-1 downto 0);
dqsundelayedout : out std_logic_vector(width-1 downto 0);
padio : inout std_logic_vector(width-1 downto 0) );
end component;
component altshift_taps
generic (
number_of_taps : integer := 4;
tap_distance : integer := 3;
width : integer := 8;
power_up_state : string := "CLEARED";
lpm_hint : string := "UNUSED";
lpm_type : string := "altshift_taps" );
port (
shiftin : in std_logic_vector (width-1 downto 0);
clock : in std_logic;
clken : in std_logic := '1';
aclr : in std_logic := '0';
shiftout : out std_logic_vector (width-1 downto 0);
taps : out std_logic_vector ((width*number_of_taps)-1 downto 0));
end component;
component altmult_add
generic (
WIDTH_A : integer := 1;
WIDTH_B : integer := 1;
WIDTH_RESULT : integer := 1;
NUMBER_OF_MULTIPLIERS : integer := 1;
-- A inputs
INPUT_REGISTER_A0 : string := "CLOCK0";
INPUT_ACLR_A0 : string := "ACLR3";
INPUT_SOURCE_A0 : string := "DATAA";
INPUT_REGISTER_A1 : string := "CLOCK0";
INPUT_ACLR_A1 : string := "ACLR3";
INPUT_SOURCE_A1 : string := "DATAA";
INPUT_REGISTER_A2 : string := "CLOCK0";
INPUT_ACLR_A2 : string := "ACLR3";
INPUT_SOURCE_A2 : string := "DATAA";
INPUT_REGISTER_A3 : string := "CLOCK0";
INPUT_ACLR_A3 : string := "ACLR3";
INPUT_SOURCE_A3 : string := "DATAA";
PORT_SIGNA : string := "PORT_CONNECTIVITY";
REPRESENTATION_A : string := "UNSIGNED";
SIGNED_REGISTER_A : string := "CLOCK0";
SIGNED_ACLR_A : string := "ACLR3";
SIGNED_PIPELINE_REGISTER_A : string := "CLOCK0";
SIGNED_PIPELINE_ACLR_A : string := "ACLR3";
-- B inputs
INPUT_REGISTER_B0 : string := "CLOCK0";
INPUT_ACLR_B0 : string := "ACLR3";
INPUT_SOURCE_B0 : string := "DATAB";
INPUT_REGISTER_B1 : string := "CLOCK0";
INPUT_ACLR_B1 : string := "ACLR3";
INPUT_SOURCE_B1 : string := "DATAB";
INPUT_REGISTER_B2 : string := "CLOCK0";
INPUT_ACLR_B2 : string := "ACLR3";
INPUT_SOURCE_B2 : string := "DATAB";
INPUT_REGISTER_B3 : string := "CLOCK0";
INPUT_ACLR_B3 : string := "ACLR3";
INPUT_SOURCE_B3 : string := "DATAB";
PORT_SIGNB : string := "PORT_CONNECTIVITY";
REPRESENTATION_B : string := "UNSIGNED";
SIGNED_REGISTER_B : string := "CLOCK0";
SIGNED_ACLR_B : string := "ACLR3";
SIGNED_PIPELINE_REGISTER_B : string := "CLOCK0";
SIGNED_PIPELINE_ACLR_B : string := "ACLR3";
MULTIPLIER_REGISTER0 : string := "CLOCK0";
MULTIPLIER_ACLR0 : string := "ACLR3";
MULTIPLIER_REGISTER1 : string := "CLOCK0";
MULTIPLIER_ACLR1 : string := "ACLR3";
MULTIPLIER_REGISTER2 : string := "CLOCK0";
MULTIPLIER_ACLR2 : string := "ACLR3";
MULTIPLIER_REGISTER3 : string := "CLOCK0";
MULTIPLIER_ACLR3 : string := "ACLR3";
PORT_ADDNSUB1 : string := "PORT_CONNECTIVITY";
ADDNSUB_MULTIPLIER_REGISTER1 : string := "CLOCK0";
ADDNSUB_MULTIPLIER_ACLR1 : string := "ACLR3";
ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1 : string := "CLOCK0";
ADDNSUB_MULTIPLIER_PIPELINE_ACLR1 : string := "ACLR3";
PORT_ADDNSUB3 : string := "PORT_CONNECTIVITY";
ADDNSUB_MULTIPLIER_REGISTER3 : string := "CLOCK0";
ADDNSUB_MULTIPLIER_ACLR3 : string := "ACLR3";
ADDNSUB_MULTIPLIER_PIPELINE_REGISTER3: string := "CLOCK0";
ADDNSUB_MULTIPLIER_PIPELINE_ACLR3 : string := "ACLR3";
ADDNSUB1_ROUND_ACLR : string := "ACLR3";
ADDNSUB1_ROUND_PIPELINE_ACLR : string := "ACLR3";
ADDNSUB1_ROUND_REGISTER : string := "CLOCK0";
ADDNSUB1_ROUND_PIPELINE_REGISTER : string := "CLOCK0";
ADDNSUB3_ROUND_ACLR : string := "ACLR3";
ADDNSUB3_ROUND_PIPELINE_ACLR : string := "ACLR3";
ADDNSUB3_ROUND_REGISTER : string := "CLOCK0";
ADDNSUB3_ROUND_PIPELINE_REGISTER : string := "CLOCK0";
MULT01_ROUND_ACLR : string := "ACLR3";
MULT01_ROUND_REGISTER : string := "CLOCK0";
MULT01_SATURATION_REGISTER : string := "CLOCK0";
MULT01_SATURATION_ACLR : string := "ACLR3";
MULT23_ROUND_REGISTER : string := "CLOCK0";
MULT23_ROUND_ACLR : string := "ACLR3";
MULT23_SATURATION_REGISTER : string := "CLOCK0";
MULT23_SATURATION_ACLR : string := "ACLR3";
multiplier1_direction : string := "ADD";
multiplier3_direction : string := "ADD";
OUTPUT_REGISTER : string := "CLOCK0";
OUTPUT_ACLR : string := "ACLR0";
-- StratixII parameters
multiplier01_rounding : string := "NO";
multiplier01_saturation : string := "NO";
multiplier23_rounding : string := "NO";
multiplier23_saturation : string := "NO";
adder1_rounding : string := "NO";
adder3_rounding : string := "NO";
port_mult0_is_saturated : string := "UNUSED";
port_mult1_is_saturated : string := "UNUSED";
port_mult2_is_saturated : string := "UNUSED";
port_mult3_is_saturated : string := "UNUSED";
-- Stratix III parameters
scanouta_register : string := "UNREGISTERED";
scanouta_aclr : string := "NONE";
-- Rounding parameters
output_rounding : string := "NO";
output_round_type : string := "NEAREST_INTEGER";
width_msb : integer := 17;
output_round_register : string := "UNREGISTERED";
output_round_aclr : string := "NONE";
output_round_pipeline_register : string := "UNREGISTERED";
output_round_pipeline_aclr : string := "NONE";
chainout_rounding : string := "NO";
chainout_round_register : string := "UNREGISTERED";
chainout_round_aclr : string := "NONE";
chainout_round_pipeline_register : string := "UNREGISTERED";
chainout_round_pipeline_aclr : string := "NONE";
chainout_round_output_register : string := "UNREGISTERED";
chainout_round_output_aclr : string := "NONE";
-- saturation parameters
port_output_is_overflow : string := "PORT_UNUSED";
port_chainout_sat_is_overflow : string := "PORT_UNUSED";
output_saturation : string := "NO";
output_saturate_type : string := "ASYMMETRIC";
width_saturate_sign : integer := 1;
output_saturate_register : string := "UNREGISTERED";
output_saturate_aclr : string := "NONE";
output_saturate_pipeline_register : string := "UNREGISTERED";
output_saturate_pipeline_aclr : string := "NONE";
chainout_saturation : string := "NO";
chainout_saturate_register : string := "UNREGISTERED";
chainout_saturate_aclr : string := "NONE";
chainout_saturate_pipeline_register : string := "UNREGISTERED";
chainout_saturate_pipeline_aclr : string := "NONE";
chainout_saturate_output_register : string := "UNREGISTERED";
chainout_saturate_output_aclr : string := "NONE";
-- chainout parameters
chainout_adder : string := "NO";
chainout_register : string := "UNREGISTERED";
chainout_aclr : string := "NONE";
width_chainin : integer := 1;
zero_chainout_output_register : string := "UNREGISTERED";
zero_chainout_output_aclr : string := "NONE";
-- rotate & shift parameters
shift_mode : string := "NO";
rotate_aclr : string := "NONE";
rotate_register : string := "UNREGISTERED";
rotate_pipeline_register : string := "UNREGISTERED";
rotate_pipeline_aclr : string := "NONE";
rotate_output_register : string := "UNREGISTERED";
rotate_output_aclr : string := "NONE";
shift_right_register : string := "UNREGISTERED";
shift_right_aclr : string := "NONE";
shift_right_pipeline_register : string := "UNREGISTERED";
shift_right_pipeline_aclr : string := "NONE";
shift_right_output_register : string := "UNREGISTERED";
shift_right_output_aclr : string := "NONE";
-- loopback parameters
zero_loopback_register : string := "UNREGISTERED";
zero_loopback_aclr : string := "NONE";
zero_loopback_pipeline_register : string := "UNREGISTERED";
zero_loopback_pipeline_aclr : string := "NONE";
zero_loopback_output_register : string := "UNREGISTERED";
zero_loopback_output_aclr : string := "NONE";
-- accumulator parameters
accum_sload_register : string := "UNREGISTERED";
accum_sload_aclr : string := "NONE";
accum_sload_pipeline_register : string := "UNREGISTERED";
accum_sload_pipeline_aclr : string := "NONE";
accum_direction : string := "ADD";
accumulator : string := "NO";
EXTRA_LATENCY : integer :=0;
DEDICATED_MULTIPLIER_CIRCUITRY:string := "AUTO";
DSP_BLOCK_BALANCING : string := "AUTO";
lpm_hint : string := "UNUSED";
lpm_type : string := "altmult_add";
intended_device_family : string := "Stratix" );
port (
dataa : in std_logic_vector(NUMBER_OF_MULTIPLIERS * WIDTH_A -1 downto 0);
datab : in std_logic_vector(NUMBER_OF_MULTIPLIERS * WIDTH_B -1 downto 0);
scanina : in std_logic_vector(width_a -1 downto 0) := (others => '0');
scaninb : in std_logic_vector(width_b -1 downto 0) := (others => '0');
sourcea : in std_logic_vector(NUMBER_OF_MULTIPLIERS -1 downto 0) := (others => '0');
sourceb : in std_logic_vector(NUMBER_OF_MULTIPLIERS -1 downto 0) := (others => '0');
-- clock ports
clock3 : in std_logic := '1';
clock2 : in std_logic := '1';
clock1 : in std_logic := '1';
clock0 : in std_logic := '1';
aclr3 : in std_logic := '0';
aclr2 : in std_logic := '0';
aclr1 : in std_logic := '0';
aclr0 : in std_logic := '0';
ena3 : in std_logic := '1';
ena2 : in std_logic := '1';
ena1 : in std_logic := '1';
ena0 : in std_logic := '1';
-- control signals
signa : in std_logic := 'Z';
signb : in std_logic := 'Z';
addnsub1 : in std_logic := 'Z';
addnsub3 : in std_logic := 'Z';
-- StratixII only input ports
mult01_round : in std_logic := '0';
mult23_round : in std_logic := '0';
mult01_saturation : in std_logic := '0';
mult23_saturation : in std_logic := '0';
addnsub1_round : in std_logic := '0';
addnsub3_round : in std_logic := '0';
-- Stratix III only input ports
output_round : in std_logic := '0';
chainout_round : in std_logic := '0';
output_saturate : in std_logic := '0';
chainout_saturate : in std_logic := '0';
chainin : in std_logic_vector (width_chainin - 1 downto 0) := (others => '0');
zero_chainout : in std_logic := '0';
rotate : in std_logic := '0';
shift_right : in std_logic := '0';
zero_loopback : in std_logic := '0';
accum_sload : in std_logic := '0';
-- output ports
result : out std_logic_vector(WIDTH_RESULT -1 downto 0);
scanouta : out std_logic_vector (WIDTH_A -1 downto 0);
scanoutb : out std_logic_vector (WIDTH_B -1 downto 0);
-- StratixII only output ports
mult0_is_saturated : out std_logic := '0';
mult1_is_saturated : out std_logic := '0';
mult2_is_saturated : out std_logic := '0';
mult3_is_saturated : out std_logic := '0';
-- Stratix III only output ports
overflow : out std_logic := '0';
chainout_sat_overflow : out std_logic := '0');
end component;
component altmult_accum
generic (
width_a : integer := 1;
width_b : integer := 1;
width_result : integer := 2;
width_upper_data : integer := 1;
input_source_a : string := "DATAA";
input_source_b : string := "DATAB";
input_reg_a : string := "CLOCK0";
input_aclr_a : string := "ACLR3";
input_reg_b : string := "CLOCK0";
input_aclr_b : string := "ACLR3";
port_addnsub : string := "PORT_CONNECTIVITY";
addnsub_reg : string := "CLOCK0";
addnsub_aclr : string := "ACLR3";
addnsub_pipeline_reg : string := "CLOCK0";
addnsub_pipeline_aclr : string := "ACLR3";
accum_direction : string := "ADD";
accum_sload_reg : string := "CLOCK0";
accum_sload_aclr : string := "ACLR3";
accum_sload_pipeline_reg : string := "CLOCK0";
accum_sload_pipeline_aclr : string := "ACLR3";
representation_a : string := "UNSIGNED";
port_signa : string := "PORT_CONNECTIVITY";
sign_reg_a : string := "CLOCK0";
sign_aclr_a : string := "ACLR3";
sign_pipeline_reg_a : string := "CLOCK0";
sign_pipeline_aclr_a : string := "ACLR3";
representation_b : string := "UNSIGNED";
port_signb : string := "PORT_CONNECTIVITY";
sign_reg_b : string := "CLOCK0";
sign_aclr_b : string := "ACLR3";
sign_pipeline_reg_b : string := "CLOCK0";
sign_pipeline_aclr_b : string := "ACLR3";
multiplier_reg : string := "CLOCK0";
multiplier_aclr : string := "ACLR3";
output_reg : string := "CLOCK0";
output_aclr : string := "ACLR0";
extra_multiplier_latency : integer := 0;
extra_accumulator_latency : integer := 0;
dedicated_multiplier_circuitry : string := "AUTO";
dsp_block_balancing : string := "AUTO";
lpm_hint : string := "UNUSED";
lpm_type : string := "altmult_accum";
intended_device_family : string := "Stratix";
multiplier_rounding : string := "NO";
multiplier_saturation : string := "NO";
accumulator_rounding : string := "NO";
accumulator_saturation : string := "NO";
port_mult_is_saturated : string := "UNUSED";
port_accum_is_saturated : string := "UNUSED";
mult_round_aclr : string := "ACLR3";
mult_round_reg : string := "CLOCK0";
mult_saturation_aclr : string := "ACLR3";
mult_saturation_reg : string := "CLOCK0";
accum_round_aclr : string := "ACLR3";
accum_round_reg : string := "CLOCK3";
accum_round_pipeline_aclr : string := "ACLR3";
accum_round_pipeline_reg : string := "CLOCK0";
accum_saturation_aclr : string := "ACLR3";
accum_saturation_reg : string := "CLOCK0";
accum_saturation_pipeline_aclr : string := "ACLR3";
accum_saturation_pipeline_reg : string := "CLOCK0";
accum_sload_upper_data_aclr : string := "ACLR3";
accum_sload_upper_data_pipeline_aclr : string := "ACLR3";
accum_sload_upper_data_pipeline_reg : string := "CLOCK0";
accum_sload_upper_data_reg : string := "CLOCK0" );
port (
dataa : in std_logic_vector(width_a -1 downto 0) := (others => '0');
datab : in std_logic_vector(width_b -1 downto 0) := (others => '0');
scanina : in std_logic_vector(width_a -1 downto 0) := (others => 'Z');
scaninb : in std_logic_vector(width_b -1 downto 0) := (others => 'Z');
accum_sload_upper_data : in std_logic_vector(width_result -1 downto width_result - width_upper_data) := (others => '0');
sourcea : in std_logic := '1';
sourceb : in std_logic := '1';
-- control signals
addnsub : in std_logic := 'Z';
accum_sload : in std_logic := '0';
signa : in std_logic := 'Z';
signb : in std_logic := 'Z';
-- clock ports
clock0 : in std_logic := '1';
clock1 : in std_logic := '1';
clock2 : in std_logic := '1';
clock3 : in std_logic := '1';
ena0 : in std_logic := '1';
ena1 : in std_logic := '1';
ena2 : in std_logic := '1';
ena3 : in std_logic := '1';
aclr0 : in std_logic := '0';
aclr1 : in std_logic := '0';
aclr2 : in std_logic := '0';
aclr3 : in std_logic := '0';
-- round and saturation ports
mult_round : in std_logic := '0';
mult_saturation : in std_logic := '0';
accum_round : in std_logic := '0';
accum_saturation : in std_logic := '0';
-- output ports
result : out std_logic_vector(width_result -1 downto 0);
overflow : out std_logic;
scanouta : out std_logic_vector (width_a -1 downto 0);
scanoutb : out std_logic_vector (width_b -1 downto 0);
mult_is_saturated : out std_logic := '0';
accum_is_saturated : out std_logic := '0' );
end component;
component altaccumulate
generic (
width_in : integer:= 4;
width_out : integer:= 8;
lpm_representation : string := "UNSIGNED";
extra_latency : integer:= 0;
use_wys : string := "ON";
lpm_hint : string := "UNUSED";
lpm_type : string := "altaccumulate" );
port (
-- Input ports
cin : in std_logic := 'Z';
data : in std_logic_vector(width_in -1 downto 0); -- Required port
add_sub : in std_logic := '1';
clock : in std_logic; -- Required port
sload : in std_logic := '0';
clken : in std_logic := '1';
sign_data : in std_logic := '0';
aclr : in std_logic := '0';
-- Output ports
result : out std_logic_vector(width_out -1 downto 0) := (others => '0');
cout : out std_logic := '0';
overflow : out std_logic := '0' );
end component;
component altsyncram
generic (
operation_mode : string := "BIDIR_DUAL_PORT";
-- port a parameters
width_a : integer := 1;
widthad_a : integer := 1;
numwords_a : integer := 0;
-- registering parameters
-- port a read parameters
outdata_reg_a : string := "UNREGISTERED";
-- clearing parameters
address_aclr_a : string := "NONE";
outdata_aclr_a : string := "NONE";
-- clearing parameters
-- port a write parameters
indata_aclr_a : string := "NONE";
wrcontrol_aclr_a : string := "NONE";
-- clear for the byte enable port reigsters which are clocked by clk0
byteena_aclr_a : string := "NONE";
-- width of the byte enable ports. if it is used, must be WIDTH_WRITE_A/8 or /9
width_byteena_a : integer := 1;
-- port b parameters
width_b : integer := 1;
widthad_b : integer := 1;
numwords_b : integer := 0;
-- registering parameters
-- port b read parameters
rdcontrol_reg_b : string := "CLOCK1";
address_reg_b : string := "CLOCK1";
outdata_reg_b : string := "UNREGISTERED";
-- clearing parameters
outdata_aclr_b : string := "NONE";
rdcontrol_aclr_b : string := "NONE";
-- registering parameters
-- port b write parameters
indata_reg_b : string := "CLOCK1";
wrcontrol_wraddress_reg_b : string := "CLOCK1";
-- registering parameter for the byte enable reister for port b
byteena_reg_b : string := "CLOCK1";
-- clearing parameters
indata_aclr_b : string := "NONE";
wrcontrol_aclr_b : string := "NONE";
address_aclr_b : string := "NONE";
-- clear parameter for byte enable port register
byteena_aclr_b : string := "NONE";
-- StratixII only : to bypass clock enable or using clock enable
clock_enable_input_a : string := "NORMAL";
clock_enable_output_a : string := "NORMAL";
clock_enable_input_b : string := "NORMAL";
clock_enable_output_b : string := "NORMAL";
-- width of the byte enable ports. if it is used, must be WIDTH_WRITE_A/8 or /9
width_byteena_b : integer := 1;
-- clock enable setting for the core
clock_enable_core_a : string := "USE_INPUT_CLKEN";
clock_enable_core_b : string := "USE_INPUT_CLKEN";
-- read-during-write-same-port setting
read_during_write_mode_port_a : string := "NEW_DATA_NO_NBE_READ";
read_during_write_mode_port_b : string := "NEW_DATA_NO_NBE_READ";
-- ECC status ports setting
enable_ecc : string := "FALSE";
-- global parameters
-- width of a byte for byte enables
byte_size : integer := 0;
read_during_write_mode_mixed_ports: string := "DONT_CARE";
-- ram block type choices are "AUTO", "M512", "M4K" and "MEGARAM"
ram_block_type : string := "AUTO";
-- determine whether LE support is turned on or off for altsyncram
implement_in_les : string := "OFF";
-- determine whether RAM would be power up to uninitialized or not
power_up_uninitialized : string := "FALSE";
sim_show_memory_data_in_port_b_layout : string := "OFF";
-- general operation parameters
init_file : string := "UNUSED";
init_file_layout : string := "UNUSED";
maximum_depth : integer := 0;
intended_device_family : string := "Stratix";
lpm_hint : string := "UNUSED";
lpm_type : string := "altsyncram" );
port (
wren_a : in std_logic := '0';
wren_b : in std_logic := '0';
rden_a : in std_logic := '1';
rden_b : in std_logic := '1';
data_a : in std_logic_vector(width_a - 1 downto 0):= (others => '1');
data_b : in std_logic_vector(width_b - 1 downto 0):= (others => '1');
address_a : in std_logic_vector(widthad_a - 1 downto 0);
address_b : in std_logic_vector(widthad_b - 1 downto 0) := (others => '1');
clock0 : in std_logic := '1';
clock1 : in std_logic := 'Z';
clocken0 : in std_logic := '1';
clocken1 : in std_logic := '1';
clocken2 : in std_logic := '1';
clocken3 : in std_logic := '1';
aclr0 : in std_logic := '0';
aclr1 : in std_logic := '0';
byteena_a : in std_logic_vector( (width_byteena_a - 1) downto 0) := (others => '1');
byteena_b : in std_logic_vector( (width_byteena_b - 1) downto 0) := (others => 'Z');
addressstall_a : in std_logic := '0';
addressstall_b : in std_logic := '0';
q_a : out std_logic_vector(width_a - 1 downto 0);
q_b : out std_logic_vector(width_b - 1 downto 0);
eccstatus : out std_logic_vector(2 downto 0) );
end component;
component altpll
generic (
intended_device_family : string := "Stratix" ;
operation_mode : string := "NORMAL" ;
pll_type : string := "AUTO" ;
qualify_conf_done : string := "OFF" ;
compensate_clock : string := "CLK0" ;
scan_chain : string := "LONG";
primary_clock : string := "inclk0" ;
inclk0_input_frequency : natural; -- required parameter
inclk1_input_frequency : natural := 0;
gate_lock_signal : string := "NO";
gate_lock_counter : integer := 0;
lock_high : natural := 1;
lock_low : natural := 5;
valid_lock_multiplier : natural := 1;
invalid_lock_multiplier : natural := 5;
switch_over_type : string := "AUTO";
switch_over_on_lossclk : string := "OFF" ;
switch_over_on_gated_lock : string := "OFF" ;
enable_switch_over_counter : string := "OFF";
switch_over_counter : natural := 0;
feedback_source : string := "EXTCLK0" ;
bandwidth : natural := 0;
bandwidth_type : string := "UNUSED";
spread_frequency : natural := 0;
down_spread : string := "0.0";
self_reset_on_gated_loss_lock : string := "OFF";
self_reset_on_loss_lock : string := "OFF";
lock_window_ui : string := "0.05";
width_clock : natural := 6;
width_phasecounterselect : natural := 4;
charge_pump_current_bits : natural := 9999;
loop_filter_c_bits : natural := 9999;
loop_filter_r_bits : natural := 9999;
scan_chain_mif_file : string := "UNUSED";
-- simulation-only parameters
simulation_type : string := "functional";
source_is_pll : string := "off";
skip_vco : string := "off";
-- internal clock specifications
clk9_multiply_by : natural := 1;
clk8_multiply_by : natural := 1;
clk7_multiply_by : natural := 1;
clk6_multiply_by : natural := 1;
clk5_multiply_by : natural := 1;
clk4_multiply_by : natural := 1;
clk3_multiply_by : natural := 1;
clk2_multiply_by : natural := 1;
clk1_multiply_by : natural := 1;
clk0_multiply_by : natural := 1;
clk9_divide_by : natural := 1;
clk8_divide_by : natural := 1;
clk7_divide_by : natural := 1;
clk6_divide_by : natural := 1;
clk5_divide_by : natural := 1;
clk4_divide_by : natural := 1;
clk3_divide_by : natural := 1;
clk2_divide_by : natural := 1;
clk1_divide_by : natural := 1;
clk0_divide_by : natural := 1;
clk9_phase_shift : string := "0";
clk8_phase_shift : string := "0";
clk7_phase_shift : string := "0";
clk6_phase_shift : string := "0";
clk5_phase_shift : string := "0";
clk4_phase_shift : string := "0";
clk3_phase_shift : string := "0";
clk2_phase_shift : string := "0";
clk1_phase_shift : string := "0";
clk0_phase_shift : string := "0";
clk5_time_delay : string := "0";
clk4_time_delay : string := "0";
clk3_time_delay : string := "0";
clk2_time_delay : string := "0";
clk1_time_delay : string := "0";
clk0_time_delay : string := "0";
clk9_duty_cycle : natural := 50;
clk8_duty_cycle : natural := 50;
clk7_duty_cycle : natural := 50;
clk6_duty_cycle : natural := 50;
clk5_duty_cycle : natural := 50;
clk4_duty_cycle : natural := 50;
clk3_duty_cycle : natural := 50;
clk2_duty_cycle : natural := 50;
clk1_duty_cycle : natural := 50;
clk0_duty_cycle : natural := 50;
clk2_output_frequency : natural := 0;
clk1_output_frequency : natural := 0;
clk0_output_frequency : natural := 0;
clk9_use_even_counter_mode : string := "OFF";
clk8_use_even_counter_mode : string := "OFF";
clk7_use_even_counter_mode : string := "OFF";
clk6_use_even_counter_mode : string := "OFF";
clk5_use_even_counter_mode : string := "OFF";
clk4_use_even_counter_mode : string := "OFF";
clk3_use_even_counter_mode : string := "OFF";
clk2_use_even_counter_mode : string := "OFF";
clk1_use_even_counter_mode : string := "OFF";
clk0_use_even_counter_mode : string := "OFF";
clk9_use_even_counter_value : string := "OFF";
clk8_use_even_counter_value : string := "OFF";
clk7_use_even_counter_value : string := "OFF";
clk6_use_even_counter_value : string := "OFF";
clk5_use_even_counter_value : string := "OFF";
clk4_use_even_counter_value : string := "OFF";
clk3_use_even_counter_value : string := "OFF";
clk2_use_even_counter_value : string := "OFF";
clk1_use_even_counter_value : string := "OFF";
clk0_use_even_counter_value : string := "OFF";
-- external clock specifications
extclk3_multiply_by : natural := 1;
extclk2_multiply_by : natural := 1;
extclk1_multiply_by : natural := 1;
extclk0_multiply_by : natural := 1;
extclk3_divide_by : natural := 1;
extclk2_divide_by : natural := 1;
extclk1_divide_by : natural := 1;
extclk0_divide_by : natural := 1;
extclk3_phase_shift : string := "0";
extclk2_phase_shift : string := "0";
extclk1_phase_shift : string := "0";
extclk0_phase_shift : string := "0";
extclk3_time_delay : string := "0";
extclk2_time_delay : string := "0";
extclk1_time_delay : string := "0";
extclk0_time_delay : string := "0";
extclk3_duty_cycle : natural := 50;
extclk2_duty_cycle : natural := 50;
extclk1_duty_cycle : natural := 50;
extclk0_duty_cycle : natural := 50;
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
sclkout0_phase_shift : string := "0";
sclkout1_phase_shift : string := "0";
dpa_multiply_by : integer := 0;
dpa_divide_by : integer := 0;
dpa_divider : integer := 0;
-- advanced user parameters
vco_min : natural := 0;
vco_max : natural := 0;
vco_center : natural := 0;
pfd_min : natural := 0;
pfd_max : natural := 0;
m_initial : natural := 1;
m : natural := 0; -- m must default to 0 to force altpll to calculate the internal parameters for itself
n : natural := 1;
m2 : natural := 1;
n2 : natural := 1;
ss : natural := 0;
c0_high : natural := 1;
c1_high : natural := 1;
c2_high : natural := 1;
c3_high : natural := 1;
c4_high : natural := 1;
c5_high : natural := 1;
c6_high : natural := 1;
c7_high : natural := 1;
c8_high : natural := 1;
c9_high : natural := 1;
l0_high : natural := 1;
l1_high : natural := 1;
g0_high : natural := 1;
g1_high : natural := 1;
g2_high : natural := 1;
g3_high : natural := 1;
e0_high : natural := 1;
e1_high : natural := 1;
e2_high : natural := 1;
e3_high : natural := 1;
c0_low : natural := 1;
c1_low : natural := 1;
c2_low : natural := 1;
c3_low : natural := 1;
c4_low : natural := 1;
c5_low : natural := 1;
c6_low : natural := 1;
c7_low : natural := 1;
c8_low : natural := 1;
c9_low : natural := 1;
l0_low : natural := 1;
l1_low : natural := 1;
g0_low : natural := 1;
g1_low : natural := 1;
g2_low : natural := 1;
g3_low : natural := 1;
e0_low : natural := 1;
e1_low : natural := 1;
e2_low : natural := 1;
e3_low : natural := 1;
c0_initial : natural := 1;
c1_initial : natural := 1;
c2_initial : natural := 1;
c3_initial : natural := 1;
c4_initial : natural := 1;
c5_initial : natural := 1;
c6_initial : natural := 1;
c7_initial : natural := 1;
c8_initial : natural := 1;
c9_initial : natural := 1;
l0_initial : natural := 1;
l1_initial : natural := 1;
g0_initial : natural := 1;
g1_initial : natural := 1;
g2_initial : natural := 1;
g3_initial : natural := 1;
e0_initial : natural := 1;
e1_initial : natural := 1;
e2_initial : natural := 1;
e3_initial : natural := 1;
c0_mode : string := "bypass" ;
c1_mode : string := "bypass" ;
c2_mode : string := "bypass" ;
c3_mode : string := "bypass" ;
c4_mode : string := "bypass" ;
c5_mode : string := "bypass" ;
c6_mode : string := "bypass" ;
c7_mode : string := "bypass" ;
c8_mode : string := "bypass" ;
c9_mode : string := "bypass" ;
l0_mode : string := "bypass" ;
l1_mode : string := "bypass" ;
g0_mode : string := "bypass" ;
g1_mode : string := "bypass" ;
g2_mode : string := "bypass" ;
g3_mode : string := "bypass" ;
e0_mode : string := "bypass" ;
e1_mode : string := "bypass" ;
e2_mode : string := "bypass" ;
e3_mode : string := "bypass" ;
c0_ph : natural := 0;
c1_ph : natural := 0;
c2_ph : natural := 0;
c3_ph : natural := 0;
c4_ph : natural := 0;
c5_ph : natural := 0;
c6_ph : natural := 0;
c7_ph : natural := 0;
c8_ph : natural := 0;
c9_ph : natural := 0;
l0_ph : natural := 0;
l1_ph : natural := 0;
g0_ph : natural := 0;
g1_ph : natural := 0;
g2_ph : natural := 0;
g3_ph : natural := 0;
e0_ph : natural := 0;
e1_ph : natural := 0;
e2_ph : natural := 0;
e3_ph : natural := 0;
m_ph : natural := 0;
l0_time_delay : natural := 0;
l1_time_delay : natural := 0;
g0_time_delay : natural := 0;
g1_time_delay : natural := 0;
g2_time_delay : natural := 0;
g3_time_delay : natural := 0;
e0_time_delay : natural := 0;
e1_time_delay : natural := 0;
e2_time_delay : natural := 0;
e3_time_delay : natural := 0;
m_time_delay : natural := 0;
n_time_delay : natural := 0;
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
c5_use_casc_in : string := "off";
c6_use_casc_in : string := "off";
c7_use_casc_in : string := "off";
c8_use_casc_in : string := "off";
c9_use_casc_in : string := "off";
m_test_source : integer := 5;
c0_test_source : integer := 5;
c1_test_source : integer := 5;
c2_test_source : integer := 5;
c3_test_source : integer := 5;
c4_test_source : integer := 5;
c5_test_source : integer := 5;
c6_test_source : integer := 5;
c7_test_source : integer := 5;
c8_test_source : integer := 5;
c9_test_source : integer := 5;
extclk3_counter : string := "e3" ;
extclk2_counter : string := "e2" ;
extclk1_counter : string := "e1" ;
extclk0_counter : string := "e0" ;
clk9_counter : string := "c9" ;
clk8_counter : string := "c8" ;
clk7_counter : string := "c7" ;
clk6_counter : string := "c6" ;
clk5_counter : string := "l1" ;
clk4_counter : string := "l0" ;
clk3_counter : string := "g3" ;
clk2_counter : string := "g2" ;
clk1_counter : string := "g1" ;
clk0_counter : string := "g0" ;
enable0_counter : string := "l0";
enable1_counter : string := "l0";
charge_pump_current : natural := 2;
loop_filter_r : string := " 1.000000";
loop_filter_c : natural := 5;
vco_post_scale : natural := 0;
vco_frequency_control : string := "AUTO";
vco_phase_shift_step : natural := 0;
lpm_hint : string := "UNUSED";
lpm_type : string := "altpll";
port_clkena0 : string := "PORT_CONNECTIVITY";
port_clkena1 : string := "PORT_CONNECTIVITY";
port_clkena2 : string := "PORT_CONNECTIVITY";
port_clkena3 : string := "PORT_CONNECTIVITY";
port_clkena4 : string := "PORT_CONNECTIVITY";
port_clkena5 : string := "PORT_CONNECTIVITY";
port_extclkena0 : string := "PORT_CONNECTIVITY";
port_extclkena1 : string := "PORT_CONNECTIVITY";
port_extclkena2 : string := "PORT_CONNECTIVITY";
port_extclkena3 : string := "PORT_CONNECTIVITY";
port_extclk0 : string := "PORT_CONNECTIVITY";
port_extclk1 : string := "PORT_CONNECTIVITY";
port_extclk2 : string := "PORT_CONNECTIVITY";
port_extclk3 : string := "PORT_CONNECTIVITY";
port_clkbad0 : string := "PORT_CONNECTIVITY";
port_clkbad1 : string := "PORT_CONNECTIVITY";
port_clk0 : string := "PORT_CONNECTIVITY";
port_clk1 : string := "PORT_CONNECTIVITY";
port_clk2 : string := "PORT_CONNECTIVITY";
port_clk3 : string := "PORT_CONNECTIVITY";
port_clk4 : string := "PORT_CONNECTIVITY";
port_clk5 : string := "PORT_CONNECTIVITY";
port_clk6 : string := "PORT_CONNECTIVITY";
port_clk7 : string := "PORT_CONNECTIVITY";
port_clk8 : string := "PORT_CONNECTIVITY";
port_clk9 : string := "PORT_CONNECTIVITY";
port_scandata : string := "PORT_CONNECTIVITY";
port_scandataout : string := "PORT_CONNECTIVITY";
port_scandone : string := "PORT_CONNECTIVITY";
port_sclkout1 : string := "PORT_CONNECTIVITY";
port_sclkout0 : string := "PORT_CONNECTIVITY";
port_activeclock : string := "PORT_CONNECTIVITY";
port_clkloss : string := "PORT_CONNECTIVITY";
port_inclk1 : string := "PORT_CONNECTIVITY";
port_inclk0 : string := "PORT_CONNECTIVITY";
port_fbin : string := "PORT_CONNECTIVITY";
port_fbout : string := "PORT_CONNECTIVITY";
port_pllena : string := "PORT_CONNECTIVITY";
port_clkswitch : string := "PORT_CONNECTIVITY";
port_areset : string := "PORT_CONNECTIVITY";
port_pfdena : string := "PORT_CONNECTIVITY";
port_scanclk : string := "PORT_CONNECTIVITY";
port_scanaclr : string := "PORT_CONNECTIVITY";
port_scanread : string := "PORT_CONNECTIVITY";
port_scanwrite : string := "PORT_CONNECTIVITY";
port_enable0 : string := "PORT_CONNECTIVITY";
port_enable1 : string := "PORT_CONNECTIVITY";
port_locked : string := "PORT_CONNECTIVITY";
port_configupdate : string := "PORT_CONNECTIVITY";
port_phasecounterselect : string := "PORT_CONNECTIVITY";
port_phasedone : string := "PORT_CONNECTIVITY";
port_phasestep : string := "PORT_CONNECTIVITY";
port_phaseupdown : string := "PORT_CONNECTIVITY";
port_vcooverrange : string := "PORT_CONNECTIVITY";
port_vcounderrange : string := "PORT_CONNECTIVITY";
port_scanclkena : string := "PORT_CONNECTIVITY";
using_fbmimicbidir_port : string := "ON";
sim_gate_lock_device_behavior : string := "OFF" );
port (
inclk : in std_logic_vector(1 downto 0) := (others => '0');
fbin : in std_logic := '0';
pllena : in std_logic := '1';
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
clkena : in std_logic_vector(5 downto 0) := (others => '1');
extclkena : in std_logic_vector(3 downto 0) := (others => '1');
scanclk : in std_logic := '0';
scanclkena : in std_logic := '1';
scanaclr : in std_logic := '0';
scanread : in std_logic := '0';
scanwrite : in std_logic := '0';
scandata : in std_logic := '0';
phasecounterselect : in std_logic_vector(width_phasecounterselect-1 downto 0) := (others => '0');
phaseupdown : in std_logic := '0';
phasestep : in std_logic := '0';
configupdate : in std_logic := '0';
fbmimicbidir : inout std_logic := '1';
clk : out std_logic_vector(width_clock-1 downto 0);
extclk : out std_logic_vector(3 downto 0);
clkbad : out std_logic_vector(1 downto 0);
enable0 : out std_logic;
enable1 : out std_logic;
activeclock : out std_logic;
clkloss : out std_logic;
locked : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
sclkout0 : out std_logic;
sclkout1 : out std_logic;
phasedone : out std_logic;
vcooverrange : out std_logic;
vcounderrange : out std_logic;
fbout : out std_logic );
end component;
component altfp_mult
generic (
width_exp : integer := 11;
width_man : integer := 31;
dedicated_multiplier_circuitry : string := "AUTO";
reduced_functionality : string := "NO";
pipeline : natural := 5;
denormal_support : string := "YES";
exception_handling : string := "YES";
lpm_hint : string := "UNUSED";
lpm_type : string := "altfp_mult" );
port (
clock : in std_logic;
clk_en : in std_logic := '1';
aclr : in std_logic := '0';
dataa : in std_logic_vector(WIDTH_EXP + WIDTH_MAN downto 0) ;
datab : in std_logic_vector(WIDTH_EXP + WIDTH_MAN downto 0) ;
result : out std_logic_vector(WIDTH_EXP + WIDTH_MAN downto 0) ;
overflow : out std_logic ;
underflow : out std_logic ;
zero : out std_logic ;
denormal : out std_logic ;
indefinite : out std_logic ;
nan : out std_logic );
end component;
component altsqrt
generic (
q_port_width : integer := 1;
r_port_width : integer := 1;
width : integer := 1;
pipeline : integer := 0;
lpm_hint : string := "UNUSED";
lpm_type : string := "altsqrt" );
port (
radical : in std_logic_vector(width - 1 downto 0) ;
clk : in std_logic := '1';
ena : in std_logic := '1';
aclr : in std_logic := '0';
q : out std_logic_vector( q_port_width - 1 downto 0) ;
remainder : out std_logic_vector( r_port_width - 1 downto 0) );
end component;
component parallel_add
generic (
width : natural := 4;
size : natural := 2;
widthr : natural := 4;
shift : natural := 0;
msw_subtract : string := "NO";
representation : string := "UNSIGNED";
pipeline : natural := 0;
result_alignment : string := "LSB";
lpm_hint : string := "UNUSED";
lpm_type : string := "parallel_add" );
port (
data : in altera_mf_logic_2D(size - 1 downto 0, width - 1 downto 0);
clock : in std_logic := '1';
aclr : in std_logic := '0';
clken : in std_logic := '1';
result : out std_logic_vector(widthr - 1 downto 0) );
end component;
component a_graycounter
generic (
width : natural;
pvalue : natural;
lpm_hint : string := "UNUSED";
lpm_type : string := "a_graycounter" );
port (
clock : in std_logic;
clk_en : in std_logic := '1';
cnt_en : in std_logic := '1';
updown : in std_logic := '1';
aclr : in std_logic := '0';
sclr : in std_logic := '0';
qbin : out std_logic_vector(width-1 downto 0);
q : out std_logic_vector(width-1 downto 0) );
end component;
component altsquare
generic (
data_width : natural;
pipeline : natural;
representation : string := "UNSIGNED";
result_alignment : string := "LSB";
result_width : natural;
lpm_hint : string := "UNUSED";
lpm_type : string := "altsquare"
);
port(
aclr : in std_logic := '0';
clock : in std_logic := '1';
data : in std_logic_vector(data_width-1 downto 0);
ena : in std_logic := '1';
result : out std_logic_vector(result_width-1 downto 0)
);
end component;
component sld_virtual_jtag
generic (
lpm_type : string;
lpm_hint : string;
sld_auto_instance_index : string;
sld_instance_index : integer;
sld_ir_width : integer;
sld_sim_n_scan : integer;
sld_sim_total_length : integer;
sld_sim_action : string);
port (
tdo : in std_logic := '0';
ir_out : in std_logic_vector(sld_ir_width - 1 downto 0) := (others => '0');
tck : out std_logic;
tdi : out std_logic;
ir_in : out std_logic_vector(sld_ir_width - 1 downto 0);
virtual_state_cdr : out std_logic;
virtual_state_sdr : out std_logic;
virtual_state_e1dr : out std_logic;
virtual_state_pdr : out std_logic;
virtual_state_e2dr : out std_logic;
virtual_state_udr : out std_logic;
virtual_state_cir : out std_logic;
virtual_state_uir : out std_logic;
jtag_state_tlr : out std_logic;
jtag_state_rti : out std_logic;
jtag_state_sdrs : out std_logic;
jtag_state_cdr : out std_logic;
jtag_state_sdr : out std_logic;
jtag_state_e1dr : out std_logic;
jtag_state_pdr : out std_logic;
jtag_state_e2dr : out std_logic;
jtag_state_udr : out std_logic;
jtag_state_sirs : out std_logic;
jtag_state_cir : out std_logic;
jtag_state_sir : out std_logic;
jtag_state_e1ir : out std_logic;
jtag_state_pir : out std_logic;
jtag_state_e2ir : out std_logic;
jtag_state_uir : out std_logic;
tms : out std_logic);
end component;
component sld_virtual_jtag_basic
generic (
lpm_type : string;
lpm_hint : string;
sld_mfg_id : natural range 0 to 2047;
sld_type_id : natural range 0 to 255;
sld_version : natural range 0 to 31;
sld_auto_instance_index : string;
sld_instance_index : integer;
sld_ir_width : integer;
sld_sim_n_scan : integer;
sld_sim_total_length : integer;
sld_sim_action : string);
port (
tdo : in std_logic := '0';
ir_out : in std_logic_vector(sld_ir_width - 1 downto 0) := (others => '0');
tck : out std_logic;
tdi : out std_logic;
ir_in : out std_logic_vector(sld_ir_width - 1 downto 0);
virtual_state_cdr : out std_logic;
virtual_state_sdr : out std_logic;
virtual_state_e1dr : out std_logic;
virtual_state_pdr : out std_logic;
virtual_state_e2dr : out std_logic;
virtual_state_udr : out std_logic;
virtual_state_cir : out std_logic;
virtual_state_uir : out std_logic;
jtag_state_tlr : out std_logic;
jtag_state_rti : out std_logic;
jtag_state_sdrs : out std_logic;
jtag_state_cdr : out std_logic;
jtag_state_sdr : out std_logic;
jtag_state_e1dr : out std_logic;
jtag_state_pdr : out std_logic;
jtag_state_e2dr : out std_logic;
jtag_state_udr : out std_logic;
jtag_state_sirs : out std_logic;
jtag_state_cir : out std_logic;
jtag_state_sir : out std_logic;
jtag_state_e1ir : out std_logic;
jtag_state_pir : out std_logic;
jtag_state_e2ir : out std_logic;
jtag_state_uir : out std_logic;
tms : out std_logic);
end component;
component altdq_dqs
generic (
delay_buffer_mode : string := "LOW";
delay_dqs_enable_by_half_cycle : string := "FALSE";
intended_device_family : string := "UNUSED";
dq_half_rate_use_dataoutbypass : string := "FALSE";
dq_input_reg_async_mode : string := "NONE";
dq_input_reg_clk_source : string := "DQS_BUS";
dq_input_reg_mode : string := "NONE";
dq_input_reg_power_up : string := "LOW";
dq_input_reg_sync_mode : string := "NONE";
dq_input_reg_use_clkn : string := "FALSE";
dq_ipa_add_input_cycle_delay : string := "FALSE";
dq_ipa_add_phase_transfer_reg : string := "FALSE";
dq_ipa_bypass_output_register : string := "FALSE";
dq_ipa_invert_phase : string := "FALSE";
dq_ipa_phase_setting : integer := 0;
dq_oe_reg_async_mode : string := "NONE";
dq_oe_reg_mode : string := "NONE";
dq_oe_reg_power_up : string := "LOW";
dq_oe_reg_sync_mode : string := "NONE";
dq_output_reg_async_mode : string := "NONE";
dq_output_reg_mode : string := "NONE";
dq_output_reg_power_up : string := "LOW";
dq_output_reg_sync_mode : string := "NONE";
dqs_ctrl_latches_enable : string := "FALSE";
dqs_delay_chain_delayctrlin_source : string := "CORE";
dqs_delay_chain_phase_setting : integer := 0;
dqs_dqsn_mode : string := "NONE";
dqs_enable_ctrl_add_phase_transfer_reg : string := "FALSE";
dqs_enable_ctrl_invert_phase : string := "FALSE";
dqs_enable_ctrl_phase_setting : integer := 0;
dqs_input_frequency : string := "UNUSED";
dqs_oe_reg_async_mode : string := "NONE";
dqs_oe_reg_mode : string := "NONE";
dqs_oe_reg_power_up : string := "LOW";
dqs_oe_reg_sync_mode : string := "NONE";
dqs_offsetctrl_enable : string := "FALSE";
dqs_output_reg_async_mode : string := "NONE";
dqs_output_reg_mode : string := "NONE";
dqs_output_reg_power_up : string := "LOW";
dqs_output_reg_sync_mode : string := "NONE";
dqs_phase_shift : integer := 0;
io_clock_divider_clk_source : string := "CORE";
io_clock_divider_invert_phase : string := "FALSE";
io_clock_divider_phase_setting : integer := 0;
level_dqs_enable : string := "FALSE";
number_of_bidir_dq : integer := 1;
number_of_clk_divider : integer := 1;
number_of_input_dq : integer := 1;
number_of_output_dq : integer := 1;
oct_reg_mode : string := "NONE";
use_dq_input_delay_chain : string := "FALSE";
use_dq_ipa : string := "FALSE";
use_dq_ipa_phasectrlin : string := "TRUE";
use_dq_oe_delay_chain1 : string := "FALSE";
use_dq_oe_delay_chain2 : string := "FALSE";
use_dq_oe_path : string := "FALSE";
use_dq_output_delay_chain1 : string := "FALSE";
use_dq_output_delay_chain2 : string := "FALSE";
use_dqs : string := "FALSE";
use_dqs_delay_chain : string := "FALSE";
use_dqs_delay_chain_phasectrlin : string := "FALSE";
use_dqs_enable : string := "FALSE";
use_dqs_enable_ctrl : string := "FALSE";
use_dqs_enable_ctrl_phasectrlin : string := "TRUE";
use_dqs_input_delay_chain : string := "FALSE";
use_dqs_input_path : string := "FALSE";
use_dqs_oe_delay_chain1 : string := "FALSE";
use_dqs_oe_delay_chain2 : string := "FALSE";
use_dqs_oe_path : string := "FALSE";
use_dqs_output_delay_chain1 : string := "FALSE";
use_dqs_output_delay_chain2 : string := "FALSE";
use_dqs_output_path : string := "FALSE";
use_dqsbusout_delay_chain : string := "FALSE";
use_dqsenable_delay_chain : string := "FALSE";
use_dynamic_oct : string := "FALSE";
use_half_rate : string := "FALSE";
use_io_clock_divider_masterin : string := "FALSE";
use_io_clock_divider_phasectrlin : string := "TRUE";
use_oct_delay_chain1 : string := "FALSE";
use_oct_delay_chain2 : string := "FALSE";
lpm_hint : string := "UNUSED";
lpm_type : string := "altdq_dqs");
port (
bidir_dq_areset : in std_logic_vector(number_of_bidir_dq - 1 downto 0) := (others => '0');
bidir_dq_hr_oct_in : in std_logic_vector(2 * number_of_bidir_dq - 1 downto 0) := (others => '0');
bidir_dq_hr_oe_in : in std_logic_vector(2 * number_of_bidir_dq - 1 downto 0) := (others => '0');
bidir_dq_hr_output_data_in : in std_logic_vector(4 * number_of_bidir_dq - 1 downto 0) := (others => '0');
bidir_dq_input_data_in : in std_logic_vector(number_of_bidir_dq - 1 downto 0) := (others => '0');
bidir_dq_io_config_ena : in std_logic_vector(number_of_bidir_dq - 1 downto 0) := (others => '1');
bidir_dq_oct_in : in std_logic_vector(number_of_bidir_dq - 1 downto 0) := (others => '0');
bidir_dq_oe_in : in std_logic_vector(number_of_bidir_dq - 1 downto 0) := (others => '0');
bidir_dq_output_data_in : in std_logic_vector(number_of_bidir_dq - 1 downto 0) := (others => '0');
bidir_dq_output_data_in_high : in std_logic_vector(number_of_bidir_dq - 1 downto 0) := (others => '0');
bidir_dq_output_data_in_low : in std_logic_vector(number_of_bidir_dq - 1 downto 0) := (others => '0');
bidir_dq_sreset : in std_logic_vector(number_of_bidir_dq - 1 downto 0) := (others => '0');
config_clk : in std_logic := '0';
config_datain : in std_logic := '0';
config_update : in std_logic := '0';
core_delayctrlin : in std_logic_vector(5 downto 0) := (others => '0');
dll_delayctrlin : in std_logic_vector(5 downto 0) := (others => '0');
dq_hr_output_reg_clk : in std_logic := '0';
dq_input_reg_clk : in std_logic := '0';
dq_input_reg_clkena : in std_logic := '1';
dq_ipa_clk : in std_logic := '0';
dq_output_reg_clk : in std_logic := '0';
dq_output_reg_clkena : in std_logic := '1';
dqs_areset : in std_logic := '0';
dqs_config_ena : in std_logic := '1';
dqs_enable_ctrl_clk : in std_logic := '1';
dqs_enable_ctrl_hr_datainhi : in std_logic := '0';
dqs_enable_ctrl_hr_datainlo : in std_logic := '0';
dqs_enable_ctrl_in : in std_logic := '1';
dqs_enable_in : in std_logic := '1';
dqs_hr_oct_in : in std_logic_vector(1 downto 0) := (others => '0');
dqs_hr_oe_in : in std_logic_vector(1 downto 0) := (others => '0');
dqs_hr_output_data_in : in std_logic_vector(3 downto 0) := (others => '0');
dqs_hr_output_reg_clk : in std_logic := '0';
dqs_input_data_in : in std_logic := '0';
dqs_io_config_ena : in std_logic := '1';
dqs_oct_in : in std_logic := '0';
dqs_oe_in : in std_logic := '0';
dqs_output_data_in : in std_logic := '0';
dqs_output_data_in_high : in std_logic := '0';
dqs_output_data_in_low : in std_logic := '0';
dqs_output_reg_clk : in std_logic := '0';
dqs_output_reg_clkena : in std_logic := '1';
dqs_sreset : in std_logic := '0';
dqsn_areset : in std_logic := '0';
dqsn_hr_oct_in : in std_logic_vector(1 downto 0) := (others => '0');
dqsn_hr_oe_in : in std_logic_vector(1 downto 0) := (others => '0');
dqsn_hr_output_data_in : in std_logic_vector(3 downto 0) := (others => '0');
dqsn_input_data_in : in std_logic := '0';
dqsn_io_config_ena : in std_logic := '1';
dqsn_oct_in : in std_logic := '0';
dqsn_oe_in : in std_logic := '0';
dqsn_output_data_in : in std_logic := '0';
dqsn_output_data_in_high : in std_logic := '0';
dqsn_output_data_in_low : in std_logic := '0';
dqsn_sreset : in std_logic := '0';
dqsupdateen : in std_logic := '0';
hr_oct_reg_clk : in std_logic := '0';
input_dq_areset : in std_logic_vector(number_of_input_dq - 1 downto 0) := (others => '0');
input_dq_hr_oct_in : in std_logic_vector(2 * number_of_input_dq - 1 downto 0) := (others => '0');
input_dq_input_data_in : in std_logic_vector(number_of_input_dq - 1 downto 0) := (others => '0');
input_dq_io_config_ena : in std_logic_vector(number_of_input_dq - 1 downto 0) := (others => '1');
input_dq_oct_in : in std_logic_vector(number_of_input_dq - 1 downto 0) := (others => '0');
input_dq_sreset : in std_logic_vector(number_of_input_dq - 1 downto 0) := (others => '0');
io_clock_divider_clk : in std_logic := '0';
io_clock_divider_masterin : in std_logic := '0';
oct_reg_clk : in std_logic := '0';
offsetctrlin : in std_logic_vector(5 downto 0) := (others => '0');
output_dq_areset : in std_logic_vector(number_of_output_dq - 1 downto 0) := (others => '0');
output_dq_hr_oct_in : in std_logic_vector(2 * number_of_output_dq - 1 downto 0) := (others => '0');
output_dq_hr_oe_in : in std_logic_vector(2 * number_of_output_dq - 1 downto 0) := (others => '0');
output_dq_hr_output_data_in : in std_logic_vector(4 * number_of_output_dq - 1 downto 0) := (others => '0');
output_dq_io_config_ena : in std_logic_vector(number_of_output_dq - 1 downto 0) := (others => '1');
output_dq_oct_in : in std_logic_vector(number_of_output_dq - 1 downto 0) := (others => '0');
output_dq_oe_in : in std_logic_vector(number_of_output_dq - 1 downto 0) := (others => '0');
output_dq_output_data_in : in std_logic_vector(number_of_output_dq - 1 downto 0) := (others => '0');
output_dq_output_data_in_high : in std_logic_vector(number_of_output_dq - 1 downto 0) := (others => '0');
output_dq_output_data_in_low : in std_logic_vector(number_of_output_dq - 1 downto 0) := (others => '0');
output_dq_sreset : in std_logic_vector(number_of_output_dq - 1 downto 0) := (others => '0');
bidir_dq_hr_input_data_out : out std_logic_vector(4 * number_of_bidir_dq - 1 downto 0);
bidir_dq_input_data_out : out std_logic_vector(number_of_bidir_dq - 1 downto 0);
bidir_dq_input_data_out_high : out std_logic_vector(number_of_bidir_dq - 1 downto 0);
bidir_dq_input_data_out_low : out std_logic_vector(number_of_bidir_dq - 1 downto 0);
bidir_dq_oct_out : out std_logic_vector(number_of_bidir_dq - 1 downto 0);
bidir_dq_oe_out : out std_logic_vector(number_of_bidir_dq - 1 downto 0);
bidir_dq_output_data_out : out std_logic_vector(number_of_bidir_dq - 1 downto 0);
dqs_bus_out : out std_logic;
dqs_input_data_out : out std_logic;
dqs_oct_out : out std_logic;
dqs_oe_out : out std_logic;
dqs_output_data_out : out std_logic;
dqsn_bus_out : out std_logic;
dqsn_input_data_out : out std_logic;
dqsn_oct_out : out std_logic;
dqsn_oe_out : out std_logic;
dqsn_output_data_out : out std_logic;
input_dq_hr_input_data_out : out std_logic_vector(4 * number_of_input_dq - 1 downto 0);
input_dq_input_data_out : out std_logic_vector(number_of_input_dq - 1 downto 0);
input_dq_input_data_out_high : out std_logic_vector(number_of_input_dq - 1 downto 0);
input_dq_input_data_out_low : out std_logic_vector(number_of_input_dq - 1 downto 0);
input_dq_oct_out : out std_logic_vector(number_of_input_dq - 1 downto 0);
io_clock_divider_clkout : out std_logic_vector(number_of_clk_divider - 1 downto 0);
io_clock_divider_slaveout : out std_logic;
output_dq_oct_out : out std_logic_vector(number_of_output_dq - 1 downto 0);
output_dq_oe_out : out std_logic_vector(number_of_output_dq - 1 downto 0);
output_dq_output_data_out : out std_logic_vector(number_of_output_dq - 1 downto 0));
end component;
component altera_std_synchronizer
generic (depth : integer := 3);
port (
clk : in std_logic;
reset_n : in std_logic;
din : in std_logic;
dout : out std_logic
);
end component;
component altera_std_synchronizer_bundle
generic (depth : integer := 3;
width : integer := 1);
port (
clk : in std_logic;
reset_n : in std_logic;
din : in std_logic_vector(width-1 downto 0);
dout : out std_logic_vector(width-1 downto 0)
);
end component;
component alt_cal
generic (
number_of_channels : integer := 1;
channel_address_width : integer := 1;
sim_model_mode : string := "TRUE";
lpm_hint : string := "UNUSED";
lpm_type : string := "alt_cal"
);
PORT
(
busy : OUT STD_LOGIC;
cal_error : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
clock : IN STD_LOGIC;
dprio_addr : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
dprio_busy : IN STD_LOGIC;
dprio_datain : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
dprio_dataout : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
dprio_rden : OUT STD_LOGIC;
dprio_wren : OUT STD_LOGIC;
quad_addr : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
remap_addr : IN STD_LOGIC_VECTOR (9 DOWNTO 0) := (OTHERS => '0');
reset : IN STD_LOGIC := '0';
retain_addr : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
start : IN STD_LOGIC := '0';
testbuses : IN STD_LOGIC_VECTOR (4 * number_of_channels - 1 DOWNTO 0) := (OTHERS => '0')
);
end component;
constant ELA_STATUS_BITS : natural := 4;
constant N_ELA_INSTRS : natural := 8;
constant SLD_IR_BITS : natural := N_ELA_INSTRS;
component sld_signaltap
generic (
SLD_CURRENT_RESOURCE_WIDTH : natural := 0;
SLD_INVERSION_MASK : std_logic_vector := "0";
SLD_POWER_UP_TRIGGER : natural := 0;
SLD_ADVANCED_TRIGGER_6 : string := "NONE";
SLD_ADVANCED_TRIGGER_9 : string := "NONE";
SLD_ADVANCED_TRIGGER_7 : string := "NONE";
SLD_STORAGE_QUALIFIER_ADVANCED_CONDITION_ENTITY : string := "basic";
SLD_STORAGE_QUALIFIER_GAP_RECORD : natural := 0;
SLD_INCREMENTAL_ROUTING : natural := 0;
SLD_STORAGE_QUALIFIER_PIPELINE : natural := 0;
SLD_TRIGGER_IN_ENABLED : natural := 0;
SLD_STATE_BITS : natural := 11;
SLD_STATE_FLOW_USE_GENERATED : natural := 0;
SLD_INVERSION_MASK_LENGTH : integer := 1;
SLD_DATA_BITS : natural := 1;
SLD_BUFFER_FULL_STOP : natural := 1;
SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH : natural := 0;
SLD_ATTRIBUTE_MEM_MODE : string := "OFF";
SLD_STORAGE_QUALIFIER_MODE : string := "OFF";
SLD_STATE_FLOW_MGR_ENTITY : string := "state_flow_mgr_entity.vhd";
SLD_NODE_CRC_LOWORD : natural := 50132;
SLD_ADVANCED_TRIGGER_5 : string := "NONE";
SLD_TRIGGER_BITS : natural := 1;
SLD_STORAGE_QUALIFIER_BITS : natural := 1;
SLD_ADVANCED_TRIGGER_10 : string := "NONE";
SLD_MEM_ADDRESS_BITS : natural := 7;
SLD_ADVANCED_TRIGGER_ENTITY : string := "basic";
SLD_ADVANCED_TRIGGER_4 : string := "NONE";
SLD_TRIGGER_LEVEL : natural := 10;
SLD_ADVANCED_TRIGGER_8 : string := "NONE";
SLD_RAM_BLOCK_TYPE : string := "AUTO";
SLD_ADVANCED_TRIGGER_2 : string := "NONE";
SLD_ADVANCED_TRIGGER_1 : string := "NONE";
SLD_DATA_BIT_CNTR_BITS : natural := 4;
lpm_type : string := "sld_signaltap";
SLD_NODE_CRC_BITS : natural := 32;
SLD_SAMPLE_DEPTH : natural := 16;
SLD_ENABLE_ADVANCED_TRIGGER : natural := 0;
SLD_SEGMENT_SIZE : natural := 0;
SLD_NODE_INFO : natural := 0;
SLD_STORAGE_QUALIFIER_ENABLE_ADVANCED_CONDITION : natural := 0;
SLD_NODE_CRC_HIWORD : natural := 41394;
SLD_TRIGGER_LEVEL_PIPELINE : natural := 1;
SLD_ADVANCED_TRIGGER_3 : string := "NONE"
);
port (
jtag_state_sdr : in std_logic := '0';
ir_out : out std_logic_vector(SLD_IR_BITS-1 downto 0);
jtag_state_cdr : in std_logic := '0';
ir_in : in std_logic_vector(SLD_IR_BITS-1 downto 0) := (others => '0');
tdi : in std_logic := '0';
acq_trigger_out : out std_logic_vector(SLD_TRIGGER_BITS-1 downto 0);
jtag_state_uir : in std_logic := '0';
acq_trigger_in : in std_logic_vector(SLD_TRIGGER_BITS-1 downto 0) := (others => '0');
trigger_out : out std_logic;
storage_enable : in std_logic := '0';
acq_data_out : out std_logic_vector(SLD_DATA_BITS-1 downto 0);
acq_data_in : in std_logic_vector(SLD_DATA_BITS-1 downto 0) := (others => '0');
acq_storage_qualifier_in : in std_logic_vector(SLD_STORAGE_QUALIFIER_BITS-1 downto 0) := (others => '0');
jtag_state_udr : in std_logic := '0';
tdo : out std_logic;
crc : in std_logic_vector(SLD_NODE_CRC_BITS-1 downto 0) := (others => '0');
jtag_state_e1dr : in std_logic := '0';
raw_tck : in std_logic := '0';
usr1 : in std_logic := '0';
acq_clk : in std_logic;
shift : in std_logic := '0';
ena : in std_logic := '0';
clr : in std_logic := '0';
trigger_in : in std_logic := '0';
update : in std_logic := '0';
rti : in std_logic := '0'
);
end component; --sld_signaltap
component altstratixii_oct
generic (
lpm_type : string := "altstratixii_oct"
);
port (
terminationenable : in std_logic;
terminationclock : in std_logic;
rdn : in std_logic;
rup : in std_logic
);
end component; --altstratixii_oct
constant TOP_PFL_IR_BITS : natural := 5;
constant N_FLASH_BITS : natural := 4;
component altparallel_flash_loader
generic (
flash_data_width : natural := 16;
normal_mode : natural := 1;
fifo_size : natural := 16;
safe_mode_revert : natural := 0;
dclk_divisor : natural := 1;
safe_mode_retry : natural := 1;
features_cfg : natural := 1;
burst_mode_numonyx : natural := 0;
burst_mode_intel : natural := 0;
burst_mode : natural := 0;
clk_divisor : natural := 1;
addr_width : natural := 20;
option_bits_start_address : natural := 0;
safe_mode_revert_addr : natural := 0;
enhanced_flash_programming : natural := 0;
page_mode : natural := 0;
lpm_type : string := "ALTPARALLEL_FLASH_LOADER";
features_pgm : natural := 1;
n_flash : natural := 1;
burst_mode_spansion : natural := 0;
auto_restart : STRING := "OFF";
page_clk_divisor : natural := 1;
conf_data_width : natural := 1;
TRISTATE_CHECKBOX : natural := 0;
safe_mode_halt : natural := 0
);
port (
fpga_data : out std_logic_vector(conf_data_width-1 downto 0);
fpga_dclk : out std_logic;
flash_nce : out std_logic;
fpga_nstatus : in std_logic := '0';
pfl_clk : in std_logic := '0';
fpga_nconfig : out std_logic;
flash_noe : out std_logic;
flash_nwe : out std_logic;
fpga_conf_done : in std_logic := '0';
pfl_flash_access_granted : in std_logic := '0';
pfl_nreconfigure : in std_logic := '1';
flash_nreset : out std_logic;
pfl_nreset : in std_logic := '0';
flash_data : inout std_logic_vector(flash_data_width-1 downto 0);
flash_nadv : out std_logic;
flash_clk : out std_logic;
flash_addr : out std_logic_vector(addr_width-1 downto 0);
pfl_flash_access_request : out std_logic;
fpga_pgm : in std_logic_vector(2 downto 0) := (others => '0')
);
end component; --altparallel_flash_loader
component altserial_flash_loader
generic (
enhanced_mode : natural := 0;
intended_device_family : STRING := "Cyclone";
enable_shared_access : STRING := "OFF";
lpm_type : STRING := "ALTSERIAL_FLASH_LOADER"
);
port (
noe : in std_logic := '0';
asmi_access_granted : in std_logic := '1';
sdoin : in std_logic := '0';
asmi_access_request : out std_logic;
data0out : out std_logic;
scein : in std_logic := '0';
dclkin : in std_logic := '0'
);
end component; --altserial_flash_loader
component altsource_probe
generic (
probe_width : natural := 1;
lpm_hint : string := "UNUSED";
source_width : natural := 1;
instance_id : string := "UNUSED";
sld_instance_index : natural := 0;
source_initial_value : string := "0";
sld_ir_width : natural := 4;
lpm_type : string := "altsource_probe";
sld_auto_instance_index : string := "YES";
SLD_NODE_INFO : natural := 4746752;
enable_metastability : string := "NO"
);
port (
jtag_state_sdr : in std_logic;
source : out std_logic_vector(source_width-1 downto 0);
ir_out : out std_logic_vector(sld_ir_width-1 downto 0);
jtag_state_cdr : in std_logic;
ir_in : in std_logic_vector(sld_ir_width-1 downto 0);
jtag_state_tlr : in std_logic;
tdi : in std_logic;
jtag_state_uir : in std_logic;
source_ena : in std_logic;
jtag_state_cir : in std_logic;
jtag_state_udr : in std_logic;
tdo : out std_logic;
clrn : in std_logic;
jtag_state_e1dr : in std_logic;
source_clk : in std_logic;
raw_tck : in std_logic;
usr1 : in std_logic;
ena : in std_logic;
probe : in std_logic_vector(probe_width-1 downto 0)
);
end component; --altsource_probe
end altera_mf_components;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity tb_via6522 is
end tb_via6522;
architecture tb of tb_via6522 is
signal clock : std_logic := '0';
signal clock_en : std_logic := '0'; -- for counters and stuff
signal reset : std_logic;
signal addr : std_logic_vector(3 downto 0) := X"0";
signal wen : std_logic := '0';
signal ren : std_logic := '0';
signal data_in : std_logic_vector(7 downto 0) := X"00";
signal data_out : std_logic_vector(7 downto 0) := X"00";
signal irq : std_logic;
-- pio --
signal port_a_o : std_logic_vector(7 downto 0);
signal port_a_t : std_logic_vector(7 downto 0);
-- signal port_a_i : std_logic_vector(7 downto 0);
signal port_b_o : std_logic_vector(7 downto 0);
signal port_b_t : std_logic_vector(7 downto 0);
-- signal port_b_i : std_logic_vector(7 downto 0);
-- handshake pins
-- signal ca1_i : std_logic;
signal ca2_o : std_logic;
-- signal ca2_i : std_logic;
signal ca2_t : std_logic;
signal cb1_o : std_logic;
-- signal cb1_i : std_logic;
signal cb1_t : std_logic;
signal cb2_o : std_logic;
-- signal cb2_i : std_logic;
signal cb2_t : std_logic;
signal ca1, ca2 : std_logic;
signal cb1, cb2 : std_logic;
signal port_a : std_logic_vector(7 downto 0);
signal port_b : std_logic_vector(7 downto 0);
begin
port_a <= (others => 'H');
port_b <= (others => 'H');
ca1 <= 'H';
ca2 <= ca2_o when ca2_t='1' else 'H';
cb1 <= cb1_o when cb1_t='1' else 'H';
cb2 <= cb2_o when cb2_t='1' else 'H';
process(port_a_o, port_a_t, port_b_o, port_b_t)
begin
for i in 0 to 7 loop
if port_a_t(i)='1' then
port_a(i) <= port_a_o(i);
else
port_a(i) <= 'H';
end if;
if port_b_t(i)='1' then
port_b(i) <= port_b_o(i);
else
port_b(i) <= 'H';
end if;
end loop;
end process;
via: entity work.via6522
port map (
clock => clock,
clock_en => clock_en, -- for counters and stuff
reset => reset,
addr => addr,
wen => wen,
ren => ren,
data_in => data_in,
data_out => data_out,
-- pio --
port_a_o => port_a_o,
port_a_t => port_a_t,
port_a_i => port_a,
port_b_o => port_b_o,
port_b_t => port_b_t,
port_b_i => port_b,
-- handshake pins
ca1_i => ca1,
ca2_o => ca2_o,
ca2_i => ca2,
ca2_t => ca2_t,
cb1_o => cb1_o,
cb1_i => cb1,
cb1_t => cb1_t,
cb2_o => cb2_o,
cb2_i => cb2,
cb2_t => cb2_t,
irq => irq );
clock <= not clock after 125 ns;
reset <= '1', '0' after 2 us;
ce: process
begin
clock_en <= '0';
wait until clock='1';
wait until clock='1';
wait until clock='1';
clock_en <= '1';
wait until clock='1';
end process;
test: process
procedure do_write(a: std_logic_vector(3 downto 0); d: std_logic_vector(7 downto 0)) is
begin
wait until clock='1';
addr <= a;
data_in <= d;
wen <= '1';
wait until clock='1';
wen <= '0';
end do_write;
procedure do_read(a: std_logic_vector(3 downto 0); d: out std_logic_vector(7 downto 0)) is
begin
wait until clock='1';
addr <= a;
ren <= '1';
wait until clock='1';
wait for 1 ns;
ren <= '0';
d := data_out;
end do_read;
variable start : time;
variable read_data : std_logic_vector(7 downto 0);
constant test_byte : std_logic_vector(7 downto 0) := X"47";
constant test_byte2 : std_logic_vector(7 downto 0) := X"E2";
begin
ca1 <= 'Z';
ca2 <= 'Z';
cb1 <= 'Z';
cb2 <= 'Z';
port_b <= (others => 'Z');
wait until reset='0';
for i in 0 to 15 loop
do_read(conv_std_logic_vector(i, 4), read_data);
end loop;
do_write(X"0", X"55"); -- set data = 55
do_write(X"2", X"33"); -- set direction = 33
do_read (X"0", read_data);
assert read_data = "HH01HH01" report "Data port B seems wrong" severity error;
do_write(X"1", X"99"); -- set data = 99
do_write(X"3", X"AA"); -- set direction = AA
do_read (X"0", read_data);
assert read_data = "1H0H1H0H" report "Data port A seems wrong" severity error;
-- TEST SHIFT REGISTER --
do_write(X"8", X"05"); -- timer 2 latch = 5
do_write(X"E", X"84"); -- enable IRQ on shift register
do_write(X"B", X"04"); -- Shift Control = 1 (shift in on timer 2)
do_write(X"A", X"00"); -- dummy write to SR, to start transfer
for i in 7 downto 0 loop
wait until cb1='0';
cb2 <= test_byte(i);
if i = 7 then
start := now;
end if;
end loop;
wait until cb1='1';
cb2 <= 'Z';
wait until irq='1';
assert integer((now - start)/7 us) = 12 report "Timing error serial mode 1." severity error;
-- report "Receiving byte. Bit time: " & integer'image(integer((now - start)/7 us)) severity note;
do_write(X"B", X"08"); -- Shift Control = 2 (shift in on system clock)
do_read (X"A", read_data); -- check byte from previous transmit
assert read_data = test_byte report "Data byte came in was not correct (mode 1)." severity error;
for i in 7 downto 0 loop
wait until cb1='0';
cb2 <= not test_byte(i);
if i = 7 then
start := now;
end if;
end loop;
wait until cb1='1';
cb2 <= 'Z';
wait until irq='1';
assert integer((now - start)/7 us) = 2 report "Timing error serial mode 2." severity error;
do_write(X"B", X"0C"); -- Shift Control = 3 (shift in under control of cb1)
do_read (X"A", read_data); -- check byte from previous transmitm, trigger new
assert read_data = not test_byte report "Data byte came in was not correct (mode 2)." severity error;
for i in test_byte2'range loop
cb1 <= '0';
wait for 2 us;
cb2 <= test_byte2(i);
wait for 2 us;
cb1 <= '1';
wait for 2 us;
end loop;
cb2 <= 'Z';
cb1 <= 'Z';
do_write(X"B", X"10"); -- Shift Control = 4 (shift out continuously)
do_read (X"A", read_data); -- check byte from previous transmitm, trigger new
assert read_data = test_byte2 report "Data byte came in was not correct (mode 3)." severity error;
wait for 150 us;
assert irq = '0' report "An IRQ was generated, but not expected.";
do_write(X"B", X"00"); -- stop endless loop
do_write(X"8", X"03"); -- timer 2 latch = 3 (8 us per bit)
do_write(X"B", X"14"); -- Shift Control = 5 (shift out on Timer 2)
do_write(X"A", X"55");
for i in 7 downto 0 loop
wait until cb1='1';
read_data(i) := cb2;
end loop;
wait until irq='1';
assert read_data = X"55" report "Data byte sent out was not correct (mode 5)." severity error;
do_write(X"B", X"18"); -- Shift Control = 6 (shift out on system clock)
do_write(X"A", X"81");
for i in 7 downto 0 loop
wait until cb1='1';
read_data(i) := cb2;
end loop;
wait until irq='1';
assert read_data = X"81" report "Data byte sent out was not correct (mode 6)." severity error;
do_write(X"B", X"1c"); -- Shift Control = 7 (shift out on own clock)
do_write(X"A", X"B3");
for i in 7 downto 0 loop
cb1 <= '0';
wait for 2 us;
read_data(i) := cb2;
cb1 <= '1';
wait for 2 us;
end loop;
cb1 <= 'Z';
assert read_data = X"B3" report "Data byte sent out was not correct (mode 7)." severity error;
do_write(X"B", X"00"); -- disable shift register
do_write(X"E", X"7F"); -- clear all interupt enable flags
-- TEST TIMER 1 --
do_write(X"E", X"C0"); -- enable interrupt on Timer 1
-- timer 1 is now in one shot mode, output disabled
do_write(X"4", X"30"); -- Set timer to 0x230
do_write(X"5", X"02"); -- ... and start one shot
start := now;
wait until irq='1';
assert integer((now - start)/ 1 us) = 561 report "Interrupt of timer 1 received. Duration Error." severity error;
do_read (X"4", read_data);
wait until clock='1';
assert irq = '0' report "Expected interrupt to be cleared by reading address 4." severity error;
do_write(X"B", X"40"); -- timer in cont. mode
do_write(X"4", X"20"); -- timer = 0x120
do_write(X"5", X"01"); -- trigger, and go
wait until irq='1';
start := now;
do_read(X"4", read_data);
wait until irq='1';
-- report integer'image(integer((now - start) / 1 us)) severity note;
assert integer((now - start) / 1 us) = 290 report "Timer 1 continuous mode, interrupt distance wrong." severity error;
do_write(X"B", X"80"); -- timer 1 one shot, PB7 enabled
do_write(X"4", X"44"); -- set timer to 0x0044
assert irq = '1' report "Expected IRQ still to be set" severity error;
do_write(X"5", X"00"); -- set timer, clear flag, go!
start := now;
wait until clock='1';
assert irq = '0' report "Expected IRQ to be cleared" severity error;
wait until irq='1';
-- report integer'image(integer((now - start) / 1 us)) severity note;
assert integer((now - start) / 1 us) = 68 report "Timer 1 one shot output mode, interrupt distance wrong." severity error;
do_write(X"B", X"C0"); -- timer 1 continuous, PB7 enabled
do_write(X"4", X"24"); -- set timer to 0x0024
do_write(X"5", X"00"); -- set timer, clear flag, go!
start := now;
wait until irq='1';
assert port_b(7)='1' report "Expected bit 7 of PB to be '1'" severity error;
do_write(X"7", X"00"); -- re-write latch value, reset flag
wait until irq='1';
assert port_b(7)='0' report "Expected bit 7 of PB to be '0'" severity error;
do_read(X"4", read_data); --reset flag
wait until irq='1';
assert port_b(7)='1' report "Expected bit 7 of PB to be '1'" severity error;
do_write(X"B", X"00"); -- timer 1 one shot, output disabled
do_write(X"E", X"7E"); -- clear interrupt enable flags
-- TEST TIMER 2 --
do_write(X"E", X"A0"); -- Set interrupt on timer 2
do_write(X"8", X"33"); -- Set lower latch to 33.
wait for 10 us; -- observe timer to count
wait until clock_en='1';
do_write(X"9", X"02"); -- Set timer to 0x233 and wait for IRQ
start := now;
wait until irq='1';
-- report integer'image(integer((now - start) / 1 us)) severity note;
assert integer((now - start) / 1 us) = 16#233# report "Timer 2 one shot mode, interrupt time wrong." severity error;
do_read(X"8", read_data);
do_write(X"B", X"20"); -- set to pulse count mode
do_write(X"2", X"00"); -- set port B to input
do_write(X"8", X"0A"); -- set to 10 pulses
do_write(X"9", X"00"); -- high byte and trigger
for i in 0 to 10 loop
port_b(6) <= '0';
wait for 5 us;
port_b(6) <= '1';
wait for 1 us;
assert not((i > 9) and (irq = '0')) report "Expected IRQ to be 1 after 10th pulse" severity error;
assert not((i < 10) and (irq = '1')) report "Expected IRQ to be 0 before 10th pulse" severity error;
wait for 15 us;
end loop;
-- TEST CA1 --
do_write(X"C", X"00");
do_write(X"E", X"7F");
do_write(X"E", X"82"); -- interrupt on CA1
wait until clock='1';
-- no transitions have taken place yet on CA1, hence IRQ should be low
assert irq='0' report "Expected CA1 interrupt to be low before any transition." severity error;
ca1 <= '0';
wait for 2 us;
assert irq='1' report "Expected CA1 IRQ to be set after negative transition." severity error;
do_read(X"1", read_data);
wait for 2 us;
assert irq='0' report "Expected CA1 IRQ to be cleared by reading port a." severity error;
do_write(X"C", X"01"); -- CA1 control = '1', expecting rising edge
wait for 2 us;
ca1 <= '1';
wait for 2 us;
assert irq='1' report "Expected CA1 IRQ to be set after positive transition." severity error;
do_write(X"1", X"47");
wait for 2 us;
assert irq='0' report "Expected CA1 IRQ to be cleared by writing port A." severity error;
-- TEST CB1 --
cb1 <= '1';
do_write(X"0", X"11"); -- clear flag
do_write(X"C", X"00");
do_write(X"E", X"7F");
do_write(X"E", X"90"); -- interrupt on CB1
wait until clock='1';
-- no transitions have taken place yet on CB1, hence IRQ should be low
assert irq='0' report "Expected CB1 interrupt to be low before any transition." severity error;
cb1 <= '0';
wait for 2 us;
assert irq='1' report "Expected CB1 IRQ to be set after negative transition." severity error;
do_read(X"0", read_data);
wait for 2 us;
assert irq='0' report "Expected CB1 IRQ to be cleared by reading port B." severity error;
do_write(X"C", X"10"); -- CB1 control = '1', expecting rising edge
wait for 2 us;
cb1 <= '1';
wait for 2 us;
assert irq='1' report "Expected CB1 IRQ to be set after positive transition." severity error;
do_write(X"0", X"47");
wait for 2 us;
assert irq='0' report "Expected CB1 IRQ to be cleared by writing port B." severity error;
-- TEST CA2 --
-- mode 0: input, negative transition, Port A out clears flag
ca2 <= '1';
do_write(X"C", X"00"); -- mode 0
do_write(X"D", X"01"); -- clear flag
do_write(X"E", X"7F"); -- reset all interrupt enables
do_write(X"E", X"81"); -- enable CA2 interrupt
wait for 2 us;
assert irq='0' report "Expected CA2 interrupt to be low before any transition." severity error;
ca2 <= '0';
wait for 2 us;
assert irq='1' report "Expected CA2 IRQ to be set after negative transition." severity error;
do_write(X"1", X"44"); -- write to Port a
wait for 2 us;
assert irq='0' report "Expected CA2 IRQ to be cleared by writing to port A." severity error;
-- mode 2: input, positive transition, Port A in/out clears flag
do_write(X"C", X"04"); -- mode 2
wait for 2 us;
ca2 <= '1';
wait for 2 us;
assert irq='1' report "Expected CA2 IRQ to be set after positive transition." severity error;
do_read(X"1", read_data);
wait for 2 us;
assert irq='0' report "Expected CA2 IRQ to be cleared by reading port A." severity error;
-- mode 1 / 3, read/write to port A does NOT clear the interrupt flag
do_write(X"C", X"02"); -- mode 1
wait for 2 us;
ca2 <= '0';
wait for 2 us;
assert irq='1' report "Expected CA2 IRQ to be set after negative transition (mode 1)." severity error;
do_read(X"1", read_data);
wait for 2 us;
assert irq='1' report "Expected CA2 IRQ to be STILL set after negative transition (mode 1)." severity error;
do_write(X"D", X"01"); -- clear flag manually
do_write(X"C", X"06"); -- mode 3
wait for 2 us;
ca2 <= '1';
wait for 2 us;
assert irq='1' report "Expected CA2 IRQ to be set after positive transition (mode 3)." severity error;
do_read(X"1", read_data);
wait for 2 us;
assert irq='1' report "Expected CA2 IRQ to be STILL set after positive transition (mode 3)." severity error;
do_write(X"D", X"01"); -- clear flag manually
-- mode 4
ca2 <= 'Z';
do_write(X"C", X"08"); -- mode 4
do_write(X"1", X"31"); -- write to Port A
wait for 2 us;
assert ca2 = '0' report "Expected CA2 to have gone low upon writing to Port A (mode 4)." severity error;
ca1 <= '0';
wait for 2 us;
assert ca2 = '1' report "Expected CA2 to have gone high upon active transition on CA1 (mode 4)." severity error;
ca1 <= '1';
wait for 2 us;
-- mode 5
do_write(X"C", X"0A"); -- mode 5
wait until clock_en='1';
do_write(X"1", X"32"); -- write to port A
wait until clock_en='1' and clock='1';
wait for 1 ns;
assert ca2 = '0' report "Expected CA2 to have gone low upon writing to Port A (mode 5)." severity error;
wait until clock_en='1' and clock='1';
wait for 1 ns;
assert ca2 = '1' report "Expected CA2 to have gone high after one cycle (mode 5)." severity error;
-- mode 6
do_write(X"C", X"0C"); -- mode 6
wait for 2 us;
assert ca2 = '0' report "Expected CA2 to be low in mode 6" severity error;
-- mode 7
do_write(X"C", X"0E"); -- mode 7
wait for 2 us;
assert ca2 = '1' report "Expected CA2 to be high in mode 7." severity error;
-- TEST CB2 --
-- mode 0: input, negative transition, Port B out clears flag
cb2 <= '1';
do_write(X"C", X"00"); -- mode 0
do_write(X"D", X"08"); -- clear flag
do_write(X"E", X"7F"); -- reset all interrupt enables
do_write(X"E", X"88"); -- enable CB2 interrupt
wait for 2 us;
assert irq='0' report "Expected CB2 interrupt to be low before any transition." severity error;
cb2 <= '0';
wait for 2 us;
assert irq='1' report "Expected CB2 IRQ to be set after negative transition." severity error;
do_write(X"0", X"44"); -- write to Port B
wait for 2 us;
assert irq='0' report "Expected CB2 IRQ to be cleared by writing to port B." severity error;
-- mode 2: input, positive transition, Port B in/out clears flag
do_write(X"C", X"40"); -- mode 2
wait for 2 us;
cb2 <= '1';
wait for 2 us;
assert irq='1' report "Expected CB2 IRQ to be set after positive transition." severity error;
do_read(X"0", read_data);
wait for 2 us;
assert irq='0' report "Expected CB2 IRQ to be cleared by reading port B." severity error;
-- mode 1 / 3, read/write to port B does NOT clear the interrupt flag
do_write(X"C", X"20"); -- mode 1
wait for 2 us;
cb2 <= '0';
wait for 2 us;
assert irq='1' report "Expected CB2 IRQ to be set after negative transition (mode 1)." severity error;
do_read(X"0", read_data);
wait for 2 us;
assert irq='1' report "Expected CB2 IRQ to be STILL set after negative transition (mode 1)." severity error;
do_write(X"D", X"08"); -- clear flag manually
do_write(X"C", X"60"); -- mode 3
wait for 2 us;
cb2 <= '1';
wait for 2 us;
assert irq='1' report "Expected CB2 IRQ to be set after positive transition (mode 3)." severity error;
do_read(X"0", read_data);
wait for 2 us;
assert irq='1' report "Expected CB2 IRQ to be STILL set after positive transition (mode 3)." severity error;
do_write(X"D", X"08"); -- clear flag manually
-- mode 4
cb2 <= 'Z';
do_write(X"C", X"80"); -- mode 4
do_write(X"0", X"31"); -- write to Port B
wait for 2 us;
assert cb2 = '0' report "Expected CB2 to have gone low upon writing to Port B (mode 4)." severity error;
cb1 <= '0';
wait for 2 us;
assert cb2 = '1' report "Expected CB2 to have gone high upon active transition on CB1 (mode 4)." severity error;
cb1 <= '1';
wait for 2 us;
-- mode 5
do_write(X"C", X"A0"); -- mode 5
wait until clock_en='1';
do_write(X"0", X"32"); -- write to port B
wait until clock_en='1' and clock='1';
wait for 1 ns;
assert cb2 = '0' report "Expected CB2 to have gone low upon writing to Port B (mode 5)." severity error;
wait until clock_en='1' and clock='1';
wait for 1 ns;
assert cb2 = '1' report "Expected CB2 to have gone high after one cycle (mode 5)." severity error;
-- mode 6
do_write(X"C", X"C0"); -- mode 6
wait for 2 us;
assert cb2 = '0' report "Expected CB2 to be low in mode 6" severity error;
-- mode 7
do_write(X"C", X"E0"); -- mode 7
wait for 2 us;
assert cb2 = '1' report "Expected CB2 to be high in mode 7." severity error;
wait;
end process;
end tb;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity tb_via6522 is
end tb_via6522;
architecture tb of tb_via6522 is
signal clock : std_logic := '0';
signal clock_en : std_logic := '0'; -- for counters and stuff
signal reset : std_logic;
signal addr : std_logic_vector(3 downto 0) := X"0";
signal wen : std_logic := '0';
signal ren : std_logic := '0';
signal data_in : std_logic_vector(7 downto 0) := X"00";
signal data_out : std_logic_vector(7 downto 0) := X"00";
signal irq : std_logic;
-- pio --
signal port_a_o : std_logic_vector(7 downto 0);
signal port_a_t : std_logic_vector(7 downto 0);
-- signal port_a_i : std_logic_vector(7 downto 0);
signal port_b_o : std_logic_vector(7 downto 0);
signal port_b_t : std_logic_vector(7 downto 0);
-- signal port_b_i : std_logic_vector(7 downto 0);
-- handshake pins
-- signal ca1_i : std_logic;
signal ca2_o : std_logic;
-- signal ca2_i : std_logic;
signal ca2_t : std_logic;
signal cb1_o : std_logic;
-- signal cb1_i : std_logic;
signal cb1_t : std_logic;
signal cb2_o : std_logic;
-- signal cb2_i : std_logic;
signal cb2_t : std_logic;
signal ca1, ca2 : std_logic;
signal cb1, cb2 : std_logic;
signal port_a : std_logic_vector(7 downto 0);
signal port_b : std_logic_vector(7 downto 0);
begin
port_a <= (others => 'H');
port_b <= (others => 'H');
ca1 <= 'H';
ca2 <= ca2_o when ca2_t='1' else 'H';
cb1 <= cb1_o when cb1_t='1' else 'H';
cb2 <= cb2_o when cb2_t='1' else 'H';
process(port_a_o, port_a_t, port_b_o, port_b_t)
begin
for i in 0 to 7 loop
if port_a_t(i)='1' then
port_a(i) <= port_a_o(i);
else
port_a(i) <= 'H';
end if;
if port_b_t(i)='1' then
port_b(i) <= port_b_o(i);
else
port_b(i) <= 'H';
end if;
end loop;
end process;
via: entity work.via6522
port map (
clock => clock,
clock_en => clock_en, -- for counters and stuff
reset => reset,
addr => addr,
wen => wen,
ren => ren,
data_in => data_in,
data_out => data_out,
-- pio --
port_a_o => port_a_o,
port_a_t => port_a_t,
port_a_i => port_a,
port_b_o => port_b_o,
port_b_t => port_b_t,
port_b_i => port_b,
-- handshake pins
ca1_i => ca1,
ca2_o => ca2_o,
ca2_i => ca2,
ca2_t => ca2_t,
cb1_o => cb1_o,
cb1_i => cb1,
cb1_t => cb1_t,
cb2_o => cb2_o,
cb2_i => cb2,
cb2_t => cb2_t,
irq => irq );
clock <= not clock after 125 ns;
reset <= '1', '0' after 2 us;
ce: process
begin
clock_en <= '0';
wait until clock='1';
wait until clock='1';
wait until clock='1';
clock_en <= '1';
wait until clock='1';
end process;
test: process
procedure do_write(a: std_logic_vector(3 downto 0); d: std_logic_vector(7 downto 0)) is
begin
wait until clock='1';
addr <= a;
data_in <= d;
wen <= '1';
wait until clock='1';
wen <= '0';
end do_write;
procedure do_read(a: std_logic_vector(3 downto 0); d: out std_logic_vector(7 downto 0)) is
begin
wait until clock='1';
addr <= a;
ren <= '1';
wait until clock='1';
wait for 1 ns;
ren <= '0';
d := data_out;
end do_read;
variable start : time;
variable read_data : std_logic_vector(7 downto 0);
constant test_byte : std_logic_vector(7 downto 0) := X"47";
constant test_byte2 : std_logic_vector(7 downto 0) := X"E2";
begin
ca1 <= 'Z';
ca2 <= 'Z';
cb1 <= 'Z';
cb2 <= 'Z';
port_b <= (others => 'Z');
wait until reset='0';
for i in 0 to 15 loop
do_read(conv_std_logic_vector(i, 4), read_data);
end loop;
do_write(X"0", X"55"); -- set data = 55
do_write(X"2", X"33"); -- set direction = 33
do_read (X"0", read_data);
assert read_data = "HH01HH01" report "Data port B seems wrong" severity error;
do_write(X"1", X"99"); -- set data = 99
do_write(X"3", X"AA"); -- set direction = AA
do_read (X"0", read_data);
assert read_data = "1H0H1H0H" report "Data port A seems wrong" severity error;
-- TEST SHIFT REGISTER --
do_write(X"8", X"05"); -- timer 2 latch = 5
do_write(X"E", X"84"); -- enable IRQ on shift register
do_write(X"B", X"04"); -- Shift Control = 1 (shift in on timer 2)
do_write(X"A", X"00"); -- dummy write to SR, to start transfer
for i in 7 downto 0 loop
wait until cb1='0';
cb2 <= test_byte(i);
if i = 7 then
start := now;
end if;
end loop;
wait until cb1='1';
cb2 <= 'Z';
wait until irq='1';
assert integer((now - start)/7 us) = 12 report "Timing error serial mode 1." severity error;
-- report "Receiving byte. Bit time: " & integer'image(integer((now - start)/7 us)) severity note;
do_write(X"B", X"08"); -- Shift Control = 2 (shift in on system clock)
do_read (X"A", read_data); -- check byte from previous transmit
assert read_data = test_byte report "Data byte came in was not correct (mode 1)." severity error;
for i in 7 downto 0 loop
wait until cb1='0';
cb2 <= not test_byte(i);
if i = 7 then
start := now;
end if;
end loop;
wait until cb1='1';
cb2 <= 'Z';
wait until irq='1';
assert integer((now - start)/7 us) = 2 report "Timing error serial mode 2." severity error;
do_write(X"B", X"0C"); -- Shift Control = 3 (shift in under control of cb1)
do_read (X"A", read_data); -- check byte from previous transmitm, trigger new
assert read_data = not test_byte report "Data byte came in was not correct (mode 2)." severity error;
for i in test_byte2'range loop
cb1 <= '0';
wait for 2 us;
cb2 <= test_byte2(i);
wait for 2 us;
cb1 <= '1';
wait for 2 us;
end loop;
cb2 <= 'Z';
cb1 <= 'Z';
do_write(X"B", X"10"); -- Shift Control = 4 (shift out continuously)
do_read (X"A", read_data); -- check byte from previous transmitm, trigger new
assert read_data = test_byte2 report "Data byte came in was not correct (mode 3)." severity error;
wait for 150 us;
assert irq = '0' report "An IRQ was generated, but not expected.";
do_write(X"B", X"00"); -- stop endless loop
do_write(X"8", X"03"); -- timer 2 latch = 3 (8 us per bit)
do_write(X"B", X"14"); -- Shift Control = 5 (shift out on Timer 2)
do_write(X"A", X"55");
for i in 7 downto 0 loop
wait until cb1='1';
read_data(i) := cb2;
end loop;
wait until irq='1';
assert read_data = X"55" report "Data byte sent out was not correct (mode 5)." severity error;
do_write(X"B", X"18"); -- Shift Control = 6 (shift out on system clock)
do_write(X"A", X"81");
for i in 7 downto 0 loop
wait until cb1='1';
read_data(i) := cb2;
end loop;
wait until irq='1';
assert read_data = X"81" report "Data byte sent out was not correct (mode 6)." severity error;
do_write(X"B", X"1c"); -- Shift Control = 7 (shift out on own clock)
do_write(X"A", X"B3");
for i in 7 downto 0 loop
cb1 <= '0';
wait for 2 us;
read_data(i) := cb2;
cb1 <= '1';
wait for 2 us;
end loop;
cb1 <= 'Z';
assert read_data = X"B3" report "Data byte sent out was not correct (mode 7)." severity error;
do_write(X"B", X"00"); -- disable shift register
do_write(X"E", X"7F"); -- clear all interupt enable flags
-- TEST TIMER 1 --
do_write(X"E", X"C0"); -- enable interrupt on Timer 1
-- timer 1 is now in one shot mode, output disabled
do_write(X"4", X"30"); -- Set timer to 0x230
do_write(X"5", X"02"); -- ... and start one shot
start := now;
wait until irq='1';
assert integer((now - start)/ 1 us) = 561 report "Interrupt of timer 1 received. Duration Error." severity error;
do_read (X"4", read_data);
wait until clock='1';
assert irq = '0' report "Expected interrupt to be cleared by reading address 4." severity error;
do_write(X"B", X"40"); -- timer in cont. mode
do_write(X"4", X"20"); -- timer = 0x120
do_write(X"5", X"01"); -- trigger, and go
wait until irq='1';
start := now;
do_read(X"4", read_data);
wait until irq='1';
-- report integer'image(integer((now - start) / 1 us)) severity note;
assert integer((now - start) / 1 us) = 290 report "Timer 1 continuous mode, interrupt distance wrong." severity error;
do_write(X"B", X"80"); -- timer 1 one shot, PB7 enabled
do_write(X"4", X"44"); -- set timer to 0x0044
assert irq = '1' report "Expected IRQ still to be set" severity error;
do_write(X"5", X"00"); -- set timer, clear flag, go!
start := now;
wait until clock='1';
assert irq = '0' report "Expected IRQ to be cleared" severity error;
wait until irq='1';
-- report integer'image(integer((now - start) / 1 us)) severity note;
assert integer((now - start) / 1 us) = 68 report "Timer 1 one shot output mode, interrupt distance wrong." severity error;
do_write(X"B", X"C0"); -- timer 1 continuous, PB7 enabled
do_write(X"4", X"24"); -- set timer to 0x0024
do_write(X"5", X"00"); -- set timer, clear flag, go!
start := now;
wait until irq='1';
assert port_b(7)='1' report "Expected bit 7 of PB to be '1'" severity error;
do_write(X"7", X"00"); -- re-write latch value, reset flag
wait until irq='1';
assert port_b(7)='0' report "Expected bit 7 of PB to be '0'" severity error;
do_read(X"4", read_data); --reset flag
wait until irq='1';
assert port_b(7)='1' report "Expected bit 7 of PB to be '1'" severity error;
do_write(X"B", X"00"); -- timer 1 one shot, output disabled
do_write(X"E", X"7E"); -- clear interrupt enable flags
-- TEST TIMER 2 --
do_write(X"E", X"A0"); -- Set interrupt on timer 2
do_write(X"8", X"33"); -- Set lower latch to 33.
wait for 10 us; -- observe timer to count
wait until clock_en='1';
do_write(X"9", X"02"); -- Set timer to 0x233 and wait for IRQ
start := now;
wait until irq='1';
-- report integer'image(integer((now - start) / 1 us)) severity note;
assert integer((now - start) / 1 us) = 16#233# report "Timer 2 one shot mode, interrupt time wrong." severity error;
do_read(X"8", read_data);
do_write(X"B", X"20"); -- set to pulse count mode
do_write(X"2", X"00"); -- set port B to input
do_write(X"8", X"0A"); -- set to 10 pulses
do_write(X"9", X"00"); -- high byte and trigger
for i in 0 to 10 loop
port_b(6) <= '0';
wait for 5 us;
port_b(6) <= '1';
wait for 1 us;
assert not((i > 9) and (irq = '0')) report "Expected IRQ to be 1 after 10th pulse" severity error;
assert not((i < 10) and (irq = '1')) report "Expected IRQ to be 0 before 10th pulse" severity error;
wait for 15 us;
end loop;
-- TEST CA1 --
do_write(X"C", X"00");
do_write(X"E", X"7F");
do_write(X"E", X"82"); -- interrupt on CA1
wait until clock='1';
-- no transitions have taken place yet on CA1, hence IRQ should be low
assert irq='0' report "Expected CA1 interrupt to be low before any transition." severity error;
ca1 <= '0';
wait for 2 us;
assert irq='1' report "Expected CA1 IRQ to be set after negative transition." severity error;
do_read(X"1", read_data);
wait for 2 us;
assert irq='0' report "Expected CA1 IRQ to be cleared by reading port a." severity error;
do_write(X"C", X"01"); -- CA1 control = '1', expecting rising edge
wait for 2 us;
ca1 <= '1';
wait for 2 us;
assert irq='1' report "Expected CA1 IRQ to be set after positive transition." severity error;
do_write(X"1", X"47");
wait for 2 us;
assert irq='0' report "Expected CA1 IRQ to be cleared by writing port A." severity error;
-- TEST CB1 --
cb1 <= '1';
do_write(X"0", X"11"); -- clear flag
do_write(X"C", X"00");
do_write(X"E", X"7F");
do_write(X"E", X"90"); -- interrupt on CB1
wait until clock='1';
-- no transitions have taken place yet on CB1, hence IRQ should be low
assert irq='0' report "Expected CB1 interrupt to be low before any transition." severity error;
cb1 <= '0';
wait for 2 us;
assert irq='1' report "Expected CB1 IRQ to be set after negative transition." severity error;
do_read(X"0", read_data);
wait for 2 us;
assert irq='0' report "Expected CB1 IRQ to be cleared by reading port B." severity error;
do_write(X"C", X"10"); -- CB1 control = '1', expecting rising edge
wait for 2 us;
cb1 <= '1';
wait for 2 us;
assert irq='1' report "Expected CB1 IRQ to be set after positive transition." severity error;
do_write(X"0", X"47");
wait for 2 us;
assert irq='0' report "Expected CB1 IRQ to be cleared by writing port B." severity error;
-- TEST CA2 --
-- mode 0: input, negative transition, Port A out clears flag
ca2 <= '1';
do_write(X"C", X"00"); -- mode 0
do_write(X"D", X"01"); -- clear flag
do_write(X"E", X"7F"); -- reset all interrupt enables
do_write(X"E", X"81"); -- enable CA2 interrupt
wait for 2 us;
assert irq='0' report "Expected CA2 interrupt to be low before any transition." severity error;
ca2 <= '0';
wait for 2 us;
assert irq='1' report "Expected CA2 IRQ to be set after negative transition." severity error;
do_write(X"1", X"44"); -- write to Port a
wait for 2 us;
assert irq='0' report "Expected CA2 IRQ to be cleared by writing to port A." severity error;
-- mode 2: input, positive transition, Port A in/out clears flag
do_write(X"C", X"04"); -- mode 2
wait for 2 us;
ca2 <= '1';
wait for 2 us;
assert irq='1' report "Expected CA2 IRQ to be set after positive transition." severity error;
do_read(X"1", read_data);
wait for 2 us;
assert irq='0' report "Expected CA2 IRQ to be cleared by reading port A." severity error;
-- mode 1 / 3, read/write to port A does NOT clear the interrupt flag
do_write(X"C", X"02"); -- mode 1
wait for 2 us;
ca2 <= '0';
wait for 2 us;
assert irq='1' report "Expected CA2 IRQ to be set after negative transition (mode 1)." severity error;
do_read(X"1", read_data);
wait for 2 us;
assert irq='1' report "Expected CA2 IRQ to be STILL set after negative transition (mode 1)." severity error;
do_write(X"D", X"01"); -- clear flag manually
do_write(X"C", X"06"); -- mode 3
wait for 2 us;
ca2 <= '1';
wait for 2 us;
assert irq='1' report "Expected CA2 IRQ to be set after positive transition (mode 3)." severity error;
do_read(X"1", read_data);
wait for 2 us;
assert irq='1' report "Expected CA2 IRQ to be STILL set after positive transition (mode 3)." severity error;
do_write(X"D", X"01"); -- clear flag manually
-- mode 4
ca2 <= 'Z';
do_write(X"C", X"08"); -- mode 4
do_write(X"1", X"31"); -- write to Port A
wait for 2 us;
assert ca2 = '0' report "Expected CA2 to have gone low upon writing to Port A (mode 4)." severity error;
ca1 <= '0';
wait for 2 us;
assert ca2 = '1' report "Expected CA2 to have gone high upon active transition on CA1 (mode 4)." severity error;
ca1 <= '1';
wait for 2 us;
-- mode 5
do_write(X"C", X"0A"); -- mode 5
wait until clock_en='1';
do_write(X"1", X"32"); -- write to port A
wait until clock_en='1' and clock='1';
wait for 1 ns;
assert ca2 = '0' report "Expected CA2 to have gone low upon writing to Port A (mode 5)." severity error;
wait until clock_en='1' and clock='1';
wait for 1 ns;
assert ca2 = '1' report "Expected CA2 to have gone high after one cycle (mode 5)." severity error;
-- mode 6
do_write(X"C", X"0C"); -- mode 6
wait for 2 us;
assert ca2 = '0' report "Expected CA2 to be low in mode 6" severity error;
-- mode 7
do_write(X"C", X"0E"); -- mode 7
wait for 2 us;
assert ca2 = '1' report "Expected CA2 to be high in mode 7." severity error;
-- TEST CB2 --
-- mode 0: input, negative transition, Port B out clears flag
cb2 <= '1';
do_write(X"C", X"00"); -- mode 0
do_write(X"D", X"08"); -- clear flag
do_write(X"E", X"7F"); -- reset all interrupt enables
do_write(X"E", X"88"); -- enable CB2 interrupt
wait for 2 us;
assert irq='0' report "Expected CB2 interrupt to be low before any transition." severity error;
cb2 <= '0';
wait for 2 us;
assert irq='1' report "Expected CB2 IRQ to be set after negative transition." severity error;
do_write(X"0", X"44"); -- write to Port B
wait for 2 us;
assert irq='0' report "Expected CB2 IRQ to be cleared by writing to port B." severity error;
-- mode 2: input, positive transition, Port B in/out clears flag
do_write(X"C", X"40"); -- mode 2
wait for 2 us;
cb2 <= '1';
wait for 2 us;
assert irq='1' report "Expected CB2 IRQ to be set after positive transition." severity error;
do_read(X"0", read_data);
wait for 2 us;
assert irq='0' report "Expected CB2 IRQ to be cleared by reading port B." severity error;
-- mode 1 / 3, read/write to port B does NOT clear the interrupt flag
do_write(X"C", X"20"); -- mode 1
wait for 2 us;
cb2 <= '0';
wait for 2 us;
assert irq='1' report "Expected CB2 IRQ to be set after negative transition (mode 1)." severity error;
do_read(X"0", read_data);
wait for 2 us;
assert irq='1' report "Expected CB2 IRQ to be STILL set after negative transition (mode 1)." severity error;
do_write(X"D", X"08"); -- clear flag manually
do_write(X"C", X"60"); -- mode 3
wait for 2 us;
cb2 <= '1';
wait for 2 us;
assert irq='1' report "Expected CB2 IRQ to be set after positive transition (mode 3)." severity error;
do_read(X"0", read_data);
wait for 2 us;
assert irq='1' report "Expected CB2 IRQ to be STILL set after positive transition (mode 3)." severity error;
do_write(X"D", X"08"); -- clear flag manually
-- mode 4
cb2 <= 'Z';
do_write(X"C", X"80"); -- mode 4
do_write(X"0", X"31"); -- write to Port B
wait for 2 us;
assert cb2 = '0' report "Expected CB2 to have gone low upon writing to Port B (mode 4)." severity error;
cb1 <= '0';
wait for 2 us;
assert cb2 = '1' report "Expected CB2 to have gone high upon active transition on CB1 (mode 4)." severity error;
cb1 <= '1';
wait for 2 us;
-- mode 5
do_write(X"C", X"A0"); -- mode 5
wait until clock_en='1';
do_write(X"0", X"32"); -- write to port B
wait until clock_en='1' and clock='1';
wait for 1 ns;
assert cb2 = '0' report "Expected CB2 to have gone low upon writing to Port B (mode 5)." severity error;
wait until clock_en='1' and clock='1';
wait for 1 ns;
assert cb2 = '1' report "Expected CB2 to have gone high after one cycle (mode 5)." severity error;
-- mode 6
do_write(X"C", X"C0"); -- mode 6
wait for 2 us;
assert cb2 = '0' report "Expected CB2 to be low in mode 6" severity error;
-- mode 7
do_write(X"C", X"E0"); -- mode 7
wait for 2 us;
assert cb2 = '1' report "Expected CB2 to be high in mode 7." severity error;
wait;
end process;
end tb;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity tb_via6522 is
end tb_via6522;
architecture tb of tb_via6522 is
signal clock : std_logic := '0';
signal clock_en : std_logic := '0'; -- for counters and stuff
signal reset : std_logic;
signal addr : std_logic_vector(3 downto 0) := X"0";
signal wen : std_logic := '0';
signal ren : std_logic := '0';
signal data_in : std_logic_vector(7 downto 0) := X"00";
signal data_out : std_logic_vector(7 downto 0) := X"00";
signal irq : std_logic;
-- pio --
signal port_a_o : std_logic_vector(7 downto 0);
signal port_a_t : std_logic_vector(7 downto 0);
-- signal port_a_i : std_logic_vector(7 downto 0);
signal port_b_o : std_logic_vector(7 downto 0);
signal port_b_t : std_logic_vector(7 downto 0);
-- signal port_b_i : std_logic_vector(7 downto 0);
-- handshake pins
-- signal ca1_i : std_logic;
signal ca2_o : std_logic;
-- signal ca2_i : std_logic;
signal ca2_t : std_logic;
signal cb1_o : std_logic;
-- signal cb1_i : std_logic;
signal cb1_t : std_logic;
signal cb2_o : std_logic;
-- signal cb2_i : std_logic;
signal cb2_t : std_logic;
signal ca1, ca2 : std_logic;
signal cb1, cb2 : std_logic;
signal port_a : std_logic_vector(7 downto 0);
signal port_b : std_logic_vector(7 downto 0);
begin
port_a <= (others => 'H');
port_b <= (others => 'H');
ca1 <= 'H';
ca2 <= ca2_o when ca2_t='1' else 'H';
cb1 <= cb1_o when cb1_t='1' else 'H';
cb2 <= cb2_o when cb2_t='1' else 'H';
process(port_a_o, port_a_t, port_b_o, port_b_t)
begin
for i in 0 to 7 loop
if port_a_t(i)='1' then
port_a(i) <= port_a_o(i);
else
port_a(i) <= 'H';
end if;
if port_b_t(i)='1' then
port_b(i) <= port_b_o(i);
else
port_b(i) <= 'H';
end if;
end loop;
end process;
via: entity work.via6522
port map (
clock => clock,
clock_en => clock_en, -- for counters and stuff
reset => reset,
addr => addr,
wen => wen,
ren => ren,
data_in => data_in,
data_out => data_out,
-- pio --
port_a_o => port_a_o,
port_a_t => port_a_t,
port_a_i => port_a,
port_b_o => port_b_o,
port_b_t => port_b_t,
port_b_i => port_b,
-- handshake pins
ca1_i => ca1,
ca2_o => ca2_o,
ca2_i => ca2,
ca2_t => ca2_t,
cb1_o => cb1_o,
cb1_i => cb1,
cb1_t => cb1_t,
cb2_o => cb2_o,
cb2_i => cb2,
cb2_t => cb2_t,
irq => irq );
clock <= not clock after 125 ns;
reset <= '1', '0' after 2 us;
ce: process
begin
clock_en <= '0';
wait until clock='1';
wait until clock='1';
wait until clock='1';
clock_en <= '1';
wait until clock='1';
end process;
test: process
procedure do_write(a: std_logic_vector(3 downto 0); d: std_logic_vector(7 downto 0)) is
begin
wait until clock='1';
addr <= a;
data_in <= d;
wen <= '1';
wait until clock='1';
wen <= '0';
end do_write;
procedure do_read(a: std_logic_vector(3 downto 0); d: out std_logic_vector(7 downto 0)) is
begin
wait until clock='1';
addr <= a;
ren <= '1';
wait until clock='1';
wait for 1 ns;
ren <= '0';
d := data_out;
end do_read;
variable start : time;
variable read_data : std_logic_vector(7 downto 0);
constant test_byte : std_logic_vector(7 downto 0) := X"47";
constant test_byte2 : std_logic_vector(7 downto 0) := X"E2";
begin
ca1 <= 'Z';
ca2 <= 'Z';
cb1 <= 'Z';
cb2 <= 'Z';
port_b <= (others => 'Z');
wait until reset='0';
for i in 0 to 15 loop
do_read(conv_std_logic_vector(i, 4), read_data);
end loop;
do_write(X"0", X"55"); -- set data = 55
do_write(X"2", X"33"); -- set direction = 33
do_read (X"0", read_data);
assert read_data = "HH01HH01" report "Data port B seems wrong" severity error;
do_write(X"1", X"99"); -- set data = 99
do_write(X"3", X"AA"); -- set direction = AA
do_read (X"0", read_data);
assert read_data = "1H0H1H0H" report "Data port A seems wrong" severity error;
-- TEST SHIFT REGISTER --
do_write(X"8", X"05"); -- timer 2 latch = 5
do_write(X"E", X"84"); -- enable IRQ on shift register
do_write(X"B", X"04"); -- Shift Control = 1 (shift in on timer 2)
do_write(X"A", X"00"); -- dummy write to SR, to start transfer
for i in 7 downto 0 loop
wait until cb1='0';
cb2 <= test_byte(i);
if i = 7 then
start := now;
end if;
end loop;
wait until cb1='1';
cb2 <= 'Z';
wait until irq='1';
assert integer((now - start)/7 us) = 12 report "Timing error serial mode 1." severity error;
-- report "Receiving byte. Bit time: " & integer'image(integer((now - start)/7 us)) severity note;
do_write(X"B", X"08"); -- Shift Control = 2 (shift in on system clock)
do_read (X"A", read_data); -- check byte from previous transmit
assert read_data = test_byte report "Data byte came in was not correct (mode 1)." severity error;
for i in 7 downto 0 loop
wait until cb1='0';
cb2 <= not test_byte(i);
if i = 7 then
start := now;
end if;
end loop;
wait until cb1='1';
cb2 <= 'Z';
wait until irq='1';
assert integer((now - start)/7 us) = 2 report "Timing error serial mode 2." severity error;
do_write(X"B", X"0C"); -- Shift Control = 3 (shift in under control of cb1)
do_read (X"A", read_data); -- check byte from previous transmitm, trigger new
assert read_data = not test_byte report "Data byte came in was not correct (mode 2)." severity error;
for i in test_byte2'range loop
cb1 <= '0';
wait for 2 us;
cb2 <= test_byte2(i);
wait for 2 us;
cb1 <= '1';
wait for 2 us;
end loop;
cb2 <= 'Z';
cb1 <= 'Z';
do_write(X"B", X"10"); -- Shift Control = 4 (shift out continuously)
do_read (X"A", read_data); -- check byte from previous transmitm, trigger new
assert read_data = test_byte2 report "Data byte came in was not correct (mode 3)." severity error;
wait for 150 us;
assert irq = '0' report "An IRQ was generated, but not expected.";
do_write(X"B", X"00"); -- stop endless loop
do_write(X"8", X"03"); -- timer 2 latch = 3 (8 us per bit)
do_write(X"B", X"14"); -- Shift Control = 5 (shift out on Timer 2)
do_write(X"A", X"55");
for i in 7 downto 0 loop
wait until cb1='1';
read_data(i) := cb2;
end loop;
wait until irq='1';
assert read_data = X"55" report "Data byte sent out was not correct (mode 5)." severity error;
do_write(X"B", X"18"); -- Shift Control = 6 (shift out on system clock)
do_write(X"A", X"81");
for i in 7 downto 0 loop
wait until cb1='1';
read_data(i) := cb2;
end loop;
wait until irq='1';
assert read_data = X"81" report "Data byte sent out was not correct (mode 6)." severity error;
do_write(X"B", X"1c"); -- Shift Control = 7 (shift out on own clock)
do_write(X"A", X"B3");
for i in 7 downto 0 loop
cb1 <= '0';
wait for 2 us;
read_data(i) := cb2;
cb1 <= '1';
wait for 2 us;
end loop;
cb1 <= 'Z';
assert read_data = X"B3" report "Data byte sent out was not correct (mode 7)." severity error;
do_write(X"B", X"00"); -- disable shift register
do_write(X"E", X"7F"); -- clear all interupt enable flags
-- TEST TIMER 1 --
do_write(X"E", X"C0"); -- enable interrupt on Timer 1
-- timer 1 is now in one shot mode, output disabled
do_write(X"4", X"30"); -- Set timer to 0x230
do_write(X"5", X"02"); -- ... and start one shot
start := now;
wait until irq='1';
assert integer((now - start)/ 1 us) = 561 report "Interrupt of timer 1 received. Duration Error." severity error;
do_read (X"4", read_data);
wait until clock='1';
assert irq = '0' report "Expected interrupt to be cleared by reading address 4." severity error;
do_write(X"B", X"40"); -- timer in cont. mode
do_write(X"4", X"20"); -- timer = 0x120
do_write(X"5", X"01"); -- trigger, and go
wait until irq='1';
start := now;
do_read(X"4", read_data);
wait until irq='1';
-- report integer'image(integer((now - start) / 1 us)) severity note;
assert integer((now - start) / 1 us) = 290 report "Timer 1 continuous mode, interrupt distance wrong." severity error;
do_write(X"B", X"80"); -- timer 1 one shot, PB7 enabled
do_write(X"4", X"44"); -- set timer to 0x0044
assert irq = '1' report "Expected IRQ still to be set" severity error;
do_write(X"5", X"00"); -- set timer, clear flag, go!
start := now;
wait until clock='1';
assert irq = '0' report "Expected IRQ to be cleared" severity error;
wait until irq='1';
-- report integer'image(integer((now - start) / 1 us)) severity note;
assert integer((now - start) / 1 us) = 68 report "Timer 1 one shot output mode, interrupt distance wrong." severity error;
do_write(X"B", X"C0"); -- timer 1 continuous, PB7 enabled
do_write(X"4", X"24"); -- set timer to 0x0024
do_write(X"5", X"00"); -- set timer, clear flag, go!
start := now;
wait until irq='1';
assert port_b(7)='1' report "Expected bit 7 of PB to be '1'" severity error;
do_write(X"7", X"00"); -- re-write latch value, reset flag
wait until irq='1';
assert port_b(7)='0' report "Expected bit 7 of PB to be '0'" severity error;
do_read(X"4", read_data); --reset flag
wait until irq='1';
assert port_b(7)='1' report "Expected bit 7 of PB to be '1'" severity error;
do_write(X"B", X"00"); -- timer 1 one shot, output disabled
do_write(X"E", X"7E"); -- clear interrupt enable flags
-- TEST TIMER 2 --
do_write(X"E", X"A0"); -- Set interrupt on timer 2
do_write(X"8", X"33"); -- Set lower latch to 33.
wait for 10 us; -- observe timer to count
wait until clock_en='1';
do_write(X"9", X"02"); -- Set timer to 0x233 and wait for IRQ
start := now;
wait until irq='1';
-- report integer'image(integer((now - start) / 1 us)) severity note;
assert integer((now - start) / 1 us) = 16#233# report "Timer 2 one shot mode, interrupt time wrong." severity error;
do_read(X"8", read_data);
do_write(X"B", X"20"); -- set to pulse count mode
do_write(X"2", X"00"); -- set port B to input
do_write(X"8", X"0A"); -- set to 10 pulses
do_write(X"9", X"00"); -- high byte and trigger
for i in 0 to 10 loop
port_b(6) <= '0';
wait for 5 us;
port_b(6) <= '1';
wait for 1 us;
assert not((i > 9) and (irq = '0')) report "Expected IRQ to be 1 after 10th pulse" severity error;
assert not((i < 10) and (irq = '1')) report "Expected IRQ to be 0 before 10th pulse" severity error;
wait for 15 us;
end loop;
-- TEST CA1 --
do_write(X"C", X"00");
do_write(X"E", X"7F");
do_write(X"E", X"82"); -- interrupt on CA1
wait until clock='1';
-- no transitions have taken place yet on CA1, hence IRQ should be low
assert irq='0' report "Expected CA1 interrupt to be low before any transition." severity error;
ca1 <= '0';
wait for 2 us;
assert irq='1' report "Expected CA1 IRQ to be set after negative transition." severity error;
do_read(X"1", read_data);
wait for 2 us;
assert irq='0' report "Expected CA1 IRQ to be cleared by reading port a." severity error;
do_write(X"C", X"01"); -- CA1 control = '1', expecting rising edge
wait for 2 us;
ca1 <= '1';
wait for 2 us;
assert irq='1' report "Expected CA1 IRQ to be set after positive transition." severity error;
do_write(X"1", X"47");
wait for 2 us;
assert irq='0' report "Expected CA1 IRQ to be cleared by writing port A." severity error;
-- TEST CB1 --
cb1 <= '1';
do_write(X"0", X"11"); -- clear flag
do_write(X"C", X"00");
do_write(X"E", X"7F");
do_write(X"E", X"90"); -- interrupt on CB1
wait until clock='1';
-- no transitions have taken place yet on CB1, hence IRQ should be low
assert irq='0' report "Expected CB1 interrupt to be low before any transition." severity error;
cb1 <= '0';
wait for 2 us;
assert irq='1' report "Expected CB1 IRQ to be set after negative transition." severity error;
do_read(X"0", read_data);
wait for 2 us;
assert irq='0' report "Expected CB1 IRQ to be cleared by reading port B." severity error;
do_write(X"C", X"10"); -- CB1 control = '1', expecting rising edge
wait for 2 us;
cb1 <= '1';
wait for 2 us;
assert irq='1' report "Expected CB1 IRQ to be set after positive transition." severity error;
do_write(X"0", X"47");
wait for 2 us;
assert irq='0' report "Expected CB1 IRQ to be cleared by writing port B." severity error;
-- TEST CA2 --
-- mode 0: input, negative transition, Port A out clears flag
ca2 <= '1';
do_write(X"C", X"00"); -- mode 0
do_write(X"D", X"01"); -- clear flag
do_write(X"E", X"7F"); -- reset all interrupt enables
do_write(X"E", X"81"); -- enable CA2 interrupt
wait for 2 us;
assert irq='0' report "Expected CA2 interrupt to be low before any transition." severity error;
ca2 <= '0';
wait for 2 us;
assert irq='1' report "Expected CA2 IRQ to be set after negative transition." severity error;
do_write(X"1", X"44"); -- write to Port a
wait for 2 us;
assert irq='0' report "Expected CA2 IRQ to be cleared by writing to port A." severity error;
-- mode 2: input, positive transition, Port A in/out clears flag
do_write(X"C", X"04"); -- mode 2
wait for 2 us;
ca2 <= '1';
wait for 2 us;
assert irq='1' report "Expected CA2 IRQ to be set after positive transition." severity error;
do_read(X"1", read_data);
wait for 2 us;
assert irq='0' report "Expected CA2 IRQ to be cleared by reading port A." severity error;
-- mode 1 / 3, read/write to port A does NOT clear the interrupt flag
do_write(X"C", X"02"); -- mode 1
wait for 2 us;
ca2 <= '0';
wait for 2 us;
assert irq='1' report "Expected CA2 IRQ to be set after negative transition (mode 1)." severity error;
do_read(X"1", read_data);
wait for 2 us;
assert irq='1' report "Expected CA2 IRQ to be STILL set after negative transition (mode 1)." severity error;
do_write(X"D", X"01"); -- clear flag manually
do_write(X"C", X"06"); -- mode 3
wait for 2 us;
ca2 <= '1';
wait for 2 us;
assert irq='1' report "Expected CA2 IRQ to be set after positive transition (mode 3)." severity error;
do_read(X"1", read_data);
wait for 2 us;
assert irq='1' report "Expected CA2 IRQ to be STILL set after positive transition (mode 3)." severity error;
do_write(X"D", X"01"); -- clear flag manually
-- mode 4
ca2 <= 'Z';
do_write(X"C", X"08"); -- mode 4
do_write(X"1", X"31"); -- write to Port A
wait for 2 us;
assert ca2 = '0' report "Expected CA2 to have gone low upon writing to Port A (mode 4)." severity error;
ca1 <= '0';
wait for 2 us;
assert ca2 = '1' report "Expected CA2 to have gone high upon active transition on CA1 (mode 4)." severity error;
ca1 <= '1';
wait for 2 us;
-- mode 5
do_write(X"C", X"0A"); -- mode 5
wait until clock_en='1';
do_write(X"1", X"32"); -- write to port A
wait until clock_en='1' and clock='1';
wait for 1 ns;
assert ca2 = '0' report "Expected CA2 to have gone low upon writing to Port A (mode 5)." severity error;
wait until clock_en='1' and clock='1';
wait for 1 ns;
assert ca2 = '1' report "Expected CA2 to have gone high after one cycle (mode 5)." severity error;
-- mode 6
do_write(X"C", X"0C"); -- mode 6
wait for 2 us;
assert ca2 = '0' report "Expected CA2 to be low in mode 6" severity error;
-- mode 7
do_write(X"C", X"0E"); -- mode 7
wait for 2 us;
assert ca2 = '1' report "Expected CA2 to be high in mode 7." severity error;
-- TEST CB2 --
-- mode 0: input, negative transition, Port B out clears flag
cb2 <= '1';
do_write(X"C", X"00"); -- mode 0
do_write(X"D", X"08"); -- clear flag
do_write(X"E", X"7F"); -- reset all interrupt enables
do_write(X"E", X"88"); -- enable CB2 interrupt
wait for 2 us;
assert irq='0' report "Expected CB2 interrupt to be low before any transition." severity error;
cb2 <= '0';
wait for 2 us;
assert irq='1' report "Expected CB2 IRQ to be set after negative transition." severity error;
do_write(X"0", X"44"); -- write to Port B
wait for 2 us;
assert irq='0' report "Expected CB2 IRQ to be cleared by writing to port B." severity error;
-- mode 2: input, positive transition, Port B in/out clears flag
do_write(X"C", X"40"); -- mode 2
wait for 2 us;
cb2 <= '1';
wait for 2 us;
assert irq='1' report "Expected CB2 IRQ to be set after positive transition." severity error;
do_read(X"0", read_data);
wait for 2 us;
assert irq='0' report "Expected CB2 IRQ to be cleared by reading port B." severity error;
-- mode 1 / 3, read/write to port B does NOT clear the interrupt flag
do_write(X"C", X"20"); -- mode 1
wait for 2 us;
cb2 <= '0';
wait for 2 us;
assert irq='1' report "Expected CB2 IRQ to be set after negative transition (mode 1)." severity error;
do_read(X"0", read_data);
wait for 2 us;
assert irq='1' report "Expected CB2 IRQ to be STILL set after negative transition (mode 1)." severity error;
do_write(X"D", X"08"); -- clear flag manually
do_write(X"C", X"60"); -- mode 3
wait for 2 us;
cb2 <= '1';
wait for 2 us;
assert irq='1' report "Expected CB2 IRQ to be set after positive transition (mode 3)." severity error;
do_read(X"0", read_data);
wait for 2 us;
assert irq='1' report "Expected CB2 IRQ to be STILL set after positive transition (mode 3)." severity error;
do_write(X"D", X"08"); -- clear flag manually
-- mode 4
cb2 <= 'Z';
do_write(X"C", X"80"); -- mode 4
do_write(X"0", X"31"); -- write to Port B
wait for 2 us;
assert cb2 = '0' report "Expected CB2 to have gone low upon writing to Port B (mode 4)." severity error;
cb1 <= '0';
wait for 2 us;
assert cb2 = '1' report "Expected CB2 to have gone high upon active transition on CB1 (mode 4)." severity error;
cb1 <= '1';
wait for 2 us;
-- mode 5
do_write(X"C", X"A0"); -- mode 5
wait until clock_en='1';
do_write(X"0", X"32"); -- write to port B
wait until clock_en='1' and clock='1';
wait for 1 ns;
assert cb2 = '0' report "Expected CB2 to have gone low upon writing to Port B (mode 5)." severity error;
wait until clock_en='1' and clock='1';
wait for 1 ns;
assert cb2 = '1' report "Expected CB2 to have gone high after one cycle (mode 5)." severity error;
-- mode 6
do_write(X"C", X"C0"); -- mode 6
wait for 2 us;
assert cb2 = '0' report "Expected CB2 to be low in mode 6" severity error;
-- mode 7
do_write(X"C", X"E0"); -- mode 7
wait for 2 us;
assert cb2 = '1' report "Expected CB2 to be high in mode 7." severity error;
wait;
end process;
end tb;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity tb_via6522 is
end tb_via6522;
architecture tb of tb_via6522 is
signal clock : std_logic := '0';
signal clock_en : std_logic := '0'; -- for counters and stuff
signal reset : std_logic;
signal addr : std_logic_vector(3 downto 0) := X"0";
signal wen : std_logic := '0';
signal ren : std_logic := '0';
signal data_in : std_logic_vector(7 downto 0) := X"00";
signal data_out : std_logic_vector(7 downto 0) := X"00";
signal irq : std_logic;
-- pio --
signal port_a_o : std_logic_vector(7 downto 0);
signal port_a_t : std_logic_vector(7 downto 0);
-- signal port_a_i : std_logic_vector(7 downto 0);
signal port_b_o : std_logic_vector(7 downto 0);
signal port_b_t : std_logic_vector(7 downto 0);
-- signal port_b_i : std_logic_vector(7 downto 0);
-- handshake pins
-- signal ca1_i : std_logic;
signal ca2_o : std_logic;
-- signal ca2_i : std_logic;
signal ca2_t : std_logic;
signal cb1_o : std_logic;
-- signal cb1_i : std_logic;
signal cb1_t : std_logic;
signal cb2_o : std_logic;
-- signal cb2_i : std_logic;
signal cb2_t : std_logic;
signal ca1, ca2 : std_logic;
signal cb1, cb2 : std_logic;
signal port_a : std_logic_vector(7 downto 0);
signal port_b : std_logic_vector(7 downto 0);
begin
port_a <= (others => 'H');
port_b <= (others => 'H');
ca1 <= 'H';
ca2 <= ca2_o when ca2_t='1' else 'H';
cb1 <= cb1_o when cb1_t='1' else 'H';
cb2 <= cb2_o when cb2_t='1' else 'H';
process(port_a_o, port_a_t, port_b_o, port_b_t)
begin
for i in 0 to 7 loop
if port_a_t(i)='1' then
port_a(i) <= port_a_o(i);
else
port_a(i) <= 'H';
end if;
if port_b_t(i)='1' then
port_b(i) <= port_b_o(i);
else
port_b(i) <= 'H';
end if;
end loop;
end process;
via: entity work.via6522
port map (
clock => clock,
clock_en => clock_en, -- for counters and stuff
reset => reset,
addr => addr,
wen => wen,
ren => ren,
data_in => data_in,
data_out => data_out,
-- pio --
port_a_o => port_a_o,
port_a_t => port_a_t,
port_a_i => port_a,
port_b_o => port_b_o,
port_b_t => port_b_t,
port_b_i => port_b,
-- handshake pins
ca1_i => ca1,
ca2_o => ca2_o,
ca2_i => ca2,
ca2_t => ca2_t,
cb1_o => cb1_o,
cb1_i => cb1,
cb1_t => cb1_t,
cb2_o => cb2_o,
cb2_i => cb2,
cb2_t => cb2_t,
irq => irq );
clock <= not clock after 125 ns;
reset <= '1', '0' after 2 us;
ce: process
begin
clock_en <= '0';
wait until clock='1';
wait until clock='1';
wait until clock='1';
clock_en <= '1';
wait until clock='1';
end process;
test: process
procedure do_write(a: std_logic_vector(3 downto 0); d: std_logic_vector(7 downto 0)) is
begin
wait until clock='1';
addr <= a;
data_in <= d;
wen <= '1';
wait until clock='1';
wen <= '0';
end do_write;
procedure do_read(a: std_logic_vector(3 downto 0); d: out std_logic_vector(7 downto 0)) is
begin
wait until clock='1';
addr <= a;
ren <= '1';
wait until clock='1';
wait for 1 ns;
ren <= '0';
d := data_out;
end do_read;
variable start : time;
variable read_data : std_logic_vector(7 downto 0);
constant test_byte : std_logic_vector(7 downto 0) := X"47";
constant test_byte2 : std_logic_vector(7 downto 0) := X"E2";
begin
ca1 <= 'Z';
ca2 <= 'Z';
cb1 <= 'Z';
cb2 <= 'Z';
port_b <= (others => 'Z');
wait until reset='0';
for i in 0 to 15 loop
do_read(conv_std_logic_vector(i, 4), read_data);
end loop;
do_write(X"0", X"55"); -- set data = 55
do_write(X"2", X"33"); -- set direction = 33
do_read (X"0", read_data);
assert read_data = "HH01HH01" report "Data port B seems wrong" severity error;
do_write(X"1", X"99"); -- set data = 99
do_write(X"3", X"AA"); -- set direction = AA
do_read (X"0", read_data);
assert read_data = "1H0H1H0H" report "Data port A seems wrong" severity error;
-- TEST SHIFT REGISTER --
do_write(X"8", X"05"); -- timer 2 latch = 5
do_write(X"E", X"84"); -- enable IRQ on shift register
do_write(X"B", X"04"); -- Shift Control = 1 (shift in on timer 2)
do_write(X"A", X"00"); -- dummy write to SR, to start transfer
for i in 7 downto 0 loop
wait until cb1='0';
cb2 <= test_byte(i);
if i = 7 then
start := now;
end if;
end loop;
wait until cb1='1';
cb2 <= 'Z';
wait until irq='1';
assert integer((now - start)/7 us) = 12 report "Timing error serial mode 1." severity error;
-- report "Receiving byte. Bit time: " & integer'image(integer((now - start)/7 us)) severity note;
do_write(X"B", X"08"); -- Shift Control = 2 (shift in on system clock)
do_read (X"A", read_data); -- check byte from previous transmit
assert read_data = test_byte report "Data byte came in was not correct (mode 1)." severity error;
for i in 7 downto 0 loop
wait until cb1='0';
cb2 <= not test_byte(i);
if i = 7 then
start := now;
end if;
end loop;
wait until cb1='1';
cb2 <= 'Z';
wait until irq='1';
assert integer((now - start)/7 us) = 2 report "Timing error serial mode 2." severity error;
do_write(X"B", X"0C"); -- Shift Control = 3 (shift in under control of cb1)
do_read (X"A", read_data); -- check byte from previous transmitm, trigger new
assert read_data = not test_byte report "Data byte came in was not correct (mode 2)." severity error;
for i in test_byte2'range loop
cb1 <= '0';
wait for 2 us;
cb2 <= test_byte2(i);
wait for 2 us;
cb1 <= '1';
wait for 2 us;
end loop;
cb2 <= 'Z';
cb1 <= 'Z';
do_write(X"B", X"10"); -- Shift Control = 4 (shift out continuously)
do_read (X"A", read_data); -- check byte from previous transmitm, trigger new
assert read_data = test_byte2 report "Data byte came in was not correct (mode 3)." severity error;
wait for 150 us;
assert irq = '0' report "An IRQ was generated, but not expected.";
do_write(X"B", X"00"); -- stop endless loop
do_write(X"8", X"03"); -- timer 2 latch = 3 (8 us per bit)
do_write(X"B", X"14"); -- Shift Control = 5 (shift out on Timer 2)
do_write(X"A", X"55");
for i in 7 downto 0 loop
wait until cb1='1';
read_data(i) := cb2;
end loop;
wait until irq='1';
assert read_data = X"55" report "Data byte sent out was not correct (mode 5)." severity error;
do_write(X"B", X"18"); -- Shift Control = 6 (shift out on system clock)
do_write(X"A", X"81");
for i in 7 downto 0 loop
wait until cb1='1';
read_data(i) := cb2;
end loop;
wait until irq='1';
assert read_data = X"81" report "Data byte sent out was not correct (mode 6)." severity error;
do_write(X"B", X"1c"); -- Shift Control = 7 (shift out on own clock)
do_write(X"A", X"B3");
for i in 7 downto 0 loop
cb1 <= '0';
wait for 2 us;
read_data(i) := cb2;
cb1 <= '1';
wait for 2 us;
end loop;
cb1 <= 'Z';
assert read_data = X"B3" report "Data byte sent out was not correct (mode 7)." severity error;
do_write(X"B", X"00"); -- disable shift register
do_write(X"E", X"7F"); -- clear all interupt enable flags
-- TEST TIMER 1 --
do_write(X"E", X"C0"); -- enable interrupt on Timer 1
-- timer 1 is now in one shot mode, output disabled
do_write(X"4", X"30"); -- Set timer to 0x230
do_write(X"5", X"02"); -- ... and start one shot
start := now;
wait until irq='1';
assert integer((now - start)/ 1 us) = 561 report "Interrupt of timer 1 received. Duration Error." severity error;
do_read (X"4", read_data);
wait until clock='1';
assert irq = '0' report "Expected interrupt to be cleared by reading address 4." severity error;
do_write(X"B", X"40"); -- timer in cont. mode
do_write(X"4", X"20"); -- timer = 0x120
do_write(X"5", X"01"); -- trigger, and go
wait until irq='1';
start := now;
do_read(X"4", read_data);
wait until irq='1';
-- report integer'image(integer((now - start) / 1 us)) severity note;
assert integer((now - start) / 1 us) = 290 report "Timer 1 continuous mode, interrupt distance wrong." severity error;
do_write(X"B", X"80"); -- timer 1 one shot, PB7 enabled
do_write(X"4", X"44"); -- set timer to 0x0044
assert irq = '1' report "Expected IRQ still to be set" severity error;
do_write(X"5", X"00"); -- set timer, clear flag, go!
start := now;
wait until clock='1';
assert irq = '0' report "Expected IRQ to be cleared" severity error;
wait until irq='1';
-- report integer'image(integer((now - start) / 1 us)) severity note;
assert integer((now - start) / 1 us) = 68 report "Timer 1 one shot output mode, interrupt distance wrong." severity error;
do_write(X"B", X"C0"); -- timer 1 continuous, PB7 enabled
do_write(X"4", X"24"); -- set timer to 0x0024
do_write(X"5", X"00"); -- set timer, clear flag, go!
start := now;
wait until irq='1';
assert port_b(7)='1' report "Expected bit 7 of PB to be '1'" severity error;
do_write(X"7", X"00"); -- re-write latch value, reset flag
wait until irq='1';
assert port_b(7)='0' report "Expected bit 7 of PB to be '0'" severity error;
do_read(X"4", read_data); --reset flag
wait until irq='1';
assert port_b(7)='1' report "Expected bit 7 of PB to be '1'" severity error;
do_write(X"B", X"00"); -- timer 1 one shot, output disabled
do_write(X"E", X"7E"); -- clear interrupt enable flags
-- TEST TIMER 2 --
do_write(X"E", X"A0"); -- Set interrupt on timer 2
do_write(X"8", X"33"); -- Set lower latch to 33.
wait for 10 us; -- observe timer to count
wait until clock_en='1';
do_write(X"9", X"02"); -- Set timer to 0x233 and wait for IRQ
start := now;
wait until irq='1';
-- report integer'image(integer((now - start) / 1 us)) severity note;
assert integer((now - start) / 1 us) = 16#233# report "Timer 2 one shot mode, interrupt time wrong." severity error;
do_read(X"8", read_data);
do_write(X"B", X"20"); -- set to pulse count mode
do_write(X"2", X"00"); -- set port B to input
do_write(X"8", X"0A"); -- set to 10 pulses
do_write(X"9", X"00"); -- high byte and trigger
for i in 0 to 10 loop
port_b(6) <= '0';
wait for 5 us;
port_b(6) <= '1';
wait for 1 us;
assert not((i > 9) and (irq = '0')) report "Expected IRQ to be 1 after 10th pulse" severity error;
assert not((i < 10) and (irq = '1')) report "Expected IRQ to be 0 before 10th pulse" severity error;
wait for 15 us;
end loop;
-- TEST CA1 --
do_write(X"C", X"00");
do_write(X"E", X"7F");
do_write(X"E", X"82"); -- interrupt on CA1
wait until clock='1';
-- no transitions have taken place yet on CA1, hence IRQ should be low
assert irq='0' report "Expected CA1 interrupt to be low before any transition." severity error;
ca1 <= '0';
wait for 2 us;
assert irq='1' report "Expected CA1 IRQ to be set after negative transition." severity error;
do_read(X"1", read_data);
wait for 2 us;
assert irq='0' report "Expected CA1 IRQ to be cleared by reading port a." severity error;
do_write(X"C", X"01"); -- CA1 control = '1', expecting rising edge
wait for 2 us;
ca1 <= '1';
wait for 2 us;
assert irq='1' report "Expected CA1 IRQ to be set after positive transition." severity error;
do_write(X"1", X"47");
wait for 2 us;
assert irq='0' report "Expected CA1 IRQ to be cleared by writing port A." severity error;
-- TEST CB1 --
cb1 <= '1';
do_write(X"0", X"11"); -- clear flag
do_write(X"C", X"00");
do_write(X"E", X"7F");
do_write(X"E", X"90"); -- interrupt on CB1
wait until clock='1';
-- no transitions have taken place yet on CB1, hence IRQ should be low
assert irq='0' report "Expected CB1 interrupt to be low before any transition." severity error;
cb1 <= '0';
wait for 2 us;
assert irq='1' report "Expected CB1 IRQ to be set after negative transition." severity error;
do_read(X"0", read_data);
wait for 2 us;
assert irq='0' report "Expected CB1 IRQ to be cleared by reading port B." severity error;
do_write(X"C", X"10"); -- CB1 control = '1', expecting rising edge
wait for 2 us;
cb1 <= '1';
wait for 2 us;
assert irq='1' report "Expected CB1 IRQ to be set after positive transition." severity error;
do_write(X"0", X"47");
wait for 2 us;
assert irq='0' report "Expected CB1 IRQ to be cleared by writing port B." severity error;
-- TEST CA2 --
-- mode 0: input, negative transition, Port A out clears flag
ca2 <= '1';
do_write(X"C", X"00"); -- mode 0
do_write(X"D", X"01"); -- clear flag
do_write(X"E", X"7F"); -- reset all interrupt enables
do_write(X"E", X"81"); -- enable CA2 interrupt
wait for 2 us;
assert irq='0' report "Expected CA2 interrupt to be low before any transition." severity error;
ca2 <= '0';
wait for 2 us;
assert irq='1' report "Expected CA2 IRQ to be set after negative transition." severity error;
do_write(X"1", X"44"); -- write to Port a
wait for 2 us;
assert irq='0' report "Expected CA2 IRQ to be cleared by writing to port A." severity error;
-- mode 2: input, positive transition, Port A in/out clears flag
do_write(X"C", X"04"); -- mode 2
wait for 2 us;
ca2 <= '1';
wait for 2 us;
assert irq='1' report "Expected CA2 IRQ to be set after positive transition." severity error;
do_read(X"1", read_data);
wait for 2 us;
assert irq='0' report "Expected CA2 IRQ to be cleared by reading port A." severity error;
-- mode 1 / 3, read/write to port A does NOT clear the interrupt flag
do_write(X"C", X"02"); -- mode 1
wait for 2 us;
ca2 <= '0';
wait for 2 us;
assert irq='1' report "Expected CA2 IRQ to be set after negative transition (mode 1)." severity error;
do_read(X"1", read_data);
wait for 2 us;
assert irq='1' report "Expected CA2 IRQ to be STILL set after negative transition (mode 1)." severity error;
do_write(X"D", X"01"); -- clear flag manually
do_write(X"C", X"06"); -- mode 3
wait for 2 us;
ca2 <= '1';
wait for 2 us;
assert irq='1' report "Expected CA2 IRQ to be set after positive transition (mode 3)." severity error;
do_read(X"1", read_data);
wait for 2 us;
assert irq='1' report "Expected CA2 IRQ to be STILL set after positive transition (mode 3)." severity error;
do_write(X"D", X"01"); -- clear flag manually
-- mode 4
ca2 <= 'Z';
do_write(X"C", X"08"); -- mode 4
do_write(X"1", X"31"); -- write to Port A
wait for 2 us;
assert ca2 = '0' report "Expected CA2 to have gone low upon writing to Port A (mode 4)." severity error;
ca1 <= '0';
wait for 2 us;
assert ca2 = '1' report "Expected CA2 to have gone high upon active transition on CA1 (mode 4)." severity error;
ca1 <= '1';
wait for 2 us;
-- mode 5
do_write(X"C", X"0A"); -- mode 5
wait until clock_en='1';
do_write(X"1", X"32"); -- write to port A
wait until clock_en='1' and clock='1';
wait for 1 ns;
assert ca2 = '0' report "Expected CA2 to have gone low upon writing to Port A (mode 5)." severity error;
wait until clock_en='1' and clock='1';
wait for 1 ns;
assert ca2 = '1' report "Expected CA2 to have gone high after one cycle (mode 5)." severity error;
-- mode 6
do_write(X"C", X"0C"); -- mode 6
wait for 2 us;
assert ca2 = '0' report "Expected CA2 to be low in mode 6" severity error;
-- mode 7
do_write(X"C", X"0E"); -- mode 7
wait for 2 us;
assert ca2 = '1' report "Expected CA2 to be high in mode 7." severity error;
-- TEST CB2 --
-- mode 0: input, negative transition, Port B out clears flag
cb2 <= '1';
do_write(X"C", X"00"); -- mode 0
do_write(X"D", X"08"); -- clear flag
do_write(X"E", X"7F"); -- reset all interrupt enables
do_write(X"E", X"88"); -- enable CB2 interrupt
wait for 2 us;
assert irq='0' report "Expected CB2 interrupt to be low before any transition." severity error;
cb2 <= '0';
wait for 2 us;
assert irq='1' report "Expected CB2 IRQ to be set after negative transition." severity error;
do_write(X"0", X"44"); -- write to Port B
wait for 2 us;
assert irq='0' report "Expected CB2 IRQ to be cleared by writing to port B." severity error;
-- mode 2: input, positive transition, Port B in/out clears flag
do_write(X"C", X"40"); -- mode 2
wait for 2 us;
cb2 <= '1';
wait for 2 us;
assert irq='1' report "Expected CB2 IRQ to be set after positive transition." severity error;
do_read(X"0", read_data);
wait for 2 us;
assert irq='0' report "Expected CB2 IRQ to be cleared by reading port B." severity error;
-- mode 1 / 3, read/write to port B does NOT clear the interrupt flag
do_write(X"C", X"20"); -- mode 1
wait for 2 us;
cb2 <= '0';
wait for 2 us;
assert irq='1' report "Expected CB2 IRQ to be set after negative transition (mode 1)." severity error;
do_read(X"0", read_data);
wait for 2 us;
assert irq='1' report "Expected CB2 IRQ to be STILL set after negative transition (mode 1)." severity error;
do_write(X"D", X"08"); -- clear flag manually
do_write(X"C", X"60"); -- mode 3
wait for 2 us;
cb2 <= '1';
wait for 2 us;
assert irq='1' report "Expected CB2 IRQ to be set after positive transition (mode 3)." severity error;
do_read(X"0", read_data);
wait for 2 us;
assert irq='1' report "Expected CB2 IRQ to be STILL set after positive transition (mode 3)." severity error;
do_write(X"D", X"08"); -- clear flag manually
-- mode 4
cb2 <= 'Z';
do_write(X"C", X"80"); -- mode 4
do_write(X"0", X"31"); -- write to Port B
wait for 2 us;
assert cb2 = '0' report "Expected CB2 to have gone low upon writing to Port B (mode 4)." severity error;
cb1 <= '0';
wait for 2 us;
assert cb2 = '1' report "Expected CB2 to have gone high upon active transition on CB1 (mode 4)." severity error;
cb1 <= '1';
wait for 2 us;
-- mode 5
do_write(X"C", X"A0"); -- mode 5
wait until clock_en='1';
do_write(X"0", X"32"); -- write to port B
wait until clock_en='1' and clock='1';
wait for 1 ns;
assert cb2 = '0' report "Expected CB2 to have gone low upon writing to Port B (mode 5)." severity error;
wait until clock_en='1' and clock='1';
wait for 1 ns;
assert cb2 = '1' report "Expected CB2 to have gone high after one cycle (mode 5)." severity error;
-- mode 6
do_write(X"C", X"C0"); -- mode 6
wait for 2 us;
assert cb2 = '0' report "Expected CB2 to be low in mode 6" severity error;
-- mode 7
do_write(X"C", X"E0"); -- mode 7
wait for 2 us;
assert cb2 = '1' report "Expected CB2 to be high in mode 7." severity error;
wait;
end process;
end tb;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Thu Sep 14 10:54:36 2017
-- Host : PC4719 running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_0_stub.vhdl
-- Design : ila_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k325tffg676-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
clk : in STD_LOGIC;
probe0 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe1 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe2 : in STD_LOGIC_VECTOR ( 31 downto 0 );
probe3 : in STD_LOGIC_VECTOR ( 31 downto 0 );
probe4 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe5 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe6 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe7 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,probe0[63:0],probe1[63:0],probe2[31:0],probe3[31:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[0:0]";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2016.3";
begin
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.pkg.all;
entity foo is
port (
bus_in : in bus_t(data(7 downto 0));
bus_out : out bus_t(data(7 downto 0))
);
end foo;
architecture foo of foo is
begin
bus_out <= bus_in;
end foo;
|
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: O.40d
-- \ \ Application: netgen
-- / / Filename: div_gen_v3_0.vhd
-- /___/ /\ Timestamp: Mon Dec 15 22:32:14 2014
-- \ \ / \
-- \___\/\___\
--
-- Command : -intstyle ise -w -sim -ofmt vhdl ./tmp/_cg/div_gen_v3_0.ngc ./tmp/_cg/div_gen_v3_0.vhd
-- Device : 3s500evq100-5
-- Input file : ./tmp/_cg/div_gen_v3_0.ngc
-- Output file : ./tmp/_cg/div_gen_v3_0.vhd
-- # of Entities : 1
-- Design Name : div_gen_v3_0
-- Xilinx : /opt/Xilinx/13.1/ISE_DS/ISE/
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Command Line Tools User Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
-- synthesis translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
entity div_gen_v3_0 is
port (
rfd : out STD_LOGIC;
clk : in STD_LOGIC := 'X';
dividend : in STD_LOGIC_VECTOR ( 7 downto 0 );
quotient : out STD_LOGIC_VECTOR ( 7 downto 0 );
divisor : in STD_LOGIC_VECTOR ( 7 downto 0 );
fractional : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end div_gen_v3_0;
architecture STRUCTURE of div_gen_v3_0 is
signal NlwRenamedSig_OI_rfd : STD_LOGIC;
signal blk00000003_sig00000272 : STD_LOGIC;
signal blk00000003_sig00000271 : STD_LOGIC;
signal blk00000003_sig00000270 : STD_LOGIC;
signal blk00000003_sig0000026f : STD_LOGIC;
signal blk00000003_sig0000026e : STD_LOGIC;
signal blk00000003_sig0000026d : STD_LOGIC;
signal blk00000003_sig0000026c : STD_LOGIC;
signal blk00000003_sig0000026b : STD_LOGIC;
signal blk00000003_sig0000026a : STD_LOGIC;
signal blk00000003_sig00000269 : STD_LOGIC;
signal blk00000003_sig00000268 : STD_LOGIC;
signal blk00000003_sig00000267 : STD_LOGIC;
signal blk00000003_sig00000266 : STD_LOGIC;
signal blk00000003_sig00000265 : STD_LOGIC;
signal blk00000003_sig00000264 : STD_LOGIC;
signal blk00000003_sig00000263 : STD_LOGIC;
signal blk00000003_sig00000262 : STD_LOGIC;
signal blk00000003_sig00000261 : STD_LOGIC;
signal blk00000003_sig00000260 : STD_LOGIC;
signal blk00000003_sig0000025f : STD_LOGIC;
signal blk00000003_sig0000025e : STD_LOGIC;
signal blk00000003_sig0000025d : STD_LOGIC;
signal blk00000003_sig0000025c : STD_LOGIC;
signal blk00000003_sig0000025b : STD_LOGIC;
signal blk00000003_sig0000025a : STD_LOGIC;
signal blk00000003_sig00000259 : STD_LOGIC;
signal blk00000003_sig00000258 : STD_LOGIC;
signal blk00000003_sig00000257 : STD_LOGIC;
signal blk00000003_sig00000256 : STD_LOGIC;
signal blk00000003_sig00000255 : STD_LOGIC;
signal blk00000003_sig00000254 : STD_LOGIC;
signal blk00000003_sig00000253 : STD_LOGIC;
signal blk00000003_sig00000252 : STD_LOGIC;
signal blk00000003_sig00000251 : STD_LOGIC;
signal blk00000003_sig00000250 : STD_LOGIC;
signal blk00000003_sig0000024f : STD_LOGIC;
signal blk00000003_sig0000024e : STD_LOGIC;
signal blk00000003_sig0000024d : STD_LOGIC;
signal blk00000003_sig0000024c : STD_LOGIC;
signal blk00000003_sig0000024b : STD_LOGIC;
signal blk00000003_sig0000024a : STD_LOGIC;
signal blk00000003_sig00000249 : STD_LOGIC;
signal blk00000003_sig00000248 : STD_LOGIC;
signal blk00000003_sig00000247 : STD_LOGIC;
signal blk00000003_sig00000246 : STD_LOGIC;
signal blk00000003_sig00000245 : STD_LOGIC;
signal blk00000003_sig00000244 : STD_LOGIC;
signal blk00000003_sig00000243 : STD_LOGIC;
signal blk00000003_sig00000242 : STD_LOGIC;
signal blk00000003_sig00000241 : STD_LOGIC;
signal blk00000003_sig00000240 : STD_LOGIC;
signal blk00000003_sig0000023f : STD_LOGIC;
signal blk00000003_sig0000023e : STD_LOGIC;
signal blk00000003_sig0000023d : STD_LOGIC;
signal blk00000003_sig0000023c : STD_LOGIC;
signal blk00000003_sig0000023b : STD_LOGIC;
signal blk00000003_sig0000023a : STD_LOGIC;
signal blk00000003_sig00000239 : STD_LOGIC;
signal blk00000003_sig00000238 : STD_LOGIC;
signal blk00000003_sig00000237 : STD_LOGIC;
signal blk00000003_sig00000236 : STD_LOGIC;
signal blk00000003_sig00000235 : STD_LOGIC;
signal blk00000003_sig00000234 : STD_LOGIC;
signal blk00000003_sig00000233 : STD_LOGIC;
signal blk00000003_sig00000232 : STD_LOGIC;
signal blk00000003_sig00000231 : STD_LOGIC;
signal blk00000003_sig00000230 : STD_LOGIC;
signal blk00000003_sig0000022f : STD_LOGIC;
signal blk00000003_sig0000022e : STD_LOGIC;
signal blk00000003_sig0000022d : STD_LOGIC;
signal blk00000003_sig0000022c : STD_LOGIC;
signal blk00000003_sig0000022b : STD_LOGIC;
signal blk00000003_sig0000022a : STD_LOGIC;
signal blk00000003_sig00000229 : STD_LOGIC;
signal blk00000003_sig00000228 : STD_LOGIC;
signal blk00000003_sig00000227 : STD_LOGIC;
signal blk00000003_sig00000226 : STD_LOGIC;
signal blk00000003_sig00000225 : STD_LOGIC;
signal blk00000003_sig00000224 : STD_LOGIC;
signal blk00000003_sig00000223 : STD_LOGIC;
signal blk00000003_sig00000222 : STD_LOGIC;
signal blk00000003_sig00000221 : STD_LOGIC;
signal blk00000003_sig00000220 : STD_LOGIC;
signal blk00000003_sig0000021f : STD_LOGIC;
signal blk00000003_sig0000021e : STD_LOGIC;
signal blk00000003_sig0000021d : STD_LOGIC;
signal blk00000003_sig0000021c : STD_LOGIC;
signal blk00000003_sig0000021b : STD_LOGIC;
signal blk00000003_sig0000021a : STD_LOGIC;
signal blk00000003_sig00000219 : STD_LOGIC;
signal blk00000003_sig00000218 : STD_LOGIC;
signal blk00000003_sig00000217 : STD_LOGIC;
signal blk00000003_sig00000216 : STD_LOGIC;
signal blk00000003_sig00000215 : STD_LOGIC;
signal blk00000003_sig00000214 : STD_LOGIC;
signal blk00000003_sig00000213 : STD_LOGIC;
signal blk00000003_sig00000212 : STD_LOGIC;
signal blk00000003_sig00000211 : STD_LOGIC;
signal blk00000003_sig00000210 : STD_LOGIC;
signal blk00000003_sig0000020f : STD_LOGIC;
signal blk00000003_sig0000020e : STD_LOGIC;
signal blk00000003_sig0000020d : STD_LOGIC;
signal blk00000003_sig0000020c : STD_LOGIC;
signal blk00000003_sig0000020b : STD_LOGIC;
signal blk00000003_sig0000020a : STD_LOGIC;
signal blk00000003_sig00000209 : STD_LOGIC;
signal blk00000003_sig00000208 : STD_LOGIC;
signal blk00000003_sig00000207 : STD_LOGIC;
signal blk00000003_sig00000206 : STD_LOGIC;
signal blk00000003_sig00000205 : STD_LOGIC;
signal blk00000003_sig00000204 : STD_LOGIC;
signal blk00000003_sig00000203 : STD_LOGIC;
signal blk00000003_sig00000202 : STD_LOGIC;
signal blk00000003_sig00000201 : STD_LOGIC;
signal blk00000003_sig00000200 : STD_LOGIC;
signal blk00000003_sig000001ff : STD_LOGIC;
signal blk00000003_sig000001fe : STD_LOGIC;
signal blk00000003_sig000001fd : STD_LOGIC;
signal blk00000003_sig000001fc : STD_LOGIC;
signal blk00000003_sig000001fb : STD_LOGIC;
signal blk00000003_sig000001fa : STD_LOGIC;
signal blk00000003_sig000001f9 : STD_LOGIC;
signal blk00000003_sig000001f8 : STD_LOGIC;
signal blk00000003_sig000001f7 : STD_LOGIC;
signal blk00000003_sig000001f6 : STD_LOGIC;
signal blk00000003_sig000001f5 : STD_LOGIC;
signal blk00000003_sig000001f4 : STD_LOGIC;
signal blk00000003_sig000001f3 : STD_LOGIC;
signal blk00000003_sig000001f2 : STD_LOGIC;
signal blk00000003_sig000001f1 : STD_LOGIC;
signal blk00000003_sig000001f0 : STD_LOGIC;
signal blk00000003_sig000001ef : STD_LOGIC;
signal blk00000003_sig000001ee : STD_LOGIC;
signal blk00000003_sig000001ed : STD_LOGIC;
signal blk00000003_sig000001ec : STD_LOGIC;
signal blk00000003_sig000001eb : STD_LOGIC;
signal blk00000003_sig000001ea : STD_LOGIC;
signal blk00000003_sig000001e9 : STD_LOGIC;
signal blk00000003_sig000001e8 : STD_LOGIC;
signal blk00000003_sig000001e7 : STD_LOGIC;
signal blk00000003_sig000001e6 : STD_LOGIC;
signal blk00000003_sig000001e5 : STD_LOGIC;
signal blk00000003_sig000001e4 : STD_LOGIC;
signal blk00000003_sig000001e3 : STD_LOGIC;
signal blk00000003_sig000001e2 : STD_LOGIC;
signal blk00000003_sig000001e1 : STD_LOGIC;
signal blk00000003_sig000001e0 : STD_LOGIC;
signal blk00000003_sig000001df : STD_LOGIC;
signal blk00000003_sig000001de : STD_LOGIC;
signal blk00000003_sig000001dd : STD_LOGIC;
signal blk00000003_sig000001dc : STD_LOGIC;
signal blk00000003_sig000001db : STD_LOGIC;
signal blk00000003_sig000001da : STD_LOGIC;
signal blk00000003_sig000001d9 : STD_LOGIC;
signal blk00000003_sig000001d8 : STD_LOGIC;
signal blk00000003_sig000001d7 : STD_LOGIC;
signal blk00000003_sig000001d6 : STD_LOGIC;
signal blk00000003_sig000001d5 : STD_LOGIC;
signal blk00000003_sig000001d4 : STD_LOGIC;
signal blk00000003_sig000001d3 : STD_LOGIC;
signal blk00000003_sig000001d2 : STD_LOGIC;
signal blk00000003_sig000001d1 : STD_LOGIC;
signal blk00000003_sig000001d0 : STD_LOGIC;
signal blk00000003_sig000001cf : STD_LOGIC;
signal blk00000003_sig000001ce : STD_LOGIC;
signal blk00000003_sig000001cd : STD_LOGIC;
signal blk00000003_sig000001cc : STD_LOGIC;
signal blk00000003_sig000001cb : STD_LOGIC;
signal blk00000003_sig000001ca : STD_LOGIC;
signal blk00000003_sig000001c9 : STD_LOGIC;
signal blk00000003_sig000001c8 : STD_LOGIC;
signal blk00000003_sig000001c7 : STD_LOGIC;
signal blk00000003_sig000001c6 : STD_LOGIC;
signal blk00000003_sig000001c5 : STD_LOGIC;
signal blk00000003_sig000001c4 : STD_LOGIC;
signal blk00000003_sig000001c3 : STD_LOGIC;
signal blk00000003_sig000001c2 : STD_LOGIC;
signal blk00000003_sig000001c1 : STD_LOGIC;
signal blk00000003_sig000001c0 : STD_LOGIC;
signal blk00000003_sig000001bf : STD_LOGIC;
signal blk00000003_sig000001be : STD_LOGIC;
signal blk00000003_sig000001bd : STD_LOGIC;
signal blk00000003_sig000001bc : STD_LOGIC;
signal blk00000003_sig000001bb : STD_LOGIC;
signal blk00000003_sig000001ba : STD_LOGIC;
signal blk00000003_sig000001b9 : STD_LOGIC;
signal blk00000003_sig000001b8 : STD_LOGIC;
signal blk00000003_sig000001b7 : STD_LOGIC;
signal blk00000003_sig000001b6 : STD_LOGIC;
signal blk00000003_sig000001b5 : STD_LOGIC;
signal blk00000003_sig000001b4 : STD_LOGIC;
signal blk00000003_sig000001b3 : STD_LOGIC;
signal blk00000003_sig000001b2 : STD_LOGIC;
signal blk00000003_sig000001b1 : STD_LOGIC;
signal blk00000003_sig000001b0 : STD_LOGIC;
signal blk00000003_sig000001af : STD_LOGIC;
signal blk00000003_sig000001ae : STD_LOGIC;
signal blk00000003_sig000001ad : STD_LOGIC;
signal blk00000003_sig000001ac : STD_LOGIC;
signal blk00000003_sig000001ab : STD_LOGIC;
signal blk00000003_sig000001aa : STD_LOGIC;
signal blk00000003_sig000001a9 : STD_LOGIC;
signal blk00000003_sig000001a8 : STD_LOGIC;
signal blk00000003_sig000001a7 : STD_LOGIC;
signal blk00000003_sig000001a6 : STD_LOGIC;
signal blk00000003_sig000001a5 : STD_LOGIC;
signal blk00000003_sig000001a4 : STD_LOGIC;
signal blk00000003_sig000001a3 : STD_LOGIC;
signal blk00000003_sig000001a2 : STD_LOGIC;
signal blk00000003_sig000001a1 : STD_LOGIC;
signal blk00000003_sig000001a0 : STD_LOGIC;
signal blk00000003_sig0000019f : STD_LOGIC;
signal blk00000003_sig0000019e : STD_LOGIC;
signal blk00000003_sig0000019d : STD_LOGIC;
signal blk00000003_sig0000019c : STD_LOGIC;
signal blk00000003_sig0000019b : STD_LOGIC;
signal blk00000003_sig0000019a : STD_LOGIC;
signal blk00000003_sig00000199 : STD_LOGIC;
signal blk00000003_sig00000198 : STD_LOGIC;
signal blk00000003_sig00000197 : STD_LOGIC;
signal blk00000003_sig00000196 : STD_LOGIC;
signal blk00000003_sig00000195 : STD_LOGIC;
signal blk00000003_sig00000194 : STD_LOGIC;
signal blk00000003_sig00000193 : STD_LOGIC;
signal blk00000003_sig00000192 : STD_LOGIC;
signal blk00000003_sig00000191 : STD_LOGIC;
signal blk00000003_sig00000190 : STD_LOGIC;
signal blk00000003_sig0000018f : STD_LOGIC;
signal blk00000003_sig0000018e : STD_LOGIC;
signal blk00000003_sig0000018d : STD_LOGIC;
signal blk00000003_sig0000018c : STD_LOGIC;
signal blk00000003_sig0000018b : STD_LOGIC;
signal blk00000003_sig0000018a : STD_LOGIC;
signal blk00000003_sig00000189 : STD_LOGIC;
signal blk00000003_sig00000188 : STD_LOGIC;
signal blk00000003_sig00000187 : STD_LOGIC;
signal blk00000003_sig00000186 : STD_LOGIC;
signal blk00000003_sig00000185 : STD_LOGIC;
signal blk00000003_sig00000184 : STD_LOGIC;
signal blk00000003_sig00000183 : STD_LOGIC;
signal blk00000003_sig00000182 : STD_LOGIC;
signal blk00000003_sig00000181 : STD_LOGIC;
signal blk00000003_sig00000180 : STD_LOGIC;
signal blk00000003_sig0000017f : STD_LOGIC;
signal blk00000003_sig0000017e : STD_LOGIC;
signal blk00000003_sig0000017d : STD_LOGIC;
signal blk00000003_sig0000017c : STD_LOGIC;
signal blk00000003_sig0000017b : STD_LOGIC;
signal blk00000003_sig0000017a : STD_LOGIC;
signal blk00000003_sig00000179 : STD_LOGIC;
signal blk00000003_sig00000178 : STD_LOGIC;
signal blk00000003_sig00000177 : STD_LOGIC;
signal blk00000003_sig00000176 : STD_LOGIC;
signal blk00000003_sig00000175 : STD_LOGIC;
signal blk00000003_sig00000174 : STD_LOGIC;
signal blk00000003_sig00000173 : STD_LOGIC;
signal blk00000003_sig00000172 : STD_LOGIC;
signal blk00000003_sig00000171 : STD_LOGIC;
signal blk00000003_sig00000170 : STD_LOGIC;
signal blk00000003_sig0000016f : STD_LOGIC;
signal blk00000003_sig0000016e : STD_LOGIC;
signal blk00000003_sig0000016d : STD_LOGIC;
signal blk00000003_sig0000016c : STD_LOGIC;
signal blk00000003_sig0000016b : STD_LOGIC;
signal blk00000003_sig0000016a : STD_LOGIC;
signal blk00000003_sig00000169 : STD_LOGIC;
signal blk00000003_sig00000168 : STD_LOGIC;
signal blk00000003_sig00000167 : STD_LOGIC;
signal blk00000003_sig00000166 : STD_LOGIC;
signal blk00000003_sig00000165 : STD_LOGIC;
signal blk00000003_sig00000164 : STD_LOGIC;
signal blk00000003_sig00000163 : STD_LOGIC;
signal blk00000003_sig00000162 : STD_LOGIC;
signal blk00000003_sig00000161 : STD_LOGIC;
signal blk00000003_sig00000160 : STD_LOGIC;
signal blk00000003_sig0000015f : STD_LOGIC;
signal blk00000003_sig0000015e : STD_LOGIC;
signal blk00000003_sig0000015d : STD_LOGIC;
signal blk00000003_sig0000015c : STD_LOGIC;
signal blk00000003_sig0000015b : STD_LOGIC;
signal blk00000003_sig0000015a : STD_LOGIC;
signal blk00000003_sig00000159 : STD_LOGIC;
signal blk00000003_sig00000158 : STD_LOGIC;
signal blk00000003_sig00000157 : STD_LOGIC;
signal blk00000003_sig00000156 : STD_LOGIC;
signal blk00000003_sig00000155 : STD_LOGIC;
signal blk00000003_sig00000154 : STD_LOGIC;
signal blk00000003_sig00000153 : STD_LOGIC;
signal blk00000003_sig00000152 : STD_LOGIC;
signal blk00000003_sig00000151 : STD_LOGIC;
signal blk00000003_sig00000150 : STD_LOGIC;
signal blk00000003_sig0000014f : STD_LOGIC;
signal blk00000003_sig0000014e : STD_LOGIC;
signal blk00000003_sig0000014d : STD_LOGIC;
signal blk00000003_sig0000014c : STD_LOGIC;
signal blk00000003_sig0000014b : STD_LOGIC;
signal blk00000003_sig0000014a : STD_LOGIC;
signal blk00000003_sig00000149 : STD_LOGIC;
signal blk00000003_sig00000148 : STD_LOGIC;
signal blk00000003_sig00000147 : STD_LOGIC;
signal blk00000003_sig00000146 : STD_LOGIC;
signal blk00000003_sig00000145 : STD_LOGIC;
signal blk00000003_sig00000144 : STD_LOGIC;
signal blk00000003_sig00000143 : STD_LOGIC;
signal blk00000003_sig00000142 : STD_LOGIC;
signal blk00000003_sig00000141 : STD_LOGIC;
signal blk00000003_sig00000140 : STD_LOGIC;
signal blk00000003_sig0000013f : STD_LOGIC;
signal blk00000003_sig0000013e : STD_LOGIC;
signal blk00000003_sig0000013d : STD_LOGIC;
signal blk00000003_sig0000013c : STD_LOGIC;
signal blk00000003_sig0000013b : STD_LOGIC;
signal blk00000003_sig0000013a : STD_LOGIC;
signal blk00000003_sig00000139 : STD_LOGIC;
signal blk00000003_sig00000138 : STD_LOGIC;
signal blk00000003_sig00000137 : STD_LOGIC;
signal blk00000003_sig00000136 : STD_LOGIC;
signal blk00000003_sig00000135 : STD_LOGIC;
signal blk00000003_sig00000134 : STD_LOGIC;
signal blk00000003_sig00000133 : STD_LOGIC;
signal blk00000003_sig00000132 : STD_LOGIC;
signal blk00000003_sig00000131 : STD_LOGIC;
signal blk00000003_sig00000130 : STD_LOGIC;
signal blk00000003_sig0000012f : STD_LOGIC;
signal blk00000003_sig0000012e : STD_LOGIC;
signal blk00000003_sig0000012d : STD_LOGIC;
signal blk00000003_sig0000012c : STD_LOGIC;
signal blk00000003_sig0000012b : STD_LOGIC;
signal blk00000003_sig0000012a : STD_LOGIC;
signal blk00000003_sig00000129 : STD_LOGIC;
signal blk00000003_sig00000128 : STD_LOGIC;
signal blk00000003_sig00000127 : STD_LOGIC;
signal blk00000003_sig00000126 : STD_LOGIC;
signal blk00000003_sig00000125 : STD_LOGIC;
signal blk00000003_sig00000124 : STD_LOGIC;
signal blk00000003_sig00000123 : STD_LOGIC;
signal blk00000003_sig00000122 : STD_LOGIC;
signal blk00000003_sig00000121 : STD_LOGIC;
signal blk00000003_sig00000120 : STD_LOGIC;
signal blk00000003_sig0000011f : STD_LOGIC;
signal blk00000003_sig0000011e : STD_LOGIC;
signal blk00000003_sig0000011d : STD_LOGIC;
signal blk00000003_sig0000011c : STD_LOGIC;
signal blk00000003_sig0000011b : STD_LOGIC;
signal blk00000003_sig0000011a : STD_LOGIC;
signal blk00000003_sig00000119 : STD_LOGIC;
signal blk00000003_sig00000118 : STD_LOGIC;
signal blk00000003_sig00000117 : STD_LOGIC;
signal blk00000003_sig00000116 : STD_LOGIC;
signal blk00000003_sig00000115 : STD_LOGIC;
signal blk00000003_sig00000114 : STD_LOGIC;
signal blk00000003_sig00000113 : STD_LOGIC;
signal blk00000003_sig00000112 : STD_LOGIC;
signal blk00000003_sig00000111 : STD_LOGIC;
signal blk00000003_sig00000110 : STD_LOGIC;
signal blk00000003_sig0000010f : STD_LOGIC;
signal blk00000003_sig0000010e : STD_LOGIC;
signal blk00000003_sig0000010d : STD_LOGIC;
signal blk00000003_sig0000010c : STD_LOGIC;
signal blk00000003_sig0000010b : STD_LOGIC;
signal blk00000003_sig0000010a : STD_LOGIC;
signal blk00000003_sig00000109 : STD_LOGIC;
signal blk00000003_sig00000108 : STD_LOGIC;
signal blk00000003_sig00000107 : STD_LOGIC;
signal blk00000003_sig00000106 : STD_LOGIC;
signal blk00000003_sig00000105 : STD_LOGIC;
signal blk00000003_sig00000104 : STD_LOGIC;
signal blk00000003_sig00000103 : STD_LOGIC;
signal blk00000003_sig00000102 : STD_LOGIC;
signal blk00000003_sig00000101 : STD_LOGIC;
signal blk00000003_sig00000100 : STD_LOGIC;
signal blk00000003_sig000000ff : STD_LOGIC;
signal blk00000003_sig000000fe : STD_LOGIC;
signal blk00000003_sig000000fd : STD_LOGIC;
signal blk00000003_sig000000fc : STD_LOGIC;
signal blk00000003_sig000000fb : STD_LOGIC;
signal blk00000003_sig000000fa : STD_LOGIC;
signal blk00000003_sig000000f9 : STD_LOGIC;
signal blk00000003_sig000000f8 : STD_LOGIC;
signal blk00000003_sig000000f7 : STD_LOGIC;
signal blk00000003_sig000000f6 : STD_LOGIC;
signal blk00000003_sig000000f5 : STD_LOGIC;
signal blk00000003_sig000000f4 : STD_LOGIC;
signal blk00000003_sig000000f3 : STD_LOGIC;
signal blk00000003_sig000000f2 : STD_LOGIC;
signal blk00000003_sig000000f1 : STD_LOGIC;
signal blk00000003_sig000000f0 : STD_LOGIC;
signal blk00000003_sig000000ef : STD_LOGIC;
signal blk00000003_sig000000ee : STD_LOGIC;
signal blk00000003_sig000000ed : STD_LOGIC;
signal blk00000003_sig000000ec : STD_LOGIC;
signal blk00000003_sig000000eb : STD_LOGIC;
signal blk00000003_sig000000ea : STD_LOGIC;
signal blk00000003_sig000000e9 : STD_LOGIC;
signal blk00000003_sig000000e8 : STD_LOGIC;
signal blk00000003_sig000000e7 : STD_LOGIC;
signal blk00000003_sig000000e6 : STD_LOGIC;
signal blk00000003_sig000000e5 : STD_LOGIC;
signal blk00000003_sig000000e4 : STD_LOGIC;
signal blk00000003_sig000000e3 : STD_LOGIC;
signal blk00000003_sig000000e2 : STD_LOGIC;
signal blk00000003_sig000000e1 : STD_LOGIC;
signal blk00000003_sig000000e0 : STD_LOGIC;
signal blk00000003_sig000000df : STD_LOGIC;
signal blk00000003_sig000000de : STD_LOGIC;
signal blk00000003_sig000000dd : STD_LOGIC;
signal blk00000003_sig000000dc : STD_LOGIC;
signal blk00000003_sig000000db : STD_LOGIC;
signal blk00000003_sig000000da : STD_LOGIC;
signal blk00000003_sig000000d9 : STD_LOGIC;
signal blk00000003_sig000000d8 : STD_LOGIC;
signal blk00000003_sig000000d7 : STD_LOGIC;
signal blk00000003_sig000000d6 : STD_LOGIC;
signal blk00000003_sig000000d5 : STD_LOGIC;
signal blk00000003_sig000000d4 : STD_LOGIC;
signal blk00000003_sig000000d3 : STD_LOGIC;
signal blk00000003_sig000000d2 : STD_LOGIC;
signal blk00000003_sig000000d1 : STD_LOGIC;
signal blk00000003_sig000000d0 : STD_LOGIC;
signal blk00000003_sig000000cf : STD_LOGIC;
signal blk00000003_sig000000ce : STD_LOGIC;
signal blk00000003_sig000000cd : STD_LOGIC;
signal blk00000003_sig000000cc : STD_LOGIC;
signal blk00000003_sig000000cb : STD_LOGIC;
signal blk00000003_sig000000ca : STD_LOGIC;
signal blk00000003_sig000000c9 : STD_LOGIC;
signal blk00000003_sig000000c8 : STD_LOGIC;
signal blk00000003_sig000000c7 : STD_LOGIC;
signal blk00000003_sig000000c6 : STD_LOGIC;
signal blk00000003_sig000000c5 : STD_LOGIC;
signal blk00000003_sig000000c4 : STD_LOGIC;
signal blk00000003_sig000000c3 : STD_LOGIC;
signal blk00000003_sig000000c2 : STD_LOGIC;
signal blk00000003_sig000000c1 : STD_LOGIC;
signal blk00000003_sig000000c0 : STD_LOGIC;
signal blk00000003_sig000000bf : STD_LOGIC;
signal blk00000003_sig000000be : STD_LOGIC;
signal blk00000003_sig000000bd : STD_LOGIC;
signal blk00000003_sig000000bc : STD_LOGIC;
signal blk00000003_sig000000bb : STD_LOGIC;
signal blk00000003_sig000000ba : STD_LOGIC;
signal blk00000003_sig000000b9 : STD_LOGIC;
signal blk00000003_sig000000b8 : STD_LOGIC;
signal blk00000003_sig000000b7 : STD_LOGIC;
signal blk00000003_sig000000b6 : STD_LOGIC;
signal blk00000003_sig000000b5 : STD_LOGIC;
signal blk00000003_sig000000b4 : STD_LOGIC;
signal blk00000003_sig000000b3 : STD_LOGIC;
signal blk00000003_sig000000b2 : STD_LOGIC;
signal blk00000003_sig000000b1 : STD_LOGIC;
signal blk00000003_sig000000b0 : STD_LOGIC;
signal blk00000003_sig000000af : STD_LOGIC;
signal blk00000003_sig000000ae : STD_LOGIC;
signal blk00000003_sig000000ad : STD_LOGIC;
signal blk00000003_sig000000ac : STD_LOGIC;
signal blk00000003_sig000000ab : STD_LOGIC;
signal blk00000003_sig000000aa : STD_LOGIC;
signal blk00000003_sig000000a9 : STD_LOGIC;
signal blk00000003_sig000000a8 : STD_LOGIC;
signal blk00000003_sig000000a7 : STD_LOGIC;
signal blk00000003_sig000000a6 : STD_LOGIC;
signal blk00000003_sig000000a5 : STD_LOGIC;
signal blk00000003_sig000000a4 : STD_LOGIC;
signal blk00000003_sig000000a3 : STD_LOGIC;
signal blk00000003_sig000000a2 : STD_LOGIC;
signal blk00000003_sig000000a1 : STD_LOGIC;
signal blk00000003_sig000000a0 : STD_LOGIC;
signal blk00000003_sig0000009f : STD_LOGIC;
signal blk00000003_sig0000009e : STD_LOGIC;
signal blk00000003_sig0000009d : STD_LOGIC;
signal blk00000003_sig0000009c : STD_LOGIC;
signal blk00000003_sig0000009b : STD_LOGIC;
signal blk00000003_sig0000009a : STD_LOGIC;
signal blk00000003_sig00000099 : STD_LOGIC;
signal blk00000003_sig00000098 : STD_LOGIC;
signal blk00000003_sig00000097 : STD_LOGIC;
signal blk00000003_sig00000096 : STD_LOGIC;
signal blk00000003_sig00000095 : STD_LOGIC;
signal blk00000003_sig00000094 : STD_LOGIC;
signal blk00000003_sig00000093 : STD_LOGIC;
signal blk00000003_sig00000092 : STD_LOGIC;
signal blk00000003_sig00000091 : STD_LOGIC;
signal blk00000003_sig00000090 : STD_LOGIC;
signal blk00000003_sig0000008f : STD_LOGIC;
signal blk00000003_sig0000008e : STD_LOGIC;
signal blk00000003_sig0000008d : STD_LOGIC;
signal blk00000003_sig0000008c : STD_LOGIC;
signal blk00000003_sig0000008b : STD_LOGIC;
signal blk00000003_sig0000008a : STD_LOGIC;
signal blk00000003_sig00000089 : STD_LOGIC;
signal blk00000003_sig00000088 : STD_LOGIC;
signal blk00000003_sig00000087 : STD_LOGIC;
signal blk00000003_sig00000086 : STD_LOGIC;
signal blk00000003_sig00000085 : STD_LOGIC;
signal blk00000003_sig00000084 : STD_LOGIC;
signal blk00000003_sig00000083 : STD_LOGIC;
signal blk00000003_sig00000082 : STD_LOGIC;
signal blk00000003_sig00000081 : STD_LOGIC;
signal blk00000003_sig00000080 : STD_LOGIC;
signal blk00000003_sig0000007f : STD_LOGIC;
signal blk00000003_sig0000007e : STD_LOGIC;
signal blk00000003_sig0000007d : STD_LOGIC;
signal blk00000003_sig0000007c : STD_LOGIC;
signal blk00000003_sig0000007b : STD_LOGIC;
signal blk00000003_sig0000007a : STD_LOGIC;
signal blk00000003_sig00000079 : STD_LOGIC;
signal blk00000003_sig00000078 : STD_LOGIC;
signal blk00000003_sig00000077 : STD_LOGIC;
signal blk00000003_sig00000076 : STD_LOGIC;
signal blk00000003_sig00000075 : STD_LOGIC;
signal blk00000003_sig00000074 : STD_LOGIC;
signal blk00000003_sig00000073 : STD_LOGIC;
signal blk00000003_sig00000072 : STD_LOGIC;
signal blk00000003_sig00000071 : STD_LOGIC;
signal blk00000003_sig00000070 : STD_LOGIC;
signal blk00000003_sig0000006f : STD_LOGIC;
signal blk00000003_sig0000006e : STD_LOGIC;
signal blk00000003_sig0000006d : STD_LOGIC;
signal blk00000003_sig0000006c : STD_LOGIC;
signal blk00000003_sig0000006b : STD_LOGIC;
signal blk00000003_sig0000006a : STD_LOGIC;
signal blk00000003_sig00000069 : STD_LOGIC;
signal blk00000003_sig00000068 : STD_LOGIC;
signal blk00000003_sig00000067 : STD_LOGIC;
signal blk00000003_sig00000066 : STD_LOGIC;
signal blk00000003_sig00000065 : STD_LOGIC;
signal blk00000003_sig00000064 : STD_LOGIC;
signal blk00000003_sig00000063 : STD_LOGIC;
signal blk00000003_sig00000062 : STD_LOGIC;
signal blk00000003_sig00000061 : STD_LOGIC;
signal blk00000003_sig00000060 : STD_LOGIC;
signal blk00000003_sig0000005f : STD_LOGIC;
signal blk00000003_sig0000005e : STD_LOGIC;
signal blk00000003_sig0000005d : STD_LOGIC;
signal blk00000003_sig0000005c : STD_LOGIC;
signal blk00000003_sig0000005b : STD_LOGIC;
signal blk00000003_sig0000005a : STD_LOGIC;
signal blk00000003_sig00000059 : STD_LOGIC;
signal blk00000003_sig00000058 : STD_LOGIC;
signal blk00000003_sig00000057 : STD_LOGIC;
signal blk00000003_sig00000056 : STD_LOGIC;
signal blk00000003_sig00000055 : STD_LOGIC;
signal blk00000003_sig00000054 : STD_LOGIC;
signal blk00000003_sig00000053 : STD_LOGIC;
signal blk00000003_sig00000052 : STD_LOGIC;
signal blk00000003_sig00000051 : STD_LOGIC;
signal blk00000003_sig00000050 : STD_LOGIC;
signal blk00000003_sig0000004f : STD_LOGIC;
signal blk00000003_sig0000004e : STD_LOGIC;
signal blk00000003_sig0000004d : STD_LOGIC;
signal blk00000003_sig0000004c : STD_LOGIC;
signal blk00000003_sig0000004b : STD_LOGIC;
signal blk00000003_sig0000004a : STD_LOGIC;
signal blk00000003_sig00000049 : STD_LOGIC;
signal blk00000003_sig00000048 : STD_LOGIC;
signal blk00000003_sig00000047 : STD_LOGIC;
signal blk00000003_sig00000046 : STD_LOGIC;
signal blk00000003_sig00000045 : STD_LOGIC;
signal blk00000003_sig00000044 : STD_LOGIC;
signal blk00000003_sig00000043 : STD_LOGIC;
signal blk00000003_sig00000042 : STD_LOGIC;
signal blk00000003_sig00000041 : STD_LOGIC;
signal blk00000003_sig00000040 : STD_LOGIC;
signal blk00000003_sig0000003f : STD_LOGIC;
signal blk00000003_sig0000003e : STD_LOGIC;
signal blk00000003_sig0000003d : STD_LOGIC;
signal blk00000003_sig0000003c : STD_LOGIC;
signal blk00000003_sig0000003b : STD_LOGIC;
signal blk00000003_sig0000003a : STD_LOGIC;
signal blk00000003_sig00000039 : STD_LOGIC;
signal blk00000003_sig00000038 : STD_LOGIC;
signal blk00000003_sig00000037 : STD_LOGIC;
signal blk00000003_sig00000036 : STD_LOGIC;
signal blk00000003_sig00000035 : STD_LOGIC;
signal blk00000003_sig00000034 : STD_LOGIC;
signal blk00000003_sig00000033 : STD_LOGIC;
signal blk00000003_sig00000032 : STD_LOGIC;
signal blk00000003_sig00000031 : STD_LOGIC;
signal blk00000003_sig00000030 : STD_LOGIC;
signal blk00000003_sig0000002f : STD_LOGIC;
signal blk00000003_sig0000002e : STD_LOGIC;
signal blk00000003_sig0000002d : STD_LOGIC;
signal blk00000003_sig0000002c : STD_LOGIC;
signal blk00000003_sig0000002b : STD_LOGIC;
signal blk00000003_sig0000002a : STD_LOGIC;
signal blk00000003_sig00000029 : STD_LOGIC;
signal blk00000003_sig00000028 : STD_LOGIC;
signal blk00000003_sig00000027 : STD_LOGIC;
signal blk00000003_sig00000026 : STD_LOGIC;
signal blk00000003_sig00000025 : STD_LOGIC;
signal blk00000003_sig00000024 : STD_LOGIC;
signal blk00000003_sig00000022 : STD_LOGIC;
signal NLW_blk00000001_P_UNCONNECTED : STD_LOGIC;
signal NLW_blk00000002_G_UNCONNECTED : STD_LOGIC;
signal dividend_0 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal divisor_1 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal quotient_2 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal fractional_3 : STD_LOGIC_VECTOR ( 7 downto 0 );
begin
dividend_0(7) <= dividend(7);
dividend_0(6) <= dividend(6);
dividend_0(5) <= dividend(5);
dividend_0(4) <= dividend(4);
dividend_0(3) <= dividend(3);
dividend_0(2) <= dividend(2);
dividend_0(1) <= dividend(1);
dividend_0(0) <= dividend(0);
quotient(7) <= quotient_2(7);
quotient(6) <= quotient_2(6);
quotient(5) <= quotient_2(5);
quotient(4) <= quotient_2(4);
quotient(3) <= quotient_2(3);
quotient(2) <= quotient_2(2);
quotient(1) <= quotient_2(1);
quotient(0) <= quotient_2(0);
divisor_1(7) <= divisor(7);
divisor_1(6) <= divisor(6);
divisor_1(5) <= divisor(5);
divisor_1(4) <= divisor(4);
divisor_1(3) <= divisor(3);
divisor_1(2) <= divisor(2);
divisor_1(1) <= divisor(1);
divisor_1(0) <= divisor(0);
rfd <= NlwRenamedSig_OI_rfd;
fractional(7) <= fractional_3(7);
fractional(6) <= fractional_3(6);
fractional(5) <= fractional_3(5);
fractional(4) <= fractional_3(4);
fractional(3) <= fractional_3(3);
fractional(2) <= fractional_3(2);
fractional(1) <= fractional_3(1);
fractional(0) <= fractional_3(0);
blk00000001 : VCC
port map (
P => NLW_blk00000001_P_UNCONNECTED
);
blk00000002 : GND
port map (
G => NLW_blk00000002_G_UNCONNECTED
);
blk00000003_blk00000264 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000272,
Q => blk00000003_sig000000dd
);
blk00000003_blk00000263 : SRL16
generic map(
INIT => X"0000"
)
port map (
A0 => blk00000003_sig00000022,
A1 => blk00000003_sig00000022,
A2 => blk00000003_sig00000022,
A3 => blk00000003_sig00000022,
CLK => clk,
D => blk00000003_sig0000026c,
Q => blk00000003_sig00000272
);
blk00000003_blk00000262 : SRL16
generic map(
INIT => X"0000"
)
port map (
A0 => NlwRenamedSig_OI_rfd,
A1 => blk00000003_sig00000022,
A2 => blk00000003_sig00000022,
A3 => blk00000003_sig00000022,
CLK => clk,
D => dividend_0(0),
Q => blk00000003_sig0000007f
);
blk00000003_blk00000261 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000271,
Q => blk00000003_sig000000e0
);
blk00000003_blk00000260 : SRL16
generic map(
INIT => X"0001"
)
port map (
A0 => blk00000003_sig00000022,
A1 => blk00000003_sig00000022,
A2 => blk00000003_sig00000022,
A3 => blk00000003_sig00000022,
CLK => clk,
D => divisor_1(0),
Q => blk00000003_sig00000271
);
blk00000003_blk0000025f : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000270,
Q => blk00000003_sig00000266
);
blk00000003_blk0000025e : SRL16
generic map(
INIT => X"0000"
)
port map (
A0 => blk00000003_sig00000022,
A1 => NlwRenamedSig_OI_rfd,
A2 => NlwRenamedSig_OI_rfd,
A3 => blk00000003_sig00000022,
CLK => clk,
D => blk00000003_sig00000041,
Q => blk00000003_sig00000270
);
blk00000003_blk0000025d : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000026f,
Q => blk00000003_sig00000264
);
blk00000003_blk0000025c : SRL16
generic map(
INIT => X"0000"
)
port map (
A0 => blk00000003_sig00000022,
A1 => NlwRenamedSig_OI_rfd,
A2 => NlwRenamedSig_OI_rfd,
A3 => blk00000003_sig00000022,
CLK => clk,
D => blk00000003_sig00000040,
Q => blk00000003_sig0000026f
);
blk00000003_blk0000025b : SRL16
generic map(
INIT => X"0000"
)
port map (
A0 => NlwRenamedSig_OI_rfd,
A1 => blk00000003_sig00000022,
A2 => blk00000003_sig00000022,
A3 => blk00000003_sig00000022,
CLK => clk,
D => blk00000003_sig0000026e,
Q => blk00000003_sig00000082
);
blk00000003_blk0000025a : MUXF5
port map (
I0 => dividend_0(3),
I1 => blk00000003_sig0000026d,
S => dividend_0(7),
O => blk00000003_sig0000026e
);
blk00000003_blk00000259 : LUT4
generic map(
INIT => X"5556"
)
port map (
I0 => dividend_0(3),
I1 => dividend_0(2),
I2 => dividend_0(1),
I3 => dividend_0(0),
O => blk00000003_sig0000026d
);
blk00000003_blk00000258 : MUXF5
port map (
I0 => divisor_1(3),
I1 => blk00000003_sig0000026b,
S => divisor_1(7),
O => blk00000003_sig0000026c
);
blk00000003_blk00000257 : LUT4
generic map(
INIT => X"5556"
)
port map (
I0 => divisor_1(3),
I1 => divisor_1(2),
I2 => divisor_1(1),
I3 => divisor_1(0),
O => blk00000003_sig0000026b
);
blk00000003_blk00000256 : INV
port map (
I => blk00000003_sig000000d9,
O => blk00000003_sig000000e4
);
blk00000003_blk00000255 : INV
port map (
I => blk00000003_sig000000da,
O => blk00000003_sig000000e7
);
blk00000003_blk00000254 : INV
port map (
I => blk00000003_sig000000db,
O => blk00000003_sig000000ea
);
blk00000003_blk00000253 : INV
port map (
I => blk00000003_sig000000dc,
O => blk00000003_sig000000ed
);
blk00000003_blk00000252 : INV
port map (
I => blk00000003_sig000000dd,
O => blk00000003_sig000000f0
);
blk00000003_blk00000251 : INV
port map (
I => blk00000003_sig000000de,
O => blk00000003_sig000000f3
);
blk00000003_blk00000250 : INV
port map (
I => blk00000003_sig000000df,
O => blk00000003_sig000000f6
);
blk00000003_blk0000024f : INV
port map (
I => blk00000003_sig0000004f,
O => blk00000003_sig00000088
);
blk00000003_blk0000024e : INV
port map (
I => blk00000003_sig0000004d,
O => blk00000003_sig0000008a
);
blk00000003_blk0000024d : INV
port map (
I => blk00000003_sig0000004b,
O => blk00000003_sig0000008c
);
blk00000003_blk0000024c : INV
port map (
I => blk00000003_sig00000049,
O => blk00000003_sig0000008e
);
blk00000003_blk0000024b : INV
port map (
I => blk00000003_sig00000047,
O => blk00000003_sig00000090
);
blk00000003_blk0000024a : INV
port map (
I => blk00000003_sig00000045,
O => blk00000003_sig00000092
);
blk00000003_blk00000249 : INV
port map (
I => blk00000003_sig00000043,
O => blk00000003_sig00000094
);
blk00000003_blk00000248 : INV
port map (
I => blk00000003_sig00000042,
O => blk00000003_sig000001fb
);
blk00000003_blk00000247 : INV
port map (
I => blk00000003_sig00000050,
O => blk00000003_sig000001d6
);
blk00000003_blk00000246 : INV
port map (
I => blk00000003_sig0000005a,
O => blk00000003_sig000001b1
);
blk00000003_blk00000245 : INV
port map (
I => blk00000003_sig00000063,
O => blk00000003_sig0000018c
);
blk00000003_blk00000244 : INV
port map (
I => blk00000003_sig0000006c,
O => blk00000003_sig00000167
);
blk00000003_blk00000243 : INV
port map (
I => blk00000003_sig00000075,
O => blk00000003_sig00000142
);
blk00000003_blk00000242 : INV
port map (
I => blk00000003_sig0000007e,
O => blk00000003_sig0000011d
);
blk00000003_blk00000241 : LUT3
generic map(
INIT => X"96"
)
port map (
I0 => blk00000003_sig00000264,
I1 => blk00000003_sig00000266,
I2 => blk00000003_sig0000008b,
O => blk00000003_sig00000239
);
blk00000003_blk00000240 : LUT3
generic map(
INIT => X"96"
)
port map (
I0 => blk00000003_sig00000264,
I1 => blk00000003_sig00000266,
I2 => blk00000003_sig0000008d,
O => blk00000003_sig0000023c
);
blk00000003_blk0000023f : LUT3
generic map(
INIT => X"96"
)
port map (
I0 => blk00000003_sig00000264,
I1 => blk00000003_sig00000266,
I2 => blk00000003_sig0000008f,
O => blk00000003_sig0000023f
);
blk00000003_blk0000023e : LUT3
generic map(
INIT => X"96"
)
port map (
I0 => blk00000003_sig00000264,
I1 => blk00000003_sig00000266,
I2 => blk00000003_sig00000091,
O => blk00000003_sig00000242
);
blk00000003_blk0000023d : LUT3
generic map(
INIT => X"96"
)
port map (
I0 => blk00000003_sig00000264,
I1 => blk00000003_sig00000266,
I2 => blk00000003_sig00000093,
O => blk00000003_sig00000245
);
blk00000003_blk0000023c : LUT3
generic map(
INIT => X"96"
)
port map (
I0 => blk00000003_sig00000264,
I1 => blk00000003_sig00000266,
I2 => blk00000003_sig00000095,
O => blk00000003_sig00000248
);
blk00000003_blk0000023b : LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => blk00000003_sig00000097,
I1 => blk00000003_sig00000266,
I2 => blk00000003_sig00000264,
I3 => blk00000003_sig0000024c,
O => blk00000003_sig0000024a
);
blk00000003_blk0000023a : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => blk00000003_sig0000022d,
I1 => blk00000003_sig00000264,
O => blk00000003_sig0000024e
);
blk00000003_blk00000239 : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => blk00000003_sig0000022e,
I1 => blk00000003_sig00000264,
O => blk00000003_sig00000251
);
blk00000003_blk00000238 : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => blk00000003_sig0000022f,
I1 => blk00000003_sig00000264,
O => blk00000003_sig00000254
);
blk00000003_blk00000237 : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => blk00000003_sig00000230,
I1 => blk00000003_sig00000264,
O => blk00000003_sig00000257
);
blk00000003_blk00000236 : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => blk00000003_sig00000231,
I1 => blk00000003_sig00000264,
O => blk00000003_sig0000025a
);
blk00000003_blk00000235 : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => blk00000003_sig00000232,
I1 => blk00000003_sig00000264,
O => blk00000003_sig0000025d
);
blk00000003_blk00000234 : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => blk00000003_sig00000233,
I1 => blk00000003_sig00000264,
O => blk00000003_sig00000260
);
blk00000003_blk00000233 : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => blk00000003_sig00000234,
I1 => blk00000003_sig00000264,
O => blk00000003_sig00000265
);
blk00000003_blk00000232 : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => blk00000003_sig00000089,
I1 => blk00000003_sig0000024c,
O => blk00000003_sig00000236
);
blk00000003_blk00000231 : LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => blk00000003_sig00000200,
I1 => blk00000003_sig0000009a,
I2 => blk00000003_sig000001ff,
O => blk00000003_sig00000209
);
blk00000003_blk00000230 : LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => blk00000003_sig00000201,
I1 => blk00000003_sig0000009c,
I2 => blk00000003_sig000001ff,
O => blk00000003_sig0000020c
);
blk00000003_blk0000022f : LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => blk00000003_sig00000202,
I1 => blk00000003_sig0000009e,
I2 => blk00000003_sig000001ff,
O => blk00000003_sig0000020f
);
blk00000003_blk0000022e : LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => blk00000003_sig00000203,
I1 => blk00000003_sig000000a0,
I2 => blk00000003_sig000001ff,
O => blk00000003_sig00000212
);
blk00000003_blk0000022d : LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => blk00000003_sig00000204,
I1 => blk00000003_sig000000a2,
I2 => blk00000003_sig000001ff,
O => blk00000003_sig00000215
);
blk00000003_blk0000022c : LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => blk00000003_sig00000205,
I1 => blk00000003_sig000000a4,
I2 => blk00000003_sig000001ff,
O => blk00000003_sig00000218
);
blk00000003_blk0000022b : LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => blk00000003_sig00000206,
I1 => blk00000003_sig000000a6,
I2 => blk00000003_sig000001ff,
O => blk00000003_sig0000021b
);
blk00000003_blk0000022a : LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => blk00000003_sig00000207,
I1 => blk00000003_sig000000a8,
I2 => blk00000003_sig000001ff,
O => blk00000003_sig00000228
);
blk00000003_blk00000229 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => blk00000003_sig000001f9,
I1 => blk00000003_sig00000042,
O => blk00000003_sig000001db
);
blk00000003_blk00000228 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000001f2,
I1 => blk00000003_sig00000099,
I2 => blk00000003_sig00000042,
O => blk00000003_sig000001de
);
blk00000003_blk00000227 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000001f3,
I1 => blk00000003_sig0000009b,
I2 => blk00000003_sig00000042,
O => blk00000003_sig000001e1
);
blk00000003_blk00000226 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000001f4,
I1 => blk00000003_sig0000009d,
I2 => blk00000003_sig00000042,
O => blk00000003_sig000001e4
);
blk00000003_blk00000225 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000001f5,
I1 => blk00000003_sig0000009f,
I2 => blk00000003_sig00000042,
O => blk00000003_sig000001e7
);
blk00000003_blk00000224 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000001f6,
I1 => blk00000003_sig000000a1,
I2 => blk00000003_sig00000042,
O => blk00000003_sig000001ea
);
blk00000003_blk00000223 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000001f7,
I1 => blk00000003_sig000000a3,
I2 => blk00000003_sig00000042,
O => blk00000003_sig000001ed
);
blk00000003_blk00000222 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000001f8,
I1 => blk00000003_sig000000a5,
I2 => blk00000003_sig00000042,
O => blk00000003_sig000001f0
);
blk00000003_blk00000221 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000087,
I1 => blk00000003_sig000000a7,
I2 => blk00000003_sig00000042,
O => blk00000003_sig000001fc
);
blk00000003_blk00000220 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => blk00000003_sig000001d4,
I1 => blk00000003_sig00000050,
O => blk00000003_sig000001b6
);
blk00000003_blk0000021f : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000001cd,
I1 => blk00000003_sig000000a9,
I2 => blk00000003_sig00000050,
O => blk00000003_sig000001b9
);
blk00000003_blk0000021e : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000001ce,
I1 => blk00000003_sig000000aa,
I2 => blk00000003_sig00000050,
O => blk00000003_sig000001bc
);
blk00000003_blk0000021d : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000001cf,
I1 => blk00000003_sig000000ab,
I2 => blk00000003_sig00000050,
O => blk00000003_sig000001bf
);
blk00000003_blk0000021c : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000001d0,
I1 => blk00000003_sig000000ac,
I2 => blk00000003_sig00000050,
O => blk00000003_sig000001c2
);
blk00000003_blk0000021b : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000001d1,
I1 => blk00000003_sig000000ad,
I2 => blk00000003_sig00000050,
O => blk00000003_sig000001c5
);
blk00000003_blk0000021a : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000001d2,
I1 => blk00000003_sig000000ae,
I2 => blk00000003_sig00000050,
O => blk00000003_sig000001c8
);
blk00000003_blk00000219 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000001d3,
I1 => blk00000003_sig000000af,
I2 => blk00000003_sig00000050,
O => blk00000003_sig000001cb
);
blk00000003_blk00000218 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000059,
I1 => blk00000003_sig000000b0,
I2 => blk00000003_sig00000050,
O => blk00000003_sig000001d7
);
blk00000003_blk00000217 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => blk00000003_sig000001af,
I1 => blk00000003_sig0000005a,
O => blk00000003_sig00000191
);
blk00000003_blk00000216 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000001a8,
I1 => blk00000003_sig000000b1,
I2 => blk00000003_sig0000005a,
O => blk00000003_sig00000194
);
blk00000003_blk00000215 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000001a9,
I1 => blk00000003_sig000000b2,
I2 => blk00000003_sig0000005a,
O => blk00000003_sig00000197
);
blk00000003_blk00000214 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000001aa,
I1 => blk00000003_sig000000b3,
I2 => blk00000003_sig0000005a,
O => blk00000003_sig0000019a
);
blk00000003_blk00000213 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000001ab,
I1 => blk00000003_sig000000b4,
I2 => blk00000003_sig0000005a,
O => blk00000003_sig0000019d
);
blk00000003_blk00000212 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000001ac,
I1 => blk00000003_sig000000b5,
I2 => blk00000003_sig0000005a,
O => blk00000003_sig000001a0
);
blk00000003_blk00000211 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000001ad,
I1 => blk00000003_sig000000b6,
I2 => blk00000003_sig0000005a,
O => blk00000003_sig000001a3
);
blk00000003_blk00000210 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig000001ae,
I1 => blk00000003_sig000000b7,
I2 => blk00000003_sig0000005a,
O => blk00000003_sig000001a6
);
blk00000003_blk0000020f : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000062,
I1 => blk00000003_sig000000b8,
I2 => blk00000003_sig0000005a,
O => blk00000003_sig000001b2
);
blk00000003_blk0000020e : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => blk00000003_sig0000018a,
I1 => blk00000003_sig00000063,
O => blk00000003_sig0000016c
);
blk00000003_blk0000020d : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000183,
I1 => blk00000003_sig000000b9,
I2 => blk00000003_sig00000063,
O => blk00000003_sig0000016f
);
blk00000003_blk0000020c : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000184,
I1 => blk00000003_sig000000ba,
I2 => blk00000003_sig00000063,
O => blk00000003_sig00000172
);
blk00000003_blk0000020b : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000185,
I1 => blk00000003_sig000000bb,
I2 => blk00000003_sig00000063,
O => blk00000003_sig00000175
);
blk00000003_blk0000020a : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000186,
I1 => blk00000003_sig000000bc,
I2 => blk00000003_sig00000063,
O => blk00000003_sig00000178
);
blk00000003_blk00000209 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000187,
I1 => blk00000003_sig000000bd,
I2 => blk00000003_sig00000063,
O => blk00000003_sig0000017b
);
blk00000003_blk00000208 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000188,
I1 => blk00000003_sig000000be,
I2 => blk00000003_sig00000063,
O => blk00000003_sig0000017e
);
blk00000003_blk00000207 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000189,
I1 => blk00000003_sig000000bf,
I2 => blk00000003_sig00000063,
O => blk00000003_sig00000181
);
blk00000003_blk00000206 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000006b,
I1 => blk00000003_sig000000c0,
I2 => blk00000003_sig00000063,
O => blk00000003_sig0000018d
);
blk00000003_blk00000205 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => blk00000003_sig00000165,
I1 => blk00000003_sig0000006c,
O => blk00000003_sig00000147
);
blk00000003_blk00000204 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000015e,
I1 => blk00000003_sig000000c1,
I2 => blk00000003_sig0000006c,
O => blk00000003_sig0000014a
);
blk00000003_blk00000203 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000015f,
I1 => blk00000003_sig000000c2,
I2 => blk00000003_sig0000006c,
O => blk00000003_sig0000014d
);
blk00000003_blk00000202 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000160,
I1 => blk00000003_sig000000c3,
I2 => blk00000003_sig0000006c,
O => blk00000003_sig00000150
);
blk00000003_blk00000201 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000161,
I1 => blk00000003_sig000000c4,
I2 => blk00000003_sig0000006c,
O => blk00000003_sig00000153
);
blk00000003_blk00000200 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000162,
I1 => blk00000003_sig000000c5,
I2 => blk00000003_sig0000006c,
O => blk00000003_sig00000156
);
blk00000003_blk000001ff : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000163,
I1 => blk00000003_sig000000c6,
I2 => blk00000003_sig0000006c,
O => blk00000003_sig00000159
);
blk00000003_blk000001fe : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000164,
I1 => blk00000003_sig000000c7,
I2 => blk00000003_sig0000006c,
O => blk00000003_sig0000015c
);
blk00000003_blk000001fd : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000074,
I1 => blk00000003_sig000000c8,
I2 => blk00000003_sig0000006c,
O => blk00000003_sig00000168
);
blk00000003_blk000001fc : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => blk00000003_sig00000140,
I1 => blk00000003_sig00000075,
O => blk00000003_sig00000122
);
blk00000003_blk000001fb : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000139,
I1 => blk00000003_sig000000c9,
I2 => blk00000003_sig00000075,
O => blk00000003_sig00000125
);
blk00000003_blk000001fa : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000013a,
I1 => blk00000003_sig000000ca,
I2 => blk00000003_sig00000075,
O => blk00000003_sig00000128
);
blk00000003_blk000001f9 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000013b,
I1 => blk00000003_sig000000cb,
I2 => blk00000003_sig00000075,
O => blk00000003_sig0000012b
);
blk00000003_blk000001f8 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000013c,
I1 => blk00000003_sig000000cc,
I2 => blk00000003_sig00000075,
O => blk00000003_sig0000012e
);
blk00000003_blk000001f7 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000013d,
I1 => blk00000003_sig000000cd,
I2 => blk00000003_sig00000075,
O => blk00000003_sig00000131
);
blk00000003_blk000001f6 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000013e,
I1 => blk00000003_sig000000ce,
I2 => blk00000003_sig00000075,
O => blk00000003_sig00000134
);
blk00000003_blk000001f5 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000013f,
I1 => blk00000003_sig000000cf,
I2 => blk00000003_sig00000075,
O => blk00000003_sig00000137
);
blk00000003_blk000001f4 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000007d,
I1 => blk00000003_sig000000d0,
I2 => blk00000003_sig00000075,
O => blk00000003_sig00000143
);
blk00000003_blk000001f3 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => blk00000003_sig0000011b,
I1 => blk00000003_sig0000007e,
O => blk00000003_sig000000fd
);
blk00000003_blk000001f2 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000114,
I1 => blk00000003_sig000000d1,
I2 => blk00000003_sig0000007e,
O => blk00000003_sig00000100
);
blk00000003_blk000001f1 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000115,
I1 => blk00000003_sig000000d2,
I2 => blk00000003_sig0000007e,
O => blk00000003_sig00000103
);
blk00000003_blk000001f0 : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000116,
I1 => blk00000003_sig000000d3,
I2 => blk00000003_sig0000007e,
O => blk00000003_sig00000106
);
blk00000003_blk000001ef : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000117,
I1 => blk00000003_sig000000d4,
I2 => blk00000003_sig0000007e,
O => blk00000003_sig00000109
);
blk00000003_blk000001ee : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000118,
I1 => blk00000003_sig000000d5,
I2 => blk00000003_sig0000007e,
O => blk00000003_sig0000010c
);
blk00000003_blk000001ed : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000119,
I1 => blk00000003_sig000000d6,
I2 => blk00000003_sig0000007e,
O => blk00000003_sig0000010f
);
blk00000003_blk000001ec : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig0000011a,
I1 => blk00000003_sig000000d7,
I2 => blk00000003_sig0000007e,
O => blk00000003_sig00000112
);
blk00000003_blk000001eb : LUT3
generic map(
INIT => X"69"
)
port map (
I0 => blk00000003_sig00000086,
I1 => blk00000003_sig000000d8,
I2 => blk00000003_sig0000007e,
O => blk00000003_sig0000011e
);
blk00000003_blk000001ea : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => blk00000003_sig00000098,
I1 => blk00000003_sig000000e0,
O => blk00000003_sig000000f9
);
blk00000003_blk000001e9 : LUT1
generic map(
INIT => X"1"
)
port map (
I0 => blk00000003_sig000001ff,
O => blk00000003_sig00000096
);
blk00000003_blk000001e8 : LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => blk00000003_sig00000269,
I1 => divisor_1(4),
I2 => divisor_1(5),
O => blk00000003_sig0000026a
);
blk00000003_blk000001e7 : LUT3
generic map(
INIT => X"04"
)
port map (
I0 => divisor_1(6),
I1 => divisor_1(7),
I2 => blk00000003_sig0000026a,
O => blk00000003_sig00000034
);
blk00000003_blk000001e6 : LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => divisor_1(6),
I1 => divisor_1(7),
I2 => blk00000003_sig0000026a,
O => blk00000003_sig00000036
);
blk00000003_blk000001e5 : LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => divisor_1(1),
I1 => divisor_1(7),
I2 => divisor_1(0),
O => blk00000003_sig0000003e
);
blk00000003_blk000001e4 : LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => divisor_1(4),
I1 => divisor_1(7),
I2 => blk00000003_sig00000269,
O => blk00000003_sig0000003a
);
blk00000003_blk000001e3 : LUT4
generic map(
INIT => X"666A"
)
port map (
I0 => divisor_1(5),
I1 => divisor_1(7),
I2 => divisor_1(4),
I3 => blk00000003_sig00000269,
O => blk00000003_sig00000038
);
blk00000003_blk000001e2 : LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => divisor_1(1),
I1 => divisor_1(2),
I2 => divisor_1(0),
I3 => divisor_1(3),
O => blk00000003_sig00000269
);
blk00000003_blk000001e1 : LUT4
generic map(
INIT => X"666A"
)
port map (
I0 => divisor_1(2),
I1 => divisor_1(7),
I2 => divisor_1(1),
I3 => divisor_1(0),
O => blk00000003_sig0000003c
);
blk00000003_blk000001e0 : LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => blk00000003_sig00000267,
I1 => dividend_0(4),
I2 => dividend_0(5),
O => blk00000003_sig00000268
);
blk00000003_blk000001df : LUT3
generic map(
INIT => X"04"
)
port map (
I0 => dividend_0(6),
I1 => dividend_0(7),
I2 => blk00000003_sig00000268,
O => blk00000003_sig00000028
);
blk00000003_blk000001de : LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => dividend_0(6),
I1 => dividend_0(7),
I2 => blk00000003_sig00000268,
O => blk00000003_sig0000002a
);
blk00000003_blk000001dd : LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => dividend_0(1),
I1 => dividend_0(7),
I2 => dividend_0(0),
O => blk00000003_sig00000032
);
blk00000003_blk000001dc : LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => dividend_0(4),
I1 => dividend_0(7),
I2 => blk00000003_sig00000267,
O => blk00000003_sig0000002e
);
blk00000003_blk000001db : LUT4
generic map(
INIT => X"666A"
)
port map (
I0 => dividend_0(5),
I1 => dividend_0(7),
I2 => dividend_0(4),
I3 => blk00000003_sig00000267,
O => blk00000003_sig0000002c
);
blk00000003_blk000001da : LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => dividend_0(1),
I1 => dividend_0(2),
I2 => dividend_0(0),
I3 => dividend_0(3),
O => blk00000003_sig00000267
);
blk00000003_blk000001d9 : LUT4
generic map(
INIT => X"666A"
)
port map (
I0 => dividend_0(2),
I1 => dividend_0(7),
I2 => dividend_0(1),
I3 => dividend_0(0),
O => blk00000003_sig00000030
);
blk00000003_blk000001d8 : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => blk00000003_sig00000266,
I1 => blk00000003_sig00000264,
O => blk00000003_sig0000024c
);
blk00000003_blk000001d7 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000263,
Q => fractional_3(0)
);
blk00000003_blk000001d6 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000261,
Q => fractional_3(1)
);
blk00000003_blk000001d5 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000025e,
Q => fractional_3(2)
);
blk00000003_blk000001d4 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000025b,
Q => fractional_3(3)
);
blk00000003_blk000001d3 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000258,
Q => fractional_3(4)
);
blk00000003_blk000001d2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000255,
Q => fractional_3(5)
);
blk00000003_blk000001d1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000252,
Q => fractional_3(6)
);
blk00000003_blk000001d0 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000024f,
Q => fractional_3(7)
);
blk00000003_blk000001cf : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => blk00000003_sig00000264,
I1 => blk00000003_sig00000265,
O => blk00000003_sig00000262
);
blk00000003_blk000001ce : MUXCY
port map (
CI => blk00000003_sig00000022,
DI => blk00000003_sig00000264,
S => blk00000003_sig00000262,
O => blk00000003_sig0000025f
);
blk00000003_blk000001cd : XORCY
port map (
CI => blk00000003_sig00000022,
LI => blk00000003_sig00000262,
O => blk00000003_sig00000263
);
blk00000003_blk000001cc : MUXCY
port map (
CI => blk00000003_sig0000025f,
DI => blk00000003_sig00000022,
S => blk00000003_sig00000260,
O => blk00000003_sig0000025c
);
blk00000003_blk000001cb : XORCY
port map (
CI => blk00000003_sig0000025f,
LI => blk00000003_sig00000260,
O => blk00000003_sig00000261
);
blk00000003_blk000001ca : MUXCY
port map (
CI => blk00000003_sig0000025c,
DI => blk00000003_sig00000022,
S => blk00000003_sig0000025d,
O => blk00000003_sig00000259
);
blk00000003_blk000001c9 : XORCY
port map (
CI => blk00000003_sig0000025c,
LI => blk00000003_sig0000025d,
O => blk00000003_sig0000025e
);
blk00000003_blk000001c8 : MUXCY
port map (
CI => blk00000003_sig00000259,
DI => blk00000003_sig00000022,
S => blk00000003_sig0000025a,
O => blk00000003_sig00000256
);
blk00000003_blk000001c7 : XORCY
port map (
CI => blk00000003_sig00000259,
LI => blk00000003_sig0000025a,
O => blk00000003_sig0000025b
);
blk00000003_blk000001c6 : MUXCY
port map (
CI => blk00000003_sig00000256,
DI => blk00000003_sig00000022,
S => blk00000003_sig00000257,
O => blk00000003_sig00000253
);
blk00000003_blk000001c5 : XORCY
port map (
CI => blk00000003_sig00000256,
LI => blk00000003_sig00000257,
O => blk00000003_sig00000258
);
blk00000003_blk000001c4 : MUXCY
port map (
CI => blk00000003_sig00000253,
DI => blk00000003_sig00000022,
S => blk00000003_sig00000254,
O => blk00000003_sig00000250
);
blk00000003_blk000001c3 : XORCY
port map (
CI => blk00000003_sig00000253,
LI => blk00000003_sig00000254,
O => blk00000003_sig00000255
);
blk00000003_blk000001c2 : MUXCY
port map (
CI => blk00000003_sig00000250,
DI => blk00000003_sig00000022,
S => blk00000003_sig00000251,
O => blk00000003_sig0000024d
);
blk00000003_blk000001c1 : XORCY
port map (
CI => blk00000003_sig00000250,
LI => blk00000003_sig00000251,
O => blk00000003_sig00000252
);
blk00000003_blk000001c0 : XORCY
port map (
CI => blk00000003_sig0000024d,
LI => blk00000003_sig0000024e,
O => blk00000003_sig0000024f
);
blk00000003_blk000001bf : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000024b,
Q => quotient_2(0)
);
blk00000003_blk000001be : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000249,
Q => quotient_2(1)
);
blk00000003_blk000001bd : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000246,
Q => quotient_2(2)
);
blk00000003_blk000001bc : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000243,
Q => quotient_2(3)
);
blk00000003_blk000001bb : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000240,
Q => quotient_2(4)
);
blk00000003_blk000001ba : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000023d,
Q => quotient_2(5)
);
blk00000003_blk000001b9 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000023a,
Q => quotient_2(6)
);
blk00000003_blk000001b8 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000237,
Q => quotient_2(7)
);
blk00000003_blk000001b7 : MUXCY
port map (
CI => blk00000003_sig00000022,
DI => blk00000003_sig0000024c,
S => blk00000003_sig0000024a,
O => blk00000003_sig00000247
);
blk00000003_blk000001b6 : XORCY
port map (
CI => blk00000003_sig00000022,
LI => blk00000003_sig0000024a,
O => blk00000003_sig0000024b
);
blk00000003_blk000001b5 : MUXCY
port map (
CI => blk00000003_sig00000247,
DI => blk00000003_sig00000022,
S => blk00000003_sig00000248,
O => blk00000003_sig00000244
);
blk00000003_blk000001b4 : XORCY
port map (
CI => blk00000003_sig00000247,
LI => blk00000003_sig00000248,
O => blk00000003_sig00000249
);
blk00000003_blk000001b3 : MUXCY
port map (
CI => blk00000003_sig00000244,
DI => blk00000003_sig00000022,
S => blk00000003_sig00000245,
O => blk00000003_sig00000241
);
blk00000003_blk000001b2 : XORCY
port map (
CI => blk00000003_sig00000244,
LI => blk00000003_sig00000245,
O => blk00000003_sig00000246
);
blk00000003_blk000001b1 : MUXCY
port map (
CI => blk00000003_sig00000241,
DI => blk00000003_sig00000022,
S => blk00000003_sig00000242,
O => blk00000003_sig0000023e
);
blk00000003_blk000001b0 : XORCY
port map (
CI => blk00000003_sig00000241,
LI => blk00000003_sig00000242,
O => blk00000003_sig00000243
);
blk00000003_blk000001af : MUXCY
port map (
CI => blk00000003_sig0000023e,
DI => blk00000003_sig00000022,
S => blk00000003_sig0000023f,
O => blk00000003_sig0000023b
);
blk00000003_blk000001ae : XORCY
port map (
CI => blk00000003_sig0000023e,
LI => blk00000003_sig0000023f,
O => blk00000003_sig00000240
);
blk00000003_blk000001ad : MUXCY
port map (
CI => blk00000003_sig0000023b,
DI => blk00000003_sig00000022,
S => blk00000003_sig0000023c,
O => blk00000003_sig00000238
);
blk00000003_blk000001ac : XORCY
port map (
CI => blk00000003_sig0000023b,
LI => blk00000003_sig0000023c,
O => blk00000003_sig0000023d
);
blk00000003_blk000001ab : MUXCY
port map (
CI => blk00000003_sig00000238,
DI => blk00000003_sig00000022,
S => blk00000003_sig00000239,
O => blk00000003_sig00000235
);
blk00000003_blk000001aa : XORCY
port map (
CI => blk00000003_sig00000238,
LI => blk00000003_sig00000239,
O => blk00000003_sig0000023a
);
blk00000003_blk000001a9 : XORCY
port map (
CI => blk00000003_sig00000235,
LI => blk00000003_sig00000236,
O => blk00000003_sig00000237
);
blk00000003_blk000001a8 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000229,
Q => blk00000003_sig00000234
);
blk00000003_blk000001a7 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000021c,
Q => blk00000003_sig00000233
);
blk00000003_blk000001a6 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000219,
Q => blk00000003_sig00000232
);
blk00000003_blk000001a5 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000216,
Q => blk00000003_sig00000231
);
blk00000003_blk000001a4 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000213,
Q => blk00000003_sig00000230
);
blk00000003_blk000001a3 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000210,
Q => blk00000003_sig0000022f
);
blk00000003_blk000001a2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000020d,
Q => blk00000003_sig0000022e
);
blk00000003_blk000001a1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000020a,
Q => blk00000003_sig0000022d
);
blk00000003_blk000001a0 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000021e,
Q => blk00000003_sig0000022c
);
blk00000003_blk0000019f : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000220,
Q => blk00000003_sig0000022b
);
blk00000003_blk0000019e : MULT_AND
port map (
I0 => blk00000003_sig000000a8,
I1 => blk00000003_sig000001ff,
LO => blk00000003_sig0000022a
);
blk00000003_blk0000019d : MULT_AND
port map (
I0 => blk00000003_sig000000a6,
I1 => blk00000003_sig000001ff,
LO => blk00000003_sig00000227
);
blk00000003_blk0000019c : MULT_AND
port map (
I0 => blk00000003_sig000000a4,
I1 => blk00000003_sig000001ff,
LO => blk00000003_sig00000226
);
blk00000003_blk0000019b : MULT_AND
port map (
I0 => blk00000003_sig000000a2,
I1 => blk00000003_sig000001ff,
LO => blk00000003_sig00000225
);
blk00000003_blk0000019a : MULT_AND
port map (
I0 => blk00000003_sig000000a0,
I1 => blk00000003_sig000001ff,
LO => blk00000003_sig00000224
);
blk00000003_blk00000199 : MULT_AND
port map (
I0 => blk00000003_sig0000009e,
I1 => blk00000003_sig000001ff,
LO => blk00000003_sig00000223
);
blk00000003_blk00000198 : MULT_AND
port map (
I0 => blk00000003_sig0000009c,
I1 => blk00000003_sig000001ff,
LO => blk00000003_sig00000222
);
blk00000003_blk00000197 : MULT_AND
port map (
I0 => blk00000003_sig0000009a,
I1 => blk00000003_sig000001ff,
LO => blk00000003_sig00000221
);
blk00000003_blk00000196 : MULT_AND
port map (
I0 => blk00000003_sig00000022,
I1 => blk00000003_sig000001ff,
LO => blk00000003_sig0000021f
);
blk00000003_blk00000195 : MUXCY
port map (
CI => blk00000003_sig00000022,
DI => blk00000003_sig0000022a,
S => blk00000003_sig00000228,
O => blk00000003_sig0000021a
);
blk00000003_blk00000194 : XORCY
port map (
CI => blk00000003_sig00000022,
LI => blk00000003_sig00000228,
O => blk00000003_sig00000229
);
blk00000003_blk00000193 : MUXCY
port map (
CI => blk00000003_sig0000021a,
DI => blk00000003_sig00000227,
S => blk00000003_sig0000021b,
O => blk00000003_sig00000217
);
blk00000003_blk00000192 : MUXCY
port map (
CI => blk00000003_sig00000217,
DI => blk00000003_sig00000226,
S => blk00000003_sig00000218,
O => blk00000003_sig00000214
);
blk00000003_blk00000191 : MUXCY
port map (
CI => blk00000003_sig00000214,
DI => blk00000003_sig00000225,
S => blk00000003_sig00000215,
O => blk00000003_sig00000211
);
blk00000003_blk00000190 : MUXCY
port map (
CI => blk00000003_sig00000211,
DI => blk00000003_sig00000224,
S => blk00000003_sig00000212,
O => blk00000003_sig0000020e
);
blk00000003_blk0000018f : MUXCY
port map (
CI => blk00000003_sig0000020e,
DI => blk00000003_sig00000223,
S => blk00000003_sig0000020f,
O => blk00000003_sig0000020b
);
blk00000003_blk0000018e : MUXCY
port map (
CI => blk00000003_sig0000020b,
DI => blk00000003_sig00000222,
S => blk00000003_sig0000020c,
O => blk00000003_sig00000208
);
blk00000003_blk0000018d : MUXCY
port map (
CI => blk00000003_sig00000208,
DI => blk00000003_sig00000221,
S => blk00000003_sig00000209,
O => blk00000003_sig0000021d
);
blk00000003_blk0000018c : MUXCY
port map (
CI => blk00000003_sig0000021d,
DI => blk00000003_sig0000021f,
S => blk00000003_sig00000022,
O => blk00000003_sig00000220
);
blk00000003_blk0000018b : XORCY
port map (
CI => blk00000003_sig0000021d,
LI => blk00000003_sig00000022,
O => blk00000003_sig0000021e
);
blk00000003_blk0000018a : XORCY
port map (
CI => blk00000003_sig0000021a,
LI => blk00000003_sig0000021b,
O => blk00000003_sig0000021c
);
blk00000003_blk00000189 : XORCY
port map (
CI => blk00000003_sig00000217,
LI => blk00000003_sig00000218,
O => blk00000003_sig00000219
);
blk00000003_blk00000188 : XORCY
port map (
CI => blk00000003_sig00000214,
LI => blk00000003_sig00000215,
O => blk00000003_sig00000216
);
blk00000003_blk00000187 : XORCY
port map (
CI => blk00000003_sig00000211,
LI => blk00000003_sig00000212,
O => blk00000003_sig00000213
);
blk00000003_blk00000186 : XORCY
port map (
CI => blk00000003_sig0000020e,
LI => blk00000003_sig0000020f,
O => blk00000003_sig00000210
);
blk00000003_blk00000185 : XORCY
port map (
CI => blk00000003_sig0000020b,
LI => blk00000003_sig0000020c,
O => blk00000003_sig0000020d
);
blk00000003_blk00000184 : XORCY
port map (
CI => blk00000003_sig00000208,
LI => blk00000003_sig00000209,
O => blk00000003_sig0000020a
);
blk00000003_blk00000183 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000000fa,
Q => blk00000003_sig0000011a
);
blk00000003_blk00000182 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000000f7,
Q => blk00000003_sig00000119
);
blk00000003_blk00000181 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000000f4,
Q => blk00000003_sig00000118
);
blk00000003_blk00000180 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000000f1,
Q => blk00000003_sig00000117
);
blk00000003_blk0000017f : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000000ee,
Q => blk00000003_sig00000116
);
blk00000003_blk0000017e : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000000eb,
Q => blk00000003_sig00000115
);
blk00000003_blk0000017d : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000000e8,
Q => blk00000003_sig00000114
);
blk00000003_blk0000017c : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000000e5,
Q => blk00000003_sig0000011b
);
blk00000003_blk0000017b : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000000e2,
Q => blk00000003_sig0000007e
);
blk00000003_blk0000017a : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000011f,
Q => blk00000003_sig0000013f
);
blk00000003_blk00000179 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000113,
Q => blk00000003_sig0000013e
);
blk00000003_blk00000178 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000110,
Q => blk00000003_sig0000013d
);
blk00000003_blk00000177 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000010d,
Q => blk00000003_sig0000013c
);
blk00000003_blk00000176 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000010a,
Q => blk00000003_sig0000013b
);
blk00000003_blk00000175 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000107,
Q => blk00000003_sig0000013a
);
blk00000003_blk00000174 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000104,
Q => blk00000003_sig00000139
);
blk00000003_blk00000173 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000101,
Q => blk00000003_sig00000140
);
blk00000003_blk00000172 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000000fe,
Q => blk00000003_sig00000075
);
blk00000003_blk00000171 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000144,
Q => blk00000003_sig00000164
);
blk00000003_blk00000170 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000138,
Q => blk00000003_sig00000163
);
blk00000003_blk0000016f : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000135,
Q => blk00000003_sig00000162
);
blk00000003_blk0000016e : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000132,
Q => blk00000003_sig00000161
);
blk00000003_blk0000016d : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000012f,
Q => blk00000003_sig00000160
);
blk00000003_blk0000016c : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000012c,
Q => blk00000003_sig0000015f
);
blk00000003_blk0000016b : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000129,
Q => blk00000003_sig0000015e
);
blk00000003_blk0000016a : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000126,
Q => blk00000003_sig00000165
);
blk00000003_blk00000169 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000123,
Q => blk00000003_sig0000006c
);
blk00000003_blk00000168 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000169,
Q => blk00000003_sig00000189
);
blk00000003_blk00000167 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000015d,
Q => blk00000003_sig00000188
);
blk00000003_blk00000166 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000015a,
Q => blk00000003_sig00000187
);
blk00000003_blk00000165 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000157,
Q => blk00000003_sig00000186
);
blk00000003_blk00000164 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000154,
Q => blk00000003_sig00000185
);
blk00000003_blk00000163 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000151,
Q => blk00000003_sig00000184
);
blk00000003_blk00000162 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000014e,
Q => blk00000003_sig00000183
);
blk00000003_blk00000161 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000014b,
Q => blk00000003_sig0000018a
);
blk00000003_blk00000160 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000148,
Q => blk00000003_sig00000063
);
blk00000003_blk0000015f : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000018e,
Q => blk00000003_sig000001ae
);
blk00000003_blk0000015e : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000182,
Q => blk00000003_sig000001ad
);
blk00000003_blk0000015d : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000017f,
Q => blk00000003_sig000001ac
);
blk00000003_blk0000015c : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000017c,
Q => blk00000003_sig000001ab
);
blk00000003_blk0000015b : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000179,
Q => blk00000003_sig000001aa
);
blk00000003_blk0000015a : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000176,
Q => blk00000003_sig000001a9
);
blk00000003_blk00000159 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000173,
Q => blk00000003_sig000001a8
);
blk00000003_blk00000158 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000170,
Q => blk00000003_sig000001af
);
blk00000003_blk00000157 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000016d,
Q => blk00000003_sig0000005a
);
blk00000003_blk00000156 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000001b3,
Q => blk00000003_sig000001d3
);
blk00000003_blk00000155 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000001a7,
Q => blk00000003_sig000001d2
);
blk00000003_blk00000154 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000001a4,
Q => blk00000003_sig000001d1
);
blk00000003_blk00000153 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000001a1,
Q => blk00000003_sig000001d0
);
blk00000003_blk00000152 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000019e,
Q => blk00000003_sig000001cf
);
blk00000003_blk00000151 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000019b,
Q => blk00000003_sig000001ce
);
blk00000003_blk00000150 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000198,
Q => blk00000003_sig000001cd
);
blk00000003_blk0000014f : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000195,
Q => blk00000003_sig000001d4
);
blk00000003_blk0000014e : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000192,
Q => blk00000003_sig00000050
);
blk00000003_blk0000014d : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000001d8,
Q => blk00000003_sig000001f8
);
blk00000003_blk0000014c : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000001cc,
Q => blk00000003_sig000001f7
);
blk00000003_blk0000014b : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000001c9,
Q => blk00000003_sig000001f6
);
blk00000003_blk0000014a : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000001c6,
Q => blk00000003_sig000001f5
);
blk00000003_blk00000149 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000001c3,
Q => blk00000003_sig000001f4
);
blk00000003_blk00000148 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000001c0,
Q => blk00000003_sig000001f3
);
blk00000003_blk00000147 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000001bd,
Q => blk00000003_sig000001f2
);
blk00000003_blk00000146 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000001ba,
Q => blk00000003_sig000001f9
);
blk00000003_blk00000145 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000001b7,
Q => blk00000003_sig00000042
);
blk00000003_blk00000144 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000001fd,
Q => blk00000003_sig00000207
);
blk00000003_blk00000143 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000001f1,
Q => blk00000003_sig00000206
);
blk00000003_blk00000142 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000001ee,
Q => blk00000003_sig00000205
);
blk00000003_blk00000141 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000001eb,
Q => blk00000003_sig00000204
);
blk00000003_blk00000140 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000001e8,
Q => blk00000003_sig00000203
);
blk00000003_blk0000013f : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000001e5,
Q => blk00000003_sig00000202
);
blk00000003_blk0000013e : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000001e2,
Q => blk00000003_sig00000201
);
blk00000003_blk0000013d : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000001df,
Q => blk00000003_sig00000200
);
blk00000003_blk0000013c : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000001dc,
Q => blk00000003_sig000001ff
);
blk00000003_blk0000013b : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001fa,
Q => blk00000003_sig000001fe
);
blk00000003_blk0000013a : MUXCY
port map (
CI => blk00000003_sig000001fb,
DI => blk00000003_sig00000087,
S => blk00000003_sig000001fc,
O => blk00000003_sig000001ef
);
blk00000003_blk00000139 : XORCY
port map (
CI => blk00000003_sig000001fb,
LI => blk00000003_sig000001fc,
O => blk00000003_sig000001fd
);
blk00000003_blk00000138 : MUXCY
port map (
CI => blk00000003_sig000001da,
DI => blk00000003_sig000001f9,
S => blk00000003_sig000001db,
O => blk00000003_sig000001fa
);
blk00000003_blk00000137 : MUXCY
port map (
CI => blk00000003_sig000001ef,
DI => blk00000003_sig000001f8,
S => blk00000003_sig000001f0,
O => blk00000003_sig000001ec
);
blk00000003_blk00000136 : MUXCY
port map (
CI => blk00000003_sig000001ec,
DI => blk00000003_sig000001f7,
S => blk00000003_sig000001ed,
O => blk00000003_sig000001e9
);
blk00000003_blk00000135 : MUXCY
port map (
CI => blk00000003_sig000001e9,
DI => blk00000003_sig000001f6,
S => blk00000003_sig000001ea,
O => blk00000003_sig000001e6
);
blk00000003_blk00000134 : MUXCY
port map (
CI => blk00000003_sig000001e6,
DI => blk00000003_sig000001f5,
S => blk00000003_sig000001e7,
O => blk00000003_sig000001e3
);
blk00000003_blk00000133 : MUXCY
port map (
CI => blk00000003_sig000001e3,
DI => blk00000003_sig000001f4,
S => blk00000003_sig000001e4,
O => blk00000003_sig000001e0
);
blk00000003_blk00000132 : MUXCY
port map (
CI => blk00000003_sig000001e0,
DI => blk00000003_sig000001f3,
S => blk00000003_sig000001e1,
O => blk00000003_sig000001dd
);
blk00000003_blk00000131 : MUXCY
port map (
CI => blk00000003_sig000001dd,
DI => blk00000003_sig000001f2,
S => blk00000003_sig000001de,
O => blk00000003_sig000001da
);
blk00000003_blk00000130 : XORCY
port map (
CI => blk00000003_sig000001ef,
LI => blk00000003_sig000001f0,
O => blk00000003_sig000001f1
);
blk00000003_blk0000012f : XORCY
port map (
CI => blk00000003_sig000001ec,
LI => blk00000003_sig000001ed,
O => blk00000003_sig000001ee
);
blk00000003_blk0000012e : XORCY
port map (
CI => blk00000003_sig000001e9,
LI => blk00000003_sig000001ea,
O => blk00000003_sig000001eb
);
blk00000003_blk0000012d : XORCY
port map (
CI => blk00000003_sig000001e6,
LI => blk00000003_sig000001e7,
O => blk00000003_sig000001e8
);
blk00000003_blk0000012c : XORCY
port map (
CI => blk00000003_sig000001e3,
LI => blk00000003_sig000001e4,
O => blk00000003_sig000001e5
);
blk00000003_blk0000012b : XORCY
port map (
CI => blk00000003_sig000001e0,
LI => blk00000003_sig000001e1,
O => blk00000003_sig000001e2
);
blk00000003_blk0000012a : XORCY
port map (
CI => blk00000003_sig000001dd,
LI => blk00000003_sig000001de,
O => blk00000003_sig000001df
);
blk00000003_blk00000129 : XORCY
port map (
CI => blk00000003_sig000001da,
LI => blk00000003_sig000001db,
O => blk00000003_sig000001dc
);
blk00000003_blk00000128 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001d5,
Q => blk00000003_sig000001d9
);
blk00000003_blk00000127 : MUXCY
port map (
CI => blk00000003_sig000001d6,
DI => blk00000003_sig00000059,
S => blk00000003_sig000001d7,
O => blk00000003_sig000001ca
);
blk00000003_blk00000126 : XORCY
port map (
CI => blk00000003_sig000001d6,
LI => blk00000003_sig000001d7,
O => blk00000003_sig000001d8
);
blk00000003_blk00000125 : MUXCY
port map (
CI => blk00000003_sig000001b5,
DI => blk00000003_sig000001d4,
S => blk00000003_sig000001b6,
O => blk00000003_sig000001d5
);
blk00000003_blk00000124 : MUXCY
port map (
CI => blk00000003_sig000001ca,
DI => blk00000003_sig000001d3,
S => blk00000003_sig000001cb,
O => blk00000003_sig000001c7
);
blk00000003_blk00000123 : MUXCY
port map (
CI => blk00000003_sig000001c7,
DI => blk00000003_sig000001d2,
S => blk00000003_sig000001c8,
O => blk00000003_sig000001c4
);
blk00000003_blk00000122 : MUXCY
port map (
CI => blk00000003_sig000001c4,
DI => blk00000003_sig000001d1,
S => blk00000003_sig000001c5,
O => blk00000003_sig000001c1
);
blk00000003_blk00000121 : MUXCY
port map (
CI => blk00000003_sig000001c1,
DI => blk00000003_sig000001d0,
S => blk00000003_sig000001c2,
O => blk00000003_sig000001be
);
blk00000003_blk00000120 : MUXCY
port map (
CI => blk00000003_sig000001be,
DI => blk00000003_sig000001cf,
S => blk00000003_sig000001bf,
O => blk00000003_sig000001bb
);
blk00000003_blk0000011f : MUXCY
port map (
CI => blk00000003_sig000001bb,
DI => blk00000003_sig000001ce,
S => blk00000003_sig000001bc,
O => blk00000003_sig000001b8
);
blk00000003_blk0000011e : MUXCY
port map (
CI => blk00000003_sig000001b8,
DI => blk00000003_sig000001cd,
S => blk00000003_sig000001b9,
O => blk00000003_sig000001b5
);
blk00000003_blk0000011d : XORCY
port map (
CI => blk00000003_sig000001ca,
LI => blk00000003_sig000001cb,
O => blk00000003_sig000001cc
);
blk00000003_blk0000011c : XORCY
port map (
CI => blk00000003_sig000001c7,
LI => blk00000003_sig000001c8,
O => blk00000003_sig000001c9
);
blk00000003_blk0000011b : XORCY
port map (
CI => blk00000003_sig000001c4,
LI => blk00000003_sig000001c5,
O => blk00000003_sig000001c6
);
blk00000003_blk0000011a : XORCY
port map (
CI => blk00000003_sig000001c1,
LI => blk00000003_sig000001c2,
O => blk00000003_sig000001c3
);
blk00000003_blk00000119 : XORCY
port map (
CI => blk00000003_sig000001be,
LI => blk00000003_sig000001bf,
O => blk00000003_sig000001c0
);
blk00000003_blk00000118 : XORCY
port map (
CI => blk00000003_sig000001bb,
LI => blk00000003_sig000001bc,
O => blk00000003_sig000001bd
);
blk00000003_blk00000117 : XORCY
port map (
CI => blk00000003_sig000001b8,
LI => blk00000003_sig000001b9,
O => blk00000003_sig000001ba
);
blk00000003_blk00000116 : XORCY
port map (
CI => blk00000003_sig000001b5,
LI => blk00000003_sig000001b6,
O => blk00000003_sig000001b7
);
blk00000003_blk00000115 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000001b0,
Q => blk00000003_sig000001b4
);
blk00000003_blk00000114 : MUXCY
port map (
CI => blk00000003_sig000001b1,
DI => blk00000003_sig00000062,
S => blk00000003_sig000001b2,
O => blk00000003_sig000001a5
);
blk00000003_blk00000113 : XORCY
port map (
CI => blk00000003_sig000001b1,
LI => blk00000003_sig000001b2,
O => blk00000003_sig000001b3
);
blk00000003_blk00000112 : MUXCY
port map (
CI => blk00000003_sig00000190,
DI => blk00000003_sig000001af,
S => blk00000003_sig00000191,
O => blk00000003_sig000001b0
);
blk00000003_blk00000111 : MUXCY
port map (
CI => blk00000003_sig000001a5,
DI => blk00000003_sig000001ae,
S => blk00000003_sig000001a6,
O => blk00000003_sig000001a2
);
blk00000003_blk00000110 : MUXCY
port map (
CI => blk00000003_sig000001a2,
DI => blk00000003_sig000001ad,
S => blk00000003_sig000001a3,
O => blk00000003_sig0000019f
);
blk00000003_blk0000010f : MUXCY
port map (
CI => blk00000003_sig0000019f,
DI => blk00000003_sig000001ac,
S => blk00000003_sig000001a0,
O => blk00000003_sig0000019c
);
blk00000003_blk0000010e : MUXCY
port map (
CI => blk00000003_sig0000019c,
DI => blk00000003_sig000001ab,
S => blk00000003_sig0000019d,
O => blk00000003_sig00000199
);
blk00000003_blk0000010d : MUXCY
port map (
CI => blk00000003_sig00000199,
DI => blk00000003_sig000001aa,
S => blk00000003_sig0000019a,
O => blk00000003_sig00000196
);
blk00000003_blk0000010c : MUXCY
port map (
CI => blk00000003_sig00000196,
DI => blk00000003_sig000001a9,
S => blk00000003_sig00000197,
O => blk00000003_sig00000193
);
blk00000003_blk0000010b : MUXCY
port map (
CI => blk00000003_sig00000193,
DI => blk00000003_sig000001a8,
S => blk00000003_sig00000194,
O => blk00000003_sig00000190
);
blk00000003_blk0000010a : XORCY
port map (
CI => blk00000003_sig000001a5,
LI => blk00000003_sig000001a6,
O => blk00000003_sig000001a7
);
blk00000003_blk00000109 : XORCY
port map (
CI => blk00000003_sig000001a2,
LI => blk00000003_sig000001a3,
O => blk00000003_sig000001a4
);
blk00000003_blk00000108 : XORCY
port map (
CI => blk00000003_sig0000019f,
LI => blk00000003_sig000001a0,
O => blk00000003_sig000001a1
);
blk00000003_blk00000107 : XORCY
port map (
CI => blk00000003_sig0000019c,
LI => blk00000003_sig0000019d,
O => blk00000003_sig0000019e
);
blk00000003_blk00000106 : XORCY
port map (
CI => blk00000003_sig00000199,
LI => blk00000003_sig0000019a,
O => blk00000003_sig0000019b
);
blk00000003_blk00000105 : XORCY
port map (
CI => blk00000003_sig00000196,
LI => blk00000003_sig00000197,
O => blk00000003_sig00000198
);
blk00000003_blk00000104 : XORCY
port map (
CI => blk00000003_sig00000193,
LI => blk00000003_sig00000194,
O => blk00000003_sig00000195
);
blk00000003_blk00000103 : XORCY
port map (
CI => blk00000003_sig00000190,
LI => blk00000003_sig00000191,
O => blk00000003_sig00000192
);
blk00000003_blk00000102 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000018b,
Q => blk00000003_sig0000018f
);
blk00000003_blk00000101 : MUXCY
port map (
CI => blk00000003_sig0000018c,
DI => blk00000003_sig0000006b,
S => blk00000003_sig0000018d,
O => blk00000003_sig00000180
);
blk00000003_blk00000100 : XORCY
port map (
CI => blk00000003_sig0000018c,
LI => blk00000003_sig0000018d,
O => blk00000003_sig0000018e
);
blk00000003_blk000000ff : MUXCY
port map (
CI => blk00000003_sig0000016b,
DI => blk00000003_sig0000018a,
S => blk00000003_sig0000016c,
O => blk00000003_sig0000018b
);
blk00000003_blk000000fe : MUXCY
port map (
CI => blk00000003_sig00000180,
DI => blk00000003_sig00000189,
S => blk00000003_sig00000181,
O => blk00000003_sig0000017d
);
blk00000003_blk000000fd : MUXCY
port map (
CI => blk00000003_sig0000017d,
DI => blk00000003_sig00000188,
S => blk00000003_sig0000017e,
O => blk00000003_sig0000017a
);
blk00000003_blk000000fc : MUXCY
port map (
CI => blk00000003_sig0000017a,
DI => blk00000003_sig00000187,
S => blk00000003_sig0000017b,
O => blk00000003_sig00000177
);
blk00000003_blk000000fb : MUXCY
port map (
CI => blk00000003_sig00000177,
DI => blk00000003_sig00000186,
S => blk00000003_sig00000178,
O => blk00000003_sig00000174
);
blk00000003_blk000000fa : MUXCY
port map (
CI => blk00000003_sig00000174,
DI => blk00000003_sig00000185,
S => blk00000003_sig00000175,
O => blk00000003_sig00000171
);
blk00000003_blk000000f9 : MUXCY
port map (
CI => blk00000003_sig00000171,
DI => blk00000003_sig00000184,
S => blk00000003_sig00000172,
O => blk00000003_sig0000016e
);
blk00000003_blk000000f8 : MUXCY
port map (
CI => blk00000003_sig0000016e,
DI => blk00000003_sig00000183,
S => blk00000003_sig0000016f,
O => blk00000003_sig0000016b
);
blk00000003_blk000000f7 : XORCY
port map (
CI => blk00000003_sig00000180,
LI => blk00000003_sig00000181,
O => blk00000003_sig00000182
);
blk00000003_blk000000f6 : XORCY
port map (
CI => blk00000003_sig0000017d,
LI => blk00000003_sig0000017e,
O => blk00000003_sig0000017f
);
blk00000003_blk000000f5 : XORCY
port map (
CI => blk00000003_sig0000017a,
LI => blk00000003_sig0000017b,
O => blk00000003_sig0000017c
);
blk00000003_blk000000f4 : XORCY
port map (
CI => blk00000003_sig00000177,
LI => blk00000003_sig00000178,
O => blk00000003_sig00000179
);
blk00000003_blk000000f3 : XORCY
port map (
CI => blk00000003_sig00000174,
LI => blk00000003_sig00000175,
O => blk00000003_sig00000176
);
blk00000003_blk000000f2 : XORCY
port map (
CI => blk00000003_sig00000171,
LI => blk00000003_sig00000172,
O => blk00000003_sig00000173
);
blk00000003_blk000000f1 : XORCY
port map (
CI => blk00000003_sig0000016e,
LI => blk00000003_sig0000016f,
O => blk00000003_sig00000170
);
blk00000003_blk000000f0 : XORCY
port map (
CI => blk00000003_sig0000016b,
LI => blk00000003_sig0000016c,
O => blk00000003_sig0000016d
);
blk00000003_blk000000ef : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000166,
Q => blk00000003_sig0000016a
);
blk00000003_blk000000ee : MUXCY
port map (
CI => blk00000003_sig00000167,
DI => blk00000003_sig00000074,
S => blk00000003_sig00000168,
O => blk00000003_sig0000015b
);
blk00000003_blk000000ed : XORCY
port map (
CI => blk00000003_sig00000167,
LI => blk00000003_sig00000168,
O => blk00000003_sig00000169
);
blk00000003_blk000000ec : MUXCY
port map (
CI => blk00000003_sig00000146,
DI => blk00000003_sig00000165,
S => blk00000003_sig00000147,
O => blk00000003_sig00000166
);
blk00000003_blk000000eb : MUXCY
port map (
CI => blk00000003_sig0000015b,
DI => blk00000003_sig00000164,
S => blk00000003_sig0000015c,
O => blk00000003_sig00000158
);
blk00000003_blk000000ea : MUXCY
port map (
CI => blk00000003_sig00000158,
DI => blk00000003_sig00000163,
S => blk00000003_sig00000159,
O => blk00000003_sig00000155
);
blk00000003_blk000000e9 : MUXCY
port map (
CI => blk00000003_sig00000155,
DI => blk00000003_sig00000162,
S => blk00000003_sig00000156,
O => blk00000003_sig00000152
);
blk00000003_blk000000e8 : MUXCY
port map (
CI => blk00000003_sig00000152,
DI => blk00000003_sig00000161,
S => blk00000003_sig00000153,
O => blk00000003_sig0000014f
);
blk00000003_blk000000e7 : MUXCY
port map (
CI => blk00000003_sig0000014f,
DI => blk00000003_sig00000160,
S => blk00000003_sig00000150,
O => blk00000003_sig0000014c
);
blk00000003_blk000000e6 : MUXCY
port map (
CI => blk00000003_sig0000014c,
DI => blk00000003_sig0000015f,
S => blk00000003_sig0000014d,
O => blk00000003_sig00000149
);
blk00000003_blk000000e5 : MUXCY
port map (
CI => blk00000003_sig00000149,
DI => blk00000003_sig0000015e,
S => blk00000003_sig0000014a,
O => blk00000003_sig00000146
);
blk00000003_blk000000e4 : XORCY
port map (
CI => blk00000003_sig0000015b,
LI => blk00000003_sig0000015c,
O => blk00000003_sig0000015d
);
blk00000003_blk000000e3 : XORCY
port map (
CI => blk00000003_sig00000158,
LI => blk00000003_sig00000159,
O => blk00000003_sig0000015a
);
blk00000003_blk000000e2 : XORCY
port map (
CI => blk00000003_sig00000155,
LI => blk00000003_sig00000156,
O => blk00000003_sig00000157
);
blk00000003_blk000000e1 : XORCY
port map (
CI => blk00000003_sig00000152,
LI => blk00000003_sig00000153,
O => blk00000003_sig00000154
);
blk00000003_blk000000e0 : XORCY
port map (
CI => blk00000003_sig0000014f,
LI => blk00000003_sig00000150,
O => blk00000003_sig00000151
);
blk00000003_blk000000df : XORCY
port map (
CI => blk00000003_sig0000014c,
LI => blk00000003_sig0000014d,
O => blk00000003_sig0000014e
);
blk00000003_blk000000de : XORCY
port map (
CI => blk00000003_sig00000149,
LI => blk00000003_sig0000014a,
O => blk00000003_sig0000014b
);
blk00000003_blk000000dd : XORCY
port map (
CI => blk00000003_sig00000146,
LI => blk00000003_sig00000147,
O => blk00000003_sig00000148
);
blk00000003_blk000000dc : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000141,
Q => blk00000003_sig00000145
);
blk00000003_blk000000db : MUXCY
port map (
CI => blk00000003_sig00000142,
DI => blk00000003_sig0000007d,
S => blk00000003_sig00000143,
O => blk00000003_sig00000136
);
blk00000003_blk000000da : XORCY
port map (
CI => blk00000003_sig00000142,
LI => blk00000003_sig00000143,
O => blk00000003_sig00000144
);
blk00000003_blk000000d9 : MUXCY
port map (
CI => blk00000003_sig00000121,
DI => blk00000003_sig00000140,
S => blk00000003_sig00000122,
O => blk00000003_sig00000141
);
blk00000003_blk000000d8 : MUXCY
port map (
CI => blk00000003_sig00000136,
DI => blk00000003_sig0000013f,
S => blk00000003_sig00000137,
O => blk00000003_sig00000133
);
blk00000003_blk000000d7 : MUXCY
port map (
CI => blk00000003_sig00000133,
DI => blk00000003_sig0000013e,
S => blk00000003_sig00000134,
O => blk00000003_sig00000130
);
blk00000003_blk000000d6 : MUXCY
port map (
CI => blk00000003_sig00000130,
DI => blk00000003_sig0000013d,
S => blk00000003_sig00000131,
O => blk00000003_sig0000012d
);
blk00000003_blk000000d5 : MUXCY
port map (
CI => blk00000003_sig0000012d,
DI => blk00000003_sig0000013c,
S => blk00000003_sig0000012e,
O => blk00000003_sig0000012a
);
blk00000003_blk000000d4 : MUXCY
port map (
CI => blk00000003_sig0000012a,
DI => blk00000003_sig0000013b,
S => blk00000003_sig0000012b,
O => blk00000003_sig00000127
);
blk00000003_blk000000d3 : MUXCY
port map (
CI => blk00000003_sig00000127,
DI => blk00000003_sig0000013a,
S => blk00000003_sig00000128,
O => blk00000003_sig00000124
);
blk00000003_blk000000d2 : MUXCY
port map (
CI => blk00000003_sig00000124,
DI => blk00000003_sig00000139,
S => blk00000003_sig00000125,
O => blk00000003_sig00000121
);
blk00000003_blk000000d1 : XORCY
port map (
CI => blk00000003_sig00000136,
LI => blk00000003_sig00000137,
O => blk00000003_sig00000138
);
blk00000003_blk000000d0 : XORCY
port map (
CI => blk00000003_sig00000133,
LI => blk00000003_sig00000134,
O => blk00000003_sig00000135
);
blk00000003_blk000000cf : XORCY
port map (
CI => blk00000003_sig00000130,
LI => blk00000003_sig00000131,
O => blk00000003_sig00000132
);
blk00000003_blk000000ce : XORCY
port map (
CI => blk00000003_sig0000012d,
LI => blk00000003_sig0000012e,
O => blk00000003_sig0000012f
);
blk00000003_blk000000cd : XORCY
port map (
CI => blk00000003_sig0000012a,
LI => blk00000003_sig0000012b,
O => blk00000003_sig0000012c
);
blk00000003_blk000000cc : XORCY
port map (
CI => blk00000003_sig00000127,
LI => blk00000003_sig00000128,
O => blk00000003_sig00000129
);
blk00000003_blk000000cb : XORCY
port map (
CI => blk00000003_sig00000124,
LI => blk00000003_sig00000125,
O => blk00000003_sig00000126
);
blk00000003_blk000000ca : XORCY
port map (
CI => blk00000003_sig00000121,
LI => blk00000003_sig00000122,
O => blk00000003_sig00000123
);
blk00000003_blk000000c9 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000011c,
Q => blk00000003_sig00000120
);
blk00000003_blk000000c8 : MUXCY
port map (
CI => blk00000003_sig0000011d,
DI => blk00000003_sig00000086,
S => blk00000003_sig0000011e,
O => blk00000003_sig00000111
);
blk00000003_blk000000c7 : XORCY
port map (
CI => blk00000003_sig0000011d,
LI => blk00000003_sig0000011e,
O => blk00000003_sig0000011f
);
blk00000003_blk000000c6 : MUXCY
port map (
CI => blk00000003_sig000000fc,
DI => blk00000003_sig0000011b,
S => blk00000003_sig000000fd,
O => blk00000003_sig0000011c
);
blk00000003_blk000000c5 : MUXCY
port map (
CI => blk00000003_sig00000111,
DI => blk00000003_sig0000011a,
S => blk00000003_sig00000112,
O => blk00000003_sig0000010e
);
blk00000003_blk000000c4 : MUXCY
port map (
CI => blk00000003_sig0000010e,
DI => blk00000003_sig00000119,
S => blk00000003_sig0000010f,
O => blk00000003_sig0000010b
);
blk00000003_blk000000c3 : MUXCY
port map (
CI => blk00000003_sig0000010b,
DI => blk00000003_sig00000118,
S => blk00000003_sig0000010c,
O => blk00000003_sig00000108
);
blk00000003_blk000000c2 : MUXCY
port map (
CI => blk00000003_sig00000108,
DI => blk00000003_sig00000117,
S => blk00000003_sig00000109,
O => blk00000003_sig00000105
);
blk00000003_blk000000c1 : MUXCY
port map (
CI => blk00000003_sig00000105,
DI => blk00000003_sig00000116,
S => blk00000003_sig00000106,
O => blk00000003_sig00000102
);
blk00000003_blk000000c0 : MUXCY
port map (
CI => blk00000003_sig00000102,
DI => blk00000003_sig00000115,
S => blk00000003_sig00000103,
O => blk00000003_sig000000ff
);
blk00000003_blk000000bf : MUXCY
port map (
CI => blk00000003_sig000000ff,
DI => blk00000003_sig00000114,
S => blk00000003_sig00000100,
O => blk00000003_sig000000fc
);
blk00000003_blk000000be : XORCY
port map (
CI => blk00000003_sig00000111,
LI => blk00000003_sig00000112,
O => blk00000003_sig00000113
);
blk00000003_blk000000bd : XORCY
port map (
CI => blk00000003_sig0000010e,
LI => blk00000003_sig0000010f,
O => blk00000003_sig00000110
);
blk00000003_blk000000bc : XORCY
port map (
CI => blk00000003_sig0000010b,
LI => blk00000003_sig0000010c,
O => blk00000003_sig0000010d
);
blk00000003_blk000000bb : XORCY
port map (
CI => blk00000003_sig00000108,
LI => blk00000003_sig00000109,
O => blk00000003_sig0000010a
);
blk00000003_blk000000ba : XORCY
port map (
CI => blk00000003_sig00000105,
LI => blk00000003_sig00000106,
O => blk00000003_sig00000107
);
blk00000003_blk000000b9 : XORCY
port map (
CI => blk00000003_sig00000102,
LI => blk00000003_sig00000103,
O => blk00000003_sig00000104
);
blk00000003_blk000000b8 : XORCY
port map (
CI => blk00000003_sig000000ff,
LI => blk00000003_sig00000100,
O => blk00000003_sig00000101
);
blk00000003_blk000000b7 : XORCY
port map (
CI => blk00000003_sig000000fc,
LI => blk00000003_sig000000fd,
O => blk00000003_sig000000fe
);
blk00000003_blk000000b6 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000f8,
Q => blk00000003_sig000000fb
);
blk00000003_blk000000b5 : MUXCY
port map (
CI => NlwRenamedSig_OI_rfd,
DI => blk00000003_sig00000098,
S => blk00000003_sig000000f9,
O => blk00000003_sig000000f5
);
blk00000003_blk000000b4 : XORCY
port map (
CI => NlwRenamedSig_OI_rfd,
LI => blk00000003_sig000000f9,
O => blk00000003_sig000000fa
);
blk00000003_blk000000b3 : MUXCY
port map (
CI => blk00000003_sig000000e1,
DI => blk00000003_sig00000022,
S => NlwRenamedSig_OI_rfd,
O => blk00000003_sig000000f8
);
blk00000003_blk000000b2 : MUXCY
port map (
CI => blk00000003_sig000000f5,
DI => blk00000003_sig00000022,
S => blk00000003_sig000000f6,
O => blk00000003_sig000000f2
);
blk00000003_blk000000b1 : MUXCY
port map (
CI => blk00000003_sig000000f2,
DI => blk00000003_sig00000022,
S => blk00000003_sig000000f3,
O => blk00000003_sig000000ef
);
blk00000003_blk000000b0 : MUXCY
port map (
CI => blk00000003_sig000000ef,
DI => blk00000003_sig00000022,
S => blk00000003_sig000000f0,
O => blk00000003_sig000000ec
);
blk00000003_blk000000af : MUXCY
port map (
CI => blk00000003_sig000000ec,
DI => blk00000003_sig00000022,
S => blk00000003_sig000000ed,
O => blk00000003_sig000000e9
);
blk00000003_blk000000ae : MUXCY
port map (
CI => blk00000003_sig000000e9,
DI => blk00000003_sig00000022,
S => blk00000003_sig000000ea,
O => blk00000003_sig000000e6
);
blk00000003_blk000000ad : MUXCY
port map (
CI => blk00000003_sig000000e6,
DI => blk00000003_sig00000022,
S => blk00000003_sig000000e7,
O => blk00000003_sig000000e3
);
blk00000003_blk000000ac : MUXCY
port map (
CI => blk00000003_sig000000e3,
DI => blk00000003_sig00000022,
S => blk00000003_sig000000e4,
O => blk00000003_sig000000e1
);
blk00000003_blk000000ab : XORCY
port map (
CI => blk00000003_sig000000f5,
LI => blk00000003_sig000000f6,
O => blk00000003_sig000000f7
);
blk00000003_blk000000aa : XORCY
port map (
CI => blk00000003_sig000000f2,
LI => blk00000003_sig000000f3,
O => blk00000003_sig000000f4
);
blk00000003_blk000000a9 : XORCY
port map (
CI => blk00000003_sig000000ef,
LI => blk00000003_sig000000f0,
O => blk00000003_sig000000f1
);
blk00000003_blk000000a8 : XORCY
port map (
CI => blk00000003_sig000000ec,
LI => blk00000003_sig000000ed,
O => blk00000003_sig000000ee
);
blk00000003_blk000000a7 : XORCY
port map (
CI => blk00000003_sig000000e9,
LI => blk00000003_sig000000ea,
O => blk00000003_sig000000eb
);
blk00000003_blk000000a6 : XORCY
port map (
CI => blk00000003_sig000000e6,
LI => blk00000003_sig000000e7,
O => blk00000003_sig000000e8
);
blk00000003_blk000000a5 : XORCY
port map (
CI => blk00000003_sig000000e3,
LI => blk00000003_sig000000e4,
O => blk00000003_sig000000e5
);
blk00000003_blk000000a4 : XORCY
port map (
CI => blk00000003_sig000000e1,
LI => NlwRenamedSig_OI_rfd,
O => blk00000003_sig000000e2
);
blk00000003_blk000000a3 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000003f,
Q => blk00000003_sig000000df
);
blk00000003_blk000000a2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000003d,
Q => blk00000003_sig000000de
);
blk00000003_blk000000a1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000003b,
Q => blk00000003_sig000000dc
);
blk00000003_blk000000a0 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000039,
Q => blk00000003_sig000000db
);
blk00000003_blk0000009f : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000037,
Q => blk00000003_sig000000da
);
blk00000003_blk0000009e : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000035,
Q => blk00000003_sig000000d9
);
blk00000003_blk0000009d : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000000e0,
Q => blk00000003_sig000000d8
);
blk00000003_blk0000009c : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000df,
Q => blk00000003_sig000000d7
);
blk00000003_blk0000009b : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000de,
Q => blk00000003_sig000000d6
);
blk00000003_blk0000009a : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000dd,
Q => blk00000003_sig000000d5
);
blk00000003_blk00000099 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000dc,
Q => blk00000003_sig000000d4
);
blk00000003_blk00000098 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000db,
Q => blk00000003_sig000000d3
);
blk00000003_blk00000097 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000da,
Q => blk00000003_sig000000d2
);
blk00000003_blk00000096 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000d9,
Q => blk00000003_sig000000d1
);
blk00000003_blk00000095 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000000d8,
Q => blk00000003_sig000000d0
);
blk00000003_blk00000094 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000d7,
Q => blk00000003_sig000000cf
);
blk00000003_blk00000093 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000d6,
Q => blk00000003_sig000000ce
);
blk00000003_blk00000092 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000d5,
Q => blk00000003_sig000000cd
);
blk00000003_blk00000091 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000d4,
Q => blk00000003_sig000000cc
);
blk00000003_blk00000090 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000d3,
Q => blk00000003_sig000000cb
);
blk00000003_blk0000008f : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000d2,
Q => blk00000003_sig000000ca
);
blk00000003_blk0000008e : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000d1,
Q => blk00000003_sig000000c9
);
blk00000003_blk0000008d : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000000d0,
Q => blk00000003_sig000000c8
);
blk00000003_blk0000008c : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000cf,
Q => blk00000003_sig000000c7
);
blk00000003_blk0000008b : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000ce,
Q => blk00000003_sig000000c6
);
blk00000003_blk0000008a : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000cd,
Q => blk00000003_sig000000c5
);
blk00000003_blk00000089 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000cc,
Q => blk00000003_sig000000c4
);
blk00000003_blk00000088 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000cb,
Q => blk00000003_sig000000c3
);
blk00000003_blk00000087 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000ca,
Q => blk00000003_sig000000c2
);
blk00000003_blk00000086 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000c9,
Q => blk00000003_sig000000c1
);
blk00000003_blk00000085 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000000c8,
Q => blk00000003_sig000000c0
);
blk00000003_blk00000084 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000c7,
Q => blk00000003_sig000000bf
);
blk00000003_blk00000083 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000c6,
Q => blk00000003_sig000000be
);
blk00000003_blk00000082 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000c5,
Q => blk00000003_sig000000bd
);
blk00000003_blk00000081 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000c4,
Q => blk00000003_sig000000bc
);
blk00000003_blk00000080 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000c3,
Q => blk00000003_sig000000bb
);
blk00000003_blk0000007f : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000c2,
Q => blk00000003_sig000000ba
);
blk00000003_blk0000007e : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000c1,
Q => blk00000003_sig000000b9
);
blk00000003_blk0000007d : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000000c0,
Q => blk00000003_sig000000b8
);
blk00000003_blk0000007c : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000bf,
Q => blk00000003_sig000000b7
);
blk00000003_blk0000007b : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000be,
Q => blk00000003_sig000000b6
);
blk00000003_blk0000007a : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000bd,
Q => blk00000003_sig000000b5
);
blk00000003_blk00000079 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000bc,
Q => blk00000003_sig000000b4
);
blk00000003_blk00000078 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000bb,
Q => blk00000003_sig000000b3
);
blk00000003_blk00000077 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000ba,
Q => blk00000003_sig000000b2
);
blk00000003_blk00000076 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000b9,
Q => blk00000003_sig000000b1
);
blk00000003_blk00000075 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000000b8,
Q => blk00000003_sig000000b0
);
blk00000003_blk00000074 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000b7,
Q => blk00000003_sig000000af
);
blk00000003_blk00000073 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000b6,
Q => blk00000003_sig000000ae
);
blk00000003_blk00000072 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000b5,
Q => blk00000003_sig000000ad
);
blk00000003_blk00000071 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000b4,
Q => blk00000003_sig000000ac
);
blk00000003_blk00000070 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000b3,
Q => blk00000003_sig000000ab
);
blk00000003_blk0000006f : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000b2,
Q => blk00000003_sig000000aa
);
blk00000003_blk0000006e : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000b1,
Q => blk00000003_sig000000a9
);
blk00000003_blk0000006d : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000000b0,
Q => blk00000003_sig000000a7
);
blk00000003_blk0000006c : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000af,
Q => blk00000003_sig000000a5
);
blk00000003_blk0000006b : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000ae,
Q => blk00000003_sig000000a3
);
blk00000003_blk0000006a : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000ad,
Q => blk00000003_sig000000a1
);
blk00000003_blk00000069 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000ac,
Q => blk00000003_sig0000009f
);
blk00000003_blk00000068 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000ab,
Q => blk00000003_sig0000009d
);
blk00000003_blk00000067 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000aa,
Q => blk00000003_sig0000009b
);
blk00000003_blk00000066 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000a9,
Q => blk00000003_sig00000099
);
blk00000003_blk00000065 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig000000a7,
Q => blk00000003_sig000000a8
);
blk00000003_blk00000064 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000a5,
Q => blk00000003_sig000000a6
);
blk00000003_blk00000063 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000a3,
Q => blk00000003_sig000000a4
);
blk00000003_blk00000062 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig000000a1,
Q => blk00000003_sig000000a2
);
blk00000003_blk00000061 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000009f,
Q => blk00000003_sig000000a0
);
blk00000003_blk00000060 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000009d,
Q => blk00000003_sig0000009e
);
blk00000003_blk0000005f : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000009b,
Q => blk00000003_sig0000009c
);
blk00000003_blk0000005e : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000099,
Q => blk00000003_sig0000009a
);
blk00000003_blk0000005d : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000033,
Q => blk00000003_sig00000080
);
blk00000003_blk0000005c : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000031,
Q => blk00000003_sig00000081
);
blk00000003_blk0000005b : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000002f,
Q => blk00000003_sig00000083
);
blk00000003_blk0000005a : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000002d,
Q => blk00000003_sig00000084
);
blk00000003_blk00000059 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000002b,
Q => blk00000003_sig00000085
);
blk00000003_blk00000058 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000029,
Q => blk00000003_sig00000098
);
blk00000003_blk00000057 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000096,
Q => blk00000003_sig00000097
);
blk00000003_blk00000056 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000094,
Q => blk00000003_sig00000095
);
blk00000003_blk00000055 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000092,
Q => blk00000003_sig00000093
);
blk00000003_blk00000054 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000090,
Q => blk00000003_sig00000091
);
blk00000003_blk00000053 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000008e,
Q => blk00000003_sig0000008f
);
blk00000003_blk00000052 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000008c,
Q => blk00000003_sig0000008d
);
blk00000003_blk00000051 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000008a,
Q => blk00000003_sig0000008b
);
blk00000003_blk00000050 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000088,
Q => blk00000003_sig00000089
);
blk00000003_blk0000004f : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000057,
Q => blk00000003_sig00000087
);
blk00000003_blk0000004e : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000085,
Q => blk00000003_sig00000086
);
blk00000003_blk0000004d : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000084,
Q => blk00000003_sig0000007c
);
blk00000003_blk0000004c : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000083,
Q => blk00000003_sig0000007b
);
blk00000003_blk0000004b : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000082,
Q => blk00000003_sig0000007a
);
blk00000003_blk0000004a : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000081,
Q => blk00000003_sig00000079
);
blk00000003_blk00000049 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000080,
Q => blk00000003_sig00000078
);
blk00000003_blk00000048 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000007f,
Q => blk00000003_sig00000077
);
blk00000003_blk00000047 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000007e,
Q => blk00000003_sig00000076
);
blk00000003_blk00000046 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000007c,
Q => blk00000003_sig0000007d
);
blk00000003_blk00000045 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000007b,
Q => blk00000003_sig00000073
);
blk00000003_blk00000044 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000007a,
Q => blk00000003_sig00000072
);
blk00000003_blk00000043 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000079,
Q => blk00000003_sig00000071
);
blk00000003_blk00000042 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000078,
Q => blk00000003_sig00000070
);
blk00000003_blk00000041 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000077,
Q => blk00000003_sig0000006f
);
blk00000003_blk00000040 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000076,
Q => blk00000003_sig0000006e
);
blk00000003_blk0000003f : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000075,
Q => blk00000003_sig0000006d
);
blk00000003_blk0000003e : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000073,
Q => blk00000003_sig00000074
);
blk00000003_blk0000003d : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000072,
Q => blk00000003_sig0000006a
);
blk00000003_blk0000003c : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000071,
Q => blk00000003_sig00000069
);
blk00000003_blk0000003b : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000070,
Q => blk00000003_sig00000068
);
blk00000003_blk0000003a : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000006f,
Q => blk00000003_sig00000067
);
blk00000003_blk00000039 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000006e,
Q => blk00000003_sig00000066
);
blk00000003_blk00000038 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000006d,
Q => blk00000003_sig00000065
);
blk00000003_blk00000037 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000006c,
Q => blk00000003_sig00000064
);
blk00000003_blk00000036 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000006a,
Q => blk00000003_sig0000006b
);
blk00000003_blk00000035 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000069,
Q => blk00000003_sig00000061
);
blk00000003_blk00000034 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000068,
Q => blk00000003_sig00000060
);
blk00000003_blk00000033 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000067,
Q => blk00000003_sig0000005f
);
blk00000003_blk00000032 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000066,
Q => blk00000003_sig0000005e
);
blk00000003_blk00000031 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000065,
Q => blk00000003_sig0000005d
);
blk00000003_blk00000030 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000064,
Q => blk00000003_sig0000005c
);
blk00000003_blk0000002f : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000063,
Q => blk00000003_sig0000005b
);
blk00000003_blk0000002e : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000061,
Q => blk00000003_sig00000062
);
blk00000003_blk0000002d : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000060,
Q => blk00000003_sig00000058
);
blk00000003_blk0000002c : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000005f,
Q => blk00000003_sig00000056
);
blk00000003_blk0000002b : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000005e,
Q => blk00000003_sig00000055
);
blk00000003_blk0000002a : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000005d,
Q => blk00000003_sig00000054
);
blk00000003_blk00000029 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000005c,
Q => blk00000003_sig00000053
);
blk00000003_blk00000028 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000005b,
Q => blk00000003_sig00000052
);
blk00000003_blk00000027 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000005a,
Q => blk00000003_sig00000051
);
blk00000003_blk00000026 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000058,
Q => blk00000003_sig00000059
);
blk00000003_blk00000025 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000056,
Q => blk00000003_sig00000057
);
blk00000003_blk00000024 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000055,
Q => blk00000003_sig0000004e
);
blk00000003_blk00000023 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000054,
Q => blk00000003_sig0000004c
);
blk00000003_blk00000022 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000053,
Q => blk00000003_sig0000004a
);
blk00000003_blk00000021 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000052,
Q => blk00000003_sig00000048
);
blk00000003_blk00000020 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000051,
Q => blk00000003_sig00000046
);
blk00000003_blk0000001f : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000050,
Q => blk00000003_sig00000044
);
blk00000003_blk0000001e : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000004e,
Q => blk00000003_sig0000004f
);
blk00000003_blk0000001d : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000004c,
Q => blk00000003_sig0000004d
);
blk00000003_blk0000001c : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig0000004a,
Q => blk00000003_sig0000004b
);
blk00000003_blk0000001b : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000048,
Q => blk00000003_sig00000049
);
blk00000003_blk0000001a : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000046,
Q => blk00000003_sig00000047
);
blk00000003_blk00000019 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000044,
Q => blk00000003_sig00000045
);
blk00000003_blk00000018 : FD
generic map(
INIT => '1'
)
port map (
C => clk,
D => blk00000003_sig00000042,
Q => blk00000003_sig00000043
);
blk00000003_blk00000017 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000027,
Q => blk00000003_sig00000041
);
blk00000003_blk00000016 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000026,
Q => blk00000003_sig00000040
);
blk00000003_blk00000015 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000003e,
Q => blk00000003_sig0000003f
);
blk00000003_blk00000014 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000003c,
Q => blk00000003_sig0000003d
);
blk00000003_blk00000013 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000003a,
Q => blk00000003_sig0000003b
);
blk00000003_blk00000012 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000038,
Q => blk00000003_sig00000039
);
blk00000003_blk00000011 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000036,
Q => blk00000003_sig00000037
);
blk00000003_blk00000010 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000034,
Q => blk00000003_sig00000035
);
blk00000003_blk0000000f : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000032,
Q => blk00000003_sig00000033
);
blk00000003_blk0000000e : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000030,
Q => blk00000003_sig00000031
);
blk00000003_blk0000000d : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000002e,
Q => blk00000003_sig0000002f
);
blk00000003_blk0000000c : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000002c,
Q => blk00000003_sig0000002d
);
blk00000003_blk0000000b : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig0000002a,
Q => blk00000003_sig0000002b
);
blk00000003_blk0000000a : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000028,
Q => blk00000003_sig00000029
);
blk00000003_blk00000009 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000025,
Q => blk00000003_sig00000027
);
blk00000003_blk00000008 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => blk00000003_sig00000024,
Q => blk00000003_sig00000026
);
blk00000003_blk00000007 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => divisor_1(7),
Q => blk00000003_sig00000025
);
blk00000003_blk00000006 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => dividend_0(7),
Q => blk00000003_sig00000024
);
blk00000003_blk00000005 : VCC
port map (
P => NlwRenamedSig_OI_rfd
);
blk00000003_blk00000004 : GND
port map (
G => blk00000003_sig00000022
);
end STRUCTURE;
-- synthesis translate_on
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2013 Fredrik Ringhage, Aeroflex Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.i2c.all;
use gaisler.spi.all;
use gaisler.misc.all;
use gaisler.jtag.all;
use gaisler.spacewire.all;
use gaisler.net.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3core is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
scantest : integer := CFG_SCAN
);
port (
resetn : in std_ulogic;
clksel : in std_logic_vector(1 downto 0);
clk : in std_ulogic;
clkapb : in std_ulogic;
clklock : in std_ulogic;
errorn : out std_ulogic;
address : out std_logic_vector(27 downto 0);
datain : in std_logic_vector(31 downto 0);
dataout : out std_logic_vector(31 downto 0);
dataen : out std_logic_vector(31 downto 0);
cbin : in std_logic_vector(7 downto 0);
cbout : out std_logic_vector(7 downto 0);
cben : out std_logic_vector(7 downto 0);
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_ulogic; -- sdram write enable
sdrasn : out std_ulogic; -- sdram ras
sdcasn : out std_ulogic; -- sdram cas
sddqm : out std_logic_vector (3 downto 0); -- sdram dqm
dsutx : out std_ulogic; -- DSU tx data
dsurx : in std_ulogic; -- DSU rx data
dsuen : in std_ulogic;
dsubre : in std_ulogic;
dsuact : out std_ulogic;
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
txd2 : out std_ulogic; -- UART2 tx data
rxd2 : in std_ulogic; -- UART2 rx data
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_ulogic;
writen : out std_ulogic;
read : out std_ulogic;
iosn : out std_ulogic;
romsn : out std_logic_vector (1 downto 0);
brdyn : in std_ulogic;
bexcn : in std_ulogic;
wdogn : out std_ulogic;
gpioin : in std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
gpioout : out std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
gpioen : out std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
i2c_sclout : out std_ulogic;
i2c_sclen : out std_ulogic;
i2c_sclin : in std_ulogic;
i2c_sdaout : out std_ulogic;
i2c_sdaen : out std_ulogic;
i2c_sdain : in std_ulogic;
spi_miso : in std_ulogic;
spi_mosi : out std_ulogic;
spi_sck : out std_ulogic;
spi_slvsel : out std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
prom32 : in std_ulogic;
spw_clksel : in std_logic_vector(1 downto 0);
spw_clk : in std_ulogic;
spw_rxd : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxs : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txd : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txs : out std_logic_vector(0 to CFG_SPW_NUM-1);
gtx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(7 downto 0);
erx_dv : in std_ulogic;
etx_clk : in std_ulogic;
etxd : out std_logic_vector(7 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
emdint : in std_ulogic;
emdioin : in std_logic;
emdioout : out std_logic;
emdioen : out std_logic;
emdc : out std_ulogic;
trst : in std_ulogic;
tck : in std_ulogic;
tms : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
tdoen : out std_ulogic;
scanen : in std_ulogic;
testen : in std_ulogic;
testrst : in std_ulogic;
testoen : in std_ulogic;
chain_tck : out std_ulogic;
chain_tckn : out std_ulogic;
chain_tdi : out std_ulogic;
chain_tdo : in std_ulogic;
bsshft : out std_ulogic;
bscapt : out std_ulogic;
bsupdi : out std_ulogic;
bsupdo : out std_ulogic;
bsdrive : out std_ulogic;
bshighz : out std_ulogic
);
end;
architecture rtl of leon3core is
--constant is_asic : integer := 1 - is_fpga(fabtech);
--constant blength : integer := 12;
--constant CFG_NCLKS : integer := 7;
constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH;
constant maxahbm : integer := (CFG_SPW_NUM*CFG_SPW_EN) + maxahbmsp;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal rstn, rstraw : std_ulogic;
signal rstapbn, rstapbraw : std_ulogic;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal gpioi, gpioi2 : gpio_in_type;
signal gpioo, gpioo2 : gpio_out_type;
signal i2ci : i2c_in_type;
signal i2co : i2c_out_type;
signal spii : spi_in_type;
signal spio : spi_out_type;
signal ethi : eth_in_type;
signal etho : eth_out_type;
-- signal tck, tms, tdi, tdo : std_ulogic;
signal jtck, jtckn, jtdi, jrst, jtdo, jcapt, jshft, jupd, jiupd: std_ulogic;
signal jninst: std_logic_vector(7 downto 0);
signal spwi : grspw_in_type_vector(0 to CFG_SPW_NUM-1);
signal spwo : grspw_out_type_vector(0 to CFG_SPW_NUM-1);
signal spw_rxclk : std_logic_vector(CFG_SPW_NUM*2-1 downto 0);
signal dtmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal stmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal stati : ahbstat_in_type;
-- SPW Clock Gating signals
signal enphy : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal spwrstn : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal gspwclk : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal rxclko : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal lspwclkn : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal spwclkn : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal rxclkphyo : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal disclk : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal disrxclk0 : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal disrxclk1 : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal distxclk : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal distxclkn : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal gclk : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal grxclk0 : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal grxclk1 : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal gtxclk : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal gtxclkn : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal grst : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal crst : std_logic_vector(CFG_SPW_NUM-1 downto 0);
constant IOAEN : integer := 0;
constant CFG_SDEN : integer := CFG_MCTRL_LEON2;
constant CFG_INVCLK : integer := CFG_MCTRL_INVCLK;
constant BOARD_FREQ : integer := 50000; -- Board frequency in KHz
constant sysfreq : integer := (CFG_CLKMUL/CFG_CLKDIV)*40000;
constant OEPOL : integer := padoen_polarity(padtech);
constant CPU_FREQ : integer := 100000;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
wpo.wprothit <= '0'; -- no write protection
rstgen0 : rstgen -- reset generator
generic map (syncrst => CFG_NOASYNC, scanen => scantest, syncin => 1)
port map (resetn, clk, clklock, rstn, rstraw, testrst);
rstgen1 : rstgen -- reset generator
generic map (syncrst => CFG_NOASYNC, scanen => scantest, syncin => 1)
port map (resetn, clkapb, clklock, rstapbn, rstapbraw, testrst);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahbctrl0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clk, ahbmi, ahbmo, ahbsi, ahbso,
testen, testrst, scanen, testoen);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
cpu : for i in 0 to CFG_NCPU-1 generate
leon3s0 : leon3cg -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP)
port map (clk, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clk);
end generate;
errorn <= dbgo(0).error when OEPOL = 0 else not dbgo(0).error;
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clk, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= dsuen; dsui.break <= dsubre; dsuact <= dsuo.active;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
ahbuart0: ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clk, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
dui.rxd <= dsurx; dsutx <= duo.txd;
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, part => JTAG_EXAMPLE_PART,
hindex => CFG_NCPU+CFG_AHB_UART, scantest => scantest, oepol => OEPOL)
port map(rstn, clk, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
jtck, jtdi, open, jrst, jcapt, jshft, jupd, jtdo, trst, tdoen, '0', jtckn, jninst, jiupd);
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
address <= memo.address(27 downto 0);
ramsn <= memo.ramsn(4 downto 0); romsn <= memo.romsn(1 downto 0);
oen <= memo.oen; rwen <= memo.wrn; ramoen <= memo.ramoen(4 downto 0);
writen <= memo.writen; read <= memo.read; iosn <= memo.iosn;
dataout <= memo.data(31 downto 0); dataen <= memo.vbdrive(31 downto 0);
memi.data(31 downto 0) <= datain;
sdwen <= sdo.sdwen; sdrasn <= sdo.rasn; sdcasn <= sdo.casn;
sddqm <= sdo.dqm(3 downto 0); sdcsn <= sdo.sdcsn;
cbout <= memo.cb(7 downto 0); cben <= memo.vcdrive(7 downto 0);
memi.bwidth <= prom32 & '0';
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
mctrl0 : mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
srbanks => 4+CFG_MCTRL_5CS, sden => CFG_MCTRL_SDEN,
ram8 => CFG_MCTRL_RAM8BIT, ram16 => CFG_MCTRL_RAM16BIT,
invclk => CFG_MCTRL_INVCLK, sepbus => CFG_MCTRL_SEPBUS,
sdbits => 32 + 32*CFG_MCTRL_SD64, pageburst => CFG_MCTRL_PAGE,
oepol => OEPOL)
port map (rstn, clk, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
end generate;
nosd0 : if (CFG_SDEN = 0) generate -- no SDRAM controller
sdo.sdcsn <= (others => '1');
end generate;
memi.writen <= '1'; memi.wrn <= "1111";
memi.brdyn <= brdyn; memi.bexcn <= bexcn;
mg0 : if CFG_MCTRL_LEON2 = 0 generate -- None PROM/SRAM controller
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
memo.ramsn <= (others => '1'); memo.romsn <= (others => '1');
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apbctrl0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstapbn, clkapb, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
apbuart0 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstapbn, clkapb, apbi, apbo(1), u1i, u1o);
u1i.ctsn <= '0'; u1i.extclk <= '0';
txd1 <= u1o.txd; u1i.rxd <= rxd1;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
ua2 : if CFG_UART2_ENABLE /= 0 generate
uart2 : apbuart -- UART 2
generic map (pindex => 4, paddr => 4, pirq => 3, fifosize => CFG_UART2_FIFO)
port map (rstapbn, clkapb, apbi, apbo(4), u2i, u2o);
u2i.rxd <= rxd2; u2i.ctsn <= '0'; u2i.extclk <= '0'; txd2 <= u2o.txd;
end generate;
noua1 : if CFG_UART2_ENABLE = 0 generate apbo(4) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clk, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
gptimer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW, wdog => CFG_GPT_WDOGEN*CFG_GPT_WDOG)
port map (rstapbn, clkapb, apbi, apbo(3), gpti, gpto);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
wdogn <= gpto.wdogn when OEPOL = 0 else gpto.wdog;
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
grgpio0: grgpio
generic map( pindex => 6, paddr => 6, imask => CFG_GRGPIO_IMASK,
nbits => CFG_GRGPIO_WIDTH, oepol => OEPOL, syncrst => CFG_NOASYNC)
port map( rstapbn, clkapb, apbi, apbo(6), gpioi, gpioo);
gpioout <= gpioo.dout(CFG_GRGPIO_WIDTH-1 downto 0);
gpioen <= gpioo.oen(CFG_GRGPIO_WIDTH-1 downto 0);
gpioi.din(CFG_GRGPIO_WIDTH-1 downto 0) <= gpioin;
end generate;
nogpio : if CFG_GRGPIO_ENABLE = 0 generate apbo(5) <= apb_none; end generate;
i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master
i2c0 : i2cmst generic map (pindex => 5, paddr => 5, pmask => 16#FFF#, pirq => 13, filter => 9)
port map (rstapbn, clkapb, apbi, apbo(5), i2ci, i2co);
i2c_sclout <= i2co.scl;
i2c_sclen <= i2co.scloen;
i2ci.scl <= i2c_sclin;
i2c_sdaout <= i2co.sda;
i2c_sdaen <= i2co.sdaoen;
i2ci.sda <= i2c_sdain;
end generate i2cm;
noi2cm: if CFG_I2C_ENABLE = 0 generate apbo(5) <= apb_none; end generate;
spic: if CFG_SPICTRL_ENABLE = 1 generate -- SPI controller
spictrl0 : spictrl
generic map(
pindex => 8,
paddr => 8,
pmask => 16#fff#,
pirq => 8,
fdepth => CFG_SPICTRL_FIFO,
slvselen => CFG_SPICTRL_SLVREG,
slvselsz => CFG_SPICTRL_SLVS,
oepol => oepol,
odmode => CFG_SPICTRL_ODMODE,
automode => CFG_SPICTRL_AM,
aslvsel => CFG_SPICTRL_ASEL,
twen => CFG_SPICTRL_TWEN,
maxwlen => CFG_SPICTRL_MAXWLEN,
syncram => CFG_SPICTRL_SYNCRAM,
memtech => memtech,
ft => CFG_SPICTRL_FT,
scantest => scantest)
port map(
rstn => rstapbn,
clk => clkapb,
apbi => apbi,
apbo => apbo(8),
spii => spii,
spio => spio,
slvsel => spi_slvsel);
spii.sck <= '0';
spii.mosi <= '0';
spii.miso <= spi_miso;
spi_mosi <= spio.mosi;
spi_sck <= spio.sck;
spii.astart <= '0'; --unused
spii.spisel <= '1'; --unused (master only)
end generate spic;
nospi: if CFG_SPICTRL_ENABLE = 0 generate apbo(14) <= apb_none; end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
stati.cerror(0) <= memo.ce;
ahbstat0 : ahbstat
generic map (pindex => 15, paddr => 15, pirq => 1, nftslv => CFG_AHBSTATN)
port map (rstn, clk, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
nop2 : if CFG_AHBSTAT = 0 generate apbo(15) <= apb_none; end generate;
-------------------------------------------------------------------------------
-- JTAG Boundary scan
-------------------------------------------------------------------------------
bscangen: if CFG_BOUNDSCAN_EN /= 0 generate
xtapgen: if CFG_AHB_JTAG = 0 generate
t0: tap
generic map (tech => fabtech, irlen => 6, scantest => scantest, oepol => OEPOL)
port map (trst,tck,tms,tdi,tdo,
jtck,jtdi,open,jrst,jcapt,jshft,jupd,open,open,'1',jtdo,'0',jninst,jiupd,jtckn,testen,testrst,testoen,tdoen,'0');
end generate;
bc0: bscanctrl
port map (
trst,jtck,jtckn,jtdi,jninst,jiupd,jrst,jcapt,jshft,jupd,jtdo,
chain_tdi, chain_tdo, bsshft, bscapt, bsupdi, bsupdo, bsdrive, bshighz,
gnd(0), testen, testrst);
chain_tck <= jtck;
chain_tckn <= jtckn;
end generate;
nobscangen: if CFG_BOUNDSCAN_EN = 0 generate
chain_tck <= '0';
chain_tckn <= '0';
chain_tdi <= '0';
bsshft <= '0';
bscapt <= '0';
bsupdi <= '0';
bsupdo <= '0';
bsdrive <= '0';
bshighz <= '0';
end generate;
-----------------------------------------------------------------------
--- SPACEWIRE -------------------------------------------------------
-----------------------------------------------------------------------
spw : if CFG_SPW_EN > 0 generate
swloop : for i in 0 to CFG_SPW_NUM-1 generate
spwi(i).clkdiv10 <=
"000" & gpioo.val(10 downto 8) & "11" when spw_clksel(1 downto 0) = "11" else
"0000" & gpioo.val(10 downto 8) & '1' when spw_clksel(1 downto 0) = "10" else
"00000" & gpioo.val(10 downto 8);
spwi(i).timerrstval <=
'0' & gpioo.val(15 downto 11) & "111111" when clksel(1 downto 0) = "11" else
"00" & gpioo.val(15 downto 11) & "11111" when clksel(1 downto 0) = "10" else
"000" & gpioo.val(15 downto 11) & "1111";
spwi(i).dcrstval <=
"00" & gpioo.val(15 downto 11) & "111" when clksel(1 downto 0) = "11" else
"000" & gpioo.val(15 downto 11) & "10" when clksel(1 downto 0) = "10" else
"0000" & gpioo.val(15 downto 11) & '0';
-- GRSPW PHY #1
spw1_input: if CFG_SPW_GRSPW = 1 generate
x : process
begin
assert false
report "ASIC Leon3 Ref design do not support GRSPW #1"
severity failure;
wait;
end process;
end generate spw1_input;
-- GRSPW PHY #2
spw2_input: if CFG_SPW_GRSPW = 2 generate
------------------------------------------------------------------------------
-- SpW Physical layer
------------------------------------------------------------------------------
--phy_loop : for i in 0 to CFG_SPWRTR_SPWPORTS-1 generate
rstphy0 : rstgen
generic map(
acthigh => 0, -- CFG_RSTGEN_ACTHIGH,
syncrst => CFG_NOASYNC, -- CFG_RSTGEN_SYNCRST,
scanen => scantest,
syncin => 1)
port map (
rstin => rstn,
clk => spw_clk,
clklock => clklock,
rstout => spwrstn(i),
rstoutraw => open,
testrst => testrst,
testen => testen);
-- Only add clockgating to tech lib which supports clock gates
clkgatephygen : if (has_clkand(fabtech) = 1) generate
-- Sync clock to clock domain
spwclkreg : process(spw_clk) is
begin
if rising_edge(spw_clk) then
-- Only disable phy when rx and tx is disabled
-- TODO: Add SW register to enable/disable the router
enphy(i) <= '1';
end if;
end process;
-- Disable spw phy clock when port is not used
spw_phy0_enable : clkand
generic map (
tech => fabtech,
ren => 0)
port map (
i => spw_clk,
en => enphy(i),
o => gspwclk(i),
tsten => testen);
-- Select rx clock (Should be removed by optimization if RX and TX clock is same i.e. normal case for ASIC)
spw_rxclk(i) <= spw_clk when (CFG_SPW_RTSAME = 1) else rxclkphyo(i);
end generate;
noclkgategen : if (has_clkand(fabtech) = 0) generate
enphy(i) <= '1';
gspwclk(i) <= spw_clk;
spw_rxclk(i) <= spw_clk when (CFG_SPW_RTSAME = 1) else rxclkphyo(i);
end generate;
notecclkmux : if (has_clkmux(fabtech) = 0) generate
spwclkn(i) <= spw_clk when (testen = '1' and scantest = 1) else not spw_clk;
end generate;
tecclkmux : if (has_clkmux(fabtech) = 1) generate
-- Use SET protected cells
spwclkni0: clkinv generic map (tech => fabtech) port map (spw_clk, lspwclkn(i));
spwclknm0 : clkmux generic map (tech => fabtech) port map (lspwclkn(i),spw_clk,testen,spwclkn(i));
end generate;
spw_phy0 : grspw2_phy
generic map(
scantest => scantest,
tech => fabtech,
input_type => CFG_SPW_INPUT)
port map(
rstn => spwrstn(i),
rxclki => gspwclk(i),
rxclkin => spwclkn(i),
nrxclki => spwclkn(i),
di => dtmp(i),
si => stmp(i),
do => spwi(i).d(1 downto 0),
dov => spwi(i).dv(1 downto 0),
dconnect => spwi(i).dconnect(1 downto 0),
rxclko => rxclkphyo(i),
testrst => testrst,
testen => testen);
dtmp(i) <= spw_rxd(i); stmp(i) <= spw_rxs(i);
spw_txd(i) <= spwo(i).d(0); spw_txs(i) <= spwo(i).s(0);
spwi(i).nd <= (others => '0'); -- Only used in GRSPW
spwi(i).dv(3 downto 2) <= "00"; -- For second port
--end generate;
end generate spw2_input;
spw1_codec: if CFG_SPW_GRSPW = 1 generate
x : process
begin
assert false
report "ASIC Leon3 Ref design do not support GRSPW #1"
severity failure;
wait;
end process;
end generate spw1_codec;
spw2_codec: if CFG_SPW_GRSPW = 2 generate
rstcodec0 : rstgen
generic map(
acthigh => 0, -- CFG_RSTGEN_ACTHIGH,
syncrst => CFG_NOASYNC, -- CFG_RSTGEN_SYNCRST,
scanen => scantest,
syncin => 1)
port map (
rstin => rstn,
clk => spw_clk,
clklock => clklock,
rstout => crst(i),
rstoutraw => open,
testrst => testrst,
testen => testen);
-- TODO: Fix SW control signals
disclk(i) <= '0';
disrxclk0(i) <= '0';
disrxclk1(i) <= '0';
distxclk(i) <= '0';
distxclkn(i) <= '0';
port0_clkgate : grspw_codec_clockgate
generic map (
tech => fabtech,
scantest => scantest,
ports => CFG_SPW_PORTS,
output_type => CFG_SPW_OUTPUT,
clkgate => 1
)
port map (
rst => crst(i),
clk => spw_clk,
rxclk0 => spw_rxclk(i),
rxclk1 => '0',
txclk => spw_clk,
txclkn => '0',
testen => testen,
testrst => testrst,
disableclk => disclk(i),
disablerxclk0 => disrxclk0(i),
disablerxclk1 => disrxclk1(i),
disabletxclk => distxclk(i),
disabletxclkn => distxclkn(i),
grst => grst(i),
gclk => gclk(i),
grxclk0 => grxclk0(i),
grxclk1 => grxclk1(i),
gtxclk => gtxclk(i),
gtxclkn => gtxclkn(i)
);
grspw0 : grspw2
generic map(
tech => fabtech, -- : integer range 0 to NTECH := inferred;
hindex => maxahbmsp+i, -- : integer range 0 to NAHBMST-1 := 0;
pindex => i+10, -- : integer range 0 to NAPBSLV-1 := 0;
paddr => i+10, -- : integer range 0 to 16#FFF# := 0;
--pmask : integer range 0 to 16#FFF# := 16#FFF#;
pirq => i+10, -- : integer range 0 to NAHBIRQ-1 := 0;
rmap => CFG_SPW_RMAP, -- : integer range 0 to 2 := 0;
rmapcrc => CFG_SPW_RMAPCRC, -- : integer range 0 to 1 := 0;
fifosize1 => CFG_SPW_AHBFIFO, -- : integer range 4 to 32 := 32;
fifosize2 => CFG_SPW_RXFIFO, -- : integer range 16 to 64 := 64;
rxclkbuftype => 0, -- : integer range 0 to 2 := 0;
rxunaligned => CFG_SPW_RXUNAL, -- : integer range 0 to 1 := 0;
rmapbufs => CFG_SPW_RMAPBUF, -- : integer range 2 to 8 := 4;
ft => CFG_SPW_FT, -- : integer range 0 to 2 := 0;
scantest => scantest, -- : integer range 0 to 1 := 0;
ports => CFG_SPW_PORTS, -- : integer range 1 to 2 := 1;
dmachan => CFG_SPW_DMACHAN, -- : integer range 1 to 4 := 1;
memtech => memtech, -- : integer range 0 to NTECH := DEFMEMTECH;
techfifo => has_2pram(memtech), -- : integer range 0 to 1 := 1;
input_type => CFG_SPW_INPUT, -- : integer range 0 to 4 := 0;
output_type => CFG_SPW_OUTPUT, -- : integer range 0 to 2 := 0;
rxtx_sameclk => CFG_SPW_RTSAME, -- : integer range 0 to 1 := 0;
netlist => CFG_SPW_NETLIST -- : integer range 0 to 1 := 0;
)
port map (
rst => grst(i),
clk => gclk(i),
rxclk0 => grxclk0(i),
rxclk1 => grxclk1(i),
txclk => gtxclk(i),
txclkn => gtxclkn(i),
ahbmi => ahbmi,
ahbmo => ahbmo(maxahbmsp+i),
apbi => apbi,
apbo => apbo(i+10),
swni => spwi(i),
swno => spwo(i)
);
end generate spw2_codec;
end generate;
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm
generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 13, paddr => 13, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 7,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G,
enable_mdint => 1)
port map(rst => rstn, clk => clk, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
apbi => apbi, apbo => apbo(13), ethi => ethi, etho => etho);
ethi.gtx_clk <= gtx_clk;
ethi.rx_clk <= erx_clk;
ethi.rxd(7 downto 0) <= erxd;
ethi.rx_dv <= erx_dv;
ethi.tx_clk <= etx_clk;
etxd <= etho.txd(7 downto 0);
etx_en <= etho.tx_en;
etx_er <= etho.tx_er;
ethi.mdint <= emdint;
ethi.mdio_i <= emdioin;
emdioout <= etho.mdio_o;
emdioen <= etho.mdio_oe;
emdc <= etho.mdc;
ethi.rx_er <= erx_er;
ethi.rx_col <= erx_col;
ethi.rx_crs <= erx_crs;
end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
noam1 : for i in maxahbm to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-- noap0 : for i in 12+(CFG_SPW_NUM*CFG_SPW_EN) to NAPBSLV-1-CFG_AHBSTAT
-- generate apbo(i) <= apb_none; end generate;
noah0 : for i in 9 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 ASIC Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
entity attr1 is
end entity;
architecture test of attr1 is
type my_int is range 10 downto 0;
begin
p1: process is
variable x : integer := 0;
variable y : my_int;
variable z : integer := 1;
begin
assert integer'succ(x) = 1;
assert integer'pred(x) = -1;
assert integer'leftof(z) = 0;
assert integer'rightof(z) = 2;
assert my_int'leftof(y) = 2;
assert my_int'rightof(y) = 0;
wait;
end process;
end architecture;
|
-- -----------------------------------------------------------------------
--
-- Turbo Chameleon
--
-- Multi purpose FPGA expansion for the Commodore 64 computer
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2017 by Peter Wendrich (pwsoft@syntiac.com)
-- http://www.syntiac.com
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
--
-- Keyboard/joystick readout in cartridge mode
--
-- -----------------------------------------------------------------------
-- clk - system clock
-- ena_1mhz - Enable must be '1' one clk cycle each 1 Mhz.
-- no_clock - High when there is no phi-2 clock, the joystick and keyboard
-- information will be unavailable.
-- reset - system reset
--
-- ba - Status of the BA line on the cartridge port
-- req - Toggles to perform a C64 access
-- ack - Acknoledge of the C64 access, becomes equal to req when complete.
-- we - Low performs read access, high performs write access
-- a - Address for C64 access
-- d - Data input from the C64 cartridge port
-- q - Data output for write accesses
--
-- joystick* - Joystick outputs (fire2, fire1, right, left, down, up) low active
-- keys - State of the keyboard (low is pressed)
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
-- -----------------------------------------------------------------------
entity chameleon_c64_joykeyb is
generic (
enable_4player : boolean
);
port (
clk : in std_logic;
ena_1mhz : in std_logic;
no_clock : in std_logic;
reset : in std_logic;
-- To C64 cartridge logic
ba : in std_logic;
req : out std_logic;
ack : in std_logic;
we : out std_logic;
a : out unsigned(15 downto 0);
d : in unsigned(7 downto 0);
q : out unsigned(7 downto 0);
joystick1 : out unsigned(6 downto 0);
joystick2 : out unsigned(6 downto 0);
joystick3 : out unsigned(6 downto 0);
joystick4 : out unsigned(6 downto 0);
-- 0 = col0, row0
-- 1 = col1, row0
-- 8 = col0, row1
-- 63 = col7, row7
keys : out unsigned(63 downto 0)
);
end entity;
-- -----------------------------------------------------------------------
architecture rtl of chameleon_c64_joykeyb is
type state_t is (
INIT_RESET, INIT_DISABLE_VIC, INIT_DISABLE_MOB,
INIT_CIA1_A, INIT_CIA1_B, INIT_CIA2_B, --INIT_CIA2_A, ,
SET_COL, READ_ROW, STORE_ROW, SET_NOCOL,
READ_JOY_EXTRA1, READ_JOY_EXTRA2, READ_JOY_EXTRA3,
READ_JOY1, STORE_JOY1, STORE_JOY2,
READ_JOY34, STORE_JOY34);
signal state : state_t := INIT_RESET;
signal req_reg : std_logic := '0';
signal joy34_flag : std_logic := '0';
signal cnt : unsigned(3 downto 0) := (others => '0');
signal pot_flag : std_logic := '0';
signal potcnt : unsigned(9 downto 0) := (others => '0');
signal col : integer range 0 to 7 := 0;
signal joystick1_reg : unsigned(joystick1'range) := (others => '1');
signal joystick2_reg : unsigned(joystick2'range) := (others => '1');
signal joystick3_reg : unsigned(joystick3'range) := (others => '1');
signal joystick4_reg : unsigned(joystick4'range) := (others => '1');
signal keys_reg : unsigned(63 downto 0) := (others => '1');
begin
joystick1 <= joystick1_reg;
joystick2 <= joystick2_reg;
joystick3 <= joystick3_reg;
joystick4 <= joystick4_reg;
keys <= keys_reg;
req <= req_reg;
process(clk)
begin
if rising_edge(clk) then
if ena_1mhz = '1' then
cnt <= cnt - 1;
if cnt = 0 then
cnt <= (others => '0');
end if;
end if;
if (req_reg = ack) and (ba = '1') and (cnt = 0) then
we <= '-';
a <= (others => '-');
q <= (others => '-');
case state is
when INIT_RESET =>
if (reset = '0') and (ba = '1') then
state <= INIT_DISABLE_VIC;
end if;
when INIT_DISABLE_VIC =>
-- Turn off VIC-II raster DMA, so we don't have to deal with BA.
we <= '1';
a <= X"D011";
q <= X"00";
req_reg <= not req_reg;
state <= INIT_DISABLE_MOB;
when INIT_DISABLE_MOB =>
-- Turn off VIC-II sprite DMA, so we don't have to deal with BA.
we <= '1';
a <= X"D015";
q <= X"00";
req_reg <= not req_reg;
state <= INIT_CIA1_A;
when INIT_CIA1_A =>
-- Set keyboard columns port (joy2) to output
we <= '1';
a <= X"DC02";
q <= X"FF";
req_reg <= not req_reg;
state <= INIT_CIA1_B;
when INIT_CIA1_B =>
-- Set keyboard rows port (joy1) to input
we <= '1';
a <= X"DC03";
q <= X"00";
req_reg <= not req_reg;
state <= SET_COL;
if enable_4player then
state <= INIT_CIA2_B;
end if;
when INIT_CIA2_B =>
-- Set CIA2 port B for 4 player adapter
-- Bit7 output and others input.
we <= '1';
a <= X"DD03";
q <= X"80";
req_reg <= not req_reg;
state <= SET_COL;
when SET_COL =>
we <= '1';
a <= X"DC00";
q <= to_unsigned(255 - 2**col, 8);
req_reg <= not req_reg;
cnt <= (others => '1');
state <= READ_ROW;
when READ_ROW =>
we <= '0';
a <= X"DC01";
req_reg <= not req_reg;
state <= STORE_ROW;
when STORE_ROW =>
keys_reg(0 + col) <= d(0);
keys_reg(8 + col) <= d(1);
keys_reg(16 + col) <= d(2);
keys_reg(24 + col) <= d(3);
keys_reg(32 + col) <= d(4);
keys_reg(40 + col) <= d(5);
keys_reg(48 + col) <= d(6);
keys_reg(56 + col) <= d(7);
if col /= 7 then
col <= col + 1;
state <= SET_COL;
else
col <= 0;
state <= SET_NOCOL;
end if;
when SET_NOCOL =>
we <= '1';
a <= X"DC00";
if pot_flag = '0' then
q <= X"BF"; -- paddle port 1
else
q <= X"7F"; -- paddle port 2
end if;
req_reg <= not req_reg;
cnt <= (others => '1');
potcnt <= potcnt + 1;
if potcnt(9) = '1' then
potcnt <= "0000000000";
pot_flag <= not pot_flag;
state <= READ_JOY_EXTRA1;
else
state <= SET_NOCOL; -- wait
end if;
when READ_JOY_EXTRA1 =>
we <= '0';
a <= X"D419"; -- POTX
req_reg <= not req_reg;
state <= READ_JOY_EXTRA2;
when READ_JOY_EXTRA2 =>
we <= '0';
a <= X"D41A"; -- POTY
req_reg <= not req_reg;
if pot_flag = '0' then
joystick1_reg(5) <= d(7); -- paddle port 1
else
joystick2_reg(5) <= d(7); -- paddle port 2
end if;
state <= READ_JOY_EXTRA3;
when READ_JOY_EXTRA3 =>
we <= '1';
a <= X"DC00";
q <= X"FF";
req_reg <= not req_reg;
if pot_flag = '0' then
joystick1_reg(6) <= d(7); -- paddle port 1
else
joystick2_reg(6) <= d(7); -- paddle port 2
end if;
state <= READ_JOY1;
when READ_JOY1 =>
-- read joystick port 1
we <= '0';
a <= X"DC01";
req_reg <= not req_reg;
state <= STORE_JOY1;
when STORE_JOY1 =>
-- read joystick port 2
we <= '0';
a <= X"DC00";
req_reg <= not req_reg;
joystick1_reg(4 downto 0) <= d(4 downto 0);
state <= STORE_JOY2;
when STORE_JOY2 =>
joystick2_reg(4 downto 0) <= d(4 downto 0);
state <= SET_COL;
if enable_4player then
state <= READ_JOY34;
end if;
when READ_JOY34 =>
-- read user port for joystick 3 or 4
we <= '0';
a <= X"DD01";
req_reg <= not req_reg;
state <= STORE_JOY34;
when STORE_JOY34 =>
joystick3_reg(4) <= d(5);
joystick4_reg(4) <= d(4);
if joy34_flag = '0' then
joystick4_reg(3 downto 0) <= d(3 downto 0);
else
joystick3_reg(3 downto 0) <= d(3 downto 0);
end if;
-- select the other joystick (3 or 4) on the userport
we <= '1';
a <= X"DD01";
q <= joy34_flag & "0000000";
joy34_flag <= not joy34_flag;
req_reg <= not req_reg;
state <= SET_COL;
end case;
end if;
if reset = '1' then
state <= INIT_RESET;
end if;
if no_clock = '1' then
joystick1_reg <= (others => '1');
joystick2_reg <= (others => '1');
joystick3_reg <= (others => '1');
joystick4_reg <= (others => '1');
keys_reg <= (others => '1');
end if;
if not enable_4player then
joystick3_reg <= (others => '1');
joystick4_reg <= (others => '1');
end if;
-- No second and third button on 4 player adapter
joystick3_reg(6 downto 5) <= "11";
joystick4_reg(6 downto 5) <= "11";
end if;
end process;
end architecture;
|
-------------------------------------------------------------------------------
-- $Id: mux_onehot.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- mux_onehot - arch and entity
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: mux_onehot.vhd
--
-- Description: Parameterizable multiplexer with one hot select lines
--
--
-------------------------------------------------------------------------------
-- Structure:
-- Multi- use module
--------------------------------------------------------------------------------
-- Author: BLT
-- History:
-- BLT 2/22/01 -- First version
--
-- ALS 3/30/01
-- ^^^^^^
-- Added process to replicate select bus for each of the data buses
-- ~~~~~~
--
-- ALS 4/19/01
-- ^^^^^^
-- Modified assignments of DI and CI to use signals one and zero. VHDL87
-- doesn't support direct assignment of these signals to '0' and '1'.
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
---------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Generic definitions:
--
-- C_DW: Data width of buses entering the mux. Valid range is 1 to 256.
-- C_NB: Number of data buses entering the mux. Valid range is 1 to 64.
--
-- The input data is represented by a one-dimensional bus that is made up
-- of all of the data buses concatenated together. For example, a 4 to 1
-- mux with 2 bit data buses (C_DW=2,C_NB=4) is represented by:
--
-- D = (Bus0Data0, Bus0Data1, Bus1Data0, Bus1Data1, Bus2Data0, Bus2Data1,
-- Bus3Data0, Bus3Data1)
--
-- There is a separate select line for EACH data bit, leaving it to the
-- user to set fanout on the select lines before using this mux. The select
-- bus into the mux is created by concatenating the one-hot select bus for
-- a single output bit as many times as needed for the data width. Continuing
-- the 4 to 1, 2 bit example from above:
--
-- S = (Sel0Data0,Sel1Data0,Sel2Data0,Sel3Data0,
-- Sel0Data1,Sel1Data1,Sel2Data1,Sel3Data1)
--
-- 4/3/01 ALS - modified the code slightly to have the select bus generated
-- from within this code - input select bus is simply one bit per bus
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- UNISIM library is required when Xilinx primitives are instantiated.
library unisim;
use unisim.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_DW: Data width of buses entering the mux. Valid range is 1 to 256.
-- C_NB: Number of data buses entering the mux. Valid range is 1 to 64.
--
-- The input data is represented by a one-dimensional bus that is made up
-- of all of the data buses concatenated together. For example, a 4 to 1
-- mux with 2 bit data buses (C_DW=2,C_NB=4) is represented by:
--
-- D = (Bus0Data0, Bus0Data1, Bus1Data0, Bus1Data1, Bus2Data0, Bus2Data1,
-- Bus3Data0, Bus3Data1)
--
-- There is a separate select line for EACH data bit, leaving it to the
-- user to set fanout on the select lines before using this mux. The select
-- bus into the mux is created by concatenating the one-hot select bus for
-- a single output bit as many times as needed for the data width. Continuing
-- the 4 to 1, 2 bit example from above:
--
-- S = (Sel0Data0,Sel1Data0,Sel2Data0,Sel3Data0,
-- Sel0Data1,Sel1Data1,Sel2Data1,Sel3Data1)
--
-- 4/3/01 ALS - modified the code slightly to have the select bus generated
-- from within this code - input select bus is simply one bit per bus
--
-- Definition of Ports:
-- input D -- input data bus
-- input S -- input select bus
--
-- output Y -- output bus
-------------------------------------------------------------------------------
entity mux_onehot is
generic( C_DW: integer := 32;
C_NB: integer := 5 );
port(
D: in std_logic_vector(0 to C_DW*C_NB-1);
S: in std_logic_vector(0 to C_NB-1);
Y: out std_logic_vector(0 to C_DW-1));
end mux_onehot;
architecture imp of mux_onehot is
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal Dreord: std_logic_vector(0 to C_DW*((C_NB+1)/2)*2-1);
signal sel: std_logic_vector(0 to C_DW*((C_NB+1)/2)*2-1);
signal lutout: std_logic_vector(0 to (C_DW*(C_NB+1)/2)-1);
signal cyout: std_logic_vector(0 to (C_DW*(C_NB+1)/2)-1);
signal one: std_logic := '1';
signal zero: std_logic := '0';
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- MUXCY used to multiplex busses
component MUXCY
port(
O : out STD_LOGIC;
DI : in STD_LOGIC;
CI : in STD_LOGIC;
S : in STD_LOGIC);
end component;
begin
-- Reorder data buses
REORD: process( D )
variable m,n: integer;
begin
for m in 0 to C_DW-1 loop
for n in 0 to C_NB-1 loop
Dreord( m*C_NB+n) <= D( n*C_DW+m );
end loop;
end loop;
end process REORD;
-------------------------------------------------------------------------------
-- REPSELS_PROCESS
-------------------------------------------------------------------------------
-- The one-hot select bus contains 1-bit for each bus. To more easily
-- parameterize the carry chains and reduce loading on the select bus, these
-- signals are replicated into a bus that replicates the select bits for the
-- data width of the busses
-------------------------------------------------------------------------------
REPSELS_PROCESS : process ( S )
variable i, j : integer;
begin
-- loop through all data bits and busses
for i in 0 to C_DW-1 loop
for j in 0 to C_NB-1 loop
sel(i*C_NB+j) <= S(j);
end loop;
end loop;
end process REPSELS_PROCESS;
-- Handle case for even number of buses
EVEN_GEN: if C_NB rem 2 = 0 and C_NB /= 2 generate
DATA_WIDTH_GEN: for i in 0 to C_DW-1 generate
lutout(i*(C_NB+1)/2) <= not((Dreord(i*C_NB) and sel(i*C_NB)) or
(Dreord(i*C_NB+1) and sel(i*C_NB+1)));
CYMUX_FIRST: MUXCY
port map (CI=> zero,
DI=> one,
S=>lutout(i*(C_NB+1)/2),
O=>cyout(i*(C_NB+1)/2));
NUM_BUSES_GEN: for j in 1 to (C_NB+1)/2-1 generate
lutout(i*(C_NB+1)/2+j) <= not((Dreord(i*C_NB+j*2) and sel(i*C_NB+j*2)) or
(Dreord(i*C_NB+j*2+1) and sel(i*C_NB+j*2+1)));
CARRY_MUX: MUXCY
port map (CI=>cyout(i*(C_NB+1)/2+j-1),
DI=> one,
S=>lutout(i*(C_NB+1)/2+j),
O=>cyout(i*(C_NB+1)/2+j));
end generate;
Y(i) <= cyout(i*(C_NB+1)/2+(C_NB+1)/2-1);
end generate;
end generate;
-- Handle case for odd number of buses
ODD_GEN: if C_NB rem 2 /= 0 and C_NB /= 1 generate
DATA_WIDTH_GEN: for i in 0 to C_DW-1 generate
lutout(i*(C_NB+1)/2) <= not((Dreord(i*C_NB) and sel(i*C_NB)) or
(Dreord(i*C_NB+1) and sel(i*C_NB+1)));
CYMUX_FIRST: MUXCY
port map (CI=> zero,
DI=> one,
S=>lutout(i*(C_NB+1)/2),
O=>cyout(i*(C_NB+1)/2));
NUM_BUSES_GEN: for j in 1 to (C_NB+1)/2-2 generate
lutout(i*(C_NB+1)/2+j) <= not((Dreord(i*C_NB+j*2) and sel(i*C_NB+j*2)) or
(Dreord(i*C_NB+j*2+1) and sel(i*C_NB+j*2+1)));
CARRY_MUX: MUXCY
port map (CI=>cyout(i*(C_NB+1)/2+j-1),
DI=> one,
S=>lutout(i*(C_NB+1)/2+j),
O=>cyout(i*(C_NB+1)/2+j));
end generate;
ODD_BUS_GEN: for j in (C_NB+1)/2-1 to (C_NB+1)/2-1 generate
lutout(i*(C_NB+1)/2+j) <= not((Dreord(i*C_NB+j*2) and sel(i*C_NB+j*2)));
CARRY_MUX: MUXCY
port map (CI=>cyout(i*(C_NB+1)/2+j-1),
DI=> one,
S=>lutout(i*(C_NB+1)/2+j),
O=>cyout(i*(C_NB+1)/2+j));
end generate;
Y(i) <= cyout(i*(C_NB+1)/2+(C_NB+1)/2-1);
end generate;
end generate;
ONE_GEN: if C_NB = 1 generate
Y <= D;
end generate;
TWO_GEN: if C_NB = 2 generate
DATA_WIDTH_GEN2: for i in 0 to C_DW-1 generate
lutout(i*(C_NB+1)/2) <= ((Dreord(i*C_NB) and sel(i*C_NB)) or
(Dreord(i*C_NB+1) and sel(i*C_NB+1)));
Y(i) <= lutout(i*(C_NB+1)/2);
end generate;
end generate;
end imp;
|
-------------------------------------------------------------------------------
-- $Id: mux_onehot.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- mux_onehot - arch and entity
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: mux_onehot.vhd
--
-- Description: Parameterizable multiplexer with one hot select lines
--
--
-------------------------------------------------------------------------------
-- Structure:
-- Multi- use module
--------------------------------------------------------------------------------
-- Author: BLT
-- History:
-- BLT 2/22/01 -- First version
--
-- ALS 3/30/01
-- ^^^^^^
-- Added process to replicate select bus for each of the data buses
-- ~~~~~~
--
-- ALS 4/19/01
-- ^^^^^^
-- Modified assignments of DI and CI to use signals one and zero. VHDL87
-- doesn't support direct assignment of these signals to '0' and '1'.
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
---------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Generic definitions:
--
-- C_DW: Data width of buses entering the mux. Valid range is 1 to 256.
-- C_NB: Number of data buses entering the mux. Valid range is 1 to 64.
--
-- The input data is represented by a one-dimensional bus that is made up
-- of all of the data buses concatenated together. For example, a 4 to 1
-- mux with 2 bit data buses (C_DW=2,C_NB=4) is represented by:
--
-- D = (Bus0Data0, Bus0Data1, Bus1Data0, Bus1Data1, Bus2Data0, Bus2Data1,
-- Bus3Data0, Bus3Data1)
--
-- There is a separate select line for EACH data bit, leaving it to the
-- user to set fanout on the select lines before using this mux. The select
-- bus into the mux is created by concatenating the one-hot select bus for
-- a single output bit as many times as needed for the data width. Continuing
-- the 4 to 1, 2 bit example from above:
--
-- S = (Sel0Data0,Sel1Data0,Sel2Data0,Sel3Data0,
-- Sel0Data1,Sel1Data1,Sel2Data1,Sel3Data1)
--
-- 4/3/01 ALS - modified the code slightly to have the select bus generated
-- from within this code - input select bus is simply one bit per bus
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- UNISIM library is required when Xilinx primitives are instantiated.
library unisim;
use unisim.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_DW: Data width of buses entering the mux. Valid range is 1 to 256.
-- C_NB: Number of data buses entering the mux. Valid range is 1 to 64.
--
-- The input data is represented by a one-dimensional bus that is made up
-- of all of the data buses concatenated together. For example, a 4 to 1
-- mux with 2 bit data buses (C_DW=2,C_NB=4) is represented by:
--
-- D = (Bus0Data0, Bus0Data1, Bus1Data0, Bus1Data1, Bus2Data0, Bus2Data1,
-- Bus3Data0, Bus3Data1)
--
-- There is a separate select line for EACH data bit, leaving it to the
-- user to set fanout on the select lines before using this mux. The select
-- bus into the mux is created by concatenating the one-hot select bus for
-- a single output bit as many times as needed for the data width. Continuing
-- the 4 to 1, 2 bit example from above:
--
-- S = (Sel0Data0,Sel1Data0,Sel2Data0,Sel3Data0,
-- Sel0Data1,Sel1Data1,Sel2Data1,Sel3Data1)
--
-- 4/3/01 ALS - modified the code slightly to have the select bus generated
-- from within this code - input select bus is simply one bit per bus
--
-- Definition of Ports:
-- input D -- input data bus
-- input S -- input select bus
--
-- output Y -- output bus
-------------------------------------------------------------------------------
entity mux_onehot is
generic( C_DW: integer := 32;
C_NB: integer := 5 );
port(
D: in std_logic_vector(0 to C_DW*C_NB-1);
S: in std_logic_vector(0 to C_NB-1);
Y: out std_logic_vector(0 to C_DW-1));
end mux_onehot;
architecture imp of mux_onehot is
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal Dreord: std_logic_vector(0 to C_DW*((C_NB+1)/2)*2-1);
signal sel: std_logic_vector(0 to C_DW*((C_NB+1)/2)*2-1);
signal lutout: std_logic_vector(0 to (C_DW*(C_NB+1)/2)-1);
signal cyout: std_logic_vector(0 to (C_DW*(C_NB+1)/2)-1);
signal one: std_logic := '1';
signal zero: std_logic := '0';
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- MUXCY used to multiplex busses
component MUXCY
port(
O : out STD_LOGIC;
DI : in STD_LOGIC;
CI : in STD_LOGIC;
S : in STD_LOGIC);
end component;
begin
-- Reorder data buses
REORD: process( D )
variable m,n: integer;
begin
for m in 0 to C_DW-1 loop
for n in 0 to C_NB-1 loop
Dreord( m*C_NB+n) <= D( n*C_DW+m );
end loop;
end loop;
end process REORD;
-------------------------------------------------------------------------------
-- REPSELS_PROCESS
-------------------------------------------------------------------------------
-- The one-hot select bus contains 1-bit for each bus. To more easily
-- parameterize the carry chains and reduce loading on the select bus, these
-- signals are replicated into a bus that replicates the select bits for the
-- data width of the busses
-------------------------------------------------------------------------------
REPSELS_PROCESS : process ( S )
variable i, j : integer;
begin
-- loop through all data bits and busses
for i in 0 to C_DW-1 loop
for j in 0 to C_NB-1 loop
sel(i*C_NB+j) <= S(j);
end loop;
end loop;
end process REPSELS_PROCESS;
-- Handle case for even number of buses
EVEN_GEN: if C_NB rem 2 = 0 and C_NB /= 2 generate
DATA_WIDTH_GEN: for i in 0 to C_DW-1 generate
lutout(i*(C_NB+1)/2) <= not((Dreord(i*C_NB) and sel(i*C_NB)) or
(Dreord(i*C_NB+1) and sel(i*C_NB+1)));
CYMUX_FIRST: MUXCY
port map (CI=> zero,
DI=> one,
S=>lutout(i*(C_NB+1)/2),
O=>cyout(i*(C_NB+1)/2));
NUM_BUSES_GEN: for j in 1 to (C_NB+1)/2-1 generate
lutout(i*(C_NB+1)/2+j) <= not((Dreord(i*C_NB+j*2) and sel(i*C_NB+j*2)) or
(Dreord(i*C_NB+j*2+1) and sel(i*C_NB+j*2+1)));
CARRY_MUX: MUXCY
port map (CI=>cyout(i*(C_NB+1)/2+j-1),
DI=> one,
S=>lutout(i*(C_NB+1)/2+j),
O=>cyout(i*(C_NB+1)/2+j));
end generate;
Y(i) <= cyout(i*(C_NB+1)/2+(C_NB+1)/2-1);
end generate;
end generate;
-- Handle case for odd number of buses
ODD_GEN: if C_NB rem 2 /= 0 and C_NB /= 1 generate
DATA_WIDTH_GEN: for i in 0 to C_DW-1 generate
lutout(i*(C_NB+1)/2) <= not((Dreord(i*C_NB) and sel(i*C_NB)) or
(Dreord(i*C_NB+1) and sel(i*C_NB+1)));
CYMUX_FIRST: MUXCY
port map (CI=> zero,
DI=> one,
S=>lutout(i*(C_NB+1)/2),
O=>cyout(i*(C_NB+1)/2));
NUM_BUSES_GEN: for j in 1 to (C_NB+1)/2-2 generate
lutout(i*(C_NB+1)/2+j) <= not((Dreord(i*C_NB+j*2) and sel(i*C_NB+j*2)) or
(Dreord(i*C_NB+j*2+1) and sel(i*C_NB+j*2+1)));
CARRY_MUX: MUXCY
port map (CI=>cyout(i*(C_NB+1)/2+j-1),
DI=> one,
S=>lutout(i*(C_NB+1)/2+j),
O=>cyout(i*(C_NB+1)/2+j));
end generate;
ODD_BUS_GEN: for j in (C_NB+1)/2-1 to (C_NB+1)/2-1 generate
lutout(i*(C_NB+1)/2+j) <= not((Dreord(i*C_NB+j*2) and sel(i*C_NB+j*2)));
CARRY_MUX: MUXCY
port map (CI=>cyout(i*(C_NB+1)/2+j-1),
DI=> one,
S=>lutout(i*(C_NB+1)/2+j),
O=>cyout(i*(C_NB+1)/2+j));
end generate;
Y(i) <= cyout(i*(C_NB+1)/2+(C_NB+1)/2-1);
end generate;
end generate;
ONE_GEN: if C_NB = 1 generate
Y <= D;
end generate;
TWO_GEN: if C_NB = 2 generate
DATA_WIDTH_GEN2: for i in 0 to C_DW-1 generate
lutout(i*(C_NB+1)/2) <= ((Dreord(i*C_NB) and sel(i*C_NB)) or
(Dreord(i*C_NB+1) and sel(i*C_NB+1)));
Y(i) <= lutout(i*(C_NB+1)/2);
end generate;
end generate;
end imp;
|
-------------------------------------------------------------------------------
-- $Id: mux_onehot.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- mux_onehot - arch and entity
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: mux_onehot.vhd
--
-- Description: Parameterizable multiplexer with one hot select lines
--
--
-------------------------------------------------------------------------------
-- Structure:
-- Multi- use module
--------------------------------------------------------------------------------
-- Author: BLT
-- History:
-- BLT 2/22/01 -- First version
--
-- ALS 3/30/01
-- ^^^^^^
-- Added process to replicate select bus for each of the data buses
-- ~~~~~~
--
-- ALS 4/19/01
-- ^^^^^^
-- Modified assignments of DI and CI to use signals one and zero. VHDL87
-- doesn't support direct assignment of these signals to '0' and '1'.
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
---------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Generic definitions:
--
-- C_DW: Data width of buses entering the mux. Valid range is 1 to 256.
-- C_NB: Number of data buses entering the mux. Valid range is 1 to 64.
--
-- The input data is represented by a one-dimensional bus that is made up
-- of all of the data buses concatenated together. For example, a 4 to 1
-- mux with 2 bit data buses (C_DW=2,C_NB=4) is represented by:
--
-- D = (Bus0Data0, Bus0Data1, Bus1Data0, Bus1Data1, Bus2Data0, Bus2Data1,
-- Bus3Data0, Bus3Data1)
--
-- There is a separate select line for EACH data bit, leaving it to the
-- user to set fanout on the select lines before using this mux. The select
-- bus into the mux is created by concatenating the one-hot select bus for
-- a single output bit as many times as needed for the data width. Continuing
-- the 4 to 1, 2 bit example from above:
--
-- S = (Sel0Data0,Sel1Data0,Sel2Data0,Sel3Data0,
-- Sel0Data1,Sel1Data1,Sel2Data1,Sel3Data1)
--
-- 4/3/01 ALS - modified the code slightly to have the select bus generated
-- from within this code - input select bus is simply one bit per bus
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- UNISIM library is required when Xilinx primitives are instantiated.
library unisim;
use unisim.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_DW: Data width of buses entering the mux. Valid range is 1 to 256.
-- C_NB: Number of data buses entering the mux. Valid range is 1 to 64.
--
-- The input data is represented by a one-dimensional bus that is made up
-- of all of the data buses concatenated together. For example, a 4 to 1
-- mux with 2 bit data buses (C_DW=2,C_NB=4) is represented by:
--
-- D = (Bus0Data0, Bus0Data1, Bus1Data0, Bus1Data1, Bus2Data0, Bus2Data1,
-- Bus3Data0, Bus3Data1)
--
-- There is a separate select line for EACH data bit, leaving it to the
-- user to set fanout on the select lines before using this mux. The select
-- bus into the mux is created by concatenating the one-hot select bus for
-- a single output bit as many times as needed for the data width. Continuing
-- the 4 to 1, 2 bit example from above:
--
-- S = (Sel0Data0,Sel1Data0,Sel2Data0,Sel3Data0,
-- Sel0Data1,Sel1Data1,Sel2Data1,Sel3Data1)
--
-- 4/3/01 ALS - modified the code slightly to have the select bus generated
-- from within this code - input select bus is simply one bit per bus
--
-- Definition of Ports:
-- input D -- input data bus
-- input S -- input select bus
--
-- output Y -- output bus
-------------------------------------------------------------------------------
entity mux_onehot is
generic( C_DW: integer := 32;
C_NB: integer := 5 );
port(
D: in std_logic_vector(0 to C_DW*C_NB-1);
S: in std_logic_vector(0 to C_NB-1);
Y: out std_logic_vector(0 to C_DW-1));
end mux_onehot;
architecture imp of mux_onehot is
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal Dreord: std_logic_vector(0 to C_DW*((C_NB+1)/2)*2-1);
signal sel: std_logic_vector(0 to C_DW*((C_NB+1)/2)*2-1);
signal lutout: std_logic_vector(0 to (C_DW*(C_NB+1)/2)-1);
signal cyout: std_logic_vector(0 to (C_DW*(C_NB+1)/2)-1);
signal one: std_logic := '1';
signal zero: std_logic := '0';
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- MUXCY used to multiplex busses
component MUXCY
port(
O : out STD_LOGIC;
DI : in STD_LOGIC;
CI : in STD_LOGIC;
S : in STD_LOGIC);
end component;
begin
-- Reorder data buses
REORD: process( D )
variable m,n: integer;
begin
for m in 0 to C_DW-1 loop
for n in 0 to C_NB-1 loop
Dreord( m*C_NB+n) <= D( n*C_DW+m );
end loop;
end loop;
end process REORD;
-------------------------------------------------------------------------------
-- REPSELS_PROCESS
-------------------------------------------------------------------------------
-- The one-hot select bus contains 1-bit for each bus. To more easily
-- parameterize the carry chains and reduce loading on the select bus, these
-- signals are replicated into a bus that replicates the select bits for the
-- data width of the busses
-------------------------------------------------------------------------------
REPSELS_PROCESS : process ( S )
variable i, j : integer;
begin
-- loop through all data bits and busses
for i in 0 to C_DW-1 loop
for j in 0 to C_NB-1 loop
sel(i*C_NB+j) <= S(j);
end loop;
end loop;
end process REPSELS_PROCESS;
-- Handle case for even number of buses
EVEN_GEN: if C_NB rem 2 = 0 and C_NB /= 2 generate
DATA_WIDTH_GEN: for i in 0 to C_DW-1 generate
lutout(i*(C_NB+1)/2) <= not((Dreord(i*C_NB) and sel(i*C_NB)) or
(Dreord(i*C_NB+1) and sel(i*C_NB+1)));
CYMUX_FIRST: MUXCY
port map (CI=> zero,
DI=> one,
S=>lutout(i*(C_NB+1)/2),
O=>cyout(i*(C_NB+1)/2));
NUM_BUSES_GEN: for j in 1 to (C_NB+1)/2-1 generate
lutout(i*(C_NB+1)/2+j) <= not((Dreord(i*C_NB+j*2) and sel(i*C_NB+j*2)) or
(Dreord(i*C_NB+j*2+1) and sel(i*C_NB+j*2+1)));
CARRY_MUX: MUXCY
port map (CI=>cyout(i*(C_NB+1)/2+j-1),
DI=> one,
S=>lutout(i*(C_NB+1)/2+j),
O=>cyout(i*(C_NB+1)/2+j));
end generate;
Y(i) <= cyout(i*(C_NB+1)/2+(C_NB+1)/2-1);
end generate;
end generate;
-- Handle case for odd number of buses
ODD_GEN: if C_NB rem 2 /= 0 and C_NB /= 1 generate
DATA_WIDTH_GEN: for i in 0 to C_DW-1 generate
lutout(i*(C_NB+1)/2) <= not((Dreord(i*C_NB) and sel(i*C_NB)) or
(Dreord(i*C_NB+1) and sel(i*C_NB+1)));
CYMUX_FIRST: MUXCY
port map (CI=> zero,
DI=> one,
S=>lutout(i*(C_NB+1)/2),
O=>cyout(i*(C_NB+1)/2));
NUM_BUSES_GEN: for j in 1 to (C_NB+1)/2-2 generate
lutout(i*(C_NB+1)/2+j) <= not((Dreord(i*C_NB+j*2) and sel(i*C_NB+j*2)) or
(Dreord(i*C_NB+j*2+1) and sel(i*C_NB+j*2+1)));
CARRY_MUX: MUXCY
port map (CI=>cyout(i*(C_NB+1)/2+j-1),
DI=> one,
S=>lutout(i*(C_NB+1)/2+j),
O=>cyout(i*(C_NB+1)/2+j));
end generate;
ODD_BUS_GEN: for j in (C_NB+1)/2-1 to (C_NB+1)/2-1 generate
lutout(i*(C_NB+1)/2+j) <= not((Dreord(i*C_NB+j*2) and sel(i*C_NB+j*2)));
CARRY_MUX: MUXCY
port map (CI=>cyout(i*(C_NB+1)/2+j-1),
DI=> one,
S=>lutout(i*(C_NB+1)/2+j),
O=>cyout(i*(C_NB+1)/2+j));
end generate;
Y(i) <= cyout(i*(C_NB+1)/2+(C_NB+1)/2-1);
end generate;
end generate;
ONE_GEN: if C_NB = 1 generate
Y <= D;
end generate;
TWO_GEN: if C_NB = 2 generate
DATA_WIDTH_GEN2: for i in 0 to C_DW-1 generate
lutout(i*(C_NB+1)/2) <= ((Dreord(i*C_NB) and sel(i*C_NB)) or
(Dreord(i*C_NB+1) and sel(i*C_NB+1)));
Y(i) <= lutout(i*(C_NB+1)/2);
end generate;
end generate;
end imp;
|
-------------------------------------------------------------------------------
-- $Id: mux_onehot.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- mux_onehot - arch and entity
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: mux_onehot.vhd
--
-- Description: Parameterizable multiplexer with one hot select lines
--
--
-------------------------------------------------------------------------------
-- Structure:
-- Multi- use module
--------------------------------------------------------------------------------
-- Author: BLT
-- History:
-- BLT 2/22/01 -- First version
--
-- ALS 3/30/01
-- ^^^^^^
-- Added process to replicate select bus for each of the data buses
-- ~~~~~~
--
-- ALS 4/19/01
-- ^^^^^^
-- Modified assignments of DI and CI to use signals one and zero. VHDL87
-- doesn't support direct assignment of these signals to '0' and '1'.
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
---------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Generic definitions:
--
-- C_DW: Data width of buses entering the mux. Valid range is 1 to 256.
-- C_NB: Number of data buses entering the mux. Valid range is 1 to 64.
--
-- The input data is represented by a one-dimensional bus that is made up
-- of all of the data buses concatenated together. For example, a 4 to 1
-- mux with 2 bit data buses (C_DW=2,C_NB=4) is represented by:
--
-- D = (Bus0Data0, Bus0Data1, Bus1Data0, Bus1Data1, Bus2Data0, Bus2Data1,
-- Bus3Data0, Bus3Data1)
--
-- There is a separate select line for EACH data bit, leaving it to the
-- user to set fanout on the select lines before using this mux. The select
-- bus into the mux is created by concatenating the one-hot select bus for
-- a single output bit as many times as needed for the data width. Continuing
-- the 4 to 1, 2 bit example from above:
--
-- S = (Sel0Data0,Sel1Data0,Sel2Data0,Sel3Data0,
-- Sel0Data1,Sel1Data1,Sel2Data1,Sel3Data1)
--
-- 4/3/01 ALS - modified the code slightly to have the select bus generated
-- from within this code - input select bus is simply one bit per bus
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- UNISIM library is required when Xilinx primitives are instantiated.
library unisim;
use unisim.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_DW: Data width of buses entering the mux. Valid range is 1 to 256.
-- C_NB: Number of data buses entering the mux. Valid range is 1 to 64.
--
-- The input data is represented by a one-dimensional bus that is made up
-- of all of the data buses concatenated together. For example, a 4 to 1
-- mux with 2 bit data buses (C_DW=2,C_NB=4) is represented by:
--
-- D = (Bus0Data0, Bus0Data1, Bus1Data0, Bus1Data1, Bus2Data0, Bus2Data1,
-- Bus3Data0, Bus3Data1)
--
-- There is a separate select line for EACH data bit, leaving it to the
-- user to set fanout on the select lines before using this mux. The select
-- bus into the mux is created by concatenating the one-hot select bus for
-- a single output bit as many times as needed for the data width. Continuing
-- the 4 to 1, 2 bit example from above:
--
-- S = (Sel0Data0,Sel1Data0,Sel2Data0,Sel3Data0,
-- Sel0Data1,Sel1Data1,Sel2Data1,Sel3Data1)
--
-- 4/3/01 ALS - modified the code slightly to have the select bus generated
-- from within this code - input select bus is simply one bit per bus
--
-- Definition of Ports:
-- input D -- input data bus
-- input S -- input select bus
--
-- output Y -- output bus
-------------------------------------------------------------------------------
entity mux_onehot is
generic( C_DW: integer := 32;
C_NB: integer := 5 );
port(
D: in std_logic_vector(0 to C_DW*C_NB-1);
S: in std_logic_vector(0 to C_NB-1);
Y: out std_logic_vector(0 to C_DW-1));
end mux_onehot;
architecture imp of mux_onehot is
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal Dreord: std_logic_vector(0 to C_DW*((C_NB+1)/2)*2-1);
signal sel: std_logic_vector(0 to C_DW*((C_NB+1)/2)*2-1);
signal lutout: std_logic_vector(0 to (C_DW*(C_NB+1)/2)-1);
signal cyout: std_logic_vector(0 to (C_DW*(C_NB+1)/2)-1);
signal one: std_logic := '1';
signal zero: std_logic := '0';
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- MUXCY used to multiplex busses
component MUXCY
port(
O : out STD_LOGIC;
DI : in STD_LOGIC;
CI : in STD_LOGIC;
S : in STD_LOGIC);
end component;
begin
-- Reorder data buses
REORD: process( D )
variable m,n: integer;
begin
for m in 0 to C_DW-1 loop
for n in 0 to C_NB-1 loop
Dreord( m*C_NB+n) <= D( n*C_DW+m );
end loop;
end loop;
end process REORD;
-------------------------------------------------------------------------------
-- REPSELS_PROCESS
-------------------------------------------------------------------------------
-- The one-hot select bus contains 1-bit for each bus. To more easily
-- parameterize the carry chains and reduce loading on the select bus, these
-- signals are replicated into a bus that replicates the select bits for the
-- data width of the busses
-------------------------------------------------------------------------------
REPSELS_PROCESS : process ( S )
variable i, j : integer;
begin
-- loop through all data bits and busses
for i in 0 to C_DW-1 loop
for j in 0 to C_NB-1 loop
sel(i*C_NB+j) <= S(j);
end loop;
end loop;
end process REPSELS_PROCESS;
-- Handle case for even number of buses
EVEN_GEN: if C_NB rem 2 = 0 and C_NB /= 2 generate
DATA_WIDTH_GEN: for i in 0 to C_DW-1 generate
lutout(i*(C_NB+1)/2) <= not((Dreord(i*C_NB) and sel(i*C_NB)) or
(Dreord(i*C_NB+1) and sel(i*C_NB+1)));
CYMUX_FIRST: MUXCY
port map (CI=> zero,
DI=> one,
S=>lutout(i*(C_NB+1)/2),
O=>cyout(i*(C_NB+1)/2));
NUM_BUSES_GEN: for j in 1 to (C_NB+1)/2-1 generate
lutout(i*(C_NB+1)/2+j) <= not((Dreord(i*C_NB+j*2) and sel(i*C_NB+j*2)) or
(Dreord(i*C_NB+j*2+1) and sel(i*C_NB+j*2+1)));
CARRY_MUX: MUXCY
port map (CI=>cyout(i*(C_NB+1)/2+j-1),
DI=> one,
S=>lutout(i*(C_NB+1)/2+j),
O=>cyout(i*(C_NB+1)/2+j));
end generate;
Y(i) <= cyout(i*(C_NB+1)/2+(C_NB+1)/2-1);
end generate;
end generate;
-- Handle case for odd number of buses
ODD_GEN: if C_NB rem 2 /= 0 and C_NB /= 1 generate
DATA_WIDTH_GEN: for i in 0 to C_DW-1 generate
lutout(i*(C_NB+1)/2) <= not((Dreord(i*C_NB) and sel(i*C_NB)) or
(Dreord(i*C_NB+1) and sel(i*C_NB+1)));
CYMUX_FIRST: MUXCY
port map (CI=> zero,
DI=> one,
S=>lutout(i*(C_NB+1)/2),
O=>cyout(i*(C_NB+1)/2));
NUM_BUSES_GEN: for j in 1 to (C_NB+1)/2-2 generate
lutout(i*(C_NB+1)/2+j) <= not((Dreord(i*C_NB+j*2) and sel(i*C_NB+j*2)) or
(Dreord(i*C_NB+j*2+1) and sel(i*C_NB+j*2+1)));
CARRY_MUX: MUXCY
port map (CI=>cyout(i*(C_NB+1)/2+j-1),
DI=> one,
S=>lutout(i*(C_NB+1)/2+j),
O=>cyout(i*(C_NB+1)/2+j));
end generate;
ODD_BUS_GEN: for j in (C_NB+1)/2-1 to (C_NB+1)/2-1 generate
lutout(i*(C_NB+1)/2+j) <= not((Dreord(i*C_NB+j*2) and sel(i*C_NB+j*2)));
CARRY_MUX: MUXCY
port map (CI=>cyout(i*(C_NB+1)/2+j-1),
DI=> one,
S=>lutout(i*(C_NB+1)/2+j),
O=>cyout(i*(C_NB+1)/2+j));
end generate;
Y(i) <= cyout(i*(C_NB+1)/2+(C_NB+1)/2-1);
end generate;
end generate;
ONE_GEN: if C_NB = 1 generate
Y <= D;
end generate;
TWO_GEN: if C_NB = 2 generate
DATA_WIDTH_GEN2: for i in 0 to C_DW-1 generate
lutout(i*(C_NB+1)/2) <= ((Dreord(i*C_NB) and sel(i*C_NB)) or
(Dreord(i*C_NB+1) and sel(i*C_NB+1)));
Y(i) <= lutout(i*(C_NB+1)/2);
end generate;
end generate;
end imp;
|
-------------------------------------------------------------------------------
-- $Id: mux_onehot.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- mux_onehot - arch and entity
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: mux_onehot.vhd
--
-- Description: Parameterizable multiplexer with one hot select lines
--
--
-------------------------------------------------------------------------------
-- Structure:
-- Multi- use module
--------------------------------------------------------------------------------
-- Author: BLT
-- History:
-- BLT 2/22/01 -- First version
--
-- ALS 3/30/01
-- ^^^^^^
-- Added process to replicate select bus for each of the data buses
-- ~~~~~~
--
-- ALS 4/19/01
-- ^^^^^^
-- Modified assignments of DI and CI to use signals one and zero. VHDL87
-- doesn't support direct assignment of these signals to '0' and '1'.
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
---------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Generic definitions:
--
-- C_DW: Data width of buses entering the mux. Valid range is 1 to 256.
-- C_NB: Number of data buses entering the mux. Valid range is 1 to 64.
--
-- The input data is represented by a one-dimensional bus that is made up
-- of all of the data buses concatenated together. For example, a 4 to 1
-- mux with 2 bit data buses (C_DW=2,C_NB=4) is represented by:
--
-- D = (Bus0Data0, Bus0Data1, Bus1Data0, Bus1Data1, Bus2Data0, Bus2Data1,
-- Bus3Data0, Bus3Data1)
--
-- There is a separate select line for EACH data bit, leaving it to the
-- user to set fanout on the select lines before using this mux. The select
-- bus into the mux is created by concatenating the one-hot select bus for
-- a single output bit as many times as needed for the data width. Continuing
-- the 4 to 1, 2 bit example from above:
--
-- S = (Sel0Data0,Sel1Data0,Sel2Data0,Sel3Data0,
-- Sel0Data1,Sel1Data1,Sel2Data1,Sel3Data1)
--
-- 4/3/01 ALS - modified the code slightly to have the select bus generated
-- from within this code - input select bus is simply one bit per bus
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- UNISIM library is required when Xilinx primitives are instantiated.
library unisim;
use unisim.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_DW: Data width of buses entering the mux. Valid range is 1 to 256.
-- C_NB: Number of data buses entering the mux. Valid range is 1 to 64.
--
-- The input data is represented by a one-dimensional bus that is made up
-- of all of the data buses concatenated together. For example, a 4 to 1
-- mux with 2 bit data buses (C_DW=2,C_NB=4) is represented by:
--
-- D = (Bus0Data0, Bus0Data1, Bus1Data0, Bus1Data1, Bus2Data0, Bus2Data1,
-- Bus3Data0, Bus3Data1)
--
-- There is a separate select line for EACH data bit, leaving it to the
-- user to set fanout on the select lines before using this mux. The select
-- bus into the mux is created by concatenating the one-hot select bus for
-- a single output bit as many times as needed for the data width. Continuing
-- the 4 to 1, 2 bit example from above:
--
-- S = (Sel0Data0,Sel1Data0,Sel2Data0,Sel3Data0,
-- Sel0Data1,Sel1Data1,Sel2Data1,Sel3Data1)
--
-- 4/3/01 ALS - modified the code slightly to have the select bus generated
-- from within this code - input select bus is simply one bit per bus
--
-- Definition of Ports:
-- input D -- input data bus
-- input S -- input select bus
--
-- output Y -- output bus
-------------------------------------------------------------------------------
entity mux_onehot is
generic( C_DW: integer := 32;
C_NB: integer := 5 );
port(
D: in std_logic_vector(0 to C_DW*C_NB-1);
S: in std_logic_vector(0 to C_NB-1);
Y: out std_logic_vector(0 to C_DW-1));
end mux_onehot;
architecture imp of mux_onehot is
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal Dreord: std_logic_vector(0 to C_DW*((C_NB+1)/2)*2-1);
signal sel: std_logic_vector(0 to C_DW*((C_NB+1)/2)*2-1);
signal lutout: std_logic_vector(0 to (C_DW*(C_NB+1)/2)-1);
signal cyout: std_logic_vector(0 to (C_DW*(C_NB+1)/2)-1);
signal one: std_logic := '1';
signal zero: std_logic := '0';
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- MUXCY used to multiplex busses
component MUXCY
port(
O : out STD_LOGIC;
DI : in STD_LOGIC;
CI : in STD_LOGIC;
S : in STD_LOGIC);
end component;
begin
-- Reorder data buses
REORD: process( D )
variable m,n: integer;
begin
for m in 0 to C_DW-1 loop
for n in 0 to C_NB-1 loop
Dreord( m*C_NB+n) <= D( n*C_DW+m );
end loop;
end loop;
end process REORD;
-------------------------------------------------------------------------------
-- REPSELS_PROCESS
-------------------------------------------------------------------------------
-- The one-hot select bus contains 1-bit for each bus. To more easily
-- parameterize the carry chains and reduce loading on the select bus, these
-- signals are replicated into a bus that replicates the select bits for the
-- data width of the busses
-------------------------------------------------------------------------------
REPSELS_PROCESS : process ( S )
variable i, j : integer;
begin
-- loop through all data bits and busses
for i in 0 to C_DW-1 loop
for j in 0 to C_NB-1 loop
sel(i*C_NB+j) <= S(j);
end loop;
end loop;
end process REPSELS_PROCESS;
-- Handle case for even number of buses
EVEN_GEN: if C_NB rem 2 = 0 and C_NB /= 2 generate
DATA_WIDTH_GEN: for i in 0 to C_DW-1 generate
lutout(i*(C_NB+1)/2) <= not((Dreord(i*C_NB) and sel(i*C_NB)) or
(Dreord(i*C_NB+1) and sel(i*C_NB+1)));
CYMUX_FIRST: MUXCY
port map (CI=> zero,
DI=> one,
S=>lutout(i*(C_NB+1)/2),
O=>cyout(i*(C_NB+1)/2));
NUM_BUSES_GEN: for j in 1 to (C_NB+1)/2-1 generate
lutout(i*(C_NB+1)/2+j) <= not((Dreord(i*C_NB+j*2) and sel(i*C_NB+j*2)) or
(Dreord(i*C_NB+j*2+1) and sel(i*C_NB+j*2+1)));
CARRY_MUX: MUXCY
port map (CI=>cyout(i*(C_NB+1)/2+j-1),
DI=> one,
S=>lutout(i*(C_NB+1)/2+j),
O=>cyout(i*(C_NB+1)/2+j));
end generate;
Y(i) <= cyout(i*(C_NB+1)/2+(C_NB+1)/2-1);
end generate;
end generate;
-- Handle case for odd number of buses
ODD_GEN: if C_NB rem 2 /= 0 and C_NB /= 1 generate
DATA_WIDTH_GEN: for i in 0 to C_DW-1 generate
lutout(i*(C_NB+1)/2) <= not((Dreord(i*C_NB) and sel(i*C_NB)) or
(Dreord(i*C_NB+1) and sel(i*C_NB+1)));
CYMUX_FIRST: MUXCY
port map (CI=> zero,
DI=> one,
S=>lutout(i*(C_NB+1)/2),
O=>cyout(i*(C_NB+1)/2));
NUM_BUSES_GEN: for j in 1 to (C_NB+1)/2-2 generate
lutout(i*(C_NB+1)/2+j) <= not((Dreord(i*C_NB+j*2) and sel(i*C_NB+j*2)) or
(Dreord(i*C_NB+j*2+1) and sel(i*C_NB+j*2+1)));
CARRY_MUX: MUXCY
port map (CI=>cyout(i*(C_NB+1)/2+j-1),
DI=> one,
S=>lutout(i*(C_NB+1)/2+j),
O=>cyout(i*(C_NB+1)/2+j));
end generate;
ODD_BUS_GEN: for j in (C_NB+1)/2-1 to (C_NB+1)/2-1 generate
lutout(i*(C_NB+1)/2+j) <= not((Dreord(i*C_NB+j*2) and sel(i*C_NB+j*2)));
CARRY_MUX: MUXCY
port map (CI=>cyout(i*(C_NB+1)/2+j-1),
DI=> one,
S=>lutout(i*(C_NB+1)/2+j),
O=>cyout(i*(C_NB+1)/2+j));
end generate;
Y(i) <= cyout(i*(C_NB+1)/2+(C_NB+1)/2-1);
end generate;
end generate;
ONE_GEN: if C_NB = 1 generate
Y <= D;
end generate;
TWO_GEN: if C_NB = 2 generate
DATA_WIDTH_GEN2: for i in 0 to C_DW-1 generate
lutout(i*(C_NB+1)/2) <= ((Dreord(i*C_NB) and sel(i*C_NB)) or
(Dreord(i*C_NB+1) and sel(i*C_NB+1)));
Y(i) <= lutout(i*(C_NB+1)/2);
end generate;
end generate;
end imp;
|
-------------------------------------------------------------------------------
-- $Id: mux_onehot.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- mux_onehot - arch and entity
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: mux_onehot.vhd
--
-- Description: Parameterizable multiplexer with one hot select lines
--
--
-------------------------------------------------------------------------------
-- Structure:
-- Multi- use module
--------------------------------------------------------------------------------
-- Author: BLT
-- History:
-- BLT 2/22/01 -- First version
--
-- ALS 3/30/01
-- ^^^^^^
-- Added process to replicate select bus for each of the data buses
-- ~~~~~~
--
-- ALS 4/19/01
-- ^^^^^^
-- Modified assignments of DI and CI to use signals one and zero. VHDL87
-- doesn't support direct assignment of these signals to '0' and '1'.
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
---------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Generic definitions:
--
-- C_DW: Data width of buses entering the mux. Valid range is 1 to 256.
-- C_NB: Number of data buses entering the mux. Valid range is 1 to 64.
--
-- The input data is represented by a one-dimensional bus that is made up
-- of all of the data buses concatenated together. For example, a 4 to 1
-- mux with 2 bit data buses (C_DW=2,C_NB=4) is represented by:
--
-- D = (Bus0Data0, Bus0Data1, Bus1Data0, Bus1Data1, Bus2Data0, Bus2Data1,
-- Bus3Data0, Bus3Data1)
--
-- There is a separate select line for EACH data bit, leaving it to the
-- user to set fanout on the select lines before using this mux. The select
-- bus into the mux is created by concatenating the one-hot select bus for
-- a single output bit as many times as needed for the data width. Continuing
-- the 4 to 1, 2 bit example from above:
--
-- S = (Sel0Data0,Sel1Data0,Sel2Data0,Sel3Data0,
-- Sel0Data1,Sel1Data1,Sel2Data1,Sel3Data1)
--
-- 4/3/01 ALS - modified the code slightly to have the select bus generated
-- from within this code - input select bus is simply one bit per bus
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- UNISIM library is required when Xilinx primitives are instantiated.
library unisim;
use unisim.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_DW: Data width of buses entering the mux. Valid range is 1 to 256.
-- C_NB: Number of data buses entering the mux. Valid range is 1 to 64.
--
-- The input data is represented by a one-dimensional bus that is made up
-- of all of the data buses concatenated together. For example, a 4 to 1
-- mux with 2 bit data buses (C_DW=2,C_NB=4) is represented by:
--
-- D = (Bus0Data0, Bus0Data1, Bus1Data0, Bus1Data1, Bus2Data0, Bus2Data1,
-- Bus3Data0, Bus3Data1)
--
-- There is a separate select line for EACH data bit, leaving it to the
-- user to set fanout on the select lines before using this mux. The select
-- bus into the mux is created by concatenating the one-hot select bus for
-- a single output bit as many times as needed for the data width. Continuing
-- the 4 to 1, 2 bit example from above:
--
-- S = (Sel0Data0,Sel1Data0,Sel2Data0,Sel3Data0,
-- Sel0Data1,Sel1Data1,Sel2Data1,Sel3Data1)
--
-- 4/3/01 ALS - modified the code slightly to have the select bus generated
-- from within this code - input select bus is simply one bit per bus
--
-- Definition of Ports:
-- input D -- input data bus
-- input S -- input select bus
--
-- output Y -- output bus
-------------------------------------------------------------------------------
entity mux_onehot is
generic( C_DW: integer := 32;
C_NB: integer := 5 );
port(
D: in std_logic_vector(0 to C_DW*C_NB-1);
S: in std_logic_vector(0 to C_NB-1);
Y: out std_logic_vector(0 to C_DW-1));
end mux_onehot;
architecture imp of mux_onehot is
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal Dreord: std_logic_vector(0 to C_DW*((C_NB+1)/2)*2-1);
signal sel: std_logic_vector(0 to C_DW*((C_NB+1)/2)*2-1);
signal lutout: std_logic_vector(0 to (C_DW*(C_NB+1)/2)-1);
signal cyout: std_logic_vector(0 to (C_DW*(C_NB+1)/2)-1);
signal one: std_logic := '1';
signal zero: std_logic := '0';
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- MUXCY used to multiplex busses
component MUXCY
port(
O : out STD_LOGIC;
DI : in STD_LOGIC;
CI : in STD_LOGIC;
S : in STD_LOGIC);
end component;
begin
-- Reorder data buses
REORD: process( D )
variable m,n: integer;
begin
for m in 0 to C_DW-1 loop
for n in 0 to C_NB-1 loop
Dreord( m*C_NB+n) <= D( n*C_DW+m );
end loop;
end loop;
end process REORD;
-------------------------------------------------------------------------------
-- REPSELS_PROCESS
-------------------------------------------------------------------------------
-- The one-hot select bus contains 1-bit for each bus. To more easily
-- parameterize the carry chains and reduce loading on the select bus, these
-- signals are replicated into a bus that replicates the select bits for the
-- data width of the busses
-------------------------------------------------------------------------------
REPSELS_PROCESS : process ( S )
variable i, j : integer;
begin
-- loop through all data bits and busses
for i in 0 to C_DW-1 loop
for j in 0 to C_NB-1 loop
sel(i*C_NB+j) <= S(j);
end loop;
end loop;
end process REPSELS_PROCESS;
-- Handle case for even number of buses
EVEN_GEN: if C_NB rem 2 = 0 and C_NB /= 2 generate
DATA_WIDTH_GEN: for i in 0 to C_DW-1 generate
lutout(i*(C_NB+1)/2) <= not((Dreord(i*C_NB) and sel(i*C_NB)) or
(Dreord(i*C_NB+1) and sel(i*C_NB+1)));
CYMUX_FIRST: MUXCY
port map (CI=> zero,
DI=> one,
S=>lutout(i*(C_NB+1)/2),
O=>cyout(i*(C_NB+1)/2));
NUM_BUSES_GEN: for j in 1 to (C_NB+1)/2-1 generate
lutout(i*(C_NB+1)/2+j) <= not((Dreord(i*C_NB+j*2) and sel(i*C_NB+j*2)) or
(Dreord(i*C_NB+j*2+1) and sel(i*C_NB+j*2+1)));
CARRY_MUX: MUXCY
port map (CI=>cyout(i*(C_NB+1)/2+j-1),
DI=> one,
S=>lutout(i*(C_NB+1)/2+j),
O=>cyout(i*(C_NB+1)/2+j));
end generate;
Y(i) <= cyout(i*(C_NB+1)/2+(C_NB+1)/2-1);
end generate;
end generate;
-- Handle case for odd number of buses
ODD_GEN: if C_NB rem 2 /= 0 and C_NB /= 1 generate
DATA_WIDTH_GEN: for i in 0 to C_DW-1 generate
lutout(i*(C_NB+1)/2) <= not((Dreord(i*C_NB) and sel(i*C_NB)) or
(Dreord(i*C_NB+1) and sel(i*C_NB+1)));
CYMUX_FIRST: MUXCY
port map (CI=> zero,
DI=> one,
S=>lutout(i*(C_NB+1)/2),
O=>cyout(i*(C_NB+1)/2));
NUM_BUSES_GEN: for j in 1 to (C_NB+1)/2-2 generate
lutout(i*(C_NB+1)/2+j) <= not((Dreord(i*C_NB+j*2) and sel(i*C_NB+j*2)) or
(Dreord(i*C_NB+j*2+1) and sel(i*C_NB+j*2+1)));
CARRY_MUX: MUXCY
port map (CI=>cyout(i*(C_NB+1)/2+j-1),
DI=> one,
S=>lutout(i*(C_NB+1)/2+j),
O=>cyout(i*(C_NB+1)/2+j));
end generate;
ODD_BUS_GEN: for j in (C_NB+1)/2-1 to (C_NB+1)/2-1 generate
lutout(i*(C_NB+1)/2+j) <= not((Dreord(i*C_NB+j*2) and sel(i*C_NB+j*2)));
CARRY_MUX: MUXCY
port map (CI=>cyout(i*(C_NB+1)/2+j-1),
DI=> one,
S=>lutout(i*(C_NB+1)/2+j),
O=>cyout(i*(C_NB+1)/2+j));
end generate;
Y(i) <= cyout(i*(C_NB+1)/2+(C_NB+1)/2-1);
end generate;
end generate;
ONE_GEN: if C_NB = 1 generate
Y <= D;
end generate;
TWO_GEN: if C_NB = 2 generate
DATA_WIDTH_GEN2: for i in 0 to C_DW-1 generate
lutout(i*(C_NB+1)/2) <= ((Dreord(i*C_NB) and sel(i*C_NB)) or
(Dreord(i*C_NB+1) and sel(i*C_NB+1)));
Y(i) <= lutout(i*(C_NB+1)/2);
end generate;
end generate;
end imp;
|
-------------------------------------------------------------------------------
-- $Id: mux_onehot.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- mux_onehot - arch and entity
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: mux_onehot.vhd
--
-- Description: Parameterizable multiplexer with one hot select lines
--
--
-------------------------------------------------------------------------------
-- Structure:
-- Multi- use module
--------------------------------------------------------------------------------
-- Author: BLT
-- History:
-- BLT 2/22/01 -- First version
--
-- ALS 3/30/01
-- ^^^^^^
-- Added process to replicate select bus for each of the data buses
-- ~~~~~~
--
-- ALS 4/19/01
-- ^^^^^^
-- Modified assignments of DI and CI to use signals one and zero. VHDL87
-- doesn't support direct assignment of these signals to '0' and '1'.
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
---------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Generic definitions:
--
-- C_DW: Data width of buses entering the mux. Valid range is 1 to 256.
-- C_NB: Number of data buses entering the mux. Valid range is 1 to 64.
--
-- The input data is represented by a one-dimensional bus that is made up
-- of all of the data buses concatenated together. For example, a 4 to 1
-- mux with 2 bit data buses (C_DW=2,C_NB=4) is represented by:
--
-- D = (Bus0Data0, Bus0Data1, Bus1Data0, Bus1Data1, Bus2Data0, Bus2Data1,
-- Bus3Data0, Bus3Data1)
--
-- There is a separate select line for EACH data bit, leaving it to the
-- user to set fanout on the select lines before using this mux. The select
-- bus into the mux is created by concatenating the one-hot select bus for
-- a single output bit as many times as needed for the data width. Continuing
-- the 4 to 1, 2 bit example from above:
--
-- S = (Sel0Data0,Sel1Data0,Sel2Data0,Sel3Data0,
-- Sel0Data1,Sel1Data1,Sel2Data1,Sel3Data1)
--
-- 4/3/01 ALS - modified the code slightly to have the select bus generated
-- from within this code - input select bus is simply one bit per bus
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- UNISIM library is required when Xilinx primitives are instantiated.
library unisim;
use unisim.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_DW: Data width of buses entering the mux. Valid range is 1 to 256.
-- C_NB: Number of data buses entering the mux. Valid range is 1 to 64.
--
-- The input data is represented by a one-dimensional bus that is made up
-- of all of the data buses concatenated together. For example, a 4 to 1
-- mux with 2 bit data buses (C_DW=2,C_NB=4) is represented by:
--
-- D = (Bus0Data0, Bus0Data1, Bus1Data0, Bus1Data1, Bus2Data0, Bus2Data1,
-- Bus3Data0, Bus3Data1)
--
-- There is a separate select line for EACH data bit, leaving it to the
-- user to set fanout on the select lines before using this mux. The select
-- bus into the mux is created by concatenating the one-hot select bus for
-- a single output bit as many times as needed for the data width. Continuing
-- the 4 to 1, 2 bit example from above:
--
-- S = (Sel0Data0,Sel1Data0,Sel2Data0,Sel3Data0,
-- Sel0Data1,Sel1Data1,Sel2Data1,Sel3Data1)
--
-- 4/3/01 ALS - modified the code slightly to have the select bus generated
-- from within this code - input select bus is simply one bit per bus
--
-- Definition of Ports:
-- input D -- input data bus
-- input S -- input select bus
--
-- output Y -- output bus
-------------------------------------------------------------------------------
entity mux_onehot is
generic( C_DW: integer := 32;
C_NB: integer := 5 );
port(
D: in std_logic_vector(0 to C_DW*C_NB-1);
S: in std_logic_vector(0 to C_NB-1);
Y: out std_logic_vector(0 to C_DW-1));
end mux_onehot;
architecture imp of mux_onehot is
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal Dreord: std_logic_vector(0 to C_DW*((C_NB+1)/2)*2-1);
signal sel: std_logic_vector(0 to C_DW*((C_NB+1)/2)*2-1);
signal lutout: std_logic_vector(0 to (C_DW*(C_NB+1)/2)-1);
signal cyout: std_logic_vector(0 to (C_DW*(C_NB+1)/2)-1);
signal one: std_logic := '1';
signal zero: std_logic := '0';
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- MUXCY used to multiplex busses
component MUXCY
port(
O : out STD_LOGIC;
DI : in STD_LOGIC;
CI : in STD_LOGIC;
S : in STD_LOGIC);
end component;
begin
-- Reorder data buses
REORD: process( D )
variable m,n: integer;
begin
for m in 0 to C_DW-1 loop
for n in 0 to C_NB-1 loop
Dreord( m*C_NB+n) <= D( n*C_DW+m );
end loop;
end loop;
end process REORD;
-------------------------------------------------------------------------------
-- REPSELS_PROCESS
-------------------------------------------------------------------------------
-- The one-hot select bus contains 1-bit for each bus. To more easily
-- parameterize the carry chains and reduce loading on the select bus, these
-- signals are replicated into a bus that replicates the select bits for the
-- data width of the busses
-------------------------------------------------------------------------------
REPSELS_PROCESS : process ( S )
variable i, j : integer;
begin
-- loop through all data bits and busses
for i in 0 to C_DW-1 loop
for j in 0 to C_NB-1 loop
sel(i*C_NB+j) <= S(j);
end loop;
end loop;
end process REPSELS_PROCESS;
-- Handle case for even number of buses
EVEN_GEN: if C_NB rem 2 = 0 and C_NB /= 2 generate
DATA_WIDTH_GEN: for i in 0 to C_DW-1 generate
lutout(i*(C_NB+1)/2) <= not((Dreord(i*C_NB) and sel(i*C_NB)) or
(Dreord(i*C_NB+1) and sel(i*C_NB+1)));
CYMUX_FIRST: MUXCY
port map (CI=> zero,
DI=> one,
S=>lutout(i*(C_NB+1)/2),
O=>cyout(i*(C_NB+1)/2));
NUM_BUSES_GEN: for j in 1 to (C_NB+1)/2-1 generate
lutout(i*(C_NB+1)/2+j) <= not((Dreord(i*C_NB+j*2) and sel(i*C_NB+j*2)) or
(Dreord(i*C_NB+j*2+1) and sel(i*C_NB+j*2+1)));
CARRY_MUX: MUXCY
port map (CI=>cyout(i*(C_NB+1)/2+j-1),
DI=> one,
S=>lutout(i*(C_NB+1)/2+j),
O=>cyout(i*(C_NB+1)/2+j));
end generate;
Y(i) <= cyout(i*(C_NB+1)/2+(C_NB+1)/2-1);
end generate;
end generate;
-- Handle case for odd number of buses
ODD_GEN: if C_NB rem 2 /= 0 and C_NB /= 1 generate
DATA_WIDTH_GEN: for i in 0 to C_DW-1 generate
lutout(i*(C_NB+1)/2) <= not((Dreord(i*C_NB) and sel(i*C_NB)) or
(Dreord(i*C_NB+1) and sel(i*C_NB+1)));
CYMUX_FIRST: MUXCY
port map (CI=> zero,
DI=> one,
S=>lutout(i*(C_NB+1)/2),
O=>cyout(i*(C_NB+1)/2));
NUM_BUSES_GEN: for j in 1 to (C_NB+1)/2-2 generate
lutout(i*(C_NB+1)/2+j) <= not((Dreord(i*C_NB+j*2) and sel(i*C_NB+j*2)) or
(Dreord(i*C_NB+j*2+1) and sel(i*C_NB+j*2+1)));
CARRY_MUX: MUXCY
port map (CI=>cyout(i*(C_NB+1)/2+j-1),
DI=> one,
S=>lutout(i*(C_NB+1)/2+j),
O=>cyout(i*(C_NB+1)/2+j));
end generate;
ODD_BUS_GEN: for j in (C_NB+1)/2-1 to (C_NB+1)/2-1 generate
lutout(i*(C_NB+1)/2+j) <= not((Dreord(i*C_NB+j*2) and sel(i*C_NB+j*2)));
CARRY_MUX: MUXCY
port map (CI=>cyout(i*(C_NB+1)/2+j-1),
DI=> one,
S=>lutout(i*(C_NB+1)/2+j),
O=>cyout(i*(C_NB+1)/2+j));
end generate;
Y(i) <= cyout(i*(C_NB+1)/2+(C_NB+1)/2-1);
end generate;
end generate;
ONE_GEN: if C_NB = 1 generate
Y <= D;
end generate;
TWO_GEN: if C_NB = 2 generate
DATA_WIDTH_GEN2: for i in 0 to C_DW-1 generate
lutout(i*(C_NB+1)/2) <= ((Dreord(i*C_NB) and sel(i*C_NB)) or
(Dreord(i*C_NB+1) and sel(i*C_NB+1)));
Y(i) <= lutout(i*(C_NB+1)/2);
end generate;
end generate;
end imp;
|
-------------------------------------------------------------------------------
-- $Id: mux_onehot.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- mux_onehot - arch and entity
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: mux_onehot.vhd
--
-- Description: Parameterizable multiplexer with one hot select lines
--
--
-------------------------------------------------------------------------------
-- Structure:
-- Multi- use module
--------------------------------------------------------------------------------
-- Author: BLT
-- History:
-- BLT 2/22/01 -- First version
--
-- ALS 3/30/01
-- ^^^^^^
-- Added process to replicate select bus for each of the data buses
-- ~~~~~~
--
-- ALS 4/19/01
-- ^^^^^^
-- Modified assignments of DI and CI to use signals one and zero. VHDL87
-- doesn't support direct assignment of these signals to '0' and '1'.
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
---------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Generic definitions:
--
-- C_DW: Data width of buses entering the mux. Valid range is 1 to 256.
-- C_NB: Number of data buses entering the mux. Valid range is 1 to 64.
--
-- The input data is represented by a one-dimensional bus that is made up
-- of all of the data buses concatenated together. For example, a 4 to 1
-- mux with 2 bit data buses (C_DW=2,C_NB=4) is represented by:
--
-- D = (Bus0Data0, Bus0Data1, Bus1Data0, Bus1Data1, Bus2Data0, Bus2Data1,
-- Bus3Data0, Bus3Data1)
--
-- There is a separate select line for EACH data bit, leaving it to the
-- user to set fanout on the select lines before using this mux. The select
-- bus into the mux is created by concatenating the one-hot select bus for
-- a single output bit as many times as needed for the data width. Continuing
-- the 4 to 1, 2 bit example from above:
--
-- S = (Sel0Data0,Sel1Data0,Sel2Data0,Sel3Data0,
-- Sel0Data1,Sel1Data1,Sel2Data1,Sel3Data1)
--
-- 4/3/01 ALS - modified the code slightly to have the select bus generated
-- from within this code - input select bus is simply one bit per bus
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- UNISIM library is required when Xilinx primitives are instantiated.
library unisim;
use unisim.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_DW: Data width of buses entering the mux. Valid range is 1 to 256.
-- C_NB: Number of data buses entering the mux. Valid range is 1 to 64.
--
-- The input data is represented by a one-dimensional bus that is made up
-- of all of the data buses concatenated together. For example, a 4 to 1
-- mux with 2 bit data buses (C_DW=2,C_NB=4) is represented by:
--
-- D = (Bus0Data0, Bus0Data1, Bus1Data0, Bus1Data1, Bus2Data0, Bus2Data1,
-- Bus3Data0, Bus3Data1)
--
-- There is a separate select line for EACH data bit, leaving it to the
-- user to set fanout on the select lines before using this mux. The select
-- bus into the mux is created by concatenating the one-hot select bus for
-- a single output bit as many times as needed for the data width. Continuing
-- the 4 to 1, 2 bit example from above:
--
-- S = (Sel0Data0,Sel1Data0,Sel2Data0,Sel3Data0,
-- Sel0Data1,Sel1Data1,Sel2Data1,Sel3Data1)
--
-- 4/3/01 ALS - modified the code slightly to have the select bus generated
-- from within this code - input select bus is simply one bit per bus
--
-- Definition of Ports:
-- input D -- input data bus
-- input S -- input select bus
--
-- output Y -- output bus
-------------------------------------------------------------------------------
entity mux_onehot is
generic( C_DW: integer := 32;
C_NB: integer := 5 );
port(
D: in std_logic_vector(0 to C_DW*C_NB-1);
S: in std_logic_vector(0 to C_NB-1);
Y: out std_logic_vector(0 to C_DW-1));
end mux_onehot;
architecture imp of mux_onehot is
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal Dreord: std_logic_vector(0 to C_DW*((C_NB+1)/2)*2-1);
signal sel: std_logic_vector(0 to C_DW*((C_NB+1)/2)*2-1);
signal lutout: std_logic_vector(0 to (C_DW*(C_NB+1)/2)-1);
signal cyout: std_logic_vector(0 to (C_DW*(C_NB+1)/2)-1);
signal one: std_logic := '1';
signal zero: std_logic := '0';
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- MUXCY used to multiplex busses
component MUXCY
port(
O : out STD_LOGIC;
DI : in STD_LOGIC;
CI : in STD_LOGIC;
S : in STD_LOGIC);
end component;
begin
-- Reorder data buses
REORD: process( D )
variable m,n: integer;
begin
for m in 0 to C_DW-1 loop
for n in 0 to C_NB-1 loop
Dreord( m*C_NB+n) <= D( n*C_DW+m );
end loop;
end loop;
end process REORD;
-------------------------------------------------------------------------------
-- REPSELS_PROCESS
-------------------------------------------------------------------------------
-- The one-hot select bus contains 1-bit for each bus. To more easily
-- parameterize the carry chains and reduce loading on the select bus, these
-- signals are replicated into a bus that replicates the select bits for the
-- data width of the busses
-------------------------------------------------------------------------------
REPSELS_PROCESS : process ( S )
variable i, j : integer;
begin
-- loop through all data bits and busses
for i in 0 to C_DW-1 loop
for j in 0 to C_NB-1 loop
sel(i*C_NB+j) <= S(j);
end loop;
end loop;
end process REPSELS_PROCESS;
-- Handle case for even number of buses
EVEN_GEN: if C_NB rem 2 = 0 and C_NB /= 2 generate
DATA_WIDTH_GEN: for i in 0 to C_DW-1 generate
lutout(i*(C_NB+1)/2) <= not((Dreord(i*C_NB) and sel(i*C_NB)) or
(Dreord(i*C_NB+1) and sel(i*C_NB+1)));
CYMUX_FIRST: MUXCY
port map (CI=> zero,
DI=> one,
S=>lutout(i*(C_NB+1)/2),
O=>cyout(i*(C_NB+1)/2));
NUM_BUSES_GEN: for j in 1 to (C_NB+1)/2-1 generate
lutout(i*(C_NB+1)/2+j) <= not((Dreord(i*C_NB+j*2) and sel(i*C_NB+j*2)) or
(Dreord(i*C_NB+j*2+1) and sel(i*C_NB+j*2+1)));
CARRY_MUX: MUXCY
port map (CI=>cyout(i*(C_NB+1)/2+j-1),
DI=> one,
S=>lutout(i*(C_NB+1)/2+j),
O=>cyout(i*(C_NB+1)/2+j));
end generate;
Y(i) <= cyout(i*(C_NB+1)/2+(C_NB+1)/2-1);
end generate;
end generate;
-- Handle case for odd number of buses
ODD_GEN: if C_NB rem 2 /= 0 and C_NB /= 1 generate
DATA_WIDTH_GEN: for i in 0 to C_DW-1 generate
lutout(i*(C_NB+1)/2) <= not((Dreord(i*C_NB) and sel(i*C_NB)) or
(Dreord(i*C_NB+1) and sel(i*C_NB+1)));
CYMUX_FIRST: MUXCY
port map (CI=> zero,
DI=> one,
S=>lutout(i*(C_NB+1)/2),
O=>cyout(i*(C_NB+1)/2));
NUM_BUSES_GEN: for j in 1 to (C_NB+1)/2-2 generate
lutout(i*(C_NB+1)/2+j) <= not((Dreord(i*C_NB+j*2) and sel(i*C_NB+j*2)) or
(Dreord(i*C_NB+j*2+1) and sel(i*C_NB+j*2+1)));
CARRY_MUX: MUXCY
port map (CI=>cyout(i*(C_NB+1)/2+j-1),
DI=> one,
S=>lutout(i*(C_NB+1)/2+j),
O=>cyout(i*(C_NB+1)/2+j));
end generate;
ODD_BUS_GEN: for j in (C_NB+1)/2-1 to (C_NB+1)/2-1 generate
lutout(i*(C_NB+1)/2+j) <= not((Dreord(i*C_NB+j*2) and sel(i*C_NB+j*2)));
CARRY_MUX: MUXCY
port map (CI=>cyout(i*(C_NB+1)/2+j-1),
DI=> one,
S=>lutout(i*(C_NB+1)/2+j),
O=>cyout(i*(C_NB+1)/2+j));
end generate;
Y(i) <= cyout(i*(C_NB+1)/2+(C_NB+1)/2-1);
end generate;
end generate;
ONE_GEN: if C_NB = 1 generate
Y <= D;
end generate;
TWO_GEN: if C_NB = 2 generate
DATA_WIDTH_GEN2: for i in 0 to C_DW-1 generate
lutout(i*(C_NB+1)/2) <= ((Dreord(i*C_NB) and sel(i*C_NB)) or
(Dreord(i*C_NB+1) and sel(i*C_NB+1)));
Y(i) <= lutout(i*(C_NB+1)/2);
end generate;
end generate;
end imp;
|
-------------------------------------------------------------------------------
-- $Id: mux_onehot.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- mux_onehot - arch and entity
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: mux_onehot.vhd
--
-- Description: Parameterizable multiplexer with one hot select lines
--
--
-------------------------------------------------------------------------------
-- Structure:
-- Multi- use module
--------------------------------------------------------------------------------
-- Author: BLT
-- History:
-- BLT 2/22/01 -- First version
--
-- ALS 3/30/01
-- ^^^^^^
-- Added process to replicate select bus for each of the data buses
-- ~~~~~~
--
-- ALS 4/19/01
-- ^^^^^^
-- Modified assignments of DI and CI to use signals one and zero. VHDL87
-- doesn't support direct assignment of these signals to '0' and '1'.
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
---------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Generic definitions:
--
-- C_DW: Data width of buses entering the mux. Valid range is 1 to 256.
-- C_NB: Number of data buses entering the mux. Valid range is 1 to 64.
--
-- The input data is represented by a one-dimensional bus that is made up
-- of all of the data buses concatenated together. For example, a 4 to 1
-- mux with 2 bit data buses (C_DW=2,C_NB=4) is represented by:
--
-- D = (Bus0Data0, Bus0Data1, Bus1Data0, Bus1Data1, Bus2Data0, Bus2Data1,
-- Bus3Data0, Bus3Data1)
--
-- There is a separate select line for EACH data bit, leaving it to the
-- user to set fanout on the select lines before using this mux. The select
-- bus into the mux is created by concatenating the one-hot select bus for
-- a single output bit as many times as needed for the data width. Continuing
-- the 4 to 1, 2 bit example from above:
--
-- S = (Sel0Data0,Sel1Data0,Sel2Data0,Sel3Data0,
-- Sel0Data1,Sel1Data1,Sel2Data1,Sel3Data1)
--
-- 4/3/01 ALS - modified the code slightly to have the select bus generated
-- from within this code - input select bus is simply one bit per bus
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- UNISIM library is required when Xilinx primitives are instantiated.
library unisim;
use unisim.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_DW: Data width of buses entering the mux. Valid range is 1 to 256.
-- C_NB: Number of data buses entering the mux. Valid range is 1 to 64.
--
-- The input data is represented by a one-dimensional bus that is made up
-- of all of the data buses concatenated together. For example, a 4 to 1
-- mux with 2 bit data buses (C_DW=2,C_NB=4) is represented by:
--
-- D = (Bus0Data0, Bus0Data1, Bus1Data0, Bus1Data1, Bus2Data0, Bus2Data1,
-- Bus3Data0, Bus3Data1)
--
-- There is a separate select line for EACH data bit, leaving it to the
-- user to set fanout on the select lines before using this mux. The select
-- bus into the mux is created by concatenating the one-hot select bus for
-- a single output bit as many times as needed for the data width. Continuing
-- the 4 to 1, 2 bit example from above:
--
-- S = (Sel0Data0,Sel1Data0,Sel2Data0,Sel3Data0,
-- Sel0Data1,Sel1Data1,Sel2Data1,Sel3Data1)
--
-- 4/3/01 ALS - modified the code slightly to have the select bus generated
-- from within this code - input select bus is simply one bit per bus
--
-- Definition of Ports:
-- input D -- input data bus
-- input S -- input select bus
--
-- output Y -- output bus
-------------------------------------------------------------------------------
entity mux_onehot is
generic( C_DW: integer := 32;
C_NB: integer := 5 );
port(
D: in std_logic_vector(0 to C_DW*C_NB-1);
S: in std_logic_vector(0 to C_NB-1);
Y: out std_logic_vector(0 to C_DW-1));
end mux_onehot;
architecture imp of mux_onehot is
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal Dreord: std_logic_vector(0 to C_DW*((C_NB+1)/2)*2-1);
signal sel: std_logic_vector(0 to C_DW*((C_NB+1)/2)*2-1);
signal lutout: std_logic_vector(0 to (C_DW*(C_NB+1)/2)-1);
signal cyout: std_logic_vector(0 to (C_DW*(C_NB+1)/2)-1);
signal one: std_logic := '1';
signal zero: std_logic := '0';
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- MUXCY used to multiplex busses
component MUXCY
port(
O : out STD_LOGIC;
DI : in STD_LOGIC;
CI : in STD_LOGIC;
S : in STD_LOGIC);
end component;
begin
-- Reorder data buses
REORD: process( D )
variable m,n: integer;
begin
for m in 0 to C_DW-1 loop
for n in 0 to C_NB-1 loop
Dreord( m*C_NB+n) <= D( n*C_DW+m );
end loop;
end loop;
end process REORD;
-------------------------------------------------------------------------------
-- REPSELS_PROCESS
-------------------------------------------------------------------------------
-- The one-hot select bus contains 1-bit for each bus. To more easily
-- parameterize the carry chains and reduce loading on the select bus, these
-- signals are replicated into a bus that replicates the select bits for the
-- data width of the busses
-------------------------------------------------------------------------------
REPSELS_PROCESS : process ( S )
variable i, j : integer;
begin
-- loop through all data bits and busses
for i in 0 to C_DW-1 loop
for j in 0 to C_NB-1 loop
sel(i*C_NB+j) <= S(j);
end loop;
end loop;
end process REPSELS_PROCESS;
-- Handle case for even number of buses
EVEN_GEN: if C_NB rem 2 = 0 and C_NB /= 2 generate
DATA_WIDTH_GEN: for i in 0 to C_DW-1 generate
lutout(i*(C_NB+1)/2) <= not((Dreord(i*C_NB) and sel(i*C_NB)) or
(Dreord(i*C_NB+1) and sel(i*C_NB+1)));
CYMUX_FIRST: MUXCY
port map (CI=> zero,
DI=> one,
S=>lutout(i*(C_NB+1)/2),
O=>cyout(i*(C_NB+1)/2));
NUM_BUSES_GEN: for j in 1 to (C_NB+1)/2-1 generate
lutout(i*(C_NB+1)/2+j) <= not((Dreord(i*C_NB+j*2) and sel(i*C_NB+j*2)) or
(Dreord(i*C_NB+j*2+1) and sel(i*C_NB+j*2+1)));
CARRY_MUX: MUXCY
port map (CI=>cyout(i*(C_NB+1)/2+j-1),
DI=> one,
S=>lutout(i*(C_NB+1)/2+j),
O=>cyout(i*(C_NB+1)/2+j));
end generate;
Y(i) <= cyout(i*(C_NB+1)/2+(C_NB+1)/2-1);
end generate;
end generate;
-- Handle case for odd number of buses
ODD_GEN: if C_NB rem 2 /= 0 and C_NB /= 1 generate
DATA_WIDTH_GEN: for i in 0 to C_DW-1 generate
lutout(i*(C_NB+1)/2) <= not((Dreord(i*C_NB) and sel(i*C_NB)) or
(Dreord(i*C_NB+1) and sel(i*C_NB+1)));
CYMUX_FIRST: MUXCY
port map (CI=> zero,
DI=> one,
S=>lutout(i*(C_NB+1)/2),
O=>cyout(i*(C_NB+1)/2));
NUM_BUSES_GEN: for j in 1 to (C_NB+1)/2-2 generate
lutout(i*(C_NB+1)/2+j) <= not((Dreord(i*C_NB+j*2) and sel(i*C_NB+j*2)) or
(Dreord(i*C_NB+j*2+1) and sel(i*C_NB+j*2+1)));
CARRY_MUX: MUXCY
port map (CI=>cyout(i*(C_NB+1)/2+j-1),
DI=> one,
S=>lutout(i*(C_NB+1)/2+j),
O=>cyout(i*(C_NB+1)/2+j));
end generate;
ODD_BUS_GEN: for j in (C_NB+1)/2-1 to (C_NB+1)/2-1 generate
lutout(i*(C_NB+1)/2+j) <= not((Dreord(i*C_NB+j*2) and sel(i*C_NB+j*2)));
CARRY_MUX: MUXCY
port map (CI=>cyout(i*(C_NB+1)/2+j-1),
DI=> one,
S=>lutout(i*(C_NB+1)/2+j),
O=>cyout(i*(C_NB+1)/2+j));
end generate;
Y(i) <= cyout(i*(C_NB+1)/2+(C_NB+1)/2-1);
end generate;
end generate;
ONE_GEN: if C_NB = 1 generate
Y <= D;
end generate;
TWO_GEN: if C_NB = 2 generate
DATA_WIDTH_GEN2: for i in 0 to C_DW-1 generate
lutout(i*(C_NB+1)/2) <= ((Dreord(i*C_NB) and sel(i*C_NB)) or
(Dreord(i*C_NB+1) and sel(i*C_NB+1)));
Y(i) <= lutout(i*(C_NB+1)/2);
end generate;
end generate;
end imp;
|
-------------------------------------------------------------------------------
-- $Id: mux_onehot.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- mux_onehot - arch and entity
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: mux_onehot.vhd
--
-- Description: Parameterizable multiplexer with one hot select lines
--
--
-------------------------------------------------------------------------------
-- Structure:
-- Multi- use module
--------------------------------------------------------------------------------
-- Author: BLT
-- History:
-- BLT 2/22/01 -- First version
--
-- ALS 3/30/01
-- ^^^^^^
-- Added process to replicate select bus for each of the data buses
-- ~~~~~~
--
-- ALS 4/19/01
-- ^^^^^^
-- Modified assignments of DI and CI to use signals one and zero. VHDL87
-- doesn't support direct assignment of these signals to '0' and '1'.
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
---------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Generic definitions:
--
-- C_DW: Data width of buses entering the mux. Valid range is 1 to 256.
-- C_NB: Number of data buses entering the mux. Valid range is 1 to 64.
--
-- The input data is represented by a one-dimensional bus that is made up
-- of all of the data buses concatenated together. For example, a 4 to 1
-- mux with 2 bit data buses (C_DW=2,C_NB=4) is represented by:
--
-- D = (Bus0Data0, Bus0Data1, Bus1Data0, Bus1Data1, Bus2Data0, Bus2Data1,
-- Bus3Data0, Bus3Data1)
--
-- There is a separate select line for EACH data bit, leaving it to the
-- user to set fanout on the select lines before using this mux. The select
-- bus into the mux is created by concatenating the one-hot select bus for
-- a single output bit as many times as needed for the data width. Continuing
-- the 4 to 1, 2 bit example from above:
--
-- S = (Sel0Data0,Sel1Data0,Sel2Data0,Sel3Data0,
-- Sel0Data1,Sel1Data1,Sel2Data1,Sel3Data1)
--
-- 4/3/01 ALS - modified the code slightly to have the select bus generated
-- from within this code - input select bus is simply one bit per bus
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- UNISIM library is required when Xilinx primitives are instantiated.
library unisim;
use unisim.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_DW: Data width of buses entering the mux. Valid range is 1 to 256.
-- C_NB: Number of data buses entering the mux. Valid range is 1 to 64.
--
-- The input data is represented by a one-dimensional bus that is made up
-- of all of the data buses concatenated together. For example, a 4 to 1
-- mux with 2 bit data buses (C_DW=2,C_NB=4) is represented by:
--
-- D = (Bus0Data0, Bus0Data1, Bus1Data0, Bus1Data1, Bus2Data0, Bus2Data1,
-- Bus3Data0, Bus3Data1)
--
-- There is a separate select line for EACH data bit, leaving it to the
-- user to set fanout on the select lines before using this mux. The select
-- bus into the mux is created by concatenating the one-hot select bus for
-- a single output bit as many times as needed for the data width. Continuing
-- the 4 to 1, 2 bit example from above:
--
-- S = (Sel0Data0,Sel1Data0,Sel2Data0,Sel3Data0,
-- Sel0Data1,Sel1Data1,Sel2Data1,Sel3Data1)
--
-- 4/3/01 ALS - modified the code slightly to have the select bus generated
-- from within this code - input select bus is simply one bit per bus
--
-- Definition of Ports:
-- input D -- input data bus
-- input S -- input select bus
--
-- output Y -- output bus
-------------------------------------------------------------------------------
entity mux_onehot is
generic( C_DW: integer := 32;
C_NB: integer := 5 );
port(
D: in std_logic_vector(0 to C_DW*C_NB-1);
S: in std_logic_vector(0 to C_NB-1);
Y: out std_logic_vector(0 to C_DW-1));
end mux_onehot;
architecture imp of mux_onehot is
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal Dreord: std_logic_vector(0 to C_DW*((C_NB+1)/2)*2-1);
signal sel: std_logic_vector(0 to C_DW*((C_NB+1)/2)*2-1);
signal lutout: std_logic_vector(0 to (C_DW*(C_NB+1)/2)-1);
signal cyout: std_logic_vector(0 to (C_DW*(C_NB+1)/2)-1);
signal one: std_logic := '1';
signal zero: std_logic := '0';
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- MUXCY used to multiplex busses
component MUXCY
port(
O : out STD_LOGIC;
DI : in STD_LOGIC;
CI : in STD_LOGIC;
S : in STD_LOGIC);
end component;
begin
-- Reorder data buses
REORD: process( D )
variable m,n: integer;
begin
for m in 0 to C_DW-1 loop
for n in 0 to C_NB-1 loop
Dreord( m*C_NB+n) <= D( n*C_DW+m );
end loop;
end loop;
end process REORD;
-------------------------------------------------------------------------------
-- REPSELS_PROCESS
-------------------------------------------------------------------------------
-- The one-hot select bus contains 1-bit for each bus. To more easily
-- parameterize the carry chains and reduce loading on the select bus, these
-- signals are replicated into a bus that replicates the select bits for the
-- data width of the busses
-------------------------------------------------------------------------------
REPSELS_PROCESS : process ( S )
variable i, j : integer;
begin
-- loop through all data bits and busses
for i in 0 to C_DW-1 loop
for j in 0 to C_NB-1 loop
sel(i*C_NB+j) <= S(j);
end loop;
end loop;
end process REPSELS_PROCESS;
-- Handle case for even number of buses
EVEN_GEN: if C_NB rem 2 = 0 and C_NB /= 2 generate
DATA_WIDTH_GEN: for i in 0 to C_DW-1 generate
lutout(i*(C_NB+1)/2) <= not((Dreord(i*C_NB) and sel(i*C_NB)) or
(Dreord(i*C_NB+1) and sel(i*C_NB+1)));
CYMUX_FIRST: MUXCY
port map (CI=> zero,
DI=> one,
S=>lutout(i*(C_NB+1)/2),
O=>cyout(i*(C_NB+1)/2));
NUM_BUSES_GEN: for j in 1 to (C_NB+1)/2-1 generate
lutout(i*(C_NB+1)/2+j) <= not((Dreord(i*C_NB+j*2) and sel(i*C_NB+j*2)) or
(Dreord(i*C_NB+j*2+1) and sel(i*C_NB+j*2+1)));
CARRY_MUX: MUXCY
port map (CI=>cyout(i*(C_NB+1)/2+j-1),
DI=> one,
S=>lutout(i*(C_NB+1)/2+j),
O=>cyout(i*(C_NB+1)/2+j));
end generate;
Y(i) <= cyout(i*(C_NB+1)/2+(C_NB+1)/2-1);
end generate;
end generate;
-- Handle case for odd number of buses
ODD_GEN: if C_NB rem 2 /= 0 and C_NB /= 1 generate
DATA_WIDTH_GEN: for i in 0 to C_DW-1 generate
lutout(i*(C_NB+1)/2) <= not((Dreord(i*C_NB) and sel(i*C_NB)) or
(Dreord(i*C_NB+1) and sel(i*C_NB+1)));
CYMUX_FIRST: MUXCY
port map (CI=> zero,
DI=> one,
S=>lutout(i*(C_NB+1)/2),
O=>cyout(i*(C_NB+1)/2));
NUM_BUSES_GEN: for j in 1 to (C_NB+1)/2-2 generate
lutout(i*(C_NB+1)/2+j) <= not((Dreord(i*C_NB+j*2) and sel(i*C_NB+j*2)) or
(Dreord(i*C_NB+j*2+1) and sel(i*C_NB+j*2+1)));
CARRY_MUX: MUXCY
port map (CI=>cyout(i*(C_NB+1)/2+j-1),
DI=> one,
S=>lutout(i*(C_NB+1)/2+j),
O=>cyout(i*(C_NB+1)/2+j));
end generate;
ODD_BUS_GEN: for j in (C_NB+1)/2-1 to (C_NB+1)/2-1 generate
lutout(i*(C_NB+1)/2+j) <= not((Dreord(i*C_NB+j*2) and sel(i*C_NB+j*2)));
CARRY_MUX: MUXCY
port map (CI=>cyout(i*(C_NB+1)/2+j-1),
DI=> one,
S=>lutout(i*(C_NB+1)/2+j),
O=>cyout(i*(C_NB+1)/2+j));
end generate;
Y(i) <= cyout(i*(C_NB+1)/2+(C_NB+1)/2-1);
end generate;
end generate;
ONE_GEN: if C_NB = 1 generate
Y <= D;
end generate;
TWO_GEN: if C_NB = 2 generate
DATA_WIDTH_GEN2: for i in 0 to C_DW-1 generate
lutout(i*(C_NB+1)/2) <= ((Dreord(i*C_NB) and sel(i*C_NB)) or
(Dreord(i*C_NB+1) and sel(i*C_NB+1)));
Y(i) <= lutout(i*(C_NB+1)/2);
end generate;
end generate;
end imp;
|
-------------------------------------------------------------------------------
-- $Id: mux_onehot.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- mux_onehot - arch and entity
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: mux_onehot.vhd
--
-- Description: Parameterizable multiplexer with one hot select lines
--
--
-------------------------------------------------------------------------------
-- Structure:
-- Multi- use module
--------------------------------------------------------------------------------
-- Author: BLT
-- History:
-- BLT 2/22/01 -- First version
--
-- ALS 3/30/01
-- ^^^^^^
-- Added process to replicate select bus for each of the data buses
-- ~~~~~~
--
-- ALS 4/19/01
-- ^^^^^^
-- Modified assignments of DI and CI to use signals one and zero. VHDL87
-- doesn't support direct assignment of these signals to '0' and '1'.
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
---------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Generic definitions:
--
-- C_DW: Data width of buses entering the mux. Valid range is 1 to 256.
-- C_NB: Number of data buses entering the mux. Valid range is 1 to 64.
--
-- The input data is represented by a one-dimensional bus that is made up
-- of all of the data buses concatenated together. For example, a 4 to 1
-- mux with 2 bit data buses (C_DW=2,C_NB=4) is represented by:
--
-- D = (Bus0Data0, Bus0Data1, Bus1Data0, Bus1Data1, Bus2Data0, Bus2Data1,
-- Bus3Data0, Bus3Data1)
--
-- There is a separate select line for EACH data bit, leaving it to the
-- user to set fanout on the select lines before using this mux. The select
-- bus into the mux is created by concatenating the one-hot select bus for
-- a single output bit as many times as needed for the data width. Continuing
-- the 4 to 1, 2 bit example from above:
--
-- S = (Sel0Data0,Sel1Data0,Sel2Data0,Sel3Data0,
-- Sel0Data1,Sel1Data1,Sel2Data1,Sel3Data1)
--
-- 4/3/01 ALS - modified the code slightly to have the select bus generated
-- from within this code - input select bus is simply one bit per bus
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- UNISIM library is required when Xilinx primitives are instantiated.
library unisim;
use unisim.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_DW: Data width of buses entering the mux. Valid range is 1 to 256.
-- C_NB: Number of data buses entering the mux. Valid range is 1 to 64.
--
-- The input data is represented by a one-dimensional bus that is made up
-- of all of the data buses concatenated together. For example, a 4 to 1
-- mux with 2 bit data buses (C_DW=2,C_NB=4) is represented by:
--
-- D = (Bus0Data0, Bus0Data1, Bus1Data0, Bus1Data1, Bus2Data0, Bus2Data1,
-- Bus3Data0, Bus3Data1)
--
-- There is a separate select line for EACH data bit, leaving it to the
-- user to set fanout on the select lines before using this mux. The select
-- bus into the mux is created by concatenating the one-hot select bus for
-- a single output bit as many times as needed for the data width. Continuing
-- the 4 to 1, 2 bit example from above:
--
-- S = (Sel0Data0,Sel1Data0,Sel2Data0,Sel3Data0,
-- Sel0Data1,Sel1Data1,Sel2Data1,Sel3Data1)
--
-- 4/3/01 ALS - modified the code slightly to have the select bus generated
-- from within this code - input select bus is simply one bit per bus
--
-- Definition of Ports:
-- input D -- input data bus
-- input S -- input select bus
--
-- output Y -- output bus
-------------------------------------------------------------------------------
entity mux_onehot is
generic( C_DW: integer := 32;
C_NB: integer := 5 );
port(
D: in std_logic_vector(0 to C_DW*C_NB-1);
S: in std_logic_vector(0 to C_NB-1);
Y: out std_logic_vector(0 to C_DW-1));
end mux_onehot;
architecture imp of mux_onehot is
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal Dreord: std_logic_vector(0 to C_DW*((C_NB+1)/2)*2-1);
signal sel: std_logic_vector(0 to C_DW*((C_NB+1)/2)*2-1);
signal lutout: std_logic_vector(0 to (C_DW*(C_NB+1)/2)-1);
signal cyout: std_logic_vector(0 to (C_DW*(C_NB+1)/2)-1);
signal one: std_logic := '1';
signal zero: std_logic := '0';
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- MUXCY used to multiplex busses
component MUXCY
port(
O : out STD_LOGIC;
DI : in STD_LOGIC;
CI : in STD_LOGIC;
S : in STD_LOGIC);
end component;
begin
-- Reorder data buses
REORD: process( D )
variable m,n: integer;
begin
for m in 0 to C_DW-1 loop
for n in 0 to C_NB-1 loop
Dreord( m*C_NB+n) <= D( n*C_DW+m );
end loop;
end loop;
end process REORD;
-------------------------------------------------------------------------------
-- REPSELS_PROCESS
-------------------------------------------------------------------------------
-- The one-hot select bus contains 1-bit for each bus. To more easily
-- parameterize the carry chains and reduce loading on the select bus, these
-- signals are replicated into a bus that replicates the select bits for the
-- data width of the busses
-------------------------------------------------------------------------------
REPSELS_PROCESS : process ( S )
variable i, j : integer;
begin
-- loop through all data bits and busses
for i in 0 to C_DW-1 loop
for j in 0 to C_NB-1 loop
sel(i*C_NB+j) <= S(j);
end loop;
end loop;
end process REPSELS_PROCESS;
-- Handle case for even number of buses
EVEN_GEN: if C_NB rem 2 = 0 and C_NB /= 2 generate
DATA_WIDTH_GEN: for i in 0 to C_DW-1 generate
lutout(i*(C_NB+1)/2) <= not((Dreord(i*C_NB) and sel(i*C_NB)) or
(Dreord(i*C_NB+1) and sel(i*C_NB+1)));
CYMUX_FIRST: MUXCY
port map (CI=> zero,
DI=> one,
S=>lutout(i*(C_NB+1)/2),
O=>cyout(i*(C_NB+1)/2));
NUM_BUSES_GEN: for j in 1 to (C_NB+1)/2-1 generate
lutout(i*(C_NB+1)/2+j) <= not((Dreord(i*C_NB+j*2) and sel(i*C_NB+j*2)) or
(Dreord(i*C_NB+j*2+1) and sel(i*C_NB+j*2+1)));
CARRY_MUX: MUXCY
port map (CI=>cyout(i*(C_NB+1)/2+j-1),
DI=> one,
S=>lutout(i*(C_NB+1)/2+j),
O=>cyout(i*(C_NB+1)/2+j));
end generate;
Y(i) <= cyout(i*(C_NB+1)/2+(C_NB+1)/2-1);
end generate;
end generate;
-- Handle case for odd number of buses
ODD_GEN: if C_NB rem 2 /= 0 and C_NB /= 1 generate
DATA_WIDTH_GEN: for i in 0 to C_DW-1 generate
lutout(i*(C_NB+1)/2) <= not((Dreord(i*C_NB) and sel(i*C_NB)) or
(Dreord(i*C_NB+1) and sel(i*C_NB+1)));
CYMUX_FIRST: MUXCY
port map (CI=> zero,
DI=> one,
S=>lutout(i*(C_NB+1)/2),
O=>cyout(i*(C_NB+1)/2));
NUM_BUSES_GEN: for j in 1 to (C_NB+1)/2-2 generate
lutout(i*(C_NB+1)/2+j) <= not((Dreord(i*C_NB+j*2) and sel(i*C_NB+j*2)) or
(Dreord(i*C_NB+j*2+1) and sel(i*C_NB+j*2+1)));
CARRY_MUX: MUXCY
port map (CI=>cyout(i*(C_NB+1)/2+j-1),
DI=> one,
S=>lutout(i*(C_NB+1)/2+j),
O=>cyout(i*(C_NB+1)/2+j));
end generate;
ODD_BUS_GEN: for j in (C_NB+1)/2-1 to (C_NB+1)/2-1 generate
lutout(i*(C_NB+1)/2+j) <= not((Dreord(i*C_NB+j*2) and sel(i*C_NB+j*2)));
CARRY_MUX: MUXCY
port map (CI=>cyout(i*(C_NB+1)/2+j-1),
DI=> one,
S=>lutout(i*(C_NB+1)/2+j),
O=>cyout(i*(C_NB+1)/2+j));
end generate;
Y(i) <= cyout(i*(C_NB+1)/2+(C_NB+1)/2-1);
end generate;
end generate;
ONE_GEN: if C_NB = 1 generate
Y <= D;
end generate;
TWO_GEN: if C_NB = 2 generate
DATA_WIDTH_GEN2: for i in 0 to C_DW-1 generate
lutout(i*(C_NB+1)/2) <= ((Dreord(i*C_NB) and sel(i*C_NB)) or
(Dreord(i*C_NB+1) and sel(i*C_NB+1)));
Y(i) <= lutout(i*(C_NB+1)/2);
end generate;
end generate;
end imp;
|
-------------------------------------------------------------------------------
-- $Id: mux_onehot.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- mux_onehot - arch and entity
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: mux_onehot.vhd
--
-- Description: Parameterizable multiplexer with one hot select lines
--
--
-------------------------------------------------------------------------------
-- Structure:
-- Multi- use module
--------------------------------------------------------------------------------
-- Author: BLT
-- History:
-- BLT 2/22/01 -- First version
--
-- ALS 3/30/01
-- ^^^^^^
-- Added process to replicate select bus for each of the data buses
-- ~~~~~~
--
-- ALS 4/19/01
-- ^^^^^^
-- Modified assignments of DI and CI to use signals one and zero. VHDL87
-- doesn't support direct assignment of these signals to '0' and '1'.
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
---------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Generic definitions:
--
-- C_DW: Data width of buses entering the mux. Valid range is 1 to 256.
-- C_NB: Number of data buses entering the mux. Valid range is 1 to 64.
--
-- The input data is represented by a one-dimensional bus that is made up
-- of all of the data buses concatenated together. For example, a 4 to 1
-- mux with 2 bit data buses (C_DW=2,C_NB=4) is represented by:
--
-- D = (Bus0Data0, Bus0Data1, Bus1Data0, Bus1Data1, Bus2Data0, Bus2Data1,
-- Bus3Data0, Bus3Data1)
--
-- There is a separate select line for EACH data bit, leaving it to the
-- user to set fanout on the select lines before using this mux. The select
-- bus into the mux is created by concatenating the one-hot select bus for
-- a single output bit as many times as needed for the data width. Continuing
-- the 4 to 1, 2 bit example from above:
--
-- S = (Sel0Data0,Sel1Data0,Sel2Data0,Sel3Data0,
-- Sel0Data1,Sel1Data1,Sel2Data1,Sel3Data1)
--
-- 4/3/01 ALS - modified the code slightly to have the select bus generated
-- from within this code - input select bus is simply one bit per bus
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- UNISIM library is required when Xilinx primitives are instantiated.
library unisim;
use unisim.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_DW: Data width of buses entering the mux. Valid range is 1 to 256.
-- C_NB: Number of data buses entering the mux. Valid range is 1 to 64.
--
-- The input data is represented by a one-dimensional bus that is made up
-- of all of the data buses concatenated together. For example, a 4 to 1
-- mux with 2 bit data buses (C_DW=2,C_NB=4) is represented by:
--
-- D = (Bus0Data0, Bus0Data1, Bus1Data0, Bus1Data1, Bus2Data0, Bus2Data1,
-- Bus3Data0, Bus3Data1)
--
-- There is a separate select line for EACH data bit, leaving it to the
-- user to set fanout on the select lines before using this mux. The select
-- bus into the mux is created by concatenating the one-hot select bus for
-- a single output bit as many times as needed for the data width. Continuing
-- the 4 to 1, 2 bit example from above:
--
-- S = (Sel0Data0,Sel1Data0,Sel2Data0,Sel3Data0,
-- Sel0Data1,Sel1Data1,Sel2Data1,Sel3Data1)
--
-- 4/3/01 ALS - modified the code slightly to have the select bus generated
-- from within this code - input select bus is simply one bit per bus
--
-- Definition of Ports:
-- input D -- input data bus
-- input S -- input select bus
--
-- output Y -- output bus
-------------------------------------------------------------------------------
entity mux_onehot is
generic( C_DW: integer := 32;
C_NB: integer := 5 );
port(
D: in std_logic_vector(0 to C_DW*C_NB-1);
S: in std_logic_vector(0 to C_NB-1);
Y: out std_logic_vector(0 to C_DW-1));
end mux_onehot;
architecture imp of mux_onehot is
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal Dreord: std_logic_vector(0 to C_DW*((C_NB+1)/2)*2-1);
signal sel: std_logic_vector(0 to C_DW*((C_NB+1)/2)*2-1);
signal lutout: std_logic_vector(0 to (C_DW*(C_NB+1)/2)-1);
signal cyout: std_logic_vector(0 to (C_DW*(C_NB+1)/2)-1);
signal one: std_logic := '1';
signal zero: std_logic := '0';
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- MUXCY used to multiplex busses
component MUXCY
port(
O : out STD_LOGIC;
DI : in STD_LOGIC;
CI : in STD_LOGIC;
S : in STD_LOGIC);
end component;
begin
-- Reorder data buses
REORD: process( D )
variable m,n: integer;
begin
for m in 0 to C_DW-1 loop
for n in 0 to C_NB-1 loop
Dreord( m*C_NB+n) <= D( n*C_DW+m );
end loop;
end loop;
end process REORD;
-------------------------------------------------------------------------------
-- REPSELS_PROCESS
-------------------------------------------------------------------------------
-- The one-hot select bus contains 1-bit for each bus. To more easily
-- parameterize the carry chains and reduce loading on the select bus, these
-- signals are replicated into a bus that replicates the select bits for the
-- data width of the busses
-------------------------------------------------------------------------------
REPSELS_PROCESS : process ( S )
variable i, j : integer;
begin
-- loop through all data bits and busses
for i in 0 to C_DW-1 loop
for j in 0 to C_NB-1 loop
sel(i*C_NB+j) <= S(j);
end loop;
end loop;
end process REPSELS_PROCESS;
-- Handle case for even number of buses
EVEN_GEN: if C_NB rem 2 = 0 and C_NB /= 2 generate
DATA_WIDTH_GEN: for i in 0 to C_DW-1 generate
lutout(i*(C_NB+1)/2) <= not((Dreord(i*C_NB) and sel(i*C_NB)) or
(Dreord(i*C_NB+1) and sel(i*C_NB+1)));
CYMUX_FIRST: MUXCY
port map (CI=> zero,
DI=> one,
S=>lutout(i*(C_NB+1)/2),
O=>cyout(i*(C_NB+1)/2));
NUM_BUSES_GEN: for j in 1 to (C_NB+1)/2-1 generate
lutout(i*(C_NB+1)/2+j) <= not((Dreord(i*C_NB+j*2) and sel(i*C_NB+j*2)) or
(Dreord(i*C_NB+j*2+1) and sel(i*C_NB+j*2+1)));
CARRY_MUX: MUXCY
port map (CI=>cyout(i*(C_NB+1)/2+j-1),
DI=> one,
S=>lutout(i*(C_NB+1)/2+j),
O=>cyout(i*(C_NB+1)/2+j));
end generate;
Y(i) <= cyout(i*(C_NB+1)/2+(C_NB+1)/2-1);
end generate;
end generate;
-- Handle case for odd number of buses
ODD_GEN: if C_NB rem 2 /= 0 and C_NB /= 1 generate
DATA_WIDTH_GEN: for i in 0 to C_DW-1 generate
lutout(i*(C_NB+1)/2) <= not((Dreord(i*C_NB) and sel(i*C_NB)) or
(Dreord(i*C_NB+1) and sel(i*C_NB+1)));
CYMUX_FIRST: MUXCY
port map (CI=> zero,
DI=> one,
S=>lutout(i*(C_NB+1)/2),
O=>cyout(i*(C_NB+1)/2));
NUM_BUSES_GEN: for j in 1 to (C_NB+1)/2-2 generate
lutout(i*(C_NB+1)/2+j) <= not((Dreord(i*C_NB+j*2) and sel(i*C_NB+j*2)) or
(Dreord(i*C_NB+j*2+1) and sel(i*C_NB+j*2+1)));
CARRY_MUX: MUXCY
port map (CI=>cyout(i*(C_NB+1)/2+j-1),
DI=> one,
S=>lutout(i*(C_NB+1)/2+j),
O=>cyout(i*(C_NB+1)/2+j));
end generate;
ODD_BUS_GEN: for j in (C_NB+1)/2-1 to (C_NB+1)/2-1 generate
lutout(i*(C_NB+1)/2+j) <= not((Dreord(i*C_NB+j*2) and sel(i*C_NB+j*2)));
CARRY_MUX: MUXCY
port map (CI=>cyout(i*(C_NB+1)/2+j-1),
DI=> one,
S=>lutout(i*(C_NB+1)/2+j),
O=>cyout(i*(C_NB+1)/2+j));
end generate;
Y(i) <= cyout(i*(C_NB+1)/2+(C_NB+1)/2-1);
end generate;
end generate;
ONE_GEN: if C_NB = 1 generate
Y <= D;
end generate;
TWO_GEN: if C_NB = 2 generate
DATA_WIDTH_GEN2: for i in 0 to C_DW-1 generate
lutout(i*(C_NB+1)/2) <= ((Dreord(i*C_NB) and sel(i*C_NB)) or
(Dreord(i*C_NB+1) and sel(i*C_NB+1)));
Y(i) <= lutout(i*(C_NB+1)/2);
end generate;
end generate;
end imp;
|
-------------------------------------------------------------------------------
-- $Id: mux_onehot.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- mux_onehot - arch and entity
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: mux_onehot.vhd
--
-- Description: Parameterizable multiplexer with one hot select lines
--
--
-------------------------------------------------------------------------------
-- Structure:
-- Multi- use module
--------------------------------------------------------------------------------
-- Author: BLT
-- History:
-- BLT 2/22/01 -- First version
--
-- ALS 3/30/01
-- ^^^^^^
-- Added process to replicate select bus for each of the data buses
-- ~~~~~~
--
-- ALS 4/19/01
-- ^^^^^^
-- Modified assignments of DI and CI to use signals one and zero. VHDL87
-- doesn't support direct assignment of these signals to '0' and '1'.
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
---------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Generic definitions:
--
-- C_DW: Data width of buses entering the mux. Valid range is 1 to 256.
-- C_NB: Number of data buses entering the mux. Valid range is 1 to 64.
--
-- The input data is represented by a one-dimensional bus that is made up
-- of all of the data buses concatenated together. For example, a 4 to 1
-- mux with 2 bit data buses (C_DW=2,C_NB=4) is represented by:
--
-- D = (Bus0Data0, Bus0Data1, Bus1Data0, Bus1Data1, Bus2Data0, Bus2Data1,
-- Bus3Data0, Bus3Data1)
--
-- There is a separate select line for EACH data bit, leaving it to the
-- user to set fanout on the select lines before using this mux. The select
-- bus into the mux is created by concatenating the one-hot select bus for
-- a single output bit as many times as needed for the data width. Continuing
-- the 4 to 1, 2 bit example from above:
--
-- S = (Sel0Data0,Sel1Data0,Sel2Data0,Sel3Data0,
-- Sel0Data1,Sel1Data1,Sel2Data1,Sel3Data1)
--
-- 4/3/01 ALS - modified the code slightly to have the select bus generated
-- from within this code - input select bus is simply one bit per bus
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- UNISIM library is required when Xilinx primitives are instantiated.
library unisim;
use unisim.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_DW: Data width of buses entering the mux. Valid range is 1 to 256.
-- C_NB: Number of data buses entering the mux. Valid range is 1 to 64.
--
-- The input data is represented by a one-dimensional bus that is made up
-- of all of the data buses concatenated together. For example, a 4 to 1
-- mux with 2 bit data buses (C_DW=2,C_NB=4) is represented by:
--
-- D = (Bus0Data0, Bus0Data1, Bus1Data0, Bus1Data1, Bus2Data0, Bus2Data1,
-- Bus3Data0, Bus3Data1)
--
-- There is a separate select line for EACH data bit, leaving it to the
-- user to set fanout on the select lines before using this mux. The select
-- bus into the mux is created by concatenating the one-hot select bus for
-- a single output bit as many times as needed for the data width. Continuing
-- the 4 to 1, 2 bit example from above:
--
-- S = (Sel0Data0,Sel1Data0,Sel2Data0,Sel3Data0,
-- Sel0Data1,Sel1Data1,Sel2Data1,Sel3Data1)
--
-- 4/3/01 ALS - modified the code slightly to have the select bus generated
-- from within this code - input select bus is simply one bit per bus
--
-- Definition of Ports:
-- input D -- input data bus
-- input S -- input select bus
--
-- output Y -- output bus
-------------------------------------------------------------------------------
entity mux_onehot is
generic( C_DW: integer := 32;
C_NB: integer := 5 );
port(
D: in std_logic_vector(0 to C_DW*C_NB-1);
S: in std_logic_vector(0 to C_NB-1);
Y: out std_logic_vector(0 to C_DW-1));
end mux_onehot;
architecture imp of mux_onehot is
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal Dreord: std_logic_vector(0 to C_DW*((C_NB+1)/2)*2-1);
signal sel: std_logic_vector(0 to C_DW*((C_NB+1)/2)*2-1);
signal lutout: std_logic_vector(0 to (C_DW*(C_NB+1)/2)-1);
signal cyout: std_logic_vector(0 to (C_DW*(C_NB+1)/2)-1);
signal one: std_logic := '1';
signal zero: std_logic := '0';
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- MUXCY used to multiplex busses
component MUXCY
port(
O : out STD_LOGIC;
DI : in STD_LOGIC;
CI : in STD_LOGIC;
S : in STD_LOGIC);
end component;
begin
-- Reorder data buses
REORD: process( D )
variable m,n: integer;
begin
for m in 0 to C_DW-1 loop
for n in 0 to C_NB-1 loop
Dreord( m*C_NB+n) <= D( n*C_DW+m );
end loop;
end loop;
end process REORD;
-------------------------------------------------------------------------------
-- REPSELS_PROCESS
-------------------------------------------------------------------------------
-- The one-hot select bus contains 1-bit for each bus. To more easily
-- parameterize the carry chains and reduce loading on the select bus, these
-- signals are replicated into a bus that replicates the select bits for the
-- data width of the busses
-------------------------------------------------------------------------------
REPSELS_PROCESS : process ( S )
variable i, j : integer;
begin
-- loop through all data bits and busses
for i in 0 to C_DW-1 loop
for j in 0 to C_NB-1 loop
sel(i*C_NB+j) <= S(j);
end loop;
end loop;
end process REPSELS_PROCESS;
-- Handle case for even number of buses
EVEN_GEN: if C_NB rem 2 = 0 and C_NB /= 2 generate
DATA_WIDTH_GEN: for i in 0 to C_DW-1 generate
lutout(i*(C_NB+1)/2) <= not((Dreord(i*C_NB) and sel(i*C_NB)) or
(Dreord(i*C_NB+1) and sel(i*C_NB+1)));
CYMUX_FIRST: MUXCY
port map (CI=> zero,
DI=> one,
S=>lutout(i*(C_NB+1)/2),
O=>cyout(i*(C_NB+1)/2));
NUM_BUSES_GEN: for j in 1 to (C_NB+1)/2-1 generate
lutout(i*(C_NB+1)/2+j) <= not((Dreord(i*C_NB+j*2) and sel(i*C_NB+j*2)) or
(Dreord(i*C_NB+j*2+1) and sel(i*C_NB+j*2+1)));
CARRY_MUX: MUXCY
port map (CI=>cyout(i*(C_NB+1)/2+j-1),
DI=> one,
S=>lutout(i*(C_NB+1)/2+j),
O=>cyout(i*(C_NB+1)/2+j));
end generate;
Y(i) <= cyout(i*(C_NB+1)/2+(C_NB+1)/2-1);
end generate;
end generate;
-- Handle case for odd number of buses
ODD_GEN: if C_NB rem 2 /= 0 and C_NB /= 1 generate
DATA_WIDTH_GEN: for i in 0 to C_DW-1 generate
lutout(i*(C_NB+1)/2) <= not((Dreord(i*C_NB) and sel(i*C_NB)) or
(Dreord(i*C_NB+1) and sel(i*C_NB+1)));
CYMUX_FIRST: MUXCY
port map (CI=> zero,
DI=> one,
S=>lutout(i*(C_NB+1)/2),
O=>cyout(i*(C_NB+1)/2));
NUM_BUSES_GEN: for j in 1 to (C_NB+1)/2-2 generate
lutout(i*(C_NB+1)/2+j) <= not((Dreord(i*C_NB+j*2) and sel(i*C_NB+j*2)) or
(Dreord(i*C_NB+j*2+1) and sel(i*C_NB+j*2+1)));
CARRY_MUX: MUXCY
port map (CI=>cyout(i*(C_NB+1)/2+j-1),
DI=> one,
S=>lutout(i*(C_NB+1)/2+j),
O=>cyout(i*(C_NB+1)/2+j));
end generate;
ODD_BUS_GEN: for j in (C_NB+1)/2-1 to (C_NB+1)/2-1 generate
lutout(i*(C_NB+1)/2+j) <= not((Dreord(i*C_NB+j*2) and sel(i*C_NB+j*2)));
CARRY_MUX: MUXCY
port map (CI=>cyout(i*(C_NB+1)/2+j-1),
DI=> one,
S=>lutout(i*(C_NB+1)/2+j),
O=>cyout(i*(C_NB+1)/2+j));
end generate;
Y(i) <= cyout(i*(C_NB+1)/2+(C_NB+1)/2-1);
end generate;
end generate;
ONE_GEN: if C_NB = 1 generate
Y <= D;
end generate;
TWO_GEN: if C_NB = 2 generate
DATA_WIDTH_GEN2: for i in 0 to C_DW-1 generate
lutout(i*(C_NB+1)/2) <= ((Dreord(i*C_NB) and sel(i*C_NB)) or
(Dreord(i*C_NB+1) and sel(i*C_NB+1)));
Y(i) <= lutout(i*(C_NB+1)/2);
end generate;
end generate;
end imp;
|
-------------------------------------------------------------------------------
-- $Id: mux_onehot.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- mux_onehot - arch and entity
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: mux_onehot.vhd
--
-- Description: Parameterizable multiplexer with one hot select lines
--
--
-------------------------------------------------------------------------------
-- Structure:
-- Multi- use module
--------------------------------------------------------------------------------
-- Author: BLT
-- History:
-- BLT 2/22/01 -- First version
--
-- ALS 3/30/01
-- ^^^^^^
-- Added process to replicate select bus for each of the data buses
-- ~~~~~~
--
-- ALS 4/19/01
-- ^^^^^^
-- Modified assignments of DI and CI to use signals one and zero. VHDL87
-- doesn't support direct assignment of these signals to '0' and '1'.
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
---------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Generic definitions:
--
-- C_DW: Data width of buses entering the mux. Valid range is 1 to 256.
-- C_NB: Number of data buses entering the mux. Valid range is 1 to 64.
--
-- The input data is represented by a one-dimensional bus that is made up
-- of all of the data buses concatenated together. For example, a 4 to 1
-- mux with 2 bit data buses (C_DW=2,C_NB=4) is represented by:
--
-- D = (Bus0Data0, Bus0Data1, Bus1Data0, Bus1Data1, Bus2Data0, Bus2Data1,
-- Bus3Data0, Bus3Data1)
--
-- There is a separate select line for EACH data bit, leaving it to the
-- user to set fanout on the select lines before using this mux. The select
-- bus into the mux is created by concatenating the one-hot select bus for
-- a single output bit as many times as needed for the data width. Continuing
-- the 4 to 1, 2 bit example from above:
--
-- S = (Sel0Data0,Sel1Data0,Sel2Data0,Sel3Data0,
-- Sel0Data1,Sel1Data1,Sel2Data1,Sel3Data1)
--
-- 4/3/01 ALS - modified the code slightly to have the select bus generated
-- from within this code - input select bus is simply one bit per bus
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- UNISIM library is required when Xilinx primitives are instantiated.
library unisim;
use unisim.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_DW: Data width of buses entering the mux. Valid range is 1 to 256.
-- C_NB: Number of data buses entering the mux. Valid range is 1 to 64.
--
-- The input data is represented by a one-dimensional bus that is made up
-- of all of the data buses concatenated together. For example, a 4 to 1
-- mux with 2 bit data buses (C_DW=2,C_NB=4) is represented by:
--
-- D = (Bus0Data0, Bus0Data1, Bus1Data0, Bus1Data1, Bus2Data0, Bus2Data1,
-- Bus3Data0, Bus3Data1)
--
-- There is a separate select line for EACH data bit, leaving it to the
-- user to set fanout on the select lines before using this mux. The select
-- bus into the mux is created by concatenating the one-hot select bus for
-- a single output bit as many times as needed for the data width. Continuing
-- the 4 to 1, 2 bit example from above:
--
-- S = (Sel0Data0,Sel1Data0,Sel2Data0,Sel3Data0,
-- Sel0Data1,Sel1Data1,Sel2Data1,Sel3Data1)
--
-- 4/3/01 ALS - modified the code slightly to have the select bus generated
-- from within this code - input select bus is simply one bit per bus
--
-- Definition of Ports:
-- input D -- input data bus
-- input S -- input select bus
--
-- output Y -- output bus
-------------------------------------------------------------------------------
entity mux_onehot is
generic( C_DW: integer := 32;
C_NB: integer := 5 );
port(
D: in std_logic_vector(0 to C_DW*C_NB-1);
S: in std_logic_vector(0 to C_NB-1);
Y: out std_logic_vector(0 to C_DW-1));
end mux_onehot;
architecture imp of mux_onehot is
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal Dreord: std_logic_vector(0 to C_DW*((C_NB+1)/2)*2-1);
signal sel: std_logic_vector(0 to C_DW*((C_NB+1)/2)*2-1);
signal lutout: std_logic_vector(0 to (C_DW*(C_NB+1)/2)-1);
signal cyout: std_logic_vector(0 to (C_DW*(C_NB+1)/2)-1);
signal one: std_logic := '1';
signal zero: std_logic := '0';
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- MUXCY used to multiplex busses
component MUXCY
port(
O : out STD_LOGIC;
DI : in STD_LOGIC;
CI : in STD_LOGIC;
S : in STD_LOGIC);
end component;
begin
-- Reorder data buses
REORD: process( D )
variable m,n: integer;
begin
for m in 0 to C_DW-1 loop
for n in 0 to C_NB-1 loop
Dreord( m*C_NB+n) <= D( n*C_DW+m );
end loop;
end loop;
end process REORD;
-------------------------------------------------------------------------------
-- REPSELS_PROCESS
-------------------------------------------------------------------------------
-- The one-hot select bus contains 1-bit for each bus. To more easily
-- parameterize the carry chains and reduce loading on the select bus, these
-- signals are replicated into a bus that replicates the select bits for the
-- data width of the busses
-------------------------------------------------------------------------------
REPSELS_PROCESS : process ( S )
variable i, j : integer;
begin
-- loop through all data bits and busses
for i in 0 to C_DW-1 loop
for j in 0 to C_NB-1 loop
sel(i*C_NB+j) <= S(j);
end loop;
end loop;
end process REPSELS_PROCESS;
-- Handle case for even number of buses
EVEN_GEN: if C_NB rem 2 = 0 and C_NB /= 2 generate
DATA_WIDTH_GEN: for i in 0 to C_DW-1 generate
lutout(i*(C_NB+1)/2) <= not((Dreord(i*C_NB) and sel(i*C_NB)) or
(Dreord(i*C_NB+1) and sel(i*C_NB+1)));
CYMUX_FIRST: MUXCY
port map (CI=> zero,
DI=> one,
S=>lutout(i*(C_NB+1)/2),
O=>cyout(i*(C_NB+1)/2));
NUM_BUSES_GEN: for j in 1 to (C_NB+1)/2-1 generate
lutout(i*(C_NB+1)/2+j) <= not((Dreord(i*C_NB+j*2) and sel(i*C_NB+j*2)) or
(Dreord(i*C_NB+j*2+1) and sel(i*C_NB+j*2+1)));
CARRY_MUX: MUXCY
port map (CI=>cyout(i*(C_NB+1)/2+j-1),
DI=> one,
S=>lutout(i*(C_NB+1)/2+j),
O=>cyout(i*(C_NB+1)/2+j));
end generate;
Y(i) <= cyout(i*(C_NB+1)/2+(C_NB+1)/2-1);
end generate;
end generate;
-- Handle case for odd number of buses
ODD_GEN: if C_NB rem 2 /= 0 and C_NB /= 1 generate
DATA_WIDTH_GEN: for i in 0 to C_DW-1 generate
lutout(i*(C_NB+1)/2) <= not((Dreord(i*C_NB) and sel(i*C_NB)) or
(Dreord(i*C_NB+1) and sel(i*C_NB+1)));
CYMUX_FIRST: MUXCY
port map (CI=> zero,
DI=> one,
S=>lutout(i*(C_NB+1)/2),
O=>cyout(i*(C_NB+1)/2));
NUM_BUSES_GEN: for j in 1 to (C_NB+1)/2-2 generate
lutout(i*(C_NB+1)/2+j) <= not((Dreord(i*C_NB+j*2) and sel(i*C_NB+j*2)) or
(Dreord(i*C_NB+j*2+1) and sel(i*C_NB+j*2+1)));
CARRY_MUX: MUXCY
port map (CI=>cyout(i*(C_NB+1)/2+j-1),
DI=> one,
S=>lutout(i*(C_NB+1)/2+j),
O=>cyout(i*(C_NB+1)/2+j));
end generate;
ODD_BUS_GEN: for j in (C_NB+1)/2-1 to (C_NB+1)/2-1 generate
lutout(i*(C_NB+1)/2+j) <= not((Dreord(i*C_NB+j*2) and sel(i*C_NB+j*2)));
CARRY_MUX: MUXCY
port map (CI=>cyout(i*(C_NB+1)/2+j-1),
DI=> one,
S=>lutout(i*(C_NB+1)/2+j),
O=>cyout(i*(C_NB+1)/2+j));
end generate;
Y(i) <= cyout(i*(C_NB+1)/2+(C_NB+1)/2-1);
end generate;
end generate;
ONE_GEN: if C_NB = 1 generate
Y <= D;
end generate;
TWO_GEN: if C_NB = 2 generate
DATA_WIDTH_GEN2: for i in 0 to C_DW-1 generate
lutout(i*(C_NB+1)/2) <= ((Dreord(i*C_NB) and sel(i*C_NB)) or
(Dreord(i*C_NB+1) and sel(i*C_NB+1)));
Y(i) <= lutout(i*(C_NB+1)/2);
end generate;
end generate;
end imp;
|
-------------------------------------------------------------------------------
-- $Id: mux_onehot.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- mux_onehot - arch and entity
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: mux_onehot.vhd
--
-- Description: Parameterizable multiplexer with one hot select lines
--
--
-------------------------------------------------------------------------------
-- Structure:
-- Multi- use module
--------------------------------------------------------------------------------
-- Author: BLT
-- History:
-- BLT 2/22/01 -- First version
--
-- ALS 3/30/01
-- ^^^^^^
-- Added process to replicate select bus for each of the data buses
-- ~~~~~~
--
-- ALS 4/19/01
-- ^^^^^^
-- Modified assignments of DI and CI to use signals one and zero. VHDL87
-- doesn't support direct assignment of these signals to '0' and '1'.
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
---------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Generic definitions:
--
-- C_DW: Data width of buses entering the mux. Valid range is 1 to 256.
-- C_NB: Number of data buses entering the mux. Valid range is 1 to 64.
--
-- The input data is represented by a one-dimensional bus that is made up
-- of all of the data buses concatenated together. For example, a 4 to 1
-- mux with 2 bit data buses (C_DW=2,C_NB=4) is represented by:
--
-- D = (Bus0Data0, Bus0Data1, Bus1Data0, Bus1Data1, Bus2Data0, Bus2Data1,
-- Bus3Data0, Bus3Data1)
--
-- There is a separate select line for EACH data bit, leaving it to the
-- user to set fanout on the select lines before using this mux. The select
-- bus into the mux is created by concatenating the one-hot select bus for
-- a single output bit as many times as needed for the data width. Continuing
-- the 4 to 1, 2 bit example from above:
--
-- S = (Sel0Data0,Sel1Data0,Sel2Data0,Sel3Data0,
-- Sel0Data1,Sel1Data1,Sel2Data1,Sel3Data1)
--
-- 4/3/01 ALS - modified the code slightly to have the select bus generated
-- from within this code - input select bus is simply one bit per bus
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- UNISIM library is required when Xilinx primitives are instantiated.
library unisim;
use unisim.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_DW: Data width of buses entering the mux. Valid range is 1 to 256.
-- C_NB: Number of data buses entering the mux. Valid range is 1 to 64.
--
-- The input data is represented by a one-dimensional bus that is made up
-- of all of the data buses concatenated together. For example, a 4 to 1
-- mux with 2 bit data buses (C_DW=2,C_NB=4) is represented by:
--
-- D = (Bus0Data0, Bus0Data1, Bus1Data0, Bus1Data1, Bus2Data0, Bus2Data1,
-- Bus3Data0, Bus3Data1)
--
-- There is a separate select line for EACH data bit, leaving it to the
-- user to set fanout on the select lines before using this mux. The select
-- bus into the mux is created by concatenating the one-hot select bus for
-- a single output bit as many times as needed for the data width. Continuing
-- the 4 to 1, 2 bit example from above:
--
-- S = (Sel0Data0,Sel1Data0,Sel2Data0,Sel3Data0,
-- Sel0Data1,Sel1Data1,Sel2Data1,Sel3Data1)
--
-- 4/3/01 ALS - modified the code slightly to have the select bus generated
-- from within this code - input select bus is simply one bit per bus
--
-- Definition of Ports:
-- input D -- input data bus
-- input S -- input select bus
--
-- output Y -- output bus
-------------------------------------------------------------------------------
entity mux_onehot is
generic( C_DW: integer := 32;
C_NB: integer := 5 );
port(
D: in std_logic_vector(0 to C_DW*C_NB-1);
S: in std_logic_vector(0 to C_NB-1);
Y: out std_logic_vector(0 to C_DW-1));
end mux_onehot;
architecture imp of mux_onehot is
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal Dreord: std_logic_vector(0 to C_DW*((C_NB+1)/2)*2-1);
signal sel: std_logic_vector(0 to C_DW*((C_NB+1)/2)*2-1);
signal lutout: std_logic_vector(0 to (C_DW*(C_NB+1)/2)-1);
signal cyout: std_logic_vector(0 to (C_DW*(C_NB+1)/2)-1);
signal one: std_logic := '1';
signal zero: std_logic := '0';
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- MUXCY used to multiplex busses
component MUXCY
port(
O : out STD_LOGIC;
DI : in STD_LOGIC;
CI : in STD_LOGIC;
S : in STD_LOGIC);
end component;
begin
-- Reorder data buses
REORD: process( D )
variable m,n: integer;
begin
for m in 0 to C_DW-1 loop
for n in 0 to C_NB-1 loop
Dreord( m*C_NB+n) <= D( n*C_DW+m );
end loop;
end loop;
end process REORD;
-------------------------------------------------------------------------------
-- REPSELS_PROCESS
-------------------------------------------------------------------------------
-- The one-hot select bus contains 1-bit for each bus. To more easily
-- parameterize the carry chains and reduce loading on the select bus, these
-- signals are replicated into a bus that replicates the select bits for the
-- data width of the busses
-------------------------------------------------------------------------------
REPSELS_PROCESS : process ( S )
variable i, j : integer;
begin
-- loop through all data bits and busses
for i in 0 to C_DW-1 loop
for j in 0 to C_NB-1 loop
sel(i*C_NB+j) <= S(j);
end loop;
end loop;
end process REPSELS_PROCESS;
-- Handle case for even number of buses
EVEN_GEN: if C_NB rem 2 = 0 and C_NB /= 2 generate
DATA_WIDTH_GEN: for i in 0 to C_DW-1 generate
lutout(i*(C_NB+1)/2) <= not((Dreord(i*C_NB) and sel(i*C_NB)) or
(Dreord(i*C_NB+1) and sel(i*C_NB+1)));
CYMUX_FIRST: MUXCY
port map (CI=> zero,
DI=> one,
S=>lutout(i*(C_NB+1)/2),
O=>cyout(i*(C_NB+1)/2));
NUM_BUSES_GEN: for j in 1 to (C_NB+1)/2-1 generate
lutout(i*(C_NB+1)/2+j) <= not((Dreord(i*C_NB+j*2) and sel(i*C_NB+j*2)) or
(Dreord(i*C_NB+j*2+1) and sel(i*C_NB+j*2+1)));
CARRY_MUX: MUXCY
port map (CI=>cyout(i*(C_NB+1)/2+j-1),
DI=> one,
S=>lutout(i*(C_NB+1)/2+j),
O=>cyout(i*(C_NB+1)/2+j));
end generate;
Y(i) <= cyout(i*(C_NB+1)/2+(C_NB+1)/2-1);
end generate;
end generate;
-- Handle case for odd number of buses
ODD_GEN: if C_NB rem 2 /= 0 and C_NB /= 1 generate
DATA_WIDTH_GEN: for i in 0 to C_DW-1 generate
lutout(i*(C_NB+1)/2) <= not((Dreord(i*C_NB) and sel(i*C_NB)) or
(Dreord(i*C_NB+1) and sel(i*C_NB+1)));
CYMUX_FIRST: MUXCY
port map (CI=> zero,
DI=> one,
S=>lutout(i*(C_NB+1)/2),
O=>cyout(i*(C_NB+1)/2));
NUM_BUSES_GEN: for j in 1 to (C_NB+1)/2-2 generate
lutout(i*(C_NB+1)/2+j) <= not((Dreord(i*C_NB+j*2) and sel(i*C_NB+j*2)) or
(Dreord(i*C_NB+j*2+1) and sel(i*C_NB+j*2+1)));
CARRY_MUX: MUXCY
port map (CI=>cyout(i*(C_NB+1)/2+j-1),
DI=> one,
S=>lutout(i*(C_NB+1)/2+j),
O=>cyout(i*(C_NB+1)/2+j));
end generate;
ODD_BUS_GEN: for j in (C_NB+1)/2-1 to (C_NB+1)/2-1 generate
lutout(i*(C_NB+1)/2+j) <= not((Dreord(i*C_NB+j*2) and sel(i*C_NB+j*2)));
CARRY_MUX: MUXCY
port map (CI=>cyout(i*(C_NB+1)/2+j-1),
DI=> one,
S=>lutout(i*(C_NB+1)/2+j),
O=>cyout(i*(C_NB+1)/2+j));
end generate;
Y(i) <= cyout(i*(C_NB+1)/2+(C_NB+1)/2-1);
end generate;
end generate;
ONE_GEN: if C_NB = 1 generate
Y <= D;
end generate;
TWO_GEN: if C_NB = 2 generate
DATA_WIDTH_GEN2: for i in 0 to C_DW-1 generate
lutout(i*(C_NB+1)/2) <= ((Dreord(i*C_NB) and sel(i*C_NB)) or
(Dreord(i*C_NB+1) and sel(i*C_NB+1)));
Y(i) <= lutout(i*(C_NB+1)/2);
end generate;
end generate;
end imp;
|
-- MDSynth Sound Chip
--
-- Copyright (c) 2012, Meldora Inc.
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification, are permitted provided that the
-- following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice, this list of conditions and the
-- following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the
-- following disclaimer in the documentation and/or other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
-- USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- Numerically-controlled oscillator
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- freq = (50E6 * (phase_delta * 2^octave)) / 2^32
entity nco is
port ( clk: in std_logic;
reset_phase: in std_logic;
ena: in std_logic;
phase_delta: in unsigned(11 downto 0);
octave: in unsigned(3 downto 0);
phase: out unsigned(7 downto 0));
end nco;
architecture nco_arch of nco is
signal phase_accumulator: unsigned(31 downto 0) := to_unsigned(0, 32);
signal toggle: std_logic := '0' ;
signal phase_delta_32: unsigned(31 downto 0) := to_unsigned(0, 32);
begin
process (clk)
begin
if (rising_edge(clk)) then
phase_delta_32(11 downto 0) <= phase_delta;
if (reset_phase = '1') then
phase_accumulator <= to_unsigned(0, 32);
elsif (ena = '1') then
phase_accumulator <= phase_accumulator + (phase_delta_32 sll (to_integer(octave)));
end if;
phase <= phase_accumulator(31 downto 24);
end if;
end process;
end nco_arch;
|
-- This file is automatically generated by a matlab script
--
-- Do not modify directly!
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_signed.all;
package sine_lut_pkg is
constant PHASE_WIDTH : integer := 16;
constant AMPL_WIDTH : integer := 8;
type lut_type is array(0 to 2**(PHASE_WIDTH-2)-1) of std_logic_vector(AMPL_WIDTH-1 downto 0);
constant sine_lut : lut_type := (
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
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conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
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conv_std_logic_vector(99,AMPL_WIDTH),
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conv_std_logic_vector(99,AMPL_WIDTH),
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conv_std_logic_vector(101,AMPL_WIDTH),
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conv_std_logic_vector(101,AMPL_WIDTH),
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conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
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conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
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conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
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conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
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conv_std_logic_vector(103,AMPL_WIDTH),
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conv_std_logic_vector(103,AMPL_WIDTH),
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conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
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conv_std_logic_vector(103,AMPL_WIDTH),
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conv_std_logic_vector(103,AMPL_WIDTH),
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conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
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conv_std_logic_vector(103,AMPL_WIDTH),
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conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
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conv_std_logic_vector(103,AMPL_WIDTH),
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conv_std_logic_vector(104,AMPL_WIDTH),
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conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
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conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
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conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
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conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
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conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
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conv_std_logic_vector(107,AMPL_WIDTH),
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conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
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conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
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conv_std_logic_vector(107,AMPL_WIDTH),
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conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
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conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
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conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
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conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
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conv_std_logic_vector(111,AMPL_WIDTH),
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conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
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conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
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conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
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conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
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conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
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conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
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conv_std_logic_vector(121,AMPL_WIDTH),
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conv_std_logic_vector(121,AMPL_WIDTH),
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conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
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conv_std_logic_vector(121,AMPL_WIDTH),
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conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
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conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
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conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
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conv_std_logic_vector(126,AMPL_WIDTH),
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conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
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conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH)
);
end sine_lut_pkg;
package body sine_lut_pkg is
end sine_lut_pkg; |
-- This file is automatically generated by a matlab script
--
-- Do not modify directly!
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_signed.all;
package sine_lut_pkg is
constant PHASE_WIDTH : integer := 16;
constant AMPL_WIDTH : integer := 8;
type lut_type is array(0 to 2**(PHASE_WIDTH-2)-1) of std_logic_vector(AMPL_WIDTH-1 downto 0);
constant sine_lut : lut_type := (
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
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conv_std_logic_vector(87,AMPL_WIDTH),
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conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
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conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
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conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
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conv_std_logic_vector(88,AMPL_WIDTH),
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conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
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conv_std_logic_vector(88,AMPL_WIDTH),
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conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
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conv_std_logic_vector(88,AMPL_WIDTH),
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conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
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conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
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conv_std_logic_vector(88,AMPL_WIDTH),
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conv_std_logic_vector(88,AMPL_WIDTH),
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conv_std_logic_vector(88,AMPL_WIDTH),
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conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
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conv_std_logic_vector(96,AMPL_WIDTH),
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conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
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conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
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conv_std_logic_vector(96,AMPL_WIDTH),
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conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
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conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
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conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
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conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
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conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
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conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
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conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
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conv_std_logic_vector(98,AMPL_WIDTH),
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conv_std_logic_vector(98,AMPL_WIDTH),
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conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
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conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
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conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
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conv_std_logic_vector(111,AMPL_WIDTH),
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conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
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conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
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conv_std_logic_vector(111,AMPL_WIDTH),
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conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
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conv_std_logic_vector(112,AMPL_WIDTH),
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conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
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conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
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conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
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conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
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conv_std_logic_vector(113,AMPL_WIDTH),
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conv_std_logic_vector(113,AMPL_WIDTH),
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conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
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conv_std_logic_vector(114,AMPL_WIDTH),
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conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
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conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
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conv_std_logic_vector(114,AMPL_WIDTH),
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conv_std_logic_vector(115,AMPL_WIDTH),
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conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
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conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
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conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
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conv_std_logic_vector(120,AMPL_WIDTH),
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conv_std_logic_vector(120,AMPL_WIDTH),
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conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
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conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
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conv_std_logic_vector(123,AMPL_WIDTH),
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conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
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conv_std_logic_vector(123,AMPL_WIDTH),
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conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
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conv_std_logic_vector(123,AMPL_WIDTH),
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conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
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conv_std_logic_vector(124,AMPL_WIDTH),
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conv_std_logic_vector(124,AMPL_WIDTH),
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conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
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conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
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conv_std_logic_vector(124,AMPL_WIDTH),
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conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
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conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
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conv_std_logic_vector(124,AMPL_WIDTH),
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conv_std_logic_vector(124,AMPL_WIDTH),
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conv_std_logic_vector(124,AMPL_WIDTH),
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conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
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conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
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conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
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conv_std_logic_vector(125,AMPL_WIDTH),
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conv_std_logic_vector(125,AMPL_WIDTH),
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conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
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conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
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conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
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conv_std_logic_vector(125,AMPL_WIDTH),
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conv_std_logic_vector(125,AMPL_WIDTH),
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conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
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conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
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conv_std_logic_vector(125,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH)
);
end sine_lut_pkg;
package body sine_lut_pkg is
end sine_lut_pkg; |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2013 Aeroflex Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.config.all;
library techmap;
use techmap.gencomp.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
scantest : integer := CFG_SCAN
);
port (
resetn : in std_ulogic;
clksel : in std_logic_vector(1 downto 0);
clk : in std_ulogic;
lock : out std_ulogic;
errorn : inout std_ulogic;
wdogn : inout std_ulogic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
cb : inout std_logic_vector(7 downto 0);
sdclk : out std_ulogic;
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_ulogic; -- sdram write enable
sdrasn : out std_ulogic; -- sdram ras
sdcasn : out std_ulogic; -- sdram cas
sddqm : out std_logic_vector (3 downto 0); -- sdram dqm
dsutx : out std_ulogic; -- DSU tx data / scanout
dsurx : in std_ulogic; -- DSU rx data / scanin
dsuen : in std_ulogic;
dsubre : in std_ulogic; -- DSU break / scanen
dsuact : out std_ulogic; -- DSU active / NT
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
txd2 : out std_ulogic; -- UART2 tx data
rxd2 : in std_ulogic; -- UART2 rx data
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_ulogic;
writen : out std_ulogic;
read : out std_ulogic;
iosn : out std_ulogic;
romsn : out std_logic_vector (1 downto 0);
brdyn : in std_ulogic;
bexcn : in std_ulogic;
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
i2c_scl : inout std_ulogic;
i2c_sda : inout std_ulogic;
spi_miso : in std_ulogic;
spi_mosi : out std_ulogic;
spi_sck : out std_ulogic;
spi_slvsel : out std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
prom32 : in std_ulogic;
spw_clksel : in std_logic_vector(1 downto 0);
spw_clk : in std_ulogic;
spw_rxd : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxs : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txd : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txs : out std_logic_vector(0 to CFG_SPW_NUM-1);
gtx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(7 downto 0);
erx_dv : in std_ulogic;
etx_clk : in std_ulogic;
etxd : out std_logic_vector(7 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
emdint : in std_ulogic;
emdio : inout std_logic;
emdc : out std_ulogic;
testen : in std_ulogic;
trst : in std_ulogic;
tck : in std_ulogic;
tms : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic
);
end;
architecture rtl of leon3mp is
signal lresetn : std_ulogic;
signal lclksel : std_logic_vector (1 downto 0);
signal lclk : std_ulogic;
signal llock : std_ulogic;
signal lerrorn : std_ulogic;
signal laddress : std_logic_vector(27 downto 0);
signal ldatain : std_logic_vector(31 downto 0);
signal ldataout : std_logic_vector(31 downto 0);
signal ldataen : std_logic_vector(31 downto 0);
signal lcbin : std_logic_vector(7 downto 0);
signal lcbout : std_logic_vector(7 downto 0);
signal lcben : std_logic_vector(7 downto 0);
signal lsdclk : std_ulogic;
signal lsdcsn : std_logic_vector (1 downto 0);
signal lsdwen : std_ulogic;
signal lsdrasn : std_ulogic;
signal lsdcasn : std_ulogic;
signal lsddqm : std_logic_vector (3 downto 0);
signal ldsutx : std_ulogic;
signal ldsurx : std_ulogic;
signal ldsuen : std_ulogic;
signal ldsubre : std_ulogic;
signal ldsuact : std_ulogic;
signal ltxd1 : std_ulogic;
signal lrxd1 : std_ulogic;
signal ltxd2 : std_ulogic;
signal lrxd2 : std_ulogic;
signal lramsn : std_logic_vector (4 downto 0);
signal lramoen : std_logic_vector (4 downto 0);
signal lrwen : std_logic_vector (3 downto 0);
signal loen : std_ulogic;
signal lwriten : std_ulogic;
signal lread : std_ulogic;
signal liosn : std_ulogic;
signal lromsn : std_logic_vector (1 downto 0);
signal lbrdyn : std_ulogic;
signal lbexcn : std_ulogic;
signal lwdogn : std_ulogic;
signal lgpioin : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal lgpioout : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal lgpioen : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal li2c_sclout : std_ulogic;
signal li2c_sclen : std_ulogic;
signal li2c_sclin : std_ulogic;
signal li2c_sdaout : std_ulogic;
signal li2c_sdaen : std_ulogic;
signal li2c_sdain : std_ulogic;
signal lspi_miso : std_ulogic;
signal lspi_mosi : std_ulogic;
signal lspi_sck : std_ulogic;
signal lspi_slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal lprom32 : std_ulogic;
signal lspw_clksel : std_logic_vector (1 downto 0);
signal lspw_clk : std_ulogic;
signal lspw_rxd : std_logic_vector(0 to CFG_SPW_NUM-1);
signal lspw_rxs : std_logic_vector(0 to CFG_SPW_NUM-1);
signal lspw_txd : std_logic_vector(0 to CFG_SPW_NUM-1);
signal lspw_txs : std_logic_vector(0 to CFG_SPW_NUM-1);
signal lgtx_clk : std_ulogic;
signal lerx_clk : std_ulogic;
signal lerxd : std_logic_vector(7 downto 0);
signal lerx_dv : std_ulogic;
signal letx_clk : std_ulogic;
signal letxd : std_logic_vector(7 downto 0);
signal letx_en : std_ulogic;
signal letx_er : std_ulogic;
signal lerx_er : std_ulogic;
signal lerx_col : std_ulogic;
signal lerx_crs : std_ulogic;
signal lemdint : std_ulogic;
signal lemdioin : std_logic;
signal lemdioout : std_logic;
signal lemdioen : std_logic;
signal lemdc : std_ulogic;
signal ltesten : std_ulogic;
signal ltrst : std_ulogic;
signal ltck : std_ulogic;
signal ltms : std_ulogic;
signal ltdi : std_ulogic;
signal ltdo : std_ulogic;
signal ltdoen : std_ulogic;
-- Use for ASIC
--constant padvoltage : integer := x33v;
--constant padlevel : integer := ttl;
-- Use for FPGA
constant padvoltage : integer := x18v;
constant padlevel : integer := cmos;
begin
-- TODO: Move PAD options to 'xconfig'
pads0 : entity work.pads
generic map (
padtech => CFG_PADTECH,
padlevel => padlevel,
padstrength => 10,
jtag_padfilter => pullup,
testen_padfilter => pulldown,
resetn_padfilter => schmitt,
clk_padfilter => 0,
spw_padstrength => 12,
jtag_padstrength => 6,
uart_padstrength => 6,
dsu_padstrength => 6,
padvoltage => padvoltage,
spw_input_type => CFG_SPW_INPUT,
oepol => padoen_polarity(CFG_PADTECH)
)
port map (
---------------------------
--to chip boundary
---------------------------
resetn => resetn ,
clksel => clksel ,
clk => clk ,
lock => lock ,
errorn => errorn ,
address => address ,
data => data ,
cb => cb ,
sdclk => sdclk ,
sdcsn => sdcsn ,
sdwen => sdwen ,
sdrasn => sdrasn ,
sdcasn => sdcasn ,
sddqm => sddqm ,
dsutx => dsutx ,
dsurx => dsurx ,
dsuen => dsuen ,
dsubre => dsubre ,
dsuact => dsuact ,
txd1 => txd1 ,
rxd1 => rxd1 ,
txd2 => txd2 ,
rxd2 => rxd2 ,
ramsn => ramsn ,
ramoen => ramoen ,
rwen => rwen ,
oen => oen ,
writen => writen ,
read => read ,
iosn => iosn ,
romsn => romsn ,
brdyn => brdyn ,
bexcn => bexcn ,
wdogn => wdogn ,
gpio => gpio ,
i2c_scl => i2c_scl ,
i2c_sda => i2c_sda ,
spi_miso => spi_miso ,
spi_mosi => spi_mosi ,
spi_sck => spi_sck ,
spi_slvsel => spi_slvsel,
prom32 => prom32 ,
spw_clksel => spw_clksel,
spw_clk => spw_clk ,
spw_rxd => spw_rxd ,
spw_rxs => spw_rxs ,
spw_txd => spw_txd ,
spw_txs => spw_txs ,
gtx_clk => gtx_clk ,
erx_clk => erx_clk ,
erxd => erxd ,
erx_dv => erx_dv ,
etx_clk => etx_clk ,
etxd => etxd ,
etx_en => etx_en ,
etx_er => etx_er ,
erx_er => erx_er ,
erx_col => erx_col ,
erx_crs => erx_crs ,
emdint => emdint ,
emdio => emdio ,
emdc => emdc ,
testen => testen ,
trst => trst ,
tck => tck ,
tms => tms ,
tdi => tdi ,
tdo => tdo ,
------------------------- ---
--to core
----------------------------
lresetn => lresetn ,
lclksel => lclksel ,
lclk => lclk ,
llock => llock ,
lerrorn => lerrorn ,
laddress => laddress ,
ldatain => ldatain ,
ldataout => ldataout ,
ldataen => ldataen ,
lcbin => lcbin ,
lcbout => lcbout ,
lcben => lcben ,
lsdclk => lsdclk ,
lsdcsn => lsdcsn ,
lsdwen => lsdwen ,
lsdrasn => lsdrasn ,
lsdcasn => lsdcasn ,
lsddqm => lsddqm ,
ldsutx => ldsutx ,
ldsurx => ldsurx ,
ldsuen => ldsuen ,
ldsubre => ldsubre ,
ldsuact => ldsuact ,
ltxd1 => ltxd1 ,
lrxd1 => lrxd1 ,
ltxd2 => ltxd2 ,
lrxd2 => lrxd2 ,
lramsn => lramsn ,
lramoen => lramoen ,
lrwen => lrwen ,
loen => loen ,
lwriten => lwriten ,
lread => lread ,
liosn => liosn ,
lromsn => lromsn ,
lbrdyn => lbrdyn ,
lbexcn => lbexcn ,
lwdogn => lwdogn ,
lgpioin => lgpioin ,
lgpioout => lgpioout ,
lgpioen => lgpioen ,
li2c_sclout => li2c_sclout,
li2c_sclen => li2c_sclen ,
li2c_sclin => li2c_sclin ,
li2c_sdaout => li2c_sdaout,
li2c_sdaen => li2c_sdaen ,
li2c_sdain => li2c_sdain ,
lspi_miso => lspi_miso ,
lspi_mosi => lspi_mosi ,
lspi_sck => lspi_sck ,
lspi_slvsel => lspi_slvsel,
lprom32 => lprom32 ,
lspw_clksel => lspw_clksel,
lspw_clk => lspw_clk ,
lspw_rxd => lspw_rxd ,
lspw_rxs => lspw_rxs ,
lspw_txd => lspw_txd ,
lspw_txs => lspw_txs ,
lgtx_clk => lgtx_clk ,
lerx_clk => lerx_clk ,
lerxd => lerxd ,
lerx_dv => lerx_dv ,
letx_clk => letx_clk ,
letxd => letxd ,
letx_en => letx_en ,
letx_er => letx_er ,
lerx_er => lerx_er ,
lerx_col => lerx_col ,
lerx_crs => lerx_crs ,
lemdint => lemdint ,
lemdioin => lemdioin ,
lemdioout => lemdioout ,
lemdioen => lemdioen ,
lemdc => lemdc ,
ltesten => ltesten ,
ltrst => ltrst ,
ltck => ltck ,
ltms => ltms ,
ltdi => ltdi ,
ltdo => ltdo ,
ltdoen => ltdoen
);
-- ASIC Core
core0 : entity work.core
generic map (
fabtech => CFG_FABTECH,
memtech => CFG_MEMTECH,
padtech => CFG_PADTECH,
clktech => CFG_CLKTECH,
disas => CFG_DISAS,
dbguart => CFG_DUART,
pclow => CFG_PCLOW,
scantest => CFG_SCAN,
bscanen => CFG_BOUNDSCAN_EN,
oepol => padoen_polarity(CFG_PADTECH)
)
port map (
----------------------------
-- ASIC Ports/Pads
----------------------------
resetn => lresetn ,
clksel => lclksel ,
clk => lclk ,
lock => llock ,
errorn => lerrorn ,
address => laddress ,
datain => ldatain ,
dataout => ldataout ,
dataen => ldataen ,
cbin => lcbin ,
cbout => lcbout ,
cben => lcben ,
sdclk => lsdclk ,
sdcsn => lsdcsn ,
sdwen => lsdwen ,
sdrasn => lsdrasn ,
sdcasn => lsdcasn ,
sddqm => lsddqm ,
dsutx => ldsutx ,
dsurx => ldsurx ,
dsuen => ldsuen ,
dsubre => ldsubre ,
dsuact => ldsuact ,
txd1 => ltxd1 ,
rxd1 => lrxd1 ,
txd2 => ltxd2 ,
rxd2 => lrxd2 ,
ramsn => lramsn ,
ramoen => lramoen ,
rwen => lrwen ,
oen => loen ,
writen => lwriten ,
read => lread ,
iosn => liosn ,
romsn => lromsn ,
brdyn => lbrdyn ,
bexcn => lbexcn ,
wdogn => lwdogn ,
gpioin => lgpioin ,
gpioout => lgpioout ,
gpioen => lgpioen ,
i2c_sclout => li2c_sclout,
i2c_sclen => li2c_sclen ,
i2c_sclin => li2c_sclin ,
i2c_sdaout => li2c_sdaout,
i2c_sdaen => li2c_sdaen ,
i2c_sdain => li2c_sdain ,
spi_miso => lspi_miso ,
spi_mosi => lspi_mosi ,
spi_sck => lspi_sck ,
spi_slvsel => lspi_slvsel,
prom32 => lprom32 ,
spw_clksel => lspw_clksel,
spw_clk => lspw_clk ,
spw_rxd => lspw_rxd ,
spw_rxs => lspw_rxs ,
spw_txd => lspw_txd ,
spw_txs => lspw_txs ,
gtx_clk => lgtx_clk ,
erx_clk => lerx_clk ,
erxd => lerxd ,
erx_dv => lerx_dv ,
etx_clk => letx_clk ,
etxd => letxd ,
etx_en => letx_en ,
etx_er => letx_er ,
erx_er => lerx_er ,
erx_col => lerx_col ,
erx_crs => lerx_crs ,
emdint => lemdint ,
emdioin => lemdioin ,
emdioout => lemdioout ,
emdioen => lemdioen ,
emdc => lemdc ,
testen => ltesten ,
trst => ltrst ,
tck => ltck ,
tms => ltms ,
tdi => ltdi ,
tdo => ltdo ,
tdoen => ltdoen ,
----------------------------
-- BSCAN
----------------------------
chain_tck => OPEN ,
chain_tckn => OPEN ,
chain_tdi => OPEN ,
chain_tdo => '0',
bsshft => OPEN ,
bscapt => OPEN ,
bsupdi => OPEN ,
bsupdo => OPEN ,
bsdrive => OPEN ,
bshighz => OPEN
);
-- BSCAN
-- TODO: ADD BSCAN
end;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_12 is
end entity inline_12;
----------------------------------------------------------------
architecture test of inline_12 is
begin
process_3_a : process is
-- code from book:
subtype pixel_row is bit_vector (0 to 15);
variable current_row, mask : pixel_row;
-- end of code from book
begin
current_row := "0000000011111111";
mask := "0000111111110000";
-- code from book:
current_row := current_row and not mask;
current_row := current_row xor X"FFFF";
-- end of code from book
-- code from book (conditions only):
assert B"10001010" sll 3 = B"01010000";
assert B"10001010" sll -2 = B"00100010";
assert B"10010111" srl 2 = B"00100101";
assert B"10010111" srl -6 = B"11000000";
assert B"01001011" sra 3 = B"00001001";
assert B"10010111" sra 3 = B"11110010";
assert B"00001100" sla 2 = B"00110000";
assert B"00010001" sla 2 = B"01000111";
assert B"00010001" sra -2 = B"01000111";
assert B"00110000" sla -2 = B"00001100";
assert B"10010011" rol 1 = B"00100111";
assert B"10010011" ror 1 = B"11001001";
assert "abc" & 'd' = "abcd";
assert 'w' & "xyz" = "wxyz";
assert 'a' & 'b' = "ab";
-- end of code from book
wait;
end process process_3_a;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_12 is
end entity inline_12;
----------------------------------------------------------------
architecture test of inline_12 is
begin
process_3_a : process is
-- code from book:
subtype pixel_row is bit_vector (0 to 15);
variable current_row, mask : pixel_row;
-- end of code from book
begin
current_row := "0000000011111111";
mask := "0000111111110000";
-- code from book:
current_row := current_row and not mask;
current_row := current_row xor X"FFFF";
-- end of code from book
-- code from book (conditions only):
assert B"10001010" sll 3 = B"01010000";
assert B"10001010" sll -2 = B"00100010";
assert B"10010111" srl 2 = B"00100101";
assert B"10010111" srl -6 = B"11000000";
assert B"01001011" sra 3 = B"00001001";
assert B"10010111" sra 3 = B"11110010";
assert B"00001100" sla 2 = B"00110000";
assert B"00010001" sla 2 = B"01000111";
assert B"00010001" sra -2 = B"01000111";
assert B"00110000" sla -2 = B"00001100";
assert B"10010011" rol 1 = B"00100111";
assert B"10010011" ror 1 = B"11001001";
assert "abc" & 'd' = "abcd";
assert 'w' & "xyz" = "wxyz";
assert 'a' & 'b' = "ab";
-- end of code from book
wait;
end process process_3_a;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_12 is
end entity inline_12;
----------------------------------------------------------------
architecture test of inline_12 is
begin
process_3_a : process is
-- code from book:
subtype pixel_row is bit_vector (0 to 15);
variable current_row, mask : pixel_row;
-- end of code from book
begin
current_row := "0000000011111111";
mask := "0000111111110000";
-- code from book:
current_row := current_row and not mask;
current_row := current_row xor X"FFFF";
-- end of code from book
-- code from book (conditions only):
assert B"10001010" sll 3 = B"01010000";
assert B"10001010" sll -2 = B"00100010";
assert B"10010111" srl 2 = B"00100101";
assert B"10010111" srl -6 = B"11000000";
assert B"01001011" sra 3 = B"00001001";
assert B"10010111" sra 3 = B"11110010";
assert B"00001100" sla 2 = B"00110000";
assert B"00010001" sla 2 = B"01000111";
assert B"00010001" sra -2 = B"01000111";
assert B"00110000" sla -2 = B"00001100";
assert B"10010011" rol 1 = B"00100111";
assert B"10010011" ror 1 = B"11001001";
assert "abc" & 'd' = "abcd";
assert 'w' & "xyz" = "wxyz";
assert 'a' & 'b' = "ab";
-- end of code from book
wait;
end process process_3_a;
end architecture test;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3078.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c12s06b02x00p06n01i03078pkg is
type time_cons_vector is array (15 downto 0) of time;
type time_cons_vectorofvector is array (0 to 15) of time_cons_vector;
constant C19 : time_cons_vectorofvector := (others => (others => 3 ns));
end c12s06b02x00p06n01i03078pkg;
use work.c12s06b02x00p06n01i03078pkg.all;
ENTITY c12s06b02x00p06n01i03078ent_a IS
PORT
(
F1: OUT integer ;
F3: IN time_cons_vectorofvector;
FF: OUT integer := 0
);
END c12s06b02x00p06n01i03078ent_a;
ARCHITECTURE c12s06b02x00p06n01i03078arch_a OF c12s06b02x00p06n01i03078ent_a IS
BEGIN
TESTING: PROCESS
begin
F1 <= 3;
wait for 0 ns;
assert F3'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3'active = true)) then
F1 <= 11;
end if;
assert F3(0)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3(0)'active = true)) then
F1 <= 11;
end if;
assert F3(15)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3(15)'active = true)) then
F1 <= 11;
end if;
wait;
END PROCESS;
END c12s06b02x00p06n01i03078arch_a;
use work.c12s06b02x00p06n01i03078pkg.all;
ENTITY c12s06b02x00p06n01i03078ent IS
END c12s06b02x00p06n01i03078ent;
ARCHITECTURE c12s06b02x00p06n01i03078arch OF c12s06b02x00p06n01i03078ent IS
function scalar_complex(s : integer) return time_cons_vectorofvector is
begin
return C19;
end scalar_complex;
component model
PORT
(
F1: OUT integer;
F3: IN time_cons_vectorofvector;
FF: OUT integer
);
end component;
for T1 : model use entity work.c12s06b02x00p06n01i03078ent_a(c12s06b02x00p06n01i03078arch_a);
signal S1 : time_cons_vectorofvector;
signal S3 : integer;
signal SS : integer := 0;
BEGIN
T1: model
port map (
scalar_complex(F1) => S1,
F3 => scalar_complex(S3),
FF => SS
);
TESTING: PROCESS
BEGIN
S3 <= 3;
wait for 0 ns;
assert S1'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert S1(0)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert S1(15)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert NOT(S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
report "***PASSED TEST: c12s06b02x00p06n01i03078"
severity NOTE;
assert (S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
report "***FAILED TEST: c12s06b02x00p06n01i03078 - Not every scalar subelement is active if the source itself is active."
severity ERROR;
wait;
END PROCESS TESTING;
END c12s06b02x00p06n01i03078arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3078.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c12s06b02x00p06n01i03078pkg is
type time_cons_vector is array (15 downto 0) of time;
type time_cons_vectorofvector is array (0 to 15) of time_cons_vector;
constant C19 : time_cons_vectorofvector := (others => (others => 3 ns));
end c12s06b02x00p06n01i03078pkg;
use work.c12s06b02x00p06n01i03078pkg.all;
ENTITY c12s06b02x00p06n01i03078ent_a IS
PORT
(
F1: OUT integer ;
F3: IN time_cons_vectorofvector;
FF: OUT integer := 0
);
END c12s06b02x00p06n01i03078ent_a;
ARCHITECTURE c12s06b02x00p06n01i03078arch_a OF c12s06b02x00p06n01i03078ent_a IS
BEGIN
TESTING: PROCESS
begin
F1 <= 3;
wait for 0 ns;
assert F3'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3'active = true)) then
F1 <= 11;
end if;
assert F3(0)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3(0)'active = true)) then
F1 <= 11;
end if;
assert F3(15)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3(15)'active = true)) then
F1 <= 11;
end if;
wait;
END PROCESS;
END c12s06b02x00p06n01i03078arch_a;
use work.c12s06b02x00p06n01i03078pkg.all;
ENTITY c12s06b02x00p06n01i03078ent IS
END c12s06b02x00p06n01i03078ent;
ARCHITECTURE c12s06b02x00p06n01i03078arch OF c12s06b02x00p06n01i03078ent IS
function scalar_complex(s : integer) return time_cons_vectorofvector is
begin
return C19;
end scalar_complex;
component model
PORT
(
F1: OUT integer;
F3: IN time_cons_vectorofvector;
FF: OUT integer
);
end component;
for T1 : model use entity work.c12s06b02x00p06n01i03078ent_a(c12s06b02x00p06n01i03078arch_a);
signal S1 : time_cons_vectorofvector;
signal S3 : integer;
signal SS : integer := 0;
BEGIN
T1: model
port map (
scalar_complex(F1) => S1,
F3 => scalar_complex(S3),
FF => SS
);
TESTING: PROCESS
BEGIN
S3 <= 3;
wait for 0 ns;
assert S1'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert S1(0)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert S1(15)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert NOT(S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
report "***PASSED TEST: c12s06b02x00p06n01i03078"
severity NOTE;
assert (S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
report "***FAILED TEST: c12s06b02x00p06n01i03078 - Not every scalar subelement is active if the source itself is active."
severity ERROR;
wait;
END PROCESS TESTING;
END c12s06b02x00p06n01i03078arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3078.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c12s06b02x00p06n01i03078pkg is
type time_cons_vector is array (15 downto 0) of time;
type time_cons_vectorofvector is array (0 to 15) of time_cons_vector;
constant C19 : time_cons_vectorofvector := (others => (others => 3 ns));
end c12s06b02x00p06n01i03078pkg;
use work.c12s06b02x00p06n01i03078pkg.all;
ENTITY c12s06b02x00p06n01i03078ent_a IS
PORT
(
F1: OUT integer ;
F3: IN time_cons_vectorofvector;
FF: OUT integer := 0
);
END c12s06b02x00p06n01i03078ent_a;
ARCHITECTURE c12s06b02x00p06n01i03078arch_a OF c12s06b02x00p06n01i03078ent_a IS
BEGIN
TESTING: PROCESS
begin
F1 <= 3;
wait for 0 ns;
assert F3'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3'active = true)) then
F1 <= 11;
end if;
assert F3(0)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3(0)'active = true)) then
F1 <= 11;
end if;
assert F3(15)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3(15)'active = true)) then
F1 <= 11;
end if;
wait;
END PROCESS;
END c12s06b02x00p06n01i03078arch_a;
use work.c12s06b02x00p06n01i03078pkg.all;
ENTITY c12s06b02x00p06n01i03078ent IS
END c12s06b02x00p06n01i03078ent;
ARCHITECTURE c12s06b02x00p06n01i03078arch OF c12s06b02x00p06n01i03078ent IS
function scalar_complex(s : integer) return time_cons_vectorofvector is
begin
return C19;
end scalar_complex;
component model
PORT
(
F1: OUT integer;
F3: IN time_cons_vectorofvector;
FF: OUT integer
);
end component;
for T1 : model use entity work.c12s06b02x00p06n01i03078ent_a(c12s06b02x00p06n01i03078arch_a);
signal S1 : time_cons_vectorofvector;
signal S3 : integer;
signal SS : integer := 0;
BEGIN
T1: model
port map (
scalar_complex(F1) => S1,
F3 => scalar_complex(S3),
FF => SS
);
TESTING: PROCESS
BEGIN
S3 <= 3;
wait for 0 ns;
assert S1'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert S1(0)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert S1(15)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert NOT(S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
report "***PASSED TEST: c12s06b02x00p06n01i03078"
severity NOTE;
assert (S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
report "***FAILED TEST: c12s06b02x00p06n01i03078 - Not every scalar subelement is active if the source itself is active."
severity ERROR;
wait;
END PROCESS TESTING;
END c12s06b02x00p06n01i03078arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.constants.all;
use work.rgbctrl_wb8_init.all;
entity rgbctrl_wb8 is
generic(
CLOCKFREQ: integer := (50 * 1000 * 1000) -- frequency (MHz)
);
-- signal naming according to Wishbone B4 spec
port(
CLK_I: in std_logic;
STB_I: in std_logic;
WE_I: in std_logic;
ADR_I: in std_logic_vector(XLEN-1 downto 0);
DAT_I: in std_logic_vector(7 downto 0);
DAT_O: out std_logic_vector(7 downto 0);
ACK_O: out std_logic;
-- RGB control signal
O_rgb_ctrl: out std_logic
);
end rgbctrl_wb8;
architecture Behavioral of rgbctrl_wb8 is
signal ram: store_t := RAM_INIT;
attribute ramstyle : string;
attribute ramstyle of ram : signal is "no_rw_check";
constant TCL: integer := (1000 * 1000 * 1000) / CLOCKFREQ; -- time per clock interval (ns)
-- timing for ws8212b
constant T0H: integer := 400; -- high time for 0 bit (ns)
constant T0L: integer := 800; -- low time for 0 bit (ns)
constant T1H: integer := 800; -- high time for 1 bit (ns)
constant T1L: integer := 400; -- low time for 1 bit (ns)
constant RES: integer := 60000; -- reset time (ns)
constant T0H_CLKS: integer := T0H / TCL; -- clock cycles for 0 bit, high
constant T0L_CLKS: integer := T0L / TCL; -- clock cycles for 0 bit, low
constant T1H_CLKS: integer := T1H / TCL; -- clock cycles for 1 bit, high
constant T1L_CLKS: integer := T1L / TCL; -- clock cycles for 1 bit, low
constant RES_CLKS: integer := RES / TCL; -- clock cycles for reset, low
-- counter to keep track of byte address in RAM
signal next_rgb_addr: integer range 0 to ((2**ADDRLEN) - 1) := 0;
-- register to keep RGB-byte to be serialized
signal next_rgb_byte: std_logic_vector(7 downto 0) := X"00";
begin
-- process to generate RGB control signal
process(CLK_I)
-- clock counter for timing
variable clkcounter: integer range 0 to (RES_CLKS + 1) := 0;
-- variable for current byte
variable current_byte: std_logic_vector(7 downto 0) := X"00";
-- alias for current bit to be output
alias current_bit: std_logic is current_byte(7);
-- counter to keep track of number of output bits
variable bitcounter: integer range 0 to 7 := 0;
-- states for state machine
type states_t is (GETBYTE, OUT_RESET, SETUP_HIGH, OUT_HIGH, SETUP_LOW, OUT_LOW);
variable state: states_t := GETBYTE;
begin
if rising_edge(CLK_I) then
-- keep rgb control signal low by default
O_rgb_ctrl <= '0';
-- It's the final countdown... for timing
clkcounter := clkcounter - 1;
case state is
when GETBYTE =>
-- put byte read by the RAM process into our buffer
current_byte := next_rgb_byte;
if next_rgb_addr = 0 then
clkcounter := RES_CLKS;
state := OUT_RESET;
else
state := SETUP_HIGH;
end if;
next_rgb_addr <= next_rgb_addr + 1;
bitcounter := 0;
when OUT_RESET =>
if clkcounter = 0 then
-- done waiting!
state := SETUP_HIGH;
end if;
when SETUP_HIGH =>
-- determine length of high-output phase
if current_bit = '0' then
clkcounter := T0H_CLKS;
else
clkcounter := T1H_CLKS;
end if;
state := OUT_HIGH;
when OUT_HIGH =>
-- output HIGH!
O_rgb_ctrl <= '1';
if clkcounter = 0 then
-- done waiting, progress state machine!
state := SETUP_LOW;
end if;
when SETUP_LOW =>
-- determine length of low-output phase
if current_bit = '0' then
clkcounter := T0L_CLKS;
else
clkcounter := T1L_CLKS;
end if;
state := OUT_LOW;
when OUT_LOW =>
if clkcounter = 0 then
-- done waiting, progress!
-- shift current byte one bit position
current_byte := current_byte(6 downto 0) & '0';
if bitcounter = 7 then
-- byte finished, get next byte
state := GETBYTE;
else
-- output next bit of current byte
state := SETUP_HIGH;
end if;
bitcounter := bitcounter + 1;
end if;
end case;
end if;
end process;
-- process to access RAM
process(CLK_I, STB_I)
variable ack: std_logic := '0';
begin
if rising_edge(CLK_I) then
ack := '0';
if STB_I = '1' then
if(WE_I = '1') then
ram(to_integer(unsigned(ADR_I(ADDRLEN-1 downto 0)))) <= DAT_I;
else
DAT_O <= ram(to_integer(unsigned(ADR_I(ADDRLEN-1 downto 0))));
end if;
ack := '1';
end if;
-- read RGB-byte and store into a buffer for consumption by the other process
next_rgb_byte <= ram(next_rgb_addr);
end if;
ACK_O <= STB_I and ack;
end process;
end Behavioral; |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_tx_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fifo_tx_pkg.ALL;
ENTITY fifo_tx_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fifo_tx_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 50 ns;
PRC_RD_EN <= prc_re_i AFTER 50 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fifo_tx_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fifo_tx_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity opfd is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal out2: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vref: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical);
end opfd;
architecture simple of opfd is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "undef";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "undef";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "undef";
attribute SigDir of out2:terminal is "output";
attribute SigType of out2:terminal is "undef";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
terminal net11: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 9.45e-06,
W => Wdiff_0,
Wdiff_0init => 1.545e-05,
scope => private
)
port map(
D => net2,
G => in1,
S => net5
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 9.45e-06,
W => Wdiff_0,
Wdiff_0init => 1.545e-05,
scope => private
)
port map(
D => net1,
G => in2,
S => net5
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 9e-07,
W => W_0,
W_0init => 1.25e-06
)
port map(
D => net5,
G => vbias4,
S => gnd
);
subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 9.45e-06,
W => Wdiff_0,
Wdiff_0init => 1.545e-05,
scope => private
)
port map(
D => net6,
G => in1,
S => net5
);
subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 9.45e-06,
W => Wdiff_0,
Wdiff_0init => 1.545e-05,
scope => private
)
port map(
D => net6,
G => in2,
S => net5
);
subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 1.29e-05,
W => Wcmdiffp_0,
Wcmdiffp_0init => 1.15e-06,
scope => private
)
port map(
D => net6,
G => net6,
S => vdd
);
subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 1.29e-05,
W => Wcmdiffp_0,
Wcmdiffp_0init => 1.15e-06,
scope => private
)
port map(
D => net6,
G => net6,
S => vdd
);
subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 1.29e-05,
W => Wcmdiffp_0,
Wcmdiffp_0init => 1.15e-06,
scope => private
)
port map(
D => net1,
G => net6,
S => vdd
);
subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 1.29e-05,
W => Wcmdiffp_0,
Wcmdiffp_0init => 1.15e-06,
scope => private
)
port map(
D => net2,
G => net6,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => L_2,
L_2init => 3e-06,
W => Wsrc_1,
Wsrc_1init => 1.6e-05,
scope => Wprivate,
symmetry_scope => sym_3
)
port map(
D => net3,
G => net1,
S => gnd
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => L_3,
L_3init => 6.75e-06,
W => Wsrc_1,
Wsrc_1init => 1.6e-05,
scope => Wprivate,
symmetry_scope => sym_3
)
port map(
D => net4,
G => net2,
S => gnd
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 3.5e-07,
W => Wcm_2,
Wcm_2init => 7.75e-06,
scope => private,
symmetry_scope => sym_4
)
port map(
D => net3,
G => net3,
S => vdd
);
subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 3.5e-07,
W => Wcmout_2,
Wcmout_2init => 6.215e-05,
scope => private,
symmetry_scope => sym_4
)
port map(
D => out1,
G => net3,
S => vdd
);
subnet0_subnet4_m1 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 3.5e-07,
W => Wcm_2,
Wcm_2init => 7.75e-06,
scope => private,
symmetry_scope => sym_4
)
port map(
D => net4,
G => net4,
S => vdd
);
subnet0_subnet4_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 3.5e-07,
W => Wcmout_2,
Wcmout_2init => 6.215e-05,
scope => private,
symmetry_scope => sym_4
)
port map(
D => out2,
G => net4,
S => vdd
);
subnet0_subnet5_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 9e-07,
W => Wcursrc_3,
Wcursrc_3init => 7.135e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => out1,
G => vbias4,
S => gnd
);
subnet0_subnet6_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 9e-07,
W => Wcursrc_3,
Wcursrc_3init => 7.135e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => out2,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 1e+07
)
port map(
P => net7,
N => out1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 1e+07
)
port map(
P => net7,
N => out2
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => Ccmfb
)
port map(
P => net10,
N => vref
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => Ccmfb
)
port map(
P => net9,
N => net7
);
subnet1_subnet0_t1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 9e-07,
W => W_1,
W_1init => 1.82e-05
)
port map(
D => net8,
G => vbias1,
S => vdd
);
subnet1_subnet0_t2 : entity pmos(behave)
generic map(
L => Lcmdiff_0,
Lcmdiff_0init => 8.35e-06,
W => Wcmdiff_0,
Wcmdiff_0init => 7.035e-05,
scope => private
)
port map(
D => net10,
G => vref,
S => net8
);
subnet1_subnet0_t3 : entity pmos(behave)
generic map(
L => Lcmdiff_0,
Lcmdiff_0init => 8.35e-06,
W => Wcmdiff_0,
Wcmdiff_0init => 7.035e-05,
scope => private
)
port map(
D => net9,
G => net7,
S => net8
);
subnet1_subnet0_t4 : entity nmos(behave)
generic map(
L => Lcm_0,
Lcm_0init => 8.85e-06,
W => Wcmfbload_0,
Wcmfbload_0init => 1.4e-06,
scope => private
)
port map(
D => net9,
G => net9,
S => gnd
);
subnet1_subnet0_t5 : entity nmos(behave)
generic map(
L => Lcm_0,
Lcm_0init => 8.85e-06,
W => Wcmfbload_0,
Wcmfbload_0init => 1.4e-06,
scope => private
)
port map(
D => net10,
G => net9,
S => gnd
);
subnet1_subnet0_t6 : entity nmos(behave)
generic map(
L => Lcmbias_0,
Lcmbias_0init => 9.5e-07,
W => Wcmbias_0,
Wcmbias_0init => 7.285e-05,
scope => private
)
port map(
D => out1,
G => net10,
S => gnd
);
subnet1_subnet0_t7 : entity nmos(behave)
generic map(
L => Lcmbias_0,
Lcmbias_0init => 9.5e-07,
W => Wcmbias_0,
Wcmbias_0init => 7.285e-05,
scope => private
)
port map(
D => out2,
G => net10,
S => gnd
);
subnet2_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 9e-07,
W => (pfak)*(WBias),
WBiasinit => 4.3e-06
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet2_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 9e-07,
W => (pfak)*(WBias),
WBiasinit => 4.3e-06
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet2_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet2_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 9e-07,
W => WBias,
WBiasinit => 4.3e-06
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet2_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 9e-07,
W => WBias,
WBiasinit => 4.3e-06
)
port map(
D => vbias2,
G => vbias3,
S => net11
);
subnet2_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 9e-07,
W => WBias,
WBiasinit => 4.3e-06
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet2_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 9e-07,
W => WBias,
WBiasinit => 4.3e-06
)
port map(
D => net11,
G => vbias4,
S => gnd
);
end simple;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity i2s_controller is
generic(
C_SLOT_WIDTH : integer := 24; -- Width of one Slot
-- Synthesis parameters
C_MSB_POS : integer := 0; -- MSB Position in the LRCLK frame (0 - MSB first, 1 - LSB first)
C_FRM_SYNC : integer := 1; -- Frame sync type (0 - 50% Duty Cycle, 1 - Pulse mode)
C_LRCLK_POL : integer := 0; -- LRCLK Polarity (0 - Falling edge, 1 - Rising edge)
C_BCLK_POL : integer := 0 -- BCLK Polarity (0 - Falling edge, 1 - Rising edge)
);
port(
CLK_I : in std_logic; -- System clock (100 MHz)
RST_I : in std_logic; -- System reset
BCLK_O : out std_logic; -- Bit Clock
LRCLK_O : out std_logic; -- Frame Clock
SDATA_O : out std_logic; -- Serial Data Output
SDATA_I : in std_logic; -- Serial Data Input
EN_TX_I : in std_logic; -- Enable TX
EN_RX_I : in std_logic; -- Enable RX
OE_S_O : out std_logic; -- Request new Slot Data
WE_S_O : out std_logic; -- Valid Slot Data
D_S_I : in std_logic_vector(C_SLOT_WIDTH-1 downto 0); -- Slot Data in
D_S_O : out std_logic_vector(C_SLOT_WIDTH-1 downto 0); -- Slot Data out
-- Runtime parameters
DIV_RATE_I : in std_logic_vector(7 downto 0);
LRCLK_RATE_I : in std_logic_vector(7 downto 0)
--NR_CHANNELS_I : in std_logic_vector(3 downto 0) -- Number of channels (2 - Stereo, 4- TDM4, 8 - TDM8)
);
end i2s_controller;
architecture Behavioral of i2s_controller is
-- Divide value for the serial clock divider
signal DIV_RATE : natural range 0 to 255 := 0;
signal PREV_DIV_RATE : natural range 0 to 255 := 0;
-- Divide value for the frame clock divider
signal LRCLK_RATE : natural range 0 to 255 := 0;
signal PREV_LRCLK_RATE : natural range 0 to 255 := 0;
-- Counter for the serial clock divider
signal Cnt_Bclk : integer range 0 to 255;
-- Counter for the frame clock divider
signal Cnt_Lrclk : integer range 0 to 512;
signal Cnt_Lrclk_TDM : std_logic;
-- Counter for TDM4 and TDM8 Output Enable signal
signal Cnt_Lrclk_OE_S : std_logic;
-- Counter for TDM4 and TDM8 Write Enable signal
signal Cnt_Lrclk_WE_S : std_logic;
-- Internal synchronous BCLK signal
signal BCLK_int : std_logic;
-- Rising and Falling edge impulses of the serial clock
signal BCLK_Fall : std_logic;
signal BCLK_Rise : std_logic;
-- Internal synchronous LRCLK signal
signal LRCLK_int : std_logic;
-- Data Out internal signal
signal Data_Out_int : std_logic_vector(31 downto 0);
-- Data In internal signal
signal Data_In_int : std_logic_vector(31 downto 0);
-- Data Left, Right and Slot internal signal
signal D_L_O_int : std_logic_vector(C_SLOT_WIDTH-1 downto 0);
signal D_R_O_int : std_logic_vector(C_SLOT_WIDTH-1 downto 0);
signal D_S_O_int : std_logic_vector(C_SLOT_WIDTH-1 downto 0);
--Internal synchronous OE signals
signal OE_R_int : std_logic;
signal OE_L_int : std_logic;
signal OE_S_int : std_logic;
--Internal synchronous WE signals
signal WE_R_int : std_logic;
signal WE_L_int : std_logic;
signal WE_S_int : std_logic;
signal enable : std_logic;
signal BCLK_trailing_edge : std_logic;
signal BCLK_leading_edge : std_logic;
signal EN_RX_INT : std_logic;
signal EN_TX_INT : std_logic;
begin
-- Division rate to ensure 48K sample rate
-- BCLK division rate
--DIV_RATE <= 32 when (NR_CHANNELS_I = "0010") else
-- 16 when (NR_CHANNELS_I = "0100") else
-- 8 when (NR_CHANNELS_I = "1000") else 0;
--
DIV_RATE <= conv_integer(DIV_RATE_I);
-- LRCLK division rate
--LRCLK_RATE <= 32 when (NR_CHANNELS_I = "0010") else
-- 64 when (NR_CHANNELS_I = "0100") else
-- 128 when (NR_CHANNELS_I = "1000") else 0;
--
LRCLK_RATE <= conv_integer(LRCLK_RATE_I);
enable <= '1' when (EN_TX_I = '1') or (EN_RX_I = '1') else '0';
-----------------------------------------------------------------------------------
-- Serial clock generation (BCLK_O, BCLK_FALL, BCLK_RISE)
-----------------------------------------------------------------------------------
SER_CLK: process(CLK_I)
begin
if(CLK_I'event and CLK_I = '1') then
if((RST_I = '1') or (DIV_RATE /= PREV_DIV_RATE) or (enable = '0')) then
Cnt_Bclk <= 0;
BCLK_Int <= '0';
PREV_DIV_RATE <= DIV_RATE;
elsif(Cnt_Bclk = ((DIV_RATE/2)-1)) then
Cnt_Bclk <= 0;
BCLK_int <= not BCLK_int;
else
Cnt_Bclk <= Cnt_Bclk + 1;
end if;
end if;
end process SER_CLK;
-- Serial clock Falling edge, Rising Edge
BCLK_Fall <= '1' when ((Cnt_Bclk = ((DIV_RATE/2)-1)) and (BCLK_int = '1') and (enable = '1')) else '0';
BCLK_Rise <= '1' when ((Cnt_Bclk = ((DIV_RATE/2)-1)) and (BCLK_int = '0') and (enable = '1')) else '0';
BCLK_trailing_edge <= BCLK_Rise when (C_BCLK_POL = 1) else BCLK_Fall;
BCLK_leading_edge <= BCLK_Fall when (C_BCLK_POL = 1) else BCLK_Rise;
-- Serial clock output
BCLK_O <= BCLK_int when enable = '1' else '1';
-----------------------------------------------------------------------------------
-- Frame clock generator (LRCLK_O)
-----------------------------------------------------------------------------------
LRCLK_GEN: process(CLK_I)
begin
if(CLK_I'event and CLK_I = '1') then
-- Reset
if((RST_I = '1') or (LRCLK_RATE /= PREV_LRCLK_RATE) or (enable = '0')) then
Cnt_Lrclk <= 0;
LRCLK_int <= '0';
PREV_LRCLK_RATE <= LRCLK_RATE;
if(C_FRM_SYNC = 1) then
Cnt_Lrclk <= LRCLK_RATE*2;
end if;
-- 50% Duty Cycle LRCLK signal, used for Stereo Mode
elsif(C_FRM_SYNC = 0) then
if (BCLK_trailing_edge = '1') then
if(Cnt_Lrclk = LRCLK_RATE-1) then
Cnt_Lrclk <= 0;
LRCLK_int <= not LRCLK_int;
else
Cnt_Lrclk <= Cnt_Lrclk + 1;
end if;
end if;
-- Pulse mode LRCLK signal, used for TDM4 and TDM8
elsif(C_FRM_SYNC = 1) then
if (BCLK_trailing_edge = '1') then
-- If the number of bits has been sent, pulse new frame
if(Cnt_Lrclk = LRCLK_RATE*2) then
Cnt_Lrclk <= 0;
LRCLK_int <= '1';
else
LRCLK_int <= '0';
Cnt_Lrclk <= Cnt_Lrclk + 1;
end if;
end if;
end if;
end if;
end process LRCLK_GEN;
-- Frame clock output
LRCLK_O <= LRCLK_int when (enable = '1') else '0';
-- Used to change data in the Slots in TDM Mode
Cnt_Lrclk_TDM <= '0' when ((Cnt_Lrclk = 0)or(Cnt_Lrclk = 32)or(Cnt_Lrclk = 64)or(Cnt_Lrclk = 96)or
(Cnt_Lrclk = 128)or(Cnt_Lrclk = 160)or(Cnt_Lrclk=192)or(Cnt_Lrclk=224)or(Cnt_Lrclk=256))
else '1';
-- Used to signal data request (TX)
Cnt_Lrclk_OE_S <= '1' when ((Cnt_Lrclk = 0)or(Cnt_Lrclk = 32)or(Cnt_Lrclk = 64)or(Cnt_Lrclk = 96)or
(Cnt_Lrclk = 128)or(Cnt_Lrclk = 160)or(Cnt_Lrclk=192)or(Cnt_Lrclk=224))
else '0';
-- Used to signal valid data (RX)
Cnt_Lrclk_WE_S <= '1' when (Cnt_Lrclk = 1)or(Cnt_Lrclk = 33)or(Cnt_Lrclk = 65)or(Cnt_Lrclk = 97)or
(Cnt_Lrclk = 129)or(Cnt_Lrclk = 161)or(Cnt_Lrclk=193)or(Cnt_Lrclk=225)
else '0';
-----------------------------------------------------------------------------------
-- Load in parallel data, shift out serial data (SDATA_O)
-----------------------------------------------------------------------------------
SER_DATA_O: process(CLK_I)
begin
if(CLK_I'event and CLK_I = '1') then
-- Reset
if((RST_I = '1') or (enable = '0')) then
-- If 50% Duty Cycle
if(C_FRM_SYNC = 0) then
if((C_MSB_POS = 0)or(C_MSB_POS = 1)) then
Data_Out_int(31) <= '0';
Data_Out_int(30 downto 31-C_SLOT_WIDTH) <= D_S_I;
Data_Out_int(30-C_SLOT_WIDTH downto 0) <= (others => '0');
end if;
-- If Pulse mode
elsif(C_FRM_SYNC = 1) then
if((C_MSB_POS = 0)or(C_MSB_POS = 1)) then
Data_Out_int(31 downto 32-C_SLOT_WIDTH) <= D_S_I;
Data_Out_int(31-C_SLOT_WIDTH downto 0) <= (others => '0');
end if;
end if;
elsif((Cnt_Lrclk_TDM = '0')and(BCLK_leading_edge = '1')) then
if((C_MSB_POS = 0)or(C_MSB_POS = 1)) then
-- 50% Duty Cycle mode
if(C_FRM_SYNC = 0) then
Data_Out_int(31) <= '0';
Data_Out_int(30 downto 31-C_SLOT_WIDTH) <= D_S_I;
Data_Out_int(30-C_SLOT_WIDTH downto 0) <= (others => '0');
-- If Pulse mode
elsif(C_FRM_SYNC = 1) then
Data_Out_int(31 downto 32-C_SLOT_WIDTH) <= D_S_I;
Data_Out_int(31-C_SLOT_WIDTH downto 0) <= (others => '0');
end if;
end if;
-- Shift out serial data
elsif(BCLK_trailing_edge = '1') then
if((C_MSB_POS = 0)or(C_MSB_POS = 1)) then
Data_Out_int <= Data_Out_int(30 downto 0) & '0';
end if;
end if;
end if;
end process SER_DATA_O;
-- Serial data output
SDATA_O <= Data_Out_int(31) when ((EN_TX_I = '1') and (C_MSB_POS = 0)) else
Data_Out_int(0) when ((EN_TX_I = '1') and (C_MSB_POS = 1)) else '0';
-----------------------------------------------------------------------------------
-- Shift in serial data, load out parallel data (SDATA_I)
-----------------------------------------------------------------------------------
SER_DATA_I: process(CLK_I)
begin
if(CLK_I'event and CLK_I = '1') then
-- Reset
if((RST_I = '1') or (enable = '0')) then
Data_In_int <= (others => '0');
D_S_O_int <= (others => '0');
-- 50% Duty Cycle mode
elsif(C_FRM_SYNC = 0) then
-- Stereo mode
-- Load parallel data
-- Depending on BCLK polarity settings
if((Cnt_Lrclk_TDM = '0') and (BCLK_trailing_edge = '1')) then
if((C_MSB_POS = 0)or(C_MSB_POS = 1)) then
D_S_O_int <= Data_In_int(31 downto 32-C_SLOT_WIDTH);
Data_In_int <= (others => '0');
end if;
-- Shift in serial data
-- Depending on BCLK polarity settings
elsif(BCLK_leading_edge = '1') then
if((C_MSB_POS = 0)or(C_MSB_POS = 1)) then
Data_In_int <= Data_In_int(30 downto 0) & SDATA_I;
end if;
end if;
-- Pulse mode
elsif(C_FRM_SYNC = 1) then
-- Load parallel data
-- Depending on BCLK polarity settings
if((Cnt_Lrclk_TDM = '0')and(BCLK_trailing_edge = '1')) then
if((C_MSB_POS = 0)or(C_MSB_POS = 1)) then
D_S_O_int <= Data_In_int(31 downto 32-C_SLOT_WIDTH);
Data_In_int <= (others => '0');
end if;
-- Shift in serial data
-- Depending on BCLK polarity settings
elsif((Lrclk_int = '0')and(BCLK_leading_edge = '1')) then
if((C_MSB_POS = 0)or(C_MSB_POS = 1)) then
Data_In_int <= Data_In_int(30 downto 0) & SDATA_I;
end if;
end if;
end if;
end if;
end process SER_DATA_I;
D_S_O <= D_S_O_int;
------------------------------------------------------------------------
-- Output Enable signals (for FIFO)
------------------------------------------------------------------------
OE_GEN: process(CLK_I)
begin
if(CLK_I'event and CLK_I = '1') then
if((RST_I = '1') or (enable = '0')) then
OE_S_int <= '0';
else
if((Cnt_Lrclk_OE_S = '1')and(BCLK_trailing_edge = '1')) then
OE_S_int <= '1';
else
OE_S_int <= '0';
end if;
end if;
end if;
end process OE_GEN;
EN_TX_INT_GEN: process(CLK_I)
begin
if(CLK_I'event and CLK_I = '1') then
if (RST_I = '1') then
EN_TX_INT <= '0';
else
-- After enabling TX the first request needs to be syncronized to Cnt_Lrclk = 0
-- otherwise we will mess up the channel order.
if((EN_TX_I = '1') and (Lrclk_int = '0') and (Cnt_Lrclk = 0) and (BCLK_trailing_edge = '1')) then
EN_TX_INT <= '1';
elsif (EN_TX_I = '0') then
EN_TX_INT <= '0';
end if;
end if;
end if;
end process EN_TX_INT_GEN;
OE_S_O <= OE_S_int when (EN_TX_INT = '1') else '0';
------------------------------------------------------------------------
-- Write Enable signals (for FIFO)
------------------------------------------------------------------------
WE_GEN: process(CLK_I)
begin
if(CLK_I'event and CLK_I = '1') then
if((RST_I = '1') or (enable = '0')) then
WE_S_int <= '0';
else
-- Depending on BCLK polarity settings
if((Cnt_Lrclk_WE_S = '1')and(BCLK_leading_edge = '1')) then
WE_S_int <= '1';
else
WE_S_int <= '0';
end if;
end if;
end if;
end process WE_GEN;
EN_RX_INT_GEN: process(CLK_I)
begin
if(CLK_I'event and CLK_I = '1') then
if (RST_I = '1') then
EN_RX_INT <= '0';
else
-- After enabling RX the first request needs to be syncronized to Cnt_Lrclk = 31
-- otherwise we will mess up the channel order.
if((EN_RX_I = '1') and (Lrclk_int = '0') and (Cnt_Lrclk = 31) and (BCLK_trailing_edge = '1')) then
EN_RX_INT <= '1';
elsif (EN_RX_I = '0') then
EN_RX_INT <= '0';
end if;
end if;
end if;
end process EN_RX_INT_GEN;
WE_S_O <= WE_S_int when (EN_RX_INT = '1') else '0';
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity i2s_controller is
generic(
C_SLOT_WIDTH : integer := 24; -- Width of one Slot
-- Synthesis parameters
C_MSB_POS : integer := 0; -- MSB Position in the LRCLK frame (0 - MSB first, 1 - LSB first)
C_FRM_SYNC : integer := 1; -- Frame sync type (0 - 50% Duty Cycle, 1 - Pulse mode)
C_LRCLK_POL : integer := 0; -- LRCLK Polarity (0 - Falling edge, 1 - Rising edge)
C_BCLK_POL : integer := 0 -- BCLK Polarity (0 - Falling edge, 1 - Rising edge)
);
port(
CLK_I : in std_logic; -- System clock (100 MHz)
RST_I : in std_logic; -- System reset
BCLK_O : out std_logic; -- Bit Clock
LRCLK_O : out std_logic; -- Frame Clock
SDATA_O : out std_logic; -- Serial Data Output
SDATA_I : in std_logic; -- Serial Data Input
EN_TX_I : in std_logic; -- Enable TX
EN_RX_I : in std_logic; -- Enable RX
OE_S_O : out std_logic; -- Request new Slot Data
WE_S_O : out std_logic; -- Valid Slot Data
D_S_I : in std_logic_vector(C_SLOT_WIDTH-1 downto 0); -- Slot Data in
D_S_O : out std_logic_vector(C_SLOT_WIDTH-1 downto 0); -- Slot Data out
-- Runtime parameters
DIV_RATE_I : in std_logic_vector(7 downto 0);
LRCLK_RATE_I : in std_logic_vector(7 downto 0)
--NR_CHANNELS_I : in std_logic_vector(3 downto 0) -- Number of channels (2 - Stereo, 4- TDM4, 8 - TDM8)
);
end i2s_controller;
architecture Behavioral of i2s_controller is
-- Divide value for the serial clock divider
signal DIV_RATE : natural range 0 to 255 := 0;
signal PREV_DIV_RATE : natural range 0 to 255 := 0;
-- Divide value for the frame clock divider
signal LRCLK_RATE : natural range 0 to 255 := 0;
signal PREV_LRCLK_RATE : natural range 0 to 255 := 0;
-- Counter for the serial clock divider
signal Cnt_Bclk : integer range 0 to 255;
-- Counter for the frame clock divider
signal Cnt_Lrclk : integer range 0 to 512;
signal Cnt_Lrclk_TDM : std_logic;
-- Counter for TDM4 and TDM8 Output Enable signal
signal Cnt_Lrclk_OE_S : std_logic;
-- Counter for TDM4 and TDM8 Write Enable signal
signal Cnt_Lrclk_WE_S : std_logic;
-- Internal synchronous BCLK signal
signal BCLK_int : std_logic;
-- Rising and Falling edge impulses of the serial clock
signal BCLK_Fall : std_logic;
signal BCLK_Rise : std_logic;
-- Internal synchronous LRCLK signal
signal LRCLK_int : std_logic;
-- Data Out internal signal
signal Data_Out_int : std_logic_vector(31 downto 0);
-- Data In internal signal
signal Data_In_int : std_logic_vector(31 downto 0);
-- Data Left, Right and Slot internal signal
signal D_L_O_int : std_logic_vector(C_SLOT_WIDTH-1 downto 0);
signal D_R_O_int : std_logic_vector(C_SLOT_WIDTH-1 downto 0);
signal D_S_O_int : std_logic_vector(C_SLOT_WIDTH-1 downto 0);
--Internal synchronous OE signals
signal OE_R_int : std_logic;
signal OE_L_int : std_logic;
signal OE_S_int : std_logic;
--Internal synchronous WE signals
signal WE_R_int : std_logic;
signal WE_L_int : std_logic;
signal WE_S_int : std_logic;
signal enable : std_logic;
signal BCLK_trailing_edge : std_logic;
signal BCLK_leading_edge : std_logic;
signal EN_RX_INT : std_logic;
signal EN_TX_INT : std_logic;
begin
-- Division rate to ensure 48K sample rate
-- BCLK division rate
--DIV_RATE <= 32 when (NR_CHANNELS_I = "0010") else
-- 16 when (NR_CHANNELS_I = "0100") else
-- 8 when (NR_CHANNELS_I = "1000") else 0;
--
DIV_RATE <= conv_integer(DIV_RATE_I);
-- LRCLK division rate
--LRCLK_RATE <= 32 when (NR_CHANNELS_I = "0010") else
-- 64 when (NR_CHANNELS_I = "0100") else
-- 128 when (NR_CHANNELS_I = "1000") else 0;
--
LRCLK_RATE <= conv_integer(LRCLK_RATE_I);
enable <= '1' when (EN_TX_I = '1') or (EN_RX_I = '1') else '0';
-----------------------------------------------------------------------------------
-- Serial clock generation (BCLK_O, BCLK_FALL, BCLK_RISE)
-----------------------------------------------------------------------------------
SER_CLK: process(CLK_I)
begin
if(CLK_I'event and CLK_I = '1') then
if((RST_I = '1') or (DIV_RATE /= PREV_DIV_RATE) or (enable = '0')) then
Cnt_Bclk <= 0;
BCLK_Int <= '0';
PREV_DIV_RATE <= DIV_RATE;
elsif(Cnt_Bclk = ((DIV_RATE/2)-1)) then
Cnt_Bclk <= 0;
BCLK_int <= not BCLK_int;
else
Cnt_Bclk <= Cnt_Bclk + 1;
end if;
end if;
end process SER_CLK;
-- Serial clock Falling edge, Rising Edge
BCLK_Fall <= '1' when ((Cnt_Bclk = ((DIV_RATE/2)-1)) and (BCLK_int = '1') and (enable = '1')) else '0';
BCLK_Rise <= '1' when ((Cnt_Bclk = ((DIV_RATE/2)-1)) and (BCLK_int = '0') and (enable = '1')) else '0';
BCLK_trailing_edge <= BCLK_Rise when (C_BCLK_POL = 1) else BCLK_Fall;
BCLK_leading_edge <= BCLK_Fall when (C_BCLK_POL = 1) else BCLK_Rise;
-- Serial clock output
BCLK_O <= BCLK_int when enable = '1' else '1';
-----------------------------------------------------------------------------------
-- Frame clock generator (LRCLK_O)
-----------------------------------------------------------------------------------
LRCLK_GEN: process(CLK_I)
begin
if(CLK_I'event and CLK_I = '1') then
-- Reset
if((RST_I = '1') or (LRCLK_RATE /= PREV_LRCLK_RATE) or (enable = '0')) then
Cnt_Lrclk <= 0;
LRCLK_int <= '0';
PREV_LRCLK_RATE <= LRCLK_RATE;
if(C_FRM_SYNC = 1) then
Cnt_Lrclk <= LRCLK_RATE*2;
end if;
-- 50% Duty Cycle LRCLK signal, used for Stereo Mode
elsif(C_FRM_SYNC = 0) then
if (BCLK_trailing_edge = '1') then
if(Cnt_Lrclk = LRCLK_RATE-1) then
Cnt_Lrclk <= 0;
LRCLK_int <= not LRCLK_int;
else
Cnt_Lrclk <= Cnt_Lrclk + 1;
end if;
end if;
-- Pulse mode LRCLK signal, used for TDM4 and TDM8
elsif(C_FRM_SYNC = 1) then
if (BCLK_trailing_edge = '1') then
-- If the number of bits has been sent, pulse new frame
if(Cnt_Lrclk = LRCLK_RATE*2) then
Cnt_Lrclk <= 0;
LRCLK_int <= '1';
else
LRCLK_int <= '0';
Cnt_Lrclk <= Cnt_Lrclk + 1;
end if;
end if;
end if;
end if;
end process LRCLK_GEN;
-- Frame clock output
LRCLK_O <= LRCLK_int when (enable = '1') else '0';
-- Used to change data in the Slots in TDM Mode
Cnt_Lrclk_TDM <= '0' when ((Cnt_Lrclk = 0)or(Cnt_Lrclk = 32)or(Cnt_Lrclk = 64)or(Cnt_Lrclk = 96)or
(Cnt_Lrclk = 128)or(Cnt_Lrclk = 160)or(Cnt_Lrclk=192)or(Cnt_Lrclk=224)or(Cnt_Lrclk=256))
else '1';
-- Used to signal data request (TX)
Cnt_Lrclk_OE_S <= '1' when ((Cnt_Lrclk = 0)or(Cnt_Lrclk = 32)or(Cnt_Lrclk = 64)or(Cnt_Lrclk = 96)or
(Cnt_Lrclk = 128)or(Cnt_Lrclk = 160)or(Cnt_Lrclk=192)or(Cnt_Lrclk=224))
else '0';
-- Used to signal valid data (RX)
Cnt_Lrclk_WE_S <= '1' when (Cnt_Lrclk = 1)or(Cnt_Lrclk = 33)or(Cnt_Lrclk = 65)or(Cnt_Lrclk = 97)or
(Cnt_Lrclk = 129)or(Cnt_Lrclk = 161)or(Cnt_Lrclk=193)or(Cnt_Lrclk=225)
else '0';
-----------------------------------------------------------------------------------
-- Load in parallel data, shift out serial data (SDATA_O)
-----------------------------------------------------------------------------------
SER_DATA_O: process(CLK_I)
begin
if(CLK_I'event and CLK_I = '1') then
-- Reset
if((RST_I = '1') or (enable = '0')) then
-- If 50% Duty Cycle
if(C_FRM_SYNC = 0) then
if((C_MSB_POS = 0)or(C_MSB_POS = 1)) then
Data_Out_int(31) <= '0';
Data_Out_int(30 downto 31-C_SLOT_WIDTH) <= D_S_I;
Data_Out_int(30-C_SLOT_WIDTH downto 0) <= (others => '0');
end if;
-- If Pulse mode
elsif(C_FRM_SYNC = 1) then
if((C_MSB_POS = 0)or(C_MSB_POS = 1)) then
Data_Out_int(31 downto 32-C_SLOT_WIDTH) <= D_S_I;
Data_Out_int(31-C_SLOT_WIDTH downto 0) <= (others => '0');
end if;
end if;
elsif((Cnt_Lrclk_TDM = '0')and(BCLK_leading_edge = '1')) then
if((C_MSB_POS = 0)or(C_MSB_POS = 1)) then
-- 50% Duty Cycle mode
if(C_FRM_SYNC = 0) then
Data_Out_int(31) <= '0';
Data_Out_int(30 downto 31-C_SLOT_WIDTH) <= D_S_I;
Data_Out_int(30-C_SLOT_WIDTH downto 0) <= (others => '0');
-- If Pulse mode
elsif(C_FRM_SYNC = 1) then
Data_Out_int(31 downto 32-C_SLOT_WIDTH) <= D_S_I;
Data_Out_int(31-C_SLOT_WIDTH downto 0) <= (others => '0');
end if;
end if;
-- Shift out serial data
elsif(BCLK_trailing_edge = '1') then
if((C_MSB_POS = 0)or(C_MSB_POS = 1)) then
Data_Out_int <= Data_Out_int(30 downto 0) & '0';
end if;
end if;
end if;
end process SER_DATA_O;
-- Serial data output
SDATA_O <= Data_Out_int(31) when ((EN_TX_I = '1') and (C_MSB_POS = 0)) else
Data_Out_int(0) when ((EN_TX_I = '1') and (C_MSB_POS = 1)) else '0';
-----------------------------------------------------------------------------------
-- Shift in serial data, load out parallel data (SDATA_I)
-----------------------------------------------------------------------------------
SER_DATA_I: process(CLK_I)
begin
if(CLK_I'event and CLK_I = '1') then
-- Reset
if((RST_I = '1') or (enable = '0')) then
Data_In_int <= (others => '0');
D_S_O_int <= (others => '0');
-- 50% Duty Cycle mode
elsif(C_FRM_SYNC = 0) then
-- Stereo mode
-- Load parallel data
-- Depending on BCLK polarity settings
if((Cnt_Lrclk_TDM = '0') and (BCLK_trailing_edge = '1')) then
if((C_MSB_POS = 0)or(C_MSB_POS = 1)) then
D_S_O_int <= Data_In_int(31 downto 32-C_SLOT_WIDTH);
Data_In_int <= (others => '0');
end if;
-- Shift in serial data
-- Depending on BCLK polarity settings
elsif(BCLK_leading_edge = '1') then
if((C_MSB_POS = 0)or(C_MSB_POS = 1)) then
Data_In_int <= Data_In_int(30 downto 0) & SDATA_I;
end if;
end if;
-- Pulse mode
elsif(C_FRM_SYNC = 1) then
-- Load parallel data
-- Depending on BCLK polarity settings
if((Cnt_Lrclk_TDM = '0')and(BCLK_trailing_edge = '1')) then
if((C_MSB_POS = 0)or(C_MSB_POS = 1)) then
D_S_O_int <= Data_In_int(31 downto 32-C_SLOT_WIDTH);
Data_In_int <= (others => '0');
end if;
-- Shift in serial data
-- Depending on BCLK polarity settings
elsif((Lrclk_int = '0')and(BCLK_leading_edge = '1')) then
if((C_MSB_POS = 0)or(C_MSB_POS = 1)) then
Data_In_int <= Data_In_int(30 downto 0) & SDATA_I;
end if;
end if;
end if;
end if;
end process SER_DATA_I;
D_S_O <= D_S_O_int;
------------------------------------------------------------------------
-- Output Enable signals (for FIFO)
------------------------------------------------------------------------
OE_GEN: process(CLK_I)
begin
if(CLK_I'event and CLK_I = '1') then
if((RST_I = '1') or (enable = '0')) then
OE_S_int <= '0';
else
if((Cnt_Lrclk_OE_S = '1')and(BCLK_trailing_edge = '1')) then
OE_S_int <= '1';
else
OE_S_int <= '0';
end if;
end if;
end if;
end process OE_GEN;
EN_TX_INT_GEN: process(CLK_I)
begin
if(CLK_I'event and CLK_I = '1') then
if (RST_I = '1') then
EN_TX_INT <= '0';
else
-- After enabling TX the first request needs to be syncronized to Cnt_Lrclk = 0
-- otherwise we will mess up the channel order.
if((EN_TX_I = '1') and (Lrclk_int = '0') and (Cnt_Lrclk = 0) and (BCLK_trailing_edge = '1')) then
EN_TX_INT <= '1';
elsif (EN_TX_I = '0') then
EN_TX_INT <= '0';
end if;
end if;
end if;
end process EN_TX_INT_GEN;
OE_S_O <= OE_S_int when (EN_TX_INT = '1') else '0';
------------------------------------------------------------------------
-- Write Enable signals (for FIFO)
------------------------------------------------------------------------
WE_GEN: process(CLK_I)
begin
if(CLK_I'event and CLK_I = '1') then
if((RST_I = '1') or (enable = '0')) then
WE_S_int <= '0';
else
-- Depending on BCLK polarity settings
if((Cnt_Lrclk_WE_S = '1')and(BCLK_leading_edge = '1')) then
WE_S_int <= '1';
else
WE_S_int <= '0';
end if;
end if;
end if;
end process WE_GEN;
EN_RX_INT_GEN: process(CLK_I)
begin
if(CLK_I'event and CLK_I = '1') then
if (RST_I = '1') then
EN_RX_INT <= '0';
else
-- After enabling RX the first request needs to be syncronized to Cnt_Lrclk = 31
-- otherwise we will mess up the channel order.
if((EN_RX_I = '1') and (Lrclk_int = '0') and (Cnt_Lrclk = 31) and (BCLK_trailing_edge = '1')) then
EN_RX_INT <= '1';
elsif (EN_RX_I = '0') then
EN_RX_INT <= '0';
end if;
end if;
end if;
end process EN_RX_INT_GEN;
WE_S_O <= WE_S_int when (EN_RX_INT = '1') else '0';
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity i2s_controller is
generic(
C_SLOT_WIDTH : integer := 24; -- Width of one Slot
-- Synthesis parameters
C_MSB_POS : integer := 0; -- MSB Position in the LRCLK frame (0 - MSB first, 1 - LSB first)
C_FRM_SYNC : integer := 1; -- Frame sync type (0 - 50% Duty Cycle, 1 - Pulse mode)
C_LRCLK_POL : integer := 0; -- LRCLK Polarity (0 - Falling edge, 1 - Rising edge)
C_BCLK_POL : integer := 0 -- BCLK Polarity (0 - Falling edge, 1 - Rising edge)
);
port(
CLK_I : in std_logic; -- System clock (100 MHz)
RST_I : in std_logic; -- System reset
BCLK_O : out std_logic; -- Bit Clock
LRCLK_O : out std_logic; -- Frame Clock
SDATA_O : out std_logic; -- Serial Data Output
SDATA_I : in std_logic; -- Serial Data Input
EN_TX_I : in std_logic; -- Enable TX
EN_RX_I : in std_logic; -- Enable RX
OE_S_O : out std_logic; -- Request new Slot Data
WE_S_O : out std_logic; -- Valid Slot Data
D_S_I : in std_logic_vector(C_SLOT_WIDTH-1 downto 0); -- Slot Data in
D_S_O : out std_logic_vector(C_SLOT_WIDTH-1 downto 0); -- Slot Data out
-- Runtime parameters
DIV_RATE_I : in std_logic_vector(7 downto 0);
LRCLK_RATE_I : in std_logic_vector(7 downto 0)
--NR_CHANNELS_I : in std_logic_vector(3 downto 0) -- Number of channels (2 - Stereo, 4- TDM4, 8 - TDM8)
);
end i2s_controller;
architecture Behavioral of i2s_controller is
-- Divide value for the serial clock divider
signal DIV_RATE : natural range 0 to 255 := 0;
signal PREV_DIV_RATE : natural range 0 to 255 := 0;
-- Divide value for the frame clock divider
signal LRCLK_RATE : natural range 0 to 255 := 0;
signal PREV_LRCLK_RATE : natural range 0 to 255 := 0;
-- Counter for the serial clock divider
signal Cnt_Bclk : integer range 0 to 255;
-- Counter for the frame clock divider
signal Cnt_Lrclk : integer range 0 to 512;
signal Cnt_Lrclk_TDM : std_logic;
-- Counter for TDM4 and TDM8 Output Enable signal
signal Cnt_Lrclk_OE_S : std_logic;
-- Counter for TDM4 and TDM8 Write Enable signal
signal Cnt_Lrclk_WE_S : std_logic;
-- Internal synchronous BCLK signal
signal BCLK_int : std_logic;
-- Rising and Falling edge impulses of the serial clock
signal BCLK_Fall : std_logic;
signal BCLK_Rise : std_logic;
-- Internal synchronous LRCLK signal
signal LRCLK_int : std_logic;
-- Data Out internal signal
signal Data_Out_int : std_logic_vector(31 downto 0);
-- Data In internal signal
signal Data_In_int : std_logic_vector(31 downto 0);
-- Data Left, Right and Slot internal signal
signal D_L_O_int : std_logic_vector(C_SLOT_WIDTH-1 downto 0);
signal D_R_O_int : std_logic_vector(C_SLOT_WIDTH-1 downto 0);
signal D_S_O_int : std_logic_vector(C_SLOT_WIDTH-1 downto 0);
--Internal synchronous OE signals
signal OE_R_int : std_logic;
signal OE_L_int : std_logic;
signal OE_S_int : std_logic;
--Internal synchronous WE signals
signal WE_R_int : std_logic;
signal WE_L_int : std_logic;
signal WE_S_int : std_logic;
signal enable : std_logic;
signal BCLK_trailing_edge : std_logic;
signal BCLK_leading_edge : std_logic;
signal EN_RX_INT : std_logic;
signal EN_TX_INT : std_logic;
begin
-- Division rate to ensure 48K sample rate
-- BCLK division rate
--DIV_RATE <= 32 when (NR_CHANNELS_I = "0010") else
-- 16 when (NR_CHANNELS_I = "0100") else
-- 8 when (NR_CHANNELS_I = "1000") else 0;
--
DIV_RATE <= conv_integer(DIV_RATE_I);
-- LRCLK division rate
--LRCLK_RATE <= 32 when (NR_CHANNELS_I = "0010") else
-- 64 when (NR_CHANNELS_I = "0100") else
-- 128 when (NR_CHANNELS_I = "1000") else 0;
--
LRCLK_RATE <= conv_integer(LRCLK_RATE_I);
enable <= '1' when (EN_TX_I = '1') or (EN_RX_I = '1') else '0';
-----------------------------------------------------------------------------------
-- Serial clock generation (BCLK_O, BCLK_FALL, BCLK_RISE)
-----------------------------------------------------------------------------------
SER_CLK: process(CLK_I)
begin
if(CLK_I'event and CLK_I = '1') then
if((RST_I = '1') or (DIV_RATE /= PREV_DIV_RATE) or (enable = '0')) then
Cnt_Bclk <= 0;
BCLK_Int <= '0';
PREV_DIV_RATE <= DIV_RATE;
elsif(Cnt_Bclk = ((DIV_RATE/2)-1)) then
Cnt_Bclk <= 0;
BCLK_int <= not BCLK_int;
else
Cnt_Bclk <= Cnt_Bclk + 1;
end if;
end if;
end process SER_CLK;
-- Serial clock Falling edge, Rising Edge
BCLK_Fall <= '1' when ((Cnt_Bclk = ((DIV_RATE/2)-1)) and (BCLK_int = '1') and (enable = '1')) else '0';
BCLK_Rise <= '1' when ((Cnt_Bclk = ((DIV_RATE/2)-1)) and (BCLK_int = '0') and (enable = '1')) else '0';
BCLK_trailing_edge <= BCLK_Rise when (C_BCLK_POL = 1) else BCLK_Fall;
BCLK_leading_edge <= BCLK_Fall when (C_BCLK_POL = 1) else BCLK_Rise;
-- Serial clock output
BCLK_O <= BCLK_int when enable = '1' else '1';
-----------------------------------------------------------------------------------
-- Frame clock generator (LRCLK_O)
-----------------------------------------------------------------------------------
LRCLK_GEN: process(CLK_I)
begin
if(CLK_I'event and CLK_I = '1') then
-- Reset
if((RST_I = '1') or (LRCLK_RATE /= PREV_LRCLK_RATE) or (enable = '0')) then
Cnt_Lrclk <= 0;
LRCLK_int <= '0';
PREV_LRCLK_RATE <= LRCLK_RATE;
if(C_FRM_SYNC = 1) then
Cnt_Lrclk <= LRCLK_RATE*2;
end if;
-- 50% Duty Cycle LRCLK signal, used for Stereo Mode
elsif(C_FRM_SYNC = 0) then
if (BCLK_trailing_edge = '1') then
if(Cnt_Lrclk = LRCLK_RATE-1) then
Cnt_Lrclk <= 0;
LRCLK_int <= not LRCLK_int;
else
Cnt_Lrclk <= Cnt_Lrclk + 1;
end if;
end if;
-- Pulse mode LRCLK signal, used for TDM4 and TDM8
elsif(C_FRM_SYNC = 1) then
if (BCLK_trailing_edge = '1') then
-- If the number of bits has been sent, pulse new frame
if(Cnt_Lrclk = LRCLK_RATE*2) then
Cnt_Lrclk <= 0;
LRCLK_int <= '1';
else
LRCLK_int <= '0';
Cnt_Lrclk <= Cnt_Lrclk + 1;
end if;
end if;
end if;
end if;
end process LRCLK_GEN;
-- Frame clock output
LRCLK_O <= LRCLK_int when (enable = '1') else '0';
-- Used to change data in the Slots in TDM Mode
Cnt_Lrclk_TDM <= '0' when ((Cnt_Lrclk = 0)or(Cnt_Lrclk = 32)or(Cnt_Lrclk = 64)or(Cnt_Lrclk = 96)or
(Cnt_Lrclk = 128)or(Cnt_Lrclk = 160)or(Cnt_Lrclk=192)or(Cnt_Lrclk=224)or(Cnt_Lrclk=256))
else '1';
-- Used to signal data request (TX)
Cnt_Lrclk_OE_S <= '1' when ((Cnt_Lrclk = 0)or(Cnt_Lrclk = 32)or(Cnt_Lrclk = 64)or(Cnt_Lrclk = 96)or
(Cnt_Lrclk = 128)or(Cnt_Lrclk = 160)or(Cnt_Lrclk=192)or(Cnt_Lrclk=224))
else '0';
-- Used to signal valid data (RX)
Cnt_Lrclk_WE_S <= '1' when (Cnt_Lrclk = 1)or(Cnt_Lrclk = 33)or(Cnt_Lrclk = 65)or(Cnt_Lrclk = 97)or
(Cnt_Lrclk = 129)or(Cnt_Lrclk = 161)or(Cnt_Lrclk=193)or(Cnt_Lrclk=225)
else '0';
-----------------------------------------------------------------------------------
-- Load in parallel data, shift out serial data (SDATA_O)
-----------------------------------------------------------------------------------
SER_DATA_O: process(CLK_I)
begin
if(CLK_I'event and CLK_I = '1') then
-- Reset
if((RST_I = '1') or (enable = '0')) then
-- If 50% Duty Cycle
if(C_FRM_SYNC = 0) then
if((C_MSB_POS = 0)or(C_MSB_POS = 1)) then
Data_Out_int(31) <= '0';
Data_Out_int(30 downto 31-C_SLOT_WIDTH) <= D_S_I;
Data_Out_int(30-C_SLOT_WIDTH downto 0) <= (others => '0');
end if;
-- If Pulse mode
elsif(C_FRM_SYNC = 1) then
if((C_MSB_POS = 0)or(C_MSB_POS = 1)) then
Data_Out_int(31 downto 32-C_SLOT_WIDTH) <= D_S_I;
Data_Out_int(31-C_SLOT_WIDTH downto 0) <= (others => '0');
end if;
end if;
elsif((Cnt_Lrclk_TDM = '0')and(BCLK_leading_edge = '1')) then
if((C_MSB_POS = 0)or(C_MSB_POS = 1)) then
-- 50% Duty Cycle mode
if(C_FRM_SYNC = 0) then
Data_Out_int(31) <= '0';
Data_Out_int(30 downto 31-C_SLOT_WIDTH) <= D_S_I;
Data_Out_int(30-C_SLOT_WIDTH downto 0) <= (others => '0');
-- If Pulse mode
elsif(C_FRM_SYNC = 1) then
Data_Out_int(31 downto 32-C_SLOT_WIDTH) <= D_S_I;
Data_Out_int(31-C_SLOT_WIDTH downto 0) <= (others => '0');
end if;
end if;
-- Shift out serial data
elsif(BCLK_trailing_edge = '1') then
if((C_MSB_POS = 0)or(C_MSB_POS = 1)) then
Data_Out_int <= Data_Out_int(30 downto 0) & '0';
end if;
end if;
end if;
end process SER_DATA_O;
-- Serial data output
SDATA_O <= Data_Out_int(31) when ((EN_TX_I = '1') and (C_MSB_POS = 0)) else
Data_Out_int(0) when ((EN_TX_I = '1') and (C_MSB_POS = 1)) else '0';
-----------------------------------------------------------------------------------
-- Shift in serial data, load out parallel data (SDATA_I)
-----------------------------------------------------------------------------------
SER_DATA_I: process(CLK_I)
begin
if(CLK_I'event and CLK_I = '1') then
-- Reset
if((RST_I = '1') or (enable = '0')) then
Data_In_int <= (others => '0');
D_S_O_int <= (others => '0');
-- 50% Duty Cycle mode
elsif(C_FRM_SYNC = 0) then
-- Stereo mode
-- Load parallel data
-- Depending on BCLK polarity settings
if((Cnt_Lrclk_TDM = '0') and (BCLK_trailing_edge = '1')) then
if((C_MSB_POS = 0)or(C_MSB_POS = 1)) then
D_S_O_int <= Data_In_int(31 downto 32-C_SLOT_WIDTH);
Data_In_int <= (others => '0');
end if;
-- Shift in serial data
-- Depending on BCLK polarity settings
elsif(BCLK_leading_edge = '1') then
if((C_MSB_POS = 0)or(C_MSB_POS = 1)) then
Data_In_int <= Data_In_int(30 downto 0) & SDATA_I;
end if;
end if;
-- Pulse mode
elsif(C_FRM_SYNC = 1) then
-- Load parallel data
-- Depending on BCLK polarity settings
if((Cnt_Lrclk_TDM = '0')and(BCLK_trailing_edge = '1')) then
if((C_MSB_POS = 0)or(C_MSB_POS = 1)) then
D_S_O_int <= Data_In_int(31 downto 32-C_SLOT_WIDTH);
Data_In_int <= (others => '0');
end if;
-- Shift in serial data
-- Depending on BCLK polarity settings
elsif((Lrclk_int = '0')and(BCLK_leading_edge = '1')) then
if((C_MSB_POS = 0)or(C_MSB_POS = 1)) then
Data_In_int <= Data_In_int(30 downto 0) & SDATA_I;
end if;
end if;
end if;
end if;
end process SER_DATA_I;
D_S_O <= D_S_O_int;
------------------------------------------------------------------------
-- Output Enable signals (for FIFO)
------------------------------------------------------------------------
OE_GEN: process(CLK_I)
begin
if(CLK_I'event and CLK_I = '1') then
if((RST_I = '1') or (enable = '0')) then
OE_S_int <= '0';
else
if((Cnt_Lrclk_OE_S = '1')and(BCLK_trailing_edge = '1')) then
OE_S_int <= '1';
else
OE_S_int <= '0';
end if;
end if;
end if;
end process OE_GEN;
EN_TX_INT_GEN: process(CLK_I)
begin
if(CLK_I'event and CLK_I = '1') then
if (RST_I = '1') then
EN_TX_INT <= '0';
else
-- After enabling TX the first request needs to be syncronized to Cnt_Lrclk = 0
-- otherwise we will mess up the channel order.
if((EN_TX_I = '1') and (Lrclk_int = '0') and (Cnt_Lrclk = 0) and (BCLK_trailing_edge = '1')) then
EN_TX_INT <= '1';
elsif (EN_TX_I = '0') then
EN_TX_INT <= '0';
end if;
end if;
end if;
end process EN_TX_INT_GEN;
OE_S_O <= OE_S_int when (EN_TX_INT = '1') else '0';
------------------------------------------------------------------------
-- Write Enable signals (for FIFO)
------------------------------------------------------------------------
WE_GEN: process(CLK_I)
begin
if(CLK_I'event and CLK_I = '1') then
if((RST_I = '1') or (enable = '0')) then
WE_S_int <= '0';
else
-- Depending on BCLK polarity settings
if((Cnt_Lrclk_WE_S = '1')and(BCLK_leading_edge = '1')) then
WE_S_int <= '1';
else
WE_S_int <= '0';
end if;
end if;
end if;
end process WE_GEN;
EN_RX_INT_GEN: process(CLK_I)
begin
if(CLK_I'event and CLK_I = '1') then
if (RST_I = '1') then
EN_RX_INT <= '0';
else
-- After enabling RX the first request needs to be syncronized to Cnt_Lrclk = 31
-- otherwise we will mess up the channel order.
if((EN_RX_I = '1') and (Lrclk_int = '0') and (Cnt_Lrclk = 31) and (BCLK_trailing_edge = '1')) then
EN_RX_INT <= '1';
elsif (EN_RX_I = '0') then
EN_RX_INT <= '0';
end if;
end if;
end if;
end process EN_RX_INT_GEN;
WE_S_O <= WE_S_int when (EN_RX_INT = '1') else '0';
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity imem is
port (a: in std_logic_vector(5 downto 0);
y: out std_logic_vector(31 downto 0));
end entity;
architecture imem_arq of imem is
type mem is array (0 to 63) of std_logic_vector(31 downto 0);
begin
process(a)
variable my_mem: mem ;
variable t1: std_logic_vector(31 downto 0);
variable pos_a: integer;
begin
for pos in 0 to 63 loop
t1 := std_logic_vector(to_unsigned(pos, 32)); --integer to logic_v
my_mem(pos) := t1;
end loop;
pos_a := to_integer(unsigned(a)); --logic_vector to integer
y <= my_mem(pos_a);
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity imem is
port (a: in std_logic_vector(5 downto 0);
y: out std_logic_vector(31 downto 0));
end entity;
architecture imem_arq of imem is
type mem is array (0 to 63) of std_logic_vector(31 downto 0);
begin
process(a)
variable my_mem: mem ;
variable t1: std_logic_vector(31 downto 0);
variable pos_a: integer;
begin
for pos in 0 to 63 loop
t1 := std_logic_vector(to_unsigned(pos, 32)); --integer to logic_v
my_mem(pos) := t1;
end loop;
pos_a := to_integer(unsigned(a)); --logic_vector to integer
y <= my_mem(pos_a);
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity dcm4 is
port (CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic);
end dcm4;
architecture BEHAVIORAL of dcm4 is
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKFX_BUFG_INST : BUFG
port map (I => CLKFX_BUF, O => CLK0_OUT);
DCM_INST : DCM
generic map(CLK_FEEDBACK => "NONE",
CLKDV_DIVIDE => 4.0, -- 25.175 = 32 * 11 / 14
CLKFX_DIVIDE => 14,
CLKFX_MULTIPLY => 11,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => 31.250,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => true,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => false)
port map (CLKFB => GND_BIT,
CLKIN => CLKIN_IN,
DSSEN => GND_BIT,
PSCLK => GND_BIT,
PSEN => GND_BIT,
PSINCDEC => GND_BIT,
RST => GND_BIT,
CLKDV => open,
CLKFX => CLKFX_BUF,
CLKFX180 => open,
CLK0 => open,
CLK2X => open,
CLK2X180 => open,
CLK90 => open,
CLK180 => open,
CLK270 => open,
LOCKED => open,
PSDONE => open,
STATUS => open);
end BEHAVIORAL;
|
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