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-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: digilentinc.com:ip:dvi2rgb:1.4
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY design_1_dvi2rgb_0_0 IS
PORT (
TMDS_Clk_p : IN STD_LOGIC;
TMDS_Clk_n : IN STD_LOGIC;
TMDS_Data_p : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
TMDS_Data_n : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
RefClk : IN STD_LOGIC;
aRst : IN STD_LOGIC;
vid_pData : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
vid_pVDE : OUT STD_LOGIC;
vid_pHSync : OUT STD_LOGIC;
vid_pVSync : OUT STD_LOGIC;
PixelClk : OUT STD_LOGIC;
aPixelClkLckd : OUT STD_LOGIC;
DDC_SDA_I : IN STD_LOGIC;
DDC_SDA_O : OUT STD_LOGIC;
DDC_SDA_T : OUT STD_LOGIC;
DDC_SCL_I : IN STD_LOGIC;
DDC_SCL_O : OUT STD_LOGIC;
DDC_SCL_T : OUT STD_LOGIC;
pRst : IN STD_LOGIC
);
END design_1_dvi2rgb_0_0;
ARCHITECTURE design_1_dvi2rgb_0_0_arch OF design_1_dvi2rgb_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_dvi2rgb_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT dvi2rgb IS
GENERIC (
kEmulateDDC : BOOLEAN;
kRstActiveHigh : BOOLEAN;
kClkRange : INTEGER;
kIDLY_TapValuePs : INTEGER;
kIDLY_TapWidth : INTEGER
);
PORT (
TMDS_Clk_p : IN STD_LOGIC;
TMDS_Clk_n : IN STD_LOGIC;
TMDS_Data_p : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
TMDS_Data_n : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
RefClk : IN STD_LOGIC;
aRst : IN STD_LOGIC;
aRst_n : IN STD_LOGIC;
vid_pData : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
vid_pVDE : OUT STD_LOGIC;
vid_pHSync : OUT STD_LOGIC;
vid_pVSync : OUT STD_LOGIC;
PixelClk : OUT STD_LOGIC;
SerialClk : OUT STD_LOGIC;
aPixelClkLckd : OUT STD_LOGIC;
DDC_SDA_I : IN STD_LOGIC;
DDC_SDA_O : OUT STD_LOGIC;
DDC_SDA_T : OUT STD_LOGIC;
DDC_SCL_I : IN STD_LOGIC;
DDC_SCL_O : OUT STD_LOGIC;
DDC_SCL_T : OUT STD_LOGIC;
pRst : IN STD_LOGIC;
pRst_n : IN STD_LOGIC
);
END COMPONENT dvi2rgb;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_dvi2rgb_0_0_arch: ARCHITECTURE IS "dvi2rgb,Vivado 2014.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_dvi2rgb_0_0_arch : ARCHITECTURE IS "design_1_dvi2rgb_0_0,dvi2rgb,{}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF TMDS_Clk_p: SIGNAL IS "digilentinc.com:interface:tmds:1.0 TMDS CLK_P";
ATTRIBUTE X_INTERFACE_INFO OF TMDS_Clk_n: SIGNAL IS "digilentinc.com:interface:tmds:1.0 TMDS CLK_N";
ATTRIBUTE X_INTERFACE_INFO OF TMDS_Data_p: SIGNAL IS "digilentinc.com:interface:tmds:1.0 TMDS DATA_P";
ATTRIBUTE X_INTERFACE_INFO OF TMDS_Data_n: SIGNAL IS "digilentinc.com:interface:tmds:1.0 TMDS DATA_N";
ATTRIBUTE X_INTERFACE_INFO OF RefClk: SIGNAL IS "xilinx.com:signal:clock:1.0 RefClk CLK";
ATTRIBUTE X_INTERFACE_INFO OF vid_pData: SIGNAL IS "xilinx.com:interface:vid_io:1.0 RGB DATA";
ATTRIBUTE X_INTERFACE_INFO OF vid_pVDE: SIGNAL IS "xilinx.com:interface:vid_io:1.0 RGB ACTIVE_VIDEO";
ATTRIBUTE X_INTERFACE_INFO OF vid_pHSync: SIGNAL IS "xilinx.com:interface:vid_io:1.0 RGB HSYNC";
ATTRIBUTE X_INTERFACE_INFO OF vid_pVSync: SIGNAL IS "xilinx.com:interface:vid_io:1.0 RGB VSYNC";
ATTRIBUTE X_INTERFACE_INFO OF PixelClk: SIGNAL IS "xilinx.com:signal:clock:1.0 PixelClk CLK";
ATTRIBUTE X_INTERFACE_INFO OF DDC_SDA_I: SIGNAL IS "xilinx.com:interface:iic:1.0 DDC SDA_I";
ATTRIBUTE X_INTERFACE_INFO OF DDC_SDA_O: SIGNAL IS "xilinx.com:interface:iic:1.0 DDC SDA_O";
ATTRIBUTE X_INTERFACE_INFO OF DDC_SDA_T: SIGNAL IS "xilinx.com:interface:iic:1.0 DDC SDA_T";
ATTRIBUTE X_INTERFACE_INFO OF DDC_SCL_I: SIGNAL IS "xilinx.com:interface:iic:1.0 DDC SCL_I";
ATTRIBUTE X_INTERFACE_INFO OF DDC_SCL_O: SIGNAL IS "xilinx.com:interface:iic:1.0 DDC SCL_O";
ATTRIBUTE X_INTERFACE_INFO OF DDC_SCL_T: SIGNAL IS "xilinx.com:interface:iic:1.0 DDC SCL_T";
BEGIN
U0 : dvi2rgb
GENERIC MAP (
kEmulateDDC => true,
kRstActiveHigh => true,
kClkRange => 2,
kIDLY_TapValuePs => 78,
kIDLY_TapWidth => 5
)
PORT MAP (
TMDS_Clk_p => TMDS_Clk_p,
TMDS_Clk_n => TMDS_Clk_n,
TMDS_Data_p => TMDS_Data_p,
TMDS_Data_n => TMDS_Data_n,
RefClk => RefClk,
aRst => aRst,
aRst_n => '1',
vid_pData => vid_pData,
vid_pVDE => vid_pVDE,
vid_pHSync => vid_pHSync,
vid_pVSync => vid_pVSync,
PixelClk => PixelClk,
aPixelClkLckd => aPixelClkLckd,
DDC_SDA_I => DDC_SDA_I,
DDC_SDA_O => DDC_SDA_O,
DDC_SDA_T => DDC_SDA_T,
DDC_SCL_I => DDC_SCL_I,
DDC_SCL_O => DDC_SCL_O,
DDC_SCL_T => DDC_SCL_T,
pRst => pRst,
pRst_n => '1'
);
END design_1_dvi2rgb_0_0_arch;
|
library verilog;
use verilog.vl_types.all;
entity reservation_alu0_entry is
port(
iCLOCK : in vl_logic;
inRESET : in vl_logic;
iREMOVE_VALID : in vl_logic;
iREGIST_VALID : in vl_logic;
iREGIST_CMD : in vl_logic_vector(4 downto 0);
iREGIST_CC : in vl_logic_vector(3 downto 0);
iREGIST_FLAGS_VALID: in vl_logic;
iREGIST_FLAGS : in vl_logic_vector(4 downto 0);
iREGIST_SOURCE1_VALID: in vl_logic;
iREGIST_SOURCE1 : in vl_logic_vector(31 downto 0);
iREGIST_PC : in vl_logic_vector(31 downto 0);
iREGIST_DESTINATION_REGNAME: in vl_logic_vector(5 downto 0);
iREGIST_COMMIT_TAG: in vl_logic_vector(5 downto 0);
iREGIST_EX_REGIST_POINTER: in vl_logic_vector(3 downto 0);
iALU1_VALID : in vl_logic;
iALU1_FLAGS_OPT_VALID: in vl_logic;
iALU1_FLAGS_REGNAME: in vl_logic_vector(3 downto 0);
iALU1_DESTINATION_REGNAME: in vl_logic_vector(5 downto 0);
iALU1_WRITEBACK : in vl_logic;
iALU1_DATA : in vl_logic_vector(31 downto 0);
iALU1_FLAGS : in vl_logic_vector(4 downto 0);
iALU2_VALID : in vl_logic;
iALU2_FLAGS_OPT_VALID: in vl_logic;
iALU2_FLAGS_REGNAME: in vl_logic_vector(3 downto 0);
iALU2_DESTINATION_REGNAME: in vl_logic_vector(5 downto 0);
iALU2_WRITEBACK : in vl_logic;
iALU2_DATA : in vl_logic_vector(31 downto 0);
iALU2_FLAGS : in vl_logic_vector(4 downto 0);
iALU3_VALID : in vl_logic;
iALU3_DESTINATION_REGNAME: in vl_logic_vector(5 downto 0);
iALU3_DATA : in vl_logic_vector(31 downto 0);
iEX_EXECUTION_POINTER: in vl_logic_vector(3 downto 0);
iEXOUT_VALID : in vl_logic;
oINFO_ENTRY_VALID: out vl_logic;
oINFO_MATCHING : out vl_logic;
oINFO_CMD : out vl_logic_vector(4 downto 0);
oINFO_CC : out vl_logic_vector(3 downto 0);
oINFO_FLAG_VALID: out vl_logic;
oINFO_FLAG : out vl_logic_vector(4 downto 0);
oINFO_SOURCE1_VALID: out vl_logic;
oINFO_SOURCE1 : out vl_logic_vector(31 downto 0);
oINFO_PC : out vl_logic_vector(31 downto 0);
oINFO_DESTINATION_REGNAME: out vl_logic_vector(5 downto 0);
oINFO_COMMIT_TAG: out vl_logic_vector(5 downto 0)
);
end reservation_alu0_entry;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: dcom_uart
-- File: dcom_uart.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Asynchronous UART with baud-rate detection.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.uart.all;
--pragma translate_off
use std.textio.all;
--pragma translate_on
entity dcom_uart is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ui : in uart_in_type;
uo : out uart_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
uarti : in dcom_uart_in_type;
uarto : out dcom_uart_out_type
);
end;
architecture rtl of dcom_uart is
constant REVISION : integer := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBUART, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
type rxfsmtype is (idle, startbit, data, stopbit);
type txfsmtype is (idle, data);
type uartregs is record
rxen : std_ulogic; -- receiver enabled
dready : std_ulogic; -- data ready
rsempty : std_ulogic; -- receiver shift register empty (internal)
tsempty : std_ulogic; -- transmitter shift register empty
thempty : std_ulogic; -- transmitter hold register empty
break : std_ulogic; -- break detected
ovf : std_ulogic; -- receiver overflow
frame : std_ulogic; -- framing error
rhold : std_logic_vector(7 downto 0);
rshift : std_logic_vector(7 downto 0);
tshift : std_logic_vector(9 downto 0);
thold : std_logic_vector(7 downto 0);
txstate : txfsmtype;
txclk : std_logic_vector(2 downto 0); -- tx clock divider
txtick : std_ulogic; -- tx clock (internal)
rxstate : rxfsmtype;
rxclk : std_logic_vector(2 downto 0); -- rx clock divider
rxdb : std_logic_vector(1 downto 0); -- rx data filtering buffer
rxtick : std_ulogic; -- rx clock (internal)
tick : std_ulogic; -- rx clock (internal)
scaler : std_logic_vector(17 downto 0);
brate : std_logic_vector(17 downto 0);
tcnt : std_logic_vector(1 downto 0); -- autobaud counter
rxf : std_logic_vector(4 downto 0); -- rx data filtering buffer
fedge : std_ulogic; -- rx falling edge
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RES : uartregs := (
rxen => '0', dready => '0', rsempty => '1', tsempty => '1', thempty => '1',
break => '0', ovf => '0', frame => '0', rhold => (others => '0'),
rshift => (others => '0'), tshift => (others => '1'), thold => (others => '0'),
txstate => idle, txclk => (others => '0'), txtick => '0', rxstate => idle,
rxclk => (others => '0'), rxdb => (others => '0'), rxtick => '0', tick => '0',
scaler => "111111111111111011", brate => (others => '1'), tcnt => (others => '0'),
rxf => (others => '0'), fedge => '0');
signal r, rin : uartregs;
begin
uartop : process(rst, r, apbi, uarti, ui )
variable rdata : std_logic_vector(31 downto 0);
variable scaler : std_logic_vector(17 downto 0);
variable rxclk, txclk : std_logic_vector(2 downto 0);
variable irxd : std_ulogic;
variable v : uartregs;
begin
v := r;
v.txtick := '0'; v.rxtick := '0'; v.tick := '0'; rdata := (others => '0');
v.rxdb(1) := r.rxdb(0);
-- scaler
if r.tcnt = "11" then scaler := r.scaler - 1;
else scaler := r.scaler + 1; end if;
if r.tcnt /= "11" then
if (r.rxdb(1) and not r.rxdb(0)) = '1' then v.fedge := '1'; end if;
if (r.fedge) = '1' then
v.scaler := scaler;
if (v.scaler(17) and not r.scaler(16)) = '1' then
v.scaler := "111111111111111011";
v.fedge := '0'; v.tcnt := "00";
end if;
end if;
if (r.rxdb(1) and r.fedge and not r.rxdb(0)) = '1' then
if (r.brate(17 downto 4)> r.scaler(17 downto 4)) then
v.brate := r.scaler; v.tcnt := "00";
end if;
v.scaler := "111111111111111011";
if (r.brate(17 downto 4) = r.scaler(17 downto 4)) then
v.tcnt := r.tcnt + 1;
if r.tcnt = "10" then
v.brate := "0000" & r.scaler(17 downto 4);
v.scaler := v.brate; v.rxen := '1';
end if;
end if;
end if;
else
if (r.break and r.rxdb(1)) = '1' then
v.scaler := "111111111111111011";
v.brate := (others => '1'); v.tcnt := "00";
v.break := '0'; v.rxen := '0';
end if;
end if;
if r.rxen = '1' then
v.scaler := scaler;
v.tick := scaler(15) and not r.scaler(15);
if v.tick = '1' then v.scaler := r.brate; end if;
end if;
-- read/write registers
if uarti.read = '1' then v.dready := '0'; end if;
case apbi.paddr(3 downto 2) is
when "01" =>
rdata(9 downto 0) := r.tcnt & r.rxdb(0) & r.frame & '0' & r.ovf &
r.break & r.thempty & r.tsempty & r.dready;
when "10" =>
rdata(1 downto 0) := (r.tcnt(1) or r.tcnt(0)) & r.rxen;
when others =>
rdata(17 downto 0) := r.brate;
end case;
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(3 downto 2) is
when "01" =>
v.frame := apbi.pwdata(6);
v.ovf := apbi.pwdata(4);
v.break := apbi.pwdata(3);
when "10" =>
v.tcnt := apbi.pwdata(1) & apbi.pwdata(1);
v.rxen := apbi.pwdata(0);
when "11" =>
v.brate := apbi.pwdata(17 downto 0);
v.scaler := apbi.pwdata(17 downto 0);
when others =>
end case;
end if;
-- tx clock
txclk := r.txclk + 1;
if r.tick = '1' then
v.txclk := txclk; v.txtick := r.txclk(2) and not txclk(2);
end if;
-- rx clock
rxclk := r.rxclk + 1;
if r.tick = '1' then
v.rxclk := rxclk; v.rxtick := r.rxclk(2) and not rxclk(2);
end if;
-- filter rx data
v.rxf(1 downto 0) := r.rxf(0) & ui.rxd; -- meta-stability filter
if ((r.tcnt /= "11") and (r.scaler(0 downto 0) = "1")) or
((r.tcnt = "11") and (r.tick = '1'))
then v.rxf(4 downto 2) := r.rxf(3 downto 1); end if;
v.rxdb(0) := (r.rxf(4) and r.rxf(3)) or (r.rxf(4) and r.rxf(2)) or
(r.rxf(3) and r.rxf(2));
irxd := r.rxdb(0);
-- transmitter operation
case r.txstate is
when idle => -- idle and stop bit state
if (r.txtick = '1') then v.tsempty := '1'; end if;
if (r.rxen and (not r.thempty) and r.txtick) = '1' then
v.tshift := '0' & r.thold & '0'; v.txstate := data;
v.thempty := '1';
v.tsempty := '0'; v.txclk := "00" & r.tick; v.txtick := '0';
end if;
when data => -- transmit data frame
if r.txtick = '1' then
v.tshift := '1' & r.tshift(9 downto 1);
if r.tshift(9 downto 1) = "111111110" then
v.tshift(0) := '1'; v.txstate := idle;
end if;
end if;
end case;
-- writing of tx data register must be done after tx fsm to get correct
-- operation of thempty flag
if uarti.write = '1' then
v.thold := uarti.data(7 downto 0); v.thempty := '0';
end if;
-- receiver operation
case r.rxstate is
when idle => -- wait for start bit
if ((not r.rsempty) and not r.dready) = '1' then
v.rhold := r.rshift; v.rsempty := '1'; v.dready := '1';
end if;
if (r.rxen and r.rxdb(1) and (not irxd)) = '1' then
v.rxstate := startbit; v.rshift := (others => '1'); v.rxclk := "100";
if v.rsempty = '0' then v.ovf := '1'; end if;
v.rsempty := '0'; v.rxtick := '0';
end if;
when startbit => -- check validity of start bit
if r.rxtick = '1' then
if irxd = '0' then
v.rshift := irxd & r.rshift(7 downto 1); v.rxstate := data;
else
v.rxstate := idle;
end if;
end if;
when data => -- receive data frame
if r.rxtick = '1' then
v.rshift := irxd & r.rshift(7 downto 1);
if r.rshift(0) = '0' then
v.rxstate := stopbit;
end if;
end if;
when stopbit => -- receive stop bit
if r.rxtick = '1' then
if irxd = '1' then
v.rsempty := '0';
if v.dready = '0' then
v.rhold := r.rshift; v.rsempty := '1'; v.dready := '1';
end if;
else
if r.rshift = "00000000" then
v.break := '1'; -- break
else
v.frame := '1'; -- framing error
end if;
v.rsempty := '1';
end if;
v.rxstate := idle;
end if;
when others =>
v.rxstate := idle;
end case;
-- reset operation
if not RESET_ALL and rst = '0' then
v.frame := RES.frame; v.rsempty := RES.rsempty;
v.ovf := RES.ovf; v.break := RES.break; v.thempty := RES.thempty;
v.tsempty := RES.tsempty; v.dready := RES.dready; v.fedge := RES.fedge;
v.txstate := RES.txstate; v.rxstate := RES.rxstate; v.tshift(0) := RES.tshift(0);
v.scaler := RES.scaler; v.brate := RES.brate;
v.rxen := RES.rxen; v.tcnt := RES.tcnt;
v.txclk := RES.txclk; v.rxclk := RES.rxclk;
end if;
-- update registers
rin <= v;
-- drive outputs
uo.txd <= r.tshift(0);
uo.scaler(31 downto 18) <= (others => '0');
uo.scaler(17 downto 0) <= r.brate;
uo.rtsn <= '0';
uo.rxen <= andv(r.tcnt);
uarto.dready <= r.dready;
uarto.tsempty <= r.tsempty;
uarto.thempty <= r.thempty;
uarto.lock <= r.tcnt(1) and r.tcnt(0);
uarto.enable <= r.rxen;
uarto.data <= r.rhold;
uo.txen <= '1'; uo.flow <= '0';
apbo.prdata <= rdata;
end process;
apbo.pirq <= (others => '0');
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
if RESET_ALL and rst = '0' then
r <= RES;
-- Sync. registers not reset
r.rxf <= rin.rxf;
end if;
end if;
end process;
end;
|
use work.sprites_pkg.all;
use work.graphics_types_pkg.all;
use work.resource_handles_pkg.all;
use work.resource_handles_helper_pkg.all;
use work.npc_pkg.all;
package resource_data_pkg is
-- Here we define all the sprites used in the game
constant GAME_SPRITES: sprite_init_array_type := (
(SPRITE_PLAYER_SHIP_1, bitmap_handle => BITMAP_PLAYER_SHIP_1),
(SPRITE_PLAYER_SHIP_2, bitmap_handle => BITMAP_PLAYER_SHIP_2),
(SPRITE_PLAYER_SHOT, bitmap_handle => BITMAP_PLAYER_SHOT),
(SPRITE_ENEMY_SHIP_1, bitmap_handle => BITMAP_ENEMY_SHIP_1),
(SPRITE_ENEMY_SHIP_2, bitmap_handle => BITMAP_ENEMY_SHIP_2),
(SPRITE_ALIEN_SHIP_1, bitmap_handle => BITMAP_ALIEN_SHIP),
(SPRITE_ALIEN_SHIP_2, bitmap_handle => BITMAP_ALIEN_SHIP),
(SPRITE_ALIEN_SHIP_3, bitmap_handle => BITMAP_ALIEN_SHIP)
);
constant GAME_COLLISIONS: sprite_collision_init_array_type := (
( COLLISION_PLAYER_SHOT_ALIEN_1, SPRITE_PLAYER_SHOT, SPRITE_ALIEN_SHIP_1 ),
( COLLISION_PLAYER_SHOT_ALIEN_2, SPRITE_PLAYER_SHOT, SPRITE_ALIEN_SHIP_2 ),
( COLLISION_PLAYER_SHOT_ALIEN_3, SPRITE_PLAYER_SHOT, SPRITE_ALIEN_SHIP_3 ),
( COLLISION_PLAYER_SHOT_ENEMY_1, SPRITE_PLAYER_SHOT, SPRITE_ENEMY_SHIP_1 ),
( COLLISION_PLAYER_2_ALIEN_1, SPRITE_PLAYER_SHIP_2, SPRITE_ALIEN_SHIP_1 ),
( COLLISION_PLAYER_2_ALIEN_2, SPRITE_PLAYER_SHIP_2, SPRITE_ALIEN_SHIP_2 ),
( COLLISION_PLAYER_2_ALIEN_2, SPRITE_PLAYER_SHIP_2, SPRITE_ALIEN_SHIP_3 ),
( COLLISION_PLAYER_2_ENEMY_1, SPRITE_PLAYER_SHIP_2, SPRITE_ENEMY_SHIP_2 )
);
-- Define the Non-Player Characters (NPCs) used in the game. NPCs have
-- their positions updated automatically; the user logic is responsible for
-- reading their positions and assigning them to the corresponding sprites
constant GAME_NPCS: npc_init_array_type := (
-- Player shot
( NPC_PLAYER_SHOT,
make_npc_projectile(
initial_position => (48, 152),
initial_speed => (4, 0),
allowed_region => (0, 0, 328, 240)
)),
-- Enemy ship 1
( NPC_ENEMY_SHIP,
make_npc_bouncer(
initial_position => (200, 60),
allowed_region => (200, 60, 300, 180),
initial_speed => (2, 2)
)),
-- Alien ship #1
( NPC_ALIEN_SHIP_1,
make_npc_bouncer(
initial_position => (400, 100),
initial_speed => (1, 2)
)),
-- Alien ship #2
( NPC_ALIEN_SHIP_2,
make_npc_bouncer(
initial_position => (410, 120),
initial_speed => (1, 2)
)),
-- Alien ship #3
( NPC_ALIEN_SHIP_3,
make_npc_bouncer(
initial_position => (420, 140),
initial_speed => (1, 2)
))
);
-- Here we define the actual bitmaps for each sprite in the game. This is
-- the second step to add a new sprite in the game.
constant GAME_BITMAPS: bitmap_init_array_type := (
( handle => BITMAP_PLAYER_SHIP_1,
bitmap => (
( 0, 20, 53, 53, 53, 53, 53, 17),
( 0, 55, 24, 20, 20, 20, 20, 53),
( 0, 0, 0, 0, 3, 3, 19, 49),
( 0, 18, 18, 18, 19, 19, 2, 54),
(18, 20, 20, 20, 53, 53, 53, 20),
( 0, 18, 18, 18, 17, 19, 19, 19),
(18, 20, 20, 20, 18, 0, 3, 3),
( 0, 18, 18, 18, 0, 0, 0, 0)
)
),
( handle => BITMAP_PLAYER_SHIP_2,
bitmap => (
(33, 0, 0, 0, 0, 0, 0, 0),
(53, 19, 0, 0, 0, 0, 0, 0),
( 5, 7, 7, 5, 5, 0, 0, 0),
( 7, 54, 10, 53, 10, 7, 0, 0),
(35, 54, 10, 10, 10, 52, 7, 0),
(18, 53, 48, 54, 54, 10, 10, 6),
( 3, 3, 18, 53, 53, 54, 54, 5),
( 0, 0, 0, 19, 20, 20, 20, 17)
)
),
( handle => BITMAP_PLAYER_SHOT,
bitmap => (
( 0, 0, 0, 0, 0, 0, 0, 0),
( 0, 0, 0, 0, 0, 0, 0, 0),
( 0, 0, 50, 43, 50, 0, 0, 0),
( 0, 51, 36, 36, 43, 50, 0, 0),
( 0, 51, 36, 36, 43, 50, 0, 0),
( 0, 0, 50, 43, 50, 0, 0, 0),
( 0, 0, 0, 0, 0, 0, 0, 0),
( 0, 0, 0, 0, 0, 0, 0, 0)
)
),
( handle => BITMAP_ENEMY_SHIP_1,
bitmap => (
( 0, 0, 0, 0, 0, 0, 0, 0),
( 0, 0, 0, 33, 17, 17, 17, 17),
( 0, 33, 17, 36, 53, 36, 8, 8),
(33, 17, 8, 8, 8, 8, 8, 17),
(17, 17, 17, 17, 17, 17, 17, 20),
(17, 24, 24, 24, 24, 24, 24, 24),
(33, 17, 17, 17, 17, 17, 24, 24),
( 0, 0, 0, 0, 0, 33, 17, 17)
)
),
( handle => BITMAP_ENEMY_SHIP_2,
bitmap => (
( 0, 0, 0, 0, 0, 0, 0, 0),
(17, 17, 0, 0, 0, 0, 0, 0),
( 8, 17, 17, 0, 17, 17, 0, 0),
(17, 20, 20, 33, 20, 17, 24, 0),
(20, 19, 19, 19, 19, 17, 40, 26),
(24, 24, 24, 17, 19, 17, 24, 0),
(24, 24, 17, 33, 17, 17, 0, 0),
(17, 17, 17, 0, 0, 0, 0, 0)
)
),
( handle => BITMAP_ALIEN_SHIP,
bitmap => (
( 0, 0, 22, 23, 23, 23, 22, 0),
(22, 23, 23, 0, 17, 19, 23, 22),
( 0, 0, 16, 3, 19, 10, 19, 23),
( 0, 54, 10, 20, 10, 36, 10, 0),
( 0, 0, 16, 3, 19, 10, 19, 23),
(22, 23, 23, 0, 17, 19, 23, 22),
( 0, 0, 22, 23, 23, 23, 22, 0),
( 0, 0, 0, 0, 0, 0, 0, 0)
)
)
);
end;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_ac_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 05:39:03 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../io.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ac_e-rtl-a.vhd,v 1.2 2006/06/26 07:42:19 wig Exp $
-- $Date: 2006/06/26 07:42:19 $
-- $Log: inst_ac_e-rtl-a.vhd,v $
-- Revision 1.2 2006/06/26 07:42:19 wig
-- Updated io, generic and mde_tests testcases
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , wilfried.gaensheimer@micronas.com
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_ac_e
--
architecture rtl of inst_ac_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
-------------------------------------------------------------------------------
--
-- SNESpad controller core
--
-- $Id: snespad.vhd,v 1.2 2004-10-05 18:22:40 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/gamepads/
--
-- The project homepage is located at:
-- http://www.opencores.org/projects.cgi/web/gamepads/overview
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity snespad is
generic (
-- number of pads connected to this core
num_pads_g : natural := 1;
-- active level of reset_i
reset_level_g : natural := 0;
-- active level of the button outputs
button_level_g : natural := 0;
-- number of clk_i periods during 6us
clocks_per_6us_g : natural := 6
);
port (
-- System Interface -------------------------------------------------------
clk_i : in std_logic;
reset_i : in std_logic;
-- Gamepad Interface ------------------------------------------------------
pad_clk_o : out std_logic;
pad_latch_o : out std_logic;
pad_data_i : in std_logic_vector(num_pads_g-1 downto 0);
-- Buttons Interface ------------------------------------------------------
but_a_o : out std_logic_vector(num_pads_g-1 downto 0);
but_b_o : out std_logic_vector(num_pads_g-1 downto 0);
but_x_o : out std_logic_vector(num_pads_g-1 downto 0);
but_y_o : out std_logic_vector(num_pads_g-1 downto 0);
but_start_o : out std_logic_vector(num_pads_g-1 downto 0);
but_sel_o : out std_logic_vector(num_pads_g-1 downto 0);
but_tl_o : out std_logic_vector(num_pads_g-1 downto 0);
but_tr_o : out std_logic_vector(num_pads_g-1 downto 0);
but_up_o : out std_logic_vector(num_pads_g-1 downto 0);
but_down_o : out std_logic_vector(num_pads_g-1 downto 0);
but_left_o : out std_logic_vector(num_pads_g-1 downto 0);
but_right_o : out std_logic_vector(num_pads_g-1 downto 0)
);
end snespad;
architecture struct of snespad is
component snespad_ctrl
generic (
reset_level_g : natural := 0;
clocks_per_6us_g : natural := 6
);
port (
clk_i : in std_logic;
reset_i : in std_logic;
clk_en_o : out boolean;
shift_buttons_o : out boolean;
save_buttons_o : out boolean;
pad_clk_o : out std_logic;
pad_latch_o : out std_logic
);
end component snespad_ctrl;
component snespad_pad
generic (
reset_level_g : natural := 0;
button_level_g : natural := 0
);
port (
clk_i : in std_logic;
reset_i : in std_logic;
clk_en_i : in boolean;
shift_buttons_i : in boolean;
save_buttons_i : in boolean;
pad_data_i : in std_logic;
but_a_o : out std_logic;
but_b_o : out std_logic;
but_x_o : out std_logic;
but_y_o : out std_logic;
but_start_o : out std_logic;
but_sel_o : out std_logic;
but_tl_o : out std_logic;
but_tr_o : out std_logic;
but_up_o : out std_logic;
but_down_o : out std_logic;
but_left_o : out std_logic;
but_right_o : out std_logic
);
end component snespad_pad;
signal clk_en_s : boolean;
signal shift_buttons_s : boolean;
signal save_buttons_s : boolean;
begin
ctrl_b : snespad_ctrl
generic map (
reset_level_g => reset_level_g,
clocks_per_6us_g => clocks_per_6us_g
)
port map (
clk_i => clk_i,
reset_i => reset_i,
clk_en_o => clk_en_s,
shift_buttons_o => shift_buttons_s,
save_buttons_o => save_buttons_s,
pad_clk_o => pad_clk_o,
pad_latch_o => pad_latch_o
);
pads: for i in 0 to num_pads_g-1 generate
pad_b : snespad_pad
generic map (
reset_level_g => reset_level_g,
button_level_g => button_level_g
)
port map (
clk_i => clk_i,
reset_i => reset_i,
clk_en_i => clk_en_s,
shift_buttons_i => shift_buttons_s,
save_buttons_i => save_buttons_s,
pad_data_i => pad_data_i(i),
but_a_o => but_a_o(i),
but_b_o => but_b_o(i),
but_x_o => but_x_o(i),
but_y_o => but_y_o(i),
but_start_o => but_start_o(i),
but_sel_o => but_sel_o(i),
but_tl_o => but_tl_o(i),
but_tr_o => but_tr_o(i),
but_up_o => but_up_o(i),
but_down_o => but_down_o(i),
but_left_o => but_left_o(i),
but_right_o => but_right_o(i)
);
end generate;
end struct;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.1 2004/10/05 17:01:27 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1158.vhd,v 1.2 2001-10-26 16:30:03 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c06s06b00x00p02n01i01158pkg is
type I1 is range 1 to 5;
subtype I11 is I1 range 2 to 4;
type A1 is array (I1 range 2 to 4) of BOOLEAN;
end c06s06b00x00p02n01i01158pkg;
use work.c06s06b00x00p02n01i01158pkg.all;
ENTITY c06s06b00x00p02n01i01158ent IS
generic (V_all : A1 := (true,false,true));
port (PT: BOOLEAN);
END c06s06b00x00p02n01i01158ent;
ARCHITECTURE c06s06b00x00p02n01i01158arch OF c06s06b00x00p02n01i01158ent IS
BEGIN
TESTING: PROCESS
variable V : boolean;
attribute AT1 : A1;
attribute AT1 of V : variable is V_all;
variable k : integer := 0;
BEGIN
if I11'BASE'Left = 1 then
k := 5;
end if;
assert NOT( k=5 )
report "***PASSED TEST: c06s06b00x00p02n01i01158"
severity NOTE;
assert ( k=5 )
report "***FAILED TEST: c06s06b00x00p02n01i01158 - The prefix of an attribute name may be a selected name."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s06b00x00p02n01i01158arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1158.vhd,v 1.2 2001-10-26 16:30:03 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c06s06b00x00p02n01i01158pkg is
type I1 is range 1 to 5;
subtype I11 is I1 range 2 to 4;
type A1 is array (I1 range 2 to 4) of BOOLEAN;
end c06s06b00x00p02n01i01158pkg;
use work.c06s06b00x00p02n01i01158pkg.all;
ENTITY c06s06b00x00p02n01i01158ent IS
generic (V_all : A1 := (true,false,true));
port (PT: BOOLEAN);
END c06s06b00x00p02n01i01158ent;
ARCHITECTURE c06s06b00x00p02n01i01158arch OF c06s06b00x00p02n01i01158ent IS
BEGIN
TESTING: PROCESS
variable V : boolean;
attribute AT1 : A1;
attribute AT1 of V : variable is V_all;
variable k : integer := 0;
BEGIN
if I11'BASE'Left = 1 then
k := 5;
end if;
assert NOT( k=5 )
report "***PASSED TEST: c06s06b00x00p02n01i01158"
severity NOTE;
assert ( k=5 )
report "***FAILED TEST: c06s06b00x00p02n01i01158 - The prefix of an attribute name may be a selected name."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s06b00x00p02n01i01158arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1158.vhd,v 1.2 2001-10-26 16:30:03 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c06s06b00x00p02n01i01158pkg is
type I1 is range 1 to 5;
subtype I11 is I1 range 2 to 4;
type A1 is array (I1 range 2 to 4) of BOOLEAN;
end c06s06b00x00p02n01i01158pkg;
use work.c06s06b00x00p02n01i01158pkg.all;
ENTITY c06s06b00x00p02n01i01158ent IS
generic (V_all : A1 := (true,false,true));
port (PT: BOOLEAN);
END c06s06b00x00p02n01i01158ent;
ARCHITECTURE c06s06b00x00p02n01i01158arch OF c06s06b00x00p02n01i01158ent IS
BEGIN
TESTING: PROCESS
variable V : boolean;
attribute AT1 : A1;
attribute AT1 of V : variable is V_all;
variable k : integer := 0;
BEGIN
if I11'BASE'Left = 1 then
k := 5;
end if;
assert NOT( k=5 )
report "***PASSED TEST: c06s06b00x00p02n01i01158"
severity NOTE;
assert ( k=5 )
report "***FAILED TEST: c06s06b00x00p02n01i01158 - The prefix of an attribute name may be a selected name."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s06b00x00p02n01i01158arch;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY TOP IS
GENERIC (
RESULT_WIDTH : integer := 9;
NODES : integer := 15;
ADDR_SHIFT : integer := 4);
PORT (
--//////////// CLOCK //////////
GCLKIN : IN std_logic;
GCLKOUT_FPGA : OUT std_logic;
OSC_50_BANK2 : IN std_logic;
OSC_50_BANK3 : IN std_logic;
OSC_50_BANK4 : IN std_logic;
OSC_50_BANK5 : IN std_logic;
OSC_50_BANK6 : IN std_logic;
OSC_50_BANK7 : IN std_logic;
PLL_CLKIN_p : IN std_logic;
--//////////// LED x 8 //////////
LED : OUT std_logic_vector(7 downto 0);
--//////////// BUTTON x 4, EXT_IO and CPU_RESET_n //////////
BUTTON : IN std_logic_vector(3 downto 0);
CPU_RESET_n : IN std_logic;
EXT_IO : IN std_logic;
--//////////// SLIDE SWITCH x 4 //////////
SLIDE_SW : IN std_logic_vector(3 downto 0);
--//////////// SEG7 //////////
SEG0_D : OUT std_logic_vector(7 downto 0);
SEG0_DP : OUT std_logic;
SEG1_D : OUT std_logic_vector(7 downto 0);
SEG1_DP : OUT std_logic;
--//////////// Temperature //////////
TEMP_INT_n : IN std_logic;
TEMP_SMCLK : OUT std_logic;
TEMP_SMDAT : IN std_logic;
--//////////// Current //////////
CSENSE_ADC_FO : OUT std_logic;
CSENSE_CS_n : OUT std_logic_vector(1 downto 0);
CSENSE_SCK : OUT std_logic;
CSENSE_SDI : OUT std_logic;
CSENSE_SDO : IN std_logic;
--//////////// Fan //////////
FAN_CTRL : OUT std_logic;
--//////////// Flash and SRAM Address/Data Share Bus //////////
FSM_A : OUT std_logic_vector(20 downto 1);
FSM_D : INOUT std_logic_vector(15 downto 0);
--//////////// SSRAM Control //////////
SSRAM_ADV : OUT std_logic;
SSRAM_BWA_n : OUT std_logic;
SSRAM_BWB_n : OUT std_logic;
SSRAM_CE_n : OUT std_logic;
SSRAM_CKE_n : OUT std_logic;
SSRAM_CLK : OUT std_logic;
SSRAM_OE_n : OUT std_logic;
SSRAM_WE_n : OUT std_logic;
--//////////// 3-Ports High-Speed USB OTG //////////
OTG_A : OUT std_logic_vector(17 downto 1);
OTG_CS_n : OUT std_logic;
OTG_D : INOUT std_logic_vector(31 downto 0);
OTG_DC_DACK : OUT std_logic;
OTG_DC_DREQ : IN std_logic;
OTG_DC_IRQ : IN std_logic;
OTG_HC_DACK : OUT std_logic;
OTG_HC_DREQ : IN std_logic;
OTG_HC_IRQ : IN std_logic;
OTG_OE_n : OUT std_logic;
OTG_RESET_n : OUT std_logic;
OTG_WE_n : OUT std_logic);
END TOP;
ARCHITECTURE Behavioural OF TOP IS
COMPONENT system1 IS
PORT (
clk_clk : IN std_logic;
reset_reset_n : IN std_logic;
input0_extern_con_export : IN std_logic_vector(31 downto 0);
input1_extern_con_export : IN std_logic_vector(31 downto 0);
input2_extern_con_export : IN std_logic_vector(31 downto 0);
input3_extern_con_export : IN std_logic_vector(31 downto 0);
output0_extern_con_export : OUT std_logic_vector(31 downto 0);
output1_extern_con_export : OUT std_logic_vector(31 downto 0);
output2_extern_con_export : OUT std_logic_vector(31 downto 0);
output3_extern_con_export : OUT std_logic_vector(31 downto 0));
END COMPONENT;
COMPONENT pll_100mhz IS
PORT (
inclk0 : IN std_logic;
c0 : OUT std_logic);
END COMPONENT;
-- FANTASI
COMPONENT FSM IS
GENERIC (DATA_WIDTH : integer;
NODES : integer);
PORT (
CLK : IN std_logic;
RST : IN std_logic;
GO : IN std_logic;
COMPL : OUT std_logic;
EN_NODES : in std_logic_vector(NODES-1 downto 0);
RESULT : OUT std_logic_vector(DATA_WIDTH downto 0));
END COMPONENT;
COMPONENT FSM_ENABLE_NODES IS
GENERIC (NODES : integer;
ADDR : integer);
PORT (
CLK : IN std_logic;
RST : IN std_logic;
EN : IN std_logic;
M_SET : IN std_logic;
ZERO : IN std_logic;
ONE : IN std_logic;
DIN : IN std_logic_vector(ADDR-1 downto 0);
SH_DONE: OUT std_logic;
DOUT : OUT std_logic_vector(NODES-1 downto 0));
END COMPONENT;
component rgen1 is
port (
clock : in std_logic := 'X'; -- clk
resetn : in std_logic := 'X'; -- reset_n
rand_num_data : out std_logic_vector(31 downto 0); -- data
rand_num_ready : in std_logic := 'X'; -- ready
rand_num_valid : out std_logic; -- valid
start : in std_logic := 'X' -- enable
);
end component rgen1;
signal clk : std_logic;
signal reset, reset_n : std_logic;
-- Nios
signal in_port_to_the_input0 : std_logic_vector(31 downto 0);
signal in_port_to_the_input1 : std_logic_vector(31 downto 0);
signal in_port_to_the_input2 : std_logic_vector(31 downto 0);
signal in_port_to_the_input3 : std_logic_vector(31 downto 0);
signal out_port_from_the_output0 : std_logic_vector(31 downto 0);
signal out_port_from_the_output1 : std_logic_vector(31 downto 0);
signal out_port_from_the_output2 : std_logic_vector(31 downto 0);
signal out_port_from_the_output3 : std_logic_vector(31 downto 0);
-- Wires for FSMs connection
signal enables : std_logic_vector(NODES-1 downto 0);
signal en_tmp : std_logic_vector(NODES-1 downto 0);
BEGIN
-- SRAM
SSRAM_BWA_n <= '0'; -- sync byte lane A write input = 1
SSRAM_BWB_n <= '0'; -- sync byte lane B write input = 1
SSRAM_WE_n <= '1'; -- write ena = ?
SSRAM_CE_n <= '0'; -- synchronous chip ena = 1
SSRAM_ADV <= '1'; -- address valid = 1
SSRAM_CKE_n <= '0'; -- clock ena = 1
SSRAM_CLK <= '0'; -- dont care
SSRAM_OE_n <= '1'; -- output ena = 1
FAN_CTRL <= '1';
process (clk)
begin
if (clk'event and clk='1') then
reset_n <= CPU_RESET_n;
reset <= NOT(CPU_RESET_n);
end if;
end process;
process(clk,reset)
begin
if(reset = '1') then --change in reset get immediately reflected on signal 'o'.
LED <= (others => '0');
in_port_to_the_input0 <= (others => '0');
elsif(rising_edge(clk)) then
LED <= out_port_from_the_output0(7 downto 0);
in_port_to_the_input0(3 downto 0) <= SLIDE_SW;
end if;
end process;
NIOS : system1
PORT MAP(
clk_clk => clk,
reset_reset_n => reset_n,
input0_extern_con_export => in_port_to_the_input0,
input1_extern_con_export => in_port_to_the_input1,
input2_extern_con_export => in_port_to_the_input2,
input3_extern_con_export => in_port_to_the_input3,
output0_extern_con_export => out_port_from_the_output0,
output1_extern_con_export => out_port_from_the_output1,
output2_extern_con_export => out_port_from_the_output2,
output3_extern_con_export => out_port_from_the_output3);
PLL : pll_100mhz PORT MAP(OSC_50_BANK2, clk);
FANTASI_TEST : FSM
GENERIC MAP(RESULT_WIDTH, NODES)
PORT MAP(
CLK => clk,
RST => out_port_from_the_output1(0),
GO => out_port_from_the_output1(1),
EN_NODES => enables,
COMPL => in_port_to_the_input2(0),
RESULT => in_port_to_the_input1(RESULT_WIDTH downto 0));
ENABLE_NODES_CONTROL : FSM_ENABLE_NODES
GENERIC MAP(NODES, ADDR_SHIFT)
PORT MAP(
CLK => clk,
RST => out_port_from_the_output1(0),
EN => '1',
M_SET => out_port_from_the_output1(2),
ZERO => out_port_from_the_output1(3),
ONE => out_port_from_the_output1(4),
SH_DONE => in_port_to_the_input2(1),
DIN => out_port_from_the_output2(ADDR_SHIFT-1 downto 0),
DOUT => enables);
END Behavioural;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:56:33 07/06/2016
-- Design Name:
-- Module Name: kb_rf_fetch - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity kb_rf_fetch is port (
kbclk : in STD_LOGIC;
reset : in STD_LOGIC;
clk : in STD_LOGIC;
rf : out STD_LOGIC);
end kb_rf_fetch;
architecture Behavioral of kb_rf_fetch is
signal clk_history: STD_LOGIC_VECTOR(1 downto 0);
begin
clk_history_shift: process(kbclk, clk, reset)
begin
if reset = '1' then
clk_history <= "11";
elsif clk'event and clk = '1' then
clk_history(1) <= clk_history(0);
clk_history(0) <= kbclk;
end if;
end process clk_history_shift;
find_rf: process(clk_history)
begin
if clk_history = "10" then
rf <= '1';
else
rf <= '0';
end if;
end process find_rf;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:56:33 07/06/2016
-- Design Name:
-- Module Name: kb_rf_fetch - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity kb_rf_fetch is port (
kbclk : in STD_LOGIC;
reset : in STD_LOGIC;
clk : in STD_LOGIC;
rf : out STD_LOGIC);
end kb_rf_fetch;
architecture Behavioral of kb_rf_fetch is
signal clk_history: STD_LOGIC_VECTOR(1 downto 0);
begin
clk_history_shift: process(kbclk, clk, reset)
begin
if reset = '1' then
clk_history <= "11";
elsif clk'event and clk = '1' then
clk_history(1) <= clk_history(0);
clk_history(0) <= kbclk;
end if;
end process clk_history_shift;
find_rf: process(clk_history)
begin
if clk_history = "10" then
rf <= '1';
else
rf <= '0';
end if;
end process find_rf;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity GAME is
port (
CLK : in std_logic;
RST : in std_logic;
BLANKING : in std_logic;
KEYCODE : in std_logic_vector(7 downto 0);
CODE_ENABLE : in std_logic;
MAP_X, MAP_Y : in std_logic_vector(5 downto 0);
TITLE : out std_logic;
SCORE : out std_logic_vector(7 downto 0);
VISIBLE : out std_logic
;DEBUG : out std_logic
);
end GAME;
architecture RTL of GAME is
component LFSR16
port (
CLK : in std_logic;
RST : in std_logic;
RAND : out std_logic_vector(15 downto 0)
);
end component;
component LFSR15
port (
CLK : in std_logic;
RST : in std_logic;
RAND : out std_logic_vector(14 downto 0)
);
end component;
type POINT is
record
X : integer range -1 to 31;
Y : integer range -1 to 31;
end record;
type REGISTERFILE is array(47 downto 0) of POINT;
signal SNAKE_FILE : REGISTERFILE;
signal SNAKE_NEXT : POINT;
type DIRECTION is (UP, DOWN, RIGHT, LEFT);
type GAME_STATE_T is (IDLE, VISIBLE_WAIT, BLANK_WAIT, COUNTER_WAIT,
CHECK_BORDER, CHECK_EAT_ONESELF, SHIFT, CHECK_FOOD, CHECK_WIN,
MAKE_FOOD, SET_WAIT, GAMECLEAR, GAMEOVER);
signal GAME_STATE : GAME_STATE_T;
signal FOOD : POINT;
signal RAND : POINT;
signal COMPRD_POINT : POINT;
signal POINT_EXIST : std_logic;
signal SNAKE_DIRECTION, PREV_DIRECTION : DIRECTION;
signal KEY_PUSH, CODE_ENABLE_PRE : std_logic;
signal SNAKE_SPEED, WAIT_CNT : integer range 0 to 120;
signal SNAKE_LENGTH : integer range 0 to 48;
signal WALL : std_logic;
signal RAND_A : std_logic_vector(15 downto 0);
signal RAND_B : std_logic_vector(14 downto 0);
begin
U_LFSR16 : LFSR16 port map(CLK => CLK, RST => RST, RAND => RAND_A);
U_LFSR15 : LFSR15 port map(CLK => CLK, RST => RST, RAND => RAND_B);
SNAKE_NEXT.Y <= (SNAKE_FILE(0).Y - 1) when SNAKE_DIRECTION = UP else
(SNAKE_FILE(0).Y + 1) when SNAKE_DIRECTION = DOWN else
SNAKE_FILE(0).Y;
SNAKE_NEXT.X <= (SNAKE_FILE(0).X - 1) when SNAKE_DIRECTION = LEFT else
(SNAKE_FILE(0).X + 1) when SNAKE_DIRECTION = RIGHT else
SNAKE_FILE(0).X;
WALL <= '1' when SNAKE_NEXT.X = -1 or SNAKE_NEXT.Y = -1 or
SNAKE_NEXT.X = 26 or SNAKE_NEXT.Y = 26 else
'0';
DEBUG <= '1' when GAME_STATE = IDLE else '0';
SCORE <= CONV_std_logic_vector(SNAKE_LENGTH, 8);
-- Compare Snake Point with oneself or food
COMPRD_POINT <= SNAKE_NEXT when GAME_STATE = CHECK_EAT_ONESELF else FOOD;
process (COMPRD_POINT, SNAKE_LENGTH, SNAKE_FILE)
variable TMP : std_logic;
begin
TMP := '0';
for I in 0 to 47 loop
if (SNAKE_FILE(I) = COMPRD_POINT and I < SNAKE_LENGTH) then
TMP := '1';
end if;
end loop;
POINT_EXIST <= TMP;
end process;
-- Compare Snake point with Graphic output
process (MAP_X, MAP_Y, SNAKE_LENGTH, SNAKE_FILE, FOOD)
variable TMP : std_logic;
begin
TMP := '0';
for I in 0 to 47 loop
if (SNAKE_FILE(I).X = MAP_X and SNAKE_FILE(I).Y = MAP_Y and I < SNAKE_LENGTH) then
TMP := '1';
elsif (FOOD.X = MAP_X and FOOD.Y = MAP_Y) then
TMP := '1';
end if;
end loop;
VISIBLE <= TMP;
end process;
-- game main state machine
process(CLK, RST)
variable TMP : std_logic;
begin
if (RST = '0') then
GAME_STATE <= IDLE;
SNAKE_LENGTH <= 1;
WAIT_CNT <= 0;
FOOD.X <= 31;
FOOD.Y <= 31;
elsif (CLK'event and CLK = '1') then
case GAME_STATE is
when IDLE =>
if (KEY_PUSH = '1' and KEYCODE = X"29") then -- push space key
WAIT_CNT <= 0;
SNAKE_LENGTH <= 1;
case RAND_A(1 downto 0) is
when "00" =>
FOOD.X <= 5;
FOOD.Y <= 5;
when "01" =>
FOOD.X <= 20;
FOOD.Y <= 5;
when "10" =>
FOOD.X <= 5;
FOOD.Y <= 20;
when others =>
FOOD.X <= 20;
FOOD.Y <= 20;
end case;
GAME_STATE <= VISIBLE_WAIT;
else
GAME_STATE <= IDLE;
end if;
when VISIBLE_WAIT =>
if (BLANKING = '1') then
GAME_STATE <= BLANK_WAIT;
else
GAME_STATE <= VISIBLE_WAIT;
end if;
when BLANK_WAIT =>
if (BLANKING = '0') then
GAME_STATE <= COUNTER_WAIT;
else
GAME_STATE <= BLANK_WAIT;
end if;
when COUNTER_WAIT =>
if (WAIT_CNT = 0) then
GAME_STATE <= CHECK_BORDER;
else
WAIT_CNT <= WAIT_CNT - 1;
GAME_STATE <= VISIBLE_WAIT;
end if;
when CHECK_BORDER =>
if (WALL = '1') then
GAME_STATE <= GAMEOVER;
else
GAME_STATE <= CHECK_EAT_ONESELF;
end if;
when CHECK_EAT_ONESELF =>
if (POINT_EXIST = '1') then
GAME_STATE <= GAMEOVER;
else
GAME_STATE <= SHIFT;
end if;
when SHIFT =>
PREV_DIRECTION <= SNAKE_DIRECTION;
GAME_STATE <= CHECK_FOOD;
when CHECK_FOOD =>
if (SNAKE_FILE(0) = FOOD) then
SNAKE_LENGTH <= SNAKE_LENGTH + 1;
GAME_STATE <= CHECK_WIN;
else
GAME_STATE <= SET_WAIT;
end if;
when CHECK_WIN =>
if (SNAKE_LENGTH = 47) then
GAME_STATE <= GAMECLEAR;
else
FOOD <= RAND;
GAME_STATE <= MAKE_FOOD;
end if;
when MAKE_FOOD =>
if (POINT_EXIST = '0') then
GAME_STATE <= SET_WAIT;
else
FOOD <= RAND;
GAME_STATE <= MAKE_FOOD;
end if;
when SET_WAIT =>
case SNAKE_LENGTH is
when 0 to 3 =>
WAIT_CNT <= 14;
when 4 to 10 =>
WAIT_CNT <= 13;
when 11 to 15 =>
WAIT_CNT <= 10;
when 16 to 20 =>
WAIT_CNT <= 8;
when 21 to 25 =>
WAIT_CNT <= 6;
when 26 to 35 =>
WAIT_CNT <= 5;
when 36 to 43 =>
WAIT_CNT <= 5;
when 44 to 47 =>
WAIT_CNT <= 3;
when others =>
WAIT_CNT <= 40;
end case;
GAME_STATE <= VISIBLE_WAIT;
when GAMECLEAR =>
GAME_STATE <= IDLE;
when GAMEOVER =>
GAME_STATE <= IDLE;
end case;
end if;
end process;
-- make food
process (RAND_A, RAND_B)
variable CANADIATE : POINT;
begin
CANADIATE.X := CONV_INTEGER(RAND_A(4 downto 0));
CANADIATE.Y := CONV_INTEGER(RAND_B(4 downto 0));
if (CANADIATE.X > 25) then
CANADIATE.X := CANADIATE.X - 13;
end if;
if (CANADIATE.Y > 25) then
CANADIATE.Y := CANADIATE.Y - 13;
end if;
RAND <= CANADIATE;
end process;
-- Shift Snake Shift Register File
-- I don't know why, but State machie viewer does not work when this process is exist.
process (CLK, RST, GAME_STATE, SNAKE_FILE, SNAKE_NEXT) begin
if (RST = '0') then
SNAKE_FILE(0).X <= 13;
SNAKE_FILE(0).Y <= 13;
for I in 1 to 47 loop
SNAKE_FILE(I).X <= 0;
SNAKE_FILE(I).Y <= 0;
end loop;
elsif (CLK'event and CLK = '1') then
if (GAME_STATE = IDLE) then
SNAKE_FILE(0).X <= 13;
SNAKE_FILE(0).Y <= 13;
elsif (GAME_STATE = SHIFT) then
SNAKE_FILE(0) <= SNAKE_NEXT;
for I in 1 to 47 loop
SNAKE_FILE(I) <= SNAKE_FILE(I-1);
end loop;
end if;
end if;
end process;
-- keyboard input
process(CLK, RST) begin
if (RST = '0') then
CODE_ENABLE_PRE <= '0';
KEY_PUSH <= '0';
elsif (CLK'event and CLK = '1') then
if (CODE_ENABLE = '1' and CODE_ENABLE_PRE = '0') then
KEY_PUSH <= '1';
CODE_ENABLE_PRE <= CODE_ENABLE;
else
KEY_PUSH <= '0';
CODE_ENABLE_PRE <= CODE_ENABLE;
end if;
end if;
end process;
-- keyboard direction
process(CLK, RST) begin
if (RST = '0') then
SNAKE_DIRECTION <= UP;
elsif(CLK'event and CLK ='1') then
if (KEY_PUSH = '1') then
if (KEYCODE = X"72" and PREV_DIRECTION /= UP) then
SNAKE_DIRECTION <= DOWN;
elsif (KEYCODE = X"75" and PREV_DIRECTION /= DOWN) then
SNAKE_DIRECTION <= UP;
elsif (KEYCODE = X"74" and PREV_DIRECTION /= LEFT) then
SNAKE_DIRECTION <= RIGHT;
elsif (KEYCODE = X"6B" and PREV_DIRECTION /= RIGHT) then
SNAKE_DIRECTION <= LEFT;
end if;
end if;
end if;
end process;
end RTL;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for ddrv4
--
-- Generated
-- by: wig
-- on: Mon Jul 18 15:46:40 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ddrv4-e.vhd,v 1.2 2005/07/19 07:13:14 wig Exp $
-- $Date: 2005/07/19 07:13:14 $
-- $Log: ddrv4-e.vhd,v $
-- Revision 1.2 2005/07/19 07:13:14 wig
-- Update testcases. Added highlow/nolowbus
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity ddrv4
--
entity ddrv4 is
-- Generics:
-- No Generated Generics for Entity ddrv4
-- Generated Port Declaration:
port(
-- Generated Port for Entity ddrv4
alarm_time_ls_hr : in std_ulogic_vector(3 downto 0);
alarm_time_ls_min : in std_ulogic_vector(3 downto 0);
alarm_time_ms_hr : in std_ulogic_vector(3 downto 0);
alarm_time_ms_min : in std_ulogic_vector(3 downto 0);
current_time_ls_hr : in std_ulogic_vector(3 downto 0);
current_time_ls_min : in std_ulogic_vector(3 downto 0);
current_time_ms_hr : in std_ulogic_vector(3 downto 0);
current_time_ms_min : in std_ulogic_vector(3 downto 0);
key_buffer_0 : in std_ulogic_vector(3 downto 0);
key_buffer_1 : in std_ulogic_vector(3 downto 0);
key_buffer_2 : in std_ulogic_vector(3 downto 0);
key_buffer_3 : in std_ulogic_vector(3 downto 0);
p_mix_display_ls_hr_go : out std_ulogic_vector(6 downto 0);
p_mix_display_ls_min_go : out std_ulogic_vector(6 downto 0);
p_mix_display_ms_hr_go : out std_ulogic_vector(6 downto 0);
p_mix_display_ms_min_go : out std_ulogic_vector(6 downto 0);
p_mix_sound_alarm_go : out std_ulogic;
show_a : in std_ulogic;
show_new_time : in std_ulogic
-- End of Generated Port for Entity ddrv4
);
end ddrv4;
--
-- End of Generated Entity ddrv4
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
ENTITY c03s04b01x00p01n01i00649ent IS
END c03s04b01x00p01n01i00649ent;
ARCHITECTURE c03s04b01x00p01n01i00649arch OF c03s04b01x00p01n01i00649ent IS
type resistance is range -2147483647 to +2147483647
units
uOhm;
mOhm = 1000 uOhm;
Ohm = 1000 mOhm;
KOhm = 1000 Ohm;
end units;
type resistance_file is file of resistance;
constant C47 : resistance := 1 Ohm;
BEGIN
TESTING: PROCESS
file filein : resistance_file open write_mode is "iofile.63";
BEGIN
for i in 1 to 100 loop
write(filein, C47);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00649 - The output file will be verified by test s010294.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00649arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
ENTITY c03s04b01x00p01n01i00649ent IS
END c03s04b01x00p01n01i00649ent;
ARCHITECTURE c03s04b01x00p01n01i00649arch OF c03s04b01x00p01n01i00649ent IS
type resistance is range -2147483647 to +2147483647
units
uOhm;
mOhm = 1000 uOhm;
Ohm = 1000 mOhm;
KOhm = 1000 Ohm;
end units;
type resistance_file is file of resistance;
constant C47 : resistance := 1 Ohm;
BEGIN
TESTING: PROCESS
file filein : resistance_file open write_mode is "iofile.63";
BEGIN
for i in 1 to 100 loop
write(filein, C47);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00649 - The output file will be verified by test s010294.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00649arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
ENTITY c03s04b01x00p01n01i00649ent IS
END c03s04b01x00p01n01i00649ent;
ARCHITECTURE c03s04b01x00p01n01i00649arch OF c03s04b01x00p01n01i00649ent IS
type resistance is range -2147483647 to +2147483647
units
uOhm;
mOhm = 1000 uOhm;
Ohm = 1000 mOhm;
KOhm = 1000 Ohm;
end units;
type resistance_file is file of resistance;
constant C47 : resistance := 1 Ohm;
BEGIN
TESTING: PROCESS
file filein : resistance_file open write_mode is "iofile.63";
BEGIN
for i in 1 to 100 loop
write(filein, C47);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00649 - The output file will be verified by test s010294.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00649arch;
|
-------------------------------------------------------------------------------------
-- FILE NAME : fmc150_spi_ctrl.vhd
--
-- AUTHOR : Peter Kortekaas
--
-- COMPANY : 4DSP
--
-- ITEM : 1
--
-- UNITS : Entity - fmc150_spi_ctrl
-- architecture - fmc150_spi_ctrl_syn
--
-- LANGUAGE : VHDL
--
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
--
-- This file initialises the internal registers of devices on the FMC150 from
-- FPGA ROM through SPI communication busses.
--
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library work;
entity fmc150_spi_ctrl is
generic(
g_sim : integer := 0
);
port (
-- VIO command interface
rd_n_wr : in std_logic;
addr : in std_logic_vector(15 downto 0);
idata : in std_logic_vector(31 downto 0);
odata : out std_logic_vector(31 downto 0);
busy : out std_logic;
cdce72010_valid : in std_logic;
ads62p49_valid : in std_logic;
dac3283_valid : in std_logic;
amc7823_valid : in std_logic;
rst : in std_logic;
clk : in std_logic;
external_clock : in std_logic;
spi_sclk : out std_logic;
spi_sdata : out std_logic;
adc_n_en : out std_logic;
adc_sdo : in std_logic;
adc_reset : out std_logic;
cdce_n_en : out std_logic;
cdce_sdo : in std_logic;
cdce_n_reset : out std_logic;
cdce_n_pd : out std_logic;
ref_en : out std_logic;
pll_status : in std_logic;
dac_n_en : out std_logic;
dac_sdo : in std_logic;
mon_n_en : out std_logic;
mon_sdo : in std_logic;
mon_n_reset : out std_logic;
mon_n_int : in std_logic;
prsnt_m2c_l : in std_logic
);
end fmc150_spi_ctrl;
architecture fmc150_spi_ctrl_syn of fmc150_spi_ctrl is
----------------------------------------------------------------------------------------------------
-- Constant declaration
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
--Component declaration
----------------------------------------------------------------------------------------------------
component cdce72010_ctrl is
generic (
START_ADDR : std_logic_vector(27 downto 0) := x"0000000";
STOP_ADDR : std_logic_vector(27 downto 0) := x"00000FF";
g_sim : integer := 0
);
port (
rst : in std_logic;
clk : in std_logic;
-- Sequence interface
init_ena : in std_logic;
init_done : out std_logic;
-- Command Interface
clk_cmd : in std_logic;
in_cmd_val : in std_logic;
in_cmd : in std_logic_vector(63 downto 0);
out_cmd_val : out std_logic;
out_cmd : out std_logic_vector(63 downto 0);
in_cmd_busy : out std_logic;
-- Direct control
external_clock : in std_logic;
cdce_n_reset : out std_logic;
cdce_n_pd : out std_logic;
ref_en : out std_logic;
pll_status : in std_logic;
-- SPI control
spi_n_oe : out std_logic;
spi_n_cs : out std_logic;
spi_sclk : out std_logic;
spi_sdo : out std_logic;
spi_sdi : in std_logic
);
end component;
component ads62p49_ctrl is
generic (
START_ADDR : std_logic_vector(27 downto 0) := x"0000000";
STOP_ADDR : std_logic_vector(27 downto 0) := x"00000FF";
g_sim : integer := 0
);
port (
rst : in std_logic;
clk : in std_logic;
-- Sequence interface
init_ena : in std_logic;
init_done : out std_logic;
-- Command Interface
clk_cmd : in std_logic;
in_cmd_val : in std_logic;
in_cmd : in std_logic_vector(63 downto 0);
out_cmd_val : out std_logic;
out_cmd : out std_logic_vector(63 downto 0);
in_cmd_busy : out std_logic;
-- Direct control
adc_reset : out std_logic;
-- SPI control
spi_n_oe : out std_logic;
spi_n_cs : out std_logic;
spi_sclk : out std_logic;
spi_sdo : out std_logic;
spi_sdi : in std_logic
);
end component;
component dac3283_ctrl is
generic (
START_ADDR : std_logic_vector(27 downto 0) := x"0000000";
STOP_ADDR : std_logic_vector(27 downto 0) := x"00000FF";
g_sim : integer := 0
);
port (
rst : in std_logic;
clk : in std_logic;
-- Sequence interface
init_ena : in std_logic;
init_done : out std_logic;
-- Command Interface
clk_cmd : in std_logic;
in_cmd_val : in std_logic;
in_cmd : in std_logic_vector(63 downto 0);
out_cmd_val : out std_logic;
out_cmd : out std_logic_vector(63 downto 0);
in_cmd_busy : out std_logic;
-- SPI control
spi_n_oe : out std_logic;
spi_n_cs : out std_logic;
spi_sclk : out std_logic;
spi_sdo : out std_logic;
spi_sdi : in std_logic
);
end component;
component amc7823_ctrl is
generic (
START_ADDR : std_logic_vector(27 downto 0) := x"0000000";
STOP_ADDR : std_logic_vector(27 downto 0) := x"00000FF";
g_sim : integer := 0
);
port (
rst : in std_logic;
clk : in std_logic;
-- Sequence interface
init_ena : in std_logic;
init_done : out std_logic;
-- Command Interface
clk_cmd : in std_logic;
in_cmd_val : in std_logic;
in_cmd : in std_logic_vector(63 downto 0);
out_cmd_val : out std_logic;
out_cmd : out std_logic_vector(63 downto 0);
in_cmd_busy : out std_logic;
-- Direct control
mon_n_reset : out std_logic;
mon_n_int : in std_logic;
-- SPI control
spi_n_oe : out std_logic;
spi_n_cs : out std_logic;
spi_sclk : out std_logic;
spi_sdo : out std_logic;
spi_sdi : in std_logic
);
end component;
----------------------------------------------------------------------------------------------------
--Signal declaration
----------------------------------------------------------------------------------------------------
signal in_cmd : std_logic_vector(63 downto 0);
signal cdce72010_valid_prev : std_logic;
signal cdce72010_in_cmd_val : std_logic;
signal cdce72010_out_cmd_val : std_logic;
signal cdce72010_out_cmd : std_logic_vector(63 downto 0);
signal cdce72010_in_cmd_busy : std_logic;
signal ads62p49_valid_prev : std_logic;
signal ads62p49_in_cmd_val : std_logic;
signal ads62p49_out_cmd_val : std_logic;
signal ads62p49_out_cmd : std_logic_vector(63 downto 0);
signal ads62p49_in_cmd_busy : std_logic;
signal dac3283_valid_prev : std_logic;
signal dac3283_in_cmd_val : std_logic;
signal dac3283_out_cmd_val : std_logic;
signal dac3283_out_cmd : std_logic_vector(63 downto 0);
signal dac3283_in_cmd_busy : std_logic;
signal amc7823_valid_prev : std_logic;
signal amc7823_in_cmd_val : std_logic;
signal amc7823_out_cmd_val : std_logic;
signal amc7823_out_cmd : std_logic_vector(63 downto 0);
signal amc7823_in_cmd_busy : std_logic;
signal init_ena_cdce72010 : std_logic;
signal init_done_cdce72010 : std_logic;
signal init_ena_ads62p49 : std_logic;
signal init_done_ads62p49 : std_logic;
signal init_ena_dac3283 : std_logic;
signal init_done_dac3283 : std_logic;
signal init_ena_amc7823 : std_logic;
signal init_done_amc7823 : std_logic;
signal spi_n_oe0 : std_logic_vector(3 downto 0);
signal spi_n_cs0 : std_logic_vector(3 downto 0);
signal spi_sclk0 : std_logic_vector(3 downto 0);
signal spi_sdo0 : std_logic_vector(3 downto 0);
signal spi_sdi0 : std_logic_vector(3 downto 0);
begin
----------------------------------------------------------------------------------------------------
-- Input control
----------------------------------------------------------------------------------------------------
process(clk)
begin
if (rising_edge(clk)) then
cdce72010_valid_prev <= cdce72010_valid;
ads62p49_valid_prev <= ads62p49_valid;
dac3283_valid_prev <= dac3283_valid;
amc7823_valid_prev <= amc7823_valid;
cdce72010_in_cmd_val <= cdce72010_valid xor cdce72010_valid_prev;
ads62p49_in_cmd_val <= ads62p49_valid xor ads62p49_valid_prev;
dac3283_in_cmd_val <= dac3283_valid xor dac3283_valid_prev;
amc7823_in_cmd_val <= amc7823_valid xor amc7823_valid_prev;
if (rd_n_wr = '0') then
in_cmd(63 downto 60) <= x"1"; -- write command
else
in_cmd(63 downto 60) <= x"2"; -- read command
end if;
in_cmd(59 downto 32) <= x"000" & addr; -- address
in_cmd(31 downto 00) <= idata; -- data
end if;
end process;
----------------------------------------------------------------------------------------------------
-- Output control
----------------------------------------------------------------------------------------------------
process(clk)
begin
if (rising_edge(clk)) then
busy <= cdce72010_in_cmd_busy or
ads62p49_in_cmd_busy or
dac3283_in_cmd_busy or
amc7823_in_cmd_busy;
if (cdce72010_out_cmd_val = '1') then
odata <= cdce72010_out_cmd(31 downto 0);
elsif (ads62p49_out_cmd_val = '1') then
odata <= ads62p49_out_cmd(31 downto 0);
elsif (dac3283_out_cmd_val = '1') then
odata <= dac3283_out_cmd(31 downto 0);
elsif (amc7823_out_cmd_val = '1') then
odata <= amc7823_out_cmd(31 downto 0);
end if;
end if;
end process;
----------------------------------------------------------------------------------------------------
-- SPI Interface controlling the clock IC
----------------------------------------------------------------------------------------------------
cdce72010_ctrl_inst : cdce72010_ctrl
generic map (
START_ADDR => x"0000000",
STOP_ADDR => x"FFFFFFF",
g_sim => g_sim
)
port map (
rst => rst,
clk => clk,
init_ena => init_ena_cdce72010,
init_done => init_done_cdce72010,
clk_cmd => clk,
in_cmd_val => cdce72010_in_cmd_val,
in_cmd => in_cmd,
out_cmd_val => cdce72010_out_cmd_val,
out_cmd => cdce72010_out_cmd,
in_cmd_busy => cdce72010_in_cmd_busy,
external_clock => external_clock,
cdce_n_reset => cdce_n_reset,
cdce_n_pd => cdce_n_pd,
ref_en => ref_en,
pll_status => pll_status,
spi_n_oe => spi_n_oe0(0),
spi_n_cs => spi_n_cs0(0),
spi_sclk => spi_sclk0(0),
spi_sdo => spi_sdo0(0),
spi_sdi => spi_sdi0(0)
);
----------------------------------------------------------------------------------------------------
-- SPI interface controlling ADC chip
----------------------------------------------------------------------------------------------------
ads62p49_ctrl_inst : ads62p49_ctrl
generic map (
START_ADDR => x"0000000",
STOP_ADDR => x"FFFFFFF",
g_sim => g_sim
)
port map (
rst => rst,
clk => clk,
init_ena => init_ena_ads62p49,
init_done => init_done_ads62p49,
clk_cmd => clk,
in_cmd_val => ads62p49_in_cmd_val,
in_cmd => in_cmd,
out_cmd_val => ads62p49_out_cmd_val,
out_cmd => ads62p49_out_cmd,
in_cmd_busy => ads62p49_in_cmd_busy,
adc_reset => adc_reset,
spi_n_oe => spi_n_oe0(1),
spi_n_cs => spi_n_cs0(1),
spi_sclk => spi_sclk0(1),
spi_sdo => spi_sdo0(1),
spi_sdi => spi_sdi0(1)
);
----------------------------------------------------------------------------------------------------
-- SPI interface controlling DAC chip
----------------------------------------------------------------------------------------------------
dac3283_ctrl_inst : dac3283_ctrl
generic map (
START_ADDR => x"0000000",
STOP_ADDR => x"FFFFFFF",
g_sim => g_sim
)
port map (
rst => rst,
clk => clk,
init_ena => init_ena_dac3283,
init_done => init_done_dac3283,
clk_cmd => clk,
in_cmd_val => dac3283_in_cmd_val,
in_cmd => in_cmd,
out_cmd_val => dac3283_out_cmd_val,
out_cmd => dac3283_out_cmd,
in_cmd_busy => dac3283_in_cmd_busy,
spi_n_oe => spi_n_oe0(2),
spi_n_cs => spi_n_cs0(2),
spi_sclk => spi_sclk0(2),
spi_sdo => spi_sdo0(2),
spi_sdi => spi_sdi0(2)
);
----------------------------------------------------------------------------------------------------
-- SPI interface controlling Monitoring chip
----------------------------------------------------------------------------------------------------
amc7823_ctrl_inst : amc7823_ctrl
generic map (
START_ADDR => x"0000000",
STOP_ADDR => x"FFFFFFF",
g_sim => g_sim
)
port map (
rst => rst,
clk => clk,
init_ena => init_ena_amc7823,
init_done => init_done_amc7823,
clk_cmd => clk,
in_cmd_val => amc7823_in_cmd_val,
in_cmd => in_cmd,
out_cmd_val => amc7823_out_cmd_val,
out_cmd => amc7823_out_cmd,
in_cmd_busy => amc7823_in_cmd_busy,
mon_n_reset => mon_n_reset,
mon_n_int => mon_n_int,
spi_n_oe => spi_n_oe0(3),
spi_n_cs => spi_n_cs0(3),
spi_sclk => spi_sclk0(3),
spi_sdo => spi_sdo0(3),
spi_sdi => spi_sdi0(3)
);
----------------------------------------------------------------------------------------------------
-- SPI PHY, shared SPI bus
----------------------------------------------------------------------------------------------------
spi_sclk <= spi_sclk0(0) when spi_n_cs0(0) = '0' else
spi_sclk0(1) when spi_n_cs0(1) = '0' else
spi_sclk0(2) when spi_n_cs0(2) = '0' else
spi_sclk0(3) when spi_n_cs0(3) = '0' else '0';
spi_sdata <= spi_sdo0(0) when spi_n_oe0(0) = '0' else
spi_sdo0(1) when spi_n_oe0(1) = '0' else
spi_sdo0(2) when spi_n_oe0(2) = '0' else
spi_sdo0(3) when spi_n_oe0(3) = '0' else '0';
cdce_n_en <= spi_n_cs0(0);
adc_n_en <= spi_n_cs0(1);
dac_n_en <= spi_n_cs0(2);
mon_n_en <= spi_n_cs0(3);
spi_sdi0(0) <= cdce_sdo;
spi_sdi0(1) <= adc_sdo;
spi_sdi0(2) <= dac_sdo;
spi_sdi0(3) <= mon_sdo;
----------------------------------------------------------------------------------------------------
-- Sequence SPI initialization
----------------------------------------------------------------------------------------------------
init_ena_cdce72010 <= '1';
init_ena_ads62p49 <= init_done_cdce72010;
init_ena_dac3283 <= init_done_ads62p49;
init_ena_amc7823 <= init_done_dac3283;
----------------------------------------------------------------------------------------------------
-- End
----------------------------------------------------------------------------------------------------
end fmc150_spi_ctrl_syn;
|
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
--Date : Thu Jun 01 02:21:04 2017
--Host : GILAMONSTER running 64-bit major release (build 9200)
--Command : generate_target system_wrapper.bd
--Design : system_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_wrapper is
port (
M_AXIS_MM2S_STS_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXIS_MM2S_STS_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXIS_MM2S_STS_tlast : out STD_LOGIC;
M_AXIS_MM2S_STS_tready : in STD_LOGIC;
M_AXIS_MM2S_STS_tvalid : out STD_LOGIC;
M_AXIS_MM2S_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXIS_MM2S_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXIS_MM2S_tlast : out STD_LOGIC;
M_AXIS_MM2S_tready : in STD_LOGIC;
M_AXIS_MM2S_tvalid : out STD_LOGIC;
M_AXIS_S2MM_STS_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXIS_S2MM_STS_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXIS_S2MM_STS_tlast : out STD_LOGIC;
M_AXIS_S2MM_STS_tready : in STD_LOGIC;
M_AXIS_S2MM_STS_tvalid : out STD_LOGIC;
M_AXI_MM2S_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_MM2S_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_MM2S_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_MM2S_arid : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_MM2S_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_MM2S_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_MM2S_arready : in STD_LOGIC;
M_AXI_MM2S_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_MM2S_aruser : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_MM2S_arvalid : out STD_LOGIC;
M_AXI_MM2S_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_MM2S_rlast : in STD_LOGIC;
M_AXI_MM2S_rready : out STD_LOGIC;
M_AXI_MM2S_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_MM2S_rvalid : in STD_LOGIC;
M_AXI_S2MM_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_S2MM_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_S2MM_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_S2MM_awid : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_S2MM_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_S2MM_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_S2MM_awready : in STD_LOGIC;
M_AXI_S2MM_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_S2MM_awuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_S2MM_awvalid : out STD_LOGIC;
M_AXI_S2MM_bready : out STD_LOGIC;
M_AXI_S2MM_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_S2MM_bvalid : in STD_LOGIC;
M_AXI_S2MM_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_S2MM_wlast : out STD_LOGIC;
M_AXI_S2MM_wready : in STD_LOGIC;
M_AXI_S2MM_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_S2MM_wvalid : out STD_LOGIC;
S_AXIS_MM2S_CMD_tdata : in STD_LOGIC_VECTOR ( 71 downto 0 );
S_AXIS_MM2S_CMD_tready : out STD_LOGIC;
S_AXIS_MM2S_CMD_tvalid : in STD_LOGIC;
S_AXIS_S2MM_CMD_tdata : in STD_LOGIC_VECTOR ( 71 downto 0 );
S_AXIS_S2MM_CMD_tready : out STD_LOGIC;
S_AXIS_S2MM_CMD_tvalid : in STD_LOGIC;
S_AXIS_S2MM_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIS_S2MM_tkeep : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXIS_S2MM_tlast : in STD_LOGIC;
S_AXIS_S2MM_tready : out STD_LOGIC;
S_AXIS_S2MM_tvalid : in STD_LOGIC;
aclk : in STD_LOGIC;
mm2s_err : out STD_LOGIC;
s2mm_err : out STD_LOGIC
);
end system_wrapper;
architecture STRUCTURE of system_wrapper is
component system is
port (
S_AXIS_S2MM_CMD_tdata : in STD_LOGIC_VECTOR ( 71 downto 0 );
S_AXIS_S2MM_CMD_tready : out STD_LOGIC;
S_AXIS_S2MM_CMD_tvalid : in STD_LOGIC;
S_AXIS_MM2S_CMD_tdata : in STD_LOGIC_VECTOR ( 71 downto 0 );
S_AXIS_MM2S_CMD_tready : out STD_LOGIC;
S_AXIS_MM2S_CMD_tvalid : in STD_LOGIC;
s2mm_err : out STD_LOGIC;
M_AXIS_MM2S_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXIS_MM2S_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXIS_MM2S_tlast : out STD_LOGIC;
M_AXIS_MM2S_tready : in STD_LOGIC;
M_AXIS_MM2S_tvalid : out STD_LOGIC;
M_AXI_S2MM_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_S2MM_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_S2MM_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_S2MM_awid : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_S2MM_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_S2MM_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_S2MM_awready : in STD_LOGIC;
M_AXI_S2MM_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_S2MM_awuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_S2MM_awvalid : out STD_LOGIC;
M_AXI_S2MM_bready : out STD_LOGIC;
M_AXI_S2MM_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_S2MM_bvalid : in STD_LOGIC;
M_AXI_S2MM_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_S2MM_wlast : out STD_LOGIC;
M_AXI_S2MM_wready : in STD_LOGIC;
M_AXI_S2MM_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_S2MM_wvalid : out STD_LOGIC;
M_AXIS_S2MM_STS_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXIS_S2MM_STS_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXIS_S2MM_STS_tlast : out STD_LOGIC;
M_AXIS_S2MM_STS_tready : in STD_LOGIC;
M_AXIS_S2MM_STS_tvalid : out STD_LOGIC;
M_AXIS_MM2S_STS_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXIS_MM2S_STS_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXIS_MM2S_STS_tlast : out STD_LOGIC;
M_AXIS_MM2S_STS_tready : in STD_LOGIC;
M_AXIS_MM2S_STS_tvalid : out STD_LOGIC;
mm2s_err : out STD_LOGIC;
M_AXI_MM2S_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_MM2S_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_MM2S_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_MM2S_arid : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_MM2S_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_MM2S_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_MM2S_arready : in STD_LOGIC;
M_AXI_MM2S_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_MM2S_aruser : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_MM2S_arvalid : out STD_LOGIC;
M_AXI_MM2S_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_MM2S_rlast : in STD_LOGIC;
M_AXI_MM2S_rready : out STD_LOGIC;
M_AXI_MM2S_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_MM2S_rvalid : in STD_LOGIC;
S_AXIS_S2MM_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIS_S2MM_tkeep : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXIS_S2MM_tlast : in STD_LOGIC;
S_AXIS_S2MM_tready : out STD_LOGIC;
S_AXIS_S2MM_tvalid : in STD_LOGIC;
aclk : in STD_LOGIC
);
end component system;
begin
system_i: component system
port map (
M_AXIS_MM2S_STS_tdata(7 downto 0) => M_AXIS_MM2S_STS_tdata(7 downto 0),
M_AXIS_MM2S_STS_tkeep(0) => M_AXIS_MM2S_STS_tkeep(0),
M_AXIS_MM2S_STS_tlast => M_AXIS_MM2S_STS_tlast,
M_AXIS_MM2S_STS_tready => M_AXIS_MM2S_STS_tready,
M_AXIS_MM2S_STS_tvalid => M_AXIS_MM2S_STS_tvalid,
M_AXIS_MM2S_tdata(31 downto 0) => M_AXIS_MM2S_tdata(31 downto 0),
M_AXIS_MM2S_tkeep(3 downto 0) => M_AXIS_MM2S_tkeep(3 downto 0),
M_AXIS_MM2S_tlast => M_AXIS_MM2S_tlast,
M_AXIS_MM2S_tready => M_AXIS_MM2S_tready,
M_AXIS_MM2S_tvalid => M_AXIS_MM2S_tvalid,
M_AXIS_S2MM_STS_tdata(7 downto 0) => M_AXIS_S2MM_STS_tdata(7 downto 0),
M_AXIS_S2MM_STS_tkeep(0) => M_AXIS_S2MM_STS_tkeep(0),
M_AXIS_S2MM_STS_tlast => M_AXIS_S2MM_STS_tlast,
M_AXIS_S2MM_STS_tready => M_AXIS_S2MM_STS_tready,
M_AXIS_S2MM_STS_tvalid => M_AXIS_S2MM_STS_tvalid,
M_AXI_MM2S_araddr(31 downto 0) => M_AXI_MM2S_araddr(31 downto 0),
M_AXI_MM2S_arburst(1 downto 0) => M_AXI_MM2S_arburst(1 downto 0),
M_AXI_MM2S_arcache(3 downto 0) => M_AXI_MM2S_arcache(3 downto 0),
M_AXI_MM2S_arid(3 downto 0) => M_AXI_MM2S_arid(3 downto 0),
M_AXI_MM2S_arlen(7 downto 0) => M_AXI_MM2S_arlen(7 downto 0),
M_AXI_MM2S_arprot(2 downto 0) => M_AXI_MM2S_arprot(2 downto 0),
M_AXI_MM2S_arready => M_AXI_MM2S_arready,
M_AXI_MM2S_arsize(2 downto 0) => M_AXI_MM2S_arsize(2 downto 0),
M_AXI_MM2S_aruser(3 downto 0) => M_AXI_MM2S_aruser(3 downto 0),
M_AXI_MM2S_arvalid => M_AXI_MM2S_arvalid,
M_AXI_MM2S_rdata(31 downto 0) => M_AXI_MM2S_rdata(31 downto 0),
M_AXI_MM2S_rlast => M_AXI_MM2S_rlast,
M_AXI_MM2S_rready => M_AXI_MM2S_rready,
M_AXI_MM2S_rresp(1 downto 0) => M_AXI_MM2S_rresp(1 downto 0),
M_AXI_MM2S_rvalid => M_AXI_MM2S_rvalid,
M_AXI_S2MM_awaddr(31 downto 0) => M_AXI_S2MM_awaddr(31 downto 0),
M_AXI_S2MM_awburst(1 downto 0) => M_AXI_S2MM_awburst(1 downto 0),
M_AXI_S2MM_awcache(3 downto 0) => M_AXI_S2MM_awcache(3 downto 0),
M_AXI_S2MM_awid(3 downto 0) => M_AXI_S2MM_awid(3 downto 0),
M_AXI_S2MM_awlen(7 downto 0) => M_AXI_S2MM_awlen(7 downto 0),
M_AXI_S2MM_awprot(2 downto 0) => M_AXI_S2MM_awprot(2 downto 0),
M_AXI_S2MM_awready => M_AXI_S2MM_awready,
M_AXI_S2MM_awsize(2 downto 0) => M_AXI_S2MM_awsize(2 downto 0),
M_AXI_S2MM_awuser(3 downto 0) => M_AXI_S2MM_awuser(3 downto 0),
M_AXI_S2MM_awvalid => M_AXI_S2MM_awvalid,
M_AXI_S2MM_bready => M_AXI_S2MM_bready,
M_AXI_S2MM_bresp(1 downto 0) => M_AXI_S2MM_bresp(1 downto 0),
M_AXI_S2MM_bvalid => M_AXI_S2MM_bvalid,
M_AXI_S2MM_wdata(31 downto 0) => M_AXI_S2MM_wdata(31 downto 0),
M_AXI_S2MM_wlast => M_AXI_S2MM_wlast,
M_AXI_S2MM_wready => M_AXI_S2MM_wready,
M_AXI_S2MM_wstrb(3 downto 0) => M_AXI_S2MM_wstrb(3 downto 0),
M_AXI_S2MM_wvalid => M_AXI_S2MM_wvalid,
S_AXIS_MM2S_CMD_tdata(71 downto 0) => S_AXIS_MM2S_CMD_tdata(71 downto 0),
S_AXIS_MM2S_CMD_tready => S_AXIS_MM2S_CMD_tready,
S_AXIS_MM2S_CMD_tvalid => S_AXIS_MM2S_CMD_tvalid,
S_AXIS_S2MM_CMD_tdata(71 downto 0) => S_AXIS_S2MM_CMD_tdata(71 downto 0),
S_AXIS_S2MM_CMD_tready => S_AXIS_S2MM_CMD_tready,
S_AXIS_S2MM_CMD_tvalid => S_AXIS_S2MM_CMD_tvalid,
S_AXIS_S2MM_tdata(31 downto 0) => S_AXIS_S2MM_tdata(31 downto 0),
S_AXIS_S2MM_tkeep(3 downto 0) => S_AXIS_S2MM_tkeep(3 downto 0),
S_AXIS_S2MM_tlast => S_AXIS_S2MM_tlast,
S_AXIS_S2MM_tready => S_AXIS_S2MM_tready,
S_AXIS_S2MM_tvalid => S_AXIS_S2MM_tvalid,
aclk => aclk,
mm2s_err => mm2s_err,
s2mm_err => s2mm_err
);
end STRUCTURE;
|
-- **********************************************************************************
-- Project : MiniBlaze
-- Author : Benjamin Lemoine
-- Module : UART
-- Date : 07/25/2016
--
-- Description :
--
-- --------------------------------------------------------------------------------
-- Modifications
-- --------------------------------------------------------------------------------
-- Date : Ver. : Author : Modification comments
-- --------------------------------------------------------------------------------
-- : : :
-- 07/25/2016 : 1.0 : B.Lemoine : First draft
-- : : :
-- **********************************************************************************
-- MIT License
--
-- Copyright (c) 07/25/2016, Benjamin Lemoine
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in all
-- copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
-- **********************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity UART is
generic (
CLK_IN : integer := 10000000;
BAUDRATE : integer := 115200;
DATA_BITS : integer := 8;
STOP_BITS : integer := 1;
USE_PARITY : integer := 0;
ODD_PARITY : integer := 0
);
port (
clk : in std_logic;
rst_n : in std_logic;
-- User intf
data_in : in std_logic_vector(DATA_BITS-1 downto 0);
data_in_en : in std_logic;
data_in_ack : out std_logic;
data_out : out std_logic_vector(DATA_BITS-1 downto 0);
data_out_en : out std_logic;
frame_error : out std_logic;
parity_error : out std_logic;
-- TX/RX
RX : in std_logic;
TX : out std_logic
);
end UART;
architecture rtl of UART is
function CALC_RATIO ( C_BAUDRATE : integer; C_CLKIN : integer) return integer is
constant C_RATIO : integer := C_CLKIN/C_BAUDRATE;
constant C_REMAIN : integer := C_CLKIN rem C_BAUDRATE;
begin
if C_BAUDRATE/2 < C_REMAIN then
return C_RATIO;
else
return C_RATIO + 1;
end if;
end function CALC_RATIO;
constant c_nb_clk_per_bit : integer := CALC_RATIO(BAUDRATE, CLK_IN);
constant c_nb_clk_per_bit_div2 : integer := c_nb_clk_per_bit/2;
-- RX
type fsm_rx is (st_wait_start_bit, st_get_data, st_get_stop_bit);
signal r_fsm_rx : fsm_rx := st_wait_start_bit;
signal r_RX : std_logic := '0';
signal r2_RX : std_logic := '0';
signal r_data_rx : std_logic_vector(DATA_BITS-1 downto 0) := (others => '0');
signal r_data_rx_en : std_logic := '0';
signal r_cnt_bit_uart : unsigned(31 downto 0) := (others => '0');
signal r_cnt_data : unsigned(31 downto 0) := (others => '0');
signal r_cnt_stop : unsigned(31 downto 0) := (others => '0');
signal r_frame_error : std_logic := '0';
-- TX
type fsm_tx is (st_wait_data, st_send_start, st_send_data, st_send_stop, st_wait_1b_for_ack);
signal r_fsm_tx : fsm_tx := st_wait_data;
signal r_cnt_bit_uart_tx : unsigned(31 downto 0) := (others => '0');
signal r_cnt_data_tx : unsigned(31 downto 0) := (others => '0');
signal r_cnt_stop_tx : unsigned(31 downto 0) := (others => '0');
signal r_data_in : std_logic_vector(DATA_BITS-1 downto 0) := (others => '0');
signal r_data_in_en : std_logic := '0';
signal r_TX : std_logic := '1';
signal r_data_tx : std_logic_vector(DATA_BITS-1 downto 0) := (others => '0');
signal r_tx_ack : std_logic := '0';
begin
-- ---------------------------------------------
-- RX side
-- ---------------------------------------------
p_pipe_in : process(clk) -- Two pipes to avoid metastability
begin
if rising_edge(clk) then
r_RX <= RX;
r2_RX <= r_RX;
end if;
end process;
p_RX : process(clk)
begin
if rising_edge(clk) then
if rst_n = '0' then
r_fsm_rx <= st_wait_start_bit;
r_data_rx_en <= '0';
else
-- default values
r_data_rx_en <= '0';
case r_fsm_rx is
when st_wait_start_bit =>
if r2_RX = '0' then
r_cnt_bit_uart <= r_cnt_bit_uart + 1;
else
r_cnt_bit_uart <= (others => '0');
end if;
if r_cnt_bit_uart = c_nb_clk_per_bit_div2 - 1 then
r_fsm_rx <= st_get_data;
r_cnt_bit_uart <= (others => '0');
r_cnt_data <= (others => '0');
r_cnt_stop <= (others => '0');
r_frame_error <= '0';
end if;
when st_get_data => -- Sample at the center of each bit
if r_cnt_bit_uart = c_nb_clk_per_bit - 1 then
r_data_rx(to_integer(r_cnt_data)) <= r2_RX;
r_cnt_bit_uart <= (others => '0');
if r_cnt_data = DATA_BITS - 1 then
r_fsm_rx <= st_get_stop_bit;
else
r_cnt_data <= r_cnt_data + 1;
end if;
else
r_cnt_bit_uart <= r_cnt_bit_uart + 1;
end if;
when st_get_stop_bit =>
if r_cnt_bit_uart = c_nb_clk_per_bit - 1 then
if r2_RX = '0' then -- NOK
r_cnt_bit_uart <= (others => '0');
r_fsm_rx <= st_wait_start_bit;
r_frame_error <= '1';
else -- OK
if r_cnt_stop = STOP_BITS - 1 then
r_fsm_rx <= st_wait_start_bit;
r_data_rx_en <= '1';
else
r_cnt_stop <= r_cnt_stop + 1;
r_cnt_bit_uart <= (others => '0');
end if;
end if;
else
r_cnt_bit_uart <= r_cnt_bit_uart + 1;
end if;
when others =>
r_fsm_rx <= st_wait_start_bit;
end case;
end if;
end if;
end process;
data_out <= r_data_rx;
data_out_en <= r_data_rx_en;
-- ---------------------------------------------
-- TX side
-- ---------------------------------------------
p_pipe_tx_in : process(clk)
begin
if rising_edge(clk) then
r_data_in <= data_in;
r_data_in_en <= data_in_en;
end if;
end process;
p_TX : process(clk)
begin
if rising_edge(clk) then
if rst_n = '0' then
r_cnt_bit_uart_tx <= (others => '0');
r_cnt_data_tx <= (others => '0');
r_cnt_stop_tx <= (others => '0');
r_fsm_tx <= st_wait_data;
r_TX <= '1';
else
-- Default values
r_tx_ack <= '0';
case r_fsm_tx is
when st_wait_data =>
r_TX <= '1';
if r_data_in_en = '1' then
r_data_tx <= r_data_in;
r_fsm_tx <= st_send_start;
r_cnt_bit_uart_tx <= (others => '0');
r_cnt_data_tx <= (others => '0');
r_cnt_stop_tx <= (others => '0');
end if;
when st_send_start =>
r_TX <= '0';
if r_cnt_bit_uart_tx = c_nb_clk_per_bit - 1 then
r_cnt_bit_uart_tx <= (others => '0');
r_fsm_tx <= st_send_data;
else
r_cnt_bit_uart_tx <= r_cnt_bit_uart_tx + 1;
end if;
when st_send_data =>
if r_cnt_data_tx = DATA_BITS then
r_fsm_tx <= st_send_stop;
r_TX <= '1';
else
if r_cnt_bit_uart_tx = c_nb_clk_per_bit - 1 then
r_cnt_data_tx <= r_cnt_data_tx + 1;
r_cnt_bit_uart_tx <= (others => '0');
r_data_tx <= r_data_tx(0) & r_data_tx(DATA_BITS - 1 downto 1);
else
r_cnt_bit_uart_tx <= r_cnt_bit_uart_tx + 1;
r_TX <= r_data_tx(0);
end if;
end if;
when st_send_stop =>
r_TX <= '1';
if r_cnt_stop_tx = STOP_BITS -1 then
r_fsm_tx <= st_wait_1b_for_ack;
r_cnt_bit_uart_tx <= (others => '0');
else
if r_cnt_bit_uart_tx = c_nb_clk_per_bit - 1 then
r_cnt_bit_uart_tx <= (others => '0');
r_cnt_stop_tx <= r_cnt_stop_tx + 1;
else
r_cnt_bit_uart_tx <= r_cnt_bit_uart_tx + 1;
end if;
end if;
when st_wait_1b_for_ack =>
r_TX <= '1';
if r_cnt_bit_uart_tx = c_nb_clk_per_bit - 1 then
r_fsm_tx <= st_wait_data;
r_tx_ack <= '1';
else
r_cnt_bit_uart_tx <= r_cnt_bit_uart_tx + 1;
end if;
when others =>
r_fsm_tx <= st_wait_data;
end case;
end if;
end if;
end process;
TX <= r_TX;
data_in_ack <= r_tx_ack;
end;
|
architecture rtl of fifo is
variable sig8 : record_type_3(
element1(7 downto 0),
element2(4 downto 0)(7 downto 0)(
elementA(7 downto 0)
,
elementB(3 downto 0)
),
element3(3 downto 0)(elementC(4 downto 1), elementD(1 downto 0)),
element5(
elementE
(3 downto
0)
(6
downto 0)
,
elementF(7 downto 0)
),
element6(4 downto
0),
element7(7 downto 0));
variable sig9 : t_data_struct(data(7 downto 0));
variable sig9 : t_data_struct(
data(7 downto 0)
);
begin
end architecture rtl;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
------------------------------------------------------------
-- This file is automatically generated!
-- Here are the parameters:
-- network size x: 2
-- network size y: 2
-- Data width: 32
-- Parity: False
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE ieee.numeric_std.ALL;
entity network_2x2 is
generic (DATA_WIDTH: integer := 32; DATA_WIDTH_LV: integer := 11);
port (reset: in std_logic;
clk: in std_logic;
--------------
--------------
RX_L_0: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_0, valid_out_L_0: out std_logic;
credit_in_L_0, valid_in_L_0: in std_logic;
TX_L_0: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_1: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_1, valid_out_L_1: out std_logic;
credit_in_L_1, valid_in_L_1: in std_logic;
TX_L_1: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_2: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_2, valid_out_L_2: out std_logic;
credit_in_L_2, valid_in_L_2: in std_logic;
TX_L_2: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_3: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_3, valid_out_L_3: out std_logic;
credit_in_L_3, valid_in_L_3: in std_logic;
TX_L_3: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
link_faults_0: out std_logic_vector(4 downto 0);
turn_faults_0: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_0: in std_logic_vector(7 downto 0);
Cx_reconf_PE_0: in std_logic_vector(3 downto 0);
Reconfig_command_0 : in std_logic;
--------------
link_faults_1: out std_logic_vector(4 downto 0);
turn_faults_1: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_1: in std_logic_vector(7 downto 0);
Cx_reconf_PE_1: in std_logic_vector(3 downto 0);
Reconfig_command_1 : in std_logic;
--------------
link_faults_2: out std_logic_vector(4 downto 0);
turn_faults_2: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_2: in std_logic_vector(7 downto 0);
Cx_reconf_PE_2: in std_logic_vector(3 downto 0);
Reconfig_command_2 : in std_logic;
--------------
link_faults_3: out std_logic_vector(4 downto 0);
turn_faults_3: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_3: in std_logic_vector(7 downto 0);
Cx_reconf_PE_3: in std_logic_vector(3 downto 0);
Reconfig_command_3 : in std_logic
);
end network_2x2;
architecture behavior of network_2x2 is
component router_credit_based_PD_C_SHMU is --fault classifier plus packet-dropping
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 0;
Rxy_rst : integer := 10;
Cx_rst : integer := 10;
healthy_counter_threshold : integer := 8;
faulty_counter_threshold: integer := 2;
counter_depth: integer := 4;
NoC_size: integer := 4
);
port (
reset, clk: in std_logic;
RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
valid_in_N, valid_in_E, valid_in_W, valid_in_S, valid_in_L : in std_logic;
valid_out_N, valid_out_E, valid_out_W, valid_out_S, valid_out_L : out std_logic;
credit_out_N, credit_out_E, credit_out_W, credit_out_S, credit_out_L: out std_logic;
TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0);
Faulty_N_in, Faulty_E_in, Faulty_W_in, Faulty_S_in: in std_logic;
Faulty_N_out, Faulty_E_out, Faulty_W_out, Faulty_S_out: out std_logic;
-- should be connected to NI
link_faults: out std_logic_vector(4 downto 0);
turn_faults: out std_logic_vector(19 downto 0);
Rxy_reconf_PE: in std_logic_vector(7 downto 0);
Cx_reconf_PE: in std_logic_vector(3 downto 0);
Reconfig_command : in std_logic
);
end component;
-- generating bulk signals. not all of them are used in the design...
signal credit_out_N_0, credit_out_E_0, credit_out_W_0, credit_out_S_0: std_logic;
signal credit_out_N_1, credit_out_E_1, credit_out_W_1, credit_out_S_1: std_logic;
signal credit_out_N_2, credit_out_E_2, credit_out_W_2, credit_out_S_2: std_logic;
signal credit_out_N_3, credit_out_E_3, credit_out_W_3, credit_out_S_3: std_logic;
signal credit_in_N_0, credit_in_E_0, credit_in_W_0, credit_in_S_0: std_logic;
signal credit_in_N_1, credit_in_E_1, credit_in_W_1, credit_in_S_1: std_logic;
signal credit_in_N_2, credit_in_E_2, credit_in_W_2, credit_in_S_2: std_logic;
signal credit_in_N_3, credit_in_E_3, credit_in_W_3, credit_in_S_3: std_logic;
signal RX_N_0, RX_E_0, RX_W_0, RX_S_0 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal RX_N_1, RX_E_1, RX_W_1, RX_S_1 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal RX_N_2, RX_E_2, RX_W_2, RX_S_2 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal RX_N_3, RX_E_3, RX_W_3, RX_S_3 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal valid_out_N_0, valid_out_E_0, valid_out_W_0, valid_out_S_0: std_logic;
signal valid_out_N_1, valid_out_E_1, valid_out_W_1, valid_out_S_1: std_logic;
signal valid_out_N_2, valid_out_E_2, valid_out_W_2, valid_out_S_2: std_logic;
signal valid_out_N_3, valid_out_E_3, valid_out_W_3, valid_out_S_3: std_logic;
signal valid_in_N_0, valid_in_E_0, valid_in_W_0, valid_in_S_0: std_logic;
signal valid_in_N_1, valid_in_E_1, valid_in_W_1, valid_in_S_1: std_logic;
signal valid_in_N_2, valid_in_E_2, valid_in_W_2, valid_in_S_2: std_logic;
signal valid_in_N_3, valid_in_E_3, valid_in_W_3, valid_in_S_3: std_logic;
signal TX_N_0, TX_E_0, TX_W_0, TX_S_0 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal TX_N_1, TX_E_1, TX_W_1, TX_S_1 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal TX_N_2, TX_E_2, TX_W_2, TX_S_2 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal TX_N_3, TX_E_3, TX_W_3, TX_S_3 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal Faulty_N_out0,Faulty_E_out0,Faulty_W_out0,Faulty_S_out0: std_logic;
signal Faulty_N_in0,Faulty_E_in0,Faulty_W_in0,Faulty_S_in0: std_logic;
signal Faulty_N_out1,Faulty_E_out1,Faulty_W_out1,Faulty_S_out1: std_logic;
signal Faulty_N_in1,Faulty_E_in1,Faulty_W_in1,Faulty_S_in1: std_logic;
signal Faulty_N_out2,Faulty_E_out2,Faulty_W_out2,Faulty_S_out2: std_logic;
signal Faulty_N_in2,Faulty_E_in2,Faulty_W_in2,Faulty_S_in2: std_logic;
signal Faulty_N_out3,Faulty_E_out3,Faulty_W_out3,Faulty_S_out3: std_logic;
signal Faulty_N_in3,Faulty_E_in3,Faulty_W_in3,Faulty_S_in3: std_logic;
-- organizaiton of the network:
-- x --------------->
-- y ---- ----
-- | | 0 | --- | 1 |
-- | ---- ----
-- | | |
-- | ---- ----
-- | | 2 | --- | 3 |
-- v ---- ----
--
begin
R_0: router_credit_based_PD_C_SHMU
generic map (DATA_WIDTH =>DATA_WIDTH, current_address => 0, Rxy_rst => 60,
Cx_rst => 10, NoC_size => 2, healthy_counter_threshold => 15, faulty_counter_threshold => 3, counter_depth => 4)
port map(
reset, clk,
RX_N_0, RX_E_0, RX_W_0, RX_S_0, RX_L_0,
credit_in_N_0, credit_in_E_0, credit_in_W_0, credit_in_S_0, credit_in_L_0,
valid_in_N_0, valid_in_E_0, valid_in_W_0, valid_in_S_0, valid_in_L_0,
valid_out_N_0, valid_out_E_0, valid_out_W_0, valid_out_S_0, valid_out_L_0,
credit_out_N_0, credit_out_E_0, credit_out_W_0, credit_out_S_0, credit_out_L_0,
TX_N_0, TX_E_0, TX_W_0, TX_S_0, TX_L_0,
Faulty_N_in0,Faulty_E_in0,Faulty_W_in0,Faulty_S_in0,
Faulty_N_out0,Faulty_E_out0,Faulty_W_out0,Faulty_S_out0,
-- should be connected to NI
link_faults_0, turn_faults_0,
Rxy_reconf_PE_0, Cx_reconf_PE_0, Reconfig_command_0
);
R_1: router_credit_based_PD_C_SHMU
generic map (DATA_WIDTH =>DATA_WIDTH, current_address => 1, Rxy_rst => 60,
Cx_rst => 12, NoC_size => 2, healthy_counter_threshold => 15, faulty_counter_threshold => 3, counter_depth => 4)
port map(
reset, clk,
RX_N_1, RX_E_1, RX_W_1, RX_S_1, RX_L_1,
credit_in_N_1, credit_in_E_1, credit_in_W_1, credit_in_S_1, credit_in_L_1,
valid_in_N_1, valid_in_E_1, valid_in_W_1, valid_in_S_1, valid_in_L_1,
valid_out_N_1, valid_out_E_1, valid_out_W_1, valid_out_S_1, valid_out_L_1,
credit_out_N_1, credit_out_E_1, credit_out_W_1, credit_out_S_1, credit_out_L_1,
TX_N_1, TX_E_1, TX_W_1, TX_S_1, TX_L_1,
Faulty_N_in1,Faulty_E_in1,Faulty_W_in1,Faulty_S_in1,
Faulty_N_out1,Faulty_E_out1,Faulty_W_out1,Faulty_S_out1,
-- should be connected to NI
link_faults_1, turn_faults_1,
Rxy_reconf_PE_1, Cx_reconf_PE_1, Reconfig_command_1
);
R_2: router_credit_based_PD_C_SHMU
generic map (DATA_WIDTH =>DATA_WIDTH, current_address => 2, Rxy_rst => 60,
Cx_rst => 3, NoC_size => 2, healthy_counter_threshold => 15, faulty_counter_threshold => 3, counter_depth => 4)
port map(
reset, clk,
RX_N_2, RX_E_2, RX_W_2, RX_S_2, RX_L_2,
credit_in_N_2, credit_in_E_2, credit_in_W_2, credit_in_S_2, credit_in_L_2,
valid_in_N_2, valid_in_E_2, valid_in_W_2, valid_in_S_2, valid_in_L_2,
valid_out_N_2, valid_out_E_2, valid_out_W_2, valid_out_S_2, valid_out_L_2,
credit_out_N_2, credit_out_E_2, credit_out_W_2, credit_out_S_2, credit_out_L_2,
TX_N_2, TX_E_2, TX_W_2, TX_S_2, TX_L_2,
Faulty_N_in2,Faulty_E_in2,Faulty_W_in2,Faulty_S_in2,
Faulty_N_out2,Faulty_E_out2,Faulty_W_out2,Faulty_S_out2,
-- should be connected to NI
link_faults_2, turn_faults_2,
Rxy_reconf_PE_2, Cx_reconf_PE_2, Reconfig_command_2
);
R_3: router_credit_based_PD_C_SHMU
generic map (DATA_WIDTH =>DATA_WIDTH, current_address => 3, Rxy_rst => 60,
Cx_rst => 5, NoC_size => 2, healthy_counter_threshold => 15, faulty_counter_threshold => 3, counter_depth => 4)
port map(
reset, clk,
RX_N_3, RX_E_3, RX_W_3, RX_S_3, RX_L_3,
credit_in_N_3, credit_in_E_3, credit_in_W_3, credit_in_S_3, credit_in_L_3,
valid_in_N_3, valid_in_E_3, valid_in_W_3, valid_in_S_3, valid_in_L_3,
valid_out_N_3, valid_out_E_3, valid_out_W_3, valid_out_S_3, valid_out_L_3,
credit_out_N_3, credit_out_E_3, credit_out_W_3, credit_out_S_3, credit_out_L_3,
TX_N_3, TX_E_3, TX_W_3, TX_S_3, TX_L_3,
Faulty_N_in3,Faulty_E_in3,Faulty_W_in3,Faulty_S_in3,
Faulty_N_out3,Faulty_E_out3,Faulty_W_out3,Faulty_S_out3,
-- should be connected to NI
link_faults_3, turn_faults_3,
Rxy_reconf_PE_3, Cx_reconf_PE_3, Reconfig_command_3
);
---------------------------------------------------------------
-- binding the routers together
-- vertical ins/outs
-- connecting router: 0 to router: 2 and vice versa
RX_N_2<= TX_S_0;
RX_S_0<= TX_N_2;
-------------------
-- connecting router: 1 to router: 3 and vice versa
RX_N_3<= TX_S_1;
RX_S_1<= TX_N_3;
-------------------
-- horizontal ins/outs
-- connecting router: 0 to router: 1 and vice versa
RX_E_0 <= TX_W_1;
RX_W_1 <= TX_E_0;
-------------------
-- connecting router: 2 to router: 3 and vice versa
RX_E_2 <= TX_W_3;
RX_W_3 <= TX_E_2;
-------------------
---------------------------------------------------------------
-- binding the routers together
-- connecting router: 0 to router: 2 and vice versa
valid_in_N_2 <= valid_out_S_0;
valid_in_S_0 <= valid_out_N_2;
credit_in_S_0 <= credit_out_N_2;
credit_in_N_2 <= credit_out_S_0;
-------------------
-- connecting router: 1 to router: 3 and vice versa
valid_in_N_3 <= valid_out_S_1;
valid_in_S_1 <= valid_out_N_3;
credit_in_S_1 <= credit_out_N_3;
credit_in_N_3 <= credit_out_S_1;
-------------------
-- connecting router: 0 to router: 1 and vice versa
valid_in_E_0 <= valid_out_W_1;
valid_in_W_1 <= valid_out_E_0;
credit_in_W_1 <= credit_out_E_0;
credit_in_E_0 <= credit_out_W_1;
-------------------
-- connecting router: 2 to router: 3 and vice versa
valid_in_E_2 <= valid_out_W_3;
valid_in_W_3 <= valid_out_E_2;
credit_in_W_3 <= credit_out_E_2;
credit_in_E_2 <= credit_out_W_3;
-------------------
Faulty_S_in0 <= Faulty_N_out2;
Faulty_E_in0 <= Faulty_W_out1;
Faulty_S_in1 <= Faulty_N_out3;
Faulty_W_in1 <= Faulty_E_out0;
Faulty_N_in2 <= Faulty_S_out0;
Faulty_E_in2 <= Faulty_W_out3;
Faulty_N_in3 <= Faulty_S_out1;
Faulty_W_in3 <= Faulty_E_out2;
end;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
------------------------------------------------------------
-- This file is automatically generated!
-- Here are the parameters:
-- network size x: 2
-- network size y: 2
-- Data width: 32
-- Parity: False
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE ieee.numeric_std.ALL;
entity network_2x2 is
generic (DATA_WIDTH: integer := 32; DATA_WIDTH_LV: integer := 11);
port (reset: in std_logic;
clk: in std_logic;
--------------
--------------
RX_L_0: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_0, valid_out_L_0: out std_logic;
credit_in_L_0, valid_in_L_0: in std_logic;
TX_L_0: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_1: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_1, valid_out_L_1: out std_logic;
credit_in_L_1, valid_in_L_1: in std_logic;
TX_L_1: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_2: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_2, valid_out_L_2: out std_logic;
credit_in_L_2, valid_in_L_2: in std_logic;
TX_L_2: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_3: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_3, valid_out_L_3: out std_logic;
credit_in_L_3, valid_in_L_3: in std_logic;
TX_L_3: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
link_faults_0: out std_logic_vector(4 downto 0);
turn_faults_0: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_0: in std_logic_vector(7 downto 0);
Cx_reconf_PE_0: in std_logic_vector(3 downto 0);
Reconfig_command_0 : in std_logic;
--------------
link_faults_1: out std_logic_vector(4 downto 0);
turn_faults_1: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_1: in std_logic_vector(7 downto 0);
Cx_reconf_PE_1: in std_logic_vector(3 downto 0);
Reconfig_command_1 : in std_logic;
--------------
link_faults_2: out std_logic_vector(4 downto 0);
turn_faults_2: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_2: in std_logic_vector(7 downto 0);
Cx_reconf_PE_2: in std_logic_vector(3 downto 0);
Reconfig_command_2 : in std_logic;
--------------
link_faults_3: out std_logic_vector(4 downto 0);
turn_faults_3: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_3: in std_logic_vector(7 downto 0);
Cx_reconf_PE_3: in std_logic_vector(3 downto 0);
Reconfig_command_3 : in std_logic
);
end network_2x2;
architecture behavior of network_2x2 is
component router_credit_based_PD_C_SHMU is --fault classifier plus packet-dropping
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 0;
Rxy_rst : integer := 10;
Cx_rst : integer := 10;
healthy_counter_threshold : integer := 8;
faulty_counter_threshold: integer := 2;
counter_depth: integer := 4;
NoC_size: integer := 4
);
port (
reset, clk: in std_logic;
RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
valid_in_N, valid_in_E, valid_in_W, valid_in_S, valid_in_L : in std_logic;
valid_out_N, valid_out_E, valid_out_W, valid_out_S, valid_out_L : out std_logic;
credit_out_N, credit_out_E, credit_out_W, credit_out_S, credit_out_L: out std_logic;
TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0);
Faulty_N_in, Faulty_E_in, Faulty_W_in, Faulty_S_in: in std_logic;
Faulty_N_out, Faulty_E_out, Faulty_W_out, Faulty_S_out: out std_logic;
-- should be connected to NI
link_faults: out std_logic_vector(4 downto 0);
turn_faults: out std_logic_vector(19 downto 0);
Rxy_reconf_PE: in std_logic_vector(7 downto 0);
Cx_reconf_PE: in std_logic_vector(3 downto 0);
Reconfig_command : in std_logic
);
end component;
-- generating bulk signals. not all of them are used in the design...
signal credit_out_N_0, credit_out_E_0, credit_out_W_0, credit_out_S_0: std_logic;
signal credit_out_N_1, credit_out_E_1, credit_out_W_1, credit_out_S_1: std_logic;
signal credit_out_N_2, credit_out_E_2, credit_out_W_2, credit_out_S_2: std_logic;
signal credit_out_N_3, credit_out_E_3, credit_out_W_3, credit_out_S_3: std_logic;
signal credit_in_N_0, credit_in_E_0, credit_in_W_0, credit_in_S_0: std_logic;
signal credit_in_N_1, credit_in_E_1, credit_in_W_1, credit_in_S_1: std_logic;
signal credit_in_N_2, credit_in_E_2, credit_in_W_2, credit_in_S_2: std_logic;
signal credit_in_N_3, credit_in_E_3, credit_in_W_3, credit_in_S_3: std_logic;
signal RX_N_0, RX_E_0, RX_W_0, RX_S_0 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal RX_N_1, RX_E_1, RX_W_1, RX_S_1 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal RX_N_2, RX_E_2, RX_W_2, RX_S_2 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal RX_N_3, RX_E_3, RX_W_3, RX_S_3 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal valid_out_N_0, valid_out_E_0, valid_out_W_0, valid_out_S_0: std_logic;
signal valid_out_N_1, valid_out_E_1, valid_out_W_1, valid_out_S_1: std_logic;
signal valid_out_N_2, valid_out_E_2, valid_out_W_2, valid_out_S_2: std_logic;
signal valid_out_N_3, valid_out_E_3, valid_out_W_3, valid_out_S_3: std_logic;
signal valid_in_N_0, valid_in_E_0, valid_in_W_0, valid_in_S_0: std_logic;
signal valid_in_N_1, valid_in_E_1, valid_in_W_1, valid_in_S_1: std_logic;
signal valid_in_N_2, valid_in_E_2, valid_in_W_2, valid_in_S_2: std_logic;
signal valid_in_N_3, valid_in_E_3, valid_in_W_3, valid_in_S_3: std_logic;
signal TX_N_0, TX_E_0, TX_W_0, TX_S_0 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal TX_N_1, TX_E_1, TX_W_1, TX_S_1 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal TX_N_2, TX_E_2, TX_W_2, TX_S_2 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal TX_N_3, TX_E_3, TX_W_3, TX_S_3 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal Faulty_N_out0,Faulty_E_out0,Faulty_W_out0,Faulty_S_out0: std_logic;
signal Faulty_N_in0,Faulty_E_in0,Faulty_W_in0,Faulty_S_in0: std_logic;
signal Faulty_N_out1,Faulty_E_out1,Faulty_W_out1,Faulty_S_out1: std_logic;
signal Faulty_N_in1,Faulty_E_in1,Faulty_W_in1,Faulty_S_in1: std_logic;
signal Faulty_N_out2,Faulty_E_out2,Faulty_W_out2,Faulty_S_out2: std_logic;
signal Faulty_N_in2,Faulty_E_in2,Faulty_W_in2,Faulty_S_in2: std_logic;
signal Faulty_N_out3,Faulty_E_out3,Faulty_W_out3,Faulty_S_out3: std_logic;
signal Faulty_N_in3,Faulty_E_in3,Faulty_W_in3,Faulty_S_in3: std_logic;
-- organizaiton of the network:
-- x --------------->
-- y ---- ----
-- | | 0 | --- | 1 |
-- | ---- ----
-- | | |
-- | ---- ----
-- | | 2 | --- | 3 |
-- v ---- ----
--
begin
R_0: router_credit_based_PD_C_SHMU
generic map (DATA_WIDTH =>DATA_WIDTH, current_address => 0, Rxy_rst => 60,
Cx_rst => 10, NoC_size => 2, healthy_counter_threshold => 15, faulty_counter_threshold => 3, counter_depth => 4)
port map(
reset, clk,
RX_N_0, RX_E_0, RX_W_0, RX_S_0, RX_L_0,
credit_in_N_0, credit_in_E_0, credit_in_W_0, credit_in_S_0, credit_in_L_0,
valid_in_N_0, valid_in_E_0, valid_in_W_0, valid_in_S_0, valid_in_L_0,
valid_out_N_0, valid_out_E_0, valid_out_W_0, valid_out_S_0, valid_out_L_0,
credit_out_N_0, credit_out_E_0, credit_out_W_0, credit_out_S_0, credit_out_L_0,
TX_N_0, TX_E_0, TX_W_0, TX_S_0, TX_L_0,
Faulty_N_in0,Faulty_E_in0,Faulty_W_in0,Faulty_S_in0,
Faulty_N_out0,Faulty_E_out0,Faulty_W_out0,Faulty_S_out0,
-- should be connected to NI
link_faults_0, turn_faults_0,
Rxy_reconf_PE_0, Cx_reconf_PE_0, Reconfig_command_0
);
R_1: router_credit_based_PD_C_SHMU
generic map (DATA_WIDTH =>DATA_WIDTH, current_address => 1, Rxy_rst => 60,
Cx_rst => 12, NoC_size => 2, healthy_counter_threshold => 15, faulty_counter_threshold => 3, counter_depth => 4)
port map(
reset, clk,
RX_N_1, RX_E_1, RX_W_1, RX_S_1, RX_L_1,
credit_in_N_1, credit_in_E_1, credit_in_W_1, credit_in_S_1, credit_in_L_1,
valid_in_N_1, valid_in_E_1, valid_in_W_1, valid_in_S_1, valid_in_L_1,
valid_out_N_1, valid_out_E_1, valid_out_W_1, valid_out_S_1, valid_out_L_1,
credit_out_N_1, credit_out_E_1, credit_out_W_1, credit_out_S_1, credit_out_L_1,
TX_N_1, TX_E_1, TX_W_1, TX_S_1, TX_L_1,
Faulty_N_in1,Faulty_E_in1,Faulty_W_in1,Faulty_S_in1,
Faulty_N_out1,Faulty_E_out1,Faulty_W_out1,Faulty_S_out1,
-- should be connected to NI
link_faults_1, turn_faults_1,
Rxy_reconf_PE_1, Cx_reconf_PE_1, Reconfig_command_1
);
R_2: router_credit_based_PD_C_SHMU
generic map (DATA_WIDTH =>DATA_WIDTH, current_address => 2, Rxy_rst => 60,
Cx_rst => 3, NoC_size => 2, healthy_counter_threshold => 15, faulty_counter_threshold => 3, counter_depth => 4)
port map(
reset, clk,
RX_N_2, RX_E_2, RX_W_2, RX_S_2, RX_L_2,
credit_in_N_2, credit_in_E_2, credit_in_W_2, credit_in_S_2, credit_in_L_2,
valid_in_N_2, valid_in_E_2, valid_in_W_2, valid_in_S_2, valid_in_L_2,
valid_out_N_2, valid_out_E_2, valid_out_W_2, valid_out_S_2, valid_out_L_2,
credit_out_N_2, credit_out_E_2, credit_out_W_2, credit_out_S_2, credit_out_L_2,
TX_N_2, TX_E_2, TX_W_2, TX_S_2, TX_L_2,
Faulty_N_in2,Faulty_E_in2,Faulty_W_in2,Faulty_S_in2,
Faulty_N_out2,Faulty_E_out2,Faulty_W_out2,Faulty_S_out2,
-- should be connected to NI
link_faults_2, turn_faults_2,
Rxy_reconf_PE_2, Cx_reconf_PE_2, Reconfig_command_2
);
R_3: router_credit_based_PD_C_SHMU
generic map (DATA_WIDTH =>DATA_WIDTH, current_address => 3, Rxy_rst => 60,
Cx_rst => 5, NoC_size => 2, healthy_counter_threshold => 15, faulty_counter_threshold => 3, counter_depth => 4)
port map(
reset, clk,
RX_N_3, RX_E_3, RX_W_3, RX_S_3, RX_L_3,
credit_in_N_3, credit_in_E_3, credit_in_W_3, credit_in_S_3, credit_in_L_3,
valid_in_N_3, valid_in_E_3, valid_in_W_3, valid_in_S_3, valid_in_L_3,
valid_out_N_3, valid_out_E_3, valid_out_W_3, valid_out_S_3, valid_out_L_3,
credit_out_N_3, credit_out_E_3, credit_out_W_3, credit_out_S_3, credit_out_L_3,
TX_N_3, TX_E_3, TX_W_3, TX_S_3, TX_L_3,
Faulty_N_in3,Faulty_E_in3,Faulty_W_in3,Faulty_S_in3,
Faulty_N_out3,Faulty_E_out3,Faulty_W_out3,Faulty_S_out3,
-- should be connected to NI
link_faults_3, turn_faults_3,
Rxy_reconf_PE_3, Cx_reconf_PE_3, Reconfig_command_3
);
---------------------------------------------------------------
-- binding the routers together
-- vertical ins/outs
-- connecting router: 0 to router: 2 and vice versa
RX_N_2<= TX_S_0;
RX_S_0<= TX_N_2;
-------------------
-- connecting router: 1 to router: 3 and vice versa
RX_N_3<= TX_S_1;
RX_S_1<= TX_N_3;
-------------------
-- horizontal ins/outs
-- connecting router: 0 to router: 1 and vice versa
RX_E_0 <= TX_W_1;
RX_W_1 <= TX_E_0;
-------------------
-- connecting router: 2 to router: 3 and vice versa
RX_E_2 <= TX_W_3;
RX_W_3 <= TX_E_2;
-------------------
---------------------------------------------------------------
-- binding the routers together
-- connecting router: 0 to router: 2 and vice versa
valid_in_N_2 <= valid_out_S_0;
valid_in_S_0 <= valid_out_N_2;
credit_in_S_0 <= credit_out_N_2;
credit_in_N_2 <= credit_out_S_0;
-------------------
-- connecting router: 1 to router: 3 and vice versa
valid_in_N_3 <= valid_out_S_1;
valid_in_S_1 <= valid_out_N_3;
credit_in_S_1 <= credit_out_N_3;
credit_in_N_3 <= credit_out_S_1;
-------------------
-- connecting router: 0 to router: 1 and vice versa
valid_in_E_0 <= valid_out_W_1;
valid_in_W_1 <= valid_out_E_0;
credit_in_W_1 <= credit_out_E_0;
credit_in_E_0 <= credit_out_W_1;
-------------------
-- connecting router: 2 to router: 3 and vice versa
valid_in_E_2 <= valid_out_W_3;
valid_in_W_3 <= valid_out_E_2;
credit_in_W_3 <= credit_out_E_2;
credit_in_E_2 <= credit_out_W_3;
-------------------
Faulty_S_in0 <= Faulty_N_out2;
Faulty_E_in0 <= Faulty_W_out1;
Faulty_S_in1 <= Faulty_N_out3;
Faulty_W_in1 <= Faulty_E_out0;
Faulty_N_in2 <= Faulty_S_out0;
Faulty_E_in2 <= Faulty_W_out3;
Faulty_N_in3 <= Faulty_S_out1;
Faulty_W_in3 <= Faulty_E_out2;
end;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
------------------------------------------------------------
-- This file is automatically generated!
-- Here are the parameters:
-- network size x: 2
-- network size y: 2
-- Data width: 32
-- Parity: False
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE ieee.numeric_std.ALL;
entity network_2x2 is
generic (DATA_WIDTH: integer := 32; DATA_WIDTH_LV: integer := 11);
port (reset: in std_logic;
clk: in std_logic;
--------------
--------------
RX_L_0: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_0, valid_out_L_0: out std_logic;
credit_in_L_0, valid_in_L_0: in std_logic;
TX_L_0: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_1: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_1, valid_out_L_1: out std_logic;
credit_in_L_1, valid_in_L_1: in std_logic;
TX_L_1: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_2: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_2, valid_out_L_2: out std_logic;
credit_in_L_2, valid_in_L_2: in std_logic;
TX_L_2: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_3: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_3, valid_out_L_3: out std_logic;
credit_in_L_3, valid_in_L_3: in std_logic;
TX_L_3: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
link_faults_0: out std_logic_vector(4 downto 0);
turn_faults_0: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_0: in std_logic_vector(7 downto 0);
Cx_reconf_PE_0: in std_logic_vector(3 downto 0);
Reconfig_command_0 : in std_logic;
--------------
link_faults_1: out std_logic_vector(4 downto 0);
turn_faults_1: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_1: in std_logic_vector(7 downto 0);
Cx_reconf_PE_1: in std_logic_vector(3 downto 0);
Reconfig_command_1 : in std_logic;
--------------
link_faults_2: out std_logic_vector(4 downto 0);
turn_faults_2: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_2: in std_logic_vector(7 downto 0);
Cx_reconf_PE_2: in std_logic_vector(3 downto 0);
Reconfig_command_2 : in std_logic;
--------------
link_faults_3: out std_logic_vector(4 downto 0);
turn_faults_3: out std_logic_vector(19 downto 0);
Rxy_reconf_PE_3: in std_logic_vector(7 downto 0);
Cx_reconf_PE_3: in std_logic_vector(3 downto 0);
Reconfig_command_3 : in std_logic
);
end network_2x2;
architecture behavior of network_2x2 is
component router_credit_based_PD_C_SHMU is --fault classifier plus packet-dropping
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 0;
Rxy_rst : integer := 10;
Cx_rst : integer := 10;
healthy_counter_threshold : integer := 8;
faulty_counter_threshold: integer := 2;
counter_depth: integer := 4;
NoC_size: integer := 4
);
port (
reset, clk: in std_logic;
RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
valid_in_N, valid_in_E, valid_in_W, valid_in_S, valid_in_L : in std_logic;
valid_out_N, valid_out_E, valid_out_W, valid_out_S, valid_out_L : out std_logic;
credit_out_N, credit_out_E, credit_out_W, credit_out_S, credit_out_L: out std_logic;
TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0);
Faulty_N_in, Faulty_E_in, Faulty_W_in, Faulty_S_in: in std_logic;
Faulty_N_out, Faulty_E_out, Faulty_W_out, Faulty_S_out: out std_logic;
-- should be connected to NI
link_faults: out std_logic_vector(4 downto 0);
turn_faults: out std_logic_vector(19 downto 0);
Rxy_reconf_PE: in std_logic_vector(7 downto 0);
Cx_reconf_PE: in std_logic_vector(3 downto 0);
Reconfig_command : in std_logic
);
end component;
-- generating bulk signals. not all of them are used in the design...
signal credit_out_N_0, credit_out_E_0, credit_out_W_0, credit_out_S_0: std_logic;
signal credit_out_N_1, credit_out_E_1, credit_out_W_1, credit_out_S_1: std_logic;
signal credit_out_N_2, credit_out_E_2, credit_out_W_2, credit_out_S_2: std_logic;
signal credit_out_N_3, credit_out_E_3, credit_out_W_3, credit_out_S_3: std_logic;
signal credit_in_N_0, credit_in_E_0, credit_in_W_0, credit_in_S_0: std_logic;
signal credit_in_N_1, credit_in_E_1, credit_in_W_1, credit_in_S_1: std_logic;
signal credit_in_N_2, credit_in_E_2, credit_in_W_2, credit_in_S_2: std_logic;
signal credit_in_N_3, credit_in_E_3, credit_in_W_3, credit_in_S_3: std_logic;
signal RX_N_0, RX_E_0, RX_W_0, RX_S_0 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal RX_N_1, RX_E_1, RX_W_1, RX_S_1 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal RX_N_2, RX_E_2, RX_W_2, RX_S_2 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal RX_N_3, RX_E_3, RX_W_3, RX_S_3 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal valid_out_N_0, valid_out_E_0, valid_out_W_0, valid_out_S_0: std_logic;
signal valid_out_N_1, valid_out_E_1, valid_out_W_1, valid_out_S_1: std_logic;
signal valid_out_N_2, valid_out_E_2, valid_out_W_2, valid_out_S_2: std_logic;
signal valid_out_N_3, valid_out_E_3, valid_out_W_3, valid_out_S_3: std_logic;
signal valid_in_N_0, valid_in_E_0, valid_in_W_0, valid_in_S_0: std_logic;
signal valid_in_N_1, valid_in_E_1, valid_in_W_1, valid_in_S_1: std_logic;
signal valid_in_N_2, valid_in_E_2, valid_in_W_2, valid_in_S_2: std_logic;
signal valid_in_N_3, valid_in_E_3, valid_in_W_3, valid_in_S_3: std_logic;
signal TX_N_0, TX_E_0, TX_W_0, TX_S_0 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal TX_N_1, TX_E_1, TX_W_1, TX_S_1 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal TX_N_2, TX_E_2, TX_W_2, TX_S_2 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal TX_N_3, TX_E_3, TX_W_3, TX_S_3 : std_logic_vector (DATA_WIDTH-1 downto 0);
signal Faulty_N_out0,Faulty_E_out0,Faulty_W_out0,Faulty_S_out0: std_logic;
signal Faulty_N_in0,Faulty_E_in0,Faulty_W_in0,Faulty_S_in0: std_logic;
signal Faulty_N_out1,Faulty_E_out1,Faulty_W_out1,Faulty_S_out1: std_logic;
signal Faulty_N_in1,Faulty_E_in1,Faulty_W_in1,Faulty_S_in1: std_logic;
signal Faulty_N_out2,Faulty_E_out2,Faulty_W_out2,Faulty_S_out2: std_logic;
signal Faulty_N_in2,Faulty_E_in2,Faulty_W_in2,Faulty_S_in2: std_logic;
signal Faulty_N_out3,Faulty_E_out3,Faulty_W_out3,Faulty_S_out3: std_logic;
signal Faulty_N_in3,Faulty_E_in3,Faulty_W_in3,Faulty_S_in3: std_logic;
-- organizaiton of the network:
-- x --------------->
-- y ---- ----
-- | | 0 | --- | 1 |
-- | ---- ----
-- | | |
-- | ---- ----
-- | | 2 | --- | 3 |
-- v ---- ----
--
begin
R_0: router_credit_based_PD_C_SHMU
generic map (DATA_WIDTH =>DATA_WIDTH, current_address => 0, Rxy_rst => 60,
Cx_rst => 10, NoC_size => 2, healthy_counter_threshold => 15, faulty_counter_threshold => 3, counter_depth => 4)
port map(
reset, clk,
RX_N_0, RX_E_0, RX_W_0, RX_S_0, RX_L_0,
credit_in_N_0, credit_in_E_0, credit_in_W_0, credit_in_S_0, credit_in_L_0,
valid_in_N_0, valid_in_E_0, valid_in_W_0, valid_in_S_0, valid_in_L_0,
valid_out_N_0, valid_out_E_0, valid_out_W_0, valid_out_S_0, valid_out_L_0,
credit_out_N_0, credit_out_E_0, credit_out_W_0, credit_out_S_0, credit_out_L_0,
TX_N_0, TX_E_0, TX_W_0, TX_S_0, TX_L_0,
Faulty_N_in0,Faulty_E_in0,Faulty_W_in0,Faulty_S_in0,
Faulty_N_out0,Faulty_E_out0,Faulty_W_out0,Faulty_S_out0,
-- should be connected to NI
link_faults_0, turn_faults_0,
Rxy_reconf_PE_0, Cx_reconf_PE_0, Reconfig_command_0
);
R_1: router_credit_based_PD_C_SHMU
generic map (DATA_WIDTH =>DATA_WIDTH, current_address => 1, Rxy_rst => 60,
Cx_rst => 12, NoC_size => 2, healthy_counter_threshold => 15, faulty_counter_threshold => 3, counter_depth => 4)
port map(
reset, clk,
RX_N_1, RX_E_1, RX_W_1, RX_S_1, RX_L_1,
credit_in_N_1, credit_in_E_1, credit_in_W_1, credit_in_S_1, credit_in_L_1,
valid_in_N_1, valid_in_E_1, valid_in_W_1, valid_in_S_1, valid_in_L_1,
valid_out_N_1, valid_out_E_1, valid_out_W_1, valid_out_S_1, valid_out_L_1,
credit_out_N_1, credit_out_E_1, credit_out_W_1, credit_out_S_1, credit_out_L_1,
TX_N_1, TX_E_1, TX_W_1, TX_S_1, TX_L_1,
Faulty_N_in1,Faulty_E_in1,Faulty_W_in1,Faulty_S_in1,
Faulty_N_out1,Faulty_E_out1,Faulty_W_out1,Faulty_S_out1,
-- should be connected to NI
link_faults_1, turn_faults_1,
Rxy_reconf_PE_1, Cx_reconf_PE_1, Reconfig_command_1
);
R_2: router_credit_based_PD_C_SHMU
generic map (DATA_WIDTH =>DATA_WIDTH, current_address => 2, Rxy_rst => 60,
Cx_rst => 3, NoC_size => 2, healthy_counter_threshold => 15, faulty_counter_threshold => 3, counter_depth => 4)
port map(
reset, clk,
RX_N_2, RX_E_2, RX_W_2, RX_S_2, RX_L_2,
credit_in_N_2, credit_in_E_2, credit_in_W_2, credit_in_S_2, credit_in_L_2,
valid_in_N_2, valid_in_E_2, valid_in_W_2, valid_in_S_2, valid_in_L_2,
valid_out_N_2, valid_out_E_2, valid_out_W_2, valid_out_S_2, valid_out_L_2,
credit_out_N_2, credit_out_E_2, credit_out_W_2, credit_out_S_2, credit_out_L_2,
TX_N_2, TX_E_2, TX_W_2, TX_S_2, TX_L_2,
Faulty_N_in2,Faulty_E_in2,Faulty_W_in2,Faulty_S_in2,
Faulty_N_out2,Faulty_E_out2,Faulty_W_out2,Faulty_S_out2,
-- should be connected to NI
link_faults_2, turn_faults_2,
Rxy_reconf_PE_2, Cx_reconf_PE_2, Reconfig_command_2
);
R_3: router_credit_based_PD_C_SHMU
generic map (DATA_WIDTH =>DATA_WIDTH, current_address => 3, Rxy_rst => 60,
Cx_rst => 5, NoC_size => 2, healthy_counter_threshold => 15, faulty_counter_threshold => 3, counter_depth => 4)
port map(
reset, clk,
RX_N_3, RX_E_3, RX_W_3, RX_S_3, RX_L_3,
credit_in_N_3, credit_in_E_3, credit_in_W_3, credit_in_S_3, credit_in_L_3,
valid_in_N_3, valid_in_E_3, valid_in_W_3, valid_in_S_3, valid_in_L_3,
valid_out_N_3, valid_out_E_3, valid_out_W_3, valid_out_S_3, valid_out_L_3,
credit_out_N_3, credit_out_E_3, credit_out_W_3, credit_out_S_3, credit_out_L_3,
TX_N_3, TX_E_3, TX_W_3, TX_S_3, TX_L_3,
Faulty_N_in3,Faulty_E_in3,Faulty_W_in3,Faulty_S_in3,
Faulty_N_out3,Faulty_E_out3,Faulty_W_out3,Faulty_S_out3,
-- should be connected to NI
link_faults_3, turn_faults_3,
Rxy_reconf_PE_3, Cx_reconf_PE_3, Reconfig_command_3
);
---------------------------------------------------------------
-- binding the routers together
-- vertical ins/outs
-- connecting router: 0 to router: 2 and vice versa
RX_N_2<= TX_S_0;
RX_S_0<= TX_N_2;
-------------------
-- connecting router: 1 to router: 3 and vice versa
RX_N_3<= TX_S_1;
RX_S_1<= TX_N_3;
-------------------
-- horizontal ins/outs
-- connecting router: 0 to router: 1 and vice versa
RX_E_0 <= TX_W_1;
RX_W_1 <= TX_E_0;
-------------------
-- connecting router: 2 to router: 3 and vice versa
RX_E_2 <= TX_W_3;
RX_W_3 <= TX_E_2;
-------------------
---------------------------------------------------------------
-- binding the routers together
-- connecting router: 0 to router: 2 and vice versa
valid_in_N_2 <= valid_out_S_0;
valid_in_S_0 <= valid_out_N_2;
credit_in_S_0 <= credit_out_N_2;
credit_in_N_2 <= credit_out_S_0;
-------------------
-- connecting router: 1 to router: 3 and vice versa
valid_in_N_3 <= valid_out_S_1;
valid_in_S_1 <= valid_out_N_3;
credit_in_S_1 <= credit_out_N_3;
credit_in_N_3 <= credit_out_S_1;
-------------------
-- connecting router: 0 to router: 1 and vice versa
valid_in_E_0 <= valid_out_W_1;
valid_in_W_1 <= valid_out_E_0;
credit_in_W_1 <= credit_out_E_0;
credit_in_E_0 <= credit_out_W_1;
-------------------
-- connecting router: 2 to router: 3 and vice versa
valid_in_E_2 <= valid_out_W_3;
valid_in_W_3 <= valid_out_E_2;
credit_in_W_3 <= credit_out_E_2;
credit_in_E_2 <= credit_out_W_3;
-------------------
Faulty_S_in0 <= Faulty_N_out2;
Faulty_E_in0 <= Faulty_W_out1;
Faulty_S_in1 <= Faulty_N_out3;
Faulty_W_in1 <= Faulty_E_out0;
Faulty_N_in2 <= Faulty_S_out0;
Faulty_E_in2 <= Faulty_W_out3;
Faulty_N_in3 <= Faulty_S_out1;
Faulty_W_in3 <= Faulty_E_out2;
end;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: startBtn_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY startBtn_tb IS
END ENTITY;
ARCHITECTURE startBtn_tb_ARCH OF startBtn_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
startBtn_synth_inst:ENTITY work.startBtn_synth
GENERIC MAP (C_ROM_SYNTH => 0)
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2648.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02648ent IS
END c13s03b01x00p02n01i02648ent;
ARCHITECTURE c13s03b01x00p02n01i02648arch OF c13s03b01x00p02n01i02648ent IS
BEGIN
TESTING: PROCESS
variable (k : integer;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02648 - Identifier can only begin with a letter."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02648arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2648.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02648ent IS
END c13s03b01x00p02n01i02648ent;
ARCHITECTURE c13s03b01x00p02n01i02648arch OF c13s03b01x00p02n01i02648ent IS
BEGIN
TESTING: PROCESS
variable (k : integer;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02648 - Identifier can only begin with a letter."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02648arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2648.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02648ent IS
END c13s03b01x00p02n01i02648ent;
ARCHITECTURE c13s03b01x00p02n01i02648arch OF c13s03b01x00p02n01i02648ent IS
BEGIN
TESTING: PROCESS
variable (k : integer;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02648 - Identifier can only begin with a letter."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02648arch;
|
-- NEED RESULT: ARCH00404.P1: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00404: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00404: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00404: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00404: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: P1: Inertial transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00404
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (3)
-- 9.5.1 (1)
-- 9.5.1 (2)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00404(ARCH00404)
-- ENT00404_Test_Bench(ARCH00404_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00404 is
port (
s_st_arr1_vector : inout st_arr1_vector
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_arr1_vector : chk_sig_type := -1 ;
--
end ENT00404 ;
--
--
architecture ARCH00404 of ENT00404 is
subtype chk_time_type is Time ;
signal s_st_arr1_vector_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_arr1_vector_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 6 ;
signal st_arr1_vector_select : select_type := 1 ;
--
begin
CHG1 :
process
variable correct : boolean ;
begin
case s_st_arr1_vector_cnt is
when 0
=> null ;
-- s_st_arr1_vector(highb)(lowb to highb-1) <=
-- c_st_arr1_vector_2(highb)(lowb to highb-1) after 10 ns,
-- c_st_arr1_vector_1(highb)(lowb to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_arr1_vector(highb)(lowb to highb-1) =
c_st_arr1_vector_2(highb)(lowb to highb-1) and
(s_st_arr1_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr1_vector(highb)(lowb to highb-1) =
c_st_arr1_vector_1(highb)(lowb to highb-1) and
(s_st_arr1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00404.P1" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr1_vector_select <= transport 2 ;
-- s_st_arr1_vector(highb)(lowb to highb-1) <=
-- c_st_arr1_vector_2(highb)(lowb to highb-1) after 10 ns ,
-- c_st_arr1_vector_1(highb)(lowb to highb-1) after 20 ns ,
-- c_st_arr1_vector_2(highb)(lowb to highb-1) after 30 ns ,
-- c_st_arr1_vector_1(highb)(lowb to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_arr1_vector(highb)(lowb to highb-1) =
c_st_arr1_vector_2(highb)(lowb to highb-1) and
(s_st_arr1_vector_savt + 10 ns) = Std.Standard.Now ;
st_arr1_vector_select <= transport 3 ;
-- s_st_arr1_vector(highb)(lowb to highb-1) <=
-- c_st_arr1_vector_1(highb)(lowb to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr1_vector(highb)(lowb to highb-1) =
c_st_arr1_vector_1(highb)(lowb to highb-1) and
(s_st_arr1_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00404" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr1_vector_select <= transport 4 ;
-- s_st_arr1_vector(highb)(lowb to highb-1) <=
-- c_st_arr1_vector_1(highb)(lowb to highb-1) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_arr1_vector(highb)(lowb to highb-1) =
c_st_arr1_vector_1(highb)(lowb to highb-1) and
(s_st_arr1_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00404" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_arr1_vector_select <= transport 5 ;
-- s_st_arr1_vector(highb)(lowb to highb-1) <=
-- c_st_arr1_vector_2(highb)(lowb to highb-1) after 10 ns ,
-- c_st_arr1_vector_1(highb)(lowb to highb-1) after 20 ns ,
-- c_st_arr1_vector_2(highb)(lowb to highb-1) after 30 ns ,
-- c_st_arr1_vector_1(highb)(lowb to highb-1) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_arr1_vector(highb)(lowb to highb-1) =
c_st_arr1_vector_2(highb)(lowb to highb-1) and
(s_st_arr1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00404" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr1_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_arr1_vector(highb)(lowb to highb-1) <=
-- c_st_arr1_vector_1(highb)(lowb to highb-1) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_arr1_vector(highb)(lowb to highb-1) =
c_st_arr1_vector_1(highb)(lowb to highb-1) and
(s_st_arr1_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_arr1_vector(highb)(lowb to highb-1) =
c_st_arr1_vector_1(highb)(lowb to highb-1) and
(s_st_arr1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00404" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00404" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_arr1_vector_savt <= transport Std.Standard.Now ;
chk_st_arr1_vector <= transport s_st_arr1_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr1_vector_cnt <= transport s_st_arr1_vector_cnt + 1 ;
wait until (not s_st_arr1_vector(highb)(lowb to highb-1)'Quiet) and
(s_st_arr1_vector_savt /= Std.Standard.Now) ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_st_arr1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions completed entirely",
chk_st_arr1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
s_st_arr1_vector(highb)(lowb to highb-1) <=
c_st_arr1_vector_2(highb)(lowb to highb-1) after 10 ns,
c_st_arr1_vector_1(highb)(lowb to highb-1) after 20 ns
when st_arr1_vector_select = 1 else
--
c_st_arr1_vector_2(highb)(lowb to highb-1) after 10 ns ,
c_st_arr1_vector_1(highb)(lowb to highb-1) after 20 ns ,
c_st_arr1_vector_2(highb)(lowb to highb-1) after 30 ns ,
c_st_arr1_vector_1(highb)(lowb to highb-1) after 40 ns
when st_arr1_vector_select = 2 else
--
c_st_arr1_vector_1(highb)(lowb to highb-1) after 5 ns
when st_arr1_vector_select = 3 else
--
c_st_arr1_vector_1(highb)(lowb to highb-1) after 100 ns
when st_arr1_vector_select = 4 else
--
c_st_arr1_vector_2(highb)(lowb to highb-1) after 10 ns ,
c_st_arr1_vector_1(highb)(lowb to highb-1) after 20 ns ,
c_st_arr1_vector_2(highb)(lowb to highb-1) after 30 ns ,
c_st_arr1_vector_1(highb)(lowb to highb-1) after 40 ns
when st_arr1_vector_select = 5 else
--
-- Last transaction above is marked
c_st_arr1_vector_1(highb)(lowb to highb-1) after 40 ns ;
--
end ARCH00404 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00404_Test_Bench is
signal s_st_arr1_vector : st_arr1_vector
:= c_st_arr1_vector_1 ;
--
end ENT00404_Test_Bench ;
--
--
architecture ARCH00404_Test_Bench of ENT00404_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_arr1_vector : inout st_arr1_vector
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00404 ( ARCH00404 ) ;
begin
CIS1 : UUT
port map (
s_st_arr1_vector
)
;
end block L1 ;
end ARCH00404_Test_Bench ;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc848.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s03b01x00p09n01i00848ent IS
port ( PT : Boolean );
END c01s03b01x00p09n01i00848ent;
ARCHITECTURE c01s03b01x00p09n01i00848arch OF c01s03b01x00p09n01i00848ent IS
BEGIN
BD : block
component comp1
end component ;
begin
CIS : comp1;
BD_nested : block
begin
process
begin
null;
wait;
End process;
end block;
end block BD ;
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s03b01x00p09n01i00848 - Invalid block specification."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s03b01x00p09n01i00848arch;
configuration c01s03b01x00p09n01i00848cfg of c01s03b01x00p09n01i00848ent is
for c01s03b01x00p09n01i00848arch
for CIS -- Failure_here
-- ERROR: the CIS is not a declared block in the declarative region.
end for ;
for BD_nested -- failure_here
-- ERROR :: BD_nested is not a block label in the related declarative region.
end for;
end for;
end c01s03b01x00p09n01i00848cfg;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc848.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s03b01x00p09n01i00848ent IS
port ( PT : Boolean );
END c01s03b01x00p09n01i00848ent;
ARCHITECTURE c01s03b01x00p09n01i00848arch OF c01s03b01x00p09n01i00848ent IS
BEGIN
BD : block
component comp1
end component ;
begin
CIS : comp1;
BD_nested : block
begin
process
begin
null;
wait;
End process;
end block;
end block BD ;
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s03b01x00p09n01i00848 - Invalid block specification."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s03b01x00p09n01i00848arch;
configuration c01s03b01x00p09n01i00848cfg of c01s03b01x00p09n01i00848ent is
for c01s03b01x00p09n01i00848arch
for CIS -- Failure_here
-- ERROR: the CIS is not a declared block in the declarative region.
end for ;
for BD_nested -- failure_here
-- ERROR :: BD_nested is not a block label in the related declarative region.
end for;
end for;
end c01s03b01x00p09n01i00848cfg;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc848.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s03b01x00p09n01i00848ent IS
port ( PT : Boolean );
END c01s03b01x00p09n01i00848ent;
ARCHITECTURE c01s03b01x00p09n01i00848arch OF c01s03b01x00p09n01i00848ent IS
BEGIN
BD : block
component comp1
end component ;
begin
CIS : comp1;
BD_nested : block
begin
process
begin
null;
wait;
End process;
end block;
end block BD ;
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s03b01x00p09n01i00848 - Invalid block specification."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s03b01x00p09n01i00848arch;
configuration c01s03b01x00p09n01i00848cfg of c01s03b01x00p09n01i00848ent is
for c01s03b01x00p09n01i00848arch
for CIS -- Failure_here
-- ERROR: the CIS is not a declared block in the declarative region.
end for ;
for BD_nested -- failure_here
-- ERROR :: BD_nested is not a block label in the related declarative region.
end for;
end for;
end c01s03b01x00p09n01i00848cfg;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT pcie_data_send_fifo_top IS
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(11-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(11-1 DOWNTO 0);
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(256-1 DOWNTO 0);
DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
|
architecture a of one is
signal x : integer;
signal y, z : integer := 7;
begin
end architecture;
architecture b of one is
begin
end b;
architecture c of one is
begin
end;
|
architecture a of one is
signal x : integer;
signal y, z : integer := 7;
begin
end architecture;
architecture b of one is
begin
end b;
architecture c of one is
begin
end;
|
architecture a of one is
signal x : integer;
signal y, z : integer := 7;
begin
end architecture;
architecture b of one is
begin
end b;
architecture c of one is
begin
end;
|
architecture a of one is
signal x : integer;
signal y, z : integer := 7;
begin
end architecture;
architecture b of one is
begin
end b;
architecture c of one is
begin
end;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity shift_out is
generic (
width : positive
);
port (
par_in : in std_logic_vector(width - 1 downto 0);
-- when load is high, par_in is loaded into the shift register
-- if ce is also high, ser_out will immediately output the MSB
load : in std_logic;
ser_out : out std_logic := '1';
clk : in std_logic;
ce : in std_logic
);
end shift_out;
architecture behavioral of shift_out is
begin
process(clk)
variable par : std_logic_vector(width - 1 downto 0) := (others => '0');
begin
if rising_edge(clk) then
if load = '1' then
par := par_in;
ser_out <= '0' after 1ns;
end if;
if ce = '1' then
ser_out <= par(0) after 1ns;
par := '0' & par((width - 1) downto 1);
else
ser_out <= '0' after 1ns; -- not necessary, but makes it easier to spot what's going on
end if;
end if;
end process;
end behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity shift_out is
generic (
width : positive
);
port (
par_in : in std_logic_vector(width - 1 downto 0);
-- when load is high, par_in is loaded into the shift register
-- if ce is also high, ser_out will immediately output the MSB
load : in std_logic;
ser_out : out std_logic := '1';
clk : in std_logic;
ce : in std_logic
);
end shift_out;
architecture behavioral of shift_out is
begin
process(clk)
variable par : std_logic_vector(width - 1 downto 0) := (others => '0');
begin
if rising_edge(clk) then
if load = '1' then
par := par_in;
ser_out <= '0' after 1ns;
end if;
if ce = '1' then
ser_out <= par(0) after 1ns;
par := '0' & par((width - 1) downto 1);
else
ser_out <= '0' after 1ns; -- not necessary, but makes it easier to spot what's going on
end if;
end if;
end process;
end behavioral;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: user.org:user:axi_pmodmic_spi_0:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY block_design_axi_pmodmic_spi_0_0_0 IS
PORT (
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
spi_clk : OUT STD_LOGIC;
spi_cs : OUT STD_LOGIC;
spi_sdata : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC
);
END block_design_axi_pmodmic_spi_0_0_0;
ARCHITECTURE block_design_axi_pmodmic_spi_0_0_0_arch OF block_design_axi_pmodmic_spi_0_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF block_design_axi_pmodmic_spi_0_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_pmodmic_spi_0_v1_0 IS
GENERIC (
C_S_AXI_DATA_WIDTH : INTEGER; -- Width of S_AXI data bus
C_S_AXI_ADDR_WIDTH : INTEGER -- Width of S_AXI address bus
);
PORT (
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
spi_clk : OUT STD_LOGIC;
spi_cs : OUT STD_LOGIC;
spi_sdata : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC
);
END COMPONENT axi_pmodmic_spi_0_v1_0;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_RST RST";
BEGIN
U0 : axi_pmodmic_spi_0_v1_0
GENERIC MAP (
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ADDR_WIDTH => 32
)
PORT MAP (
s_axi_awaddr => s_axi_awaddr,
s_axi_awprot => s_axi_awprot,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arprot => s_axi_arprot,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
spi_clk => spi_clk,
spi_cs => spi_cs,
spi_sdata => spi_sdata,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn
);
END block_design_axi_pmodmic_spi_0_0_0_arch;
|
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fir_compiler:7.1
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fir_compiler_v7_1;
USE fir_compiler_v7_1.fir_compiler_v7_1;
ENTITY fir_lp_800kHz IS
PORT (
aclk : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(95 DOWNTO 0)
);
END fir_lp_800kHz;
ARCHITECTURE fir_lp_800kHz_arch OF fir_lp_800kHz IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF fir_lp_800kHz_arch: ARCHITECTURE IS "yes";
COMPONENT fir_compiler_v7_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_COMPONENT_NAME : STRING;
C_COEF_FILE : STRING;
C_COEF_FILE_LINES : INTEGER;
C_FILTER_TYPE : INTEGER;
C_INTERP_RATE : INTEGER;
C_DECIM_RATE : INTEGER;
C_ZERO_PACKING_FACTOR : INTEGER;
C_SYMMETRY : INTEGER;
C_NUM_FILTS : INTEGER;
C_NUM_TAPS : INTEGER;
C_NUM_CHANNELS : INTEGER;
C_CHANNEL_PATTERN : STRING;
C_ROUND_MODE : INTEGER;
C_COEF_RELOAD : INTEGER;
C_NUM_RELOAD_SLOTS : INTEGER;
C_COL_MODE : INTEGER;
C_COL_PIPE_LEN : INTEGER;
C_COL_CONFIG : STRING;
C_OPTIMIZATION : INTEGER;
C_DATA_PATH_WIDTHS : STRING;
C_DATA_IP_PATH_WIDTHS : STRING;
C_DATA_PX_PATH_WIDTHS : STRING;
C_DATA_WIDTH : INTEGER;
C_COEF_PATH_WIDTHS : STRING;
C_COEF_WIDTH : INTEGER;
C_DATA_PATH_SRC : STRING;
C_COEF_PATH_SRC : STRING;
C_DATA_PATH_SIGN : STRING;
C_COEF_PATH_SIGN : STRING;
C_ACCUM_PATH_WIDTHS : STRING;
C_OUTPUT_WIDTH : INTEGER;
C_OUTPUT_PATH_WIDTHS : STRING;
C_ACCUM_OP_PATH_WIDTHS : STRING;
C_EXT_MULT_CNFG : STRING;
C_DATA_PATH_PSAMP_SRC : STRING;
C_OP_PATH_PSAMP_SRC : STRING;
C_NUM_MADDS : INTEGER;
C_OPT_MADDS : STRING;
C_OVERSAMPLING_RATE : INTEGER;
C_INPUT_RATE : INTEGER;
C_OUTPUT_RATE : INTEGER;
C_DATA_MEMTYPE : INTEGER;
C_COEF_MEMTYPE : INTEGER;
C_IPBUFF_MEMTYPE : INTEGER;
C_OPBUFF_MEMTYPE : INTEGER;
C_DATAPATH_MEMTYPE : INTEGER;
C_MEM_ARRANGEMENT : INTEGER;
C_DATA_MEM_PACKING : INTEGER;
C_COEF_MEM_PACKING : INTEGER;
C_FILTS_PACKED : INTEGER;
C_LATENCY : INTEGER;
C_HAS_ARESETn : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_DATA_HAS_TLAST : INTEGER;
C_S_DATA_HAS_FIFO : INTEGER;
C_S_DATA_HAS_TUSER : INTEGER;
C_S_DATA_TDATA_WIDTH : INTEGER;
C_S_DATA_TUSER_WIDTH : INTEGER;
C_M_DATA_HAS_TREADY : INTEGER;
C_M_DATA_HAS_TUSER : INTEGER;
C_M_DATA_TDATA_WIDTH : INTEGER;
C_M_DATA_TUSER_WIDTH : INTEGER;
C_HAS_CONFIG_CHANNEL : INTEGER;
C_CONFIG_SYNC_MODE : INTEGER;
C_CONFIG_PACKET_SIZE : INTEGER;
C_CONFIG_TDATA_WIDTH : INTEGER;
C_RELOAD_TDATA_WIDTH : INTEGER
);
PORT (
aresetn : IN STD_LOGIC;
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
s_axis_data_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_data_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_config_tlast : IN STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_reload_tvalid : IN STD_LOGIC;
s_axis_reload_tready : OUT STD_LOGIC;
s_axis_reload_tlast : IN STD_LOGIC;
s_axis_reload_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tready : IN STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
event_s_data_tlast_missing : OUT STD_LOGIC;
event_s_data_tlast_unexpected : OUT STD_LOGIC;
event_s_data_chanid_incorrect : OUT STD_LOGIC;
event_s_config_tlast_missing : OUT STD_LOGIC;
event_s_config_tlast_unexpected : OUT STD_LOGIC;
event_s_reload_tlast_missing : OUT STD_LOGIC;
event_s_reload_tlast_unexpected : OUT STD_LOGIC
);
END COMPONENT fir_compiler_v7_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF fir_lp_800kHz_arch: ARCHITECTURE IS "fir_compiler_v7_1,Vivado 2014.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF fir_lp_800kHz_arch : ARCHITECTURE IS "fir_lp_800kHz,fir_compiler_v7_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF fir_lp_800kHz_arch: ARCHITECTURE IS "fir_lp_800kHz,fir_compiler_v7_1,{x_ipProduct=Vivado 2014.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fir_compiler,x_ipVersion=7.1,x_ipCoreRevision=3,x_ipLanguage=VHDL,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_COMPONENT_NAME=fir_lp_800kHz,C_COEF_FILE=fir_lp_800kHz.mif,C_COEF_FILE_LINES=1024,C_FILTER_TYPE=1,C_INTERP_RATE=1,C_DECIM_RATE=16,C_ZERO_PACKING_FACTOR=1,C_SYMMETRY=1,C_NUM_FILTS=1,C_NUM_TAPS=2048,C_NUM_CHANNELS=1,C_CHANNEL_PATTERN=fixed,C_ROUND_MODE=0,C_COEF_RELOAD=0,C_NUM_RELOAD_SLOTS=1,C_COL_MODE=1,C_COL_PIPE_LEN=4,C_COL_CONFIG=60_4,C_OPTIMIZATION=2046,C_DATA_PATH_WIDTHS=16_16,C_DATA_IP_PATH_WIDTHS=16_16,C_DATA_PX_PATH_WIDTHS=16_16,C_DATA_WIDTH=16,C_COEF_PATH_WIDTHS=24_24,C_COEF_WIDTH=24,C_DATA_PATH_SRC=0_1,C_COEF_PATH_SRC=0_0,C_DATA_PATH_SIGN=0_0,C_COEF_PATH_SIGN=0_0,C_ACCUM_PATH_WIDTHS=48_48,C_OUTPUT_WIDTH=48,C_OUTPUT_PATH_WIDTHS=48_48,C_ACCUM_OP_PATH_WIDTHS=48_48,C_EXT_MULT_CNFG=none,C_DATA_PATH_PSAMP_SRC=0,C_OP_PATH_PSAMP_SRC=0,C_NUM_MADDS=64,C_OPT_MADDS=none,C_OVERSAMPLING_RATE=1,C_INPUT_RATE=1,C_OUTPUT_RATE=16,C_DATA_MEMTYPE=0,C_COEF_MEMTYPE=2,C_IPBUFF_MEMTYPE=0,C_OPBUFF_MEMTYPE=0,C_DATAPATH_MEMTYPE=2,C_MEM_ARRANGEMENT=1,C_DATA_MEM_PACKING=0,C_COEF_MEM_PACKING=0,C_FILTS_PACKED=0,C_LATENCY=78,C_HAS_ARESETn=0,C_HAS_ACLKEN=0,C_DATA_HAS_TLAST=0,C_S_DATA_HAS_FIFO=1,C_S_DATA_HAS_TUSER=0,C_S_DATA_TDATA_WIDTH=32,C_S_DATA_TUSER_WIDTH=1,C_M_DATA_HAS_TREADY=0,C_M_DATA_HAS_TUSER=0,C_M_DATA_TDATA_WIDTH=96,C_M_DATA_TUSER_WIDTH=1,C_HAS_CONFIG_CHANNEL=0,C_CONFIG_SYNC_MODE=0,C_CONFIG_PACKET_SIZE=0,C_CONFIG_TDATA_WIDTH=1,C_RELOAD_TDATA_WIDTH=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
BEGIN
U0 : fir_compiler_v7_1
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_COMPONENT_NAME => "fir_lp_800kHz",
C_COEF_FILE => "fir_lp_800kHz.mif",
C_COEF_FILE_LINES => 1024,
C_FILTER_TYPE => 1,
C_INTERP_RATE => 1,
C_DECIM_RATE => 16,
C_ZERO_PACKING_FACTOR => 1,
C_SYMMETRY => 1,
C_NUM_FILTS => 1,
C_NUM_TAPS => 2048,
C_NUM_CHANNELS => 1,
C_CHANNEL_PATTERN => "fixed",
C_ROUND_MODE => 0,
C_COEF_RELOAD => 0,
C_NUM_RELOAD_SLOTS => 1,
C_COL_MODE => 1,
C_COL_PIPE_LEN => 4,
C_COL_CONFIG => "60,4",
C_OPTIMIZATION => 2046,
C_DATA_PATH_WIDTHS => "16,16",
C_DATA_IP_PATH_WIDTHS => "16,16",
C_DATA_PX_PATH_WIDTHS => "16,16",
C_DATA_WIDTH => 16,
C_COEF_PATH_WIDTHS => "24,24",
C_COEF_WIDTH => 24,
C_DATA_PATH_SRC => "0,1",
C_COEF_PATH_SRC => "0,0",
C_DATA_PATH_SIGN => "0,0",
C_COEF_PATH_SIGN => "0,0",
C_ACCUM_PATH_WIDTHS => "48,48",
C_OUTPUT_WIDTH => 48,
C_OUTPUT_PATH_WIDTHS => "48,48",
C_ACCUM_OP_PATH_WIDTHS => "48,48",
C_EXT_MULT_CNFG => "none",
C_DATA_PATH_PSAMP_SRC => "0",
C_OP_PATH_PSAMP_SRC => "0",
C_NUM_MADDS => 64,
C_OPT_MADDS => "none",
C_OVERSAMPLING_RATE => 1,
C_INPUT_RATE => 1,
C_OUTPUT_RATE => 16,
C_DATA_MEMTYPE => 0,
C_COEF_MEMTYPE => 2,
C_IPBUFF_MEMTYPE => 0,
C_OPBUFF_MEMTYPE => 0,
C_DATAPATH_MEMTYPE => 2,
C_MEM_ARRANGEMENT => 1,
C_DATA_MEM_PACKING => 0,
C_COEF_MEM_PACKING => 0,
C_FILTS_PACKED => 0,
C_LATENCY => 78,
C_HAS_ARESETn => 0,
C_HAS_ACLKEN => 0,
C_DATA_HAS_TLAST => 0,
C_S_DATA_HAS_FIFO => 1,
C_S_DATA_HAS_TUSER => 0,
C_S_DATA_TDATA_WIDTH => 32,
C_S_DATA_TUSER_WIDTH => 1,
C_M_DATA_HAS_TREADY => 0,
C_M_DATA_HAS_TUSER => 0,
C_M_DATA_TDATA_WIDTH => 96,
C_M_DATA_TUSER_WIDTH => 1,
C_HAS_CONFIG_CHANNEL => 0,
C_CONFIG_SYNC_MODE => 0,
C_CONFIG_PACKET_SIZE => 0,
C_CONFIG_TDATA_WIDTH => 1,
C_RELOAD_TDATA_WIDTH => 1
)
PORT MAP (
aresetn => '1',
aclk => aclk,
aclken => '1',
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tlast => '0',
s_axis_data_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_data_tdata => s_axis_data_tdata,
s_axis_config_tvalid => '0',
s_axis_config_tlast => '0',
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_reload_tvalid => '0',
s_axis_reload_tlast => '0',
s_axis_reload_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tready => '1',
m_axis_data_tdata => m_axis_data_tdata
);
END fir_lp_800kHz_arch;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.config.all; -- configuration
use work.debug.all;
use std.textio.all;
library grlib;
use grlib.stdlib.all;
use grlib.stdio.all;
use grlib.devices.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 10; -- system clock period
romwidth : integer := 16; -- rom data width (8/32)
romdepth : integer := 16 -- rom address depth
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal rst : std_logic := '1'; -- Reset
signal rstn: std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(22 downto 0);
signal data : std_logic_vector(31 downto 0);
signal romsn : std_logic_vector(1 downto 0);
signal oen : std_ulogic;
signal writen : std_ulogic;
signal iosn : std_ulogic;
-- ddr memory
signal ddr_clk : std_logic;
signal ddr_clkb : std_logic;
signal ddr_clk_fb : std_logic;
signal ddr_cke : std_logic;
signal ddr_csb : std_logic;
signal ddr_web : std_ulogic; -- ddr write enable
signal ddr_rasb : std_ulogic; -- ddr ras
signal ddr_casb : std_ulogic; -- ddr cas
signal ddr_dm : std_logic_vector (1 downto 0); -- ddr dm
signal ddr_dqs : std_logic_vector (1 downto 0); -- ddr dqs
signal ddr_ad : std_logic_vector (12 downto 0); -- ddr address
signal ddr_ba : std_logic_vector (1 downto 0); -- ddr bank address
signal ddr_dq : std_logic_vector (15 downto 0); -- ddr data
signal brdyn : std_ulogic;
signal bexcn : std_ulogic;
signal wdog : std_ulogic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal rtsn, ctsn : std_ulogic;
signal error : std_logic;
signal pio : std_logic_vector(15 downto 0);
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal clk50 : std_ulogic := '1';
signal clk_200p : std_ulogic := '0';
signal clk_200n : std_ulogic := '1';
signal plllock : std_ulogic;
-- pulled up high, therefore std_logic
signal txd1, rxd1 : std_logic;
signal eth_macclk, etx_clk, erx_clk, erx_dv, erx_er, erx_col, erx_crs, etx_en, etx_er : std_logic := '0';
signal erxd, etxd : std_logic_vector(3 downto 0) := (others => '0');
signal erxdt, etxdt : std_logic_vector(7 downto 0) := (others => '0');
signal emdc, emdio : std_logic; --dummy signal for the mdc,mdio in the phy which is not used
constant lresp : boolean := false;
signal resoutn : std_logic;
signal dsubren : std_ulogic;
signal dsuactn : std_ulogic;
begin
dsubren <= not dsubre;
-- clock and reset
clk <= not clk after ct * 1 ns;
clk50 <= not clk50 after 10 ns;
clk_200p <= not clk_200p after 2.5 ns;
clk_200n <= not clk_200n after 2.5 ns;
rst <= '1', '0' after 1000 ns;
rstn <= not rst;
dsuen <= '0'; dsubre <= '0'; rxd1 <= 'H';
address(0) <= '0';
ddr_dqs <= (others => 'L');
d3 : entity work.leon3mp
port map (
resetn => rst,
resoutn => resoutn,
clk_100mhz => clk,
clk_50mhz => clk50,
clk_200p => clk_200p,
clk_200n => clk_200n,
errorn => error,
address => address(22 downto 1),
data => data(31 downto 16),
testdata => data(15 downto 0),
ddr_clk0 => ddr_clk,
ddr_clk0b => ddr_clkb,
ddr_clk_fb => ddr_clk_fb,
ddr_cke0 => ddr_cke,
ddr_cs0b => ddr_csb,
ddr_web => ddr_web,
ddr_rasb => ddr_rasb,
ddr_casb => ddr_casb,
ddr_dm => ddr_dm,
ddr_dqs => ddr_dqs,
ddr_ad => ddr_ad,
ddr_ba => ddr_ba,
ddr_dq => ddr_dq,
sertx => dsutx,
serrx => dsurx,
rtsn => rtsn,
ctsn => ctsn,
dsuen => dsuen,
dsubre => dsubre,
dsuact => dsuactn,
oen => oen,
writen => writen,
iosn => iosn,
romsn => romsn(0),
emdio => emdio,
etx_clk => etx_clk,
erx_clk => erx_clk,
erxd => erxd,
erx_dv => erx_dv,
erx_er => erx_er,
erx_col => erx_col,
erx_crs => erx_crs,
etxd => etxd,
etx_en => etx_en,
etx_er => etx_er,
emdc => emdc
);
ddr_clk_fb <= ddr_clk;
u1 : mt46v16m16
generic map (index => -1, fname => sdramfile, fdelay => 300*CFG_MIG_DDR2)
port map(
Dq => ddr_dq(15 downto 0), Dqs => ddr_dqs(1 downto 0), Addr => ddr_ad,
Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke,
Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
Dm => ddr_dm(1 downto 0));
prom0 : for i in 0 to (romwidth/8)-1 generate
sr0 : sram generic map (index => i+4, abits => romdepth, fname => promfile)
port map (address(romdepth downto 1), data(31-i*8 downto 24-i*8), romsn(0),
writen, oen);
end generate;
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
erxd <= erxdt(3 downto 0);
etxdt <= "0000" & etxd;
p0: phy
generic map(base1000_t_fd => 0, base1000_t_hd => 0, address => 3)
port map(resoutn, emdio, etx_clk, erx_clk, erxdt, erx_dv,
erx_er, erx_col, erx_crs, etxdt, etx_en, etx_er, emdc, eth_macclk);
end generate;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 5 us;
assert (to_X01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure;
end process;
test0 : grtestmod
port map ( rstn, clk, error, address(21 downto 2), data,
iosn, oen, writen, brdyn);
data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#ef#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
--
-- txc(dsutx, 16#80#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: jtagcom
-- File: jtagcom.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: JTAG Debug Interface with AHB master interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.libjtagcom.all;
use gaisler.misc.all;
entity jtagcom is
generic (
isel : integer range 0 to 1 := 0;
nsync : integer range 1 to 2 := 2;
ainst : integer range 0 to 255 := 2;
dinst : integer range 0 to 255 := 3);
port (
rst : in std_ulogic;
clk : in std_ulogic;
tapo : in tap_out_type;
tapi : out tap_in_type;
dmao : in ahb_dma_out_type;
dmai : out ahb_dma_in_type
);
end;
architecture rtl of jtagcom is
constant ADDBITS : integer := 10;
constant NOCMP : boolean := (isel /= 0);
type state_type is (shft, ahb);
type reg_type is record
addr : std_logic_vector(34 downto 0);
data : std_logic_vector(32 downto 0);
state : state_type;
tck : std_logic_vector(nsync-1 downto 0);
tck2 : std_ulogic;
trst : std_logic_vector(nsync-1 downto 0);
tdi : std_logic_vector(nsync-1 downto 0);
shift : std_logic_vector(nsync-1 downto 0);
shift2: std_ulogic;
shift3: std_ulogic;
asel : std_logic_vector(nsync-1 downto 0);
dsel : std_logic_vector(nsync-1 downto 0);
tdi2 : std_ulogic;
end record;
signal r, rin : reg_type;
begin
comb : process (rst, r, tapo, dmao)
variable v : reg_type;
variable redge : std_ulogic;
variable vdmai : ahb_dma_in_type;
variable asel, dsel : std_ulogic;
variable vtapi : tap_in_type;
variable write, seq : std_ulogic;
begin
v := r;
if NOCMP then
asel := tapo.asel; dsel := tapo.dsel;
else
if tapo.inst = conv_std_logic_vector(ainst, 8) then asel := '1'; else asel := '0'; end if;
if tapo.inst = conv_std_logic_vector(dinst, 8) then dsel := '1'; else dsel := '0'; end if;
end if;
write := r.addr(34); seq := r.data(32);
v.tck(0) := r.tck(nsync-1); v.tck(nsync-1) := tapo.tck; v.tck2 := r.tck(0); v.shift2 := r.shift(0); v.shift3 := r.shift2;
v.trst(0) := r.trst(nsync-1); v.trst(nsync-1) := tapo.reset;
v.tdi(0) := r.tdi(nsync-1); v.tdi(nsync-1) := tapo.tdi;
v.shift(0) := r.shift(nsync-1); v.shift(nsync-1) := tapo.shift;
v.asel(0) := r.asel(nsync-1); v.asel(nsync-1) := asel;
v.dsel(0) := r.dsel(nsync-1); v.dsel(nsync-1) := dsel;
v.tdi2 := r.tdi(0);
redge := not r.tck2 and r.tck(0);
vdmai.address := r.addr(31 downto 0); vdmai.wdata := r.data(31 downto 0);
vdmai.start := '0'; vdmai.burst := '0'; vdmai.write := write;
vdmai.busy := '0'; vdmai.irq := '0'; vdmai.size := r.addr(33 downto 32);
vtapi.en := r.asel(0) or r.dsel(0);
if r.asel(0) = '1' then vtapi.tdo := r.addr(0); else vtapi.tdo := r.data(0); end if;
case r.state is
when shft =>
if (r.asel(0) or r.dsel(0)) = '1' then
if r.shift2 = '1' then
if redge = '1' then
if r.asel(0) = '1' then v.addr := r.tdi2 & r.addr(34 downto 1); end if;
if r.dsel(0) = '1' then v.data := r.tdi2 & r.data(32 downto 1); end if;
end if;
elsif r.shift3 = '1' then
if (r.asel(0) and not write) = '1' then v.state := ahb; end if;
if (r.dsel(0) and (write or (not write and seq))) = '1' then -- data register
v.state := ahb;
if (seq and not write) = '1' then
v.addr(ADDBITS-1 downto 2) := r.addr(ADDBITS-1 downto 2) + 1;
end if;
end if;
end if;
end if;
vdmai.size := "00";
when ahb =>
if dmao.active = '1' then
if dmao.ready = '1' then
v.data(31 downto 0) := dmao.rdata;
v.state := shft;
if (write and seq) = '1' then
v.addr(ADDBITS-1 downto 2) := r.addr(ADDBITS-1 downto 2) + 1;
end if;
end if;
else
vdmai.start := '1';
end if;
end case;
if (rst = '0') or (r.trst(0) = '1') then
v.state := shft; v.addr(34) := '0'; v.data(32) := '0';
end if;
rin <= v; dmai <= vdmai; tapi <= vtapi;
end process;
reg : process (clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process;
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: jtagcom
-- File: jtagcom.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: JTAG Debug Interface with AHB master interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.libjtagcom.all;
use gaisler.misc.all;
entity jtagcom is
generic (
isel : integer range 0 to 1 := 0;
nsync : integer range 1 to 2 := 2;
ainst : integer range 0 to 255 := 2;
dinst : integer range 0 to 255 := 3);
port (
rst : in std_ulogic;
clk : in std_ulogic;
tapo : in tap_out_type;
tapi : out tap_in_type;
dmao : in ahb_dma_out_type;
dmai : out ahb_dma_in_type
);
end;
architecture rtl of jtagcom is
constant ADDBITS : integer := 10;
constant NOCMP : boolean := (isel /= 0);
type state_type is (shft, ahb);
type reg_type is record
addr : std_logic_vector(34 downto 0);
data : std_logic_vector(32 downto 0);
state : state_type;
tck : std_logic_vector(nsync-1 downto 0);
tck2 : std_ulogic;
trst : std_logic_vector(nsync-1 downto 0);
tdi : std_logic_vector(nsync-1 downto 0);
shift : std_logic_vector(nsync-1 downto 0);
shift2: std_ulogic;
shift3: std_ulogic;
asel : std_logic_vector(nsync-1 downto 0);
dsel : std_logic_vector(nsync-1 downto 0);
tdi2 : std_ulogic;
end record;
signal r, rin : reg_type;
begin
comb : process (rst, r, tapo, dmao)
variable v : reg_type;
variable redge : std_ulogic;
variable vdmai : ahb_dma_in_type;
variable asel, dsel : std_ulogic;
variable vtapi : tap_in_type;
variable write, seq : std_ulogic;
begin
v := r;
if NOCMP then
asel := tapo.asel; dsel := tapo.dsel;
else
if tapo.inst = conv_std_logic_vector(ainst, 8) then asel := '1'; else asel := '0'; end if;
if tapo.inst = conv_std_logic_vector(dinst, 8) then dsel := '1'; else dsel := '0'; end if;
end if;
write := r.addr(34); seq := r.data(32);
v.tck(0) := r.tck(nsync-1); v.tck(nsync-1) := tapo.tck; v.tck2 := r.tck(0); v.shift2 := r.shift(0); v.shift3 := r.shift2;
v.trst(0) := r.trst(nsync-1); v.trst(nsync-1) := tapo.reset;
v.tdi(0) := r.tdi(nsync-1); v.tdi(nsync-1) := tapo.tdi;
v.shift(0) := r.shift(nsync-1); v.shift(nsync-1) := tapo.shift;
v.asel(0) := r.asel(nsync-1); v.asel(nsync-1) := asel;
v.dsel(0) := r.dsel(nsync-1); v.dsel(nsync-1) := dsel;
v.tdi2 := r.tdi(0);
redge := not r.tck2 and r.tck(0);
vdmai.address := r.addr(31 downto 0); vdmai.wdata := r.data(31 downto 0);
vdmai.start := '0'; vdmai.burst := '0'; vdmai.write := write;
vdmai.busy := '0'; vdmai.irq := '0'; vdmai.size := r.addr(33 downto 32);
vtapi.en := r.asel(0) or r.dsel(0);
if r.asel(0) = '1' then vtapi.tdo := r.addr(0); else vtapi.tdo := r.data(0); end if;
case r.state is
when shft =>
if (r.asel(0) or r.dsel(0)) = '1' then
if r.shift2 = '1' then
if redge = '1' then
if r.asel(0) = '1' then v.addr := r.tdi2 & r.addr(34 downto 1); end if;
if r.dsel(0) = '1' then v.data := r.tdi2 & r.data(32 downto 1); end if;
end if;
elsif r.shift3 = '1' then
if (r.asel(0) and not write) = '1' then v.state := ahb; end if;
if (r.dsel(0) and (write or (not write and seq))) = '1' then -- data register
v.state := ahb;
if (seq and not write) = '1' then
v.addr(ADDBITS-1 downto 2) := r.addr(ADDBITS-1 downto 2) + 1;
end if;
end if;
end if;
end if;
vdmai.size := "00";
when ahb =>
if dmao.active = '1' then
if dmao.ready = '1' then
v.data(31 downto 0) := dmao.rdata;
v.state := shft;
if (write and seq) = '1' then
v.addr(ADDBITS-1 downto 2) := r.addr(ADDBITS-1 downto 2) + 1;
end if;
end if;
else
vdmai.start := '1';
end if;
end case;
if (rst = '0') or (r.trst(0) = '1') then
v.state := shft; v.addr(34) := '0'; v.data(32) := '0';
end if;
rin <= v; dmai <= vdmai; tapi <= vtapi;
end process;
reg : process (clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process;
end;
|
library IEEE;
use IEEE.std_logic_1164.all;
entity pfb_core_snbxfft32 is
port (
ce_1: in std_logic;
clk_1: in std_logic;
en_in: in std_logic;
pol0_in: in std_logic_vector(35 downto 0);
pol1_in: in std_logic_vector(35 downto 0);
sync_in: in std_logic;
en_out: out std_logic;
pol0_out: out std_logic_vector(35 downto 0);
pol1_out: out std_logic_vector(35 downto 0);
specsync_out: out std_logic;
sync_out: out std_logic
);
end pfb_core_snbxfft32;
architecture structural of pfb_core_snbxfft32 is
begin
end structural;
|
------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2006 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.ddrpkg.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
reset : in std_ulogic;
reset_o1 : out std_ulogic;
reset_o2 : out std_ulogic;
clk27 : in std_ulogic;
clk200_p : in std_ulogic;
clk200_n : in std_ulogic;
errorn : out std_ulogic;
-- PROM interface
address : out std_logic_vector(23 downto 0);
data : inout std_logic_vector(7 downto 0);
romsn : out std_ulogic;
oen : out std_ulogic;
writen : out std_ulogic;
-- pragma translate_off
iosn : out std_ulogic;
testdata : inout std_logic_vector(23 downto 0);
-- pragma translate_on
-- DDR2 memory
ddr_clk : out std_logic;
ddr_clkb : out std_logic;
ddr_cke : out std_logic;
ddr_we : out std_ulogic; -- write enable
ddr_ras : out std_ulogic; -- ras
ddr_cas : out std_ulogic; -- cas
ddr_dm : out std_logic_vector(1 downto 0); -- dm
ddr_dqs : inout std_logic_vector(1 downto 0); -- dqs
ddr_dqsn : inout std_logic_vector(1 downto 0); -- dqsn
ddr_ad : out std_logic_vector(12 downto 0); -- address
ddr_ba : out std_logic_vector(2 downto 0); -- bank address
ddr_dq : inout std_logic_vector(15 downto 0); -- data
ddr_odt : out std_logic;
ddr_rzq : inout std_logic;
ddr_zio : inout std_logic;
-- Debug support unit
dsubre : in std_ulogic; -- Debug Unit break (connect to button)
-- AHB Uart
dsurx : in std_ulogic;
dsutx : out std_ulogic;
-- Ethernet signals
etx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(7 downto 0);
erx_dv : in std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
etxd : out std_logic_vector(7 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
emdc : out std_ulogic;
emdio : inout std_logic;
-- SPI flash
-- spi_sel_n : inout std_ulogic;
-- spi_clk : out std_ulogic;
-- spi_mosi : out std_ulogic;
-- Output signals to LEDs
led : out std_logic_vector(2 downto 0)
);
end;
architecture rtl of leon3mp is
signal vcc : std_logic;
signal gnd : std_logic;
signal ddr_clk_fb_out : std_logic;
signal ddr_clk_fb : std_logic;
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal gpti : gptimer_in_type;
signal spii : spi_in_type;
signal spio : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal spmi : spimctrl_in_type;
signal spmo : spimctrl_out_type;
signal lclk, lclk200 : std_ulogic;
signal clkm, rstn, clkml : std_ulogic;
signal tck, tms, tdi, tdo : std_ulogic;
signal rstraw : std_logic;
signal lock : std_logic;
-- RS232 APB Uart
signal rxd1 : std_logic;
signal txd1 : std_logic;
-- Used for connecting input/output signals to the DDR2 controller
signal core_ddr_clk : std_logic_vector(2 downto 0);
signal core_ddr_clkb : std_logic_vector(2 downto 0);
signal core_ddr_cke : std_logic_vector(1 downto 0);
signal core_ddr_csb : std_logic_vector(1 downto 0);
signal core_ddr_ad : std_logic_vector(13 downto 0);
signal core_ddr_odt : std_logic_vector(1 downto 0);
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of lock : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_keep of clkm : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute keep of lock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
constant BOARD_FREQ : integer := 27000; -- CLK input frequency in KHz
constant DDR2_FREQ : integer := 200000; -- DDR2 input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1';
gnd <= '0';
cgi.pllctrl <= "00";
cgi.pllrst <= rstraw;
-- Glitch free reset that can be used for the Eth Phy and flash memory
reset_o1 <= rstn;
reset_o2 <= rstn;
rst0 : rstgen generic map (acthigh => 1)
port map (reset, clkm, lock, rstn, rstraw);
clk27_pad : clkpad generic map (tech => padtech) port map (clk27, lclk);
-- clock generator
clkgen0 : clkgen
generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd, clkm, open, open, open, open, cgi, cgo, open, open, open);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH,
nahbs => 8, devid => XILINX_SP601)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
-- LEON3 processor
leon3gen : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR,
CFG_NCPU-1, CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
error_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
-- LEON3 Debug Support Unit
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsui.enable <= '1';
led(2) <= dsuo.active;
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
-- Debug UART
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
led(0) <= not dui.rxd;
led(1) <= not duo.txd;
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd);
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 5, pindex => 0, paddr => 0,
ram8 => CFG_MCTRL_RAM8BIT, ram16 => CFG_MCTRL_RAM16BIT, rammask => 0)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(5), apbi, apbo(0), wpo, open);
end generate;
memi.brdyn <= '1';
memi.bexcn <= '1';
memi.writen <= '1';
memi.wrn <= "1111";
memi.bwidth <= "00";
mg0 : if (CFG_MCTRL_LEON2 = 0) generate
apbo(0) <= apb_none;
ahbso(5) <= ahbs_none;
roms_pad : outpad generic map (tech => padtech)
port map (romsn, vcc);
memo.bdrive(0) <= '1';
end generate;
mgpads : if (CFG_MCTRL_LEON2 /= 0) generate
addr_pad : outpadv generic map (tech => padtech, width => 24)
port map (address, memo.address(23 downto 0));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
-- pragma translate_off
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
tbdr : iopadv generic map (tech => padtech, width => 24)
port map (testdata(23 downto 0), memo.data(23 downto 0),
memo.bdrive(1), memi.data(23 downto 0));
-- pragma translate_on
end generate;
bdr : iopadv generic map (tech => padtech, width => 8)
port map (data(7 downto 0), memo.data(31 downto 24),
memo.bdrive(0), memi.data(31 downto 24));
----------------------------------------------------------------------
--- DDR2 memory controller ------------------------------------------
----------------------------------------------------------------------
ddr2sp0 : if (CFG_DDR2SP /= 0) generate
clk200_pad : inpad_ds generic map (tech => padtech, voltage => x25v)
port map (clk200_p, clk200_n, lclk200);
ddrc0 : ddr2spa generic map ( fabtech => fabtech, memtech => memtech,
hindex => 4, haddr => 16#400#, hmask => 16#F00#, ioaddr => 1,
pwron => CFG_DDR2SP_INIT, MHz => DDR2_FREQ/1000, clkmul => 5, clkdiv => 8,
TRFC => CFG_DDR2SP_TRFC,
ahbfreq => CPU_FREQ/1000, col => CFG_DDR2SP_COL, Mbyte => CFG_DDR2SP_SIZE,
ddrbits => 16, eightbanks => 1, odten => 0)
port map ( cgo.clklock, rstn, lclk200, clkm, vcc, lock, clkml, clkml, ahbsi, ahbso(4),
core_ddr_clk, core_ddr_clkb, ddr_clk_fb_out, ddr_clk_fb, core_ddr_cke,
core_ddr_csb, ddr_we, ddr_ras, ddr_cas, ddr_dm, ddr_dqs, ddr_dqsn,
core_ddr_ad, ddr_ba, ddr_dq, core_ddr_odt);
ddr_clk <= core_ddr_clk(0);
ddr_clkb <= core_ddr_clkb(0);
ddr_cke <= core_ddr_cke(0);
ddr_ad <= core_ddr_ad(12 downto 0);
ddr_odt <= core_ddr_odt(0);
end generate;
mig_gen : if (CFG_MIG_DDR2 = 1) generate
ddrc : entity work.ahb2mig_sp601 generic map(
hindex => 4, haddr => 16#400#, hmask => 16#F80#,
pindex => 5, paddr => 5)
port map(
mcb3_dram_dq => ddr_dq,
mcb3_dram_a => ddr_ad,
mcb3_dram_ba => ddr_ba,
mcb3_dram_ras_n => ddr_ras,
mcb3_dram_cas_n => ddr_cas,
mcb3_dram_we_n => ddr_we,
mcb3_dram_odt => ddr_odt,
mcb3_dram_cke => ddr_cke,
mcb3_dram_dm => ddr_dm(0),
mcb3_dram_udqs => ddr_dqs(1),
mcb3_dram_udqs_n => ddr_dqsn(1),
mcb3_rzq => ddr_rzq,
mcb3_zio => ddr_zio,
mcb3_dram_udm => ddr_dm(1),
mcb3_dram_dqs => ddr_dqs(0),
mcb3_dram_dqs_n => ddr_dqsn(0),
mcb3_dram_ck => ddr_clk,
mcb3_dram_ck_n => ddr_clkb,
ahbsi => ahbsi,
ahbso => ahbso(4),
apbi => apbi,
apbo => apbo(5),
calib_done => lock,
rst_n_syn => rstn,
rst_n_async => rstraw,
clk_amba => clkm,
clk_mem_n => clk200_n,
clk_mem_p => clk200_p,
test_error => open
);
end generate;
noddr : if (CFG_DDR2SP+CFG_MIG_DDR2) = 0 generate lock <= '1'; end generate;
----------------------------------------------------------------------
--- SPI Memory Controller--------------------------------------------
----------------------------------------------------------------------
-- spimc: if CFG_SPICTRL_ENABLE = 0 and CFG_SPIMCTRL = 1 generate
-- spimctrl0 : spimctrl -- SPI Memory Controller
-- generic map (hindex => 7, hirq => 11, faddr => 16#e00#, fmask => 16#ff8#,
-- ioaddr => 16#002#, iomask => 16#fff#,
-- spliten => CFG_SPLIT, oepol => 0,
-- sdcard => CFG_SPIMCTRL_SDCARD,
-- readcmd => CFG_SPIMCTRL_READCMD,
-- dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
-- dualoutput => CFG_SPIMCTRL_DUALOUTPUT,
-- scaler => CFG_SPIMCTRL_SCALER,
-- altscaler => CFG_SPIMCTRL_ASCALER,
-- pwrupcnt => CFG_SPIMCTRL_PWRUPCNT)
-- port map (rstn, clkm, ahbsi, ahbso(7), spmi, spmo);
--
-- -- MISO is shared with Flash data 0
-- spmi.miso <= memi.data(24);
-- mosi_pad : outpad generic map (tech => padtech)
-- port map (spi_mosi, spmo.mosi);
-- sck_pad : outpad generic map (tech => padtech)
-- port map (spi_clk, spmo.sck);
-- slvsel0_pad : odpad generic map (tech => padtech)
-- port map (spi_sel_n, spmo.csn);
-- end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
-- APB Bridge
apb0 : apbctrl
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
-- Interrupt controller
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
-- Time Unit
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW,
ntimers => CFG_GPT_NTIM, nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop;
gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
-- GPIO Unit
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate
grgpio0: grgpio
generic map(pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 12)
port map(rstn, clkm, apbi, apbo(11), gpioi, gpioo);
end generate;
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1;
u1i.ctsn <= '0';
u1i.extclk <= '0';
txd1 <= u1o.txd;
serrx_pad : inpad generic map (tech => padtech) port map (dsurx, rxd1);
sertx_pad : outpad generic map (tech => padtech) port map (dsutx, txd1);
led(0) <= not rxd1;
led(1) <= not txd1;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
-- spic: if CFG_SPICTRL_ENABLE = 1 generate -- SPI controller
-- spi1 : spictrl
-- generic map (pindex => 7, paddr => 7, pmask => 16#fff#, pirq => 11,
-- fdepth => CFG_SPICTRL_FIFO, slvselen => CFG_SPICTRL_SLVREG,
-- slvselsz => CFG_SPICTRL_SLVS, odmode => 0)
-- port map (rstn, clkm, apbi, apbo(7), spii, spio, slvsel);
-- spii.spisel <= '1'; -- Master only
-- -- MISO is shared with Flash data 0
-- spii.miso <= memi.data(24);
-- mosi_pad : outpad generic map (tech => padtech)
-- port map (spi_mosi, spio.mosi);
-- sck_pad : outpad generic map (tech => padtech)
-- port map (spi_clk, spio.sck);
-- slvsel_pad : odpad generic map (tech => padtech)
-- port map (spi_sel_n, slvsel(0));
-- end generate spic;
nospi: if CFG_SPICTRL_ENABLE = 0 and CFG_SPIMCTRL = 0 generate
apbo(7) <= apb_none;
-- mosi_pad : outpad generic map (tech => padtech)
-- port map (spi_mosi, gnd);
-- sck_pad : outpad generic map (tech => padtech)
-- port map (spi_clk, gnd);
-- slvsel_pad : odpad generic map (tech => padtech)
-- port map (spi_sel_n, vcc);
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm
generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 15, paddr => 15, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 7,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G)
port map(rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
apbi => apbi, apbo => apbo(15), ethi => ethi, etho => etho);
end generate;
ethpads : if (CFG_GRETH = 1) generate -- eth pads
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 8)
port map (erxd, ethi.rxd(7 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 8)
port map (etxd, etho.txd(7 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram
generic map (hindex => 3, haddr => CFG_AHBRADDR, tech => CFG_MEMTECH,
kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+1) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Demonstration design for Xilinx Spartan6 SP601 board",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end rtl;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-- =============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Package: Global configuration settings.
--
-- Description:
-- -------------------------------------
-- This file evaluates the settings declared in the project specific package my_config.
-- See also template file my_config.vhdl.template.
--
-- License:
-- =============================================================================
-- Copyright 2007-2016 Technische Universitaet Dresden - Germany,
-- Chair of VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library PoC;
use PoC.utils.all;
package config_private is
-- TODO:
-- ===========================================================================
subtype T_BOARD_STRING is string(1 to 16);
subtype T_BOARD_CONFIG_STRING is string(1 to 64);
subtype T_DEVICE_STRING is string(1 to 32);
-- Data structures to describe UART / RS232
type T_BOARD_UART_DESC is record
IsDTE : boolean; -- Data terminal Equipment (e.g. PC, Printer)
FlowControl : T_BOARD_CONFIG_STRING; -- (NONE, SW, HW_CTS_RTS, HW_RTR_RTS)
BaudRate : T_BOARD_CONFIG_STRING; -- e.g. "115.2 kBd"
BaudRate_Max : T_BOARD_CONFIG_STRING;
end record;
-- Data structures to describe Ethernet
type T_BOARD_ETHERNET_DESC is record
IPStyle : T_BOARD_CONFIG_STRING;
RS_DataInterface : T_BOARD_CONFIG_STRING;
PHY_Device : T_BOARD_CONFIG_STRING;
PHY_DeviceAddress : std_logic_vector(7 downto 0);
PHY_DataInterface : T_BOARD_CONFIG_STRING;
PHY_ManagementInterface : T_BOARD_CONFIG_STRING;
end record;
subtype T_BOARD_ETHERNET_DESC_INDEX is natural range 0 to 7;
type T_BOARD_ETHERNET_DESC_VECTOR is array(natural range <>) of T_BOARD_ETHERNET_DESC;
-- Data structures to describe a board layout
type T_BOARD_INFO is record
BoardName : T_BOARD_CONFIG_STRING;
FPGADevice : T_BOARD_CONFIG_STRING;
UART : T_BOARD_UART_DESC;
Ethernet : T_BOARD_ETHERNET_DESC_VECTOR(T_BOARD_ETHERNET_DESC_INDEX);
EthernetCount : T_BOARD_ETHERNET_DESC_INDEX;
end record;
type T_BOARD_INFO_VECTOR is array (natural range <>) of T_BOARD_INFO;
constant C_POC_NUL : character;
constant C_BOARD_STRING_EMPTY : T_BOARD_STRING;
constant C_BOARD_CONFIG_STRING_EMPTY : T_BOARD_CONFIG_STRING;
constant C_DEVICE_STRING_EMPTY : T_DEVICE_STRING;
constant C_BOARD_INFO_LIST : T_BOARD_INFO_VECTOR;
function conf(str : string) return T_BOARD_CONFIG_STRING;
end package;
package body config_private is
constant C_POC_NUL : character := '~';
constant C_BOARD_STRING_EMPTY : T_BOARD_STRING := (others => C_POC_NUL);
constant C_BOARD_CONFIG_STRING_EMPTY : T_BOARD_CONFIG_STRING := (others => C_POC_NUL);
constant C_DEVICE_STRING_EMPTY : T_DEVICE_STRING := (others => C_POC_NUL);
function conf(str : string) return T_BOARD_CONFIG_STRING is
constant ConstNUL : string(1 to 1) := (others => C_POC_NUL);
variable Result : string(1 to T_BOARD_CONFIG_STRING'length);
begin
Result := (others => C_POC_NUL);
if (str'length > 0) then
Result(1 to bound(T_BOARD_CONFIG_STRING'length, 1, str'length)) := ite((str'length > 0), str(1 to imin(T_BOARD_CONFIG_STRING'length, str'length)), ConstNUL);
end if;
return Result;
end function;
constant C_BOARD_ETHERNET_DESC_EMPTY : T_BOARD_ETHERNET_DESC := (
IPStyle => C_BOARD_CONFIG_STRING_EMPTY,
RS_DataInterface => C_BOARD_CONFIG_STRING_EMPTY,
PHY_Device => C_BOARD_CONFIG_STRING_EMPTY,
PHY_DeviceAddress => x"00",
PHY_DataInterface => C_BOARD_CONFIG_STRING_EMPTY,
PHY_ManagementInterface => C_BOARD_CONFIG_STRING_EMPTY
);
-- predefined UART descriptions
function brd_CreateUART(IsDTE : boolean; FlowControl : string; BaudRate : string; BaudRate_Max : string := "") return T_BOARD_UART_DESC is
variable Result : T_BOARD_UART_DESC;
begin
Result.IsDTE := IsDTE;
Result.FlowControl := conf(FlowControl);
Result.BaudRate := conf(BaudRate);
Result.BaudRate_Max := ite((BaudRate_Max = ""), conf(BaudRate), conf(BaudRate_Max));
return Result;
end function;
-- IsDTE FlowControl BaudRate
constant C_BOARD_UART_EMPTY : T_BOARD_UART_DESC := brd_CreateUART(TRUE, "NONE", "0 Bd");
constant C_BOARD_UART_DTE_115200_NONE : T_BOARD_UART_DESC := brd_CreateUART(TRUE, "NONE", "115.2 kBd");
constant C_BOARD_UART_DCE_115200_NONE : T_BOARD_UART_DESC := brd_CreateUART(FALSE, "NONE", "115.2 kBd");
constant C_BOARD_UART_DCE_115200_HWCTS : T_BOARD_UART_DESC := brd_CreateUART(FALSE, "HW_CTS_RTS", "115.2 kBd");
constant C_BOARD_UART_DCE_460800_NONE : T_BOARD_UART_DESC := brd_CreateUART(FALSE, "NONE", "460.8 kBd");
constant C_BOARD_UART_DTE_921600_NONE : T_BOARD_UART_DESC := brd_CreateUART(FALSE, "NONE", "921.6 kBd");
function brd_CreateEthernet(IPStyle : string; RS_DataInt : string; PHY_Device : string; PHY_DevAddress : std_logic_vector(7 downto 0); PHY_DataInt : string; PHY_MgntInt : string) return T_BOARD_ETHERNET_DESC is
variable Result : T_BOARD_ETHERNET_DESC;
begin
Result.IPStyle := conf(IPStyle);
Result.RS_DataInterface := conf(RS_DataInt);
Result.PHY_Device := conf(PHY_Device);
Result.PHY_DeviceAddress := PHY_DevAddress;
Result.PHY_DataInterface := conf(PHY_DataInt);
Result.PHY_ManagementInterface := conf(PHY_MgntInt);
return Result;
end function;
constant C_BOARD_ETH_EMPTY : T_BOARD_ETHERNET_DESC := brd_CreateEthernet("", "", "", x"00", "", "");
constant C_BOARD_ETH_SOFT_GMII_88E1111 : T_BOARD_ETHERNET_DESC := brd_CreateEthernet("SOFT", "GMII", "MARVEL_88E1111", x"07", "GMII", "MDIO");
constant C_BOARD_ETH_HARD_GMII_88E1111 : T_BOARD_ETHERNET_DESC := brd_CreateEthernet("HARD", "GMII", "MARVEL_88E1111", x"07", "GMII", "MDIO");
constant C_BOARD_ETH_SOFT_SGMII_88E1111 : T_BOARD_ETHERNET_DESC := brd_CreateEthernet("SOFT", "GMII", "MARVEL_88E1111", x"07", "SGMII", "MDIO_OVER_IIC");
constant C_BOARD_ETH_NONE : T_BOARD_ETHERNET_DESC_VECTOR(T_BOARD_ETHERNET_DESC_INDEX) := (others => C_BOARD_ETH_EMPTY);
-- Board Descriptions
-- ===========================================================================
constant C_BOARD_INFO_LIST : T_BOARD_INFO_VECTOR := (
(
BoardName => conf("GENERIC"),
FPGADevice => conf("GENERIC"), -- GENERIC
UART => C_BOARD_UART_DTE_921600_NONE,
Ethernet => (
0 => C_BOARD_ETH_HARD_GMII_88E1111,
others => C_BOARD_ETH_EMPTY
),
EthernetCount => 1
),
-- Altera boards
-- =========================================================================
(
BoardName => conf("DE0"),
FPGADevice => conf("EP3C16F484"), -- EP3C16F484
UART => C_BOARD_UART_EMPTY,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
),(
BoardName => conf("S2GXAV"),
FPGADevice => conf("EP2SGX90FF1508C3"), -- EP2SGX90FF1508C3
UART => C_BOARD_UART_EMPTY,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
),(
BoardName => conf("DE4"),
FPGADevice => conf("EP4SGX230KF40C2"), -- EP4SGX230KF40C2
UART => C_BOARD_UART_DCE_460800_NONE,
Ethernet => (
0 => brd_CreateEthernet("SOFT", "GMII", "MARVEL_88E1111", x"00", "RGMII", "MDIO"),
1 => brd_CreateEthernet("SOFT", "GMII", "MARVEL_88E1111", x"01", "RGMII", "MDIO"),
2 => brd_CreateEthernet("SOFT", "GMII", "MARVEL_88E1111", x"02", "RGMII", "MDIO"),
3 => brd_CreateEthernet("SOFT", "GMII", "MARVEL_88E1111", x"03", "RGMII", "MDIO"),
others => C_BOARD_ETH_EMPTY
),
EthernetCount => 4
),(
BoardName => conf("DE5"),
FPGADevice => conf("EP5SGXEA7N2F45C2"), -- EP5SGXEA7N2F45C2
UART => C_BOARD_UART_EMPTY,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
),
-- Lattice boards
-- =========================================================================
(
BoardName => conf("ECP5 Versa"),
FPGADevice => conf("LFE5UM-45F-6BG381C"), -- LFE5UM-45F-6BG381C
UART => C_BOARD_UART_EMPTY,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
),
-- Xilinx boards
-- =========================================================================
(
BoardName => conf("S3SK200"),
FPGADevice => conf("XC3S200-4FT256"), -- XC3S200-4FT256
UART => C_BOARD_UART_EMPTY,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
),(
BoardName => conf("S3SK1000"),
FPGADevice => conf("XC3S1000-4FT256"), -- XC2S1000-4FT256
UART => C_BOARD_UART_EMPTY,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
),(
BoardName => conf("S3ESK500"),
FPGADevice => conf("XC3S500E-4FG320"), -- XC3S500E-4FG320
UART => C_BOARD_UART_EMPTY,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
),(
BoardName => conf("S3ESK1600"),
FPGADevice => conf("XC3S1600E-4FG320"), -- XC3S1600E-4FG320
UART => C_BOARD_UART_EMPTY,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
),(
BoardName => conf("ATLYS"),
FPGADevice => conf("XC6SLX45-3CSG324"), -- XC6SLX45-3CSG324
UART => C_BOARD_UART_DCE_460800_NONE,
Ethernet => (
0 => C_BOARD_ETH_HARD_GMII_88E1111,
others => C_BOARD_ETH_EMPTY),
EthernetCount => 1
),(
BoardName => conf("ZC706"),
FPGADevice => conf("XC7Z045-2FFG900"), -- XC7Z045-2FFG900C
UART => C_BOARD_UART_DTE_921600_NONE,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
),(
BoardName => conf("ZedBoard"),
FPGADevice => conf("XC7Z020-1CLG484"), -- XC7Z020-1CLG484
UART => C_BOARD_UART_DTE_921600_NONE,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
),(
BoardName => conf("AC701"),
FPGADevice => conf("XC7A200T-2FBG676C"), -- XC7A200T-2FBG676C
UART => C_BOARD_UART_DTE_921600_NONE,
Ethernet => (
0 => C_BOARD_ETH_SOFT_GMII_88E1111,
others => C_BOARD_ETH_EMPTY),
EthernetCount => 1
),(
BoardName => conf("KC705"),
FPGADevice => conf("XC7K325T-2FFG900C"), -- XC7K325T-2FFG900C
UART => C_BOARD_UART_DTE_921600_NONE,
Ethernet => (
0 => C_BOARD_ETH_SOFT_GMII_88E1111,
others => C_BOARD_ETH_EMPTY),
EthernetCount => 1
),(
BoardName => conf("ML505"),
FPGADevice => conf("XC5VLX50T-1FF1136"), -- XC5VLX50T-1FF1136
UART => C_BOARD_UART_DCE_115200_NONE,
Ethernet => (
0 => C_BOARD_ETH_HARD_GMII_88E1111,
others => C_BOARD_ETH_EMPTY),
EthernetCount => 1
),(
BoardName => conf("ML506"),
FPGADevice => conf("XC5VSX50T-1FFG1136"), -- XC5VSX50T-1FFG1136
UART => C_BOARD_UART_DCE_115200_NONE,
Ethernet => (
0 => C_BOARD_ETH_HARD_GMII_88E1111,
others => C_BOARD_ETH_EMPTY),
EthernetCount => 1
),(
BoardName => conf("ML507"),
FPGADevice => conf("XC5VFX70T-1FFG1136"), -- XC5VFX70T-1FFG1136
UART => C_BOARD_UART_DCE_115200_NONE,
Ethernet => (
0 => C_BOARD_ETH_HARD_GMII_88E1111,
others => C_BOARD_ETH_EMPTY),
EthernetCount => 1
),(
BoardName => conf("XUPV5"),
FPGADevice => conf("XC5VLX110T-1FF1136"), -- XC5VLX110T-1FF1136
UART => C_BOARD_UART_DCE_115200_NONE,
Ethernet => (
0 => C_BOARD_ETH_HARD_GMII_88E1111,
others => C_BOARD_ETH_EMPTY),
EthernetCount => 1
),(
BoardName => conf("ML605"),
FPGADevice => conf("XC6VLX240T-1FF1156"), -- XC6VLX240T-1FF1156
UART => C_BOARD_UART_EMPTY,
Ethernet => (
0 => C_BOARD_ETH_HARD_GMII_88E1111,
others => C_BOARD_ETH_EMPTY),
EthernetCount => 1
),(
BoardName => conf("VC707"),
FPGADevice => conf("XC7VX485T-2FFG1761C"), -- XC7VX485T-2FFG1761C
UART => C_BOARD_UART_DTE_921600_NONE,
Ethernet => (
0 => C_BOARD_ETH_SOFT_SGMII_88E1111,
others => C_BOARD_ETH_EMPTY),
EthernetCount => 1
),(
BoardName => conf("VC709"),
FPGADevice => conf("XC7VX690T-2FFG1761C"), -- XC7VX690T-2FFG1761C
UART => C_BOARD_UART_DTE_921600_NONE,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
),
-- Custom Board (MUST BE LAST ONE)
-- =========================================================================
(
BoardName => conf("Custom"),
FPGADevice => conf("Device is unknown for a custom board"),
UART => C_BOARD_UART_EMPTY,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
)
);
end package body;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library PoC;
use PoC.my_config.all;
use PoC.my_project.all;
use PoC.config_private.all;
use PoC.utils.all;
package config is
constant PROJECT_DIR : string := MY_PROJECT_DIR;
constant OPERATING_SYSTEM : string := MY_OPERATING_SYSTEM;
constant POC_VERBOSE : boolean := MY_VERBOSE;
-- List of known FPGA / Chip vendors
-- ---------------------------------------------------------------------------
type T_VENDOR is (
VENDOR_UNKNOWN,
VENDOR_GENERIC,
VENDOR_ALTERA,
VENDOR_LATTICE,
VENDOR_XILINX
);
-- List of known synthesis tool chains
-- ---------------------------------------------------------------------------
type T_SYNTHESIS_TOOL is (
SYNTHESIS_TOOL_UNKNOWN,
SYNTHESIS_TOOL_GENERIC,
SYNTHESIS_TOOL_ALTERA_QUARTUS2,
SYNTHESIS_TOOL_LATTICE_LSE,
SYNTHESIS_TOOL_SYNOPSIS,
SYNTHESIS_TOOL_XILINX_XST,
SYNTHESIS_TOOL_XILINX_VIVADO
);
-- List of known device families
-- ---------------------------------------------------------------------------
type T_DEVICE_FAMILY is (
DEVICE_FAMILY_UNKNOWN,
DEVICE_FAMILY_GENERIC,
-- Altera
DEVICE_FAMILY_ARRIA,
DEVICE_FAMILY_CYCLONE,
DEVICE_FAMILY_STRATIX,
-- Lattice
DEVICE_FAMILY_ICE,
DEVICE_FAMILY_MACHXO,
DEVICE_FAMILY_ECP,
-- Xilinx
DEVICE_FAMILY_SPARTAN,
DEVICE_FAMILY_ZYNQ,
DEVICE_FAMILY_ARTIX,
DEVICE_FAMILY_KINTEX,
DEVICE_FAMILY_VIRTEX
);
type T_DEVICE_SERIES is (
DEVICE_SERIES_UNKNOWN,
DEVICE_SERIES_GENERIC,
-- Xilinx FPGA series
DEVICE_SERIES_7_SERIES,
DEVICE_SERIES_ULTRASCALE,
DEVICE_SERIES_ULTRASCALE_PLUS
);
-- List of known devices
-- ---------------------------------------------------------------------------
type T_DEVICE is (
DEVICE_UNKNOWN,
DEVICE_GENERIC,
-- Altera
DEVICE_MAX2, DEVICE_MAX10, -- Altera.Max
DEVICE_ARRIA1, DEVICE_ARRIA2, DEVICE_ARRIA5, DEVICE_ARRIA10, -- Altera.Arria
DEVICE_CYCLONE1, DEVICE_CYCLONE2, DEVICE_CYCLONE3, DEVICE_CYCLONE4, -- Altera.Cyclone
DEVICE_CYCLONE5, --
DEVICE_STRATIX1, DEVICE_STRATIX2, DEVICE_STRATIX3, DEVICE_STRATIX4, -- Altera.Stratix
DEVICE_STRATIX5, DEVICE_STRATIX10, --
-- Lattice
DEVICE_ICE40, DEVICE_ICE65, DEVICE_ICE5, -- Lattice.iCE
DEVICE_MACHXO, DEVICE_MACHXO2, -- Lattice.MachXO
DEVICE_ECP3, DEVICE_ECP4, DEVICE_ECP5, -- Lattice.ECP
-- Xilinx
DEVICE_SPARTAN3, DEVICE_SPARTAN6, -- Xilinx.Spartan
DEVICE_ZYNQ7, DEVICE_ZYNQ_ULTRA_PLUS, -- Xilinx.Zynq
DEVICE_ARTIX7, -- Xilinx.Artix
DEVICE_KINTEX7, DEVICE_KINTEX_ULTRA, DEVICE_KINTEX_ULTRA_PLUS, -- Xilinx.Kintex
DEVICE_VIRTEX4, DEVICE_VIRTEX5, DEVICE_VIRTEX6, DEVICE_VIRTEX7, -- Xilinx.Virtex
DEVICE_VIRTEX_ULTRA, DEVICE_VIRTEX_ULTRA_PLUS --
);
-- List of known device subtypes
-- ---------------------------------------------------------------------------
type T_DEVICE_SUBTYPE is (
DEVICE_SUBTYPE_NONE,
DEVICE_SUBTYPE_GENERIC,
-- Altera
DEVICE_SUBTYPE_E,
DEVICE_SUBTYPE_GS,
DEVICE_SUBTYPE_GX,
DEVICE_SUBTYPE_GT,
-- Lattice
DEVICE_SUBTYPE_U,
DEVICE_SUBTYPE_UM,
-- Xilinx
DEVICE_SUBTYPE_X,
DEVICE_SUBTYPE_T,
DEVICE_SUBTYPE_XT,
DEVICE_SUBTYPE_HT,
DEVICE_SUBTYPE_LX,
DEVICE_SUBTYPE_SXT,
DEVICE_SUBTYPE_LXT,
DEVICE_SUBTYPE_TXT,
DEVICE_SUBTYPE_FXT,
DEVICE_SUBTYPE_CXT,
DEVICE_SUBTYPE_HXT
);
-- List of known transceiver (sub-)types
-- ---------------------------------------------------------------------------
type T_TRANSCEIVER is (
TRANSCEIVER_NONE,
TRANSCEIVER_GENERIC,
-- TODO: add more? Altera transceivers
-- Altera transceivers
TRANSCEIVER_GXB, -- Altera GXB transceiver
--Lattice transceivers
TRANSCEIVER_MGT, -- Lattice transceiver
-- Xilinx transceivers
TRANSCEIVER_GTP_DUAL, TRANSCEIVER_GTPE1, TRANSCEIVER_GTPE2, -- Xilinx GTP transceivers
TRANSCEIVER_GTX, TRANSCEIVER_GTXE1, TRANSCEIVER_GTXE2, -- Xilinx GTX transceivers
TRANSCEIVER_GTH, TRANSCEIVER_GTHE1, TRANSCEIVER_GTHE2, -- Xilinx GTH transceivers
TRANSCEIVER_GTZ, -- Xilinx GTZ transceivers
TRANSCEIVER_GTY -- Xilinx GTY transceivers
);
-- Properties of an FPGA architecture
-- ===========================================================================
type T_DEVICE_INFO is record
Vendor : T_VENDOR;
Device : T_DEVICE;
DevFamily : T_DEVICE_FAMILY;
DevGeneration : natural;
DevNumber : natural;
DevSubType : T_DEVICE_SUBTYPE;
DevSeries : T_DEVICE_SERIES;
TransceiverType : T_TRANSCEIVER;
LUT_FanIn : positive;
end record;
-- Functions extracting board and PCB properties from "MY_BOARD"
-- which is declared in package "my_config".
-- ===========================================================================
function BOARD(BoardConfig : string := C_BOARD_STRING_EMPTY) return natural;
function BOARD_INFO(BoardConfig : string := C_BOARD_STRING_EMPTY) return T_BOARD_INFO;
function BOARD_NAME(BoardConfig : string := C_BOARD_STRING_EMPTY) return string;
function BOARD_DEVICE(BoardConfig : string := C_BOARD_STRING_EMPTY) return string;
function BOARD_UART_BAUDRATE(BoardConfig : string := C_BOARD_STRING_EMPTY) return string;
-- Functions extracting device and architecture properties from "MY_DEVICE"
-- which is declared in package "my_config".
-- ===========================================================================
function VENDOR(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_VENDOR;
function SYNTHESIS_TOOL(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_SYNTHESIS_TOOL;
function DEVICE(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE;
function DEVICE_FAMILY(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_FAMILY;
function DEVICE_SUBTYPE(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_SUBTYPE;
function DEVICE_SERIES(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_SERIES;
function DEVICE_GENERATION(DeviceString : string := C_DEVICE_STRING_EMPTY) return natural;
function DEVICE_NUMBER(DeviceString : string := C_DEVICE_STRING_EMPTY) return natural;
function TRANSCEIVER_TYPE(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_TRANSCEIVER;
function LUT_FANIN(DeviceString : string := C_DEVICE_STRING_EMPTY) return positive;
function DEVICE_INFO(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_INFO;
-- Convert T_DEVICE to string representation as required by "altera_mf" library
-- ===========================================================================
function getAlteraDeviceName (device : T_DEVICE) return string;
-- force FSM to predefined encoding in debug mode
-- ===========================================================================
function getFSMEncoding_gray(debug : boolean) return string;
end package;
package body config is
-- inlined function from PoC.utils, to break dependency
-- ===========================================================================
function ite(cond : boolean; value1 : string; value2 : string) return string is begin
if cond then return value1; else return value2; end if;
end function;
-- chr_is* function
function chr_isDigit(chr : character) return boolean is
begin
return ((character'pos('0') <= CHARACTER'pos(chr)) and (character'pos(chr) <= CHARACTER'pos('9')));
end function;
function chr_isAlpha(chr : character) return boolean is
begin
return (((character'pos('a') <= CHARACTER'pos(chr)) and (character'pos(chr) <= CHARACTER'pos('z'))) or
((character'pos('A') <= CHARACTER'pos(chr)) and (character'pos(chr) <= CHARACTER'pos('Z'))));
end function;
function str_length(str : string) return natural is
begin
for i in str'range loop
if str(i) = C_POC_NUL then
return i - str'low;
end if;
end loop;
return str'length;
end function;
function str_trim(str : string) return string is
begin
for i in str'range loop
if str(i) = C_POC_NUL then
return str(str'low to i-1);
end if;
end loop;
return str;
end function;
function str_imatch(str1 : string; str2 : string) return boolean is
constant len : natural := imin(str1'length, str2'length);
variable chr1 : character;
variable chr2 : character;
begin
-- if both strings are empty
if ((str1'length = 0 ) and (str2'length = 0)) then return TRUE; end if;
-- compare char by char
for i in 0 to len-1 loop
chr1 := str1(str1'low + i);
chr2 := str2(str2'low + i);
if (character'pos('A') <= CHARACTER'pos(chr1)) and (character'pos(chr1) <= CHARACTER'pos('Z')) then
chr1 := character'val(CHARACTER'pos(chr1) - character'pos('A') + CHARACTER'pos('a'));
end if;
if (character'pos('A') <= CHARACTER'pos(chr2)) and (character'pos(chr2) <= CHARACTER'pos('Z')) then
chr2 := character'val(CHARACTER'pos(chr2) - character'pos('A') + CHARACTER'pos('a'));
end if;
if chr1 /= chr2 then
return FALSE;
elsif (chr1 = C_POC_NUL) xor (chr2 = C_POC_NUL) then
return FALSE;
elsif (chr1 = C_POC_NUL) and (chr2 = C_POC_NUL) then
return TRUE;
end if;
end loop;
-- check special cases,
if ((str1'length = len) and (str2'length = len)) then -- both strings are fully consumed and equal
return TRUE;
elsif (str1'length > len) then
return (str1(str1'low + len) = C_POC_NUL); -- str1 is longer, but str_length equals len
else
return (str2(str2'low + len) = C_POC_NUL); -- str2 is longer, but str_length equals len
end if;
end function;
function str_find(str : string; pattern : string; start : natural := 0) return boolean is
begin
for i in imax(str'low, start) to (str'high - pattern'length + 1) loop
exit when (str(i) = C_POC_NUL);
if (str(i to i + pattern'length - 1) = pattern) then
return TRUE;
end if;
end loop;
return FALSE;
end function;
-- private functions required by board description
-- ModelSim requires that this functions is defined before it is used below.
-- ===========================================================================
function getLocalDeviceString(DeviceString : string) return string is
constant ConstNUL : string(1 to 1) := (others => C_POC_NUL);
constant MY_DEVICE_STR : string := BOARD_DEVICE;
variable Result : string(1 to T_DEVICE_STRING'length);
begin
Result := (others => C_POC_NUL);
-- report DeviceString for debugging
if POC_VERBOSE then
report "getLocalDeviceString: DeviceString='" & str_trim(DeviceString) & "' MY_DEVICE='" & str_trim(MY_DEVICE) & "' MY_DEVICE_STR='" & str_trim(MY_DEVICE_STR) & "'" severity NOTE;
end if;
-- if DeviceString is populated
if (str_length(DeviceString) /= 0) and not str_imatch(DeviceString, "None") then
Result(1 to bound(T_DEVICE_STRING'length, 1, DeviceString'length)) := ite((DeviceString'length > 0), DeviceString(1 to imin(T_DEVICE_STRING'length, DeviceString'length)), ConstNUL);
-- if MY_DEVICE is set, prefer it
elsif (str_length(MY_DEVICE) /= 0) and not str_imatch(MY_DEVICE, "None") then
Result(1 to bound(T_DEVICE_STRING'length, 1, MY_DEVICE'length)) := ite((MY_DEVICE'length > 0), MY_DEVICE(1 to imin(T_DEVICE_STRING'length, MY_DEVICE'length)), ConstNUL);
-- otherwise use MY_BOARD
else
Result(1 to bound(T_DEVICE_STRING'length, 1, MY_DEVICE_STR'length)) := ite((MY_DEVICE_STR'length > 0), MY_DEVICE_STR(1 to imin(T_DEVICE_STRING'length, MY_DEVICE_STR'length)), ConstNUL);
end if;
return Result;
end function;
function extractFirstNumber(str : string) return natural is
variable low : integer;
variable high : integer;
variable Result : natural;
variable Digit : integer;
begin
low := -1;
high := -1;
for i in str'low to str'high loop
if chr_isDigit(str(i)) then
low := i;
exit;
end if;
end loop;
-- abort if no digit can be found
if low = -1 then return 0; end if;
for i in (low + 1) to str'high loop
if chr_isAlpha(str(i)) then
high := i - 1;
exit;
end if;
end loop;
if high = -1 then return 0; end if;
-- return INTEGER'value(str(low to high)); -- 'value(...) is not supported by Vivado Synth 2014.1
-- convert substring to a number
for i in low to high loop
if not chr_isDigit(str(i)) then
return 0;
end if;
Result := (Result * 10) + (character'pos(str(i)) - character'pos('0'));
end loop;
return Result;
end function;
-- Public functions
-- ===========================================================================
-- TODO: comment
function BOARD(BoardConfig : string := C_BOARD_STRING_EMPTY) return natural is
constant MY_BRD : T_BOARD_CONFIG_STRING := ite((BoardConfig /= C_BOARD_STRING_EMPTY), conf(BoardConfig), conf(MY_BOARD));
constant BOARD_NAME : string := str_trim(MY_BRD);
begin
if POC_VERBOSE then report "PoC configuration: Used board is '" & BOARD_NAME & "'" severity NOTE; end if;
for i in C_BOARD_INFO_LIST'range loop
if str_imatch(BOARD_NAME, C_BOARD_INFO_LIST(i).BoardName) then
return i;
end if;
end loop;
report "Unknown board name in MY_BOARD = " & MY_BRD & "." severity failure;
return C_BOARD_INFO_LIST'high;
end function;
function BOARD_INFO(BoardConfig : string := C_BOARD_STRING_EMPTY) return T_BOARD_INFO is
constant BRD : natural := BOARD(BoardConfig);
begin
return C_BOARD_INFO_LIST(BRD);
end function;
-- TODO: comment
function BOARD_NAME(BoardConfig : string := C_BOARD_STRING_EMPTY) return string is
constant BRD : natural := BOARD(BoardConfig);
begin
return str_trim(C_BOARD_INFO_LIST(BRD).BoardName);
end function;
-- TODO: comment
function BOARD_DEVICE(BoardConfig : string := C_BOARD_STRING_EMPTY) return string is
constant BRD : natural := BOARD(BoardConfig);
begin
return str_trim(C_BOARD_INFO_LIST(BRD).FPGADevice);
end function;
function BOARD_UART_BAUDRATE(BoardConfig : string := C_BOARD_STRING_EMPTY) return string is
constant BRD : natural := BOARD(BoardConfig);
begin
return str_trim(C_BOARD_INFO_LIST(BRD).UART.BaudRate);
end function;
-- purpose: extract vendor from MY_DEVICE
function VENDOR(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_VENDOR is
constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString);
constant VEN_STR2 : string(1 to 2) := MY_DEV(1 to 2); -- TODO: test if alias declarations also work out on all platforms
constant VEN_STR3 : string(1 to 3) := MY_DEV(1 to 3); -- TODO: test if alias declarations also work out on all platforms
begin
case VEN_STR2 is
when "GE" => return VENDOR_GENERIC;
when "EP" => return VENDOR_ALTERA;
when "XC" => return VENDOR_XILINX;
when others => null;
end case;
case VEN_STR3 is
when "iCE" => return VENDOR_LATTICE; -- iCE devices
when "LCM" => return VENDOR_LATTICE; -- MachXO device
when "LFE" => return VENDOR_LATTICE; -- ECP devices
when others => report "Unknown vendor in MY_DEVICE = '" & MY_DEV & "'" severity failure;
return VENDOR_UNKNOWN;
end case;
end function;
function SYNTHESIS_TOOL(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_SYNTHESIS_TOOL is
constant VEN : T_VENDOR := VENDOR(DeviceString);
begin
case VEN is
when VENDOR_GENERIC =>
return SYNTHESIS_TOOL_GENERIC;
when VENDOR_ALTERA =>
return SYNTHESIS_TOOL_ALTERA_QUARTUS2;
when VENDOR_LATTICE =>
return SYNTHESIS_TOOL_LATTICE_LSE;
--return SYNTHESIS_TOOL_SYNOPSIS;
when VENDOR_XILINX =>
if (1 fs /= 1 us) then
return SYNTHESIS_TOOL_XILINX_XST;
else
return SYNTHESIS_TOOL_XILINX_VIVADO;
end if;
when others =>
return SYNTHESIS_TOOL_UNKNOWN;
end case;
end function;
-- purpose: extract device from MY_DEVICE
function DEVICE(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE is
constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString);
constant VEN : T_VENDOR := VENDOR(DeviceString);
constant DEV_STR : string(3 to 4) := MY_DEV(3 to 4); -- TODO: test if alias declarations also work out on all platforms
begin
case VEN is
when VENDOR_GENERIC =>
if (MY_DEV(1 to 7) = "GENERIC") then return DEVICE_GENERIC;
else report "Unknown Generic device in MY_DEVICE = '" & MY_DEV & "'" severity failure;
end if;
when VENDOR_ALTERA =>
case DEV_STR is
when "1C" => return DEVICE_CYCLONE1;
when "2C" => return DEVICE_CYCLONE2;
when "3C" => return DEVICE_CYCLONE3;
when "1S" => return DEVICE_STRATIX1;
when "2S" => return DEVICE_STRATIX2;
when "4S" => return DEVICE_STRATIX4;
when "5S" => return DEVICE_STRATIX5;
when others => report "Unknown Altera device in MY_DEVICE = '" & MY_DEV & "'" severity failure;
end case;
when VENDOR_LATTICE =>
if (MY_DEV(1 to 6) = "LCMX02") then return DEVICE_MACHXO2;
elsif (MY_DEV(1 to 5) = "LCMX0") then return DEVICE_MACHXO;
elsif (MY_DEV(1 to 5) = "iCE40") then return DEVICE_ICE40;
elsif (MY_DEV(1 to 5) = "iCE65") then return DEVICE_ICE65;
elsif (MY_DEV(1 to 4) = "iCE5") then return DEVICE_ICE5;
elsif (MY_DEV(1 to 4) = "LFE3") then return DEVICE_ECP3;
elsif (MY_DEV(1 to 4) = "LFE4") then return DEVICE_ECP4;
elsif (MY_DEV(1 to 4) = "LFE5") then return DEVICE_ECP5;
else report "Unknown Lattice device in MY_DEVICE = '" & MY_DEV & "'" severity failure;
end if;
when VENDOR_XILINX =>
case DEV_STR is
when "7A" => return DEVICE_ARTIX7;
when "7K" => return DEVICE_KINTEX7;
when "KU" => return DEVICE_KINTEX_ULTRA;
when "3S" => return DEVICE_SPARTAN3;
when "6S" => return DEVICE_SPARTAN6;
when "4V" => return DEVICE_VIRTEX4;
when "5V" => return DEVICE_VIRTEX5;
when "6V" => return DEVICE_VIRTEX6;
when "7V" => return DEVICE_VIRTEX7;
when "VU" => return DEVICE_VIRTEX_ULTRA;
when "7Z" => return DEVICE_ZYNQ7;
when others => report "Unknown Xilinx device in MY_DEVICE = '" & MY_DEV & "'" severity failure;
end case;
when others => report "Unknown vendor in MY_DEVICE = " & MY_DEV & "." severity failure;
end case;
return DEVICE_UNKNOWN;
end function;
-- purpose: extract device from MY_DEVICE
function DEVICE_FAMILY(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_FAMILY is
constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString);
constant VEN : T_VENDOR := VENDOR(DeviceString);
constant FAM_CHAR : character := MY_DEV(4);
begin
case VEN is
when VENDOR_GENERIC =>
return DEVICE_FAMILY_GENERIC;
when VENDOR_ALTERA =>
case FAM_CHAR is
when 'C' => return DEVICE_FAMILY_CYCLONE;
when 'S' => return DEVICE_FAMILY_STRATIX;
when others => report "Unknown Altera device family in MY_DEVICE = '" & MY_DEV & "'" severity failure;
end case;
when VENDOR_LATTICE =>
case FAM_CHAR is
--when 'M' => return DEVICE_FAMILY_MACHXO;
when 'E' => return DEVICE_FAMILY_ECP;
when others => report "Unknown Lattice device family in MY_DEVICE = '" & MY_DEV & "'" severity failure;
end case;
when VENDOR_XILINX =>
case FAM_CHAR is
when 'A' => return DEVICE_FAMILY_ARTIX;
when 'K' => return DEVICE_FAMILY_KINTEX;
when 'S' => return DEVICE_FAMILY_SPARTAN;
when 'V' => return DEVICE_FAMILY_VIRTEX;
when 'Z' => return DEVICE_FAMILY_ZYNQ;
when others => report "Unknown Xilinx device family in MY_DEVICE = '" & MY_DEV & "'" severity failure;
end case;
when others => report "Unknown vendor in MY_DEVICE = '" & MY_DEV & "'" severity failure;
end case;
return DEVICE_FAMILY_UNKNOWN;
end function;
-- some devices share some common features: e.g. XADC, BlockRAM, ...
function DEVICE_SERIES(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_SERIES is
constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString);
constant DEV : T_DEVICE := DEVICE(DeviceString);
begin
case DEV is
when DEVICE_GENERIC =>
return DEVICE_SERIES_GENERIC;
-- all Xilinx ****7 devices
when DEVICE_ARTIX7 | DEVICE_KINTEX7 | DEVICE_VIRTEX7 | DEVICE_ZYNQ7 =>
return DEVICE_SERIES_7_SERIES;
-- all Xilinx ****UltraScale devices
when DEVICE_KINTEX_ULTRA | DEVICE_VIRTEX_ULTRA =>
return DEVICE_SERIES_ULTRASCALE;
-- all Xilinx ****UltraScale+ devices
when DEVICE_KINTEX_ULTRA_PLUS | DEVICE_VIRTEX_ULTRA_PLUS | DEVICE_ZYNQ_ULTRA_PLUS =>
return DEVICE_SERIES_ULTRASCALE_PLUS;
when others =>
return DEVICE_SERIES_UNKNOWN;
end case;
end function;
function DEVICE_GENERATION(DeviceString : string := C_DEVICE_STRING_EMPTY) return natural is
constant SERIES : T_DEVICE_SERIES := DEVICE_SERIES(DeviceString);
begin
if SERIES = DEVICE_SERIES_7_SERIES then
return 7;
else
return 0;
end if;
end function;
function DEVICE_NUMBER(DeviceString : string := C_DEVICE_STRING_EMPTY) return natural is
constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString);
constant VEN : T_VENDOR := VENDOR(DeviceString);
begin
case VEN is
when VENDOR_GENERIC => return 0;
when VENDOR_ALTERA => return extractFirstNumber(MY_DEV(5 to MY_DEV'high));
when VENDOR_LATTICE => return extractFirstNumber(MY_DEV(6 to MY_DEV'high));
when VENDOR_XILINX => return extractFirstNumber(MY_DEV(5 to MY_DEV'high));
when others => report "Unknown vendor in MY_DEVICE = '" & MY_DEV & "'" severity failure;
return 0;
end case;
end function;
function DEVICE_SUBTYPE(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_SUBTYPE is
constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString);
constant DEV : T_DEVICE := DEVICE(MY_DEV);
constant DEV_SUB_STR : string(1 to 2) := MY_DEV(5 to 6); -- WORKAROUND: for GHDL
begin
case DEV is
when DEVICE_GENERIC => return DEVICE_SUBTYPE_GENERIC;
-- TODO: extract Arria GX subtype
when DEVICE_ARRIA1 =>
report "TODO: parse Arria device subtype." severity failure;
return DEVICE_SUBTYPE_NONE;
-- TODO: extract ArriaII GX,GZ subtype
when DEVICE_ARRIA2 =>
report "TODO: parse ArriaII device subtype." severity failure;
return DEVICE_SUBTYPE_NONE;
-- TODO: extract ArriaV GX, GT, SX, GZ subtype
when DEVICE_ARRIA5 =>
report "TODO: parse ArriaV device subtype." severity failure;
return DEVICE_SUBTYPE_NONE;
-- TODO: extract Arria10 GX, GT, SX subtype
when DEVICE_ARRIA10 =>
report "TODO: parse Arria10 device subtype." severity failure;
return DEVICE_SUBTYPE_NONE;
-- Altera Cyclon I, II, III, IV, V devices have no subtype
when DEVICE_CYCLONE1 | DEVICE_CYCLONE2 | DEVICE_CYCLONE3 | DEVICE_CYCLONE4 |
DEVICE_CYCLONE5 => return DEVICE_SUBTYPE_NONE;
when DEVICE_STRATIX2 =>
if chr_isDigit(DEV_SUB_STR(1)) then return DEVICE_SUBTYPE_NONE;
elsif DEV_SUB_STR = "GX" then return DEVICE_SUBTYPE_GX;
else report "Unknown Stratix II subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure;
end if;
when DEVICE_STRATIX4 =>
if (DEV_SUB_STR(1) = 'E') then return DEVICE_SUBTYPE_E;
elsif DEV_SUB_STR = "GX" then return DEVICE_SUBTYPE_GX;
-- elsif (DEV_SUB_STR = "GT") then return DEVICE_SUBTYPE_GT;
else report "Unknown Stratix IV subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure;
end if;
-- TODO: extract StratixV subtype
when DEVICE_STRATIX5 =>
report "TODO: parse Stratix V device subtype." severity failure;
return DEVICE_SUBTYPE_NONE;
when DEVICE_ECP5 =>
if (DEV_SUB_STR(1) = 'U') then return DEVICE_SUBTYPE_U;
elsif DEV_SUB_STR = "UM" then return DEVICE_SUBTYPE_UM;
else report "Unknown Lattice ECP5 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure;
end if;
when DEVICE_SPARTAN3 =>
report "TODO: parse Spartan3 / Spartan3E / Spartan3AN device subtype." severity failure;
return DEVICE_SUBTYPE_NONE;
when DEVICE_SPARTAN6 =>
if ((DEV_SUB_STR = "LX") and (not str_find(MY_DEV(7 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LX;
elsif ((DEV_SUB_STR = "LX") and ( str_find(MY_DEV(7 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LXT;
else report "Unknown Virtex-5 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure;
end if;
when DEVICE_VIRTEX4 =>
report "Unkown Virtex 4" severity failure;
when DEVICE_VIRTEX5 =>
if ((DEV_SUB_STR = "LX") and (not str_find(MY_DEV(7 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LX;
elsif ((DEV_SUB_STR = "LX") and ( str_find(MY_DEV(7 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LXT;
elsif ((DEV_SUB_STR = "SX") and ( str_find(MY_DEV(7 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_SXT;
elsif ((DEV_SUB_STR = "TX") and ( str_find(MY_DEV(7 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_TXT;
elsif ((DEV_SUB_STR = "FX") and ( str_find(MY_DEV(7 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_FXT;
else report "Unknown Virtex-5 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure;
end if;
when DEVICE_VIRTEX6 =>
if ((DEV_SUB_STR = "LX") and (not str_find(MY_DEV(7 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LX;
elsif ((DEV_SUB_STR = "LX") and ( str_find(MY_DEV(7 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LXT;
elsif ((DEV_SUB_STR = "SX") and ( str_find(MY_DEV(7 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_SXT;
elsif ((DEV_SUB_STR = "CX") and ( str_find(MY_DEV(7 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_CXT;
elsif ((DEV_SUB_STR = "HX") and ( str_find(MY_DEV(7 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_HXT;
else report "Unknown Virtex-6 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure;
end if;
when DEVICE_ARTIX7 =>
if ( ( str_find(MY_DEV(5 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_T;
else report "Unknown Artix-7 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure;
end if;
when DEVICE_KINTEX7 =>
if ( ( str_find(MY_DEV(5 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_T;
else report "Unknown Kintex-7 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure;
end if;
when DEVICE_KINTEX_ULTRA => return DEVICE_SUBTYPE_NONE;
when DEVICE_KINTEX_ULTRA_PLUS => return DEVICE_SUBTYPE_NONE;
when DEVICE_VIRTEX7 =>
if ( ( str_find(MY_DEV(5 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_T;
elsif ((DEV_SUB_STR(1) = 'X') and ( str_find(MY_DEV(6 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_XT;
elsif ((DEV_SUB_STR(1) = 'H') and ( str_find(MY_DEV(6 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_HT;
else report "Unknown Virtex-7 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure;
end if;
when DEVICE_VIRTEX_ULTRA => return DEVICE_SUBTYPE_NONE;
when DEVICE_VIRTEX_ULTRA_PLUS => return DEVICE_SUBTYPE_NONE;
when DEVICE_ZYNQ7 => return DEVICE_SUBTYPE_NONE;
when DEVICE_ZYNQ_ULTRA_PLUS => return DEVICE_SUBTYPE_NONE;
when others => report "Device sub-type is unknown for the given device." severity failure;
end case;
return DEVICE_SUBTYPE_NONE;
end function;
function LUT_FANIN(DeviceString : string := C_DEVICE_STRING_EMPTY) return positive is
constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString);
constant DEV : T_DEVICE := DEVICE(DeviceString);
constant SERIES : T_DEVICE_SERIES := DEVICE_SERIES(DeviceString);
begin
case SERIES is
when DEVICE_SERIES_GENERIC => return 6;
when DEVICE_SERIES_7_SERIES | DEVICE_SERIES_ULTRASCALE |
DEVICE_SERIES_ULTRASCALE_PLUS => return 6;
when others => null;
end case;
case DEV is
when DEVICE_CYCLONE1 | DEVICE_CYCLONE2 | DEVICE_CYCLONE3 => return 4;
when DEVICE_STRATIX1 | DEVICE_STRATIX2 => return 4;
when DEVICE_STRATIX4 | DEVICE_STRATIX5 => return 6;
when DEVICE_ECP5 => return 4;
when DEVICE_SPARTAN3 => return 4;
when DEVICE_SPARTAN6 => return 6;
when DEVICE_VIRTEX4 | DEVICE_VIRTEX5 | DEVICE_VIRTEX6 => return 6;
when others => report "LUT fan-in is unknown for the given device, using default (4)." severity failure;
return 4;
end case;
end function;
function TRANSCEIVER_TYPE(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_TRANSCEIVER is
constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString);
constant DEV : T_DEVICE := DEVICE(DeviceString);
constant DEV_NUM : natural := DEVICE_NUMBER(DeviceString);
constant DEV_SUB : T_DEVICE_SUBTYPE := DEVICE_SUBTYPE(DeviceString);
begin
case DEV is
when DEVICE_GENERIC => return TRANSCEIVER_GENERIC;
when DEVICE_MAX2 | DEVICE_MAX10 => return TRANSCEIVER_NONE; -- Altera MAX II, 10 devices have no transceivers
when DEVICE_CYCLONE1 | DEVICE_CYCLONE2 | DEVICE_CYCLONE3 => return TRANSCEIVER_NONE; -- Altera Cyclon I, II, III devices have no transceivers
when DEVICE_STRATIX2 => return TRANSCEIVER_GXB;
when DEVICE_STRATIX4 => return TRANSCEIVER_GXB;
--when DEVICE_STRATIX5 => return TRANSCEIVER_GXB;
when DEVICE_ECP5 => return TRANSCEIVER_MGT;
when DEVICE_SPARTAN3 => return TRANSCEIVER_NONE; -- Xilinx Spartan3 devices have no transceivers
when DEVICE_SPARTAN6 =>
case DEV_SUB is
when DEVICE_SUBTYPE_LX => return TRANSCEIVER_NONE;
when DEVICE_SUBTYPE_LXT => return TRANSCEIVER_GTPE1;
when others => report "Unknown Spartan-6 subtype: " & T_DEVICE_SUBTYPE'image(DEV_SUB) severity failure;
end case;
when DEVICE_VIRTEX4 =>
report "Unknown Virtex-4" severity failure;
when DEVICE_VIRTEX5 =>
case DEV_SUB is
when DEVICE_SUBTYPE_LX => return TRANSCEIVER_NONE;
when DEVICE_SUBTYPE_SXT => return TRANSCEIVER_GTP_DUAL;
when DEVICE_SUBTYPE_LXT => return TRANSCEIVER_GTP_DUAL;
when DEVICE_SUBTYPE_TXT => return TRANSCEIVER_GTX;
when DEVICE_SUBTYPE_FXT => return TRANSCEIVER_GTX;
when others => report "Unknown Virtex-5 subtype: " & T_DEVICE_SUBTYPE'image(DEV_SUB) severity failure;
end case;
when DEVICE_VIRTEX6 =>
case DEV_SUB is
when DEVICE_SUBTYPE_LX => return TRANSCEIVER_NONE;
when DEVICE_SUBTYPE_SXT => return TRANSCEIVER_GTXE1;
when DEVICE_SUBTYPE_LXT => return TRANSCEIVER_GTXE1;
when DEVICE_SUBTYPE_HXT => return TRANSCEIVER_GTXE1;
when others => report "Unknown Virtex-6 subtype: " & T_DEVICE_SUBTYPE'image(DEV_SUB) severity failure;
end case;
when DEVICE_ARTIX7 => return TRANSCEIVER_GTPE2;
when DEVICE_KINTEX7 => return TRANSCEIVER_GTXE2;
when DEVICE_VIRTEX7 =>
case DEV_SUB is
when DEVICE_SUBTYPE_T => return TRANSCEIVER_GTXE2;
when DEVICE_SUBTYPE_XT =>
if DEV_NUM = 485 then return TRANSCEIVER_GTXE2;
else return TRANSCEIVER_GTHE2;
end if;
when DEVICE_SUBTYPE_HT => return TRANSCEIVER_GTHE2;
when others => report "Unknown Virtex-7 subtype: " & T_DEVICE_SUBTYPE'image(DEV_SUB) severity failure;
end case;
when DEVICE_ZYNQ7 =>
case DEV_NUM is
when 10 | 20 => return TRANSCEIVER_NONE;
when 15 => return TRANSCEIVER_GTPE2;
when others => return TRANSCEIVER_GTXE2;
end case;
when others => report "Unknown device." severity failure;
end case;
return TRANSCEIVER_NONE;
end function;
-- purpose: extract architecture properties from DEVICE
function DEVICE_INFO(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_INFO is
variable Result : T_DEVICE_INFO;
begin
Result.Vendor := VENDOR(DeviceString);
Result.Device := DEVICE(DeviceString);
Result.DevFamily := DEVICE_FAMILY(DeviceString);
Result.DevSubType := DEVICE_SUBTYPE(DeviceString);
Result.DevSeries := DEVICE_SERIES(DeviceString);
Result.DevGeneration := DEVICE_GENERATION(DeviceString);
Result.DevNumber := DEVICE_NUMBER(DeviceString);
Result.TransceiverType := TRANSCEIVER_TYPE(DeviceString);
Result.LUT_FanIn := LUT_FANIN(DeviceString);
return Result;
end function;
-- Convert T_DEVICE to string representation as required by "altera_mf" library
function getAlteraDeviceName (device : T_DEVICE) return string is
begin
case device is
when DEVICE_ARRIA1 => return "Arria";
when DEVICE_ARRIA2 => return "Arria II";
when DEVICE_ARRIA5 => return "Arria V";
when DEVICE_ARRIA10 => return "Arria 10";
when DEVICE_CYCLONE1 => return "Cyclone";
when DEVICE_CYCLONE2 => return "Cyclone II";
when DEVICE_CYCLONE3 => return "Cyclone III";
when DEVICE_CYCLONE4 => return "Cyclone IV";
when DEVICE_CYCLONE5 => return "Cyclone V";
when DEVICE_STRATIX1 => return "Stratix";
when DEVICE_STRATIX2 => return "Stratix II";
when DEVICE_STRATIX3 => return "Stratix III";
when DEVICE_STRATIX4 => return "Stratix IV";
when DEVICE_STRATIX5 => return "Stratix V";
when DEVICE_STRATIX10 => return "Stratix 10";
when others =>
report "Unknown Altera device." severity failure;
return "";
end case;
end function;
-- force FSM to predefined encoding in debug mode
function getFSMEncoding_gray(debug : boolean) return string is
begin
if debug then
return "gray";
else
case VENDOR is
when VENDOR_ALTERA => return "default";
--when VENDOR_LATTICE => return "default";
when VENDOR_XILINX => return "auto";
when others => report "Unknown vendor." severity failure;
return "";
end case;
end if;
end function;
end package body;
|
entity tb_dpram2r is
end tb_dpram2r;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_dpram2r is
signal raddr : natural range 0 to 3;
signal rnib : natural range 0 to 1;
signal rdat : std_logic_vector (3 downto 0);
signal waddr : natural range 0 to 3;
signal wdat : std_logic_vector(7 downto 0);
signal clk : std_logic;
begin
dut: entity work.dpram2r
port map (raddr => raddr, rnib => rnib, rdat => rdat,
waddr => waddr, wdat => wdat,
clk => clk);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
raddr <= 0;
rnib <= 0;
waddr <= 1;
wdat <= x"e1";
pulse;
raddr <= 1;
rnib <= 0;
waddr <= 0;
wdat <= x"f0";
pulse;
assert rdat = x"1" severity failure;
raddr <= 1;
rnib <= 1;
waddr <= 2;
wdat <= x"d2";
pulse;
assert rdat = x"e" severity failure;
raddr <= 2;
rnib <= 1;
waddr <= 3;
wdat <= x"c3";
pulse;
assert rdat = x"d" severity failure;
raddr <= 3;
rnib <= 0;
waddr <= 0;
wdat <= x"f0";
pulse;
assert rdat = x"3" severity failure;
raddr <= 3;
rnib <= 1;
waddr <= 0;
wdat <= x"f0";
pulse;
assert rdat = x"c" severity failure;
wait;
end process;
end behav;
|
-- $Id: tb_tst_rlink_cuff_ic_n2.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_rlink_cuff_ic_n2
-- Description: Configuration for tb_tst_rlink_cuff_ic_n2 for
-- tb_nexys2_fusp_cuff
--
-- Dependencies: sys_tst_rlink_cuff_n2 (fx2_type = 'ic2')
--
-- To test: sys_tst_rlink_cuff_n2 (fx2_type = 'ic2')
--
-- Verified:
-- Date Rev Code ghdl ise Target Comment
-- 2013-01-xx xxx - 0.29 12.1 M53d xc3s1200e u:???
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-01-01 467 1.0 Initial version
------------------------------------------------------------------------------
configuration tb_tst_rlink_cuff_ic_n2 of tb_nexys2_fusp_cuff is
for sim
for all : nexys2_fusp_cuff_aif
use entity work.sys_tst_rlink_cuff_n2;
end for;
end for;
end tb_tst_rlink_cuff_ic_n2;
|
-------------------------------------------------------------------------------
--
-- The Program Memory control unit.
-- All operations related to the Program Memory are managed here.
--
-- $Id: pmem_ctrl.vhd,v 1.5 2005-06-11 10:08:43 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t48_pack.pmem_addr_t;
use work.t48_pack.word_t;
use work.t48_pmem_ctrl_pack.pmem_addr_ident_t;
entity t48_pmem_ctrl is
port (
-- Global Interface -------------------------------------------------------
clk_i : in std_logic;
res_i : in std_logic;
en_clk_i : in boolean;
-- T48 Bus Interface ------------------------------------------------------
data_i : in word_t;
data_o : out word_t;
write_pcl_i : in boolean;
read_pcl_i : in boolean;
write_pch_i : in boolean;
read_pch_i : in boolean;
inc_pc_i : in boolean;
write_pmem_addr_i : in boolean;
addr_type_i : in pmem_addr_ident_t;
read_pmem_i : in boolean;
-- Porgram Memroy Interface -----------------------------------------------
pmem_addr_o : out pmem_addr_t;
pmem_data_i : in word_t
);
end t48_pmem_ctrl;
library ieee;
use ieee.numeric_std.all;
use work.t48_pmem_ctrl_pack.all;
use work.t48_pack.res_active_c;
use work.t48_pack.clk_active_c;
use work.t48_pack.bus_idle_level_c;
use work.t48_pack.pmem_addr_width_c;
use work.t48_pack.dmem_addr_width_c;
use work.t48_pack.page_t;
architecture rtl of t48_pmem_ctrl is
-- implemented counter width of Program Counter
-- the upper bit is only altered by JMP, CALL and RET(R)
subtype pc_count_range_t is natural range pmem_addr_width_c-2 downto 0;
-- the Program Counter
signal program_counter_q : unsigned(pmem_addr_t'range);
-- the Program Memory address
signal pmem_addr_s,
pmem_addr_q : std_logic_vector(pmem_addr_t'range);
begin
-----------------------------------------------------------------------------
-- Process program_counter
--
-- Purpose:
-- Implements the Program Counter.
--
program_counter: process (res_i, clk_i)
begin
if res_i = res_active_c then
program_counter_q <= (others => '0');
pmem_addr_q <= (others => '0');
elsif clk_i'event and clk_i = clk_active_c then
if en_clk_i then
-- parallel load mode
if write_pcl_i then
program_counter_q(data_i'range) <= UNSIGNED(data_i);
elsif write_pch_i then
program_counter_q(pmem_addr_width_c-1 downto data_i'high+1) <=
UNSIGNED(data_i(pmem_addr_width_c - dmem_addr_width_c - 1 downto 0));
elsif inc_pc_i then
-- increment mode
-- the MSB is not modified by linear increments
-- it can only be altered by JMP, CALL or RET(R)
program_counter_q(pc_count_range_t) <=
program_counter_q(pc_count_range_t) + 1;
end if;
-- set pmem address
if write_pmem_addr_i then
pmem_addr_q <= pmem_addr_s;
end if;
end if;
end if;
end process program_counter;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process pmem_addr
--
-- Purpose:
-- Multiplex the Program Memory address.
--
pmem_addr: process (program_counter_q,
addr_type_i,
pmem_addr_q,
data_i)
begin
-- default assignment
pmem_addr_s <= STD_LOGIC_VECTOR(program_counter_q);
case addr_type_i is
when PM_PC =>
-- default is ok
null;
when PM_PAGE =>
pmem_addr_s(word_t'range) <= data_i;
-- take page address from program counter
-- => important for JMPP, MOVP!
-- they must wrap to next page when at FF!
when PM_PAGE3 =>
pmem_addr_s(word_t'range) <= data_i;
-- page address is explicitely specified
pmem_addr_s(page_t'range) <= "0011";
when others =>
null;
end case;
end process pmem_addr;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process data_output
--
-- Purpose:
-- Multiplex the data bus output.
--
data_output: process (read_pmem_i,
read_pcl_i,
read_pch_i,
pmem_data_i,
program_counter_q)
begin
data_o <= (others => bus_idle_level_c);
if read_pmem_i then
data_o <= pmem_data_i;
elsif read_pcl_i then
data_o <= STD_LOGIC_VECTOR(program_counter_q(data_o'range));
elsif read_pch_i then
data_o(3 downto 0) <= STD_LOGIC_VECTOR(program_counter_q(pmem_addr_width_c-1 downto data_o'high+1));
end if;
end process data_output;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output Mapping.
-----------------------------------------------------------------------------
pmem_addr_o <= pmem_addr_q;
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.4 2005/06/08 19:13:53 arniml
-- fix bug report
-- "MSB of Program Counter changed upon PC increment"
--
-- Revision 1.3 2004/07/11 16:51:33 arniml
-- cleanup copyright notice
--
-- Revision 1.2 2004/04/24 23:44:25 arniml
-- move from std_logic_arith to numeric_std
--
-- Revision 1.1 2004/03/23 21:31:53 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1393.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p04n01i01393ent IS
END c08s05b00x00p04n01i01393ent;
ARCHITECTURE c08s05b00x00p04n01i01393arch OF c08s05b00x00p04n01i01393ent IS
BEGIN
TESTING: PROCESS
type RT is
record
a : CHARACTER;
b : CHARACTER;
end record;
variable v1, v2 : CHARACTER := NUL;
variable rv : RT := ('1', '2');
BEGIN
assert v1 = NUL;
assert v2 = NUL;
(v1, v2) := rv;
assert v1 = '1';
assert v2 = '2';
wait for 1 ns;
assert NOT( v1 = '1' and v2 = '2' )
report "***PASSED TEST: c08s05b00x00p04n01i01393"
severity NOTE;
assert ( v1 = '1' and v2 = '2' )
report "***FAILED TEST: c08s05b00x00p04n01i01393 - Aggregate (record type) assignment for variable test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p04n01i01393arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1393.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p04n01i01393ent IS
END c08s05b00x00p04n01i01393ent;
ARCHITECTURE c08s05b00x00p04n01i01393arch OF c08s05b00x00p04n01i01393ent IS
BEGIN
TESTING: PROCESS
type RT is
record
a : CHARACTER;
b : CHARACTER;
end record;
variable v1, v2 : CHARACTER := NUL;
variable rv : RT := ('1', '2');
BEGIN
assert v1 = NUL;
assert v2 = NUL;
(v1, v2) := rv;
assert v1 = '1';
assert v2 = '2';
wait for 1 ns;
assert NOT( v1 = '1' and v2 = '2' )
report "***PASSED TEST: c08s05b00x00p04n01i01393"
severity NOTE;
assert ( v1 = '1' and v2 = '2' )
report "***FAILED TEST: c08s05b00x00p04n01i01393 - Aggregate (record type) assignment for variable test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p04n01i01393arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1393.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p04n01i01393ent IS
END c08s05b00x00p04n01i01393ent;
ARCHITECTURE c08s05b00x00p04n01i01393arch OF c08s05b00x00p04n01i01393ent IS
BEGIN
TESTING: PROCESS
type RT is
record
a : CHARACTER;
b : CHARACTER;
end record;
variable v1, v2 : CHARACTER := NUL;
variable rv : RT := ('1', '2');
BEGIN
assert v1 = NUL;
assert v2 = NUL;
(v1, v2) := rv;
assert v1 = '1';
assert v2 = '2';
wait for 1 ns;
assert NOT( v1 = '1' and v2 = '2' )
report "***PASSED TEST: c08s05b00x00p04n01i01393"
severity NOTE;
assert ( v1 = '1' and v2 = '2' )
report "***FAILED TEST: c08s05b00x00p04n01i01393 - Aggregate (record type) assignment for variable test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p04n01i01393arch;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := spartan3;
constant CFG_MEMTECH : integer := spartan3;
constant CFG_PADTECH : integer := spartan3;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := spartan3;
constant CFG_CLKMUL : integer := (4);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (0);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 1;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 8;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 1;
constant CFG_AHBROPIP : integer := 1;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#100#;
constant CFG_ROMMASK : integer := 16#E00# + 16#100#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#00F0#;
constant CFG_GRGPIO_WIDTH : integer := (18);
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 1;
constant CFG_VGA_ENABLE : integer := 1;
constant CFG_SVGA_ENABLE : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:45:03 07/06/2016
-- Design Name:
-- Module Name: segment_out - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity segment_out is port (
clk : in STD_LOGIC;
ready : in STD_LOGIC;
reset : in STD_LOGIC;
scancode : in STD_LOGIC_VECTOR(7 downto 0);
segments : out STD_LOGIC_VECTOR(14 downto 0);
anyKeyDown : out STD_LOGIC);
end segment_out;
architecture Behavioral of segment_out is
component seg_scancode_to_segments is port (
scancode : in STD_LOGIC_VECTOR(7 downto 0);
segment_repr : out STD_LOGIC_VECTOR(6 downto 0));
end component;
signal isE0, isF0, stw_q: STD_LOGIC;
signal segment_repr : STD_LOGIC_VECTOR(6 downto 0);
signal clock_divide_counter : Integer range 0 to 100000;
signal current_digit : Integer range 0 to 7;
signal digit0 : STD_LOGIC_VECTOR (6 downto 0);
signal digit1 : STD_LOGIC_VECTOR (6 downto 0);
signal digit2 : STD_LOGIC_VECTOR (6 downto 0);
signal digit3 : STD_LOGIC_VECTOR (6 downto 0);
signal digit4 : STD_LOGIC_VECTOR (6 downto 0);
signal digit5 : STD_LOGIC_VECTOR (6 downto 0);
signal digit6 : STD_LOGIC_VECTOR (6 downto 0);
signal digit7 : STD_LOGIC_VECTOR (6 downto 0);
begin
seg_scancode_to_segments0: seg_scancode_to_segments port map (scancode, segment_repr);
ef0_detector : process(scancode)
begin
if(scancode = "11100000") then
isE0 <= '1';
else
isE0 <= '0';
end if;
if(scancode = "11110000") then
isF0 <= '1';
else
isF0 <= '0';
end if;
end process ef0_detector;
stw : process (isE0, isF0, ready, clk)
begin
if clk'event and clk = '1' and ready = '1' then
if stw_q = '0' then
if isE0 = '0' AND isF0 = '0' then
digit7 <= digit6;
digit6 <= digit5;
digit5 <= digit4;
digit4 <= digit3;
digit3 <= digit2;
digit2 <= digit1;
digit1 <= digit0;
digit0 <= segment_repr;
anyKeyDown <= '1';
elsif isE0 = '0' AND isF0 = '1' then
stw_q <= '1';
anyKeyDown <= '0';
end if;
else
stw_q <= '0';
end if;
end if;
end process stw;
digit_select_clock_divider : process(clk)
begin
if clk'event and clk = '1' then
if clock_divide_counter >= 99999 then
clock_divide_counter <= 0;
current_digit <= current_digit + 1; -- overflows automatically with mod 8
else
clock_divide_counter <= clock_divide_counter + 1;
end if;
end if;
end process digit_select_clock_divider;
digit_time_multiplex : process (current_digit)
begin
if current_digit = 0 then
segments <= "11111110" & digit0;
elsif current_digit = 1 then
segments <= "11111101" & digit1;
elsif current_digit = 2 then
segments <= "11111011" & digit2;
elsif current_digit = 3 then
segments <= "11110111" & digit3;
elsif current_digit = 4 then
segments <= "11101111" & digit4;
elsif current_digit = 5 then
segments <= "11011111" & digit5;
elsif current_digit = 6 then
segments <= "10111111" & digit6;
else
segments <= "01111111" & digit7;
end if;
end process digit_time_multiplex;
end Behavioral;
|
----------------------------------------------------------------------------------
-- LIBRARIES --
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.math_pkg.all;
package display_controller_pkg is
constant DISPLAY_WIDTH : integer := 800;
constant DISPLAY_HEIGHT : integer := 480;
type COLOR_TYPE is array (0 to 15) of std_logic_vector(23 downto 0);
constant COLOR_TABLE : COLOR_TYPE :=
(
x"000000", -- black
x"0000AA", -- blue
x"00AA00", -- green
x"00AAAA", -- cyan
x"AA0000", -- red
x"AA00AA", -- pink
x"AA5500", -- brown
x"AAAAAA", -- gray
x"555555", -- dark gray
x"5555FF", -- light blue
x"55FF55", -- light green
x"55FFFF", -- light cyan
x"FF5555", -- light red
x"FF55FF", --
x"FFFF55", -- yellow
x"FFFFFF" -- white
);
component display_controller is
port
(
clk : in std_logic; -- global system clk
res_n : in std_logic; -- system reset
-- connection video ram
vram_addr_row : out std_logic_vector(log2c(30)-1 downto 0);
vram_addr_colum : out std_logic_vector(log2c(100)-1 downto 0);
vram_data : in std_logic_vector(15 downto 0);
vram_rd : out std_logic;
-- connection to font rom
char : out std_logic_vector(log2c(256) - 1 downto 0);
char_height_pixel : out std_logic_vector(log2c(16) - 1 downto 0);
decoded_char : in std_logic_vector(0 to 8 - 1);
-- connection to display
--nclk : out std_logic; -- display clk
hd : out std_logic; -- horizontal sync signal
vd : out std_logic; -- vertical sync signal
den : out std_logic; -- data enable
r : out std_logic_vector(7 downto 0); -- pixel color value (red)
g : out std_logic_vector(7 downto 0); -- pixel color value (green)
b : out std_logic_vector(7 downto 0); -- pixel color value (blue)
grest : out std_logic -- display reset
);
end component display_controller;
end display_controller_pkg;
|
----------------------------------------------------------------------------------
-- LIBRARIES --
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.math_pkg.all;
package display_controller_pkg is
constant DISPLAY_WIDTH : integer := 800;
constant DISPLAY_HEIGHT : integer := 480;
type COLOR_TYPE is array (0 to 15) of std_logic_vector(23 downto 0);
constant COLOR_TABLE : COLOR_TYPE :=
(
x"000000", -- black
x"0000AA", -- blue
x"00AA00", -- green
x"00AAAA", -- cyan
x"AA0000", -- red
x"AA00AA", -- pink
x"AA5500", -- brown
x"AAAAAA", -- gray
x"555555", -- dark gray
x"5555FF", -- light blue
x"55FF55", -- light green
x"55FFFF", -- light cyan
x"FF5555", -- light red
x"FF55FF", --
x"FFFF55", -- yellow
x"FFFFFF" -- white
);
component display_controller is
port
(
clk : in std_logic; -- global system clk
res_n : in std_logic; -- system reset
-- connection video ram
vram_addr_row : out std_logic_vector(log2c(30)-1 downto 0);
vram_addr_colum : out std_logic_vector(log2c(100)-1 downto 0);
vram_data : in std_logic_vector(15 downto 0);
vram_rd : out std_logic;
-- connection to font rom
char : out std_logic_vector(log2c(256) - 1 downto 0);
char_height_pixel : out std_logic_vector(log2c(16) - 1 downto 0);
decoded_char : in std_logic_vector(0 to 8 - 1);
-- connection to display
--nclk : out std_logic; -- display clk
hd : out std_logic; -- horizontal sync signal
vd : out std_logic; -- vertical sync signal
den : out std_logic; -- data enable
r : out std_logic_vector(7 downto 0); -- pixel color value (red)
g : out std_logic_vector(7 downto 0); -- pixel color value (green)
b : out std_logic_vector(7 downto 0); -- pixel color value (blue)
grest : out std_logic -- display reset
);
end component display_controller;
end display_controller_pkg;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc573.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:34 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:25:33 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:06 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00573ent IS
END c03s04b01x00p01n01i00573ent;
ARCHITECTURE c03s04b01x00p01n01i00573arch OF c03s04b01x00p01n01i00573ent IS
type time_file is file of time;
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : time_file open read_mode is "iofile.20";
variable v : time;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= 3 ns) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00573"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00573 - File reading operation failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00573arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc573.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:34 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:25:33 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:06 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00573ent IS
END c03s04b01x00p01n01i00573ent;
ARCHITECTURE c03s04b01x00p01n01i00573arch OF c03s04b01x00p01n01i00573ent IS
type time_file is file of time;
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : time_file open read_mode is "iofile.20";
variable v : time;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= 3 ns) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00573"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00573 - File reading operation failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00573arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc573.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:34 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:25:33 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:06 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00573ent IS
END c03s04b01x00p01n01i00573ent;
ARCHITECTURE c03s04b01x00p01n01i00573arch OF c03s04b01x00p01n01i00573ent IS
type time_file is file of time;
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : time_file open read_mode is "iofile.20";
variable v : time;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= 3 ns) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00573"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00573 - File reading operation failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00573arch;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_e_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:29 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_e_e-rtl-a.vhd,v 1.1 2004/04/06 10:50:20 wig Exp $
-- $Date: 2004/04/06 10:50:20 $
-- $Log: inst_e_e-rtl-a.vhd,v $
-- Revision 1.1 2004/04/06 10:50:20 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Revision: 1.26 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_e_e
--
architecture rtl of inst_e_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component inst_ea_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_ea_e
egi_scani : in std_ulogic_vector(10 downto 0);
egi_scano : out std_ulogic_vector(10 downto 0);
p_mix_cp_laddr_31_1_gi : in std_ulogic_vector(30 downto 0);
p_mix_cp_lcmd_6_6_gi : in std_ulogic;
p_mix_gpio_int_4_0_go : out std_ulogic_vector(4 downto 0);
p_mix_nreset_gi : in std_ulogic;
p_mix_nreset_s_gi : in std_ulogic;
p_mix_tmi_sbist_fail_11_10_gi : in std_ulogic_vector(1 downto 0);
p_mix_tmi_sbist_fail_9_0_go : out std_ulogic_vector(9 downto 0);
p_mix_tmu_dac_reset_go : out std_ulogic;
p_mix_v_select_2_2_gi : in std_ulogic;
p_mix_v_select_5_5_gi : in std_ulogic
-- End of Generated Port for Entity inst_ea_e
);
end component;
-- ---------
component inst_eb_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_eb_e
p_mix_nreset_gi : in std_ulogic;
p_mix_nreset_s_gi : in std_ulogic;
p_mix_tmi_sbist_fail_12_10_go : out std_ulogic_vector(2 downto 0);
p_mix_v_select_5_0_go : out std_ulogic_vector(5 downto 0);
vclkl27 : in std_ulogic;
vio_scani : in std_ulogic_vector(30 downto 0);
vio_scano : out std_ulogic_vector(30 downto 0)
-- End of Generated Port for Entity inst_eb_e
);
end component;
-- ---------
component inst_ec_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_ec_e
p_mix_nreset_gi : in std_ulogic;
p_mix_nreset_s_gi : in std_ulogic;
p_mix_v_select_5_0_gi : in std_ulogic_vector(5 downto 0);
tpm_scani : in std_ulogic_vector(12 downto 0);
tpm_scano : out std_ulogic_vector(12 downto 0)
-- End of Generated Port for Entity inst_ec_e
);
end component;
-- ---------
component inst_ed_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_ed_e
p_mix_acg_systime_init_30_0_gi : in std_ulogic_vector(30 downto 0);
p_mix_cgs_ramclk_go : out std_ulogic;
p_mix_gpio_int_2_0_gi : in std_ulogic_vector(2 downto 0);
p_mix_itm_scani_0_0_gi : in std_ulogic;
p_mix_nreset_go : out std_ulogic;
p_mix_nreset_s_go : out std_ulogic;
p_mix_tmi_scano_0_0_go : out std_ulogic;
p_mix_vclkl27_go : out std_ulogic
-- End of Generated Port for Entity inst_ed_e
);
end component;
-- ---------
component inst_ee_e --
-- No Generated Generics
-- Generated Generics for Entity inst_ee_e
-- End of Generated Generics for Entity inst_ee_e
port (
-- Generated Port for Entity inst_ee_e
cgs_ramclk : in std_ulogic;
itm_scani : out std_ulogic_vector(70 downto 0);
nreset : in std_ulogic;
nreset_s : in std_ulogic;
si_vclkx2 : in std_ulogic;
tmi_sbist_fail : in std_ulogic_vector(12 downto 0);
tmi_scano : in std_ulogic_vector(70 downto 0)
-- End of Generated Port for Entity inst_ee_e
);
end component;
-- ---------
component inst_ef_e --
-- No Generated Generics
-- Generated Generics for Entity inst_ef_e
-- End of Generated Generics for Entity inst_ef_e
port (
-- Generated Port for Entity inst_ef_e
cp_laddro : out std_ulogic_vector(31 downto 0);
cp_lcmd : out std_ulogic_vector(6 downto 0);
cpu_scani : in std_ulogic_vector(7 downto 0);
cpu_scano : out std_ulogic_vector(7 downto 0);
int23 : in std_ulogic;
int24 : in std_ulogic;
int25 : in std_ulogic;
int26 : in std_ulogic;
int27 : in std_ulogic;
nreset : in std_ulogic;
nreset_s : in std_ulogic;
tap_reset_n : in std_ulogic;
tap_reset_n_o : out std_ulogic
-- End of Generated Port for Entity inst_ef_e
);
end component;
-- ---------
component inst_eg_e --
-- No Generated Generics
-- Generated Generics for Entity inst_eg_e
-- End of Generated Generics for Entity inst_eg_e
port (
-- Generated Port for Entity inst_eg_e
acg_systime_init : out std_ulogic_vector(30 downto 0);
adp_scani : in std_ulogic_vector(6 downto 0);
adp_scano : out std_ulogic_vector(6 downto 0);
nreset : in std_ulogic;
nreset_s : in std_ulogic
-- End of Generated Port for Entity inst_eg_e
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal acg_systime_init : std_ulogic_vector(30 downto 0);
signal s_int_cgs_ramclk : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal cp_laddr : std_ulogic_vector(31 downto 0);
signal cp_lcmd : std_ulogic_vector(6 downto 0);
signal gpio_int : std_ulogic_vector(4 downto 0);
signal itm_scani : std_ulogic_vector(70 downto 0);
signal nreset : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal nreset_s : std_ulogic;
signal tap_reset_n_o : std_ulogic;
signal tmi_sbist_fail : std_ulogic_vector(12 downto 0);
signal tmi_scano : std_ulogic_vector(70 downto 0);
signal v_select : std_ulogic_vector(5 downto 0);
signal s_int_vclkl27 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
cgs_ramclk <= s_int_cgs_ramclk; -- __I_O_BIT_PORT
p_mix_nreset_go <= nreset; -- __I_O_BIT_PORT
vclkl27 <= s_int_vclkl27; -- __I_O_BIT_PORT
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_ea
inst_ea: inst_ea_e
port map (
egi_scani => itm_scani(31 downto 21),
egi_scano => tmi_scano(31 downto 21),
p_mix_cp_laddr_31_1_gi => cp_laddr(31 downto 1), -- GuestBusLBC(memorymappedI/O)InterfaceLBCinterfacetobeusecurrentlybyGuestBus
p_mix_cp_lcmd_6_6_gi => cp_lcmd(6), -- GuestBusLBC(memorymappedI/O)Interface
p_mix_gpio_int_4_0_go => gpio_int, -- GPIOWakeUPSignalsInterruptinputs
p_mix_nreset_gi => nreset, -- GlobalRESET(Verilogmacro)
p_mix_nreset_s_gi => nreset_s, -- GlobalRESET(Verilogmacro)
p_mix_tmi_sbist_fail_11_10_gi => tmi_sbist_fail(11 downto 10),
p_mix_tmi_sbist_fail_9_0_go => tmi_sbist_fail(9 downto 0),
p_mix_tmu_dac_reset_go => tmu_dac_reset, -- CADCTestModeRGBADAC
p_mix_v_select_2_2_gi => v_select(2), -- VPUinterfaceRequestBusinterface:RequestBus#6(VPU)requestbusinterfaceforcgpandcgclientserver
p_mix_v_select_5_5_gi => v_select(5) -- VPUinterfaceRequestBusinterface:RequestBus#6(VPU)requestbusinterfaceforcgpandcgclientserver
);
-- End of Generated Instance Port Map for inst_ea
-- Generated Instance Port Map for inst_eb
inst_eb: inst_eb_e
port map (
p_mix_nreset_gi => nreset, -- GlobalRESET(Verilogmacro)
p_mix_nreset_s_gi => nreset_s, -- GlobalRESET(Verilogmacro)
p_mix_tmi_sbist_fail_12_10_go => tmi_sbist_fail(12 downto 10),
p_mix_v_select_5_0_go => v_select, -- VPUinterfaceRequestBusinterface:RequestBus#6(VPU)requestbusinterfaceforcgpandcgclientserver
vclkl27 => s_int_vclkl27, -- ClockSignalsClocksforMacrosglobalsignaldefinitonsclock,reset&powerdown
vio_scani => itm_scani(70 downto 40),
vio_scano => tmi_scano(70 downto 40)
);
-- End of Generated Instance Port Map for inst_eb
-- Generated Instance Port Map for inst_ec
inst_ec: inst_ec_e
port map (
p_mix_nreset_gi => nreset, -- GlobalRESET(Verilogmacro)
p_mix_nreset_s_gi => nreset_s, -- GlobalRESET(Verilogmacro)
p_mix_v_select_5_0_gi => v_select, -- VPUinterfaceRequestBusinterface:RequestBus#6(VPU)requestbusinterfaceforcgpandcgclientserver
tpm_scani => itm_scani(20 downto 8),
tpm_scano => tmi_scano(20 downto 8)
);
-- End of Generated Instance Port Map for inst_ec
-- Generated Instance Port Map for inst_ed
inst_ed: inst_ed_e
port map (
p_mix_acg_systime_init_30_0_gi => acg_systime_init, -- ADPinterfaceScan
p_mix_cgs_ramclk_go => s_int_cgs_ramclk, -- ClockSignalsESDRAMInterface
p_mix_gpio_int_2_0_gi => gpio_int(2 downto 0), -- GPIOWakeUPSignalsInterruptinputs
p_mix_itm_scani_0_0_gi => itm_scani(0),
p_mix_nreset_go => nreset, -- GlobalRESET(Verilogmacro)
p_mix_nreset_s_go => nreset_s, -- GlobalRESET(Verilogmacro)
p_mix_tmi_scano_0_0_go => tmi_scano(0),
p_mix_vclkl27_go => s_int_vclkl27 -- ClockSignalsClocksforMacrosglobalsignaldefinitonsclock,reset&powerdown
);
-- End of Generated Instance Port Map for inst_ed
-- Generated Instance Port Map for inst_ee
inst_ee: inst_ee_e
port map (
cgs_ramclk => s_int_cgs_ramclk, -- ClockSignalsESDRAMInterface
itm_scani => itm_scani,
nreset => nreset, -- GlobalRESET(Verilogmacro)
nreset_s => nreset_s, -- GlobalRESET(Verilogmacro)
si_vclkx2 => si_vclkx2, -- DigitalVideoPort
tmi_sbist_fail => tmi_sbist_fail,
tmi_scano => tmi_scano
);
-- End of Generated Instance Port Map for inst_ee
-- Generated Instance Port Map for inst_ef
inst_ef: inst_ef_e
port map (
cp_laddro => cp_laddr, -- GuestBusLBC(memorymappedI/O)InterfaceLBCinterfacetobeusecurrentlybyGuestBus
cp_lcmd => cp_lcmd, -- GuestBusLBC(memorymappedI/O)Interface
cpu_scani => itm_scani(39 downto 32),
cpu_scano => tmi_scano(39 downto 32),
int23 => gpio_int(0), -- GPIOWakeUPSignalsInterruptinputs
int24 => gpio_int(1), -- GPIOWakeUPSignalsInterruptinputs
int25 => gpio_int(2), -- GPIOWakeUPSignalsInterruptinputs
int26 => gpio_int(3), -- GPIOWakeUPSignalsInterruptinputs
int27 => gpio_int(4), -- GPIOWakeUPSignalsInterruptinputs
nreset => nreset, -- GlobalRESET(Verilogmacro)
nreset_s => nreset_s, -- GlobalRESET(Verilogmacro)
tap_reset_n => tap_reset_n_o, -- RESETports
tap_reset_n_o => tap_reset_n_o -- RESETports
);
-- End of Generated Instance Port Map for inst_ef
-- Generated Instance Port Map for inst_eg
inst_eg: inst_eg_e
port map (
acg_systime_init => acg_systime_init, -- ADPinterfaceScan
adp_scani => itm_scani(7 downto 1),
adp_scano => tmi_scano(7 downto 1),
nreset => nreset, -- GlobalRESET(Verilogmacro)
nreset_s => nreset_s -- GlobalRESET(Verilogmacro)
);
-- End of Generated Instance Port Map for inst_eg
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY BJT_transistor_simple IS
GENERIC ( VT : REAL := 25.85e-3;
AF : REAL := 1.0;
KF : REAL := 0.0;
PT : REAL := 3.0;
EG : REAL := 1.11;
MC : REAL := 0.5;
PC : REAL := 1.0;
CJC : REAL := 2.5e-12;
ME : REAL := 0.5;
PE : REAL := 1.0;
CJE : REAL := 2.5e-12;
CCS : REAL := 2.5e-12;
TR : REAL := 4.0e-9;
TF : REAL := 4.0e-9;
NCL : REAL := 2.0;
C4 : REAL := 0.0;
NEL : REAL := 2.0;
C2 : REAL := 0.0;
RS : REAL := 1.0;
RE : REAL := 1.0;
RC : REAL := 1.0;
RB : REAL := 1.0;
ISS : REAL := 10.0e-14;
BR : REAL := 1.0;
BF : REAL := 100.0 );
PORT ( terminal Emitter : electrical;
terminal Collector : electrical;
terminal Base : electrical );
END ENTITY BJT_transistor_simple;
|
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY BJT_transistor_simple IS
GENERIC ( VT : REAL := 25.85e-3;
AF : REAL := 1.0;
KF : REAL := 0.0;
PT : REAL := 3.0;
EG : REAL := 1.11;
MC : REAL := 0.5;
PC : REAL := 1.0;
CJC : REAL := 2.5e-12;
ME : REAL := 0.5;
PE : REAL := 1.0;
CJE : REAL := 2.5e-12;
CCS : REAL := 2.5e-12;
TR : REAL := 4.0e-9;
TF : REAL := 4.0e-9;
NCL : REAL := 2.0;
C4 : REAL := 0.0;
NEL : REAL := 2.0;
C2 : REAL := 0.0;
RS : REAL := 1.0;
RE : REAL := 1.0;
RC : REAL := 1.0;
RB : REAL := 1.0;
ISS : REAL := 10.0e-14;
BR : REAL := 1.0;
BF : REAL := 100.0 );
PORT ( terminal Emitter : electrical;
terminal Collector : electrical;
terminal Base : electrical );
END ENTITY BJT_transistor_simple;
|
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY BJT_transistor_simple IS
GENERIC ( VT : REAL := 25.85e-3;
AF : REAL := 1.0;
KF : REAL := 0.0;
PT : REAL := 3.0;
EG : REAL := 1.11;
MC : REAL := 0.5;
PC : REAL := 1.0;
CJC : REAL := 2.5e-12;
ME : REAL := 0.5;
PE : REAL := 1.0;
CJE : REAL := 2.5e-12;
CCS : REAL := 2.5e-12;
TR : REAL := 4.0e-9;
TF : REAL := 4.0e-9;
NCL : REAL := 2.0;
C4 : REAL := 0.0;
NEL : REAL := 2.0;
C2 : REAL := 0.0;
RS : REAL := 1.0;
RE : REAL := 1.0;
RC : REAL := 1.0;
RB : REAL := 1.0;
ISS : REAL := 10.0e-14;
BR : REAL := 1.0;
BF : REAL := 100.0 );
PORT ( terminal Emitter : electrical;
terminal Collector : electrical;
terminal Base : electrical );
END ENTITY BJT_transistor_simple;
|
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY BJT_transistor_simple IS
GENERIC ( VT : REAL := 25.85e-3;
AF : REAL := 1.0;
KF : REAL := 0.0;
PT : REAL := 3.0;
EG : REAL := 1.11;
MC : REAL := 0.5;
PC : REAL := 1.0;
CJC : REAL := 2.5e-12;
ME : REAL := 0.5;
PE : REAL := 1.0;
CJE : REAL := 2.5e-12;
CCS : REAL := 2.5e-12;
TR : REAL := 4.0e-9;
TF : REAL := 4.0e-9;
NCL : REAL := 2.0;
C4 : REAL := 0.0;
NEL : REAL := 2.0;
C2 : REAL := 0.0;
RS : REAL := 1.0;
RE : REAL := 1.0;
RC : REAL := 1.0;
RB : REAL := 1.0;
ISS : REAL := 10.0e-14;
BR : REAL := 1.0;
BF : REAL := 100.0 );
PORT ( terminal Emitter : electrical;
terminal Collector : electrical;
terminal Base : electrical );
END ENTITY BJT_transistor_simple;
|
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY BJT_transistor_simple IS
GENERIC ( VT : REAL := 25.85e-3;
AF : REAL := 1.0;
KF : REAL := 0.0;
PT : REAL := 3.0;
EG : REAL := 1.11;
MC : REAL := 0.5;
PC : REAL := 1.0;
CJC : REAL := 2.5e-12;
ME : REAL := 0.5;
PE : REAL := 1.0;
CJE : REAL := 2.5e-12;
CCS : REAL := 2.5e-12;
TR : REAL := 4.0e-9;
TF : REAL := 4.0e-9;
NCL : REAL := 2.0;
C4 : REAL := 0.0;
NEL : REAL := 2.0;
C2 : REAL := 0.0;
RS : REAL := 1.0;
RE : REAL := 1.0;
RC : REAL := 1.0;
RB : REAL := 1.0;
ISS : REAL := 10.0e-14;
BR : REAL := 1.0;
BF : REAL := 100.0 );
PORT ( terminal Emitter : electrical;
terminal Collector : electrical;
terminal Base : electrical );
END ENTITY BJT_transistor_simple;
|
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY BJT_transistor_simple IS
GENERIC ( VT : REAL := 25.85e-3;
AF : REAL := 1.0;
KF : REAL := 0.0;
PT : REAL := 3.0;
EG : REAL := 1.11;
MC : REAL := 0.5;
PC : REAL := 1.0;
CJC : REAL := 2.5e-12;
ME : REAL := 0.5;
PE : REAL := 1.0;
CJE : REAL := 2.5e-12;
CCS : REAL := 2.5e-12;
TR : REAL := 4.0e-9;
TF : REAL := 4.0e-9;
NCL : REAL := 2.0;
C4 : REAL := 0.0;
NEL : REAL := 2.0;
C2 : REAL := 0.0;
RS : REAL := 1.0;
RE : REAL := 1.0;
RC : REAL := 1.0;
RB : REAL := 1.0;
ISS : REAL := 10.0e-14;
BR : REAL := 1.0;
BF : REAL := 100.0 );
PORT ( terminal Emitter : electrical;
terminal Collector : electrical;
terminal Base : electrical );
END ENTITY BJT_transistor_simple;
|
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY BJT_transistor_simple IS
GENERIC ( VT : REAL := 25.85e-3;
AF : REAL := 1.0;
KF : REAL := 0.0;
PT : REAL := 3.0;
EG : REAL := 1.11;
MC : REAL := 0.5;
PC : REAL := 1.0;
CJC : REAL := 2.5e-12;
ME : REAL := 0.5;
PE : REAL := 1.0;
CJE : REAL := 2.5e-12;
CCS : REAL := 2.5e-12;
TR : REAL := 4.0e-9;
TF : REAL := 4.0e-9;
NCL : REAL := 2.0;
C4 : REAL := 0.0;
NEL : REAL := 2.0;
C2 : REAL := 0.0;
RS : REAL := 1.0;
RE : REAL := 1.0;
RC : REAL := 1.0;
RB : REAL := 1.0;
ISS : REAL := 10.0e-14;
BR : REAL := 1.0;
BF : REAL := 100.0 );
PORT ( terminal Emitter : electrical;
terminal Collector : electrical;
terminal Base : electrical );
END ENTITY BJT_transistor_simple;
|
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY BJT_transistor_simple IS
GENERIC ( VT : REAL := 25.85e-3;
AF : REAL := 1.0;
KF : REAL := 0.0;
PT : REAL := 3.0;
EG : REAL := 1.11;
MC : REAL := 0.5;
PC : REAL := 1.0;
CJC : REAL := 2.5e-12;
ME : REAL := 0.5;
PE : REAL := 1.0;
CJE : REAL := 2.5e-12;
CCS : REAL := 2.5e-12;
TR : REAL := 4.0e-9;
TF : REAL := 4.0e-9;
NCL : REAL := 2.0;
C4 : REAL := 0.0;
NEL : REAL := 2.0;
C2 : REAL := 0.0;
RS : REAL := 1.0;
RE : REAL := 1.0;
RC : REAL := 1.0;
RB : REAL := 1.0;
ISS : REAL := 10.0e-14;
BR : REAL := 1.0;
BF : REAL := 100.0 );
PORT ( terminal Emitter : electrical;
terminal Collector : electrical;
terminal Base : electrical );
END ENTITY BJT_transistor_simple;
|
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY BJT_transistor_simple IS
GENERIC ( VT : REAL := 25.85e-3;
AF : REAL := 1.0;
KF : REAL := 0.0;
PT : REAL := 3.0;
EG : REAL := 1.11;
MC : REAL := 0.5;
PC : REAL := 1.0;
CJC : REAL := 2.5e-12;
ME : REAL := 0.5;
PE : REAL := 1.0;
CJE : REAL := 2.5e-12;
CCS : REAL := 2.5e-12;
TR : REAL := 4.0e-9;
TF : REAL := 4.0e-9;
NCL : REAL := 2.0;
C4 : REAL := 0.0;
NEL : REAL := 2.0;
C2 : REAL := 0.0;
RS : REAL := 1.0;
RE : REAL := 1.0;
RC : REAL := 1.0;
RB : REAL := 1.0;
ISS : REAL := 10.0e-14;
BR : REAL := 1.0;
BF : REAL := 100.0 );
PORT ( terminal Emitter : electrical;
terminal Collector : electrical;
terminal Base : electrical );
END ENTITY BJT_transistor_simple;
|
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY BJT_transistor_simple IS
GENERIC ( VT : REAL := 25.85e-3;
AF : REAL := 1.0;
KF : REAL := 0.0;
PT : REAL := 3.0;
EG : REAL := 1.11;
MC : REAL := 0.5;
PC : REAL := 1.0;
CJC : REAL := 2.5e-12;
ME : REAL := 0.5;
PE : REAL := 1.0;
CJE : REAL := 2.5e-12;
CCS : REAL := 2.5e-12;
TR : REAL := 4.0e-9;
TF : REAL := 4.0e-9;
NCL : REAL := 2.0;
C4 : REAL := 0.0;
NEL : REAL := 2.0;
C2 : REAL := 0.0;
RS : REAL := 1.0;
RE : REAL := 1.0;
RC : REAL := 1.0;
RB : REAL := 1.0;
ISS : REAL := 10.0e-14;
BR : REAL := 1.0;
BF : REAL := 100.0 );
PORT ( terminal Emitter : electrical;
terminal Collector : electrical;
terminal Base : electrical );
END ENTITY BJT_transistor_simple;
|
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY BJT_transistor_simple IS
GENERIC ( VT : REAL := 25.85e-3;
AF : REAL := 1.0;
KF : REAL := 0.0;
PT : REAL := 3.0;
EG : REAL := 1.11;
MC : REAL := 0.5;
PC : REAL := 1.0;
CJC : REAL := 2.5e-12;
ME : REAL := 0.5;
PE : REAL := 1.0;
CJE : REAL := 2.5e-12;
CCS : REAL := 2.5e-12;
TR : REAL := 4.0e-9;
TF : REAL := 4.0e-9;
NCL : REAL := 2.0;
C4 : REAL := 0.0;
NEL : REAL := 2.0;
C2 : REAL := 0.0;
RS : REAL := 1.0;
RE : REAL := 1.0;
RC : REAL := 1.0;
RB : REAL := 1.0;
ISS : REAL := 10.0e-14;
BR : REAL := 1.0;
BF : REAL := 100.0 );
PORT ( terminal Emitter : electrical;
terminal Collector : electrical;
terminal Base : electrical );
END ENTITY BJT_transistor_simple;
|
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY BJT_transistor_simple IS
GENERIC ( VT : REAL := 25.85e-3;
AF : REAL := 1.0;
KF : REAL := 0.0;
PT : REAL := 3.0;
EG : REAL := 1.11;
MC : REAL := 0.5;
PC : REAL := 1.0;
CJC : REAL := 2.5e-12;
ME : REAL := 0.5;
PE : REAL := 1.0;
CJE : REAL := 2.5e-12;
CCS : REAL := 2.5e-12;
TR : REAL := 4.0e-9;
TF : REAL := 4.0e-9;
NCL : REAL := 2.0;
C4 : REAL := 0.0;
NEL : REAL := 2.0;
C2 : REAL := 0.0;
RS : REAL := 1.0;
RE : REAL := 1.0;
RC : REAL := 1.0;
RB : REAL := 1.0;
ISS : REAL := 10.0e-14;
BR : REAL := 1.0;
BF : REAL := 100.0 );
PORT ( terminal Emitter : electrical;
terminal Collector : electrical;
terminal Base : electrical );
END ENTITY BJT_transistor_simple;
|
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY BJT_transistor_simple IS
GENERIC ( VT : REAL := 25.85e-3;
AF : REAL := 1.0;
KF : REAL := 0.0;
PT : REAL := 3.0;
EG : REAL := 1.11;
MC : REAL := 0.5;
PC : REAL := 1.0;
CJC : REAL := 2.5e-12;
ME : REAL := 0.5;
PE : REAL := 1.0;
CJE : REAL := 2.5e-12;
CCS : REAL := 2.5e-12;
TR : REAL := 4.0e-9;
TF : REAL := 4.0e-9;
NCL : REAL := 2.0;
C4 : REAL := 0.0;
NEL : REAL := 2.0;
C2 : REAL := 0.0;
RS : REAL := 1.0;
RE : REAL := 1.0;
RC : REAL := 1.0;
RB : REAL := 1.0;
ISS : REAL := 10.0e-14;
BR : REAL := 1.0;
BF : REAL := 100.0 );
PORT ( terminal Emitter : electrical;
terminal Collector : electrical;
terminal Base : electrical );
END ENTITY BJT_transistor_simple;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2638.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02638ent IS
END c13s03b01x00p02n01i02638ent;
ARCHITECTURE c13s03b01x00p02n01i02638arch OF c13s03b01x00p02n01i02638ent IS
BEGIN
TESTING: PROCESS
variable k\k : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02638 - Identifier can not contain '\'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02638arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2638.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02638ent IS
END c13s03b01x00p02n01i02638ent;
ARCHITECTURE c13s03b01x00p02n01i02638arch OF c13s03b01x00p02n01i02638ent IS
BEGIN
TESTING: PROCESS
variable k\k : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02638 - Identifier can not contain '\'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02638arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2638.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02638ent IS
END c13s03b01x00p02n01i02638ent;
ARCHITECTURE c13s03b01x00p02n01i02638arch OF c13s03b01x00p02n01i02638ent IS
BEGIN
TESTING: PROCESS
variable k\k : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02638 - Identifier can not contain '\'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02638arch;
|
entity proc7 is
end entity;
architecture test of proc7 is
procedure foo(signal b : in bit_vector; i : in integer) is
variable c : bit_vector(b'range);
begin
assert c(c'left) = '0';
--wait for 1 ns;
for i in b'range loop
c(i) := b(i);
end loop;
wait for 1 ns;
for i in c'range loop
report bit'image(c(i));
end loop;
end procedure;
signal s : bit_vector(1 to 3) := ( '1', '0', '1' );
begin
process is
begin
s <= "110";
foo(s, 1);
foo(s, 1);
wait;
end process;
end architecture;
|
entity proc7 is
end entity;
architecture test of proc7 is
procedure foo(signal b : in bit_vector; i : in integer) is
variable c : bit_vector(b'range);
begin
assert c(c'left) = '0';
--wait for 1 ns;
for i in b'range loop
c(i) := b(i);
end loop;
wait for 1 ns;
for i in c'range loop
report bit'image(c(i));
end loop;
end procedure;
signal s : bit_vector(1 to 3) := ( '1', '0', '1' );
begin
process is
begin
s <= "110";
foo(s, 1);
foo(s, 1);
wait;
end process;
end architecture;
|
entity proc7 is
end entity;
architecture test of proc7 is
procedure foo(signal b : in bit_vector; i : in integer) is
variable c : bit_vector(b'range);
begin
assert c(c'left) = '0';
--wait for 1 ns;
for i in b'range loop
c(i) := b(i);
end loop;
wait for 1 ns;
for i in c'range loop
report bit'image(c(i));
end loop;
end procedure;
signal s : bit_vector(1 to 3) := ( '1', '0', '1' );
begin
process is
begin
s <= "110";
foo(s, 1);
foo(s, 1);
wait;
end process;
end architecture;
|
entity proc7 is
end entity;
architecture test of proc7 is
procedure foo(signal b : in bit_vector; i : in integer) is
variable c : bit_vector(b'range);
begin
assert c(c'left) = '0';
--wait for 1 ns;
for i in b'range loop
c(i) := b(i);
end loop;
wait for 1 ns;
for i in c'range loop
report bit'image(c(i));
end loop;
end procedure;
signal s : bit_vector(1 to 3) := ( '1', '0', '1' );
begin
process is
begin
s <= "110";
foo(s, 1);
foo(s, 1);
wait;
end process;
end architecture;
|
entity proc7 is
end entity;
architecture test of proc7 is
procedure foo(signal b : in bit_vector; i : in integer) is
variable c : bit_vector(b'range);
begin
assert c(c'left) = '0';
--wait for 1 ns;
for i in b'range loop
c(i) := b(i);
end loop;
wait for 1 ns;
for i in c'range loop
report bit'image(c(i));
end loop;
end procedure;
signal s : bit_vector(1 to 3) := ( '1', '0', '1' );
begin
process is
begin
s <= "110";
foo(s, 1);
foo(s, 1);
wait;
end process;
end architecture;
|
------------------------------------------------------------------------------
-- Schedule controller; implemented as a Mealy FSM
--
-- Project :
-- File : $URL: svn+ssh://plessl@yosemite.ethz.ch/home/plessl/SVN/simzippy/trunk/vhdl/schedulectrl.vhd $
-- Authors : Rolf Enzler <enzler@ife.ee.ethz.ch>
-- Christian Plessl <plessl@tik.ee.ethz.ch>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2003-10-16
-- $Id: schedulectrl.vhd 242 2005-04-07 09:17:51Z plessl $
------------------------------------------------------------------------------
-- The schedule controller implements the sequencing of the contexts. The
-- sequence is specified in the context sequence program store (see Rolfs PhD
-- thesis pp 77ff).
--
-- The controller stays in idle mode, until the sequencing is
-- acitvated (StartxEI = '1'). After activation it switches to the
-- first context and executes it (run state) until the number of
-- execution cycles for this context has been reached (RunningSI =
-- '0'). If the last context has been executed (LastxSI=0) the
-- scheduler is stopped, otherwise the scheduler switches to the next
-- context as specified with the next address field in the instruction
-- word.
--
-- FIXME: Maybe the switch context state could be removed, thus the
-- context could be switched in a single cycle. While this doesn't
-- make much of a difference in performance when contexts are executed
-- for many cycles, it makes a differenece when the context has to be switched
-- every cycle, which is the case for certain virtualization modes.
--
-- FIXME: The sequencer could be extended to provide a little more microcode
-- features. E.g. the ability to run a certain schedule repeatedly.
--
-- FIXME: Rolf mentioned something about status flags, that can be polled from
-- CPUs. What flags can be polled?
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ScheduleCtrl is
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
StartxEI : in std_logic;
RunningxSI : in std_logic;
LastxSI : in std_logic;
SwitchxEO : out std_logic; -- initiate context switch
BusyxSO : out std_logic); -- busy status flag
end ScheduleCtrl;
architecture simple of ScheduleCtrl is
type state is (idle, switch, run);
signal currstate : state;
signal nextstate : state;
begin -- simple
--
-- computation of next state and current outputs
--
process (LastxSI, RunningxSI, StartxEI, currstate)
begin -- process
-- default assignments
nextstate <= currstate;
SwitchxEO <= '0';
BusyxSO <= '0';
-- non-default transitions and current outputs
case currstate is
when idle =>
if StartxEI = '1' then
SwitchxEO <= '1';
BusyxSO <= '1';
nextstate <= switch;
end if;
when switch =>
BusyxSO <= '1';
nextstate <= run;
when run =>
BusyxSO <= '1';
if (RunningxSI = '0') and (LastxSI = '0') then
SwitchxEO <= '1';
nextstate <= switch;
elsif (RunningxSI = '0') and (LastxSI = '1') then
nextstate <= idle;
end if;
-- have all parasitic states flow into idle state
when others =>
nextstate <= idle;
end case;
end process;
--
-- updating of state
--
process (ClkxC, RstxRB)
begin -- process
if RstxRB = '0' then -- asynchronous reset (active low)
currstate <= idle;
elsif ClkxC'event and ClkxC = '1' then -- rising clock edge
currstate <= nextstate;
end if;
end process;
end simple;
|
use std.textio.all;
entity ent is
end entity;
architecture a of ent is
begin
main : process
type binary_file is file of character;
file fptr_text : text;
file fptr_binary : binary_file;
begin
file_open(fptr_text, "file.txt", write_mode);
write(fptr_text, string'("a"));
write(fptr_text, string'("b"));
file_close(fptr_text);
file_open(fptr_binary, "file.raw", write_mode);
write(fptr_binary, character'('a'));
write(fptr_binary, character'('b'));
file_close(fptr_binary);
write(output, string'("a"));
write(output, string'("b"));
wait;
end process;
end architecture;
|
use std.textio.all;
entity ent is
end entity;
architecture a of ent is
begin
main : process
type binary_file is file of character;
file fptr_text : text;
file fptr_binary : binary_file;
begin
file_open(fptr_text, "file.txt", write_mode);
write(fptr_text, string'("a"));
write(fptr_text, string'("b"));
file_close(fptr_text);
file_open(fptr_binary, "file.raw", write_mode);
write(fptr_binary, character'('a'));
write(fptr_binary, character'('b'));
file_close(fptr_binary);
write(output, string'("a"));
write(output, string'("b"));
wait;
end process;
end architecture;
|
use std.textio.all;
entity ent is
end entity;
architecture a of ent is
begin
main : process
type binary_file is file of character;
file fptr_text : text;
file fptr_binary : binary_file;
begin
file_open(fptr_text, "file.txt", write_mode);
write(fptr_text, string'("a"));
write(fptr_text, string'("b"));
file_close(fptr_text);
file_open(fptr_binary, "file.raw", write_mode);
write(fptr_binary, character'('a'));
write(fptr_binary, character'('b'));
file_close(fptr_binary);
write(output, string'("a"));
write(output, string'("b"));
wait;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity issue3 is
port (foo : in integer;
foobar : out signed (3 downto 0));
end issue3;
architecture beh of issue3 is
subtype n_int is integer range -1 to 1;
begin
with n_int'(foo) select
foobar <= signed'("0001") when -1,
signed'("0010") when 0,
signed'("0011") when 1;
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1320.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p08n03i01320ent IS
END c08s04b00x00p08n03i01320ent;
ARCHITECTURE c08s04b00x00p08n03i01320arch OF c08s04b00x00p08n03i01320ent IS
type BIT_VECTOR is array (natural range <>) of bit;
subtype BVI is BIT_VECTOR(0 to 31);
signal S : BVI;
BEGIN
TESTING: PROCESS
BEGIN
(S(0 to 5), S(6), S(7 to 7)) <= BVI'(0 to 5 => '0', 6 => '1', others => '0');
assert FALSE
report "***FAILED TEST: c08s04b00x00p08n03i01320 - The expression in element association can not be a discrete range."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p08n03i01320arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1320.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p08n03i01320ent IS
END c08s04b00x00p08n03i01320ent;
ARCHITECTURE c08s04b00x00p08n03i01320arch OF c08s04b00x00p08n03i01320ent IS
type BIT_VECTOR is array (natural range <>) of bit;
subtype BVI is BIT_VECTOR(0 to 31);
signal S : BVI;
BEGIN
TESTING: PROCESS
BEGIN
(S(0 to 5), S(6), S(7 to 7)) <= BVI'(0 to 5 => '0', 6 => '1', others => '0');
assert FALSE
report "***FAILED TEST: c08s04b00x00p08n03i01320 - The expression in element association can not be a discrete range."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p08n03i01320arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1320.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p08n03i01320ent IS
END c08s04b00x00p08n03i01320ent;
ARCHITECTURE c08s04b00x00p08n03i01320arch OF c08s04b00x00p08n03i01320ent IS
type BIT_VECTOR is array (natural range <>) of bit;
subtype BVI is BIT_VECTOR(0 to 31);
signal S : BVI;
BEGIN
TESTING: PROCESS
BEGIN
(S(0 to 5), S(6), S(7 to 7)) <= BVI'(0 to 5 => '0', 6 => '1', others => '0');
assert FALSE
report "***FAILED TEST: c08s04b00x00p08n03i01320 - The expression in element association can not be a discrete range."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p08n03i01320arch;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
-- Thomas B. Preusser
--
-- Package: Simulation constants, functions and utilities.
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2016 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
use STD.TextIO.all;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library PoC;
use PoC.utils.all;
use PoC.strings.all;
use PoC.vectors.all;
use PoC.physical.all;
use PoC.sim_types.all;
package sim_protected is
-- Simulation Task and Status Management
-- ===========================================================================
type T_SIM_STATUS is protected
-- Initializer and Finalizer
procedure initialize;
procedure finalize;
-- Assertions
procedure fail(Message : STRING := "");
procedure assertion(Condition : BOOLEAN; Message : STRING := "");
procedure writeMessage(Message : STRING);
procedure writeReport;
-- Process Management
-- impure function registerProcess(Name : STRING; InstanceName : STRING) return T_SIM_PROCESS_ID;
impure function registerProcess(Name : STRING) return T_SIM_PROCESS_ID;
procedure deactivateProcess(procID : T_SIM_PROCESS_ID);
-- Test Management
impure function createTest(Name : STRING) return T_SIM_TEST_ID;
-- Run Management
procedure stopAllClocks;
impure function isStopped return BOOLEAN;
end protected;
end package;
package body sim_protected is
-- Simulation process and Status Management
-- ===========================================================================
type T_SIM_STATUS is protected body
-- status
variable IsInitialized : BOOLEAN := FALSE;
variable IsFinalized : BOOLEAN := FALSE;
-- Internal state variable to log a failure condition for final reporting.
-- Once de-asserted, this variable will never return to a value of true.
variable Passed : BOOLEAN := TRUE;
variable AssertCount : NATURAL := 0;
variable FailedAssertCount : NATURAL := 0;
-- Clock Management
variable MainClockEnable : BOOLEAN := TRUE;
-- Process Management
variable ProcessCount : NATURAL := 0;
variable ActiveProcessCount : NATURAL := 0;
variable Processes : T_SIM_PROCESS_VECTOR(T_SIM_PROCESS_ID);
-- Test Management
variable TestCount : NATURAL := 0;
variable Tests : T_SIM_TEST_VECTOR(T_SIM_TEST_ID);
-- Initializer
procedure initialize is
begin
IsInitialized := TRUE;
end procedure;
procedure finalize is
begin
if (IsFinalized = FALSE) then
if (ActiveProcessCount = 0) then
writeReport;
IsFinalized := TRUE;
end if;
end if;
end procedure;
procedure fail(Message : STRING := "") is
begin
if (Message'length > 0) then
report Message severity ERROR;
end if;
Passed := FALSE;
end procedure;
procedure assertion(condition : BOOLEAN; Message : STRING := "") is
begin
AssertCount := AssertCount + 1;
if (condition = FALSE) then
fail(Message);
FailedAssertCount := FailedAssertCount + 1;
end if;
end procedure;
procedure writeMessage(Message : STRING) is
variable LineBuffer : LINE;
begin
write(LineBuffer, Message);
writeline(output, LineBuffer);
end procedure;
procedure writeReport is
variable LineBuffer : LINE;
begin
write(LineBuffer, (CR & STRING'("========================================")));
write(LineBuffer, (CR & STRING'("POC TESTBENCH REPORT")));
write(LineBuffer, (CR & STRING'("========================================")));
write(LineBuffer, (CR & STRING'("Assertions ") & INTEGER'image(AssertCount)));
write(LineBuffer, (CR & STRING'(" failed ") & INTEGER'image(FailedAssertCount)));
write(LineBuffer, (CR & STRING'("Processes ") & INTEGER'image(ProcessCount)));
write(LineBuffer, (CR & STRING'(" active ") & INTEGER'image(ActiveProcessCount)));
for i in 0 to ProcessCount - 1 loop
if (Processes(i).Status = SIM_PROCESS_STATUS_ACTIVE) then
write(LineBuffer, (CR & STRING'(" ") & str_trim(Processes(i).Name)));
end if;
end loop;
write(LineBuffer, (CR & STRING'("Tests ") & INTEGER'image(TestCount)));
for i in 0 to TestCount - 1 loop
write(LineBuffer, (CR & STRING'(" ") & str_ralign(INTEGER'image(i), log10ceil(T_SIM_TEST_ID'high)) & ": " & str_trim(Tests(i).Name)));
end loop;
write(LineBuffer, (CR & STRING'("========================================")));
if (AssertCount = 0) then
write(LineBuffer, (CR & STRING'("SIMULATION RESULT = NO ASSERTS")));
elsif (Passed = TRUE) then
write(LineBuffer, (CR & STRING'("SIMULATION RESULT = PASSED")));
else
write(LineBuffer, (CR & STRING'("SIMULATION RESULT = FAILED")));
end if;
write(LineBuffer, (CR & STRING'("========================================")));
writeline(output, LineBuffer);
end procedure;
-- impure function registerProcess(Name : STRING; InstanceName : STRING) return T_SIM_PROCESS_ID is
impure function registerProcess(Name : STRING) return T_SIM_PROCESS_ID is
variable Proc : T_SIM_PROCESS;
begin
Proc.ID := ProcessCount;
Proc.Name := resize(Name, T_SIM_PROCESS_NAME'length);
-- Proc.InstanceName := resize(InstanceName, T_SIM_PROCESS_INSTNAME'length);
Proc.Status := SIM_PROCESS_STATUS_ACTIVE;
Processes(Proc.ID) := Proc;
ProcessCount := ProcessCount + 1;
ActiveProcessCount := ActiveProcessCount + 1;
return Proc.ID;
end function;
procedure deactivateProcess(ProcID : T_SIM_PROCESS_ID) is
variable hasActiveProcesses : BOOLEAN := FALSE;
begin
if (ProcID < ProcessCount) then
if (Processes(ProcID).Status = SIM_PROCESS_STATUS_ACTIVE) then
Processes(ProcID).Status := SIM_PROCESS_STATUS_ENDED;
ActiveProcessCount := ActiveProcessCount - 1;
end if;
end if;
if (ActiveProcessCount = 0) then
stopAllClocks;
end if;
end procedure;
impure function createTest(Name : STRING) return T_SIM_TEST_ID is
variable Test : T_SIM_TEST;
begin
Test.ID := TestCount;
Test.Name := resize(Name, T_SIM_TEST_NAME'length);
Test.Status := SIM_TEST_STATUS_ACTIVE;
Tests(Test.ID) := Test;
TestCount := TestCount + 1;
return Test.ID;
end function;
procedure stopAllClocks is
begin
MainClockEnable := FALSE;
end procedure;
impure function isStopped return BOOLEAN is
begin
return not MainClockEnable;
end function;
end protected body;
end package body;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
-- Thomas B. Preusser
--
-- Package: Simulation constants, functions and utilities.
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2016 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
use STD.TextIO.all;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library PoC;
use PoC.utils.all;
use PoC.strings.all;
use PoC.vectors.all;
use PoC.physical.all;
use PoC.sim_types.all;
package sim_protected is
-- Simulation Task and Status Management
-- ===========================================================================
type T_SIM_STATUS is protected
-- Initializer and Finalizer
procedure initialize;
procedure finalize;
-- Assertions
procedure fail(Message : STRING := "");
procedure assertion(Condition : BOOLEAN; Message : STRING := "");
procedure writeMessage(Message : STRING);
procedure writeReport;
-- Process Management
-- impure function registerProcess(Name : STRING; InstanceName : STRING) return T_SIM_PROCESS_ID;
impure function registerProcess(Name : STRING) return T_SIM_PROCESS_ID;
procedure deactivateProcess(procID : T_SIM_PROCESS_ID);
-- Test Management
impure function createTest(Name : STRING) return T_SIM_TEST_ID;
-- Run Management
procedure stopAllClocks;
impure function isStopped return BOOLEAN;
end protected;
end package;
package body sim_protected is
-- Simulation process and Status Management
-- ===========================================================================
type T_SIM_STATUS is protected body
-- status
variable IsInitialized : BOOLEAN := FALSE;
variable IsFinalized : BOOLEAN := FALSE;
-- Internal state variable to log a failure condition for final reporting.
-- Once de-asserted, this variable will never return to a value of true.
variable Passed : BOOLEAN := TRUE;
variable AssertCount : NATURAL := 0;
variable FailedAssertCount : NATURAL := 0;
-- Clock Management
variable MainClockEnable : BOOLEAN := TRUE;
-- Process Management
variable ProcessCount : NATURAL := 0;
variable ActiveProcessCount : NATURAL := 0;
variable Processes : T_SIM_PROCESS_VECTOR(T_SIM_PROCESS_ID);
-- Test Management
variable TestCount : NATURAL := 0;
variable Tests : T_SIM_TEST_VECTOR(T_SIM_TEST_ID);
-- Initializer
procedure initialize is
begin
IsInitialized := TRUE;
end procedure;
procedure finalize is
begin
if (IsFinalized = FALSE) then
if (ActiveProcessCount = 0) then
writeReport;
IsFinalized := TRUE;
end if;
end if;
end procedure;
procedure fail(Message : STRING := "") is
begin
if (Message'length > 0) then
report Message severity ERROR;
end if;
Passed := FALSE;
end procedure;
procedure assertion(condition : BOOLEAN; Message : STRING := "") is
begin
AssertCount := AssertCount + 1;
if (condition = FALSE) then
fail(Message);
FailedAssertCount := FailedAssertCount + 1;
end if;
end procedure;
procedure writeMessage(Message : STRING) is
variable LineBuffer : LINE;
begin
write(LineBuffer, Message);
writeline(output, LineBuffer);
end procedure;
procedure writeReport is
variable LineBuffer : LINE;
begin
write(LineBuffer, (CR & STRING'("========================================")));
write(LineBuffer, (CR & STRING'("POC TESTBENCH REPORT")));
write(LineBuffer, (CR & STRING'("========================================")));
write(LineBuffer, (CR & STRING'("Assertions ") & INTEGER'image(AssertCount)));
write(LineBuffer, (CR & STRING'(" failed ") & INTEGER'image(FailedAssertCount)));
write(LineBuffer, (CR & STRING'("Processes ") & INTEGER'image(ProcessCount)));
write(LineBuffer, (CR & STRING'(" active ") & INTEGER'image(ActiveProcessCount)));
for i in 0 to ProcessCount - 1 loop
if (Processes(i).Status = SIM_PROCESS_STATUS_ACTIVE) then
write(LineBuffer, (CR & STRING'(" ") & str_trim(Processes(i).Name)));
end if;
end loop;
write(LineBuffer, (CR & STRING'("Tests ") & INTEGER'image(TestCount)));
for i in 0 to TestCount - 1 loop
write(LineBuffer, (CR & STRING'(" ") & str_ralign(INTEGER'image(i), log10ceil(T_SIM_TEST_ID'high)) & ": " & str_trim(Tests(i).Name)));
end loop;
write(LineBuffer, (CR & STRING'("========================================")));
if (AssertCount = 0) then
write(LineBuffer, (CR & STRING'("SIMULATION RESULT = NO ASSERTS")));
elsif (Passed = TRUE) then
write(LineBuffer, (CR & STRING'("SIMULATION RESULT = PASSED")));
else
write(LineBuffer, (CR & STRING'("SIMULATION RESULT = FAILED")));
end if;
write(LineBuffer, (CR & STRING'("========================================")));
writeline(output, LineBuffer);
end procedure;
-- impure function registerProcess(Name : STRING; InstanceName : STRING) return T_SIM_PROCESS_ID is
impure function registerProcess(Name : STRING) return T_SIM_PROCESS_ID is
variable Proc : T_SIM_PROCESS;
begin
Proc.ID := ProcessCount;
Proc.Name := resize(Name, T_SIM_PROCESS_NAME'length);
-- Proc.InstanceName := resize(InstanceName, T_SIM_PROCESS_INSTNAME'length);
Proc.Status := SIM_PROCESS_STATUS_ACTIVE;
Processes(Proc.ID) := Proc;
ProcessCount := ProcessCount + 1;
ActiveProcessCount := ActiveProcessCount + 1;
return Proc.ID;
end function;
procedure deactivateProcess(ProcID : T_SIM_PROCESS_ID) is
variable hasActiveProcesses : BOOLEAN := FALSE;
begin
if (ProcID < ProcessCount) then
if (Processes(ProcID).Status = SIM_PROCESS_STATUS_ACTIVE) then
Processes(ProcID).Status := SIM_PROCESS_STATUS_ENDED;
ActiveProcessCount := ActiveProcessCount - 1;
end if;
end if;
if (ActiveProcessCount = 0) then
stopAllClocks;
end if;
end procedure;
impure function createTest(Name : STRING) return T_SIM_TEST_ID is
variable Test : T_SIM_TEST;
begin
Test.ID := TestCount;
Test.Name := resize(Name, T_SIM_TEST_NAME'length);
Test.Status := SIM_TEST_STATUS_ACTIVE;
Tests(Test.ID) := Test;
TestCount := TestCount + 1;
return Test.ID;
end function;
procedure stopAllClocks is
begin
MainClockEnable := FALSE;
end procedure;
impure function isStopped return BOOLEAN is
begin
return not MainClockEnable;
end function;
end protected body;
end package body;
|
-------------------------------------------------------------------------------
--
-- Title : ID_EXE_Register
-- Design : ALU
-- Author : riczhang
-- Company : Stony Brook University
--
-------------------------------------------------------------------------------
--
-- File : c:\My_Designs\ESE345_PROJECT\ALU\src\ID_EXE_Register.vhd
-- Generated : Wed Dec 7 15:21:24 2016
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {ID_EXE_Register} architecture {behavioral}}
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity ID_EXE_Register is
port (
rs1_in, rs2_in : in std_logic_vector(63 downto 0);
op_code_in : in std_logic_vector(3 downto 0);
rd_address_in : in std_logic_vector(3 downto 0);
rs1_out, rs2_out : out std_logic_vector(63 downto 0);
op_code_out : out std_logic_vector(3 downto 0);
rd_address_out : out std_logic_vector(3 downto 0);
clk : in std_logic
);
end ID_EXE_Register;
architecture behavioral of ID_EXE_Register is
begin
process (clk)
variable rs1_in_reg, rs2_in_reg : std_logic_vector(63 downto 0);
variable op_code_in_reg : std_logic_vector(3 downto 0) := "0000";
variable rd_address_in_reg : std_logic_vector(3 downto 0);
variable rs1_out_reg, rs2_out_reg : std_logic_vector(63 downto 0);
variable op_code_out_reg : std_logic_vector(3 downto 0) := "0000";
variable rd_address_out_reg : std_logic_vector(3 downto 0);
begin
if rising_edge(clk) then
rs1_out_reg := rs1_in_reg;
rs2_out_reg := rs2_in_reg;
op_code_out_reg := op_code_in_reg;
rd_address_out_reg := rd_address_in_reg;
rs1_in_reg := rs1_in;
rs2_in_reg := rs2_in;
op_code_in_reg := op_code_in;
rd_address_in_reg := rd_address_in;
end if;
rs1_out <= rs1_out_reg;
rs2_out <= rs2_out_reg;
op_code_out <= op_code_out_reg;
rd_address_out <= rd_address_out_reg;
end process;
end behavioral;
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/RADIX22FFT_SDNF2_4_block3.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF2_4_block3
-- Source Path: fft_16_bit/FFT HDL Optimized/RADIX22FFT_SDNF2_4
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY RADIX22FFT_SDNF2_4_block3 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
rotate_9 : IN std_logic; -- ufix1
dout_9_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20
dout_9_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20
dout_11_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20
dout_11_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_9_re_1 : OUT std_logic_vector(20 DOWNTO 0); -- sfix21
dout_9_im_1 : OUT std_logic_vector(20 DOWNTO 0); -- sfix21
dout_10_re : OUT std_logic_vector(20 DOWNTO 0); -- sfix21
dout_10_im : OUT std_logic_vector(20 DOWNTO 0); -- sfix21
dout_4_vld : OUT std_logic
);
END RADIX22FFT_SDNF2_4_block3;
ARCHITECTURE rtl OF RADIX22FFT_SDNF2_4_block3 IS
-- Signals
SIGNAL dout_9_re_signed : signed(19 DOWNTO 0); -- sfix20
SIGNAL din1_re : signed(20 DOWNTO 0); -- sfix21
SIGNAL dout_9_im_signed : signed(19 DOWNTO 0); -- sfix20
SIGNAL din1_im : signed(20 DOWNTO 0); -- sfix21
SIGNAL dout_11_re_signed : signed(19 DOWNTO 0); -- sfix20
SIGNAL din2_re : signed(20 DOWNTO 0); -- sfix21
SIGNAL dout_11_im_signed : signed(19 DOWNTO 0); -- sfix20
SIGNAL din2_im : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG2_NF_din_vld_dly : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg : signed(21 DOWNTO 0); -- sfix22
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg : signed(21 DOWNTO 0); -- sfix22
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg : signed(21 DOWNTO 0); -- sfix22
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg : signed(21 DOWNTO 0); -- sfix22
SIGNAL Radix22ButterflyG2_NF_din_vld_dly_next : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg_next : signed(21 DOWNTO 0); -- sfix22
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg_next : signed(21 DOWNTO 0); -- sfix22
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg_next : signed(21 DOWNTO 0); -- sfix22
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg_next : signed(21 DOWNTO 0); -- sfix22
SIGNAL dout_9_re_tmp : signed(20 DOWNTO 0); -- sfix21
SIGNAL dout_9_im_tmp : signed(20 DOWNTO 0); -- sfix21
SIGNAL dout_10_re_tmp : signed(20 DOWNTO 0); -- sfix21
SIGNAL dout_10_im_tmp : signed(20 DOWNTO 0); -- sfix21
BEGIN
dout_9_re_signed <= signed(dout_9_re);
din1_re <= resize(dout_9_re_signed, 21);
dout_9_im_signed <= signed(dout_9_im);
din1_im <= resize(dout_9_im_signed, 21);
dout_11_re_signed <= signed(dout_11_re);
din2_re <= resize(dout_11_re_signed, 21);
dout_11_im_signed <= signed(dout_11_im);
din2_im <= resize(dout_11_im_signed, 21);
-- Radix22ButterflyG2_NF
Radix22ButterflyG2_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= '0';
Radix22ButterflyG2_NF_btf1_re_reg <= to_signed(16#000000#, 22);
Radix22ButterflyG2_NF_btf1_im_reg <= to_signed(16#000000#, 22);
Radix22ButterflyG2_NF_btf2_re_reg <= to_signed(16#000000#, 22);
Radix22ButterflyG2_NF_btf2_im_reg <= to_signed(16#000000#, 22);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= Radix22ButterflyG2_NF_din_vld_dly_next;
Radix22ButterflyG2_NF_btf1_re_reg <= Radix22ButterflyG2_NF_btf1_re_reg_next;
Radix22ButterflyG2_NF_btf1_im_reg <= Radix22ButterflyG2_NF_btf1_im_reg_next;
Radix22ButterflyG2_NF_btf2_re_reg <= Radix22ButterflyG2_NF_btf2_re_reg_next;
Radix22ButterflyG2_NF_btf2_im_reg <= Radix22ButterflyG2_NF_btf2_im_reg_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG2_NF_process;
Radix22ButterflyG2_NF_output : PROCESS (Radix22ButterflyG2_NF_din_vld_dly, Radix22ButterflyG2_NF_btf1_re_reg,
Radix22ButterflyG2_NF_btf1_im_reg, Radix22ButterflyG2_NF_btf2_re_reg,
Radix22ButterflyG2_NF_btf2_im_reg, din1_re, din1_im, din2_re, din2_im,
dout_1_vld, rotate_9)
BEGIN
Radix22ButterflyG2_NF_btf1_re_reg_next <= Radix22ButterflyG2_NF_btf1_re_reg;
Radix22ButterflyG2_NF_btf1_im_reg_next <= Radix22ButterflyG2_NF_btf1_im_reg;
Radix22ButterflyG2_NF_btf2_re_reg_next <= Radix22ButterflyG2_NF_btf2_re_reg;
Radix22ButterflyG2_NF_btf2_im_reg_next <= Radix22ButterflyG2_NF_btf2_im_reg;
Radix22ButterflyG2_NF_din_vld_dly_next <= dout_1_vld;
IF rotate_9 /= '0' THEN
IF dout_1_vld = '1' THEN
Radix22ButterflyG2_NF_btf1_re_reg_next <= resize(din1_re, 22) + resize(din2_im, 22);
Radix22ButterflyG2_NF_btf2_re_reg_next <= resize(din1_re, 22) - resize(din2_im, 22);
Radix22ButterflyG2_NF_btf2_im_reg_next <= resize(din1_im, 22) + resize(din2_re, 22);
Radix22ButterflyG2_NF_btf1_im_reg_next <= resize(din1_im, 22) - resize(din2_re, 22);
END IF;
ELSIF dout_1_vld = '1' THEN
Radix22ButterflyG2_NF_btf1_re_reg_next <= resize(din1_re, 22) + resize(din2_re, 22);
Radix22ButterflyG2_NF_btf2_re_reg_next <= resize(din1_re, 22) - resize(din2_re, 22);
Radix22ButterflyG2_NF_btf1_im_reg_next <= resize(din1_im, 22) + resize(din2_im, 22);
Radix22ButterflyG2_NF_btf2_im_reg_next <= resize(din1_im, 22) - resize(din2_im, 22);
END IF;
dout_9_re_tmp <= Radix22ButterflyG2_NF_btf1_re_reg(20 DOWNTO 0);
dout_9_im_tmp <= Radix22ButterflyG2_NF_btf1_im_reg(20 DOWNTO 0);
dout_10_re_tmp <= Radix22ButterflyG2_NF_btf2_re_reg(20 DOWNTO 0);
dout_10_im_tmp <= Radix22ButterflyG2_NF_btf2_im_reg(20 DOWNTO 0);
dout_4_vld <= Radix22ButterflyG2_NF_din_vld_dly;
END PROCESS Radix22ButterflyG2_NF_output;
dout_10_re <= std_logic_vector(dout_10_re_tmp);
dout_10_im <= std_logic_vector(dout_10_im_tmp);
dout_9_re_1 <= std_logic_vector(dout_9_re_tmp);
dout_9_im_1 <= std_logic_vector(dout_9_im_tmp);
END rtl;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_3_exdes.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity system_axi_vdma_0_wrapper_fifo_generator_v9_3_exdes is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(7-1 DOWNTO 0);
WR_ACK : OUT std_logic;
VALID : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(67-1 DOWNTO 0);
DOUT : OUT std_logic_vector(67-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end system_axi_vdma_0_wrapper_fifo_generator_v9_3_exdes;
architecture xilinx of system_axi_vdma_0_wrapper_fifo_generator_v9_3_exdes is
signal clk_i : std_logic;
component system_axi_vdma_0_wrapper_fifo_generator_v9_3 is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(7-1 DOWNTO 0);
WR_ACK : OUT std_logic;
VALID : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(67-1 DOWNTO 0);
DOUT : OUT std_logic_vector(67-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
exdes_inst : system_axi_vdma_0_wrapper_fifo_generator_v9_3
PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
WR_ACK => wr_ack,
VALID => valid,
ALMOST_EMPTY => almost_empty,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_3_exdes.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity system_axi_vdma_0_wrapper_fifo_generator_v9_3_exdes is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(7-1 DOWNTO 0);
WR_ACK : OUT std_logic;
VALID : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(67-1 DOWNTO 0);
DOUT : OUT std_logic_vector(67-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end system_axi_vdma_0_wrapper_fifo_generator_v9_3_exdes;
architecture xilinx of system_axi_vdma_0_wrapper_fifo_generator_v9_3_exdes is
signal clk_i : std_logic;
component system_axi_vdma_0_wrapper_fifo_generator_v9_3 is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(7-1 DOWNTO 0);
WR_ACK : OUT std_logic;
VALID : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(67-1 DOWNTO 0);
DOUT : OUT std_logic_vector(67-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
exdes_inst : system_axi_vdma_0_wrapper_fifo_generator_v9_3
PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
WR_ACK => wr_ack,
VALID => valid,
ALMOST_EMPTY => almost_empty,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_3_exdes.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity system_axi_vdma_0_wrapper_fifo_generator_v9_3_exdes is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(7-1 DOWNTO 0);
WR_ACK : OUT std_logic;
VALID : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(67-1 DOWNTO 0);
DOUT : OUT std_logic_vector(67-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end system_axi_vdma_0_wrapper_fifo_generator_v9_3_exdes;
architecture xilinx of system_axi_vdma_0_wrapper_fifo_generator_v9_3_exdes is
signal clk_i : std_logic;
component system_axi_vdma_0_wrapper_fifo_generator_v9_3 is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(7-1 DOWNTO 0);
WR_ACK : OUT std_logic;
VALID : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(67-1 DOWNTO 0);
DOUT : OUT std_logic_vector(67-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
exdes_inst : system_axi_vdma_0_wrapper_fifo_generator_v9_3
PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
WR_ACK => wr_ack,
VALID => valid,
ALMOST_EMPTY => almost_empty,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1804.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p06n01i01804ent IS
END c07s01b00x00p06n01i01804ent;
ARCHITECTURE c07s01b00x00p06n01i01804arch OF c07s01b00x00p06n01i01804ent IS
BEGIN
TESTING: PROCESS
variable x : integer := 0;
variable y : integer := 2;
variable z : integer := 5;
BEGIN
x := y * 10 * z; -- No_failure_here
assert NOT( x=100 )
report "***PASSED TEST: c07s01b00x00p06n01i01804"
severity NOTE;
assert ( x=100 )
report "***FAILED TEST: c07s01b00x00p06n01i01804 - The term must be factor or a sequence of factors combined with multiplying operators."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p06n01i01804arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1804.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p06n01i01804ent IS
END c07s01b00x00p06n01i01804ent;
ARCHITECTURE c07s01b00x00p06n01i01804arch OF c07s01b00x00p06n01i01804ent IS
BEGIN
TESTING: PROCESS
variable x : integer := 0;
variable y : integer := 2;
variable z : integer := 5;
BEGIN
x := y * 10 * z; -- No_failure_here
assert NOT( x=100 )
report "***PASSED TEST: c07s01b00x00p06n01i01804"
severity NOTE;
assert ( x=100 )
report "***FAILED TEST: c07s01b00x00p06n01i01804 - The term must be factor or a sequence of factors combined with multiplying operators."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p06n01i01804arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1804.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p06n01i01804ent IS
END c07s01b00x00p06n01i01804ent;
ARCHITECTURE c07s01b00x00p06n01i01804arch OF c07s01b00x00p06n01i01804ent IS
BEGIN
TESTING: PROCESS
variable x : integer := 0;
variable y : integer := 2;
variable z : integer := 5;
BEGIN
x := y * 10 * z; -- No_failure_here
assert NOT( x=100 )
report "***PASSED TEST: c07s01b00x00p06n01i01804"
severity NOTE;
assert ( x=100 )
report "***FAILED TEST: c07s01b00x00p06n01i01804 - The term must be factor or a sequence of factors combined with multiplying operators."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p06n01i01804arch;
|
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