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-------------------------------------------------------------------------------
-- $Id: pf_dpram_select.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_dpram_select.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
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-- ** of this text at all times. **
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-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_dpram_select.vhd
--
-- Description: This vhdl design file uses three input parameters describing
-- the desired storage depth, data width, and FPGA family type.
-- From these, the design selects the optimum Block RAM
-- primitive for the basic storage element and connects them
-- in parallel to accomodate the desired data width.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_dpram_select.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- DET Oct. 7, 2001 First Version
-- - Adopted design concepts from Goran Bilski's
-- opb_bram.vhd design in the formulation of this
-- design for the Mauna Loa packet FIFO dual port
-- core function.
--
-- DET Oct-31-2001
-- - Changed the generic input parameter C_FAMILY of type string
-- back to the boolean type parameter C_VIRTEX_II. XST support
-- change.
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library unisim;
use unisim.all; -- uses BRAM primitives
-------------------------------------------------------------------------------
entity pf_dpram_select is
generic (
C_DP_DATA_WIDTH : Integer := 32;
C_DP_ADDRESS_WIDTH : Integer := 9;
C_VIRTEX_II : Boolean := true
);
port (
-- Write Port signals
Wr_rst : In std_logic;
Wr_Clk : in std_logic;
Wr_Enable : In std_logic;
Wr_Req : In std_logic;
Wr_Address : in std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1);
Wr_Data : In std_logic_vector(0 to C_DP_DATA_WIDTH-1);
-- Read Port Signals
Rd_rst : In std_logic;
Rd_Clk : in std_logic;
Rd_Enable : In std_logic;
Rd_Address : in std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1);
Rd_Data : out std_logic_vector(0 to C_DP_DATA_WIDTH-1)
);
end entity pf_dpram_select;
architecture implementation of pf_dpram_select is
Type family_type is (
any ,
x4k ,
x4ke ,
x4kl ,
x4kex ,
x4kxl ,
x4kxv ,
x4kxla ,
spartan ,
spartanxl,
spartan2 ,
spartan2e,
virtex ,
virtexe ,
virtex2 ,
virtex2p ,
unsupported
);
Type bram_prim_type is (
use_srl ,
B4_S1_S1 ,
B4_S2_S2 ,
B4_S4_S4 ,
B4_S8_S8 ,
B4_S16_S16 ,
B16_S1_S1 ,
B16_S2_S2 ,
B16_S4_S4 ,
B16_S9_S9 ,
B16_S18_S18 ,
B16_S36_S36 ,
indeterminate
);
-----------------------------------------------------------------------------
-- This function converts the input C_VIRTEX_II boolean type to an enumerated
-- type. Only Virtex and Virtex II types are currently supported. This
-- used to convert a string to a family type function but string support in
-- the synthesis tools was found to be mutually exclusive between Synplicity
-- and XST.
-----------------------------------------------------------------------------
function get_prim_family (vertex2_select : boolean) return family_type is
Variable prim_family : family_type;
begin
If (vertex2_select) Then
prim_family := virtex2;
else
prim_family := virtex;
End if;
Return (prim_family);
end function get_prim_family;
-----------------------------------------------------------------------------
-- This function chooses the optimum BRAM primitive to utilize as
-- specified by the inputs for data depth, data width, and FPGA part family.
-----------------------------------------------------------------------------
function get_bram_primitive (target_depth: integer;
target_width: integer;
family : family_type )
return bram_prim_type is
Variable primitive : bram_prim_type;
begin
Case family Is
When virtex2p | virtex2 =>
Case target_depth Is
When 1 | 2 =>
primitive := indeterminate; -- depth is too small for BRAM
-- based fifo control logic
When 4 | 8 | 16 =>
-- primitive := use_srl; -- activate when SRL FIFO incorporated
Case target_width Is -- use BRAM for now
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When 5 | 6 | 7 | 8 | 9 =>
primitive := B16_S9_S9;
When 10 | 11 | 12 | 13 | 14 |
15 | 16 | 17 | 18 =>
primitive := B16_S18_S18;
When others =>
primitive := B16_S36_S36;
End case;
when 32 | 64 | 128 | 256 | 512 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When 5 | 6 | 7 | 8 | 9 =>
primitive := B16_S9_S9;
When 10 | 11 | 12 | 13 | 14 |
15 | 16 | 17 | 18 =>
primitive := B16_S18_S18;
When others =>
primitive := B16_S36_S36;
End case;
When 1024 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When 5 | 6 | 7 | 8 | 9 =>
primitive := B16_S9_S9;
When others =>
primitive := B16_S18_S18;
End case;
When 2048 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When others =>
primitive := B16_S9_S9;
End case;
When 4096 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When others =>
primitive := B16_S4_S4;
End case;
When 8192 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When others =>
primitive := B16_S2_S2;
End case;
When 16384 =>
primitive := B16_S1_S1;
When others =>
primitive := indeterminate;
End case;
When spartan2 | spartan2e | virtex | virtexe =>
Case target_depth Is
When 1 | 2 =>
primitive := indeterminate; -- depth is too small for BRAM
-- based fifo control logic
When 4 | 8 | 16 =>
-- primitive := use_srl; -- activate this when SRL FIFO is
-- incorporated
Case target_width Is -- use BRAM for now
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When 3 | 4 =>
primitive := B4_S4_S4;
When 5 | 6 | 7 | 8 =>
primitive := B4_S8_S8;
When others =>
primitive := B4_S16_S16;
End case;
when 32 | 64 | 128 | 256 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When 3 | 4 =>
primitive := B4_S4_S4;
When 5 | 6 | 7 | 8 =>
primitive := B4_S8_S8;
When others =>
primitive := B4_S16_S16;
End case;
when 512 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When 3 | 4 =>
primitive := B4_S4_S4;
When others =>
primitive := B4_S8_S8;
End case;
When 1024 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When others =>
primitive := B4_S4_S4;
End case;
When 2048 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When others =>
primitive := B4_S2_S2;
End case;
When 4096 =>
primitive := B4_S1_S1;
When others =>
primitive := indeterminate;
End case;
When others =>
primitive := indeterminate;
End case;
Return primitive;
end function get_bram_primitive;
-----------------------------------------------------------------------------
-- This function calculates the number of BRAM primitives required as
-- specified by the inputs for data width and BRAM primitive type.
-----------------------------------------------------------------------------
function get_num_prims (bram_prim : bram_prim_type;
mem_width : integer)
return integer is
Variable bram_num : integer;
begin
Case bram_prim Is
When B16_S1_S1 | B4_S1_S1 =>
bram_num := mem_width;
When B16_S2_S2 | B4_S2_S2 =>
bram_num := (mem_width+1)/2;
When B16_S4_S4 | B4_S4_S4 =>
bram_num := (mem_width+3)/4;
When B4_S8_S8 =>
bram_num := (mem_width+7)/8;
When B16_S9_S9 =>
bram_num := (mem_width+8)/9;
When B4_S16_S16 =>
bram_num := (mem_width+15)/16;
When B16_S18_S18 =>
bram_num := (mem_width+17)/18;
When B16_S36_S36 =>
bram_num := (mem_width+35)/36;
When others =>
bram_num := 1;
End case;
Return (bram_num);
end function get_num_prims;
-- Now set the global CONSTANTS needed for IF-Generates
-- Determine the number of BRAM storage locations needed
constant FIFO_DEPTH : Integer := 2**C_DP_ADDRESS_WIDTH;
-- Convert the input C_VIRTEX_II generic boolean to enumerated type
Constant BRAM_FAMILY : family_type :=
get_prim_family(C_VIRTEX_II);
-- Select the optimum BRAM primitive to use
constant BRAM_PRIMITIVE : bram_prim_type :=
get_bram_primitive(FIFO_DEPTH,
C_DP_DATA_WIDTH,
BRAM_FAMILY);
-- Calculate how many of the selected primitives are needed
-- to populate the desired data width
constant BRAM_NUM : integer :=
get_num_prims(BRAM_PRIMITIVE,
C_DP_DATA_WIDTH);
begin -- architecture
----------------------------------------------------------------------------
-- Using VII 512 x 36 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S36_S36 : if (BRAM_PRIMITIVE = B16_S36_S36) generate
component RAMB16_S36_S36
port (DIA : in STD_LOGIC_VECTOR (31 downto 0);
DIB : in STD_LOGIC_VECTOR (31 downto 0);
DIPA : in STD_LOGIC_VECTOR (3 downto 0);
DIPB : in STD_LOGIC_VECTOR (3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in STD_LOGIC_VECTOR (8 downto 0);
ADDRB : in STD_LOGIC_VECTOR (8 downto 0);
DOA : out STD_LOGIC_VECTOR (31 downto 0);
DOB : out STD_LOGIC_VECTOR (31 downto 0);
DOPA : out STD_LOGIC_VECTOR (3 downto 0);
DOPB : out STD_LOGIC_VECTOR (3 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 9; -- 512 deep
Constant PRIM_PDBUS_WIDTH : integer := 4; -- 4 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 32; -- 4 parity data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
type pdbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_512x32 : RAMB16_S36_S36
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
DIPA => slice_a_pdbus_in(i),
DIPB => slice_b_pdbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i),
DOPA => slice_a_pdbus_out(i),
DOPB => slice_b_pdbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S36_S36;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 1024 x 18 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S18_S18 : if (BRAM_PRIMITIVE = B16_S18_S18) generate
component RAMB16_S18_S18
port (DIA : in STD_LOGIC_VECTOR (15 downto 0);
DIB : in STD_LOGIC_VECTOR (15 downto 0);
DIPA : in STD_LOGIC_VECTOR (1 downto 0);
DIPB : in STD_LOGIC_VECTOR (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in STD_LOGIC_VECTOR (9 downto 0);
ADDRB : in STD_LOGIC_VECTOR (9 downto 0);
DOA : out STD_LOGIC_VECTOR (15 downto 0);
DOB : out STD_LOGIC_VECTOR (15 downto 0);
DOPA : out STD_LOGIC_VECTOR (1 downto 0);
DOPB : out STD_LOGIC_VECTOR (1 downto 0)
);
end component;
Constant PRIM_ADDR_WIDTH : integer := 10; -- 1024 deep
Constant PRIM_PDBUS_WIDTH : integer := 2; -- 2 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 16; -- 16 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
type pdbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_1024x18 : RAMB16_S18_S18
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
DIPA => slice_a_pdbus_in(i),
DIPB => slice_b_pdbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i),
DOPA => slice_a_pdbus_out(i),
DOPB => slice_b_pdbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S18_S18;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 2048 x 9 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S9_S9 : if (BRAM_PRIMITIVE = B16_S9_S9) generate
component RAMB16_S9_S9
port (
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
DIPA : in std_logic_vector (0 downto 0);
DIPB : in std_logic_vector (0 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0);
DOPA : out std_logic_vector (0 downto 0);
DOPB : out std_logic_vector (0 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 11; -- 2048 deep
Constant PRIM_PDBUS_WIDTH : integer := 1; -- 1 parity data bit
Constant PRIM_DBUS_WIDTH : integer := 8; -- 8 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
type pdbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_2048x9 : RAMB16_S9_S9
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
DIPA => slice_a_pdbus_in(i),
DIPB => slice_b_pdbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i),
DOPA => slice_a_pdbus_out(i),
DOPB => slice_b_pdbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S9_S9;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 4096 x 4 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S4_S4 : if (BRAM_PRIMITIVE = B16_S4_S4) generate
component RAMB16_S4_S4
port (
DIA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (11 downto 0);
ADDRB : in std_logic_vector (11 downto 0);
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (3 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 12; -- 4096 deep
Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 4; -- 4 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--type pdbus_slice_array is array(BRAM_NUM downto 1) of
-- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
--slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
--slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_4096x4 : RAMB16_S4_S4
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S4_S4;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 8192 x 2 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S2_S2 : if (BRAM_PRIMITIVE = B16_S2_S2) generate
component RAMB16_S2_S2
port (
DIA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (12 downto 0);
ADDRB : in std_logic_vector (12 downto 0);
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 13; -- 8192 deep
Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 2; -- 2 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--type pdbus_slice_array is array(BRAM_NUM downto 1) of
-- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
--slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
--slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_8192x2 : RAMB16_S2_S2
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S2_S2;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 16384 x 1 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S1_S1 : if (BRAM_PRIMITIVE = B16_S1_S1) generate
component RAMB16_S1_S1
port (
DIA : in std_logic_vector (0 downto 0);
DIB : in std_logic_vector (0 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (13 downto 0);
ADDRB : in std_logic_vector (13 downto 0);
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (0 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 14; -- 16384 deep
Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 1; -- 1 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--type pdbus_slice_array is array(BRAM_NUM downto 1) of
-- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
--slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
--slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_16384x1 : RAMB16_S1_S1
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S1_S1;
--==========================================================================
-- End of Virtex-II and Virtex-II Pro support
--///////////////////////////////////////////////////////////////////////////
--///////////////////////////////////////////////////////////////////////////
-- Start Spartan-II, Spartan-IIE, Virtex, and VirtexE support
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 4096 x 1 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S1_S1 : if (BRAM_PRIMITIVE = B4_S1_S1) generate
component RAMB4_S1_S1
port (
DIA : in std_logic_vector (0 downto 0);
DIB : in std_logic_vector (0 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (11 downto 0);
ADDRB : in std_logic_vector (11 downto 0);
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (0 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 12; -- 4096 deep
Constant PRIM_DBUS_WIDTH : integer := 1; -- 1 data bit
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_4096x1 : RAMB4_S1_S1
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S1_S1;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 2048 x 2 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S2_S2 : if (BRAM_PRIMITIVE = B4_S2_S2) generate
component RAMB4_S2_S2
port (
DIA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 11; -- 2048 deep
Constant PRIM_DBUS_WIDTH : integer := 2; -- 2 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_2048x2 : RAMB4_S2_S2
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S2_S2;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 1024 x 4 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S4_S4 : if (BRAM_PRIMITIVE = B4_S4_S4) generate
component RAMB4_S4_S4
port (
DIA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (9 downto 0);
ADDRB : in std_logic_vector (9 downto 0);
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (3 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 10; -- 1024 deep
Constant PRIM_DBUS_WIDTH : integer := 4; -- 4 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_1024x4 : RAMB4_S4_S4
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S4_S4;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 512 x 8 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S8_S8 : if (BRAM_PRIMITIVE = B4_S8_S8) generate
component RAMB4_S8_S8
port (
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (8 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 9; -- 512 deep
Constant PRIM_DBUS_WIDTH : integer := 8; -- 8 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_512x8 : RAMB4_S8_S8
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S8_S8;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 256 x 16 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S16_S16 : if (BRAM_PRIMITIVE = B4_S16_S16) generate
component RAMB4_S16_S16
port (DIA : in STD_LOGIC_VECTOR (15 downto 0);
DIB : in STD_LOGIC_VECTOR (15 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in STD_LOGIC_VECTOR (7 downto 0);
ADDRB : in STD_LOGIC_VECTOR (7 downto 0);
DOA : out STD_LOGIC_VECTOR (15 downto 0);
DOB : out STD_LOGIC_VECTOR (15 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 8; -- 256 deep
Constant PRIM_DBUS_WIDTH : integer := 16; -- 16 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_256x16 : RAMB4_S16_S16
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S16_S16;
--==========================================================================
UNSUPPORTED_FAMILY : if (BRAM_PRIMITIVE = indeterminate) generate
begin
-- assert (false)
-- report "Unsupported Part Family Selected or FIFO Depth/Width is invalid!"
-- severity failure;
--
end generate UNSUPPORTED_FAMILY;
end architecture implementation;
|
-------------------------------------------------------------------------------
-- $Id: pf_dpram_select.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_dpram_select.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_dpram_select.vhd
--
-- Description: This vhdl design file uses three input parameters describing
-- the desired storage depth, data width, and FPGA family type.
-- From these, the design selects the optimum Block RAM
-- primitive for the basic storage element and connects them
-- in parallel to accomodate the desired data width.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_dpram_select.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- DET Oct. 7, 2001 First Version
-- - Adopted design concepts from Goran Bilski's
-- opb_bram.vhd design in the formulation of this
-- design for the Mauna Loa packet FIFO dual port
-- core function.
--
-- DET Oct-31-2001
-- - Changed the generic input parameter C_FAMILY of type string
-- back to the boolean type parameter C_VIRTEX_II. XST support
-- change.
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library unisim;
use unisim.all; -- uses BRAM primitives
-------------------------------------------------------------------------------
entity pf_dpram_select is
generic (
C_DP_DATA_WIDTH : Integer := 32;
C_DP_ADDRESS_WIDTH : Integer := 9;
C_VIRTEX_II : Boolean := true
);
port (
-- Write Port signals
Wr_rst : In std_logic;
Wr_Clk : in std_logic;
Wr_Enable : In std_logic;
Wr_Req : In std_logic;
Wr_Address : in std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1);
Wr_Data : In std_logic_vector(0 to C_DP_DATA_WIDTH-1);
-- Read Port Signals
Rd_rst : In std_logic;
Rd_Clk : in std_logic;
Rd_Enable : In std_logic;
Rd_Address : in std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1);
Rd_Data : out std_logic_vector(0 to C_DP_DATA_WIDTH-1)
);
end entity pf_dpram_select;
architecture implementation of pf_dpram_select is
Type family_type is (
any ,
x4k ,
x4ke ,
x4kl ,
x4kex ,
x4kxl ,
x4kxv ,
x4kxla ,
spartan ,
spartanxl,
spartan2 ,
spartan2e,
virtex ,
virtexe ,
virtex2 ,
virtex2p ,
unsupported
);
Type bram_prim_type is (
use_srl ,
B4_S1_S1 ,
B4_S2_S2 ,
B4_S4_S4 ,
B4_S8_S8 ,
B4_S16_S16 ,
B16_S1_S1 ,
B16_S2_S2 ,
B16_S4_S4 ,
B16_S9_S9 ,
B16_S18_S18 ,
B16_S36_S36 ,
indeterminate
);
-----------------------------------------------------------------------------
-- This function converts the input C_VIRTEX_II boolean type to an enumerated
-- type. Only Virtex and Virtex II types are currently supported. This
-- used to convert a string to a family type function but string support in
-- the synthesis tools was found to be mutually exclusive between Synplicity
-- and XST.
-----------------------------------------------------------------------------
function get_prim_family (vertex2_select : boolean) return family_type is
Variable prim_family : family_type;
begin
If (vertex2_select) Then
prim_family := virtex2;
else
prim_family := virtex;
End if;
Return (prim_family);
end function get_prim_family;
-----------------------------------------------------------------------------
-- This function chooses the optimum BRAM primitive to utilize as
-- specified by the inputs for data depth, data width, and FPGA part family.
-----------------------------------------------------------------------------
function get_bram_primitive (target_depth: integer;
target_width: integer;
family : family_type )
return bram_prim_type is
Variable primitive : bram_prim_type;
begin
Case family Is
When virtex2p | virtex2 =>
Case target_depth Is
When 1 | 2 =>
primitive := indeterminate; -- depth is too small for BRAM
-- based fifo control logic
When 4 | 8 | 16 =>
-- primitive := use_srl; -- activate when SRL FIFO incorporated
Case target_width Is -- use BRAM for now
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When 5 | 6 | 7 | 8 | 9 =>
primitive := B16_S9_S9;
When 10 | 11 | 12 | 13 | 14 |
15 | 16 | 17 | 18 =>
primitive := B16_S18_S18;
When others =>
primitive := B16_S36_S36;
End case;
when 32 | 64 | 128 | 256 | 512 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When 5 | 6 | 7 | 8 | 9 =>
primitive := B16_S9_S9;
When 10 | 11 | 12 | 13 | 14 |
15 | 16 | 17 | 18 =>
primitive := B16_S18_S18;
When others =>
primitive := B16_S36_S36;
End case;
When 1024 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When 5 | 6 | 7 | 8 | 9 =>
primitive := B16_S9_S9;
When others =>
primitive := B16_S18_S18;
End case;
When 2048 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When others =>
primitive := B16_S9_S9;
End case;
When 4096 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When others =>
primitive := B16_S4_S4;
End case;
When 8192 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When others =>
primitive := B16_S2_S2;
End case;
When 16384 =>
primitive := B16_S1_S1;
When others =>
primitive := indeterminate;
End case;
When spartan2 | spartan2e | virtex | virtexe =>
Case target_depth Is
When 1 | 2 =>
primitive := indeterminate; -- depth is too small for BRAM
-- based fifo control logic
When 4 | 8 | 16 =>
-- primitive := use_srl; -- activate this when SRL FIFO is
-- incorporated
Case target_width Is -- use BRAM for now
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When 3 | 4 =>
primitive := B4_S4_S4;
When 5 | 6 | 7 | 8 =>
primitive := B4_S8_S8;
When others =>
primitive := B4_S16_S16;
End case;
when 32 | 64 | 128 | 256 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When 3 | 4 =>
primitive := B4_S4_S4;
When 5 | 6 | 7 | 8 =>
primitive := B4_S8_S8;
When others =>
primitive := B4_S16_S16;
End case;
when 512 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When 3 | 4 =>
primitive := B4_S4_S4;
When others =>
primitive := B4_S8_S8;
End case;
When 1024 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When others =>
primitive := B4_S4_S4;
End case;
When 2048 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When others =>
primitive := B4_S2_S2;
End case;
When 4096 =>
primitive := B4_S1_S1;
When others =>
primitive := indeterminate;
End case;
When others =>
primitive := indeterminate;
End case;
Return primitive;
end function get_bram_primitive;
-----------------------------------------------------------------------------
-- This function calculates the number of BRAM primitives required as
-- specified by the inputs for data width and BRAM primitive type.
-----------------------------------------------------------------------------
function get_num_prims (bram_prim : bram_prim_type;
mem_width : integer)
return integer is
Variable bram_num : integer;
begin
Case bram_prim Is
When B16_S1_S1 | B4_S1_S1 =>
bram_num := mem_width;
When B16_S2_S2 | B4_S2_S2 =>
bram_num := (mem_width+1)/2;
When B16_S4_S4 | B4_S4_S4 =>
bram_num := (mem_width+3)/4;
When B4_S8_S8 =>
bram_num := (mem_width+7)/8;
When B16_S9_S9 =>
bram_num := (mem_width+8)/9;
When B4_S16_S16 =>
bram_num := (mem_width+15)/16;
When B16_S18_S18 =>
bram_num := (mem_width+17)/18;
When B16_S36_S36 =>
bram_num := (mem_width+35)/36;
When others =>
bram_num := 1;
End case;
Return (bram_num);
end function get_num_prims;
-- Now set the global CONSTANTS needed for IF-Generates
-- Determine the number of BRAM storage locations needed
constant FIFO_DEPTH : Integer := 2**C_DP_ADDRESS_WIDTH;
-- Convert the input C_VIRTEX_II generic boolean to enumerated type
Constant BRAM_FAMILY : family_type :=
get_prim_family(C_VIRTEX_II);
-- Select the optimum BRAM primitive to use
constant BRAM_PRIMITIVE : bram_prim_type :=
get_bram_primitive(FIFO_DEPTH,
C_DP_DATA_WIDTH,
BRAM_FAMILY);
-- Calculate how many of the selected primitives are needed
-- to populate the desired data width
constant BRAM_NUM : integer :=
get_num_prims(BRAM_PRIMITIVE,
C_DP_DATA_WIDTH);
begin -- architecture
----------------------------------------------------------------------------
-- Using VII 512 x 36 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S36_S36 : if (BRAM_PRIMITIVE = B16_S36_S36) generate
component RAMB16_S36_S36
port (DIA : in STD_LOGIC_VECTOR (31 downto 0);
DIB : in STD_LOGIC_VECTOR (31 downto 0);
DIPA : in STD_LOGIC_VECTOR (3 downto 0);
DIPB : in STD_LOGIC_VECTOR (3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in STD_LOGIC_VECTOR (8 downto 0);
ADDRB : in STD_LOGIC_VECTOR (8 downto 0);
DOA : out STD_LOGIC_VECTOR (31 downto 0);
DOB : out STD_LOGIC_VECTOR (31 downto 0);
DOPA : out STD_LOGIC_VECTOR (3 downto 0);
DOPB : out STD_LOGIC_VECTOR (3 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 9; -- 512 deep
Constant PRIM_PDBUS_WIDTH : integer := 4; -- 4 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 32; -- 4 parity data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
type pdbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_512x32 : RAMB16_S36_S36
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
DIPA => slice_a_pdbus_in(i),
DIPB => slice_b_pdbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i),
DOPA => slice_a_pdbus_out(i),
DOPB => slice_b_pdbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S36_S36;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 1024 x 18 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S18_S18 : if (BRAM_PRIMITIVE = B16_S18_S18) generate
component RAMB16_S18_S18
port (DIA : in STD_LOGIC_VECTOR (15 downto 0);
DIB : in STD_LOGIC_VECTOR (15 downto 0);
DIPA : in STD_LOGIC_VECTOR (1 downto 0);
DIPB : in STD_LOGIC_VECTOR (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in STD_LOGIC_VECTOR (9 downto 0);
ADDRB : in STD_LOGIC_VECTOR (9 downto 0);
DOA : out STD_LOGIC_VECTOR (15 downto 0);
DOB : out STD_LOGIC_VECTOR (15 downto 0);
DOPA : out STD_LOGIC_VECTOR (1 downto 0);
DOPB : out STD_LOGIC_VECTOR (1 downto 0)
);
end component;
Constant PRIM_ADDR_WIDTH : integer := 10; -- 1024 deep
Constant PRIM_PDBUS_WIDTH : integer := 2; -- 2 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 16; -- 16 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
type pdbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_1024x18 : RAMB16_S18_S18
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
DIPA => slice_a_pdbus_in(i),
DIPB => slice_b_pdbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i),
DOPA => slice_a_pdbus_out(i),
DOPB => slice_b_pdbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S18_S18;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 2048 x 9 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S9_S9 : if (BRAM_PRIMITIVE = B16_S9_S9) generate
component RAMB16_S9_S9
port (
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
DIPA : in std_logic_vector (0 downto 0);
DIPB : in std_logic_vector (0 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0);
DOPA : out std_logic_vector (0 downto 0);
DOPB : out std_logic_vector (0 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 11; -- 2048 deep
Constant PRIM_PDBUS_WIDTH : integer := 1; -- 1 parity data bit
Constant PRIM_DBUS_WIDTH : integer := 8; -- 8 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
type pdbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_2048x9 : RAMB16_S9_S9
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
DIPA => slice_a_pdbus_in(i),
DIPB => slice_b_pdbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i),
DOPA => slice_a_pdbus_out(i),
DOPB => slice_b_pdbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S9_S9;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 4096 x 4 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S4_S4 : if (BRAM_PRIMITIVE = B16_S4_S4) generate
component RAMB16_S4_S4
port (
DIA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (11 downto 0);
ADDRB : in std_logic_vector (11 downto 0);
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (3 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 12; -- 4096 deep
Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 4; -- 4 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--type pdbus_slice_array is array(BRAM_NUM downto 1) of
-- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
--slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
--slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_4096x4 : RAMB16_S4_S4
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S4_S4;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 8192 x 2 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S2_S2 : if (BRAM_PRIMITIVE = B16_S2_S2) generate
component RAMB16_S2_S2
port (
DIA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (12 downto 0);
ADDRB : in std_logic_vector (12 downto 0);
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 13; -- 8192 deep
Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 2; -- 2 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--type pdbus_slice_array is array(BRAM_NUM downto 1) of
-- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
--slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
--slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_8192x2 : RAMB16_S2_S2
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S2_S2;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 16384 x 1 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S1_S1 : if (BRAM_PRIMITIVE = B16_S1_S1) generate
component RAMB16_S1_S1
port (
DIA : in std_logic_vector (0 downto 0);
DIB : in std_logic_vector (0 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (13 downto 0);
ADDRB : in std_logic_vector (13 downto 0);
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (0 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 14; -- 16384 deep
Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 1; -- 1 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--type pdbus_slice_array is array(BRAM_NUM downto 1) of
-- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
--slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
--slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_16384x1 : RAMB16_S1_S1
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S1_S1;
--==========================================================================
-- End of Virtex-II and Virtex-II Pro support
--///////////////////////////////////////////////////////////////////////////
--///////////////////////////////////////////////////////////////////////////
-- Start Spartan-II, Spartan-IIE, Virtex, and VirtexE support
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 4096 x 1 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S1_S1 : if (BRAM_PRIMITIVE = B4_S1_S1) generate
component RAMB4_S1_S1
port (
DIA : in std_logic_vector (0 downto 0);
DIB : in std_logic_vector (0 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (11 downto 0);
ADDRB : in std_logic_vector (11 downto 0);
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (0 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 12; -- 4096 deep
Constant PRIM_DBUS_WIDTH : integer := 1; -- 1 data bit
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_4096x1 : RAMB4_S1_S1
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S1_S1;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 2048 x 2 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S2_S2 : if (BRAM_PRIMITIVE = B4_S2_S2) generate
component RAMB4_S2_S2
port (
DIA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 11; -- 2048 deep
Constant PRIM_DBUS_WIDTH : integer := 2; -- 2 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_2048x2 : RAMB4_S2_S2
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S2_S2;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 1024 x 4 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S4_S4 : if (BRAM_PRIMITIVE = B4_S4_S4) generate
component RAMB4_S4_S4
port (
DIA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (9 downto 0);
ADDRB : in std_logic_vector (9 downto 0);
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (3 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 10; -- 1024 deep
Constant PRIM_DBUS_WIDTH : integer := 4; -- 4 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_1024x4 : RAMB4_S4_S4
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S4_S4;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 512 x 8 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S8_S8 : if (BRAM_PRIMITIVE = B4_S8_S8) generate
component RAMB4_S8_S8
port (
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (8 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 9; -- 512 deep
Constant PRIM_DBUS_WIDTH : integer := 8; -- 8 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_512x8 : RAMB4_S8_S8
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S8_S8;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 256 x 16 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S16_S16 : if (BRAM_PRIMITIVE = B4_S16_S16) generate
component RAMB4_S16_S16
port (DIA : in STD_LOGIC_VECTOR (15 downto 0);
DIB : in STD_LOGIC_VECTOR (15 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in STD_LOGIC_VECTOR (7 downto 0);
ADDRB : in STD_LOGIC_VECTOR (7 downto 0);
DOA : out STD_LOGIC_VECTOR (15 downto 0);
DOB : out STD_LOGIC_VECTOR (15 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 8; -- 256 deep
Constant PRIM_DBUS_WIDTH : integer := 16; -- 16 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_256x16 : RAMB4_S16_S16
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S16_S16;
--==========================================================================
UNSUPPORTED_FAMILY : if (BRAM_PRIMITIVE = indeterminate) generate
begin
-- assert (false)
-- report "Unsupported Part Family Selected or FIFO Depth/Width is invalid!"
-- severity failure;
--
end generate UNSUPPORTED_FAMILY;
end architecture implementation;
|
-------------------------------------------------------------------------------
-- $Id: pf_dpram_select.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_dpram_select.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_dpram_select.vhd
--
-- Description: This vhdl design file uses three input parameters describing
-- the desired storage depth, data width, and FPGA family type.
-- From these, the design selects the optimum Block RAM
-- primitive for the basic storage element and connects them
-- in parallel to accomodate the desired data width.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_dpram_select.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- DET Oct. 7, 2001 First Version
-- - Adopted design concepts from Goran Bilski's
-- opb_bram.vhd design in the formulation of this
-- design for the Mauna Loa packet FIFO dual port
-- core function.
--
-- DET Oct-31-2001
-- - Changed the generic input parameter C_FAMILY of type string
-- back to the boolean type parameter C_VIRTEX_II. XST support
-- change.
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library unisim;
use unisim.all; -- uses BRAM primitives
-------------------------------------------------------------------------------
entity pf_dpram_select is
generic (
C_DP_DATA_WIDTH : Integer := 32;
C_DP_ADDRESS_WIDTH : Integer := 9;
C_VIRTEX_II : Boolean := true
);
port (
-- Write Port signals
Wr_rst : In std_logic;
Wr_Clk : in std_logic;
Wr_Enable : In std_logic;
Wr_Req : In std_logic;
Wr_Address : in std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1);
Wr_Data : In std_logic_vector(0 to C_DP_DATA_WIDTH-1);
-- Read Port Signals
Rd_rst : In std_logic;
Rd_Clk : in std_logic;
Rd_Enable : In std_logic;
Rd_Address : in std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1);
Rd_Data : out std_logic_vector(0 to C_DP_DATA_WIDTH-1)
);
end entity pf_dpram_select;
architecture implementation of pf_dpram_select is
Type family_type is (
any ,
x4k ,
x4ke ,
x4kl ,
x4kex ,
x4kxl ,
x4kxv ,
x4kxla ,
spartan ,
spartanxl,
spartan2 ,
spartan2e,
virtex ,
virtexe ,
virtex2 ,
virtex2p ,
unsupported
);
Type bram_prim_type is (
use_srl ,
B4_S1_S1 ,
B4_S2_S2 ,
B4_S4_S4 ,
B4_S8_S8 ,
B4_S16_S16 ,
B16_S1_S1 ,
B16_S2_S2 ,
B16_S4_S4 ,
B16_S9_S9 ,
B16_S18_S18 ,
B16_S36_S36 ,
indeterminate
);
-----------------------------------------------------------------------------
-- This function converts the input C_VIRTEX_II boolean type to an enumerated
-- type. Only Virtex and Virtex II types are currently supported. This
-- used to convert a string to a family type function but string support in
-- the synthesis tools was found to be mutually exclusive between Synplicity
-- and XST.
-----------------------------------------------------------------------------
function get_prim_family (vertex2_select : boolean) return family_type is
Variable prim_family : family_type;
begin
If (vertex2_select) Then
prim_family := virtex2;
else
prim_family := virtex;
End if;
Return (prim_family);
end function get_prim_family;
-----------------------------------------------------------------------------
-- This function chooses the optimum BRAM primitive to utilize as
-- specified by the inputs for data depth, data width, and FPGA part family.
-----------------------------------------------------------------------------
function get_bram_primitive (target_depth: integer;
target_width: integer;
family : family_type )
return bram_prim_type is
Variable primitive : bram_prim_type;
begin
Case family Is
When virtex2p | virtex2 =>
Case target_depth Is
When 1 | 2 =>
primitive := indeterminate; -- depth is too small for BRAM
-- based fifo control logic
When 4 | 8 | 16 =>
-- primitive := use_srl; -- activate when SRL FIFO incorporated
Case target_width Is -- use BRAM for now
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When 5 | 6 | 7 | 8 | 9 =>
primitive := B16_S9_S9;
When 10 | 11 | 12 | 13 | 14 |
15 | 16 | 17 | 18 =>
primitive := B16_S18_S18;
When others =>
primitive := B16_S36_S36;
End case;
when 32 | 64 | 128 | 256 | 512 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When 5 | 6 | 7 | 8 | 9 =>
primitive := B16_S9_S9;
When 10 | 11 | 12 | 13 | 14 |
15 | 16 | 17 | 18 =>
primitive := B16_S18_S18;
When others =>
primitive := B16_S36_S36;
End case;
When 1024 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When 5 | 6 | 7 | 8 | 9 =>
primitive := B16_S9_S9;
When others =>
primitive := B16_S18_S18;
End case;
When 2048 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When others =>
primitive := B16_S9_S9;
End case;
When 4096 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When others =>
primitive := B16_S4_S4;
End case;
When 8192 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When others =>
primitive := B16_S2_S2;
End case;
When 16384 =>
primitive := B16_S1_S1;
When others =>
primitive := indeterminate;
End case;
When spartan2 | spartan2e | virtex | virtexe =>
Case target_depth Is
When 1 | 2 =>
primitive := indeterminate; -- depth is too small for BRAM
-- based fifo control logic
When 4 | 8 | 16 =>
-- primitive := use_srl; -- activate this when SRL FIFO is
-- incorporated
Case target_width Is -- use BRAM for now
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When 3 | 4 =>
primitive := B4_S4_S4;
When 5 | 6 | 7 | 8 =>
primitive := B4_S8_S8;
When others =>
primitive := B4_S16_S16;
End case;
when 32 | 64 | 128 | 256 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When 3 | 4 =>
primitive := B4_S4_S4;
When 5 | 6 | 7 | 8 =>
primitive := B4_S8_S8;
When others =>
primitive := B4_S16_S16;
End case;
when 512 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When 3 | 4 =>
primitive := B4_S4_S4;
When others =>
primitive := B4_S8_S8;
End case;
When 1024 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When others =>
primitive := B4_S4_S4;
End case;
When 2048 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When others =>
primitive := B4_S2_S2;
End case;
When 4096 =>
primitive := B4_S1_S1;
When others =>
primitive := indeterminate;
End case;
When others =>
primitive := indeterminate;
End case;
Return primitive;
end function get_bram_primitive;
-----------------------------------------------------------------------------
-- This function calculates the number of BRAM primitives required as
-- specified by the inputs for data width and BRAM primitive type.
-----------------------------------------------------------------------------
function get_num_prims (bram_prim : bram_prim_type;
mem_width : integer)
return integer is
Variable bram_num : integer;
begin
Case bram_prim Is
When B16_S1_S1 | B4_S1_S1 =>
bram_num := mem_width;
When B16_S2_S2 | B4_S2_S2 =>
bram_num := (mem_width+1)/2;
When B16_S4_S4 | B4_S4_S4 =>
bram_num := (mem_width+3)/4;
When B4_S8_S8 =>
bram_num := (mem_width+7)/8;
When B16_S9_S9 =>
bram_num := (mem_width+8)/9;
When B4_S16_S16 =>
bram_num := (mem_width+15)/16;
When B16_S18_S18 =>
bram_num := (mem_width+17)/18;
When B16_S36_S36 =>
bram_num := (mem_width+35)/36;
When others =>
bram_num := 1;
End case;
Return (bram_num);
end function get_num_prims;
-- Now set the global CONSTANTS needed for IF-Generates
-- Determine the number of BRAM storage locations needed
constant FIFO_DEPTH : Integer := 2**C_DP_ADDRESS_WIDTH;
-- Convert the input C_VIRTEX_II generic boolean to enumerated type
Constant BRAM_FAMILY : family_type :=
get_prim_family(C_VIRTEX_II);
-- Select the optimum BRAM primitive to use
constant BRAM_PRIMITIVE : bram_prim_type :=
get_bram_primitive(FIFO_DEPTH,
C_DP_DATA_WIDTH,
BRAM_FAMILY);
-- Calculate how many of the selected primitives are needed
-- to populate the desired data width
constant BRAM_NUM : integer :=
get_num_prims(BRAM_PRIMITIVE,
C_DP_DATA_WIDTH);
begin -- architecture
----------------------------------------------------------------------------
-- Using VII 512 x 36 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S36_S36 : if (BRAM_PRIMITIVE = B16_S36_S36) generate
component RAMB16_S36_S36
port (DIA : in STD_LOGIC_VECTOR (31 downto 0);
DIB : in STD_LOGIC_VECTOR (31 downto 0);
DIPA : in STD_LOGIC_VECTOR (3 downto 0);
DIPB : in STD_LOGIC_VECTOR (3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in STD_LOGIC_VECTOR (8 downto 0);
ADDRB : in STD_LOGIC_VECTOR (8 downto 0);
DOA : out STD_LOGIC_VECTOR (31 downto 0);
DOB : out STD_LOGIC_VECTOR (31 downto 0);
DOPA : out STD_LOGIC_VECTOR (3 downto 0);
DOPB : out STD_LOGIC_VECTOR (3 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 9; -- 512 deep
Constant PRIM_PDBUS_WIDTH : integer := 4; -- 4 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 32; -- 4 parity data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
type pdbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_512x32 : RAMB16_S36_S36
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
DIPA => slice_a_pdbus_in(i),
DIPB => slice_b_pdbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i),
DOPA => slice_a_pdbus_out(i),
DOPB => slice_b_pdbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S36_S36;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 1024 x 18 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S18_S18 : if (BRAM_PRIMITIVE = B16_S18_S18) generate
component RAMB16_S18_S18
port (DIA : in STD_LOGIC_VECTOR (15 downto 0);
DIB : in STD_LOGIC_VECTOR (15 downto 0);
DIPA : in STD_LOGIC_VECTOR (1 downto 0);
DIPB : in STD_LOGIC_VECTOR (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in STD_LOGIC_VECTOR (9 downto 0);
ADDRB : in STD_LOGIC_VECTOR (9 downto 0);
DOA : out STD_LOGIC_VECTOR (15 downto 0);
DOB : out STD_LOGIC_VECTOR (15 downto 0);
DOPA : out STD_LOGIC_VECTOR (1 downto 0);
DOPB : out STD_LOGIC_VECTOR (1 downto 0)
);
end component;
Constant PRIM_ADDR_WIDTH : integer := 10; -- 1024 deep
Constant PRIM_PDBUS_WIDTH : integer := 2; -- 2 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 16; -- 16 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
type pdbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_1024x18 : RAMB16_S18_S18
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
DIPA => slice_a_pdbus_in(i),
DIPB => slice_b_pdbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i),
DOPA => slice_a_pdbus_out(i),
DOPB => slice_b_pdbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S18_S18;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 2048 x 9 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S9_S9 : if (BRAM_PRIMITIVE = B16_S9_S9) generate
component RAMB16_S9_S9
port (
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
DIPA : in std_logic_vector (0 downto 0);
DIPB : in std_logic_vector (0 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0);
DOPA : out std_logic_vector (0 downto 0);
DOPB : out std_logic_vector (0 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 11; -- 2048 deep
Constant PRIM_PDBUS_WIDTH : integer := 1; -- 1 parity data bit
Constant PRIM_DBUS_WIDTH : integer := 8; -- 8 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
type pdbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_2048x9 : RAMB16_S9_S9
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
DIPA => slice_a_pdbus_in(i),
DIPB => slice_b_pdbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i),
DOPA => slice_a_pdbus_out(i),
DOPB => slice_b_pdbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S9_S9;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 4096 x 4 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S4_S4 : if (BRAM_PRIMITIVE = B16_S4_S4) generate
component RAMB16_S4_S4
port (
DIA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (11 downto 0);
ADDRB : in std_logic_vector (11 downto 0);
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (3 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 12; -- 4096 deep
Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 4; -- 4 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--type pdbus_slice_array is array(BRAM_NUM downto 1) of
-- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
--slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
--slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_4096x4 : RAMB16_S4_S4
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S4_S4;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 8192 x 2 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S2_S2 : if (BRAM_PRIMITIVE = B16_S2_S2) generate
component RAMB16_S2_S2
port (
DIA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (12 downto 0);
ADDRB : in std_logic_vector (12 downto 0);
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 13; -- 8192 deep
Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 2; -- 2 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--type pdbus_slice_array is array(BRAM_NUM downto 1) of
-- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
--slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
--slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_8192x2 : RAMB16_S2_S2
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S2_S2;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 16384 x 1 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S1_S1 : if (BRAM_PRIMITIVE = B16_S1_S1) generate
component RAMB16_S1_S1
port (
DIA : in std_logic_vector (0 downto 0);
DIB : in std_logic_vector (0 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (13 downto 0);
ADDRB : in std_logic_vector (13 downto 0);
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (0 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 14; -- 16384 deep
Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 1; -- 1 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--type pdbus_slice_array is array(BRAM_NUM downto 1) of
-- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
--slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
--slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_16384x1 : RAMB16_S1_S1
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S1_S1;
--==========================================================================
-- End of Virtex-II and Virtex-II Pro support
--///////////////////////////////////////////////////////////////////////////
--///////////////////////////////////////////////////////////////////////////
-- Start Spartan-II, Spartan-IIE, Virtex, and VirtexE support
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 4096 x 1 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S1_S1 : if (BRAM_PRIMITIVE = B4_S1_S1) generate
component RAMB4_S1_S1
port (
DIA : in std_logic_vector (0 downto 0);
DIB : in std_logic_vector (0 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (11 downto 0);
ADDRB : in std_logic_vector (11 downto 0);
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (0 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 12; -- 4096 deep
Constant PRIM_DBUS_WIDTH : integer := 1; -- 1 data bit
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_4096x1 : RAMB4_S1_S1
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S1_S1;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 2048 x 2 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S2_S2 : if (BRAM_PRIMITIVE = B4_S2_S2) generate
component RAMB4_S2_S2
port (
DIA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 11; -- 2048 deep
Constant PRIM_DBUS_WIDTH : integer := 2; -- 2 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_2048x2 : RAMB4_S2_S2
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S2_S2;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 1024 x 4 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S4_S4 : if (BRAM_PRIMITIVE = B4_S4_S4) generate
component RAMB4_S4_S4
port (
DIA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (9 downto 0);
ADDRB : in std_logic_vector (9 downto 0);
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (3 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 10; -- 1024 deep
Constant PRIM_DBUS_WIDTH : integer := 4; -- 4 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_1024x4 : RAMB4_S4_S4
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S4_S4;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 512 x 8 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S8_S8 : if (BRAM_PRIMITIVE = B4_S8_S8) generate
component RAMB4_S8_S8
port (
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (8 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 9; -- 512 deep
Constant PRIM_DBUS_WIDTH : integer := 8; -- 8 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_512x8 : RAMB4_S8_S8
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S8_S8;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 256 x 16 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S16_S16 : if (BRAM_PRIMITIVE = B4_S16_S16) generate
component RAMB4_S16_S16
port (DIA : in STD_LOGIC_VECTOR (15 downto 0);
DIB : in STD_LOGIC_VECTOR (15 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in STD_LOGIC_VECTOR (7 downto 0);
ADDRB : in STD_LOGIC_VECTOR (7 downto 0);
DOA : out STD_LOGIC_VECTOR (15 downto 0);
DOB : out STD_LOGIC_VECTOR (15 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 8; -- 256 deep
Constant PRIM_DBUS_WIDTH : integer := 16; -- 16 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_256x16 : RAMB4_S16_S16
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S16_S16;
--==========================================================================
UNSUPPORTED_FAMILY : if (BRAM_PRIMITIVE = indeterminate) generate
begin
-- assert (false)
-- report "Unsupported Part Family Selected or FIFO Depth/Width is invalid!"
-- severity failure;
--
end generate UNSUPPORTED_FAMILY;
end architecture implementation;
|
-------------------------------------------------------------------------------
-- $Id: pf_dpram_select.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_dpram_select.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_dpram_select.vhd
--
-- Description: This vhdl design file uses three input parameters describing
-- the desired storage depth, data width, and FPGA family type.
-- From these, the design selects the optimum Block RAM
-- primitive for the basic storage element and connects them
-- in parallel to accomodate the desired data width.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_dpram_select.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- DET Oct. 7, 2001 First Version
-- - Adopted design concepts from Goran Bilski's
-- opb_bram.vhd design in the formulation of this
-- design for the Mauna Loa packet FIFO dual port
-- core function.
--
-- DET Oct-31-2001
-- - Changed the generic input parameter C_FAMILY of type string
-- back to the boolean type parameter C_VIRTEX_II. XST support
-- change.
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library unisim;
use unisim.all; -- uses BRAM primitives
-------------------------------------------------------------------------------
entity pf_dpram_select is
generic (
C_DP_DATA_WIDTH : Integer := 32;
C_DP_ADDRESS_WIDTH : Integer := 9;
C_VIRTEX_II : Boolean := true
);
port (
-- Write Port signals
Wr_rst : In std_logic;
Wr_Clk : in std_logic;
Wr_Enable : In std_logic;
Wr_Req : In std_logic;
Wr_Address : in std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1);
Wr_Data : In std_logic_vector(0 to C_DP_DATA_WIDTH-1);
-- Read Port Signals
Rd_rst : In std_logic;
Rd_Clk : in std_logic;
Rd_Enable : In std_logic;
Rd_Address : in std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1);
Rd_Data : out std_logic_vector(0 to C_DP_DATA_WIDTH-1)
);
end entity pf_dpram_select;
architecture implementation of pf_dpram_select is
Type family_type is (
any ,
x4k ,
x4ke ,
x4kl ,
x4kex ,
x4kxl ,
x4kxv ,
x4kxla ,
spartan ,
spartanxl,
spartan2 ,
spartan2e,
virtex ,
virtexe ,
virtex2 ,
virtex2p ,
unsupported
);
Type bram_prim_type is (
use_srl ,
B4_S1_S1 ,
B4_S2_S2 ,
B4_S4_S4 ,
B4_S8_S8 ,
B4_S16_S16 ,
B16_S1_S1 ,
B16_S2_S2 ,
B16_S4_S4 ,
B16_S9_S9 ,
B16_S18_S18 ,
B16_S36_S36 ,
indeterminate
);
-----------------------------------------------------------------------------
-- This function converts the input C_VIRTEX_II boolean type to an enumerated
-- type. Only Virtex and Virtex II types are currently supported. This
-- used to convert a string to a family type function but string support in
-- the synthesis tools was found to be mutually exclusive between Synplicity
-- and XST.
-----------------------------------------------------------------------------
function get_prim_family (vertex2_select : boolean) return family_type is
Variable prim_family : family_type;
begin
If (vertex2_select) Then
prim_family := virtex2;
else
prim_family := virtex;
End if;
Return (prim_family);
end function get_prim_family;
-----------------------------------------------------------------------------
-- This function chooses the optimum BRAM primitive to utilize as
-- specified by the inputs for data depth, data width, and FPGA part family.
-----------------------------------------------------------------------------
function get_bram_primitive (target_depth: integer;
target_width: integer;
family : family_type )
return bram_prim_type is
Variable primitive : bram_prim_type;
begin
Case family Is
When virtex2p | virtex2 =>
Case target_depth Is
When 1 | 2 =>
primitive := indeterminate; -- depth is too small for BRAM
-- based fifo control logic
When 4 | 8 | 16 =>
-- primitive := use_srl; -- activate when SRL FIFO incorporated
Case target_width Is -- use BRAM for now
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When 5 | 6 | 7 | 8 | 9 =>
primitive := B16_S9_S9;
When 10 | 11 | 12 | 13 | 14 |
15 | 16 | 17 | 18 =>
primitive := B16_S18_S18;
When others =>
primitive := B16_S36_S36;
End case;
when 32 | 64 | 128 | 256 | 512 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When 5 | 6 | 7 | 8 | 9 =>
primitive := B16_S9_S9;
When 10 | 11 | 12 | 13 | 14 |
15 | 16 | 17 | 18 =>
primitive := B16_S18_S18;
When others =>
primitive := B16_S36_S36;
End case;
When 1024 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When 5 | 6 | 7 | 8 | 9 =>
primitive := B16_S9_S9;
When others =>
primitive := B16_S18_S18;
End case;
When 2048 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When others =>
primitive := B16_S9_S9;
End case;
When 4096 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When others =>
primitive := B16_S4_S4;
End case;
When 8192 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When others =>
primitive := B16_S2_S2;
End case;
When 16384 =>
primitive := B16_S1_S1;
When others =>
primitive := indeterminate;
End case;
When spartan2 | spartan2e | virtex | virtexe =>
Case target_depth Is
When 1 | 2 =>
primitive := indeterminate; -- depth is too small for BRAM
-- based fifo control logic
When 4 | 8 | 16 =>
-- primitive := use_srl; -- activate this when SRL FIFO is
-- incorporated
Case target_width Is -- use BRAM for now
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When 3 | 4 =>
primitive := B4_S4_S4;
When 5 | 6 | 7 | 8 =>
primitive := B4_S8_S8;
When others =>
primitive := B4_S16_S16;
End case;
when 32 | 64 | 128 | 256 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When 3 | 4 =>
primitive := B4_S4_S4;
When 5 | 6 | 7 | 8 =>
primitive := B4_S8_S8;
When others =>
primitive := B4_S16_S16;
End case;
when 512 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When 3 | 4 =>
primitive := B4_S4_S4;
When others =>
primitive := B4_S8_S8;
End case;
When 1024 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When others =>
primitive := B4_S4_S4;
End case;
When 2048 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When others =>
primitive := B4_S2_S2;
End case;
When 4096 =>
primitive := B4_S1_S1;
When others =>
primitive := indeterminate;
End case;
When others =>
primitive := indeterminate;
End case;
Return primitive;
end function get_bram_primitive;
-----------------------------------------------------------------------------
-- This function calculates the number of BRAM primitives required as
-- specified by the inputs for data width and BRAM primitive type.
-----------------------------------------------------------------------------
function get_num_prims (bram_prim : bram_prim_type;
mem_width : integer)
return integer is
Variable bram_num : integer;
begin
Case bram_prim Is
When B16_S1_S1 | B4_S1_S1 =>
bram_num := mem_width;
When B16_S2_S2 | B4_S2_S2 =>
bram_num := (mem_width+1)/2;
When B16_S4_S4 | B4_S4_S4 =>
bram_num := (mem_width+3)/4;
When B4_S8_S8 =>
bram_num := (mem_width+7)/8;
When B16_S9_S9 =>
bram_num := (mem_width+8)/9;
When B4_S16_S16 =>
bram_num := (mem_width+15)/16;
When B16_S18_S18 =>
bram_num := (mem_width+17)/18;
When B16_S36_S36 =>
bram_num := (mem_width+35)/36;
When others =>
bram_num := 1;
End case;
Return (bram_num);
end function get_num_prims;
-- Now set the global CONSTANTS needed for IF-Generates
-- Determine the number of BRAM storage locations needed
constant FIFO_DEPTH : Integer := 2**C_DP_ADDRESS_WIDTH;
-- Convert the input C_VIRTEX_II generic boolean to enumerated type
Constant BRAM_FAMILY : family_type :=
get_prim_family(C_VIRTEX_II);
-- Select the optimum BRAM primitive to use
constant BRAM_PRIMITIVE : bram_prim_type :=
get_bram_primitive(FIFO_DEPTH,
C_DP_DATA_WIDTH,
BRAM_FAMILY);
-- Calculate how many of the selected primitives are needed
-- to populate the desired data width
constant BRAM_NUM : integer :=
get_num_prims(BRAM_PRIMITIVE,
C_DP_DATA_WIDTH);
begin -- architecture
----------------------------------------------------------------------------
-- Using VII 512 x 36 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S36_S36 : if (BRAM_PRIMITIVE = B16_S36_S36) generate
component RAMB16_S36_S36
port (DIA : in STD_LOGIC_VECTOR (31 downto 0);
DIB : in STD_LOGIC_VECTOR (31 downto 0);
DIPA : in STD_LOGIC_VECTOR (3 downto 0);
DIPB : in STD_LOGIC_VECTOR (3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in STD_LOGIC_VECTOR (8 downto 0);
ADDRB : in STD_LOGIC_VECTOR (8 downto 0);
DOA : out STD_LOGIC_VECTOR (31 downto 0);
DOB : out STD_LOGIC_VECTOR (31 downto 0);
DOPA : out STD_LOGIC_VECTOR (3 downto 0);
DOPB : out STD_LOGIC_VECTOR (3 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 9; -- 512 deep
Constant PRIM_PDBUS_WIDTH : integer := 4; -- 4 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 32; -- 4 parity data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
type pdbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_512x32 : RAMB16_S36_S36
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
DIPA => slice_a_pdbus_in(i),
DIPB => slice_b_pdbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i),
DOPA => slice_a_pdbus_out(i),
DOPB => slice_b_pdbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S36_S36;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 1024 x 18 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S18_S18 : if (BRAM_PRIMITIVE = B16_S18_S18) generate
component RAMB16_S18_S18
port (DIA : in STD_LOGIC_VECTOR (15 downto 0);
DIB : in STD_LOGIC_VECTOR (15 downto 0);
DIPA : in STD_LOGIC_VECTOR (1 downto 0);
DIPB : in STD_LOGIC_VECTOR (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in STD_LOGIC_VECTOR (9 downto 0);
ADDRB : in STD_LOGIC_VECTOR (9 downto 0);
DOA : out STD_LOGIC_VECTOR (15 downto 0);
DOB : out STD_LOGIC_VECTOR (15 downto 0);
DOPA : out STD_LOGIC_VECTOR (1 downto 0);
DOPB : out STD_LOGIC_VECTOR (1 downto 0)
);
end component;
Constant PRIM_ADDR_WIDTH : integer := 10; -- 1024 deep
Constant PRIM_PDBUS_WIDTH : integer := 2; -- 2 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 16; -- 16 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
type pdbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_1024x18 : RAMB16_S18_S18
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
DIPA => slice_a_pdbus_in(i),
DIPB => slice_b_pdbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i),
DOPA => slice_a_pdbus_out(i),
DOPB => slice_b_pdbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S18_S18;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 2048 x 9 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S9_S9 : if (BRAM_PRIMITIVE = B16_S9_S9) generate
component RAMB16_S9_S9
port (
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
DIPA : in std_logic_vector (0 downto 0);
DIPB : in std_logic_vector (0 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0);
DOPA : out std_logic_vector (0 downto 0);
DOPB : out std_logic_vector (0 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 11; -- 2048 deep
Constant PRIM_PDBUS_WIDTH : integer := 1; -- 1 parity data bit
Constant PRIM_DBUS_WIDTH : integer := 8; -- 8 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
type pdbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_2048x9 : RAMB16_S9_S9
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
DIPA => slice_a_pdbus_in(i),
DIPB => slice_b_pdbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i),
DOPA => slice_a_pdbus_out(i),
DOPB => slice_b_pdbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S9_S9;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 4096 x 4 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S4_S4 : if (BRAM_PRIMITIVE = B16_S4_S4) generate
component RAMB16_S4_S4
port (
DIA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (11 downto 0);
ADDRB : in std_logic_vector (11 downto 0);
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (3 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 12; -- 4096 deep
Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 4; -- 4 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--type pdbus_slice_array is array(BRAM_NUM downto 1) of
-- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
--slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
--slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_4096x4 : RAMB16_S4_S4
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S4_S4;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 8192 x 2 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S2_S2 : if (BRAM_PRIMITIVE = B16_S2_S2) generate
component RAMB16_S2_S2
port (
DIA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (12 downto 0);
ADDRB : in std_logic_vector (12 downto 0);
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 13; -- 8192 deep
Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 2; -- 2 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--type pdbus_slice_array is array(BRAM_NUM downto 1) of
-- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
--slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
--slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_8192x2 : RAMB16_S2_S2
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S2_S2;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 16384 x 1 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S1_S1 : if (BRAM_PRIMITIVE = B16_S1_S1) generate
component RAMB16_S1_S1
port (
DIA : in std_logic_vector (0 downto 0);
DIB : in std_logic_vector (0 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (13 downto 0);
ADDRB : in std_logic_vector (13 downto 0);
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (0 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 14; -- 16384 deep
Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 1; -- 1 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--type pdbus_slice_array is array(BRAM_NUM downto 1) of
-- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
--slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
--slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_16384x1 : RAMB16_S1_S1
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S1_S1;
--==========================================================================
-- End of Virtex-II and Virtex-II Pro support
--///////////////////////////////////////////////////////////////////////////
--///////////////////////////////////////////////////////////////////////////
-- Start Spartan-II, Spartan-IIE, Virtex, and VirtexE support
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 4096 x 1 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S1_S1 : if (BRAM_PRIMITIVE = B4_S1_S1) generate
component RAMB4_S1_S1
port (
DIA : in std_logic_vector (0 downto 0);
DIB : in std_logic_vector (0 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (11 downto 0);
ADDRB : in std_logic_vector (11 downto 0);
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (0 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 12; -- 4096 deep
Constant PRIM_DBUS_WIDTH : integer := 1; -- 1 data bit
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_4096x1 : RAMB4_S1_S1
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S1_S1;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 2048 x 2 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S2_S2 : if (BRAM_PRIMITIVE = B4_S2_S2) generate
component RAMB4_S2_S2
port (
DIA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 11; -- 2048 deep
Constant PRIM_DBUS_WIDTH : integer := 2; -- 2 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_2048x2 : RAMB4_S2_S2
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S2_S2;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 1024 x 4 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S4_S4 : if (BRAM_PRIMITIVE = B4_S4_S4) generate
component RAMB4_S4_S4
port (
DIA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (9 downto 0);
ADDRB : in std_logic_vector (9 downto 0);
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (3 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 10; -- 1024 deep
Constant PRIM_DBUS_WIDTH : integer := 4; -- 4 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_1024x4 : RAMB4_S4_S4
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S4_S4;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 512 x 8 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S8_S8 : if (BRAM_PRIMITIVE = B4_S8_S8) generate
component RAMB4_S8_S8
port (
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (8 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 9; -- 512 deep
Constant PRIM_DBUS_WIDTH : integer := 8; -- 8 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_512x8 : RAMB4_S8_S8
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S8_S8;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 256 x 16 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S16_S16 : if (BRAM_PRIMITIVE = B4_S16_S16) generate
component RAMB4_S16_S16
port (DIA : in STD_LOGIC_VECTOR (15 downto 0);
DIB : in STD_LOGIC_VECTOR (15 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in STD_LOGIC_VECTOR (7 downto 0);
ADDRB : in STD_LOGIC_VECTOR (7 downto 0);
DOA : out STD_LOGIC_VECTOR (15 downto 0);
DOB : out STD_LOGIC_VECTOR (15 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 8; -- 256 deep
Constant PRIM_DBUS_WIDTH : integer := 16; -- 16 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_256x16 : RAMB4_S16_S16
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S16_S16;
--==========================================================================
UNSUPPORTED_FAMILY : if (BRAM_PRIMITIVE = indeterminate) generate
begin
-- assert (false)
-- report "Unsupported Part Family Selected or FIFO Depth/Width is invalid!"
-- severity failure;
--
end generate UNSUPPORTED_FAMILY;
end architecture implementation;
|
-------------------------------------------------------------------------------
-- $Id: pf_dpram_select.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_dpram_select.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_dpram_select.vhd
--
-- Description: This vhdl design file uses three input parameters describing
-- the desired storage depth, data width, and FPGA family type.
-- From these, the design selects the optimum Block RAM
-- primitive for the basic storage element and connects them
-- in parallel to accomodate the desired data width.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_dpram_select.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- DET Oct. 7, 2001 First Version
-- - Adopted design concepts from Goran Bilski's
-- opb_bram.vhd design in the formulation of this
-- design for the Mauna Loa packet FIFO dual port
-- core function.
--
-- DET Oct-31-2001
-- - Changed the generic input parameter C_FAMILY of type string
-- back to the boolean type parameter C_VIRTEX_II. XST support
-- change.
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library unisim;
use unisim.all; -- uses BRAM primitives
-------------------------------------------------------------------------------
entity pf_dpram_select is
generic (
C_DP_DATA_WIDTH : Integer := 32;
C_DP_ADDRESS_WIDTH : Integer := 9;
C_VIRTEX_II : Boolean := true
);
port (
-- Write Port signals
Wr_rst : In std_logic;
Wr_Clk : in std_logic;
Wr_Enable : In std_logic;
Wr_Req : In std_logic;
Wr_Address : in std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1);
Wr_Data : In std_logic_vector(0 to C_DP_DATA_WIDTH-1);
-- Read Port Signals
Rd_rst : In std_logic;
Rd_Clk : in std_logic;
Rd_Enable : In std_logic;
Rd_Address : in std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1);
Rd_Data : out std_logic_vector(0 to C_DP_DATA_WIDTH-1)
);
end entity pf_dpram_select;
architecture implementation of pf_dpram_select is
Type family_type is (
any ,
x4k ,
x4ke ,
x4kl ,
x4kex ,
x4kxl ,
x4kxv ,
x4kxla ,
spartan ,
spartanxl,
spartan2 ,
spartan2e,
virtex ,
virtexe ,
virtex2 ,
virtex2p ,
unsupported
);
Type bram_prim_type is (
use_srl ,
B4_S1_S1 ,
B4_S2_S2 ,
B4_S4_S4 ,
B4_S8_S8 ,
B4_S16_S16 ,
B16_S1_S1 ,
B16_S2_S2 ,
B16_S4_S4 ,
B16_S9_S9 ,
B16_S18_S18 ,
B16_S36_S36 ,
indeterminate
);
-----------------------------------------------------------------------------
-- This function converts the input C_VIRTEX_II boolean type to an enumerated
-- type. Only Virtex and Virtex II types are currently supported. This
-- used to convert a string to a family type function but string support in
-- the synthesis tools was found to be mutually exclusive between Synplicity
-- and XST.
-----------------------------------------------------------------------------
function get_prim_family (vertex2_select : boolean) return family_type is
Variable prim_family : family_type;
begin
If (vertex2_select) Then
prim_family := virtex2;
else
prim_family := virtex;
End if;
Return (prim_family);
end function get_prim_family;
-----------------------------------------------------------------------------
-- This function chooses the optimum BRAM primitive to utilize as
-- specified by the inputs for data depth, data width, and FPGA part family.
-----------------------------------------------------------------------------
function get_bram_primitive (target_depth: integer;
target_width: integer;
family : family_type )
return bram_prim_type is
Variable primitive : bram_prim_type;
begin
Case family Is
When virtex2p | virtex2 =>
Case target_depth Is
When 1 | 2 =>
primitive := indeterminate; -- depth is too small for BRAM
-- based fifo control logic
When 4 | 8 | 16 =>
-- primitive := use_srl; -- activate when SRL FIFO incorporated
Case target_width Is -- use BRAM for now
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When 5 | 6 | 7 | 8 | 9 =>
primitive := B16_S9_S9;
When 10 | 11 | 12 | 13 | 14 |
15 | 16 | 17 | 18 =>
primitive := B16_S18_S18;
When others =>
primitive := B16_S36_S36;
End case;
when 32 | 64 | 128 | 256 | 512 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When 5 | 6 | 7 | 8 | 9 =>
primitive := B16_S9_S9;
When 10 | 11 | 12 | 13 | 14 |
15 | 16 | 17 | 18 =>
primitive := B16_S18_S18;
When others =>
primitive := B16_S36_S36;
End case;
When 1024 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When 5 | 6 | 7 | 8 | 9 =>
primitive := B16_S9_S9;
When others =>
primitive := B16_S18_S18;
End case;
When 2048 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When others =>
primitive := B16_S9_S9;
End case;
When 4096 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When others =>
primitive := B16_S4_S4;
End case;
When 8192 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When others =>
primitive := B16_S2_S2;
End case;
When 16384 =>
primitive := B16_S1_S1;
When others =>
primitive := indeterminate;
End case;
When spartan2 | spartan2e | virtex | virtexe =>
Case target_depth Is
When 1 | 2 =>
primitive := indeterminate; -- depth is too small for BRAM
-- based fifo control logic
When 4 | 8 | 16 =>
-- primitive := use_srl; -- activate this when SRL FIFO is
-- incorporated
Case target_width Is -- use BRAM for now
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When 3 | 4 =>
primitive := B4_S4_S4;
When 5 | 6 | 7 | 8 =>
primitive := B4_S8_S8;
When others =>
primitive := B4_S16_S16;
End case;
when 32 | 64 | 128 | 256 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When 3 | 4 =>
primitive := B4_S4_S4;
When 5 | 6 | 7 | 8 =>
primitive := B4_S8_S8;
When others =>
primitive := B4_S16_S16;
End case;
when 512 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When 3 | 4 =>
primitive := B4_S4_S4;
When others =>
primitive := B4_S8_S8;
End case;
When 1024 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When others =>
primitive := B4_S4_S4;
End case;
When 2048 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When others =>
primitive := B4_S2_S2;
End case;
When 4096 =>
primitive := B4_S1_S1;
When others =>
primitive := indeterminate;
End case;
When others =>
primitive := indeterminate;
End case;
Return primitive;
end function get_bram_primitive;
-----------------------------------------------------------------------------
-- This function calculates the number of BRAM primitives required as
-- specified by the inputs for data width and BRAM primitive type.
-----------------------------------------------------------------------------
function get_num_prims (bram_prim : bram_prim_type;
mem_width : integer)
return integer is
Variable bram_num : integer;
begin
Case bram_prim Is
When B16_S1_S1 | B4_S1_S1 =>
bram_num := mem_width;
When B16_S2_S2 | B4_S2_S2 =>
bram_num := (mem_width+1)/2;
When B16_S4_S4 | B4_S4_S4 =>
bram_num := (mem_width+3)/4;
When B4_S8_S8 =>
bram_num := (mem_width+7)/8;
When B16_S9_S9 =>
bram_num := (mem_width+8)/9;
When B4_S16_S16 =>
bram_num := (mem_width+15)/16;
When B16_S18_S18 =>
bram_num := (mem_width+17)/18;
When B16_S36_S36 =>
bram_num := (mem_width+35)/36;
When others =>
bram_num := 1;
End case;
Return (bram_num);
end function get_num_prims;
-- Now set the global CONSTANTS needed for IF-Generates
-- Determine the number of BRAM storage locations needed
constant FIFO_DEPTH : Integer := 2**C_DP_ADDRESS_WIDTH;
-- Convert the input C_VIRTEX_II generic boolean to enumerated type
Constant BRAM_FAMILY : family_type :=
get_prim_family(C_VIRTEX_II);
-- Select the optimum BRAM primitive to use
constant BRAM_PRIMITIVE : bram_prim_type :=
get_bram_primitive(FIFO_DEPTH,
C_DP_DATA_WIDTH,
BRAM_FAMILY);
-- Calculate how many of the selected primitives are needed
-- to populate the desired data width
constant BRAM_NUM : integer :=
get_num_prims(BRAM_PRIMITIVE,
C_DP_DATA_WIDTH);
begin -- architecture
----------------------------------------------------------------------------
-- Using VII 512 x 36 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S36_S36 : if (BRAM_PRIMITIVE = B16_S36_S36) generate
component RAMB16_S36_S36
port (DIA : in STD_LOGIC_VECTOR (31 downto 0);
DIB : in STD_LOGIC_VECTOR (31 downto 0);
DIPA : in STD_LOGIC_VECTOR (3 downto 0);
DIPB : in STD_LOGIC_VECTOR (3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in STD_LOGIC_VECTOR (8 downto 0);
ADDRB : in STD_LOGIC_VECTOR (8 downto 0);
DOA : out STD_LOGIC_VECTOR (31 downto 0);
DOB : out STD_LOGIC_VECTOR (31 downto 0);
DOPA : out STD_LOGIC_VECTOR (3 downto 0);
DOPB : out STD_LOGIC_VECTOR (3 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 9; -- 512 deep
Constant PRIM_PDBUS_WIDTH : integer := 4; -- 4 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 32; -- 4 parity data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
type pdbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_512x32 : RAMB16_S36_S36
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
DIPA => slice_a_pdbus_in(i),
DIPB => slice_b_pdbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i),
DOPA => slice_a_pdbus_out(i),
DOPB => slice_b_pdbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S36_S36;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 1024 x 18 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S18_S18 : if (BRAM_PRIMITIVE = B16_S18_S18) generate
component RAMB16_S18_S18
port (DIA : in STD_LOGIC_VECTOR (15 downto 0);
DIB : in STD_LOGIC_VECTOR (15 downto 0);
DIPA : in STD_LOGIC_VECTOR (1 downto 0);
DIPB : in STD_LOGIC_VECTOR (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in STD_LOGIC_VECTOR (9 downto 0);
ADDRB : in STD_LOGIC_VECTOR (9 downto 0);
DOA : out STD_LOGIC_VECTOR (15 downto 0);
DOB : out STD_LOGIC_VECTOR (15 downto 0);
DOPA : out STD_LOGIC_VECTOR (1 downto 0);
DOPB : out STD_LOGIC_VECTOR (1 downto 0)
);
end component;
Constant PRIM_ADDR_WIDTH : integer := 10; -- 1024 deep
Constant PRIM_PDBUS_WIDTH : integer := 2; -- 2 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 16; -- 16 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
type pdbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_1024x18 : RAMB16_S18_S18
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
DIPA => slice_a_pdbus_in(i),
DIPB => slice_b_pdbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i),
DOPA => slice_a_pdbus_out(i),
DOPB => slice_b_pdbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S18_S18;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 2048 x 9 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S9_S9 : if (BRAM_PRIMITIVE = B16_S9_S9) generate
component RAMB16_S9_S9
port (
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
DIPA : in std_logic_vector (0 downto 0);
DIPB : in std_logic_vector (0 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0);
DOPA : out std_logic_vector (0 downto 0);
DOPB : out std_logic_vector (0 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 11; -- 2048 deep
Constant PRIM_PDBUS_WIDTH : integer := 1; -- 1 parity data bit
Constant PRIM_DBUS_WIDTH : integer := 8; -- 8 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
type pdbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_2048x9 : RAMB16_S9_S9
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
DIPA => slice_a_pdbus_in(i),
DIPB => slice_b_pdbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i),
DOPA => slice_a_pdbus_out(i),
DOPB => slice_b_pdbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S9_S9;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 4096 x 4 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S4_S4 : if (BRAM_PRIMITIVE = B16_S4_S4) generate
component RAMB16_S4_S4
port (
DIA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (11 downto 0);
ADDRB : in std_logic_vector (11 downto 0);
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (3 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 12; -- 4096 deep
Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 4; -- 4 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--type pdbus_slice_array is array(BRAM_NUM downto 1) of
-- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
--slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
--slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_4096x4 : RAMB16_S4_S4
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S4_S4;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 8192 x 2 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S2_S2 : if (BRAM_PRIMITIVE = B16_S2_S2) generate
component RAMB16_S2_S2
port (
DIA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (12 downto 0);
ADDRB : in std_logic_vector (12 downto 0);
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 13; -- 8192 deep
Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 2; -- 2 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--type pdbus_slice_array is array(BRAM_NUM downto 1) of
-- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
--slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
--slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_8192x2 : RAMB16_S2_S2
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S2_S2;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 16384 x 1 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S1_S1 : if (BRAM_PRIMITIVE = B16_S1_S1) generate
component RAMB16_S1_S1
port (
DIA : in std_logic_vector (0 downto 0);
DIB : in std_logic_vector (0 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (13 downto 0);
ADDRB : in std_logic_vector (13 downto 0);
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (0 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 14; -- 16384 deep
Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 1; -- 1 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--type pdbus_slice_array is array(BRAM_NUM downto 1) of
-- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
--slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
--slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_16384x1 : RAMB16_S1_S1
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S1_S1;
--==========================================================================
-- End of Virtex-II and Virtex-II Pro support
--///////////////////////////////////////////////////////////////////////////
--///////////////////////////////////////////////////////////////////////////
-- Start Spartan-II, Spartan-IIE, Virtex, and VirtexE support
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 4096 x 1 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S1_S1 : if (BRAM_PRIMITIVE = B4_S1_S1) generate
component RAMB4_S1_S1
port (
DIA : in std_logic_vector (0 downto 0);
DIB : in std_logic_vector (0 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (11 downto 0);
ADDRB : in std_logic_vector (11 downto 0);
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (0 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 12; -- 4096 deep
Constant PRIM_DBUS_WIDTH : integer := 1; -- 1 data bit
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_4096x1 : RAMB4_S1_S1
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S1_S1;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 2048 x 2 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S2_S2 : if (BRAM_PRIMITIVE = B4_S2_S2) generate
component RAMB4_S2_S2
port (
DIA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 11; -- 2048 deep
Constant PRIM_DBUS_WIDTH : integer := 2; -- 2 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_2048x2 : RAMB4_S2_S2
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S2_S2;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 1024 x 4 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S4_S4 : if (BRAM_PRIMITIVE = B4_S4_S4) generate
component RAMB4_S4_S4
port (
DIA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (9 downto 0);
ADDRB : in std_logic_vector (9 downto 0);
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (3 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 10; -- 1024 deep
Constant PRIM_DBUS_WIDTH : integer := 4; -- 4 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_1024x4 : RAMB4_S4_S4
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S4_S4;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 512 x 8 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S8_S8 : if (BRAM_PRIMITIVE = B4_S8_S8) generate
component RAMB4_S8_S8
port (
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (8 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 9; -- 512 deep
Constant PRIM_DBUS_WIDTH : integer := 8; -- 8 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_512x8 : RAMB4_S8_S8
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S8_S8;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 256 x 16 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S16_S16 : if (BRAM_PRIMITIVE = B4_S16_S16) generate
component RAMB4_S16_S16
port (DIA : in STD_LOGIC_VECTOR (15 downto 0);
DIB : in STD_LOGIC_VECTOR (15 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in STD_LOGIC_VECTOR (7 downto 0);
ADDRB : in STD_LOGIC_VECTOR (7 downto 0);
DOA : out STD_LOGIC_VECTOR (15 downto 0);
DOB : out STD_LOGIC_VECTOR (15 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 8; -- 256 deep
Constant PRIM_DBUS_WIDTH : integer := 16; -- 16 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_256x16 : RAMB4_S16_S16
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S16_S16;
--==========================================================================
UNSUPPORTED_FAMILY : if (BRAM_PRIMITIVE = indeterminate) generate
begin
-- assert (false)
-- report "Unsupported Part Family Selected or FIFO Depth/Width is invalid!"
-- severity failure;
--
end generate UNSUPPORTED_FAMILY;
end architecture implementation;
|
-------------------------------------------------------------------------------
-- $Id: pf_dpram_select.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_dpram_select.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
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-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_dpram_select.vhd
--
-- Description: This vhdl design file uses three input parameters describing
-- the desired storage depth, data width, and FPGA family type.
-- From these, the design selects the optimum Block RAM
-- primitive for the basic storage element and connects them
-- in parallel to accomodate the desired data width.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_dpram_select.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- DET Oct. 7, 2001 First Version
-- - Adopted design concepts from Goran Bilski's
-- opb_bram.vhd design in the formulation of this
-- design for the Mauna Loa packet FIFO dual port
-- core function.
--
-- DET Oct-31-2001
-- - Changed the generic input parameter C_FAMILY of type string
-- back to the boolean type parameter C_VIRTEX_II. XST support
-- change.
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library unisim;
use unisim.all; -- uses BRAM primitives
-------------------------------------------------------------------------------
entity pf_dpram_select is
generic (
C_DP_DATA_WIDTH : Integer := 32;
C_DP_ADDRESS_WIDTH : Integer := 9;
C_VIRTEX_II : Boolean := true
);
port (
-- Write Port signals
Wr_rst : In std_logic;
Wr_Clk : in std_logic;
Wr_Enable : In std_logic;
Wr_Req : In std_logic;
Wr_Address : in std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1);
Wr_Data : In std_logic_vector(0 to C_DP_DATA_WIDTH-1);
-- Read Port Signals
Rd_rst : In std_logic;
Rd_Clk : in std_logic;
Rd_Enable : In std_logic;
Rd_Address : in std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1);
Rd_Data : out std_logic_vector(0 to C_DP_DATA_WIDTH-1)
);
end entity pf_dpram_select;
architecture implementation of pf_dpram_select is
Type family_type is (
any ,
x4k ,
x4ke ,
x4kl ,
x4kex ,
x4kxl ,
x4kxv ,
x4kxla ,
spartan ,
spartanxl,
spartan2 ,
spartan2e,
virtex ,
virtexe ,
virtex2 ,
virtex2p ,
unsupported
);
Type bram_prim_type is (
use_srl ,
B4_S1_S1 ,
B4_S2_S2 ,
B4_S4_S4 ,
B4_S8_S8 ,
B4_S16_S16 ,
B16_S1_S1 ,
B16_S2_S2 ,
B16_S4_S4 ,
B16_S9_S9 ,
B16_S18_S18 ,
B16_S36_S36 ,
indeterminate
);
-----------------------------------------------------------------------------
-- This function converts the input C_VIRTEX_II boolean type to an enumerated
-- type. Only Virtex and Virtex II types are currently supported. This
-- used to convert a string to a family type function but string support in
-- the synthesis tools was found to be mutually exclusive between Synplicity
-- and XST.
-----------------------------------------------------------------------------
function get_prim_family (vertex2_select : boolean) return family_type is
Variable prim_family : family_type;
begin
If (vertex2_select) Then
prim_family := virtex2;
else
prim_family := virtex;
End if;
Return (prim_family);
end function get_prim_family;
-----------------------------------------------------------------------------
-- This function chooses the optimum BRAM primitive to utilize as
-- specified by the inputs for data depth, data width, and FPGA part family.
-----------------------------------------------------------------------------
function get_bram_primitive (target_depth: integer;
target_width: integer;
family : family_type )
return bram_prim_type is
Variable primitive : bram_prim_type;
begin
Case family Is
When virtex2p | virtex2 =>
Case target_depth Is
When 1 | 2 =>
primitive := indeterminate; -- depth is too small for BRAM
-- based fifo control logic
When 4 | 8 | 16 =>
-- primitive := use_srl; -- activate when SRL FIFO incorporated
Case target_width Is -- use BRAM for now
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When 5 | 6 | 7 | 8 | 9 =>
primitive := B16_S9_S9;
When 10 | 11 | 12 | 13 | 14 |
15 | 16 | 17 | 18 =>
primitive := B16_S18_S18;
When others =>
primitive := B16_S36_S36;
End case;
when 32 | 64 | 128 | 256 | 512 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When 5 | 6 | 7 | 8 | 9 =>
primitive := B16_S9_S9;
When 10 | 11 | 12 | 13 | 14 |
15 | 16 | 17 | 18 =>
primitive := B16_S18_S18;
When others =>
primitive := B16_S36_S36;
End case;
When 1024 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When 5 | 6 | 7 | 8 | 9 =>
primitive := B16_S9_S9;
When others =>
primitive := B16_S18_S18;
End case;
When 2048 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When others =>
primitive := B16_S9_S9;
End case;
When 4096 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When others =>
primitive := B16_S4_S4;
End case;
When 8192 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When others =>
primitive := B16_S2_S2;
End case;
When 16384 =>
primitive := B16_S1_S1;
When others =>
primitive := indeterminate;
End case;
When spartan2 | spartan2e | virtex | virtexe =>
Case target_depth Is
When 1 | 2 =>
primitive := indeterminate; -- depth is too small for BRAM
-- based fifo control logic
When 4 | 8 | 16 =>
-- primitive := use_srl; -- activate this when SRL FIFO is
-- incorporated
Case target_width Is -- use BRAM for now
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When 3 | 4 =>
primitive := B4_S4_S4;
When 5 | 6 | 7 | 8 =>
primitive := B4_S8_S8;
When others =>
primitive := B4_S16_S16;
End case;
when 32 | 64 | 128 | 256 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When 3 | 4 =>
primitive := B4_S4_S4;
When 5 | 6 | 7 | 8 =>
primitive := B4_S8_S8;
When others =>
primitive := B4_S16_S16;
End case;
when 512 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When 3 | 4 =>
primitive := B4_S4_S4;
When others =>
primitive := B4_S8_S8;
End case;
When 1024 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When others =>
primitive := B4_S4_S4;
End case;
When 2048 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When others =>
primitive := B4_S2_S2;
End case;
When 4096 =>
primitive := B4_S1_S1;
When others =>
primitive := indeterminate;
End case;
When others =>
primitive := indeterminate;
End case;
Return primitive;
end function get_bram_primitive;
-----------------------------------------------------------------------------
-- This function calculates the number of BRAM primitives required as
-- specified by the inputs for data width and BRAM primitive type.
-----------------------------------------------------------------------------
function get_num_prims (bram_prim : bram_prim_type;
mem_width : integer)
return integer is
Variable bram_num : integer;
begin
Case bram_prim Is
When B16_S1_S1 | B4_S1_S1 =>
bram_num := mem_width;
When B16_S2_S2 | B4_S2_S2 =>
bram_num := (mem_width+1)/2;
When B16_S4_S4 | B4_S4_S4 =>
bram_num := (mem_width+3)/4;
When B4_S8_S8 =>
bram_num := (mem_width+7)/8;
When B16_S9_S9 =>
bram_num := (mem_width+8)/9;
When B4_S16_S16 =>
bram_num := (mem_width+15)/16;
When B16_S18_S18 =>
bram_num := (mem_width+17)/18;
When B16_S36_S36 =>
bram_num := (mem_width+35)/36;
When others =>
bram_num := 1;
End case;
Return (bram_num);
end function get_num_prims;
-- Now set the global CONSTANTS needed for IF-Generates
-- Determine the number of BRAM storage locations needed
constant FIFO_DEPTH : Integer := 2**C_DP_ADDRESS_WIDTH;
-- Convert the input C_VIRTEX_II generic boolean to enumerated type
Constant BRAM_FAMILY : family_type :=
get_prim_family(C_VIRTEX_II);
-- Select the optimum BRAM primitive to use
constant BRAM_PRIMITIVE : bram_prim_type :=
get_bram_primitive(FIFO_DEPTH,
C_DP_DATA_WIDTH,
BRAM_FAMILY);
-- Calculate how many of the selected primitives are needed
-- to populate the desired data width
constant BRAM_NUM : integer :=
get_num_prims(BRAM_PRIMITIVE,
C_DP_DATA_WIDTH);
begin -- architecture
----------------------------------------------------------------------------
-- Using VII 512 x 36 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S36_S36 : if (BRAM_PRIMITIVE = B16_S36_S36) generate
component RAMB16_S36_S36
port (DIA : in STD_LOGIC_VECTOR (31 downto 0);
DIB : in STD_LOGIC_VECTOR (31 downto 0);
DIPA : in STD_LOGIC_VECTOR (3 downto 0);
DIPB : in STD_LOGIC_VECTOR (3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in STD_LOGIC_VECTOR (8 downto 0);
ADDRB : in STD_LOGIC_VECTOR (8 downto 0);
DOA : out STD_LOGIC_VECTOR (31 downto 0);
DOB : out STD_LOGIC_VECTOR (31 downto 0);
DOPA : out STD_LOGIC_VECTOR (3 downto 0);
DOPB : out STD_LOGIC_VECTOR (3 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 9; -- 512 deep
Constant PRIM_PDBUS_WIDTH : integer := 4; -- 4 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 32; -- 4 parity data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
type pdbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_512x32 : RAMB16_S36_S36
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
DIPA => slice_a_pdbus_in(i),
DIPB => slice_b_pdbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i),
DOPA => slice_a_pdbus_out(i),
DOPB => slice_b_pdbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S36_S36;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 1024 x 18 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S18_S18 : if (BRAM_PRIMITIVE = B16_S18_S18) generate
component RAMB16_S18_S18
port (DIA : in STD_LOGIC_VECTOR (15 downto 0);
DIB : in STD_LOGIC_VECTOR (15 downto 0);
DIPA : in STD_LOGIC_VECTOR (1 downto 0);
DIPB : in STD_LOGIC_VECTOR (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in STD_LOGIC_VECTOR (9 downto 0);
ADDRB : in STD_LOGIC_VECTOR (9 downto 0);
DOA : out STD_LOGIC_VECTOR (15 downto 0);
DOB : out STD_LOGIC_VECTOR (15 downto 0);
DOPA : out STD_LOGIC_VECTOR (1 downto 0);
DOPB : out STD_LOGIC_VECTOR (1 downto 0)
);
end component;
Constant PRIM_ADDR_WIDTH : integer := 10; -- 1024 deep
Constant PRIM_PDBUS_WIDTH : integer := 2; -- 2 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 16; -- 16 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
type pdbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_1024x18 : RAMB16_S18_S18
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
DIPA => slice_a_pdbus_in(i),
DIPB => slice_b_pdbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i),
DOPA => slice_a_pdbus_out(i),
DOPB => slice_b_pdbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S18_S18;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 2048 x 9 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S9_S9 : if (BRAM_PRIMITIVE = B16_S9_S9) generate
component RAMB16_S9_S9
port (
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
DIPA : in std_logic_vector (0 downto 0);
DIPB : in std_logic_vector (0 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0);
DOPA : out std_logic_vector (0 downto 0);
DOPB : out std_logic_vector (0 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 11; -- 2048 deep
Constant PRIM_PDBUS_WIDTH : integer := 1; -- 1 parity data bit
Constant PRIM_DBUS_WIDTH : integer := 8; -- 8 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
type pdbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_2048x9 : RAMB16_S9_S9
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
DIPA => slice_a_pdbus_in(i),
DIPB => slice_b_pdbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i),
DOPA => slice_a_pdbus_out(i),
DOPB => slice_b_pdbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S9_S9;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 4096 x 4 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S4_S4 : if (BRAM_PRIMITIVE = B16_S4_S4) generate
component RAMB16_S4_S4
port (
DIA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (11 downto 0);
ADDRB : in std_logic_vector (11 downto 0);
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (3 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 12; -- 4096 deep
Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 4; -- 4 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--type pdbus_slice_array is array(BRAM_NUM downto 1) of
-- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
--slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
--slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_4096x4 : RAMB16_S4_S4
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S4_S4;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 8192 x 2 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S2_S2 : if (BRAM_PRIMITIVE = B16_S2_S2) generate
component RAMB16_S2_S2
port (
DIA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (12 downto 0);
ADDRB : in std_logic_vector (12 downto 0);
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 13; -- 8192 deep
Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 2; -- 2 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--type pdbus_slice_array is array(BRAM_NUM downto 1) of
-- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
--slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
--slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_8192x2 : RAMB16_S2_S2
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S2_S2;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 16384 x 1 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S1_S1 : if (BRAM_PRIMITIVE = B16_S1_S1) generate
component RAMB16_S1_S1
port (
DIA : in std_logic_vector (0 downto 0);
DIB : in std_logic_vector (0 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (13 downto 0);
ADDRB : in std_logic_vector (13 downto 0);
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (0 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 14; -- 16384 deep
Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 1; -- 1 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--type pdbus_slice_array is array(BRAM_NUM downto 1) of
-- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
--slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
--slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_16384x1 : RAMB16_S1_S1
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S1_S1;
--==========================================================================
-- End of Virtex-II and Virtex-II Pro support
--///////////////////////////////////////////////////////////////////////////
--///////////////////////////////////////////////////////////////////////////
-- Start Spartan-II, Spartan-IIE, Virtex, and VirtexE support
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 4096 x 1 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S1_S1 : if (BRAM_PRIMITIVE = B4_S1_S1) generate
component RAMB4_S1_S1
port (
DIA : in std_logic_vector (0 downto 0);
DIB : in std_logic_vector (0 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (11 downto 0);
ADDRB : in std_logic_vector (11 downto 0);
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (0 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 12; -- 4096 deep
Constant PRIM_DBUS_WIDTH : integer := 1; -- 1 data bit
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_4096x1 : RAMB4_S1_S1
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S1_S1;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 2048 x 2 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S2_S2 : if (BRAM_PRIMITIVE = B4_S2_S2) generate
component RAMB4_S2_S2
port (
DIA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 11; -- 2048 deep
Constant PRIM_DBUS_WIDTH : integer := 2; -- 2 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_2048x2 : RAMB4_S2_S2
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S2_S2;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 1024 x 4 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S4_S4 : if (BRAM_PRIMITIVE = B4_S4_S4) generate
component RAMB4_S4_S4
port (
DIA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (9 downto 0);
ADDRB : in std_logic_vector (9 downto 0);
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (3 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 10; -- 1024 deep
Constant PRIM_DBUS_WIDTH : integer := 4; -- 4 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_1024x4 : RAMB4_S4_S4
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S4_S4;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 512 x 8 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S8_S8 : if (BRAM_PRIMITIVE = B4_S8_S8) generate
component RAMB4_S8_S8
port (
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (8 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 9; -- 512 deep
Constant PRIM_DBUS_WIDTH : integer := 8; -- 8 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_512x8 : RAMB4_S8_S8
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S8_S8;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 256 x 16 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S16_S16 : if (BRAM_PRIMITIVE = B4_S16_S16) generate
component RAMB4_S16_S16
port (DIA : in STD_LOGIC_VECTOR (15 downto 0);
DIB : in STD_LOGIC_VECTOR (15 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in STD_LOGIC_VECTOR (7 downto 0);
ADDRB : in STD_LOGIC_VECTOR (7 downto 0);
DOA : out STD_LOGIC_VECTOR (15 downto 0);
DOB : out STD_LOGIC_VECTOR (15 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 8; -- 256 deep
Constant PRIM_DBUS_WIDTH : integer := 16; -- 16 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_256x16 : RAMB4_S16_S16
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S16_S16;
--==========================================================================
UNSUPPORTED_FAMILY : if (BRAM_PRIMITIVE = indeterminate) generate
begin
-- assert (false)
-- report "Unsupported Part Family Selected or FIFO Depth/Width is invalid!"
-- severity failure;
--
end generate UNSUPPORTED_FAMILY;
end architecture implementation;
|
-------------------------------------------------------------------------------
-- $Id: pf_dpram_select.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_dpram_select.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_dpram_select.vhd
--
-- Description: This vhdl design file uses three input parameters describing
-- the desired storage depth, data width, and FPGA family type.
-- From these, the design selects the optimum Block RAM
-- primitive for the basic storage element and connects them
-- in parallel to accomodate the desired data width.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_dpram_select.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- DET Oct. 7, 2001 First Version
-- - Adopted design concepts from Goran Bilski's
-- opb_bram.vhd design in the formulation of this
-- design for the Mauna Loa packet FIFO dual port
-- core function.
--
-- DET Oct-31-2001
-- - Changed the generic input parameter C_FAMILY of type string
-- back to the boolean type parameter C_VIRTEX_II. XST support
-- change.
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library unisim;
use unisim.all; -- uses BRAM primitives
-------------------------------------------------------------------------------
entity pf_dpram_select is
generic (
C_DP_DATA_WIDTH : Integer := 32;
C_DP_ADDRESS_WIDTH : Integer := 9;
C_VIRTEX_II : Boolean := true
);
port (
-- Write Port signals
Wr_rst : In std_logic;
Wr_Clk : in std_logic;
Wr_Enable : In std_logic;
Wr_Req : In std_logic;
Wr_Address : in std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1);
Wr_Data : In std_logic_vector(0 to C_DP_DATA_WIDTH-1);
-- Read Port Signals
Rd_rst : In std_logic;
Rd_Clk : in std_logic;
Rd_Enable : In std_logic;
Rd_Address : in std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1);
Rd_Data : out std_logic_vector(0 to C_DP_DATA_WIDTH-1)
);
end entity pf_dpram_select;
architecture implementation of pf_dpram_select is
Type family_type is (
any ,
x4k ,
x4ke ,
x4kl ,
x4kex ,
x4kxl ,
x4kxv ,
x4kxla ,
spartan ,
spartanxl,
spartan2 ,
spartan2e,
virtex ,
virtexe ,
virtex2 ,
virtex2p ,
unsupported
);
Type bram_prim_type is (
use_srl ,
B4_S1_S1 ,
B4_S2_S2 ,
B4_S4_S4 ,
B4_S8_S8 ,
B4_S16_S16 ,
B16_S1_S1 ,
B16_S2_S2 ,
B16_S4_S4 ,
B16_S9_S9 ,
B16_S18_S18 ,
B16_S36_S36 ,
indeterminate
);
-----------------------------------------------------------------------------
-- This function converts the input C_VIRTEX_II boolean type to an enumerated
-- type. Only Virtex and Virtex II types are currently supported. This
-- used to convert a string to a family type function but string support in
-- the synthesis tools was found to be mutually exclusive between Synplicity
-- and XST.
-----------------------------------------------------------------------------
function get_prim_family (vertex2_select : boolean) return family_type is
Variable prim_family : family_type;
begin
If (vertex2_select) Then
prim_family := virtex2;
else
prim_family := virtex;
End if;
Return (prim_family);
end function get_prim_family;
-----------------------------------------------------------------------------
-- This function chooses the optimum BRAM primitive to utilize as
-- specified by the inputs for data depth, data width, and FPGA part family.
-----------------------------------------------------------------------------
function get_bram_primitive (target_depth: integer;
target_width: integer;
family : family_type )
return bram_prim_type is
Variable primitive : bram_prim_type;
begin
Case family Is
When virtex2p | virtex2 =>
Case target_depth Is
When 1 | 2 =>
primitive := indeterminate; -- depth is too small for BRAM
-- based fifo control logic
When 4 | 8 | 16 =>
-- primitive := use_srl; -- activate when SRL FIFO incorporated
Case target_width Is -- use BRAM for now
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When 5 | 6 | 7 | 8 | 9 =>
primitive := B16_S9_S9;
When 10 | 11 | 12 | 13 | 14 |
15 | 16 | 17 | 18 =>
primitive := B16_S18_S18;
When others =>
primitive := B16_S36_S36;
End case;
when 32 | 64 | 128 | 256 | 512 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When 5 | 6 | 7 | 8 | 9 =>
primitive := B16_S9_S9;
When 10 | 11 | 12 | 13 | 14 |
15 | 16 | 17 | 18 =>
primitive := B16_S18_S18;
When others =>
primitive := B16_S36_S36;
End case;
When 1024 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When 5 | 6 | 7 | 8 | 9 =>
primitive := B16_S9_S9;
When others =>
primitive := B16_S18_S18;
End case;
When 2048 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When others =>
primitive := B16_S9_S9;
End case;
When 4096 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When others =>
primitive := B16_S4_S4;
End case;
When 8192 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When others =>
primitive := B16_S2_S2;
End case;
When 16384 =>
primitive := B16_S1_S1;
When others =>
primitive := indeterminate;
End case;
When spartan2 | spartan2e | virtex | virtexe =>
Case target_depth Is
When 1 | 2 =>
primitive := indeterminate; -- depth is too small for BRAM
-- based fifo control logic
When 4 | 8 | 16 =>
-- primitive := use_srl; -- activate this when SRL FIFO is
-- incorporated
Case target_width Is -- use BRAM for now
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When 3 | 4 =>
primitive := B4_S4_S4;
When 5 | 6 | 7 | 8 =>
primitive := B4_S8_S8;
When others =>
primitive := B4_S16_S16;
End case;
when 32 | 64 | 128 | 256 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When 3 | 4 =>
primitive := B4_S4_S4;
When 5 | 6 | 7 | 8 =>
primitive := B4_S8_S8;
When others =>
primitive := B4_S16_S16;
End case;
when 512 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When 3 | 4 =>
primitive := B4_S4_S4;
When others =>
primitive := B4_S8_S8;
End case;
When 1024 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When others =>
primitive := B4_S4_S4;
End case;
When 2048 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When others =>
primitive := B4_S2_S2;
End case;
When 4096 =>
primitive := B4_S1_S1;
When others =>
primitive := indeterminate;
End case;
When others =>
primitive := indeterminate;
End case;
Return primitive;
end function get_bram_primitive;
-----------------------------------------------------------------------------
-- This function calculates the number of BRAM primitives required as
-- specified by the inputs for data width and BRAM primitive type.
-----------------------------------------------------------------------------
function get_num_prims (bram_prim : bram_prim_type;
mem_width : integer)
return integer is
Variable bram_num : integer;
begin
Case bram_prim Is
When B16_S1_S1 | B4_S1_S1 =>
bram_num := mem_width;
When B16_S2_S2 | B4_S2_S2 =>
bram_num := (mem_width+1)/2;
When B16_S4_S4 | B4_S4_S4 =>
bram_num := (mem_width+3)/4;
When B4_S8_S8 =>
bram_num := (mem_width+7)/8;
When B16_S9_S9 =>
bram_num := (mem_width+8)/9;
When B4_S16_S16 =>
bram_num := (mem_width+15)/16;
When B16_S18_S18 =>
bram_num := (mem_width+17)/18;
When B16_S36_S36 =>
bram_num := (mem_width+35)/36;
When others =>
bram_num := 1;
End case;
Return (bram_num);
end function get_num_prims;
-- Now set the global CONSTANTS needed for IF-Generates
-- Determine the number of BRAM storage locations needed
constant FIFO_DEPTH : Integer := 2**C_DP_ADDRESS_WIDTH;
-- Convert the input C_VIRTEX_II generic boolean to enumerated type
Constant BRAM_FAMILY : family_type :=
get_prim_family(C_VIRTEX_II);
-- Select the optimum BRAM primitive to use
constant BRAM_PRIMITIVE : bram_prim_type :=
get_bram_primitive(FIFO_DEPTH,
C_DP_DATA_WIDTH,
BRAM_FAMILY);
-- Calculate how many of the selected primitives are needed
-- to populate the desired data width
constant BRAM_NUM : integer :=
get_num_prims(BRAM_PRIMITIVE,
C_DP_DATA_WIDTH);
begin -- architecture
----------------------------------------------------------------------------
-- Using VII 512 x 36 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S36_S36 : if (BRAM_PRIMITIVE = B16_S36_S36) generate
component RAMB16_S36_S36
port (DIA : in STD_LOGIC_VECTOR (31 downto 0);
DIB : in STD_LOGIC_VECTOR (31 downto 0);
DIPA : in STD_LOGIC_VECTOR (3 downto 0);
DIPB : in STD_LOGIC_VECTOR (3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in STD_LOGIC_VECTOR (8 downto 0);
ADDRB : in STD_LOGIC_VECTOR (8 downto 0);
DOA : out STD_LOGIC_VECTOR (31 downto 0);
DOB : out STD_LOGIC_VECTOR (31 downto 0);
DOPA : out STD_LOGIC_VECTOR (3 downto 0);
DOPB : out STD_LOGIC_VECTOR (3 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 9; -- 512 deep
Constant PRIM_PDBUS_WIDTH : integer := 4; -- 4 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 32; -- 4 parity data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
type pdbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_512x32 : RAMB16_S36_S36
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
DIPA => slice_a_pdbus_in(i),
DIPB => slice_b_pdbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i),
DOPA => slice_a_pdbus_out(i),
DOPB => slice_b_pdbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S36_S36;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 1024 x 18 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S18_S18 : if (BRAM_PRIMITIVE = B16_S18_S18) generate
component RAMB16_S18_S18
port (DIA : in STD_LOGIC_VECTOR (15 downto 0);
DIB : in STD_LOGIC_VECTOR (15 downto 0);
DIPA : in STD_LOGIC_VECTOR (1 downto 0);
DIPB : in STD_LOGIC_VECTOR (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in STD_LOGIC_VECTOR (9 downto 0);
ADDRB : in STD_LOGIC_VECTOR (9 downto 0);
DOA : out STD_LOGIC_VECTOR (15 downto 0);
DOB : out STD_LOGIC_VECTOR (15 downto 0);
DOPA : out STD_LOGIC_VECTOR (1 downto 0);
DOPB : out STD_LOGIC_VECTOR (1 downto 0)
);
end component;
Constant PRIM_ADDR_WIDTH : integer := 10; -- 1024 deep
Constant PRIM_PDBUS_WIDTH : integer := 2; -- 2 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 16; -- 16 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
type pdbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_1024x18 : RAMB16_S18_S18
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
DIPA => slice_a_pdbus_in(i),
DIPB => slice_b_pdbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i),
DOPA => slice_a_pdbus_out(i),
DOPB => slice_b_pdbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S18_S18;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 2048 x 9 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S9_S9 : if (BRAM_PRIMITIVE = B16_S9_S9) generate
component RAMB16_S9_S9
port (
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
DIPA : in std_logic_vector (0 downto 0);
DIPB : in std_logic_vector (0 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0);
DOPA : out std_logic_vector (0 downto 0);
DOPB : out std_logic_vector (0 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 11; -- 2048 deep
Constant PRIM_PDBUS_WIDTH : integer := 1; -- 1 parity data bit
Constant PRIM_DBUS_WIDTH : integer := 8; -- 8 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
type pdbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_2048x9 : RAMB16_S9_S9
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
DIPA => slice_a_pdbus_in(i),
DIPB => slice_b_pdbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i),
DOPA => slice_a_pdbus_out(i),
DOPB => slice_b_pdbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S9_S9;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 4096 x 4 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S4_S4 : if (BRAM_PRIMITIVE = B16_S4_S4) generate
component RAMB16_S4_S4
port (
DIA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (11 downto 0);
ADDRB : in std_logic_vector (11 downto 0);
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (3 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 12; -- 4096 deep
Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 4; -- 4 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--type pdbus_slice_array is array(BRAM_NUM downto 1) of
-- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
--slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
--slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_4096x4 : RAMB16_S4_S4
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S4_S4;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 8192 x 2 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S2_S2 : if (BRAM_PRIMITIVE = B16_S2_S2) generate
component RAMB16_S2_S2
port (
DIA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (12 downto 0);
ADDRB : in std_logic_vector (12 downto 0);
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 13; -- 8192 deep
Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 2; -- 2 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--type pdbus_slice_array is array(BRAM_NUM downto 1) of
-- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
--slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
--slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_8192x2 : RAMB16_S2_S2
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S2_S2;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 16384 x 1 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S1_S1 : if (BRAM_PRIMITIVE = B16_S1_S1) generate
component RAMB16_S1_S1
port (
DIA : in std_logic_vector (0 downto 0);
DIB : in std_logic_vector (0 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (13 downto 0);
ADDRB : in std_logic_vector (13 downto 0);
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (0 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 14; -- 16384 deep
Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 1; -- 1 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--type pdbus_slice_array is array(BRAM_NUM downto 1) of
-- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
--slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
--slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_16384x1 : RAMB16_S1_S1
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S1_S1;
--==========================================================================
-- End of Virtex-II and Virtex-II Pro support
--///////////////////////////////////////////////////////////////////////////
--///////////////////////////////////////////////////////////////////////////
-- Start Spartan-II, Spartan-IIE, Virtex, and VirtexE support
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 4096 x 1 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S1_S1 : if (BRAM_PRIMITIVE = B4_S1_S1) generate
component RAMB4_S1_S1
port (
DIA : in std_logic_vector (0 downto 0);
DIB : in std_logic_vector (0 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (11 downto 0);
ADDRB : in std_logic_vector (11 downto 0);
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (0 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 12; -- 4096 deep
Constant PRIM_DBUS_WIDTH : integer := 1; -- 1 data bit
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_4096x1 : RAMB4_S1_S1
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S1_S1;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 2048 x 2 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S2_S2 : if (BRAM_PRIMITIVE = B4_S2_S2) generate
component RAMB4_S2_S2
port (
DIA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 11; -- 2048 deep
Constant PRIM_DBUS_WIDTH : integer := 2; -- 2 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_2048x2 : RAMB4_S2_S2
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S2_S2;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 1024 x 4 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S4_S4 : if (BRAM_PRIMITIVE = B4_S4_S4) generate
component RAMB4_S4_S4
port (
DIA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (9 downto 0);
ADDRB : in std_logic_vector (9 downto 0);
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (3 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 10; -- 1024 deep
Constant PRIM_DBUS_WIDTH : integer := 4; -- 4 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_1024x4 : RAMB4_S4_S4
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S4_S4;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 512 x 8 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S8_S8 : if (BRAM_PRIMITIVE = B4_S8_S8) generate
component RAMB4_S8_S8
port (
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (8 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 9; -- 512 deep
Constant PRIM_DBUS_WIDTH : integer := 8; -- 8 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_512x8 : RAMB4_S8_S8
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S8_S8;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 256 x 16 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S16_S16 : if (BRAM_PRIMITIVE = B4_S16_S16) generate
component RAMB4_S16_S16
port (DIA : in STD_LOGIC_VECTOR (15 downto 0);
DIB : in STD_LOGIC_VECTOR (15 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in STD_LOGIC_VECTOR (7 downto 0);
ADDRB : in STD_LOGIC_VECTOR (7 downto 0);
DOA : out STD_LOGIC_VECTOR (15 downto 0);
DOB : out STD_LOGIC_VECTOR (15 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 8; -- 256 deep
Constant PRIM_DBUS_WIDTH : integer := 16; -- 16 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_256x16 : RAMB4_S16_S16
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S16_S16;
--==========================================================================
UNSUPPORTED_FAMILY : if (BRAM_PRIMITIVE = indeterminate) generate
begin
-- assert (false)
-- report "Unsupported Part Family Selected or FIFO Depth/Width is invalid!"
-- severity failure;
--
end generate UNSUPPORTED_FAMILY;
end architecture implementation;
|
-------------------------------------------------------------------------------
-- $Id: pf_dpram_select.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_dpram_select.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
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-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
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-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_dpram_select.vhd
--
-- Description: This vhdl design file uses three input parameters describing
-- the desired storage depth, data width, and FPGA family type.
-- From these, the design selects the optimum Block RAM
-- primitive for the basic storage element and connects them
-- in parallel to accomodate the desired data width.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_dpram_select.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- DET Oct. 7, 2001 First Version
-- - Adopted design concepts from Goran Bilski's
-- opb_bram.vhd design in the formulation of this
-- design for the Mauna Loa packet FIFO dual port
-- core function.
--
-- DET Oct-31-2001
-- - Changed the generic input parameter C_FAMILY of type string
-- back to the boolean type parameter C_VIRTEX_II. XST support
-- change.
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library unisim;
use unisim.all; -- uses BRAM primitives
-------------------------------------------------------------------------------
entity pf_dpram_select is
generic (
C_DP_DATA_WIDTH : Integer := 32;
C_DP_ADDRESS_WIDTH : Integer := 9;
C_VIRTEX_II : Boolean := true
);
port (
-- Write Port signals
Wr_rst : In std_logic;
Wr_Clk : in std_logic;
Wr_Enable : In std_logic;
Wr_Req : In std_logic;
Wr_Address : in std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1);
Wr_Data : In std_logic_vector(0 to C_DP_DATA_WIDTH-1);
-- Read Port Signals
Rd_rst : In std_logic;
Rd_Clk : in std_logic;
Rd_Enable : In std_logic;
Rd_Address : in std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1);
Rd_Data : out std_logic_vector(0 to C_DP_DATA_WIDTH-1)
);
end entity pf_dpram_select;
architecture implementation of pf_dpram_select is
Type family_type is (
any ,
x4k ,
x4ke ,
x4kl ,
x4kex ,
x4kxl ,
x4kxv ,
x4kxla ,
spartan ,
spartanxl,
spartan2 ,
spartan2e,
virtex ,
virtexe ,
virtex2 ,
virtex2p ,
unsupported
);
Type bram_prim_type is (
use_srl ,
B4_S1_S1 ,
B4_S2_S2 ,
B4_S4_S4 ,
B4_S8_S8 ,
B4_S16_S16 ,
B16_S1_S1 ,
B16_S2_S2 ,
B16_S4_S4 ,
B16_S9_S9 ,
B16_S18_S18 ,
B16_S36_S36 ,
indeterminate
);
-----------------------------------------------------------------------------
-- This function converts the input C_VIRTEX_II boolean type to an enumerated
-- type. Only Virtex and Virtex II types are currently supported. This
-- used to convert a string to a family type function but string support in
-- the synthesis tools was found to be mutually exclusive between Synplicity
-- and XST.
-----------------------------------------------------------------------------
function get_prim_family (vertex2_select : boolean) return family_type is
Variable prim_family : family_type;
begin
If (vertex2_select) Then
prim_family := virtex2;
else
prim_family := virtex;
End if;
Return (prim_family);
end function get_prim_family;
-----------------------------------------------------------------------------
-- This function chooses the optimum BRAM primitive to utilize as
-- specified by the inputs for data depth, data width, and FPGA part family.
-----------------------------------------------------------------------------
function get_bram_primitive (target_depth: integer;
target_width: integer;
family : family_type )
return bram_prim_type is
Variable primitive : bram_prim_type;
begin
Case family Is
When virtex2p | virtex2 =>
Case target_depth Is
When 1 | 2 =>
primitive := indeterminate; -- depth is too small for BRAM
-- based fifo control logic
When 4 | 8 | 16 =>
-- primitive := use_srl; -- activate when SRL FIFO incorporated
Case target_width Is -- use BRAM for now
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When 5 | 6 | 7 | 8 | 9 =>
primitive := B16_S9_S9;
When 10 | 11 | 12 | 13 | 14 |
15 | 16 | 17 | 18 =>
primitive := B16_S18_S18;
When others =>
primitive := B16_S36_S36;
End case;
when 32 | 64 | 128 | 256 | 512 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When 5 | 6 | 7 | 8 | 9 =>
primitive := B16_S9_S9;
When 10 | 11 | 12 | 13 | 14 |
15 | 16 | 17 | 18 =>
primitive := B16_S18_S18;
When others =>
primitive := B16_S36_S36;
End case;
When 1024 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When 5 | 6 | 7 | 8 | 9 =>
primitive := B16_S9_S9;
When others =>
primitive := B16_S18_S18;
End case;
When 2048 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When others =>
primitive := B16_S9_S9;
End case;
When 4096 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When others =>
primitive := B16_S4_S4;
End case;
When 8192 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When others =>
primitive := B16_S2_S2;
End case;
When 16384 =>
primitive := B16_S1_S1;
When others =>
primitive := indeterminate;
End case;
When spartan2 | spartan2e | virtex | virtexe =>
Case target_depth Is
When 1 | 2 =>
primitive := indeterminate; -- depth is too small for BRAM
-- based fifo control logic
When 4 | 8 | 16 =>
-- primitive := use_srl; -- activate this when SRL FIFO is
-- incorporated
Case target_width Is -- use BRAM for now
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When 3 | 4 =>
primitive := B4_S4_S4;
When 5 | 6 | 7 | 8 =>
primitive := B4_S8_S8;
When others =>
primitive := B4_S16_S16;
End case;
when 32 | 64 | 128 | 256 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When 3 | 4 =>
primitive := B4_S4_S4;
When 5 | 6 | 7 | 8 =>
primitive := B4_S8_S8;
When others =>
primitive := B4_S16_S16;
End case;
when 512 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When 3 | 4 =>
primitive := B4_S4_S4;
When others =>
primitive := B4_S8_S8;
End case;
When 1024 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When others =>
primitive := B4_S4_S4;
End case;
When 2048 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When others =>
primitive := B4_S2_S2;
End case;
When 4096 =>
primitive := B4_S1_S1;
When others =>
primitive := indeterminate;
End case;
When others =>
primitive := indeterminate;
End case;
Return primitive;
end function get_bram_primitive;
-----------------------------------------------------------------------------
-- This function calculates the number of BRAM primitives required as
-- specified by the inputs for data width and BRAM primitive type.
-----------------------------------------------------------------------------
function get_num_prims (bram_prim : bram_prim_type;
mem_width : integer)
return integer is
Variable bram_num : integer;
begin
Case bram_prim Is
When B16_S1_S1 | B4_S1_S1 =>
bram_num := mem_width;
When B16_S2_S2 | B4_S2_S2 =>
bram_num := (mem_width+1)/2;
When B16_S4_S4 | B4_S4_S4 =>
bram_num := (mem_width+3)/4;
When B4_S8_S8 =>
bram_num := (mem_width+7)/8;
When B16_S9_S9 =>
bram_num := (mem_width+8)/9;
When B4_S16_S16 =>
bram_num := (mem_width+15)/16;
When B16_S18_S18 =>
bram_num := (mem_width+17)/18;
When B16_S36_S36 =>
bram_num := (mem_width+35)/36;
When others =>
bram_num := 1;
End case;
Return (bram_num);
end function get_num_prims;
-- Now set the global CONSTANTS needed for IF-Generates
-- Determine the number of BRAM storage locations needed
constant FIFO_DEPTH : Integer := 2**C_DP_ADDRESS_WIDTH;
-- Convert the input C_VIRTEX_II generic boolean to enumerated type
Constant BRAM_FAMILY : family_type :=
get_prim_family(C_VIRTEX_II);
-- Select the optimum BRAM primitive to use
constant BRAM_PRIMITIVE : bram_prim_type :=
get_bram_primitive(FIFO_DEPTH,
C_DP_DATA_WIDTH,
BRAM_FAMILY);
-- Calculate how many of the selected primitives are needed
-- to populate the desired data width
constant BRAM_NUM : integer :=
get_num_prims(BRAM_PRIMITIVE,
C_DP_DATA_WIDTH);
begin -- architecture
----------------------------------------------------------------------------
-- Using VII 512 x 36 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S36_S36 : if (BRAM_PRIMITIVE = B16_S36_S36) generate
component RAMB16_S36_S36
port (DIA : in STD_LOGIC_VECTOR (31 downto 0);
DIB : in STD_LOGIC_VECTOR (31 downto 0);
DIPA : in STD_LOGIC_VECTOR (3 downto 0);
DIPB : in STD_LOGIC_VECTOR (3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in STD_LOGIC_VECTOR (8 downto 0);
ADDRB : in STD_LOGIC_VECTOR (8 downto 0);
DOA : out STD_LOGIC_VECTOR (31 downto 0);
DOB : out STD_LOGIC_VECTOR (31 downto 0);
DOPA : out STD_LOGIC_VECTOR (3 downto 0);
DOPB : out STD_LOGIC_VECTOR (3 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 9; -- 512 deep
Constant PRIM_PDBUS_WIDTH : integer := 4; -- 4 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 32; -- 4 parity data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
type pdbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_512x32 : RAMB16_S36_S36
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
DIPA => slice_a_pdbus_in(i),
DIPB => slice_b_pdbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i),
DOPA => slice_a_pdbus_out(i),
DOPB => slice_b_pdbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S36_S36;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 1024 x 18 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S18_S18 : if (BRAM_PRIMITIVE = B16_S18_S18) generate
component RAMB16_S18_S18
port (DIA : in STD_LOGIC_VECTOR (15 downto 0);
DIB : in STD_LOGIC_VECTOR (15 downto 0);
DIPA : in STD_LOGIC_VECTOR (1 downto 0);
DIPB : in STD_LOGIC_VECTOR (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in STD_LOGIC_VECTOR (9 downto 0);
ADDRB : in STD_LOGIC_VECTOR (9 downto 0);
DOA : out STD_LOGIC_VECTOR (15 downto 0);
DOB : out STD_LOGIC_VECTOR (15 downto 0);
DOPA : out STD_LOGIC_VECTOR (1 downto 0);
DOPB : out STD_LOGIC_VECTOR (1 downto 0)
);
end component;
Constant PRIM_ADDR_WIDTH : integer := 10; -- 1024 deep
Constant PRIM_PDBUS_WIDTH : integer := 2; -- 2 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 16; -- 16 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
type pdbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_1024x18 : RAMB16_S18_S18
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
DIPA => slice_a_pdbus_in(i),
DIPB => slice_b_pdbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i),
DOPA => slice_a_pdbus_out(i),
DOPB => slice_b_pdbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S18_S18;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 2048 x 9 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S9_S9 : if (BRAM_PRIMITIVE = B16_S9_S9) generate
component RAMB16_S9_S9
port (
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
DIPA : in std_logic_vector (0 downto 0);
DIPB : in std_logic_vector (0 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0);
DOPA : out std_logic_vector (0 downto 0);
DOPB : out std_logic_vector (0 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 11; -- 2048 deep
Constant PRIM_PDBUS_WIDTH : integer := 1; -- 1 parity data bit
Constant PRIM_DBUS_WIDTH : integer := 8; -- 8 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
type pdbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_2048x9 : RAMB16_S9_S9
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
DIPA => slice_a_pdbus_in(i),
DIPB => slice_b_pdbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i),
DOPA => slice_a_pdbus_out(i),
DOPB => slice_b_pdbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S9_S9;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 4096 x 4 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S4_S4 : if (BRAM_PRIMITIVE = B16_S4_S4) generate
component RAMB16_S4_S4
port (
DIA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (11 downto 0);
ADDRB : in std_logic_vector (11 downto 0);
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (3 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 12; -- 4096 deep
Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 4; -- 4 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--type pdbus_slice_array is array(BRAM_NUM downto 1) of
-- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
--slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
--slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_4096x4 : RAMB16_S4_S4
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S4_S4;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 8192 x 2 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S2_S2 : if (BRAM_PRIMITIVE = B16_S2_S2) generate
component RAMB16_S2_S2
port (
DIA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (12 downto 0);
ADDRB : in std_logic_vector (12 downto 0);
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 13; -- 8192 deep
Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 2; -- 2 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--type pdbus_slice_array is array(BRAM_NUM downto 1) of
-- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
--slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
--slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_8192x2 : RAMB16_S2_S2
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S2_S2;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 16384 x 1 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S1_S1 : if (BRAM_PRIMITIVE = B16_S1_S1) generate
component RAMB16_S1_S1
port (
DIA : in std_logic_vector (0 downto 0);
DIB : in std_logic_vector (0 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (13 downto 0);
ADDRB : in std_logic_vector (13 downto 0);
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (0 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 14; -- 16384 deep
Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 1; -- 1 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--type pdbus_slice_array is array(BRAM_NUM downto 1) of
-- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
--slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
--slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_16384x1 : RAMB16_S1_S1
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S1_S1;
--==========================================================================
-- End of Virtex-II and Virtex-II Pro support
--///////////////////////////////////////////////////////////////////////////
--///////////////////////////////////////////////////////////////////////////
-- Start Spartan-II, Spartan-IIE, Virtex, and VirtexE support
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 4096 x 1 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S1_S1 : if (BRAM_PRIMITIVE = B4_S1_S1) generate
component RAMB4_S1_S1
port (
DIA : in std_logic_vector (0 downto 0);
DIB : in std_logic_vector (0 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (11 downto 0);
ADDRB : in std_logic_vector (11 downto 0);
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (0 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 12; -- 4096 deep
Constant PRIM_DBUS_WIDTH : integer := 1; -- 1 data bit
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_4096x1 : RAMB4_S1_S1
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S1_S1;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 2048 x 2 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S2_S2 : if (BRAM_PRIMITIVE = B4_S2_S2) generate
component RAMB4_S2_S2
port (
DIA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 11; -- 2048 deep
Constant PRIM_DBUS_WIDTH : integer := 2; -- 2 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_2048x2 : RAMB4_S2_S2
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S2_S2;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 1024 x 4 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S4_S4 : if (BRAM_PRIMITIVE = B4_S4_S4) generate
component RAMB4_S4_S4
port (
DIA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (9 downto 0);
ADDRB : in std_logic_vector (9 downto 0);
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (3 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 10; -- 1024 deep
Constant PRIM_DBUS_WIDTH : integer := 4; -- 4 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_1024x4 : RAMB4_S4_S4
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S4_S4;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 512 x 8 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S8_S8 : if (BRAM_PRIMITIVE = B4_S8_S8) generate
component RAMB4_S8_S8
port (
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (8 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 9; -- 512 deep
Constant PRIM_DBUS_WIDTH : integer := 8; -- 8 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_512x8 : RAMB4_S8_S8
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S8_S8;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 256 x 16 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S16_S16 : if (BRAM_PRIMITIVE = B4_S16_S16) generate
component RAMB4_S16_S16
port (DIA : in STD_LOGIC_VECTOR (15 downto 0);
DIB : in STD_LOGIC_VECTOR (15 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in STD_LOGIC_VECTOR (7 downto 0);
ADDRB : in STD_LOGIC_VECTOR (7 downto 0);
DOA : out STD_LOGIC_VECTOR (15 downto 0);
DOB : out STD_LOGIC_VECTOR (15 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 8; -- 256 deep
Constant PRIM_DBUS_WIDTH : integer := 16; -- 16 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_256x16 : RAMB4_S16_S16
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S16_S16;
--==========================================================================
UNSUPPORTED_FAMILY : if (BRAM_PRIMITIVE = indeterminate) generate
begin
-- assert (false)
-- report "Unsupported Part Family Selected or FIFO Depth/Width is invalid!"
-- severity failure;
--
end generate UNSUPPORTED_FAMILY;
end architecture implementation;
|
-------------------------------------------------------------------------------
-- $Id: pf_dpram_select.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_dpram_select.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
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-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_dpram_select.vhd
--
-- Description: This vhdl design file uses three input parameters describing
-- the desired storage depth, data width, and FPGA family type.
-- From these, the design selects the optimum Block RAM
-- primitive for the basic storage element and connects them
-- in parallel to accomodate the desired data width.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_dpram_select.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- DET Oct. 7, 2001 First Version
-- - Adopted design concepts from Goran Bilski's
-- opb_bram.vhd design in the formulation of this
-- design for the Mauna Loa packet FIFO dual port
-- core function.
--
-- DET Oct-31-2001
-- - Changed the generic input parameter C_FAMILY of type string
-- back to the boolean type parameter C_VIRTEX_II. XST support
-- change.
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library unisim;
use unisim.all; -- uses BRAM primitives
-------------------------------------------------------------------------------
entity pf_dpram_select is
generic (
C_DP_DATA_WIDTH : Integer := 32;
C_DP_ADDRESS_WIDTH : Integer := 9;
C_VIRTEX_II : Boolean := true
);
port (
-- Write Port signals
Wr_rst : In std_logic;
Wr_Clk : in std_logic;
Wr_Enable : In std_logic;
Wr_Req : In std_logic;
Wr_Address : in std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1);
Wr_Data : In std_logic_vector(0 to C_DP_DATA_WIDTH-1);
-- Read Port Signals
Rd_rst : In std_logic;
Rd_Clk : in std_logic;
Rd_Enable : In std_logic;
Rd_Address : in std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1);
Rd_Data : out std_logic_vector(0 to C_DP_DATA_WIDTH-1)
);
end entity pf_dpram_select;
architecture implementation of pf_dpram_select is
Type family_type is (
any ,
x4k ,
x4ke ,
x4kl ,
x4kex ,
x4kxl ,
x4kxv ,
x4kxla ,
spartan ,
spartanxl,
spartan2 ,
spartan2e,
virtex ,
virtexe ,
virtex2 ,
virtex2p ,
unsupported
);
Type bram_prim_type is (
use_srl ,
B4_S1_S1 ,
B4_S2_S2 ,
B4_S4_S4 ,
B4_S8_S8 ,
B4_S16_S16 ,
B16_S1_S1 ,
B16_S2_S2 ,
B16_S4_S4 ,
B16_S9_S9 ,
B16_S18_S18 ,
B16_S36_S36 ,
indeterminate
);
-----------------------------------------------------------------------------
-- This function converts the input C_VIRTEX_II boolean type to an enumerated
-- type. Only Virtex and Virtex II types are currently supported. This
-- used to convert a string to a family type function but string support in
-- the synthesis tools was found to be mutually exclusive between Synplicity
-- and XST.
-----------------------------------------------------------------------------
function get_prim_family (vertex2_select : boolean) return family_type is
Variable prim_family : family_type;
begin
If (vertex2_select) Then
prim_family := virtex2;
else
prim_family := virtex;
End if;
Return (prim_family);
end function get_prim_family;
-----------------------------------------------------------------------------
-- This function chooses the optimum BRAM primitive to utilize as
-- specified by the inputs for data depth, data width, and FPGA part family.
-----------------------------------------------------------------------------
function get_bram_primitive (target_depth: integer;
target_width: integer;
family : family_type )
return bram_prim_type is
Variable primitive : bram_prim_type;
begin
Case family Is
When virtex2p | virtex2 =>
Case target_depth Is
When 1 | 2 =>
primitive := indeterminate; -- depth is too small for BRAM
-- based fifo control logic
When 4 | 8 | 16 =>
-- primitive := use_srl; -- activate when SRL FIFO incorporated
Case target_width Is -- use BRAM for now
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When 5 | 6 | 7 | 8 | 9 =>
primitive := B16_S9_S9;
When 10 | 11 | 12 | 13 | 14 |
15 | 16 | 17 | 18 =>
primitive := B16_S18_S18;
When others =>
primitive := B16_S36_S36;
End case;
when 32 | 64 | 128 | 256 | 512 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When 5 | 6 | 7 | 8 | 9 =>
primitive := B16_S9_S9;
When 10 | 11 | 12 | 13 | 14 |
15 | 16 | 17 | 18 =>
primitive := B16_S18_S18;
When others =>
primitive := B16_S36_S36;
End case;
When 1024 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When 5 | 6 | 7 | 8 | 9 =>
primitive := B16_S9_S9;
When others =>
primitive := B16_S18_S18;
End case;
When 2048 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When others =>
primitive := B16_S9_S9;
End case;
When 4096 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When others =>
primitive := B16_S4_S4;
End case;
When 8192 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When others =>
primitive := B16_S2_S2;
End case;
When 16384 =>
primitive := B16_S1_S1;
When others =>
primitive := indeterminate;
End case;
When spartan2 | spartan2e | virtex | virtexe =>
Case target_depth Is
When 1 | 2 =>
primitive := indeterminate; -- depth is too small for BRAM
-- based fifo control logic
When 4 | 8 | 16 =>
-- primitive := use_srl; -- activate this when SRL FIFO is
-- incorporated
Case target_width Is -- use BRAM for now
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When 3 | 4 =>
primitive := B4_S4_S4;
When 5 | 6 | 7 | 8 =>
primitive := B4_S8_S8;
When others =>
primitive := B4_S16_S16;
End case;
when 32 | 64 | 128 | 256 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When 3 | 4 =>
primitive := B4_S4_S4;
When 5 | 6 | 7 | 8 =>
primitive := B4_S8_S8;
When others =>
primitive := B4_S16_S16;
End case;
when 512 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When 3 | 4 =>
primitive := B4_S4_S4;
When others =>
primitive := B4_S8_S8;
End case;
When 1024 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When others =>
primitive := B4_S4_S4;
End case;
When 2048 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When others =>
primitive := B4_S2_S2;
End case;
When 4096 =>
primitive := B4_S1_S1;
When others =>
primitive := indeterminate;
End case;
When others =>
primitive := indeterminate;
End case;
Return primitive;
end function get_bram_primitive;
-----------------------------------------------------------------------------
-- This function calculates the number of BRAM primitives required as
-- specified by the inputs for data width and BRAM primitive type.
-----------------------------------------------------------------------------
function get_num_prims (bram_prim : bram_prim_type;
mem_width : integer)
return integer is
Variable bram_num : integer;
begin
Case bram_prim Is
When B16_S1_S1 | B4_S1_S1 =>
bram_num := mem_width;
When B16_S2_S2 | B4_S2_S2 =>
bram_num := (mem_width+1)/2;
When B16_S4_S4 | B4_S4_S4 =>
bram_num := (mem_width+3)/4;
When B4_S8_S8 =>
bram_num := (mem_width+7)/8;
When B16_S9_S9 =>
bram_num := (mem_width+8)/9;
When B4_S16_S16 =>
bram_num := (mem_width+15)/16;
When B16_S18_S18 =>
bram_num := (mem_width+17)/18;
When B16_S36_S36 =>
bram_num := (mem_width+35)/36;
When others =>
bram_num := 1;
End case;
Return (bram_num);
end function get_num_prims;
-- Now set the global CONSTANTS needed for IF-Generates
-- Determine the number of BRAM storage locations needed
constant FIFO_DEPTH : Integer := 2**C_DP_ADDRESS_WIDTH;
-- Convert the input C_VIRTEX_II generic boolean to enumerated type
Constant BRAM_FAMILY : family_type :=
get_prim_family(C_VIRTEX_II);
-- Select the optimum BRAM primitive to use
constant BRAM_PRIMITIVE : bram_prim_type :=
get_bram_primitive(FIFO_DEPTH,
C_DP_DATA_WIDTH,
BRAM_FAMILY);
-- Calculate how many of the selected primitives are needed
-- to populate the desired data width
constant BRAM_NUM : integer :=
get_num_prims(BRAM_PRIMITIVE,
C_DP_DATA_WIDTH);
begin -- architecture
----------------------------------------------------------------------------
-- Using VII 512 x 36 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S36_S36 : if (BRAM_PRIMITIVE = B16_S36_S36) generate
component RAMB16_S36_S36
port (DIA : in STD_LOGIC_VECTOR (31 downto 0);
DIB : in STD_LOGIC_VECTOR (31 downto 0);
DIPA : in STD_LOGIC_VECTOR (3 downto 0);
DIPB : in STD_LOGIC_VECTOR (3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in STD_LOGIC_VECTOR (8 downto 0);
ADDRB : in STD_LOGIC_VECTOR (8 downto 0);
DOA : out STD_LOGIC_VECTOR (31 downto 0);
DOB : out STD_LOGIC_VECTOR (31 downto 0);
DOPA : out STD_LOGIC_VECTOR (3 downto 0);
DOPB : out STD_LOGIC_VECTOR (3 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 9; -- 512 deep
Constant PRIM_PDBUS_WIDTH : integer := 4; -- 4 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 32; -- 4 parity data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
type pdbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_512x32 : RAMB16_S36_S36
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
DIPA => slice_a_pdbus_in(i),
DIPB => slice_b_pdbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i),
DOPA => slice_a_pdbus_out(i),
DOPB => slice_b_pdbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S36_S36;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 1024 x 18 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S18_S18 : if (BRAM_PRIMITIVE = B16_S18_S18) generate
component RAMB16_S18_S18
port (DIA : in STD_LOGIC_VECTOR (15 downto 0);
DIB : in STD_LOGIC_VECTOR (15 downto 0);
DIPA : in STD_LOGIC_VECTOR (1 downto 0);
DIPB : in STD_LOGIC_VECTOR (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in STD_LOGIC_VECTOR (9 downto 0);
ADDRB : in STD_LOGIC_VECTOR (9 downto 0);
DOA : out STD_LOGIC_VECTOR (15 downto 0);
DOB : out STD_LOGIC_VECTOR (15 downto 0);
DOPA : out STD_LOGIC_VECTOR (1 downto 0);
DOPB : out STD_LOGIC_VECTOR (1 downto 0)
);
end component;
Constant PRIM_ADDR_WIDTH : integer := 10; -- 1024 deep
Constant PRIM_PDBUS_WIDTH : integer := 2; -- 2 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 16; -- 16 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
type pdbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_1024x18 : RAMB16_S18_S18
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
DIPA => slice_a_pdbus_in(i),
DIPB => slice_b_pdbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i),
DOPA => slice_a_pdbus_out(i),
DOPB => slice_b_pdbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S18_S18;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 2048 x 9 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S9_S9 : if (BRAM_PRIMITIVE = B16_S9_S9) generate
component RAMB16_S9_S9
port (
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
DIPA : in std_logic_vector (0 downto 0);
DIPB : in std_logic_vector (0 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0);
DOPA : out std_logic_vector (0 downto 0);
DOPB : out std_logic_vector (0 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 11; -- 2048 deep
Constant PRIM_PDBUS_WIDTH : integer := 1; -- 1 parity data bit
Constant PRIM_DBUS_WIDTH : integer := 8; -- 8 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
type pdbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_2048x9 : RAMB16_S9_S9
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
DIPA => slice_a_pdbus_in(i),
DIPB => slice_b_pdbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i),
DOPA => slice_a_pdbus_out(i),
DOPB => slice_b_pdbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S9_S9;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 4096 x 4 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S4_S4 : if (BRAM_PRIMITIVE = B16_S4_S4) generate
component RAMB16_S4_S4
port (
DIA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (11 downto 0);
ADDRB : in std_logic_vector (11 downto 0);
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (3 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 12; -- 4096 deep
Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 4; -- 4 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--type pdbus_slice_array is array(BRAM_NUM downto 1) of
-- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
--slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
--slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_4096x4 : RAMB16_S4_S4
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S4_S4;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 8192 x 2 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S2_S2 : if (BRAM_PRIMITIVE = B16_S2_S2) generate
component RAMB16_S2_S2
port (
DIA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (12 downto 0);
ADDRB : in std_logic_vector (12 downto 0);
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 13; -- 8192 deep
Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 2; -- 2 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--type pdbus_slice_array is array(BRAM_NUM downto 1) of
-- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
--slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
--slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_8192x2 : RAMB16_S2_S2
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S2_S2;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 16384 x 1 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S1_S1 : if (BRAM_PRIMITIVE = B16_S1_S1) generate
component RAMB16_S1_S1
port (
DIA : in std_logic_vector (0 downto 0);
DIB : in std_logic_vector (0 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (13 downto 0);
ADDRB : in std_logic_vector (13 downto 0);
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (0 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 14; -- 16384 deep
Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 1; -- 1 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--type pdbus_slice_array is array(BRAM_NUM downto 1) of
-- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
--slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
--slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_16384x1 : RAMB16_S1_S1
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S1_S1;
--==========================================================================
-- End of Virtex-II and Virtex-II Pro support
--///////////////////////////////////////////////////////////////////////////
--///////////////////////////////////////////////////////////////////////////
-- Start Spartan-II, Spartan-IIE, Virtex, and VirtexE support
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 4096 x 1 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S1_S1 : if (BRAM_PRIMITIVE = B4_S1_S1) generate
component RAMB4_S1_S1
port (
DIA : in std_logic_vector (0 downto 0);
DIB : in std_logic_vector (0 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (11 downto 0);
ADDRB : in std_logic_vector (11 downto 0);
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (0 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 12; -- 4096 deep
Constant PRIM_DBUS_WIDTH : integer := 1; -- 1 data bit
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_4096x1 : RAMB4_S1_S1
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S1_S1;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 2048 x 2 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S2_S2 : if (BRAM_PRIMITIVE = B4_S2_S2) generate
component RAMB4_S2_S2
port (
DIA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 11; -- 2048 deep
Constant PRIM_DBUS_WIDTH : integer := 2; -- 2 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_2048x2 : RAMB4_S2_S2
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S2_S2;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 1024 x 4 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S4_S4 : if (BRAM_PRIMITIVE = B4_S4_S4) generate
component RAMB4_S4_S4
port (
DIA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (9 downto 0);
ADDRB : in std_logic_vector (9 downto 0);
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (3 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 10; -- 1024 deep
Constant PRIM_DBUS_WIDTH : integer := 4; -- 4 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_1024x4 : RAMB4_S4_S4
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S4_S4;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 512 x 8 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S8_S8 : if (BRAM_PRIMITIVE = B4_S8_S8) generate
component RAMB4_S8_S8
port (
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (8 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 9; -- 512 deep
Constant PRIM_DBUS_WIDTH : integer := 8; -- 8 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_512x8 : RAMB4_S8_S8
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S8_S8;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 256 x 16 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S16_S16 : if (BRAM_PRIMITIVE = B4_S16_S16) generate
component RAMB4_S16_S16
port (DIA : in STD_LOGIC_VECTOR (15 downto 0);
DIB : in STD_LOGIC_VECTOR (15 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in STD_LOGIC_VECTOR (7 downto 0);
ADDRB : in STD_LOGIC_VECTOR (7 downto 0);
DOA : out STD_LOGIC_VECTOR (15 downto 0);
DOB : out STD_LOGIC_VECTOR (15 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 8; -- 256 deep
Constant PRIM_DBUS_WIDTH : integer := 16; -- 16 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_256x16 : RAMB4_S16_S16
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S16_S16;
--==========================================================================
UNSUPPORTED_FAMILY : if (BRAM_PRIMITIVE = indeterminate) generate
begin
-- assert (false)
-- report "Unsupported Part Family Selected or FIFO Depth/Width is invalid!"
-- severity failure;
--
end generate UNSUPPORTED_FAMILY;
end architecture implementation;
|
-------------------------------------------------------------------------------
-- $Id: pf_dpram_select.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_dpram_select.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_dpram_select.vhd
--
-- Description: This vhdl design file uses three input parameters describing
-- the desired storage depth, data width, and FPGA family type.
-- From these, the design selects the optimum Block RAM
-- primitive for the basic storage element and connects them
-- in parallel to accomodate the desired data width.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_dpram_select.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- DET Oct. 7, 2001 First Version
-- - Adopted design concepts from Goran Bilski's
-- opb_bram.vhd design in the formulation of this
-- design for the Mauna Loa packet FIFO dual port
-- core function.
--
-- DET Oct-31-2001
-- - Changed the generic input parameter C_FAMILY of type string
-- back to the boolean type parameter C_VIRTEX_II. XST support
-- change.
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library unisim;
use unisim.all; -- uses BRAM primitives
-------------------------------------------------------------------------------
entity pf_dpram_select is
generic (
C_DP_DATA_WIDTH : Integer := 32;
C_DP_ADDRESS_WIDTH : Integer := 9;
C_VIRTEX_II : Boolean := true
);
port (
-- Write Port signals
Wr_rst : In std_logic;
Wr_Clk : in std_logic;
Wr_Enable : In std_logic;
Wr_Req : In std_logic;
Wr_Address : in std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1);
Wr_Data : In std_logic_vector(0 to C_DP_DATA_WIDTH-1);
-- Read Port Signals
Rd_rst : In std_logic;
Rd_Clk : in std_logic;
Rd_Enable : In std_logic;
Rd_Address : in std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1);
Rd_Data : out std_logic_vector(0 to C_DP_DATA_WIDTH-1)
);
end entity pf_dpram_select;
architecture implementation of pf_dpram_select is
Type family_type is (
any ,
x4k ,
x4ke ,
x4kl ,
x4kex ,
x4kxl ,
x4kxv ,
x4kxla ,
spartan ,
spartanxl,
spartan2 ,
spartan2e,
virtex ,
virtexe ,
virtex2 ,
virtex2p ,
unsupported
);
Type bram_prim_type is (
use_srl ,
B4_S1_S1 ,
B4_S2_S2 ,
B4_S4_S4 ,
B4_S8_S8 ,
B4_S16_S16 ,
B16_S1_S1 ,
B16_S2_S2 ,
B16_S4_S4 ,
B16_S9_S9 ,
B16_S18_S18 ,
B16_S36_S36 ,
indeterminate
);
-----------------------------------------------------------------------------
-- This function converts the input C_VIRTEX_II boolean type to an enumerated
-- type. Only Virtex and Virtex II types are currently supported. This
-- used to convert a string to a family type function but string support in
-- the synthesis tools was found to be mutually exclusive between Synplicity
-- and XST.
-----------------------------------------------------------------------------
function get_prim_family (vertex2_select : boolean) return family_type is
Variable prim_family : family_type;
begin
If (vertex2_select) Then
prim_family := virtex2;
else
prim_family := virtex;
End if;
Return (prim_family);
end function get_prim_family;
-----------------------------------------------------------------------------
-- This function chooses the optimum BRAM primitive to utilize as
-- specified by the inputs for data depth, data width, and FPGA part family.
-----------------------------------------------------------------------------
function get_bram_primitive (target_depth: integer;
target_width: integer;
family : family_type )
return bram_prim_type is
Variable primitive : bram_prim_type;
begin
Case family Is
When virtex2p | virtex2 =>
Case target_depth Is
When 1 | 2 =>
primitive := indeterminate; -- depth is too small for BRAM
-- based fifo control logic
When 4 | 8 | 16 =>
-- primitive := use_srl; -- activate when SRL FIFO incorporated
Case target_width Is -- use BRAM for now
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When 5 | 6 | 7 | 8 | 9 =>
primitive := B16_S9_S9;
When 10 | 11 | 12 | 13 | 14 |
15 | 16 | 17 | 18 =>
primitive := B16_S18_S18;
When others =>
primitive := B16_S36_S36;
End case;
when 32 | 64 | 128 | 256 | 512 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When 5 | 6 | 7 | 8 | 9 =>
primitive := B16_S9_S9;
When 10 | 11 | 12 | 13 | 14 |
15 | 16 | 17 | 18 =>
primitive := B16_S18_S18;
When others =>
primitive := B16_S36_S36;
End case;
When 1024 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When 5 | 6 | 7 | 8 | 9 =>
primitive := B16_S9_S9;
When others =>
primitive := B16_S18_S18;
End case;
When 2048 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When others =>
primitive := B16_S9_S9;
End case;
When 4096 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When others =>
primitive := B16_S4_S4;
End case;
When 8192 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When others =>
primitive := B16_S2_S2;
End case;
When 16384 =>
primitive := B16_S1_S1;
When others =>
primitive := indeterminate;
End case;
When spartan2 | spartan2e | virtex | virtexe =>
Case target_depth Is
When 1 | 2 =>
primitive := indeterminate; -- depth is too small for BRAM
-- based fifo control logic
When 4 | 8 | 16 =>
-- primitive := use_srl; -- activate this when SRL FIFO is
-- incorporated
Case target_width Is -- use BRAM for now
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When 3 | 4 =>
primitive := B4_S4_S4;
When 5 | 6 | 7 | 8 =>
primitive := B4_S8_S8;
When others =>
primitive := B4_S16_S16;
End case;
when 32 | 64 | 128 | 256 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When 3 | 4 =>
primitive := B4_S4_S4;
When 5 | 6 | 7 | 8 =>
primitive := B4_S8_S8;
When others =>
primitive := B4_S16_S16;
End case;
when 512 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When 3 | 4 =>
primitive := B4_S4_S4;
When others =>
primitive := B4_S8_S8;
End case;
When 1024 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When others =>
primitive := B4_S4_S4;
End case;
When 2048 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When others =>
primitive := B4_S2_S2;
End case;
When 4096 =>
primitive := B4_S1_S1;
When others =>
primitive := indeterminate;
End case;
When others =>
primitive := indeterminate;
End case;
Return primitive;
end function get_bram_primitive;
-----------------------------------------------------------------------------
-- This function calculates the number of BRAM primitives required as
-- specified by the inputs for data width and BRAM primitive type.
-----------------------------------------------------------------------------
function get_num_prims (bram_prim : bram_prim_type;
mem_width : integer)
return integer is
Variable bram_num : integer;
begin
Case bram_prim Is
When B16_S1_S1 | B4_S1_S1 =>
bram_num := mem_width;
When B16_S2_S2 | B4_S2_S2 =>
bram_num := (mem_width+1)/2;
When B16_S4_S4 | B4_S4_S4 =>
bram_num := (mem_width+3)/4;
When B4_S8_S8 =>
bram_num := (mem_width+7)/8;
When B16_S9_S9 =>
bram_num := (mem_width+8)/9;
When B4_S16_S16 =>
bram_num := (mem_width+15)/16;
When B16_S18_S18 =>
bram_num := (mem_width+17)/18;
When B16_S36_S36 =>
bram_num := (mem_width+35)/36;
When others =>
bram_num := 1;
End case;
Return (bram_num);
end function get_num_prims;
-- Now set the global CONSTANTS needed for IF-Generates
-- Determine the number of BRAM storage locations needed
constant FIFO_DEPTH : Integer := 2**C_DP_ADDRESS_WIDTH;
-- Convert the input C_VIRTEX_II generic boolean to enumerated type
Constant BRAM_FAMILY : family_type :=
get_prim_family(C_VIRTEX_II);
-- Select the optimum BRAM primitive to use
constant BRAM_PRIMITIVE : bram_prim_type :=
get_bram_primitive(FIFO_DEPTH,
C_DP_DATA_WIDTH,
BRAM_FAMILY);
-- Calculate how many of the selected primitives are needed
-- to populate the desired data width
constant BRAM_NUM : integer :=
get_num_prims(BRAM_PRIMITIVE,
C_DP_DATA_WIDTH);
begin -- architecture
----------------------------------------------------------------------------
-- Using VII 512 x 36 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S36_S36 : if (BRAM_PRIMITIVE = B16_S36_S36) generate
component RAMB16_S36_S36
port (DIA : in STD_LOGIC_VECTOR (31 downto 0);
DIB : in STD_LOGIC_VECTOR (31 downto 0);
DIPA : in STD_LOGIC_VECTOR (3 downto 0);
DIPB : in STD_LOGIC_VECTOR (3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in STD_LOGIC_VECTOR (8 downto 0);
ADDRB : in STD_LOGIC_VECTOR (8 downto 0);
DOA : out STD_LOGIC_VECTOR (31 downto 0);
DOB : out STD_LOGIC_VECTOR (31 downto 0);
DOPA : out STD_LOGIC_VECTOR (3 downto 0);
DOPB : out STD_LOGIC_VECTOR (3 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 9; -- 512 deep
Constant PRIM_PDBUS_WIDTH : integer := 4; -- 4 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 32; -- 4 parity data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
type pdbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_512x32 : RAMB16_S36_S36
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
DIPA => slice_a_pdbus_in(i),
DIPB => slice_b_pdbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i),
DOPA => slice_a_pdbus_out(i),
DOPB => slice_b_pdbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S36_S36;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 1024 x 18 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S18_S18 : if (BRAM_PRIMITIVE = B16_S18_S18) generate
component RAMB16_S18_S18
port (DIA : in STD_LOGIC_VECTOR (15 downto 0);
DIB : in STD_LOGIC_VECTOR (15 downto 0);
DIPA : in STD_LOGIC_VECTOR (1 downto 0);
DIPB : in STD_LOGIC_VECTOR (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in STD_LOGIC_VECTOR (9 downto 0);
ADDRB : in STD_LOGIC_VECTOR (9 downto 0);
DOA : out STD_LOGIC_VECTOR (15 downto 0);
DOB : out STD_LOGIC_VECTOR (15 downto 0);
DOPA : out STD_LOGIC_VECTOR (1 downto 0);
DOPB : out STD_LOGIC_VECTOR (1 downto 0)
);
end component;
Constant PRIM_ADDR_WIDTH : integer := 10; -- 1024 deep
Constant PRIM_PDBUS_WIDTH : integer := 2; -- 2 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 16; -- 16 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
type pdbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_1024x18 : RAMB16_S18_S18
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
DIPA => slice_a_pdbus_in(i),
DIPB => slice_b_pdbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i),
DOPA => slice_a_pdbus_out(i),
DOPB => slice_b_pdbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S18_S18;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 2048 x 9 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S9_S9 : if (BRAM_PRIMITIVE = B16_S9_S9) generate
component RAMB16_S9_S9
port (
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
DIPA : in std_logic_vector (0 downto 0);
DIPB : in std_logic_vector (0 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0);
DOPA : out std_logic_vector (0 downto 0);
DOPB : out std_logic_vector (0 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 11; -- 2048 deep
Constant PRIM_PDBUS_WIDTH : integer := 1; -- 1 parity data bit
Constant PRIM_DBUS_WIDTH : integer := 8; -- 8 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
type pdbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_2048x9 : RAMB16_S9_S9
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
DIPA => slice_a_pdbus_in(i),
DIPB => slice_b_pdbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i),
DOPA => slice_a_pdbus_out(i),
DOPB => slice_b_pdbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S9_S9;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 4096 x 4 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S4_S4 : if (BRAM_PRIMITIVE = B16_S4_S4) generate
component RAMB16_S4_S4
port (
DIA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (11 downto 0);
ADDRB : in std_logic_vector (11 downto 0);
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (3 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 12; -- 4096 deep
Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 4; -- 4 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--type pdbus_slice_array is array(BRAM_NUM downto 1) of
-- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
--slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
--slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_4096x4 : RAMB16_S4_S4
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S4_S4;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 8192 x 2 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S2_S2 : if (BRAM_PRIMITIVE = B16_S2_S2) generate
component RAMB16_S2_S2
port (
DIA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (12 downto 0);
ADDRB : in std_logic_vector (12 downto 0);
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 13; -- 8192 deep
Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 2; -- 2 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--type pdbus_slice_array is array(BRAM_NUM downto 1) of
-- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
--slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
--slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_8192x2 : RAMB16_S2_S2
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S2_S2;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 16384 x 1 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S1_S1 : if (BRAM_PRIMITIVE = B16_S1_S1) generate
component RAMB16_S1_S1
port (
DIA : in std_logic_vector (0 downto 0);
DIB : in std_logic_vector (0 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (13 downto 0);
ADDRB : in std_logic_vector (13 downto 0);
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (0 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 14; -- 16384 deep
Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 1; -- 1 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--type pdbus_slice_array is array(BRAM_NUM downto 1) of
-- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
--slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
--slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_16384x1 : RAMB16_S1_S1
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S1_S1;
--==========================================================================
-- End of Virtex-II and Virtex-II Pro support
--///////////////////////////////////////////////////////////////////////////
--///////////////////////////////////////////////////////////////////////////
-- Start Spartan-II, Spartan-IIE, Virtex, and VirtexE support
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 4096 x 1 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S1_S1 : if (BRAM_PRIMITIVE = B4_S1_S1) generate
component RAMB4_S1_S1
port (
DIA : in std_logic_vector (0 downto 0);
DIB : in std_logic_vector (0 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (11 downto 0);
ADDRB : in std_logic_vector (11 downto 0);
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (0 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 12; -- 4096 deep
Constant PRIM_DBUS_WIDTH : integer := 1; -- 1 data bit
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_4096x1 : RAMB4_S1_S1
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S1_S1;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 2048 x 2 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S2_S2 : if (BRAM_PRIMITIVE = B4_S2_S2) generate
component RAMB4_S2_S2
port (
DIA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 11; -- 2048 deep
Constant PRIM_DBUS_WIDTH : integer := 2; -- 2 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_2048x2 : RAMB4_S2_S2
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S2_S2;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 1024 x 4 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S4_S4 : if (BRAM_PRIMITIVE = B4_S4_S4) generate
component RAMB4_S4_S4
port (
DIA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (9 downto 0);
ADDRB : in std_logic_vector (9 downto 0);
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (3 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 10; -- 1024 deep
Constant PRIM_DBUS_WIDTH : integer := 4; -- 4 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_1024x4 : RAMB4_S4_S4
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S4_S4;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 512 x 8 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S8_S8 : if (BRAM_PRIMITIVE = B4_S8_S8) generate
component RAMB4_S8_S8
port (
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (8 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 9; -- 512 deep
Constant PRIM_DBUS_WIDTH : integer := 8; -- 8 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_512x8 : RAMB4_S8_S8
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S8_S8;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 256 x 16 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S16_S16 : if (BRAM_PRIMITIVE = B4_S16_S16) generate
component RAMB4_S16_S16
port (DIA : in STD_LOGIC_VECTOR (15 downto 0);
DIB : in STD_LOGIC_VECTOR (15 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in STD_LOGIC_VECTOR (7 downto 0);
ADDRB : in STD_LOGIC_VECTOR (7 downto 0);
DOA : out STD_LOGIC_VECTOR (15 downto 0);
DOB : out STD_LOGIC_VECTOR (15 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 8; -- 256 deep
Constant PRIM_DBUS_WIDTH : integer := 16; -- 16 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_256x16 : RAMB4_S16_S16
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S16_S16;
--==========================================================================
UNSUPPORTED_FAMILY : if (BRAM_PRIMITIVE = indeterminate) generate
begin
-- assert (false)
-- report "Unsupported Part Family Selected or FIFO Depth/Width is invalid!"
-- severity failure;
--
end generate UNSUPPORTED_FAMILY;
end architecture implementation;
|
-------------------------------------------------------------------------------
-- $Id: pf_dpram_select.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_dpram_select.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
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-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_dpram_select.vhd
--
-- Description: This vhdl design file uses three input parameters describing
-- the desired storage depth, data width, and FPGA family type.
-- From these, the design selects the optimum Block RAM
-- primitive for the basic storage element and connects them
-- in parallel to accomodate the desired data width.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_dpram_select.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- DET Oct. 7, 2001 First Version
-- - Adopted design concepts from Goran Bilski's
-- opb_bram.vhd design in the formulation of this
-- design for the Mauna Loa packet FIFO dual port
-- core function.
--
-- DET Oct-31-2001
-- - Changed the generic input parameter C_FAMILY of type string
-- back to the boolean type parameter C_VIRTEX_II. XST support
-- change.
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library unisim;
use unisim.all; -- uses BRAM primitives
-------------------------------------------------------------------------------
entity pf_dpram_select is
generic (
C_DP_DATA_WIDTH : Integer := 32;
C_DP_ADDRESS_WIDTH : Integer := 9;
C_VIRTEX_II : Boolean := true
);
port (
-- Write Port signals
Wr_rst : In std_logic;
Wr_Clk : in std_logic;
Wr_Enable : In std_logic;
Wr_Req : In std_logic;
Wr_Address : in std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1);
Wr_Data : In std_logic_vector(0 to C_DP_DATA_WIDTH-1);
-- Read Port Signals
Rd_rst : In std_logic;
Rd_Clk : in std_logic;
Rd_Enable : In std_logic;
Rd_Address : in std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1);
Rd_Data : out std_logic_vector(0 to C_DP_DATA_WIDTH-1)
);
end entity pf_dpram_select;
architecture implementation of pf_dpram_select is
Type family_type is (
any ,
x4k ,
x4ke ,
x4kl ,
x4kex ,
x4kxl ,
x4kxv ,
x4kxla ,
spartan ,
spartanxl,
spartan2 ,
spartan2e,
virtex ,
virtexe ,
virtex2 ,
virtex2p ,
unsupported
);
Type bram_prim_type is (
use_srl ,
B4_S1_S1 ,
B4_S2_S2 ,
B4_S4_S4 ,
B4_S8_S8 ,
B4_S16_S16 ,
B16_S1_S1 ,
B16_S2_S2 ,
B16_S4_S4 ,
B16_S9_S9 ,
B16_S18_S18 ,
B16_S36_S36 ,
indeterminate
);
-----------------------------------------------------------------------------
-- This function converts the input C_VIRTEX_II boolean type to an enumerated
-- type. Only Virtex and Virtex II types are currently supported. This
-- used to convert a string to a family type function but string support in
-- the synthesis tools was found to be mutually exclusive between Synplicity
-- and XST.
-----------------------------------------------------------------------------
function get_prim_family (vertex2_select : boolean) return family_type is
Variable prim_family : family_type;
begin
If (vertex2_select) Then
prim_family := virtex2;
else
prim_family := virtex;
End if;
Return (prim_family);
end function get_prim_family;
-----------------------------------------------------------------------------
-- This function chooses the optimum BRAM primitive to utilize as
-- specified by the inputs for data depth, data width, and FPGA part family.
-----------------------------------------------------------------------------
function get_bram_primitive (target_depth: integer;
target_width: integer;
family : family_type )
return bram_prim_type is
Variable primitive : bram_prim_type;
begin
Case family Is
When virtex2p | virtex2 =>
Case target_depth Is
When 1 | 2 =>
primitive := indeterminate; -- depth is too small for BRAM
-- based fifo control logic
When 4 | 8 | 16 =>
-- primitive := use_srl; -- activate when SRL FIFO incorporated
Case target_width Is -- use BRAM for now
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When 5 | 6 | 7 | 8 | 9 =>
primitive := B16_S9_S9;
When 10 | 11 | 12 | 13 | 14 |
15 | 16 | 17 | 18 =>
primitive := B16_S18_S18;
When others =>
primitive := B16_S36_S36;
End case;
when 32 | 64 | 128 | 256 | 512 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When 5 | 6 | 7 | 8 | 9 =>
primitive := B16_S9_S9;
When 10 | 11 | 12 | 13 | 14 |
15 | 16 | 17 | 18 =>
primitive := B16_S18_S18;
When others =>
primitive := B16_S36_S36;
End case;
When 1024 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When 5 | 6 | 7 | 8 | 9 =>
primitive := B16_S9_S9;
When others =>
primitive := B16_S18_S18;
End case;
When 2048 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When others =>
primitive := B16_S9_S9;
End case;
When 4096 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When others =>
primitive := B16_S4_S4;
End case;
When 8192 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When others =>
primitive := B16_S2_S2;
End case;
When 16384 =>
primitive := B16_S1_S1;
When others =>
primitive := indeterminate;
End case;
When spartan2 | spartan2e | virtex | virtexe =>
Case target_depth Is
When 1 | 2 =>
primitive := indeterminate; -- depth is too small for BRAM
-- based fifo control logic
When 4 | 8 | 16 =>
-- primitive := use_srl; -- activate this when SRL FIFO is
-- incorporated
Case target_width Is -- use BRAM for now
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When 3 | 4 =>
primitive := B4_S4_S4;
When 5 | 6 | 7 | 8 =>
primitive := B4_S8_S8;
When others =>
primitive := B4_S16_S16;
End case;
when 32 | 64 | 128 | 256 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When 3 | 4 =>
primitive := B4_S4_S4;
When 5 | 6 | 7 | 8 =>
primitive := B4_S8_S8;
When others =>
primitive := B4_S16_S16;
End case;
when 512 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When 3 | 4 =>
primitive := B4_S4_S4;
When others =>
primitive := B4_S8_S8;
End case;
When 1024 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When others =>
primitive := B4_S4_S4;
End case;
When 2048 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When others =>
primitive := B4_S2_S2;
End case;
When 4096 =>
primitive := B4_S1_S1;
When others =>
primitive := indeterminate;
End case;
When others =>
primitive := indeterminate;
End case;
Return primitive;
end function get_bram_primitive;
-----------------------------------------------------------------------------
-- This function calculates the number of BRAM primitives required as
-- specified by the inputs for data width and BRAM primitive type.
-----------------------------------------------------------------------------
function get_num_prims (bram_prim : bram_prim_type;
mem_width : integer)
return integer is
Variable bram_num : integer;
begin
Case bram_prim Is
When B16_S1_S1 | B4_S1_S1 =>
bram_num := mem_width;
When B16_S2_S2 | B4_S2_S2 =>
bram_num := (mem_width+1)/2;
When B16_S4_S4 | B4_S4_S4 =>
bram_num := (mem_width+3)/4;
When B4_S8_S8 =>
bram_num := (mem_width+7)/8;
When B16_S9_S9 =>
bram_num := (mem_width+8)/9;
When B4_S16_S16 =>
bram_num := (mem_width+15)/16;
When B16_S18_S18 =>
bram_num := (mem_width+17)/18;
When B16_S36_S36 =>
bram_num := (mem_width+35)/36;
When others =>
bram_num := 1;
End case;
Return (bram_num);
end function get_num_prims;
-- Now set the global CONSTANTS needed for IF-Generates
-- Determine the number of BRAM storage locations needed
constant FIFO_DEPTH : Integer := 2**C_DP_ADDRESS_WIDTH;
-- Convert the input C_VIRTEX_II generic boolean to enumerated type
Constant BRAM_FAMILY : family_type :=
get_prim_family(C_VIRTEX_II);
-- Select the optimum BRAM primitive to use
constant BRAM_PRIMITIVE : bram_prim_type :=
get_bram_primitive(FIFO_DEPTH,
C_DP_DATA_WIDTH,
BRAM_FAMILY);
-- Calculate how many of the selected primitives are needed
-- to populate the desired data width
constant BRAM_NUM : integer :=
get_num_prims(BRAM_PRIMITIVE,
C_DP_DATA_WIDTH);
begin -- architecture
----------------------------------------------------------------------------
-- Using VII 512 x 36 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S36_S36 : if (BRAM_PRIMITIVE = B16_S36_S36) generate
component RAMB16_S36_S36
port (DIA : in STD_LOGIC_VECTOR (31 downto 0);
DIB : in STD_LOGIC_VECTOR (31 downto 0);
DIPA : in STD_LOGIC_VECTOR (3 downto 0);
DIPB : in STD_LOGIC_VECTOR (3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in STD_LOGIC_VECTOR (8 downto 0);
ADDRB : in STD_LOGIC_VECTOR (8 downto 0);
DOA : out STD_LOGIC_VECTOR (31 downto 0);
DOB : out STD_LOGIC_VECTOR (31 downto 0);
DOPA : out STD_LOGIC_VECTOR (3 downto 0);
DOPB : out STD_LOGIC_VECTOR (3 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 9; -- 512 deep
Constant PRIM_PDBUS_WIDTH : integer := 4; -- 4 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 32; -- 4 parity data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
type pdbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_512x32 : RAMB16_S36_S36
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
DIPA => slice_a_pdbus_in(i),
DIPB => slice_b_pdbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i),
DOPA => slice_a_pdbus_out(i),
DOPB => slice_b_pdbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S36_S36;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 1024 x 18 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S18_S18 : if (BRAM_PRIMITIVE = B16_S18_S18) generate
component RAMB16_S18_S18
port (DIA : in STD_LOGIC_VECTOR (15 downto 0);
DIB : in STD_LOGIC_VECTOR (15 downto 0);
DIPA : in STD_LOGIC_VECTOR (1 downto 0);
DIPB : in STD_LOGIC_VECTOR (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in STD_LOGIC_VECTOR (9 downto 0);
ADDRB : in STD_LOGIC_VECTOR (9 downto 0);
DOA : out STD_LOGIC_VECTOR (15 downto 0);
DOB : out STD_LOGIC_VECTOR (15 downto 0);
DOPA : out STD_LOGIC_VECTOR (1 downto 0);
DOPB : out STD_LOGIC_VECTOR (1 downto 0)
);
end component;
Constant PRIM_ADDR_WIDTH : integer := 10; -- 1024 deep
Constant PRIM_PDBUS_WIDTH : integer := 2; -- 2 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 16; -- 16 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
type pdbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_1024x18 : RAMB16_S18_S18
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
DIPA => slice_a_pdbus_in(i),
DIPB => slice_b_pdbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i),
DOPA => slice_a_pdbus_out(i),
DOPB => slice_b_pdbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S18_S18;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 2048 x 9 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S9_S9 : if (BRAM_PRIMITIVE = B16_S9_S9) generate
component RAMB16_S9_S9
port (
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
DIPA : in std_logic_vector (0 downto 0);
DIPB : in std_logic_vector (0 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0);
DOPA : out std_logic_vector (0 downto 0);
DOPB : out std_logic_vector (0 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 11; -- 2048 deep
Constant PRIM_PDBUS_WIDTH : integer := 1; -- 1 parity data bit
Constant PRIM_DBUS_WIDTH : integer := 8; -- 8 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
type pdbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_2048x9 : RAMB16_S9_S9
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
DIPA => slice_a_pdbus_in(i),
DIPB => slice_b_pdbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i),
DOPA => slice_a_pdbus_out(i),
DOPB => slice_b_pdbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S9_S9;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 4096 x 4 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S4_S4 : if (BRAM_PRIMITIVE = B16_S4_S4) generate
component RAMB16_S4_S4
port (
DIA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (11 downto 0);
ADDRB : in std_logic_vector (11 downto 0);
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (3 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 12; -- 4096 deep
Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 4; -- 4 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--type pdbus_slice_array is array(BRAM_NUM downto 1) of
-- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
--slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
--slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_4096x4 : RAMB16_S4_S4
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S4_S4;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 8192 x 2 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S2_S2 : if (BRAM_PRIMITIVE = B16_S2_S2) generate
component RAMB16_S2_S2
port (
DIA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (12 downto 0);
ADDRB : in std_logic_vector (12 downto 0);
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 13; -- 8192 deep
Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 2; -- 2 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--type pdbus_slice_array is array(BRAM_NUM downto 1) of
-- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
--slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
--slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_8192x2 : RAMB16_S2_S2
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S2_S2;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 16384 x 1 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S1_S1 : if (BRAM_PRIMITIVE = B16_S1_S1) generate
component RAMB16_S1_S1
port (
DIA : in std_logic_vector (0 downto 0);
DIB : in std_logic_vector (0 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (13 downto 0);
ADDRB : in std_logic_vector (13 downto 0);
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (0 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 14; -- 16384 deep
Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 1; -- 1 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--type pdbus_slice_array is array(BRAM_NUM downto 1) of
-- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
--slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
--slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_16384x1 : RAMB16_S1_S1
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S1_S1;
--==========================================================================
-- End of Virtex-II and Virtex-II Pro support
--///////////////////////////////////////////////////////////////////////////
--///////////////////////////////////////////////////////////////////////////
-- Start Spartan-II, Spartan-IIE, Virtex, and VirtexE support
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 4096 x 1 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S1_S1 : if (BRAM_PRIMITIVE = B4_S1_S1) generate
component RAMB4_S1_S1
port (
DIA : in std_logic_vector (0 downto 0);
DIB : in std_logic_vector (0 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (11 downto 0);
ADDRB : in std_logic_vector (11 downto 0);
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (0 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 12; -- 4096 deep
Constant PRIM_DBUS_WIDTH : integer := 1; -- 1 data bit
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_4096x1 : RAMB4_S1_S1
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S1_S1;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 2048 x 2 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S2_S2 : if (BRAM_PRIMITIVE = B4_S2_S2) generate
component RAMB4_S2_S2
port (
DIA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 11; -- 2048 deep
Constant PRIM_DBUS_WIDTH : integer := 2; -- 2 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_2048x2 : RAMB4_S2_S2
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S2_S2;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 1024 x 4 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S4_S4 : if (BRAM_PRIMITIVE = B4_S4_S4) generate
component RAMB4_S4_S4
port (
DIA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (9 downto 0);
ADDRB : in std_logic_vector (9 downto 0);
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (3 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 10; -- 1024 deep
Constant PRIM_DBUS_WIDTH : integer := 4; -- 4 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_1024x4 : RAMB4_S4_S4
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S4_S4;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 512 x 8 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S8_S8 : if (BRAM_PRIMITIVE = B4_S8_S8) generate
component RAMB4_S8_S8
port (
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (8 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 9; -- 512 deep
Constant PRIM_DBUS_WIDTH : integer := 8; -- 8 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_512x8 : RAMB4_S8_S8
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S8_S8;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 256 x 16 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S16_S16 : if (BRAM_PRIMITIVE = B4_S16_S16) generate
component RAMB4_S16_S16
port (DIA : in STD_LOGIC_VECTOR (15 downto 0);
DIB : in STD_LOGIC_VECTOR (15 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in STD_LOGIC_VECTOR (7 downto 0);
ADDRB : in STD_LOGIC_VECTOR (7 downto 0);
DOA : out STD_LOGIC_VECTOR (15 downto 0);
DOB : out STD_LOGIC_VECTOR (15 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 8; -- 256 deep
Constant PRIM_DBUS_WIDTH : integer := 16; -- 16 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_256x16 : RAMB4_S16_S16
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S16_S16;
--==========================================================================
UNSUPPORTED_FAMILY : if (BRAM_PRIMITIVE = indeterminate) generate
begin
-- assert (false)
-- report "Unsupported Part Family Selected or FIFO Depth/Width is invalid!"
-- severity failure;
--
end generate UNSUPPORTED_FAMILY;
end architecture implementation;
|
-------------------------------------------------------------------------------
-- $Id: pf_dpram_select.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_dpram_select.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_dpram_select.vhd
--
-- Description: This vhdl design file uses three input parameters describing
-- the desired storage depth, data width, and FPGA family type.
-- From these, the design selects the optimum Block RAM
-- primitive for the basic storage element and connects them
-- in parallel to accomodate the desired data width.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_dpram_select.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- DET Oct. 7, 2001 First Version
-- - Adopted design concepts from Goran Bilski's
-- opb_bram.vhd design in the formulation of this
-- design for the Mauna Loa packet FIFO dual port
-- core function.
--
-- DET Oct-31-2001
-- - Changed the generic input parameter C_FAMILY of type string
-- back to the boolean type parameter C_VIRTEX_II. XST support
-- change.
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library unisim;
use unisim.all; -- uses BRAM primitives
-------------------------------------------------------------------------------
entity pf_dpram_select is
generic (
C_DP_DATA_WIDTH : Integer := 32;
C_DP_ADDRESS_WIDTH : Integer := 9;
C_VIRTEX_II : Boolean := true
);
port (
-- Write Port signals
Wr_rst : In std_logic;
Wr_Clk : in std_logic;
Wr_Enable : In std_logic;
Wr_Req : In std_logic;
Wr_Address : in std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1);
Wr_Data : In std_logic_vector(0 to C_DP_DATA_WIDTH-1);
-- Read Port Signals
Rd_rst : In std_logic;
Rd_Clk : in std_logic;
Rd_Enable : In std_logic;
Rd_Address : in std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1);
Rd_Data : out std_logic_vector(0 to C_DP_DATA_WIDTH-1)
);
end entity pf_dpram_select;
architecture implementation of pf_dpram_select is
Type family_type is (
any ,
x4k ,
x4ke ,
x4kl ,
x4kex ,
x4kxl ,
x4kxv ,
x4kxla ,
spartan ,
spartanxl,
spartan2 ,
spartan2e,
virtex ,
virtexe ,
virtex2 ,
virtex2p ,
unsupported
);
Type bram_prim_type is (
use_srl ,
B4_S1_S1 ,
B4_S2_S2 ,
B4_S4_S4 ,
B4_S8_S8 ,
B4_S16_S16 ,
B16_S1_S1 ,
B16_S2_S2 ,
B16_S4_S4 ,
B16_S9_S9 ,
B16_S18_S18 ,
B16_S36_S36 ,
indeterminate
);
-----------------------------------------------------------------------------
-- This function converts the input C_VIRTEX_II boolean type to an enumerated
-- type. Only Virtex and Virtex II types are currently supported. This
-- used to convert a string to a family type function but string support in
-- the synthesis tools was found to be mutually exclusive between Synplicity
-- and XST.
-----------------------------------------------------------------------------
function get_prim_family (vertex2_select : boolean) return family_type is
Variable prim_family : family_type;
begin
If (vertex2_select) Then
prim_family := virtex2;
else
prim_family := virtex;
End if;
Return (prim_family);
end function get_prim_family;
-----------------------------------------------------------------------------
-- This function chooses the optimum BRAM primitive to utilize as
-- specified by the inputs for data depth, data width, and FPGA part family.
-----------------------------------------------------------------------------
function get_bram_primitive (target_depth: integer;
target_width: integer;
family : family_type )
return bram_prim_type is
Variable primitive : bram_prim_type;
begin
Case family Is
When virtex2p | virtex2 =>
Case target_depth Is
When 1 | 2 =>
primitive := indeterminate; -- depth is too small for BRAM
-- based fifo control logic
When 4 | 8 | 16 =>
-- primitive := use_srl; -- activate when SRL FIFO incorporated
Case target_width Is -- use BRAM for now
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When 5 | 6 | 7 | 8 | 9 =>
primitive := B16_S9_S9;
When 10 | 11 | 12 | 13 | 14 |
15 | 16 | 17 | 18 =>
primitive := B16_S18_S18;
When others =>
primitive := B16_S36_S36;
End case;
when 32 | 64 | 128 | 256 | 512 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When 5 | 6 | 7 | 8 | 9 =>
primitive := B16_S9_S9;
When 10 | 11 | 12 | 13 | 14 |
15 | 16 | 17 | 18 =>
primitive := B16_S18_S18;
When others =>
primitive := B16_S36_S36;
End case;
When 1024 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When 5 | 6 | 7 | 8 | 9 =>
primitive := B16_S9_S9;
When others =>
primitive := B16_S18_S18;
End case;
When 2048 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When others =>
primitive := B16_S9_S9;
End case;
When 4096 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When others =>
primitive := B16_S4_S4;
End case;
When 8192 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When others =>
primitive := B16_S2_S2;
End case;
When 16384 =>
primitive := B16_S1_S1;
When others =>
primitive := indeterminate;
End case;
When spartan2 | spartan2e | virtex | virtexe =>
Case target_depth Is
When 1 | 2 =>
primitive := indeterminate; -- depth is too small for BRAM
-- based fifo control logic
When 4 | 8 | 16 =>
-- primitive := use_srl; -- activate this when SRL FIFO is
-- incorporated
Case target_width Is -- use BRAM for now
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When 3 | 4 =>
primitive := B4_S4_S4;
When 5 | 6 | 7 | 8 =>
primitive := B4_S8_S8;
When others =>
primitive := B4_S16_S16;
End case;
when 32 | 64 | 128 | 256 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When 3 | 4 =>
primitive := B4_S4_S4;
When 5 | 6 | 7 | 8 =>
primitive := B4_S8_S8;
When others =>
primitive := B4_S16_S16;
End case;
when 512 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When 3 | 4 =>
primitive := B4_S4_S4;
When others =>
primitive := B4_S8_S8;
End case;
When 1024 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When others =>
primitive := B4_S4_S4;
End case;
When 2048 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When others =>
primitive := B4_S2_S2;
End case;
When 4096 =>
primitive := B4_S1_S1;
When others =>
primitive := indeterminate;
End case;
When others =>
primitive := indeterminate;
End case;
Return primitive;
end function get_bram_primitive;
-----------------------------------------------------------------------------
-- This function calculates the number of BRAM primitives required as
-- specified by the inputs for data width and BRAM primitive type.
-----------------------------------------------------------------------------
function get_num_prims (bram_prim : bram_prim_type;
mem_width : integer)
return integer is
Variable bram_num : integer;
begin
Case bram_prim Is
When B16_S1_S1 | B4_S1_S1 =>
bram_num := mem_width;
When B16_S2_S2 | B4_S2_S2 =>
bram_num := (mem_width+1)/2;
When B16_S4_S4 | B4_S4_S4 =>
bram_num := (mem_width+3)/4;
When B4_S8_S8 =>
bram_num := (mem_width+7)/8;
When B16_S9_S9 =>
bram_num := (mem_width+8)/9;
When B4_S16_S16 =>
bram_num := (mem_width+15)/16;
When B16_S18_S18 =>
bram_num := (mem_width+17)/18;
When B16_S36_S36 =>
bram_num := (mem_width+35)/36;
When others =>
bram_num := 1;
End case;
Return (bram_num);
end function get_num_prims;
-- Now set the global CONSTANTS needed for IF-Generates
-- Determine the number of BRAM storage locations needed
constant FIFO_DEPTH : Integer := 2**C_DP_ADDRESS_WIDTH;
-- Convert the input C_VIRTEX_II generic boolean to enumerated type
Constant BRAM_FAMILY : family_type :=
get_prim_family(C_VIRTEX_II);
-- Select the optimum BRAM primitive to use
constant BRAM_PRIMITIVE : bram_prim_type :=
get_bram_primitive(FIFO_DEPTH,
C_DP_DATA_WIDTH,
BRAM_FAMILY);
-- Calculate how many of the selected primitives are needed
-- to populate the desired data width
constant BRAM_NUM : integer :=
get_num_prims(BRAM_PRIMITIVE,
C_DP_DATA_WIDTH);
begin -- architecture
----------------------------------------------------------------------------
-- Using VII 512 x 36 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S36_S36 : if (BRAM_PRIMITIVE = B16_S36_S36) generate
component RAMB16_S36_S36
port (DIA : in STD_LOGIC_VECTOR (31 downto 0);
DIB : in STD_LOGIC_VECTOR (31 downto 0);
DIPA : in STD_LOGIC_VECTOR (3 downto 0);
DIPB : in STD_LOGIC_VECTOR (3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in STD_LOGIC_VECTOR (8 downto 0);
ADDRB : in STD_LOGIC_VECTOR (8 downto 0);
DOA : out STD_LOGIC_VECTOR (31 downto 0);
DOB : out STD_LOGIC_VECTOR (31 downto 0);
DOPA : out STD_LOGIC_VECTOR (3 downto 0);
DOPB : out STD_LOGIC_VECTOR (3 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 9; -- 512 deep
Constant PRIM_PDBUS_WIDTH : integer := 4; -- 4 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 32; -- 4 parity data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
type pdbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_512x32 : RAMB16_S36_S36
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
DIPA => slice_a_pdbus_in(i),
DIPB => slice_b_pdbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i),
DOPA => slice_a_pdbus_out(i),
DOPB => slice_b_pdbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S36_S36;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 1024 x 18 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S18_S18 : if (BRAM_PRIMITIVE = B16_S18_S18) generate
component RAMB16_S18_S18
port (DIA : in STD_LOGIC_VECTOR (15 downto 0);
DIB : in STD_LOGIC_VECTOR (15 downto 0);
DIPA : in STD_LOGIC_VECTOR (1 downto 0);
DIPB : in STD_LOGIC_VECTOR (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in STD_LOGIC_VECTOR (9 downto 0);
ADDRB : in STD_LOGIC_VECTOR (9 downto 0);
DOA : out STD_LOGIC_VECTOR (15 downto 0);
DOB : out STD_LOGIC_VECTOR (15 downto 0);
DOPA : out STD_LOGIC_VECTOR (1 downto 0);
DOPB : out STD_LOGIC_VECTOR (1 downto 0)
);
end component;
Constant PRIM_ADDR_WIDTH : integer := 10; -- 1024 deep
Constant PRIM_PDBUS_WIDTH : integer := 2; -- 2 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 16; -- 16 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
type pdbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_1024x18 : RAMB16_S18_S18
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
DIPA => slice_a_pdbus_in(i),
DIPB => slice_b_pdbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i),
DOPA => slice_a_pdbus_out(i),
DOPB => slice_b_pdbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S18_S18;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 2048 x 9 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S9_S9 : if (BRAM_PRIMITIVE = B16_S9_S9) generate
component RAMB16_S9_S9
port (
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
DIPA : in std_logic_vector (0 downto 0);
DIPB : in std_logic_vector (0 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0);
DOPA : out std_logic_vector (0 downto 0);
DOPB : out std_logic_vector (0 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 11; -- 2048 deep
Constant PRIM_PDBUS_WIDTH : integer := 1; -- 1 parity data bit
Constant PRIM_DBUS_WIDTH : integer := 8; -- 8 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
type pdbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_2048x9 : RAMB16_S9_S9
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
DIPA => slice_a_pdbus_in(i),
DIPB => slice_b_pdbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i),
DOPA => slice_a_pdbus_out(i),
DOPB => slice_b_pdbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S9_S9;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 4096 x 4 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S4_S4 : if (BRAM_PRIMITIVE = B16_S4_S4) generate
component RAMB16_S4_S4
port (
DIA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (11 downto 0);
ADDRB : in std_logic_vector (11 downto 0);
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (3 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 12; -- 4096 deep
Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 4; -- 4 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--type pdbus_slice_array is array(BRAM_NUM downto 1) of
-- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
--slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
--slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_4096x4 : RAMB16_S4_S4
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S4_S4;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 8192 x 2 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S2_S2 : if (BRAM_PRIMITIVE = B16_S2_S2) generate
component RAMB16_S2_S2
port (
DIA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (12 downto 0);
ADDRB : in std_logic_vector (12 downto 0);
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 13; -- 8192 deep
Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 2; -- 2 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--type pdbus_slice_array is array(BRAM_NUM downto 1) of
-- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
--slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
--slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_8192x2 : RAMB16_S2_S2
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S2_S2;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 16384 x 1 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S1_S1 : if (BRAM_PRIMITIVE = B16_S1_S1) generate
component RAMB16_S1_S1
port (
DIA : in std_logic_vector (0 downto 0);
DIB : in std_logic_vector (0 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (13 downto 0);
ADDRB : in std_logic_vector (13 downto 0);
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (0 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 14; -- 16384 deep
Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 1; -- 1 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--type pdbus_slice_array is array(BRAM_NUM downto 1) of
-- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
--slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
--slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_16384x1 : RAMB16_S1_S1
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S1_S1;
--==========================================================================
-- End of Virtex-II and Virtex-II Pro support
--///////////////////////////////////////////////////////////////////////////
--///////////////////////////////////////////////////////////////////////////
-- Start Spartan-II, Spartan-IIE, Virtex, and VirtexE support
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 4096 x 1 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S1_S1 : if (BRAM_PRIMITIVE = B4_S1_S1) generate
component RAMB4_S1_S1
port (
DIA : in std_logic_vector (0 downto 0);
DIB : in std_logic_vector (0 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (11 downto 0);
ADDRB : in std_logic_vector (11 downto 0);
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (0 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 12; -- 4096 deep
Constant PRIM_DBUS_WIDTH : integer := 1; -- 1 data bit
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_4096x1 : RAMB4_S1_S1
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S1_S1;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 2048 x 2 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S2_S2 : if (BRAM_PRIMITIVE = B4_S2_S2) generate
component RAMB4_S2_S2
port (
DIA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 11; -- 2048 deep
Constant PRIM_DBUS_WIDTH : integer := 2; -- 2 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_2048x2 : RAMB4_S2_S2
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S2_S2;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 1024 x 4 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S4_S4 : if (BRAM_PRIMITIVE = B4_S4_S4) generate
component RAMB4_S4_S4
port (
DIA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (9 downto 0);
ADDRB : in std_logic_vector (9 downto 0);
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (3 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 10; -- 1024 deep
Constant PRIM_DBUS_WIDTH : integer := 4; -- 4 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_1024x4 : RAMB4_S4_S4
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S4_S4;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 512 x 8 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S8_S8 : if (BRAM_PRIMITIVE = B4_S8_S8) generate
component RAMB4_S8_S8
port (
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (8 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 9; -- 512 deep
Constant PRIM_DBUS_WIDTH : integer := 8; -- 8 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_512x8 : RAMB4_S8_S8
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S8_S8;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 256 x 16 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S16_S16 : if (BRAM_PRIMITIVE = B4_S16_S16) generate
component RAMB4_S16_S16
port (DIA : in STD_LOGIC_VECTOR (15 downto 0);
DIB : in STD_LOGIC_VECTOR (15 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in STD_LOGIC_VECTOR (7 downto 0);
ADDRB : in STD_LOGIC_VECTOR (7 downto 0);
DOA : out STD_LOGIC_VECTOR (15 downto 0);
DOB : out STD_LOGIC_VECTOR (15 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 8; -- 256 deep
Constant PRIM_DBUS_WIDTH : integer := 16; -- 16 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_256x16 : RAMB4_S16_S16
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S16_S16;
--==========================================================================
UNSUPPORTED_FAMILY : if (BRAM_PRIMITIVE = indeterminate) generate
begin
-- assert (false)
-- report "Unsupported Part Family Selected or FIFO Depth/Width is invalid!"
-- severity failure;
--
end generate UNSUPPORTED_FAMILY;
end architecture implementation;
|
-------------------------------------------------------------------------------
-- $Id: pf_dpram_select.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_dpram_select.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
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-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
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-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
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-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_dpram_select.vhd
--
-- Description: This vhdl design file uses three input parameters describing
-- the desired storage depth, data width, and FPGA family type.
-- From these, the design selects the optimum Block RAM
-- primitive for the basic storage element and connects them
-- in parallel to accomodate the desired data width.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_dpram_select.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- DET Oct. 7, 2001 First Version
-- - Adopted design concepts from Goran Bilski's
-- opb_bram.vhd design in the formulation of this
-- design for the Mauna Loa packet FIFO dual port
-- core function.
--
-- DET Oct-31-2001
-- - Changed the generic input parameter C_FAMILY of type string
-- back to the boolean type parameter C_VIRTEX_II. XST support
-- change.
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library unisim;
use unisim.all; -- uses BRAM primitives
-------------------------------------------------------------------------------
entity pf_dpram_select is
generic (
C_DP_DATA_WIDTH : Integer := 32;
C_DP_ADDRESS_WIDTH : Integer := 9;
C_VIRTEX_II : Boolean := true
);
port (
-- Write Port signals
Wr_rst : In std_logic;
Wr_Clk : in std_logic;
Wr_Enable : In std_logic;
Wr_Req : In std_logic;
Wr_Address : in std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1);
Wr_Data : In std_logic_vector(0 to C_DP_DATA_WIDTH-1);
-- Read Port Signals
Rd_rst : In std_logic;
Rd_Clk : in std_logic;
Rd_Enable : In std_logic;
Rd_Address : in std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1);
Rd_Data : out std_logic_vector(0 to C_DP_DATA_WIDTH-1)
);
end entity pf_dpram_select;
architecture implementation of pf_dpram_select is
Type family_type is (
any ,
x4k ,
x4ke ,
x4kl ,
x4kex ,
x4kxl ,
x4kxv ,
x4kxla ,
spartan ,
spartanxl,
spartan2 ,
spartan2e,
virtex ,
virtexe ,
virtex2 ,
virtex2p ,
unsupported
);
Type bram_prim_type is (
use_srl ,
B4_S1_S1 ,
B4_S2_S2 ,
B4_S4_S4 ,
B4_S8_S8 ,
B4_S16_S16 ,
B16_S1_S1 ,
B16_S2_S2 ,
B16_S4_S4 ,
B16_S9_S9 ,
B16_S18_S18 ,
B16_S36_S36 ,
indeterminate
);
-----------------------------------------------------------------------------
-- This function converts the input C_VIRTEX_II boolean type to an enumerated
-- type. Only Virtex and Virtex II types are currently supported. This
-- used to convert a string to a family type function but string support in
-- the synthesis tools was found to be mutually exclusive between Synplicity
-- and XST.
-----------------------------------------------------------------------------
function get_prim_family (vertex2_select : boolean) return family_type is
Variable prim_family : family_type;
begin
If (vertex2_select) Then
prim_family := virtex2;
else
prim_family := virtex;
End if;
Return (prim_family);
end function get_prim_family;
-----------------------------------------------------------------------------
-- This function chooses the optimum BRAM primitive to utilize as
-- specified by the inputs for data depth, data width, and FPGA part family.
-----------------------------------------------------------------------------
function get_bram_primitive (target_depth: integer;
target_width: integer;
family : family_type )
return bram_prim_type is
Variable primitive : bram_prim_type;
begin
Case family Is
When virtex2p | virtex2 =>
Case target_depth Is
When 1 | 2 =>
primitive := indeterminate; -- depth is too small for BRAM
-- based fifo control logic
When 4 | 8 | 16 =>
-- primitive := use_srl; -- activate when SRL FIFO incorporated
Case target_width Is -- use BRAM for now
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When 5 | 6 | 7 | 8 | 9 =>
primitive := B16_S9_S9;
When 10 | 11 | 12 | 13 | 14 |
15 | 16 | 17 | 18 =>
primitive := B16_S18_S18;
When others =>
primitive := B16_S36_S36;
End case;
when 32 | 64 | 128 | 256 | 512 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When 5 | 6 | 7 | 8 | 9 =>
primitive := B16_S9_S9;
When 10 | 11 | 12 | 13 | 14 |
15 | 16 | 17 | 18 =>
primitive := B16_S18_S18;
When others =>
primitive := B16_S36_S36;
End case;
When 1024 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When 5 | 6 | 7 | 8 | 9 =>
primitive := B16_S9_S9;
When others =>
primitive := B16_S18_S18;
End case;
When 2048 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When others =>
primitive := B16_S9_S9;
End case;
When 4096 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When others =>
primitive := B16_S4_S4;
End case;
When 8192 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When others =>
primitive := B16_S2_S2;
End case;
When 16384 =>
primitive := B16_S1_S1;
When others =>
primitive := indeterminate;
End case;
When spartan2 | spartan2e | virtex | virtexe =>
Case target_depth Is
When 1 | 2 =>
primitive := indeterminate; -- depth is too small for BRAM
-- based fifo control logic
When 4 | 8 | 16 =>
-- primitive := use_srl; -- activate this when SRL FIFO is
-- incorporated
Case target_width Is -- use BRAM for now
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When 3 | 4 =>
primitive := B4_S4_S4;
When 5 | 6 | 7 | 8 =>
primitive := B4_S8_S8;
When others =>
primitive := B4_S16_S16;
End case;
when 32 | 64 | 128 | 256 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When 3 | 4 =>
primitive := B4_S4_S4;
When 5 | 6 | 7 | 8 =>
primitive := B4_S8_S8;
When others =>
primitive := B4_S16_S16;
End case;
when 512 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When 3 | 4 =>
primitive := B4_S4_S4;
When others =>
primitive := B4_S8_S8;
End case;
When 1024 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When others =>
primitive := B4_S4_S4;
End case;
When 2048 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When others =>
primitive := B4_S2_S2;
End case;
When 4096 =>
primitive := B4_S1_S1;
When others =>
primitive := indeterminate;
End case;
When others =>
primitive := indeterminate;
End case;
Return primitive;
end function get_bram_primitive;
-----------------------------------------------------------------------------
-- This function calculates the number of BRAM primitives required as
-- specified by the inputs for data width and BRAM primitive type.
-----------------------------------------------------------------------------
function get_num_prims (bram_prim : bram_prim_type;
mem_width : integer)
return integer is
Variable bram_num : integer;
begin
Case bram_prim Is
When B16_S1_S1 | B4_S1_S1 =>
bram_num := mem_width;
When B16_S2_S2 | B4_S2_S2 =>
bram_num := (mem_width+1)/2;
When B16_S4_S4 | B4_S4_S4 =>
bram_num := (mem_width+3)/4;
When B4_S8_S8 =>
bram_num := (mem_width+7)/8;
When B16_S9_S9 =>
bram_num := (mem_width+8)/9;
When B4_S16_S16 =>
bram_num := (mem_width+15)/16;
When B16_S18_S18 =>
bram_num := (mem_width+17)/18;
When B16_S36_S36 =>
bram_num := (mem_width+35)/36;
When others =>
bram_num := 1;
End case;
Return (bram_num);
end function get_num_prims;
-- Now set the global CONSTANTS needed for IF-Generates
-- Determine the number of BRAM storage locations needed
constant FIFO_DEPTH : Integer := 2**C_DP_ADDRESS_WIDTH;
-- Convert the input C_VIRTEX_II generic boolean to enumerated type
Constant BRAM_FAMILY : family_type :=
get_prim_family(C_VIRTEX_II);
-- Select the optimum BRAM primitive to use
constant BRAM_PRIMITIVE : bram_prim_type :=
get_bram_primitive(FIFO_DEPTH,
C_DP_DATA_WIDTH,
BRAM_FAMILY);
-- Calculate how many of the selected primitives are needed
-- to populate the desired data width
constant BRAM_NUM : integer :=
get_num_prims(BRAM_PRIMITIVE,
C_DP_DATA_WIDTH);
begin -- architecture
----------------------------------------------------------------------------
-- Using VII 512 x 36 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S36_S36 : if (BRAM_PRIMITIVE = B16_S36_S36) generate
component RAMB16_S36_S36
port (DIA : in STD_LOGIC_VECTOR (31 downto 0);
DIB : in STD_LOGIC_VECTOR (31 downto 0);
DIPA : in STD_LOGIC_VECTOR (3 downto 0);
DIPB : in STD_LOGIC_VECTOR (3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in STD_LOGIC_VECTOR (8 downto 0);
ADDRB : in STD_LOGIC_VECTOR (8 downto 0);
DOA : out STD_LOGIC_VECTOR (31 downto 0);
DOB : out STD_LOGIC_VECTOR (31 downto 0);
DOPA : out STD_LOGIC_VECTOR (3 downto 0);
DOPB : out STD_LOGIC_VECTOR (3 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 9; -- 512 deep
Constant PRIM_PDBUS_WIDTH : integer := 4; -- 4 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 32; -- 4 parity data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
type pdbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_512x32 : RAMB16_S36_S36
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
DIPA => slice_a_pdbus_in(i),
DIPB => slice_b_pdbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i),
DOPA => slice_a_pdbus_out(i),
DOPB => slice_b_pdbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S36_S36;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 1024 x 18 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S18_S18 : if (BRAM_PRIMITIVE = B16_S18_S18) generate
component RAMB16_S18_S18
port (DIA : in STD_LOGIC_VECTOR (15 downto 0);
DIB : in STD_LOGIC_VECTOR (15 downto 0);
DIPA : in STD_LOGIC_VECTOR (1 downto 0);
DIPB : in STD_LOGIC_VECTOR (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in STD_LOGIC_VECTOR (9 downto 0);
ADDRB : in STD_LOGIC_VECTOR (9 downto 0);
DOA : out STD_LOGIC_VECTOR (15 downto 0);
DOB : out STD_LOGIC_VECTOR (15 downto 0);
DOPA : out STD_LOGIC_VECTOR (1 downto 0);
DOPB : out STD_LOGIC_VECTOR (1 downto 0)
);
end component;
Constant PRIM_ADDR_WIDTH : integer := 10; -- 1024 deep
Constant PRIM_PDBUS_WIDTH : integer := 2; -- 2 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 16; -- 16 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
type pdbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_1024x18 : RAMB16_S18_S18
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
DIPA => slice_a_pdbus_in(i),
DIPB => slice_b_pdbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i),
DOPA => slice_a_pdbus_out(i),
DOPB => slice_b_pdbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S18_S18;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 2048 x 9 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S9_S9 : if (BRAM_PRIMITIVE = B16_S9_S9) generate
component RAMB16_S9_S9
port (
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
DIPA : in std_logic_vector (0 downto 0);
DIPB : in std_logic_vector (0 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0);
DOPA : out std_logic_vector (0 downto 0);
DOPB : out std_logic_vector (0 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 11; -- 2048 deep
Constant PRIM_PDBUS_WIDTH : integer := 1; -- 1 parity data bit
Constant PRIM_DBUS_WIDTH : integer := 8; -- 8 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
type pdbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_2048x9 : RAMB16_S9_S9
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
DIPA => slice_a_pdbus_in(i),
DIPB => slice_b_pdbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i),
DOPA => slice_a_pdbus_out(i),
DOPB => slice_b_pdbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S9_S9;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 4096 x 4 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S4_S4 : if (BRAM_PRIMITIVE = B16_S4_S4) generate
component RAMB16_S4_S4
port (
DIA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (11 downto 0);
ADDRB : in std_logic_vector (11 downto 0);
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (3 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 12; -- 4096 deep
Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 4; -- 4 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--type pdbus_slice_array is array(BRAM_NUM downto 1) of
-- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
--slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
--slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_4096x4 : RAMB16_S4_S4
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S4_S4;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 8192 x 2 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S2_S2 : if (BRAM_PRIMITIVE = B16_S2_S2) generate
component RAMB16_S2_S2
port (
DIA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (12 downto 0);
ADDRB : in std_logic_vector (12 downto 0);
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 13; -- 8192 deep
Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 2; -- 2 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--type pdbus_slice_array is array(BRAM_NUM downto 1) of
-- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
--slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
--slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_8192x2 : RAMB16_S2_S2
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S2_S2;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 16384 x 1 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S1_S1 : if (BRAM_PRIMITIVE = B16_S1_S1) generate
component RAMB16_S1_S1
port (
DIA : in std_logic_vector (0 downto 0);
DIB : in std_logic_vector (0 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (13 downto 0);
ADDRB : in std_logic_vector (13 downto 0);
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (0 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 14; -- 16384 deep
Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 1; -- 1 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--type pdbus_slice_array is array(BRAM_NUM downto 1) of
-- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
--slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
--slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_16384x1 : RAMB16_S1_S1
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S1_S1;
--==========================================================================
-- End of Virtex-II and Virtex-II Pro support
--///////////////////////////////////////////////////////////////////////////
--///////////////////////////////////////////////////////////////////////////
-- Start Spartan-II, Spartan-IIE, Virtex, and VirtexE support
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 4096 x 1 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S1_S1 : if (BRAM_PRIMITIVE = B4_S1_S1) generate
component RAMB4_S1_S1
port (
DIA : in std_logic_vector (0 downto 0);
DIB : in std_logic_vector (0 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (11 downto 0);
ADDRB : in std_logic_vector (11 downto 0);
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (0 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 12; -- 4096 deep
Constant PRIM_DBUS_WIDTH : integer := 1; -- 1 data bit
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_4096x1 : RAMB4_S1_S1
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S1_S1;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 2048 x 2 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S2_S2 : if (BRAM_PRIMITIVE = B4_S2_S2) generate
component RAMB4_S2_S2
port (
DIA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 11; -- 2048 deep
Constant PRIM_DBUS_WIDTH : integer := 2; -- 2 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_2048x2 : RAMB4_S2_S2
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S2_S2;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 1024 x 4 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S4_S4 : if (BRAM_PRIMITIVE = B4_S4_S4) generate
component RAMB4_S4_S4
port (
DIA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (9 downto 0);
ADDRB : in std_logic_vector (9 downto 0);
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (3 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 10; -- 1024 deep
Constant PRIM_DBUS_WIDTH : integer := 4; -- 4 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_1024x4 : RAMB4_S4_S4
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S4_S4;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 512 x 8 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S8_S8 : if (BRAM_PRIMITIVE = B4_S8_S8) generate
component RAMB4_S8_S8
port (
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (8 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 9; -- 512 deep
Constant PRIM_DBUS_WIDTH : integer := 8; -- 8 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_512x8 : RAMB4_S8_S8
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S8_S8;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 256 x 16 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S16_S16 : if (BRAM_PRIMITIVE = B4_S16_S16) generate
component RAMB4_S16_S16
port (DIA : in STD_LOGIC_VECTOR (15 downto 0);
DIB : in STD_LOGIC_VECTOR (15 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in STD_LOGIC_VECTOR (7 downto 0);
ADDRB : in STD_LOGIC_VECTOR (7 downto 0);
DOA : out STD_LOGIC_VECTOR (15 downto 0);
DOB : out STD_LOGIC_VECTOR (15 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 8; -- 256 deep
Constant PRIM_DBUS_WIDTH : integer := 16; -- 16 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_256x16 : RAMB4_S16_S16
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S16_S16;
--==========================================================================
UNSUPPORTED_FAMILY : if (BRAM_PRIMITIVE = indeterminate) generate
begin
-- assert (false)
-- report "Unsupported Part Family Selected or FIFO Depth/Width is invalid!"
-- severity failure;
--
end generate UNSUPPORTED_FAMILY;
end architecture implementation;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity val1 is
generic(
n:integer:=9
);
port(
NewWord : IN STD_LOGIC_VECTOR(n-1 downto 0); --cadena recien hecha
Clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
GoodWord : OUT STD_LOGIC_VECTOR(n-1 downto 0) --palabra que saldra si pasa los filtros
);
end val1;
architecture Behavioral of val1 is
signal AlreadyInWord : STD_LOGIC_VECTOR(n-1 downto 0); --cadena de comprobacion o estado presente
signal FinalWord : STD_LOGIC_VECTOR(n-1 downto 0); --cadena de comprobacion nueva o proximo estado
signal GoodWord2 : STD_LOGIC_VECTOR(n-1 downto 0);
begin
comb: process (NewWord,AlreadyInWord)
begin
for I in 0 to n-1 loop
if(AlreadyInWord(I)='0') then
GoodWord2(I)<=NewWord(I);
else
GoodWord2(I)<='0';
end if;
FinalWord(I) <= NewWord(I) OR AlreadyInWord(I);
end loop;
end process;
sequ: process(Clk,FinalWord,rst)
begin
if(rst = '1') then
AlreadyInWord <= "000000000";
elsif(Clk'event AND Clk='1') then
AlreadyInWord<=FinalWord;
GoodWord<=GoodWord2;
end if;
end process;
end Behavioral;
|
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: P.20131013
-- \ \ Application: netgen
-- / / Filename: rc5_timesim.vhd
-- /___/ /\ Timestamp: Tue Apr 07 17:38:47 2015
-- \ \ / \
-- \___\/\___\
--
-- Command : -filter C:/SkyDrive/School/Polytechnic/EL6463_AdvancedHardwareDesign/Labs/Lab7/rc5_impl/iseconfig/filter.filter -intstyle ise -s 4 -pcf rc5.pcf -rpw 100 -tpw 0 -ar Structure -tm rc5 -insert_pp_buffers true -w -dir netgen/par -ofmt vhdl -sim rc5.ncd rc5_timesim.vhd
-- Device : 3s100ecp132-4 (PRODUCTION 1.27 2013-10-13)
-- Input file : rc5.ncd
-- Output file : C:\SkyDrive\School\Polytechnic\EL6463_AdvancedHardwareDesign\Labs\Lab7\rc5_impl\netgen\par\rc5_timesim.vhd
-- # of Entities : 1
-- Design Name : rc5
-- Xilinx : C:\Xilinx\14.7\ISE_DS\ISE\
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Command Line Tools User Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity rc5 is
port (
clr : in STD_LOGIC := 'X';
segment_e_i : out STD_LOGIC;
do_rdy : out STD_LOGIC;
segment_f_i : out STD_LOGIC;
segment_g_i : out STD_LOGIC;
clk_25 : in STD_LOGIC := 'X';
di_vld : in STD_LOGIC := 'X';
segment_a_i : out STD_LOGIC;
segment_b_i : out STD_LOGIC;
segment_c_i : out STD_LOGIC;
segment_d_i : out STD_LOGIC;
AN : out STD_LOGIC_VECTOR ( 3 downto 0 );
swtch_led : out STD_LOGIC_VECTOR ( 7 downto 0 );
din_lower : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
end rc5;
architecture Structure of rc5 is
signal NlwRenamedSig_IO_clr : STD_LOGIC;
signal NlwRenamedSig_IO_di_vld : STD_LOGIC;
signal clk_25_BUFGP : STD_LOGIC;
signal clr_IBUF_3948 : STD_LOGIC;
signal Mcount_LED_flash_cnt_cy_1_Q : STD_LOGIC;
signal Mcount_LED_flash_cnt_cy_3_Q : STD_LOGIC;
signal Mcount_LED_flash_cnt_cy_5_Q : STD_LOGIC;
signal Sh64_0 : STD_LOGIC;
signal Mrom_a_rom0000_0 : STD_LOGIC;
signal Mrom_a_rom00001_0 : STD_LOGIC;
signal Sh33 : STD_LOGIC;
signal Sh49 : STD_LOGIC;
signal Madd_a_cy_1_Q : STD_LOGIC;
signal Mrom_a_rom00002_0 : STD_LOGIC;
signal Sh34 : STD_LOGIC;
signal Sh50 : STD_LOGIC;
signal N224_0 : STD_LOGIC;
signal Sh35 : STD_LOGIC;
signal Sh51 : STD_LOGIC;
signal Madd_a_cy_3_Q : STD_LOGIC;
signal Mrom_a_rom00004_0 : STD_LOGIC;
signal Sh36 : STD_LOGIC;
signal Sh52 : STD_LOGIC;
signal Mrom_a_rom00005_0 : STD_LOGIC;
signal Sh37 : STD_LOGIC;
signal Sh53 : STD_LOGIC;
signal Madd_a_cy_5_Q : STD_LOGIC;
signal Mrom_a_rom00006_0 : STD_LOGIC;
signal Sh38 : STD_LOGIC;
signal Sh54 : STD_LOGIC;
signal N286_0 : STD_LOGIC;
signal Sh55 : STD_LOGIC;
signal Sh39 : STD_LOGIC;
signal Madd_a_cy_7_Q : STD_LOGIC;
signal Mrom_a_rom00008_0 : STD_LOGIC;
signal Sh40 : STD_LOGIC;
signal Sh56 : STD_LOGIC;
signal Mrom_a_rom00009_0 : STD_LOGIC;
signal Sh41 : STD_LOGIC;
signal Sh57 : STD_LOGIC;
signal Madd_a_cy_9_Q : STD_LOGIC;
signal Mrom_a_rom000010_0 : STD_LOGIC;
signal Sh42 : STD_LOGIC;
signal Sh58 : STD_LOGIC;
signal Sh59 : STD_LOGIC;
signal Mrom_a_rom000011_0 : STD_LOGIC;
signal Sh43 : STD_LOGIC;
signal Madd_a_cy_11_Q : STD_LOGIC;
signal Sh60 : STD_LOGIC;
signal N222_0 : STD_LOGIC;
signal Sh44 : STD_LOGIC;
signal Mrom_a_rom000013_0 : STD_LOGIC;
signal Sh45 : STD_LOGIC;
signal Sh61 : STD_LOGIC;
signal Madd_a_cy_13_Q : STD_LOGIC;
signal N226_0 : STD_LOGIC;
signal Sh46 : STD_LOGIC;
signal Sh62 : STD_LOGIC;
signal Sh63 : STD_LOGIC;
signal Mrom_a_rom000015_0 : STD_LOGIC;
signal Sh47 : STD_LOGIC;
signal Madd_a_cy_15_Q : STD_LOGIC;
signal Sh32 : STD_LOGIC;
signal Mrom_a_rom000016_0 : STD_LOGIC;
signal Sh48 : STD_LOGIC;
signal Mrom_a_rom000017_0 : STD_LOGIC;
signal Madd_a_cy_17_Q : STD_LOGIC;
signal Mrom_a_rom000018_0 : STD_LOGIC;
signal Mrom_a_rom000019_0 : STD_LOGIC;
signal Madd_a_cy_19_Q : STD_LOGIC;
signal Sh84_0 : STD_LOGIC;
signal Mrom_a_rom000021_0 : STD_LOGIC;
signal Madd_a_cy_21_Q : STD_LOGIC;
signal N520_0 : STD_LOGIC;
signal Mrom_a_rom000023_0 : STD_LOGIC;
signal Madd_a_cy_23_Q : STD_LOGIC;
signal Mrom_a_rom000024_0 : STD_LOGIC;
signal Mrom_a_rom000025_0 : STD_LOGIC;
signal Madd_a_cy_25_Q : STD_LOGIC;
signal Mrom_a_rom000026_0 : STD_LOGIC;
signal Mrom_a_rom000027_0 : STD_LOGIC;
signal Madd_a_cy_27_Q : STD_LOGIC;
signal N518_0 : STD_LOGIC;
signal Mrom_a_rom000029_0 : STD_LOGIC;
signal Mrom_a_rom000030_0 : STD_LOGIC;
signal Mrom_a_rom000031_0 : STD_LOGIC;
signal Sh160 : STD_LOGIC;
signal Mrom_b_rom0000_0 : STD_LOGIC;
signal Sh145 : STD_LOGIC;
signal Mrom_b_rom00001_0 : STD_LOGIC;
signal Sh129 : STD_LOGIC;
signal b_1_Q : STD_LOGIC;
signal Madd_b_cy_1_Q : STD_LOGIC;
signal Sh162 : STD_LOGIC;
signal N14_0 : STD_LOGIC;
signal N17_0 : STD_LOGIC;
signal Sh163 : STD_LOGIC;
signal N33_0 : STD_LOGIC;
signal N12_0 : STD_LOGIC;
signal i_cnt_mux0001_0_22_4123 : STD_LOGIC;
signal b_2_Q : STD_LOGIC;
signal b_3_Q : STD_LOGIC;
signal Madd_b_cy_3_Q : STD_LOGIC;
signal Sh164 : STD_LOGIC;
signal N20_0 : STD_LOGIC;
signal Mrom_b_rom00005_0 : STD_LOGIC;
signal Sh133 : STD_LOGIC;
signal Sh149 : STD_LOGIC;
signal b_4_Q : STD_LOGIC;
signal b_5_Q : STD_LOGIC;
signal Madd_b_cy_5_Q : STD_LOGIC;
signal Sh150_0 : STD_LOGIC;
signal Mrom_b_rom00006_0 : STD_LOGIC;
signal Sh134 : STD_LOGIC;
signal Sh151 : STD_LOGIC;
signal Mrom_b_rom00007_0 : STD_LOGIC;
signal Sh135 : STD_LOGIC;
signal b_6_Q : STD_LOGIC;
signal b_7_Q : STD_LOGIC;
signal Madd_b_cy_7_Q : STD_LOGIC;
signal Mrom_b_rom00008_0 : STD_LOGIC;
signal Sh136 : STD_LOGIC;
signal Sh152 : STD_LOGIC;
signal Mrom_b_rom00009_0 : STD_LOGIC;
signal Sh137 : STD_LOGIC;
signal Sh153 : STD_LOGIC;
signal Madd_b_cy_9_Q : STD_LOGIC;
signal Sh154_0 : STD_LOGIC;
signal Mrom_b_rom000010_0 : STD_LOGIC;
signal Sh138 : STD_LOGIC;
signal Mrom_b_rom000011_0 : STD_LOGIC;
signal Sh139 : STD_LOGIC;
signal Sh155 : STD_LOGIC;
signal b_11_Q : STD_LOGIC;
signal Madd_b_cy_11_Q : STD_LOGIC;
signal Mrom_b_rom000012_0 : STD_LOGIC;
signal Sh140 : STD_LOGIC;
signal Sh156 : STD_LOGIC;
signal Mrom_b_rom000013_0 : STD_LOGIC;
signal Sh141 : STD_LOGIC;
signal Sh157 : STD_LOGIC;
signal b_12_Q : STD_LOGIC;
signal b_13_Q : STD_LOGIC;
signal Madd_b_cy_13_Q : STD_LOGIC;
signal Sh158 : STD_LOGIC;
signal Mrom_b_rom000014_0 : STD_LOGIC;
signal Sh142 : STD_LOGIC;
signal Sh175 : STD_LOGIC;
signal N522_0 : STD_LOGIC;
signal b_14_Q : STD_LOGIC;
signal b_15_Q : STD_LOGIC;
signal Madd_b_cy_15_Q : STD_LOGIC;
signal Mrom_b_rom000016_0 : STD_LOGIC;
signal Sh144_0 : STD_LOGIC;
signal Sh128 : STD_LOGIC;
signal Mrom_b_rom000017_0 : STD_LOGIC;
signal b_16_Q : STD_LOGIC;
signal b_17_Q : STD_LOGIC;
signal Madd_b_cy_17_Q : STD_LOGIC;
signal Sh178 : STD_LOGIC;
signal N27_0 : STD_LOGIC;
signal N77_0 : STD_LOGIC;
signal N34_0 : STD_LOGIC;
signal Mrom_b_rom000019_0 : STD_LOGIC;
signal Sh147_0 : STD_LOGIC;
signal Sh131 : STD_LOGIC;
signal b_18_Q : STD_LOGIC;
signal b_19_Q : STD_LOGIC;
signal Madd_b_cy_19_Q : STD_LOGIC;
signal Mrom_b_rom000020_0 : STD_LOGIC;
signal Sh148_0 : STD_LOGIC;
signal Sh132 : STD_LOGIC;
signal Mrom_b_rom000021_0 : STD_LOGIC;
signal b_20_Q : STD_LOGIC;
signal b_21_Q : STD_LOGIC;
signal Madd_b_cy_21_Q : STD_LOGIC;
signal Mrom_b_rom000022_0 : STD_LOGIC;
signal Mrom_b_rom000023_0 : STD_LOGIC;
signal b_22_Q : STD_LOGIC;
signal b_23_Q : STD_LOGIC;
signal Madd_b_cy_23_Q : STD_LOGIC;
signal Mrom_b_rom000024_0 : STD_LOGIC;
signal Sh185_0 : STD_LOGIC;
signal N111_0 : STD_LOGIC;
signal b_24_Q : STD_LOGIC;
signal b_25_Q : STD_LOGIC;
signal Madd_b_cy_25_Q : STD_LOGIC;
signal Mrom_b_rom000026_0 : STD_LOGIC;
signal Mrom_b_rom000027_0 : STD_LOGIC;
signal b_26_Q : STD_LOGIC;
signal b_27_Q : STD_LOGIC;
signal Madd_b_cy_27_Q : STD_LOGIC;
signal Mrom_b_rom000028_0 : STD_LOGIC;
signal Mrom_b_rom000029_0 : STD_LOGIC;
signal b_28_Q : STD_LOGIC;
signal b_29_Q : STD_LOGIC;
signal Mrom_b_rom000030_0 : STD_LOGIC;
signal Mrom_b_rom000031_0 : STD_LOGIC;
signal Sh159_0 : STD_LOGIC;
signal Sh143_0 : STD_LOGIC;
signal b_30_Q : STD_LOGIC;
signal b_31_Q : STD_LOGIC;
signal Madd_b_pre_cy_0_Q : STD_LOGIC;
signal swtch_led_1_OBUF_4254 : STD_LOGIC;
signal swtch_led_3_OBUF_4256 : STD_LOGIC;
signal swtch_led_4_OBUF_4257 : STD_LOGIC;
signal swtch_led_5_OBUF_4258 : STD_LOGIC;
signal swtch_led_6_OBUF_4259 : STD_LOGIC;
signal swtch_led_7_OBUF_4260 : STD_LOGIC;
signal AN_0_4261 : STD_LOGIC;
signal AN_1_4262 : STD_LOGIC;
signal AN_2_4263 : STD_LOGIC;
signal AN_3_4264 : STD_LOGIC;
signal di_vld_IBUF_4273 : STD_LOGIC;
signal Sh1212_0 : STD_LOGIC;
signal Sh1232_0 : STD_LOGIC;
signal Sh991_0 : STD_LOGIC;
signal Sh1011 : STD_LOGIC;
signal Sh13120 : STD_LOGIC;
signal Sh125 : STD_LOGIC;
signal Sh121 : STD_LOGIC;
signal Sh101 : STD_LOGIC;
signal Sh97 : STD_LOGIC;
signal Sh100 : STD_LOGIC;
signal Sh96 : STD_LOGIC;
signal Sh108 : STD_LOGIC;
signal Sh104 : STD_LOGIC;
signal Sh109 : STD_LOGIC;
signal Sh105 : STD_LOGIC;
signal Sh102_0 : STD_LOGIC;
signal Sh98_0 : STD_LOGIC;
signal Sh110_0 : STD_LOGIC;
signal Sh106_0 : STD_LOGIC;
signal Sh123 : STD_LOGIC;
signal Sh127 : STD_LOGIC;
signal Sh103_0 : STD_LOGIC;
signal Sh99_0 : STD_LOGIC;
signal Sh1022_0 : STD_LOGIC;
signal Sh1002_0 : STD_LOGIC;
signal Sh1102_0 : STD_LOGIC;
signal Sh1082_0 : STD_LOGIC;
signal Sh14612 : STD_LOGIC;
signal Sh124 : STD_LOGIC;
signal Sh1032_0 : STD_LOGIC;
signal Sh1012_0 : STD_LOGIC;
signal Sh1112_0 : STD_LOGIC;
signal Sh1092_0 : STD_LOGIC;
signal Sh14712 : STD_LOGIC;
signal Sh107 : STD_LOGIC;
signal state_FSM_FFd1_4311 : STD_LOGIC;
signal state_FSM_FFd2_4312 : STD_LOGIC;
signal b_reg_mux0000_10_10_0 : STD_LOGIC;
signal b_reg_0_3_4316 : STD_LOGIC;
signal ab_xor_7_0 : STD_LOGIC;
signal ab_xor_9_0 : STD_LOGIC;
signal Sh10 : STD_LOGIC;
signal b_reg_0_2_4323 : STD_LOGIC;
signal ab_xor_11_0 : STD_LOGIC;
signal ab_xor_12_0 : STD_LOGIC;
signal Sh13 : STD_LOGIC;
signal ab_xor_19_0 : STD_LOGIC;
signal ab_xor_20_0 : STD_LOGIC;
signal Sh21 : STD_LOGIC;
signal ab_xor_13_0 : STD_LOGIC;
signal Sh14 : STD_LOGIC;
signal ab_xor_21_0 : STD_LOGIC;
signal Sh22_4347 : STD_LOGIC;
signal ab_xor_27_0 : STD_LOGIC;
signal ab_xor_29_0 : STD_LOGIC;
signal Sh30 : STD_LOGIC;
signal ab_xor_15_0 : STD_LOGIC;
signal ab_xor_16_0 : STD_LOGIC;
signal Sh17 : STD_LOGIC;
signal ab_xor_23_0 : STD_LOGIC;
signal ab_xor_24_0 : STD_LOGIC;
signal Sh25 : STD_LOGIC;
signal ab_xor_17_0 : STD_LOGIC;
signal Sh18 : STD_LOGIC;
signal ab_xor_25_0 : STD_LOGIC;
signal Sh26 : STD_LOGIC;
signal ab_xor_28_0 : STD_LOGIC;
signal Sh29 : STD_LOGIC;
signal b_reg_2_1_4381 : STD_LOGIC;
signal b_reg_0_1_4382 : STD_LOGIC;
signal b_reg_4_1_4383 : STD_LOGIC;
signal ab_xor_3_0 : STD_LOGIC;
signal Sh4 : STD_LOGIC;
signal ab_xor_5_0 : STD_LOGIC;
signal Sh8 : STD_LOGIC;
signal Sh1262_0 : STD_LOGIC;
signal Sh962_0 : STD_LOGIC;
signal Sh1272_0 : STD_LOGIC;
signal N264_0 : STD_LOGIC;
signal N263_0 : STD_LOGIC;
signal N247_0 : STD_LOGIC;
signal N246_0 : STD_LOGIC;
signal Sh1182_0 : STD_LOGIC;
signal N182_0 : STD_LOGIC;
signal N181_0 : STD_LOGIC;
signal Sh120 : STD_LOGIC;
signal Sh1202_0 : STD_LOGIC;
signal N194_0 : STD_LOGIC;
signal N193_0 : STD_LOGIC;
signal Sh112 : STD_LOGIC;
signal Sh1122_0 : STD_LOGIC;
signal N261_0 : STD_LOGIC;
signal N260_0 : STD_LOGIC;
signal Sh1042_0 : STD_LOGIC;
signal Sh1192_0 : STD_LOGIC;
signal N179_0 : STD_LOGIC;
signal N178_0 : STD_LOGIC;
signal N191_0 : STD_LOGIC;
signal N190_0 : STD_LOGIC;
signal Sh113 : STD_LOGIC;
signal Sh1132_0 : STD_LOGIC;
signal N241_0 : STD_LOGIC;
signal N240_0 : STD_LOGIC;
signal Sh1052_0 : STD_LOGIC;
signal Sh1222_0 : STD_LOGIC;
signal N176_0 : STD_LOGIC;
signal N175_0 : STD_LOGIC;
signal Sh1242_0 : STD_LOGIC;
signal Sh1142_0 : STD_LOGIC;
signal N188_0 : STD_LOGIC;
signal N187_0 : STD_LOGIC;
signal Sh116 : STD_LOGIC;
signal Sh1162_0 : STD_LOGIC;
signal Sh1062_0 : STD_LOGIC;
signal N258_0 : STD_LOGIC;
signal N257_0 : STD_LOGIC;
signal N173_0 : STD_LOGIC;
signal N172_0 : STD_LOGIC;
signal Sh1252_0 : STD_LOGIC;
signal Sh1152_0 : STD_LOGIC;
signal N185_0 : STD_LOGIC;
signal N184_0 : STD_LOGIC;
signal Sh117 : STD_LOGIC;
signal Sh1172_0 : STD_LOGIC;
signal Sh1072_0 : STD_LOGIC;
signal N235_0 : STD_LOGIC;
signal N234_0 : STD_LOGIC;
signal Sh3 : STD_LOGIC;
signal ab_xor_4_0 : STD_LOGIC;
signal Sh7 : STD_LOGIC;
signal ab_xor_8_0 : STD_LOGIC;
signal Sh11 : STD_LOGIC;
signal Sh15 : STD_LOGIC;
signal Sh23_4457 : STD_LOGIC;
signal ab_xor_31_0 : STD_LOGIC;
signal Sh31 : STD_LOGIC;
signal Sh19 : STD_LOGIC;
signal Sh27 : STD_LOGIC;
signal Sh12 : STD_LOGIC;
signal Sh20 : STD_LOGIC;
signal Sh16 : STD_LOGIC;
signal Sh24 : STD_LOGIC;
signal Sh28 : STD_LOGIC;
signal N200 : STD_LOGIC;
signal N199_0 : STD_LOGIC;
signal N197 : STD_LOGIC;
signal N196_0 : STD_LOGIC;
signal Sh : STD_LOGIC;
signal b_reg_mux0000_2_5_0 : STD_LOGIC;
signal b_reg_mux0000_2_13_0 : STD_LOGIC;
signal N291 : STD_LOGIC;
signal N292 : STD_LOGIC;
signal Madd_b_pre_cy_2_Q : STD_LOGIC;
signal N281 : STD_LOGIC;
signal N282 : STD_LOGIC;
signal b_reg_mux0000_4_3_0 : STD_LOGIC;
signal b_reg_mux0000_4_12_0 : STD_LOGIC;
signal N278 : STD_LOGIC;
signal N279 : STD_LOGIC;
signal Sh1307 : STD_LOGIC;
signal Sh14416_4486 : STD_LOGIC;
signal Sh14412_0 : STD_LOGIC;
signal Sh14413_0 : STD_LOGIC;
signal Sh12813_0 : STD_LOGIC;
signal Sh1287_0 : STD_LOGIC;
signal Sh12816_0 : STD_LOGIC;
signal Sh1507 : STD_LOGIC;
signal Sh982_4493 : STD_LOGIC;
signal Sh13820 : STD_LOGIC;
signal Sh1517 : STD_LOGIC;
signal Sh14613_0 : STD_LOGIC;
signal Sh14616_0 : STD_LOGIC;
signal Sh13013_0 : STD_LOGIC;
signal Sh13016_0 : STD_LOGIC;
signal Sh14713_4500 : STD_LOGIC;
signal Sh14716_4501 : STD_LOGIC;
signal Sh1310_0 : STD_LOGIC;
signal Sh1313 : STD_LOGIC;
signal Sh1487_4504 : STD_LOGIC;
signal Sh14816_0 : STD_LOGIC;
signal Sh14813_0 : STD_LOGIC;
signal Sh13220_0 : STD_LOGIC;
signal Sh5 : STD_LOGIC;
signal Sh1 : STD_LOGIC;
signal Sh9 : STD_LOGIC;
signal Sh1547 : STD_LOGIC;
signal Sh13420 : STD_LOGIC;
signal Sh1557 : STD_LOGIC;
signal Sh6 : STD_LOGIC;
signal Sh2 : STD_LOGIC;
signal Sh1597 : STD_LOGIC;
signal Sh14313_0 : STD_LOGIC;
signal Sh14316_4518 : STD_LOGIC;
signal Sh1437_0 : STD_LOGIC;
signal Sh1587 : STD_LOGIC;
signal Madd_b_pre_cy_4_0 : STD_LOGIC;
signal N275 : STD_LOGIC;
signal N276 : STD_LOGIC;
signal b_reg_mux0000_6_3_0 : STD_LOGIC;
signal b_reg_mux0000_6_12_0 : STD_LOGIC;
signal N272 : STD_LOGIC;
signal N273 : STD_LOGIC;
signal Madd_b_pre_cy_6_Q : STD_LOGIC;
signal N269 : STD_LOGIC;
signal N270 : STD_LOGIC;
signal b_reg_mux0000_0_Q : STD_LOGIC;
signal N266 : STD_LOGIC;
signal N267 : STD_LOGIC;
signal i_cnt_mux0001_0_25_0 : STD_LOGIC;
signal N514_0 : STD_LOGIC;
signal Sh15013_0 : STD_LOGIC;
signal Sh15016_O : STD_LOGIC;
signal Sh15413_0 : STD_LOGIC;
signal Sh15416_O : STD_LOGIC;
signal Sh5720_0 : STD_LOGIC;
signal Sh5320_0 : STD_LOGIC;
signal Sh5820_0 : STD_LOGIC;
signal Sh5420_0 : STD_LOGIC;
signal Sh337_0 : STD_LOGIC;
signal Sh347_0 : STD_LOGIC;
signal N249_0 : STD_LOGIC;
signal Mxor_ba_xor_Result_5_1_SW1_O : STD_LOGIC;
signal N243_0 : STD_LOGIC;
signal Mxor_ba_xor_Result_13_1_SW1_O : STD_LOGIC;
signal N231_0 : STD_LOGIC;
signal Mxor_ba_xor_Result_7_1_SW1_O : STD_LOGIC;
signal N254_0 : STD_LOGIC;
signal Mxor_ba_xor_Result_15_1_SW1_O : STD_LOGIC;
signal N228_0 : STD_LOGIC;
signal Mxor_ba_xor_Result_9_1_SW1_O : STD_LOGIC;
signal N237_0 : STD_LOGIC;
signal Mxor_ba_xor_Result_17_1_SW1_O : STD_LOGIC;
signal N217_0 : STD_LOGIC;
signal Mxor_ba_xor_Result_25_1_SW1_O : STD_LOGIC;
signal N211_0 : STD_LOGIC;
signal Mxor_ba_xor_Result_11_1_SW1_O : STD_LOGIC;
signal N251_0 : STD_LOGIC;
signal Mxor_ba_xor_Result_19_1_SW1_O : STD_LOGIC;
signal N205_0 : STD_LOGIC;
signal Mxor_ba_xor_Result_21_1_SW1_O : STD_LOGIC;
signal N214_0 : STD_LOGIC;
signal Mxor_ba_xor_Result_29_1_SW1_O : STD_LOGIC;
signal N208_0 : STD_LOGIC;
signal Mxor_ba_xor_Result_23_1_SW1_O : STD_LOGIC;
signal N202_0 : STD_LOGIC;
signal Sh12913_0 : STD_LOGIC;
signal Sh1297_0 : STD_LOGIC;
signal Sh12916_0 : STD_LOGIC;
signal Sh15513_0 : STD_LOGIC;
signal Sh15516_0 : STD_LOGIC;
signal Sh1567_0 : STD_LOGIC;
signal Sh1497_0 : STD_LOGIC;
signal Sh1537_0 : STD_LOGIC;
signal Sh1577_0 : STD_LOGIC;
signal Sh15813_0 : STD_LOGIC;
signal Sh15816_0 : STD_LOGIC;
signal Sh15113_0 : STD_LOGIC;
signal Sh15116_0 : STD_LOGIC;
signal Sh1527_0 : STD_LOGIC;
signal b_reg_3_1_4597 : STD_LOGIC;
signal N289_0 : STD_LOGIC;
signal N288_0 : STD_LOGIC;
signal N516 : STD_LOGIC;
signal state_cmp_eq0000 : STD_LOGIC;
signal LED_flash_cnt_0_DXMUX_4658 : STD_LOGIC;
signal LED_flash_cnt_0_XORF_4656 : STD_LOGIC;
signal LED_flash_cnt_0_LOGIC_ONE_4655 : STD_LOGIC;
signal LED_flash_cnt_0_CYINIT_4654 : STD_LOGIC;
signal LED_flash_cnt_0_CYSELF_4645 : STD_LOGIC;
signal LED_flash_cnt_0_BXINV_4643 : STD_LOGIC;
signal LED_flash_cnt_0_DYMUX_4636 : STD_LOGIC;
signal LED_flash_cnt_0_XORG_4634 : STD_LOGIC;
signal LED_flash_cnt_0_CYMUXG_4633 : STD_LOGIC;
signal Mcount_LED_flash_cnt_cy_0_Q : STD_LOGIC;
signal LED_flash_cnt_0_LOGIC_ZERO_4631 : STD_LOGIC;
signal LED_flash_cnt_0_CYSELG_4622 : STD_LOGIC;
signal LED_flash_cnt_0_G : STD_LOGIC;
signal LED_flash_cnt_0_SRINV_4620 : STD_LOGIC;
signal LED_flash_cnt_0_CLKINV_4619 : STD_LOGIC;
signal LED_flash_cnt_2_DXMUX_4714 : STD_LOGIC;
signal LED_flash_cnt_2_XORF_4712 : STD_LOGIC;
signal LED_flash_cnt_2_CYINIT_4711 : STD_LOGIC;
signal LED_flash_cnt_2_F : STD_LOGIC;
signal LED_flash_cnt_2_DYMUX_4695 : STD_LOGIC;
signal LED_flash_cnt_2_XORG_4693 : STD_LOGIC;
signal Mcount_LED_flash_cnt_cy_2_Q : STD_LOGIC;
signal LED_flash_cnt_2_CYSELF_4691 : STD_LOGIC;
signal LED_flash_cnt_2_CYMUXFAST_4690 : STD_LOGIC;
signal LED_flash_cnt_2_CYAND_4689 : STD_LOGIC;
signal LED_flash_cnt_2_FASTCARRY_4688 : STD_LOGIC;
signal LED_flash_cnt_2_CYMUXG2_4687 : STD_LOGIC;
signal LED_flash_cnt_2_CYMUXF2_4686 : STD_LOGIC;
signal LED_flash_cnt_2_LOGIC_ZERO_4685 : STD_LOGIC;
signal LED_flash_cnt_2_CYSELG_4676 : STD_LOGIC;
signal LED_flash_cnt_2_G : STD_LOGIC;
signal LED_flash_cnt_2_SRINV_4674 : STD_LOGIC;
signal LED_flash_cnt_2_CLKINV_4673 : STD_LOGIC;
signal LED_flash_cnt_4_FFY_RST : STD_LOGIC;
signal LED_flash_cnt_4_DXMUX_4770 : STD_LOGIC;
signal LED_flash_cnt_4_XORF_4768 : STD_LOGIC;
signal LED_flash_cnt_4_CYINIT_4767 : STD_LOGIC;
signal LED_flash_cnt_4_F : STD_LOGIC;
signal LED_flash_cnt_4_DYMUX_4751 : STD_LOGIC;
signal LED_flash_cnt_4_XORG_4749 : STD_LOGIC;
signal Mcount_LED_flash_cnt_cy_4_Q : STD_LOGIC;
signal LED_flash_cnt_4_CYSELF_4747 : STD_LOGIC;
signal LED_flash_cnt_4_CYMUXFAST_4746 : STD_LOGIC;
signal LED_flash_cnt_4_CYAND_4745 : STD_LOGIC;
signal LED_flash_cnt_4_FASTCARRY_4744 : STD_LOGIC;
signal LED_flash_cnt_4_CYMUXG2_4743 : STD_LOGIC;
signal LED_flash_cnt_4_CYMUXF2_4742 : STD_LOGIC;
signal LED_flash_cnt_4_LOGIC_ZERO_4741 : STD_LOGIC;
signal LED_flash_cnt_4_CYSELG_4732 : STD_LOGIC;
signal LED_flash_cnt_4_G : STD_LOGIC;
signal LED_flash_cnt_4_SRINV_4730 : STD_LOGIC;
signal LED_flash_cnt_4_CLKINV_4729 : STD_LOGIC;
signal LED_flash_cnt_6_DXMUX_4826 : STD_LOGIC;
signal LED_flash_cnt_6_XORF_4824 : STD_LOGIC;
signal LED_flash_cnt_6_CYINIT_4823 : STD_LOGIC;
signal LED_flash_cnt_6_F : STD_LOGIC;
signal LED_flash_cnt_6_DYMUX_4807 : STD_LOGIC;
signal LED_flash_cnt_6_XORG_4805 : STD_LOGIC;
signal Mcount_LED_flash_cnt_cy_6_Q : STD_LOGIC;
signal LED_flash_cnt_6_CYSELF_4803 : STD_LOGIC;
signal LED_flash_cnt_6_CYMUXFAST_4802 : STD_LOGIC;
signal LED_flash_cnt_6_CYAND_4801 : STD_LOGIC;
signal LED_flash_cnt_6_FASTCARRY_4800 : STD_LOGIC;
signal LED_flash_cnt_6_CYMUXG2_4799 : STD_LOGIC;
signal LED_flash_cnt_6_CYMUXF2_4798 : STD_LOGIC;
signal LED_flash_cnt_6_LOGIC_ZERO_4797 : STD_LOGIC;
signal LED_flash_cnt_6_CYSELG_4788 : STD_LOGIC;
signal LED_flash_cnt_6_G : STD_LOGIC;
signal LED_flash_cnt_6_SRINV_4786 : STD_LOGIC;
signal LED_flash_cnt_6_CLKINV_4785 : STD_LOGIC;
signal LED_flash_cnt_8_DXMUX_4875 : STD_LOGIC;
signal LED_flash_cnt_8_XORF_4873 : STD_LOGIC;
signal LED_flash_cnt_8_LOGIC_ZERO_4872 : STD_LOGIC;
signal LED_flash_cnt_8_CYINIT_4871 : STD_LOGIC;
signal LED_flash_cnt_8_CYSELF_4862 : STD_LOGIC;
signal LED_flash_cnt_8_F : STD_LOGIC;
signal LED_flash_cnt_8_DYMUX_4854 : STD_LOGIC;
signal LED_flash_cnt_8_XORG_4852 : STD_LOGIC;
signal Mcount_LED_flash_cnt_cy_8_Q : STD_LOGIC;
signal LED_flash_cnt_9_rt_4849 : STD_LOGIC;
signal LED_flash_cnt_8_SRINV_4841 : STD_LOGIC;
signal LED_flash_cnt_8_CLKINV_4840 : STD_LOGIC;
signal a_0_XORF_4918 : STD_LOGIC;
signal a_0_CYINIT_4917 : STD_LOGIC;
signal a_0_CY0F_4916 : STD_LOGIC;
signal a_0_CYSELF_4908 : STD_LOGIC;
signal a_0_BXINV_4906 : STD_LOGIC;
signal a_0_XORG_4904 : STD_LOGIC;
signal a_0_CYMUXG_4903 : STD_LOGIC;
signal Madd_a_cy_0_Q : STD_LOGIC;
signal a_0_CY0G_4901 : STD_LOGIC;
signal a_0_CYSELG_4895 : STD_LOGIC;
signal a_2_XORF_4961 : STD_LOGIC;
signal a_2_CYINIT_4960 : STD_LOGIC;
signal a_2_CY0F_4959 : STD_LOGIC;
signal a_2_XORG_4950 : STD_LOGIC;
signal Madd_a_cy_2_Q : STD_LOGIC;
signal a_2_CYSELF_4948 : STD_LOGIC;
signal a_2_CYMUXFAST_4947 : STD_LOGIC;
signal a_2_CYAND_4946 : STD_LOGIC;
signal a_2_FASTCARRY_4945 : STD_LOGIC;
signal a_2_CYMUXG2_4944 : STD_LOGIC;
signal a_2_CYMUXF2_4943 : STD_LOGIC;
signal a_2_CY0G_4942 : STD_LOGIC;
signal a_2_CYSELG_4936 : STD_LOGIC;
signal a_4_XORF_5004 : STD_LOGIC;
signal a_4_CYINIT_5003 : STD_LOGIC;
signal a_4_CY0F_5002 : STD_LOGIC;
signal a_4_XORG_4993 : STD_LOGIC;
signal Madd_a_cy_4_Q : STD_LOGIC;
signal a_4_CYSELF_4991 : STD_LOGIC;
signal a_4_CYMUXFAST_4990 : STD_LOGIC;
signal a_4_CYAND_4989 : STD_LOGIC;
signal a_4_FASTCARRY_4988 : STD_LOGIC;
signal a_4_CYMUXG2_4987 : STD_LOGIC;
signal a_4_CYMUXF2_4986 : STD_LOGIC;
signal a_4_CY0G_4985 : STD_LOGIC;
signal a_4_CYSELG_4979 : STD_LOGIC;
signal a_6_XORF_5047 : STD_LOGIC;
signal a_6_CYINIT_5046 : STD_LOGIC;
signal a_6_CY0F_5045 : STD_LOGIC;
signal a_6_XORG_5036 : STD_LOGIC;
signal Madd_a_cy_6_Q : STD_LOGIC;
signal a_6_CYSELF_5034 : STD_LOGIC;
signal a_6_CYMUXFAST_5033 : STD_LOGIC;
signal a_6_CYAND_5032 : STD_LOGIC;
signal a_6_FASTCARRY_5031 : STD_LOGIC;
signal a_6_CYMUXG2_5030 : STD_LOGIC;
signal a_6_CYMUXF2_5029 : STD_LOGIC;
signal a_6_CY0G_5028 : STD_LOGIC;
signal a_6_CYSELG_5022 : STD_LOGIC;
signal a_8_XORF_5090 : STD_LOGIC;
signal a_8_CYINIT_5089 : STD_LOGIC;
signal a_8_CY0F_5088 : STD_LOGIC;
signal a_8_XORG_5079 : STD_LOGIC;
signal Madd_a_cy_8_Q : STD_LOGIC;
signal a_8_CYSELF_5077 : STD_LOGIC;
signal a_8_CYMUXFAST_5076 : STD_LOGIC;
signal a_8_CYAND_5075 : STD_LOGIC;
signal a_8_FASTCARRY_5074 : STD_LOGIC;
signal a_8_CYMUXG2_5073 : STD_LOGIC;
signal a_8_CYMUXF2_5072 : STD_LOGIC;
signal a_8_CY0G_5071 : STD_LOGIC;
signal a_8_CYSELG_5065 : STD_LOGIC;
signal a_10_XORF_5133 : STD_LOGIC;
signal a_10_CYINIT_5132 : STD_LOGIC;
signal a_10_CY0F_5131 : STD_LOGIC;
signal a_10_XORG_5122 : STD_LOGIC;
signal Madd_a_cy_10_Q : STD_LOGIC;
signal a_10_CYSELF_5120 : STD_LOGIC;
signal a_10_CYMUXFAST_5119 : STD_LOGIC;
signal a_10_CYAND_5118 : STD_LOGIC;
signal a_10_FASTCARRY_5117 : STD_LOGIC;
signal a_10_CYMUXG2_5116 : STD_LOGIC;
signal a_10_CYMUXF2_5115 : STD_LOGIC;
signal a_10_CY0G_5114 : STD_LOGIC;
signal a_10_CYSELG_5108 : STD_LOGIC;
signal a_12_XORF_5176 : STD_LOGIC;
signal a_12_CYINIT_5175 : STD_LOGIC;
signal a_12_CY0F_5174 : STD_LOGIC;
signal a_12_XORG_5165 : STD_LOGIC;
signal Madd_a_cy_12_Q : STD_LOGIC;
signal a_12_CYSELF_5163 : STD_LOGIC;
signal a_12_CYMUXFAST_5162 : STD_LOGIC;
signal a_12_CYAND_5161 : STD_LOGIC;
signal a_12_FASTCARRY_5160 : STD_LOGIC;
signal a_12_CYMUXG2_5159 : STD_LOGIC;
signal a_12_CYMUXF2_5158 : STD_LOGIC;
signal a_12_CY0G_5157 : STD_LOGIC;
signal a_12_CYSELG_5151 : STD_LOGIC;
signal a_14_XORF_5219 : STD_LOGIC;
signal a_14_CYINIT_5218 : STD_LOGIC;
signal a_14_CY0F_5217 : STD_LOGIC;
signal a_14_XORG_5208 : STD_LOGIC;
signal Madd_a_cy_14_Q : STD_LOGIC;
signal a_14_CYSELF_5206 : STD_LOGIC;
signal a_14_CYMUXFAST_5205 : STD_LOGIC;
signal a_14_CYAND_5204 : STD_LOGIC;
signal a_14_FASTCARRY_5203 : STD_LOGIC;
signal a_14_CYMUXG2_5202 : STD_LOGIC;
signal a_14_CYMUXF2_5201 : STD_LOGIC;
signal a_14_CY0G_5200 : STD_LOGIC;
signal a_14_CYSELG_5194 : STD_LOGIC;
signal a_16_XORF_5262 : STD_LOGIC;
signal a_16_CYINIT_5261 : STD_LOGIC;
signal a_16_CY0F_5260 : STD_LOGIC;
signal a_16_XORG_5251 : STD_LOGIC;
signal Madd_a_cy_16_Q : STD_LOGIC;
signal a_16_CYSELF_5249 : STD_LOGIC;
signal a_16_CYMUXFAST_5248 : STD_LOGIC;
signal a_16_CYAND_5247 : STD_LOGIC;
signal a_16_FASTCARRY_5246 : STD_LOGIC;
signal a_16_CYMUXG2_5245 : STD_LOGIC;
signal a_16_CYMUXF2_5244 : STD_LOGIC;
signal a_16_CY0G_5243 : STD_LOGIC;
signal a_16_CYSELG_5237 : STD_LOGIC;
signal a_18_XORF_5305 : STD_LOGIC;
signal a_18_CYINIT_5304 : STD_LOGIC;
signal a_18_CY0F_5303 : STD_LOGIC;
signal a_18_XORG_5294 : STD_LOGIC;
signal Madd_a_cy_18_Q : STD_LOGIC;
signal a_18_CYSELF_5292 : STD_LOGIC;
signal a_18_CYMUXFAST_5291 : STD_LOGIC;
signal a_18_CYAND_5290 : STD_LOGIC;
signal a_18_FASTCARRY_5289 : STD_LOGIC;
signal a_18_CYMUXG2_5288 : STD_LOGIC;
signal a_18_CYMUXF2_5287 : STD_LOGIC;
signal a_18_CY0G_5286 : STD_LOGIC;
signal a_18_CYSELG_5280 : STD_LOGIC;
signal a_20_XORF_5346 : STD_LOGIC;
signal a_20_CYINIT_5345 : STD_LOGIC;
signal a_20_CY0F_5344 : STD_LOGIC;
signal a_20_XORG_5336 : STD_LOGIC;
signal Madd_a_cy_20_Q : STD_LOGIC;
signal a_20_CYSELF_5334 : STD_LOGIC;
signal a_20_CYMUXFAST_5333 : STD_LOGIC;
signal a_20_CYAND_5332 : STD_LOGIC;
signal a_20_FASTCARRY_5331 : STD_LOGIC;
signal a_20_CYMUXG2_5330 : STD_LOGIC;
signal a_20_CYMUXF2_5329 : STD_LOGIC;
signal a_20_CY0G_5328 : STD_LOGIC;
signal a_20_CYSELG_5322 : STD_LOGIC;
signal a_22_XORF_5389 : STD_LOGIC;
signal a_22_CYINIT_5388 : STD_LOGIC;
signal a_22_CY0F_5387 : STD_LOGIC;
signal a_22_XORG_5378 : STD_LOGIC;
signal Madd_a_cy_22_Q : STD_LOGIC;
signal a_22_CYSELF_5376 : STD_LOGIC;
signal a_22_CYMUXFAST_5375 : STD_LOGIC;
signal a_22_CYAND_5374 : STD_LOGIC;
signal a_22_FASTCARRY_5373 : STD_LOGIC;
signal a_22_CYMUXG2_5372 : STD_LOGIC;
signal a_22_CYMUXF2_5371 : STD_LOGIC;
signal a_22_CY0G_5370 : STD_LOGIC;
signal a_22_CYSELG_5364 : STD_LOGIC;
signal a_24_XORF_5432 : STD_LOGIC;
signal a_24_CYINIT_5431 : STD_LOGIC;
signal a_24_CY0F_5430 : STD_LOGIC;
signal a_24_XORG_5421 : STD_LOGIC;
signal Madd_a_cy_24_Q : STD_LOGIC;
signal a_24_CYSELF_5419 : STD_LOGIC;
signal a_24_CYMUXFAST_5418 : STD_LOGIC;
signal a_24_CYAND_5417 : STD_LOGIC;
signal a_24_FASTCARRY_5416 : STD_LOGIC;
signal a_24_CYMUXG2_5415 : STD_LOGIC;
signal a_24_CYMUXF2_5414 : STD_LOGIC;
signal a_24_CY0G_5413 : STD_LOGIC;
signal a_24_CYSELG_5407 : STD_LOGIC;
signal a_26_XORF_5475 : STD_LOGIC;
signal a_26_CYINIT_5474 : STD_LOGIC;
signal a_26_CY0F_5473 : STD_LOGIC;
signal a_26_XORG_5464 : STD_LOGIC;
signal Madd_a_cy_26_Q : STD_LOGIC;
signal a_26_CYSELF_5462 : STD_LOGIC;
signal a_26_CYMUXFAST_5461 : STD_LOGIC;
signal a_26_CYAND_5460 : STD_LOGIC;
signal a_26_FASTCARRY_5459 : STD_LOGIC;
signal a_26_CYMUXG2_5458 : STD_LOGIC;
signal a_26_CYMUXF2_5457 : STD_LOGIC;
signal a_26_CY0G_5456 : STD_LOGIC;
signal a_26_CYSELG_5450 : STD_LOGIC;
signal a_28_XORF_5518 : STD_LOGIC;
signal a_28_CYINIT_5517 : STD_LOGIC;
signal a_28_CY0F_5516 : STD_LOGIC;
signal a_28_XORG_5507 : STD_LOGIC;
signal Madd_a_cy_28_Q : STD_LOGIC;
signal a_28_CYSELF_5505 : STD_LOGIC;
signal a_28_CYMUXFAST_5504 : STD_LOGIC;
signal a_28_CYAND_5503 : STD_LOGIC;
signal a_28_FASTCARRY_5502 : STD_LOGIC;
signal a_28_CYMUXG2_5501 : STD_LOGIC;
signal a_28_CYMUXF2_5500 : STD_LOGIC;
signal a_28_CY0G_5499 : STD_LOGIC;
signal a_28_CYSELG_5493 : STD_LOGIC;
signal a_30_XORF_5551 : STD_LOGIC;
signal a_30_CYINIT_5550 : STD_LOGIC;
signal a_30_CY0F_5549 : STD_LOGIC;
signal a_30_CYSELF_5543 : STD_LOGIC;
signal a_30_XORG_5539 : STD_LOGIC;
signal Madd_a_cy_30_Q : STD_LOGIC;
signal b_0_XORF_5589 : STD_LOGIC;
signal b_0_CYINIT_5588 : STD_LOGIC;
signal b_0_CY0F_5587 : STD_LOGIC;
signal b_0_CYSELF_5579 : STD_LOGIC;
signal b_0_BXINV_5577 : STD_LOGIC;
signal b_0_XORG_5575 : STD_LOGIC;
signal b_0_CYMUXG_5574 : STD_LOGIC;
signal Madd_b_cy_0_Q : STD_LOGIC;
signal b_0_CY0G_5572 : STD_LOGIC;
signal b_0_CYSELG_5566 : STD_LOGIC;
signal b_2_XORF_5628 : STD_LOGIC;
signal b_2_CYINIT_5627 : STD_LOGIC;
signal b_2_CY0F_5626 : STD_LOGIC;
signal b_2_XORG_5618 : STD_LOGIC;
signal Madd_b_cy_2_Q : STD_LOGIC;
signal b_2_CYSELF_5616 : STD_LOGIC;
signal b_2_CYMUXFAST_5615 : STD_LOGIC;
signal b_2_CYAND_5614 : STD_LOGIC;
signal b_2_FASTCARRY_5613 : STD_LOGIC;
signal b_2_CYMUXG2_5612 : STD_LOGIC;
signal b_2_CYMUXF2_5611 : STD_LOGIC;
signal b_2_CY0G_5610 : STD_LOGIC;
signal b_2_CYSELG_5604 : STD_LOGIC;
signal b_4_XORF_5669 : STD_LOGIC;
signal b_4_CYINIT_5668 : STD_LOGIC;
signal b_4_CY0F_5667 : STD_LOGIC;
signal b_4_XORG_5658 : STD_LOGIC;
signal Madd_b_cy_4_Q : STD_LOGIC;
signal b_4_CYSELF_5656 : STD_LOGIC;
signal b_4_CYMUXFAST_5655 : STD_LOGIC;
signal b_4_CYAND_5654 : STD_LOGIC;
signal b_4_FASTCARRY_5653 : STD_LOGIC;
signal b_4_CYMUXG2_5652 : STD_LOGIC;
signal b_4_CYMUXF2_5651 : STD_LOGIC;
signal b_4_CY0G_5650 : STD_LOGIC;
signal b_4_CYSELG_5644 : STD_LOGIC;
signal b_6_XORF_5712 : STD_LOGIC;
signal b_6_CYINIT_5711 : STD_LOGIC;
signal b_6_CY0F_5710 : STD_LOGIC;
signal b_6_XORG_5701 : STD_LOGIC;
signal Madd_b_cy_6_Q : STD_LOGIC;
signal b_6_CYSELF_5699 : STD_LOGIC;
signal b_6_CYMUXFAST_5698 : STD_LOGIC;
signal b_6_CYAND_5697 : STD_LOGIC;
signal b_6_FASTCARRY_5696 : STD_LOGIC;
signal b_6_CYMUXG2_5695 : STD_LOGIC;
signal b_6_CYMUXF2_5694 : STD_LOGIC;
signal b_6_CY0G_5693 : STD_LOGIC;
signal b_6_CYSELG_5687 : STD_LOGIC;
signal b_8_XORF_5755 : STD_LOGIC;
signal b_8_CYINIT_5754 : STD_LOGIC;
signal b_8_CY0F_5753 : STD_LOGIC;
signal b_8_XORG_5744 : STD_LOGIC;
signal Madd_b_cy_8_Q : STD_LOGIC;
signal b_8_CYSELF_5742 : STD_LOGIC;
signal b_8_CYMUXFAST_5741 : STD_LOGIC;
signal b_8_CYAND_5740 : STD_LOGIC;
signal b_8_FASTCARRY_5739 : STD_LOGIC;
signal b_8_CYMUXG2_5738 : STD_LOGIC;
signal b_8_CYMUXF2_5737 : STD_LOGIC;
signal b_8_CY0G_5736 : STD_LOGIC;
signal b_8_CYSELG_5730 : STD_LOGIC;
signal b_10_XORF_5798 : STD_LOGIC;
signal b_10_CYINIT_5797 : STD_LOGIC;
signal b_10_CY0F_5796 : STD_LOGIC;
signal b_10_XORG_5787 : STD_LOGIC;
signal Madd_b_cy_10_Q : STD_LOGIC;
signal b_10_CYSELF_5785 : STD_LOGIC;
signal b_10_CYMUXFAST_5784 : STD_LOGIC;
signal b_10_CYAND_5783 : STD_LOGIC;
signal b_10_FASTCARRY_5782 : STD_LOGIC;
signal b_10_CYMUXG2_5781 : STD_LOGIC;
signal b_10_CYMUXF2_5780 : STD_LOGIC;
signal b_10_CY0G_5779 : STD_LOGIC;
signal b_10_CYSELG_5773 : STD_LOGIC;
signal b_12_XORF_5841 : STD_LOGIC;
signal b_12_CYINIT_5840 : STD_LOGIC;
signal b_12_CY0F_5839 : STD_LOGIC;
signal b_12_XORG_5830 : STD_LOGIC;
signal Madd_b_cy_12_Q : STD_LOGIC;
signal b_12_CYSELF_5828 : STD_LOGIC;
signal b_12_CYMUXFAST_5827 : STD_LOGIC;
signal b_12_CYAND_5826 : STD_LOGIC;
signal b_12_FASTCARRY_5825 : STD_LOGIC;
signal b_12_CYMUXG2_5824 : STD_LOGIC;
signal b_12_CYMUXF2_5823 : STD_LOGIC;
signal b_12_CY0G_5822 : STD_LOGIC;
signal b_12_CYSELG_5816 : STD_LOGIC;
signal b_14_XORF_5882 : STD_LOGIC;
signal b_14_CYINIT_5881 : STD_LOGIC;
signal b_14_CY0F_5880 : STD_LOGIC;
signal b_14_XORG_5871 : STD_LOGIC;
signal Madd_b_cy_14_Q : STD_LOGIC;
signal b_14_CYSELF_5869 : STD_LOGIC;
signal b_14_CYMUXFAST_5868 : STD_LOGIC;
signal b_14_CYAND_5867 : STD_LOGIC;
signal b_14_FASTCARRY_5866 : STD_LOGIC;
signal b_14_CYMUXG2_5865 : STD_LOGIC;
signal b_14_CYMUXF2_5864 : STD_LOGIC;
signal b_14_CY0G_5863 : STD_LOGIC;
signal b_14_CYSELG_5857 : STD_LOGIC;
signal b_16_XORF_5925 : STD_LOGIC;
signal b_16_CYINIT_5924 : STD_LOGIC;
signal b_16_CY0F_5923 : STD_LOGIC;
signal b_16_XORG_5914 : STD_LOGIC;
signal Madd_b_cy_16_Q : STD_LOGIC;
signal b_16_CYSELF_5912 : STD_LOGIC;
signal b_16_CYMUXFAST_5911 : STD_LOGIC;
signal b_16_CYAND_5910 : STD_LOGIC;
signal b_16_FASTCARRY_5909 : STD_LOGIC;
signal b_16_CYMUXG2_5908 : STD_LOGIC;
signal b_16_CYMUXF2_5907 : STD_LOGIC;
signal b_16_CY0G_5906 : STD_LOGIC;
signal b_16_CYSELG_5900 : STD_LOGIC;
signal b_18_XORF_5966 : STD_LOGIC;
signal b_18_CYINIT_5965 : STD_LOGIC;
signal b_18_CY0F_5964 : STD_LOGIC;
signal b_18_XORG_5956 : STD_LOGIC;
signal Madd_b_cy_18_Q : STD_LOGIC;
signal b_18_CYSELF_5954 : STD_LOGIC;
signal b_18_CYMUXFAST_5953 : STD_LOGIC;
signal b_18_CYAND_5952 : STD_LOGIC;
signal b_18_FASTCARRY_5951 : STD_LOGIC;
signal b_18_CYMUXG2_5950 : STD_LOGIC;
signal b_18_CYMUXF2_5949 : STD_LOGIC;
signal b_18_CY0G_5948 : STD_LOGIC;
signal b_18_CYSELG_5942 : STD_LOGIC;
signal b_20_XORF_6009 : STD_LOGIC;
signal b_20_CYINIT_6008 : STD_LOGIC;
signal b_20_CY0F_6007 : STD_LOGIC;
signal b_20_XORG_5998 : STD_LOGIC;
signal Madd_b_cy_20_Q : STD_LOGIC;
signal b_20_CYSELF_5996 : STD_LOGIC;
signal b_20_CYMUXFAST_5995 : STD_LOGIC;
signal b_20_CYAND_5994 : STD_LOGIC;
signal b_20_FASTCARRY_5993 : STD_LOGIC;
signal b_20_CYMUXG2_5992 : STD_LOGIC;
signal b_20_CYMUXF2_5991 : STD_LOGIC;
signal b_20_CY0G_5990 : STD_LOGIC;
signal b_20_CYSELG_5984 : STD_LOGIC;
signal b_22_XORF_6052 : STD_LOGIC;
signal b_22_CYINIT_6051 : STD_LOGIC;
signal b_22_CY0F_6050 : STD_LOGIC;
signal b_22_XORG_6041 : STD_LOGIC;
signal Madd_b_cy_22_Q : STD_LOGIC;
signal b_22_CYSELF_6039 : STD_LOGIC;
signal b_22_CYMUXFAST_6038 : STD_LOGIC;
signal b_22_CYAND_6037 : STD_LOGIC;
signal b_22_FASTCARRY_6036 : STD_LOGIC;
signal b_22_CYMUXG2_6035 : STD_LOGIC;
signal b_22_CYMUXF2_6034 : STD_LOGIC;
signal b_22_CY0G_6033 : STD_LOGIC;
signal b_22_CYSELG_6027 : STD_LOGIC;
signal b_24_XORF_6093 : STD_LOGIC;
signal b_24_CYINIT_6092 : STD_LOGIC;
signal b_24_CY0F_6091 : STD_LOGIC;
signal b_24_XORG_6082 : STD_LOGIC;
signal Madd_b_cy_24_Q : STD_LOGIC;
signal b_24_CYSELF_6080 : STD_LOGIC;
signal b_24_CYMUXFAST_6079 : STD_LOGIC;
signal b_24_CYAND_6078 : STD_LOGIC;
signal b_24_FASTCARRY_6077 : STD_LOGIC;
signal b_24_CYMUXG2_6076 : STD_LOGIC;
signal b_24_CYMUXF2_6075 : STD_LOGIC;
signal b_24_CY0G_6074 : STD_LOGIC;
signal b_24_CYSELG_6068 : STD_LOGIC;
signal b_26_XORF_6136 : STD_LOGIC;
signal b_26_CYINIT_6135 : STD_LOGIC;
signal b_26_CY0F_6134 : STD_LOGIC;
signal b_26_XORG_6125 : STD_LOGIC;
signal Madd_b_cy_26_Q : STD_LOGIC;
signal b_26_CYSELF_6123 : STD_LOGIC;
signal b_26_CYMUXFAST_6122 : STD_LOGIC;
signal b_26_CYAND_6121 : STD_LOGIC;
signal b_26_FASTCARRY_6120 : STD_LOGIC;
signal b_26_CYMUXG2_6119 : STD_LOGIC;
signal b_26_CYMUXF2_6118 : STD_LOGIC;
signal b_26_CY0G_6117 : STD_LOGIC;
signal b_26_CYSELG_6111 : STD_LOGIC;
signal b_28_XORF_6179 : STD_LOGIC;
signal b_28_CYINIT_6178 : STD_LOGIC;
signal b_28_CY0F_6177 : STD_LOGIC;
signal b_28_XORG_6168 : STD_LOGIC;
signal Madd_b_cy_28_Q : STD_LOGIC;
signal b_28_CYSELF_6166 : STD_LOGIC;
signal b_28_CYMUXFAST_6165 : STD_LOGIC;
signal b_28_CYAND_6164 : STD_LOGIC;
signal b_28_FASTCARRY_6163 : STD_LOGIC;
signal b_28_CYMUXG2_6162 : STD_LOGIC;
signal b_28_CYMUXF2_6161 : STD_LOGIC;
signal b_28_CY0G_6160 : STD_LOGIC;
signal b_28_CYSELG_6154 : STD_LOGIC;
signal b_30_XORF_6212 : STD_LOGIC;
signal b_30_CYINIT_6211 : STD_LOGIC;
signal b_30_CY0F_6210 : STD_LOGIC;
signal b_30_CYSELF_6204 : STD_LOGIC;
signal b_30_XORG_6200 : STD_LOGIC;
signal Madd_b_cy_30_Q : STD_LOGIC;
signal din_lower_0_INBUF : STD_LOGIC;
signal din_lower_1_INBUF : STD_LOGIC;
signal din_lower_2_INBUF : STD_LOGIC;
signal din_lower_3_INBUF : STD_LOGIC;
signal din_lower_4_INBUF : STD_LOGIC;
signal din_lower_5_INBUF : STD_LOGIC;
signal din_lower_6_INBUF : STD_LOGIC;
signal din_lower_7_INBUF : STD_LOGIC;
signal clr_INBUF : STD_LOGIC;
signal AN_0_O : STD_LOGIC;
signal AN_1_O : STD_LOGIC;
signal AN_2_O : STD_LOGIC;
signal AN_3_O : STD_LOGIC;
signal segment_a_i_O : STD_LOGIC;
signal segment_b_i_O : STD_LOGIC;
signal segment_c_i_O : STD_LOGIC;
signal segment_d_i_O : STD_LOGIC;
signal segment_e_i_O : STD_LOGIC;
signal segment_f_i_O : STD_LOGIC;
signal segment_g_i_O : STD_LOGIC;
signal clk_25_INBUF : STD_LOGIC;
signal di_vld_INBUF : STD_LOGIC;
signal do_rdy_O : STD_LOGIC;
signal swtch_led_0_O : STD_LOGIC;
signal swtch_led_1_O : STD_LOGIC;
signal swtch_led_2_O : STD_LOGIC;
signal swtch_led_3_O : STD_LOGIC;
signal swtch_led_4_O : STD_LOGIC;
signal swtch_led_5_O : STD_LOGIC;
signal swtch_led_6_O : STD_LOGIC;
signal swtch_led_7_O : STD_LOGIC;
signal clk_25_BUFGP_BUFG_S_INVNOT : STD_LOGIC;
signal clk_25_BUFGP_BUFG_I0_INV : STD_LOGIC;
signal Sh13120_F5MUX_6468 : STD_LOGIC;
signal N403 : STD_LOGIC;
signal Sh13120_BXINV_6460 : STD_LOGIC;
signal N402 : STD_LOGIC;
signal Sh133_F5MUX_6493 : STD_LOGIC;
signal N527 : STD_LOGIC;
signal Sh133_BXINV_6485 : STD_LOGIC;
signal N526 : STD_LOGIC;
signal Sh140_F5MUX_6518 : STD_LOGIC;
signal N407 : STD_LOGIC;
signal Sh140_BXINV_6510 : STD_LOGIC;
signal N406 : STD_LOGIC;
signal Sh141_F5MUX_6543 : STD_LOGIC;
signal N409 : STD_LOGIC;
signal Sh141_BXINV_6535 : STD_LOGIC;
signal N408 : STD_LOGIC;
signal Sh142_F5MUX_6568 : STD_LOGIC;
signal N315 : STD_LOGIC;
signal Sh142_BXINV_6560 : STD_LOGIC;
signal N314 : STD_LOGIC;
signal Sh135_F5MUX_6593 : STD_LOGIC;
signal N303 : STD_LOGIC;
signal Sh135_BXINV_6585 : STD_LOGIC;
signal N302 : STD_LOGIC;
signal Sh14612_F5MUX_6618 : STD_LOGIC;
signal N415 : STD_LOGIC;
signal Sh14612_BXINV_6611 : STD_LOGIC;
signal N414 : STD_LOGIC;
signal Sh136_F5MUX_6643 : STD_LOGIC;
signal N305 : STD_LOGIC;
signal Sh136_BXINV_6635 : STD_LOGIC;
signal N304 : STD_LOGIC;
signal Sh14712_F5MUX_6668 : STD_LOGIC;
signal N413 : STD_LOGIC;
signal Sh14712_BXINV_6661 : STD_LOGIC;
signal N412 : STD_LOGIC;
signal Sh137_F5MUX_6693 : STD_LOGIC;
signal N307 : STD_LOGIC;
signal Sh137_BXINV_6685 : STD_LOGIC;
signal N306 : STD_LOGIC;
signal Sh139_F5MUX_6718 : STD_LOGIC;
signal N299 : STD_LOGIC;
signal Sh139_BXINV_6710 : STD_LOGIC;
signal N298 : STD_LOGIC;
signal b_reg_10_FFX_RST : STD_LOGIC;
signal b_reg_10_DXMUX_6749 : STD_LOGIC;
signal b_reg_10_F5MUX_6747 : STD_LOGIC;
signal N529 : STD_LOGIC;
signal b_reg_10_BXINV_6740 : STD_LOGIC;
signal N528 : STD_LOGIC;
signal b_reg_10_CLKINV_6731 : STD_LOGIC;
signal Sh10_F5MUX_6779 : STD_LOGIC;
signal N471 : STD_LOGIC;
signal Sh10_BXINV_6772 : STD_LOGIC;
signal N470 : STD_LOGIC;
signal Sh13_F5MUX_6804 : STD_LOGIC;
signal N495 : STD_LOGIC;
signal Sh13_BXINV_6797 : STD_LOGIC;
signal N494 : STD_LOGIC;
signal Sh21_F5MUX_6829 : STD_LOGIC;
signal N491 : STD_LOGIC;
signal Sh21_BXINV_6822 : STD_LOGIC;
signal N490 : STD_LOGIC;
signal Sh14_F5MUX_6854 : STD_LOGIC;
signal N487 : STD_LOGIC;
signal Sh14_BXINV_6847 : STD_LOGIC;
signal N486 : STD_LOGIC;
signal Sh22_F5MUX_6879 : STD_LOGIC;
signal N483 : STD_LOGIC;
signal Sh22_BXINV_6872 : STD_LOGIC;
signal N482 : STD_LOGIC;
signal Sh30_F5MUX_6904 : STD_LOGIC;
signal N473 : STD_LOGIC;
signal Sh30_BXINV_6897 : STD_LOGIC;
signal N472 : STD_LOGIC;
signal Sh17_F5MUX_6929 : STD_LOGIC;
signal N493 : STD_LOGIC;
signal Sh17_BXINV_6922 : STD_LOGIC;
signal N492 : STD_LOGIC;
signal Sh25_F5MUX_6954 : STD_LOGIC;
signal N489 : STD_LOGIC;
signal Sh25_BXINV_6947 : STD_LOGIC;
signal N488 : STD_LOGIC;
signal Sh18_F5MUX_6979 : STD_LOGIC;
signal N485 : STD_LOGIC;
signal Sh18_BXINV_6972 : STD_LOGIC;
signal N484 : STD_LOGIC;
signal Sh26_F5MUX_7004 : STD_LOGIC;
signal N481 : STD_LOGIC;
signal Sh26_BXINV_6997 : STD_LOGIC;
signal N480 : STD_LOGIC;
signal Sh29_F5MUX_7029 : STD_LOGIC;
signal N479 : STD_LOGIC;
signal Sh29_BXINV_7022 : STD_LOGIC;
signal N478 : STD_LOGIC;
signal Sh4_F5MUX_7054 : STD_LOGIC;
signal N301 : STD_LOGIC;
signal Sh4_BXINV_7047 : STD_LOGIC;
signal N300 : STD_LOGIC;
signal Sh8_F5MUX_7079 : STD_LOGIC;
signal N325 : STD_LOGIC;
signal Sh8_BXINV_7072 : STD_LOGIC;
signal N324 : STD_LOGIC;
signal Sh96_F5MUX_7106 : STD_LOGIC;
signal Sh1262_rt_7104 : STD_LOGIC;
signal Sh96_BXINV_7096 : STD_LOGIC;
signal Sh962 : STD_LOGIC;
signal Sh97_F5MUX_7131 : STD_LOGIC;
signal Sh1272_rt_7129 : STD_LOGIC;
signal Sh97_BXINV_7121 : STD_LOGIC;
signal Sh972_7119 : STD_LOGIC;
signal Sh100_F5MUX_7158 : STD_LOGIC;
signal Sh1001_7156 : STD_LOGIC;
signal Sh100_BXINV_7151 : STD_LOGIC;
signal Sh1002 : STD_LOGIC;
signal Sh101_F5MUX_7185 : STD_LOGIC;
signal Sh1011_rt_7183 : STD_LOGIC;
signal Sh101_BXINV_7175 : STD_LOGIC;
signal Sh1012 : STD_LOGIC;
signal Sh120_F5MUX_7212 : STD_LOGIC;
signal Sh1182_rt_7210 : STD_LOGIC;
signal Sh120_BXINV_7202 : STD_LOGIC;
signal Sh1202 : STD_LOGIC;
signal Sh112_F5MUX_7239 : STD_LOGIC;
signal Sh1102_rt_7237 : STD_LOGIC;
signal Sh112_BXINV_7229 : STD_LOGIC;
signal Sh1122 : STD_LOGIC;
signal Sh104_F5MUX_7266 : STD_LOGIC;
signal Sh1022_rt_7264 : STD_LOGIC;
signal Sh104_BXINV_7256 : STD_LOGIC;
signal Sh1042 : STD_LOGIC;
signal Sh121_F5MUX_7293 : STD_LOGIC;
signal Sh1192_rt_7291 : STD_LOGIC;
signal Sh121_BXINV_7283 : STD_LOGIC;
signal Sh1212 : STD_LOGIC;
signal Sh113_F5MUX_7320 : STD_LOGIC;
signal Sh1112_rt_7318 : STD_LOGIC;
signal Sh113_BXINV_7310 : STD_LOGIC;
signal Sh1132 : STD_LOGIC;
signal Sh105_F5MUX_7347 : STD_LOGIC;
signal Sh1032_rt_7345 : STD_LOGIC;
signal Sh105_BXINV_7337 : STD_LOGIC;
signal Sh1052 : STD_LOGIC;
signal Sh124_F5MUX_7374 : STD_LOGIC;
signal Sh1222_rt_7372 : STD_LOGIC;
signal Sh124_BXINV_7364 : STD_LOGIC;
signal Sh1242 : STD_LOGIC;
signal Sh116_F5MUX_7401 : STD_LOGIC;
signal Sh1142_rt_7399 : STD_LOGIC;
signal Sh116_BXINV_7391 : STD_LOGIC;
signal Sh1162 : STD_LOGIC;
signal Sh108_F5MUX_7428 : STD_LOGIC;
signal Sh1062_rt_7426 : STD_LOGIC;
signal Sh108_BXINV_7418 : STD_LOGIC;
signal Sh1082 : STD_LOGIC;
signal Sh125_F5MUX_7455 : STD_LOGIC;
signal Sh1232_rt_7453 : STD_LOGIC;
signal Sh125_BXINV_7445 : STD_LOGIC;
signal Sh1252 : STD_LOGIC;
signal Sh117_F5MUX_7482 : STD_LOGIC;
signal Sh1152_rt_7480 : STD_LOGIC;
signal Sh117_BXINV_7472 : STD_LOGIC;
signal Sh1172 : STD_LOGIC;
signal Sh109_F5MUX_7509 : STD_LOGIC;
signal Sh1072_rt_7507 : STD_LOGIC;
signal Sh109_BXINV_7499 : STD_LOGIC;
signal Sh1092 : STD_LOGIC;
signal Sh3_F5MUX_7534 : STD_LOGIC;
signal N309 : STD_LOGIC;
signal Sh3_BXINV_7526 : STD_LOGIC;
signal N308 : STD_LOGIC;
signal Sh7_F5MUX_7559 : STD_LOGIC;
signal N337 : STD_LOGIC;
signal Sh7_BXINV_7552 : STD_LOGIC;
signal N336 : STD_LOGIC;
signal Sh11_F5MUX_7584 : STD_LOGIC;
signal N349 : STD_LOGIC;
signal Sh11_BXINV_7577 : STD_LOGIC;
signal N348 : STD_LOGIC;
signal Sh15_F5MUX_7609 : STD_LOGIC;
signal N347 : STD_LOGIC;
signal Sh15_BXINV_7602 : STD_LOGIC;
signal N346 : STD_LOGIC;
signal Sh23_F5MUX_7634 : STD_LOGIC;
signal N343 : STD_LOGIC;
signal Sh23_BXINV_7627 : STD_LOGIC;
signal N342 : STD_LOGIC;
signal Sh31_F5MUX_7659 : STD_LOGIC;
signal N339 : STD_LOGIC;
signal Sh31_BXINV_7652 : STD_LOGIC;
signal N338 : STD_LOGIC;
signal Sh19_F5MUX_7684 : STD_LOGIC;
signal N345 : STD_LOGIC;
signal Sh19_BXINV_7677 : STD_LOGIC;
signal N344 : STD_LOGIC;
signal Sh27_F5MUX_7709 : STD_LOGIC;
signal N341 : STD_LOGIC;
signal Sh27_BXINV_7702 : STD_LOGIC;
signal N340 : STD_LOGIC;
signal Sh12_F5MUX_7734 : STD_LOGIC;
signal N335 : STD_LOGIC;
signal Sh12_BXINV_7727 : STD_LOGIC;
signal N334 : STD_LOGIC;
signal Sh20_F5MUX_7759 : STD_LOGIC;
signal N331 : STD_LOGIC;
signal Sh20_BXINV_7752 : STD_LOGIC;
signal N330 : STD_LOGIC;
signal Sh16_F5MUX_7784 : STD_LOGIC;
signal N333 : STD_LOGIC;
signal Sh16_BXINV_7777 : STD_LOGIC;
signal N332 : STD_LOGIC;
signal Sh24_F5MUX_7809 : STD_LOGIC;
signal N329 : STD_LOGIC;
signal Sh24_BXINV_7802 : STD_LOGIC;
signal N328 : STD_LOGIC;
signal Sh28_F5MUX_7834 : STD_LOGIC;
signal N327 : STD_LOGIC;
signal Sh28_BXINV_7827 : STD_LOGIC;
signal N326 : STD_LOGIC;
signal Sh123_F5MUX_7859 : STD_LOGIC;
signal N497 : STD_LOGIC;
signal Sh123_BXINV_7852 : STD_LOGIC;
signal N496 : STD_LOGIC;
signal Sh127_F5MUX_7884 : STD_LOGIC;
signal N461 : STD_LOGIC;
signal Sh127_BXINV_7877 : STD_LOGIC;
signal N460 : STD_LOGIC;
signal Sh145_F5MUX_7909 : STD_LOGIC;
signal Sh14531 : STD_LOGIC;
signal Sh145_BXINV_7901 : STD_LOGIC;
signal Sh145311_7899 : STD_LOGIC;
signal Sh_F5MUX_7934 : STD_LOGIC;
signal N411 : STD_LOGIC;
signal Sh_BXINV_7927 : STD_LOGIC;
signal N410 : STD_LOGIC;
signal N291_F5MUX_7959 : STD_LOGIC;
signal N465 : STD_LOGIC;
signal N291_BXINV_7950 : STD_LOGIC;
signal N464 : STD_LOGIC;
signal N292_F5MUX_7984 : STD_LOGIC;
signal N467 : STD_LOGIC;
signal N292_BXINV_7975 : STD_LOGIC;
signal N466 : STD_LOGIC;
signal N281_F5MUX_8009 : STD_LOGIC;
signal N457 : STD_LOGIC;
signal N281_BXINV_8000 : STD_LOGIC;
signal N456 : STD_LOGIC;
signal N282_F5MUX_8034 : STD_LOGIC;
signal N459 : STD_LOGIC;
signal N282_BXINV_8025 : STD_LOGIC;
signal N458 : STD_LOGIC;
signal N278_F5MUX_8059 : STD_LOGIC;
signal N453 : STD_LOGIC;
signal N278_BXINV_8050 : STD_LOGIC;
signal N452 : STD_LOGIC;
signal N279_F5MUX_8084 : STD_LOGIC;
signal N455 : STD_LOGIC;
signal N279_BXINV_8075 : STD_LOGIC;
signal N454 : STD_LOGIC;
signal Sh1307_F5MUX_8109 : STD_LOGIC;
signal N371 : STD_LOGIC;
signal Sh1307_BXINV_8101 : STD_LOGIC;
signal N370 : STD_LOGIC;
signal Sh160_F5MUX_8134 : STD_LOGIC;
signal N319 : STD_LOGIC;
signal Sh160_BXINV_8127 : STD_LOGIC;
signal N318 : STD_LOGIC;
signal Sh1507_F5MUX_8159 : STD_LOGIC;
signal N435 : STD_LOGIC;
signal Sh1507_BXINV_8151 : STD_LOGIC;
signal N434 : STD_LOGIC;
signal Sh13820_F5MUX_8184 : STD_LOGIC;
signal N417 : STD_LOGIC;
signal Sh13820_BXINV_8176 : STD_LOGIC;
signal N416 : STD_LOGIC;
signal Sh1517_F5MUX_8209 : STD_LOGIC;
signal N433 : STD_LOGIC;
signal Sh1517_BXINV_8201 : STD_LOGIC;
signal N432 : STD_LOGIC;
signal Sh162_F5MUX_8234 : STD_LOGIC;
signal N317 : STD_LOGIC;
signal Sh162_BXINV_8227 : STD_LOGIC;
signal N316 : STD_LOGIC;
signal Sh40_F5MUX_8259 : STD_LOGIC;
signal N369 : STD_LOGIC;
signal Sh40_BXINV_8251 : STD_LOGIC;
signal N368 : STD_LOGIC;
signal Sh32_F5MUX_8284 : STD_LOGIC;
signal N353 : STD_LOGIC;
signal Sh32_BXINV_8276 : STD_LOGIC;
signal N352 : STD_LOGIC;
signal Sh163_F5MUX_8309 : STD_LOGIC;
signal N311 : STD_LOGIC;
signal Sh163_BXINV_8302 : STD_LOGIC;
signal N310 : STD_LOGIC;
signal Sh164_F5MUX_8334 : STD_LOGIC;
signal N313 : STD_LOGIC;
signal Sh164_BXINV_8327 : STD_LOGIC;
signal N312 : STD_LOGIC;
signal Sh41_F5MUX_8359 : STD_LOGIC;
signal N425 : STD_LOGIC;
signal Sh41_BXINV_8351 : STD_LOGIC;
signal N424 : STD_LOGIC;
signal Sh1547_F5MUX_8384 : STD_LOGIC;
signal N421 : STD_LOGIC;
signal Sh1547_BXINV_8376 : STD_LOGIC;
signal N420 : STD_LOGIC;
signal Sh13420_F5MUX_8409 : STD_LOGIC;
signal N401 : STD_LOGIC;
signal Sh13420_BXINV_8401 : STD_LOGIC;
signal N400 : STD_LOGIC;
signal Sh33_F5MUX_8434 : STD_LOGIC;
signal N375 : STD_LOGIC;
signal Sh33_BXINV_8426 : STD_LOGIC;
signal N374 : STD_LOGIC;
signal Sh1557_F5MUX_8459 : STD_LOGIC;
signal N419 : STD_LOGIC;
signal Sh1557_BXINV_8451 : STD_LOGIC;
signal N418 : STD_LOGIC;
signal Sh42_F5MUX_8484 : STD_LOGIC;
signal N429 : STD_LOGIC;
signal Sh42_BXINV_8476 : STD_LOGIC;
signal N428 : STD_LOGIC;
signal Sh34_F5MUX_8509 : STD_LOGIC;
signal N379 : STD_LOGIC;
signal Sh34_BXINV_8501 : STD_LOGIC;
signal N378 : STD_LOGIC;
signal Sh50_F5MUX_8534 : STD_LOGIC;
signal N377 : STD_LOGIC;
signal Sh50_BXINV_8526 : STD_LOGIC;
signal N376 : STD_LOGIC;
signal Sh175_F5MUX_8559 : STD_LOGIC;
signal N321 : STD_LOGIC;
signal Sh175_BXINV_8552 : STD_LOGIC;
signal N320 : STD_LOGIC;
signal Sh1587_F5MUX_8584 : STD_LOGIC;
signal N427 : STD_LOGIC;
signal Sh1587_BXINV_8576 : STD_LOGIC;
signal N426 : STD_LOGIC;
signal Sh43_F5MUX_8609 : STD_LOGIC;
signal N383 : STD_LOGIC;
signal Sh43_BXINV_8601 : STD_LOGIC;
signal N382 : STD_LOGIC;
signal Sh35_F5MUX_8634 : STD_LOGIC;
signal N357 : STD_LOGIC;
signal Sh35_BXINV_8626 : STD_LOGIC;
signal N356 : STD_LOGIC;
signal Sh51_F5MUX_8659 : STD_LOGIC;
signal N355 : STD_LOGIC;
signal Sh51_BXINV_8651 : STD_LOGIC;
signal N354 : STD_LOGIC;
signal Sh1597_F5MUX_8684 : STD_LOGIC;
signal N469 : STD_LOGIC;
signal Sh1597_BXINV_8676 : STD_LOGIC;
signal N468 : STD_LOGIC;
signal Sh178_F5MUX_8709 : STD_LOGIC;
signal N323 : STD_LOGIC;
signal Sh178_BXINV_8702 : STD_LOGIC;
signal N322 : STD_LOGIC;
signal Sh44_F5MUX_8734 : STD_LOGIC;
signal N387 : STD_LOGIC;
signal Sh44_BXINV_8726 : STD_LOGIC;
signal N386 : STD_LOGIC;
signal Sh60_F5MUX_8759 : STD_LOGIC;
signal N385 : STD_LOGIC;
signal Sh60_BXINV_8751 : STD_LOGIC;
signal N384 : STD_LOGIC;
signal Sh36_F5MUX_8784 : STD_LOGIC;
signal N361 : STD_LOGIC;
signal Sh36_BXINV_8776 : STD_LOGIC;
signal N360 : STD_LOGIC;
signal Sh52_F5MUX_8809 : STD_LOGIC;
signal N359 : STD_LOGIC;
signal Sh52_BXINV_8801 : STD_LOGIC;
signal N358 : STD_LOGIC;
signal Sh45_F5MUX_8834 : STD_LOGIC;
signal N431 : STD_LOGIC;
signal Sh45_BXINV_8826 : STD_LOGIC;
signal N430 : STD_LOGIC;
signal Sh37_F5MUX_8859 : STD_LOGIC;
signal N391 : STD_LOGIC;
signal Sh37_BXINV_8851 : STD_LOGIC;
signal N390 : STD_LOGIC;
signal Sh53_F5MUX_8884 : STD_LOGIC;
signal N389 : STD_LOGIC;
signal Sh53_BXINV_8876 : STD_LOGIC;
signal N388 : STD_LOGIC;
signal Sh46_F5MUX_8909 : STD_LOGIC;
signal N423 : STD_LOGIC;
signal Sh46_BXINV_8901 : STD_LOGIC;
signal N422 : STD_LOGIC;
signal Sh38_F5MUX_8934 : STD_LOGIC;
signal N395 : STD_LOGIC;
signal Sh38_BXINV_8926 : STD_LOGIC;
signal N394 : STD_LOGIC;
signal Sh54_F5MUX_8959 : STD_LOGIC;
signal N393 : STD_LOGIC;
signal Sh54_BXINV_8951 : STD_LOGIC;
signal N392 : STD_LOGIC;
signal Sh47_F5MUX_8984 : STD_LOGIC;
signal N399 : STD_LOGIC;
signal Sh47_BXINV_8976 : STD_LOGIC;
signal N398 : STD_LOGIC;
signal Sh63_F5MUX_9009 : STD_LOGIC;
signal N397 : STD_LOGIC;
signal Sh63_BXINV_9001 : STD_LOGIC;
signal N396 : STD_LOGIC;
signal Sh39_F5MUX_9034 : STD_LOGIC;
signal N365 : STD_LOGIC;
signal Sh39_BXINV_9026 : STD_LOGIC;
signal N364 : STD_LOGIC;
signal Sh55_F5MUX_9059 : STD_LOGIC;
signal N363 : STD_LOGIC;
signal Sh55_BXINV_9051 : STD_LOGIC;
signal N362 : STD_LOGIC;
signal Sh56_F5MUX_9084 : STD_LOGIC;
signal N367 : STD_LOGIC;
signal Sh56_BXINV_9076 : STD_LOGIC;
signal N366 : STD_LOGIC;
signal Sh48_F5MUX_9109 : STD_LOGIC;
signal N351 : STD_LOGIC;
signal Sh48_BXINV_9101 : STD_LOGIC;
signal N350 : STD_LOGIC;
signal Sh49_F5MUX_9134 : STD_LOGIC;
signal N373 : STD_LOGIC;
signal Sh49_BXINV_9126 : STD_LOGIC;
signal N372 : STD_LOGIC;
signal Sh59_F5MUX_9159 : STD_LOGIC;
signal N381 : STD_LOGIC;
signal Sh59_BXINV_9151 : STD_LOGIC;
signal N380 : STD_LOGIC;
signal N275_F5MUX_9184 : STD_LOGIC;
signal N449 : STD_LOGIC;
signal N275_BXINV_9175 : STD_LOGIC;
signal N448 : STD_LOGIC;
signal N276_F5MUX_9209 : STD_LOGIC;
signal N451 : STD_LOGIC;
signal N276_BXINV_9200 : STD_LOGIC;
signal N450 : STD_LOGIC;
signal b_reg_8_DXMUX_9240 : STD_LOGIC;
signal b_reg_8_F5MUX_9238 : STD_LOGIC;
signal N533 : STD_LOGIC;
signal b_reg_8_BXINV_9231 : STD_LOGIC;
signal N532 : STD_LOGIC;
signal b_reg_8_CLKINV_9222 : STD_LOGIC;
signal b_reg_9_DXMUX_9276 : STD_LOGIC;
signal b_reg_9_F5MUX_9274 : STD_LOGIC;
signal N531 : STD_LOGIC;
signal b_reg_9_BXINV_9267 : STD_LOGIC;
signal N530 : STD_LOGIC;
signal b_reg_9_CLKINV_9258 : STD_LOGIC;
signal N272_F5MUX_9306 : STD_LOGIC;
signal N445 : STD_LOGIC;
signal N272_BXINV_9297 : STD_LOGIC;
signal N444 : STD_LOGIC;
signal N273_F5MUX_9331 : STD_LOGIC;
signal N447 : STD_LOGIC;
signal N273_BXINV_9322 : STD_LOGIC;
signal N446 : STD_LOGIC;
signal Sh1_F5MUX_9356 : STD_LOGIC;
signal N405 : STD_LOGIC;
signal Sh1_BXINV_9349 : STD_LOGIC;
signal N404 : STD_LOGIC;
signal Sh2_F5MUX_9381 : STD_LOGIC;
signal Sh210 : STD_LOGIC;
signal Sh2_BXINV_9374 : STD_LOGIC;
signal Sh211 : STD_LOGIC;
signal Sh5_F5MUX_9406 : STD_LOGIC;
signal N477 : STD_LOGIC;
signal Sh5_BXINV_9399 : STD_LOGIC;
signal N476 : STD_LOGIC;
signal N269_F5MUX_9431 : STD_LOGIC;
signal N441 : STD_LOGIC;
signal N269_BXINV_9422 : STD_LOGIC;
signal N440 : STD_LOGIC;
signal N270_F5MUX_9456 : STD_LOGIC;
signal N443 : STD_LOGIC;
signal N270_BXINV_9447 : STD_LOGIC;
signal N442 : STD_LOGIC;
signal Sh6_F5MUX_9481 : STD_LOGIC;
signal N463 : STD_LOGIC;
signal Sh6_BXINV_9474 : STD_LOGIC;
signal N462 : STD_LOGIC;
signal Sh9_F5MUX_9506 : STD_LOGIC;
signal N475 : STD_LOGIC;
signal Sh9_BXINV_9499 : STD_LOGIC;
signal N474 : STD_LOGIC;
signal b_reg_0_1_DXMUX_9538 : STD_LOGIC;
signal b_reg_0_1_FXMUX_9537 : STD_LOGIC;
signal b_reg_0_1_F5MUX_9536 : STD_LOGIC;
signal N525 : STD_LOGIC;
signal b_reg_0_1_BXINV_9529 : STD_LOGIC;
signal N524 : STD_LOGIC;
signal b_reg_0_1_CLKINV_9521 : STD_LOGIC;
signal hex_digit_i_0_DXMUX_9574 : STD_LOGIC;
signal hex_digit_i_0_F5MUX_9572 : STD_LOGIC;
signal Mmux_hex_digit_i_mux0001_3_9570 : STD_LOGIC;
signal hex_digit_i_0_BXINV_9564 : STD_LOGIC;
signal Mmux_hex_digit_i_mux0001_4_9562 : STD_LOGIC;
signal hex_digit_i_0_CLKINV_9555 : STD_LOGIC;
signal N266_F5MUX_9604 : STD_LOGIC;
signal N437 : STD_LOGIC;
signal N266_BXINV_9595 : STD_LOGIC;
signal N436 : STD_LOGIC;
signal N267_F5MUX_9629 : STD_LOGIC;
signal N439 : STD_LOGIC;
signal N267_BXINV_9620 : STD_LOGIC;
signal N438 : STD_LOGIC;
signal i_cnt_3_DXMUX_9660 : STD_LOGIC;
signal i_cnt_3_F5MUX_9658 : STD_LOGIC;
signal i_cnt_mux0001_0_56 : STD_LOGIC;
signal i_cnt_3_BXINV_9651 : STD_LOGIC;
signal i_cnt_mux0001_0_561_9649 : STD_LOGIC;
signal i_cnt_3_CLKINV_9642 : STD_LOGIC;
signal hex_digit_i_1_DXMUX_9696 : STD_LOGIC;
signal hex_digit_i_1_F5MUX_9694 : STD_LOGIC;
signal Mmux_hex_digit_i_mux0001_31_9692 : STD_LOGIC;
signal hex_digit_i_1_BXINV_9686 : STD_LOGIC;
signal Mmux_hex_digit_i_mux0001_41_9684 : STD_LOGIC;
signal hex_digit_i_1_CLKINV_9677 : STD_LOGIC;
signal hex_digit_i_2_DXMUX_9732 : STD_LOGIC;
signal hex_digit_i_2_F5MUX_9730 : STD_LOGIC;
signal Mmux_hex_digit_i_mux0001_32_9728 : STD_LOGIC;
signal hex_digit_i_2_BXINV_9722 : STD_LOGIC;
signal Mmux_hex_digit_i_mux0001_42_9720 : STD_LOGIC;
signal hex_digit_i_2_CLKINV_9713 : STD_LOGIC;
signal hex_digit_i_3_DXMUX_9768 : STD_LOGIC;
signal hex_digit_i_3_F5MUX_9766 : STD_LOGIC;
signal Mmux_hex_digit_i_mux0001_33_9764 : STD_LOGIC;
signal hex_digit_i_3_BXINV_9758 : STD_LOGIC;
signal Mmux_hex_digit_i_mux0001_43_9756 : STD_LOGIC;
signal hex_digit_i_3_CLKINV_9749 : STD_LOGIC;
signal Sh150 : STD_LOGIC;
signal Sh15016_O_pack_1 : STD_LOGIC;
signal Sh143 : STD_LOGIC;
signal Sh14316_pack_1 : STD_LOGIC;
signal Sh144 : STD_LOGIC;
signal Sh14416_pack_1 : STD_LOGIC;
signal Sh154 : STD_LOGIC;
signal Sh15416_O_pack_1 : STD_LOGIC;
signal Sh147 : STD_LOGIC;
signal Sh14713_pack_1 : STD_LOGIC;
signal Sh148 : STD_LOGIC;
signal Sh1487_pack_1 : STD_LOGIC;
signal Sh159 : STD_LOGIC;
signal Sh1313_pack_1 : STD_LOGIC;
signal Sh73 : STD_LOGIC;
signal Sh57_pack_1 : STD_LOGIC;
signal Sh74 : STD_LOGIC;
signal Sh58_pack_1 : STD_LOGIC;
signal Sh77 : STD_LOGIC;
signal Sh61_pack_1 : STD_LOGIC;
signal Sh78 : STD_LOGIC;
signal Sh62_pack_1 : STD_LOGIC;
signal N249 : STD_LOGIC;
signal Sh14716_pack_1 : STD_LOGIC;
signal Sh1022_10084 : STD_LOGIC;
signal Mxor_ba_xor_Result_5_1_SW1_O_pack_1 : STD_LOGIC;
signal Sh1102_10108 : STD_LOGIC;
signal Mxor_ba_xor_Result_13_1_SW1_O_pack_1 : STD_LOGIC;
signal Sh1032_10132 : STD_LOGIC;
signal Mxor_ba_xor_Result_7_1_SW1_O_pack_1 : STD_LOGIC;
signal Sh1112_10156 : STD_LOGIC;
signal Mxor_ba_xor_Result_15_1_SW1_O_pack_1 : STD_LOGIC;
signal Sh1062_10180 : STD_LOGIC;
signal Mxor_ba_xor_Result_9_1_SW1_O_pack_1 : STD_LOGIC;
signal Sh1142_10204 : STD_LOGIC;
signal Mxor_ba_xor_Result_17_1_SW1_O_pack_1 : STD_LOGIC;
signal Sh1222_10228 : STD_LOGIC;
signal Mxor_ba_xor_Result_25_1_SW1_O_pack_1 : STD_LOGIC;
signal Sh1072_10252 : STD_LOGIC;
signal Mxor_ba_xor_Result_11_1_SW1_O_pack_1 : STD_LOGIC;
signal Sh1152_10276 : STD_LOGIC;
signal Mxor_ba_xor_Result_19_1_SW1_O_pack_1 : STD_LOGIC;
signal Sh1232_10300 : STD_LOGIC;
signal N200_pack_1 : STD_LOGIC;
signal Sh1182_10324 : STD_LOGIC;
signal Mxor_ba_xor_Result_21_1_SW1_O_pack_1 : STD_LOGIC;
signal Sh1262_10348 : STD_LOGIC;
signal Mxor_ba_xor_Result_29_1_SW1_O_pack_1 : STD_LOGIC;
signal Sh13016 : STD_LOGIC;
signal Sh982_pack_1 : STD_LOGIC;
signal Sh1192_10396 : STD_LOGIC;
signal Mxor_ba_xor_Result_23_1_SW1_O_pack_1 : STD_LOGIC;
signal Sh1272_10420 : STD_LOGIC;
signal N197_pack_1 : STD_LOGIC;
signal Sh161 : STD_LOGIC;
signal Sh129_pack_1 : STD_LOGIC;
signal Sh170 : STD_LOGIC;
signal Sh138_pack_1 : STD_LOGIC;
signal Sh1437_10492 : STD_LOGIC;
signal Sh107_pack_1 : STD_LOGIC;
signal Sh171 : STD_LOGIC;
signal Sh155_pack_1 : STD_LOGIC;
signal Sh172 : STD_LOGIC;
signal Sh156_pack_1 : STD_LOGIC;
signal Sh180 : STD_LOGIC;
signal Sh132_pack_1 : STD_LOGIC;
signal Sh165 : STD_LOGIC;
signal Sh149_pack_1 : STD_LOGIC;
signal Sh173 : STD_LOGIC;
signal Sh157_pack_1 : STD_LOGIC;
signal Sh166 : STD_LOGIC;
signal Sh134_pack_1 : STD_LOGIC;
signal Sh174 : STD_LOGIC;
signal Sh158_pack_1 : STD_LOGIC;
signal Sh167 : STD_LOGIC;
signal Sh151_pack_1 : STD_LOGIC;
signal Sh168 : STD_LOGIC;
signal Sh152_pack_1 : STD_LOGIC;
signal Sh176 : STD_LOGIC;
signal Sh128_pack_1 : STD_LOGIC;
signal Sh169 : STD_LOGIC;
signal Sh153_pack_1 : STD_LOGIC;
signal Sh179 : STD_LOGIC;
signal Sh131_pack_1 : STD_LOGIC;
signal b_reg_2_1_DYMUX_10800 : STD_LOGIC;
signal b_reg_2_1_GYMUX_10799 : STD_LOGIC;
signal b_reg_mux0000_2_Q : STD_LOGIC;
signal b_reg_2_1_CLKINV_10790 : STD_LOGIC;
signal b_reg_3_1_DYMUX_10824 : STD_LOGIC;
signal b_reg_3_1_GYMUX_10823 : STD_LOGIC;
signal b_reg_mux0000_3_Q : STD_LOGIC;
signal b_reg_3_1_CLKINV_10814 : STD_LOGIC;
signal b_reg_4_1_DYMUX_10848 : STD_LOGIC;
signal b_reg_4_1_GYMUX_10847 : STD_LOGIC;
signal b_reg_mux0000_4_Q : STD_LOGIC;
signal b_reg_4_1_CLKINV_10838 : STD_LOGIC;
signal AN_1_DXMUX_10889 : STD_LOGIC;
signal Mrom_AN_mux00011 : STD_LOGIC;
signal AN_1_DYMUX_10874 : STD_LOGIC;
signal Mrom_AN_mux0001 : STD_LOGIC;
signal AN_1_SRINV_10864 : STD_LOGIC;
signal AN_1_CLKINV_10863 : STD_LOGIC;
signal AN_3_DXMUX_10929 : STD_LOGIC;
signal Mrom_AN_mux00013 : STD_LOGIC;
signal AN_3_DYMUX_10914 : STD_LOGIC;
signal Mrom_AN_mux00012 : STD_LOGIC;
signal AN_3_SRINV_10904 : STD_LOGIC;
signal AN_3_CLKINV_10903 : STD_LOGIC;
signal a_reg_1_DXMUX_10970 : STD_LOGIC;
signal a_reg_1_DYMUX_10956 : STD_LOGIC;
signal a_reg_1_SRINV_10948 : STD_LOGIC;
signal a_reg_1_CLKINV_10947 : STD_LOGIC;
signal a_reg_3_DXMUX_11012 : STD_LOGIC;
signal a_reg_3_DYMUX_10998 : STD_LOGIC;
signal a_reg_3_SRINV_10990 : STD_LOGIC;
signal a_reg_3_CLKINV_10989 : STD_LOGIC;
signal a_reg_5_DXMUX_11054 : STD_LOGIC;
signal a_reg_5_DYMUX_11040 : STD_LOGIC;
signal a_reg_5_SRINV_11032 : STD_LOGIC;
signal a_reg_5_CLKINV_11031 : STD_LOGIC;
signal a_reg_7_DXMUX_11096 : STD_LOGIC;
signal a_reg_7_DYMUX_11082 : STD_LOGIC;
signal a_reg_7_SRINV_11074 : STD_LOGIC;
signal a_reg_7_CLKINV_11073 : STD_LOGIC;
signal a_reg_9_DXMUX_11138 : STD_LOGIC;
signal a_reg_9_DYMUX_11124 : STD_LOGIC;
signal a_reg_9_SRINV_11116 : STD_LOGIC;
signal a_reg_9_CLKINV_11115 : STD_LOGIC;
signal b_reg_7_DXMUX_11180 : STD_LOGIC;
signal b_reg_mux0000_7_Q : STD_LOGIC;
signal b_reg_7_DYMUX_11165 : STD_LOGIC;
signal b_reg_mux0000_6_Q : STD_LOGIC;
signal b_reg_7_SRINV_11156 : STD_LOGIC;
signal b_reg_7_CLKINV_11155 : STD_LOGIC;
signal i_cnt_1_DXMUX_11221 : STD_LOGIC;
signal i_cnt_1_DYMUX_11208 : STD_LOGIC;
signal i_cnt_1_SRINV_11199 : STD_LOGIC;
signal i_cnt_1_CLKINV_11198 : STD_LOGIC;
signal a_reg_11_DXMUX_11263 : STD_LOGIC;
signal a_reg_11_DYMUX_11249 : STD_LOGIC;
signal a_reg_11_SRINV_11241 : STD_LOGIC;
signal a_reg_11_CLKINV_11240 : STD_LOGIC;
signal a_reg_21_FFY_RST : STD_LOGIC;
signal a_reg_21_FFX_RST : STD_LOGIC;
signal a_reg_21_DXMUX_11305 : STD_LOGIC;
signal a_reg_21_DYMUX_11291 : STD_LOGIC;
signal a_reg_21_SRINV_11283 : STD_LOGIC;
signal a_reg_21_CLKINV_11282 : STD_LOGIC;
signal a_reg_13_FFY_RST : STD_LOGIC;
signal a_reg_13_FFX_RST : STD_LOGIC;
signal a_reg_13_DXMUX_11347 : STD_LOGIC;
signal a_reg_13_DYMUX_11333 : STD_LOGIC;
signal a_reg_13_SRINV_11325 : STD_LOGIC;
signal a_reg_13_CLKINV_11324 : STD_LOGIC;
signal a_reg_31_FFY_RST : STD_LOGIC;
signal a_reg_31_FFX_RST : STD_LOGIC;
signal a_reg_31_DXMUX_11389 : STD_LOGIC;
signal a_reg_31_DYMUX_11375 : STD_LOGIC;
signal a_reg_31_SRINV_11367 : STD_LOGIC;
signal a_reg_31_CLKINV_11366 : STD_LOGIC;
signal a_reg_23_FFY_RST : STD_LOGIC;
signal a_reg_23_DXMUX_11431 : STD_LOGIC;
signal a_reg_23_DYMUX_11417 : STD_LOGIC;
signal a_reg_23_SRINV_11409 : STD_LOGIC;
signal a_reg_23_CLKINV_11408 : STD_LOGIC;
signal a_reg_15_DXMUX_11473 : STD_LOGIC;
signal a_reg_15_DYMUX_11459 : STD_LOGIC;
signal a_reg_15_SRINV_11451 : STD_LOGIC;
signal a_reg_15_CLKINV_11450 : STD_LOGIC;
signal a_reg_25_DXMUX_11515 : STD_LOGIC;
signal a_reg_25_DYMUX_11501 : STD_LOGIC;
signal a_reg_25_SRINV_11493 : STD_LOGIC;
signal a_reg_25_CLKINV_11492 : STD_LOGIC;
signal a_reg_17_DXMUX_11557 : STD_LOGIC;
signal a_reg_17_DYMUX_11543 : STD_LOGIC;
signal a_reg_17_SRINV_11535 : STD_LOGIC;
signal a_reg_17_CLKINV_11534 : STD_LOGIC;
signal a_reg_27_DXMUX_11599 : STD_LOGIC;
signal a_reg_27_DYMUX_11585 : STD_LOGIC;
signal a_reg_27_SRINV_11577 : STD_LOGIC;
signal a_reg_27_CLKINV_11576 : STD_LOGIC;
signal a_reg_19_DXMUX_11641 : STD_LOGIC;
signal a_reg_19_DYMUX_11627 : STD_LOGIC;
signal a_reg_19_SRINV_11619 : STD_LOGIC;
signal a_reg_19_CLKINV_11618 : STD_LOGIC;
signal a_reg_29_DXMUX_11683 : STD_LOGIC;
signal a_reg_29_DYMUX_11669 : STD_LOGIC;
signal a_reg_29_SRINV_11661 : STD_LOGIC;
signal a_reg_29_CLKINV_11660 : STD_LOGIC;
signal b_reg_11_DYMUX_11706 : STD_LOGIC;
signal b_reg_mux0000_11_Q : STD_LOGIC;
signal b_reg_11_CLKINV_11696 : STD_LOGIC;
signal b_reg_21_DXMUX_11748 : STD_LOGIC;
signal b_reg_mux0000_21_Q : STD_LOGIC;
signal b_reg_21_DYMUX_11734 : STD_LOGIC;
signal b_reg_mux0000_20_Q : STD_LOGIC;
signal b_reg_21_SRINV_11726 : STD_LOGIC;
signal b_reg_21_CLKINV_11725 : STD_LOGIC;
signal b_reg_13_DXMUX_11790 : STD_LOGIC;
signal b_reg_mux0000_13_Q : STD_LOGIC;
signal b_reg_13_DYMUX_11776 : STD_LOGIC;
signal b_reg_mux0000_12_Q : STD_LOGIC;
signal b_reg_13_SRINV_11768 : STD_LOGIC;
signal b_reg_13_CLKINV_11767 : STD_LOGIC;
signal b_reg_31_DXMUX_11832 : STD_LOGIC;
signal b_reg_mux0000_31_Q : STD_LOGIC;
signal b_reg_31_DYMUX_11818 : STD_LOGIC;
signal b_reg_mux0000_30_Q : STD_LOGIC;
signal b_reg_31_SRINV_11810 : STD_LOGIC;
signal b_reg_31_CLKINV_11809 : STD_LOGIC;
signal b_reg_23_DXMUX_11874 : STD_LOGIC;
signal b_reg_mux0000_23_Q : STD_LOGIC;
signal b_reg_23_DYMUX_11860 : STD_LOGIC;
signal b_reg_mux0000_22_Q : STD_LOGIC;
signal b_reg_23_SRINV_11852 : STD_LOGIC;
signal b_reg_23_CLKINV_11851 : STD_LOGIC;
signal b_reg_15_DXMUX_11916 : STD_LOGIC;
signal b_reg_mux0000_15_Q : STD_LOGIC;
signal b_reg_15_DYMUX_11902 : STD_LOGIC;
signal b_reg_mux0000_14_Q : STD_LOGIC;
signal b_reg_15_SRINV_11894 : STD_LOGIC;
signal b_reg_15_CLKINV_11893 : STD_LOGIC;
signal b_reg_25_DXMUX_11958 : STD_LOGIC;
signal b_reg_mux0000_25_Q : STD_LOGIC;
signal b_reg_25_DYMUX_11944 : STD_LOGIC;
signal b_reg_mux0000_24_Q : STD_LOGIC;
signal b_reg_25_SRINV_11936 : STD_LOGIC;
signal b_reg_25_CLKINV_11935 : STD_LOGIC;
signal b_reg_17_DXMUX_12000 : STD_LOGIC;
signal b_reg_mux0000_17_Q : STD_LOGIC;
signal b_reg_17_DYMUX_11986 : STD_LOGIC;
signal b_reg_mux0000_16_Q : STD_LOGIC;
signal b_reg_17_SRINV_11978 : STD_LOGIC;
signal b_reg_17_CLKINV_11977 : STD_LOGIC;
signal b_reg_27_DXMUX_12042 : STD_LOGIC;
signal b_reg_mux0000_27_Q : STD_LOGIC;
signal b_reg_27_DYMUX_12028 : STD_LOGIC;
signal b_reg_mux0000_26_Q : STD_LOGIC;
signal b_reg_27_SRINV_12020 : STD_LOGIC;
signal b_reg_27_CLKINV_12019 : STD_LOGIC;
signal b_reg_19_DXMUX_12084 : STD_LOGIC;
signal b_reg_mux0000_19_Q : STD_LOGIC;
signal b_reg_19_DYMUX_12070 : STD_LOGIC;
signal b_reg_mux0000_18_Q : STD_LOGIC;
signal b_reg_19_SRINV_12062 : STD_LOGIC;
signal b_reg_19_CLKINV_12061 : STD_LOGIC;
signal b_reg_29_DXMUX_12126 : STD_LOGIC;
signal b_reg_mux0000_29_Q : STD_LOGIC;
signal b_reg_29_DYMUX_12112 : STD_LOGIC;
signal b_reg_mux0000_28_Q : STD_LOGIC;
signal b_reg_29_SRINV_12104 : STD_LOGIC;
signal b_reg_29_CLKINV_12103 : STD_LOGIC;
signal Sh1287_12154 : STD_LOGIC;
signal Sh13220_12146 : STD_LOGIC;
signal Sh110 : STD_LOGIC;
signal Sh15013_12170 : STD_LOGIC;
signal Sh103 : STD_LOGIC;
signal Sh14313_12194 : STD_LOGIC;
signal Sh15816_12226 : STD_LOGIC;
signal Sh15113_12219 : STD_LOGIC;
signal Sh1310 : STD_LOGIC;
signal Sh15116_12243 : STD_LOGIC;
signal Sh14813_12274 : STD_LOGIC;
signal Sh14412_12265 : STD_LOGIC;
signal Sh12816 : STD_LOGIC;
signal Sh14413_12289 : STD_LOGIC;
signal Sh14616_12322 : STD_LOGIC;
signal Sh15413_12315 : STD_LOGIC;
signal Sh106 : STD_LOGIC;
signal Sh14613_12338 : STD_LOGIC;
signal Sh15516_12370 : STD_LOGIC;
signal Sh15513_12363 : STD_LOGIC;
signal Sh1527_12394 : STD_LOGIC;
signal Sh14816_12386 : STD_LOGIC;
signal Sh13013 : STD_LOGIC;
signal Sh15813_12411 : STD_LOGIC;
signal b_reg_0_2_DYMUX_12428 : STD_LOGIC;
signal b_reg_0_2_CLKINV_12425 : STD_LOGIC;
signal b_reg_0_3_DYMUX_12442 : STD_LOGIC;
signal b_reg_0_3_CLKINV_12439 : STD_LOGIC;
signal ab_xor_3_Q : STD_LOGIC;
signal ab_xor_4_Q : STD_LOGIC;
signal N247 : STD_LOGIC;
signal ab_xor_5_Q : STD_LOGIC;
signal N261 : STD_LOGIC;
signal ab_xor_7_Q : STD_LOGIC;
signal N260 : STD_LOGIC;
signal ab_xor_8_Q : STD_LOGIC;
signal N241 : STD_LOGIC;
signal ab_xor_9_Q : STD_LOGIC;
signal Sh102 : STD_LOGIC;
signal Sh98 : STD_LOGIC;
signal N520 : STD_LOGIC;
signal N286 : STD_LOGIC;
signal N522 : STD_LOGIC;
signal N224 : STD_LOGIC;
signal N518 : STD_LOGIC;
signal N226 : STD_LOGIC;
signal N258 : STD_LOGIC;
signal ab_xor_11_Q : STD_LOGIC;
signal N257 : STD_LOGIC;
signal ab_xor_12_Q : STD_LOGIC;
signal N188 : STD_LOGIC;
signal ab_xor_20_Q : STD_LOGIC;
signal N235 : STD_LOGIC;
signal ab_xor_13_Q : STD_LOGIC;
signal N214 : STD_LOGIC;
signal ab_xor_21_Q : STD_LOGIC;
signal N228 : STD_LOGIC;
signal ab_xor_15_Q : STD_LOGIC;
signal N202 : STD_LOGIC;
signal ab_xor_23_Q : STD_LOGIC;
signal N196 : STD_LOGIC;
signal ab_xor_31_Q : STD_LOGIC;
signal N194 : STD_LOGIC;
signal ab_xor_16_Q : STD_LOGIC;
signal N182 : STD_LOGIC;
signal ab_xor_24_Q : STD_LOGIC;
signal N217 : STD_LOGIC;
signal ab_xor_17_Q : STD_LOGIC;
signal N211 : STD_LOGIC;
signal ab_xor_25_Q : STD_LOGIC;
signal N205 : STD_LOGIC;
signal ab_xor_19_Q : STD_LOGIC;
signal N199 : STD_LOGIC;
signal ab_xor_27_Q : STD_LOGIC;
signal N176 : STD_LOGIC;
signal ab_xor_28_Q : STD_LOGIC;
signal N208 : STD_LOGIC;
signal ab_xor_29_Q : STD_LOGIC;
signal N191 : STD_LOGIC;
signal N193 : STD_LOGIC;
signal N179 : STD_LOGIC;
signal N181 : STD_LOGIC;
signal N289 : STD_LOGIC;
signal N190 : STD_LOGIC;
signal N288 : STD_LOGIC;
signal N178 : STD_LOGIC;
signal N185 : STD_LOGIC;
signal N187 : STD_LOGIC;
signal N173 : STD_LOGIC;
signal N175 : STD_LOGIC;
signal N264 : STD_LOGIC;
signal N184 : STD_LOGIC;
signal N263 : STD_LOGIC;
signal N172 : STD_LOGIC;
signal Sh86 : STD_LOGIC;
signal Sh70 : STD_LOGIC;
signal Sh87 : STD_LOGIC;
signal Sh71 : STD_LOGIC;
signal Sh80 : STD_LOGIC;
signal Sh64 : STD_LOGIC;
signal Sh88 : STD_LOGIC;
signal Sh72 : STD_LOGIC;
signal Sh5320 : STD_LOGIC;
signal Sh5720 : STD_LOGIC;
signal Sh81 : STD_LOGIC;
signal Sh65 : STD_LOGIC;
signal Sh5420 : STD_LOGIC;
signal Sh5820 : STD_LOGIC;
signal Sh82 : STD_LOGIC;
signal Sh66 : STD_LOGIC;
signal N246 : STD_LOGIC;
signal Sh90 : STD_LOGIC;
signal Sh83 : STD_LOGIC;
signal Sh67 : STD_LOGIC;
signal Sh91 : STD_LOGIC;
signal Sh75 : STD_LOGIC;
signal Sh84 : STD_LOGIC;
signal Sh68 : STD_LOGIC;
signal Sh92 : STD_LOGIC;
signal Sh76 : STD_LOGIC;
signal Sh85 : STD_LOGIC;
signal Sh69 : STD_LOGIC;
signal Sh79 : STD_LOGIC;
signal Sh93 : STD_LOGIC;
signal Sh89 : STD_LOGIC;
signal Sh94 : STD_LOGIC;
signal N254 : STD_LOGIC;
signal Sh991_13638 : STD_LOGIC;
signal Sh99 : STD_LOGIC;
signal Sh1011_pack_1 : STD_LOGIC;
signal b_reg_mux0000_2_13_13694 : STD_LOGIC;
signal b_reg_mux0000_2_5_13686 : STD_LOGIC;
signal b_reg_1_DXMUX_13736 : STD_LOGIC;
signal b_reg_1_F5MUX_13734 : STD_LOGIC;
signal N499 : STD_LOGIC;
signal b_reg_1_BXINV_13726 : STD_LOGIC;
signal b_reg_1_DYMUX_13719 : STD_LOGIC;
signal N498 : STD_LOGIC;
signal b_reg_1_SRINV_13711 : STD_LOGIC;
signal b_reg_1_CLKINV_13710 : STD_LOGIC;
signal b_reg_3_DXMUX_13760 : STD_LOGIC;
signal b_reg_3_DYMUX_13752 : STD_LOGIC;
signal b_reg_3_SRINV_13750 : STD_LOGIC;
signal b_reg_3_CLKINV_13749 : STD_LOGIC;
signal b_reg_4_DXMUX_13793 : STD_LOGIC;
signal b_reg_4_DYMUX_13785 : STD_LOGIC;
signal b_reg_mux0000_5_Q : STD_LOGIC;
signal b_reg_4_SRINV_13776 : STD_LOGIC;
signal b_reg_4_CLKINV_13775 : STD_LOGIC;
signal b_reg_mux0000_4_12_13821 : STD_LOGIC;
signal b_reg_mux0000_4_3_13813 : STD_LOGIC;
signal b_reg_mux0000_6_12_13845 : STD_LOGIC;
signal b_reg_mux0000_6_3_13837 : STD_LOGIC;
signal Mrom_b_rom000024_13869 : STD_LOGIC;
signal N27 : STD_LOGIC;
signal N111 : STD_LOGIC;
signal N12 : STD_LOGIC;
signal N20 : STD_LOGIC;
signal N17 : STD_LOGIC;
signal Mrom_b_rom00005_13941 : STD_LOGIC;
signal N222 : STD_LOGIC;
signal i_cnt_mux0001_0_25_13965 : STD_LOGIC;
signal i_cnt_mux0001_0_22_pack_1 : STD_LOGIC;
signal Sh1567_13989 : STD_LOGIC;
signal Sh12813 : STD_LOGIC;
signal Sh1577_14013 : STD_LOGIC;
signal Sh12913 : STD_LOGIC;
signal Sh1297_14037 : STD_LOGIC;
signal Sh12916 : STD_LOGIC;
signal Sh1497_14061 : STD_LOGIC;
signal Sh1537_14053 : STD_LOGIC;
signal Sh177 : STD_LOGIC;
signal Sh181 : STD_LOGIC;
signal Sh183 : STD_LOGIC;
signal Sh182 : STD_LOGIC;
signal Sh184 : STD_LOGIC;
signal Sh190 : STD_LOGIC;
signal Sh186 : STD_LOGIC;
signal Sh185 : STD_LOGIC;
signal Sh188 : STD_LOGIC;
signal Sh187 : STD_LOGIC;
signal Sh347 : STD_LOGIC;
signal Sh337 : STD_LOGIC;
signal Sh189 : STD_LOGIC;
signal Madd_b_pre_cy_4_Q : STD_LOGIC;
signal Madd_b_pre_cy_2_pack_1 : STD_LOGIC;
signal b_reg_mux0000_10_10 : STD_LOGIC;
signal Madd_b_pre_cy_6_pack_1 : STD_LOGIC;
signal segment_a_i_OBUF_14289 : STD_LOGIC;
signal segment_g_i_OBUF_14282 : STD_LOGIC;
signal segment_d_i_OBUF_14313 : STD_LOGIC;
signal segment_e_i_OBUF_14306 : STD_LOGIC;
signal segment_f_i_OBUF_14337 : STD_LOGIC;
signal segment_c_i_OBUF_14330 : STD_LOGIC;
signal segment_b_i_OBUF_14349 : STD_LOGIC;
signal N14 : STD_LOGIC;
signal N514 : STD_LOGIC;
signal i_cnt_2_DXMUX_14404 : STD_LOGIC;
signal N516_pack_3 : STD_LOGIC;
signal i_cnt_2_CLKINV_14388 : STD_LOGIC;
signal Mrom_b_rom000012_14432 : STD_LOGIC;
signal Mrom_a_rom000010 : STD_LOGIC;
signal Mrom_b_rom000020_14456 : STD_LOGIC;
signal Mrom_a_rom000011_14449 : STD_LOGIC;
signal Mrom_b_rom00008_14480 : STD_LOGIC;
signal Mrom_a_rom000021 : STD_LOGIC;
signal Mrom_b_rom000013_14504 : STD_LOGIC;
signal Mrom_a_rom000030 : STD_LOGIC;
signal Mrom_b_rom000031 : STD_LOGIC;
signal Mrom_a_rom000031 : STD_LOGIC;
signal Mrom_b_rom000023 : STD_LOGIC;
signal Mrom_a_rom000025 : STD_LOGIC;
signal Mrom_b_rom000017_14576 : STD_LOGIC;
signal Mrom_a_rom000026 : STD_LOGIC;
signal Mrom_b_rom00007 : STD_LOGIC;
signal Mrom_a_rom000019 : STD_LOGIC;
signal Mrom_b_rom000030 : STD_LOGIC;
signal Mrom_a_rom000027 : STD_LOGIC;
signal N237 : STD_LOGIC;
signal N251 : STD_LOGIC;
signal Mrom_b_rom000028 : STD_LOGIC;
signal Mrom_b_rom000011_14665 : STD_LOGIC;
signal N231 : STD_LOGIC;
signal N234 : STD_LOGIC;
signal Mrom_b_rom000026 : STD_LOGIC;
signal N77 : STD_LOGIC;
signal N33 : STD_LOGIC;
signal N34 : STD_LOGIC;
signal do_rdy_OBUF_14756 : STD_LOGIC;
signal Mrom_b_rom000022 : STD_LOGIC;
signal Mrom_a_rom00001 : STD_LOGIC;
signal Mrom_b_rom000016 : STD_LOGIC;
signal Mrom_a_rom0000 : STD_LOGIC;
signal Mrom_b_rom000010 : STD_LOGIC;
signal Mrom_a_rom000013_14821 : STD_LOGIC;
signal Mrom_b_rom00006 : STD_LOGIC;
signal Mrom_a_rom000023_14845 : STD_LOGIC;
signal Mrom_b_rom00009_14876 : STD_LOGIC;
signal Mrom_a_rom000015_14869 : STD_LOGIC;
signal Mrom_b_rom000021 : STD_LOGIC;
signal Mrom_a_rom000024_14893 : STD_LOGIC;
signal Mrom_b_rom000014_14924 : STD_LOGIC;
signal Mrom_a_rom000016_14917 : STD_LOGIC;
signal Mrom_b_rom00001 : STD_LOGIC;
signal Mrom_a_rom000017_14941 : STD_LOGIC;
signal Mrom_a_rom000029_14972 : STD_LOGIC;
signal Mrom_a_rom000018_14965 : STD_LOGIC;
signal Mrom_b_rom000029_14996 : STD_LOGIC;
signal Mrom_a_rom00006 : STD_LOGIC;
signal Mrom_a_rom00009_15020 : STD_LOGIC;
signal Mrom_a_rom00008 : STD_LOGIC;
signal Mrom_a_rom00005_15044 : STD_LOGIC;
signal Mrom_b_rom000019 : STD_LOGIC;
signal Mrom_a_rom00002_15068 : STD_LOGIC;
signal Mrom_b_rom000027 : STD_LOGIC;
signal state_FSM_FFd2_DXMUX_15109 : STD_LOGIC;
signal state_FSM_FFd2_In : STD_LOGIC;
signal state_FSM_FFd2_DYMUX_15095 : STD_LOGIC;
signal state_cmp_eq0000_pack_4 : STD_LOGIC;
signal state_FSM_FFd2_SRINV_15086 : STD_LOGIC;
signal state_FSM_FFd2_CLKINV_15085 : STD_LOGIC;
signal Mrom_b_rom0000 : STD_LOGIC;
signal Mrom_a_rom00004_15130 : STD_LOGIC;
signal N240 : STD_LOGIC;
signal N243 : STD_LOGIC;
signal hex_digit_i_3_FFX_RSTAND_9773 : STD_LOGIC;
signal b_reg_8_FFX_RSTAND_9245 : STD_LOGIC;
signal b_reg_9_FFX_RSTAND_9281 : STD_LOGIC;
signal b_reg_0_1_FFX_RSTAND_9543 : STD_LOGIC;
signal hex_digit_i_0_FFX_RSTAND_9579 : STD_LOGIC;
signal i_cnt_3_FFX_RSTAND_9665 : STD_LOGIC;
signal hex_digit_i_1_FFX_RSTAND_9701 : STD_LOGIC;
signal hex_digit_i_2_FFX_RSTAND_9737 : STD_LOGIC;
signal b_reg_2_1_FFY_RSTAND_10805 : STD_LOGIC;
signal b_reg_3_1_FFY_RSTAND_10829 : STD_LOGIC;
signal b_reg_4_1_FFY_RSTAND_10853 : STD_LOGIC;
signal b_reg_11_FFY_RSTAND_11711 : STD_LOGIC;
signal b_reg_0_2_FFY_RSTAND_12433 : STD_LOGIC;
signal b_reg_0_3_FFY_RSTAND_12447 : STD_LOGIC;
signal i_cnt_2_FFX_RSTAND_14409 : STD_LOGIC;
signal VCC : STD_LOGIC;
signal GND : STD_LOGIC;
signal LED_flash_cnt : STD_LOGIC_VECTOR ( 9 downto 0 );
signal b_reg : STD_LOGIC_VECTOR ( 31 downto 0 );
signal a : STD_LOGIC_VECTOR ( 31 downto 0 );
signal i_cnt : STD_LOGIC_VECTOR ( 3 downto 0 );
signal Madd_b_pre_lut : STD_LOGIC_VECTOR ( 2 downto 2 );
signal a_reg : STD_LOGIC_VECTOR ( 31 downto 0 );
signal hex_digit_i : STD_LOGIC_VECTOR ( 3 downto 0 );
signal Mcount_LED_flash_cnt_lut : STD_LOGIC_VECTOR ( 0 downto 0 );
signal Madd_a_lut : STD_LOGIC_VECTOR ( 31 downto 0 );
signal Madd_b_lut : STD_LOGIC_VECTOR ( 31 downto 0 );
signal a_reg_mux0000 : STD_LOGIC_VECTOR ( 31 downto 0 );
signal i_cnt_mux0001 : STD_LOGIC_VECTOR ( 3 downto 1 );
begin
NlwRenamedSig_IO_clr <= clr;
NlwRenamedSig_IO_di_vld <= di_vld;
LED_flash_cnt_0_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X31Y10"
)
port map (
O => LED_flash_cnt_0_LOGIC_ZERO_4631
);
LED_flash_cnt_0_LOGIC_ONE : X_ONE
generic map(
LOC => "SLICE_X31Y10"
)
port map (
O => LED_flash_cnt_0_LOGIC_ONE_4655
);
LED_flash_cnt_0_DXMUX : X_BUF
generic map(
LOC => "SLICE_X31Y10",
PATHPULSE => 638 ps
)
port map (
I => LED_flash_cnt_0_XORF_4656,
O => LED_flash_cnt_0_DXMUX_4658
);
LED_flash_cnt_0_XORF : X_XOR2
generic map(
LOC => "SLICE_X31Y10"
)
port map (
I0 => LED_flash_cnt_0_CYINIT_4654,
I1 => Mcount_LED_flash_cnt_lut(0),
O => LED_flash_cnt_0_XORF_4656
);
LED_flash_cnt_0_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X31Y10"
)
port map (
IA => LED_flash_cnt_0_LOGIC_ONE_4655,
IB => LED_flash_cnt_0_CYINIT_4654,
SEL => LED_flash_cnt_0_CYSELF_4645,
O => Mcount_LED_flash_cnt_cy_0_Q
);
LED_flash_cnt_0_CYINIT : X_BUF
generic map(
LOC => "SLICE_X31Y10",
PATHPULSE => 638 ps
)
port map (
I => LED_flash_cnt_0_BXINV_4643,
O => LED_flash_cnt_0_CYINIT_4654
);
LED_flash_cnt_0_CYSELF : X_BUF
generic map(
LOC => "SLICE_X31Y10",
PATHPULSE => 638 ps
)
port map (
I => Mcount_LED_flash_cnt_lut(0),
O => LED_flash_cnt_0_CYSELF_4645
);
LED_flash_cnt_0_BXINV : X_BUF
generic map(
LOC => "SLICE_X31Y10",
PATHPULSE => 638 ps
)
port map (
I => '0',
O => LED_flash_cnt_0_BXINV_4643
);
LED_flash_cnt_0_DYMUX : X_BUF
generic map(
LOC => "SLICE_X31Y10",
PATHPULSE => 638 ps
)
port map (
I => LED_flash_cnt_0_XORG_4634,
O => LED_flash_cnt_0_DYMUX_4636
);
LED_flash_cnt_0_XORG : X_XOR2
generic map(
LOC => "SLICE_X31Y10"
)
port map (
I0 => Mcount_LED_flash_cnt_cy_0_Q,
I1 => LED_flash_cnt_0_G,
O => LED_flash_cnt_0_XORG_4634
);
LED_flash_cnt_0_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X31Y10",
PATHPULSE => 638 ps
)
port map (
I => LED_flash_cnt_0_CYMUXG_4633,
O => Mcount_LED_flash_cnt_cy_1_Q
);
LED_flash_cnt_0_CYMUXG : X_MUX2
generic map(
LOC => "SLICE_X31Y10"
)
port map (
IA => LED_flash_cnt_0_LOGIC_ZERO_4631,
IB => Mcount_LED_flash_cnt_cy_0_Q,
SEL => LED_flash_cnt_0_CYSELG_4622,
O => LED_flash_cnt_0_CYMUXG_4633
);
LED_flash_cnt_0_CYSELG : X_BUF
generic map(
LOC => "SLICE_X31Y10",
PATHPULSE => 638 ps
)
port map (
I => LED_flash_cnt_0_G,
O => LED_flash_cnt_0_CYSELG_4622
);
LED_flash_cnt_0_SRINV : X_BUF
generic map(
LOC => "SLICE_X31Y10",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => LED_flash_cnt_0_SRINV_4620
);
LED_flash_cnt_0_CLKINV : X_BUF
generic map(
LOC => "SLICE_X31Y10",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => LED_flash_cnt_0_CLKINV_4619
);
LED_flash_cnt_2_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X31Y11"
)
port map (
O => LED_flash_cnt_2_LOGIC_ZERO_4685
);
LED_flash_cnt_2_DXMUX : X_BUF
generic map(
LOC => "SLICE_X31Y11",
PATHPULSE => 638 ps
)
port map (
I => LED_flash_cnt_2_XORF_4712,
O => LED_flash_cnt_2_DXMUX_4714
);
LED_flash_cnt_2_XORF : X_XOR2
generic map(
LOC => "SLICE_X31Y11"
)
port map (
I0 => LED_flash_cnt_2_CYINIT_4711,
I1 => LED_flash_cnt_2_F,
O => LED_flash_cnt_2_XORF_4712
);
LED_flash_cnt_2_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X31Y11"
)
port map (
IA => LED_flash_cnt_2_LOGIC_ZERO_4685,
IB => LED_flash_cnt_2_CYINIT_4711,
SEL => LED_flash_cnt_2_CYSELF_4691,
O => Mcount_LED_flash_cnt_cy_2_Q
);
LED_flash_cnt_2_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X31Y11"
)
port map (
IA => LED_flash_cnt_2_LOGIC_ZERO_4685,
IB => LED_flash_cnt_2_LOGIC_ZERO_4685,
SEL => LED_flash_cnt_2_CYSELF_4691,
O => LED_flash_cnt_2_CYMUXF2_4686
);
LED_flash_cnt_2_CYINIT : X_BUF
generic map(
LOC => "SLICE_X31Y11",
PATHPULSE => 638 ps
)
port map (
I => Mcount_LED_flash_cnt_cy_1_Q,
O => LED_flash_cnt_2_CYINIT_4711
);
LED_flash_cnt_2_CYSELF : X_BUF
generic map(
LOC => "SLICE_X31Y11",
PATHPULSE => 638 ps
)
port map (
I => LED_flash_cnt_2_F,
O => LED_flash_cnt_2_CYSELF_4691
);
LED_flash_cnt_2_DYMUX : X_BUF
generic map(
LOC => "SLICE_X31Y11",
PATHPULSE => 638 ps
)
port map (
I => LED_flash_cnt_2_XORG_4693,
O => LED_flash_cnt_2_DYMUX_4695
);
LED_flash_cnt_2_XORG : X_XOR2
generic map(
LOC => "SLICE_X31Y11"
)
port map (
I0 => Mcount_LED_flash_cnt_cy_2_Q,
I1 => LED_flash_cnt_2_G,
O => LED_flash_cnt_2_XORG_4693
);
LED_flash_cnt_2_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X31Y11",
PATHPULSE => 638 ps
)
port map (
I => LED_flash_cnt_2_CYMUXFAST_4690,
O => Mcount_LED_flash_cnt_cy_3_Q
);
LED_flash_cnt_2_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X31Y11",
PATHPULSE => 638 ps
)
port map (
I => Mcount_LED_flash_cnt_cy_1_Q,
O => LED_flash_cnt_2_FASTCARRY_4688
);
LED_flash_cnt_2_CYAND : X_AND2
generic map(
LOC => "SLICE_X31Y11"
)
port map (
I0 => LED_flash_cnt_2_CYSELG_4676,
I1 => LED_flash_cnt_2_CYSELF_4691,
O => LED_flash_cnt_2_CYAND_4689
);
LED_flash_cnt_2_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X31Y11"
)
port map (
IA => LED_flash_cnt_2_CYMUXG2_4687,
IB => LED_flash_cnt_2_FASTCARRY_4688,
SEL => LED_flash_cnt_2_CYAND_4689,
O => LED_flash_cnt_2_CYMUXFAST_4690
);
LED_flash_cnt_2_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X31Y11"
)
port map (
IA => LED_flash_cnt_2_LOGIC_ZERO_4685,
IB => LED_flash_cnt_2_CYMUXF2_4686,
SEL => LED_flash_cnt_2_CYSELG_4676,
O => LED_flash_cnt_2_CYMUXG2_4687
);
LED_flash_cnt_2_CYSELG : X_BUF
generic map(
LOC => "SLICE_X31Y11",
PATHPULSE => 638 ps
)
port map (
I => LED_flash_cnt_2_G,
O => LED_flash_cnt_2_CYSELG_4676
);
LED_flash_cnt_2_SRINV : X_BUF
generic map(
LOC => "SLICE_X31Y11",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => LED_flash_cnt_2_SRINV_4674
);
LED_flash_cnt_2_CLKINV : X_BUF
generic map(
LOC => "SLICE_X31Y11",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => LED_flash_cnt_2_CLKINV_4673
);
LED_flash_cnt_4_FFY_RSTOR : X_BUF
generic map(
LOC => "SLICE_X31Y12",
PATHPULSE => 638 ps
)
port map (
I => LED_flash_cnt_4_SRINV_4730,
O => LED_flash_cnt_4_FFY_RST
);
LED_flash_cnt_5 : X_FF
generic map(
LOC => "SLICE_X31Y12",
INIT => '0'
)
port map (
I => LED_flash_cnt_4_DYMUX_4751,
CE => VCC,
CLK => LED_flash_cnt_4_CLKINV_4729,
SET => GND,
RST => LED_flash_cnt_4_FFY_RST,
O => LED_flash_cnt(5)
);
LED_flash_cnt_4_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X31Y12"
)
port map (
O => LED_flash_cnt_4_LOGIC_ZERO_4741
);
LED_flash_cnt_4_DXMUX : X_BUF
generic map(
LOC => "SLICE_X31Y12",
PATHPULSE => 638 ps
)
port map (
I => LED_flash_cnt_4_XORF_4768,
O => LED_flash_cnt_4_DXMUX_4770
);
LED_flash_cnt_4_XORF : X_XOR2
generic map(
LOC => "SLICE_X31Y12"
)
port map (
I0 => LED_flash_cnt_4_CYINIT_4767,
I1 => LED_flash_cnt_4_F,
O => LED_flash_cnt_4_XORF_4768
);
LED_flash_cnt_4_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X31Y12"
)
port map (
IA => LED_flash_cnt_4_LOGIC_ZERO_4741,
IB => LED_flash_cnt_4_CYINIT_4767,
SEL => LED_flash_cnt_4_CYSELF_4747,
O => Mcount_LED_flash_cnt_cy_4_Q
);
LED_flash_cnt_4_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X31Y12"
)
port map (
IA => LED_flash_cnt_4_LOGIC_ZERO_4741,
IB => LED_flash_cnt_4_LOGIC_ZERO_4741,
SEL => LED_flash_cnt_4_CYSELF_4747,
O => LED_flash_cnt_4_CYMUXF2_4742
);
LED_flash_cnt_4_CYINIT : X_BUF
generic map(
LOC => "SLICE_X31Y12",
PATHPULSE => 638 ps
)
port map (
I => Mcount_LED_flash_cnt_cy_3_Q,
O => LED_flash_cnt_4_CYINIT_4767
);
LED_flash_cnt_4_CYSELF : X_BUF
generic map(
LOC => "SLICE_X31Y12",
PATHPULSE => 638 ps
)
port map (
I => LED_flash_cnt_4_F,
O => LED_flash_cnt_4_CYSELF_4747
);
LED_flash_cnt_4_DYMUX : X_BUF
generic map(
LOC => "SLICE_X31Y12",
PATHPULSE => 638 ps
)
port map (
I => LED_flash_cnt_4_XORG_4749,
O => LED_flash_cnt_4_DYMUX_4751
);
LED_flash_cnt_4_XORG : X_XOR2
generic map(
LOC => "SLICE_X31Y12"
)
port map (
I0 => Mcount_LED_flash_cnt_cy_4_Q,
I1 => LED_flash_cnt_4_G,
O => LED_flash_cnt_4_XORG_4749
);
LED_flash_cnt_4_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X31Y12",
PATHPULSE => 638 ps
)
port map (
I => LED_flash_cnt_4_CYMUXFAST_4746,
O => Mcount_LED_flash_cnt_cy_5_Q
);
LED_flash_cnt_4_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X31Y12",
PATHPULSE => 638 ps
)
port map (
I => Mcount_LED_flash_cnt_cy_3_Q,
O => LED_flash_cnt_4_FASTCARRY_4744
);
LED_flash_cnt_4_CYAND : X_AND2
generic map(
LOC => "SLICE_X31Y12"
)
port map (
I0 => LED_flash_cnt_4_CYSELG_4732,
I1 => LED_flash_cnt_4_CYSELF_4747,
O => LED_flash_cnt_4_CYAND_4745
);
LED_flash_cnt_4_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X31Y12"
)
port map (
IA => LED_flash_cnt_4_CYMUXG2_4743,
IB => LED_flash_cnt_4_FASTCARRY_4744,
SEL => LED_flash_cnt_4_CYAND_4745,
O => LED_flash_cnt_4_CYMUXFAST_4746
);
LED_flash_cnt_4_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X31Y12"
)
port map (
IA => LED_flash_cnt_4_LOGIC_ZERO_4741,
IB => LED_flash_cnt_4_CYMUXF2_4742,
SEL => LED_flash_cnt_4_CYSELG_4732,
O => LED_flash_cnt_4_CYMUXG2_4743
);
LED_flash_cnt_4_CYSELG : X_BUF
generic map(
LOC => "SLICE_X31Y12",
PATHPULSE => 638 ps
)
port map (
I => LED_flash_cnt_4_G,
O => LED_flash_cnt_4_CYSELG_4732
);
LED_flash_cnt_4_SRINV : X_BUF
generic map(
LOC => "SLICE_X31Y12",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => LED_flash_cnt_4_SRINV_4730
);
LED_flash_cnt_4_CLKINV : X_BUF
generic map(
LOC => "SLICE_X31Y12",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => LED_flash_cnt_4_CLKINV_4729
);
LED_flash_cnt_6_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X31Y13"
)
port map (
O => LED_flash_cnt_6_LOGIC_ZERO_4797
);
LED_flash_cnt_6_DXMUX : X_BUF
generic map(
LOC => "SLICE_X31Y13",
PATHPULSE => 638 ps
)
port map (
I => LED_flash_cnt_6_XORF_4824,
O => LED_flash_cnt_6_DXMUX_4826
);
LED_flash_cnt_6_XORF : X_XOR2
generic map(
LOC => "SLICE_X31Y13"
)
port map (
I0 => LED_flash_cnt_6_CYINIT_4823,
I1 => LED_flash_cnt_6_F,
O => LED_flash_cnt_6_XORF_4824
);
LED_flash_cnt_6_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X31Y13"
)
port map (
IA => LED_flash_cnt_6_LOGIC_ZERO_4797,
IB => LED_flash_cnt_6_CYINIT_4823,
SEL => LED_flash_cnt_6_CYSELF_4803,
O => Mcount_LED_flash_cnt_cy_6_Q
);
LED_flash_cnt_6_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X31Y13"
)
port map (
IA => LED_flash_cnt_6_LOGIC_ZERO_4797,
IB => LED_flash_cnt_6_LOGIC_ZERO_4797,
SEL => LED_flash_cnt_6_CYSELF_4803,
O => LED_flash_cnt_6_CYMUXF2_4798
);
LED_flash_cnt_6_CYINIT : X_BUF
generic map(
LOC => "SLICE_X31Y13",
PATHPULSE => 638 ps
)
port map (
I => Mcount_LED_flash_cnt_cy_5_Q,
O => LED_flash_cnt_6_CYINIT_4823
);
LED_flash_cnt_6_CYSELF : X_BUF
generic map(
LOC => "SLICE_X31Y13",
PATHPULSE => 638 ps
)
port map (
I => LED_flash_cnt_6_F,
O => LED_flash_cnt_6_CYSELF_4803
);
LED_flash_cnt_6_DYMUX : X_BUF
generic map(
LOC => "SLICE_X31Y13",
PATHPULSE => 638 ps
)
port map (
I => LED_flash_cnt_6_XORG_4805,
O => LED_flash_cnt_6_DYMUX_4807
);
LED_flash_cnt_6_XORG : X_XOR2
generic map(
LOC => "SLICE_X31Y13"
)
port map (
I0 => Mcount_LED_flash_cnt_cy_6_Q,
I1 => LED_flash_cnt_6_G,
O => LED_flash_cnt_6_XORG_4805
);
LED_flash_cnt_6_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X31Y13",
PATHPULSE => 638 ps
)
port map (
I => Mcount_LED_flash_cnt_cy_5_Q,
O => LED_flash_cnt_6_FASTCARRY_4800
);
LED_flash_cnt_6_CYAND : X_AND2
generic map(
LOC => "SLICE_X31Y13"
)
port map (
I0 => LED_flash_cnt_6_CYSELG_4788,
I1 => LED_flash_cnt_6_CYSELF_4803,
O => LED_flash_cnt_6_CYAND_4801
);
LED_flash_cnt_6_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X31Y13"
)
port map (
IA => LED_flash_cnt_6_CYMUXG2_4799,
IB => LED_flash_cnt_6_FASTCARRY_4800,
SEL => LED_flash_cnt_6_CYAND_4801,
O => LED_flash_cnt_6_CYMUXFAST_4802
);
LED_flash_cnt_6_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X31Y13"
)
port map (
IA => LED_flash_cnt_6_LOGIC_ZERO_4797,
IB => LED_flash_cnt_6_CYMUXF2_4798,
SEL => LED_flash_cnt_6_CYSELG_4788,
O => LED_flash_cnt_6_CYMUXG2_4799
);
LED_flash_cnt_6_CYSELG : X_BUF
generic map(
LOC => "SLICE_X31Y13",
PATHPULSE => 638 ps
)
port map (
I => LED_flash_cnt_6_G,
O => LED_flash_cnt_6_CYSELG_4788
);
LED_flash_cnt_6_SRINV : X_BUF
generic map(
LOC => "SLICE_X31Y13",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => LED_flash_cnt_6_SRINV_4786
);
LED_flash_cnt_6_CLKINV : X_BUF
generic map(
LOC => "SLICE_X31Y13",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => LED_flash_cnt_6_CLKINV_4785
);
LED_flash_cnt_8_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X31Y14"
)
port map (
O => LED_flash_cnt_8_LOGIC_ZERO_4872
);
LED_flash_cnt_8_DXMUX : X_BUF
generic map(
LOC => "SLICE_X31Y14",
PATHPULSE => 638 ps
)
port map (
I => LED_flash_cnt_8_XORF_4873,
O => LED_flash_cnt_8_DXMUX_4875
);
LED_flash_cnt_8_XORF : X_XOR2
generic map(
LOC => "SLICE_X31Y14"
)
port map (
I0 => LED_flash_cnt_8_CYINIT_4871,
I1 => LED_flash_cnt_8_F,
O => LED_flash_cnt_8_XORF_4873
);
LED_flash_cnt_8_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X31Y14"
)
port map (
IA => LED_flash_cnt_8_LOGIC_ZERO_4872,
IB => LED_flash_cnt_8_CYINIT_4871,
SEL => LED_flash_cnt_8_CYSELF_4862,
O => Mcount_LED_flash_cnt_cy_8_Q
);
LED_flash_cnt_8_CYINIT : X_BUF
generic map(
LOC => "SLICE_X31Y14",
PATHPULSE => 638 ps
)
port map (
I => LED_flash_cnt_6_CYMUXFAST_4802,
O => LED_flash_cnt_8_CYINIT_4871
);
LED_flash_cnt_8_CYSELF : X_BUF
generic map(
LOC => "SLICE_X31Y14",
PATHPULSE => 638 ps
)
port map (
I => LED_flash_cnt_8_F,
O => LED_flash_cnt_8_CYSELF_4862
);
LED_flash_cnt_8_DYMUX : X_BUF
generic map(
LOC => "SLICE_X31Y14",
PATHPULSE => 638 ps
)
port map (
I => LED_flash_cnt_8_XORG_4852,
O => LED_flash_cnt_8_DYMUX_4854
);
LED_flash_cnt_8_XORG : X_XOR2
generic map(
LOC => "SLICE_X31Y14"
)
port map (
I0 => Mcount_LED_flash_cnt_cy_8_Q,
I1 => LED_flash_cnt_9_rt_4849,
O => LED_flash_cnt_8_XORG_4852
);
LED_flash_cnt_8_SRINV : X_BUF
generic map(
LOC => "SLICE_X31Y14",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => LED_flash_cnt_8_SRINV_4841
);
LED_flash_cnt_8_CLKINV : X_BUF
generic map(
LOC => "SLICE_X31Y14",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => LED_flash_cnt_8_CLKINV_4840
);
LED_flash_cnt_9_rt : X_LUT4
generic map(
INIT => X"AAAA",
LOC => "SLICE_X31Y14"
)
port map (
ADR0 => LED_flash_cnt(9),
ADR1 => VCC,
ADR2 => VCC,
ADR3 => VCC,
O => LED_flash_cnt_9_rt_4849
);
a_0_XUSED : X_BUF
generic map(
LOC => "SLICE_X17Y16",
PATHPULSE => 638 ps
)
port map (
I => a_0_XORF_4918,
O => a(0)
);
a_0_XORF : X_XOR2
generic map(
LOC => "SLICE_X17Y16"
)
port map (
I0 => a_0_CYINIT_4917,
I1 => Madd_a_lut(0),
O => a_0_XORF_4918
);
a_0_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X17Y16"
)
port map (
IA => a_0_CY0F_4916,
IB => a_0_CYINIT_4917,
SEL => a_0_CYSELF_4908,
O => Madd_a_cy_0_Q
);
a_0_CYINIT : X_BUF
generic map(
LOC => "SLICE_X17Y16",
PATHPULSE => 638 ps
)
port map (
I => a_0_BXINV_4906,
O => a_0_CYINIT_4917
);
a_0_CY0F : X_BUF
generic map(
LOC => "SLICE_X17Y16",
PATHPULSE => 638 ps
)
port map (
I => Sh64_0,
O => a_0_CY0F_4916
);
a_0_CYSELF : X_BUF
generic map(
LOC => "SLICE_X17Y16",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(0),
O => a_0_CYSELF_4908
);
a_0_BXINV : X_BUF
generic map(
LOC => "SLICE_X17Y16",
PATHPULSE => 638 ps
)
port map (
I => '0',
O => a_0_BXINV_4906
);
a_0_YUSED : X_BUF
generic map(
LOC => "SLICE_X17Y16",
PATHPULSE => 638 ps
)
port map (
I => a_0_XORG_4904,
O => a(1)
);
a_0_XORG : X_XOR2
generic map(
LOC => "SLICE_X17Y16"
)
port map (
I0 => Madd_a_cy_0_Q,
I1 => Madd_a_lut(1),
O => a_0_XORG_4904
);
a_0_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X17Y16",
PATHPULSE => 638 ps
)
port map (
I => a_0_CYMUXG_4903,
O => Madd_a_cy_1_Q
);
a_0_CYMUXG : X_MUX2
generic map(
LOC => "SLICE_X17Y16"
)
port map (
IA => a_0_CY0G_4901,
IB => Madd_a_cy_0_Q,
SEL => a_0_CYSELG_4895,
O => a_0_CYMUXG_4903
);
a_0_CY0G : X_BUF
generic map(
LOC => "SLICE_X17Y16",
PATHPULSE => 638 ps
)
port map (
I => Sh65,
O => a_0_CY0G_4901
);
a_0_CYSELG : X_BUF
generic map(
LOC => "SLICE_X17Y16",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(1),
O => a_0_CYSELG_4895
);
a_2_XUSED : X_BUF
generic map(
LOC => "SLICE_X17Y17",
PATHPULSE => 638 ps
)
port map (
I => a_2_XORF_4961,
O => a(2)
);
a_2_XORF : X_XOR2
generic map(
LOC => "SLICE_X17Y17"
)
port map (
I0 => a_2_CYINIT_4960,
I1 => Madd_a_lut(2),
O => a_2_XORF_4961
);
a_2_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X17Y17"
)
port map (
IA => a_2_CY0F_4959,
IB => a_2_CYINIT_4960,
SEL => a_2_CYSELF_4948,
O => Madd_a_cy_2_Q
);
a_2_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X17Y17"
)
port map (
IA => a_2_CY0F_4959,
IB => a_2_CY0F_4959,
SEL => a_2_CYSELF_4948,
O => a_2_CYMUXF2_4943
);
a_2_CYINIT : X_BUF
generic map(
LOC => "SLICE_X17Y17",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_cy_1_Q,
O => a_2_CYINIT_4960
);
a_2_CY0F : X_BUF
generic map(
LOC => "SLICE_X17Y17",
PATHPULSE => 638 ps
)
port map (
I => Sh66,
O => a_2_CY0F_4959
);
a_2_CYSELF : X_BUF
generic map(
LOC => "SLICE_X17Y17",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(2),
O => a_2_CYSELF_4948
);
a_2_YUSED : X_BUF
generic map(
LOC => "SLICE_X17Y17",
PATHPULSE => 638 ps
)
port map (
I => a_2_XORG_4950,
O => a(3)
);
a_2_XORG : X_XOR2
generic map(
LOC => "SLICE_X17Y17"
)
port map (
I0 => Madd_a_cy_2_Q,
I1 => Madd_a_lut(3),
O => a_2_XORG_4950
);
a_2_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X17Y17",
PATHPULSE => 638 ps
)
port map (
I => a_2_CYMUXFAST_4947,
O => Madd_a_cy_3_Q
);
a_2_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X17Y17",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_cy_1_Q,
O => a_2_FASTCARRY_4945
);
a_2_CYAND : X_AND2
generic map(
LOC => "SLICE_X17Y17"
)
port map (
I0 => a_2_CYSELG_4936,
I1 => a_2_CYSELF_4948,
O => a_2_CYAND_4946
);
a_2_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X17Y17"
)
port map (
IA => a_2_CYMUXG2_4944,
IB => a_2_FASTCARRY_4945,
SEL => a_2_CYAND_4946,
O => a_2_CYMUXFAST_4947
);
a_2_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X17Y17"
)
port map (
IA => a_2_CY0G_4942,
IB => a_2_CYMUXF2_4943,
SEL => a_2_CYSELG_4936,
O => a_2_CYMUXG2_4944
);
a_2_CY0G : X_BUF
generic map(
LOC => "SLICE_X17Y17",
PATHPULSE => 638 ps
)
port map (
I => Sh67,
O => a_2_CY0G_4942
);
a_2_CYSELG : X_BUF
generic map(
LOC => "SLICE_X17Y17",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(3),
O => a_2_CYSELG_4936
);
Madd_a_lut_5_Q : X_LUT4
generic map(
INIT => X"1ED2",
LOC => "SLICE_X17Y18"
)
port map (
ADR0 => Sh37,
ADR1 => b_reg(4),
ADR2 => Mrom_a_rom00005_0,
ADR3 => Sh53,
O => Madd_a_lut(5)
);
a_4_XUSED : X_BUF
generic map(
LOC => "SLICE_X17Y18",
PATHPULSE => 638 ps
)
port map (
I => a_4_XORF_5004,
O => a(4)
);
a_4_XORF : X_XOR2
generic map(
LOC => "SLICE_X17Y18"
)
port map (
I0 => a_4_CYINIT_5003,
I1 => Madd_a_lut(4),
O => a_4_XORF_5004
);
a_4_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X17Y18"
)
port map (
IA => a_4_CY0F_5002,
IB => a_4_CYINIT_5003,
SEL => a_4_CYSELF_4991,
O => Madd_a_cy_4_Q
);
a_4_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X17Y18"
)
port map (
IA => a_4_CY0F_5002,
IB => a_4_CY0F_5002,
SEL => a_4_CYSELF_4991,
O => a_4_CYMUXF2_4986
);
a_4_CYINIT : X_BUF
generic map(
LOC => "SLICE_X17Y18",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_cy_3_Q,
O => a_4_CYINIT_5003
);
a_4_CY0F : X_BUF
generic map(
LOC => "SLICE_X17Y18",
PATHPULSE => 638 ps
)
port map (
I => Sh68,
O => a_4_CY0F_5002
);
a_4_CYSELF : X_BUF
generic map(
LOC => "SLICE_X17Y18",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(4),
O => a_4_CYSELF_4991
);
a_4_YUSED : X_BUF
generic map(
LOC => "SLICE_X17Y18",
PATHPULSE => 638 ps
)
port map (
I => a_4_XORG_4993,
O => a(5)
);
a_4_XORG : X_XOR2
generic map(
LOC => "SLICE_X17Y18"
)
port map (
I0 => Madd_a_cy_4_Q,
I1 => Madd_a_lut(5),
O => a_4_XORG_4993
);
a_4_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X17Y18",
PATHPULSE => 638 ps
)
port map (
I => a_4_CYMUXFAST_4990,
O => Madd_a_cy_5_Q
);
a_4_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X17Y18",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_cy_3_Q,
O => a_4_FASTCARRY_4988
);
a_4_CYAND : X_AND2
generic map(
LOC => "SLICE_X17Y18"
)
port map (
I0 => a_4_CYSELG_4979,
I1 => a_4_CYSELF_4991,
O => a_4_CYAND_4989
);
a_4_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X17Y18"
)
port map (
IA => a_4_CYMUXG2_4987,
IB => a_4_FASTCARRY_4988,
SEL => a_4_CYAND_4989,
O => a_4_CYMUXFAST_4990
);
a_4_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X17Y18"
)
port map (
IA => a_4_CY0G_4985,
IB => a_4_CYMUXF2_4986,
SEL => a_4_CYSELG_4979,
O => a_4_CYMUXG2_4987
);
a_4_CY0G : X_BUF
generic map(
LOC => "SLICE_X17Y18",
PATHPULSE => 638 ps
)
port map (
I => Sh69,
O => a_4_CY0G_4985
);
a_4_CYSELG : X_BUF
generic map(
LOC => "SLICE_X17Y18",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(5),
O => a_4_CYSELG_4979
);
a_6_XUSED : X_BUF
generic map(
LOC => "SLICE_X17Y19",
PATHPULSE => 638 ps
)
port map (
I => a_6_XORF_5047,
O => a(6)
);
a_6_XORF : X_XOR2
generic map(
LOC => "SLICE_X17Y19"
)
port map (
I0 => a_6_CYINIT_5046,
I1 => Madd_a_lut(6),
O => a_6_XORF_5047
);
a_6_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X17Y19"
)
port map (
IA => a_6_CY0F_5045,
IB => a_6_CYINIT_5046,
SEL => a_6_CYSELF_5034,
O => Madd_a_cy_6_Q
);
a_6_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X17Y19"
)
port map (
IA => a_6_CY0F_5045,
IB => a_6_CY0F_5045,
SEL => a_6_CYSELF_5034,
O => a_6_CYMUXF2_5029
);
a_6_CYINIT : X_BUF
generic map(
LOC => "SLICE_X17Y19",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_cy_5_Q,
O => a_6_CYINIT_5046
);
a_6_CY0F : X_BUF
generic map(
LOC => "SLICE_X17Y19",
PATHPULSE => 638 ps
)
port map (
I => Sh70,
O => a_6_CY0F_5045
);
a_6_CYSELF : X_BUF
generic map(
LOC => "SLICE_X17Y19",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(6),
O => a_6_CYSELF_5034
);
a_6_YUSED : X_BUF
generic map(
LOC => "SLICE_X17Y19",
PATHPULSE => 638 ps
)
port map (
I => a_6_XORG_5036,
O => a(7)
);
a_6_XORG : X_XOR2
generic map(
LOC => "SLICE_X17Y19"
)
port map (
I0 => Madd_a_cy_6_Q,
I1 => Madd_a_lut(7),
O => a_6_XORG_5036
);
a_6_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X17Y19",
PATHPULSE => 638 ps
)
port map (
I => a_6_CYMUXFAST_5033,
O => Madd_a_cy_7_Q
);
a_6_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X17Y19",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_cy_5_Q,
O => a_6_FASTCARRY_5031
);
a_6_CYAND : X_AND2
generic map(
LOC => "SLICE_X17Y19"
)
port map (
I0 => a_6_CYSELG_5022,
I1 => a_6_CYSELF_5034,
O => a_6_CYAND_5032
);
a_6_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X17Y19"
)
port map (
IA => a_6_CYMUXG2_5030,
IB => a_6_FASTCARRY_5031,
SEL => a_6_CYAND_5032,
O => a_6_CYMUXFAST_5033
);
a_6_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X17Y19"
)
port map (
IA => a_6_CY0G_5028,
IB => a_6_CYMUXF2_5029,
SEL => a_6_CYSELG_5022,
O => a_6_CYMUXG2_5030
);
a_6_CY0G : X_BUF
generic map(
LOC => "SLICE_X17Y19",
PATHPULSE => 638 ps
)
port map (
I => Sh71,
O => a_6_CY0G_5028
);
a_6_CYSELG : X_BUF
generic map(
LOC => "SLICE_X17Y19",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(7),
O => a_6_CYSELG_5022
);
a_8_XUSED : X_BUF
generic map(
LOC => "SLICE_X17Y20",
PATHPULSE => 638 ps
)
port map (
I => a_8_XORF_5090,
O => a(8)
);
a_8_XORF : X_XOR2
generic map(
LOC => "SLICE_X17Y20"
)
port map (
I0 => a_8_CYINIT_5089,
I1 => Madd_a_lut(8),
O => a_8_XORF_5090
);
a_8_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X17Y20"
)
port map (
IA => a_8_CY0F_5088,
IB => a_8_CYINIT_5089,
SEL => a_8_CYSELF_5077,
O => Madd_a_cy_8_Q
);
a_8_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X17Y20"
)
port map (
IA => a_8_CY0F_5088,
IB => a_8_CY0F_5088,
SEL => a_8_CYSELF_5077,
O => a_8_CYMUXF2_5072
);
a_8_CYINIT : X_BUF
generic map(
LOC => "SLICE_X17Y20",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_cy_7_Q,
O => a_8_CYINIT_5089
);
a_8_CY0F : X_BUF
generic map(
LOC => "SLICE_X17Y20",
PATHPULSE => 638 ps
)
port map (
I => Sh72,
O => a_8_CY0F_5088
);
a_8_CYSELF : X_BUF
generic map(
LOC => "SLICE_X17Y20",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(8),
O => a_8_CYSELF_5077
);
a_8_YUSED : X_BUF
generic map(
LOC => "SLICE_X17Y20",
PATHPULSE => 638 ps
)
port map (
I => a_8_XORG_5079,
O => a(9)
);
a_8_XORG : X_XOR2
generic map(
LOC => "SLICE_X17Y20"
)
port map (
I0 => Madd_a_cy_8_Q,
I1 => Madd_a_lut(9),
O => a_8_XORG_5079
);
a_8_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X17Y20",
PATHPULSE => 638 ps
)
port map (
I => a_8_CYMUXFAST_5076,
O => Madd_a_cy_9_Q
);
a_8_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X17Y20",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_cy_7_Q,
O => a_8_FASTCARRY_5074
);
a_8_CYAND : X_AND2
generic map(
LOC => "SLICE_X17Y20"
)
port map (
I0 => a_8_CYSELG_5065,
I1 => a_8_CYSELF_5077,
O => a_8_CYAND_5075
);
a_8_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X17Y20"
)
port map (
IA => a_8_CYMUXG2_5073,
IB => a_8_FASTCARRY_5074,
SEL => a_8_CYAND_5075,
O => a_8_CYMUXFAST_5076
);
a_8_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X17Y20"
)
port map (
IA => a_8_CY0G_5071,
IB => a_8_CYMUXF2_5072,
SEL => a_8_CYSELG_5065,
O => a_8_CYMUXG2_5073
);
a_8_CY0G : X_BUF
generic map(
LOC => "SLICE_X17Y20",
PATHPULSE => 638 ps
)
port map (
I => Sh73,
O => a_8_CY0G_5071
);
a_8_CYSELG : X_BUF
generic map(
LOC => "SLICE_X17Y20",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(9),
O => a_8_CYSELG_5065
);
a_10_XUSED : X_BUF
generic map(
LOC => "SLICE_X17Y21",
PATHPULSE => 638 ps
)
port map (
I => a_10_XORF_5133,
O => a(10)
);
a_10_XORF : X_XOR2
generic map(
LOC => "SLICE_X17Y21"
)
port map (
I0 => a_10_CYINIT_5132,
I1 => Madd_a_lut(10),
O => a_10_XORF_5133
);
a_10_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X17Y21"
)
port map (
IA => a_10_CY0F_5131,
IB => a_10_CYINIT_5132,
SEL => a_10_CYSELF_5120,
O => Madd_a_cy_10_Q
);
a_10_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X17Y21"
)
port map (
IA => a_10_CY0F_5131,
IB => a_10_CY0F_5131,
SEL => a_10_CYSELF_5120,
O => a_10_CYMUXF2_5115
);
a_10_CYINIT : X_BUF
generic map(
LOC => "SLICE_X17Y21",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_cy_9_Q,
O => a_10_CYINIT_5132
);
a_10_CY0F : X_BUF
generic map(
LOC => "SLICE_X17Y21",
PATHPULSE => 638 ps
)
port map (
I => Sh74,
O => a_10_CY0F_5131
);
a_10_CYSELF : X_BUF
generic map(
LOC => "SLICE_X17Y21",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(10),
O => a_10_CYSELF_5120
);
a_10_YUSED : X_BUF
generic map(
LOC => "SLICE_X17Y21",
PATHPULSE => 638 ps
)
port map (
I => a_10_XORG_5122,
O => a(11)
);
a_10_XORG : X_XOR2
generic map(
LOC => "SLICE_X17Y21"
)
port map (
I0 => Madd_a_cy_10_Q,
I1 => Madd_a_lut(11),
O => a_10_XORG_5122
);
a_10_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X17Y21",
PATHPULSE => 638 ps
)
port map (
I => a_10_CYMUXFAST_5119,
O => Madd_a_cy_11_Q
);
a_10_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X17Y21",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_cy_9_Q,
O => a_10_FASTCARRY_5117
);
a_10_CYAND : X_AND2
generic map(
LOC => "SLICE_X17Y21"
)
port map (
I0 => a_10_CYSELG_5108,
I1 => a_10_CYSELF_5120,
O => a_10_CYAND_5118
);
a_10_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X17Y21"
)
port map (
IA => a_10_CYMUXG2_5116,
IB => a_10_FASTCARRY_5117,
SEL => a_10_CYAND_5118,
O => a_10_CYMUXFAST_5119
);
a_10_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X17Y21"
)
port map (
IA => a_10_CY0G_5114,
IB => a_10_CYMUXF2_5115,
SEL => a_10_CYSELG_5108,
O => a_10_CYMUXG2_5116
);
a_10_CY0G : X_BUF
generic map(
LOC => "SLICE_X17Y21",
PATHPULSE => 638 ps
)
port map (
I => Sh75,
O => a_10_CY0G_5114
);
a_10_CYSELG : X_BUF
generic map(
LOC => "SLICE_X17Y21",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(11),
O => a_10_CYSELG_5108
);
Madd_a_lut_13_Q : X_LUT4
generic map(
INIT => X"4B78",
LOC => "SLICE_X17Y22"
)
port map (
ADR0 => Sh61,
ADR1 => b_reg(4),
ADR2 => Mrom_a_rom000013_0,
ADR3 => Sh45,
O => Madd_a_lut(13)
);
a_12_XUSED : X_BUF
generic map(
LOC => "SLICE_X17Y22",
PATHPULSE => 638 ps
)
port map (
I => a_12_XORF_5176,
O => a(12)
);
a_12_XORF : X_XOR2
generic map(
LOC => "SLICE_X17Y22"
)
port map (
I0 => a_12_CYINIT_5175,
I1 => Madd_a_lut(12),
O => a_12_XORF_5176
);
a_12_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X17Y22"
)
port map (
IA => a_12_CY0F_5174,
IB => a_12_CYINIT_5175,
SEL => a_12_CYSELF_5163,
O => Madd_a_cy_12_Q
);
a_12_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X17Y22"
)
port map (
IA => a_12_CY0F_5174,
IB => a_12_CY0F_5174,
SEL => a_12_CYSELF_5163,
O => a_12_CYMUXF2_5158
);
a_12_CYINIT : X_BUF
generic map(
LOC => "SLICE_X17Y22",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_cy_11_Q,
O => a_12_CYINIT_5175
);
a_12_CY0F : X_BUF
generic map(
LOC => "SLICE_X17Y22",
PATHPULSE => 638 ps
)
port map (
I => Sh76,
O => a_12_CY0F_5174
);
a_12_CYSELF : X_BUF
generic map(
LOC => "SLICE_X17Y22",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(12),
O => a_12_CYSELF_5163
);
a_12_YUSED : X_BUF
generic map(
LOC => "SLICE_X17Y22",
PATHPULSE => 638 ps
)
port map (
I => a_12_XORG_5165,
O => a(13)
);
a_12_XORG : X_XOR2
generic map(
LOC => "SLICE_X17Y22"
)
port map (
I0 => Madd_a_cy_12_Q,
I1 => Madd_a_lut(13),
O => a_12_XORG_5165
);
a_12_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X17Y22",
PATHPULSE => 638 ps
)
port map (
I => a_12_CYMUXFAST_5162,
O => Madd_a_cy_13_Q
);
a_12_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X17Y22",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_cy_11_Q,
O => a_12_FASTCARRY_5160
);
a_12_CYAND : X_AND2
generic map(
LOC => "SLICE_X17Y22"
)
port map (
I0 => a_12_CYSELG_5151,
I1 => a_12_CYSELF_5163,
O => a_12_CYAND_5161
);
a_12_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X17Y22"
)
port map (
IA => a_12_CYMUXG2_5159,
IB => a_12_FASTCARRY_5160,
SEL => a_12_CYAND_5161,
O => a_12_CYMUXFAST_5162
);
a_12_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X17Y22"
)
port map (
IA => a_12_CY0G_5157,
IB => a_12_CYMUXF2_5158,
SEL => a_12_CYSELG_5151,
O => a_12_CYMUXG2_5159
);
a_12_CY0G : X_BUF
generic map(
LOC => "SLICE_X17Y22",
PATHPULSE => 638 ps
)
port map (
I => Sh77,
O => a_12_CY0G_5157
);
a_12_CYSELG : X_BUF
generic map(
LOC => "SLICE_X17Y22",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(13),
O => a_12_CYSELG_5151
);
a_14_XUSED : X_BUF
generic map(
LOC => "SLICE_X17Y23",
PATHPULSE => 638 ps
)
port map (
I => a_14_XORF_5219,
O => a(14)
);
a_14_XORF : X_XOR2
generic map(
LOC => "SLICE_X17Y23"
)
port map (
I0 => a_14_CYINIT_5218,
I1 => Madd_a_lut(14),
O => a_14_XORF_5219
);
a_14_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X17Y23"
)
port map (
IA => a_14_CY0F_5217,
IB => a_14_CYINIT_5218,
SEL => a_14_CYSELF_5206,
O => Madd_a_cy_14_Q
);
a_14_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X17Y23"
)
port map (
IA => a_14_CY0F_5217,
IB => a_14_CY0F_5217,
SEL => a_14_CYSELF_5206,
O => a_14_CYMUXF2_5201
);
a_14_CYINIT : X_BUF
generic map(
LOC => "SLICE_X17Y23",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_cy_13_Q,
O => a_14_CYINIT_5218
);
a_14_CY0F : X_BUF
generic map(
LOC => "SLICE_X17Y23",
PATHPULSE => 638 ps
)
port map (
I => Sh78,
O => a_14_CY0F_5217
);
a_14_CYSELF : X_BUF
generic map(
LOC => "SLICE_X17Y23",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(14),
O => a_14_CYSELF_5206
);
a_14_YUSED : X_BUF
generic map(
LOC => "SLICE_X17Y23",
PATHPULSE => 638 ps
)
port map (
I => a_14_XORG_5208,
O => a(15)
);
a_14_XORG : X_XOR2
generic map(
LOC => "SLICE_X17Y23"
)
port map (
I0 => Madd_a_cy_14_Q,
I1 => Madd_a_lut(15),
O => a_14_XORG_5208
);
a_14_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X17Y23",
PATHPULSE => 638 ps
)
port map (
I => a_14_CYMUXFAST_5205,
O => Madd_a_cy_15_Q
);
a_14_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X17Y23",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_cy_13_Q,
O => a_14_FASTCARRY_5203
);
a_14_CYAND : X_AND2
generic map(
LOC => "SLICE_X17Y23"
)
port map (
I0 => a_14_CYSELG_5194,
I1 => a_14_CYSELF_5206,
O => a_14_CYAND_5204
);
a_14_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X17Y23"
)
port map (
IA => a_14_CYMUXG2_5202,
IB => a_14_FASTCARRY_5203,
SEL => a_14_CYAND_5204,
O => a_14_CYMUXFAST_5205
);
a_14_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X17Y23"
)
port map (
IA => a_14_CY0G_5200,
IB => a_14_CYMUXF2_5201,
SEL => a_14_CYSELG_5194,
O => a_14_CYMUXG2_5202
);
a_14_CY0G : X_BUF
generic map(
LOC => "SLICE_X17Y23",
PATHPULSE => 638 ps
)
port map (
I => Sh79,
O => a_14_CY0G_5200
);
a_14_CYSELG : X_BUF
generic map(
LOC => "SLICE_X17Y23",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(15),
O => a_14_CYSELG_5194
);
a_16_XUSED : X_BUF
generic map(
LOC => "SLICE_X17Y24",
PATHPULSE => 638 ps
)
port map (
I => a_16_XORF_5262,
O => a(16)
);
a_16_XORF : X_XOR2
generic map(
LOC => "SLICE_X17Y24"
)
port map (
I0 => a_16_CYINIT_5261,
I1 => Madd_a_lut(16),
O => a_16_XORF_5262
);
a_16_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X17Y24"
)
port map (
IA => a_16_CY0F_5260,
IB => a_16_CYINIT_5261,
SEL => a_16_CYSELF_5249,
O => Madd_a_cy_16_Q
);
a_16_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X17Y24"
)
port map (
IA => a_16_CY0F_5260,
IB => a_16_CY0F_5260,
SEL => a_16_CYSELF_5249,
O => a_16_CYMUXF2_5244
);
a_16_CYINIT : X_BUF
generic map(
LOC => "SLICE_X17Y24",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_cy_15_Q,
O => a_16_CYINIT_5261
);
a_16_CY0F : X_BUF
generic map(
LOC => "SLICE_X17Y24",
PATHPULSE => 638 ps
)
port map (
I => Sh80,
O => a_16_CY0F_5260
);
a_16_CYSELF : X_BUF
generic map(
LOC => "SLICE_X17Y24",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(16),
O => a_16_CYSELF_5249
);
a_16_YUSED : X_BUF
generic map(
LOC => "SLICE_X17Y24",
PATHPULSE => 638 ps
)
port map (
I => a_16_XORG_5251,
O => a(17)
);
a_16_XORG : X_XOR2
generic map(
LOC => "SLICE_X17Y24"
)
port map (
I0 => Madd_a_cy_16_Q,
I1 => Madd_a_lut(17),
O => a_16_XORG_5251
);
a_16_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X17Y24",
PATHPULSE => 638 ps
)
port map (
I => a_16_CYMUXFAST_5248,
O => Madd_a_cy_17_Q
);
a_16_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X17Y24",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_cy_15_Q,
O => a_16_FASTCARRY_5246
);
a_16_CYAND : X_AND2
generic map(
LOC => "SLICE_X17Y24"
)
port map (
I0 => a_16_CYSELG_5237,
I1 => a_16_CYSELF_5249,
O => a_16_CYAND_5247
);
a_16_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X17Y24"
)
port map (
IA => a_16_CYMUXG2_5245,
IB => a_16_FASTCARRY_5246,
SEL => a_16_CYAND_5247,
O => a_16_CYMUXFAST_5248
);
a_16_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X17Y24"
)
port map (
IA => a_16_CY0G_5243,
IB => a_16_CYMUXF2_5244,
SEL => a_16_CYSELG_5237,
O => a_16_CYMUXG2_5245
);
a_16_CY0G : X_BUF
generic map(
LOC => "SLICE_X17Y24",
PATHPULSE => 638 ps
)
port map (
I => Sh81,
O => a_16_CY0G_5243
);
a_16_CYSELG : X_BUF
generic map(
LOC => "SLICE_X17Y24",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(17),
O => a_16_CYSELG_5237
);
Madd_a_lut_16_Q : X_LUT4
generic map(
INIT => X"569A",
LOC => "SLICE_X17Y24"
)
port map (
ADR0 => Mrom_a_rom000016_0,
ADR1 => b_reg(4),
ADR2 => Sh48,
ADR3 => Sh32,
O => Madd_a_lut(16)
);
a_18_XUSED : X_BUF
generic map(
LOC => "SLICE_X17Y25",
PATHPULSE => 638 ps
)
port map (
I => a_18_XORF_5305,
O => a(18)
);
a_18_XORF : X_XOR2
generic map(
LOC => "SLICE_X17Y25"
)
port map (
I0 => a_18_CYINIT_5304,
I1 => Madd_a_lut(18),
O => a_18_XORF_5305
);
a_18_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X17Y25"
)
port map (
IA => a_18_CY0F_5303,
IB => a_18_CYINIT_5304,
SEL => a_18_CYSELF_5292,
O => Madd_a_cy_18_Q
);
a_18_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X17Y25"
)
port map (
IA => a_18_CY0F_5303,
IB => a_18_CY0F_5303,
SEL => a_18_CYSELF_5292,
O => a_18_CYMUXF2_5287
);
a_18_CYINIT : X_BUF
generic map(
LOC => "SLICE_X17Y25",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_cy_17_Q,
O => a_18_CYINIT_5304
);
a_18_CY0F : X_BUF
generic map(
LOC => "SLICE_X17Y25",
PATHPULSE => 638 ps
)
port map (
I => Sh82,
O => a_18_CY0F_5303
);
a_18_CYSELF : X_BUF
generic map(
LOC => "SLICE_X17Y25",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(18),
O => a_18_CYSELF_5292
);
a_18_YUSED : X_BUF
generic map(
LOC => "SLICE_X17Y25",
PATHPULSE => 638 ps
)
port map (
I => a_18_XORG_5294,
O => a(19)
);
a_18_XORG : X_XOR2
generic map(
LOC => "SLICE_X17Y25"
)
port map (
I0 => Madd_a_cy_18_Q,
I1 => Madd_a_lut(19),
O => a_18_XORG_5294
);
a_18_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X17Y25",
PATHPULSE => 638 ps
)
port map (
I => a_18_CYMUXFAST_5291,
O => Madd_a_cy_19_Q
);
a_18_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X17Y25",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_cy_17_Q,
O => a_18_FASTCARRY_5289
);
a_18_CYAND : X_AND2
generic map(
LOC => "SLICE_X17Y25"
)
port map (
I0 => a_18_CYSELG_5280,
I1 => a_18_CYSELF_5292,
O => a_18_CYAND_5290
);
a_18_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X17Y25"
)
port map (
IA => a_18_CYMUXG2_5288,
IB => a_18_FASTCARRY_5289,
SEL => a_18_CYAND_5290,
O => a_18_CYMUXFAST_5291
);
a_18_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X17Y25"
)
port map (
IA => a_18_CY0G_5286,
IB => a_18_CYMUXF2_5287,
SEL => a_18_CYSELG_5280,
O => a_18_CYMUXG2_5288
);
a_18_CY0G : X_BUF
generic map(
LOC => "SLICE_X17Y25",
PATHPULSE => 638 ps
)
port map (
I => Sh83,
O => a_18_CY0G_5286
);
a_18_CYSELG : X_BUF
generic map(
LOC => "SLICE_X17Y25",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(19),
O => a_18_CYSELG_5280
);
a_20_XUSED : X_BUF
generic map(
LOC => "SLICE_X17Y26",
PATHPULSE => 638 ps
)
port map (
I => a_20_XORF_5346,
O => a(20)
);
a_20_XORF : X_XOR2
generic map(
LOC => "SLICE_X17Y26"
)
port map (
I0 => a_20_CYINIT_5345,
I1 => Madd_a_lut(20),
O => a_20_XORF_5346
);
a_20_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X17Y26"
)
port map (
IA => a_20_CY0F_5344,
IB => a_20_CYINIT_5345,
SEL => a_20_CYSELF_5334,
O => Madd_a_cy_20_Q
);
a_20_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X17Y26"
)
port map (
IA => a_20_CY0F_5344,
IB => a_20_CY0F_5344,
SEL => a_20_CYSELF_5334,
O => a_20_CYMUXF2_5329
);
a_20_CYINIT : X_BUF
generic map(
LOC => "SLICE_X17Y26",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_cy_19_Q,
O => a_20_CYINIT_5345
);
a_20_CY0F : X_BUF
generic map(
LOC => "SLICE_X17Y26",
PATHPULSE => 638 ps
)
port map (
I => Sh84_0,
O => a_20_CY0F_5344
);
a_20_CYSELF : X_BUF
generic map(
LOC => "SLICE_X17Y26",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(20),
O => a_20_CYSELF_5334
);
a_20_YUSED : X_BUF
generic map(
LOC => "SLICE_X17Y26",
PATHPULSE => 638 ps
)
port map (
I => a_20_XORG_5336,
O => a(21)
);
a_20_XORG : X_XOR2
generic map(
LOC => "SLICE_X17Y26"
)
port map (
I0 => Madd_a_cy_20_Q,
I1 => Madd_a_lut(21),
O => a_20_XORG_5336
);
a_20_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X17Y26",
PATHPULSE => 638 ps
)
port map (
I => a_20_CYMUXFAST_5333,
O => Madd_a_cy_21_Q
);
a_20_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X17Y26",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_cy_19_Q,
O => a_20_FASTCARRY_5331
);
a_20_CYAND : X_AND2
generic map(
LOC => "SLICE_X17Y26"
)
port map (
I0 => a_20_CYSELG_5322,
I1 => a_20_CYSELF_5334,
O => a_20_CYAND_5332
);
a_20_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X17Y26"
)
port map (
IA => a_20_CYMUXG2_5330,
IB => a_20_FASTCARRY_5331,
SEL => a_20_CYAND_5332,
O => a_20_CYMUXFAST_5333
);
a_20_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X17Y26"
)
port map (
IA => a_20_CY0G_5328,
IB => a_20_CYMUXF2_5329,
SEL => a_20_CYSELG_5322,
O => a_20_CYMUXG2_5330
);
a_20_CY0G : X_BUF
generic map(
LOC => "SLICE_X17Y26",
PATHPULSE => 638 ps
)
port map (
I => Sh85,
O => a_20_CY0G_5328
);
a_20_CYSELG : X_BUF
generic map(
LOC => "SLICE_X17Y26",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(21),
O => a_20_CYSELG_5322
);
Madd_a_lut_23_Q : X_LUT4
generic map(
INIT => X"1ED2",
LOC => "SLICE_X17Y27"
)
port map (
ADR0 => Sh55,
ADR1 => b_reg(4),
ADR2 => Mrom_a_rom000023_0,
ADR3 => Sh39,
O => Madd_a_lut(23)
);
a_22_XUSED : X_BUF
generic map(
LOC => "SLICE_X17Y27",
PATHPULSE => 638 ps
)
port map (
I => a_22_XORF_5389,
O => a(22)
);
a_22_XORF : X_XOR2
generic map(
LOC => "SLICE_X17Y27"
)
port map (
I0 => a_22_CYINIT_5388,
I1 => Madd_a_lut(22),
O => a_22_XORF_5389
);
a_22_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X17Y27"
)
port map (
IA => a_22_CY0F_5387,
IB => a_22_CYINIT_5388,
SEL => a_22_CYSELF_5376,
O => Madd_a_cy_22_Q
);
a_22_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X17Y27"
)
port map (
IA => a_22_CY0F_5387,
IB => a_22_CY0F_5387,
SEL => a_22_CYSELF_5376,
O => a_22_CYMUXF2_5371
);
a_22_CYINIT : X_BUF
generic map(
LOC => "SLICE_X17Y27",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_cy_21_Q,
O => a_22_CYINIT_5388
);
a_22_CY0F : X_BUF
generic map(
LOC => "SLICE_X17Y27",
PATHPULSE => 638 ps
)
port map (
I => Sh86,
O => a_22_CY0F_5387
);
a_22_CYSELF : X_BUF
generic map(
LOC => "SLICE_X17Y27",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(22),
O => a_22_CYSELF_5376
);
a_22_YUSED : X_BUF
generic map(
LOC => "SLICE_X17Y27",
PATHPULSE => 638 ps
)
port map (
I => a_22_XORG_5378,
O => a(23)
);
a_22_XORG : X_XOR2
generic map(
LOC => "SLICE_X17Y27"
)
port map (
I0 => Madd_a_cy_22_Q,
I1 => Madd_a_lut(23),
O => a_22_XORG_5378
);
a_22_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X17Y27",
PATHPULSE => 638 ps
)
port map (
I => a_22_CYMUXFAST_5375,
O => Madd_a_cy_23_Q
);
a_22_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X17Y27",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_cy_21_Q,
O => a_22_FASTCARRY_5373
);
a_22_CYAND : X_AND2
generic map(
LOC => "SLICE_X17Y27"
)
port map (
I0 => a_22_CYSELG_5364,
I1 => a_22_CYSELF_5376,
O => a_22_CYAND_5374
);
a_22_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X17Y27"
)
port map (
IA => a_22_CYMUXG2_5372,
IB => a_22_FASTCARRY_5373,
SEL => a_22_CYAND_5374,
O => a_22_CYMUXFAST_5375
);
a_22_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X17Y27"
)
port map (
IA => a_22_CY0G_5370,
IB => a_22_CYMUXF2_5371,
SEL => a_22_CYSELG_5364,
O => a_22_CYMUXG2_5372
);
a_22_CY0G : X_BUF
generic map(
LOC => "SLICE_X17Y27",
PATHPULSE => 638 ps
)
port map (
I => Sh87,
O => a_22_CY0G_5370
);
a_22_CYSELG : X_BUF
generic map(
LOC => "SLICE_X17Y27",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(23),
O => a_22_CYSELG_5364
);
a_24_XUSED : X_BUF
generic map(
LOC => "SLICE_X17Y28",
PATHPULSE => 638 ps
)
port map (
I => a_24_XORF_5432,
O => a(24)
);
a_24_XORF : X_XOR2
generic map(
LOC => "SLICE_X17Y28"
)
port map (
I0 => a_24_CYINIT_5431,
I1 => Madd_a_lut(24),
O => a_24_XORF_5432
);
a_24_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X17Y28"
)
port map (
IA => a_24_CY0F_5430,
IB => a_24_CYINIT_5431,
SEL => a_24_CYSELF_5419,
O => Madd_a_cy_24_Q
);
a_24_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X17Y28"
)
port map (
IA => a_24_CY0F_5430,
IB => a_24_CY0F_5430,
SEL => a_24_CYSELF_5419,
O => a_24_CYMUXF2_5414
);
a_24_CYINIT : X_BUF
generic map(
LOC => "SLICE_X17Y28",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_cy_23_Q,
O => a_24_CYINIT_5431
);
a_24_CY0F : X_BUF
generic map(
LOC => "SLICE_X17Y28",
PATHPULSE => 638 ps
)
port map (
I => Sh88,
O => a_24_CY0F_5430
);
a_24_CYSELF : X_BUF
generic map(
LOC => "SLICE_X17Y28",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(24),
O => a_24_CYSELF_5419
);
a_24_YUSED : X_BUF
generic map(
LOC => "SLICE_X17Y28",
PATHPULSE => 638 ps
)
port map (
I => a_24_XORG_5421,
O => a(25)
);
a_24_XORG : X_XOR2
generic map(
LOC => "SLICE_X17Y28"
)
port map (
I0 => Madd_a_cy_24_Q,
I1 => Madd_a_lut(25),
O => a_24_XORG_5421
);
a_24_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X17Y28",
PATHPULSE => 638 ps
)
port map (
I => a_24_CYMUXFAST_5418,
O => Madd_a_cy_25_Q
);
a_24_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X17Y28",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_cy_23_Q,
O => a_24_FASTCARRY_5416
);
a_24_CYAND : X_AND2
generic map(
LOC => "SLICE_X17Y28"
)
port map (
I0 => a_24_CYSELG_5407,
I1 => a_24_CYSELF_5419,
O => a_24_CYAND_5417
);
a_24_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X17Y28"
)
port map (
IA => a_24_CYMUXG2_5415,
IB => a_24_FASTCARRY_5416,
SEL => a_24_CYAND_5417,
O => a_24_CYMUXFAST_5418
);
a_24_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X17Y28"
)
port map (
IA => a_24_CY0G_5413,
IB => a_24_CYMUXF2_5414,
SEL => a_24_CYSELG_5407,
O => a_24_CYMUXG2_5415
);
a_24_CY0G : X_BUF
generic map(
LOC => "SLICE_X17Y28",
PATHPULSE => 638 ps
)
port map (
I => Sh89,
O => a_24_CY0G_5413
);
a_24_CYSELG : X_BUF
generic map(
LOC => "SLICE_X17Y28",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(25),
O => a_24_CYSELG_5407
);
a_26_XUSED : X_BUF
generic map(
LOC => "SLICE_X17Y29",
PATHPULSE => 638 ps
)
port map (
I => a_26_XORF_5475,
O => a(26)
);
a_26_XORF : X_XOR2
generic map(
LOC => "SLICE_X17Y29"
)
port map (
I0 => a_26_CYINIT_5474,
I1 => Madd_a_lut(26),
O => a_26_XORF_5475
);
a_26_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X17Y29"
)
port map (
IA => a_26_CY0F_5473,
IB => a_26_CYINIT_5474,
SEL => a_26_CYSELF_5462,
O => Madd_a_cy_26_Q
);
a_26_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X17Y29"
)
port map (
IA => a_26_CY0F_5473,
IB => a_26_CY0F_5473,
SEL => a_26_CYSELF_5462,
O => a_26_CYMUXF2_5457
);
a_26_CYINIT : X_BUF
generic map(
LOC => "SLICE_X17Y29",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_cy_25_Q,
O => a_26_CYINIT_5474
);
a_26_CY0F : X_BUF
generic map(
LOC => "SLICE_X17Y29",
PATHPULSE => 638 ps
)
port map (
I => Sh90,
O => a_26_CY0F_5473
);
a_26_CYSELF : X_BUF
generic map(
LOC => "SLICE_X17Y29",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(26),
O => a_26_CYSELF_5462
);
a_26_YUSED : X_BUF
generic map(
LOC => "SLICE_X17Y29",
PATHPULSE => 638 ps
)
port map (
I => a_26_XORG_5464,
O => a(27)
);
a_26_XORG : X_XOR2
generic map(
LOC => "SLICE_X17Y29"
)
port map (
I0 => Madd_a_cy_26_Q,
I1 => Madd_a_lut(27),
O => a_26_XORG_5464
);
a_26_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X17Y29",
PATHPULSE => 638 ps
)
port map (
I => a_26_CYMUXFAST_5461,
O => Madd_a_cy_27_Q
);
a_26_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X17Y29",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_cy_25_Q,
O => a_26_FASTCARRY_5459
);
a_26_CYAND : X_AND2
generic map(
LOC => "SLICE_X17Y29"
)
port map (
I0 => a_26_CYSELG_5450,
I1 => a_26_CYSELF_5462,
O => a_26_CYAND_5460
);
a_26_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X17Y29"
)
port map (
IA => a_26_CYMUXG2_5458,
IB => a_26_FASTCARRY_5459,
SEL => a_26_CYAND_5460,
O => a_26_CYMUXFAST_5461
);
a_26_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X17Y29"
)
port map (
IA => a_26_CY0G_5456,
IB => a_26_CYMUXF2_5457,
SEL => a_26_CYSELG_5450,
O => a_26_CYMUXG2_5458
);
a_26_CY0G : X_BUF
generic map(
LOC => "SLICE_X17Y29",
PATHPULSE => 638 ps
)
port map (
I => Sh91,
O => a_26_CY0G_5456
);
a_26_CYSELG : X_BUF
generic map(
LOC => "SLICE_X17Y29",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(27),
O => a_26_CYSELG_5450
);
Madd_a_lut_26_Q : X_LUT4
generic map(
INIT => X"5A66",
LOC => "SLICE_X17Y29"
)
port map (
ADR0 => Mrom_a_rom000026_0,
ADR1 => Sh58,
ADR2 => Sh42,
ADR3 => b_reg(4),
O => Madd_a_lut(26)
);
a_28_XUSED : X_BUF
generic map(
LOC => "SLICE_X17Y30",
PATHPULSE => 638 ps
)
port map (
I => a_28_XORF_5518,
O => a(28)
);
a_28_XORF : X_XOR2
generic map(
LOC => "SLICE_X17Y30"
)
port map (
I0 => a_28_CYINIT_5517,
I1 => Madd_a_lut(28),
O => a_28_XORF_5518
);
a_28_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X17Y30"
)
port map (
IA => a_28_CY0F_5516,
IB => a_28_CYINIT_5517,
SEL => a_28_CYSELF_5505,
O => Madd_a_cy_28_Q
);
a_28_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X17Y30"
)
port map (
IA => a_28_CY0F_5516,
IB => a_28_CY0F_5516,
SEL => a_28_CYSELF_5505,
O => a_28_CYMUXF2_5500
);
a_28_CYINIT : X_BUF
generic map(
LOC => "SLICE_X17Y30",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_cy_27_Q,
O => a_28_CYINIT_5517
);
a_28_CY0F : X_BUF
generic map(
LOC => "SLICE_X17Y30",
PATHPULSE => 638 ps
)
port map (
I => Sh92,
O => a_28_CY0F_5516
);
a_28_CYSELF : X_BUF
generic map(
LOC => "SLICE_X17Y30",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(28),
O => a_28_CYSELF_5505
);
a_28_YUSED : X_BUF
generic map(
LOC => "SLICE_X17Y30",
PATHPULSE => 638 ps
)
port map (
I => a_28_XORG_5507,
O => a(29)
);
a_28_XORG : X_XOR2
generic map(
LOC => "SLICE_X17Y30"
)
port map (
I0 => Madd_a_cy_28_Q,
I1 => Madd_a_lut(29),
O => a_28_XORG_5507
);
a_28_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X17Y30",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_cy_27_Q,
O => a_28_FASTCARRY_5502
);
a_28_CYAND : X_AND2
generic map(
LOC => "SLICE_X17Y30"
)
port map (
I0 => a_28_CYSELG_5493,
I1 => a_28_CYSELF_5505,
O => a_28_CYAND_5503
);
a_28_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X17Y30"
)
port map (
IA => a_28_CYMUXG2_5501,
IB => a_28_FASTCARRY_5502,
SEL => a_28_CYAND_5503,
O => a_28_CYMUXFAST_5504
);
a_28_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X17Y30"
)
port map (
IA => a_28_CY0G_5499,
IB => a_28_CYMUXF2_5500,
SEL => a_28_CYSELG_5493,
O => a_28_CYMUXG2_5501
);
a_28_CY0G : X_BUF
generic map(
LOC => "SLICE_X17Y30",
PATHPULSE => 638 ps
)
port map (
I => Sh93,
O => a_28_CY0G_5499
);
a_28_CYSELG : X_BUF
generic map(
LOC => "SLICE_X17Y30",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(29),
O => a_28_CYSELG_5493
);
a_30_XUSED : X_BUF
generic map(
LOC => "SLICE_X17Y31",
PATHPULSE => 638 ps
)
port map (
I => a_30_XORF_5551,
O => a(30)
);
a_30_XORF : X_XOR2
generic map(
LOC => "SLICE_X17Y31"
)
port map (
I0 => a_30_CYINIT_5550,
I1 => Madd_a_lut(30),
O => a_30_XORF_5551
);
a_30_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X17Y31"
)
port map (
IA => a_30_CY0F_5549,
IB => a_30_CYINIT_5550,
SEL => a_30_CYSELF_5543,
O => Madd_a_cy_30_Q
);
a_30_CYINIT : X_BUF
generic map(
LOC => "SLICE_X17Y31",
PATHPULSE => 638 ps
)
port map (
I => a_28_CYMUXFAST_5504,
O => a_30_CYINIT_5550
);
a_30_CY0F : X_BUF
generic map(
LOC => "SLICE_X17Y31",
PATHPULSE => 638 ps
)
port map (
I => Sh94,
O => a_30_CY0F_5549
);
a_30_CYSELF : X_BUF
generic map(
LOC => "SLICE_X17Y31",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(30),
O => a_30_CYSELF_5543
);
a_30_YUSED : X_BUF
generic map(
LOC => "SLICE_X17Y31",
PATHPULSE => 638 ps
)
port map (
I => a_30_XORG_5539,
O => a(31)
);
a_30_XORG : X_XOR2
generic map(
LOC => "SLICE_X17Y31"
)
port map (
I0 => Madd_a_cy_30_Q,
I1 => Madd_a_lut(31),
O => a_30_XORG_5539
);
Madd_b_lut_0_Q : X_LUT4
generic map(
INIT => X"6666",
LOC => "SLICE_X21Y12"
)
port map (
ADR0 => Mrom_b_rom0000_0,
ADR1 => Sh160,
ADR2 => VCC,
ADR3 => VCC,
O => Madd_b_lut(0)
);
b_0_XORF : X_XOR2
generic map(
LOC => "SLICE_X21Y12"
)
port map (
I0 => b_0_CYINIT_5588,
I1 => Madd_b_lut(0),
O => b_0_XORF_5589
);
b_0_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X21Y12"
)
port map (
IA => b_0_CY0F_5587,
IB => b_0_CYINIT_5588,
SEL => b_0_CYSELF_5579,
O => Madd_b_cy_0_Q
);
b_0_CYINIT : X_BUF
generic map(
LOC => "SLICE_X21Y12",
PATHPULSE => 638 ps
)
port map (
I => b_0_BXINV_5577,
O => b_0_CYINIT_5588
);
b_0_CY0F : X_BUF
generic map(
LOC => "SLICE_X21Y12",
PATHPULSE => 638 ps
)
port map (
I => Sh160,
O => b_0_CY0F_5587
);
b_0_CYSELF : X_BUF
generic map(
LOC => "SLICE_X21Y12",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(0),
O => b_0_CYSELF_5579
);
b_0_BXINV : X_BUF
generic map(
LOC => "SLICE_X21Y12",
PATHPULSE => 638 ps
)
port map (
I => '0',
O => b_0_BXINV_5577
);
b_0_YUSED : X_BUF
generic map(
LOC => "SLICE_X21Y12",
PATHPULSE => 638 ps
)
port map (
I => b_0_XORG_5575,
O => b_1_Q
);
b_0_XORG : X_XOR2
generic map(
LOC => "SLICE_X21Y12"
)
port map (
I0 => Madd_b_cy_0_Q,
I1 => Madd_b_lut(1),
O => b_0_XORG_5575
);
b_0_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X21Y12",
PATHPULSE => 638 ps
)
port map (
I => b_0_CYMUXG_5574,
O => Madd_b_cy_1_Q
);
b_0_CYMUXG : X_MUX2
generic map(
LOC => "SLICE_X21Y12"
)
port map (
IA => b_0_CY0G_5572,
IB => Madd_b_cy_0_Q,
SEL => b_0_CYSELG_5566,
O => b_0_CYMUXG_5574
);
b_0_CY0G : X_BUF
generic map(
LOC => "SLICE_X21Y12",
PATHPULSE => 638 ps
)
port map (
I => Sh161,
O => b_0_CY0G_5572
);
b_0_CYSELG : X_BUF
generic map(
LOC => "SLICE_X21Y12",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(1),
O => b_0_CYSELG_5566
);
b_2_XUSED : X_BUF
generic map(
LOC => "SLICE_X21Y13",
PATHPULSE => 638 ps
)
port map (
I => b_2_XORF_5628,
O => b_2_Q
);
b_2_XORF : X_XOR2
generic map(
LOC => "SLICE_X21Y13"
)
port map (
I0 => b_2_CYINIT_5627,
I1 => Madd_b_lut(2),
O => b_2_XORF_5628
);
b_2_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X21Y13"
)
port map (
IA => b_2_CY0F_5626,
IB => b_2_CYINIT_5627,
SEL => b_2_CYSELF_5616,
O => Madd_b_cy_2_Q
);
b_2_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X21Y13"
)
port map (
IA => b_2_CY0F_5626,
IB => b_2_CY0F_5626,
SEL => b_2_CYSELF_5616,
O => b_2_CYMUXF2_5611
);
b_2_CYINIT : X_BUF
generic map(
LOC => "SLICE_X21Y13",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_cy_1_Q,
O => b_2_CYINIT_5627
);
b_2_CY0F : X_BUF
generic map(
LOC => "SLICE_X21Y13",
PATHPULSE => 638 ps
)
port map (
I => Sh162,
O => b_2_CY0F_5626
);
b_2_CYSELF : X_BUF
generic map(
LOC => "SLICE_X21Y13",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(2),
O => b_2_CYSELF_5616
);
b_2_YUSED : X_BUF
generic map(
LOC => "SLICE_X21Y13",
PATHPULSE => 638 ps
)
port map (
I => b_2_XORG_5618,
O => b_3_Q
);
b_2_XORG : X_XOR2
generic map(
LOC => "SLICE_X21Y13"
)
port map (
I0 => Madd_b_cy_2_Q,
I1 => Madd_b_lut(3),
O => b_2_XORG_5618
);
b_2_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X21Y13",
PATHPULSE => 638 ps
)
port map (
I => b_2_CYMUXFAST_5615,
O => Madd_b_cy_3_Q
);
b_2_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X21Y13",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_cy_1_Q,
O => b_2_FASTCARRY_5613
);
b_2_CYAND : X_AND2
generic map(
LOC => "SLICE_X21Y13"
)
port map (
I0 => b_2_CYSELG_5604,
I1 => b_2_CYSELF_5616,
O => b_2_CYAND_5614
);
b_2_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X21Y13"
)
port map (
IA => b_2_CYMUXG2_5612,
IB => b_2_FASTCARRY_5613,
SEL => b_2_CYAND_5614,
O => b_2_CYMUXFAST_5615
);
b_2_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X21Y13"
)
port map (
IA => b_2_CY0G_5610,
IB => b_2_CYMUXF2_5611,
SEL => b_2_CYSELG_5604,
O => b_2_CYMUXG2_5612
);
b_2_CY0G : X_BUF
generic map(
LOC => "SLICE_X21Y13",
PATHPULSE => 638 ps
)
port map (
I => Sh163,
O => b_2_CY0G_5610
);
b_2_CYSELG : X_BUF
generic map(
LOC => "SLICE_X21Y13",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(3),
O => b_2_CYSELG_5604
);
Madd_b_lut_5_Q : X_LUT4
generic map(
INIT => X"396C",
LOC => "SLICE_X21Y14"
)
port map (
ADR0 => a(4),
ADR1 => Mrom_b_rom00005_0,
ADR2 => Sh149,
ADR3 => Sh133,
O => Madd_b_lut(5)
);
b_4_XUSED : X_BUF
generic map(
LOC => "SLICE_X21Y14",
PATHPULSE => 638 ps
)
port map (
I => b_4_XORF_5669,
O => b_4_Q
);
b_4_XORF : X_XOR2
generic map(
LOC => "SLICE_X21Y14"
)
port map (
I0 => b_4_CYINIT_5668,
I1 => Madd_b_lut(4),
O => b_4_XORF_5669
);
b_4_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X21Y14"
)
port map (
IA => b_4_CY0F_5667,
IB => b_4_CYINIT_5668,
SEL => b_4_CYSELF_5656,
O => Madd_b_cy_4_Q
);
b_4_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X21Y14"
)
port map (
IA => b_4_CY0F_5667,
IB => b_4_CY0F_5667,
SEL => b_4_CYSELF_5656,
O => b_4_CYMUXF2_5651
);
b_4_CYINIT : X_BUF
generic map(
LOC => "SLICE_X21Y14",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_cy_3_Q,
O => b_4_CYINIT_5668
);
b_4_CY0F : X_BUF
generic map(
LOC => "SLICE_X21Y14",
PATHPULSE => 638 ps
)
port map (
I => Sh164,
O => b_4_CY0F_5667
);
b_4_CYSELF : X_BUF
generic map(
LOC => "SLICE_X21Y14",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(4),
O => b_4_CYSELF_5656
);
b_4_YUSED : X_BUF
generic map(
LOC => "SLICE_X21Y14",
PATHPULSE => 638 ps
)
port map (
I => b_4_XORG_5658,
O => b_5_Q
);
b_4_XORG : X_XOR2
generic map(
LOC => "SLICE_X21Y14"
)
port map (
I0 => Madd_b_cy_4_Q,
I1 => Madd_b_lut(5),
O => b_4_XORG_5658
);
b_4_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X21Y14",
PATHPULSE => 638 ps
)
port map (
I => b_4_CYMUXFAST_5655,
O => Madd_b_cy_5_Q
);
b_4_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X21Y14",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_cy_3_Q,
O => b_4_FASTCARRY_5653
);
b_4_CYAND : X_AND2
generic map(
LOC => "SLICE_X21Y14"
)
port map (
I0 => b_4_CYSELG_5644,
I1 => b_4_CYSELF_5656,
O => b_4_CYAND_5654
);
b_4_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X21Y14"
)
port map (
IA => b_4_CYMUXG2_5652,
IB => b_4_FASTCARRY_5653,
SEL => b_4_CYAND_5654,
O => b_4_CYMUXFAST_5655
);
b_4_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X21Y14"
)
port map (
IA => b_4_CY0G_5650,
IB => b_4_CYMUXF2_5651,
SEL => b_4_CYSELG_5644,
O => b_4_CYMUXG2_5652
);
b_4_CY0G : X_BUF
generic map(
LOC => "SLICE_X21Y14",
PATHPULSE => 638 ps
)
port map (
I => Sh165,
O => b_4_CY0G_5650
);
b_4_CYSELG : X_BUF
generic map(
LOC => "SLICE_X21Y14",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(5),
O => b_4_CYSELG_5644
);
b_6_XUSED : X_BUF
generic map(
LOC => "SLICE_X21Y15",
PATHPULSE => 638 ps
)
port map (
I => b_6_XORF_5712,
O => b_6_Q
);
b_6_XORF : X_XOR2
generic map(
LOC => "SLICE_X21Y15"
)
port map (
I0 => b_6_CYINIT_5711,
I1 => Madd_b_lut(6),
O => b_6_XORF_5712
);
b_6_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X21Y15"
)
port map (
IA => b_6_CY0F_5710,
IB => b_6_CYINIT_5711,
SEL => b_6_CYSELF_5699,
O => Madd_b_cy_6_Q
);
b_6_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X21Y15"
)
port map (
IA => b_6_CY0F_5710,
IB => b_6_CY0F_5710,
SEL => b_6_CYSELF_5699,
O => b_6_CYMUXF2_5694
);
b_6_CYINIT : X_BUF
generic map(
LOC => "SLICE_X21Y15",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_cy_5_Q,
O => b_6_CYINIT_5711
);
b_6_CY0F : X_BUF
generic map(
LOC => "SLICE_X21Y15",
PATHPULSE => 638 ps
)
port map (
I => Sh166,
O => b_6_CY0F_5710
);
b_6_CYSELF : X_BUF
generic map(
LOC => "SLICE_X21Y15",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(6),
O => b_6_CYSELF_5699
);
b_6_YUSED : X_BUF
generic map(
LOC => "SLICE_X21Y15",
PATHPULSE => 638 ps
)
port map (
I => b_6_XORG_5701,
O => b_7_Q
);
b_6_XORG : X_XOR2
generic map(
LOC => "SLICE_X21Y15"
)
port map (
I0 => Madd_b_cy_6_Q,
I1 => Madd_b_lut(7),
O => b_6_XORG_5701
);
b_6_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X21Y15",
PATHPULSE => 638 ps
)
port map (
I => b_6_CYMUXFAST_5698,
O => Madd_b_cy_7_Q
);
b_6_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X21Y15",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_cy_5_Q,
O => b_6_FASTCARRY_5696
);
b_6_CYAND : X_AND2
generic map(
LOC => "SLICE_X21Y15"
)
port map (
I0 => b_6_CYSELG_5687,
I1 => b_6_CYSELF_5699,
O => b_6_CYAND_5697
);
b_6_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X21Y15"
)
port map (
IA => b_6_CYMUXG2_5695,
IB => b_6_FASTCARRY_5696,
SEL => b_6_CYAND_5697,
O => b_6_CYMUXFAST_5698
);
b_6_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X21Y15"
)
port map (
IA => b_6_CY0G_5693,
IB => b_6_CYMUXF2_5694,
SEL => b_6_CYSELG_5687,
O => b_6_CYMUXG2_5695
);
b_6_CY0G : X_BUF
generic map(
LOC => "SLICE_X21Y15",
PATHPULSE => 638 ps
)
port map (
I => Sh167,
O => b_6_CY0G_5693
);
b_6_CYSELG : X_BUF
generic map(
LOC => "SLICE_X21Y15",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(7),
O => b_6_CYSELG_5687
);
b_8_XORF : X_XOR2
generic map(
LOC => "SLICE_X21Y16"
)
port map (
I0 => b_8_CYINIT_5754,
I1 => Madd_b_lut(8),
O => b_8_XORF_5755
);
b_8_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X21Y16"
)
port map (
IA => b_8_CY0F_5753,
IB => b_8_CYINIT_5754,
SEL => b_8_CYSELF_5742,
O => Madd_b_cy_8_Q
);
b_8_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X21Y16"
)
port map (
IA => b_8_CY0F_5753,
IB => b_8_CY0F_5753,
SEL => b_8_CYSELF_5742,
O => b_8_CYMUXF2_5737
);
b_8_CYINIT : X_BUF
generic map(
LOC => "SLICE_X21Y16",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_cy_7_Q,
O => b_8_CYINIT_5754
);
b_8_CY0F : X_BUF
generic map(
LOC => "SLICE_X21Y16",
PATHPULSE => 638 ps
)
port map (
I => Sh168,
O => b_8_CY0F_5753
);
b_8_CYSELF : X_BUF
generic map(
LOC => "SLICE_X21Y16",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(8),
O => b_8_CYSELF_5742
);
b_8_XORG : X_XOR2
generic map(
LOC => "SLICE_X21Y16"
)
port map (
I0 => Madd_b_cy_8_Q,
I1 => Madd_b_lut(9),
O => b_8_XORG_5744
);
b_8_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X21Y16",
PATHPULSE => 638 ps
)
port map (
I => b_8_CYMUXFAST_5741,
O => Madd_b_cy_9_Q
);
b_8_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X21Y16",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_cy_7_Q,
O => b_8_FASTCARRY_5739
);
b_8_CYAND : X_AND2
generic map(
LOC => "SLICE_X21Y16"
)
port map (
I0 => b_8_CYSELG_5730,
I1 => b_8_CYSELF_5742,
O => b_8_CYAND_5740
);
b_8_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X21Y16"
)
port map (
IA => b_8_CYMUXG2_5738,
IB => b_8_FASTCARRY_5739,
SEL => b_8_CYAND_5740,
O => b_8_CYMUXFAST_5741
);
b_8_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X21Y16"
)
port map (
IA => b_8_CY0G_5736,
IB => b_8_CYMUXF2_5737,
SEL => b_8_CYSELG_5730,
O => b_8_CYMUXG2_5738
);
b_8_CY0G : X_BUF
generic map(
LOC => "SLICE_X21Y16",
PATHPULSE => 638 ps
)
port map (
I => Sh169,
O => b_8_CY0G_5736
);
b_8_CYSELG : X_BUF
generic map(
LOC => "SLICE_X21Y16",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(9),
O => b_8_CYSELG_5730
);
b_10_XORF : X_XOR2
generic map(
LOC => "SLICE_X21Y17"
)
port map (
I0 => b_10_CYINIT_5797,
I1 => Madd_b_lut(10),
O => b_10_XORF_5798
);
b_10_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X21Y17"
)
port map (
IA => b_10_CY0F_5796,
IB => b_10_CYINIT_5797,
SEL => b_10_CYSELF_5785,
O => Madd_b_cy_10_Q
);
b_10_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X21Y17"
)
port map (
IA => b_10_CY0F_5796,
IB => b_10_CY0F_5796,
SEL => b_10_CYSELF_5785,
O => b_10_CYMUXF2_5780
);
b_10_CYINIT : X_BUF
generic map(
LOC => "SLICE_X21Y17",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_cy_9_Q,
O => b_10_CYINIT_5797
);
b_10_CY0F : X_BUF
generic map(
LOC => "SLICE_X21Y17",
PATHPULSE => 638 ps
)
port map (
I => Sh170,
O => b_10_CY0F_5796
);
b_10_CYSELF : X_BUF
generic map(
LOC => "SLICE_X21Y17",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(10),
O => b_10_CYSELF_5785
);
b_10_YUSED : X_BUF
generic map(
LOC => "SLICE_X21Y17",
PATHPULSE => 638 ps
)
port map (
I => b_10_XORG_5787,
O => b_11_Q
);
b_10_XORG : X_XOR2
generic map(
LOC => "SLICE_X21Y17"
)
port map (
I0 => Madd_b_cy_10_Q,
I1 => Madd_b_lut(11),
O => b_10_XORG_5787
);
b_10_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X21Y17",
PATHPULSE => 638 ps
)
port map (
I => b_10_CYMUXFAST_5784,
O => Madd_b_cy_11_Q
);
b_10_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X21Y17",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_cy_9_Q,
O => b_10_FASTCARRY_5782
);
b_10_CYAND : X_AND2
generic map(
LOC => "SLICE_X21Y17"
)
port map (
I0 => b_10_CYSELG_5773,
I1 => b_10_CYSELF_5785,
O => b_10_CYAND_5783
);
b_10_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X21Y17"
)
port map (
IA => b_10_CYMUXG2_5781,
IB => b_10_FASTCARRY_5782,
SEL => b_10_CYAND_5783,
O => b_10_CYMUXFAST_5784
);
b_10_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X21Y17"
)
port map (
IA => b_10_CY0G_5779,
IB => b_10_CYMUXF2_5780,
SEL => b_10_CYSELG_5773,
O => b_10_CYMUXG2_5781
);
b_10_CY0G : X_BUF
generic map(
LOC => "SLICE_X21Y17",
PATHPULSE => 638 ps
)
port map (
I => Sh171,
O => b_10_CY0G_5779
);
b_10_CYSELG : X_BUF
generic map(
LOC => "SLICE_X21Y17",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(11),
O => b_10_CYSELG_5773
);
b_12_XUSED : X_BUF
generic map(
LOC => "SLICE_X21Y18",
PATHPULSE => 638 ps
)
port map (
I => b_12_XORF_5841,
O => b_12_Q
);
b_12_XORF : X_XOR2
generic map(
LOC => "SLICE_X21Y18"
)
port map (
I0 => b_12_CYINIT_5840,
I1 => Madd_b_lut(12),
O => b_12_XORF_5841
);
b_12_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X21Y18"
)
port map (
IA => b_12_CY0F_5839,
IB => b_12_CYINIT_5840,
SEL => b_12_CYSELF_5828,
O => Madd_b_cy_12_Q
);
b_12_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X21Y18"
)
port map (
IA => b_12_CY0F_5839,
IB => b_12_CY0F_5839,
SEL => b_12_CYSELF_5828,
O => b_12_CYMUXF2_5823
);
b_12_CYINIT : X_BUF
generic map(
LOC => "SLICE_X21Y18",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_cy_11_Q,
O => b_12_CYINIT_5840
);
b_12_CY0F : X_BUF
generic map(
LOC => "SLICE_X21Y18",
PATHPULSE => 638 ps
)
port map (
I => Sh172,
O => b_12_CY0F_5839
);
b_12_CYSELF : X_BUF
generic map(
LOC => "SLICE_X21Y18",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(12),
O => b_12_CYSELF_5828
);
b_12_YUSED : X_BUF
generic map(
LOC => "SLICE_X21Y18",
PATHPULSE => 638 ps
)
port map (
I => b_12_XORG_5830,
O => b_13_Q
);
b_12_XORG : X_XOR2
generic map(
LOC => "SLICE_X21Y18"
)
port map (
I0 => Madd_b_cy_12_Q,
I1 => Madd_b_lut(13),
O => b_12_XORG_5830
);
b_12_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X21Y18",
PATHPULSE => 638 ps
)
port map (
I => b_12_CYMUXFAST_5827,
O => Madd_b_cy_13_Q
);
b_12_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X21Y18",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_cy_11_Q,
O => b_12_FASTCARRY_5825
);
b_12_CYAND : X_AND2
generic map(
LOC => "SLICE_X21Y18"
)
port map (
I0 => b_12_CYSELG_5816,
I1 => b_12_CYSELF_5828,
O => b_12_CYAND_5826
);
b_12_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X21Y18"
)
port map (
IA => b_12_CYMUXG2_5824,
IB => b_12_FASTCARRY_5825,
SEL => b_12_CYAND_5826,
O => b_12_CYMUXFAST_5827
);
b_12_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X21Y18"
)
port map (
IA => b_12_CY0G_5822,
IB => b_12_CYMUXF2_5823,
SEL => b_12_CYSELG_5816,
O => b_12_CYMUXG2_5824
);
b_12_CY0G : X_BUF
generic map(
LOC => "SLICE_X21Y18",
PATHPULSE => 638 ps
)
port map (
I => Sh173,
O => b_12_CY0G_5822
);
b_12_CYSELG : X_BUF
generic map(
LOC => "SLICE_X21Y18",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(13),
O => b_12_CYSELG_5816
);
b_14_XUSED : X_BUF
generic map(
LOC => "SLICE_X21Y19",
PATHPULSE => 638 ps
)
port map (
I => b_14_XORF_5882,
O => b_14_Q
);
b_14_XORF : X_XOR2
generic map(
LOC => "SLICE_X21Y19"
)
port map (
I0 => b_14_CYINIT_5881,
I1 => Madd_b_lut(14),
O => b_14_XORF_5882
);
b_14_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X21Y19"
)
port map (
IA => b_14_CY0F_5880,
IB => b_14_CYINIT_5881,
SEL => b_14_CYSELF_5869,
O => Madd_b_cy_14_Q
);
b_14_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X21Y19"
)
port map (
IA => b_14_CY0F_5880,
IB => b_14_CY0F_5880,
SEL => b_14_CYSELF_5869,
O => b_14_CYMUXF2_5864
);
b_14_CYINIT : X_BUF
generic map(
LOC => "SLICE_X21Y19",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_cy_13_Q,
O => b_14_CYINIT_5881
);
b_14_CY0F : X_BUF
generic map(
LOC => "SLICE_X21Y19",
PATHPULSE => 638 ps
)
port map (
I => Sh174,
O => b_14_CY0F_5880
);
b_14_CYSELF : X_BUF
generic map(
LOC => "SLICE_X21Y19",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(14),
O => b_14_CYSELF_5869
);
b_14_YUSED : X_BUF
generic map(
LOC => "SLICE_X21Y19",
PATHPULSE => 638 ps
)
port map (
I => b_14_XORG_5871,
O => b_15_Q
);
b_14_XORG : X_XOR2
generic map(
LOC => "SLICE_X21Y19"
)
port map (
I0 => Madd_b_cy_14_Q,
I1 => Madd_b_lut(15),
O => b_14_XORG_5871
);
b_14_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X21Y19",
PATHPULSE => 638 ps
)
port map (
I => b_14_CYMUXFAST_5868,
O => Madd_b_cy_15_Q
);
b_14_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X21Y19",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_cy_13_Q,
O => b_14_FASTCARRY_5866
);
b_14_CYAND : X_AND2
generic map(
LOC => "SLICE_X21Y19"
)
port map (
I0 => b_14_CYSELG_5857,
I1 => b_14_CYSELF_5869,
O => b_14_CYAND_5867
);
b_14_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X21Y19"
)
port map (
IA => b_14_CYMUXG2_5865,
IB => b_14_FASTCARRY_5866,
SEL => b_14_CYAND_5867,
O => b_14_CYMUXFAST_5868
);
b_14_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X21Y19"
)
port map (
IA => b_14_CY0G_5863,
IB => b_14_CYMUXF2_5864,
SEL => b_14_CYSELG_5857,
O => b_14_CYMUXG2_5865
);
b_14_CY0G : X_BUF
generic map(
LOC => "SLICE_X21Y19",
PATHPULSE => 638 ps
)
port map (
I => Sh175,
O => b_14_CY0G_5863
);
b_14_CYSELG : X_BUF
generic map(
LOC => "SLICE_X21Y19",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(15),
O => b_14_CYSELG_5857
);
b_16_XUSED : X_BUF
generic map(
LOC => "SLICE_X21Y20",
PATHPULSE => 638 ps
)
port map (
I => b_16_XORF_5925,
O => b_16_Q
);
b_16_XORF : X_XOR2
generic map(
LOC => "SLICE_X21Y20"
)
port map (
I0 => b_16_CYINIT_5924,
I1 => Madd_b_lut(16),
O => b_16_XORF_5925
);
b_16_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X21Y20"
)
port map (
IA => b_16_CY0F_5923,
IB => b_16_CYINIT_5924,
SEL => b_16_CYSELF_5912,
O => Madd_b_cy_16_Q
);
b_16_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X21Y20"
)
port map (
IA => b_16_CY0F_5923,
IB => b_16_CY0F_5923,
SEL => b_16_CYSELF_5912,
O => b_16_CYMUXF2_5907
);
b_16_CYINIT : X_BUF
generic map(
LOC => "SLICE_X21Y20",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_cy_15_Q,
O => b_16_CYINIT_5924
);
b_16_CY0F : X_BUF
generic map(
LOC => "SLICE_X21Y20",
PATHPULSE => 638 ps
)
port map (
I => Sh176,
O => b_16_CY0F_5923
);
b_16_CYSELF : X_BUF
generic map(
LOC => "SLICE_X21Y20",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(16),
O => b_16_CYSELF_5912
);
b_16_YUSED : X_BUF
generic map(
LOC => "SLICE_X21Y20",
PATHPULSE => 638 ps
)
port map (
I => b_16_XORG_5914,
O => b_17_Q
);
b_16_XORG : X_XOR2
generic map(
LOC => "SLICE_X21Y20"
)
port map (
I0 => Madd_b_cy_16_Q,
I1 => Madd_b_lut(17),
O => b_16_XORG_5914
);
b_16_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X21Y20",
PATHPULSE => 638 ps
)
port map (
I => b_16_CYMUXFAST_5911,
O => Madd_b_cy_17_Q
);
b_16_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X21Y20",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_cy_15_Q,
O => b_16_FASTCARRY_5909
);
b_16_CYAND : X_AND2
generic map(
LOC => "SLICE_X21Y20"
)
port map (
I0 => b_16_CYSELG_5900,
I1 => b_16_CYSELF_5912,
O => b_16_CYAND_5910
);
b_16_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X21Y20"
)
port map (
IA => b_16_CYMUXG2_5908,
IB => b_16_FASTCARRY_5909,
SEL => b_16_CYAND_5910,
O => b_16_CYMUXFAST_5911
);
b_16_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X21Y20"
)
port map (
IA => b_16_CY0G_5906,
IB => b_16_CYMUXF2_5907,
SEL => b_16_CYSELG_5900,
O => b_16_CYMUXG2_5908
);
b_16_CY0G : X_BUF
generic map(
LOC => "SLICE_X21Y20",
PATHPULSE => 638 ps
)
port map (
I => Sh177,
O => b_16_CY0G_5906
);
b_16_CYSELG : X_BUF
generic map(
LOC => "SLICE_X21Y20",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(17),
O => b_16_CYSELG_5900
);
b_18_XUSED : X_BUF
generic map(
LOC => "SLICE_X21Y21",
PATHPULSE => 638 ps
)
port map (
I => b_18_XORF_5966,
O => b_18_Q
);
b_18_XORF : X_XOR2
generic map(
LOC => "SLICE_X21Y21"
)
port map (
I0 => b_18_CYINIT_5965,
I1 => Madd_b_lut(18),
O => b_18_XORF_5966
);
b_18_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X21Y21"
)
port map (
IA => b_18_CY0F_5964,
IB => b_18_CYINIT_5965,
SEL => b_18_CYSELF_5954,
O => Madd_b_cy_18_Q
);
b_18_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X21Y21"
)
port map (
IA => b_18_CY0F_5964,
IB => b_18_CY0F_5964,
SEL => b_18_CYSELF_5954,
O => b_18_CYMUXF2_5949
);
b_18_CYINIT : X_BUF
generic map(
LOC => "SLICE_X21Y21",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_cy_17_Q,
O => b_18_CYINIT_5965
);
b_18_CY0F : X_BUF
generic map(
LOC => "SLICE_X21Y21",
PATHPULSE => 638 ps
)
port map (
I => Sh178,
O => b_18_CY0F_5964
);
b_18_CYSELF : X_BUF
generic map(
LOC => "SLICE_X21Y21",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(18),
O => b_18_CYSELF_5954
);
b_18_YUSED : X_BUF
generic map(
LOC => "SLICE_X21Y21",
PATHPULSE => 638 ps
)
port map (
I => b_18_XORG_5956,
O => b_19_Q
);
b_18_XORG : X_XOR2
generic map(
LOC => "SLICE_X21Y21"
)
port map (
I0 => Madd_b_cy_18_Q,
I1 => Madd_b_lut(19),
O => b_18_XORG_5956
);
b_18_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X21Y21",
PATHPULSE => 638 ps
)
port map (
I => b_18_CYMUXFAST_5953,
O => Madd_b_cy_19_Q
);
b_18_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X21Y21",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_cy_17_Q,
O => b_18_FASTCARRY_5951
);
b_18_CYAND : X_AND2
generic map(
LOC => "SLICE_X21Y21"
)
port map (
I0 => b_18_CYSELG_5942,
I1 => b_18_CYSELF_5954,
O => b_18_CYAND_5952
);
b_18_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X21Y21"
)
port map (
IA => b_18_CYMUXG2_5950,
IB => b_18_FASTCARRY_5951,
SEL => b_18_CYAND_5952,
O => b_18_CYMUXFAST_5953
);
b_18_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X21Y21"
)
port map (
IA => b_18_CY0G_5948,
IB => b_18_CYMUXF2_5949,
SEL => b_18_CYSELG_5942,
O => b_18_CYMUXG2_5950
);
b_18_CY0G : X_BUF
generic map(
LOC => "SLICE_X21Y21",
PATHPULSE => 638 ps
)
port map (
I => Sh179,
O => b_18_CY0G_5948
);
b_18_CYSELG : X_BUF
generic map(
LOC => "SLICE_X21Y21",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(19),
O => b_18_CYSELG_5942
);
b_20_XUSED : X_BUF
generic map(
LOC => "SLICE_X21Y22",
PATHPULSE => 638 ps
)
port map (
I => b_20_XORF_6009,
O => b_20_Q
);
b_20_XORF : X_XOR2
generic map(
LOC => "SLICE_X21Y22"
)
port map (
I0 => b_20_CYINIT_6008,
I1 => Madd_b_lut(20),
O => b_20_XORF_6009
);
b_20_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X21Y22"
)
port map (
IA => b_20_CY0F_6007,
IB => b_20_CYINIT_6008,
SEL => b_20_CYSELF_5996,
O => Madd_b_cy_20_Q
);
b_20_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X21Y22"
)
port map (
IA => b_20_CY0F_6007,
IB => b_20_CY0F_6007,
SEL => b_20_CYSELF_5996,
O => b_20_CYMUXF2_5991
);
b_20_CYINIT : X_BUF
generic map(
LOC => "SLICE_X21Y22",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_cy_19_Q,
O => b_20_CYINIT_6008
);
b_20_CY0F : X_BUF
generic map(
LOC => "SLICE_X21Y22",
PATHPULSE => 638 ps
)
port map (
I => Sh180,
O => b_20_CY0F_6007
);
b_20_CYSELF : X_BUF
generic map(
LOC => "SLICE_X21Y22",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(20),
O => b_20_CYSELF_5996
);
b_20_YUSED : X_BUF
generic map(
LOC => "SLICE_X21Y22",
PATHPULSE => 638 ps
)
port map (
I => b_20_XORG_5998,
O => b_21_Q
);
b_20_XORG : X_XOR2
generic map(
LOC => "SLICE_X21Y22"
)
port map (
I0 => Madd_b_cy_20_Q,
I1 => Madd_b_lut(21),
O => b_20_XORG_5998
);
b_20_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X21Y22",
PATHPULSE => 638 ps
)
port map (
I => b_20_CYMUXFAST_5995,
O => Madd_b_cy_21_Q
);
b_20_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X21Y22",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_cy_19_Q,
O => b_20_FASTCARRY_5993
);
b_20_CYAND : X_AND2
generic map(
LOC => "SLICE_X21Y22"
)
port map (
I0 => b_20_CYSELG_5984,
I1 => b_20_CYSELF_5996,
O => b_20_CYAND_5994
);
b_20_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X21Y22"
)
port map (
IA => b_20_CYMUXG2_5992,
IB => b_20_FASTCARRY_5993,
SEL => b_20_CYAND_5994,
O => b_20_CYMUXFAST_5995
);
b_20_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X21Y22"
)
port map (
IA => b_20_CY0G_5990,
IB => b_20_CYMUXF2_5991,
SEL => b_20_CYSELG_5984,
O => b_20_CYMUXG2_5992
);
b_20_CY0G : X_BUF
generic map(
LOC => "SLICE_X21Y22",
PATHPULSE => 638 ps
)
port map (
I => Sh181,
O => b_20_CY0G_5990
);
b_20_CYSELG : X_BUF
generic map(
LOC => "SLICE_X21Y22",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(21),
O => b_20_CYSELG_5984
);
b_22_XUSED : X_BUF
generic map(
LOC => "SLICE_X21Y23",
PATHPULSE => 638 ps
)
port map (
I => b_22_XORF_6052,
O => b_22_Q
);
b_22_XORF : X_XOR2
generic map(
LOC => "SLICE_X21Y23"
)
port map (
I0 => b_22_CYINIT_6051,
I1 => Madd_b_lut(22),
O => b_22_XORF_6052
);
b_22_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X21Y23"
)
port map (
IA => b_22_CY0F_6050,
IB => b_22_CYINIT_6051,
SEL => b_22_CYSELF_6039,
O => Madd_b_cy_22_Q
);
b_22_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X21Y23"
)
port map (
IA => b_22_CY0F_6050,
IB => b_22_CY0F_6050,
SEL => b_22_CYSELF_6039,
O => b_22_CYMUXF2_6034
);
b_22_CYINIT : X_BUF
generic map(
LOC => "SLICE_X21Y23",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_cy_21_Q,
O => b_22_CYINIT_6051
);
b_22_CY0F : X_BUF
generic map(
LOC => "SLICE_X21Y23",
PATHPULSE => 638 ps
)
port map (
I => Sh182,
O => b_22_CY0F_6050
);
b_22_CYSELF : X_BUF
generic map(
LOC => "SLICE_X21Y23",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(22),
O => b_22_CYSELF_6039
);
b_22_YUSED : X_BUF
generic map(
LOC => "SLICE_X21Y23",
PATHPULSE => 638 ps
)
port map (
I => b_22_XORG_6041,
O => b_23_Q
);
b_22_XORG : X_XOR2
generic map(
LOC => "SLICE_X21Y23"
)
port map (
I0 => Madd_b_cy_22_Q,
I1 => Madd_b_lut(23),
O => b_22_XORG_6041
);
b_22_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X21Y23",
PATHPULSE => 638 ps
)
port map (
I => b_22_CYMUXFAST_6038,
O => Madd_b_cy_23_Q
);
b_22_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X21Y23",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_cy_21_Q,
O => b_22_FASTCARRY_6036
);
b_22_CYAND : X_AND2
generic map(
LOC => "SLICE_X21Y23"
)
port map (
I0 => b_22_CYSELG_6027,
I1 => b_22_CYSELF_6039,
O => b_22_CYAND_6037
);
b_22_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X21Y23"
)
port map (
IA => b_22_CYMUXG2_6035,
IB => b_22_FASTCARRY_6036,
SEL => b_22_CYAND_6037,
O => b_22_CYMUXFAST_6038
);
b_22_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X21Y23"
)
port map (
IA => b_22_CY0G_6033,
IB => b_22_CYMUXF2_6034,
SEL => b_22_CYSELG_6027,
O => b_22_CYMUXG2_6035
);
b_22_CY0G : X_BUF
generic map(
LOC => "SLICE_X21Y23",
PATHPULSE => 638 ps
)
port map (
I => Sh183,
O => b_22_CY0G_6033
);
b_22_CYSELG : X_BUF
generic map(
LOC => "SLICE_X21Y23",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(23),
O => b_22_CYSELG_6027
);
b_24_XUSED : X_BUF
generic map(
LOC => "SLICE_X21Y24",
PATHPULSE => 638 ps
)
port map (
I => b_24_XORF_6093,
O => b_24_Q
);
b_24_XORF : X_XOR2
generic map(
LOC => "SLICE_X21Y24"
)
port map (
I0 => b_24_CYINIT_6092,
I1 => Madd_b_lut(24),
O => b_24_XORF_6093
);
b_24_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X21Y24"
)
port map (
IA => b_24_CY0F_6091,
IB => b_24_CYINIT_6092,
SEL => b_24_CYSELF_6080,
O => Madd_b_cy_24_Q
);
b_24_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X21Y24"
)
port map (
IA => b_24_CY0F_6091,
IB => b_24_CY0F_6091,
SEL => b_24_CYSELF_6080,
O => b_24_CYMUXF2_6075
);
b_24_CYINIT : X_BUF
generic map(
LOC => "SLICE_X21Y24",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_cy_23_Q,
O => b_24_CYINIT_6092
);
b_24_CY0F : X_BUF
generic map(
LOC => "SLICE_X21Y24",
PATHPULSE => 638 ps
)
port map (
I => Sh184,
O => b_24_CY0F_6091
);
b_24_CYSELF : X_BUF
generic map(
LOC => "SLICE_X21Y24",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(24),
O => b_24_CYSELF_6080
);
b_24_YUSED : X_BUF
generic map(
LOC => "SLICE_X21Y24",
PATHPULSE => 638 ps
)
port map (
I => b_24_XORG_6082,
O => b_25_Q
);
b_24_XORG : X_XOR2
generic map(
LOC => "SLICE_X21Y24"
)
port map (
I0 => Madd_b_cy_24_Q,
I1 => Madd_b_lut(25),
O => b_24_XORG_6082
);
b_24_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X21Y24",
PATHPULSE => 638 ps
)
port map (
I => b_24_CYMUXFAST_6079,
O => Madd_b_cy_25_Q
);
b_24_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X21Y24",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_cy_23_Q,
O => b_24_FASTCARRY_6077
);
b_24_CYAND : X_AND2
generic map(
LOC => "SLICE_X21Y24"
)
port map (
I0 => b_24_CYSELG_6068,
I1 => b_24_CYSELF_6080,
O => b_24_CYAND_6078
);
b_24_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X21Y24"
)
port map (
IA => b_24_CYMUXG2_6076,
IB => b_24_FASTCARRY_6077,
SEL => b_24_CYAND_6078,
O => b_24_CYMUXFAST_6079
);
b_24_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X21Y24"
)
port map (
IA => b_24_CY0G_6074,
IB => b_24_CYMUXF2_6075,
SEL => b_24_CYSELG_6068,
O => b_24_CYMUXG2_6076
);
b_24_CY0G : X_BUF
generic map(
LOC => "SLICE_X21Y24",
PATHPULSE => 638 ps
)
port map (
I => Sh185_0,
O => b_24_CY0G_6074
);
b_24_CYSELG : X_BUF
generic map(
LOC => "SLICE_X21Y24",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(25),
O => b_24_CYSELG_6068
);
b_26_XUSED : X_BUF
generic map(
LOC => "SLICE_X21Y25",
PATHPULSE => 638 ps
)
port map (
I => b_26_XORF_6136,
O => b_26_Q
);
b_26_XORF : X_XOR2
generic map(
LOC => "SLICE_X21Y25"
)
port map (
I0 => b_26_CYINIT_6135,
I1 => Madd_b_lut(26),
O => b_26_XORF_6136
);
b_26_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X21Y25"
)
port map (
IA => b_26_CY0F_6134,
IB => b_26_CYINIT_6135,
SEL => b_26_CYSELF_6123,
O => Madd_b_cy_26_Q
);
b_26_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X21Y25"
)
port map (
IA => b_26_CY0F_6134,
IB => b_26_CY0F_6134,
SEL => b_26_CYSELF_6123,
O => b_26_CYMUXF2_6118
);
b_26_CYINIT : X_BUF
generic map(
LOC => "SLICE_X21Y25",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_cy_25_Q,
O => b_26_CYINIT_6135
);
b_26_CY0F : X_BUF
generic map(
LOC => "SLICE_X21Y25",
PATHPULSE => 638 ps
)
port map (
I => Sh186,
O => b_26_CY0F_6134
);
b_26_CYSELF : X_BUF
generic map(
LOC => "SLICE_X21Y25",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(26),
O => b_26_CYSELF_6123
);
b_26_YUSED : X_BUF
generic map(
LOC => "SLICE_X21Y25",
PATHPULSE => 638 ps
)
port map (
I => b_26_XORG_6125,
O => b_27_Q
);
b_26_XORG : X_XOR2
generic map(
LOC => "SLICE_X21Y25"
)
port map (
I0 => Madd_b_cy_26_Q,
I1 => Madd_b_lut(27),
O => b_26_XORG_6125
);
b_26_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X21Y25",
PATHPULSE => 638 ps
)
port map (
I => b_26_CYMUXFAST_6122,
O => Madd_b_cy_27_Q
);
b_26_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X21Y25",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_cy_25_Q,
O => b_26_FASTCARRY_6120
);
b_26_CYAND : X_AND2
generic map(
LOC => "SLICE_X21Y25"
)
port map (
I0 => b_26_CYSELG_6111,
I1 => b_26_CYSELF_6123,
O => b_26_CYAND_6121
);
b_26_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X21Y25"
)
port map (
IA => b_26_CYMUXG2_6119,
IB => b_26_FASTCARRY_6120,
SEL => b_26_CYAND_6121,
O => b_26_CYMUXFAST_6122
);
b_26_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X21Y25"
)
port map (
IA => b_26_CY0G_6117,
IB => b_26_CYMUXF2_6118,
SEL => b_26_CYSELG_6111,
O => b_26_CYMUXG2_6119
);
b_26_CY0G : X_BUF
generic map(
LOC => "SLICE_X21Y25",
PATHPULSE => 638 ps
)
port map (
I => Sh187,
O => b_26_CY0G_6117
);
b_26_CYSELG : X_BUF
generic map(
LOC => "SLICE_X21Y25",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(27),
O => b_26_CYSELG_6111
);
b_28_XUSED : X_BUF
generic map(
LOC => "SLICE_X21Y26",
PATHPULSE => 638 ps
)
port map (
I => b_28_XORF_6179,
O => b_28_Q
);
b_28_XORF : X_XOR2
generic map(
LOC => "SLICE_X21Y26"
)
port map (
I0 => b_28_CYINIT_6178,
I1 => Madd_b_lut(28),
O => b_28_XORF_6179
);
b_28_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X21Y26"
)
port map (
IA => b_28_CY0F_6177,
IB => b_28_CYINIT_6178,
SEL => b_28_CYSELF_6166,
O => Madd_b_cy_28_Q
);
b_28_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X21Y26"
)
port map (
IA => b_28_CY0F_6177,
IB => b_28_CY0F_6177,
SEL => b_28_CYSELF_6166,
O => b_28_CYMUXF2_6161
);
b_28_CYINIT : X_BUF
generic map(
LOC => "SLICE_X21Y26",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_cy_27_Q,
O => b_28_CYINIT_6178
);
b_28_CY0F : X_BUF
generic map(
LOC => "SLICE_X21Y26",
PATHPULSE => 638 ps
)
port map (
I => Sh188,
O => b_28_CY0F_6177
);
b_28_CYSELF : X_BUF
generic map(
LOC => "SLICE_X21Y26",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(28),
O => b_28_CYSELF_6166
);
b_28_YUSED : X_BUF
generic map(
LOC => "SLICE_X21Y26",
PATHPULSE => 638 ps
)
port map (
I => b_28_XORG_6168,
O => b_29_Q
);
b_28_XORG : X_XOR2
generic map(
LOC => "SLICE_X21Y26"
)
port map (
I0 => Madd_b_cy_28_Q,
I1 => Madd_b_lut(29),
O => b_28_XORG_6168
);
b_28_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X21Y26",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_cy_27_Q,
O => b_28_FASTCARRY_6163
);
b_28_CYAND : X_AND2
generic map(
LOC => "SLICE_X21Y26"
)
port map (
I0 => b_28_CYSELG_6154,
I1 => b_28_CYSELF_6166,
O => b_28_CYAND_6164
);
b_28_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X21Y26"
)
port map (
IA => b_28_CYMUXG2_6162,
IB => b_28_FASTCARRY_6163,
SEL => b_28_CYAND_6164,
O => b_28_CYMUXFAST_6165
);
b_28_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X21Y26"
)
port map (
IA => b_28_CY0G_6160,
IB => b_28_CYMUXF2_6161,
SEL => b_28_CYSELG_6154,
O => b_28_CYMUXG2_6162
);
b_28_CY0G : X_BUF
generic map(
LOC => "SLICE_X21Y26",
PATHPULSE => 638 ps
)
port map (
I => Sh189,
O => b_28_CY0G_6160
);
b_28_CYSELG : X_BUF
generic map(
LOC => "SLICE_X21Y26",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(29),
O => b_28_CYSELG_6154
);
b_30_XUSED : X_BUF
generic map(
LOC => "SLICE_X21Y27",
PATHPULSE => 638 ps
)
port map (
I => b_30_XORF_6212,
O => b_30_Q
);
b_30_XORF : X_XOR2
generic map(
LOC => "SLICE_X21Y27"
)
port map (
I0 => b_30_CYINIT_6211,
I1 => Madd_b_lut(30),
O => b_30_XORF_6212
);
b_30_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X21Y27"
)
port map (
IA => b_30_CY0F_6210,
IB => b_30_CYINIT_6211,
SEL => b_30_CYSELF_6204,
O => Madd_b_cy_30_Q
);
b_30_CYINIT : X_BUF
generic map(
LOC => "SLICE_X21Y27",
PATHPULSE => 638 ps
)
port map (
I => b_28_CYMUXFAST_6165,
O => b_30_CYINIT_6211
);
b_30_CY0F : X_BUF
generic map(
LOC => "SLICE_X21Y27",
PATHPULSE => 638 ps
)
port map (
I => Sh190,
O => b_30_CY0F_6210
);
b_30_CYSELF : X_BUF
generic map(
LOC => "SLICE_X21Y27",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(30),
O => b_30_CYSELF_6204
);
b_30_YUSED : X_BUF
generic map(
LOC => "SLICE_X21Y27",
PATHPULSE => 638 ps
)
port map (
I => b_30_XORG_6200,
O => b_31_Q
);
b_30_XORG : X_XOR2
generic map(
LOC => "SLICE_X21Y27"
)
port map (
I0 => Madd_b_cy_30_Q,
I1 => Madd_b_lut(31),
O => b_30_XORG_6200
);
din_lower_0_IBUF : X_BUF
generic map(
LOC => "IPAD60",
PATHPULSE => 638 ps
)
port map (
I => din_lower(0),
O => din_lower_0_INBUF
);
din_lower_1_IBUF : X_BUF
generic map(
LOC => "PAD83",
PATHPULSE => 638 ps
)
port map (
I => din_lower(1),
O => din_lower_1_INBUF
);
din_lower_2_IBUF : X_BUF
generic map(
LOC => "IPAD86",
PATHPULSE => 638 ps
)
port map (
I => din_lower(2),
O => din_lower_2_INBUF
);
din_lower_3_IBUF : X_BUF
generic map(
LOC => "IPAD3",
PATHPULSE => 638 ps
)
port map (
I => din_lower(3),
O => din_lower_3_INBUF
);
din_lower_4_IBUF : X_BUF
generic map(
LOC => "PAD94",
PATHPULSE => 638 ps
)
port map (
I => din_lower(4),
O => din_lower_4_INBUF
);
din_lower_5_IBUF : X_BUF
generic map(
LOC => "PAD99",
PATHPULSE => 638 ps
)
port map (
I => din_lower(5),
O => din_lower_5_INBUF
);
din_lower_6_IBUF : X_BUF
generic map(
LOC => "IPAD100",
PATHPULSE => 638 ps
)
port map (
I => din_lower(6),
O => din_lower_6_INBUF
);
din_lower_7_IBUF : X_BUF
generic map(
LOC => "IPAD73",
PATHPULSE => 638 ps
)
port map (
I => din_lower(7),
O => din_lower_7_INBUF
);
clr_PULLUP : X_PU
generic map(
LOC => "PAD11"
)
port map (
O => NlwRenamedSig_IO_clr
);
clr_IBUF : X_BUF
generic map(
LOC => "PAD11",
PATHPULSE => 638 ps
)
port map (
I => NlwRenamedSig_IO_clr,
O => clr_INBUF
);
AN_0_OBUF : X_OBUF
generic map(
LOC => "PAD33"
)
port map (
I => AN_0_O,
O => AN(0)
);
AN_1_OBUF : X_OBUF
generic map(
LOC => "PAD44"
)
port map (
I => AN_1_O,
O => AN(1)
);
AN_2_OBUF : X_OBUF
generic map(
LOC => "PAD51"
)
port map (
I => AN_2_O,
O => AN(2)
);
AN_3_OBUF : X_OBUF
generic map(
LOC => "PAD45"
)
port map (
I => AN_3_O,
O => AN(3)
);
segment_a_i_OBUF : X_OBUF
generic map(
LOC => "PAD48"
)
port map (
I => segment_a_i_O,
O => segment_a_i
);
segment_b_i_OBUF : X_OBUF
generic map(
LOC => "PAD39"
)
port map (
I => segment_b_i_O,
O => segment_b_i
);
segment_c_i_OBUF : X_OBUF
generic map(
LOC => "PAD53"
)
port map (
I => segment_c_i_O,
O => segment_c_i
);
segment_d_i_OBUF : X_OBUF
generic map(
LOC => "PAD59"
)
port map (
I => segment_d_i_O,
O => segment_d_i
);
segment_e_i_OBUF : X_OBUF
generic map(
LOC => "PAD56"
)
port map (
I => segment_e_i_O,
O => segment_e_i
);
segment_f_i_OBUF : X_OBUF
generic map(
LOC => "PAD49"
)
port map (
I => segment_f_i_O,
O => segment_f_i
);
segment_g_i_OBUF : X_OBUF
generic map(
LOC => "PAD52"
)
port map (
I => segment_g_i_O,
O => segment_g_i
);
clk_25_BUFGP_IBUFG : X_BUF
generic map(
LOC => "IPAD13",
PATHPULSE => 638 ps
)
port map (
I => clk_25,
O => clk_25_INBUF
);
di_vld_PULLUP : X_PU
generic map(
LOC => "PAD72"
)
port map (
O => NlwRenamedSig_IO_di_vld
);
di_vld_IBUF : X_BUF
generic map(
LOC => "PAD72",
PATHPULSE => 638 ps
)
port map (
I => NlwRenamedSig_IO_di_vld,
O => di_vld_INBUF
);
do_rdy_OBUF : X_OBUF
generic map(
LOC => "PAD79"
)
port map (
I => do_rdy_O,
O => do_rdy
);
swtch_led_0_OBUF : X_OBUF
generic map(
LOC => "PAD69"
)
port map (
I => swtch_led_0_O,
O => swtch_led(0)
);
swtch_led_1_OBUF : X_OBUF
generic map(
LOC => "PAD58"
)
port map (
I => swtch_led_1_O,
O => swtch_led(1)
);
swtch_led_2_OBUF : X_OBUF
generic map(
LOC => "PAD64"
)
port map (
I => swtch_led_2_O,
O => swtch_led(2)
);
swtch_led_3_OBUF : X_OBUF
generic map(
LOC => "PAD65"
)
port map (
I => swtch_led_3_O,
O => swtch_led(3)
);
swtch_led_4_OBUF : X_OBUF
generic map(
LOC => "PAD68"
)
port map (
I => swtch_led_4_O,
O => swtch_led(4)
);
swtch_led_5_OBUF : X_OBUF
generic map(
LOC => "PAD71"
)
port map (
I => swtch_led_5_O,
O => swtch_led(5)
);
swtch_led_6_OBUF : X_OBUF
generic map(
LOC => "PAD70"
)
port map (
I => swtch_led_6_O,
O => swtch_led(6)
);
swtch_led_7_OBUF : X_OBUF
generic map(
LOC => "PAD96"
)
port map (
I => swtch_led_7_O,
O => swtch_led(7)
);
clk_25_BUFGP_BUFG : X_BUFGMUX
generic map(
LOC => "BUFGMUX_X2Y11"
)
port map (
I0 => clk_25_BUFGP_BUFG_I0_INV,
I1 => GND,
S => clk_25_BUFGP_BUFG_S_INVNOT,
O => clk_25_BUFGP
);
clk_25_BUFGP_BUFG_SINV : X_INV
generic map(
LOC => "BUFGMUX_X2Y11",
PATHPULSE => 638 ps
)
port map (
I => '1',
O => clk_25_BUFGP_BUFG_S_INVNOT
);
clk_25_BUFGP_BUFG_I0_USED : X_BUF
generic map(
LOC => "BUFGMUX_X2Y11",
PATHPULSE => 638 ps
)
port map (
I => clk_25_INBUF,
O => clk_25_BUFGP_BUFG_I0_INV
);
Sh13120_XUSED : X_BUF
generic map(
LOC => "SLICE_X26Y18",
PATHPULSE => 638 ps
)
port map (
I => Sh13120_F5MUX_6468,
O => Sh13120
);
Sh13120_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X26Y18"
)
port map (
IA => N402,
IB => N403,
SEL => Sh13120_BXINV_6460,
O => Sh13120_F5MUX_6468
);
Sh13120_BXINV : X_BUF
generic map(
LOC => "SLICE_X26Y18",
PATHPULSE => 638 ps
)
port map (
I => a(3),
O => Sh13120_BXINV_6460
);
Sh13332_G : X_LUT4
generic map(
INIT => X"AACC",
LOC => "SLICE_X26Y14"
)
port map (
ADR0 => Sh121,
ADR1 => Sh125,
ADR2 => VCC,
ADR3 => a(2),
O => N527
);
Sh133_XUSED : X_BUF
generic map(
LOC => "SLICE_X26Y14",
PATHPULSE => 638 ps
)
port map (
I => Sh133_F5MUX_6493,
O => Sh133
);
Sh133_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X26Y14"
)
port map (
IA => N526,
IB => N527,
SEL => Sh133_BXINV_6485,
O => Sh133_F5MUX_6493
);
Sh133_BXINV : X_BUF
generic map(
LOC => "SLICE_X26Y14",
PATHPULSE => 638 ps
)
port map (
I => a(3),
O => Sh133_BXINV_6485
);
Sh13332_F : X_LUT4
generic map(
INIT => X"FC30",
LOC => "SLICE_X26Y14"
)
port map (
ADR0 => VCC,
ADR1 => a(2),
ADR2 => Sh101,
ADR3 => Sh97,
O => N526
);
Sh14029_G : X_LUT4
generic map(
INIT => X"AFA0",
LOC => "SLICE_X26Y16"
)
port map (
ADR0 => Sh96,
ADR1 => VCC,
ADR2 => a(2),
ADR3 => Sh100,
O => N407
);
Sh140_XUSED : X_BUF
generic map(
LOC => "SLICE_X26Y16",
PATHPULSE => 638 ps
)
port map (
I => Sh140_F5MUX_6518,
O => Sh140
);
Sh140_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X26Y16"
)
port map (
IA => N406,
IB => N407,
SEL => Sh140_BXINV_6510,
O => Sh140_F5MUX_6518
);
Sh140_BXINV : X_BUF
generic map(
LOC => "SLICE_X26Y16",
PATHPULSE => 638 ps
)
port map (
I => a(3),
O => Sh140_BXINV_6510
);
Sh14029_F : X_LUT4
generic map(
INIT => X"AACC",
LOC => "SLICE_X26Y16"
)
port map (
ADR0 => Sh104,
ADR1 => Sh108,
ADR2 => VCC,
ADR3 => a(2),
O => N406
);
Sh14129_G : X_LUT4
generic map(
INIT => X"ACAC",
LOC => "SLICE_X25Y15"
)
port map (
ADR0 => Sh97,
ADR1 => Sh101,
ADR2 => a(2),
ADR3 => VCC,
O => N409
);
Sh141_XUSED : X_BUF
generic map(
LOC => "SLICE_X25Y15",
PATHPULSE => 638 ps
)
port map (
I => Sh141_F5MUX_6543,
O => Sh141
);
Sh141_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X25Y15"
)
port map (
IA => N408,
IB => N409,
SEL => Sh141_BXINV_6535,
O => Sh141_F5MUX_6543
);
Sh141_BXINV : X_BUF
generic map(
LOC => "SLICE_X25Y15",
PATHPULSE => 638 ps
)
port map (
I => a(3),
O => Sh141_BXINV_6535
);
Sh14129_F : X_LUT4
generic map(
INIT => X"E4E4",
LOC => "SLICE_X25Y15"
)
port map (
ADR0 => a(2),
ADR1 => Sh109,
ADR2 => Sh105,
ADR3 => VCC,
O => N408
);
Sh14229_G : X_LUT4
generic map(
INIT => X"D8D8",
LOC => "SLICE_X27Y19"
)
port map (
ADR0 => a(2),
ADR1 => Sh98_0,
ADR2 => Sh102_0,
ADR3 => VCC,
O => N315
);
Sh142_XUSED : X_BUF
generic map(
LOC => "SLICE_X27Y19",
PATHPULSE => 638 ps
)
port map (
I => Sh142_F5MUX_6568,
O => Sh142
);
Sh142_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X27Y19"
)
port map (
IA => N314,
IB => N315,
SEL => Sh142_BXINV_6560,
O => Sh142_F5MUX_6568
);
Sh142_BXINV : X_BUF
generic map(
LOC => "SLICE_X27Y19",
PATHPULSE => 638 ps
)
port map (
I => a(3),
O => Sh142_BXINV_6560
);
Sh14229_F : X_LUT4
generic map(
INIT => X"EE44",
LOC => "SLICE_X27Y19"
)
port map (
ADR0 => a(2),
ADR1 => Sh110_0,
ADR2 => VCC,
ADR3 => Sh106_0,
O => N314
);
Sh13528_G : X_LUT4
generic map(
INIT => X"CCF0",
LOC => "SLICE_X22Y26"
)
port map (
ADR0 => VCC,
ADR1 => Sh123,
ADR2 => Sh127,
ADR3 => a(2),
O => N303
);
Sh135_XUSED : X_BUF
generic map(
LOC => "SLICE_X22Y26",
PATHPULSE => 638 ps
)
port map (
I => Sh135_F5MUX_6593,
O => Sh135
);
Sh135_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X22Y26"
)
port map (
IA => N302,
IB => N303,
SEL => Sh135_BXINV_6585,
O => Sh135_F5MUX_6593
);
Sh135_BXINV : X_BUF
generic map(
LOC => "SLICE_X22Y26",
PATHPULSE => 638 ps
)
port map (
I => a(3),
O => Sh135_BXINV_6585
);
Sh13528_F : X_LUT4
generic map(
INIT => X"FC30",
LOC => "SLICE_X22Y26"
)
port map (
ADR0 => VCC,
ADR1 => a(2),
ADR2 => Sh103_0,
ADR3 => Sh99_0,
O => N302
);
Sh14612_G : X_LUT4
generic map(
INIT => X"CA00",
LOC => "SLICE_X27Y20"
)
port map (
ADR0 => Sh1022_0,
ADR1 => Sh1002_0,
ADR2 => a(1),
ADR3 => a(2),
O => N415
);
Sh14612_XUSED : X_BUF
generic map(
LOC => "SLICE_X27Y20",
PATHPULSE => 638 ps
)
port map (
I => Sh14612_F5MUX_6618,
O => Sh14612
);
Sh14612_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X27Y20"
)
port map (
IA => N414,
IB => N415,
SEL => Sh14612_BXINV_6611,
O => Sh14612_F5MUX_6618
);
Sh14612_BXINV : X_BUF
generic map(
LOC => "SLICE_X27Y20",
PATHPULSE => 638 ps
)
port map (
I => a(3),
O => Sh14612_BXINV_6611
);
Sh14612_F : X_LUT4
generic map(
INIT => X"E400",
LOC => "SLICE_X27Y20"
)
port map (
ADR0 => a(1),
ADR1 => Sh1102_0,
ADR2 => Sh1082_0,
ADR3 => a(2),
O => N414
);
Sh13628_G : X_LUT4
generic map(
INIT => X"F5A0",
LOC => "SLICE_X27Y16"
)
port map (
ADR0 => a(2),
ADR1 => VCC,
ADR2 => Sh124,
ADR3 => Sh96,
O => N305
);
Sh136_XUSED : X_BUF
generic map(
LOC => "SLICE_X27Y16",
PATHPULSE => 638 ps
)
port map (
I => Sh136_F5MUX_6643,
O => Sh136
);
Sh136_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X27Y16"
)
port map (
IA => N304,
IB => N305,
SEL => Sh136_BXINV_6635,
O => Sh136_F5MUX_6643
);
Sh136_BXINV : X_BUF
generic map(
LOC => "SLICE_X27Y16",
PATHPULSE => 638 ps
)
port map (
I => a(3),
O => Sh136_BXINV_6635
);
Sh13628_F : X_LUT4
generic map(
INIT => X"BB88",
LOC => "SLICE_X27Y16"
)
port map (
ADR0 => Sh100,
ADR1 => a(2),
ADR2 => VCC,
ADR3 => Sh104,
O => N304
);
Sh14712_G : X_LUT4
generic map(
INIT => X"88A0",
LOC => "SLICE_X25Y18"
)
port map (
ADR0 => a(2),
ADR1 => Sh1012_0,
ADR2 => Sh1032_0,
ADR3 => a(1),
O => N413
);
Sh14712_XUSED : X_BUF
generic map(
LOC => "SLICE_X25Y18",
PATHPULSE => 638 ps
)
port map (
I => Sh14712_F5MUX_6668,
O => Sh14712
);
Sh14712_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X25Y18"
)
port map (
IA => N412,
IB => N413,
SEL => Sh14712_BXINV_6661,
O => Sh14712_F5MUX_6668
);
Sh14712_BXINV : X_BUF
generic map(
LOC => "SLICE_X25Y18",
PATHPULSE => 638 ps
)
port map (
I => a(3),
O => Sh14712_BXINV_6661
);
Sh14712_F : X_LUT4
generic map(
INIT => X"8A80",
LOC => "SLICE_X25Y18"
)
port map (
ADR0 => a(2),
ADR1 => Sh1092_0,
ADR2 => a(1),
ADR3 => Sh1112_0,
O => N412
);
Sh13728_G : X_LUT4
generic map(
INIT => X"E4E4",
LOC => "SLICE_X29Y14"
)
port map (
ADR0 => a(2),
ADR1 => Sh97,
ADR2 => Sh125,
ADR3 => VCC,
O => N307
);
Sh137_XUSED : X_BUF
generic map(
LOC => "SLICE_X29Y14",
PATHPULSE => 638 ps
)
port map (
I => Sh137_F5MUX_6693,
O => Sh137
);
Sh137_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X29Y14"
)
port map (
IA => N306,
IB => N307,
SEL => Sh137_BXINV_6685,
O => Sh137_F5MUX_6693
);
Sh137_BXINV : X_BUF
generic map(
LOC => "SLICE_X29Y14",
PATHPULSE => 638 ps
)
port map (
I => a(3),
O => Sh137_BXINV_6685
);
Sh13728_F : X_LUT4
generic map(
INIT => X"D8D8",
LOC => "SLICE_X29Y14"
)
port map (
ADR0 => a(2),
ADR1 => Sh101,
ADR2 => Sh105,
ADR3 => VCC,
O => N306
);
Sh13929_G : X_LUT4
generic map(
INIT => X"CCAA",
LOC => "SLICE_X24Y24"
)
port map (
ADR0 => Sh99_0,
ADR1 => Sh127,
ADR2 => VCC,
ADR3 => a(2),
O => N299
);
Sh139_XUSED : X_BUF
generic map(
LOC => "SLICE_X24Y24",
PATHPULSE => 638 ps
)
port map (
I => Sh139_F5MUX_6718,
O => Sh139
);
Sh139_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X24Y24"
)
port map (
IA => N298,
IB => N299,
SEL => Sh139_BXINV_6710,
O => Sh139_F5MUX_6718
);
Sh139_BXINV : X_BUF
generic map(
LOC => "SLICE_X24Y24",
PATHPULSE => 638 ps
)
port map (
I => a(3),
O => Sh139_BXINV_6710
);
Sh13929_F : X_LUT4
generic map(
INIT => X"EE22",
LOC => "SLICE_X24Y24"
)
port map (
ADR0 => Sh107,
ADR1 => a(2),
ADR2 => VCC,
ADR3 => Sh103_0,
O => N298
);
b_reg_mux0000_10_21_G : X_LUT4
generic map(
INIT => X"FEAE",
LOC => "SLICE_X14Y14"
)
port map (
ADR0 => b_reg_mux0000_10_10_0,
ADR1 => b_reg(10),
ADR2 => state_FSM_FFd2_4312,
ADR3 => state_FSM_FFd1_4311,
O => N529
);
b_reg_mux0000_10_21_F : X_LUT4
generic map(
INIT => X"AFAA",
LOC => "SLICE_X14Y14"
)
port map (
ADR0 => b_reg_mux0000_10_10_0,
ADR1 => VCC,
ADR2 => state_FSM_FFd2_4312,
ADR3 => b_reg(10),
O => N528
);
b_reg_10_FFX_RSTOR : X_BUF
generic map(
LOC => "SLICE_X14Y14",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => b_reg_10_FFX_RST
);
b_reg_10 : X_FF
generic map(
LOC => "SLICE_X14Y14",
INIT => '0'
)
port map (
I => b_reg_10_DXMUX_6749,
CE => VCC,
CLK => b_reg_10_CLKINV_6731,
SET => GND,
RST => b_reg_10_FFX_RST,
O => b_reg(10)
);
b_reg_10_DXMUX : X_BUF
generic map(
LOC => "SLICE_X14Y14",
PATHPULSE => 638 ps
)
port map (
I => b_reg_10_F5MUX_6747,
O => b_reg_10_DXMUX_6749
);
b_reg_10_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X14Y14"
)
port map (
IA => N528,
IB => N529,
SEL => b_reg_10_BXINV_6740,
O => b_reg_10_F5MUX_6747
);
b_reg_10_BXINV : X_BUF
generic map(
LOC => "SLICE_X14Y14",
PATHPULSE => 638 ps
)
port map (
I => b_10_XORF_5798,
O => b_reg_10_BXINV_6740
);
b_reg_10_CLKINV : X_BUF
generic map(
LOC => "SLICE_X14Y14",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => b_reg_10_CLKINV_6731
);
Sh10_XUSED : X_BUF
generic map(
LOC => "SLICE_X12Y13",
PATHPULSE => 638 ps
)
port map (
I => Sh10_F5MUX_6779,
O => Sh10
);
Sh10_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X12Y13"
)
port map (
IA => N470,
IB => N471,
SEL => Sh10_BXINV_6772,
O => Sh10_F5MUX_6779
);
Sh10_BXINV : X_BUF
generic map(
LOC => "SLICE_X12Y13",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh10_BXINV_6772
);
Sh13_XUSED : X_BUF
generic map(
LOC => "SLICE_X14Y17",
PATHPULSE => 638 ps
)
port map (
I => Sh13_F5MUX_6804,
O => Sh13
);
Sh13_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X14Y17"
)
port map (
IA => N494,
IB => N495,
SEL => Sh13_BXINV_6797,
O => Sh13_F5MUX_6804
);
Sh13_BXINV : X_BUF
generic map(
LOC => "SLICE_X14Y17",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh13_BXINV_6797
);
Sh21_f5_G : X_LUT4
generic map(
INIT => X"7D28",
LOC => "SLICE_X14Y30"
)
port map (
ADR0 => b_reg_0_2_4323,
ADR1 => b_reg(18),
ADR2 => a_reg(18),
ADR3 => ab_xor_19_0,
O => N491
);
Sh21_XUSED : X_BUF
generic map(
LOC => "SLICE_X14Y30",
PATHPULSE => 638 ps
)
port map (
I => Sh21_F5MUX_6829,
O => Sh21
);
Sh21_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X14Y30"
)
port map (
IA => N490,
IB => N491,
SEL => Sh21_BXINV_6822,
O => Sh21_F5MUX_6829
);
Sh21_BXINV : X_BUF
generic map(
LOC => "SLICE_X14Y30",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh21_BXINV_6822
);
Sh21_f5_F : X_LUT4
generic map(
INIT => X"BE14",
LOC => "SLICE_X14Y30"
)
port map (
ADR0 => b_reg_0_2_4323,
ADR1 => b_reg(21),
ADR2 => a_reg(21),
ADR3 => ab_xor_20_0,
O => N490
);
Sh14_XUSED : X_BUF
generic map(
LOC => "SLICE_X12Y16",
PATHPULSE => 638 ps
)
port map (
I => Sh14_F5MUX_6854,
O => Sh14
);
Sh14_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X12Y16"
)
port map (
IA => N486,
IB => N487,
SEL => Sh14_BXINV_6847,
O => Sh14_F5MUX_6854
);
Sh14_BXINV : X_BUF
generic map(
LOC => "SLICE_X12Y16",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh14_BXINV_6847
);
Sh14_f5_G : X_LUT4
generic map(
INIT => X"F066",
LOC => "SLICE_X12Y16"
)
port map (
ADR0 => b_reg(12),
ADR1 => a_reg(12),
ADR2 => ab_xor_11_0,
ADR3 => b_reg_0_3_4316,
O => N487
);
Sh22_XUSED : X_BUF
generic map(
LOC => "SLICE_X15Y31",
PATHPULSE => 638 ps
)
port map (
I => Sh22_F5MUX_6879,
O => Sh22_4347
);
Sh22_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X15Y31"
)
port map (
IA => N482,
IB => N483,
SEL => Sh22_BXINV_6872,
O => Sh22_F5MUX_6879
);
Sh22_BXINV : X_BUF
generic map(
LOC => "SLICE_X15Y31",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh22_BXINV_6872
);
Sh30_XUSED : X_BUF
generic map(
LOC => "SLICE_X14Y35",
PATHPULSE => 638 ps
)
port map (
I => Sh30_F5MUX_6904,
O => Sh30
);
Sh30_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X14Y35"
)
port map (
IA => N472,
IB => N473,
SEL => Sh30_BXINV_6897,
O => Sh30_F5MUX_6904
);
Sh30_BXINV : X_BUF
generic map(
LOC => "SLICE_X14Y35",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh30_BXINV_6897
);
Sh17_XUSED : X_BUF
generic map(
LOC => "SLICE_X14Y23",
PATHPULSE => 638 ps
)
port map (
I => Sh17_F5MUX_6929,
O => Sh17
);
Sh17_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X14Y23"
)
port map (
IA => N492,
IB => N493,
SEL => Sh17_BXINV_6922,
O => Sh17_F5MUX_6929
);
Sh17_BXINV : X_BUF
generic map(
LOC => "SLICE_X14Y23",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh17_BXINV_6922
);
Sh25_XUSED : X_BUF
generic map(
LOC => "SLICE_X15Y32",
PATHPULSE => 638 ps
)
port map (
I => Sh25_F5MUX_6954,
O => Sh25
);
Sh25_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X15Y32"
)
port map (
IA => N488,
IB => N489,
SEL => Sh25_BXINV_6947,
O => Sh25_F5MUX_6954
);
Sh25_BXINV : X_BUF
generic map(
LOC => "SLICE_X15Y32",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh25_BXINV_6947
);
Sh18_XUSED : X_BUF
generic map(
LOC => "SLICE_X13Y20",
PATHPULSE => 638 ps
)
port map (
I => Sh18_F5MUX_6979,
O => Sh18
);
Sh18_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X13Y20"
)
port map (
IA => N484,
IB => N485,
SEL => Sh18_BXINV_6972,
O => Sh18_F5MUX_6979
);
Sh18_BXINV : X_BUF
generic map(
LOC => "SLICE_X13Y20",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh18_BXINV_6972
);
Sh26_XUSED : X_BUF
generic map(
LOC => "SLICE_X14Y32",
PATHPULSE => 638 ps
)
port map (
I => Sh26_F5MUX_7004,
O => Sh26
);
Sh26_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X14Y32"
)
port map (
IA => N480,
IB => N481,
SEL => Sh26_BXINV_6997,
O => Sh26_F5MUX_7004
);
Sh26_BXINV : X_BUF
generic map(
LOC => "SLICE_X14Y32",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh26_BXINV_6997
);
Sh29_XUSED : X_BUF
generic map(
LOC => "SLICE_X15Y34",
PATHPULSE => 638 ps
)
port map (
I => Sh29_F5MUX_7029,
O => Sh29
);
Sh29_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X15Y34"
)
port map (
IA => N478,
IB => N479,
SEL => Sh29_BXINV_7022,
O => Sh29_F5MUX_7029
);
Sh29_BXINV : X_BUF
generic map(
LOC => "SLICE_X15Y34",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh29_BXINV_7022
);
Sh4_XUSED : X_BUF
generic map(
LOC => "SLICE_X15Y19",
PATHPULSE => 638 ps
)
port map (
I => Sh4_F5MUX_7054,
O => Sh4
);
Sh4_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X15Y19"
)
port map (
IA => N300,
IB => N301,
SEL => Sh4_BXINV_7047,
O => Sh4_F5MUX_7054
);
Sh4_BXINV : X_BUF
generic map(
LOC => "SLICE_X15Y19",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh4_BXINV_7047
);
Sh8_XUSED : X_BUF
generic map(
LOC => "SLICE_X12Y14",
PATHPULSE => 638 ps
)
port map (
I => Sh8_F5MUX_7079,
O => Sh8
);
Sh8_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X12Y14"
)
port map (
IA => N324,
IB => N325,
SEL => Sh8_BXINV_7072,
O => Sh8_F5MUX_7079
);
Sh8_BXINV : X_BUF
generic map(
LOC => "SLICE_X12Y14",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh8_BXINV_7072
);
Sh96_XUSED : X_BUF
generic map(
LOC => "SLICE_X23Y27",
PATHPULSE => 638 ps
)
port map (
I => Sh96_F5MUX_7106,
O => Sh96
);
Sh96_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X23Y27"
)
port map (
IA => Sh962,
IB => Sh1262_rt_7104,
SEL => Sh96_BXINV_7096,
O => Sh96_F5MUX_7106
);
Sh96_BXINV : X_BUF
generic map(
LOC => "SLICE_X23Y27",
PATHPULSE => 638 ps
)
port map (
I => a(1),
O => Sh96_BXINV_7096
);
Sh96_YUSED : X_BUF
generic map(
LOC => "SLICE_X23Y27",
PATHPULSE => 638 ps
)
port map (
I => Sh962,
O => Sh962_0
);
Sh97_XUSED : X_BUF
generic map(
LOC => "SLICE_X24Y27",
PATHPULSE => 638 ps
)
port map (
I => Sh97_F5MUX_7131,
O => Sh97
);
Sh97_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X24Y27"
)
port map (
IA => Sh972_7119,
IB => Sh1272_rt_7129,
SEL => Sh97_BXINV_7121,
O => Sh97_F5MUX_7131
);
Sh97_BXINV : X_BUF
generic map(
LOC => "SLICE_X24Y27",
PATHPULSE => 638 ps
)
port map (
I => a(1),
O => Sh97_BXINV_7121
);
Sh100_XUSED : X_BUF
generic map(
LOC => "SLICE_X25Y27",
PATHPULSE => 638 ps
)
port map (
I => Sh100_F5MUX_7158,
O => Sh100
);
Sh100_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X25Y27"
)
port map (
IA => Sh1002,
IB => Sh1001_7156,
SEL => Sh100_BXINV_7151,
O => Sh100_F5MUX_7158
);
Sh100_BXINV : X_BUF
generic map(
LOC => "SLICE_X25Y27",
PATHPULSE => 638 ps
)
port map (
I => a(1),
O => Sh100_BXINV_7151
);
Sh100_YUSED : X_BUF
generic map(
LOC => "SLICE_X25Y27",
PATHPULSE => 638 ps
)
port map (
I => Sh1002,
O => Sh1002_0
);
Sh101_XUSED : X_BUF
generic map(
LOC => "SLICE_X22Y18",
PATHPULSE => 638 ps
)
port map (
I => Sh101_F5MUX_7185,
O => Sh101
);
Sh101_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X22Y18"
)
port map (
IA => Sh1012,
IB => Sh1011_rt_7183,
SEL => Sh101_BXINV_7175,
O => Sh101_F5MUX_7185
);
Sh101_BXINV : X_BUF
generic map(
LOC => "SLICE_X22Y18",
PATHPULSE => 638 ps
)
port map (
I => a(1),
O => Sh101_BXINV_7175
);
Sh101_YUSED : X_BUF
generic map(
LOC => "SLICE_X22Y18",
PATHPULSE => 638 ps
)
port map (
I => Sh1012,
O => Sh1012_0
);
Sh120_XUSED : X_BUF
generic map(
LOC => "SLICE_X21Y28",
PATHPULSE => 638 ps
)
port map (
I => Sh120_F5MUX_7212,
O => Sh120
);
Sh120_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X21Y28"
)
port map (
IA => Sh1202,
IB => Sh1182_rt_7210,
SEL => Sh120_BXINV_7202,
O => Sh120_F5MUX_7212
);
Sh120_BXINV : X_BUF
generic map(
LOC => "SLICE_X21Y28",
PATHPULSE => 638 ps
)
port map (
I => a(1),
O => Sh120_BXINV_7202
);
Sh120_YUSED : X_BUF
generic map(
LOC => "SLICE_X21Y28",
PATHPULSE => 638 ps
)
port map (
I => Sh1202,
O => Sh1202_0
);
Sh112_XUSED : X_BUF
generic map(
LOC => "SLICE_X25Y20",
PATHPULSE => 638 ps
)
port map (
I => Sh112_F5MUX_7239,
O => Sh112
);
Sh112_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X25Y20"
)
port map (
IA => Sh1122,
IB => Sh1102_rt_7237,
SEL => Sh112_BXINV_7229,
O => Sh112_F5MUX_7239
);
Sh112_BXINV : X_BUF
generic map(
LOC => "SLICE_X25Y20",
PATHPULSE => 638 ps
)
port map (
I => a(1),
O => Sh112_BXINV_7229
);
Sh112_YUSED : X_BUF
generic map(
LOC => "SLICE_X25Y20",
PATHPULSE => 638 ps
)
port map (
I => Sh1122,
O => Sh1122_0
);
Sh104_XUSED : X_BUF
generic map(
LOC => "SLICE_X20Y13",
PATHPULSE => 638 ps
)
port map (
I => Sh104_F5MUX_7266,
O => Sh104
);
Sh104_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X20Y13"
)
port map (
IA => Sh1042,
IB => Sh1022_rt_7264,
SEL => Sh104_BXINV_7256,
O => Sh104_F5MUX_7266
);
Sh104_BXINV : X_BUF
generic map(
LOC => "SLICE_X20Y13",
PATHPULSE => 638 ps
)
port map (
I => a(1),
O => Sh104_BXINV_7256
);
Sh104_YUSED : X_BUF
generic map(
LOC => "SLICE_X20Y13",
PATHPULSE => 638 ps
)
port map (
I => Sh1042,
O => Sh1042_0
);
Sh121_XUSED : X_BUF
generic map(
LOC => "SLICE_X23Y29",
PATHPULSE => 638 ps
)
port map (
I => Sh121_F5MUX_7293,
O => Sh121
);
Sh121_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X23Y29"
)
port map (
IA => Sh1212,
IB => Sh1192_rt_7291,
SEL => Sh121_BXINV_7283,
O => Sh121_F5MUX_7293
);
Sh121_BXINV : X_BUF
generic map(
LOC => "SLICE_X23Y29",
PATHPULSE => 638 ps
)
port map (
I => a(1),
O => Sh121_BXINV_7283
);
Sh121_YUSED : X_BUF
generic map(
LOC => "SLICE_X23Y29",
PATHPULSE => 638 ps
)
port map (
I => Sh1212,
O => Sh1212_0
);
Sh113_XUSED : X_BUF
generic map(
LOC => "SLICE_X24Y20",
PATHPULSE => 638 ps
)
port map (
I => Sh113_F5MUX_7320,
O => Sh113
);
Sh113_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X24Y20"
)
port map (
IA => Sh1132,
IB => Sh1112_rt_7318,
SEL => Sh113_BXINV_7310,
O => Sh113_F5MUX_7320
);
Sh113_BXINV : X_BUF
generic map(
LOC => "SLICE_X24Y20",
PATHPULSE => 638 ps
)
port map (
I => a(1),
O => Sh113_BXINV_7310
);
Sh113_YUSED : X_BUF
generic map(
LOC => "SLICE_X24Y20",
PATHPULSE => 638 ps
)
port map (
I => Sh1132,
O => Sh1132_0
);
Sh105_XUSED : X_BUF
generic map(
LOC => "SLICE_X20Y12",
PATHPULSE => 638 ps
)
port map (
I => Sh105_F5MUX_7347,
O => Sh105
);
Sh105_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X20Y12"
)
port map (
IA => Sh1052,
IB => Sh1032_rt_7345,
SEL => Sh105_BXINV_7337,
O => Sh105_F5MUX_7347
);
Sh105_BXINV : X_BUF
generic map(
LOC => "SLICE_X20Y12",
PATHPULSE => 638 ps
)
port map (
I => a(1),
O => Sh105_BXINV_7337
);
Sh105_YUSED : X_BUF
generic map(
LOC => "SLICE_X20Y12",
PATHPULSE => 638 ps
)
port map (
I => Sh1052,
O => Sh1052_0
);
Sh124_XUSED : X_BUF
generic map(
LOC => "SLICE_X22Y29",
PATHPULSE => 638 ps
)
port map (
I => Sh124_F5MUX_7374,
O => Sh124
);
Sh124_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X22Y29"
)
port map (
IA => Sh1242,
IB => Sh1222_rt_7372,
SEL => Sh124_BXINV_7364,
O => Sh124_F5MUX_7374
);
Sh124_BXINV : X_BUF
generic map(
LOC => "SLICE_X22Y29",
PATHPULSE => 638 ps
)
port map (
I => a(1),
O => Sh124_BXINV_7364
);
Sh124_YUSED : X_BUF
generic map(
LOC => "SLICE_X22Y29",
PATHPULSE => 638 ps
)
port map (
I => Sh1242,
O => Sh1242_0
);
Sh116_XUSED : X_BUF
generic map(
LOC => "SLICE_X25Y24",
PATHPULSE => 638 ps
)
port map (
I => Sh116_F5MUX_7401,
O => Sh116
);
Sh116_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X25Y24"
)
port map (
IA => Sh1162,
IB => Sh1142_rt_7399,
SEL => Sh116_BXINV_7391,
O => Sh116_F5MUX_7401
);
Sh116_BXINV : X_BUF
generic map(
LOC => "SLICE_X25Y24",
PATHPULSE => 638 ps
)
port map (
I => a(1),
O => Sh116_BXINV_7391
);
Sh116_YUSED : X_BUF
generic map(
LOC => "SLICE_X25Y24",
PATHPULSE => 638 ps
)
port map (
I => Sh1162,
O => Sh1162_0
);
Sh108_XUSED : X_BUF
generic map(
LOC => "SLICE_X22Y12",
PATHPULSE => 638 ps
)
port map (
I => Sh108_F5MUX_7428,
O => Sh108
);
Sh108_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X22Y12"
)
port map (
IA => Sh1082,
IB => Sh1062_rt_7426,
SEL => Sh108_BXINV_7418,
O => Sh108_F5MUX_7428
);
Sh108_BXINV : X_BUF
generic map(
LOC => "SLICE_X22Y12",
PATHPULSE => 638 ps
)
port map (
I => a(1),
O => Sh108_BXINV_7418
);
Sh108_YUSED : X_BUF
generic map(
LOC => "SLICE_X22Y12",
PATHPULSE => 638 ps
)
port map (
I => Sh1082,
O => Sh1082_0
);
Sh125_XUSED : X_BUF
generic map(
LOC => "SLICE_X23Y30",
PATHPULSE => 638 ps
)
port map (
I => Sh125_F5MUX_7455,
O => Sh125
);
Sh125_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X23Y30"
)
port map (
IA => Sh1252,
IB => Sh1232_rt_7453,
SEL => Sh125_BXINV_7445,
O => Sh125_F5MUX_7455
);
Sh125_BXINV : X_BUF
generic map(
LOC => "SLICE_X23Y30",
PATHPULSE => 638 ps
)
port map (
I => a(1),
O => Sh125_BXINV_7445
);
Sh125_YUSED : X_BUF
generic map(
LOC => "SLICE_X23Y30",
PATHPULSE => 638 ps
)
port map (
I => Sh1252,
O => Sh1252_0
);
Sh117_XUSED : X_BUF
generic map(
LOC => "SLICE_X25Y25",
PATHPULSE => 638 ps
)
port map (
I => Sh117_F5MUX_7482,
O => Sh117
);
Sh117_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X25Y25"
)
port map (
IA => Sh1172,
IB => Sh1152_rt_7480,
SEL => Sh117_BXINV_7472,
O => Sh117_F5MUX_7482
);
Sh117_BXINV : X_BUF
generic map(
LOC => "SLICE_X25Y25",
PATHPULSE => 638 ps
)
port map (
I => a(1),
O => Sh117_BXINV_7472
);
Sh117_YUSED : X_BUF
generic map(
LOC => "SLICE_X25Y25",
PATHPULSE => 638 ps
)
port map (
I => Sh1172,
O => Sh1172_0
);
Sh109_XUSED : X_BUF
generic map(
LOC => "SLICE_X22Y16",
PATHPULSE => 638 ps
)
port map (
I => Sh109_F5MUX_7509,
O => Sh109
);
Sh109_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X22Y16"
)
port map (
IA => Sh1092,
IB => Sh1072_rt_7507,
SEL => Sh109_BXINV_7499,
O => Sh109_F5MUX_7509
);
Sh109_BXINV : X_BUF
generic map(
LOC => "SLICE_X22Y16",
PATHPULSE => 638 ps
)
port map (
I => a(1),
O => Sh109_BXINV_7499
);
Sh109_YUSED : X_BUF
generic map(
LOC => "SLICE_X22Y16",
PATHPULSE => 638 ps
)
port map (
I => Sh1092,
O => Sh1092_0
);
Sh3_XUSED : X_BUF
generic map(
LOC => "SLICE_X12Y20",
PATHPULSE => 638 ps
)
port map (
I => Sh3_F5MUX_7534,
O => Sh3
);
Sh3_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X12Y20"
)
port map (
IA => N308,
IB => N309,
SEL => Sh3_BXINV_7526,
O => Sh3_F5MUX_7534
);
Sh3_BXINV : X_BUF
generic map(
LOC => "SLICE_X12Y20",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh3_BXINV_7526
);
Sh7_XUSED : X_BUF
generic map(
LOC => "SLICE_X13Y17",
PATHPULSE => 638 ps
)
port map (
I => Sh7_F5MUX_7559,
O => Sh7
);
Sh7_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X13Y17"
)
port map (
IA => N336,
IB => N337,
SEL => Sh7_BXINV_7552,
O => Sh7_F5MUX_7559
);
Sh7_BXINV : X_BUF
generic map(
LOC => "SLICE_X13Y17",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh7_BXINV_7552
);
Sh11_XUSED : X_BUF
generic map(
LOC => "SLICE_X13Y12",
PATHPULSE => 638 ps
)
port map (
I => Sh11_F5MUX_7584,
O => Sh11
);
Sh11_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X13Y12"
)
port map (
IA => N348,
IB => N349,
SEL => Sh11_BXINV_7577,
O => Sh11_F5MUX_7584
);
Sh11_BXINV : X_BUF
generic map(
LOC => "SLICE_X13Y12",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh11_BXINV_7577
);
Sh15_XUSED : X_BUF
generic map(
LOC => "SLICE_X13Y16",
PATHPULSE => 638 ps
)
port map (
I => Sh15_F5MUX_7609,
O => Sh15
);
Sh15_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X13Y16"
)
port map (
IA => N346,
IB => N347,
SEL => Sh15_BXINV_7602,
O => Sh15_F5MUX_7609
);
Sh15_BXINV : X_BUF
generic map(
LOC => "SLICE_X13Y16",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh15_BXINV_7602
);
Sh23_XUSED : X_BUF
generic map(
LOC => "SLICE_X15Y33",
PATHPULSE => 638 ps
)
port map (
I => Sh23_F5MUX_7634,
O => Sh23_4457
);
Sh23_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X15Y33"
)
port map (
IA => N342,
IB => N343,
SEL => Sh23_BXINV_7627,
O => Sh23_F5MUX_7634
);
Sh23_BXINV : X_BUF
generic map(
LOC => "SLICE_X15Y33",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh23_BXINV_7627
);
Sh31_XUSED : X_BUF
generic map(
LOC => "SLICE_X12Y34",
PATHPULSE => 638 ps
)
port map (
I => Sh31_F5MUX_7659,
O => Sh31
);
Sh31_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X12Y34"
)
port map (
IA => N338,
IB => N339,
SEL => Sh31_BXINV_7652,
O => Sh31_F5MUX_7659
);
Sh31_BXINV : X_BUF
generic map(
LOC => "SLICE_X12Y34",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh31_BXINV_7652
);
Sh19_XUSED : X_BUF
generic map(
LOC => "SLICE_X14Y22",
PATHPULSE => 638 ps
)
port map (
I => Sh19_F5MUX_7684,
O => Sh19
);
Sh19_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X14Y22"
)
port map (
IA => N344,
IB => N345,
SEL => Sh19_BXINV_7677,
O => Sh19_F5MUX_7684
);
Sh19_BXINV : X_BUF
generic map(
LOC => "SLICE_X14Y22",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh19_BXINV_7677
);
Sh27_XUSED : X_BUF
generic map(
LOC => "SLICE_X14Y34",
PATHPULSE => 638 ps
)
port map (
I => Sh27_F5MUX_7709,
O => Sh27
);
Sh27_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X14Y34"
)
port map (
IA => N340,
IB => N341,
SEL => Sh27_BXINV_7702,
O => Sh27_F5MUX_7709
);
Sh27_BXINV : X_BUF
generic map(
LOC => "SLICE_X14Y34",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh27_BXINV_7702
);
Sh12_XUSED : X_BUF
generic map(
LOC => "SLICE_X12Y15",
PATHPULSE => 638 ps
)
port map (
I => Sh12_F5MUX_7734,
O => Sh12
);
Sh12_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X12Y15"
)
port map (
IA => N334,
IB => N335,
SEL => Sh12_BXINV_7727,
O => Sh12_F5MUX_7734
);
Sh12_BXINV : X_BUF
generic map(
LOC => "SLICE_X12Y15",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh12_BXINV_7727
);
Sh20_XUSED : X_BUF
generic map(
LOC => "SLICE_X15Y25",
PATHPULSE => 638 ps
)
port map (
I => Sh20_F5MUX_7759,
O => Sh20
);
Sh20_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X15Y25"
)
port map (
IA => N330,
IB => N331,
SEL => Sh20_BXINV_7752,
O => Sh20_F5MUX_7759
);
Sh20_BXINV : X_BUF
generic map(
LOC => "SLICE_X15Y25",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh20_BXINV_7752
);
Sh16_XUSED : X_BUF
generic map(
LOC => "SLICE_X12Y21",
PATHPULSE => 638 ps
)
port map (
I => Sh16_F5MUX_7784,
O => Sh16
);
Sh16_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X12Y21"
)
port map (
IA => N332,
IB => N333,
SEL => Sh16_BXINV_7777,
O => Sh16_F5MUX_7784
);
Sh16_BXINV : X_BUF
generic map(
LOC => "SLICE_X12Y21",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh16_BXINV_7777
);
Sh24_XUSED : X_BUF
generic map(
LOC => "SLICE_X14Y33",
PATHPULSE => 638 ps
)
port map (
I => Sh24_F5MUX_7809,
O => Sh24
);
Sh24_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X14Y33"
)
port map (
IA => N328,
IB => N329,
SEL => Sh24_BXINV_7802,
O => Sh24_F5MUX_7809
);
Sh24_BXINV : X_BUF
generic map(
LOC => "SLICE_X14Y33",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh24_BXINV_7802
);
Sh28_XUSED : X_BUF
generic map(
LOC => "SLICE_X15Y35",
PATHPULSE => 638 ps
)
port map (
I => Sh28_F5MUX_7834,
O => Sh28
);
Sh28_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X15Y35"
)
port map (
IA => N326,
IB => N327,
SEL => Sh28_BXINV_7827,
O => Sh28_F5MUX_7834
);
Sh28_BXINV : X_BUF
generic map(
LOC => "SLICE_X15Y35",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh28_BXINV_7827
);
Sh123_XUSED : X_BUF
generic map(
LOC => "SLICE_X23Y28",
PATHPULSE => 638 ps
)
port map (
I => Sh123_F5MUX_7859,
O => Sh123
);
Sh123_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X23Y28"
)
port map (
IA => N496,
IB => N497,
SEL => Sh123_BXINV_7852,
O => Sh123_F5MUX_7859
);
Sh123_BXINV : X_BUF
generic map(
LOC => "SLICE_X23Y28",
PATHPULSE => 638 ps
)
port map (
I => a(1),
O => Sh123_BXINV_7852
);
Sh127_XUSED : X_BUF
generic map(
LOC => "SLICE_X21Y30",
PATHPULSE => 638 ps
)
port map (
I => Sh127_F5MUX_7884,
O => Sh127
);
Sh127_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X21Y30"
)
port map (
IA => N460,
IB => N461,
SEL => Sh127_BXINV_7877,
O => Sh127_F5MUX_7884
);
Sh127_BXINV : X_BUF
generic map(
LOC => "SLICE_X21Y30",
PATHPULSE => 638 ps
)
port map (
I => a(1),
O => Sh127_BXINV_7877
);
Sh145_XUSED : X_BUF
generic map(
LOC => "SLICE_X24Y15",
PATHPULSE => 638 ps
)
port map (
I => Sh145_F5MUX_7909,
O => Sh145
);
Sh145_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X24Y15"
)
port map (
IA => Sh145311_7899,
IB => Sh14531,
SEL => Sh145_BXINV_7901,
O => Sh145_F5MUX_7909
);
Sh145_BXINV : X_BUF
generic map(
LOC => "SLICE_X24Y15",
PATHPULSE => 638 ps
)
port map (
I => a(3),
O => Sh145_BXINV_7901
);
Sh_XUSED : X_BUF
generic map(
LOC => "SLICE_X12Y35",
PATHPULSE => 638 ps
)
port map (
I => Sh_F5MUX_7934,
O => Sh
);
Sh_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X12Y35"
)
port map (
IA => N410,
IB => N411,
SEL => Sh_BXINV_7927,
O => Sh_F5MUX_7934
);
Sh_BXINV : X_BUF
generic map(
LOC => "SLICE_X12Y35",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh_BXINV_7927
);
N291_XUSED : X_BUF
generic map(
LOC => "SLICE_X8Y3",
PATHPULSE => 638 ps
)
port map (
I => N291_F5MUX_7959,
O => N291
);
N291_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X8Y3"
)
port map (
IA => N464,
IB => N465,
SEL => N291_BXINV_7950,
O => N291_F5MUX_7959
);
N291_BXINV : X_BUF
generic map(
LOC => "SLICE_X8Y3",
PATHPULSE => 638 ps
)
port map (
I => state_FSM_FFd1_4311,
O => N291_BXINV_7950
);
N292_XUSED : X_BUF
generic map(
LOC => "SLICE_X8Y2",
PATHPULSE => 638 ps
)
port map (
I => N292_F5MUX_7984,
O => N292
);
N292_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X8Y2"
)
port map (
IA => N466,
IB => N467,
SEL => N292_BXINV_7975,
O => N292_F5MUX_7984
);
N292_BXINV : X_BUF
generic map(
LOC => "SLICE_X8Y2",
PATHPULSE => 638 ps
)
port map (
I => state_FSM_FFd1_4311,
O => N292_BXINV_7975
);
N281_XUSED : X_BUF
generic map(
LOC => "SLICE_X2Y20",
PATHPULSE => 638 ps
)
port map (
I => N281_F5MUX_8009,
O => N281
);
N281_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X2Y20"
)
port map (
IA => N456,
IB => N457,
SEL => N281_BXINV_8000,
O => N281_F5MUX_8009
);
N281_BXINV : X_BUF
generic map(
LOC => "SLICE_X2Y20",
PATHPULSE => 638 ps
)
port map (
I => state_FSM_FFd1_4311,
O => N281_BXINV_8000
);
b_reg_mux0000_3_24_SW0_G : X_LUT4
generic map(
INIT => X"2222",
LOC => "SLICE_X2Y20"
)
port map (
ADR0 => b_reg(3),
ADR1 => state_FSM_FFd2_4312,
ADR2 => VCC,
ADR3 => VCC,
O => N457
);
b_reg_mux0000_3_24_SW1_G : X_LUT4
generic map(
INIT => X"FFF0",
LOC => "SLICE_X2Y23"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => state_FSM_FFd2_4312,
ADR3 => b_reg(3),
O => N459
);
N282_XUSED : X_BUF
generic map(
LOC => "SLICE_X2Y23",
PATHPULSE => 638 ps
)
port map (
I => N282_F5MUX_8034,
O => N282
);
N282_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X2Y23"
)
port map (
IA => N458,
IB => N459,
SEL => N282_BXINV_8025,
O => N282_F5MUX_8034
);
N282_BXINV : X_BUF
generic map(
LOC => "SLICE_X2Y23",
PATHPULSE => 638 ps
)
port map (
I => state_FSM_FFd1_4311,
O => N282_BXINV_8025
);
b_reg_mux0000_3_24_SW1_F : X_LUT4
generic map(
INIT => X"B784",
LOC => "SLICE_X2Y23"
)
port map (
ADR0 => Madd_b_pre_cy_2_Q,
ADR1 => state_FSM_FFd2_4312,
ADR2 => swtch_led_3_OBUF_4256,
ADR3 => b_reg(3),
O => N458
);
b_reg_mux0000_4_34_SW0_G : X_LUT4
generic map(
INIT => X"0A0A",
LOC => "SLICE_X1Y20"
)
port map (
ADR0 => b_reg(4),
ADR1 => VCC,
ADR2 => state_FSM_FFd2_4312,
ADR3 => VCC,
O => N453
);
N278_XUSED : X_BUF
generic map(
LOC => "SLICE_X1Y20",
PATHPULSE => 638 ps
)
port map (
I => N278_F5MUX_8059,
O => N278
);
N278_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X1Y20"
)
port map (
IA => N452,
IB => N453,
SEL => N278_BXINV_8050,
O => N278_F5MUX_8059
);
N278_BXINV : X_BUF
generic map(
LOC => "SLICE_X1Y20",
PATHPULSE => 638 ps
)
port map (
I => state_FSM_FFd1_4311,
O => N278_BXINV_8050
);
b_reg_mux0000_4_34_SW0_F : X_LUT4
generic map(
INIT => X"FCAC",
LOC => "SLICE_X1Y20"
)
port map (
ADR0 => b_reg_mux0000_4_3_0,
ADR1 => b_reg(4),
ADR2 => state_FSM_FFd2_4312,
ADR3 => b_reg_mux0000_4_12_0,
O => N452
);
b_reg_mux0000_4_34_SW1_G : X_LUT4
generic map(
INIT => X"FFCC",
LOC => "SLICE_X0Y21"
)
port map (
ADR0 => VCC,
ADR1 => state_FSM_FFd2_4312,
ADR2 => VCC,
ADR3 => b_reg(4),
O => N455
);
N279_XUSED : X_BUF
generic map(
LOC => "SLICE_X0Y21",
PATHPULSE => 638 ps
)
port map (
I => N279_F5MUX_8084,
O => N279
);
N279_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X0Y21"
)
port map (
IA => N454,
IB => N455,
SEL => N279_BXINV_8075,
O => N279_F5MUX_8084
);
N279_BXINV : X_BUF
generic map(
LOC => "SLICE_X0Y21",
PATHPULSE => 638 ps
)
port map (
I => state_FSM_FFd1_4311,
O => N279_BXINV_8075
);
b_reg_mux0000_4_34_SW1_F : X_LUT4
generic map(
INIT => X"FCB8",
LOC => "SLICE_X0Y21"
)
port map (
ADR0 => b_reg_mux0000_4_12_0,
ADR1 => state_FSM_FFd2_4312,
ADR2 => b_reg(4),
ADR3 => b_reg_mux0000_4_3_0,
O => N454
);
Sh1307_G : X_LUT4
generic map(
INIT => X"BB88",
LOC => "SLICE_X26Y23"
)
port map (
ADR0 => Sh1162_0,
ADR1 => a(1),
ADR2 => VCC,
ADR3 => Sh1182_0,
O => N371
);
Sh1307_XUSED : X_BUF
generic map(
LOC => "SLICE_X26Y23",
PATHPULSE => 638 ps
)
port map (
I => Sh1307_F5MUX_8109,
O => Sh1307
);
Sh1307_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X26Y23"
)
port map (
IA => N370,
IB => N371,
SEL => Sh1307_BXINV_8101,
O => Sh1307_F5MUX_8109
);
Sh1307_BXINV : X_BUF
generic map(
LOC => "SLICE_X26Y23",
PATHPULSE => 638 ps
)
port map (
I => a(3),
O => Sh1307_BXINV_8101
);
Sh1307_F : X_LUT4
generic map(
INIT => X"EE22",
LOC => "SLICE_X26Y23"
)
port map (
ADR0 => Sh1262_0,
ADR1 => a(1),
ADR2 => VCC,
ADR3 => Sh1242_0,
O => N370
);
Sh1601_G : X_LUT4
generic map(
INIT => X"DDDC",
LOC => "SLICE_X23Y12"
)
port map (
ADR0 => a(2),
ADR1 => Sh14412_0,
ADR2 => Sh14413_0,
ADR3 => Sh14416_4486,
O => N319
);
Sh160_XUSED : X_BUF
generic map(
LOC => "SLICE_X23Y12",
PATHPULSE => 638 ps
)
port map (
I => Sh160_F5MUX_8134,
O => Sh160
);
Sh160_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X23Y12"
)
port map (
IA => N318,
IB => N319,
SEL => Sh160_BXINV_8127,
O => Sh160_F5MUX_8134
);
Sh160_BXINV : X_BUF
generic map(
LOC => "SLICE_X23Y12",
PATHPULSE => 638 ps
)
port map (
I => a(4),
O => Sh160_BXINV_8127
);
Sh1601_F : X_LUT4
generic map(
INIT => X"FE54",
LOC => "SLICE_X23Y12"
)
port map (
ADR0 => a(2),
ADR1 => Sh12813_0,
ADR2 => Sh12816_0,
ADR3 => Sh1287_0,
O => N318
);
Sh1507_G : X_LUT4
generic map(
INIT => X"E4E4",
LOC => "SLICE_X29Y20"
)
port map (
ADR0 => a(1),
ADR1 => Sh1062_0,
ADR2 => Sh1042_0,
ADR3 => VCC,
O => N435
);
Sh1507_XUSED : X_BUF
generic map(
LOC => "SLICE_X29Y20",
PATHPULSE => 638 ps
)
port map (
I => Sh1507_F5MUX_8159,
O => Sh1507
);
Sh1507_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X29Y20"
)
port map (
IA => N434,
IB => N435,
SEL => Sh1507_BXINV_8151,
O => Sh1507_F5MUX_8159
);
Sh1507_BXINV : X_BUF
generic map(
LOC => "SLICE_X29Y20",
PATHPULSE => 638 ps
)
port map (
I => a(3),
O => Sh1507_BXINV_8151
);
Sh1507_F : X_LUT4
generic map(
INIT => X"ACAC",
LOC => "SLICE_X29Y20"
)
port map (
ADR0 => Sh1122_0,
ADR1 => Sh1142_0,
ADR2 => a(1),
ADR3 => VCC,
O => N434
);
Sh1427_G : X_LUT4
generic map(
INIT => X"F0CC",
LOC => "SLICE_X28Y18"
)
port map (
ADR0 => VCC,
ADR1 => Sh982_4493,
ADR2 => Sh962_0,
ADR3 => a(1),
O => N417
);
Sh13820_XUSED : X_BUF
generic map(
LOC => "SLICE_X28Y18",
PATHPULSE => 638 ps
)
port map (
I => Sh13820_F5MUX_8184,
O => Sh13820
);
Sh13820_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X28Y18"
)
port map (
IA => N416,
IB => N417,
SEL => Sh13820_BXINV_8176,
O => Sh13820_F5MUX_8184
);
Sh13820_BXINV : X_BUF
generic map(
LOC => "SLICE_X28Y18",
PATHPULSE => 638 ps
)
port map (
I => a(3),
O => Sh13820_BXINV_8176
);
Sh1427_F : X_LUT4
generic map(
INIT => X"EE44",
LOC => "SLICE_X28Y18"
)
port map (
ADR0 => a(1),
ADR1 => Sh1062_0,
ADR2 => VCC,
ADR3 => Sh1042_0,
O => N416
);
Sh1517_XUSED : X_BUF
generic map(
LOC => "SLICE_X23Y17",
PATHPULSE => 638 ps
)
port map (
I => Sh1517_F5MUX_8209,
O => Sh1517
);
Sh1517_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X23Y17"
)
port map (
IA => N432,
IB => N433,
SEL => Sh1517_BXINV_8201,
O => Sh1517_F5MUX_8209
);
Sh1517_BXINV : X_BUF
generic map(
LOC => "SLICE_X23Y17",
PATHPULSE => 638 ps
)
port map (
I => a(3),
O => Sh1517_BXINV_8201
);
Sh162_XUSED : X_BUF
generic map(
LOC => "SLICE_X27Y15",
PATHPULSE => 638 ps
)
port map (
I => Sh162_F5MUX_8234,
O => Sh162
);
Sh162_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X27Y15"
)
port map (
IA => N316,
IB => N317,
SEL => Sh162_BXINV_8227,
O => Sh162_F5MUX_8234
);
Sh162_BXINV : X_BUF
generic map(
LOC => "SLICE_X27Y15",
PATHPULSE => 638 ps
)
port map (
I => a(4),
O => Sh162_BXINV_8227
);
Sh40_XUSED : X_BUF
generic map(
LOC => "SLICE_X12Y24",
PATHPULSE => 638 ps
)
port map (
I => Sh40_F5MUX_8259,
O => Sh40
);
Sh40_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X12Y24"
)
port map (
IA => N368,
IB => N369,
SEL => Sh40_BXINV_8251,
O => Sh40_F5MUX_8259
);
Sh40_BXINV : X_BUF
generic map(
LOC => "SLICE_X12Y24",
PATHPULSE => 638 ps
)
port map (
I => b_reg(2),
O => Sh40_BXINV_8251
);
Sh32_XUSED : X_BUF
generic map(
LOC => "SLICE_X13Y26",
PATHPULSE => 638 ps
)
port map (
I => Sh32_F5MUX_8284,
O => Sh32
);
Sh32_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X13Y26"
)
port map (
IA => N352,
IB => N353,
SEL => Sh32_BXINV_8276,
O => Sh32_F5MUX_8284
);
Sh32_BXINV : X_BUF
generic map(
LOC => "SLICE_X13Y26",
PATHPULSE => 638 ps
)
port map (
I => b_reg(2),
O => Sh32_BXINV_8276
);
Sh163_XUSED : X_BUF
generic map(
LOC => "SLICE_X24Y16",
PATHPULSE => 638 ps
)
port map (
I => Sh163_F5MUX_8309,
O => Sh163
);
Sh163_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X24Y16"
)
port map (
IA => N310,
IB => N311,
SEL => Sh163_BXINV_8302,
O => Sh163_F5MUX_8309
);
Sh163_BXINV : X_BUF
generic map(
LOC => "SLICE_X24Y16",
PATHPULSE => 638 ps
)
port map (
I => a(4),
O => Sh163_BXINV_8302
);
Sh164_XUSED : X_BUF
generic map(
LOC => "SLICE_X25Y12",
PATHPULSE => 638 ps
)
port map (
I => Sh164_F5MUX_8334,
O => Sh164
);
Sh164_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X25Y12"
)
port map (
IA => N312,
IB => N313,
SEL => Sh164_BXINV_8327,
O => Sh164_F5MUX_8334
);
Sh164_BXINV : X_BUF
generic map(
LOC => "SLICE_X25Y12",
PATHPULSE => 638 ps
)
port map (
I => a(4),
O => Sh164_BXINV_8327
);
Sh4131_F : X_LUT4
generic map(
INIT => X"D8D8",
LOC => "SLICE_X15Y26"
)
port map (
ADR0 => b_reg(3),
ADR1 => Sh1,
ADR2 => Sh9,
ADR3 => VCC,
O => N424
);
Sh4131_G : X_LUT4
generic map(
INIT => X"ACAC",
LOC => "SLICE_X15Y26"
)
port map (
ADR0 => Sh29,
ADR1 => Sh5,
ADR2 => b_reg(3),
ADR3 => VCC,
O => N425
);
Sh41_XUSED : X_BUF
generic map(
LOC => "SLICE_X15Y26",
PATHPULSE => 638 ps
)
port map (
I => Sh41_F5MUX_8359,
O => Sh41
);
Sh41_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X15Y26"
)
port map (
IA => N424,
IB => N425,
SEL => Sh41_BXINV_8351,
O => Sh41_F5MUX_8359
);
Sh41_BXINV : X_BUF
generic map(
LOC => "SLICE_X15Y26",
PATHPULSE => 638 ps
)
port map (
I => b_reg(2),
O => Sh41_BXINV_8351
);
Sh1547_F : X_LUT4
generic map(
INIT => X"F0AA",
LOC => "SLICE_X27Y25"
)
port map (
ADR0 => Sh1182_0,
ADR1 => VCC,
ADR2 => Sh1162_0,
ADR3 => a(1),
O => N420
);
Sh1547_G : X_LUT4
generic map(
INIT => X"CFC0",
LOC => "SLICE_X27Y25"
)
port map (
ADR0 => VCC,
ADR1 => Sh1082_0,
ADR2 => a(1),
ADR3 => Sh1102_0,
O => N421
);
Sh1547_XUSED : X_BUF
generic map(
LOC => "SLICE_X27Y25",
PATHPULSE => 638 ps
)
port map (
I => Sh1547_F5MUX_8384,
O => Sh1547
);
Sh1547_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X27Y25"
)
port map (
IA => N420,
IB => N421,
SEL => Sh1547_BXINV_8376,
O => Sh1547_F5MUX_8384
);
Sh1547_BXINV : X_BUF
generic map(
LOC => "SLICE_X27Y25",
PATHPULSE => 638 ps
)
port map (
I => a(3),
O => Sh1547_BXINV_8376
);
Sh1387_F : X_LUT4
generic map(
INIT => X"F3C0",
LOC => "SLICE_X26Y21"
)
port map (
ADR0 => VCC,
ADR1 => a(1),
ADR2 => Sh1002_0,
ADR3 => Sh1022_0,
O => N400
);
Sh1387_G : X_LUT4
generic map(
INIT => X"CCAA",
LOC => "SLICE_X26Y21"
)
port map (
ADR0 => Sh1262_0,
ADR1 => Sh1242_0,
ADR2 => VCC,
ADR3 => a(1),
O => N401
);
Sh13420_XUSED : X_BUF
generic map(
LOC => "SLICE_X26Y21",
PATHPULSE => 638 ps
)
port map (
I => Sh13420_F5MUX_8409,
O => Sh13420
);
Sh13420_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X26Y21"
)
port map (
IA => N400,
IB => N401,
SEL => Sh13420_BXINV_8401,
O => Sh13420_F5MUX_8409
);
Sh13420_BXINV : X_BUF
generic map(
LOC => "SLICE_X26Y21",
PATHPULSE => 638 ps
)
port map (
I => a(3),
O => Sh13420_BXINV_8401
);
Sh3331_F : X_LUT4
generic map(
INIT => X"FA50",
LOC => "SLICE_X14Y27"
)
port map (
ADR0 => b_reg(3),
ADR1 => VCC,
ADR2 => Sh1,
ADR3 => Sh25,
O => N374
);
Sh3331_G : X_LUT4
generic map(
INIT => X"DD88",
LOC => "SLICE_X14Y27"
)
port map (
ADR0 => b_reg(3),
ADR1 => Sh21,
ADR2 => VCC,
ADR3 => Sh29,
O => N375
);
Sh33_XUSED : X_BUF
generic map(
LOC => "SLICE_X14Y27",
PATHPULSE => 638 ps
)
port map (
I => Sh33_F5MUX_8434,
O => Sh33
);
Sh33_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X14Y27"
)
port map (
IA => N374,
IB => N375,
SEL => Sh33_BXINV_8426,
O => Sh33_F5MUX_8434
);
Sh33_BXINV : X_BUF
generic map(
LOC => "SLICE_X14Y27",
PATHPULSE => 638 ps
)
port map (
I => b_reg(2),
O => Sh33_BXINV_8426
);
Sh1557_F : X_LUT4
generic map(
INIT => X"CFC0",
LOC => "SLICE_X27Y23"
)
port map (
ADR0 => VCC,
ADR1 => Sh1172_0,
ADR2 => a(1),
ADR3 => Sh1192_0,
O => N418
);
Sh1557_G : X_LUT4
generic map(
INIT => X"FC30",
LOC => "SLICE_X27Y23"
)
port map (
ADR0 => VCC,
ADR1 => a(1),
ADR2 => Sh1112_0,
ADR3 => Sh1092_0,
O => N419
);
Sh1557_XUSED : X_BUF
generic map(
LOC => "SLICE_X27Y23",
PATHPULSE => 638 ps
)
port map (
I => Sh1557_F5MUX_8459,
O => Sh1557
);
Sh1557_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X27Y23"
)
port map (
IA => N418,
IB => N419,
SEL => Sh1557_BXINV_8451,
O => Sh1557_F5MUX_8459
);
Sh1557_BXINV : X_BUF
generic map(
LOC => "SLICE_X27Y23",
PATHPULSE => 638 ps
)
port map (
I => a(3),
O => Sh1557_BXINV_8451
);
Sh4231_G : X_LUT4
generic map(
INIT => X"AFA0",
LOC => "SLICE_X15Y29"
)
port map (
ADR0 => Sh30,
ADR1 => VCC,
ADR2 => b_reg(3),
ADR3 => Sh6,
O => N429
);
Sh42_XUSED : X_BUF
generic map(
LOC => "SLICE_X15Y29",
PATHPULSE => 638 ps
)
port map (
I => Sh42_F5MUX_8484,
O => Sh42
);
Sh42_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X15Y29"
)
port map (
IA => N428,
IB => N429,
SEL => Sh42_BXINV_8476,
O => Sh42_F5MUX_8484
);
Sh42_BXINV : X_BUF
generic map(
LOC => "SLICE_X15Y29",
PATHPULSE => 638 ps
)
port map (
I => b_reg(2),
O => Sh42_BXINV_8476
);
Sh4231_F : X_LUT4
generic map(
INIT => X"CCF0",
LOC => "SLICE_X15Y29"
)
port map (
ADR0 => VCC,
ADR1 => Sh2,
ADR2 => Sh10,
ADR3 => b_reg(3),
O => N428
);
Sh3431_G : X_LUT4
generic map(
INIT => X"FA0A",
LOC => "SLICE_X15Y30"
)
port map (
ADR0 => Sh30,
ADR1 => VCC,
ADR2 => b_reg(3),
ADR3 => Sh22_4347,
O => N379
);
Sh34_XUSED : X_BUF
generic map(
LOC => "SLICE_X15Y30",
PATHPULSE => 638 ps
)
port map (
I => Sh34_F5MUX_8509,
O => Sh34
);
Sh34_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X15Y30"
)
port map (
IA => N378,
IB => N379,
SEL => Sh34_BXINV_8501,
O => Sh34_F5MUX_8509
);
Sh34_BXINV : X_BUF
generic map(
LOC => "SLICE_X15Y30",
PATHPULSE => 638 ps
)
port map (
I => b_reg(2),
O => Sh34_BXINV_8501
);
Sh3431_F : X_LUT4
generic map(
INIT => X"F0CC",
LOC => "SLICE_X15Y30"
)
port map (
ADR0 => VCC,
ADR1 => Sh2,
ADR2 => Sh26,
ADR3 => b_reg(3),
O => N378
);
Sh5031_G : X_LUT4
generic map(
INIT => X"CCAA",
LOC => "SLICE_X12Y23"
)
port map (
ADR0 => Sh14,
ADR1 => Sh6,
ADR2 => VCC,
ADR3 => b_reg(3),
O => N377
);
Sh50_XUSED : X_BUF
generic map(
LOC => "SLICE_X12Y23",
PATHPULSE => 638 ps
)
port map (
I => Sh50_F5MUX_8534,
O => Sh50
);
Sh50_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X12Y23"
)
port map (
IA => N376,
IB => N377,
SEL => Sh50_BXINV_8526,
O => Sh50_F5MUX_8534
);
Sh50_BXINV : X_BUF
generic map(
LOC => "SLICE_X12Y23",
PATHPULSE => 638 ps
)
port map (
I => b_reg(2),
O => Sh50_BXINV_8526
);
Sh5031_F : X_LUT4
generic map(
INIT => X"F0AA",
LOC => "SLICE_X12Y23"
)
port map (
ADR0 => Sh18,
ADR1 => VCC,
ADR2 => Sh10,
ADR3 => b_reg(3),
O => N376
);
Sh175_XUSED : X_BUF
generic map(
LOC => "SLICE_X25Y23",
PATHPULSE => 638 ps
)
port map (
I => Sh175_F5MUX_8559,
O => Sh175
);
Sh175_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X25Y23"
)
port map (
IA => N320,
IB => N321,
SEL => Sh175_BXINV_8552,
O => Sh175_F5MUX_8559
);
Sh175_BXINV : X_BUF
generic map(
LOC => "SLICE_X25Y23",
PATHPULSE => 638 ps
)
port map (
I => a(4),
O => Sh175_BXINV_8552
);
Sh1587_XUSED : X_BUF
generic map(
LOC => "SLICE_X28Y22",
PATHPULSE => 638 ps
)
port map (
I => Sh1587_F5MUX_8584,
O => Sh1587
);
Sh1587_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X28Y22"
)
port map (
IA => N426,
IB => N427,
SEL => Sh1587_BXINV_8576,
O => Sh1587_F5MUX_8584
);
Sh1587_BXINV : X_BUF
generic map(
LOC => "SLICE_X28Y22",
PATHPULSE => 638 ps
)
port map (
I => a(3),
O => Sh1587_BXINV_8576
);
Sh4331_G : X_LUT4
generic map(
INIT => X"F0CC",
LOC => "SLICE_X12Y29"
)
port map (
ADR0 => VCC,
ADR1 => Sh7,
ADR2 => Sh31,
ADR3 => b_reg(3),
O => N383
);
Sh43_XUSED : X_BUF
generic map(
LOC => "SLICE_X12Y29",
PATHPULSE => 638 ps
)
port map (
I => Sh43_F5MUX_8609,
O => Sh43
);
Sh43_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X12Y29"
)
port map (
IA => N382,
IB => N383,
SEL => Sh43_BXINV_8601,
O => Sh43_F5MUX_8609
);
Sh43_BXINV : X_BUF
generic map(
LOC => "SLICE_X12Y29",
PATHPULSE => 638 ps
)
port map (
I => b_reg(2),
O => Sh43_BXINV_8601
);
Sh4331_F : X_LUT4
generic map(
INIT => X"AAF0",
LOC => "SLICE_X12Y29"
)
port map (
ADR0 => Sh3,
ADR1 => VCC,
ADR2 => Sh11,
ADR3 => b_reg(3),
O => N382
);
Sh3531_G : X_LUT4
generic map(
INIT => X"FA0A",
LOC => "SLICE_X13Y31"
)
port map (
ADR0 => Sh31,
ADR1 => VCC,
ADR2 => b_reg(3),
ADR3 => Sh23_4457,
O => N357
);
Sh35_XUSED : X_BUF
generic map(
LOC => "SLICE_X13Y31",
PATHPULSE => 638 ps
)
port map (
I => Sh35_F5MUX_8634,
O => Sh35
);
Sh35_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X13Y31"
)
port map (
IA => N356,
IB => N357,
SEL => Sh35_BXINV_8626,
O => Sh35_F5MUX_8634
);
Sh35_BXINV : X_BUF
generic map(
LOC => "SLICE_X13Y31",
PATHPULSE => 638 ps
)
port map (
I => b_reg(2),
O => Sh35_BXINV_8626
);
Sh51_XUSED : X_BUF
generic map(
LOC => "SLICE_X13Y25",
PATHPULSE => 638 ps
)
port map (
I => Sh51_F5MUX_8659,
O => Sh51
);
Sh51_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X13Y25"
)
port map (
IA => N354,
IB => N355,
SEL => Sh51_BXINV_8651,
O => Sh51_F5MUX_8659
);
Sh51_BXINV : X_BUF
generic map(
LOC => "SLICE_X13Y25",
PATHPULSE => 638 ps
)
port map (
I => b_reg(2),
O => Sh51_BXINV_8651
);
Sh1597_XUSED : X_BUF
generic map(
LOC => "SLICE_X26Y26",
PATHPULSE => 638 ps
)
port map (
I => Sh1597_F5MUX_8684,
O => Sh1597
);
Sh1597_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X26Y26"
)
port map (
IA => N468,
IB => N469,
SEL => Sh1597_BXINV_8676,
O => Sh1597_F5MUX_8684
);
Sh1597_BXINV : X_BUF
generic map(
LOC => "SLICE_X26Y26",
PATHPULSE => 638 ps
)
port map (
I => a(3),
O => Sh1597_BXINV_8676
);
Sh178_XUSED : X_BUF
generic map(
LOC => "SLICE_X27Y14",
PATHPULSE => 638 ps
)
port map (
I => Sh178_F5MUX_8709,
O => Sh178
);
Sh178_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X27Y14"
)
port map (
IA => N322,
IB => N323,
SEL => Sh178_BXINV_8702,
O => Sh178_F5MUX_8709
);
Sh178_BXINV : X_BUF
generic map(
LOC => "SLICE_X27Y14",
PATHPULSE => 638 ps
)
port map (
I => a(4),
O => Sh178_BXINV_8702
);
Sh44_XUSED : X_BUF
generic map(
LOC => "SLICE_X12Y22",
PATHPULSE => 638 ps
)
port map (
I => Sh44_F5MUX_8734,
O => Sh44
);
Sh44_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X12Y22"
)
port map (
IA => N386,
IB => N387,
SEL => Sh44_BXINV_8726,
O => Sh44_F5MUX_8734
);
Sh44_BXINV : X_BUF
generic map(
LOC => "SLICE_X12Y22",
PATHPULSE => 638 ps
)
port map (
I => b_reg(2),
O => Sh44_BXINV_8726
);
Sh60_XUSED : X_BUF
generic map(
LOC => "SLICE_X12Y27",
PATHPULSE => 638 ps
)
port map (
I => Sh60_F5MUX_8759,
O => Sh60
);
Sh60_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X12Y27"
)
port map (
IA => N384,
IB => N385,
SEL => Sh60_BXINV_8751,
O => Sh60_F5MUX_8759
);
Sh60_BXINV : X_BUF
generic map(
LOC => "SLICE_X12Y27",
PATHPULSE => 638 ps
)
port map (
I => b_reg(2),
O => Sh60_BXINV_8751
);
Sh36_XUSED : X_BUF
generic map(
LOC => "SLICE_X13Y24",
PATHPULSE => 638 ps
)
port map (
I => Sh36_F5MUX_8784,
O => Sh36
);
Sh36_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X13Y24"
)
port map (
IA => N360,
IB => N361,
SEL => Sh36_BXINV_8776,
O => Sh36_F5MUX_8784
);
Sh36_BXINV : X_BUF
generic map(
LOC => "SLICE_X13Y24",
PATHPULSE => 638 ps
)
port map (
I => b_reg(2),
O => Sh36_BXINV_8776
);
Sh52_XUSED : X_BUF
generic map(
LOC => "SLICE_X13Y18",
PATHPULSE => 638 ps
)
port map (
I => Sh52_F5MUX_8809,
O => Sh52
);
Sh52_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X13Y18"
)
port map (
IA => N358,
IB => N359,
SEL => Sh52_BXINV_8801,
O => Sh52_F5MUX_8809
);
Sh52_BXINV : X_BUF
generic map(
LOC => "SLICE_X13Y18",
PATHPULSE => 638 ps
)
port map (
I => b_reg(2),
O => Sh52_BXINV_8801
);
Sh45_XUSED : X_BUF
generic map(
LOC => "SLICE_X16Y26",
PATHPULSE => 638 ps
)
port map (
I => Sh45_F5MUX_8834,
O => Sh45
);
Sh45_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X16Y26"
)
port map (
IA => N430,
IB => N431,
SEL => Sh45_BXINV_8826,
O => Sh45_F5MUX_8834
);
Sh45_BXINV : X_BUF
generic map(
LOC => "SLICE_X16Y26",
PATHPULSE => 638 ps
)
port map (
I => b_reg(2),
O => Sh45_BXINV_8826
);
Sh37_XUSED : X_BUF
generic map(
LOC => "SLICE_X14Y26",
PATHPULSE => 638 ps
)
port map (
I => Sh37_F5MUX_8859,
O => Sh37
);
Sh37_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X14Y26"
)
port map (
IA => N390,
IB => N391,
SEL => Sh37_BXINV_8851,
O => Sh37_F5MUX_8859
);
Sh37_BXINV : X_BUF
generic map(
LOC => "SLICE_X14Y26",
PATHPULSE => 638 ps
)
port map (
I => b_reg(2),
O => Sh37_BXINV_8851
);
Sh53_XUSED : X_BUF
generic map(
LOC => "SLICE_X15Y27",
PATHPULSE => 638 ps
)
port map (
I => Sh53_F5MUX_8884,
O => Sh53
);
Sh53_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X15Y27"
)
port map (
IA => N388,
IB => N389,
SEL => Sh53_BXINV_8876,
O => Sh53_F5MUX_8884
);
Sh53_BXINV : X_BUF
generic map(
LOC => "SLICE_X15Y27",
PATHPULSE => 638 ps
)
port map (
I => b_reg(2),
O => Sh53_BXINV_8876
);
Sh46_XUSED : X_BUF
generic map(
LOC => "SLICE_X14Y28",
PATHPULSE => 638 ps
)
port map (
I => Sh46_F5MUX_8909,
O => Sh46
);
Sh46_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X14Y28"
)
port map (
IA => N422,
IB => N423,
SEL => Sh46_BXINV_8901,
O => Sh46_F5MUX_8909
);
Sh46_BXINV : X_BUF
generic map(
LOC => "SLICE_X14Y28",
PATHPULSE => 638 ps
)
port map (
I => b_reg(2),
O => Sh46_BXINV_8901
);
Sh38_XUSED : X_BUF
generic map(
LOC => "SLICE_X14Y31",
PATHPULSE => 638 ps
)
port map (
I => Sh38_F5MUX_8934,
O => Sh38
);
Sh38_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X14Y31"
)
port map (
IA => N394,
IB => N395,
SEL => Sh38_BXINV_8926,
O => Sh38_F5MUX_8934
);
Sh38_BXINV : X_BUF
generic map(
LOC => "SLICE_X14Y31",
PATHPULSE => 638 ps
)
port map (
I => b_reg(2),
O => Sh38_BXINV_8926
);
Sh54_XUSED : X_BUF
generic map(
LOC => "SLICE_X12Y28",
PATHPULSE => 638 ps
)
port map (
I => Sh54_F5MUX_8959,
O => Sh54
);
Sh54_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X12Y28"
)
port map (
IA => N392,
IB => N393,
SEL => Sh54_BXINV_8951,
O => Sh54_F5MUX_8959
);
Sh54_BXINV : X_BUF
generic map(
LOC => "SLICE_X12Y28",
PATHPULSE => 638 ps
)
port map (
I => b_reg(2),
O => Sh54_BXINV_8951
);
Sh47_XUSED : X_BUF
generic map(
LOC => "SLICE_X13Y21",
PATHPULSE => 638 ps
)
port map (
I => Sh47_F5MUX_8984,
O => Sh47
);
Sh47_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X13Y21"
)
port map (
IA => N398,
IB => N399,
SEL => Sh47_BXINV_8976,
O => Sh47_F5MUX_8984
);
Sh47_BXINV : X_BUF
generic map(
LOC => "SLICE_X13Y21",
PATHPULSE => 638 ps
)
port map (
I => b_reg(2),
O => Sh47_BXINV_8976
);
Sh63_XUSED : X_BUF
generic map(
LOC => "SLICE_X12Y33",
PATHPULSE => 638 ps
)
port map (
I => Sh63_F5MUX_9009,
O => Sh63
);
Sh63_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X12Y33"
)
port map (
IA => N396,
IB => N397,
SEL => Sh63_BXINV_9001,
O => Sh63_F5MUX_9009
);
Sh63_BXINV : X_BUF
generic map(
LOC => "SLICE_X12Y33",
PATHPULSE => 638 ps
)
port map (
I => b_reg(2),
O => Sh63_BXINV_9001
);
Sh39_XUSED : X_BUF
generic map(
LOC => "SLICE_X13Y28",
PATHPULSE => 638 ps
)
port map (
I => Sh39_F5MUX_9034,
O => Sh39
);
Sh39_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X13Y28"
)
port map (
IA => N364,
IB => N365,
SEL => Sh39_BXINV_9026,
O => Sh39_F5MUX_9034
);
Sh39_BXINV : X_BUF
generic map(
LOC => "SLICE_X13Y28",
PATHPULSE => 638 ps
)
port map (
I => b_reg(2),
O => Sh39_BXINV_9026
);
Sh55_XUSED : X_BUF
generic map(
LOC => "SLICE_X13Y30",
PATHPULSE => 638 ps
)
port map (
I => Sh55_F5MUX_9059,
O => Sh55
);
Sh55_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X13Y30"
)
port map (
IA => N362,
IB => N363,
SEL => Sh55_BXINV_9051,
O => Sh55_F5MUX_9059
);
Sh55_BXINV : X_BUF
generic map(
LOC => "SLICE_X13Y30",
PATHPULSE => 638 ps
)
port map (
I => b_reg(2),
O => Sh55_BXINV_9051
);
Sh56_XUSED : X_BUF
generic map(
LOC => "SLICE_X13Y27",
PATHPULSE => 638 ps
)
port map (
I => Sh56_F5MUX_9084,
O => Sh56
);
Sh56_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X13Y27"
)
port map (
IA => N366,
IB => N367,
SEL => Sh56_BXINV_9076,
O => Sh56_F5MUX_9084
);
Sh56_BXINV : X_BUF
generic map(
LOC => "SLICE_X13Y27",
PATHPULSE => 638 ps
)
port map (
I => b_reg(2),
O => Sh56_BXINV_9076
);
Sh48_XUSED : X_BUF
generic map(
LOC => "SLICE_X12Y25",
PATHPULSE => 638 ps
)
port map (
I => Sh48_F5MUX_9109,
O => Sh48
);
Sh48_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X12Y25"
)
port map (
IA => N350,
IB => N351,
SEL => Sh48_BXINV_9101,
O => Sh48_F5MUX_9109
);
Sh48_BXINV : X_BUF
generic map(
LOC => "SLICE_X12Y25",
PATHPULSE => 638 ps
)
port map (
I => b_reg(2),
O => Sh48_BXINV_9101
);
Sh49_XUSED : X_BUF
generic map(
LOC => "SLICE_X14Y24",
PATHPULSE => 638 ps
)
port map (
I => Sh49_F5MUX_9134,
O => Sh49
);
Sh49_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X14Y24"
)
port map (
IA => N372,
IB => N373,
SEL => Sh49_BXINV_9126,
O => Sh49_F5MUX_9134
);
Sh49_BXINV : X_BUF
generic map(
LOC => "SLICE_X14Y24",
PATHPULSE => 638 ps
)
port map (
I => b_reg(2),
O => Sh49_BXINV_9126
);
Sh59_XUSED : X_BUF
generic map(
LOC => "SLICE_X12Y31",
PATHPULSE => 638 ps
)
port map (
I => Sh59_F5MUX_9159,
O => Sh59
);
Sh59_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X12Y31"
)
port map (
IA => N380,
IB => N381,
SEL => Sh59_BXINV_9151,
O => Sh59_F5MUX_9159
);
Sh59_BXINV : X_BUF
generic map(
LOC => "SLICE_X12Y31",
PATHPULSE => 638 ps
)
port map (
I => b_reg(2),
O => Sh59_BXINV_9151
);
N275_XUSED : X_BUF
generic map(
LOC => "SLICE_X3Y17",
PATHPULSE => 638 ps
)
port map (
I => N275_F5MUX_9184,
O => N275
);
N275_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X3Y17"
)
port map (
IA => N448,
IB => N449,
SEL => N275_BXINV_9175,
O => N275_F5MUX_9184
);
N275_BXINV : X_BUF
generic map(
LOC => "SLICE_X3Y17",
PATHPULSE => 638 ps
)
port map (
I => state_FSM_FFd1_4311,
O => N275_BXINV_9175
);
N276_XUSED : X_BUF
generic map(
LOC => "SLICE_X2Y17",
PATHPULSE => 638 ps
)
port map (
I => N276_F5MUX_9209,
O => N276
);
N276_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X2Y17"
)
port map (
IA => N450,
IB => N451,
SEL => N276_BXINV_9200,
O => N276_F5MUX_9209
);
N276_BXINV : X_BUF
generic map(
LOC => "SLICE_X2Y17",
PATHPULSE => 638 ps
)
port map (
I => state_FSM_FFd1_4311,
O => N276_BXINV_9200
);
b_reg_8_DXMUX : X_BUF
generic map(
LOC => "SLICE_X16Y15",
PATHPULSE => 638 ps
)
port map (
I => b_reg_8_F5MUX_9238,
O => b_reg_8_DXMUX_9240
);
b_reg_8_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X16Y15"
)
port map (
IA => N532,
IB => N533,
SEL => b_reg_8_BXINV_9231,
O => b_reg_8_F5MUX_9238
);
b_reg_8_BXINV : X_BUF
generic map(
LOC => "SLICE_X16Y15",
PATHPULSE => 638 ps
)
port map (
I => b_8_XORF_5755,
O => b_reg_8_BXINV_9231
);
b_reg_8_CLKINV : X_BUF
generic map(
LOC => "SLICE_X16Y15",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => b_reg_8_CLKINV_9222
);
b_reg_9_DXMUX : X_BUF
generic map(
LOC => "SLICE_X16Y14",
PATHPULSE => 638 ps
)
port map (
I => b_reg_9_F5MUX_9274,
O => b_reg_9_DXMUX_9276
);
b_reg_9_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X16Y14"
)
port map (
IA => N530,
IB => N531,
SEL => b_reg_9_BXINV_9267,
O => b_reg_9_F5MUX_9274
);
b_reg_9_BXINV : X_BUF
generic map(
LOC => "SLICE_X16Y14",
PATHPULSE => 638 ps
)
port map (
I => b_8_XORG_5744,
O => b_reg_9_BXINV_9267
);
b_reg_9_CLKINV : X_BUF
generic map(
LOC => "SLICE_X16Y14",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => b_reg_9_CLKINV_9258
);
N272_XUSED : X_BUF
generic map(
LOC => "SLICE_X3Y13",
PATHPULSE => 638 ps
)
port map (
I => N272_F5MUX_9306,
O => N272
);
N272_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X3Y13"
)
port map (
IA => N444,
IB => N445,
SEL => N272_BXINV_9297,
O => N272_F5MUX_9306
);
N272_BXINV : X_BUF
generic map(
LOC => "SLICE_X3Y13",
PATHPULSE => 638 ps
)
port map (
I => state_FSM_FFd1_4311,
O => N272_BXINV_9297
);
N273_XUSED : X_BUF
generic map(
LOC => "SLICE_X2Y13",
PATHPULSE => 638 ps
)
port map (
I => N273_F5MUX_9331,
O => N273
);
N273_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X2Y13"
)
port map (
IA => N446,
IB => N447,
SEL => N273_BXINV_9322,
O => N273_F5MUX_9331
);
N273_BXINV : X_BUF
generic map(
LOC => "SLICE_X2Y13",
PATHPULSE => 638 ps
)
port map (
I => state_FSM_FFd1_4311,
O => N273_BXINV_9322
);
Sh1_XUSED : X_BUF
generic map(
LOC => "SLICE_X13Y35",
PATHPULSE => 638 ps
)
port map (
I => Sh1_F5MUX_9356,
O => Sh1
);
Sh1_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X13Y35"
)
port map (
IA => N404,
IB => N405,
SEL => Sh1_BXINV_9349,
O => Sh1_F5MUX_9356
);
Sh1_BXINV : X_BUF
generic map(
LOC => "SLICE_X13Y35",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh1_BXINV_9349
);
Sh2_XUSED : X_BUF
generic map(
LOC => "SLICE_X13Y32",
PATHPULSE => 638 ps
)
port map (
I => Sh2_F5MUX_9381,
O => Sh2
);
Sh2_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X13Y32"
)
port map (
IA => Sh211,
IB => Sh210,
SEL => Sh2_BXINV_9374,
O => Sh2_F5MUX_9381
);
Sh2_BXINV : X_BUF
generic map(
LOC => "SLICE_X13Y32",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh2_BXINV_9374
);
Sh5_XUSED : X_BUF
generic map(
LOC => "SLICE_X12Y19",
PATHPULSE => 638 ps
)
port map (
I => Sh5_F5MUX_9406,
O => Sh5
);
Sh5_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X12Y19"
)
port map (
IA => N476,
IB => N477,
SEL => Sh5_BXINV_9399,
O => Sh5_F5MUX_9406
);
Sh5_BXINV : X_BUF
generic map(
LOC => "SLICE_X12Y19",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh5_BXINV_9399
);
N269_XUSED : X_BUF
generic map(
LOC => "SLICE_X12Y8",
PATHPULSE => 638 ps
)
port map (
I => N269_F5MUX_9431,
O => N269
);
N269_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X12Y8"
)
port map (
IA => N440,
IB => N441,
SEL => N269_BXINV_9422,
O => N269_F5MUX_9431
);
N269_BXINV : X_BUF
generic map(
LOC => "SLICE_X12Y8",
PATHPULSE => 638 ps
)
port map (
I => state_FSM_FFd1_4311,
O => N269_BXINV_9422
);
N270_XUSED : X_BUF
generic map(
LOC => "SLICE_X9Y3",
PATHPULSE => 638 ps
)
port map (
I => N270_F5MUX_9456,
O => N270
);
N270_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X9Y3"
)
port map (
IA => N442,
IB => N443,
SEL => N270_BXINV_9447,
O => N270_F5MUX_9456
);
N270_BXINV : X_BUF
generic map(
LOC => "SLICE_X9Y3",
PATHPULSE => 638 ps
)
port map (
I => state_FSM_FFd1_4311,
O => N270_BXINV_9447
);
Sh6_XUSED : X_BUF
generic map(
LOC => "SLICE_X12Y18",
PATHPULSE => 638 ps
)
port map (
I => Sh6_F5MUX_9481,
O => Sh6
);
Sh6_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X12Y18"
)
port map (
IA => N462,
IB => N463,
SEL => Sh6_BXINV_9474,
O => Sh6_F5MUX_9481
);
Sh6_BXINV : X_BUF
generic map(
LOC => "SLICE_X12Y18",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh6_BXINV_9474
);
Sh9_XUSED : X_BUF
generic map(
LOC => "SLICE_X15Y15",
PATHPULSE => 638 ps
)
port map (
I => Sh9_F5MUX_9506,
O => Sh9
);
Sh9_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X15Y15"
)
port map (
IA => N474,
IB => N475,
SEL => Sh9_BXINV_9499,
O => Sh9_F5MUX_9506
);
Sh9_BXINV : X_BUF
generic map(
LOC => "SLICE_X15Y15",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh9_BXINV_9499
);
b_reg_0_1_DXMUX : X_BUF
generic map(
LOC => "SLICE_X14Y15",
PATHPULSE => 638 ps
)
port map (
I => b_reg_0_1_FXMUX_9537,
O => b_reg_0_1_DXMUX_9538
);
b_reg_0_1_XUSED : X_BUF
generic map(
LOC => "SLICE_X14Y15",
PATHPULSE => 638 ps
)
port map (
I => b_reg_0_1_FXMUX_9537,
O => b_reg_mux0000_0_Q
);
b_reg_0_1_FXMUX : X_BUF
generic map(
LOC => "SLICE_X14Y15",
PATHPULSE => 638 ps
)
port map (
I => b_reg_0_1_F5MUX_9536,
O => b_reg_0_1_FXMUX_9537
);
b_reg_0_1_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X14Y15"
)
port map (
IA => N524,
IB => N525,
SEL => b_reg_0_1_BXINV_9529,
O => b_reg_0_1_F5MUX_9536
);
b_reg_0_1_BXINV : X_BUF
generic map(
LOC => "SLICE_X14Y15",
PATHPULSE => 638 ps
)
port map (
I => b_0_XORF_5589,
O => b_reg_0_1_BXINV_9529
);
b_reg_0_1_CLKINV : X_BUF
generic map(
LOC => "SLICE_X14Y15",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => b_reg_0_1_CLKINV_9521
);
hex_digit_i_0_DXMUX : X_BUF
generic map(
LOC => "SLICE_X28Y15",
PATHPULSE => 638 ps
)
port map (
I => hex_digit_i_0_F5MUX_9572,
O => hex_digit_i_0_DXMUX_9574
);
hex_digit_i_0_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X28Y15"
)
port map (
IA => Mmux_hex_digit_i_mux0001_4_9562,
IB => Mmux_hex_digit_i_mux0001_3_9570,
SEL => hex_digit_i_0_BXINV_9564,
O => hex_digit_i_0_F5MUX_9572
);
hex_digit_i_0_BXINV : X_BUF
generic map(
LOC => "SLICE_X28Y15",
PATHPULSE => 638 ps
)
port map (
I => LED_flash_cnt(9),
O => hex_digit_i_0_BXINV_9564
);
hex_digit_i_0_CLKINV : X_BUF
generic map(
LOC => "SLICE_X28Y15",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => hex_digit_i_0_CLKINV_9555
);
N266_XUSED : X_BUF
generic map(
LOC => "SLICE_X12Y11",
PATHPULSE => 638 ps
)
port map (
I => N266_F5MUX_9604,
O => N266
);
N266_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X12Y11"
)
port map (
IA => N436,
IB => N437,
SEL => N266_BXINV_9595,
O => N266_F5MUX_9604
);
N266_BXINV : X_BUF
generic map(
LOC => "SLICE_X12Y11",
PATHPULSE => 638 ps
)
port map (
I => state_FSM_FFd1_4311,
O => N266_BXINV_9595
);
N267_XUSED : X_BUF
generic map(
LOC => "SLICE_X13Y11",
PATHPULSE => 638 ps
)
port map (
I => N267_F5MUX_9629,
O => N267
);
N267_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X13Y11"
)
port map (
IA => N438,
IB => N439,
SEL => N267_BXINV_9620,
O => N267_F5MUX_9629
);
N267_BXINV : X_BUF
generic map(
LOC => "SLICE_X13Y11",
PATHPULSE => 638 ps
)
port map (
I => state_FSM_FFd1_4311,
O => N267_BXINV_9620
);
i_cnt_3_DXMUX : X_BUF
generic map(
LOC => "SLICE_X19Y14",
PATHPULSE => 638 ps
)
port map (
I => i_cnt_3_F5MUX_9658,
O => i_cnt_3_DXMUX_9660
);
i_cnt_3_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X19Y14"
)
port map (
IA => i_cnt_mux0001_0_561_9649,
IB => i_cnt_mux0001_0_56,
SEL => i_cnt_3_BXINV_9651,
O => i_cnt_3_F5MUX_9658
);
i_cnt_3_BXINV : X_BUF
generic map(
LOC => "SLICE_X19Y14",
PATHPULSE => 638 ps
)
port map (
I => state_FSM_FFd2_4312,
O => i_cnt_3_BXINV_9651
);
i_cnt_3_CLKINV : X_BUF
generic map(
LOC => "SLICE_X19Y14",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => i_cnt_3_CLKINV_9642
);
hex_digit_i_1_DXMUX : X_BUF
generic map(
LOC => "SLICE_X27Y12",
PATHPULSE => 638 ps
)
port map (
I => hex_digit_i_1_F5MUX_9694,
O => hex_digit_i_1_DXMUX_9696
);
hex_digit_i_1_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X27Y12"
)
port map (
IA => Mmux_hex_digit_i_mux0001_41_9684,
IB => Mmux_hex_digit_i_mux0001_31_9692,
SEL => hex_digit_i_1_BXINV_9686,
O => hex_digit_i_1_F5MUX_9694
);
hex_digit_i_1_BXINV : X_BUF
generic map(
LOC => "SLICE_X27Y12",
PATHPULSE => 638 ps
)
port map (
I => LED_flash_cnt(9),
O => hex_digit_i_1_BXINV_9686
);
hex_digit_i_1_CLKINV : X_BUF
generic map(
LOC => "SLICE_X27Y12",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => hex_digit_i_1_CLKINV_9677
);
hex_digit_i_2_DXMUX : X_BUF
generic map(
LOC => "SLICE_X27Y13",
PATHPULSE => 638 ps
)
port map (
I => hex_digit_i_2_F5MUX_9730,
O => hex_digit_i_2_DXMUX_9732
);
hex_digit_i_2_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X27Y13"
)
port map (
IA => Mmux_hex_digit_i_mux0001_42_9720,
IB => Mmux_hex_digit_i_mux0001_32_9728,
SEL => hex_digit_i_2_BXINV_9722,
O => hex_digit_i_2_F5MUX_9730
);
hex_digit_i_2_BXINV : X_BUF
generic map(
LOC => "SLICE_X27Y13",
PATHPULSE => 638 ps
)
port map (
I => LED_flash_cnt(9),
O => hex_digit_i_2_BXINV_9722
);
hex_digit_i_2_CLKINV : X_BUF
generic map(
LOC => "SLICE_X27Y13",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => hex_digit_i_2_CLKINV_9713
);
hex_digit_i_3_DXMUX : X_BUF
generic map(
LOC => "SLICE_X26Y12",
PATHPULSE => 638 ps
)
port map (
I => hex_digit_i_3_F5MUX_9766,
O => hex_digit_i_3_DXMUX_9768
);
hex_digit_i_3_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X26Y12"
)
port map (
IA => Mmux_hex_digit_i_mux0001_43_9756,
IB => Mmux_hex_digit_i_mux0001_33_9764,
SEL => hex_digit_i_3_BXINV_9758,
O => hex_digit_i_3_F5MUX_9766
);
hex_digit_i_3_BXINV : X_BUF
generic map(
LOC => "SLICE_X26Y12",
PATHPULSE => 638 ps
)
port map (
I => LED_flash_cnt(9),
O => hex_digit_i_3_BXINV_9758
);
hex_digit_i_3_CLKINV : X_BUF
generic map(
LOC => "SLICE_X26Y12",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => hex_digit_i_3_CLKINV_9749
);
Sh150_XUSED : X_BUF
generic map(
LOC => "SLICE_X27Y22",
PATHPULSE => 638 ps
)
port map (
I => Sh150,
O => Sh150_0
);
Sh150_YUSED : X_BUF
generic map(
LOC => "SLICE_X27Y22",
PATHPULSE => 638 ps
)
port map (
I => Sh15016_O_pack_1,
O => Sh15016_O
);
Sh143_XUSED : X_BUF
generic map(
LOC => "SLICE_X25Y22",
PATHPULSE => 638 ps
)
port map (
I => Sh143,
O => Sh143_0
);
Sh143_YUSED : X_BUF
generic map(
LOC => "SLICE_X25Y22",
PATHPULSE => 638 ps
)
port map (
I => Sh14316_pack_1,
O => Sh14316_4518
);
Sh144_XUSED : X_BUF
generic map(
LOC => "SLICE_X23Y13",
PATHPULSE => 638 ps
)
port map (
I => Sh144,
O => Sh144_0
);
Sh144_YUSED : X_BUF
generic map(
LOC => "SLICE_X23Y13",
PATHPULSE => 638 ps
)
port map (
I => Sh14416_pack_1,
O => Sh14416_4486
);
Sh154_XUSED : X_BUF
generic map(
LOC => "SLICE_X28Y25",
PATHPULSE => 638 ps
)
port map (
I => Sh154,
O => Sh154_0
);
Sh154_YUSED : X_BUF
generic map(
LOC => "SLICE_X28Y25",
PATHPULSE => 638 ps
)
port map (
I => Sh15416_O_pack_1,
O => Sh15416_O
);
Sh147_XUSED : X_BUF
generic map(
LOC => "SLICE_X25Y16",
PATHPULSE => 638 ps
)
port map (
I => Sh147,
O => Sh147_0
);
Sh147_YUSED : X_BUF
generic map(
LOC => "SLICE_X25Y16",
PATHPULSE => 638 ps
)
port map (
I => Sh14713_pack_1,
O => Sh14713_4500
);
Sh14832 : X_LUT4
generic map(
INIT => X"FE0E",
LOC => "SLICE_X24Y12"
)
port map (
ADR0 => Sh14816_0,
ADR1 => Sh14813_0,
ADR2 => a(2),
ADR3 => Sh1487_4504,
O => Sh148
);
Sh148_XUSED : X_BUF
generic map(
LOC => "SLICE_X24Y12",
PATHPULSE => 638 ps
)
port map (
I => Sh148,
O => Sh148_0
);
Sh148_YUSED : X_BUF
generic map(
LOC => "SLICE_X24Y12",
PATHPULSE => 638 ps
)
port map (
I => Sh1487_pack_1,
O => Sh1487_4504
);
Sh1487 : X_LUT4
generic map(
INIT => X"EE22",
LOC => "SLICE_X24Y12"
)
port map (
ADR0 => Sh112,
ADR1 => a(3),
ADR2 => VCC,
ADR3 => Sh104,
O => Sh1487_pack_1
);
Sh15932 : X_LUT4
generic map(
INIT => X"BBB8",
LOC => "SLICE_X25Y26"
)
port map (
ADR0 => Sh1597,
ADR1 => a(2),
ADR2 => Sh1313,
ADR3 => Sh1310_0,
O => Sh159
);
Sh159_XUSED : X_BUF
generic map(
LOC => "SLICE_X25Y26",
PATHPULSE => 638 ps
)
port map (
I => Sh159,
O => Sh159_0
);
Sh159_YUSED : X_BUF
generic map(
LOC => "SLICE_X25Y26",
PATHPULSE => 638 ps
)
port map (
I => Sh1313_pack_1,
O => Sh1313
);
Sh15916 : X_LUT4
generic map(
INIT => X"3202",
LOC => "SLICE_X25Y26"
)
port map (
ADR0 => Sh1272_0,
ADR1 => a(3),
ADR2 => a(1),
ADR3 => Sh1252_0,
O => Sh1313_pack_1
);
Sh731 : X_LUT4
generic map(
INIT => X"FC0C",
LOC => "SLICE_X15Y21"
)
port map (
ADR0 => VCC,
ADR1 => Sh41,
ADR2 => b_reg(4),
ADR3 => Sh57,
O => Sh73
);
Sh73_YUSED : X_BUF
generic map(
LOC => "SLICE_X15Y21",
PATHPULSE => 638 ps
)
port map (
I => Sh57_pack_1,
O => Sh57
);
Sh5731 : X_LUT4
generic map(
INIT => X"F0CC",
LOC => "SLICE_X15Y21"
)
port map (
ADR0 => VCC,
ADR1 => Sh5720_0,
ADR2 => Sh5320_0,
ADR3 => b_reg(2),
O => Sh57_pack_1
);
Sh741 : X_LUT4
generic map(
INIT => X"F5A0",
LOC => "SLICE_X14Y29"
)
port map (
ADR0 => b_reg(4),
ADR1 => VCC,
ADR2 => Sh58,
ADR3 => Sh42,
O => Sh74
);
Sh74_YUSED : X_BUF
generic map(
LOC => "SLICE_X14Y29",
PATHPULSE => 638 ps
)
port map (
I => Sh58_pack_1,
O => Sh58
);
Sh5831 : X_LUT4
generic map(
INIT => X"EE44",
LOC => "SLICE_X14Y29"
)
port map (
ADR0 => b_reg(2),
ADR1 => Sh5820_0,
ADR2 => VCC,
ADR3 => Sh5420_0,
O => Sh58_pack_1
);
Sh771 : X_LUT4
generic map(
INIT => X"FC0C",
LOC => "SLICE_X15Y23"
)
port map (
ADR0 => VCC,
ADR1 => Sh45,
ADR2 => b_reg(4),
ADR3 => Sh61,
O => Sh77
);
Sh77_YUSED : X_BUF
generic map(
LOC => "SLICE_X15Y23",
PATHPULSE => 638 ps
)
port map (
I => Sh61_pack_1,
O => Sh61
);
Sh6131 : X_LUT4
generic map(
INIT => X"CCAA",
LOC => "SLICE_X15Y23"
)
port map (
ADR0 => Sh337_0,
ADR1 => Sh5720_0,
ADR2 => VCC,
ADR3 => b_reg(2),
O => Sh61_pack_1
);
Sh781 : X_LUT4
generic map(
INIT => X"F5A0",
LOC => "SLICE_X16Y29"
)
port map (
ADR0 => b_reg(4),
ADR1 => VCC,
ADR2 => Sh62,
ADR3 => Sh46,
O => Sh78
);
Sh78_YUSED : X_BUF
generic map(
LOC => "SLICE_X16Y29",
PATHPULSE => 638 ps
)
port map (
I => Sh62_pack_1,
O => Sh62
);
Sh6231 : X_LUT4
generic map(
INIT => X"CACA",
LOC => "SLICE_X16Y29"
)
port map (
ADR0 => Sh347_0,
ADR1 => Sh5820_0,
ADR2 => b_reg(2),
ADR3 => VCC,
O => Sh62_pack_1
);
Sh14731_SW0 : X_LUT4
generic map(
INIT => X"AAAF",
LOC => "SLICE_X25Y17"
)
port map (
ADR0 => a(2),
ADR1 => VCC,
ADR2 => Sh14713_4500,
ADR3 => Sh14716_4501,
O => N249
);
N249_XUSED : X_BUF
generic map(
LOC => "SLICE_X25Y17",
PATHPULSE => 638 ps
)
port map (
I => N249,
O => N249_0
);
N249_YUSED : X_BUF
generic map(
LOC => "SLICE_X25Y17",
PATHPULSE => 638 ps
)
port map (
I => Sh14716_pack_1,
O => Sh14716_4501
);
Sh14716 : X_LUT4
generic map(
INIT => X"3120",
LOC => "SLICE_X25Y17"
)
port map (
ADR0 => a(1),
ADR1 => a(3),
ADR2 => Sh1132_0,
ADR3 => Sh1152_0,
O => Sh14716_pack_1
);
Sh1022 : X_LUT4
generic map(
INIT => X"8BD1",
LOC => "SLICE_X18Y12"
)
port map (
ADR0 => a(6),
ADR1 => N243_0,
ADR2 => a(5),
ADR3 => Mxor_ba_xor_Result_5_1_SW1_O,
O => Sh1022_10084
);
Sh1022_XUSED : X_BUF
generic map(
LOC => "SLICE_X18Y12",
PATHPULSE => 638 ps
)
port map (
I => Sh1022_10084,
O => Sh1022_0
);
Sh1022_YUSED : X_BUF
generic map(
LOC => "SLICE_X18Y12",
PATHPULSE => 638 ps
)
port map (
I => Mxor_ba_xor_Result_5_1_SW1_O_pack_1,
O => Mxor_ba_xor_Result_5_1_SW1_O
);
Mxor_ba_xor_Result_5_1_SW1 : X_LUT4
generic map(
INIT => X"88DD",
LOC => "SLICE_X18Y12"
)
port map (
ADR0 => a(0),
ADR1 => b_reg(5),
ADR2 => VCC,
ADR3 => b_reg(6),
O => Mxor_ba_xor_Result_5_1_SW1_O_pack_1
);
Sh1102 : X_LUT4
generic map(
INIT => X"8BD1",
LOC => "SLICE_X22Y19"
)
port map (
ADR0 => N231_0,
ADR1 => a(14),
ADR2 => Mxor_ba_xor_Result_13_1_SW1_O,
ADR3 => a(13),
O => Sh1102_10108
);
Sh1102_XUSED : X_BUF
generic map(
LOC => "SLICE_X22Y19",
PATHPULSE => 638 ps
)
port map (
I => Sh1102_10108,
O => Sh1102_0
);
Sh1102_YUSED : X_BUF
generic map(
LOC => "SLICE_X22Y19",
PATHPULSE => 638 ps
)
port map (
I => Mxor_ba_xor_Result_13_1_SW1_O_pack_1,
O => Mxor_ba_xor_Result_13_1_SW1_O
);
Mxor_ba_xor_Result_13_1_SW1 : X_LUT4
generic map(
INIT => X"F505",
LOC => "SLICE_X22Y19"
)
port map (
ADR0 => b_reg(14),
ADR1 => VCC,
ADR2 => a(0),
ADR3 => b_reg(13),
O => Mxor_ba_xor_Result_13_1_SW1_O_pack_1
);
Sh1032 : X_LUT4
generic map(
INIT => X"D18B",
LOC => "SLICE_X25Y13"
)
port map (
ADR0 => Mxor_ba_xor_Result_7_1_SW1_O,
ADR1 => a(7),
ADR2 => N254_0,
ADR3 => a(6),
O => Sh1032_10132
);
Sh1032_XUSED : X_BUF
generic map(
LOC => "SLICE_X25Y13",
PATHPULSE => 638 ps
)
port map (
I => Sh1032_10132,
O => Sh1032_0
);
Sh1032_YUSED : X_BUF
generic map(
LOC => "SLICE_X25Y13",
PATHPULSE => 638 ps
)
port map (
I => Mxor_ba_xor_Result_7_1_SW1_O_pack_1,
O => Mxor_ba_xor_Result_7_1_SW1_O
);
Mxor_ba_xor_Result_7_1_SW1 : X_LUT4
generic map(
INIT => X"AA0F",
LOC => "SLICE_X25Y13"
)
port map (
ADR0 => b_reg(6),
ADR1 => VCC,
ADR2 => b_reg(7),
ADR3 => a(0),
O => Mxor_ba_xor_Result_7_1_SW1_O_pack_1
);
Sh1112 : X_LUT4
generic map(
INIT => X"D81B",
LOC => "SLICE_X19Y20"
)
port map (
ADR0 => a(14),
ADR1 => N228_0,
ADR2 => Mxor_ba_xor_Result_15_1_SW1_O,
ADR3 => a(15),
O => Sh1112_10156
);
Sh1112_XUSED : X_BUF
generic map(
LOC => "SLICE_X19Y20",
PATHPULSE => 638 ps
)
port map (
I => Sh1112_10156,
O => Sh1112_0
);
Sh1112_YUSED : X_BUF
generic map(
LOC => "SLICE_X19Y20",
PATHPULSE => 638 ps
)
port map (
I => Mxor_ba_xor_Result_15_1_SW1_O_pack_1,
O => Mxor_ba_xor_Result_15_1_SW1_O
);
Mxor_ba_xor_Result_15_1_SW1 : X_LUT4
generic map(
INIT => X"C0CF",
LOC => "SLICE_X19Y20"
)
port map (
ADR0 => VCC,
ADR1 => b_reg(14),
ADR2 => a(0),
ADR3 => b_reg(15),
O => Mxor_ba_xor_Result_15_1_SW1_O_pack_1
);
Sh1062 : X_LUT4
generic map(
INIT => X"C5A3",
LOC => "SLICE_X20Y10"
)
port map (
ADR0 => Mxor_ba_xor_Result_9_1_SW1_O,
ADR1 => N237_0,
ADR2 => a(10),
ADR3 => a(9),
O => Sh1062_10180
);
Sh1062_XUSED : X_BUF
generic map(
LOC => "SLICE_X20Y10",
PATHPULSE => 638 ps
)
port map (
I => Sh1062_10180,
O => Sh1062_0
);
Sh1062_YUSED : X_BUF
generic map(
LOC => "SLICE_X20Y10",
PATHPULSE => 638 ps
)
port map (
I => Mxor_ba_xor_Result_9_1_SW1_O_pack_1,
O => Mxor_ba_xor_Result_9_1_SW1_O
);
Mxor_ba_xor_Result_9_1_SW1 : X_LUT4
generic map(
INIT => X"F055",
LOC => "SLICE_X20Y10"
)
port map (
ADR0 => b_reg(10),
ADR1 => VCC,
ADR2 => b_reg(9),
ADR3 => a(0),
O => Mxor_ba_xor_Result_9_1_SW1_O_pack_1
);
Sh1142 : X_LUT4
generic map(
INIT => X"A3C5",
LOC => "SLICE_X23Y25"
)
port map (
ADR0 => a(18),
ADR1 => a(17),
ADR2 => N217_0,
ADR3 => Mxor_ba_xor_Result_17_1_SW1_O,
O => Sh1142_10204
);
Sh1142_XUSED : X_BUF
generic map(
LOC => "SLICE_X23Y25",
PATHPULSE => 638 ps
)
port map (
I => Sh1142_10204,
O => Sh1142_0
);
Sh1142_YUSED : X_BUF
generic map(
LOC => "SLICE_X23Y25",
PATHPULSE => 638 ps
)
port map (
I => Mxor_ba_xor_Result_17_1_SW1_O_pack_1,
O => Mxor_ba_xor_Result_17_1_SW1_O
);
Mxor_ba_xor_Result_17_1_SW1 : X_LUT4
generic map(
INIT => X"F055",
LOC => "SLICE_X23Y25"
)
port map (
ADR0 => b_reg(18),
ADR1 => VCC,
ADR2 => b_reg(17),
ADR3 => a(0),
O => Mxor_ba_xor_Result_17_1_SW1_O_pack_1
);
Sh1222_XUSED : X_BUF
generic map(
LOC => "SLICE_X22Y28",
PATHPULSE => 638 ps
)
port map (
I => Sh1222_10228,
O => Sh1222_0
);
Sh1222_YUSED : X_BUF
generic map(
LOC => "SLICE_X22Y28",
PATHPULSE => 638 ps
)
port map (
I => Mxor_ba_xor_Result_25_1_SW1_O_pack_1,
O => Mxor_ba_xor_Result_25_1_SW1_O
);
Mxor_ba_xor_Result_25_1_SW1 : X_LUT4
generic map(
INIT => X"AF05",
LOC => "SLICE_X22Y28"
)
port map (
ADR0 => a(0),
ADR1 => VCC,
ADR2 => b_reg(26),
ADR3 => b_reg(25),
O => Mxor_ba_xor_Result_25_1_SW1_O_pack_1
);
Sh1072_XUSED : X_BUF
generic map(
LOC => "SLICE_X18Y13",
PATHPULSE => 638 ps
)
port map (
I => Sh1072_10252,
O => Sh1072_0
);
Sh1072_YUSED : X_BUF
generic map(
LOC => "SLICE_X18Y13",
PATHPULSE => 638 ps
)
port map (
I => Mxor_ba_xor_Result_11_1_SW1_O_pack_1,
O => Mxor_ba_xor_Result_11_1_SW1_O
);
Sh1152_XUSED : X_BUF
generic map(
LOC => "SLICE_X22Y24",
PATHPULSE => 638 ps
)
port map (
I => Sh1152_10276,
O => Sh1152_0
);
Sh1152_YUSED : X_BUF
generic map(
LOC => "SLICE_X22Y24",
PATHPULSE => 638 ps
)
port map (
I => Mxor_ba_xor_Result_19_1_SW1_O_pack_1,
O => Mxor_ba_xor_Result_19_1_SW1_O
);
Sh1232_XUSED : X_BUF
generic map(
LOC => "SLICE_X22Y31",
PATHPULSE => 638 ps
)
port map (
I => Sh1232_10300,
O => Sh1232_0
);
Sh1232_YUSED : X_BUF
generic map(
LOC => "SLICE_X22Y31",
PATHPULSE => 638 ps
)
port map (
I => N200_pack_1,
O => N200
);
Sh1182_XUSED : X_BUF
generic map(
LOC => "SLICE_X18Y33",
PATHPULSE => 638 ps
)
port map (
I => Sh1182_10324,
O => Sh1182_0
);
Sh1182_YUSED : X_BUF
generic map(
LOC => "SLICE_X18Y33",
PATHPULSE => 638 ps
)
port map (
I => Mxor_ba_xor_Result_21_1_SW1_O_pack_1,
O => Mxor_ba_xor_Result_21_1_SW1_O
);
Sh1262_XUSED : X_BUF
generic map(
LOC => "SLICE_X20Y31",
PATHPULSE => 638 ps
)
port map (
I => Sh1262_10348,
O => Sh1262_0
);
Sh1262_YUSED : X_BUF
generic map(
LOC => "SLICE_X20Y31",
PATHPULSE => 638 ps
)
port map (
I => Mxor_ba_xor_Result_29_1_SW1_O_pack_1,
O => Mxor_ba_xor_Result_29_1_SW1_O
);
Sh13016_XUSED : X_BUF
generic map(
LOC => "SLICE_X26Y17",
PATHPULSE => 638 ps
)
port map (
I => Sh13016,
O => Sh13016_0
);
Sh13016_YUSED : X_BUF
generic map(
LOC => "SLICE_X26Y17",
PATHPULSE => 638 ps
)
port map (
I => Sh982_pack_1,
O => Sh982_4493
);
Sh1192_XUSED : X_BUF
generic map(
LOC => "SLICE_X18Y28",
PATHPULSE => 638 ps
)
port map (
I => Sh1192_10396,
O => Sh1192_0
);
Sh1192_YUSED : X_BUF
generic map(
LOC => "SLICE_X18Y28",
PATHPULSE => 638 ps
)
port map (
I => Mxor_ba_xor_Result_23_1_SW1_O_pack_1,
O => Mxor_ba_xor_Result_23_1_SW1_O
);
Sh1272_XUSED : X_BUF
generic map(
LOC => "SLICE_X21Y31",
PATHPULSE => 638 ps
)
port map (
I => Sh1272_10420,
O => Sh1272_0
);
Sh1272_YUSED : X_BUF
generic map(
LOC => "SLICE_X21Y31",
PATHPULSE => 638 ps
)
port map (
I => N197_pack_1,
O => N197
);
Sh161_YUSED : X_BUF
generic map(
LOC => "SLICE_X20Y14",
PATHPULSE => 638 ps
)
port map (
I => Sh129_pack_1,
O => Sh129
);
Sh170_YUSED : X_BUF
generic map(
LOC => "SLICE_X27Y18",
PATHPULSE => 638 ps
)
port map (
I => Sh138_pack_1,
O => Sh138
);
Sh1437_XUSED : X_BUF
generic map(
LOC => "SLICE_X24Y22",
PATHPULSE => 638 ps
)
port map (
I => Sh1437_10492,
O => Sh1437_0
);
Sh1437_YUSED : X_BUF
generic map(
LOC => "SLICE_X24Y22",
PATHPULSE => 638 ps
)
port map (
I => Sh107_pack_1,
O => Sh107
);
Sh171_YUSED : X_BUF
generic map(
LOC => "SLICE_X27Y24",
PATHPULSE => 638 ps
)
port map (
I => Sh155_pack_1,
O => Sh155
);
Sh172_YUSED : X_BUF
generic map(
LOC => "SLICE_X23Y19",
PATHPULSE => 638 ps
)
port map (
I => Sh156_pack_1,
O => Sh156
);
Sh180_YUSED : X_BUF
generic map(
LOC => "SLICE_X23Y21",
PATHPULSE => 638 ps
)
port map (
I => Sh132_pack_1,
O => Sh132
);
Sh165_YUSED : X_BUF
generic map(
LOC => "SLICE_X23Y15",
PATHPULSE => 638 ps
)
port map (
I => Sh149_pack_1,
O => Sh149
);
Sh173_YUSED : X_BUF
generic map(
LOC => "SLICE_X20Y16",
PATHPULSE => 638 ps
)
port map (
I => Sh157_pack_1,
O => Sh157
);
Sh166_YUSED : X_BUF
generic map(
LOC => "SLICE_X26Y15",
PATHPULSE => 638 ps
)
port map (
I => Sh134_pack_1,
O => Sh134
);
Sh174_YUSED : X_BUF
generic map(
LOC => "SLICE_X26Y22",
PATHPULSE => 638 ps
)
port map (
I => Sh158_pack_1,
O => Sh158
);
Sh167_YUSED : X_BUF
generic map(
LOC => "SLICE_X22Y21",
PATHPULSE => 638 ps
)
port map (
I => Sh151_pack_1,
O => Sh151
);
Sh168_YUSED : X_BUF
generic map(
LOC => "SLICE_X22Y17",
PATHPULSE => 638 ps
)
port map (
I => Sh152_pack_1,
O => Sh152
);
Sh176_YUSED : X_BUF
generic map(
LOC => "SLICE_X22Y20",
PATHPULSE => 638 ps
)
port map (
I => Sh128_pack_1,
O => Sh128
);
Sh169_YUSED : X_BUF
generic map(
LOC => "SLICE_X23Y16",
PATHPULSE => 638 ps
)
port map (
I => Sh153_pack_1,
O => Sh153
);
Sh179_YUSED : X_BUF
generic map(
LOC => "SLICE_X25Y19",
PATHPULSE => 638 ps
)
port map (
I => Sh131_pack_1,
O => Sh131
);
b_reg_2_1_DYMUX : X_BUF
generic map(
LOC => "SLICE_X12Y10",
PATHPULSE => 638 ps
)
port map (
I => b_reg_2_1_GYMUX_10799,
O => b_reg_2_1_DYMUX_10800
);
b_reg_2_1_GYMUX : X_BUF
generic map(
LOC => "SLICE_X12Y10",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_2_Q,
O => b_reg_2_1_GYMUX_10799
);
b_reg_2_1_CLKINV : X_BUF
generic map(
LOC => "SLICE_X12Y10",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => b_reg_2_1_CLKINV_10790
);
b_reg_3_1_DYMUX : X_BUF
generic map(
LOC => "SLICE_X3Y21",
PATHPULSE => 638 ps
)
port map (
I => b_reg_3_1_GYMUX_10823,
O => b_reg_3_1_DYMUX_10824
);
b_reg_3_1_GYMUX : X_BUF
generic map(
LOC => "SLICE_X3Y21",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_3_Q,
O => b_reg_3_1_GYMUX_10823
);
b_reg_3_1_CLKINV : X_BUF
generic map(
LOC => "SLICE_X3Y21",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => b_reg_3_1_CLKINV_10814
);
b_reg_4_1_DYMUX : X_BUF
generic map(
LOC => "SLICE_X3Y19",
PATHPULSE => 638 ps
)
port map (
I => b_reg_4_1_GYMUX_10847,
O => b_reg_4_1_DYMUX_10848
);
b_reg_4_1_GYMUX : X_BUF
generic map(
LOC => "SLICE_X3Y19",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_4_Q,
O => b_reg_4_1_GYMUX_10847
);
b_reg_4_1_CLKINV : X_BUF
generic map(
LOC => "SLICE_X3Y19",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => b_reg_4_1_CLKINV_10838
);
AN_1_DXMUX : X_BUF
generic map(
LOC => "SLICE_X30Y14",
PATHPULSE => 638 ps
)
port map (
I => Mrom_AN_mux00011,
O => AN_1_DXMUX_10889
);
AN_1_DYMUX : X_BUF
generic map(
LOC => "SLICE_X30Y14",
PATHPULSE => 638 ps
)
port map (
I => Mrom_AN_mux0001,
O => AN_1_DYMUX_10874
);
AN_1_SRINV : X_BUF
generic map(
LOC => "SLICE_X30Y14",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => AN_1_SRINV_10864
);
AN_1_CLKINV : X_BUF
generic map(
LOC => "SLICE_X30Y14",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => AN_1_CLKINV_10863
);
AN_3_DXMUX : X_BUF
generic map(
LOC => "SLICE_X30Y12",
PATHPULSE => 638 ps
)
port map (
I => Mrom_AN_mux00013,
O => AN_3_DXMUX_10929
);
AN_3_DYMUX : X_BUF
generic map(
LOC => "SLICE_X30Y12",
PATHPULSE => 638 ps
)
port map (
I => Mrom_AN_mux00012,
O => AN_3_DYMUX_10914
);
AN_3_SRINV : X_BUF
generic map(
LOC => "SLICE_X30Y12",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => AN_3_SRINV_10904
);
AN_3_CLKINV : X_BUF
generic map(
LOC => "SLICE_X30Y12",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => AN_3_CLKINV_10903
);
a_reg_1_DXMUX : X_BUF
generic map(
LOC => "SLICE_X13Y33",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(1),
O => a_reg_1_DXMUX_10970
);
a_reg_1_DYMUX : X_BUF
generic map(
LOC => "SLICE_X13Y33",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(0),
O => a_reg_1_DYMUX_10956
);
a_reg_1_SRINV : X_BUF
generic map(
LOC => "SLICE_X13Y33",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => a_reg_1_SRINV_10948
);
a_reg_1_CLKINV : X_BUF
generic map(
LOC => "SLICE_X13Y33",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => a_reg_1_CLKINV_10947
);
a_reg_3_DXMUX : X_BUF
generic map(
LOC => "SLICE_X2Y21",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(3),
O => a_reg_3_DXMUX_11012
);
a_reg_3_DYMUX : X_BUF
generic map(
LOC => "SLICE_X2Y21",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(2),
O => a_reg_3_DYMUX_10998
);
a_reg_3_SRINV : X_BUF
generic map(
LOC => "SLICE_X2Y21",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => a_reg_3_SRINV_10990
);
a_reg_3_CLKINV : X_BUF
generic map(
LOC => "SLICE_X2Y21",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => a_reg_3_CLKINV_10989
);
a_reg_5_DXMUX : X_BUF
generic map(
LOC => "SLICE_X15Y18",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(5),
O => a_reg_5_DXMUX_11054
);
a_reg_5_DYMUX : X_BUF
generic map(
LOC => "SLICE_X15Y18",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(4),
O => a_reg_5_DYMUX_11040
);
a_reg_5_SRINV : X_BUF
generic map(
LOC => "SLICE_X15Y18",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => a_reg_5_SRINV_11032
);
a_reg_5_CLKINV : X_BUF
generic map(
LOC => "SLICE_X15Y18",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => a_reg_5_CLKINV_11031
);
a_reg_7_DXMUX : X_BUF
generic map(
LOC => "SLICE_X17Y15",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(7),
O => a_reg_7_DXMUX_11096
);
a_reg_7_DYMUX : X_BUF
generic map(
LOC => "SLICE_X17Y15",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(6),
O => a_reg_7_DYMUX_11082
);
a_reg_7_SRINV : X_BUF
generic map(
LOC => "SLICE_X17Y15",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => a_reg_7_SRINV_11074
);
a_reg_7_CLKINV : X_BUF
generic map(
LOC => "SLICE_X17Y15",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => a_reg_7_CLKINV_11073
);
a_reg_9_DXMUX : X_BUF
generic map(
LOC => "SLICE_X16Y12",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(9),
O => a_reg_9_DXMUX_11138
);
a_reg_9_DYMUX : X_BUF
generic map(
LOC => "SLICE_X16Y12",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(8),
O => a_reg_9_DYMUX_11124
);
a_reg_9_SRINV : X_BUF
generic map(
LOC => "SLICE_X16Y12",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => a_reg_9_SRINV_11116
);
a_reg_9_CLKINV : X_BUF
generic map(
LOC => "SLICE_X16Y12",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => a_reg_9_CLKINV_11115
);
b_reg_7_DXMUX : X_BUF
generic map(
LOC => "SLICE_X12Y12",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_7_Q,
O => b_reg_7_DXMUX_11180
);
b_reg_7_DYMUX : X_BUF
generic map(
LOC => "SLICE_X12Y12",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_6_Q,
O => b_reg_7_DYMUX_11165
);
b_reg_7_SRINV : X_BUF
generic map(
LOC => "SLICE_X12Y12",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => b_reg_7_SRINV_11156
);
b_reg_7_CLKINV : X_BUF
generic map(
LOC => "SLICE_X12Y12",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => b_reg_7_CLKINV_11155
);
i_cnt_1_DXMUX : X_BUF
generic map(
LOC => "SLICE_X12Y32",
PATHPULSE => 638 ps
)
port map (
I => i_cnt_mux0001(2),
O => i_cnt_1_DXMUX_11221
);
i_cnt_1_DYMUX : X_BUF
generic map(
LOC => "SLICE_X12Y32",
PATHPULSE => 638 ps
)
port map (
I => i_cnt_mux0001(3),
O => i_cnt_1_DYMUX_11208
);
i_cnt_1_SRINV : X_BUF
generic map(
LOC => "SLICE_X12Y32",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => i_cnt_1_SRINV_11199
);
i_cnt_1_CLKINV : X_BUF
generic map(
LOC => "SLICE_X12Y32",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => i_cnt_1_CLKINV_11198
);
a_reg_11_DXMUX : X_BUF
generic map(
LOC => "SLICE_X14Y13",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(11),
O => a_reg_11_DXMUX_11263
);
a_reg_11_DYMUX : X_BUF
generic map(
LOC => "SLICE_X14Y13",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(10),
O => a_reg_11_DYMUX_11249
);
a_reg_11_SRINV : X_BUF
generic map(
LOC => "SLICE_X14Y13",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => a_reg_11_SRINV_11241
);
a_reg_11_CLKINV : X_BUF
generic map(
LOC => "SLICE_X14Y13",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => a_reg_11_CLKINV_11240
);
a_reg_mux0000_20_1 : X_LUT4
generic map(
INIT => X"BFB0",
LOC => "SLICE_X16Y32"
)
port map (
ADR0 => a(20),
ADR1 => state_FSM_FFd1_4311,
ADR2 => state_FSM_FFd2_4312,
ADR3 => a_reg(20),
O => a_reg_mux0000(20)
);
a_reg_21_FFY_RSTOR : X_BUF
generic map(
LOC => "SLICE_X16Y32",
PATHPULSE => 638 ps
)
port map (
I => a_reg_21_SRINV_11283,
O => a_reg_21_FFY_RST
);
a_reg_20 : X_FF
generic map(
LOC => "SLICE_X16Y32",
INIT => '0'
)
port map (
I => a_reg_21_DYMUX_11291,
CE => VCC,
CLK => a_reg_21_CLKINV_11282,
SET => GND,
RST => a_reg_21_FFY_RST,
O => a_reg(20)
);
a_reg_mux0000_21_1 : X_LUT4
generic map(
INIT => X"F7C4",
LOC => "SLICE_X16Y32"
)
port map (
ADR0 => state_FSM_FFd1_4311,
ADR1 => state_FSM_FFd2_4312,
ADR2 => a(21),
ADR3 => a_reg(21),
O => a_reg_mux0000(21)
);
a_reg_21_FFX_RSTOR : X_BUF
generic map(
LOC => "SLICE_X16Y32",
PATHPULSE => 638 ps
)
port map (
I => a_reg_21_SRINV_11283,
O => a_reg_21_FFX_RST
);
a_reg_21 : X_FF
generic map(
LOC => "SLICE_X16Y32",
INIT => '0'
)
port map (
I => a_reg_21_DXMUX_11305,
CE => VCC,
CLK => a_reg_21_CLKINV_11282,
SET => GND,
RST => a_reg_21_FFX_RST,
O => a_reg(21)
);
a_reg_21_DXMUX : X_BUF
generic map(
LOC => "SLICE_X16Y32",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(21),
O => a_reg_21_DXMUX_11305
);
a_reg_21_DYMUX : X_BUF
generic map(
LOC => "SLICE_X16Y32",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(20),
O => a_reg_21_DYMUX_11291
);
a_reg_21_SRINV : X_BUF
generic map(
LOC => "SLICE_X16Y32",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => a_reg_21_SRINV_11283
);
a_reg_21_CLKINV : X_BUF
generic map(
LOC => "SLICE_X16Y32",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => a_reg_21_CLKINV_11282
);
a_reg_13_FFY_RSTOR : X_BUF
generic map(
LOC => "SLICE_X16Y16",
PATHPULSE => 638 ps
)
port map (
I => a_reg_13_SRINV_11325,
O => a_reg_13_FFY_RST
);
a_reg_12 : X_FF
generic map(
LOC => "SLICE_X16Y16",
INIT => '0'
)
port map (
I => a_reg_13_DYMUX_11333,
CE => VCC,
CLK => a_reg_13_CLKINV_11324,
SET => GND,
RST => a_reg_13_FFY_RST,
O => a_reg(12)
);
a_reg_mux0000_12_1 : X_LUT4
generic map(
INIT => X"E2EE",
LOC => "SLICE_X16Y16"
)
port map (
ADR0 => a_reg(12),
ADR1 => state_FSM_FFd2_4312,
ADR2 => a(12),
ADR3 => state_FSM_FFd1_4311,
O => a_reg_mux0000(12)
);
a_reg_mux0000_13_1 : X_LUT4
generic map(
INIT => X"8F80",
LOC => "SLICE_X16Y16"
)
port map (
ADR0 => a(13),
ADR1 => state_FSM_FFd1_4311,
ADR2 => state_FSM_FFd2_4312,
ADR3 => a_reg(13),
O => a_reg_mux0000(13)
);
a_reg_13_FFX_RSTOR : X_BUF
generic map(
LOC => "SLICE_X16Y16",
PATHPULSE => 638 ps
)
port map (
I => a_reg_13_SRINV_11325,
O => a_reg_13_FFX_RST
);
a_reg_13 : X_FF
generic map(
LOC => "SLICE_X16Y16",
INIT => '0'
)
port map (
I => a_reg_13_DXMUX_11347,
CE => VCC,
CLK => a_reg_13_CLKINV_11324,
SET => GND,
RST => a_reg_13_FFX_RST,
O => a_reg(13)
);
a_reg_13_DXMUX : X_BUF
generic map(
LOC => "SLICE_X16Y16",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(13),
O => a_reg_13_DXMUX_11347
);
a_reg_13_DYMUX : X_BUF
generic map(
LOC => "SLICE_X16Y16",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(12),
O => a_reg_13_DYMUX_11333
);
a_reg_13_SRINV : X_BUF
generic map(
LOC => "SLICE_X16Y16",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => a_reg_13_SRINV_11325
);
a_reg_13_CLKINV : X_BUF
generic map(
LOC => "SLICE_X16Y16",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => a_reg_13_CLKINV_11324
);
a_reg_31_FFY_RSTOR : X_BUF
generic map(
LOC => "SLICE_X16Y35",
PATHPULSE => 638 ps
)
port map (
I => a_reg_31_SRINV_11367,
O => a_reg_31_FFY_RST
);
a_reg_30 : X_FF
generic map(
LOC => "SLICE_X16Y35",
INIT => '0'
)
port map (
I => a_reg_31_DYMUX_11375,
CE => VCC,
CLK => a_reg_31_CLKINV_11366,
SET => GND,
RST => a_reg_31_FFY_RST,
O => a_reg(30)
);
a_reg_mux0000_30_1 : X_LUT4
generic map(
INIT => X"B830",
LOC => "SLICE_X16Y35"
)
port map (
ADR0 => state_FSM_FFd1_4311,
ADR1 => state_FSM_FFd2_4312,
ADR2 => a_reg(30),
ADR3 => a(30),
O => a_reg_mux0000(30)
);
a_reg_mux0000_31_1 : X_LUT4
generic map(
INIT => X"BF8C",
LOC => "SLICE_X16Y35"
)
port map (
ADR0 => a(31),
ADR1 => state_FSM_FFd2_4312,
ADR2 => state_FSM_FFd1_4311,
ADR3 => a_reg(31),
O => a_reg_mux0000(31)
);
a_reg_31_FFX_RSTOR : X_BUF
generic map(
LOC => "SLICE_X16Y35",
PATHPULSE => 638 ps
)
port map (
I => a_reg_31_SRINV_11367,
O => a_reg_31_FFX_RST
);
a_reg_31 : X_FF
generic map(
LOC => "SLICE_X16Y35",
INIT => '0'
)
port map (
I => a_reg_31_DXMUX_11389,
CE => VCC,
CLK => a_reg_31_CLKINV_11366,
SET => GND,
RST => a_reg_31_FFX_RST,
O => a_reg(31)
);
a_reg_31_DXMUX : X_BUF
generic map(
LOC => "SLICE_X16Y35",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(31),
O => a_reg_31_DXMUX_11389
);
a_reg_31_DYMUX : X_BUF
generic map(
LOC => "SLICE_X16Y35",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(30),
O => a_reg_31_DYMUX_11375
);
a_reg_31_SRINV : X_BUF
generic map(
LOC => "SLICE_X16Y35",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => a_reg_31_SRINV_11367
);
a_reg_31_CLKINV : X_BUF
generic map(
LOC => "SLICE_X16Y35",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => a_reg_31_CLKINV_11366
);
a_reg_23_FFY_RSTOR : X_BUF
generic map(
LOC => "SLICE_X18Y31",
PATHPULSE => 638 ps
)
port map (
I => a_reg_23_SRINV_11409,
O => a_reg_23_FFY_RST
);
a_reg_22 : X_FF
generic map(
LOC => "SLICE_X18Y31",
INIT => '0'
)
port map (
I => a_reg_23_DYMUX_11417,
CE => VCC,
CLK => a_reg_23_CLKINV_11408,
SET => GND,
RST => a_reg_23_FFY_RST,
O => a_reg(22)
);
a_reg_mux0000_22_1 : X_LUT4
generic map(
INIT => X"C0AA",
LOC => "SLICE_X18Y31"
)
port map (
ADR0 => a_reg(22),
ADR1 => a(22),
ADR2 => state_FSM_FFd1_4311,
ADR3 => state_FSM_FFd2_4312,
O => a_reg_mux0000(22)
);
a_reg_mux0000_23_1 : X_LUT4
generic map(
INIT => X"F5CC",
LOC => "SLICE_X18Y31"
)
port map (
ADR0 => state_FSM_FFd1_4311,
ADR1 => a_reg(23),
ADR2 => a(23),
ADR3 => state_FSM_FFd2_4312,
O => a_reg_mux0000(23)
);
a_reg_23_DXMUX : X_BUF
generic map(
LOC => "SLICE_X18Y31",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(23),
O => a_reg_23_DXMUX_11431
);
a_reg_23_DYMUX : X_BUF
generic map(
LOC => "SLICE_X18Y31",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(22),
O => a_reg_23_DYMUX_11417
);
a_reg_23_SRINV : X_BUF
generic map(
LOC => "SLICE_X18Y31",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => a_reg_23_SRINV_11409
);
a_reg_23_CLKINV : X_BUF
generic map(
LOC => "SLICE_X18Y31",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => a_reg_23_CLKINV_11408
);
a_reg_15_DXMUX : X_BUF
generic map(
LOC => "SLICE_X15Y22",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(15),
O => a_reg_15_DXMUX_11473
);
a_reg_15_DYMUX : X_BUF
generic map(
LOC => "SLICE_X15Y22",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(14),
O => a_reg_15_DYMUX_11459
);
a_reg_15_SRINV : X_BUF
generic map(
LOC => "SLICE_X15Y22",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => a_reg_15_SRINV_11451
);
a_reg_15_CLKINV : X_BUF
generic map(
LOC => "SLICE_X15Y22",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => a_reg_15_CLKINV_11450
);
a_reg_mux0000_24_1 : X_LUT4
generic map(
INIT => X"BF8C",
LOC => "SLICE_X17Y33"
)
port map (
ADR0 => a(24),
ADR1 => state_FSM_FFd2_4312,
ADR2 => state_FSM_FFd1_4311,
ADR3 => a_reg(24),
O => a_reg_mux0000(24)
);
a_reg_25_DXMUX : X_BUF
generic map(
LOC => "SLICE_X17Y33",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(25),
O => a_reg_25_DXMUX_11515
);
a_reg_25_DYMUX : X_BUF
generic map(
LOC => "SLICE_X17Y33",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(24),
O => a_reg_25_DYMUX_11501
);
a_reg_25_SRINV : X_BUF
generic map(
LOC => "SLICE_X17Y33",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => a_reg_25_SRINV_11493
);
a_reg_25_CLKINV : X_BUF
generic map(
LOC => "SLICE_X17Y33",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => a_reg_25_CLKINV_11492
);
a_reg_17_DXMUX : X_BUF
generic map(
LOC => "SLICE_X13Y22",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(17),
O => a_reg_17_DXMUX_11557
);
a_reg_17_DYMUX : X_BUF
generic map(
LOC => "SLICE_X13Y22",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(16),
O => a_reg_17_DYMUX_11543
);
a_reg_17_SRINV : X_BUF
generic map(
LOC => "SLICE_X13Y22",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => a_reg_17_SRINV_11535
);
a_reg_17_CLKINV : X_BUF
generic map(
LOC => "SLICE_X13Y22",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => a_reg_17_CLKINV_11534
);
a_reg_27_DXMUX : X_BUF
generic map(
LOC => "SLICE_X18Y30",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(27),
O => a_reg_27_DXMUX_11599
);
a_reg_27_DYMUX : X_BUF
generic map(
LOC => "SLICE_X18Y30",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(26),
O => a_reg_27_DYMUX_11585
);
a_reg_27_SRINV : X_BUF
generic map(
LOC => "SLICE_X18Y30",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => a_reg_27_SRINV_11577
);
a_reg_27_CLKINV : X_BUF
generic map(
LOC => "SLICE_X18Y30",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => a_reg_27_CLKINV_11576
);
a_reg_19_DXMUX : X_BUF
generic map(
LOC => "SLICE_X14Y25",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(19),
O => a_reg_19_DXMUX_11641
);
a_reg_19_DYMUX : X_BUF
generic map(
LOC => "SLICE_X14Y25",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(18),
O => a_reg_19_DYMUX_11627
);
a_reg_19_SRINV : X_BUF
generic map(
LOC => "SLICE_X14Y25",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => a_reg_19_SRINV_11619
);
a_reg_19_CLKINV : X_BUF
generic map(
LOC => "SLICE_X14Y25",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => a_reg_19_CLKINV_11618
);
a_reg_29_DXMUX : X_BUF
generic map(
LOC => "SLICE_X17Y34",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(29),
O => a_reg_29_DXMUX_11683
);
a_reg_29_DYMUX : X_BUF
generic map(
LOC => "SLICE_X17Y34",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(28),
O => a_reg_29_DYMUX_11669
);
a_reg_29_SRINV : X_BUF
generic map(
LOC => "SLICE_X17Y34",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => a_reg_29_SRINV_11661
);
a_reg_29_CLKINV : X_BUF
generic map(
LOC => "SLICE_X17Y34",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => a_reg_29_CLKINV_11660
);
b_reg_11_DYMUX : X_BUF
generic map(
LOC => "SLICE_X15Y11",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_11_Q,
O => b_reg_11_DYMUX_11706
);
b_reg_11_CLKINV : X_BUF
generic map(
LOC => "SLICE_X15Y11",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => b_reg_11_CLKINV_11696
);
b_reg_21_DXMUX : X_BUF
generic map(
LOC => "SLICE_X19Y23",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_21_Q,
O => b_reg_21_DXMUX_11748
);
b_reg_21_DYMUX : X_BUF
generic map(
LOC => "SLICE_X19Y23",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_20_Q,
O => b_reg_21_DYMUX_11734
);
b_reg_21_SRINV : X_BUF
generic map(
LOC => "SLICE_X19Y23",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => b_reg_21_SRINV_11726
);
b_reg_21_CLKINV : X_BUF
generic map(
LOC => "SLICE_X19Y23",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => b_reg_21_CLKINV_11725
);
b_reg_13_DXMUX : X_BUF
generic map(
LOC => "SLICE_X18Y19",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_13_Q,
O => b_reg_13_DXMUX_11790
);
b_reg_13_DYMUX : X_BUF
generic map(
LOC => "SLICE_X18Y19",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_12_Q,
O => b_reg_13_DYMUX_11776
);
b_reg_13_SRINV : X_BUF
generic map(
LOC => "SLICE_X18Y19",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => b_reg_13_SRINV_11768
);
b_reg_13_CLKINV : X_BUF
generic map(
LOC => "SLICE_X18Y19",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => b_reg_13_CLKINV_11767
);
b_reg_31_DXMUX : X_BUF
generic map(
LOC => "SLICE_X19Y26",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_31_Q,
O => b_reg_31_DXMUX_11832
);
b_reg_31_DYMUX : X_BUF
generic map(
LOC => "SLICE_X19Y26",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_30_Q,
O => b_reg_31_DYMUX_11818
);
b_reg_31_SRINV : X_BUF
generic map(
LOC => "SLICE_X19Y26",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => b_reg_31_SRINV_11810
);
b_reg_31_CLKINV : X_BUF
generic map(
LOC => "SLICE_X19Y26",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => b_reg_31_CLKINV_11809
);
b_reg_23_DXMUX : X_BUF
generic map(
LOC => "SLICE_X19Y22",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_23_Q,
O => b_reg_23_DXMUX_11874
);
b_reg_23_DYMUX : X_BUF
generic map(
LOC => "SLICE_X19Y22",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_22_Q,
O => b_reg_23_DYMUX_11860
);
b_reg_23_SRINV : X_BUF
generic map(
LOC => "SLICE_X19Y22",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => b_reg_23_SRINV_11852
);
b_reg_23_CLKINV : X_BUF
generic map(
LOC => "SLICE_X19Y22",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => b_reg_23_CLKINV_11851
);
b_reg_15_DXMUX : X_BUF
generic map(
LOC => "SLICE_X19Y18",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_15_Q,
O => b_reg_15_DXMUX_11916
);
b_reg_15_DYMUX : X_BUF
generic map(
LOC => "SLICE_X19Y18",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_14_Q,
O => b_reg_15_DYMUX_11902
);
b_reg_15_SRINV : X_BUF
generic map(
LOC => "SLICE_X19Y18",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => b_reg_15_SRINV_11894
);
b_reg_15_CLKINV : X_BUF
generic map(
LOC => "SLICE_X19Y18",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => b_reg_15_CLKINV_11893
);
b_reg_25_DXMUX : X_BUF
generic map(
LOC => "SLICE_X19Y24",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_25_Q,
O => b_reg_25_DXMUX_11958
);
b_reg_25_DYMUX : X_BUF
generic map(
LOC => "SLICE_X19Y24",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_24_Q,
O => b_reg_25_DYMUX_11944
);
b_reg_25_SRINV : X_BUF
generic map(
LOC => "SLICE_X19Y24",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => b_reg_25_SRINV_11936
);
b_reg_25_CLKINV : X_BUF
generic map(
LOC => "SLICE_X19Y24",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => b_reg_25_CLKINV_11935
);
b_reg_17_DXMUX : X_BUF
generic map(
LOC => "SLICE_X18Y21",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_17_Q,
O => b_reg_17_DXMUX_12000
);
b_reg_17_DYMUX : X_BUF
generic map(
LOC => "SLICE_X18Y21",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_16_Q,
O => b_reg_17_DYMUX_11986
);
b_reg_17_SRINV : X_BUF
generic map(
LOC => "SLICE_X18Y21",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => b_reg_17_SRINV_11978
);
b_reg_17_CLKINV : X_BUF
generic map(
LOC => "SLICE_X18Y21",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => b_reg_17_CLKINV_11977
);
b_reg_27_DXMUX : X_BUF
generic map(
LOC => "SLICE_X19Y25",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_27_Q,
O => b_reg_27_DXMUX_12042
);
b_reg_27_DYMUX : X_BUF
generic map(
LOC => "SLICE_X19Y25",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_26_Q,
O => b_reg_27_DYMUX_12028
);
b_reg_27_SRINV : X_BUF
generic map(
LOC => "SLICE_X19Y25",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => b_reg_27_SRINV_12020
);
b_reg_27_CLKINV : X_BUF
generic map(
LOC => "SLICE_X19Y25",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => b_reg_27_CLKINV_12019
);
b_reg_19_DXMUX : X_BUF
generic map(
LOC => "SLICE_X18Y20",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_19_Q,
O => b_reg_19_DXMUX_12084
);
b_reg_19_DYMUX : X_BUF
generic map(
LOC => "SLICE_X18Y20",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_18_Q,
O => b_reg_19_DYMUX_12070
);
b_reg_19_SRINV : X_BUF
generic map(
LOC => "SLICE_X18Y20",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => b_reg_19_SRINV_12062
);
b_reg_19_CLKINV : X_BUF
generic map(
LOC => "SLICE_X18Y20",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => b_reg_19_CLKINV_12061
);
b_reg_29_DXMUX : X_BUF
generic map(
LOC => "SLICE_X19Y27",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_29_Q,
O => b_reg_29_DXMUX_12126
);
b_reg_29_DYMUX : X_BUF
generic map(
LOC => "SLICE_X19Y27",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_28_Q,
O => b_reg_29_DYMUX_12112
);
b_reg_29_SRINV : X_BUF
generic map(
LOC => "SLICE_X19Y27",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => b_reg_29_SRINV_12104
);
b_reg_29_CLKINV : X_BUF
generic map(
LOC => "SLICE_X19Y27",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => b_reg_29_CLKINV_12103
);
Sh1287_XUSED : X_BUF
generic map(
LOC => "SLICE_X24Y19",
PATHPULSE => 638 ps
)
port map (
I => Sh1287_12154,
O => Sh1287_0
);
Sh1287_YUSED : X_BUF
generic map(
LOC => "SLICE_X24Y19",
PATHPULSE => 638 ps
)
port map (
I => Sh13220_12146,
O => Sh13220_0
);
Sh110_XUSED : X_BUF
generic map(
LOC => "SLICE_X26Y20",
PATHPULSE => 638 ps
)
port map (
I => Sh110,
O => Sh110_0
);
Sh110_YUSED : X_BUF
generic map(
LOC => "SLICE_X26Y20",
PATHPULSE => 638 ps
)
port map (
I => Sh15013_12170,
O => Sh15013_0
);
Sh103_XUSED : X_BUF
generic map(
LOC => "SLICE_X24Y21",
PATHPULSE => 638 ps
)
port map (
I => Sh103,
O => Sh103_0
);
Sh103_YUSED : X_BUF
generic map(
LOC => "SLICE_X24Y21",
PATHPULSE => 638 ps
)
port map (
I => Sh14313_12194,
O => Sh14313_0
);
Sh15816_XUSED : X_BUF
generic map(
LOC => "SLICE_X22Y22",
PATHPULSE => 638 ps
)
port map (
I => Sh15816_12226,
O => Sh15816_0
);
Sh15816_YUSED : X_BUF
generic map(
LOC => "SLICE_X22Y22",
PATHPULSE => 638 ps
)
port map (
I => Sh15113_12219,
O => Sh15113_0
);
Sh1310_XUSED : X_BUF
generic map(
LOC => "SLICE_X24Y23",
PATHPULSE => 638 ps
)
port map (
I => Sh1310,
O => Sh1310_0
);
Sh1310_YUSED : X_BUF
generic map(
LOC => "SLICE_X24Y23",
PATHPULSE => 638 ps
)
port map (
I => Sh15116_12243,
O => Sh15116_0
);
Sh14813_XUSED : X_BUF
generic map(
LOC => "SLICE_X24Y13",
PATHPULSE => 638 ps
)
port map (
I => Sh14813_12274,
O => Sh14813_0
);
Sh14813_YUSED : X_BUF
generic map(
LOC => "SLICE_X24Y13",
PATHPULSE => 638 ps
)
port map (
I => Sh14412_12265,
O => Sh14412_0
);
Sh12816_XUSED : X_BUF
generic map(
LOC => "SLICE_X22Y13",
PATHPULSE => 638 ps
)
port map (
I => Sh12816,
O => Sh12816_0
);
Sh12816_YUSED : X_BUF
generic map(
LOC => "SLICE_X22Y13",
PATHPULSE => 638 ps
)
port map (
I => Sh14413_12289,
O => Sh14413_0
);
Sh14616_XUSED : X_BUF
generic map(
LOC => "SLICE_X28Y23",
PATHPULSE => 638 ps
)
port map (
I => Sh14616_12322,
O => Sh14616_0
);
Sh14616_YUSED : X_BUF
generic map(
LOC => "SLICE_X28Y23",
PATHPULSE => 638 ps
)
port map (
I => Sh15413_12315,
O => Sh15413_0
);
Sh106_XUSED : X_BUF
generic map(
LOC => "SLICE_X27Y17",
PATHPULSE => 638 ps
)
port map (
I => Sh106,
O => Sh106_0
);
Sh106_YUSED : X_BUF
generic map(
LOC => "SLICE_X27Y17",
PATHPULSE => 638 ps
)
port map (
I => Sh14613_12338,
O => Sh14613_0
);
Sh15516_XUSED : X_BUF
generic map(
LOC => "SLICE_X26Y25",
PATHPULSE => 638 ps
)
port map (
I => Sh15516_12370,
O => Sh15516_0
);
Sh15516_YUSED : X_BUF
generic map(
LOC => "SLICE_X26Y25",
PATHPULSE => 638 ps
)
port map (
I => Sh15513_12363,
O => Sh15513_0
);
Sh1527_XUSED : X_BUF
generic map(
LOC => "SLICE_X24Y17",
PATHPULSE => 638 ps
)
port map (
I => Sh1527_12394,
O => Sh1527_0
);
Sh1527_YUSED : X_BUF
generic map(
LOC => "SLICE_X24Y17",
PATHPULSE => 638 ps
)
port map (
I => Sh14816_12386,
O => Sh14816_0
);
Sh13013_XUSED : X_BUF
generic map(
LOC => "SLICE_X29Y22",
PATHPULSE => 638 ps
)
port map (
I => Sh13013,
O => Sh13013_0
);
Sh13013_YUSED : X_BUF
generic map(
LOC => "SLICE_X29Y22",
PATHPULSE => 638 ps
)
port map (
I => Sh15813_12411,
O => Sh15813_0
);
b_reg_0_2_DYMUX : X_BUF
generic map(
LOC => "SLICE_X15Y17",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_0_Q,
O => b_reg_0_2_DYMUX_12428
);
b_reg_0_2_CLKINV : X_BUF
generic map(
LOC => "SLICE_X15Y17",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => b_reg_0_2_CLKINV_12425
);
b_reg_0_3_DYMUX : X_BUF
generic map(
LOC => "SLICE_X14Y16",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_0_Q,
O => b_reg_0_3_DYMUX_12442
);
b_reg_0_3_CLKINV : X_BUF
generic map(
LOC => "SLICE_X14Y16",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => b_reg_0_3_CLKINV_12439
);
ab_xor_3_XUSED : X_BUF
generic map(
LOC => "SLICE_X3Y20",
PATHPULSE => 638 ps
)
port map (
I => ab_xor_3_Q,
O => ab_xor_3_0
);
ab_xor_4_XUSED : X_BUF
generic map(
LOC => "SLICE_X13Y19",
PATHPULSE => 638 ps
)
port map (
I => ab_xor_4_Q,
O => ab_xor_4_0
);
N247_XUSED : X_BUF
generic map(
LOC => "SLICE_X14Y19",
PATHPULSE => 638 ps
)
port map (
I => N247,
O => N247_0
);
N247_YUSED : X_BUF
generic map(
LOC => "SLICE_X14Y19",
PATHPULSE => 638 ps
)
port map (
I => ab_xor_5_Q,
O => ab_xor_5_0
);
Mxor_ba_xor_Result_7_1_SW3 : X_LUT4
generic map(
INIT => X"C0F3",
LOC => "SLICE_X16Y13"
)
port map (
ADR0 => VCC,
ADR1 => a(0),
ADR2 => b_reg(7),
ADR3 => b_reg(8),
O => N261
);
N261_XUSED : X_BUF
generic map(
LOC => "SLICE_X16Y13",
PATHPULSE => 638 ps
)
port map (
I => N261,
O => N261_0
);
N261_YUSED : X_BUF
generic map(
LOC => "SLICE_X16Y13",
PATHPULSE => 638 ps
)
port map (
I => ab_xor_7_Q,
O => ab_xor_7_0
);
Mxor_ba_xor_Result_7_1_SW2 : X_LUT4
generic map(
INIT => X"1D1D",
LOC => "SLICE_X15Y13"
)
port map (
ADR0 => b_reg(8),
ADR1 => a(0),
ADR2 => b_reg(7),
ADR3 => VCC,
O => N260
);
N260_XUSED : X_BUF
generic map(
LOC => "SLICE_X15Y13",
PATHPULSE => 638 ps
)
port map (
I => N260,
O => N260_0
);
N260_YUSED : X_BUF
generic map(
LOC => "SLICE_X15Y13",
PATHPULSE => 638 ps
)
port map (
I => ab_xor_8_Q,
O => ab_xor_8_0
);
Mxor_ab_xor_Result_8_1 : X_LUT4
generic map(
INIT => X"5A5A",
LOC => "SLICE_X15Y13"
)
port map (
ADR0 => b_reg(8),
ADR1 => VCC,
ADR2 => a_reg(8),
ADR3 => VCC,
O => ab_xor_8_Q
);
Mxor_ba_xor_Result_8_1_SW1 : X_LUT4
generic map(
INIT => X"88BB",
LOC => "SLICE_X15Y12"
)
port map (
ADR0 => b_reg(8),
ADR1 => a(0),
ADR2 => VCC,
ADR3 => b_reg(9),
O => N241
);
N241_XUSED : X_BUF
generic map(
LOC => "SLICE_X15Y12",
PATHPULSE => 638 ps
)
port map (
I => N241,
O => N241_0
);
N241_YUSED : X_BUF
generic map(
LOC => "SLICE_X15Y12",
PATHPULSE => 638 ps
)
port map (
I => ab_xor_9_Q,
O => ab_xor_9_0
);
Mxor_ab_xor_Result_9_1 : X_LUT4
generic map(
INIT => X"33CC",
LOC => "SLICE_X15Y12"
)
port map (
ADR0 => VCC,
ADR1 => a_reg(9),
ADR2 => VCC,
ADR3 => b_reg(9),
O => ab_xor_9_Q
);
Sh102_f51 : X_LUT4
generic map(
INIT => X"F3C0",
LOC => "SLICE_X26Y19"
)
port map (
ADR0 => VCC,
ADR1 => a(1),
ADR2 => Sh1002_0,
ADR3 => Sh1022_0,
O => Sh102
);
Sh102_XUSED : X_BUF
generic map(
LOC => "SLICE_X26Y19",
PATHPULSE => 638 ps
)
port map (
I => Sh102,
O => Sh102_0
);
Sh102_YUSED : X_BUF
generic map(
LOC => "SLICE_X26Y19",
PATHPULSE => 638 ps
)
port map (
I => Sh98,
O => Sh98_0
);
Sh98_f51 : X_LUT4
generic map(
INIT => X"AACC",
LOC => "SLICE_X26Y19"
)
port map (
ADR0 => Sh962_0,
ADR1 => Sh982_4493,
ADR2 => VCC,
ADR3 => a(1),
O => Sh98
);
Madd_a_lut_22_SW0 : X_LUT4
generic map(
INIT => X"1946",
LOC => "SLICE_X18Y27"
)
port map (
ADR0 => i_cnt(0),
ADR1 => i_cnt(3),
ADR2 => i_cnt(2),
ADR3 => i_cnt(1),
O => N520
);
N520_XUSED : X_BUF
generic map(
LOC => "SLICE_X18Y27",
PATHPULSE => 638 ps
)
port map (
I => N520,
O => N520_0
);
N520_YUSED : X_BUF
generic map(
LOC => "SLICE_X18Y27",
PATHPULSE => 638 ps
)
port map (
I => N286,
O => N286_0
);
Sh711_SW0 : X_LUT4
generic map(
INIT => X"EEF0",
LOC => "SLICE_X18Y27"
)
port map (
ADR0 => i_cnt(0),
ADR1 => i_cnt(3),
ADR2 => i_cnt(2),
ADR3 => i_cnt(1),
O => N286
);
Sh671_SW0 : X_LUT4
generic map(
INIT => X"F30C",
LOC => "SLICE_X20Y18"
)
port map (
ADR0 => VCC,
ADR1 => i_cnt(0),
ADR2 => i_cnt(2),
ADR3 => i_cnt(3),
O => N224
);
Madd_b_lut_15_SW0 : X_LUT4
generic map(
INIT => X"4343",
LOC => "SLICE_X20Y18"
)
port map (
ADR0 => i_cnt(3),
ADR1 => i_cnt(0),
ADR2 => i_cnt(2),
ADR3 => VCC,
O => N522
);
N522_XUSED : X_BUF
generic map(
LOC => "SLICE_X20Y18",
PATHPULSE => 638 ps
)
port map (
I => N522,
O => N522_0
);
N522_YUSED : X_BUF
generic map(
LOC => "SLICE_X20Y18",
PATHPULSE => 638 ps
)
port map (
I => N224,
O => N224_0
);
Sh781_SW0 : X_LUT4
generic map(
INIT => X"4341",
LOC => "SLICE_X12Y30"
)
port map (
ADR0 => i_cnt(2),
ADR1 => i_cnt(1),
ADR2 => i_cnt(3),
ADR3 => i_cnt(0),
O => N226
);
Madd_a_lut_28_SW0 : X_LUT4
generic map(
INIT => X"4637",
LOC => "SLICE_X12Y30"
)
port map (
ADR0 => i_cnt(2),
ADR1 => i_cnt(1),
ADR2 => i_cnt(3),
ADR3 => i_cnt(0),
O => N518
);
N518_XUSED : X_BUF
generic map(
LOC => "SLICE_X12Y30",
PATHPULSE => 638 ps
)
port map (
I => N518,
O => N518_0
);
N518_YUSED : X_BUF
generic map(
LOC => "SLICE_X12Y30",
PATHPULSE => 638 ps
)
port map (
I => N226,
O => N226_0
);
Mxor_ab_xor_Result_11_1 : X_LUT4
generic map(
INIT => X"33CC",
LOC => "SLICE_X14Y12"
)
port map (
ADR0 => VCC,
ADR1 => b_reg(11),
ADR2 => VCC,
ADR3 => a_reg(11),
O => ab_xor_11_Q
);
N258_XUSED : X_BUF
generic map(
LOC => "SLICE_X14Y12",
PATHPULSE => 638 ps
)
port map (
I => N258,
O => N258_0
);
N258_YUSED : X_BUF
generic map(
LOC => "SLICE_X14Y12",
PATHPULSE => 638 ps
)
port map (
I => ab_xor_11_Q,
O => ab_xor_11_0
);
N257_XUSED : X_BUF
generic map(
LOC => "SLICE_X15Y14",
PATHPULSE => 638 ps
)
port map (
I => N257,
O => N257_0
);
N257_YUSED : X_BUF
generic map(
LOC => "SLICE_X15Y14",
PATHPULSE => 638 ps
)
port map (
I => ab_xor_12_Q,
O => ab_xor_12_0
);
Sh1181_SW1 : X_LUT4
generic map(
INIT => X"BB11",
LOC => "SLICE_X22Y25"
)
port map (
ADR0 => a(0),
ADR1 => b_reg(20),
ADR2 => VCC,
ADR3 => b_reg(19),
O => N188
);
N188_XUSED : X_BUF
generic map(
LOC => "SLICE_X22Y25",
PATHPULSE => 638 ps
)
port map (
I => N188,
O => N188_0
);
N188_YUSED : X_BUF
generic map(
LOC => "SLICE_X22Y25",
PATHPULSE => 638 ps
)
port map (
I => ab_xor_20_Q,
O => ab_xor_20_0
);
N235_XUSED : X_BUF
generic map(
LOC => "SLICE_X15Y16",
PATHPULSE => 638 ps
)
port map (
I => N235,
O => N235_0
);
N235_YUSED : X_BUF
generic map(
LOC => "SLICE_X15Y16",
PATHPULSE => 638 ps
)
port map (
I => ab_xor_13_Q,
O => ab_xor_13_0
);
Mxor_ab_xor_Result_13_1 : X_LUT4
generic map(
INIT => X"6666",
LOC => "SLICE_X15Y16"
)
port map (
ADR0 => a_reg(13),
ADR1 => b_reg(13),
ADR2 => VCC,
ADR3 => VCC,
O => ab_xor_13_Q
);
N214_XUSED : X_BUF
generic map(
LOC => "SLICE_X17Y32",
PATHPULSE => 638 ps
)
port map (
I => N214,
O => N214_0
);
N214_YUSED : X_BUF
generic map(
LOC => "SLICE_X17Y32",
PATHPULSE => 638 ps
)
port map (
I => ab_xor_21_Q,
O => ab_xor_21_0
);
N228_XUSED : X_BUF
generic map(
LOC => "SLICE_X15Y20",
PATHPULSE => 638 ps
)
port map (
I => N228,
O => N228_0
);
N228_YUSED : X_BUF
generic map(
LOC => "SLICE_X15Y20",
PATHPULSE => 638 ps
)
port map (
I => ab_xor_15_Q,
O => ab_xor_15_0
);
N202_XUSED : X_BUF
generic map(
LOC => "SLICE_X19Y31",
PATHPULSE => 638 ps
)
port map (
I => N202,
O => N202_0
);
N202_YUSED : X_BUF
generic map(
LOC => "SLICE_X19Y31",
PATHPULSE => 638 ps
)
port map (
I => ab_xor_23_Q,
O => ab_xor_23_0
);
N196_XUSED : X_BUF
generic map(
LOC => "SLICE_X17Y35",
PATHPULSE => 638 ps
)
port map (
I => N196,
O => N196_0
);
N196_YUSED : X_BUF
generic map(
LOC => "SLICE_X17Y35",
PATHPULSE => 638 ps
)
port map (
I => ab_xor_31_Q,
O => ab_xor_31_0
);
N194_XUSED : X_BUF
generic map(
LOC => "SLICE_X14Y20",
PATHPULSE => 638 ps
)
port map (
I => N194,
O => N194_0
);
N194_YUSED : X_BUF
generic map(
LOC => "SLICE_X14Y20",
PATHPULSE => 638 ps
)
port map (
I => ab_xor_16_Q,
O => ab_xor_16_0
);
N182_XUSED : X_BUF
generic map(
LOC => "SLICE_X18Y32",
PATHPULSE => 638 ps
)
port map (
I => N182,
O => N182_0
);
N182_YUSED : X_BUF
generic map(
LOC => "SLICE_X18Y32",
PATHPULSE => 638 ps
)
port map (
I => ab_xor_24_Q,
O => ab_xor_24_0
);
N217_XUSED : X_BUF
generic map(
LOC => "SLICE_X13Y23",
PATHPULSE => 638 ps
)
port map (
I => N217,
O => N217_0
);
N217_YUSED : X_BUF
generic map(
LOC => "SLICE_X13Y23",
PATHPULSE => 638 ps
)
port map (
I => ab_xor_17_Q,
O => ab_xor_17_0
);
N211_XUSED : X_BUF
generic map(
LOC => "SLICE_X16Y33",
PATHPULSE => 638 ps
)
port map (
I => N211,
O => N211_0
);
N211_YUSED : X_BUF
generic map(
LOC => "SLICE_X16Y33",
PATHPULSE => 638 ps
)
port map (
I => ab_xor_25_Q,
O => ab_xor_25_0
);
N205_XUSED : X_BUF
generic map(
LOC => "SLICE_X18Y25",
PATHPULSE => 638 ps
)
port map (
I => N205,
O => N205_0
);
N205_YUSED : X_BUF
generic map(
LOC => "SLICE_X18Y25",
PATHPULSE => 638 ps
)
port map (
I => ab_xor_19_Q,
O => ab_xor_19_0
);
N199_XUSED : X_BUF
generic map(
LOC => "SLICE_X19Y30",
PATHPULSE => 638 ps
)
port map (
I => N199,
O => N199_0
);
N199_YUSED : X_BUF
generic map(
LOC => "SLICE_X19Y30",
PATHPULSE => 638 ps
)
port map (
I => ab_xor_27_Q,
O => ab_xor_27_0
);
N176_XUSED : X_BUF
generic map(
LOC => "SLICE_X18Y34",
PATHPULSE => 638 ps
)
port map (
I => N176,
O => N176_0
);
N176_YUSED : X_BUF
generic map(
LOC => "SLICE_X18Y34",
PATHPULSE => 638 ps
)
port map (
I => ab_xor_28_Q,
O => ab_xor_28_0
);
N208_XUSED : X_BUF
generic map(
LOC => "SLICE_X16Y34",
PATHPULSE => 638 ps
)
port map (
I => N208,
O => N208_0
);
N208_YUSED : X_BUF
generic map(
LOC => "SLICE_X16Y34",
PATHPULSE => 638 ps
)
port map (
I => ab_xor_29_Q,
O => ab_xor_29_0
);
N191_XUSED : X_BUF
generic map(
LOC => "SLICE_X25Y21",
PATHPULSE => 638 ps
)
port map (
I => N191,
O => N191_0
);
N191_YUSED : X_BUF
generic map(
LOC => "SLICE_X25Y21",
PATHPULSE => 638 ps
)
port map (
I => N193,
O => N193_0
);
N179_XUSED : X_BUF
generic map(
LOC => "SLICE_X20Y28",
PATHPULSE => 638 ps
)
port map (
I => N179,
O => N179_0
);
N179_YUSED : X_BUF
generic map(
LOC => "SLICE_X20Y28",
PATHPULSE => 638 ps
)
port map (
I => N181,
O => N181_0
);
N289_XUSED : X_BUF
generic map(
LOC => "SLICE_X27Y21",
PATHPULSE => 638 ps
)
port map (
I => N289,
O => N289_0
);
N289_YUSED : X_BUF
generic map(
LOC => "SLICE_X27Y21",
PATHPULSE => 638 ps
)
port map (
I => N190,
O => N190_0
);
N288_XUSED : X_BUF
generic map(
LOC => "SLICE_X23Y26",
PATHPULSE => 638 ps
)
port map (
I => N288,
O => N288_0
);
N288_YUSED : X_BUF
generic map(
LOC => "SLICE_X23Y26",
PATHPULSE => 638 ps
)
port map (
I => N178,
O => N178_0
);
N185_XUSED : X_BUF
generic map(
LOC => "SLICE_X24Y25",
PATHPULSE => 638 ps
)
port map (
I => N185,
O => N185_0
);
N185_YUSED : X_BUF
generic map(
LOC => "SLICE_X24Y25",
PATHPULSE => 638 ps
)
port map (
I => N187,
O => N187_0
);
N173_XUSED : X_BUF
generic map(
LOC => "SLICE_X22Y30",
PATHPULSE => 638 ps
)
port map (
I => N173,
O => N173_0
);
N173_YUSED : X_BUF
generic map(
LOC => "SLICE_X22Y30",
PATHPULSE => 638 ps
)
port map (
I => N175,
O => N175_0
);
N264_XUSED : X_BUF
generic map(
LOC => "SLICE_X24Y26",
PATHPULSE => 638 ps
)
port map (
I => N264,
O => N264_0
);
N264_YUSED : X_BUF
generic map(
LOC => "SLICE_X24Y26",
PATHPULSE => 638 ps
)
port map (
I => N184,
O => N184_0
);
N263_XUSED : X_BUF
generic map(
LOC => "SLICE_X22Y27",
PATHPULSE => 638 ps
)
port map (
I => N263,
O => N263_0
);
N263_YUSED : X_BUF
generic map(
LOC => "SLICE_X22Y27",
PATHPULSE => 638 ps
)
port map (
I => N172,
O => N172_0
);
Sh80_YUSED : X_BUF
generic map(
LOC => "SLICE_X15Y24",
PATHPULSE => 638 ps
)
port map (
I => Sh64,
O => Sh64_0
);
Sh5320_XUSED : X_BUF
generic map(
LOC => "SLICE_X14Y21",
PATHPULSE => 638 ps
)
port map (
I => Sh5320,
O => Sh5320_0
);
Sh5320_YUSED : X_BUF
generic map(
LOC => "SLICE_X14Y21",
PATHPULSE => 638 ps
)
port map (
I => Sh5720,
O => Sh5720_0
);
Sh5420_XUSED : X_BUF
generic map(
LOC => "SLICE_X13Y29",
PATHPULSE => 638 ps
)
port map (
I => Sh5420,
O => Sh5420_0
);
Sh5420_YUSED : X_BUF
generic map(
LOC => "SLICE_X13Y29",
PATHPULSE => 638 ps
)
port map (
I => Sh5820,
O => Sh5820_0
);
N246_XUSED : X_BUF
generic map(
LOC => "SLICE_X16Y21",
PATHPULSE => 638 ps
)
port map (
I => N246,
O => N246_0
);
Sh84_XUSED : X_BUF
generic map(
LOC => "SLICE_X14Y18",
PATHPULSE => 638 ps
)
port map (
I => Sh84,
O => Sh84_0
);
N254_XUSED : X_BUF
generic map(
LOC => "SLICE_X25Y14",
PATHPULSE => 638 ps
)
port map (
I => N254,
O => N254_0
);
N254_YUSED : X_BUF
generic map(
LOC => "SLICE_X25Y14",
PATHPULSE => 638 ps
)
port map (
I => Sh991_13638,
O => Sh991_0
);
Sh99_XUSED : X_BUF
generic map(
LOC => "SLICE_X24Y18",
PATHPULSE => 638 ps
)
port map (
I => Sh99,
O => Sh99_0
);
Sh99_YUSED : X_BUF
generic map(
LOC => "SLICE_X24Y18",
PATHPULSE => 638 ps
)
port map (
I => Sh1011_pack_1,
O => Sh1011
);
b_reg_mux0000_2_13_XUSED : X_BUF
generic map(
LOC => "SLICE_X9Y2",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_2_13_13694,
O => b_reg_mux0000_2_13_0
);
b_reg_mux0000_2_13_YUSED : X_BUF
generic map(
LOC => "SLICE_X9Y2",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_2_5_13686,
O => b_reg_mux0000_2_5_0
);
b_reg_1_DXMUX : X_BUF
generic map(
LOC => "SLICE_X13Y15",
PATHPULSE => 638 ps
)
port map (
I => b_reg_1_F5MUX_13734,
O => b_reg_1_DXMUX_13736
);
b_reg_1_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X13Y15"
)
port map (
IA => N498,
IB => N499,
SEL => b_reg_1_BXINV_13726,
O => b_reg_1_F5MUX_13734
);
b_reg_1_BXINV : X_BUF
generic map(
LOC => "SLICE_X13Y15",
PATHPULSE => 638 ps
)
port map (
I => state_FSM_FFd1_4311,
O => b_reg_1_BXINV_13726
);
b_reg_1_DYMUX : X_BUF
generic map(
LOC => "SLICE_X13Y15",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_0_Q,
O => b_reg_1_DYMUX_13719
);
b_reg_1_SRINV : X_BUF
generic map(
LOC => "SLICE_X13Y15",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => b_reg_1_SRINV_13711
);
b_reg_1_CLKINV : X_BUF
generic map(
LOC => "SLICE_X13Y15",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => b_reg_1_CLKINV_13710
);
b_reg_3_DXMUX : X_BUF
generic map(
LOC => "SLICE_X3Y18",
PATHPULSE => 638 ps
)
port map (
I => b_reg_3_1_GYMUX_10823,
O => b_reg_3_DXMUX_13760
);
b_reg_3_DYMUX : X_BUF
generic map(
LOC => "SLICE_X3Y18",
PATHPULSE => 638 ps
)
port map (
I => b_reg_2_1_GYMUX_10799,
O => b_reg_3_DYMUX_13752
);
b_reg_3_SRINV : X_BUF
generic map(
LOC => "SLICE_X3Y18",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => b_reg_3_SRINV_13750
);
b_reg_3_CLKINV : X_BUF
generic map(
LOC => "SLICE_X3Y18",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => b_reg_3_CLKINV_13749
);
b_reg_4_DXMUX : X_BUF
generic map(
LOC => "SLICE_X2Y16",
PATHPULSE => 638 ps
)
port map (
I => b_reg_4_1_GYMUX_10847,
O => b_reg_4_DXMUX_13793
);
b_reg_4_DYMUX : X_BUF
generic map(
LOC => "SLICE_X2Y16",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_5_Q,
O => b_reg_4_DYMUX_13785
);
b_reg_4_SRINV : X_BUF
generic map(
LOC => "SLICE_X2Y16",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => b_reg_4_SRINV_13776
);
b_reg_4_CLKINV : X_BUF
generic map(
LOC => "SLICE_X2Y16",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => b_reg_4_CLKINV_13775
);
b_reg_mux0000_4_12_XUSED : X_BUF
generic map(
LOC => "SLICE_X0Y20",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_4_12_13821,
O => b_reg_mux0000_4_12_0
);
b_reg_mux0000_4_12_YUSED : X_BUF
generic map(
LOC => "SLICE_X0Y20",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_4_3_13813,
O => b_reg_mux0000_4_3_0
);
b_reg_mux0000_6_12_XUSED : X_BUF
generic map(
LOC => "SLICE_X2Y12",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_6_12_13845,
O => b_reg_mux0000_6_12_0
);
b_reg_mux0000_6_12_YUSED : X_BUF
generic map(
LOC => "SLICE_X2Y12",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_6_3_13837,
O => b_reg_mux0000_6_3_0
);
Mrom_b_rom000024 : X_LUT4
generic map(
INIT => X"427A",
LOC => "SLICE_X20Y22"
)
port map (
ADR0 => i_cnt(2),
ADR1 => i_cnt(0),
ADR2 => i_cnt(3),
ADR3 => i_cnt(1),
O => Mrom_b_rom000024_13869
);
Mrom_b_rom000024_XUSED : X_BUF
generic map(
LOC => "SLICE_X20Y22",
PATHPULSE => 638 ps
)
port map (
I => Mrom_b_rom000024_13869,
O => Mrom_b_rom000024_0
);
Mrom_b_rom000024_YUSED : X_BUF
generic map(
LOC => "SLICE_X20Y22",
PATHPULSE => 638 ps
)
port map (
I => N27,
O => N27_0
);
Mrom_a_rom00002321 : X_LUT4
generic map(
INIT => X"0800",
LOC => "SLICE_X20Y22"
)
port map (
ADR0 => i_cnt(2),
ADR1 => i_cnt(0),
ADR2 => i_cnt(3),
ADR3 => i_cnt(1),
O => N27
);
Mrom_b_rom00002921 : X_LUT4
generic map(
INIT => X"EEFF",
LOC => "SLICE_X20Y17"
)
port map (
ADR0 => i_cnt(3),
ADR1 => i_cnt(0),
ADR2 => VCC,
ADR3 => i_cnt(1),
O => N111
);
N111_XUSED : X_BUF
generic map(
LOC => "SLICE_X20Y17",
PATHPULSE => 638 ps
)
port map (
I => N111,
O => N111_0
);
N111_YUSED : X_BUF
generic map(
LOC => "SLICE_X20Y17",
PATHPULSE => 638 ps
)
port map (
I => N12,
O => N12_0
);
Mrom_a_rom00001611 : X_LUT4
generic map(
INIT => X"0011",
LOC => "SLICE_X20Y17"
)
port map (
ADR0 => i_cnt(3),
ADR1 => i_cnt(0),
ADR2 => VCC,
ADR3 => i_cnt(1),
O => N12
);
Mrom_b_rom00002311 : X_LUT4
generic map(
INIT => X"0A00",
LOC => "SLICE_X21Y10"
)
port map (
ADR0 => i_cnt(2),
ADR1 => VCC,
ADR2 => i_cnt(3),
ADR3 => i_cnt(1),
O => N20
);
N20_XUSED : X_BUF
generic map(
LOC => "SLICE_X21Y10",
PATHPULSE => 638 ps
)
port map (
I => N20,
O => N20_0
);
N20_YUSED : X_BUF
generic map(
LOC => "SLICE_X21Y10",
PATHPULSE => 638 ps
)
port map (
I => N17,
O => N17_0
);
Mrom_a_rom00001811 : X_LUT4
generic map(
INIT => X"5000",
LOC => "SLICE_X21Y10"
)
port map (
ADR0 => i_cnt(2),
ADR1 => VCC,
ADR2 => i_cnt(3),
ADR3 => i_cnt(1),
O => N17
);
Mrom_b_rom00005 : X_LUT4
generic map(
INIT => X"1261",
LOC => "SLICE_X18Y15"
)
port map (
ADR0 => i_cnt(1),
ADR1 => i_cnt(2),
ADR2 => i_cnt(0),
ADR3 => i_cnt(3),
O => Mrom_b_rom00005_13941
);
Mrom_b_rom00005_XUSED : X_BUF
generic map(
LOC => "SLICE_X18Y15",
PATHPULSE => 638 ps
)
port map (
I => Mrom_b_rom00005_13941,
O => Mrom_b_rom00005_0
);
Mrom_b_rom00005_YUSED : X_BUF
generic map(
LOC => "SLICE_X18Y15",
PATHPULSE => 638 ps
)
port map (
I => N222,
O => N222_0
);
Madd_a_lut_12_SW0 : X_LUT4
generic map(
INIT => X"501B",
LOC => "SLICE_X18Y15"
)
port map (
ADR0 => i_cnt(3),
ADR1 => i_cnt(2),
ADR2 => i_cnt(1),
ADR3 => i_cnt(0),
O => N222
);
i_cnt_mux0001_0_25 : X_LUT4
generic map(
INIT => X"8000",
LOC => "SLICE_X19Y13"
)
port map (
ADR0 => i_cnt(0),
ADR1 => state_FSM_FFd2_4312,
ADR2 => i_cnt(1),
ADR3 => i_cnt_mux0001_0_22_4123,
O => i_cnt_mux0001_0_25_13965
);
i_cnt_mux0001_0_25_XUSED : X_BUF
generic map(
LOC => "SLICE_X19Y13",
PATHPULSE => 638 ps
)
port map (
I => i_cnt_mux0001_0_25_13965,
O => i_cnt_mux0001_0_25_0
);
i_cnt_mux0001_0_25_YUSED : X_BUF
generic map(
LOC => "SLICE_X19Y13",
PATHPULSE => 638 ps
)
port map (
I => i_cnt_mux0001_0_22_pack_1,
O => i_cnt_mux0001_0_22_4123
);
i_cnt_mux0001_0_22 : X_LUT4
generic map(
INIT => X"3030",
LOC => "SLICE_X19Y13"
)
port map (
ADR0 => VCC,
ADR1 => i_cnt(3),
ADR2 => i_cnt(2),
ADR3 => VCC,
O => i_cnt_mux0001_0_22_pack_1
);
Sh1567 : X_LUT4
generic map(
INIT => X"CFC0",
LOC => "SLICE_X23Y20"
)
port map (
ADR0 => VCC,
ADR1 => Sh112,
ADR2 => a(3),
ADR3 => Sh120,
O => Sh1567_13989
);
Sh1567_XUSED : X_BUF
generic map(
LOC => "SLICE_X23Y20",
PATHPULSE => 638 ps
)
port map (
I => Sh1567_13989,
O => Sh1567_0
);
Sh1567_YUSED : X_BUF
generic map(
LOC => "SLICE_X23Y20",
PATHPULSE => 638 ps
)
port map (
I => Sh12813,
O => Sh12813_0
);
Sh1320 : X_LUT4
generic map(
INIT => X"F000",
LOC => "SLICE_X23Y20"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => a(3),
ADR3 => Sh120,
O => Sh12813
);
Sh1577 : X_LUT4
generic map(
INIT => X"CACA",
LOC => "SLICE_X22Y14"
)
port map (
ADR0 => Sh121,
ADR1 => Sh113,
ADR2 => a(3),
ADR3 => VCC,
O => Sh1577_14013
);
Sh1577_XUSED : X_BUF
generic map(
LOC => "SLICE_X22Y14",
PATHPULSE => 638 ps
)
port map (
I => Sh1577_14013,
O => Sh1577_0
);
Sh1577_YUSED : X_BUF
generic map(
LOC => "SLICE_X22Y14",
PATHPULSE => 638 ps
)
port map (
I => Sh12913,
O => Sh12913_0
);
Sh1330 : X_LUT4
generic map(
INIT => X"A0A0",
LOC => "SLICE_X22Y14"
)
port map (
ADR0 => Sh121,
ADR1 => VCC,
ADR2 => a(3),
ADR3 => VCC,
O => Sh12913
);
Sh1297_XUSED : X_BUF
generic map(
LOC => "SLICE_X22Y15",
PATHPULSE => 638 ps
)
port map (
I => Sh1297_14037,
O => Sh1297_0
);
Sh1297_YUSED : X_BUF
generic map(
LOC => "SLICE_X22Y15",
PATHPULSE => 638 ps
)
port map (
I => Sh12916,
O => Sh12916_0
);
Sh1333 : X_LUT4
generic map(
INIT => X"0F00",
LOC => "SLICE_X22Y15"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => a(3),
ADR3 => Sh97,
O => Sh12916
);
Sh1497_XUSED : X_BUF
generic map(
LOC => "SLICE_X24Y14",
PATHPULSE => 638 ps
)
port map (
I => Sh1497_14061,
O => Sh1497_0
);
Sh1497_YUSED : X_BUF
generic map(
LOC => "SLICE_X24Y14",
PATHPULSE => 638 ps
)
port map (
I => Sh1537_14053,
O => Sh1537_0
);
Sh186_YUSED : X_BUF
generic map(
LOC => "SLICE_X23Y18",
PATHPULSE => 638 ps
)
port map (
I => Sh185,
O => Sh185_0
);
Sh347_XUSED : X_BUF
generic map(
LOC => "SLICE_X15Y28",
PATHPULSE => 638 ps
)
port map (
I => Sh347,
O => Sh347_0
);
Sh347_YUSED : X_BUF
generic map(
LOC => "SLICE_X15Y28",
PATHPULSE => 638 ps
)
port map (
I => Sh337,
O => Sh337_0
);
Madd_b_pre_cy_4_XUSED : X_BUF
generic map(
LOC => "SLICE_X3Y15",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_pre_cy_4_Q,
O => Madd_b_pre_cy_4_0
);
Madd_b_pre_cy_4_YUSED : X_BUF
generic map(
LOC => "SLICE_X3Y15",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_pre_cy_2_pack_1,
O => Madd_b_pre_cy_2_Q
);
b_reg_mux0000_10_10_XUSED : X_BUF
generic map(
LOC => "SLICE_X2Y14",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_10_10,
O => b_reg_mux0000_10_10_0
);
b_reg_mux0000_10_10_YUSED : X_BUF
generic map(
LOC => "SLICE_X2Y14",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_pre_cy_6_pack_1,
O => Madd_b_pre_cy_6_Q
);
N14_XUSED : X_BUF
generic map(
LOC => "SLICE_X18Y14",
PATHPULSE => 638 ps
)
port map (
I => N14,
O => N14_0
);
N14_YUSED : X_BUF
generic map(
LOC => "SLICE_X18Y14",
PATHPULSE => 638 ps
)
port map (
I => N514,
O => N514_0
);
i_cnt_2_DXMUX : X_BUF
generic map(
LOC => "SLICE_X19Y28",
PATHPULSE => 638 ps
)
port map (
I => i_cnt_mux0001(1),
O => i_cnt_2_DXMUX_14404
);
i_cnt_2_YUSED : X_BUF
generic map(
LOC => "SLICE_X19Y28",
PATHPULSE => 638 ps
)
port map (
I => N516_pack_3,
O => N516
);
i_cnt_2_CLKINV : X_BUF
generic map(
LOC => "SLICE_X19Y28",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => i_cnt_2_CLKINV_14388
);
Mrom_b_rom000012_XUSED : X_BUF
generic map(
LOC => "SLICE_X18Y18",
PATHPULSE => 638 ps
)
port map (
I => Mrom_b_rom000012_14432,
O => Mrom_b_rom000012_0
);
Mrom_b_rom000012_YUSED : X_BUF
generic map(
LOC => "SLICE_X18Y18",
PATHPULSE => 638 ps
)
port map (
I => Mrom_a_rom000010,
O => Mrom_a_rom000010_0
);
Mrom_b_rom000020_XUSED : X_BUF
generic map(
LOC => "SLICE_X19Y21",
PATHPULSE => 638 ps
)
port map (
I => Mrom_b_rom000020_14456,
O => Mrom_b_rom000020_0
);
Mrom_b_rom000020_YUSED : X_BUF
generic map(
LOC => "SLICE_X19Y21",
PATHPULSE => 638 ps
)
port map (
I => Mrom_a_rom000011_14449,
O => Mrom_a_rom000011_0
);
Mrom_b_rom00008_XUSED : X_BUF
generic map(
LOC => "SLICE_X16Y19",
PATHPULSE => 638 ps
)
port map (
I => Mrom_b_rom00008_14480,
O => Mrom_b_rom00008_0
);
Mrom_b_rom00008_YUSED : X_BUF
generic map(
LOC => "SLICE_X16Y19",
PATHPULSE => 638 ps
)
port map (
I => Mrom_a_rom000021,
O => Mrom_a_rom000021_0
);
Mrom_b_rom000013_XUSED : X_BUF
generic map(
LOC => "SLICE_X19Y29",
PATHPULSE => 638 ps
)
port map (
I => Mrom_b_rom000013_14504,
O => Mrom_b_rom000013_0
);
Mrom_b_rom000013_YUSED : X_BUF
generic map(
LOC => "SLICE_X19Y29",
PATHPULSE => 638 ps
)
port map (
I => Mrom_a_rom000030,
O => Mrom_a_rom000030_0
);
Mrom_b_rom000031_XUSED : X_BUF
generic map(
LOC => "SLICE_X21Y29",
PATHPULSE => 638 ps
)
port map (
I => Mrom_b_rom000031,
O => Mrom_b_rom000031_0
);
Mrom_b_rom000031_YUSED : X_BUF
generic map(
LOC => "SLICE_X21Y29",
PATHPULSE => 638 ps
)
port map (
I => Mrom_a_rom000031,
O => Mrom_a_rom000031_0
);
Mrom_b_rom000023_XUSED : X_BUF
generic map(
LOC => "SLICE_X20Y25",
PATHPULSE => 638 ps
)
port map (
I => Mrom_b_rom000023,
O => Mrom_b_rom000023_0
);
Mrom_b_rom000023_YUSED : X_BUF
generic map(
LOC => "SLICE_X20Y25",
PATHPULSE => 638 ps
)
port map (
I => Mrom_a_rom000025,
O => Mrom_a_rom000025_0
);
Mrom_b_rom000017_XUSED : X_BUF
generic map(
LOC => "SLICE_X20Y29",
PATHPULSE => 638 ps
)
port map (
I => Mrom_b_rom000017_14576,
O => Mrom_b_rom000017_0
);
Mrom_b_rom000017_YUSED : X_BUF
generic map(
LOC => "SLICE_X20Y29",
PATHPULSE => 638 ps
)
port map (
I => Mrom_a_rom000026,
O => Mrom_a_rom000026_0
);
Mrom_b_rom00007_XUSED : X_BUF
generic map(
LOC => "SLICE_X17Y14",
PATHPULSE => 638 ps
)
port map (
I => Mrom_b_rom00007,
O => Mrom_b_rom00007_0
);
Mrom_b_rom00007_YUSED : X_BUF
generic map(
LOC => "SLICE_X17Y14",
PATHPULSE => 638 ps
)
port map (
I => Mrom_a_rom000019,
O => Mrom_a_rom000019_0
);
Mrom_b_rom000030_XUSED : X_BUF
generic map(
LOC => "SLICE_X20Y27",
PATHPULSE => 638 ps
)
port map (
I => Mrom_b_rom000030,
O => Mrom_b_rom000030_0
);
Mrom_b_rom000030_YUSED : X_BUF
generic map(
LOC => "SLICE_X20Y27",
PATHPULSE => 638 ps
)
port map (
I => Mrom_a_rom000027,
O => Mrom_a_rom000027_0
);
N237_XUSED : X_BUF
generic map(
LOC => "SLICE_X18Y10",
PATHPULSE => 638 ps
)
port map (
I => N237,
O => N237_0
);
N237_YUSED : X_BUF
generic map(
LOC => "SLICE_X18Y10",
PATHPULSE => 638 ps
)
port map (
I => N251,
O => N251_0
);
Mrom_b_rom000028_XUSED : X_BUF
generic map(
LOC => "SLICE_X20Y23",
PATHPULSE => 638 ps
)
port map (
I => Mrom_b_rom000028,
O => Mrom_b_rom000028_0
);
Mrom_b_rom000028_YUSED : X_BUF
generic map(
LOC => "SLICE_X20Y23",
PATHPULSE => 638 ps
)
port map (
I => Mrom_b_rom000011_14665,
O => Mrom_b_rom000011_0
);
N231_XUSED : X_BUF
generic map(
LOC => "SLICE_X23Y14",
PATHPULSE => 638 ps
)
port map (
I => N231,
O => N231_0
);
N231_YUSED : X_BUF
generic map(
LOC => "SLICE_X23Y14",
PATHPULSE => 638 ps
)
port map (
I => N234,
O => N234_0
);
Mrom_b_rom000026_XUSED : X_BUF
generic map(
LOC => "SLICE_X22Y23",
PATHPULSE => 638 ps
)
port map (
I => Mrom_b_rom000026,
O => Mrom_b_rom000026_0
);
Mrom_b_rom000026_YUSED : X_BUF
generic map(
LOC => "SLICE_X22Y23",
PATHPULSE => 638 ps
)
port map (
I => N77,
O => N77_0
);
N33_XUSED : X_BUF
generic map(
LOC => "SLICE_X20Y15",
PATHPULSE => 638 ps
)
port map (
I => N33,
O => N33_0
);
N33_YUSED : X_BUF
generic map(
LOC => "SLICE_X20Y15",
PATHPULSE => 638 ps
)
port map (
I => N34,
O => N34_0
);
Mrom_b_rom000022_XUSED : X_BUF
generic map(
LOC => "SLICE_X19Y16",
PATHPULSE => 638 ps
)
port map (
I => Mrom_b_rom000022,
O => Mrom_b_rom000022_0
);
Mrom_b_rom000022_YUSED : X_BUF
generic map(
LOC => "SLICE_X19Y16",
PATHPULSE => 638 ps
)
port map (
I => Mrom_a_rom00001,
O => Mrom_a_rom00001_0
);
Mrom_b_rom000016_XUSED : X_BUF
generic map(
LOC => "SLICE_X18Y17",
PATHPULSE => 638 ps
)
port map (
I => Mrom_b_rom000016,
O => Mrom_b_rom000016_0
);
Mrom_b_rom000016_YUSED : X_BUF
generic map(
LOC => "SLICE_X18Y17",
PATHPULSE => 638 ps
)
port map (
I => Mrom_a_rom0000,
O => Mrom_a_rom0000_0
);
Mrom_b_rom000010_XUSED : X_BUF
generic map(
LOC => "SLICE_X18Y16",
PATHPULSE => 638 ps
)
port map (
I => Mrom_b_rom000010,
O => Mrom_b_rom000010_0
);
Mrom_b_rom000010_YUSED : X_BUF
generic map(
LOC => "SLICE_X18Y16",
PATHPULSE => 638 ps
)
port map (
I => Mrom_a_rom000013_14821,
O => Mrom_a_rom000013_0
);
Mrom_b_rom00006_XUSED : X_BUF
generic map(
LOC => "SLICE_X18Y23",
PATHPULSE => 638 ps
)
port map (
I => Mrom_b_rom00006,
O => Mrom_b_rom00006_0
);
Mrom_b_rom00006_YUSED : X_BUF
generic map(
LOC => "SLICE_X18Y23",
PATHPULSE => 638 ps
)
port map (
I => Mrom_a_rom000023_14845,
O => Mrom_a_rom000023_0
);
Mrom_b_rom00009_XUSED : X_BUF
generic map(
LOC => "SLICE_X19Y17",
PATHPULSE => 638 ps
)
port map (
I => Mrom_b_rom00009_14876,
O => Mrom_b_rom00009_0
);
Mrom_b_rom00009_YUSED : X_BUF
generic map(
LOC => "SLICE_X19Y17",
PATHPULSE => 638 ps
)
port map (
I => Mrom_a_rom000015_14869,
O => Mrom_a_rom000015_0
);
Mrom_b_rom000021_XUSED : X_BUF
generic map(
LOC => "SLICE_X18Y29",
PATHPULSE => 638 ps
)
port map (
I => Mrom_b_rom000021,
O => Mrom_b_rom000021_0
);
Mrom_b_rom000021_YUSED : X_BUF
generic map(
LOC => "SLICE_X18Y29",
PATHPULSE => 638 ps
)
port map (
I => Mrom_a_rom000024_14893,
O => Mrom_a_rom000024_0
);
Mrom_b_rom000014_XUSED : X_BUF
generic map(
LOC => "SLICE_X20Y20",
PATHPULSE => 638 ps
)
port map (
I => Mrom_b_rom000014_14924,
O => Mrom_b_rom000014_0
);
Mrom_b_rom000014_YUSED : X_BUF
generic map(
LOC => "SLICE_X20Y20",
PATHPULSE => 638 ps
)
port map (
I => Mrom_a_rom000016_14917,
O => Mrom_a_rom000016_0
);
Mrom_b_rom00001_XUSED : X_BUF
generic map(
LOC => "SLICE_X20Y19",
PATHPULSE => 638 ps
)
port map (
I => Mrom_b_rom00001,
O => Mrom_b_rom00001_0
);
Mrom_b_rom00001_YUSED : X_BUF
generic map(
LOC => "SLICE_X20Y19",
PATHPULSE => 638 ps
)
port map (
I => Mrom_a_rom000017_14941,
O => Mrom_a_rom000017_0
);
Mrom_a_rom000029_XUSED : X_BUF
generic map(
LOC => "SLICE_X16Y30",
PATHPULSE => 638 ps
)
port map (
I => Mrom_a_rom000029_14972,
O => Mrom_a_rom000029_0
);
Mrom_a_rom000029_YUSED : X_BUF
generic map(
LOC => "SLICE_X16Y30",
PATHPULSE => 638 ps
)
port map (
I => Mrom_a_rom000018_14965,
O => Mrom_a_rom000018_0
);
Mrom_b_rom000029_XUSED : X_BUF
generic map(
LOC => "SLICE_X18Y24",
PATHPULSE => 638 ps
)
port map (
I => Mrom_b_rom000029_14996,
O => Mrom_b_rom000029_0
);
Mrom_b_rom000029_YUSED : X_BUF
generic map(
LOC => "SLICE_X18Y24",
PATHPULSE => 638 ps
)
port map (
I => Mrom_a_rom00006,
O => Mrom_a_rom00006_0
);
Mrom_a_rom00009_XUSED : X_BUF
generic map(
LOC => "SLICE_X16Y20",
PATHPULSE => 638 ps
)
port map (
I => Mrom_a_rom00009_15020,
O => Mrom_a_rom00009_0
);
Mrom_a_rom00009_YUSED : X_BUF
generic map(
LOC => "SLICE_X16Y20",
PATHPULSE => 638 ps
)
port map (
I => Mrom_a_rom00008,
O => Mrom_a_rom00008_0
);
Mrom_a_rom00005_XUSED : X_BUF
generic map(
LOC => "SLICE_X19Y19",
PATHPULSE => 638 ps
)
port map (
I => Mrom_a_rom00005_15044,
O => Mrom_a_rom00005_0
);
Mrom_a_rom00005_YUSED : X_BUF
generic map(
LOC => "SLICE_X19Y19",
PATHPULSE => 638 ps
)
port map (
I => Mrom_b_rom000019,
O => Mrom_b_rom000019_0
);
Mrom_a_rom00002_XUSED : X_BUF
generic map(
LOC => "SLICE_X18Y22",
PATHPULSE => 638 ps
)
port map (
I => Mrom_a_rom00002_15068,
O => Mrom_a_rom00002_0
);
Mrom_a_rom00002_YUSED : X_BUF
generic map(
LOC => "SLICE_X18Y22",
PATHPULSE => 638 ps
)
port map (
I => Mrom_b_rom000027,
O => Mrom_b_rom000027_0
);
state_FSM_FFd2_DXMUX : X_BUF
generic map(
LOC => "SLICE_X15Y10",
PATHPULSE => 638 ps
)
port map (
I => state_FSM_FFd2_In,
O => state_FSM_FFd2_DXMUX_15109
);
state_FSM_FFd2_DYMUX : X_BUF
generic map(
LOC => "SLICE_X15Y10",
PATHPULSE => 638 ps
)
port map (
I => state_FSM_FFd2_4312,
O => state_FSM_FFd2_DYMUX_15095
);
state_FSM_FFd2_YUSED : X_BUF
generic map(
LOC => "SLICE_X15Y10",
PATHPULSE => 638 ps
)
port map (
I => state_cmp_eq0000_pack_4,
O => state_cmp_eq0000
);
state_FSM_FFd2_SRINV : X_BUF
generic map(
LOC => "SLICE_X15Y10",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => state_FSM_FFd2_SRINV_15086
);
state_FSM_FFd2_CLKINV : X_BUF
generic map(
LOC => "SLICE_X15Y10",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => state_FSM_FFd2_CLKINV_15085
);
Mrom_b_rom0000_XUSED : X_BUF
generic map(
LOC => "SLICE_X19Y15",
PATHPULSE => 638 ps
)
port map (
I => Mrom_b_rom0000,
O => Mrom_b_rom0000_0
);
Mrom_b_rom0000_YUSED : X_BUF
generic map(
LOC => "SLICE_X19Y15",
PATHPULSE => 638 ps
)
port map (
I => Mrom_a_rom00004_15130,
O => Mrom_a_rom00004_0
);
N240_XUSED : X_BUF
generic map(
LOC => "SLICE_X19Y12",
PATHPULSE => 638 ps
)
port map (
I => N240,
O => N240_0
);
N240_YUSED : X_BUF
generic map(
LOC => "SLICE_X19Y12",
PATHPULSE => 638 ps
)
port map (
I => N243,
O => N243_0
);
Madd_a_lut_6_Q : X_LUT4
generic map(
INIT => X"665A",
LOC => "SLICE_X17Y19"
)
port map (
ADR0 => Mrom_a_rom00006_0,
ADR1 => Sh54,
ADR2 => Sh38,
ADR3 => b_reg(4),
O => Madd_a_lut(6)
);
Madd_b_lut_8_Q : X_LUT4
generic map(
INIT => X"1DE2",
LOC => "SLICE_X21Y16"
)
port map (
ADR0 => Sh136,
ADR1 => a(4),
ADR2 => Sh152,
ADR3 => Mrom_b_rom00008_0,
O => Madd_b_lut(8)
);
Sh13120_G : X_LUT4
generic map(
INIT => X"F3C0",
LOC => "SLICE_X26Y18"
)
port map (
ADR0 => VCC,
ADR1 => a(1),
ADR2 => Sh1212_0,
ADR3 => Sh1232_0,
O => N403
);
Sh13120_F : X_LUT4
generic map(
INIT => X"F0CC",
LOC => "SLICE_X26Y18"
)
port map (
ADR0 => VCC,
ADR1 => Sh1011,
ADR2 => Sh991_0,
ADR3 => a(1),
O => N402
);
Sh13_f5_G : X_LUT4
generic map(
INIT => X"5ACC",
LOC => "SLICE_X14Y17"
)
port map (
ADR0 => b_reg(10),
ADR1 => ab_xor_11_0,
ADR2 => a_reg(10),
ADR3 => b_reg_0_2_4323,
O => N495
);
Sh10_f5_G : X_LUT4
generic map(
INIT => X"A3AC",
LOC => "SLICE_X12Y13"
)
port map (
ADR0 => ab_xor_7_0,
ADR1 => a_reg(8),
ADR2 => b_reg_0_3_4316,
ADR3 => b_reg(8),
O => N471
);
Sh10_f5_F : X_LUT4
generic map(
INIT => X"B1E4",
LOC => "SLICE_X12Y13"
)
port map (
ADR0 => b_reg_0_3_4316,
ADR1 => b_reg(10),
ADR2 => ab_xor_9_0,
ADR3 => a_reg(10),
O => N470
);
Sh13_f5_F : X_LUT4
generic map(
INIT => X"AA3C",
LOC => "SLICE_X14Y17"
)
port map (
ADR0 => ab_xor_12_0,
ADR1 => a_reg(13),
ADR2 => b_reg(13),
ADR3 => b_reg_0_2_4323,
O => N494
);
Sh14_f5_F : X_LUT4
generic map(
INIT => X"CC5A",
LOC => "SLICE_X12Y16"
)
port map (
ADR0 => a_reg(14),
ADR1 => ab_xor_13_0,
ADR2 => b_reg(14),
ADR3 => b_reg_0_3_4316,
O => N486
);
Sh1641_G : X_LUT4
generic map(
INIT => X"BBB8",
LOC => "SLICE_X25Y12"
)
port map (
ADR0 => Sh1487_4504,
ADR1 => a(2),
ADR2 => Sh14813_0,
ADR3 => Sh14816_0,
O => N313
);
Sh1641_F : X_LUT4
generic map(
INIT => X"FCAA",
LOC => "SLICE_X25Y12"
)
port map (
ADR0 => Sh13220_0,
ADR1 => Sh12816_0,
ADR2 => Sh12813_0,
ADR3 => a(2),
O => N312
);
Sh1631_G : X_LUT4
generic map(
INIT => X"F0FE",
LOC => "SLICE_X24Y16"
)
port map (
ADR0 => Sh14716_4501,
ADR1 => Sh14713_4500,
ADR2 => Sh14712,
ADR3 => a(2),
O => N311
);
Sh1631_F : X_LUT4
generic map(
INIT => X"FCB8",
LOC => "SLICE_X24Y16"
)
port map (
ADR0 => Sh1313,
ADR1 => a(2),
ADR2 => Sh13120,
ADR3 => Sh1310_0,
O => N310
);
Sh3231_G : X_LUT4
generic map(
INIT => X"F5A0",
LOC => "SLICE_X13Y26"
)
port map (
ADR0 => b_reg(3),
ADR1 => VCC,
ADR2 => Sh20,
ADR3 => Sh28,
O => N353
);
Sh3231_F : X_LUT4
generic map(
INIT => X"E4E4",
LOC => "SLICE_X13Y26"
)
port map (
ADR0 => b_reg(3),
ADR1 => Sh,
ADR2 => Sh24,
ADR3 => VCC,
O => N352
);
Sh4031_G : X_LUT4
generic map(
INIT => X"B8B8",
LOC => "SLICE_X12Y24"
)
port map (
ADR0 => Sh28,
ADR1 => b_reg(3),
ADR2 => Sh4,
ADR3 => VCC,
O => N369
);
Sh4031_F : X_LUT4
generic map(
INIT => X"EE22",
LOC => "SLICE_X12Y24"
)
port map (
ADR0 => Sh8,
ADR1 => b_reg(3),
ADR2 => VCC,
ADR3 => Sh,
O => N368
);
Sh1621_G : X_LUT4
generic map(
INIT => X"DDDC",
LOC => "SLICE_X27Y15"
)
port map (
ADR0 => a(2),
ADR1 => Sh14612,
ADR2 => Sh14613_0,
ADR3 => Sh14616_0,
O => N317
);
Sh1621_F : X_LUT4
generic map(
INIT => X"FE0E",
LOC => "SLICE_X27Y15"
)
port map (
ADR0 => Sh13016_0,
ADR1 => Sh13013_0,
ADR2 => a(2),
ADR3 => Sh1307,
O => N316
);
Sh1517_G : X_LUT4
generic map(
INIT => X"E2E2",
LOC => "SLICE_X23Y17"
)
port map (
ADR0 => Sh1072_0,
ADR1 => a(1),
ADR2 => Sh1052_0,
ADR3 => VCC,
O => N433
);
Sh1517_F : X_LUT4
generic map(
INIT => X"DD88",
LOC => "SLICE_X23Y17"
)
port map (
ADR0 => a(1),
ADR1 => Sh1132_0,
ADR2 => VCC,
ADR3 => Sh1152_0,
O => N432
);
Sh1587_G : X_LUT4
generic map(
INIT => X"FC30",
LOC => "SLICE_X28Y22"
)
port map (
ADR0 => VCC,
ADR1 => a(1),
ADR2 => Sh1142_0,
ADR3 => Sh1122_0,
O => N427
);
Sh1751_G : X_LUT4
generic map(
INIT => X"FE32",
LOC => "SLICE_X25Y23"
)
port map (
ADR0 => Sh1310_0,
ADR1 => a(2),
ADR2 => Sh1313,
ADR3 => Sh1597,
O => N321
);
Sh1751_F : X_LUT4
generic map(
INIT => X"FE54",
LOC => "SLICE_X25Y23"
)
port map (
ADR0 => a(2),
ADR1 => Sh14313_0,
ADR2 => Sh14316_4518,
ADR3 => Sh1437_0,
O => N320
);
Sh1587_F : X_LUT4
generic map(
INIT => X"E2E2",
LOC => "SLICE_X28Y22"
)
port map (
ADR0 => Sh1222_0,
ADR1 => a(1),
ADR2 => Sh1202_0,
ADR3 => VCC,
O => N426
);
Sh3531_F : X_LUT4
generic map(
INIT => X"CFC0",
LOC => "SLICE_X13Y31"
)
port map (
ADR0 => VCC,
ADR1 => Sh27,
ADR2 => b_reg(3),
ADR3 => Sh3,
O => N356
);
Sh14731 : X_LUT4
generic map(
INIT => X"DDDC",
LOC => "SLICE_X25Y16"
)
port map (
ADR0 => a(2),
ADR1 => Sh14712,
ADR2 => Sh14713_4500,
ADR3 => Sh14716_4501,
O => Sh147
);
Sh14713 : X_LUT4
generic map(
INIT => X"C480",
LOC => "SLICE_X25Y16"
)
port map (
ADR0 => a(1),
ADR1 => a(3),
ADR2 => Sh1052_0,
ADR3 => Sh1072_0,
O => Sh14713_pack_1
);
Sh15432 : X_LUT4
generic map(
INIT => X"FE32",
LOC => "SLICE_X28Y25"
)
port map (
ADR0 => Sh15413_0,
ADR1 => a(2),
ADR2 => Sh15416_O,
ADR3 => Sh1547,
O => Sh154
);
Sh15416 : X_LUT4
generic map(
INIT => X"3022",
LOC => "SLICE_X28Y25"
)
port map (
ADR0 => Sh1222_0,
ADR1 => a(3),
ADR2 => Sh1202_0,
ADR3 => a(1),
O => Sh15416_O_pack_1
);
Sh14431 : X_LUT4
generic map(
INIT => X"DDDC",
LOC => "SLICE_X23Y13"
)
port map (
ADR0 => a(2),
ADR1 => Sh14412_0,
ADR2 => Sh14413_0,
ADR3 => Sh14416_4486,
O => Sh144
);
Sh14416 : X_LUT4
generic map(
INIT => X"3300",
LOC => "SLICE_X23Y13"
)
port map (
ADR0 => VCC,
ADR1 => a(3),
ADR2 => VCC,
ADR3 => Sh112,
O => Sh14416_pack_1
);
Sh14332 : X_LUT4
generic map(
INIT => X"FE54",
LOC => "SLICE_X25Y22"
)
port map (
ADR0 => a(2),
ADR1 => Sh14313_0,
ADR2 => Sh14316_4518,
ADR3 => Sh1437_0,
O => Sh143
);
Sh14316 : X_LUT4
generic map(
INIT => X"3210",
LOC => "SLICE_X25Y22"
)
port map (
ADR0 => a(1),
ADR1 => a(3),
ADR2 => Sh1112_0,
ADR3 => Sh1092_0,
O => Sh14316_pack_1
);
Sh15032 : X_LUT4
generic map(
INIT => X"AAFC",
LOC => "SLICE_X27Y22"
)
port map (
ADR0 => Sh1507,
ADR1 => Sh15013_0,
ADR2 => Sh15016_O,
ADR3 => a(2),
O => Sh150
);
Sh15016 : X_LUT4
generic map(
INIT => X"3202",
LOC => "SLICE_X27Y22"
)
port map (
ADR0 => Sh1182_0,
ADR1 => a(3),
ADR2 => a(1),
ADR3 => Sh1162_0,
O => Sh15016_O_pack_1
);
hex_digit_i_3 : X_FF
generic map(
LOC => "SLICE_X26Y12",
INIT => '0'
)
port map (
I => hex_digit_i_3_DXMUX_9768,
CE => VCC,
CLK => hex_digit_i_3_CLKINV_9749,
SET => GND,
RST => hex_digit_i_3_FFX_RSTAND_9773,
O => hex_digit_i(3)
);
hex_digit_i_3_FFX_RSTAND : X_BUF
generic map(
LOC => "SLICE_X26Y12",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => hex_digit_i_3_FFX_RSTAND_9773
);
Mmux_hex_digit_i_mux0001_43 : X_LUT4
generic map(
INIT => X"F5A0",
LOC => "SLICE_X26Y12"
)
port map (
ADR0 => LED_flash_cnt(8),
ADR1 => VCC,
ADR2 => b_reg(11),
ADR3 => b_reg(15),
O => Mmux_hex_digit_i_mux0001_43_9756
);
Mmux_hex_digit_i_mux0001_33 : X_LUT4
generic map(
INIT => X"EE22",
LOC => "SLICE_X26Y12"
)
port map (
ADR0 => b_reg(7),
ADR1 => LED_flash_cnt(8),
ADR2 => VCC,
ADR3 => b_reg(3),
O => Mmux_hex_digit_i_mux0001_33_9764
);
a_reg_mux0000_15_1 : X_LUT4
generic map(
INIT => X"F5CC",
LOC => "SLICE_X15Y22"
)
port map (
ADR0 => state_FSM_FFd1_4311,
ADR1 => a_reg(15),
ADR2 => a(15),
ADR3 => state_FSM_FFd2_4312,
O => a_reg_mux0000(15)
);
a_reg_mux0000_14_1 : X_LUT4
generic map(
INIT => X"DDF0",
LOC => "SLICE_X15Y22"
)
port map (
ADR0 => state_FSM_FFd1_4311,
ADR1 => a(14),
ADR2 => a_reg(14),
ADR3 => state_FSM_FFd2_4312,
O => a_reg_mux0000(14)
);
a_reg_14 : X_FF
generic map(
LOC => "SLICE_X15Y22",
INIT => '0'
)
port map (
I => a_reg_15_DYMUX_11459,
CE => VCC,
CLK => a_reg_15_CLKINV_11450,
SET => GND,
RST => a_reg_15_SRINV_11451,
O => a_reg(14)
);
a_reg_23 : X_FF
generic map(
LOC => "SLICE_X18Y31",
INIT => '0'
)
port map (
I => a_reg_23_DXMUX_11431,
CE => VCC,
CLK => a_reg_23_CLKINV_11408,
SET => GND,
RST => a_reg_23_SRINV_11409,
O => a_reg(23)
);
Mxor_ab_xor_Result_20_1 : X_LUT4
generic map(
INIT => X"3C3C",
LOC => "SLICE_X22Y25"
)
port map (
ADR0 => VCC,
ADR1 => b_reg(20),
ADR2 => a_reg(20),
ADR3 => VCC,
O => ab_xor_20_Q
);
Mxor_ba_xor_Result_11_1_SW2 : X_LUT4
generic map(
INIT => X"0F55",
LOC => "SLICE_X15Y14"
)
port map (
ADR0 => b_reg(12),
ADR1 => VCC,
ADR2 => b_reg(11),
ADR3 => a(0),
O => N257
);
Mxor_ab_xor_Result_12_1 : X_LUT4
generic map(
INIT => X"33CC",
LOC => "SLICE_X15Y14"
)
port map (
ADR0 => VCC,
ADR1 => b_reg(12),
ADR2 => VCC,
ADR3 => a_reg(12),
O => ab_xor_12_Q
);
Mxor_ba_xor_Result_11_1_SW3 : X_LUT4
generic map(
INIT => X"C5C5",
LOC => "SLICE_X14Y12"
)
port map (
ADR0 => b_reg(12),
ADR1 => b_reg(11),
ADR2 => a(0),
ADR3 => VCC,
O => N258
);
Sh1297 : X_LUT4
generic map(
INIT => X"CFC0",
LOC => "SLICE_X22Y15"
)
port map (
ADR0 => VCC,
ADR1 => Sh117,
ADR2 => a(3),
ADR3 => Sh125,
O => Sh1297_14037
);
LED_flash_cnt_4 : X_FF
generic map(
LOC => "SLICE_X31Y12",
INIT => '0'
)
port map (
I => LED_flash_cnt_4_DXMUX_4770,
CE => VCC,
CLK => LED_flash_cnt_4_CLKINV_4729,
SET => GND,
RST => LED_flash_cnt_4_SRINV_4730,
O => LED_flash_cnt(4)
);
LED_flash_cnt_9 : X_FF
generic map(
LOC => "SLICE_X31Y14",
INIT => '0'
)
port map (
I => LED_flash_cnt_8_DYMUX_4854,
CE => VCC,
CLK => LED_flash_cnt_8_CLKINV_4840,
SET => GND,
RST => LED_flash_cnt_8_SRINV_4841,
O => LED_flash_cnt(9)
);
LED_flash_cnt_7 : X_FF
generic map(
LOC => "SLICE_X31Y13",
INIT => '0'
)
port map (
I => LED_flash_cnt_6_DYMUX_4807,
CE => VCC,
CLK => LED_flash_cnt_6_CLKINV_4785,
SET => GND,
RST => LED_flash_cnt_6_SRINV_4786,
O => LED_flash_cnt(7)
);
LED_flash_cnt_1 : X_FF
generic map(
LOC => "SLICE_X31Y10",
INIT => '0'
)
port map (
I => LED_flash_cnt_0_DYMUX_4636,
CE => VCC,
CLK => LED_flash_cnt_0_CLKINV_4619,
SET => GND,
RST => LED_flash_cnt_0_SRINV_4620,
O => LED_flash_cnt(1)
);
Mcount_LED_flash_cnt_lut_0_INV_0 : X_LUT4
generic map(
INIT => X"0F0F",
LOC => "SLICE_X31Y10"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => LED_flash_cnt(0),
ADR3 => VCC,
O => Mcount_LED_flash_cnt_lut(0)
);
LED_flash_cnt_0 : X_FF
generic map(
LOC => "SLICE_X31Y10",
INIT => '0'
)
port map (
I => LED_flash_cnt_0_DXMUX_4658,
CE => VCC,
CLK => LED_flash_cnt_0_CLKINV_4619,
SET => GND,
RST => LED_flash_cnt_0_SRINV_4620,
O => LED_flash_cnt(0)
);
LED_flash_cnt_3 : X_FF
generic map(
LOC => "SLICE_X31Y11",
INIT => '0'
)
port map (
I => LED_flash_cnt_2_DYMUX_4695,
CE => VCC,
CLK => LED_flash_cnt_2_CLKINV_4673,
SET => GND,
RST => LED_flash_cnt_2_SRINV_4674,
O => LED_flash_cnt(3)
);
LED_flash_cnt_2 : X_FF
generic map(
LOC => "SLICE_X31Y11",
INIT => '0'
)
port map (
I => LED_flash_cnt_2_DXMUX_4714,
CE => VCC,
CLK => LED_flash_cnt_2_CLKINV_4673,
SET => GND,
RST => LED_flash_cnt_2_SRINV_4674,
O => LED_flash_cnt(2)
);
LED_flash_cnt_6 : X_FF
generic map(
LOC => "SLICE_X31Y13",
INIT => '0'
)
port map (
I => LED_flash_cnt_6_DXMUX_4826,
CE => VCC,
CLK => LED_flash_cnt_6_CLKINV_4785,
SET => GND,
RST => LED_flash_cnt_6_SRINV_4786,
O => LED_flash_cnt(6)
);
LED_flash_cnt_8 : X_FF
generic map(
LOC => "SLICE_X31Y14",
INIT => '0'
)
port map (
I => LED_flash_cnt_8_DXMUX_4875,
CE => VCC,
CLK => LED_flash_cnt_8_CLKINV_4840,
SET => GND,
RST => LED_flash_cnt_8_SRINV_4841,
O => LED_flash_cnt(8)
);
Madd_a_lut_1_Q : X_LUT4
generic map(
INIT => X"1ED2",
LOC => "SLICE_X17Y16"
)
port map (
ADR0 => Sh33,
ADR1 => b_reg(4),
ADR2 => Mrom_a_rom00001_0,
ADR3 => Sh49,
O => Madd_a_lut(1)
);
Madd_a_lut_0_Q : X_LUT4
generic map(
INIT => X"3C3C",
LOC => "SLICE_X17Y16"
)
port map (
ADR0 => VCC,
ADR1 => Sh64_0,
ADR2 => Mrom_a_rom0000_0,
ADR3 => VCC,
O => Madd_a_lut(0)
);
Madd_a_lut_3_Q : X_LUT4
generic map(
INIT => X"A695",
LOC => "SLICE_X17Y17"
)
port map (
ADR0 => N224_0,
ADR1 => b_reg(4),
ADR2 => Sh51,
ADR3 => Sh35,
O => Madd_a_lut(3)
);
Madd_a_lut_2_Q : X_LUT4
generic map(
INIT => X"47B8",
LOC => "SLICE_X17Y17"
)
port map (
ADR0 => Sh50,
ADR1 => b_reg(4),
ADR2 => Sh34,
ADR3 => Mrom_a_rom00002_0,
O => Madd_a_lut(2)
);
Madd_a_lut_4_Q : X_LUT4
generic map(
INIT => X"5A3C",
LOC => "SLICE_X17Y18"
)
port map (
ADR0 => Sh52,
ADR1 => Sh36,
ADR2 => Mrom_a_rom00004_0,
ADR3 => b_reg(4),
O => Madd_a_lut(4)
);
Madd_a_lut_7_Q : X_LUT4
generic map(
INIT => X"99A5",
LOC => "SLICE_X17Y19"
)
port map (
ADR0 => N286_0,
ADR1 => Sh55,
ADR2 => Sh39,
ADR3 => b_reg(4),
O => Madd_a_lut(7)
);
Madd_a_lut_9_Q : X_LUT4
generic map(
INIT => X"5A66",
LOC => "SLICE_X17Y20"
)
port map (
ADR0 => Mrom_a_rom00009_0,
ADR1 => Sh41,
ADR2 => Sh57,
ADR3 => b_reg(4),
O => Madd_a_lut(9)
);
Madd_a_lut_8_Q : X_LUT4
generic map(
INIT => X"4B78",
LOC => "SLICE_X17Y20"
)
port map (
ADR0 => Sh56,
ADR1 => b_reg(4),
ADR2 => Mrom_a_rom00008_0,
ADR3 => Sh40,
O => Madd_a_lut(8)
);
Madd_a_lut_11_Q : X_LUT4
generic map(
INIT => X"1ED2",
LOC => "SLICE_X17Y21"
)
port map (
ADR0 => Sh43,
ADR1 => b_reg(4),
ADR2 => Mrom_a_rom000011_0,
ADR3 => Sh59,
O => Madd_a_lut(11)
);
Madd_a_lut_10_Q : X_LUT4
generic map(
INIT => X"596A",
LOC => "SLICE_X17Y21"
)
port map (
ADR0 => Mrom_a_rom000010_0,
ADR1 => b_reg(4),
ADR2 => Sh58,
ADR3 => Sh42,
O => Madd_a_lut(10)
);
Madd_a_lut_12_Q : X_LUT4
generic map(
INIT => X"596A",
LOC => "SLICE_X17Y22"
)
port map (
ADR0 => N222_0,
ADR1 => b_reg(4),
ADR2 => Sh60,
ADR3 => Sh44,
O => Madd_a_lut(12)
);
Madd_a_lut_15_Q : X_LUT4
generic map(
INIT => X"47B8",
LOC => "SLICE_X17Y23"
)
port map (
ADR0 => Sh63,
ADR1 => b_reg(4),
ADR2 => Sh47,
ADR3 => Mrom_a_rom000015_0,
O => Madd_a_lut(15)
);
Madd_a_lut_14_Q : X_LUT4
generic map(
INIT => X"1ED2",
LOC => "SLICE_X17Y23"
)
port map (
ADR0 => Sh46,
ADR1 => b_reg(4),
ADR2 => N226_0,
ADR3 => Sh62,
O => Madd_a_lut(14)
);
Madd_a_lut_17_Q : X_LUT4
generic map(
INIT => X"569A",
LOC => "SLICE_X17Y24"
)
port map (
ADR0 => Mrom_a_rom000017_0,
ADR1 => b_reg(4),
ADR2 => Sh49,
ADR3 => Sh33,
O => Madd_a_lut(17)
);
Madd_a_lut_19_Q : X_LUT4
generic map(
INIT => X"4B78",
LOC => "SLICE_X17Y25"
)
port map (
ADR0 => Sh35,
ADR1 => b_reg(4),
ADR2 => Mrom_a_rom000019_0,
ADR3 => Sh51,
O => Madd_a_lut(19)
);
Madd_a_lut_18_Q : X_LUT4
generic map(
INIT => X"665A",
LOC => "SLICE_X17Y25"
)
port map (
ADR0 => Mrom_a_rom000018_0,
ADR1 => Sh34,
ADR2 => Sh50,
ADR3 => b_reg(4),
O => Madd_a_lut(18)
);
Madd_a_lut_21_Q : X_LUT4
generic map(
INIT => X"596A",
LOC => "SLICE_X17Y26"
)
port map (
ADR0 => Mrom_a_rom000021_0,
ADR1 => b_reg(4),
ADR2 => Sh37,
ADR3 => Sh53,
O => Madd_a_lut(21)
);
Madd_a_lut_20_Q : X_LUT4
generic map(
INIT => X"A665",
LOC => "SLICE_X17Y26"
)
port map (
ADR0 => Sh84_0,
ADR1 => i_cnt(1),
ADR2 => i_cnt(2),
ADR3 => i_cnt(3),
O => Madd_a_lut(20)
);
Madd_a_lut_22_Q : X_LUT4
generic map(
INIT => X"569A",
LOC => "SLICE_X17Y27"
)
port map (
ADR0 => N520_0,
ADR1 => b_reg(4),
ADR2 => Sh54,
ADR3 => Sh38,
O => Madd_a_lut(22)
);
Madd_a_lut_25_Q : X_LUT4
generic map(
INIT => X"5A66",
LOC => "SLICE_X17Y28"
)
port map (
ADR0 => Mrom_a_rom000025_0,
ADR1 => Sh57,
ADR2 => Sh41,
ADR3 => b_reg(4),
O => Madd_a_lut(25)
);
Madd_a_lut_24_Q : X_LUT4
generic map(
INIT => X"3C5A",
LOC => "SLICE_X17Y28"
)
port map (
ADR0 => Sh56,
ADR1 => Sh40,
ADR2 => Mrom_a_rom000024_0,
ADR3 => b_reg(4),
O => Madd_a_lut(24)
);
Madd_a_lut_27_Q : X_LUT4
generic map(
INIT => X"663C",
LOC => "SLICE_X17Y29"
)
port map (
ADR0 => Sh43,
ADR1 => Mrom_a_rom000027_0,
ADR2 => Sh59,
ADR3 => b_reg(4),
O => Madd_a_lut(27)
);
Madd_a_lut_29_Q : X_LUT4
generic map(
INIT => X"569A",
LOC => "SLICE_X17Y30"
)
port map (
ADR0 => Mrom_a_rom000029_0,
ADR1 => b_reg(4),
ADR2 => Sh61,
ADR3 => Sh45,
O => Madd_a_lut(29)
);
Madd_a_lut_28_Q : X_LUT4
generic map(
INIT => X"665A",
LOC => "SLICE_X17Y30"
)
port map (
ADR0 => N518_0,
ADR1 => Sh44,
ADR2 => Sh60,
ADR3 => b_reg(4),
O => Madd_a_lut(28)
);
Madd_a_lut_31_Q : X_LUT4
generic map(
INIT => X"596A",
LOC => "SLICE_X17Y31"
)
port map (
ADR0 => Mrom_a_rom000031_0,
ADR1 => b_reg(4),
ADR2 => Sh47,
ADR3 => Sh63,
O => Madd_a_lut(31)
);
Madd_a_lut_30_Q : X_LUT4
generic map(
INIT => X"5A66",
LOC => "SLICE_X17Y31"
)
port map (
ADR0 => Mrom_a_rom000030_0,
ADR1 => Sh62,
ADR2 => Sh46,
ADR3 => b_reg(4),
O => Madd_a_lut(30)
);
Madd_b_lut_1_Q : X_LUT4
generic map(
INIT => X"27D8",
LOC => "SLICE_X21Y12"
)
port map (
ADR0 => a(4),
ADR1 => Sh145,
ADR2 => Sh129,
ADR3 => Mrom_b_rom00001_0,
O => Madd_b_lut(1)
);
Madd_b_lut_3_Q : X_LUT4
generic map(
INIT => X"3336",
LOC => "SLICE_X21Y13"
)
port map (
ADR0 => N33_0,
ADR1 => Sh163,
ADR2 => N12_0,
ADR3 => i_cnt_mux0001_0_22_4123,
O => Madd_b_lut(3)
);
Madd_b_lut_2_Q : X_LUT4
generic map(
INIT => X"5A59",
LOC => "SLICE_X21Y13"
)
port map (
ADR0 => Sh162,
ADR1 => i_cnt(3),
ADR2 => N17_0,
ADR3 => N14_0,
O => Madd_b_lut(2)
);
Madd_b_lut_4_Q : X_LUT4
generic map(
INIT => X"5656",
LOC => "SLICE_X21Y14"
)
port map (
ADR0 => Sh164,
ADR1 => N20_0,
ADR2 => N12_0,
ADR3 => VCC,
O => Madd_b_lut(4)
);
Madd_b_lut_7_Q : X_LUT4
generic map(
INIT => X"369C",
LOC => "SLICE_X21Y15"
)
port map (
ADR0 => a(4),
ADR1 => Mrom_b_rom00007_0,
ADR2 => Sh135,
ADR3 => Sh151,
O => Madd_b_lut(7)
);
Madd_b_lut_6_Q : X_LUT4
generic map(
INIT => X"1BE4",
LOC => "SLICE_X21Y15"
)
port map (
ADR0 => a(4),
ADR1 => Sh134,
ADR2 => Sh150_0,
ADR3 => Mrom_b_rom00006_0,
O => Madd_b_lut(6)
);
Madd_b_lut_9_Q : X_LUT4
generic map(
INIT => X"4B78",
LOC => "SLICE_X21Y16"
)
port map (
ADR0 => Sh153,
ADR1 => a(4),
ADR2 => Mrom_b_rom00009_0,
ADR3 => Sh137,
O => Madd_b_lut(9)
);
Madd_b_lut_11_Q : X_LUT4
generic map(
INIT => X"656A",
LOC => "SLICE_X21Y17"
)
port map (
ADR0 => Mrom_b_rom000011_0,
ADR1 => Sh155,
ADR2 => a(4),
ADR3 => Sh139,
O => Madd_b_lut(11)
);
Madd_b_lut_10_Q : X_LUT4
generic map(
INIT => X"53AC",
LOC => "SLICE_X21Y17"
)
port map (
ADR0 => Sh154_0,
ADR1 => Sh138,
ADR2 => a(4),
ADR3 => Mrom_b_rom000010_0,
O => Madd_b_lut(10)
);
Madd_b_lut_13_Q : X_LUT4
generic map(
INIT => X"56A6",
LOC => "SLICE_X21Y18"
)
port map (
ADR0 => Mrom_b_rom000013_0,
ADR1 => Sh141,
ADR2 => a(4),
ADR3 => Sh157,
O => Madd_b_lut(13)
);
Madd_b_lut_12_Q : X_LUT4
generic map(
INIT => X"1DE2",
LOC => "SLICE_X21Y18"
)
port map (
ADR0 => Sh140,
ADR1 => a(4),
ADR2 => Sh156,
ADR3 => Mrom_b_rom000012_0,
O => Madd_b_lut(12)
);
Madd_b_lut_15_Q : X_LUT4
generic map(
INIT => X"95A6",
LOC => "SLICE_X21Y19"
)
port map (
ADR0 => Sh175,
ADR1 => i_cnt(1),
ADR2 => i_cnt(3),
ADR3 => N522_0,
O => Madd_b_lut(15)
);
Madd_b_lut_14_Q : X_LUT4
generic map(
INIT => X"4B78",
LOC => "SLICE_X21Y19"
)
port map (
ADR0 => Sh158,
ADR1 => a(4),
ADR2 => Mrom_b_rom000014_0,
ADR3 => Sh142,
O => Madd_b_lut(14)
);
Madd_b_lut_17_Q : X_LUT4
generic map(
INIT => X"35CA",
LOC => "SLICE_X21Y20"
)
port map (
ADR0 => Sh145,
ADR1 => Sh129,
ADR2 => a(4),
ADR3 => Mrom_b_rom000017_0,
O => Madd_b_lut(17)
);
Madd_b_lut_16_Q : X_LUT4
generic map(
INIT => X"4B78",
LOC => "SLICE_X21Y20"
)
port map (
ADR0 => Sh128,
ADR1 => a(4),
ADR2 => Mrom_b_rom000016_0,
ADR3 => Sh144_0,
O => Madd_b_lut(16)
);
Madd_b_lut_19_Q : X_LUT4
generic map(
INIT => X"569A",
LOC => "SLICE_X21Y21"
)
port map (
ADR0 => Mrom_b_rom000019_0,
ADR1 => a(4),
ADR2 => Sh147_0,
ADR3 => Sh131,
O => Madd_b_lut(19)
);
Madd_b_lut_18_Q : X_LUT4
generic map(
INIT => X"3336",
LOC => "SLICE_X21Y21"
)
port map (
ADR0 => N27_0,
ADR1 => Sh178,
ADR2 => N34_0,
ADR3 => N77_0,
O => Madd_b_lut(18)
);
Madd_b_lut_21_Q : X_LUT4
generic map(
INIT => X"1DE2",
LOC => "SLICE_X21Y22"
)
port map (
ADR0 => Sh149,
ADR1 => a(4),
ADR2 => Sh133,
ADR3 => Mrom_b_rom000021_0,
O => Madd_b_lut(21)
);
Madd_b_lut_20_Q : X_LUT4
generic map(
INIT => X"4B78",
LOC => "SLICE_X21Y22"
)
port map (
ADR0 => Sh132,
ADR1 => a(4),
ADR2 => Mrom_b_rom000020_0,
ADR3 => Sh148_0,
O => Madd_b_lut(20)
);
Madd_b_lut_23_Q : X_LUT4
generic map(
INIT => X"369C",
LOC => "SLICE_X21Y23"
)
port map (
ADR0 => a(4),
ADR1 => Mrom_b_rom000023_0,
ADR2 => Sh151,
ADR3 => Sh135,
O => Madd_b_lut(23)
);
Madd_b_lut_22_Q : X_LUT4
generic map(
INIT => X"1EB4",
LOC => "SLICE_X21Y23"
)
port map (
ADR0 => a(4),
ADR1 => Sh150_0,
ADR2 => Mrom_b_rom000022_0,
ADR3 => Sh134,
O => Madd_b_lut(22)
);
Madd_b_lut_25_Q : X_LUT4
generic map(
INIT => X"595A",
LOC => "SLICE_X21Y24"
)
port map (
ADR0 => Sh185_0,
ADR1 => i_cnt(2),
ADR2 => N20_0,
ADR3 => N111_0,
O => Madd_b_lut(25)
);
Madd_b_lut_24_Q : X_LUT4
generic map(
INIT => X"27D8",
LOC => "SLICE_X21Y24"
)
port map (
ADR0 => a(4),
ADR1 => Sh136,
ADR2 => Sh152,
ADR3 => Mrom_b_rom000024_0,
O => Madd_b_lut(24)
);
Madd_b_lut_27_Q : X_LUT4
generic map(
INIT => X"1ED2",
LOC => "SLICE_X21Y25"
)
port map (
ADR0 => Sh155,
ADR1 => a(4),
ADR2 => Mrom_b_rom000027_0,
ADR3 => Sh139,
O => Madd_b_lut(27)
);
Madd_b_lut_26_Q : X_LUT4
generic map(
INIT => X"596A",
LOC => "SLICE_X21Y25"
)
port map (
ADR0 => Mrom_b_rom000026_0,
ADR1 => a(4),
ADR2 => Sh138,
ADR3 => Sh154_0,
O => Madd_b_lut(26)
);
Madd_b_lut_29_Q : X_LUT4
generic map(
INIT => X"36C6",
LOC => "SLICE_X21Y26"
)
port map (
ADR0 => Sh157,
ADR1 => Mrom_b_rom000029_0,
ADR2 => a(4),
ADR3 => Sh141,
O => Madd_b_lut(29)
);
Madd_b_lut_28_Q : X_LUT4
generic map(
INIT => X"3C66",
LOC => "SLICE_X21Y26"
)
port map (
ADR0 => Sh156,
ADR1 => Mrom_b_rom000028_0,
ADR2 => Sh140,
ADR3 => a(4),
O => Madd_b_lut(28)
);
Madd_b_lut_31_Q : X_LUT4
generic map(
INIT => X"56A6",
LOC => "SLICE_X21Y27"
)
port map (
ADR0 => Mrom_b_rom000031_0,
ADR1 => Sh159_0,
ADR2 => a(4),
ADR3 => Sh143_0,
O => Madd_b_lut(31)
);
Madd_b_lut_30_Q : X_LUT4
generic map(
INIT => X"1ED2",
LOC => "SLICE_X21Y27"
)
port map (
ADR0 => Sh158,
ADR1 => a(4),
ADR2 => Mrom_b_rom000030_0,
ADR3 => Sh142,
O => Madd_b_lut(30)
);
din_lower_0_IFF_IMUX : X_BUF
generic map(
LOC => "IPAD60",
PATHPULSE => 638 ps
)
port map (
I => din_lower_0_INBUF,
O => Madd_b_pre_cy_0_Q
);
din_lower_1_IFF_IMUX : X_BUF
generic map(
LOC => "PAD83",
PATHPULSE => 638 ps
)
port map (
I => din_lower_1_INBUF,
O => swtch_led_1_OBUF_4254
);
din_lower_2_IFF_IMUX : X_BUF
generic map(
LOC => "IPAD86",
PATHPULSE => 638 ps
)
port map (
I => din_lower_2_INBUF,
O => Madd_b_pre_lut(2)
);
din_lower_3_IFF_IMUX : X_BUF
generic map(
LOC => "IPAD3",
PATHPULSE => 638 ps
)
port map (
I => din_lower_3_INBUF,
O => swtch_led_3_OBUF_4256
);
din_lower_4_IFF_IMUX : X_BUF
generic map(
LOC => "PAD94",
PATHPULSE => 638 ps
)
port map (
I => din_lower_4_INBUF,
O => swtch_led_4_OBUF_4257
);
din_lower_5_IFF_IMUX : X_BUF
generic map(
LOC => "PAD99",
PATHPULSE => 638 ps
)
port map (
I => din_lower_5_INBUF,
O => swtch_led_5_OBUF_4258
);
din_lower_6_IFF_IMUX : X_BUF
generic map(
LOC => "IPAD100",
PATHPULSE => 638 ps
)
port map (
I => din_lower_6_INBUF,
O => swtch_led_6_OBUF_4259
);
din_lower_7_IFF_IMUX : X_BUF
generic map(
LOC => "IPAD73",
PATHPULSE => 638 ps
)
port map (
I => din_lower_7_INBUF,
O => swtch_led_7_OBUF_4260
);
clr_IFF_IMUX : X_BUF
generic map(
LOC => "PAD11",
PATHPULSE => 638 ps
)
port map (
I => clr_INBUF,
O => clr_IBUF_3948
);
di_vld_IFF_IMUX : X_BUF
generic map(
LOC => "PAD72",
PATHPULSE => 638 ps
)
port map (
I => di_vld_INBUF,
O => di_vld_IBUF_4273
);
Sh22_f5_F : X_LUT4
generic map(
INIT => X"AA3C",
LOC => "SLICE_X15Y31"
)
port map (
ADR0 => ab_xor_21_0,
ADR1 => a_reg(22),
ADR2 => b_reg(22),
ADR3 => b_reg_0_2_4323,
O => N482
);
Sh22_f5_G : X_LUT4
generic map(
INIT => X"AA3C",
LOC => "SLICE_X15Y31"
)
port map (
ADR0 => ab_xor_19_0,
ADR1 => a_reg(20),
ADR2 => b_reg(20),
ADR3 => b_reg_0_2_4323,
O => N483
);
Sh30_f5_F : X_LUT4
generic map(
INIT => X"CC5A",
LOC => "SLICE_X14Y35"
)
port map (
ADR0 => b_reg(30),
ADR1 => ab_xor_29_0,
ADR2 => a_reg(30),
ADR3 => b_reg_0_3_4316,
O => N472
);
Sh30_f5_G : X_LUT4
generic map(
INIT => X"F066",
LOC => "SLICE_X14Y35"
)
port map (
ADR0 => a_reg(28),
ADR1 => b_reg(28),
ADR2 => ab_xor_27_0,
ADR3 => b_reg_0_3_4316,
O => N473
);
Sh17_f5_F : X_LUT4
generic map(
INIT => X"A3AC",
LOC => "SLICE_X14Y23"
)
port map (
ADR0 => ab_xor_16_0,
ADR1 => a_reg(17),
ADR2 => b_reg_0_2_4323,
ADR3 => b_reg(17),
O => N492
);
Sh17_f5_G : X_LUT4
generic map(
INIT => X"72D8",
LOC => "SLICE_X14Y23"
)
port map (
ADR0 => b_reg_0_2_4323,
ADR1 => b_reg(14),
ADR2 => ab_xor_15_0,
ADR3 => a_reg(14),
O => N493
);
Sh25_f5_F : X_LUT4
generic map(
INIT => X"F066",
LOC => "SLICE_X15Y32"
)
port map (
ADR0 => b_reg(25),
ADR1 => a_reg(25),
ADR2 => ab_xor_24_0,
ADR3 => b_reg_0_2_4323,
O => N488
);
Sh25_f5_G : X_LUT4
generic map(
INIT => X"72D8",
LOC => "SLICE_X15Y32"
)
port map (
ADR0 => b_reg_0_2_4323,
ADR1 => a_reg(22),
ADR2 => ab_xor_23_0,
ADR3 => b_reg(22),
O => N489
);
Sh18_f5_F : X_LUT4
generic map(
INIT => X"D1E2",
LOC => "SLICE_X13Y20"
)
port map (
ADR0 => a_reg(18),
ADR1 => b_reg_0_2_4323,
ADR2 => ab_xor_17_0,
ADR3 => b_reg(18),
O => N484
);
Sh18_f5_G : X_LUT4
generic map(
INIT => X"D1E2",
LOC => "SLICE_X13Y20"
)
port map (
ADR0 => b_reg(16),
ADR1 => b_reg_0_2_4323,
ADR2 => ab_xor_15_0,
ADR3 => a_reg(16),
O => N485
);
Sh26_f5_F : X_LUT4
generic map(
INIT => X"8DD8",
LOC => "SLICE_X14Y32"
)
port map (
ADR0 => b_reg_0_2_4323,
ADR1 => ab_xor_25_0,
ADR2 => a_reg(26),
ADR3 => b_reg(26),
O => N480
);
Sh26_f5_G : X_LUT4
generic map(
INIT => X"CC5A",
LOC => "SLICE_X14Y32"
)
port map (
ADR0 => b_reg(24),
ADR1 => ab_xor_23_0,
ADR2 => a_reg(24),
ADR3 => b_reg_0_2_4323,
O => N481
);
Sh29_f5_F : X_LUT4
generic map(
INIT => X"D1E2",
LOC => "SLICE_X15Y34"
)
port map (
ADR0 => b_reg(29),
ADR1 => b_reg_0_3_4316,
ADR2 => ab_xor_28_0,
ADR3 => a_reg(29),
O => N478
);
Sh29_f5_G : X_LUT4
generic map(
INIT => X"4EE4",
LOC => "SLICE_X15Y34"
)
port map (
ADR0 => b_reg_0_3_4316,
ADR1 => ab_xor_27_0,
ADR2 => b_reg(26),
ADR3 => a_reg(26),
O => N479
);
Sh4_F : X_LUT4
generic map(
INIT => X"F606",
LOC => "SLICE_X15Y19"
)
port map (
ADR0 => b_reg_4_1_4383,
ADR1 => a_reg(4),
ADR2 => b_reg_0_1_4382,
ADR3 => ab_xor_3_0,
O => N300
);
Sh4_G : X_LUT4
generic map(
INIT => X"2772",
LOC => "SLICE_X15Y19"
)
port map (
ADR0 => b_reg_0_2_4323,
ADR1 => a_reg(1),
ADR2 => a_reg(2),
ADR3 => b_reg_2_1_4381,
O => N301
);
Sh8_F : X_LUT4
generic map(
INIT => X"8DD8",
LOC => "SLICE_X12Y14"
)
port map (
ADR0 => b_reg_0_1_4382,
ADR1 => ab_xor_7_0,
ADR2 => a_reg(8),
ADR3 => b_reg(8),
O => N324
);
Sh8_G : X_LUT4
generic map(
INIT => X"AA3C",
LOC => "SLICE_X12Y14"
)
port map (
ADR0 => ab_xor_5_0,
ADR1 => a_reg(6),
ADR2 => b_reg(6),
ADR3 => b_reg_0_1_4382,
O => N325
);
Sh981 : X_LUT4
generic map(
INIT => X"66F0",
LOC => "SLICE_X23Y27"
)
port map (
ADR0 => b_reg(31),
ADR1 => a(31),
ADR2 => b_reg(0),
ADR3 => a(0),
O => Sh962
);
Sh1262_rt : X_LUT4
generic map(
INIT => X"AAAA",
LOC => "SLICE_X23Y27"
)
port map (
ADR0 => Sh1262_0,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => VCC,
O => Sh1262_rt_7104
);
Sh972 : X_LUT4
generic map(
INIT => X"7272",
LOC => "SLICE_X24Y27"
)
port map (
ADR0 => a(0),
ADR1 => b_reg(0),
ADR2 => b_reg(1),
ADR3 => VCC,
O => Sh972_7119
);
Sh1272_rt : X_LUT4
generic map(
INIT => X"FF00",
LOC => "SLICE_X24Y27"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => Sh1272_0,
O => Sh1272_rt_7129
);
Sh1021 : X_LUT4
generic map(
INIT => X"B18D",
LOC => "SLICE_X25Y27"
)
port map (
ADR0 => N263_0,
ADR1 => a(3),
ADR2 => a(4),
ADR3 => N264_0,
O => Sh1002
);
Sh1001 : X_LUT4
generic map(
INIT => X"335A",
LOC => "SLICE_X25Y27"
)
port map (
ADR0 => a(2),
ADR1 => b_reg(1),
ADR2 => b_reg(2),
ADR3 => a(0),
O => Sh1001_7156
);
Sh1031 : X_LUT4
generic map(
INIT => X"D18B",
LOC => "SLICE_X22Y18"
)
port map (
ADR0 => a(4),
ADR1 => N246_0,
ADR2 => a(5),
ADR3 => N247_0,
O => Sh1012
);
Sh1011_rt : X_LUT4
generic map(
INIT => X"FF00",
LOC => "SLICE_X22Y18"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => Sh1011,
O => Sh1011_rt_7183
);
Sh1221 : X_LUT4
generic map(
INIT => X"B18D",
LOC => "SLICE_X21Y28"
)
port map (
ADR0 => N181_0,
ADR1 => a(23),
ADR2 => a(24),
ADR3 => N182_0,
O => Sh1202
);
Sh1182_rt : X_LUT4
generic map(
INIT => X"FF00",
LOC => "SLICE_X21Y28"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => Sh1182_0,
O => Sh1182_rt_7210
);
Sh1141 : X_LUT4
generic map(
INIT => X"AC35",
LOC => "SLICE_X25Y20"
)
port map (
ADR0 => a(16),
ADR1 => a(15),
ADR2 => N194_0,
ADR3 => N193_0,
O => Sh1122
);
Sh1102_rt : X_LUT4
generic map(
INIT => X"F0F0",
LOC => "SLICE_X25Y20"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => Sh1102_0,
ADR3 => VCC,
O => Sh1102_rt_7237
);
Sh1061 : X_LUT4
generic map(
INIT => X"8BD1",
LOC => "SLICE_X20Y13"
)
port map (
ADR0 => a(8),
ADR1 => N260_0,
ADR2 => a(7),
ADR3 => N261_0,
O => Sh1042
);
Sh1022_rt : X_LUT4
generic map(
INIT => X"FF00",
LOC => "SLICE_X20Y13"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => Sh1022_0,
O => Sh1022_rt_7264
);
Sh1231 : X_LUT4
generic map(
INIT => X"B18D",
LOC => "SLICE_X23Y29"
)
port map (
ADR0 => a(25),
ADR1 => N179_0,
ADR2 => N178_0,
ADR3 => a(24),
O => Sh1212
);
Sh1192_rt : X_LUT4
generic map(
INIT => X"FF00",
LOC => "SLICE_X23Y29"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => Sh1192_0,
O => Sh1192_rt_7291
);
Sh1151 : X_LUT4
generic map(
INIT => X"D18B",
LOC => "SLICE_X24Y20"
)
port map (
ADR0 => N191_0,
ADR1 => a(17),
ADR2 => N190_0,
ADR3 => a(16),
O => Sh1132
);
Sh1112_rt : X_LUT4
generic map(
INIT => X"F0F0",
LOC => "SLICE_X24Y20"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => Sh1112_0,
ADR3 => VCC,
O => Sh1112_rt_7318
);
Sh1071 : X_LUT4
generic map(
INIT => X"D81B",
LOC => "SLICE_X20Y12"
)
port map (
ADR0 => a(8),
ADR1 => N240_0,
ADR2 => N241_0,
ADR3 => a(9),
O => Sh1052
);
Sh1032_rt : X_LUT4
generic map(
INIT => X"FF00",
LOC => "SLICE_X20Y12"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => Sh1032_0,
O => Sh1032_rt_7345
);
Sh1261 : X_LUT4
generic map(
INIT => X"AC35",
LOC => "SLICE_X22Y29"
)
port map (
ADR0 => a(28),
ADR1 => a(27),
ADR2 => N176_0,
ADR3 => N175_0,
O => Sh1242
);
Sh1222_rt : X_LUT4
generic map(
INIT => X"AAAA",
LOC => "SLICE_X22Y29"
)
port map (
ADR0 => Sh1222_0,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => VCC,
O => Sh1222_rt_7372
);
Sh1181 : X_LUT4
generic map(
INIT => X"E247",
LOC => "SLICE_X25Y24"
)
port map (
ADR0 => N188_0,
ADR1 => a(19),
ADR2 => N187_0,
ADR3 => a(20),
O => Sh1162
);
Sh1142_rt : X_LUT4
generic map(
INIT => X"F0F0",
LOC => "SLICE_X25Y24"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => Sh1142_0,
ADR3 => VCC,
O => Sh1142_rt_7399
);
Sh1101 : X_LUT4
generic map(
INIT => X"CA53",
LOC => "SLICE_X22Y12"
)
port map (
ADR0 => N258_0,
ADR1 => N257_0,
ADR2 => a(11),
ADR3 => a(12),
O => Sh1082
);
Sh1062_rt : X_LUT4
generic map(
INIT => X"CCCC",
LOC => "SLICE_X22Y12"
)
port map (
ADR0 => VCC,
ADR1 => Sh1062_0,
ADR2 => VCC,
ADR3 => VCC,
O => Sh1062_rt_7426
);
Sh1271 : X_LUT4
generic map(
INIT => X"8DB1",
LOC => "SLICE_X23Y30"
)
port map (
ADR0 => N172_0,
ADR1 => a(29),
ADR2 => a(28),
ADR3 => N173_0,
O => Sh1252
);
Sh1232_rt : X_LUT4
generic map(
INIT => X"F0F0",
LOC => "SLICE_X23Y30"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => Sh1232_0,
ADR3 => VCC,
O => Sh1232_rt_7453
);
Sh1191 : X_LUT4
generic map(
INIT => X"8BD1",
LOC => "SLICE_X25Y25"
)
port map (
ADR0 => N184_0,
ADR1 => a(21),
ADR2 => N185_0,
ADR3 => a(20),
O => Sh1172
);
Sh1152_rt : X_LUT4
generic map(
INIT => X"FF00",
LOC => "SLICE_X25Y25"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => Sh1152_0,
O => Sh1152_rt_7480
);
Sh1111 : X_LUT4
generic map(
INIT => X"B81D",
LOC => "SLICE_X22Y16"
)
port map (
ADR0 => N234_0,
ADR1 => a(12),
ADR2 => N235_0,
ADR3 => a(13),
O => Sh1092
);
Sh1072_rt : X_LUT4
generic map(
INIT => X"CCCC",
LOC => "SLICE_X22Y16"
)
port map (
ADR0 => VCC,
ADR1 => Sh1072_0,
ADR2 => VCC,
ADR3 => VCC,
O => Sh1072_rt_7507
);
Sh3_f51_F : X_LUT4
generic map(
INIT => X"7B48",
LOC => "SLICE_X12Y20"
)
port map (
ADR0 => b_reg_2_1_4381,
ADR1 => b_reg_0_3_4316,
ADR2 => a_reg(2),
ADR3 => ab_xor_3_0,
O => N308
);
Sh3_f51_G : X_LUT4
generic map(
INIT => X"3355",
LOC => "SLICE_X12Y20"
)
port map (
ADR0 => a_reg(1),
ADR1 => a_reg(0),
ADR2 => VCC,
ADR3 => b_reg(0),
O => N309
);
Sh7_f51_F : X_LUT4
generic map(
INIT => X"72D8",
LOC => "SLICE_X13Y17"
)
port map (
ADR0 => b_reg_0_3_4316,
ADR1 => a_reg(6),
ADR2 => ab_xor_7_0,
ADR3 => b_reg(6),
O => N336
);
Sh7_f51_G : X_LUT4
generic map(
INIT => X"B1E4",
LOC => "SLICE_X13Y17"
)
port map (
ADR0 => b_reg_0_3_4316,
ADR1 => b_reg(5),
ADR2 => ab_xor_4_0,
ADR3 => a_reg(5),
O => N337
);
Sh11_f51_F : X_LUT4
generic map(
INIT => X"74B8",
LOC => "SLICE_X13Y12"
)
port map (
ADR0 => a_reg(10),
ADR1 => b_reg_0_3_4316,
ADR2 => ab_xor_11_0,
ADR3 => b_reg(10),
O => N348
);
Sh11_f51_G : X_LUT4
generic map(
INIT => X"D1E2",
LOC => "SLICE_X13Y12"
)
port map (
ADR0 => a_reg(9),
ADR1 => b_reg_0_3_4316,
ADR2 => ab_xor_8_0,
ADR3 => b_reg(9),
O => N349
);
Sh15_f51_F : X_LUT4
generic map(
INIT => X"72D8",
LOC => "SLICE_X13Y16"
)
port map (
ADR0 => b_reg_0_3_4316,
ADR1 => b_reg(14),
ADR2 => ab_xor_15_0,
ADR3 => a_reg(14),
O => N346
);
Sh15_f51_G : X_LUT4
generic map(
INIT => X"BE14",
LOC => "SLICE_X13Y16"
)
port map (
ADR0 => b_reg_0_3_4316,
ADR1 => b_reg(13),
ADR2 => a_reg(13),
ADR3 => ab_xor_12_0,
O => N347
);
Sh23_f51_F : X_LUT4
generic map(
INIT => X"72D8",
LOC => "SLICE_X15Y33"
)
port map (
ADR0 => b_reg_0_3_4316,
ADR1 => a_reg(22),
ADR2 => ab_xor_23_0,
ADR3 => b_reg(22),
O => N342
);
Sh23_f51_G : X_LUT4
generic map(
INIT => X"B1E4",
LOC => "SLICE_X15Y33"
)
port map (
ADR0 => b_reg_0_3_4316,
ADR1 => b_reg(21),
ADR2 => ab_xor_20_0,
ADR3 => a_reg(21),
O => N343
);
Sh31_f51_F : X_LUT4
generic map(
INIT => X"66F0",
LOC => "SLICE_X12Y34"
)
port map (
ADR0 => a_reg(30),
ADR1 => b_reg(30),
ADR2 => ab_xor_31_0,
ADR3 => b_reg_0_3_4316,
O => N338
);
Sh31_f51_G : X_LUT4
generic map(
INIT => X"D1E2",
LOC => "SLICE_X12Y34"
)
port map (
ADR0 => a_reg(29),
ADR1 => b_reg_0_3_4316,
ADR2 => ab_xor_28_0,
ADR3 => b_reg(29),
O => N339
);
Sh19_f51_F : X_LUT4
generic map(
INIT => X"66F0",
LOC => "SLICE_X14Y22"
)
port map (
ADR0 => b_reg(18),
ADR1 => a_reg(18),
ADR2 => ab_xor_19_0,
ADR3 => b_reg_0_3_4316,
O => N344
);
Sh19_f51_G : X_LUT4
generic map(
INIT => X"A3AC",
LOC => "SLICE_X14Y22"
)
port map (
ADR0 => ab_xor_16_0,
ADR1 => a_reg(17),
ADR2 => b_reg_0_3_4316,
ADR3 => b_reg(17),
O => N345
);
Sh27_f51_F : X_LUT4
generic map(
INIT => X"66F0",
LOC => "SLICE_X14Y34"
)
port map (
ADR0 => a_reg(26),
ADR1 => b_reg(26),
ADR2 => ab_xor_27_0,
ADR3 => b_reg_0_3_4316,
O => N340
);
Sh27_f51_G : X_LUT4
generic map(
INIT => X"F066",
LOC => "SLICE_X14Y34"
)
port map (
ADR0 => a_reg(25),
ADR1 => b_reg(25),
ADR2 => ab_xor_24_0,
ADR3 => b_reg_0_3_4316,
O => N341
);
Sh12_F : X_LUT4
generic map(
INIT => X"8DD8",
LOC => "SLICE_X12Y15"
)
port map (
ADR0 => b_reg_0_1_4382,
ADR1 => ab_xor_11_0,
ADR2 => a_reg(12),
ADR3 => b_reg(12),
O => N334
);
Sh12_G : X_LUT4
generic map(
INIT => X"F606",
LOC => "SLICE_X12Y15"
)
port map (
ADR0 => a_reg(10),
ADR1 => b_reg(10),
ADR2 => b_reg_0_1_4382,
ADR3 => ab_xor_9_0,
O => N335
);
Sh20_F : X_LUT4
generic map(
INIT => X"BE14",
LOC => "SLICE_X15Y25"
)
port map (
ADR0 => b_reg_0_1_4382,
ADR1 => a_reg(20),
ADR2 => b_reg(20),
ADR3 => ab_xor_19_0,
O => N330
);
Sh20_G : X_LUT4
generic map(
INIT => X"B1E4",
LOC => "SLICE_X15Y25"
)
port map (
ADR0 => b_reg_0_1_4382,
ADR1 => a_reg(18),
ADR2 => ab_xor_17_0,
ADR3 => b_reg(18),
O => N331
);
Sh16_F : X_LUT4
generic map(
INIT => X"8DD8",
LOC => "SLICE_X12Y21"
)
port map (
ADR0 => b_reg_0_1_4382,
ADR1 => ab_xor_15_0,
ADR2 => a_reg(16),
ADR3 => b_reg(16),
O => N332
);
Sh16_G : X_LUT4
generic map(
INIT => X"8DD8",
LOC => "SLICE_X12Y21"
)
port map (
ADR0 => b_reg_0_1_4382,
ADR1 => ab_xor_13_0,
ADR2 => a_reg(14),
ADR3 => b_reg(14),
O => N333
);
Sh24_F : X_LUT4
generic map(
INIT => X"CC5A",
LOC => "SLICE_X14Y33"
)
port map (
ADR0 => b_reg(24),
ADR1 => ab_xor_23_0,
ADR2 => a_reg(24),
ADR3 => b_reg_0_1_4382,
O => N328
);
Sh24_G : X_LUT4
generic map(
INIT => X"BE14",
LOC => "SLICE_X14Y33"
)
port map (
ADR0 => b_reg_0_1_4382,
ADR1 => b_reg(22),
ADR2 => a_reg(22),
ADR3 => ab_xor_21_0,
O => N329
);
Sh28_F : X_LUT4
generic map(
INIT => X"CC5A",
LOC => "SLICE_X15Y35"
)
port map (
ADR0 => a_reg(28),
ADR1 => ab_xor_27_0,
ADR2 => b_reg(28),
ADR3 => b_reg_0_1_4382,
O => N326
);
Sh28_G : X_LUT4
generic map(
INIT => X"AA3C",
LOC => "SLICE_X15Y35"
)
port map (
ADR0 => ab_xor_25_0,
ADR1 => a_reg(26),
ADR2 => b_reg(26),
ADR3 => b_reg_0_1_4382,
O => N327
);
Sh123_f51_F : X_LUT4
generic map(
INIT => X"D18B",
LOC => "SLICE_X23Y28"
)
port map (
ADR0 => a(26),
ADR1 => N199_0,
ADR2 => a(27),
ADR3 => N200,
O => N496
);
Sh123_f51_G : X_LUT4
generic map(
INIT => X"B18D",
LOC => "SLICE_X23Y28"
)
port map (
ADR0 => a(25),
ADR1 => N179_0,
ADR2 => N178_0,
ADR3 => a(24),
O => N497
);
Sh127_f51_F : X_LUT4
generic map(
INIT => X"8DB1",
LOC => "SLICE_X21Y30"
)
port map (
ADR0 => N196_0,
ADR1 => a(31),
ADR2 => a(30),
ADR3 => N197,
O => N460
);
Sh127_f51_G : X_LUT4
generic map(
INIT => X"8BD1",
LOC => "SLICE_X21Y30"
)
port map (
ADR0 => a(29),
ADR1 => N172_0,
ADR2 => a(28),
ADR3 => N173_0,
O => N461
);
Sh145312 : X_LUT4
generic map(
INIT => X"F0CC",
LOC => "SLICE_X24Y15"
)
port map (
ADR0 => VCC,
ADR1 => Sh113,
ADR2 => Sh109,
ADR3 => a(2),
O => Sh145311_7899
);
Sh145311 : X_LUT4
generic map(
INIT => X"F0CC",
LOC => "SLICE_X24Y15"
)
port map (
ADR0 => VCC,
ADR1 => Sh105,
ADR2 => Sh101,
ADR3 => a(2),
O => Sh14531
);
Sh192_F : X_LUT4
generic map(
INIT => X"4EE4",
LOC => "SLICE_X12Y35"
)
port map (
ADR0 => b_reg_0_1_4382,
ADR1 => a_reg(0),
ADR2 => b_reg(31),
ADR3 => a_reg(31),
O => N410
);
Sh192_G : X_LUT4
generic map(
INIT => X"BE14",
LOC => "SLICE_X12Y35"
)
port map (
ADR0 => b_reg_0_1_4382,
ADR1 => b_reg(30),
ADR2 => a_reg(30),
ADR3 => ab_xor_29_0,
O => N411
);
b_reg_mux0000_2_37_SW0_F : X_LUT4
generic map(
INIT => X"FCAA",
LOC => "SLICE_X8Y3"
)
port map (
ADR0 => b_reg(2),
ADR1 => b_reg_mux0000_2_5_0,
ADR2 => b_reg_mux0000_2_13_0,
ADR3 => state_FSM_FFd2_4312,
O => N464
);
b_reg_mux0000_2_37_SW0_G : X_LUT4
generic map(
INIT => X"00CC",
LOC => "SLICE_X8Y3"
)
port map (
ADR0 => VCC,
ADR1 => b_reg(2),
ADR2 => VCC,
ADR3 => state_FSM_FFd2_4312,
O => N465
);
b_reg_mux0000_2_37_SW1_F : X_LUT4
generic map(
INIT => X"FCAA",
LOC => "SLICE_X8Y2"
)
port map (
ADR0 => b_reg(2),
ADR1 => b_reg_mux0000_2_5_0,
ADR2 => b_reg_mux0000_2_13_0,
ADR3 => state_FSM_FFd2_4312,
O => N466
);
b_reg_mux0000_2_37_SW1_G : X_LUT4
generic map(
INIT => X"FFCC",
LOC => "SLICE_X8Y2"
)
port map (
ADR0 => VCC,
ADR1 => b_reg(2),
ADR2 => VCC,
ADR3 => state_FSM_FFd2_4312,
O => N467
);
b_reg_mux0000_3_24_SW0_F : X_LUT4
generic map(
INIT => X"A5CC",
LOC => "SLICE_X2Y20"
)
port map (
ADR0 => Madd_b_pre_cy_2_Q,
ADR1 => b_reg(3),
ADR2 => swtch_led_3_OBUF_4256,
ADR3 => state_FSM_FFd2_4312,
O => N456
);
Sh5131_F : X_LUT4
generic map(
INIT => X"CACA",
LOC => "SLICE_X13Y25"
)
port map (
ADR0 => Sh19,
ADR1 => Sh11,
ADR2 => b_reg(3),
ADR3 => VCC,
O => N354
);
Sh5131_G : X_LUT4
generic map(
INIT => X"E4E4",
LOC => "SLICE_X13Y25"
)
port map (
ADR0 => b_reg(3),
ADR1 => Sh15,
ADR2 => Sh7,
ADR3 => VCC,
O => N355
);
Sh1597_F : X_LUT4
generic map(
INIT => X"F5A0",
LOC => "SLICE_X26Y26"
)
port map (
ADR0 => a(1),
ADR1 => VCC,
ADR2 => Sh1212_0,
ADR3 => Sh1232_0,
O => N468
);
Sh1597_G : X_LUT4
generic map(
INIT => X"E4E4",
LOC => "SLICE_X26Y26"
)
port map (
ADR0 => a(1),
ADR1 => Sh1152_0,
ADR2 => Sh1132_0,
ADR3 => VCC,
O => N469
);
Sh1781_F : X_LUT4
generic map(
INIT => X"DDDC",
LOC => "SLICE_X27Y14"
)
port map (
ADR0 => a(2),
ADR1 => Sh14612,
ADR2 => Sh14613_0,
ADR3 => Sh14616_0,
O => N322
);
Sh1781_G : X_LUT4
generic map(
INIT => X"FE0E",
LOC => "SLICE_X27Y14"
)
port map (
ADR0 => Sh13016_0,
ADR1 => Sh13013_0,
ADR2 => a(2),
ADR3 => Sh1307,
O => N323
);
Sh4431_F : X_LUT4
generic map(
INIT => X"CCF0",
LOC => "SLICE_X12Y22"
)
port map (
ADR0 => VCC,
ADR1 => Sh4,
ADR2 => Sh12,
ADR3 => b_reg(3),
O => N386
);
Sh4431_G : X_LUT4
generic map(
INIT => X"CCAA",
LOC => "SLICE_X12Y22"
)
port map (
ADR0 => Sh8,
ADR1 => Sh,
ADR2 => VCC,
ADR3 => b_reg(3),
O => N387
);
Sh6031_F : X_LUT4
generic map(
INIT => X"CCAA",
LOC => "SLICE_X12Y27"
)
port map (
ADR0 => Sh28,
ADR1 => Sh20,
ADR2 => VCC,
ADR3 => b_reg(3),
O => N384
);
Sh6031_G : X_LUT4
generic map(
INIT => X"AACC",
LOC => "SLICE_X12Y27"
)
port map (
ADR0 => Sh16,
ADR1 => Sh24,
ADR2 => VCC,
ADR3 => b_reg(3),
O => N385
);
Sh3631_F : X_LUT4
generic map(
INIT => X"EE44",
LOC => "SLICE_X13Y24"
)
port map (
ADR0 => b_reg(3),
ADR1 => Sh4,
ADR2 => VCC,
ADR3 => Sh28,
O => N360
);
Sh3631_G : X_LUT4
generic map(
INIT => X"FA0A",
LOC => "SLICE_X13Y24"
)
port map (
ADR0 => Sh,
ADR1 => VCC,
ADR2 => b_reg(3),
ADR3 => Sh24,
O => N361
);
Sh5231_F : X_LUT4
generic map(
INIT => X"F5A0",
LOC => "SLICE_X13Y18"
)
port map (
ADR0 => b_reg(3),
ADR1 => VCC,
ADR2 => Sh12,
ADR3 => Sh20,
O => N358
);
Sh5231_G : X_LUT4
generic map(
INIT => X"FA50",
LOC => "SLICE_X13Y18"
)
port map (
ADR0 => b_reg(3),
ADR1 => VCC,
ADR2 => Sh16,
ADR3 => Sh8,
O => N359
);
Sh4531_F : X_LUT4
generic map(
INIT => X"AACC",
LOC => "SLICE_X16Y26"
)
port map (
ADR0 => Sh5,
ADR1 => Sh13,
ADR2 => VCC,
ADR3 => b_reg(3),
O => N430
);
Sh4531_G : X_LUT4
generic map(
INIT => X"F0CC",
LOC => "SLICE_X16Y26"
)
port map (
ADR0 => VCC,
ADR1 => Sh9,
ADR2 => Sh1,
ADR3 => b_reg(3),
O => N431
);
Sh3731_F : X_LUT4
generic map(
INIT => X"FA50",
LOC => "SLICE_X14Y26"
)
port map (
ADR0 => b_reg(3),
ADR1 => VCC,
ADR2 => Sh5,
ADR3 => Sh29,
O => N390
);
Sh3731_G : X_LUT4
generic map(
INIT => X"FA50",
LOC => "SLICE_X14Y26"
)
port map (
ADR0 => b_reg(3),
ADR1 => VCC,
ADR2 => Sh1,
ADR3 => Sh25,
O => N391
);
Sh5331_F : X_LUT4
generic map(
INIT => X"AAF0",
LOC => "SLICE_X15Y27"
)
port map (
ADR0 => Sh13,
ADR1 => VCC,
ADR2 => Sh21,
ADR3 => b_reg(3),
O => N388
);
Sh5331_G : X_LUT4
generic map(
INIT => X"E4E4",
LOC => "SLICE_X15Y27"
)
port map (
ADR0 => b_reg(3),
ADR1 => Sh17,
ADR2 => Sh9,
ADR3 => VCC,
O => N389
);
Sh4631_F : X_LUT4
generic map(
INIT => X"AAF0",
LOC => "SLICE_X14Y28"
)
port map (
ADR0 => Sh6,
ADR1 => VCC,
ADR2 => Sh14,
ADR3 => b_reg(3),
O => N422
);
Sh4631_G : X_LUT4
generic map(
INIT => X"E4E4",
LOC => "SLICE_X14Y28"
)
port map (
ADR0 => b_reg(3),
ADR1 => Sh10,
ADR2 => Sh2,
ADR3 => VCC,
O => N423
);
Sh3831_F : X_LUT4
generic map(
INIT => X"EE22",
LOC => "SLICE_X14Y31"
)
port map (
ADR0 => Sh6,
ADR1 => b_reg(3),
ADR2 => VCC,
ADR3 => Sh30,
O => N394
);
Sh3831_G : X_LUT4
generic map(
INIT => X"D8D8",
LOC => "SLICE_X14Y31"
)
port map (
ADR0 => b_reg(3),
ADR1 => Sh26,
ADR2 => Sh2,
ADR3 => VCC,
O => N395
);
Sh5431_F : X_LUT4
generic map(
INIT => X"AAF0",
LOC => "SLICE_X12Y28"
)
port map (
ADR0 => Sh14,
ADR1 => VCC,
ADR2 => Sh22_4347,
ADR3 => b_reg(3),
O => N392
);
Sh5431_G : X_LUT4
generic map(
INIT => X"CCAA",
LOC => "SLICE_X12Y28"
)
port map (
ADR0 => Sh18,
ADR1 => Sh10,
ADR2 => VCC,
ADR3 => b_reg(3),
O => N393
);
Sh4731_F : X_LUT4
generic map(
INIT => X"E4E4",
LOC => "SLICE_X13Y21"
)
port map (
ADR0 => b_reg(3),
ADR1 => Sh15,
ADR2 => Sh7,
ADR3 => VCC,
O => N398
);
Sh4731_G : X_LUT4
generic map(
INIT => X"EE44",
LOC => "SLICE_X13Y21"
)
port map (
ADR0 => b_reg(3),
ADR1 => Sh11,
ADR2 => VCC,
ADR3 => Sh3,
O => N399
);
Sh6331_F : X_LUT4
generic map(
INIT => X"CCAA",
LOC => "SLICE_X12Y33"
)
port map (
ADR0 => Sh31,
ADR1 => Sh23_4457,
ADR2 => VCC,
ADR3 => b_reg(3),
O => N396
);
Sh6331_G : X_LUT4
generic map(
INIT => X"FC30",
LOC => "SLICE_X12Y33"
)
port map (
ADR0 => VCC,
ADR1 => b_reg(3),
ADR2 => Sh27,
ADR3 => Sh19,
O => N397
);
Sh3931_F : X_LUT4
generic map(
INIT => X"D8D8",
LOC => "SLICE_X13Y28"
)
port map (
ADR0 => b_reg(3),
ADR1 => Sh31,
ADR2 => Sh7,
ADR3 => VCC,
O => N364
);
Sh3931_G : X_LUT4
generic map(
INIT => X"DD88",
LOC => "SLICE_X13Y28"
)
port map (
ADR0 => b_reg(3),
ADR1 => Sh27,
ADR2 => VCC,
ADR3 => Sh3,
O => N365
);
Sh5531_F : X_LUT4
generic map(
INIT => X"CFC0",
LOC => "SLICE_X13Y30"
)
port map (
ADR0 => VCC,
ADR1 => Sh15,
ADR2 => b_reg(3),
ADR3 => Sh23_4457,
O => N362
);
Sh5531_G : X_LUT4
generic map(
INIT => X"FA0A",
LOC => "SLICE_X13Y30"
)
port map (
ADR0 => Sh19,
ADR1 => VCC,
ADR2 => b_reg(3),
ADR3 => Sh11,
O => N363
);
Sh5631_F : X_LUT4
generic map(
INIT => X"FA50",
LOC => "SLICE_X13Y27"
)
port map (
ADR0 => b_reg(3),
ADR1 => VCC,
ADR2 => Sh24,
ADR3 => Sh16,
O => N366
);
Sh5631_G : X_LUT4
generic map(
INIT => X"D8D8",
LOC => "SLICE_X13Y27"
)
port map (
ADR0 => b_reg(3),
ADR1 => Sh12,
ADR2 => Sh20,
ADR3 => VCC,
O => N367
);
Sh4831_F : X_LUT4
generic map(
INIT => X"BB88",
LOC => "SLICE_X12Y25"
)
port map (
ADR0 => Sh8,
ADR1 => b_reg(3),
ADR2 => VCC,
ADR3 => Sh16,
O => N350
);
Sh4831_G : X_LUT4
generic map(
INIT => X"F3C0",
LOC => "SLICE_X12Y25"
)
port map (
ADR0 => VCC,
ADR1 => b_reg(3),
ADR2 => Sh4,
ADR3 => Sh12,
O => N351
);
Sh4931_F : X_LUT4
generic map(
INIT => X"CCF0",
LOC => "SLICE_X14Y24"
)
port map (
ADR0 => VCC,
ADR1 => Sh9,
ADR2 => Sh17,
ADR3 => b_reg(3),
O => N372
);
Sh4931_G : X_LUT4
generic map(
INIT => X"F3C0",
LOC => "SLICE_X14Y24"
)
port map (
ADR0 => VCC,
ADR1 => b_reg(3),
ADR2 => Sh5,
ADR3 => Sh13,
O => N373
);
Sh5931_F : X_LUT4
generic map(
INIT => X"B8B8",
LOC => "SLICE_X12Y31"
)
port map (
ADR0 => Sh19,
ADR1 => b_reg(3),
ADR2 => Sh27,
ADR3 => VCC,
O => N380
);
Sh5931_G : X_LUT4
generic map(
INIT => X"E2E2",
LOC => "SLICE_X12Y31"
)
port map (
ADR0 => Sh23_4457,
ADR1 => b_reg(3),
ADR2 => Sh15,
ADR3 => VCC,
O => N381
);
b_reg_mux0000_5_24_SW0_F : X_LUT4
generic map(
INIT => X"AC5C",
LOC => "SLICE_X3Y17"
)
port map (
ADR0 => swtch_led_5_OBUF_4258,
ADR1 => b_reg(5),
ADR2 => state_FSM_FFd2_4312,
ADR3 => Madd_b_pre_cy_4_0,
O => N448
);
b_reg_mux0000_5_24_SW0_G : X_LUT4
generic map(
INIT => X"0F00",
LOC => "SLICE_X3Y17"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => state_FSM_FFd2_4312,
ADR3 => b_reg(5),
O => N449
);
b_reg_mux0000_5_24_SW1_F : X_LUT4
generic map(
INIT => X"B874",
LOC => "SLICE_X2Y17"
)
port map (
ADR0 => Madd_b_pre_cy_4_0,
ADR1 => state_FSM_FFd2_4312,
ADR2 => b_reg(5),
ADR3 => swtch_led_5_OBUF_4258,
O => N450
);
b_reg_mux0000_5_24_SW1_G : X_LUT4
generic map(
INIT => X"EEEE",
LOC => "SLICE_X2Y17"
)
port map (
ADR0 => b_reg(5),
ADR1 => state_FSM_FFd2_4312,
ADR2 => VCC,
ADR3 => VCC,
O => N451
);
b_reg_mux0000_8_21_F : X_LUT4
generic map(
INIT => X"BBAA",
LOC => "SLICE_X16Y15"
)
port map (
ADR0 => b_reg_mux0000_10_10_0,
ADR1 => state_FSM_FFd2_4312,
ADR2 => VCC,
ADR3 => b_reg(8),
O => N532
);
b_reg_mux0000_8_21_G : X_LUT4
generic map(
INIT => X"EFEA",
LOC => "SLICE_X16Y15"
)
port map (
ADR0 => b_reg_mux0000_10_10_0,
ADR1 => state_FSM_FFd1_4311,
ADR2 => state_FSM_FFd2_4312,
ADR3 => b_reg(8),
O => N533
);
b_reg_8 : X_FF
generic map(
LOC => "SLICE_X16Y15",
INIT => '0'
)
port map (
I => b_reg_8_DXMUX_9240,
CE => VCC,
CLK => b_reg_8_CLKINV_9222,
SET => GND,
RST => b_reg_8_FFX_RSTAND_9245,
O => b_reg(8)
);
b_reg_8_FFX_RSTAND : X_BUF
generic map(
LOC => "SLICE_X16Y15",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => b_reg_8_FFX_RSTAND_9245
);
b_reg_mux0000_9_21_F : X_LUT4
generic map(
INIT => X"BABA",
LOC => "SLICE_X16Y14"
)
port map (
ADR0 => b_reg_mux0000_10_10_0,
ADR1 => state_FSM_FFd2_4312,
ADR2 => b_reg(9),
ADR3 => VCC,
O => N530
);
b_reg_mux0000_9_21_G : X_LUT4
generic map(
INIT => X"FEBA",
LOC => "SLICE_X16Y14"
)
port map (
ADR0 => b_reg_mux0000_10_10_0,
ADR1 => state_FSM_FFd2_4312,
ADR2 => b_reg(9),
ADR3 => state_FSM_FFd1_4311,
O => N531
);
b_reg_9 : X_FF
generic map(
LOC => "SLICE_X16Y14",
INIT => '0'
)
port map (
I => b_reg_9_DXMUX_9276,
CE => VCC,
CLK => b_reg_9_CLKINV_9258,
SET => GND,
RST => b_reg_9_FFX_RSTAND_9281,
O => b_reg(9)
);
b_reg_9_FFX_RSTAND : X_BUF
generic map(
LOC => "SLICE_X16Y14",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => b_reg_9_FFX_RSTAND_9281
);
b_reg_mux0000_6_34_SW0_F : X_LUT4
generic map(
INIT => X"FCAC",
LOC => "SLICE_X3Y13"
)
port map (
ADR0 => b_reg_mux0000_6_3_0,
ADR1 => b_reg(6),
ADR2 => state_FSM_FFd2_4312,
ADR3 => b_reg_mux0000_6_12_0,
O => N444
);
b_reg_mux0000_6_34_SW0_G : X_LUT4
generic map(
INIT => X"0F00",
LOC => "SLICE_X3Y13"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => state_FSM_FFd2_4312,
ADR3 => b_reg(6),
O => N445
);
b_reg_mux0000_6_34_SW1_F : X_LUT4
generic map(
INIT => X"FCB8",
LOC => "SLICE_X2Y13"
)
port map (
ADR0 => b_reg_mux0000_6_12_0,
ADR1 => state_FSM_FFd2_4312,
ADR2 => b_reg(6),
ADR3 => b_reg_mux0000_6_3_0,
O => N446
);
b_reg_mux0000_6_34_SW1_G : X_LUT4
generic map(
INIT => X"EEEE",
LOC => "SLICE_X2Y13"
)
port map (
ADR0 => b_reg(6),
ADR1 => state_FSM_FFd2_4312,
ADR2 => VCC,
ADR3 => VCC,
O => N447
);
Sh1_f5_F : X_LUT4
generic map(
INIT => X"3F30",
LOC => "SLICE_X13Y35"
)
port map (
ADR0 => VCC,
ADR1 => a_reg(0),
ADR2 => b_reg_0_3_4316,
ADR3 => a_reg(1),
O => N404
);
Sh1_f5_G : X_LUT4
generic map(
INIT => X"4EE4",
LOC => "SLICE_X13Y35"
)
port map (
ADR0 => b_reg_0_3_4316,
ADR1 => ab_xor_31_0,
ADR2 => b_reg(30),
ADR3 => a_reg(30),
O => N405
);
Sh23 : X_LUT4
generic map(
INIT => X"A3AC",
LOC => "SLICE_X13Y32"
)
port map (
ADR0 => a_reg(1),
ADR1 => a_reg(2),
ADR2 => b_reg_0_3_4316,
ADR3 => b_reg_2_1_4381,
O => Sh211
);
Sh22 : X_LUT4
generic map(
INIT => X"7D28",
LOC => "SLICE_X13Y32"
)
port map (
ADR0 => b_reg_0_3_4316,
ADR1 => a_reg(31),
ADR2 => b_reg(31),
ADR3 => a_reg(0),
O => Sh210
);
Sh5_f5_F : X_LUT4
generic map(
INIT => X"DE12",
LOC => "SLICE_X12Y19"
)
port map (
ADR0 => a_reg(5),
ADR1 => b_reg_0_3_4316,
ADR2 => b_reg(5),
ADR3 => ab_xor_4_0,
O => N476
);
Sh5_f5_G : X_LUT4
generic map(
INIT => X"7B48",
LOC => "SLICE_X12Y19"
)
port map (
ADR0 => b_reg_2_1_4381,
ADR1 => b_reg_0_3_4316,
ADR2 => a_reg(2),
ADR3 => ab_xor_3_0,
O => N477
);
b_reg_mux0000_7_24_SW0_F : X_LUT4
generic map(
INIT => X"D872",
LOC => "SLICE_X12Y8"
)
port map (
ADR0 => state_FSM_FFd2_4312,
ADR1 => Madd_b_pre_cy_6_Q,
ADR2 => b_reg(7),
ADR3 => swtch_led_7_OBUF_4260,
O => N440
);
b_reg_mux0000_7_24_SW0_G : X_LUT4
generic map(
INIT => X"3030",
LOC => "SLICE_X12Y8"
)
port map (
ADR0 => VCC,
ADR1 => state_FSM_FFd2_4312,
ADR2 => b_reg(7),
ADR3 => VCC,
O => N441
);
b_reg_mux0000_7_24_SW1_F : X_LUT4
generic map(
INIT => X"D872",
LOC => "SLICE_X9Y3"
)
port map (
ADR0 => state_FSM_FFd2_4312,
ADR1 => Madd_b_pre_cy_6_Q,
ADR2 => b_reg(7),
ADR3 => swtch_led_7_OBUF_4260,
O => N442
);
b_reg_mux0000_7_24_SW1_G : X_LUT4
generic map(
INIT => X"FAFA",
LOC => "SLICE_X9Y3"
)
port map (
ADR0 => state_FSM_FFd2_4312,
ADR1 => VCC,
ADR2 => b_reg(7),
ADR3 => VCC,
O => N443
);
Sh6_f5_F : X_LUT4
generic map(
INIT => X"DE12",
LOC => "SLICE_X12Y18"
)
port map (
ADR0 => b_reg(6),
ADR1 => b_reg_0_3_4316,
ADR2 => a_reg(6),
ADR3 => ab_xor_5_0,
O => N462
);
Sh6_f5_G : X_LUT4
generic map(
INIT => X"D1E2",
LOC => "SLICE_X12Y18"
)
port map (
ADR0 => a_reg(4),
ADR1 => b_reg_0_3_4316,
ADR2 => ab_xor_3_0,
ADR3 => b_reg(4),
O => N463
);
Sh9_f5_F : X_LUT4
generic map(
INIT => X"BE14",
LOC => "SLICE_X15Y15"
)
port map (
ADR0 => b_reg_0_3_4316,
ADR1 => b_reg(9),
ADR2 => a_reg(9),
ADR3 => ab_xor_8_0,
O => N474
);
Sh9_f5_G : X_LUT4
generic map(
INIT => X"74B8",
LOC => "SLICE_X15Y15"
)
port map (
ADR0 => a_reg(6),
ADR1 => b_reg_0_3_4316,
ADR2 => ab_xor_7_0,
ADR3 => b_reg(6),
O => N475
);
b_reg_mux0000_0_F : X_LUT4
generic map(
INIT => X"444E",
LOC => "SLICE_X14Y15"
)
port map (
ADR0 => state_FSM_FFd2_4312,
ADR1 => b_reg(0),
ADR2 => Madd_b_pre_cy_0_Q,
ADR3 => state_FSM_FFd1_4311,
O => N524
);
b_reg_mux0000_0_G : X_LUT4
generic map(
INIT => X"EE4E",
LOC => "SLICE_X14Y15"
)
port map (
ADR0 => state_FSM_FFd2_4312,
ADR1 => b_reg(0),
ADR2 => Madd_b_pre_cy_0_Q,
ADR3 => state_FSM_FFd1_4311,
O => N525
);
b_reg_0_1 : X_FF
generic map(
LOC => "SLICE_X14Y15",
INIT => '0'
)
port map (
I => b_reg_0_1_DXMUX_9538,
CE => VCC,
CLK => b_reg_0_1_CLKINV_9521,
SET => GND,
RST => b_reg_0_1_FFX_RSTAND_9543,
O => b_reg_0_1_4382
);
b_reg_0_1_FFX_RSTAND : X_BUF
generic map(
LOC => "SLICE_X14Y15",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => b_reg_0_1_FFX_RSTAND_9543
);
Mmux_hex_digit_i_mux0001_4 : X_LUT4
generic map(
INIT => X"FC30",
LOC => "SLICE_X28Y15"
)
port map (
ADR0 => VCC,
ADR1 => LED_flash_cnt(8),
ADR2 => b_reg(12),
ADR3 => b_reg(8),
O => Mmux_hex_digit_i_mux0001_4_9562
);
Mmux_hex_digit_i_mux0001_3 : X_LUT4
generic map(
INIT => X"E2E2",
LOC => "SLICE_X28Y15"
)
port map (
ADR0 => b_reg(4),
ADR1 => LED_flash_cnt(8),
ADR2 => b_reg(0),
ADR3 => VCC,
O => Mmux_hex_digit_i_mux0001_3_9570
);
hex_digit_i_0 : X_FF
generic map(
LOC => "SLICE_X28Y15",
INIT => '0'
)
port map (
I => hex_digit_i_0_DXMUX_9574,
CE => VCC,
CLK => hex_digit_i_0_CLKINV_9555,
SET => GND,
RST => hex_digit_i_0_FFX_RSTAND_9579,
O => hex_digit_i(0)
);
hex_digit_i_0_FFX_RSTAND : X_BUF
generic map(
LOC => "SLICE_X28Y15",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => hex_digit_i_0_FFX_RSTAND_9579
);
b_reg_mux0000_11_10_SW0_F : X_LUT4
generic map(
INIT => X"FAD8",
LOC => "SLICE_X12Y11"
)
port map (
ADR0 => state_FSM_FFd2_4312,
ADR1 => Madd_b_pre_cy_6_Q,
ADR2 => b_reg(11),
ADR3 => swtch_led_7_OBUF_4260,
O => N436
);
b_reg_mux0000_11_10_SW0_G : X_LUT4
generic map(
INIT => X"3300",
LOC => "SLICE_X12Y11"
)
port map (
ADR0 => VCC,
ADR1 => state_FSM_FFd2_4312,
ADR2 => VCC,
ADR3 => b_reg(11),
O => N437
);
b_reg_mux0000_11_10_SW1_F : X_LUT4
generic map(
INIT => X"FCAC",
LOC => "SLICE_X13Y11"
)
port map (
ADR0 => swtch_led_7_OBUF_4260,
ADR1 => b_reg(11),
ADR2 => state_FSM_FFd2_4312,
ADR3 => Madd_b_pre_cy_6_Q,
O => N438
);
b_reg_mux0000_11_10_SW1_G : X_LUT4
generic map(
INIT => X"FAFA",
LOC => "SLICE_X13Y11"
)
port map (
ADR0 => b_reg(11),
ADR1 => VCC,
ADR2 => state_FSM_FFd2_4312,
ADR3 => VCC,
O => N439
);
i_cnt_mux0001_0_562 : X_LUT4
generic map(
INIT => X"FCCC",
LOC => "SLICE_X19Y14"
)
port map (
ADR0 => VCC,
ADR1 => i_cnt(3),
ADR2 => state_FSM_FFd1_4311,
ADR3 => i_cnt_mux0001_0_25_0,
O => i_cnt_mux0001_0_561_9649
);
i_cnt_mux0001_0_561 : X_LUT4
generic map(
INIT => X"B080",
LOC => "SLICE_X19Y14"
)
port map (
ADR0 => N514_0,
ADR1 => i_cnt(3),
ADR2 => state_FSM_FFd1_4311,
ADR3 => i_cnt_mux0001_0_25_0,
O => i_cnt_mux0001_0_56
);
i_cnt_3 : X_FF
generic map(
LOC => "SLICE_X19Y14",
INIT => '0'
)
port map (
I => i_cnt_3_DXMUX_9660,
CE => VCC,
CLK => i_cnt_3_CLKINV_9642,
SET => GND,
RST => i_cnt_3_FFX_RSTAND_9665,
O => i_cnt(3)
);
i_cnt_3_FFX_RSTAND : X_BUF
generic map(
LOC => "SLICE_X19Y14",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => i_cnt_3_FFX_RSTAND_9665
);
Mmux_hex_digit_i_mux0001_41 : X_LUT4
generic map(
INIT => X"CCAA",
LOC => "SLICE_X27Y12"
)
port map (
ADR0 => b_reg(13),
ADR1 => b_reg(9),
ADR2 => VCC,
ADR3 => LED_flash_cnt(8),
O => Mmux_hex_digit_i_mux0001_41_9684
);
Mmux_hex_digit_i_mux0001_31 : X_LUT4
generic map(
INIT => X"F0AA",
LOC => "SLICE_X27Y12"
)
port map (
ADR0 => b_reg(5),
ADR1 => VCC,
ADR2 => b_reg(1),
ADR3 => LED_flash_cnt(8),
O => Mmux_hex_digit_i_mux0001_31_9692
);
hex_digit_i_1 : X_FF
generic map(
LOC => "SLICE_X27Y12",
INIT => '0'
)
port map (
I => hex_digit_i_1_DXMUX_9696,
CE => VCC,
CLK => hex_digit_i_1_CLKINV_9677,
SET => GND,
RST => hex_digit_i_1_FFX_RSTAND_9701,
O => hex_digit_i(1)
);
hex_digit_i_1_FFX_RSTAND : X_BUF
generic map(
LOC => "SLICE_X27Y12",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => hex_digit_i_1_FFX_RSTAND_9701
);
Mmux_hex_digit_i_mux0001_42 : X_LUT4
generic map(
INIT => X"FA50",
LOC => "SLICE_X27Y13"
)
port map (
ADR0 => LED_flash_cnt(8),
ADR1 => VCC,
ADR2 => b_reg(14),
ADR3 => b_reg(10),
O => Mmux_hex_digit_i_mux0001_42_9720
);
Mmux_hex_digit_i_mux0001_32 : X_LUT4
generic map(
INIT => X"AAF0",
LOC => "SLICE_X27Y13"
)
port map (
ADR0 => b_reg(2),
ADR1 => VCC,
ADR2 => b_reg(6),
ADR3 => LED_flash_cnt(8),
O => Mmux_hex_digit_i_mux0001_32_9728
);
hex_digit_i_2 : X_FF
generic map(
LOC => "SLICE_X27Y13",
INIT => '0'
)
port map (
I => hex_digit_i_2_DXMUX_9732,
CE => VCC,
CLK => hex_digit_i_2_CLKINV_9713,
SET => GND,
RST => hex_digit_i_2_FFX_RSTAND_9737,
O => hex_digit_i(2)
);
hex_digit_i_2_FFX_RSTAND : X_BUF
generic map(
LOC => "SLICE_X27Y13",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => hex_digit_i_2_FFX_RSTAND_9737
);
Sh1222 : X_LUT4
generic map(
INIT => X"C5A3",
LOC => "SLICE_X22Y28"
)
port map (
ADR0 => a(25),
ADR1 => a(26),
ADR2 => N211_0,
ADR3 => Mxor_ba_xor_Result_25_1_SW1_O,
O => Sh1222_10228
);
Mxor_ba_xor_Result_11_1_SW1 : X_LUT4
generic map(
INIT => X"A0AF",
LOC => "SLICE_X18Y13"
)
port map (
ADR0 => b_reg(10),
ADR1 => VCC,
ADR2 => a(0),
ADR3 => b_reg(11),
O => Mxor_ba_xor_Result_11_1_SW1_O_pack_1
);
Sh1072 : X_LUT4
generic map(
INIT => X"8BD1",
LOC => "SLICE_X18Y13"
)
port map (
ADR0 => N251_0,
ADR1 => a(11),
ADR2 => Mxor_ba_xor_Result_11_1_SW1_O,
ADR3 => a(10),
O => Sh1072_10252
);
Mxor_ba_xor_Result_19_1_SW1 : X_LUT4
generic map(
INIT => X"A0F5",
LOC => "SLICE_X22Y24"
)
port map (
ADR0 => a(0),
ADR1 => VCC,
ADR2 => b_reg(18),
ADR3 => b_reg(19),
O => Mxor_ba_xor_Result_19_1_SW1_O_pack_1
);
Sh1152 : X_LUT4
generic map(
INIT => X"8BD1",
LOC => "SLICE_X22Y24"
)
port map (
ADR0 => a(19),
ADR1 => N205_0,
ADR2 => a(18),
ADR3 => Mxor_ba_xor_Result_19_1_SW1_O,
O => Sh1152_10276
);
Mxor_ba_xor_Result_27_1_SW1 : X_LUT4
generic map(
INIT => X"88BB",
LOC => "SLICE_X22Y31"
)
port map (
ADR0 => b_reg(26),
ADR1 => a(0),
ADR2 => VCC,
ADR3 => b_reg(27),
O => N200_pack_1
);
Sh1232 : X_LUT4
generic map(
INIT => X"C5A3",
LOC => "SLICE_X22Y31"
)
port map (
ADR0 => a(26),
ADR1 => a(27),
ADR2 => N199_0,
ADR3 => N200,
O => Sh1232_10300
);
Mxor_ba_xor_Result_21_1_SW1 : X_LUT4
generic map(
INIT => X"AF05",
LOC => "SLICE_X18Y33"
)
port map (
ADR0 => a(0),
ADR1 => VCC,
ADR2 => b_reg(22),
ADR3 => b_reg(21),
O => Mxor_ba_xor_Result_21_1_SW1_O_pack_1
);
Sh1182 : X_LUT4
generic map(
INIT => X"D81B",
LOC => "SLICE_X18Y33"
)
port map (
ADR0 => a(21),
ADR1 => N214_0,
ADR2 => Mxor_ba_xor_Result_21_1_SW1_O,
ADR3 => a(22),
O => Sh1182_10324
);
Mxor_ba_xor_Result_29_1_SW1 : X_LUT4
generic map(
INIT => X"88DD",
LOC => "SLICE_X20Y31"
)
port map (
ADR0 => a(0),
ADR1 => b_reg(29),
ADR2 => VCC,
ADR3 => b_reg(30),
O => Mxor_ba_xor_Result_29_1_SW1_O_pack_1
);
Sh1262 : X_LUT4
generic map(
INIT => X"8DB1",
LOC => "SLICE_X20Y31"
)
port map (
ADR0 => a(30),
ADR1 => N208_0,
ADR2 => Mxor_ba_xor_Result_29_1_SW1_O,
ADR3 => a(29),
O => Sh1262_10348
);
Sh982 : X_LUT4
generic map(
INIT => X"B1E4",
LOC => "SLICE_X26Y17"
)
port map (
ADR0 => a(0),
ADR1 => b_reg(2),
ADR2 => b_reg(1),
ADR3 => a(2),
O => Sh982_pack_1
);
Sh1343 : X_LUT4
generic map(
INIT => X"5044",
LOC => "SLICE_X26Y17"
)
port map (
ADR0 => a(3),
ADR1 => Sh982_4493,
ADR2 => Sh962_0,
ADR3 => a(1),
O => Sh13016
);
Mxor_ba_xor_Result_23_1_SW1 : X_LUT4
generic map(
INIT => X"F033",
LOC => "SLICE_X18Y28"
)
port map (
ADR0 => VCC,
ADR1 => b_reg(23),
ADR2 => b_reg(22),
ADR3 => a(0),
O => Mxor_ba_xor_Result_23_1_SW1_O_pack_1
);
Sh1192 : X_LUT4
generic map(
INIT => X"8BD1",
LOC => "SLICE_X18Y28"
)
port map (
ADR0 => a(23),
ADR1 => N202_0,
ADR2 => a(22),
ADR3 => Mxor_ba_xor_Result_23_1_SW1_O,
O => Sh1192_10396
);
Mxor_ba_xor_Result_31_1_SW1 : X_LUT4
generic map(
INIT => X"AA33",
LOC => "SLICE_X21Y31"
)
port map (
ADR0 => b_reg(30),
ADR1 => b_reg(31),
ADR2 => VCC,
ADR3 => a(0),
O => N197_pack_1
);
Sh1272 : X_LUT4
generic map(
INIT => X"8DB1",
LOC => "SLICE_X21Y31"
)
port map (
ADR0 => N196_0,
ADR1 => a(31),
ADR2 => a(30),
ADR3 => N197,
O => Sh1272_10420
);
Sh12932 : X_LUT4
generic map(
INIT => X"AFAC",
LOC => "SLICE_X20Y14"
)
port map (
ADR0 => Sh1297_0,
ADR1 => Sh12913_0,
ADR2 => a(2),
ADR3 => Sh12916_0,
O => Sh129_pack_1
);
Sh1611 : X_LUT4
generic map(
INIT => X"CFC0",
LOC => "SLICE_X20Y14"
)
port map (
ADR0 => VCC,
ADR1 => Sh145,
ADR2 => a(4),
ADR3 => Sh129,
O => Sh161
);
Sh13831 : X_LUT4
generic map(
INIT => X"E4E4",
LOC => "SLICE_X27Y18"
)
port map (
ADR0 => a(2),
ADR1 => Sh13820,
ADR2 => Sh13420,
ADR3 => VCC,
O => Sh138_pack_1
);
Sh1701 : X_LUT4
generic map(
INIT => X"FA50",
LOC => "SLICE_X27Y18"
)
port map (
ADR0 => a(4),
ADR1 => VCC,
ADR2 => Sh138,
ADR3 => Sh154_0,
O => Sh170
);
Sh107_f51 : X_LUT4
generic map(
INIT => X"ACAC",
LOC => "SLICE_X24Y22"
)
port map (
ADR0 => Sh1052_0,
ADR1 => Sh1072_0,
ADR2 => a(1),
ADR3 => VCC,
O => Sh107_pack_1
);
Sh1437 : X_LUT4
generic map(
INIT => X"AFA0",
LOC => "SLICE_X24Y22"
)
port map (
ADR0 => Sh99_0,
ADR1 => VCC,
ADR2 => a(3),
ADR3 => Sh107,
O => Sh1437_10492
);
Sh15532 : X_LUT4
generic map(
INIT => X"FE54",
LOC => "SLICE_X27Y24"
)
port map (
ADR0 => a(2),
ADR1 => Sh15513_0,
ADR2 => Sh15516_0,
ADR3 => Sh1557,
O => Sh155_pack_1
);
Sh1711 : X_LUT4
generic map(
INIT => X"E4E4",
LOC => "SLICE_X27Y24"
)
port map (
ADR0 => a(4),
ADR1 => Sh139,
ADR2 => Sh155,
ADR3 => VCC,
O => Sh171
);
Sh15632 : X_LUT4
generic map(
INIT => X"B8B8",
LOC => "SLICE_X23Y19"
)
port map (
ADR0 => Sh1567_0,
ADR1 => a(2),
ADR2 => Sh1287_0,
ADR3 => VCC,
O => Sh156_pack_1
);
Sh1721 : X_LUT4
generic map(
INIT => X"FA0A",
LOC => "SLICE_X23Y19"
)
port map (
ADR0 => Sh140,
ADR1 => VCC,
ADR2 => a(4),
ADR3 => Sh156,
O => Sh172
);
Sh13232 : X_LUT4
generic map(
INIT => X"FCAA",
LOC => "SLICE_X23Y21"
)
port map (
ADR0 => Sh13220_0,
ADR1 => Sh12816_0,
ADR2 => Sh12813_0,
ADR3 => a(2),
O => Sh132_pack_1
);
Sh1801 : X_LUT4
generic map(
INIT => X"EE44",
LOC => "SLICE_X23Y21"
)
port map (
ADR0 => a(4),
ADR1 => Sh148_0,
ADR2 => VCC,
ADR3 => Sh132,
O => Sh180
);
Sh14932 : X_LUT4
generic map(
INIT => X"DD88",
LOC => "SLICE_X23Y15"
)
port map (
ADR0 => a(2),
ADR1 => Sh1497_0,
ADR2 => VCC,
ADR3 => Sh1537_0,
O => Sh149_pack_1
);
Sh1651 : X_LUT4
generic map(
INIT => X"EE44",
LOC => "SLICE_X23Y15"
)
port map (
ADR0 => a(4),
ADR1 => Sh133,
ADR2 => VCC,
ADR3 => Sh149,
O => Sh165
);
Sh15732 : X_LUT4
generic map(
INIT => X"FC0C",
LOC => "SLICE_X20Y16"
)
port map (
ADR0 => VCC,
ADR1 => Sh1297_0,
ADR2 => a(2),
ADR3 => Sh1577_0,
O => Sh157_pack_1
);
Sh1731 : X_LUT4
generic map(
INIT => X"FC0C",
LOC => "SLICE_X20Y16"
)
port map (
ADR0 => VCC,
ADR1 => Sh141,
ADR2 => a(4),
ADR3 => Sh157,
O => Sh173
);
Sh13432 : X_LUT4
generic map(
INIT => X"EEE4",
LOC => "SLICE_X26Y15"
)
port map (
ADR0 => a(2),
ADR1 => Sh13420,
ADR2 => Sh13013_0,
ADR3 => Sh13016_0,
O => Sh134_pack_1
);
Sh1661 : X_LUT4
generic map(
INIT => X"B8B8",
LOC => "SLICE_X26Y15"
)
port map (
ADR0 => Sh150_0,
ADR1 => a(4),
ADR2 => Sh134,
ADR3 => VCC,
O => Sh166
);
Sh15832 : X_LUT4
generic map(
INIT => X"DDD8",
LOC => "SLICE_X26Y22"
)
port map (
ADR0 => a(2),
ADR1 => Sh1587,
ADR2 => Sh15816_0,
ADR3 => Sh15813_0,
O => Sh158_pack_1
);
Sh1741 : X_LUT4
generic map(
INIT => X"FC0C",
LOC => "SLICE_X26Y22"
)
port map (
ADR0 => VCC,
ADR1 => Sh142,
ADR2 => a(4),
ADR3 => Sh158,
O => Sh174
);
Sh15132 : X_LUT4
generic map(
INIT => X"CCFA",
LOC => "SLICE_X22Y21"
)
port map (
ADR0 => Sh15113_0,
ADR1 => Sh1517,
ADR2 => Sh15116_0,
ADR3 => a(2),
O => Sh151_pack_1
);
Sh1671 : X_LUT4
generic map(
INIT => X"F0AA",
LOC => "SLICE_X22Y21"
)
port map (
ADR0 => Sh135,
ADR1 => VCC,
ADR2 => Sh151,
ADR3 => a(4),
O => Sh167
);
Sh15232 : X_LUT4
generic map(
INIT => X"CFC0",
LOC => "SLICE_X22Y17"
)
port map (
ADR0 => VCC,
ADR1 => Sh1527_0,
ADR2 => a(2),
ADR3 => Sh1567_0,
O => Sh152_pack_1
);
Sh1681 : X_LUT4
generic map(
INIT => X"F3C0",
LOC => "SLICE_X22Y17"
)
port map (
ADR0 => VCC,
ADR1 => a(4),
ADR2 => Sh152,
ADR3 => Sh136,
O => Sh168
);
Sh12832 : X_LUT4
generic map(
INIT => X"FE54",
LOC => "SLICE_X22Y20"
)
port map (
ADR0 => a(2),
ADR1 => Sh12813_0,
ADR2 => Sh12816_0,
ADR3 => Sh1287_0,
O => Sh128_pack_1
);
Sh1761 : X_LUT4
generic map(
INIT => X"FC30",
LOC => "SLICE_X22Y20"
)
port map (
ADR0 => VCC,
ADR1 => a(4),
ADR2 => Sh144_0,
ADR3 => Sh128,
O => Sh176
);
Sh15332 : X_LUT4
generic map(
INIT => X"E2E2",
LOC => "SLICE_X23Y16"
)
port map (
ADR0 => Sh1577_0,
ADR1 => a(2),
ADR2 => Sh1537_0,
ADR3 => VCC,
O => Sh153_pack_1
);
Sh1691 : X_LUT4
generic map(
INIT => X"F5A0",
LOC => "SLICE_X23Y16"
)
port map (
ADR0 => a(4),
ADR1 => VCC,
ADR2 => Sh153,
ADR3 => Sh137,
O => Sh169
);
Sh13132 : X_LUT4
generic map(
INIT => X"EEE2",
LOC => "SLICE_X25Y19"
)
port map (
ADR0 => Sh13120,
ADR1 => a(2),
ADR2 => Sh1310_0,
ADR3 => Sh1313,
O => Sh131_pack_1
);
Sh1791 : X_LUT4
generic map(
INIT => X"FD0D",
LOC => "SLICE_X25Y19"
)
port map (
ADR0 => N249_0,
ADR1 => Sh14712,
ADR2 => a(4),
ADR3 => Sh131,
O => Sh179
);
b_reg_mux0000_2_62 : X_LUT4
generic map(
INIT => X"FA50",
LOC => "SLICE_X12Y10"
)
port map (
ADR0 => b_2_Q,
ADR1 => VCC,
ADR2 => N291,
ADR3 => N292,
O => b_reg_mux0000_2_Q
);
b_reg_2_1 : X_FF
generic map(
LOC => "SLICE_X12Y10",
INIT => '0'
)
port map (
I => b_reg_2_1_DYMUX_10800,
CE => VCC,
CLK => b_reg_2_1_CLKINV_10790,
SET => GND,
RST => b_reg_2_1_FFY_RSTAND_10805,
O => b_reg_2_1_4381
);
b_reg_2_1_FFY_RSTAND : X_BUF
generic map(
LOC => "SLICE_X12Y10",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => b_reg_2_1_FFY_RSTAND_10805
);
b_reg_mux0000_3_38 : X_LUT4
generic map(
INIT => X"F5A0",
LOC => "SLICE_X3Y21"
)
port map (
ADR0 => b_3_Q,
ADR1 => VCC,
ADR2 => N282,
ADR3 => N281,
O => b_reg_mux0000_3_Q
);
b_reg_3_1 : X_FF
generic map(
LOC => "SLICE_X3Y21",
INIT => '0'
)
port map (
I => b_reg_3_1_DYMUX_10824,
CE => VCC,
CLK => b_reg_3_1_CLKINV_10814,
SET => GND,
RST => b_reg_3_1_FFY_RSTAND_10829,
O => b_reg_3_1_4597
);
b_reg_3_1_FFY_RSTAND : X_BUF
generic map(
LOC => "SLICE_X3Y21",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => b_reg_3_1_FFY_RSTAND_10829
);
b_reg_mux0000_4_57 : X_LUT4
generic map(
INIT => X"F0CC",
LOC => "SLICE_X3Y19"
)
port map (
ADR0 => VCC,
ADR1 => N278,
ADR2 => N279,
ADR3 => b_4_Q,
O => b_reg_mux0000_4_Q
);
b_reg_4_1 : X_FF
generic map(
LOC => "SLICE_X3Y19",
INIT => '0'
)
port map (
I => b_reg_4_1_DYMUX_10848,
CE => VCC,
CLK => b_reg_4_1_CLKINV_10838,
SET => GND,
RST => b_reg_4_1_FFY_RSTAND_10853,
O => b_reg_4_1_4383
);
b_reg_4_1_FFY_RSTAND : X_BUF
generic map(
LOC => "SLICE_X3Y19",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => b_reg_4_1_FFY_RSTAND_10853
);
Mrom_AN_mux000111 : X_LUT4
generic map(
INIT => X"33FF",
LOC => "SLICE_X30Y14"
)
port map (
ADR0 => VCC,
ADR1 => LED_flash_cnt(8),
ADR2 => VCC,
ADR3 => LED_flash_cnt(9),
O => Mrom_AN_mux0001
);
AN_0 : X_FF
generic map(
LOC => "SLICE_X30Y14",
INIT => '1'
)
port map (
I => AN_1_DYMUX_10874,
CE => VCC,
CLK => AN_1_CLKINV_10863,
SET => AN_1_SRINV_10864,
RST => GND,
O => AN_0_4261
);
Mrom_AN_mux0001111 : X_LUT4
generic map(
INIT => X"CCFF",
LOC => "SLICE_X30Y14"
)
port map (
ADR0 => VCC,
ADR1 => LED_flash_cnt(8),
ADR2 => VCC,
ADR3 => LED_flash_cnt(9),
O => Mrom_AN_mux00011
);
AN_1 : X_FF
generic map(
LOC => "SLICE_X30Y14",
INIT => '1'
)
port map (
I => AN_1_DXMUX_10889,
CE => VCC,
CLK => AN_1_CLKINV_10863,
SET => AN_1_SRINV_10864,
RST => GND,
O => AN_1_4262
);
Mrom_AN_mux000121 : X_LUT4
generic map(
INIT => X"DDDD",
LOC => "SLICE_X30Y12"
)
port map (
ADR0 => LED_flash_cnt(8),
ADR1 => LED_flash_cnt(9),
ADR2 => VCC,
ADR3 => VCC,
O => Mrom_AN_mux00012
);
AN_2 : X_FF
generic map(
LOC => "SLICE_X30Y12",
INIT => '1'
)
port map (
I => AN_3_DYMUX_10914,
CE => VCC,
CLK => AN_3_CLKINV_10903,
SET => AN_3_SRINV_10904,
RST => GND,
O => AN_2_4263
);
Mrom_AN_mux000131 : X_LUT4
generic map(
INIT => X"EEEE",
LOC => "SLICE_X30Y12"
)
port map (
ADR0 => LED_flash_cnt(8),
ADR1 => LED_flash_cnt(9),
ADR2 => VCC,
ADR3 => VCC,
O => Mrom_AN_mux00013
);
AN_3 : X_FF
generic map(
LOC => "SLICE_X30Y12",
INIT => '1'
)
port map (
I => AN_3_DXMUX_10929,
CE => VCC,
CLK => AN_3_CLKINV_10903,
SET => AN_3_SRINV_10904,
RST => GND,
O => AN_3_4264
);
a_reg_0 : X_FF
generic map(
LOC => "SLICE_X13Y33",
INIT => '0'
)
port map (
I => a_reg_1_DYMUX_10956,
CE => VCC,
CLK => a_reg_1_CLKINV_10947,
SET => GND,
RST => a_reg_1_SRINV_10948,
O => a_reg(0)
);
a_reg_mux0000_0_1 : X_LUT4
generic map(
INIT => X"8F80",
LOC => "SLICE_X13Y33"
)
port map (
ADR0 => state_FSM_FFd1_4311,
ADR1 => a(0),
ADR2 => state_FSM_FFd2_4312,
ADR3 => a_reg(0),
O => a_reg_mux0000(0)
);
a_reg_mux0000_1_1 : X_LUT4
generic map(
INIT => X"A0CC",
LOC => "SLICE_X13Y33"
)
port map (
ADR0 => a(1),
ADR1 => a_reg(1),
ADR2 => state_FSM_FFd1_4311,
ADR3 => state_FSM_FFd2_4312,
O => a_reg_mux0000(1)
);
a_reg_1 : X_FF
generic map(
LOC => "SLICE_X13Y33",
INIT => '0'
)
port map (
I => a_reg_1_DXMUX_10970,
CE => VCC,
CLK => a_reg_1_CLKINV_10947,
SET => GND,
RST => a_reg_1_SRINV_10948,
O => a_reg(1)
);
a_reg_2 : X_FF
generic map(
LOC => "SLICE_X2Y21",
INIT => '0'
)
port map (
I => a_reg_3_DYMUX_10998,
CE => VCC,
CLK => a_reg_3_CLKINV_10989,
SET => GND,
RST => a_reg_3_SRINV_10990,
O => a_reg(2)
);
a_reg_mux0000_2_1 : X_LUT4
generic map(
INIT => X"D850",
LOC => "SLICE_X2Y21"
)
port map (
ADR0 => state_FSM_FFd2_4312,
ADR1 => a(2),
ADR2 => a_reg(2),
ADR3 => state_FSM_FFd1_4311,
O => a_reg_mux0000(2)
);
a_reg_mux0000_3_1 : X_LUT4
generic map(
INIT => X"ACFC",
LOC => "SLICE_X2Y21"
)
port map (
ADR0 => a(3),
ADR1 => a_reg(3),
ADR2 => state_FSM_FFd2_4312,
ADR3 => state_FSM_FFd1_4311,
O => a_reg_mux0000(3)
);
a_reg_3 : X_FF
generic map(
LOC => "SLICE_X2Y21",
INIT => '0'
)
port map (
I => a_reg_3_DXMUX_11012,
CE => VCC,
CLK => a_reg_3_CLKINV_10989,
SET => GND,
RST => a_reg_3_SRINV_10990,
O => a_reg(3)
);
a_reg_4 : X_FF
generic map(
LOC => "SLICE_X15Y18",
INIT => '0'
)
port map (
I => a_reg_5_DYMUX_11040,
CE => VCC,
CLK => a_reg_5_CLKINV_11031,
SET => GND,
RST => a_reg_5_SRINV_11032,
O => a_reg(4)
);
a_reg_mux0000_4_1 : X_LUT4
generic map(
INIT => X"A0CC",
LOC => "SLICE_X15Y18"
)
port map (
ADR0 => state_FSM_FFd1_4311,
ADR1 => a_reg(4),
ADR2 => a(4),
ADR3 => state_FSM_FFd2_4312,
O => a_reg_mux0000(4)
);
a_reg_mux0000_5_1 : X_LUT4
generic map(
INIT => X"E222",
LOC => "SLICE_X15Y18"
)
port map (
ADR0 => a_reg(5),
ADR1 => state_FSM_FFd2_4312,
ADR2 => state_FSM_FFd1_4311,
ADR3 => a(5),
O => a_reg_mux0000(5)
);
a_reg_5 : X_FF
generic map(
LOC => "SLICE_X15Y18",
INIT => '0'
)
port map (
I => a_reg_5_DXMUX_11054,
CE => VCC,
CLK => a_reg_5_CLKINV_11031,
SET => GND,
RST => a_reg_5_SRINV_11032,
O => a_reg(5)
);
a_reg_6 : X_FF
generic map(
LOC => "SLICE_X17Y15",
INIT => '0'
)
port map (
I => a_reg_7_DYMUX_11082,
CE => VCC,
CLK => a_reg_7_CLKINV_11073,
SET => GND,
RST => a_reg_7_SRINV_11074,
O => a_reg(6)
);
a_reg_mux0000_6_1 : X_LUT4
generic map(
INIT => X"B8FC",
LOC => "SLICE_X17Y15"
)
port map (
ADR0 => a(6),
ADR1 => state_FSM_FFd2_4312,
ADR2 => a_reg(6),
ADR3 => state_FSM_FFd1_4311,
O => a_reg_mux0000(6)
);
a_reg_mux0000_7_1 : X_LUT4
generic map(
INIT => X"FC5C",
LOC => "SLICE_X17Y15"
)
port map (
ADR0 => state_FSM_FFd1_4311,
ADR1 => a_reg(7),
ADR2 => state_FSM_FFd2_4312,
ADR3 => a(7),
O => a_reg_mux0000(7)
);
a_reg_7 : X_FF
generic map(
LOC => "SLICE_X17Y15",
INIT => '0'
)
port map (
I => a_reg_7_DXMUX_11096,
CE => VCC,
CLK => a_reg_7_CLKINV_11073,
SET => GND,
RST => a_reg_7_SRINV_11074,
O => a_reg(7)
);
a_reg_8 : X_FF
generic map(
LOC => "SLICE_X16Y12",
INIT => '0'
)
port map (
I => a_reg_9_DYMUX_11124,
CE => VCC,
CLK => a_reg_9_CLKINV_11115,
SET => GND,
RST => a_reg_9_SRINV_11116,
O => a_reg(8)
);
a_reg_mux0000_8_1 : X_LUT4
generic map(
INIT => X"AC0C",
LOC => "SLICE_X16Y12"
)
port map (
ADR0 => a(8),
ADR1 => a_reg(8),
ADR2 => state_FSM_FFd2_4312,
ADR3 => state_FSM_FFd1_4311,
O => a_reg_mux0000(8)
);
a_reg_mux0000_9_1 : X_LUT4
generic map(
INIT => X"D850",
LOC => "SLICE_X16Y12"
)
port map (
ADR0 => state_FSM_FFd2_4312,
ADR1 => a(9),
ADR2 => a_reg(9),
ADR3 => state_FSM_FFd1_4311,
O => a_reg_mux0000(9)
);
a_reg_9 : X_FF
generic map(
LOC => "SLICE_X16Y12",
INIT => '0'
)
port map (
I => a_reg_9_DXMUX_11138,
CE => VCC,
CLK => a_reg_9_CLKINV_11115,
SET => GND,
RST => a_reg_9_SRINV_11116,
O => a_reg(9)
);
b_reg_mux0000_6_57 : X_LUT4
generic map(
INIT => X"EE44",
LOC => "SLICE_X12Y12"
)
port map (
ADR0 => b_6_Q,
ADR1 => N272,
ADR2 => VCC,
ADR3 => N273,
O => b_reg_mux0000_6_Q
);
b_reg_6 : X_FF
generic map(
LOC => "SLICE_X12Y12",
INIT => '0'
)
port map (
I => b_reg_7_DYMUX_11165,
CE => VCC,
CLK => b_reg_7_CLKINV_11155,
SET => GND,
RST => b_reg_7_SRINV_11156,
O => b_reg(6)
);
b_reg_mux0000_7_38 : X_LUT4
generic map(
INIT => X"E4E4",
LOC => "SLICE_X12Y12"
)
port map (
ADR0 => b_7_Q,
ADR1 => N269,
ADR2 => N270,
ADR3 => VCC,
O => b_reg_mux0000_7_Q
);
b_reg_7 : X_FF
generic map(
LOC => "SLICE_X12Y12",
INIT => '0'
)
port map (
I => b_reg_7_DXMUX_11180,
CE => VCC,
CLK => b_reg_7_CLKINV_11155,
SET => GND,
RST => b_reg_7_SRINV_11156,
O => b_reg(7)
);
i_cnt_mux0001_3_1 : X_LUT4
generic map(
INIT => X"3CFC",
LOC => "SLICE_X12Y32"
)
port map (
ADR0 => VCC,
ADR1 => state_FSM_FFd2_4312,
ADR2 => i_cnt(0),
ADR3 => state_FSM_FFd1_4311,
O => i_cnt_mux0001(3)
);
i_cnt_0 : X_FF
generic map(
LOC => "SLICE_X12Y32",
INIT => '1'
)
port map (
I => i_cnt_1_DYMUX_11208,
CE => VCC,
CLK => i_cnt_1_CLKINV_11198,
SET => i_cnt_1_SRINV_11199,
RST => GND,
O => i_cnt(0)
);
i_cnt_mux0001_2_1 : X_LUT4
generic map(
INIT => X"6C44",
LOC => "SLICE_X12Y32"
)
port map (
ADR0 => state_FSM_FFd2_4312,
ADR1 => i_cnt(1),
ADR2 => i_cnt(0),
ADR3 => state_FSM_FFd1_4311,
O => i_cnt_mux0001(2)
);
i_cnt_1 : X_FF
generic map(
LOC => "SLICE_X12Y32",
INIT => '0'
)
port map (
I => i_cnt_1_DXMUX_11221,
CE => VCC,
CLK => i_cnt_1_CLKINV_11198,
SET => GND,
RST => i_cnt_1_SRINV_11199,
O => i_cnt(1)
);
a_reg_10 : X_FF
generic map(
LOC => "SLICE_X14Y13",
INIT => '0'
)
port map (
I => a_reg_11_DYMUX_11249,
CE => VCC,
CLK => a_reg_11_CLKINV_11240,
SET => GND,
RST => a_reg_11_SRINV_11241,
O => a_reg(10)
);
a_reg_mux0000_10_1 : X_LUT4
generic map(
INIT => X"CA0A",
LOC => "SLICE_X14Y13"
)
port map (
ADR0 => a_reg(10),
ADR1 => state_FSM_FFd1_4311,
ADR2 => state_FSM_FFd2_4312,
ADR3 => a(10),
O => a_reg_mux0000(10)
);
a_reg_mux0000_11_1 : X_LUT4
generic map(
INIT => X"BFB0",
LOC => "SLICE_X14Y13"
)
port map (
ADR0 => a(11),
ADR1 => state_FSM_FFd1_4311,
ADR2 => state_FSM_FFd2_4312,
ADR3 => a_reg(11),
O => a_reg_mux0000(11)
);
a_reg_11 : X_FF
generic map(
LOC => "SLICE_X14Y13",
INIT => '0'
)
port map (
I => a_reg_11_DXMUX_11263,
CE => VCC,
CLK => a_reg_11_CLKINV_11240,
SET => GND,
RST => a_reg_11_SRINV_11241,
O => a_reg(11)
);
a_reg_15 : X_FF
generic map(
LOC => "SLICE_X15Y22",
INIT => '0'
)
port map (
I => a_reg_15_DXMUX_11473,
CE => VCC,
CLK => a_reg_15_CLKINV_11450,
SET => GND,
RST => a_reg_15_SRINV_11451,
O => a_reg(15)
);
a_reg_24 : X_FF
generic map(
LOC => "SLICE_X17Y33",
INIT => '0'
)
port map (
I => a_reg_25_DYMUX_11501,
CE => VCC,
CLK => a_reg_25_CLKINV_11492,
SET => GND,
RST => a_reg_25_SRINV_11493,
O => a_reg(24)
);
a_reg_mux0000_25_1 : X_LUT4
generic map(
INIT => X"ACFC",
LOC => "SLICE_X17Y33"
)
port map (
ADR0 => a(25),
ADR1 => a_reg(25),
ADR2 => state_FSM_FFd2_4312,
ADR3 => state_FSM_FFd1_4311,
O => a_reg_mux0000(25)
);
a_reg_25 : X_FF
generic map(
LOC => "SLICE_X17Y33",
INIT => '0'
)
port map (
I => a_reg_25_DXMUX_11515,
CE => VCC,
CLK => a_reg_25_CLKINV_11492,
SET => GND,
RST => a_reg_25_SRINV_11493,
O => a_reg(25)
);
a_reg_16 : X_FF
generic map(
LOC => "SLICE_X13Y22",
INIT => '0'
)
port map (
I => a_reg_17_DYMUX_11543,
CE => VCC,
CLK => a_reg_17_CLKINV_11534,
SET => GND,
RST => a_reg_17_SRINV_11535,
O => a_reg(16)
);
a_reg_mux0000_16_1 : X_LUT4
generic map(
INIT => X"FC5C",
LOC => "SLICE_X13Y22"
)
port map (
ADR0 => state_FSM_FFd1_4311,
ADR1 => a_reg(16),
ADR2 => state_FSM_FFd2_4312,
ADR3 => a(16),
O => a_reg_mux0000(16)
);
a_reg_mux0000_17_1 : X_LUT4
generic map(
INIT => X"DFD0",
LOC => "SLICE_X13Y22"
)
port map (
ADR0 => state_FSM_FFd1_4311,
ADR1 => a(17),
ADR2 => state_FSM_FFd2_4312,
ADR3 => a_reg(17),
O => a_reg_mux0000(17)
);
a_reg_17 : X_FF
generic map(
LOC => "SLICE_X13Y22",
INIT => '0'
)
port map (
I => a_reg_17_DXMUX_11557,
CE => VCC,
CLK => a_reg_17_CLKINV_11534,
SET => GND,
RST => a_reg_17_SRINV_11535,
O => a_reg(17)
);
a_reg_26 : X_FF
generic map(
LOC => "SLICE_X18Y30",
INIT => '0'
)
port map (
I => a_reg_27_DYMUX_11585,
CE => VCC,
CLK => a_reg_27_CLKINV_11576,
SET => GND,
RST => a_reg_27_SRINV_11577,
O => a_reg(26)
);
a_reg_mux0000_26_1 : X_LUT4
generic map(
INIT => X"88F0",
LOC => "SLICE_X18Y30"
)
port map (
ADR0 => state_FSM_FFd1_4311,
ADR1 => a(26),
ADR2 => a_reg(26),
ADR3 => state_FSM_FFd2_4312,
O => a_reg_mux0000(26)
);
a_reg_mux0000_27_1 : X_LUT4
generic map(
INIT => X"F5CC",
LOC => "SLICE_X18Y30"
)
port map (
ADR0 => state_FSM_FFd1_4311,
ADR1 => a_reg(27),
ADR2 => a(27),
ADR3 => state_FSM_FFd2_4312,
O => a_reg_mux0000(27)
);
a_reg_27 : X_FF
generic map(
LOC => "SLICE_X18Y30",
INIT => '0'
)
port map (
I => a_reg_27_DXMUX_11599,
CE => VCC,
CLK => a_reg_27_CLKINV_11576,
SET => GND,
RST => a_reg_27_SRINV_11577,
O => a_reg(27)
);
a_reg_18 : X_FF
generic map(
LOC => "SLICE_X14Y25",
INIT => '0'
)
port map (
I => a_reg_19_DYMUX_11627,
CE => VCC,
CLK => a_reg_19_CLKINV_11618,
SET => GND,
RST => a_reg_19_SRINV_11619,
O => a_reg(18)
);
a_reg_mux0000_18_1 : X_LUT4
generic map(
INIT => X"88F0",
LOC => "SLICE_X14Y25"
)
port map (
ADR0 => a(18),
ADR1 => state_FSM_FFd1_4311,
ADR2 => a_reg(18),
ADR3 => state_FSM_FFd2_4312,
O => a_reg_mux0000(18)
);
a_reg_mux0000_19_1 : X_LUT4
generic map(
INIT => X"F7A2",
LOC => "SLICE_X14Y25"
)
port map (
ADR0 => state_FSM_FFd2_4312,
ADR1 => state_FSM_FFd1_4311,
ADR2 => a(19),
ADR3 => a_reg(19),
O => a_reg_mux0000(19)
);
a_reg_19 : X_FF
generic map(
LOC => "SLICE_X14Y25",
INIT => '0'
)
port map (
I => a_reg_19_DXMUX_11641,
CE => VCC,
CLK => a_reg_19_CLKINV_11618,
SET => GND,
RST => a_reg_19_SRINV_11619,
O => a_reg(19)
);
a_reg_28 : X_FF
generic map(
LOC => "SLICE_X17Y34",
INIT => '0'
)
port map (
I => a_reg_29_DYMUX_11669,
CE => VCC,
CLK => a_reg_29_CLKINV_11660,
SET => GND,
RST => a_reg_29_SRINV_11661,
O => a_reg(28)
);
a_reg_mux0000_28_1 : X_LUT4
generic map(
INIT => X"DF8A",
LOC => "SLICE_X17Y34"
)
port map (
ADR0 => state_FSM_FFd2_4312,
ADR1 => a(28),
ADR2 => state_FSM_FFd1_4311,
ADR3 => a_reg(28),
O => a_reg_mux0000(28)
);
a_reg_mux0000_29_1 : X_LUT4
generic map(
INIT => X"D580",
LOC => "SLICE_X17Y34"
)
port map (
ADR0 => state_FSM_FFd2_4312,
ADR1 => a(29),
ADR2 => state_FSM_FFd1_4311,
ADR3 => a_reg(29),
O => a_reg_mux0000(29)
);
a_reg_29 : X_FF
generic map(
LOC => "SLICE_X17Y34",
INIT => '0'
)
port map (
I => a_reg_29_DXMUX_11683,
CE => VCC,
CLK => a_reg_29_CLKINV_11660,
SET => GND,
RST => a_reg_29_SRINV_11661,
O => a_reg(29)
);
b_reg_mux0000_11_21 : X_LUT4
generic map(
INIT => X"CCAA",
LOC => "SLICE_X15Y11"
)
port map (
ADR0 => N266,
ADR1 => N267,
ADR2 => VCC,
ADR3 => b_11_Q,
O => b_reg_mux0000_11_Q
);
b_reg_11 : X_FF
generic map(
LOC => "SLICE_X15Y11",
INIT => '0'
)
port map (
I => b_reg_11_DYMUX_11706,
CE => VCC,
CLK => b_reg_11_CLKINV_11696,
SET => GND,
RST => b_reg_11_FFY_RSTAND_11711,
O => b_reg(11)
);
b_reg_11_FFY_RSTAND : X_BUF
generic map(
LOC => "SLICE_X15Y11",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => b_reg_11_FFY_RSTAND_11711
);
b_reg_20 : X_FF
generic map(
LOC => "SLICE_X19Y23",
INIT => '0'
)
port map (
I => b_reg_21_DYMUX_11734,
CE => VCC,
CLK => b_reg_21_CLKINV_11725,
SET => GND,
RST => b_reg_21_SRINV_11726,
O => b_reg(20)
);
b_reg_mux0000_20_1 : X_LUT4
generic map(
INIT => X"F5CC",
LOC => "SLICE_X19Y23"
)
port map (
ADR0 => state_FSM_FFd1_4311,
ADR1 => b_reg(20),
ADR2 => b_20_Q,
ADR3 => state_FSM_FFd2_4312,
O => b_reg_mux0000_20_Q
);
b_reg_mux0000_21_1 : X_LUT4
generic map(
INIT => X"EE4E",
LOC => "SLICE_X19Y23"
)
port map (
ADR0 => state_FSM_FFd2_4312,
ADR1 => b_reg(21),
ADR2 => state_FSM_FFd1_4311,
ADR3 => b_21_Q,
O => b_reg_mux0000_21_Q
);
b_reg_21 : X_FF
generic map(
LOC => "SLICE_X19Y23",
INIT => '0'
)
port map (
I => b_reg_21_DXMUX_11748,
CE => VCC,
CLK => b_reg_21_CLKINV_11725,
SET => GND,
RST => b_reg_21_SRINV_11726,
O => b_reg(21)
);
b_reg_12 : X_FF
generic map(
LOC => "SLICE_X18Y19",
INIT => '0'
)
port map (
I => b_reg_13_DYMUX_11776,
CE => VCC,
CLK => b_reg_13_CLKINV_11767,
SET => GND,
RST => b_reg_13_SRINV_11768,
O => b_reg(12)
);
b_reg_mux0000_12_1 : X_LUT4
generic map(
INIT => X"CAFA",
LOC => "SLICE_X18Y19"
)
port map (
ADR0 => b_reg(12),
ADR1 => b_12_Q,
ADR2 => state_FSM_FFd2_4312,
ADR3 => state_FSM_FFd1_4311,
O => b_reg_mux0000_12_Q
);
b_reg_mux0000_13_1 : X_LUT4
generic map(
INIT => X"FC74",
LOC => "SLICE_X18Y19"
)
port map (
ADR0 => state_FSM_FFd1_4311,
ADR1 => state_FSM_FFd2_4312,
ADR2 => b_reg(13),
ADR3 => b_13_Q,
O => b_reg_mux0000_13_Q
);
b_reg_13 : X_FF
generic map(
LOC => "SLICE_X18Y19",
INIT => '0'
)
port map (
I => b_reg_13_DXMUX_11790,
CE => VCC,
CLK => b_reg_13_CLKINV_11767,
SET => GND,
RST => b_reg_13_SRINV_11768,
O => b_reg(13)
);
b_reg_30 : X_FF
generic map(
LOC => "SLICE_X19Y26",
INIT => '0'
)
port map (
I => b_reg_31_DYMUX_11818,
CE => VCC,
CLK => b_reg_31_CLKINV_11809,
SET => GND,
RST => b_reg_31_SRINV_11810,
O => b_reg(30)
);
b_reg_mux0000_30_1 : X_LUT4
generic map(
INIT => X"E444",
LOC => "SLICE_X19Y26"
)
port map (
ADR0 => state_FSM_FFd2_4312,
ADR1 => b_reg(30),
ADR2 => b_30_Q,
ADR3 => state_FSM_FFd1_4311,
O => b_reg_mux0000_30_Q
);
b_reg_mux0000_31_1 : X_LUT4
generic map(
INIT => X"C0AA",
LOC => "SLICE_X19Y26"
)
port map (
ADR0 => b_reg(31),
ADR1 => b_31_Q,
ADR2 => state_FSM_FFd1_4311,
ADR3 => state_FSM_FFd2_4312,
O => b_reg_mux0000_31_Q
);
b_reg_31 : X_FF
generic map(
LOC => "SLICE_X19Y26",
INIT => '0'
)
port map (
I => b_reg_31_DXMUX_11832,
CE => VCC,
CLK => b_reg_31_CLKINV_11809,
SET => GND,
RST => b_reg_31_SRINV_11810,
O => b_reg(31)
);
b_reg_22 : X_FF
generic map(
LOC => "SLICE_X19Y22",
INIT => '0'
)
port map (
I => b_reg_23_DYMUX_11860,
CE => VCC,
CLK => b_reg_23_CLKINV_11851,
SET => GND,
RST => b_reg_23_SRINV_11852,
O => b_reg(22)
);
b_reg_mux0000_22_1 : X_LUT4
generic map(
INIT => X"88F0",
LOC => "SLICE_X19Y22"
)
port map (
ADR0 => state_FSM_FFd1_4311,
ADR1 => b_22_Q,
ADR2 => b_reg(22),
ADR3 => state_FSM_FFd2_4312,
O => b_reg_mux0000_22_Q
);
b_reg_mux0000_23_1 : X_LUT4
generic map(
INIT => X"B380",
LOC => "SLICE_X19Y22"
)
port map (
ADR0 => b_23_Q,
ADR1 => state_FSM_FFd2_4312,
ADR2 => state_FSM_FFd1_4311,
ADR3 => b_reg(23),
O => b_reg_mux0000_23_Q
);
b_reg_23 : X_FF
generic map(
LOC => "SLICE_X19Y22",
INIT => '0'
)
port map (
I => b_reg_23_DXMUX_11874,
CE => VCC,
CLK => b_reg_23_CLKINV_11851,
SET => GND,
RST => b_reg_23_SRINV_11852,
O => b_reg(23)
);
b_reg_14 : X_FF
generic map(
LOC => "SLICE_X19Y18",
INIT => '0'
)
port map (
I => b_reg_15_DYMUX_11902,
CE => VCC,
CLK => b_reg_15_CLKINV_11893,
SET => GND,
RST => b_reg_15_SRINV_11894,
O => b_reg(14)
);
b_reg_mux0000_14_1 : X_LUT4
generic map(
INIT => X"FC74",
LOC => "SLICE_X19Y18"
)
port map (
ADR0 => state_FSM_FFd1_4311,
ADR1 => state_FSM_FFd2_4312,
ADR2 => b_reg(14),
ADR3 => b_14_Q,
O => b_reg_mux0000_14_Q
);
b_reg_mux0000_15_1 : X_LUT4
generic map(
INIT => X"CFAA",
LOC => "SLICE_X19Y18"
)
port map (
ADR0 => b_reg(15),
ADR1 => b_15_Q,
ADR2 => state_FSM_FFd1_4311,
ADR3 => state_FSM_FFd2_4312,
O => b_reg_mux0000_15_Q
);
b_reg_15 : X_FF
generic map(
LOC => "SLICE_X19Y18",
INIT => '0'
)
port map (
I => b_reg_15_DXMUX_11916,
CE => VCC,
CLK => b_reg_15_CLKINV_11893,
SET => GND,
RST => b_reg_15_SRINV_11894,
O => b_reg(15)
);
b_reg_24 : X_FF
generic map(
LOC => "SLICE_X19Y24",
INIT => '0'
)
port map (
I => b_reg_25_DYMUX_11944,
CE => VCC,
CLK => b_reg_25_CLKINV_11935,
SET => GND,
RST => b_reg_25_SRINV_11936,
O => b_reg(24)
);
b_reg_mux0000_24_1 : X_LUT4
generic map(
INIT => X"B830",
LOC => "SLICE_X19Y24"
)
port map (
ADR0 => b_24_Q,
ADR1 => state_FSM_FFd2_4312,
ADR2 => b_reg(24),
ADR3 => state_FSM_FFd1_4311,
O => b_reg_mux0000_24_Q
);
b_reg_mux0000_25_1 : X_LUT4
generic map(
INIT => X"E2EE",
LOC => "SLICE_X19Y24"
)
port map (
ADR0 => b_reg(25),
ADR1 => state_FSM_FFd2_4312,
ADR2 => b_25_Q,
ADR3 => state_FSM_FFd1_4311,
O => b_reg_mux0000_25_Q
);
b_reg_25 : X_FF
generic map(
LOC => "SLICE_X19Y24",
INIT => '0'
)
port map (
I => b_reg_25_DXMUX_11958,
CE => VCC,
CLK => b_reg_25_CLKINV_11935,
SET => GND,
RST => b_reg_25_SRINV_11936,
O => b_reg(25)
);
b_reg_16 : X_FF
generic map(
LOC => "SLICE_X18Y21",
INIT => '0'
)
port map (
I => b_reg_17_DYMUX_11986,
CE => VCC,
CLK => b_reg_17_CLKINV_11977,
SET => GND,
RST => b_reg_17_SRINV_11978,
O => b_reg(16)
);
b_reg_mux0000_16_1 : X_LUT4
generic map(
INIT => X"CFAA",
LOC => "SLICE_X18Y21"
)
port map (
ADR0 => b_reg(16),
ADR1 => b_16_Q,
ADR2 => state_FSM_FFd1_4311,
ADR3 => state_FSM_FFd2_4312,
O => b_reg_mux0000_16_Q
);
b_reg_mux0000_17_1 : X_LUT4
generic map(
INIT => X"EE2E",
LOC => "SLICE_X18Y21"
)
port map (
ADR0 => b_reg(17),
ADR1 => state_FSM_FFd2_4312,
ADR2 => state_FSM_FFd1_4311,
ADR3 => b_17_Q,
O => b_reg_mux0000_17_Q
);
b_reg_17 : X_FF
generic map(
LOC => "SLICE_X18Y21",
INIT => '0'
)
port map (
I => b_reg_17_DXMUX_12000,
CE => VCC,
CLK => b_reg_17_CLKINV_11977,
SET => GND,
RST => b_reg_17_SRINV_11978,
O => b_reg(17)
);
b_reg_26 : X_FF
generic map(
LOC => "SLICE_X19Y25",
INIT => '0'
)
port map (
I => b_reg_27_DYMUX_12028,
CE => VCC,
CLK => b_reg_27_CLKINV_12019,
SET => GND,
RST => b_reg_27_SRINV_12020,
O => b_reg(26)
);
b_reg_mux0000_26_1 : X_LUT4
generic map(
INIT => X"B830",
LOC => "SLICE_X19Y25"
)
port map (
ADR0 => state_FSM_FFd1_4311,
ADR1 => state_FSM_FFd2_4312,
ADR2 => b_reg(26),
ADR3 => b_26_Q,
O => b_reg_mux0000_26_Q
);
b_reg_mux0000_27_1 : X_LUT4
generic map(
INIT => X"DF8A",
LOC => "SLICE_X19Y25"
)
port map (
ADR0 => state_FSM_FFd2_4312,
ADR1 => b_27_Q,
ADR2 => state_FSM_FFd1_4311,
ADR3 => b_reg(27),
O => b_reg_mux0000_27_Q
);
b_reg_27 : X_FF
generic map(
LOC => "SLICE_X19Y25",
INIT => '0'
)
port map (
I => b_reg_27_DXMUX_12042,
CE => VCC,
CLK => b_reg_27_CLKINV_12019,
SET => GND,
RST => b_reg_27_SRINV_12020,
O => b_reg(27)
);
b_reg_18 : X_FF
generic map(
LOC => "SLICE_X18Y20",
INIT => '0'
)
port map (
I => b_reg_19_DYMUX_12070,
CE => VCC,
CLK => b_reg_19_CLKINV_12061,
SET => GND,
RST => b_reg_19_SRINV_12062,
O => b_reg(18)
);
b_reg_mux0000_18_1 : X_LUT4
generic map(
INIT => X"D8FA",
LOC => "SLICE_X18Y20"
)
port map (
ADR0 => state_FSM_FFd2_4312,
ADR1 => b_18_Q,
ADR2 => b_reg(18),
ADR3 => state_FSM_FFd1_4311,
O => b_reg_mux0000_18_Q
);
b_reg_mux0000_19_1 : X_LUT4
generic map(
INIT => X"B380",
LOC => "SLICE_X18Y20"
)
port map (
ADR0 => b_19_Q,
ADR1 => state_FSM_FFd2_4312,
ADR2 => state_FSM_FFd1_4311,
ADR3 => b_reg(19),
O => b_reg_mux0000_19_Q
);
b_reg_19 : X_FF
generic map(
LOC => "SLICE_X18Y20",
INIT => '0'
)
port map (
I => b_reg_19_DXMUX_12084,
CE => VCC,
CLK => b_reg_19_CLKINV_12061,
SET => GND,
RST => b_reg_19_SRINV_12062,
O => b_reg(19)
);
b_reg_28 : X_FF
generic map(
LOC => "SLICE_X19Y27",
INIT => '0'
)
port map (
I => b_reg_29_DYMUX_12112,
CE => VCC,
CLK => b_reg_29_CLKINV_12103,
SET => GND,
RST => b_reg_29_SRINV_12104,
O => b_reg(28)
);
b_reg_mux0000_28_1 : X_LUT4
generic map(
INIT => X"B8FC",
LOC => "SLICE_X19Y27"
)
port map (
ADR0 => b_28_Q,
ADR1 => state_FSM_FFd2_4312,
ADR2 => b_reg(28),
ADR3 => state_FSM_FFd1_4311,
O => b_reg_mux0000_28_Q
);
b_reg_mux0000_29_1 : X_LUT4
generic map(
INIT => X"D580",
LOC => "SLICE_X19Y27"
)
port map (
ADR0 => state_FSM_FFd2_4312,
ADR1 => b_29_Q,
ADR2 => state_FSM_FFd1_4311,
ADR3 => b_reg(29),
O => b_reg_mux0000_29_Q
);
b_reg_29 : X_FF
generic map(
LOC => "SLICE_X19Y27",
INIT => '0'
)
port map (
I => b_reg_29_DXMUX_12126,
CE => VCC,
CLK => b_reg_29_CLKINV_12103,
SET => GND,
RST => b_reg_29_SRINV_12104,
O => b_reg(29)
);
Sh13220 : X_LUT4
generic map(
INIT => X"FA50",
LOC => "SLICE_X24Y19"
)
port map (
ADR0 => a(3),
ADR1 => VCC,
ADR2 => Sh100,
ADR3 => Sh124,
O => Sh13220_12146
);
Sh1287 : X_LUT4
generic map(
INIT => X"EE44",
LOC => "SLICE_X24Y19"
)
port map (
ADR0 => a(3),
ADR1 => Sh124,
ADR2 => VCC,
ADR3 => Sh116,
O => Sh1287_12154
);
Sh15013 : X_LUT4
generic map(
INIT => X"88A0",
LOC => "SLICE_X26Y20"
)
port map (
ADR0 => a(3),
ADR1 => Sh1082_0,
ADR2 => Sh1102_0,
ADR3 => a(1),
O => Sh15013_12170
);
Sh110_f51 : X_LUT4
generic map(
INIT => X"CCF0",
LOC => "SLICE_X26Y20"
)
port map (
ADR0 => VCC,
ADR1 => Sh1082_0,
ADR2 => Sh1102_0,
ADR3 => a(1),
O => Sh110
);
Sh14313 : X_LUT4
generic map(
INIT => X"A808",
LOC => "SLICE_X24Y21"
)
port map (
ADR0 => a(3),
ADR1 => Sh1032_0,
ADR2 => a(1),
ADR3 => Sh1012_0,
O => Sh14313_12194
);
Sh103_f51 : X_LUT4
generic map(
INIT => X"EE44",
LOC => "SLICE_X24Y21"
)
port map (
ADR0 => a(1),
ADR1 => Sh1032_0,
ADR2 => VCC,
ADR3 => Sh1012_0,
O => Sh103
);
Sh15113 : X_LUT4
generic map(
INIT => X"E400",
LOC => "SLICE_X22Y22"
)
port map (
ADR0 => a(1),
ADR1 => Sh1112_0,
ADR2 => Sh1092_0,
ADR3 => a(3),
O => Sh15113_12219
);
Sh15816 : X_LUT4
generic map(
INIT => X"00E2",
LOC => "SLICE_X22Y22"
)
port map (
ADR0 => Sh1262_0,
ADR1 => a(1),
ADR2 => Sh1242_0,
ADR3 => a(3),
O => Sh15816_12226
);
Sh15116 : X_LUT4
generic map(
INIT => X"00E2",
LOC => "SLICE_X24Y23"
)
port map (
ADR0 => Sh1192_0,
ADR1 => a(1),
ADR2 => Sh1172_0,
ADR3 => a(3),
O => Sh15116_12243
);
Sh15913 : X_LUT4
generic map(
INIT => X"C0A0",
LOC => "SLICE_X24Y23"
)
port map (
ADR0 => Sh1192_0,
ADR1 => Sh1172_0,
ADR2 => a(3),
ADR3 => a(1),
O => Sh1310
);
Sh14412 : X_LUT4
generic map(
INIT => X"A808",
LOC => "SLICE_X24Y13"
)
port map (
ADR0 => a(2),
ADR1 => Sh108,
ADR2 => a(3),
ADR3 => Sh100,
O => Sh14412_12265
);
Sh14813 : X_LUT4
generic map(
INIT => X"CC00",
LOC => "SLICE_X24Y13"
)
port map (
ADR0 => VCC,
ADR1 => a(3),
ADR2 => VCC,
ADR3 => Sh108,
O => Sh14813_12274
);
Sh14413 : X_LUT4
generic map(
INIT => X"CC00",
LOC => "SLICE_X22Y13"
)
port map (
ADR0 => VCC,
ADR1 => a(3),
ADR2 => VCC,
ADR3 => Sh104,
O => Sh14413_12289
);
Sh1323 : X_LUT4
generic map(
INIT => X"2222",
LOC => "SLICE_X22Y13"
)
port map (
ADR0 => Sh96,
ADR1 => a(3),
ADR2 => VCC,
ADR3 => VCC,
O => Sh12816
);
Sh15413 : X_LUT4
generic map(
INIT => X"C840",
LOC => "SLICE_X28Y23"
)
port map (
ADR0 => a(1),
ADR1 => a(3),
ADR2 => Sh1142_0,
ADR3 => Sh1122_0,
O => Sh15413_12315
);
Sh14616 : X_LUT4
generic map(
INIT => X"3210",
LOC => "SLICE_X28Y23"
)
port map (
ADR0 => a(1),
ADR1 => a(3),
ADR2 => Sh1142_0,
ADR3 => Sh1122_0,
O => Sh14616_12322
);
Sh14613 : X_LUT4
generic map(
INIT => X"A808",
LOC => "SLICE_X27Y17"
)
port map (
ADR0 => a(3),
ADR1 => Sh1062_0,
ADR2 => a(1),
ADR3 => Sh1042_0,
O => Sh14613_12338
);
Sh106_f51 : X_LUT4
generic map(
INIT => X"EE44",
LOC => "SLICE_X27Y17"
)
port map (
ADR0 => a(1),
ADR1 => Sh1062_0,
ADR2 => VCC,
ADR3 => Sh1042_0,
O => Sh106
);
Sh15513 : X_LUT4
generic map(
INIT => X"E400",
LOC => "SLICE_X26Y25"
)
port map (
ADR0 => a(1),
ADR1 => Sh1152_0,
ADR2 => Sh1132_0,
ADR3 => a(3),
O => Sh15513_12363
);
Sh15516 : X_LUT4
generic map(
INIT => X"5140",
LOC => "SLICE_X26Y25"
)
port map (
ADR0 => a(3),
ADR1 => a(1),
ADR2 => Sh1212_0,
ADR3 => Sh1232_0,
O => Sh15516_12370
);
Sh14816 : X_LUT4
generic map(
INIT => X"0F00",
LOC => "SLICE_X24Y17"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => a(3),
ADR3 => Sh116,
O => Sh14816_12386
);
Sh1527 : X_LUT4
generic map(
INIT => X"CFC0",
LOC => "SLICE_X24Y17"
)
port map (
ADR0 => VCC,
ADR1 => Sh108,
ADR2 => a(3),
ADR3 => Sh116,
O => Sh1527_12394
);
Sh15813 : X_LUT4
generic map(
INIT => X"C0A0",
LOC => "SLICE_X29Y22"
)
port map (
ADR0 => Sh1182_0,
ADR1 => Sh1162_0,
ADR2 => a(3),
ADR3 => a(1),
O => Sh15813_12411
);
Sh1340 : X_LUT4
generic map(
INIT => X"D080",
LOC => "SLICE_X29Y22"
)
port map (
ADR0 => a(1),
ADR1 => Sh1202_0,
ADR2 => a(3),
ADR3 => Sh1222_0,
O => Sh13013
);
b_reg_0_2 : X_FF
generic map(
LOC => "SLICE_X15Y17",
INIT => '0'
)
port map (
I => b_reg_0_2_DYMUX_12428,
CE => VCC,
CLK => b_reg_0_2_CLKINV_12425,
SET => GND,
RST => b_reg_0_2_FFY_RSTAND_12433,
O => b_reg_0_2_4323
);
b_reg_0_2_FFY_RSTAND : X_BUF
generic map(
LOC => "SLICE_X15Y17",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => b_reg_0_2_FFY_RSTAND_12433
);
b_reg_0_3 : X_FF
generic map(
LOC => "SLICE_X14Y16",
INIT => '0'
)
port map (
I => b_reg_0_3_DYMUX_12442,
CE => VCC,
CLK => b_reg_0_3_CLKINV_12439,
SET => GND,
RST => b_reg_0_3_FFY_RSTAND_12447,
O => b_reg_0_3_4316
);
b_reg_0_3_FFY_RSTAND : X_BUF
generic map(
LOC => "SLICE_X14Y16",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => b_reg_0_3_FFY_RSTAND_12447
);
Mxor_ab_xor_Result_3_1 : X_LUT4
generic map(
INIT => X"5A5A",
LOC => "SLICE_X3Y20"
)
port map (
ADR0 => b_reg_3_1_4597,
ADR1 => VCC,
ADR2 => a_reg(3),
ADR3 => VCC,
O => ab_xor_3_Q
);
Mxor_ab_xor_Result_4_1 : X_LUT4
generic map(
INIT => X"33CC",
LOC => "SLICE_X13Y19"
)
port map (
ADR0 => VCC,
ADR1 => b_reg_4_1_4383,
ADR2 => VCC,
ADR3 => a_reg(4),
O => ab_xor_4_Q
);
Mxor_ab_xor_Result_5_1 : X_LUT4
generic map(
INIT => X"33CC",
LOC => "SLICE_X14Y19"
)
port map (
ADR0 => VCC,
ADR1 => b_reg(5),
ADR2 => VCC,
ADR3 => a_reg(5),
O => ab_xor_5_Q
);
Mxor_ba_xor_Result_4_1_SW1 : X_LUT4
generic map(
INIT => X"AA33",
LOC => "SLICE_X14Y19"
)
port map (
ADR0 => b_reg(4),
ADR1 => b_reg(5),
ADR2 => VCC,
ADR3 => a(0),
O => N247
);
Mxor_ab_xor_Result_7_1 : X_LUT4
generic map(
INIT => X"3C3C",
LOC => "SLICE_X16Y13"
)
port map (
ADR0 => VCC,
ADR1 => a_reg(7),
ADR2 => b_reg(7),
ADR3 => VCC,
O => ab_xor_7_Q
);
Mxor_ba_xor_Result_12_1_SW1 : X_LUT4
generic map(
INIT => X"AA33",
LOC => "SLICE_X15Y16"
)
port map (
ADR0 => b_reg(12),
ADR1 => b_reg(13),
ADR2 => VCC,
ADR3 => a(0),
O => N235
);
Mxor_ab_xor_Result_21_1 : X_LUT4
generic map(
INIT => X"6666",
LOC => "SLICE_X17Y32"
)
port map (
ADR0 => a_reg(21),
ADR1 => b_reg(21),
ADR2 => VCC,
ADR3 => VCC,
O => ab_xor_21_Q
);
Mxor_ba_xor_Result_21_1_SW0 : X_LUT4
generic map(
INIT => X"0F33",
LOC => "SLICE_X17Y32"
)
port map (
ADR0 => VCC,
ADR1 => b_reg(22),
ADR2 => b_reg(21),
ADR3 => a(0),
O => N214
);
Mxor_ab_xor_Result_15_1 : X_LUT4
generic map(
INIT => X"5A5A",
LOC => "SLICE_X15Y20"
)
port map (
ADR0 => b_reg(15),
ADR1 => VCC,
ADR2 => a_reg(15),
ADR3 => VCC,
O => ab_xor_15_Q
);
Mxor_ba_xor_Result_15_1_SW0 : X_LUT4
generic map(
INIT => X"2727",
LOC => "SLICE_X15Y20"
)
port map (
ADR0 => a(0),
ADR1 => b_reg(14),
ADR2 => b_reg(15),
ADR3 => VCC,
O => N228
);
Mxor_ab_xor_Result_23_1 : X_LUT4
generic map(
INIT => X"6666",
LOC => "SLICE_X19Y31"
)
port map (
ADR0 => a_reg(23),
ADR1 => b_reg(23),
ADR2 => VCC,
ADR3 => VCC,
O => ab_xor_23_Q
);
Mxor_ba_xor_Result_23_1_SW0 : X_LUT4
generic map(
INIT => X"0F55",
LOC => "SLICE_X19Y31"
)
port map (
ADR0 => b_reg(23),
ADR1 => VCC,
ADR2 => b_reg(22),
ADR3 => a(0),
O => N202
);
Mxor_ab_xor_Result_31_1 : X_LUT4
generic map(
INIT => X"5A5A",
LOC => "SLICE_X17Y35"
)
port map (
ADR0 => a_reg(31),
ADR1 => VCC,
ADR2 => b_reg(31),
ADR3 => VCC,
O => ab_xor_31_Q
);
Mxor_ba_xor_Result_31_1_SW0 : X_LUT4
generic map(
INIT => X"05AF",
LOC => "SLICE_X17Y35"
)
port map (
ADR0 => a(0),
ADR1 => VCC,
ADR2 => b_reg(31),
ADR3 => b_reg(30),
O => N196
);
Mxor_ab_xor_Result_16_1 : X_LUT4
generic map(
INIT => X"0FF0",
LOC => "SLICE_X14Y20"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => a_reg(16),
ADR3 => b_reg(16),
O => ab_xor_16_Q
);
Sh1141_SW1 : X_LUT4
generic map(
INIT => X"AA33",
LOC => "SLICE_X14Y20"
)
port map (
ADR0 => b_reg(15),
ADR1 => b_reg(16),
ADR2 => VCC,
ADR3 => a(0),
O => N194
);
Mxor_ab_xor_Result_24_1 : X_LUT4
generic map(
INIT => X"5A5A",
LOC => "SLICE_X18Y32"
)
port map (
ADR0 => b_reg(24),
ADR1 => VCC,
ADR2 => a_reg(24),
ADR3 => VCC,
O => ab_xor_24_Q
);
Sh1221_SW1 : X_LUT4
generic map(
INIT => X"DD11",
LOC => "SLICE_X18Y32"
)
port map (
ADR0 => b_reg(24),
ADR1 => a(0),
ADR2 => VCC,
ADR3 => b_reg(23),
O => N182
);
Mxor_ab_xor_Result_17_1 : X_LUT4
generic map(
INIT => X"0FF0",
LOC => "SLICE_X13Y23"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => b_reg(17),
ADR3 => a_reg(17),
O => ab_xor_17_Q
);
Mxor_ba_xor_Result_17_1_SW0 : X_LUT4
generic map(
INIT => X"0F55",
LOC => "SLICE_X13Y23"
)
port map (
ADR0 => b_reg(18),
ADR1 => VCC,
ADR2 => b_reg(17),
ADR3 => a(0),
O => N217
);
Mxor_ab_xor_Result_25_1 : X_LUT4
generic map(
INIT => X"3C3C",
LOC => "SLICE_X16Y33"
)
port map (
ADR0 => VCC,
ADR1 => b_reg(25),
ADR2 => a_reg(25),
ADR3 => VCC,
O => ab_xor_25_Q
);
Mxor_ba_xor_Result_25_1_SW0 : X_LUT4
generic map(
INIT => X"2277",
LOC => "SLICE_X16Y33"
)
port map (
ADR0 => a(0),
ADR1 => b_reg(25),
ADR2 => VCC,
ADR3 => b_reg(26),
O => N211
);
Mxor_ab_xor_Result_19_1 : X_LUT4
generic map(
INIT => X"33CC",
LOC => "SLICE_X18Y25"
)
port map (
ADR0 => VCC,
ADR1 => b_reg(19),
ADR2 => VCC,
ADR3 => a_reg(19),
O => ab_xor_19_Q
);
Mxor_ba_xor_Result_19_1_SW0 : X_LUT4
generic map(
INIT => X"4477",
LOC => "SLICE_X18Y25"
)
port map (
ADR0 => b_reg(18),
ADR1 => a(0),
ADR2 => VCC,
ADR3 => b_reg(19),
O => N205
);
Mxor_ab_xor_Result_27_1 : X_LUT4
generic map(
INIT => X"5A5A",
LOC => "SLICE_X19Y30"
)
port map (
ADR0 => b_reg(27),
ADR1 => VCC,
ADR2 => a_reg(27),
ADR3 => VCC,
O => ab_xor_27_Q
);
Mxor_ba_xor_Result_27_1_SW0 : X_LUT4
generic map(
INIT => X"05F5",
LOC => "SLICE_X19Y30"
)
port map (
ADR0 => b_reg(27),
ADR1 => VCC,
ADR2 => a(0),
ADR3 => b_reg(26),
O => N199
);
Mxor_ab_xor_Result_28_1 : X_LUT4
generic map(
INIT => X"6666",
LOC => "SLICE_X18Y34"
)
port map (
ADR0 => a_reg(28),
ADR1 => b_reg(28),
ADR2 => VCC,
ADR3 => VCC,
O => ab_xor_28_Q
);
Sh1261_SW1 : X_LUT4
generic map(
INIT => X"F303",
LOC => "SLICE_X18Y34"
)
port map (
ADR0 => VCC,
ADR1 => b_reg(28),
ADR2 => a(0),
ADR3 => b_reg(27),
O => N176
);
Mxor_ab_xor_Result_29_1 : X_LUT4
generic map(
INIT => X"55AA",
LOC => "SLICE_X16Y34"
)
port map (
ADR0 => a_reg(29),
ADR1 => VCC,
ADR2 => VCC,
ADR3 => b_reg(29),
O => ab_xor_29_Q
);
Mxor_ba_xor_Result_29_1_SW0 : X_LUT4
generic map(
INIT => X"0F33",
LOC => "SLICE_X16Y34"
)
port map (
ADR0 => VCC,
ADR1 => b_reg(30),
ADR2 => b_reg(29),
ADR3 => a(0),
O => N208
);
Sh1141_SW0 : X_LUT4
generic map(
INIT => X"0F33",
LOC => "SLICE_X25Y21"
)
port map (
ADR0 => VCC,
ADR1 => b_reg(16),
ADR2 => b_reg(15),
ADR3 => a(0),
O => N193
);
Sh1151_SW1 : X_LUT4
generic map(
INIT => X"CC55",
LOC => "SLICE_X25Y21"
)
port map (
ADR0 => b_reg(17),
ADR1 => b_reg(16),
ADR2 => VCC,
ADR3 => a(0),
O => N191
);
Sh1221_SW0 : X_LUT4
generic map(
INIT => X"2277",
LOC => "SLICE_X20Y28"
)
port map (
ADR0 => a(0),
ADR1 => b_reg(23),
ADR2 => VCC,
ADR3 => b_reg(24),
O => N181
);
Sh1231_SW1 : X_LUT4
generic map(
INIT => X"88DD",
LOC => "SLICE_X20Y28"
)
port map (
ADR0 => a(0),
ADR1 => b_reg(24),
ADR2 => VCC,
ADR3 => b_reg(25),
O => N179
);
Sh1151_SW0 : X_LUT4
generic map(
INIT => X"3355",
LOC => "SLICE_X27Y21"
)
port map (
ADR0 => b_reg(17),
ADR1 => b_reg(16),
ADR2 => VCC,
ADR3 => a(0),
O => N190
);
Mxor_ba_xor_Result_3_1_SW3 : X_LUT4
generic map(
INIT => X"F033",
LOC => "SLICE_X27Y21"
)
port map (
ADR0 => VCC,
ADR1 => b_reg(3),
ADR2 => b_reg(2),
ADR3 => a(0),
O => N289
);
Sh1231_SW0 : X_LUT4
generic map(
INIT => X"3355",
LOC => "SLICE_X23Y26"
)
port map (
ADR0 => b_reg(25),
ADR1 => b_reg(24),
ADR2 => VCC,
ADR3 => a(0),
O => N178
);
Mxor_ba_xor_Result_3_1_SW2 : X_LUT4
generic map(
INIT => X"3355",
LOC => "SLICE_X23Y26"
)
port map (
ADR0 => b_reg(3),
ADR1 => b_reg(2),
ADR2 => VCC,
ADR3 => a(0),
O => N288
);
Sh1181_SW0 : X_LUT4
generic map(
INIT => X"11BB",
LOC => "SLICE_X24Y25"
)
port map (
ADR0 => a(0),
ADR1 => b_reg(20),
ADR2 => VCC,
ADR3 => b_reg(19),
O => N187
);
Sh1191_SW1 : X_LUT4
generic map(
INIT => X"BB11",
LOC => "SLICE_X24Y25"
)
port map (
ADR0 => a(0),
ADR1 => b_reg(21),
ADR2 => VCC,
ADR3 => b_reg(20),
O => N185
);
Sh1261_SW0 : X_LUT4
generic map(
INIT => X"11BB",
LOC => "SLICE_X22Y30"
)
port map (
ADR0 => a(0),
ADR1 => b_reg(28),
ADR2 => VCC,
ADR3 => b_reg(27),
O => N175
);
Sh1271_SW1 : X_LUT4
generic map(
INIT => X"DD11",
LOC => "SLICE_X22Y30"
)
port map (
ADR0 => b_reg(29),
ADR1 => a(0),
ADR2 => VCC,
ADR3 => b_reg(28),
O => N173
);
Sh1191_SW0 : X_LUT4
generic map(
INIT => X"2277",
LOC => "SLICE_X24Y26"
)
port map (
ADR0 => a(0),
ADR1 => b_reg(20),
ADR2 => VCC,
ADR3 => b_reg(21),
O => N184
);
Mxor_ba_xor_Result_3_1_SW1 : X_LUT4
generic map(
INIT => X"AF05",
LOC => "SLICE_X24Y26"
)
port map (
ADR0 => a(0),
ADR1 => VCC,
ADR2 => b_reg(4),
ADR3 => b_reg(3),
O => N264
);
Sh1271_SW0 : X_LUT4
generic map(
INIT => X"3535",
LOC => "SLICE_X22Y27"
)
port map (
ADR0 => b_reg(29),
ADR1 => b_reg(28),
ADR2 => a(0),
ADR3 => VCC,
O => N172
);
Mxor_ba_xor_Result_3_1_SW0 : X_LUT4
generic map(
INIT => X"05F5",
LOC => "SLICE_X22Y27"
)
port map (
ADR0 => b_reg(4),
ADR1 => VCC,
ADR2 => a(0),
ADR3 => b_reg(3),
O => N263
);
Sh701 : X_LUT4
generic map(
INIT => X"AFA0",
LOC => "SLICE_X16Y22"
)
port map (
ADR0 => Sh54,
ADR1 => VCC,
ADR2 => b_reg(4),
ADR3 => Sh38,
O => Sh70
);
Sh861 : X_LUT4
generic map(
INIT => X"FA0A",
LOC => "SLICE_X16Y22"
)
port map (
ADR0 => Sh54,
ADR1 => VCC,
ADR2 => b_reg(4),
ADR3 => Sh38,
O => Sh86
);
Sh711 : X_LUT4
generic map(
INIT => X"FA0A",
LOC => "SLICE_X18Y26"
)
port map (
ADR0 => Sh39,
ADR1 => VCC,
ADR2 => b_reg(4),
ADR3 => Sh55,
O => Sh71
);
Sh871 : X_LUT4
generic map(
INIT => X"AFA0",
LOC => "SLICE_X18Y26"
)
port map (
ADR0 => Sh39,
ADR1 => VCC,
ADR2 => b_reg(4),
ADR3 => Sh55,
O => Sh87
);
Sh641 : X_LUT4
generic map(
INIT => X"AACC",
LOC => "SLICE_X15Y24"
)
port map (
ADR0 => Sh48,
ADR1 => Sh32,
ADR2 => VCC,
ADR3 => b_reg(4),
O => Sh64
);
Sh801 : X_LUT4
generic map(
INIT => X"CCAA",
LOC => "SLICE_X15Y24"
)
port map (
ADR0 => Sh48,
ADR1 => Sh32,
ADR2 => VCC,
ADR3 => b_reg(4),
O => Sh80
);
Sh721 : X_LUT4
generic map(
INIT => X"EE44",
LOC => "SLICE_X12Y26"
)
port map (
ADR0 => b_reg(4),
ADR1 => Sh40,
ADR2 => VCC,
ADR3 => Sh56,
O => Sh72
);
Sh881 : X_LUT4
generic map(
INIT => X"DD88",
LOC => "SLICE_X12Y26"
)
port map (
ADR0 => b_reg(4),
ADR1 => Sh40,
ADR2 => VCC,
ADR3 => Sh56,
O => Sh88
);
Sh617 : X_LUT4
generic map(
INIT => X"FA0A",
LOC => "SLICE_X14Y21"
)
port map (
ADR0 => Sh25,
ADR1 => VCC,
ADR2 => b_reg(3),
ADR3 => Sh17,
O => Sh5720
);
Sh577 : X_LUT4
generic map(
INIT => X"F5A0",
LOC => "SLICE_X14Y21"
)
port map (
ADR0 => b_reg(3),
ADR1 => VCC,
ADR2 => Sh13,
ADR3 => Sh21,
O => Sh5320
);
Sh651 : X_LUT4
generic map(
INIT => X"AFA0",
LOC => "SLICE_X16Y18"
)
port map (
ADR0 => Sh49,
ADR1 => VCC,
ADR2 => b_reg(4),
ADR3 => Sh33,
O => Sh65
);
Sh811 : X_LUT4
generic map(
INIT => X"FA0A",
LOC => "SLICE_X16Y18"
)
port map (
ADR0 => Sh49,
ADR1 => VCC,
ADR2 => b_reg(4),
ADR3 => Sh33,
O => Sh81
);
Sh627 : X_LUT4
generic map(
INIT => X"F5A0",
LOC => "SLICE_X13Y29"
)
port map (
ADR0 => b_reg(3),
ADR1 => VCC,
ADR2 => Sh18,
ADR3 => Sh26,
O => Sh5820
);
Sh587 : X_LUT4
generic map(
INIT => X"EE44",
LOC => "SLICE_X13Y29"
)
port map (
ADR0 => b_reg(3),
ADR1 => Sh22_4347,
ADR2 => VCC,
ADR3 => Sh14,
O => Sh5420
);
Sh661 : X_LUT4
generic map(
INIT => X"D8D8",
LOC => "SLICE_X16Y23"
)
port map (
ADR0 => b_reg(4),
ADR1 => Sh50,
ADR2 => Sh34,
ADR3 => VCC,
O => Sh66
);
Sh821 : X_LUT4
generic map(
INIT => X"E4E4",
LOC => "SLICE_X16Y23"
)
port map (
ADR0 => b_reg(4),
ADR1 => Sh50,
ADR2 => Sh34,
ADR3 => VCC,
O => Sh82
);
Sh901 : X_LUT4
generic map(
INIT => X"ACAC",
LOC => "SLICE_X16Y21"
)
port map (
ADR0 => Sh42,
ADR1 => Sh58,
ADR2 => b_reg(4),
ADR3 => VCC,
O => Sh90
);
Mxor_ba_xor_Result_4_1_SW0 : X_LUT4
generic map(
INIT => X"550F",
LOC => "SLICE_X16Y21"
)
port map (
ADR0 => b_reg(4),
ADR1 => VCC,
ADR2 => b_reg(5),
ADR3 => a(0),
O => N246
);
Sh671 : X_LUT4
generic map(
INIT => X"CACA",
LOC => "SLICE_X16Y17"
)
port map (
ADR0 => Sh35,
ADR1 => Sh51,
ADR2 => b_reg(4),
ADR3 => VCC,
O => Sh67
);
Sh831 : X_LUT4
generic map(
INIT => X"ACAC",
LOC => "SLICE_X16Y17"
)
port map (
ADR0 => Sh35,
ADR1 => Sh51,
ADR2 => b_reg(4),
ADR3 => VCC,
O => Sh83
);
Sh751 : X_LUT4
generic map(
INIT => X"AFA0",
LOC => "SLICE_X16Y25"
)
port map (
ADR0 => Sh59,
ADR1 => VCC,
ADR2 => b_reg(4),
ADR3 => Sh43,
O => Sh75
);
Sh911 : X_LUT4
generic map(
INIT => X"FA0A",
LOC => "SLICE_X16Y25"
)
port map (
ADR0 => Sh59,
ADR1 => VCC,
ADR2 => b_reg(4),
ADR3 => Sh43,
O => Sh91
);
Sh681 : X_LUT4
generic map(
INIT => X"FA50",
LOC => "SLICE_X14Y18"
)
port map (
ADR0 => b_reg(4),
ADR1 => VCC,
ADR2 => Sh36,
ADR3 => Sh52,
O => Sh68
);
Sh841 : X_LUT4
generic map(
INIT => X"F5A0",
LOC => "SLICE_X14Y18"
)
port map (
ADR0 => b_reg(4),
ADR1 => VCC,
ADR2 => Sh36,
ADR3 => Sh52,
O => Sh84
);
Sh761 : X_LUT4
generic map(
INIT => X"CACA",
LOC => "SLICE_X16Y27"
)
port map (
ADR0 => Sh44,
ADR1 => Sh60,
ADR2 => b_reg(4),
ADR3 => VCC,
O => Sh76
);
Sh921 : X_LUT4
generic map(
INIT => X"ACAC",
LOC => "SLICE_X16Y27"
)
port map (
ADR0 => Sh44,
ADR1 => Sh60,
ADR2 => b_reg(4),
ADR3 => VCC,
O => Sh92
);
Sh691 : X_LUT4
generic map(
INIT => X"CACA",
LOC => "SLICE_X16Y24"
)
port map (
ADR0 => Sh37,
ADR1 => Sh53,
ADR2 => b_reg(4),
ADR3 => VCC,
O => Sh69
);
Sh851 : X_LUT4
generic map(
INIT => X"ACAC",
LOC => "SLICE_X16Y24"
)
port map (
ADR0 => Sh37,
ADR1 => Sh53,
ADR2 => b_reg(4),
ADR3 => VCC,
O => Sh85
);
Sh931 : X_LUT4
generic map(
INIT => X"ACAC",
LOC => "SLICE_X16Y31"
)
port map (
ADR0 => Sh45,
ADR1 => Sh61,
ADR2 => b_reg(4),
ADR3 => VCC,
O => Sh93
);
Sh791 : X_LUT4
generic map(
INIT => X"ACAC",
LOC => "SLICE_X16Y31"
)
port map (
ADR0 => Sh63,
ADR1 => Sh47,
ADR2 => b_reg(4),
ADR3 => VCC,
O => Sh79
);
Sh941 : X_LUT4
generic map(
INIT => X"FA50",
LOC => "SLICE_X16Y28"
)
port map (
ADR0 => b_reg(4),
ADR1 => VCC,
ADR2 => Sh62,
ADR3 => Sh46,
O => Sh94
);
Sh891 : X_LUT4
generic map(
INIT => X"D8D8",
LOC => "SLICE_X16Y28"
)
port map (
ADR0 => b_reg(4),
ADR1 => Sh41,
ADR2 => Sh57,
ADR3 => VCC,
O => Sh89
);
Sh991 : X_LUT4
generic map(
INIT => X"4747",
LOC => "SLICE_X25Y14"
)
port map (
ADR0 => b_reg(0),
ADR1 => a(0),
ADR2 => b_reg(1),
ADR3 => VCC,
O => Sh991_13638
);
Mxor_ba_xor_Result_7_1_SW0 : X_LUT4
generic map(
INIT => X"0C3F",
LOC => "SLICE_X25Y14"
)
port map (
ADR0 => VCC,
ADR1 => a(0),
ADR2 => b_reg(6),
ADR3 => b_reg(7),
O => N254
);
Sh992 : X_LUT4
generic map(
INIT => X"D18B",
LOC => "SLICE_X24Y18"
)
port map (
ADR0 => N289_0,
ADR1 => a(3),
ADR2 => N288_0,
ADR3 => a(2),
O => Sh1011_pack_1
);
Sh99_f51 : X_LUT4
generic map(
INIT => X"F3C0",
LOC => "SLICE_X24Y18"
)
port map (
ADR0 => VCC,
ADR1 => a(1),
ADR2 => Sh991_0,
ADR3 => Sh1011,
O => Sh99
);
b_reg_mux0000_2_5 : X_LUT4
generic map(
INIT => X"0F0A",
LOC => "SLICE_X9Y2"
)
port map (
ADR0 => swtch_led_1_OBUF_4254,
ADR1 => VCC,
ADR2 => Madd_b_pre_lut(2),
ADR3 => Madd_b_pre_cy_0_Q,
O => b_reg_mux0000_2_5_13686
);
b_reg_mux0000_2_13 : X_LUT4
generic map(
INIT => X"0050",
LOC => "SLICE_X9Y2"
)
port map (
ADR0 => swtch_led_1_OBUF_4254,
ADR1 => VCC,
ADR2 => Madd_b_pre_lut(2),
ADR3 => Madd_b_pre_cy_0_Q,
O => b_reg_mux0000_2_13_13694
);
b_reg_0 : X_FF
generic map(
LOC => "SLICE_X13Y15",
INIT => '0'
)
port map (
I => b_reg_1_DYMUX_13719,
CE => VCC,
CLK => b_reg_1_CLKINV_13710,
SET => GND,
RST => b_reg_1_SRINV_13711,
O => b_reg(0)
);
b_reg_mux0000_1_38_F : X_LUT4
generic map(
INIT => X"9F90",
LOC => "SLICE_X13Y15"
)
port map (
ADR0 => swtch_led_1_OBUF_4254,
ADR1 => Madd_b_pre_cy_0_Q,
ADR2 => state_FSM_FFd2_4312,
ADR3 => b_reg(1),
O => N498
);
b_reg_mux0000_1_38_G : X_LUT4
generic map(
INIT => X"FA0A",
LOC => "SLICE_X13Y15"
)
port map (
ADR0 => b_reg(1),
ADR1 => VCC,
ADR2 => state_FSM_FFd2_4312,
ADR3 => b_1_Q,
O => N499
);
b_reg_1 : X_FF
generic map(
LOC => "SLICE_X13Y15",
INIT => '0'
)
port map (
I => b_reg_1_DXMUX_13736,
CE => VCC,
CLK => b_reg_1_CLKINV_13710,
SET => GND,
RST => b_reg_1_SRINV_13711,
O => b_reg(1)
);
b_reg_2 : X_FF
generic map(
LOC => "SLICE_X3Y18",
INIT => '0'
)
port map (
I => b_reg_3_DYMUX_13752,
CE => VCC,
CLK => b_reg_3_CLKINV_13749,
SET => GND,
RST => b_reg_3_SRINV_13750,
O => b_reg(2)
);
b_reg_3 : X_FF
generic map(
LOC => "SLICE_X3Y18",
INIT => '0'
)
port map (
I => b_reg_3_DXMUX_13760,
CE => VCC,
CLK => b_reg_3_CLKINV_13749,
SET => GND,
RST => b_reg_3_SRINV_13750,
O => b_reg(3)
);
b_reg_mux0000_5_38 : X_LUT4
generic map(
INIT => X"CFC0",
LOC => "SLICE_X2Y16"
)
port map (
ADR0 => VCC,
ADR1 => N276,
ADR2 => b_5_Q,
ADR3 => N275,
O => b_reg_mux0000_5_Q
);
b_reg_5 : X_FF
generic map(
LOC => "SLICE_X2Y16",
INIT => '0'
)
port map (
I => b_reg_4_DYMUX_13785,
CE => VCC,
CLK => b_reg_4_CLKINV_13775,
SET => GND,
RST => b_reg_4_SRINV_13776,
O => b_reg(5)
);
b_reg_4 : X_FF
generic map(
LOC => "SLICE_X2Y16",
INIT => '0'
)
port map (
I => b_reg_4_DXMUX_13793,
CE => VCC,
CLK => b_reg_4_CLKINV_13775,
SET => GND,
RST => b_reg_4_SRINV_13776,
O => b_reg(4)
);
b_reg_mux0000_4_3 : X_LUT4
generic map(
INIT => X"CCC0",
LOC => "SLICE_X0Y20"
)
port map (
ADR0 => VCC,
ADR1 => swtch_led_4_OBUF_4257,
ADR2 => swtch_led_3_OBUF_4256,
ADR3 => Madd_b_pre_cy_2_Q,
O => b_reg_mux0000_4_3_13813
);
b_reg_mux0000_4_12 : X_LUT4
generic map(
INIT => X"0003",
LOC => "SLICE_X0Y20"
)
port map (
ADR0 => VCC,
ADR1 => swtch_led_4_OBUF_4257,
ADR2 => swtch_led_3_OBUF_4256,
ADR3 => Madd_b_pre_cy_2_Q,
O => b_reg_mux0000_4_12_13821
);
b_reg_mux0000_6_3 : X_LUT4
generic map(
INIT => X"EE00",
LOC => "SLICE_X2Y12"
)
port map (
ADR0 => swtch_led_5_OBUF_4258,
ADR1 => Madd_b_pre_cy_4_0,
ADR2 => VCC,
ADR3 => swtch_led_6_OBUF_4259,
O => b_reg_mux0000_6_3_13837
);
b_reg_mux0000_6_12 : X_LUT4
generic map(
INIT => X"0011",
LOC => "SLICE_X2Y12"
)
port map (
ADR0 => swtch_led_5_OBUF_4258,
ADR1 => Madd_b_pre_cy_4_0,
ADR2 => VCC,
ADR3 => swtch_led_6_OBUF_4259,
O => b_reg_mux0000_6_12_13845
);
Sh1537 : X_LUT4
generic map(
INIT => X"E4E4",
LOC => "SLICE_X24Y14"
)
port map (
ADR0 => a(3),
ADR1 => Sh117,
ADR2 => Sh109,
ADR3 => VCC,
O => Sh1537_14053
);
Sh1497 : X_LUT4
generic map(
INIT => X"ACAC",
LOC => "SLICE_X24Y14"
)
port map (
ADR0 => Sh105,
ADR1 => Sh113,
ADR2 => a(3),
ADR3 => VCC,
O => Sh1497_14061
);
Sh1811 : X_LUT4
generic map(
INIT => X"EE22",
LOC => "SLICE_X20Y21"
)
port map (
ADR0 => Sh149,
ADR1 => a(4),
ADR2 => VCC,
ADR3 => Sh133,
O => Sh181
);
Sh1771 : X_LUT4
generic map(
INIT => X"F3C0",
LOC => "SLICE_X20Y21"
)
port map (
ADR0 => VCC,
ADR1 => a(4),
ADR2 => Sh129,
ADR3 => Sh145,
O => Sh177
);
Sh1821 : X_LUT4
generic map(
INIT => X"EE44",
LOC => "SLICE_X23Y23"
)
port map (
ADR0 => a(4),
ADR1 => Sh150_0,
ADR2 => VCC,
ADR3 => Sh134,
O => Sh182
);
Sh1831 : X_LUT4
generic map(
INIT => X"EE44",
LOC => "SLICE_X23Y23"
)
port map (
ADR0 => a(4),
ADR1 => Sh151,
ADR2 => VCC,
ADR3 => Sh135,
O => Sh183
);
Sh1901 : X_LUT4
generic map(
INIT => X"AFA0",
LOC => "SLICE_X20Y24"
)
port map (
ADR0 => Sh142,
ADR1 => VCC,
ADR2 => a(4),
ADR3 => Sh158,
O => Sh190
);
Sh1841 : X_LUT4
generic map(
INIT => X"F0CC",
LOC => "SLICE_X20Y24"
)
port map (
ADR0 => VCC,
ADR1 => Sh152,
ADR2 => Sh136,
ADR3 => a(4),
O => Sh184
);
Sh1851 : X_LUT4
generic map(
INIT => X"CFC0",
LOC => "SLICE_X23Y18"
)
port map (
ADR0 => VCC,
ADR1 => Sh137,
ADR2 => a(4),
ADR3 => Sh153,
O => Sh185
);
Sh1861 : X_LUT4
generic map(
INIT => X"CFC0",
LOC => "SLICE_X23Y18"
)
port map (
ADR0 => VCC,
ADR1 => Sh138,
ADR2 => a(4),
ADR3 => Sh154_0,
O => Sh186
);
Sh1871 : X_LUT4
generic map(
INIT => X"EE44",
LOC => "SLICE_X23Y24"
)
port map (
ADR0 => a(4),
ADR1 => Sh155,
ADR2 => VCC,
ADR3 => Sh139,
O => Sh187
);
Sh1881 : X_LUT4
generic map(
INIT => X"F5A0",
LOC => "SLICE_X23Y24"
)
port map (
ADR0 => a(4),
ADR1 => VCC,
ADR2 => Sh140,
ADR3 => Sh156,
O => Sh188
);
Sh6120 : X_LUT4
generic map(
INIT => X"E4E4",
LOC => "SLICE_X15Y28"
)
port map (
ADR0 => b_reg(3),
ADR1 => Sh29,
ADR2 => Sh21,
ADR3 => VCC,
O => Sh337
);
Sh6220 : X_LUT4
generic map(
INIT => X"FA0A",
LOC => "SLICE_X15Y28"
)
port map (
ADR0 => Sh30,
ADR1 => VCC,
ADR2 => b_reg(3),
ADR3 => Sh22_4347,
O => Sh347
);
Sh1891 : X_LUT4
generic map(
INIT => X"AACC",
LOC => "SLICE_X20Y26"
)
port map (
ADR0 => Sh141,
ADR1 => Sh157,
ADR2 => VCC,
ADR3 => a(4),
O => Sh189
);
Madd_b_pre_cy_2_11 : X_LUT4
generic map(
INIT => X"CCC0",
LOC => "SLICE_X3Y15"
)
port map (
ADR0 => VCC,
ADR1 => Madd_b_pre_lut(2),
ADR2 => swtch_led_1_OBUF_4254,
ADR3 => Madd_b_pre_cy_0_Q,
O => Madd_b_pre_cy_2_pack_1
);
Madd_b_pre_cy_4_11 : X_LUT4
generic map(
INIT => X"FFEE",
LOC => "SLICE_X3Y15"
)
port map (
ADR0 => swtch_led_3_OBUF_4256,
ADR1 => swtch_led_4_OBUF_4257,
ADR2 => VCC,
ADR3 => Madd_b_pre_cy_2_Q,
O => Madd_b_pre_cy_4_Q
);
Madd_b_pre_cy_6_11 : X_LUT4
generic map(
INIT => X"FFEE",
LOC => "SLICE_X2Y14"
)
port map (
ADR0 => swtch_led_5_OBUF_4258,
ADR1 => Madd_b_pre_cy_4_0,
ADR2 => VCC,
ADR3 => swtch_led_6_OBUF_4259,
O => Madd_b_pre_cy_6_pack_1
);
b_reg_mux0000_8_10 : X_LUT4
generic map(
INIT => X"0002",
LOC => "SLICE_X2Y14"
)
port map (
ADR0 => state_FSM_FFd2_4312,
ADR1 => state_FSM_FFd1_4311,
ADR2 => swtch_led_7_OBUF_4260,
ADR3 => Madd_b_pre_cy_6_Q,
O => b_reg_mux0000_10_10
);
hex2_7seg_Mrom_segment_data11 : X_LUT4
generic map(
INIT => X"0285",
LOC => "SLICE_X29Y9"
)
port map (
ADR0 => hex_digit_i(2),
ADR1 => hex_digit_i(0),
ADR2 => hex_digit_i(1),
ADR3 => hex_digit_i(3),
O => segment_g_i_OBUF_14282
);
hex2_7seg_Mrom_segment_data61 : X_LUT4
generic map(
INIT => X"4806",
LOC => "SLICE_X29Y9"
)
port map (
ADR0 => hex_digit_i(2),
ADR1 => hex_digit_i(0),
ADR2 => hex_digit_i(1),
ADR3 => hex_digit_i(3),
O => segment_a_i_OBUF_14289
);
hex2_7seg_Mrom_segment_data21 : X_LUT4
generic map(
INIT => X"5170",
LOC => "SLICE_X28Y9"
)
port map (
ADR0 => hex_digit_i(3),
ADR1 => hex_digit_i(1),
ADR2 => hex_digit_i(0),
ADR3 => hex_digit_i(2),
O => segment_e_i_OBUF_14306
);
hex2_7seg_Mrom_segment_data31 : X_LUT4
generic map(
INIT => X"C118",
LOC => "SLICE_X28Y9"
)
port map (
ADR0 => hex_digit_i(3),
ADR1 => hex_digit_i(1),
ADR2 => hex_digit_i(0),
ADR3 => hex_digit_i(2),
O => segment_d_i_OBUF_14313
);
hex2_7seg_Mrom_segment_data41 : X_LUT4
generic map(
INIT => X"A210",
LOC => "SLICE_X29Y8"
)
port map (
ADR0 => hex_digit_i(2),
ADR1 => hex_digit_i(0),
ADR2 => hex_digit_i(1),
ADR3 => hex_digit_i(3),
O => segment_c_i_OBUF_14330
);
hex2_7seg_Mrom_segment_data111 : X_LUT4
generic map(
INIT => X"08D4",
LOC => "SLICE_X29Y8"
)
port map (
ADR0 => hex_digit_i(2),
ADR1 => hex_digit_i(0),
ADR2 => hex_digit_i(1),
ADR3 => hex_digit_i(3),
O => segment_f_i_OBUF_14337
);
hex2_7seg_Mrom_segment_data51 : X_LUT4
generic map(
INIT => X"9E80",
LOC => "SLICE_X28Y12"
)
port map (
ADR0 => hex_digit_i(3),
ADR1 => hex_digit_i(1),
ADR2 => hex_digit_i(0),
ADR3 => hex_digit_i(2),
O => segment_b_i_OBUF_14349
);
i_cnt_mux0001_0_45_SW0 : X_LUT4
generic map(
INIT => X"BFF3",
LOC => "SLICE_X18Y14"
)
port map (
ADR0 => i_cnt_mux0001_0_25_0,
ADR1 => i_cnt(2),
ADR2 => i_cnt(1),
ADR3 => i_cnt(0),
O => N514
);
Mrom_b_rom0000821 : X_LUT4
generic map(
INIT => X"F033",
LOC => "SLICE_X18Y14"
)
port map (
ADR0 => VCC,
ADR1 => i_cnt(2),
ADR2 => i_cnt(1),
ADR3 => i_cnt(0),
O => N14
);
i_cnt_mux0001_1_27_SW0 : X_LUT4
generic map(
INIT => X"9975",
LOC => "SLICE_X19Y28"
)
port map (
ADR0 => i_cnt(2),
ADR1 => i_cnt(1),
ADR2 => i_cnt(3),
ADR3 => i_cnt(0),
O => N516_pack_3
);
i_cnt_mux0001_1_27 : X_LUT4
generic map(
INIT => X"44E4",
LOC => "SLICE_X19Y28"
)
port map (
ADR0 => state_FSM_FFd2_4312,
ADR1 => i_cnt(2),
ADR2 => state_FSM_FFd1_4311,
ADR3 => N516,
O => i_cnt_mux0001(1)
);
i_cnt_2 : X_FF
generic map(
LOC => "SLICE_X19Y28",
INIT => '0'
)
port map (
I => i_cnt_2_DXMUX_14404,
CE => VCC,
CLK => i_cnt_2_CLKINV_14388,
SET => GND,
RST => i_cnt_2_FFX_RSTAND_14409,
O => i_cnt(2)
);
i_cnt_2_FFX_RSTAND : X_BUF
generic map(
LOC => "SLICE_X19Y28",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => i_cnt_2_FFX_RSTAND_14409
);
Mrom_a_rom0000101 : X_LUT4
generic map(
INIT => X"504C",
LOC => "SLICE_X18Y18"
)
port map (
ADR0 => i_cnt(3),
ADR1 => i_cnt(2),
ADR2 => i_cnt(1),
ADR3 => i_cnt(0),
O => Mrom_a_rom000010
);
Mrom_b_rom000012 : X_LUT4
generic map(
INIT => X"0065",
LOC => "SLICE_X18Y18"
)
port map (
ADR0 => i_cnt(3),
ADR1 => i_cnt(2),
ADR2 => i_cnt(0),
ADR3 => i_cnt(1),
O => Mrom_b_rom000012_14432
);
Mrom_a_rom0000111 : X_LUT4
generic map(
INIT => X"54BD",
LOC => "SLICE_X19Y21"
)
port map (
ADR0 => i_cnt(2),
ADR1 => i_cnt(0),
ADR2 => i_cnt(1),
ADR3 => i_cnt(3),
O => Mrom_a_rom000011_14449
);
Mrom_b_rom000020 : X_LUT4
generic map(
INIT => X"50A9",
LOC => "SLICE_X19Y21"
)
port map (
ADR0 => i_cnt(2),
ADR1 => i_cnt(0),
ADR2 => i_cnt(1),
ADR3 => i_cnt(3),
O => Mrom_b_rom000020_14456
);
Mrom_a_rom0000211 : X_LUT4
generic map(
INIT => X"175D",
LOC => "SLICE_X16Y19"
)
port map (
ADR0 => i_cnt(3),
ADR1 => i_cnt(0),
ADR2 => i_cnt(2),
ADR3 => i_cnt(1),
O => Mrom_a_rom000021
);
Mrom_b_rom00008 : X_LUT4
generic map(
INIT => X"4F29",
LOC => "SLICE_X16Y19"
)
port map (
ADR0 => i_cnt(3),
ADR1 => i_cnt(0),
ADR2 => i_cnt(2),
ADR3 => i_cnt(1),
O => Mrom_b_rom00008_14480
);
Mrom_a_rom0000301 : X_LUT4
generic map(
INIT => X"176C",
LOC => "SLICE_X19Y29"
)
port map (
ADR0 => i_cnt(2),
ADR1 => i_cnt(1),
ADR2 => i_cnt(3),
ADR3 => i_cnt(0),
O => Mrom_a_rom000030
);
Mrom_b_rom000013 : X_LUT4
generic map(
INIT => X"456B",
LOC => "SLICE_X19Y29"
)
port map (
ADR0 => i_cnt(2),
ADR1 => i_cnt(1),
ADR2 => i_cnt(3),
ADR3 => i_cnt(0),
O => Mrom_b_rom000013_14504
);
Mrom_a_rom0000311 : X_LUT4
generic map(
INIT => X"0A21",
LOC => "SLICE_X21Y29"
)
port map (
ADR0 => i_cnt(2),
ADR1 => i_cnt(1),
ADR2 => i_cnt(3),
ADR3 => i_cnt(0),
O => Mrom_a_rom000031
);
Mrom_b_rom0000311 : X_LUT4
generic map(
INIT => X"0C50",
LOC => "SLICE_X21Y29"
)
port map (
ADR0 => i_cnt(2),
ADR1 => i_cnt(1),
ADR2 => i_cnt(3),
ADR3 => i_cnt(0),
O => Mrom_b_rom000031
);
Mrom_a_rom0000251 : X_LUT4
generic map(
INIT => X"0939",
LOC => "SLICE_X20Y25"
)
port map (
ADR0 => i_cnt(2),
ADR1 => i_cnt(1),
ADR2 => i_cnt(3),
ADR3 => i_cnt(0),
O => Mrom_a_rom000025
);
Mrom_b_rom0000232 : X_LUT4
generic map(
INIT => X"081A",
LOC => "SLICE_X20Y25"
)
port map (
ADR0 => i_cnt(2),
ADR1 => i_cnt(1),
ADR2 => i_cnt(3),
ADR3 => i_cnt(0),
O => Mrom_b_rom000023
);
Mrom_a_rom0000261 : X_LUT4
generic map(
INIT => X"2646",
LOC => "SLICE_X20Y29"
)
port map (
ADR0 => i_cnt(0),
ADR1 => i_cnt(3),
ADR2 => i_cnt(1),
ADR3 => i_cnt(2),
O => Mrom_a_rom000026
);
Mrom_b_rom0000171 : X_LUT4
generic map(
INIT => X"225D",
LOC => "SLICE_X20Y29"
)
port map (
ADR0 => i_cnt(0),
ADR1 => i_cnt(3),
ADR2 => i_cnt(1),
ADR3 => i_cnt(2),
O => Mrom_b_rom000017_14576
);
Mrom_a_rom0000191 : X_LUT4
generic map(
INIT => X"1473",
LOC => "SLICE_X17Y14"
)
port map (
ADR0 => i_cnt(0),
ADR1 => i_cnt(3),
ADR2 => i_cnt(1),
ADR3 => i_cnt(2),
O => Mrom_a_rom000019
);
Mrom_b_rom000071 : X_LUT4
generic map(
INIT => X"1403",
LOC => "SLICE_X17Y14"
)
port map (
ADR0 => i_cnt(0),
ADR1 => i_cnt(3),
ADR2 => i_cnt(1),
ADR3 => i_cnt(2),
O => Mrom_b_rom00007
);
Mrom_a_rom0000271 : X_LUT4
generic map(
INIT => X"0049",
LOC => "SLICE_X20Y27"
)
port map (
ADR0 => i_cnt(3),
ADR1 => i_cnt(1),
ADR2 => i_cnt(2),
ADR3 => i_cnt(0),
O => Mrom_a_rom000027
);
Mrom_b_rom0000301 : X_LUT4
generic map(
INIT => X"5D20",
LOC => "SLICE_X20Y27"
)
port map (
ADR0 => i_cnt(3),
ADR1 => i_cnt(1),
ADR2 => i_cnt(2),
ADR3 => i_cnt(0),
O => Mrom_b_rom000030
);
Mxor_ba_xor_Result_11_1_SW0 : X_LUT4
generic map(
INIT => X"5353",
LOC => "SLICE_X18Y10"
)
port map (
ADR0 => b_reg(10),
ADR1 => b_reg(11),
ADR2 => a(0),
ADR3 => VCC,
O => N251
);
Mxor_ba_xor_Result_9_1_SW0 : X_LUT4
generic map(
INIT => X"5353",
LOC => "SLICE_X18Y10"
)
port map (
ADR0 => b_reg(9),
ADR1 => b_reg(10),
ADR2 => a(0),
ADR3 => VCC,
O => N237
);
Mrom_b_rom00001111 : X_LUT4
generic map(
INIT => X"044A",
LOC => "SLICE_X20Y23"
)
port map (
ADR0 => i_cnt(2),
ADR1 => i_cnt(0),
ADR2 => i_cnt(3),
ADR3 => i_cnt(1),
O => Mrom_b_rom000011_14665
);
Mrom_b_rom0000281 : X_LUT4
generic map(
INIT => X"4459",
LOC => "SLICE_X20Y23"
)
port map (
ADR0 => i_cnt(3),
ADR1 => i_cnt(0),
ADR2 => i_cnt(2),
ADR3 => i_cnt(1),
O => Mrom_b_rom000028
);
Mxor_ba_xor_Result_12_1_SW0 : X_LUT4
generic map(
INIT => X"0F55",
LOC => "SLICE_X23Y14"
)
port map (
ADR0 => b_reg(13),
ADR1 => VCC,
ADR2 => b_reg(12),
ADR3 => a(0),
O => N234
);
Mxor_ba_xor_Result_13_1_SW0 : X_LUT4
generic map(
INIT => X"550F",
LOC => "SLICE_X23Y14"
)
port map (
ADR0 => b_reg(13),
ADR1 => VCC,
ADR2 => b_reg(14),
ADR3 => a(0),
O => N231
);
Mrom_b_rom00002611 : X_LUT4
generic map(
INIT => X"1050",
LOC => "SLICE_X22Y23"
)
port map (
ADR0 => i_cnt(0),
ADR1 => i_cnt(1),
ADR2 => i_cnt(3),
ADR3 => i_cnt(2),
O => N77
);
Mrom_b_rom0000262 : X_LUT4
generic map(
INIT => X"1C5A",
LOC => "SLICE_X22Y23"
)
port map (
ADR0 => i_cnt(0),
ADR1 => i_cnt(1),
ADR2 => i_cnt(3),
ADR3 => i_cnt(2),
O => Mrom_b_rom000026
);
Mrom_b_rom00001821 : X_LUT4
generic map(
INIT => X"0011",
LOC => "SLICE_X20Y15"
)
port map (
ADR0 => i_cnt(2),
ADR1 => i_cnt(3),
ADR2 => VCC,
ADR3 => i_cnt(1),
O => N34
);
Mrom_b_rom00002721 : X_LUT4
generic map(
INIT => X"0022",
LOC => "SLICE_X20Y15"
)
port map (
ADR0 => i_cnt(3),
ADR1 => i_cnt(2),
ADR2 => VCC,
ADR3 => i_cnt(1),
O => N33
);
state_FSM_Out21 : X_LUT4
generic map(
INIT => X"3300",
LOC => "SLICE_X3Y0"
)
port map (
ADR0 => VCC,
ADR1 => state_FSM_FFd2_4312,
ADR2 => VCC,
ADR3 => state_FSM_FFd1_4311,
O => do_rdy_OBUF_14756
);
Mrom_a_rom000011 : X_LUT4
generic map(
INIT => X"0B42",
LOC => "SLICE_X19Y16"
)
port map (
ADR0 => i_cnt(1),
ADR1 => i_cnt(0),
ADR2 => i_cnt(2),
ADR3 => i_cnt(3),
O => Mrom_a_rom00001
);
Mrom_b_rom0000221 : X_LUT4
generic map(
INIT => X"0182",
LOC => "SLICE_X19Y16"
)
port map (
ADR0 => i_cnt(1),
ADR1 => i_cnt(0),
ADR2 => i_cnt(2),
ADR3 => i_cnt(3),
O => Mrom_b_rom000022
);
Mrom_a_rom000012 : X_LUT4
generic map(
INIT => X"445C",
LOC => "SLICE_X18Y17"
)
port map (
ADR0 => i_cnt(3),
ADR1 => i_cnt(2),
ADR2 => i_cnt(0),
ADR3 => i_cnt(1),
O => Mrom_a_rom0000
);
Mrom_b_rom0000161 : X_LUT4
generic map(
INIT => X"3503",
LOC => "SLICE_X18Y17"
)
port map (
ADR0 => i_cnt(3),
ADR1 => i_cnt(2),
ADR2 => i_cnt(0),
ADR3 => i_cnt(1),
O => Mrom_b_rom000016
);
Mrom_a_rom000013 : X_LUT4
generic map(
INIT => X"2552",
LOC => "SLICE_X18Y16"
)
port map (
ADR0 => i_cnt(3),
ADR1 => i_cnt(2),
ADR2 => i_cnt(0),
ADR3 => i_cnt(1),
O => Mrom_a_rom000013_14821
);
Mrom_b_rom0000101 : X_LUT4
generic map(
INIT => X"5421",
LOC => "SLICE_X18Y16"
)
port map (
ADR0 => i_cnt(3),
ADR1 => i_cnt(2),
ADR2 => i_cnt(0),
ADR3 => i_cnt(1),
O => Mrom_b_rom000010
);
Mrom_a_rom000023 : X_LUT4
generic map(
INIT => X"42BF",
LOC => "SLICE_X18Y23"
)
port map (
ADR0 => i_cnt(3),
ADR1 => i_cnt(0),
ADR2 => i_cnt(1),
ADR3 => i_cnt(2),
O => Mrom_a_rom000023_14845
);
Mrom_b_rom000061 : X_LUT4
generic map(
INIT => X"1123",
LOC => "SLICE_X18Y23"
)
port map (
ADR0 => i_cnt(2),
ADR1 => i_cnt(0),
ADR2 => i_cnt(1),
ADR3 => i_cnt(3),
O => Mrom_b_rom00006
);
Mrom_a_rom000015 : X_LUT4
generic map(
INIT => X"0605",
LOC => "SLICE_X19Y17"
)
port map (
ADR0 => i_cnt(1),
ADR1 => i_cnt(0),
ADR2 => i_cnt(2),
ADR3 => i_cnt(3),
O => Mrom_a_rom000015_14869
);
Mrom_b_rom00009 : X_LUT4
generic map(
INIT => X"1993",
LOC => "SLICE_X19Y17"
)
port map (
ADR0 => i_cnt(1),
ADR1 => i_cnt(0),
ADR2 => i_cnt(2),
ADR3 => i_cnt(3),
O => Mrom_b_rom00009_14876
);
Mrom_a_rom000024 : X_LUT4
generic map(
INIT => X"3169",
LOC => "SLICE_X18Y29"
)
port map (
ADR0 => i_cnt(0),
ADR1 => i_cnt(3),
ADR2 => i_cnt(1),
ADR3 => i_cnt(2),
O => Mrom_a_rom000024_14893
);
Mrom_b_rom0000211 : X_LUT4
generic map(
INIT => X"0325",
LOC => "SLICE_X18Y29"
)
port map (
ADR0 => i_cnt(0),
ADR1 => i_cnt(3),
ADR2 => i_cnt(1),
ADR3 => i_cnt(2),
O => Mrom_b_rom000021
);
Mrom_a_rom000016 : X_LUT4
generic map(
INIT => X"0E71",
LOC => "SLICE_X20Y20"
)
port map (
ADR0 => i_cnt(1),
ADR1 => i_cnt(0),
ADR2 => i_cnt(2),
ADR3 => i_cnt(3),
O => Mrom_a_rom000016_14917
);
Mrom_b_rom000014 : X_LUT4
generic map(
INIT => X"114D",
LOC => "SLICE_X20Y20"
)
port map (
ADR0 => i_cnt(1),
ADR1 => i_cnt(0),
ADR2 => i_cnt(2),
ADR3 => i_cnt(3),
O => Mrom_b_rom000014_14924
);
Mrom_a_rom000017 : X_LUT4
generic map(
INIT => X"0E49",
LOC => "SLICE_X20Y19"
)
port map (
ADR0 => i_cnt(3),
ADR1 => i_cnt(0),
ADR2 => i_cnt(2),
ADR3 => i_cnt(1),
O => Mrom_a_rom000017_14941
);
Mrom_b_rom000011 : X_LUT4
generic map(
INIT => X"4709",
LOC => "SLICE_X20Y19"
)
port map (
ADR0 => i_cnt(3),
ADR1 => i_cnt(0),
ADR2 => i_cnt(2),
ADR3 => i_cnt(1),
O => Mrom_b_rom00001
);
Mrom_a_rom000018 : X_LUT4
generic map(
INIT => X"362C",
LOC => "SLICE_X16Y30"
)
port map (
ADR0 => i_cnt(0),
ADR1 => i_cnt(2),
ADR2 => i_cnt(1),
ADR3 => i_cnt(3),
O => Mrom_a_rom000018_14965
);
Mrom_a_rom000029 : X_LUT4
generic map(
INIT => X"2794",
LOC => "SLICE_X16Y30"
)
port map (
ADR0 => i_cnt(0),
ADR1 => i_cnt(2),
ADR2 => i_cnt(1),
ADR3 => i_cnt(3),
O => Mrom_a_rom000029_14972
);
Mrom_a_rom000061 : X_LUT4
generic map(
INIT => X"5255",
LOC => "SLICE_X18Y24"
)
port map (
ADR0 => i_cnt(3),
ADR1 => i_cnt(2),
ADR2 => i_cnt(0),
ADR3 => i_cnt(1),
O => Mrom_a_rom00006
);
Mrom_b_rom000029 : X_LUT4
generic map(
INIT => X"176A",
LOC => "SLICE_X18Y24"
)
port map (
ADR0 => i_cnt(3),
ADR1 => i_cnt(2),
ADR2 => i_cnt(0),
ADR3 => i_cnt(1),
O => Mrom_b_rom000029_14996
);
Mrom_a_rom000081 : X_LUT4
generic map(
INIT => X"190A",
LOC => "SLICE_X16Y20"
)
port map (
ADR0 => i_cnt(3),
ADR1 => i_cnt(0),
ADR2 => i_cnt(2),
ADR3 => i_cnt(1),
O => Mrom_a_rom00008
);
Mrom_a_rom00009 : X_LUT4
generic map(
INIT => X"1B18",
LOC => "SLICE_X16Y20"
)
port map (
ADR0 => i_cnt(3),
ADR1 => i_cnt(0),
ADR2 => i_cnt(2),
ADR3 => i_cnt(1),
O => Mrom_a_rom00009_15020
);
Mrom_b_rom0000191 : X_LUT4
generic map(
INIT => X"0DF6",
LOC => "SLICE_X19Y19"
)
port map (
ADR0 => i_cnt(1),
ADR1 => i_cnt(0),
ADR2 => i_cnt(2),
ADR3 => i_cnt(3),
O => Mrom_b_rom000019
);
Mrom_a_rom00005 : X_LUT4
generic map(
INIT => X"1620",
LOC => "SLICE_X19Y19"
)
port map (
ADR0 => i_cnt(2),
ADR1 => i_cnt(1),
ADR2 => i_cnt(0),
ADR3 => i_cnt(3),
O => Mrom_a_rom00005_15044
);
Mrom_b_rom0000271 : X_LUT4
generic map(
INIT => X"1491",
LOC => "SLICE_X18Y22"
)
port map (
ADR0 => i_cnt(2),
ADR1 => i_cnt(0),
ADR2 => i_cnt(1),
ADR3 => i_cnt(3),
O => Mrom_b_rom000027
);
Mrom_a_rom00002 : X_LUT4
generic map(
INIT => X"1146",
LOC => "SLICE_X18Y22"
)
port map (
ADR0 => i_cnt(2),
ADR1 => i_cnt(0),
ADR2 => i_cnt(1),
ADR3 => i_cnt(3),
O => Mrom_a_rom00002_15068
);
state_cmp_eq00001 : X_LUT4
generic map(
INIT => X"0008",
LOC => "SLICE_X15Y10"
)
port map (
ADR0 => i_cnt(2),
ADR1 => i_cnt(3),
ADR2 => i_cnt(1),
ADR3 => i_cnt(0),
O => state_cmp_eq0000_pack_4
);
state_FSM_FFd1 : X_FF
generic map(
LOC => "SLICE_X15Y10",
INIT => '0'
)
port map (
I => state_FSM_FFd2_DYMUX_15095,
CE => VCC,
CLK => state_FSM_FFd2_CLKINV_15085,
SET => GND,
RST => state_FSM_FFd2_SRINV_15086,
O => state_FSM_FFd1_4311
);
state_FSM_FFd2_In1 : X_LUT4
generic map(
INIT => X"5F44",
LOC => "SLICE_X15Y10"
)
port map (
ADR0 => state_FSM_FFd1_4311,
ADR1 => di_vld_IBUF_4273,
ADR2 => state_cmp_eq0000,
ADR3 => state_FSM_FFd2_4312,
O => state_FSM_FFd2_In
);
state_FSM_FFd2 : X_FF
generic map(
LOC => "SLICE_X15Y10",
INIT => '0'
)
port map (
I => state_FSM_FFd2_DXMUX_15109,
CE => VCC,
CLK => state_FSM_FFd2_CLKINV_15085,
SET => GND,
RST => state_FSM_FFd2_SRINV_15086,
O => state_FSM_FFd2_4312
);
Mrom_a_rom00004 : X_LUT4
generic map(
INIT => X"1738",
LOC => "SLICE_X19Y15"
)
port map (
ADR0 => i_cnt(1),
ADR1 => i_cnt(0),
ADR2 => i_cnt(2),
ADR3 => i_cnt(3),
O => Mrom_a_rom00004_15130
);
Mrom_b_rom000017 : X_LUT4
generic map(
INIT => X"0777",
LOC => "SLICE_X19Y15"
)
port map (
ADR0 => i_cnt(1),
ADR1 => i_cnt(0),
ADR2 => i_cnt(2),
ADR3 => i_cnt(3),
O => Mrom_b_rom0000
);
Mxor_ba_xor_Result_5_1_SW0 : X_LUT4
generic map(
INIT => X"0F55",
LOC => "SLICE_X19Y12"
)
port map (
ADR0 => b_reg(6),
ADR1 => VCC,
ADR2 => b_reg(5),
ADR3 => a(0),
O => N243
);
Mxor_ba_xor_Result_8_1_SW0 : X_LUT4
generic map(
INIT => X"3355",
LOC => "SLICE_X19Y12"
)
port map (
ADR0 => b_reg(9),
ADR1 => b_reg(8),
ADR2 => VCC,
ADR3 => a(0),
O => N240
);
LED_flash_cnt_0_G_X_LUT4 : X_LUT4
generic map(
INIT => X"CCCC",
LOC => "SLICE_X31Y10"
)
port map (
ADR0 => VCC,
ADR1 => LED_flash_cnt(1),
ADR2 => VCC,
ADR3 => VCC,
O => LED_flash_cnt_0_G
);
LED_flash_cnt_2_F_X_LUT4 : X_LUT4
generic map(
INIT => X"AAAA",
LOC => "SLICE_X31Y11"
)
port map (
ADR0 => LED_flash_cnt(2),
ADR1 => VCC,
ADR2 => VCC,
ADR3 => VCC,
O => LED_flash_cnt_2_F
);
LED_flash_cnt_2_G_X_LUT4 : X_LUT4
generic map(
INIT => X"FF00",
LOC => "SLICE_X31Y11"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => LED_flash_cnt(3),
O => LED_flash_cnt_2_G
);
LED_flash_cnt_4_F_X_LUT4 : X_LUT4
generic map(
INIT => X"AAAA",
LOC => "SLICE_X31Y12"
)
port map (
ADR0 => LED_flash_cnt(4),
ADR1 => VCC,
ADR2 => VCC,
ADR3 => VCC,
O => LED_flash_cnt_4_F
);
LED_flash_cnt_4_G_X_LUT4 : X_LUT4
generic map(
INIT => X"F0F0",
LOC => "SLICE_X31Y12"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => LED_flash_cnt(5),
ADR3 => VCC,
O => LED_flash_cnt_4_G
);
LED_flash_cnt_6_F_X_LUT4 : X_LUT4
generic map(
INIT => X"CCCC",
LOC => "SLICE_X31Y13"
)
port map (
ADR0 => VCC,
ADR1 => LED_flash_cnt(6),
ADR2 => VCC,
ADR3 => VCC,
O => LED_flash_cnt_6_F
);
LED_flash_cnt_6_G_X_LUT4 : X_LUT4
generic map(
INIT => X"FF00",
LOC => "SLICE_X31Y13"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => LED_flash_cnt(7),
O => LED_flash_cnt_6_G
);
LED_flash_cnt_8_F_X_LUT4 : X_LUT4
generic map(
INIT => X"FF00",
LOC => "SLICE_X31Y14"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => LED_flash_cnt(8),
O => LED_flash_cnt_8_F
);
AN_0_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD33",
PATHPULSE => 638 ps
)
port map (
I => AN_0_4261,
O => AN_0_O
);
AN_1_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD44",
PATHPULSE => 638 ps
)
port map (
I => AN_1_4262,
O => AN_1_O
);
AN_2_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD51",
PATHPULSE => 638 ps
)
port map (
I => AN_2_4263,
O => AN_2_O
);
AN_3_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD45",
PATHPULSE => 638 ps
)
port map (
I => AN_3_4264,
O => AN_3_O
);
segment_a_i_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD48",
PATHPULSE => 638 ps
)
port map (
I => segment_a_i_OBUF_14289,
O => segment_a_i_O
);
segment_b_i_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD39",
PATHPULSE => 638 ps
)
port map (
I => segment_b_i_OBUF_14349,
O => segment_b_i_O
);
segment_c_i_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD53",
PATHPULSE => 638 ps
)
port map (
I => segment_c_i_OBUF_14330,
O => segment_c_i_O
);
segment_d_i_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD59",
PATHPULSE => 638 ps
)
port map (
I => segment_d_i_OBUF_14313,
O => segment_d_i_O
);
segment_e_i_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD56",
PATHPULSE => 638 ps
)
port map (
I => segment_e_i_OBUF_14306,
O => segment_e_i_O
);
segment_f_i_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD49",
PATHPULSE => 638 ps
)
port map (
I => segment_f_i_OBUF_14337,
O => segment_f_i_O
);
segment_g_i_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD52",
PATHPULSE => 638 ps
)
port map (
I => segment_g_i_OBUF_14282,
O => segment_g_i_O
);
do_rdy_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD79",
PATHPULSE => 638 ps
)
port map (
I => do_rdy_OBUF_14756,
O => do_rdy_O
);
swtch_led_0_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD69",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_pre_cy_0_Q,
O => swtch_led_0_O
);
swtch_led_1_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD58",
PATHPULSE => 638 ps
)
port map (
I => swtch_led_1_OBUF_4254,
O => swtch_led_1_O
);
swtch_led_2_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD64",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_pre_lut(2),
O => swtch_led_2_O
);
swtch_led_3_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD65",
PATHPULSE => 638 ps
)
port map (
I => swtch_led_3_OBUF_4256,
O => swtch_led_3_O
);
swtch_led_4_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD68",
PATHPULSE => 638 ps
)
port map (
I => swtch_led_4_OBUF_4257,
O => swtch_led_4_O
);
swtch_led_5_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD71",
PATHPULSE => 638 ps
)
port map (
I => swtch_led_5_OBUF_4258,
O => swtch_led_5_O
);
swtch_led_6_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD70",
PATHPULSE => 638 ps
)
port map (
I => swtch_led_6_OBUF_4259,
O => swtch_led_6_O
);
swtch_led_7_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD96",
PATHPULSE => 638 ps
)
port map (
I => swtch_led_7_OBUF_4260,
O => swtch_led_7_O
);
NlwBlock_rc5_VCC : X_ONE
port map (
O => VCC
);
NlwBlock_rc5_GND : X_ZERO
port map (
O => GND
);
NlwBlockROC : X_ROC
generic map (ROC_WIDTH => 100 ns)
port map (O => GSR);
NlwBlockTOC : X_TOC
port map (O => GTS);
end Structure;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:51:54 10/29/2013
-- Design Name:
-- Module Name: InstructionMemory - Behavioral_InstructionMemory
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Fetch is
PORT(
clk: in std_logic;
reset: in std_logic;
In_stall_if: in std_logic;
Instruction : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
PC_out : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
BEQ_PC : IN STD_LOGIC_VECTOR( 31 DOWNTO 0 );
PCSrc : IN STD_LOGIC;
Jump : IN STD_LOGIC;
JumpPC : IN STD_LOGIC_VECTOR( 31 DOWNTO 0 ); -- JUmp address
IF_ID_Flush: out std_logic
);
end Fetch;
architecture Behavioral of Fetch is
component ram_instr
port (
ADDR : in std_logic_vector(31 downto 0);
DATA : out std_logic_vector(31 downto 0));
end component;
signal PC: std_logic_vector (31 downto 0); -- fetched instruction
signal nextPC: std_logic_vector(31 downto 0); -- Next PC
signal read_addr: std_logic_vector(31 downto 0);
signal IncPC: std_logic_vector (31 downto 0); -- PC + 4
begin
instr_mem: ram_instr port map (ADDR => read_addr, DATA => Instruction);
-- multiplex next PC
nextPC <= (JumpPC - x"00000004") when (Jump = '1')
else BEQ_PC when (PCSrc = '1')
else incPC;
incPC <= PC + X"00000004"; -- incPC = PC +4 ;
PC_out <= incPC;
read_addr <= "00"&PC(31 downto 2);
IF_ID_Flush <='1' when (Jump='1' or PCSrc = '1') -- in case Jump and Branch, flush the IF_ID
else '0';
process (Clk,Reset)
begin
if (Reset = '1') then
PC <= X"00000000"; -- currently start from 0 for test
elsif (Clk'event and Clk = '1') then
if(In_stall_if = '0') then
PC <= nextPC;
else
PC <= PC;
end if;
end if;
end process;
end Behavioral;
--------------------------------------------------------------------------
-- Instruction RAM
--------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ram_instr is
port (
ADDR : in std_logic_vector(31 downto 0);
DATA : out std_logic_vector(31 downto 0)
);
end ram_instr;
architecture syn of ram_instr is
type rom_type is array (0 to 31) of std_logic_vector (31 downto 0);
-- currently, set 0-6 for test purpose
CONSTANT ROM : rom_type := (
x"34020003",x"34030009",x"00432020",x"00822020",x"00832020",x"8c050004",x"00852020",x"ac040008",
x"8c060008",x"0086382a",x"28480004",X"000341c0",x"00622804",x"00033843",x"00433807",x"00034042",
x"00434006",x"10420002",x"34020007",x"34020009",x"3402000b",x"08000019",x"34030008",x"3403000a",
x"3403000c",x"08000019",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000");
begin
DATA <= ROM(conv_integer(ADDR));
end syn; |
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|
`protect begin_protected
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 8208)
`protect data_block
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`protect end_protected
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:33:48 11/17/2015
-- Design Name:
-- Module Name: Datapath - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Datapath is
end Datapath;
architecture Behavioral of Datapath is
begin
end Behavioral;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:59:22 01/11/2012
-- Design Name:
-- Module Name: F:/repos/cpe-233-test-benches/lab-4-arc/RegisterFileTestBench.vhd
-- Project Name: lab-4-arc
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: RegisterFile
--
-- Dependencies: RegisterFile
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- Runtime must be set to 700ns for proper execution
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RegisterFileTestBench IS
END RegisterFileTestBench;
ARCHITECTURE behavior OF RegisterFileTestBench IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT RegisterFile
PORT(
D_IN : IN std_logic_vector(7 downto 0);
DX_OUT : OUT std_logic_vector(7 downto 0);
DY_OUT : OUT std_logic_vector(7 downto 0);
ADRX : IN std_logic_vector(4 downto 0);
ADRY : IN std_logic_vector(4 downto 0);
WE : IN std_logic;
CLK : IN std_logic
);
END COMPONENT;
-- test signals
signal data_x_exp : std_logic_vector(7 downto 0) := x"00";
signal data_y_exp : std_logic_vector(7 downto 0) := x"00";
--Inputs
signal D_IN_tb : std_logic_vector(7 downto 0) := (others => '0');
signal ADRX_tb : std_logic_vector(4 downto 0) := (others => '0');
signal ADRY_tb : std_logic_vector(4 downto 0) := (others => '0');
signal WE_tb : std_logic := '0';
signal CLK_tb : std_logic := '0';
--Outputs
signal DX_OUT_tb : std_logic_vector(7 downto 0);
signal DY_OUT_tb : std_logic_vector(7 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: RegisterFile PORT MAP (
D_IN => D_IN_tb,
DX_OUT => DX_OUT_tb,
DY_OUT => DY_OUT_tb,
ADRX => ADRX_tb,
ADRY => ADRY_tb,
WE => WE_tb,
CLK => CLK_tb
);
-- Clock process definitions
CLK_process :process
begin
CLK_tb <= '0';
wait for CLK_period/2;
CLK_tb <= '1';
wait for CLK_period/2;
end process;
-- verify memory
VERIFY_process :process
variable I : integer range 0 to 32 := 0;
begin
--Write to RegisterFile
ADRX_tb<="00000";
D_IN_tb<="00000000";
wait for 4ns;
WE_tb <= '1'; --togle high before rising edge
wait for 1ns;
while( I < 32) loop
wait for 1ns;
WE_tb <= '0'; --drop after rising edge
wait for 1ns;
ADRX_tb <= ADRX_tb + 1; --prepare next address and data
wait for 1ns;
D_IN_tb <= D_IN_tb +2;
wait for 6ns;
I := I+1;
if(I <32) then
WE_tb <= '1';
end if;
wait for 1ns;
end loop;
WE_tb <= '0';
-- DX_OE_tb <= '1';
wait for 75ns; --no reason, just like to start at a nice number such as 400ns...
-- Read from RegisterFile
I := 0;
-- set initial values
data_x_exp <= "00000000";
data_y_exp <= "00000010";
ADRX_tb <= "00000";
ADRY_tb <= "00001";
-- loop through all memory locations. NOTE: can read two at once
while ( I < 16) loop
WE_tb <= '0';
wait for 1ns;
if not(DX_OUT_tb = data_x_exp) then
report "error with data X at t= " & time'image(now)
severity failure;
else
report "data X at t= " & time'image(now) & " is good"
severity note;
end if;
if not(DY_OUT_tb = data_y_exp) then
report "error with data Y at t= " & time'image(now)
severity failure;
else
report "data Y at t= " & time'image(now) & " is good"
severity note;
end if;
wait for 1ns;
--get new values
data_x_exp <= data_x_exp + 4 ; --add 4 because each location increases by 2, and you're increasing by 2 memory locations
data_y_exp <= data_y_exp + 4 ;
ADRX_tb <= ADRX_tb + 2;
ADRY_tb <= ADRY_tb + 2;
wait for 8ns;
I := I + 1;
end loop;
wait for 40ns; -- again, just lining up for a nice start time of 600ns.
-- -- Test OE pin of RegisterFile
-- DX_OE_tb <= '0';
-- wait for 50ns;
-- if not (DX_OUT_tb = "ZZZZZZZZ") then
-- report "error with OE pin"
-- severity failure;
-- else
-- report "OE pin test 1 passed"
-- severity note;
-- end if;
-- -- DX_OE_tb <= '1';
-- wait for 50ns;
-- if (DX_OUT_tb = "ZZZZZZZZ") then
-- report "error with OE pin"
-- severity failure;
-- else
-- report "OE pin test 2 passed"
-- severity note;
-- end if;
-- report "Error checking complete at 700ns" severity note;
end process VERIFY_process;
END;
|
entity tb_dff01 is
end tb_dff01;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_dff01 is
signal clk : std_logic;
signal en1 : std_logic;
signal en2 : std_logic;
signal din : std_logic;
signal dout : std_logic;
begin
dut: entity work.dff01
port map (
q => dout,
d => din,
en1 => en1,
en2 => en2,
clk => clk);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
en1 <= '1';
en2 <= '1';
din <= '0';
pulse;
assert dout = '0' severity failure;
din <= '1';
pulse;
assert dout = '1' severity failure;
en1 <= '0';
din <= '0';
pulse;
assert dout = '1' severity failure;
en1 <= '1';
din <= '0';
pulse;
assert dout = '0' severity failure;
wait;
end process;
end behav;
|
--------------------------------------------------------------------------------
-- PROJECT: PIPE MANIA - GAME FOR FPGA
--------------------------------------------------------------------------------
-- NAME: BRAM_SYNC_TDP
-- AUTHORS: Jakub Cabal <xcabal05@stud.feec.vutbr.cz>
-- LICENSE: The MIT License, please read LICENSE file
-- WEBSITE: https://github.com/jakubcabal/pipemania-fpga-game
--------------------------------------------------------------------------------
-- BRAM_SYNC_TDP is optimized for Altera Cyclone IV BRAM!
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity BRAM_SYNC_TDP is
Generic (
DATA_WIDTH : integer := 32; -- Sirka datoveho vstupu a vystupu
ADDR_WIDTH : integer := 9 -- Sirka adresove sbernice, urcuje take pocet polozek v pameti (2^ADDR_WIDTH)
);
Port (
CLK : in std_logic;
-- Port A
WE_A : in std_logic;
ADDR_A : in std_logic_vector(ADDR_WIDTH-1 downto 0);
DATAIN_A : in std_logic_vector(DATA_WIDTH-1 downto 0);
DATAOUT_A : out std_logic_vector(DATA_WIDTH-1 downto 0);
-- Port B
WE_B : in std_logic;
ADDR_B : in std_logic_vector(ADDR_WIDTH-1 downto 0);
DATAIN_B : in std_logic_vector(DATA_WIDTH-1 downto 0);
DATAOUT_B : out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end BRAM_SYNC_TDP;
architecture FULL of BRAM_SYNC_TDP is
type ram_t is array((2**ADDR_WIDTH)-1 downto 0) of std_logic_vector(DATA_WIDTH-1 downto 0);
shared variable ram : ram_t := (others => (others => '0'));
begin
process (CLK)
begin
if (rising_edge(CLK)) then
if (WE_A = '1') then
ram(to_integer(unsigned(ADDR_A))) := DATAIN_A;
end if;
DATAOUT_A <= ram(to_integer(unsigned(ADDR_A)));
end if;
end process;
process (CLK)
begin
if (rising_edge(CLK)) then
if (WE_B = '1') then
ram(to_integer(unsigned(ADDR_B))) := DATAIN_B;
end if;
DATAOUT_B <= ram(to_integer(unsigned(ADDR_B)));
end if;
end process;
end FULL;
|
-- Test case from Brian Padalino
--
entity wait22 is end entity ;
architecture arch of wait22 is
procedure generate_clock(signal ena : in boolean ; signal clock : inout bit) is
begin
-- Inspired by UVVM clock_generator procedure
loop
if not ena then
if now /= 0 ps then
report "Stopping clock" ;
end if ;
clock <= '0' ;
wait until ena ;
end if ;
clock <= '1' ;
wait for 5 ns ;
clock <= '0' ;
wait for 5 ns ;
end loop ;
end procedure ;
signal clock_enable : boolean := false ;
signal clock : bit := '0' ;
signal reset : bit := '1' ;
begin
gen_clock_p: generate_clock(clock_enable, clock) ;
tick_p: process(clock, reset)
begin
if reset = '1' then
else
if clock'event and clock = '1' then
report "Clock tick" ;
end if ;
end if ;
end process ;
tb : process
begin
report "About to begin" ;
wait for 10 ns ;
reset <= '0' ;
wait for 10 ns ;
clock_enable <= true ;
wait for 100 ns ;
std.env.stop;
end process ;
end architecture ;
|
--!-----------------------------------------------------------------------------
--! --
--! BNL - Brookhaven National Lboratory --
--! Physics Department --
--! Omega Group --
--!-----------------------------------------------------------------------------
--|
--! author: Kai Chen (kchen@bnl.gov)
--!
--!
--!-----------------------------------------------------------------------------
--
-- Create Date: 21:33:01 2015/11/18
-- Design Name:
-- Module Name: HDLC_TXRX - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: The MODULE to send data to IC/EC bit, and receive data from
-- IC/EC bit. The data encoding and decoding to/from HDLC shold
-- be done in software. This module only send and receive data
-- to a multi-bytes register. users can change its width.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
use work.pcie_package.all;
use work.FELIX_gbt_package.all;
entity HDLC_TXRX_WRAPPER is
generic (
REG_WIDTH : integer := 256;
GBT_NUM : integer := 24
);
port (
txclk_40m : in std_logic;
rxclk_40m : in std_logic;
ICECBUSY : out std_logic_vector(15 downto 0);
ICEC_INT_RX_DATA : out txrx64b_24ch_type;
register_map_control: in register_map_control_type;
ICEC_RX_4b : in txrx4b_type;
ICEC_TX_4b : out txrx4b_type
);
end HDLC_TXRX_WRAPPER;
architecture behv of HDLC_TXRX_WRAPPER is
type txrx256b_24ch_type is array (23 downto 0) of std_logic_vector(REG_WIDTH-1 downto 0);
signal rx_ic_reg : txrx256b_24ch_type;
signal tx_ic_reg : txrx256b_24ch_type;
signal rx_ec_reg : txrx256b_24ch_type;
signal tx_ec_reg : txrx256b_24ch_type;
signal ic_trig : std_logic_vector(23 downto 0);
signal ec_trig : std_logic_vector(23 downto 0);
signal IC_RX_REG_BUF : std_logic_vector(REG_WIDTH-1 downto 0);
signal EC_RX_REG_BUF : std_logic_vector(REG_WIDTH-1 downto 0);
signal ic_ch_sel : std_logic_vector(4 downto 0);
signal ec_ch_sel : std_logic_vector(4 downto 0);
signal ICEC_TX_4b_i : txrx4b_type(0 to GBT_NUM-1);
signal ICEC_RX_4b_i : txrx4b_type(0 to GBT_NUM-1);
signal ic_trig_i : std_logic_vector(23 downto 0):=x"000000";
signal ic_trig_r : std_logic_vector(23 downto 0):=x"000000";
signal ic_trig_2r : std_logic_vector(23 downto 0):=x"000000";
signal ic_trig_3r : std_logic_vector(23 downto 0):=x"000000";
signal ic_sel_rx_i : std_logic_vector(23 downto 0):=x"000000";
signal IC_busy_pull : std_logic_vector(23 downto 0):=x"000000";
signal ic_int : std_logic_vector(23 downto 0):=x"000000";
signal ec_trig_i : std_logic_vector(23 downto 0):=x"000000";
signal ec_trig_r : std_logic_vector(23 downto 0):=x"000000";
signal ec_trig_2r : std_logic_vector(23 downto 0):=x"000000";
signal ec_trig_3r : std_logic_vector(23 downto 0):=x"000000";
signal EC_busy_pull : std_logic_vector(23 downto 0):=x"000000";
signal ec_int : std_logic_vector(23 downto 0):=x"000000";
signal muxsel : std_logic_vector(23 downto 0);
begin
ic_trig_i(4 downto 0) <= register_map_control.ICEC_TRIG(4 downto 0);
ic_sel_rx_i(4 downto 0) <= register_map_control.ICEC_TRIG(20 downto 16);
ec_trig_i(4 downto 0) <= register_map_control.ICEC_TRIG(12 downto 8);
tx_ec_reg(0) <= register_map_control.EC_TXDATA03 & register_map_control.EC_TXDATA02
& register_map_control.EC_TXDATA01 & register_map_control.EC_TXDATA00;
tx_ec_reg(1) <= register_map_control.EC_TXDATA13 & register_map_control.EC_TXDATA12
& register_map_control.EC_TXDATA11 & register_map_control.EC_TXDATA10;
tx_ec_reg(2) <= register_map_control.EC_TXDATA23 & register_map_control.EC_TXDATA22
& register_map_control.EC_TXDATA21 & register_map_control.EC_TXDATA20;
tx_ec_reg(3) <= register_map_control.EC_TXDATA33 & register_map_control.EC_TXDATA32
& register_map_control.EC_TXDATA31 & register_map_control.EC_TXDATA30;
tx_ec_reg(4) <= register_map_control.EC_TXDATA43 & register_map_control.EC_TXDATA42
& register_map_control.EC_TXDATA41 & register_map_control.EC_TXDATA40;
ch_gen : for i in GBT_NUM-1 downto 0 generate
tx_ic_reg(i) <= register_map_control.IC_TXDATA03 & register_map_control.IC_TXDATA02
& register_map_control.IC_TXDATA01 & register_map_control.IC_TXDATA00;
process (txclk_40m)
begin
if txclk_40m'event and txclk_40m='1' then
ic_trig_r(i) <= ic_trig_i(i);
ic_trig_2r(i) <= ic_trig_r(i);
ic_trig_3r(i) <= ic_trig_2r(i);
IC_busy_pull(i) <= ic_trig_r(i) and (not ic_trig_3r(i));
ic_trig(i) <= ic_trig_r(i) and (not ic_trig_2r(i));
ec_trig_r(i) <= ec_trig_i(i);
ec_trig_2r(i) <= ec_trig_r(i);
ec_trig_3r(i) <= ec_trig_2r(i);
EC_busy_pull(i) <= ec_trig_r(i) and (not ec_trig_3r(i));
ec_trig(i) <= ec_trig_r(i) and (not ec_trig_2r(i));
end if;
end process;
process(rxclk_40m)
begin
if rxclk_40m'event and rxclk_40m='1' then
if ic_busy_pull(i) = '1' then
ICECBUSY(i) <= '1';
elsif ic_int(i)='1' then
ICECBUSY(i) <= '0';
end if;
if ec_busy_pull(i)= '1' then
ICECBUSY(i+8) <= '1';
elsif ec_int(i)='1' then
ICECBUSY(i+8) <= '0';
end if;
end if;
end process;
end generate;
ICEC_INT_RX_DATA(3) <= IC_RX_REG_BUF(255 downto 192);
ICEC_INT_RX_DATA(2) <= IC_RX_REG_BUF(191 downto 128);
ICEC_INT_RX_DATA(1) <= IC_RX_REG_BUF(127 downto 64);
ICEC_INT_RX_DATA(0) <= IC_RX_REG_BUF(63 downto 0);
ICEC_INT_RX_DATA(7) <= rx_ec_reg(0)(255 downto 192);
ICEC_INT_RX_DATA(6) <= rx_ec_reg(0)(191 downto 128);
ICEC_INT_RX_DATA(5) <= rx_ec_reg(0)(127 downto 64);
ICEC_INT_RX_DATA(4) <= rx_ec_reg(0)(63 downto 0);
ICEC_INT_RX_DATA(11) <= rx_ec_reg(1)(255 downto 192);
ICEC_INT_RX_DATA(10) <= rx_ec_reg(1)(191 downto 128);
ICEC_INT_RX_DATA(9) <= rx_ec_reg(1)(127 downto 64);
ICEC_INT_RX_DATA(8) <= rx_ec_reg(1)(63 downto 0);
ICEC_INT_RX_DATA(15) <= rx_ec_reg(2)(255 downto 192);
ICEC_INT_RX_DATA(14) <= rx_ec_reg(2)(191 downto 128);
ICEC_INT_RX_DATA(13) <= rx_ec_reg(2)(127 downto 64);
ICEC_INT_RX_DATA(12) <= rx_ec_reg(2)(63 downto 0);
ICEC_INT_RX_DATA(19) <= rx_ec_reg(3)(255 downto 192);
ICEC_INT_RX_DATA(18) <= rx_ec_reg(3)(191 downto 128);
ICEC_INT_RX_DATA(17) <= rx_ec_reg(3)(127 downto 64);
ICEC_INT_RX_DATA(16) <= rx_ec_reg(3)(63 downto 0);
ICEC_INT_RX_DATA(23) <= rx_ec_reg(4)(255 downto 192);
ICEC_INT_RX_DATA(22) <= rx_ec_reg(4)(191 downto 128);
ICEC_INT_RX_DATA(21) <= rx_ec_reg(4)(127 downto 64);
ICEC_INT_RX_DATA(20) <= rx_ec_reg(4)(63 downto 0);
IC_RX_REG_BUF <= rx_ic_reg(0) when ic_sel_rx_i(0) = '1' else
rx_ic_reg(1) when ic_sel_rx_i(1) = '1' else
rx_ic_reg(2) when ic_sel_rx_i(2) = '1' else
rx_ic_reg(3) when ic_sel_rx_i(3) = '1' else
rx_ic_reg(4) when ic_sel_rx_i(4) = '1' else
IC_RX_REG_BUF;
-- EC_RX_REG_BUF <= rx_ec_reg(0) when ec_ch_sel = "00000" else
-- rx_ec_reg(1) when ec_ch_sel = "00001" else
-- rx_ec_reg(2) when ec_ch_sel = "00010" else
-- rx_ec_reg(3) when ec_ch_sel = "00011" else
-- rx_ec_reg(4) when ec_ch_sel = "00100" else
-- rx_ec_reg(5) when ec_ch_sel = "00101" else
-- rx_ec_reg(6) when ec_ch_sel = "00110" else
-- rx_ec_reg(7) when ec_ch_sel = "00111" else
-- rx_ec_reg(8) when ec_ch_sel = "01000" else
-- rx_ec_reg(9) when ec_ch_sel = "01001" else
-- rx_ec_reg(10) when ec_ch_sel = "01010" else
-- rx_ec_reg(11) when ec_ch_sel = "01011" else
-- rx_ec_reg(12) when ec_ch_sel = "01100" else
-- rx_ec_reg(13) when ec_ch_sel = "01101" else
-- rx_ec_reg(14) when ec_ch_sel = "01110" else
-- rx_ec_reg(15) when ec_ch_sel = "01111" else
-- rx_ec_reg(16) when ec_ch_sel = "10000" else
-- rx_ec_reg(17) when ec_ch_sel = "10001" else
-- rx_ec_reg(18) when ec_ch_sel = "10010" else
-- rx_ec_reg(19) when ec_ch_sel = "10011" else
-- rx_ec_reg(20) when ec_ch_sel = "10100" else
-- rx_ec_reg(21) when ec_ch_sel = "10101" else
-- rx_ec_reg(22) when ec_ch_sel = "10110" else
-- rx_ec_reg(23) when ec_ch_sel = "10111" else
-- rx_ec_reg(0);
ICEC_HDLC_TXRX_GEN : for i in GBT_NUM-1 downto 0 generate
IC_HDLC_TXRX_inst : entity work.HDLC_TXRX
generic map(
REG_WIDTH => REG_WIDTH
)
port map(
rx_long_data_reg_o => rx_ic_reg(i),
tx_long_data_reg_i => tx_ic_reg(i),
tx_trig_i => ic_trig(i), --one tx40m cycle
rx_trig_o => ic_int(i), --one rx40m cycle
txclk_40m => txclk_40m,
rxclk_40m => rxclk_40m,
IC_RX_2b => ICEC_RX_4b(i)(3 downto 2),
IC_TX_2b => ICEC_TX_4b(i)(3 downto 2)
);
EC_HDLC_TXRX_inst : entity work.HDLC_TXRX
generic map(
REG_WIDTH => 256
)
port map(
rx_long_data_reg_o => rx_ec_reg(i),
tx_long_data_reg_i => tx_ec_reg(i),
tx_trig_i => ec_trig(i), --one tx40m cycle
rx_trig_o => ec_int(i), --one rx40m cycle
txclk_40m => txclk_40m,
rxclk_40m => rxclk_40m,
IC_RX_2b => ICEC_RX_4b_i(i)(1 downto 0),
IC_TX_2b => ICEC_TX_4b_i(i)(1 downto 0)
);
process(rxclk_40m)
begin
if rxclk_40m'event and rxclk_40m='1' then
--if muxsel(i)='0' then
ICEC_RX_4b_i(i)(1) <= ICEC_RX_4b(i)(0);
ICEC_RX_4b_i(i)(0) <= ICEC_RX_4b(i)(1);
--else
-- ICEC_RX_4b_i(i)(0) <= ICEC_RX_4b(i)(0);
--ICEC_RX_4b_i(i)(1) <= ICEC_RX_4b(i)(1);
--end if;
end if;
end process;
ICEC_TX_4b(i)(0) <= ICEC_TX_4b_i(i)(1);
ICEC_TX_4b(i)(1) <= ICEC_TX_4b_i(i)(0);
end generate;
end behv;
|
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 65248)
`protect data_block
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`protect end_protected
|
entity tb_ent is
end tb_ent;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture behav of tb_ent is
-- Interrupt mapping register:
signal iar : unsigned(15 downto 0) := "0000000010010000";
signal ipend : unsigned(3 downto 0) := (others => '0');
signal irq : unsigned(3 downto 0);
signal clk : std_logic := '0';
begin
dut: entity work.ent
generic map (NUM_CHANNELS => 4)
port map (iar => iar, ipend => ipend, irq => irq, clk => clk);
process
begin
clk <= not clk;
wait for 1 ns;
end process;
stim:
process
begin
wait for 10 ns;
ipend(0) <= '1';
wait for 10 ns;
ipend(1) <= '1';
wait for 10 ns;
ipend(2) <= '1';
wait for 10 ns;
ipend <= (others => '0');
wait for 10 ns;
ipend(3) <= '1';
wait for 10 ns;
ipend(2) <= '1';
wait for 10 ns;
ipend(1) <= '1';
wait for 10 ns;
ipend <= (others => '0');
wait;
end process;
end behav;
|
/***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented by
/ Altera and Xilinx in their software.
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/
/
**************************************************************************************************/
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
library work;
use work.fixed_float_types.all;
use work.fixed_generic_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity pipelines_u is
generic(
LENGTH : natural
);
port(
clk : in std_ulogic;
input : in u_ufixed;
output : out u_ufixed
);
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture pipelines_u_1 of pipelines_u is
signal input_aux : std_ulogic_vector(input'length-1 downto 0);
signal output_aux : std_ulogic_vector(input'length-1 downto 0);
begin
pipelines_core_1:
entity work.pipelines_core
generic map(
LENGTH => LENGTH,
INPUT_HIGH => input'high,
INPUT_LOW => input'low
)
port map(
clk => clk,
input => input_aux,
output => output_aux
);
output <= to_ufixed(output_aux, input'high, input'low);
input_aux <= std_ulogic_vector(input);
end architecture; |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity feedforward_p_uOut_ram is
generic(
mem_type : string := "block";
dwidth : integer := 32;
awidth : integer := 8;
mem_size : integer := 140
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
d0 : in std_logic_vector(dwidth-1 downto 0);
we0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
addr1 : in std_logic_vector(awidth-1 downto 0);
ce1 : in std_logic;
q1 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of feedforward_p_uOut_ram is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
signal addr1_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
shared variable ram : mem_array;
attribute syn_ramstyle : string;
attribute syn_ramstyle of ram : variable is "block_ram";
attribute ram_style : string;
attribute ram_style of ram : variable is mem_type;
attribute EQUIVALENT_REGISTER_REMOVAL : string;
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_memory_access_0: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
if (we0 = '1') then
ram(CONV_INTEGER(addr0_tmp)) := d0;
end if;
q0 <= ram(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
memory_access_guard_1: process (addr1)
begin
addr1_tmp <= addr1;
--synthesis translate_off
if (CONV_INTEGER(addr1) > mem_size-1) then
addr1_tmp <= (others => '0');
else
addr1_tmp <= addr1;
end if;
--synthesis translate_on
end process;
p_memory_access_1: process (clk)
begin
if (clk'event and clk = '1') then
if (ce1 = '1') then
q1 <= ram(CONV_INTEGER(addr1_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity feedforward_p_uOut is
generic (
DataWidth : INTEGER := 32;
AddressRange : INTEGER := 140;
AddressWidth : INTEGER := 8);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of feedforward_p_uOut is
component feedforward_p_uOut_ram is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR;
we0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR;
addr1 : IN STD_LOGIC_VECTOR;
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR);
end component;
begin
feedforward_p_uOut_ram_U : component feedforward_p_uOut_ram
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
d0 => d0,
we0 => we0,
q0 => q0,
addr1 => address1,
ce1 => ce1,
q1 => q1);
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity feedforward_p_uOut_ram is
generic(
mem_type : string := "block";
dwidth : integer := 32;
awidth : integer := 8;
mem_size : integer := 140
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
d0 : in std_logic_vector(dwidth-1 downto 0);
we0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
addr1 : in std_logic_vector(awidth-1 downto 0);
ce1 : in std_logic;
q1 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of feedforward_p_uOut_ram is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
signal addr1_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
shared variable ram : mem_array;
attribute syn_ramstyle : string;
attribute syn_ramstyle of ram : variable is "block_ram";
attribute ram_style : string;
attribute ram_style of ram : variable is mem_type;
attribute EQUIVALENT_REGISTER_REMOVAL : string;
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_memory_access_0: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
if (we0 = '1') then
ram(CONV_INTEGER(addr0_tmp)) := d0;
end if;
q0 <= ram(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
memory_access_guard_1: process (addr1)
begin
addr1_tmp <= addr1;
--synthesis translate_off
if (CONV_INTEGER(addr1) > mem_size-1) then
addr1_tmp <= (others => '0');
else
addr1_tmp <= addr1;
end if;
--synthesis translate_on
end process;
p_memory_access_1: process (clk)
begin
if (clk'event and clk = '1') then
if (ce1 = '1') then
q1 <= ram(CONV_INTEGER(addr1_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity feedforward_p_uOut is
generic (
DataWidth : INTEGER := 32;
AddressRange : INTEGER := 140;
AddressWidth : INTEGER := 8);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of feedforward_p_uOut is
component feedforward_p_uOut_ram is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR;
we0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR;
addr1 : IN STD_LOGIC_VECTOR;
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR);
end component;
begin
feedforward_p_uOut_ram_U : component feedforward_p_uOut_ram
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
d0 => d0,
we0 => we0,
q0 => q0,
addr1 => address1,
ce1 => ce1,
q1 => q1);
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity feedforward_p_uOut_ram is
generic(
mem_type : string := "block";
dwidth : integer := 32;
awidth : integer := 8;
mem_size : integer := 140
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
d0 : in std_logic_vector(dwidth-1 downto 0);
we0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
addr1 : in std_logic_vector(awidth-1 downto 0);
ce1 : in std_logic;
q1 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of feedforward_p_uOut_ram is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
signal addr1_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
shared variable ram : mem_array;
attribute syn_ramstyle : string;
attribute syn_ramstyle of ram : variable is "block_ram";
attribute ram_style : string;
attribute ram_style of ram : variable is mem_type;
attribute EQUIVALENT_REGISTER_REMOVAL : string;
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_memory_access_0: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
if (we0 = '1') then
ram(CONV_INTEGER(addr0_tmp)) := d0;
end if;
q0 <= ram(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
memory_access_guard_1: process (addr1)
begin
addr1_tmp <= addr1;
--synthesis translate_off
if (CONV_INTEGER(addr1) > mem_size-1) then
addr1_tmp <= (others => '0');
else
addr1_tmp <= addr1;
end if;
--synthesis translate_on
end process;
p_memory_access_1: process (clk)
begin
if (clk'event and clk = '1') then
if (ce1 = '1') then
q1 <= ram(CONV_INTEGER(addr1_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity feedforward_p_uOut is
generic (
DataWidth : INTEGER := 32;
AddressRange : INTEGER := 140;
AddressWidth : INTEGER := 8);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of feedforward_p_uOut is
component feedforward_p_uOut_ram is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR;
we0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR;
addr1 : IN STD_LOGIC_VECTOR;
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR);
end component;
begin
feedforward_p_uOut_ram_U : component feedforward_p_uOut_ram
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
d0 => d0,
we0 => we0,
q0 => q0,
addr1 => address1,
ce1 => ce1,
q1 => q1);
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity feedforward_p_uOut_ram is
generic(
mem_type : string := "block";
dwidth : integer := 32;
awidth : integer := 8;
mem_size : integer := 140
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
d0 : in std_logic_vector(dwidth-1 downto 0);
we0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
addr1 : in std_logic_vector(awidth-1 downto 0);
ce1 : in std_logic;
q1 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of feedforward_p_uOut_ram is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
signal addr1_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
shared variable ram : mem_array;
attribute syn_ramstyle : string;
attribute syn_ramstyle of ram : variable is "block_ram";
attribute ram_style : string;
attribute ram_style of ram : variable is mem_type;
attribute EQUIVALENT_REGISTER_REMOVAL : string;
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_memory_access_0: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
if (we0 = '1') then
ram(CONV_INTEGER(addr0_tmp)) := d0;
end if;
q0 <= ram(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
memory_access_guard_1: process (addr1)
begin
addr1_tmp <= addr1;
--synthesis translate_off
if (CONV_INTEGER(addr1) > mem_size-1) then
addr1_tmp <= (others => '0');
else
addr1_tmp <= addr1;
end if;
--synthesis translate_on
end process;
p_memory_access_1: process (clk)
begin
if (clk'event and clk = '1') then
if (ce1 = '1') then
q1 <= ram(CONV_INTEGER(addr1_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity feedforward_p_uOut is
generic (
DataWidth : INTEGER := 32;
AddressRange : INTEGER := 140;
AddressWidth : INTEGER := 8);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of feedforward_p_uOut is
component feedforward_p_uOut_ram is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR;
we0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR;
addr1 : IN STD_LOGIC_VECTOR;
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR);
end component;
begin
feedforward_p_uOut_ram_U : component feedforward_p_uOut_ram
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
d0 => d0,
we0 => we0,
q0 => q0,
addr1 => address1,
ce1 => ce1,
q1 => q1);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Assume beginning of LVDS packet occurs at same time as
-- falling edge of I2S_SCLK where WS also falls (or
-- any multiple of exactly 8 bits later than this time).
-- This means that the first packet actually contains the
-- LSB of the last frame and then the seven MSBs of the
-- current frame, etc.
entity i2s_dio_2 is
port(
main_clk, reset, seq_reset: in std_logic;
--
i2s_out_dat, i2s_out_sh, i2s_out_ld: in std_logic;
i2s_in_ld, i2s_in_sh: in std_logic;
i2s_in_dat: out std_logic;
i2s_lr_st: in std_logic;
--
i2s_sclk: out std_logic;
i2s_ws: out std_logic;
i2s_din: in std_logic;
i2s_dout: out std_logic
);
end entity;
architecture a of i2s_dio_2 is
component sr8_rising is
port(
clk, reset: in std_logic;
ld, sh: in std_logic;
pin: in std_logic_vector(7 downto 0);
pout: out std_logic_vector(7 downto 0);
sin: in std_logic;
sout: out std_logic
);
end component;
component sr8_falling is
port(
clk, reset: in std_logic;
ld, sh: in std_logic;
pin: in std_logic_vector(7 downto 0);
pout: out std_logic_vector(7 downto 0);
sin: in std_logic;
sout: out std_logic
);
end component;
component r8_rising is
port(
clk, reset: in std_logic;
ld: in std_logic;
din: in std_logic_vector(7 downto 0);
dout: out std_logic_vector(7 downto 0)
);
end component;
signal out_1, out_2, out_3: std_logic_vector(7 downto 0);
signal in_1, in_2, in_3: std_logic_vector(7 downto 0);
signal lvds_bit_ctr: unsigned(4 downto 0);
signal cycle_begin: std_logic;
signal i2s_out_shiften, i2s_in_shiften: std_logic;
signal lrst_1: std_logic;
begin
-- SCLK is aligned to main_clk rising edge but 4x slower
i2s_sclk <= lvds_bit_ctr(1);
process(main_clk, reset) is begin
if reset = '1' then
lvds_bit_ctr <= "00000";
i2s_out_shiften <= '0';
i2s_in_shiften <= '0';
cycle_begin <= '0';
elsif rising_edge(main_clk) then
if seq_reset = '1' then
-- This happens at the start of bit 2 of a LVDS cycle
lvds_bit_ctr <= "00010";
else
lvds_bit_ctr <= lvds_bit_ctr + 1;
end if;
elsif falling_edge(main_clk) then
--
cycle_begin <= '0';
if lvds_bit_ctr = "11111" then
cycle_begin <= '1';
end if;
--
i2s_out_shiften <= '0';
if lvds_bit_ctr(1 downto 0) = "11" then
i2s_out_shiften <= '1';
end if;
--
i2s_in_shiften <= '0';
if lvds_bit_ctr(1 downto 0) = "01" then
i2s_in_shiften <= '1';
end if;
end if;
end process;
out_lvds_sr: sr8_rising port map(
clk => main_clk, reset => reset, ld => '0', sh => i2s_out_sh,
pin => "00000000", pout => out_1, sin => i2s_out_dat, sout => open
);
out_reg_1: r8_rising port map(
clk => main_clk, reset => reset, ld => i2s_out_ld, din => out_1, dout => out_2
);
out_reg_2: r8_rising port map(
clk => main_clk, reset => reset, ld => i2s_out_ld, din => out_2, dout => out_3
);
out_i2s_sr: sr8_rising port map(
clk => main_clk, reset => reset, ld => cycle_begin, sh => i2s_out_shiften,
pin => out_3, pout => open, sin => '0', sout => i2s_dout
);
in_i2s_sr: sr8_rising port map(
clk => main_clk, reset => reset, ld => '0', sh => i2s_in_shiften,
pin => "00000000", pout => in_1, sin => i2s_din, sout => open
);
in_reg_1: r8_rising port map(
clk => main_clk, reset => reset, ld => cycle_begin, din => in_1, dout => in_2
);
in_reg_2: r8_rising port map(
clk => main_clk, reset => reset, ld => cycle_begin, din => in_2, dout => in_3
);
in_lvds_sr: sr8_falling port map(
clk => main_clk, reset => reset, ld => i2s_in_ld, sh => i2s_in_sh,
pin => in_3, pout => open, sin => '0', sout => i2s_in_dat
);
process(main_clk, reset) is begin
if reset = '1' then
i2s_ws <= '0';
lrst_1 <= '0';
elsif rising_edge(main_clk) then
if cycle_begin = '1' then
i2s_ws <= lrst_1;
lrst_1 <= i2s_lr_st;
end if;
end if;
end process;
end architecture; |
architecture RTL of FIFO is
begin
process
begin
-- These are passing
ret := (
data => (others => '-'),
valid => '0',
sop => '0',
eop => '0',
empty => (others => '0'),
error => (others => '0')
);
-- These are failing
ret := (data => (others => '-'), valid => '0', sop => '0', eop => '0', empty => (others => '0'), error => (others => '0'));
end process;
end architecture RTL;
|
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`protect begin_protected
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`protect end_protected
|
------------------------------------------------------------------------------
-- axi_tpg.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: axi_tpg.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Mon Oct 22 10:34:41 2007 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_00_a;
use axi_lite_ipif_v1_00_a.axi_lite_ipif;
library axi_tpg_v2_00_a;
use axi_tpg_v2_00_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- AXI slave: base address
-- C_HIGHADDR -- AXI slave: high address
-- C_S_AXI_ADDR_WIDTH -- AXI address bus width - allowed value - 32 only
-- C_S_AXI_DATA_WIDTH -- AXI data bus width - allowed value - 32 or 64 only
-- C_S_AXI_ID_WIDTH -- AXI Identification TAG width - 1 to 16
-- C_S_AXI_CLK_FREQ_HZ -- AXI Clock Frequency in Hz
-- Not used:
-- C_S_AXI_SUPPORTS_NARROW = 1, DT = INTEGER, RANGE = (0:1), BUS = S_AXI
-- C_S_AXI_WRITE_ACCEPTANCE
-- C_S_AXI_READ_ACCEPTANCE
-- C_S_AXI_READ_ACCEPTANCE
-- C_S_AXI_SUPPORTS_NARROW_BURST
-- C_FAMILY -- Xilinx FPGA family
--
-- Definition of Ports:
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESETN -- AXI Reset - active low
--==================================
-- AXI Write Address Channel Signals
--==================================
-- S_AXI_AWID -- AXI Write Address ID
-- S_AXI_AWADDR -- AXI Write address - 32 bit
-- S_AXI_AWLEN -- AXI Write Data Length
-- S_AXI_AWSIZE -- AXI Burst Size - allowed values
-- -- 000 - byte burst
-- -- 001 - half word
-- -- 010 - word
-- -- 011 - double word
-- -- NA for all remaining values
-- S_AXI_AWBURST -- AXI Burst Type
-- -- 00 - Fixed
-- -- 01 - Incr
-- -- 10 - Wrap
-- -- 11 - Reserved
-- S_AXI_AWLOCK -- AXI Lock type
-- S_AXI_AWCACHE -- AXI Cache Type
-- S_AXI_AWPROT -- AXI Protection Type
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
--===============================
-- AXI Write Data Channel Signals
--===============================
-- S_AXI_WDATA -- AXI Write data width
-- S_AXI_WSTRB -- AXI Write strobes
-- S_AXI_WLAST -- AXI Last write indicator signal
-- S_AXI_WVALID -- AXI Write valid
-- S_AXI_WREADY -- AXI Write ready
--================================
-- AXI Write Data Response Signals
--================================
-- S_AXI_BID -- AXI Write Response channel number
-- S_AXI_BRESP -- AXI Write response
-- -- 00 - Okay
-- -- 01 - ExOkay
-- -- 10 - Slave Error
-- -- 11 - Decode Error
-- S_AXI_BVALID -- AXI Write response valid
-- S_AXI_BREADY -- AXI Response ready
--=================================
-- AXI Read Address Channel Signals
--=================================
-- S_AXI_ARID -- AXI Read ID
-- S_AXI_ARADDR -- AXI Read address
-- S_AXI_ARLEN -- AXI Read Data length
-- S_AXI_ARSIZE -- AXI Read Size
-- S_AXI_ARBURST -- AXI Read Burst length
-- S_AXI_ARLOCK -- AXI Read Lock
-- S_AXI_ARCACHE -- AXI Read Cache
-- S_AXI_ARPROT -- AXI Read Protection
-- S_AXI_RVALID -- AXI Read valid
-- S_AXI_RREADY -- AXI Read ready
--==============================
-- AXI Read Data Channel Signals
--==============================
-- S_AXI_RID -- AXI Read Channel ID
-- S_AXI_RDATA -- AXI Read data
-- S_AXI_RRESP -- AXI Read response
-- S_AXI_RLAST -- AXI Read Data Last signal
-- S_AXI_RVALID -- AXI Read address valid
-- S_AXI_RREADY -- AXI Read address ready
------------------------------------------------------------------------------
entity axi_tpg is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
C_CHROMA_FORMAT : integer := 0;
C_DATA_WIDTH : integer := 8;
C_NUM_CHANNELS : integer := 2;
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_S_AXI_ADDR_WIDTH : integer range 32 to 32 := 32;
C_S_AXI_DATA_WIDTH : integer range 32 to 64 := 32;
C_S_AXI_CLK_FREQ_HZ : integer := 100000000;
C_FAMILY : string := "virtex5"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
-- USER ports added here
clk : in STD_LOGIC;
-- XSVI input bus.
vsync_in : in std_logic;
hsync_in : in std_logic;
vblank_in : in std_logic;
hblank_in : in std_logic;
active_video_in : in std_logic;
video_data_in : in std_logic_vector((C_NUM_CHANNELS*C_DATA_WIDTH)-1 downto 0);
-- XSVI output bus.
vsync_out : out std_logic;
hsync_out : out std_logic;
vblank_out : out std_logic;
hblank_out : out std_logic;
active_video_out : out std_logic;
video_data_out : out std_logic_vector((C_NUM_CHANNELS*C_DATA_WIDTH)-1 downto 0);
-- Video out to VDMA to VFBC to MPMC to external memory
VDMA_wd_clk : out std_logic;
VDMA_wd_reset : out std_logic;
VDMA_video_out_we : out std_logic;
VDMA_video_out_full : in std_logic;
VDMA_video_data_out : out std_logic_vector((C_DATA_WIDTH*C_NUM_CHANNELS)-1 downto 0);
ZP_debug : out std_logic_vector(57 downto 0);
TPG_debug : out std_logic_vector(38 downto 0);
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
-- -- AXI Slave signals ------------------------------------------------------
-- -- AXI Global System Signals
S_AXI_ACLK : in std_logic := '0';
S_AXI_ARESETN : in std_logic := '1';
-- -- AXI Write Address Channel Signals
S_AXI_AWADDR : in std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0) := (others => '0');
S_AXI_AWVALID : in std_logic := '0';
S_AXI_AWREADY : out std_logic;
-- -- AXI Write Channel Signals
S_AXI_WDATA : in std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0) := (others => '0');
S_AXI_WSTRB : in std_logic_vector
(((C_S_AXI_DATA_WIDTH/8)-1) downto 0) := (others => '0');
S_AXI_WVALID : in std_logic := '0';
S_AXI_WREADY : out std_logic;
-- -- AXI Write Response Channel Signals
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic := '0';
-- -- AXI Read Address Channel Signals
S_AXI_ARADDR : in std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0) := (others => '0');
S_AXI_ARVALID : in std_logic := '0';
S_AXI_ARREADY : out std_logic := '0';
-- -- AXI Read Data Channel Signals
S_AXI_RDATA : out std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic := '0'
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of S_AXI_ACLK : signal is "CLK";
attribute SIGIS of S_AXI_ARESETN : signal is "RST";
end entity axi_tpg;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of axi_tpg is
------------------------------------------
-- Array of base/high address pairs for each address range
------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
------------------------------------------
-- Array of desired number of chip enables for each address range
------------------------------------------
constant USER_SLV_NUM_REG : integer := 8;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => pad_power2(USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Ratio of bus clock to core clock (for use in dual clock systems)
-- 1 = ratio is 1:1
-- 2 = ratio is 2:1
------------------------------------------
constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
------------------------------------------
-- Width of the slave data bus (32 only)
------------------------------------------
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
--function swap_endian (a : std_logic_vector) return std_logic_vector is
-- variable result : std_logic_vector(a'length-1 downto 0);
--begin
-- for i in result'RANGE loop
-- result(i) := a(a'length-1-i);
-- end loop;
-- return result;
--end;
signal le_ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal le_ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal le_ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal le_ipif_Bus2IP_CS : std_logic_vector(((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1 downto 0);
signal le_ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal le_ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal le_ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Reset : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1);
signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
signal t_vsync_out : std_logic;
signal t_video_data_out : std_logic_vector((C_NUM_CHANNELS*C_DATA_WIDTH)-1 downto 0);
signal t_active_video_out : std_logic;
signal red_out : std_logic_vector((C_DATA_WIDTH -1) downto 0);
signal green_out : std_logic_vector((C_DATA_WIDTH -1) downto 0);
signal blue_out : std_logic_vector((C_DATA_WIDTH -1) downto 0);
signal red_in : std_logic_vector((C_DATA_WIDTH -1) downto 0);
signal green_in : std_logic_vector((C_DATA_WIDTH -1) downto 0);
signal blue_in : std_logic_vector((C_DATA_WIDTH -1) downto 0);
begin
------------------------------------------
-- instantiate axi_lite_ipif
------------------------------------------
-------------------------------------------------------------------------
--REG_RESET_FROM_IPIF: convert active low to active high reset to rest of
-- the core.
-------------------------------------------------------------------------
REG_RESET_FROM_IPIF: process (S_AXI_ACLK) is
begin
if(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
ipif_Bus2IP_Reset <= not(ipif_Bus2IP_Resetn);
end if;
end process REG_RESET_FROM_IPIF;
-- ipif_Bus2IP_Addr <= swap_endian(le_ipif_Bus2IP_Addr);
-- ipif_Bus2IP_Data <= swap_endian(le_ipif_Bus2IP_Data);
-- ipif_Bus2IP_BE <= swap_endian(le_ipif_Bus2IP_BE);
-- ipif_Bus2IP_CS <= swap_endian(le_ipif_Bus2IP_CS);
-- ipif_Bus2IP_RdCE <= swap_endian(le_ipif_Bus2IP_RdCE);
-- ipif_Bus2IP_WrCE <= swap_endian(le_ipif_Bus2IP_WrCE);
-- le_ipif_IP2Bus_Data <= swap_endian(ipif_IP2Bus_Data);
ipif_Bus2IP_Addr <= le_ipif_Bus2IP_Addr;
ipif_Bus2IP_Data <= le_ipif_Bus2IP_Data;
ipif_Bus2IP_BE <= le_ipif_Bus2IP_BE;
ipif_Bus2IP_CS <= le_ipif_Bus2IP_CS;
ipif_Bus2IP_RdCE <= le_ipif_Bus2IP_RdCE;
ipif_Bus2IP_WrCE <= le_ipif_Bus2IP_WrCE;
le_ipif_IP2Bus_Data <= ipif_IP2Bus_Data;
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_00_a.axi_lite_ipif
generic map
(
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_MIN_SIZE => X"000003FF",
C_USE_WSTRB => 0,
C_DPHASE_TIMEOUT => 8,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
IP2Bus_Data => le_ipif_IP2Bus_Data, --swap_endian(ipif_IP2Bus_Data),
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
Bus2IP_Addr => le_ipif_Bus2IP_Addr,
Bus2IP_Data => le_ipif_Bus2IP_Data,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => le_ipif_Bus2IP_BE,
Bus2IP_CS => le_ipif_Bus2IP_CS,
Bus2IP_RdCE => le_ipif_Bus2IP_RdCE,
Bus2IP_WrCE => le_ipif_Bus2IP_WrCE
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity axi_tpg_v2_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
C_FAMILY => C_FAMILY,
C_Chroma_Format => C_CHROMA_FORMAT,
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_SLV_DWIDTH => USER_SLV_DWIDTH,
C_NUM_REG => USER_NUM_REG
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
clk => clk,
rst => ipif_Bus2IP_Reset,
vsync_in => vsync_in,
hsync_in => hsync_in,
vblank_in => vblank_in,
hblank_in => hblank_in,
de_in => active_video_in,
blue_in => blue_in,
green_in => green_in,
red_in => red_in,
vsync_out => t_vsync_out,
hsync_out => hsync_out,
vblank_out => vblank_out,
hblank_out => hblank_out,
de_out => t_active_video_out,
blue_out => blue_out,
green_out => green_out,
red_out => red_out,
ZP_debug => ZP_debug,
TPG_debug => TPG_debug,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
Select_2_Channels : if (C_NUM_CHANNELS = 2) generate
t_video_data_out((2*C_DATA_WIDTH)-1 downto C_DATA_WIDTH) <= green_out;
t_video_data_out(C_DATA_WIDTH-1 downto 0) <= red_out;
blue_in <= (others=> '0');
green_in <= video_data_in((2*C_DATA_WIDTH)-1 downto C_DATA_WIDTH);
red_in <= video_data_in(C_DATA_WIDTH-1 downto 0);
end generate;
Select_3_Channels : if (C_NUM_CHANNELS = 3) generate
t_video_data_out((3*C_DATA_WIDTH)-1 downto (2*C_DATA_WIDTH)) <= red_out;
t_video_data_out((2*C_DATA_WIDTH)-1 downto C_DATA_WIDTH) <= blue_out;
t_video_data_out(C_DATA_WIDTH-1 downto 0) <= green_out;
red_in <= video_data_in((3*C_DATA_WIDTH)-1 downto (2*C_DATA_WIDTH));
blue_in <= video_data_in((2*C_DATA_WIDTH)-1 downto C_DATA_WIDTH);
green_in <= video_data_in(C_DATA_WIDTH-1 downto 0);
end generate;
vsync_out <= t_vsync_out;
active_video_out <= t_active_video_out;
video_data_out <= t_video_data_out;
VDMA_wd_clk <= clk;
VDMA_wd_reset <= t_vsync_out;
VDMA_video_out_we <= t_active_video_out;
VDMA_video_data_out <= t_video_data_out;
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
end IMP;
|
-- brdConst_pkg (for Maker Board)
----------------------------------------------------------------------
-- (c) 2019 by Anton Mause
--
-- board/kit dependency : LEDs & SW polarity
--
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
----------------------------------------------------------------------
entity brdLexSwx is
port ( o_lex, o_pbx : out std_logic );
end brdLexSwx;
----------------------------------------------------------------------
architecture rtl of brdLexSwx is
begin
-- polarity of LED driver output
-- '0' = low idle, high active
-- '1' = high idle, low active
o_lex <= '1';
-- polarity of push button switch
-- '0' = low idle, high active (pressed)
-- '1' = high idle, low active (pressed)
o_pbx <= '0';
end rtl; |
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- * Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- * Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written agreement from the author.
--
-- * License is granted for non-commercial use only. A fee may not be charged
-- for redistributions as source code or in synthesized/hardware form without
-- specific prior written agreement from the author.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity i2s_intf is
generic (
mclk_rate : positive := 12000000;
sample_rate : positive := 8000;
preamble : positive := 1; -- I2S
word_length : positive := 16
);
port (
-- 2x MCLK in (e.g. 24 MHz for WM8731 USB mode)
clock_i : in std_logic;
reset_i : in std_logic;
-- Parallel IO
pcm_inl_o : out std_logic_vector(word_length - 1 downto 0);
pcm_inr_o : out std_logic_vector(word_length - 1 downto 0);
pcm_outl_i : in std_logic_vector(word_length - 1 downto 0);
pcm_outr_i : in std_logic_vector(word_length - 1 downto 0);
-- Codec interface (right justified mode)
-- MCLK is generated at half of the CLK input
i2s_mclk_o : out std_logic;
-- LRCLK is equal to the sample rate and is synchronous to
-- MCLK. It must be related to MCLK by the oversampling ratio
-- given in the codec datasheet.
i2s_lrclk_o : out std_logic;
-- Data is shifted out on the falling edge of BCLK, sampled
-- on the rising edge. The bit rate is determined such that
-- it is fast enough to fit preamble + word_length bits into
-- each LRCLK half cycle. The last cycle of each word may be
-- stretched to fit to LRCLK. This is OK at least for the
-- WM8731 codec.
-- The first falling edge of each timeslot is always synchronised
-- with the LRCLK edge.
i2s_bclk_o : out std_logic;
-- Output bitstream
i2s_d_o : out std_logic;
-- Input bitstream
i2s_d_i : in std_logic
);
end entity;
architecture rtl of i2s_intf is
constant ratio_mclk_fs : positive := (mclk_rate / sample_rate);
constant lrdivider_top : positive := ratio_mclk_fs - 1;
constant bdivider_top : positive := (ratio_mclk_fs / 4 / (preamble + word_length) * 2) - 1;
constant nbits : positive := preamble + word_length;
subtype lrdivider_t is integer range 0 to lrdivider_top;
subtype bdivider_t is integer range 0 to bdivider_top;
subtype bitcount_t is integer range 0 to nbits;
signal lrdivider : lrdivider_t;
signal bdivider : bdivider_t;
signal bitcount : bitcount_t;
signal mclk_r : std_logic;
signal lrclk_r : std_logic;
signal bclk_r : std_logic;
-- Shift register is long enough for the number of data bits
-- plus the preamble, plus an extra bit on the right to register
-- the incoming data
signal shiftreg : std_logic_vector(nbits downto 0);
begin
i2s_mclk_o <= mclk_r;
i2s_lrclk_o <= lrclk_r;
i2s_bclk_o <= bclk_r;
i2s_d_o <= shiftreg(nbits); -- data goes out MSb first
process(reset_i, clock_i)
begin
if reset_i = '1' then
pcm_inl_o <= (others => '0');
pcm_inr_o <= (others => '0');
-- Preload down-counters for clock generation
lrdivider <= lrdivider_top;
bdivider <= bdivider_top;
bitcount <= nbits;
mclk_r <= '0';
lrclk_r <= '0';
bclk_r <= '0';
shiftreg <= (others => '0');
elsif rising_edge(clock_i) then
-- Generate MCLK at half input clock rate
mclk_r <= not mclk_r;
-- Generate LRCLK at rate specified by codec configuration
if lrdivider = 0 then
-- LRCLK divider has reached 0 - start again from the top
lrdivider <= lrdivider_top;
-- Generate LRCLK edge and sync the BCLK counter
lrclk_r <= not lrclk_r;
bclk_r <= '0';
bitcount <= nbits; -- 1 extra required for setup
bdivider <= bdivider_top;
-- Load shift register with output data padding preamble
-- with 0s. Load output buses with input word from the
-- previous timeslot.
shiftreg(nbits downto nbits - preamble + 1) <= (others => '0');
if lrclk_r = '0' then
-- Previous channel input is LEFT. This is available in the
-- shift register at the end of a cycle, right justified
pcm_inl_o <= shiftreg(word_length - 1 downto 0);
-- Next channel to output is RIGHT. Load this into the
-- shift register at the start of a cycle, left justified
shiftreg(word_length downto 1) <= pcm_outr_i;
else
-- Previous channel input is RIGHT
pcm_inr_o <= shiftreg(word_length - 1 downto 0);
-- Next channel is LEFT
shiftreg(word_length downto 1) <= pcm_outl_i;
end if;
else
-- Decrement the LRCLK counter
lrdivider <= lrdivider - 1;
-- Generate BCLK at a suitable rate to fit the required number
-- of bits into each timeslot. Data is changed on the falling edge,
-- sampled on the rising edge
if bdivider = 0 then
-- If all bits have been output for this phase then
-- stop and wait to sync back up with LRCLK
if bitcount > 0 then
-- Reset
bdivider <= bdivider_top;
-- Toggle BCLK
bclk_r <= not bclk_r;
if bclk_r = '0' then
-- Rising edge - shift in current bit and decrement bit counter
bitcount <= bitcount - 1;
shiftreg(0) <= i2s_d_i;
else
-- Falling edge - shift out next bit
shiftreg(nbits downto 1) <= shiftreg(nbits - 1 downto 0);
end if;
end if;
else
-- Decrement the BCLK counter
bdivider <= bdivider - 1;
end if;
end if;
end if;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity clkkey is
port
(
clkkey_port_clk: in std_logic;
clkkey_clk: out std_logic
);
end clkkey;
architecture Behavioral of clkkey is
begin
clkkey_clk <= clkkey_port_clk;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
entity lfsr_tb is
generic (
LFSR_LENGTH : positive := 8;
DUMP_FILE : string := string'("lfsr_dump.txt"));
end entity;
architecture sim of lfsr_tb is
file dump : text open write_mode is DUMP_FILE;
component lfsr is
generic (
INTERNAL_SIZE : positive;
SEED : natural);
port (
clk : in std_logic;
rst : in std_logic;
q : out std_logic_vector);
end component;
constant clk_p : time := 2 ns;
signal clk : std_logic := '0'; -- clock for uut
signal rst : std_logic := '0'; -- reset for uut
signal q : std_logic_vector((LFSR_LENGTH - 1) downto 0); -- LFSR out vector
-- Record all values output by LFSR. Set chosen(q) to '1' on each clock cycle
signal chosen : std_logic_vector(((2 ** q'length) -2) downto 0);
-- If LFSR is maximal length, then chosen will match this after
-- 2**LFSR_LENGTH - 1 clock cycles.
constant ALL_CHOSEN : std_logic_vector(chosen'range) := (others => '1');
begin
-- Instantiate the LFSR to test
uut : lfsr
generic map (
INTERNAL_SIZE => LFSR_LENGTH,
SEED => 1
) port map (
clk => clk,
rst => rst,
q => q);
-- Generate clock
clk_gen : process
begin
clk <= not clk;
wait for (clk_p / 2);
end process;
-- Generate Reset signal for 1 clock cycle
rst_proc : process
begin
rst <= '1';
wait for clk_p;
rst <= '0';
wait;
end process;
-- Record each output from LFSR into 'chosen' and file.
record_output : process
variable value : integer;
variable buf : line;
begin
wait for clk_p;
value := to_integer(unsigned(q));
write(buf, value);
writeline(dump, buf);
chosen(value) <= '1';
end process;
-- Check to see if LFSR has iterated over all values.
check_states : process
variable buf : line;
begin
wait for (clk_p * (2 ** LFSR_LENGTH)); -- Give 1 extra cycle for reset.
if chosen = ALL_CHOSEN then
write(buf, string'("Maximal LFSR"));
else
write(buf, string'("Non-maximal LFSR"));
end if;
writeline(output, buf);
wait;
end process;
end sim;
|
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Company:LAAS-CNRS
-- Author:Jonathan Piat <piat.jonathan@gmail.com>
--
-- Create Date: 10:54:36 06/19/2012
-- Design Name:
-- Module Name: fifo_peripheral - Behavioral
-- Project Name:
-- Target Devices: Spartan 6 Spartan 6
-- Tool versions: ISE 14.1 ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
library work ;
use work.logi_utils_pack.all ;
--! peripheral with fifo interface to the logic
--! fifo B can be written from logic and read from bus
--! fifo A can be written from bus and read from logic
entity wishbone_to_xil_fifo is
generic( ADDR_WIDTH: positive := 16; --! width of the address bus
WIDTH : positive := 16; --! width of the data bus
WR_FIFO_SIZE : natural := 128;
RD_FIFO_SIZE : natural := 128
);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(ADDR_WIDTH-1 downto 0) ;
wbs_writedata : in std_logic_vector( WIDTH-1 downto 0);
wbs_readdata : out std_logic_vector( WIDTH-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- fifo signals
fifo_rst : out std_logic;
-- write xil_fifo signals
wr_clk : out std_logic ;
dout : out std_logic_vector(15 downto 0);
wr_en : out std_logic ;
full : in std_logic ;
wr_data_count : in std_logic_vector(15 downto 0);
overflow : in std_logic;
-- read xil_fifo signals
rd_clk : out std_logic ;
din : in std_logic_vector(15 downto 0);
rd_en : out std_logic ;
empty : in std_logic ;
rd_data_count : in std_logic_vector(15 downto 0);
underflow : in std_logic
);
end wishbone_to_xil_fifo;
architecture RTL of wishbone_to_xil_fifo is
constant address_space_nbit : integer := MAX(nbit(WR_FIFO_SIZE), nbit(RD_FIFO_SIZE));
signal write_ack, read_ack : std_logic ;
signal gls_resetn : std_logic ;
signal control_latched : std_logic_vector(15 downto 0) ;
signal control_data, fifo_status : std_logic_vector(15 downto 0) ;
signal fifo_data : std_logic_vector(15 downto 0) ;
signal data_access : std_logic ;
signal control_space_data_spacen : std_logic ;
begin
rd_clk <= gls_clk ;
wr_clk <= gls_clk ;
gls_resetn <= NOT gls_reset ;
write_bloc : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
write_ack <= '0';
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then
write_ack <= '1';
else
write_ack <= '0';
end if;
end if;
end process write_bloc;
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
elsif rising_edge(gls_clk) then
control_latched <= control_data ;
if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' ) then
read_ack <= '1';
else
read_ack <= '0';
end if;
end if;
end process read_bloc;
wbs_ack <= read_ack or write_ack;
control_space_data_spacen <= wbs_address(address_space_nbit) ;
wbs_readdata <= control_latched when control_space_data_spacen = '1' else --data_access = '0' else
fifo_data ;
rd_en <= '1' when control_space_data_spacen = '0' and wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' and read_ack = '0' else
'0' ;
wr_en <= '1' when control_space_data_spacen = '0' and (wbs_strobe and wbs_write and wbs_cycle)= '1' and write_ack = '0' else
'0' ;
with conv_integer(wbs_address(address_space_nbit-1 downto 0)) select
control_data <= std_logic_vector(to_unsigned(RD_FIFO_SIZE, 16)) when 0,
std_logic_vector(to_unsigned(WR_FIFO_SIZE, 16)) when 1,
std_logic_vector(resize(unsigned(rd_data_count), 16)) when 2,
std_logic_vector(resize(unsigned(wr_data_count), 16)) when 3,
fifo_status when others;
fifo_status <= X"000" & empty & underflow & full & overflow ;
fifo_rst <= '1' when gls_reset = '1' else
'1' when control_space_data_spacen = '1' and (wbs_strobe and wbs_write and wbs_cycle)= '1' else
'0' ;
dout <= wbs_writedata ;
process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
fifo_data <= (others => '0');
elsif rising_edge(gls_clk) then
if control_space_data_spacen = '0' and wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' and read_ack = '0' then
fifo_data <= din ;
end if ;
end if;
end process;
end RTL;
|
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Company:LAAS-CNRS
-- Author:Jonathan Piat <piat.jonathan@gmail.com>
--
-- Create Date: 10:54:36 06/19/2012
-- Design Name:
-- Module Name: fifo_peripheral - Behavioral
-- Project Name:
-- Target Devices: Spartan 6 Spartan 6
-- Tool versions: ISE 14.1 ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
library work ;
use work.logi_utils_pack.all ;
--! peripheral with fifo interface to the logic
--! fifo B can be written from logic and read from bus
--! fifo A can be written from bus and read from logic
entity wishbone_to_xil_fifo is
generic( ADDR_WIDTH: positive := 16; --! width of the address bus
WIDTH : positive := 16; --! width of the data bus
WR_FIFO_SIZE : natural := 128;
RD_FIFO_SIZE : natural := 128
);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(ADDR_WIDTH-1 downto 0) ;
wbs_writedata : in std_logic_vector( WIDTH-1 downto 0);
wbs_readdata : out std_logic_vector( WIDTH-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- fifo signals
fifo_rst : out std_logic;
-- write xil_fifo signals
wr_clk : out std_logic ;
dout : out std_logic_vector(15 downto 0);
wr_en : out std_logic ;
full : in std_logic ;
wr_data_count : in std_logic_vector(15 downto 0);
overflow : in std_logic;
-- read xil_fifo signals
rd_clk : out std_logic ;
din : in std_logic_vector(15 downto 0);
rd_en : out std_logic ;
empty : in std_logic ;
rd_data_count : in std_logic_vector(15 downto 0);
underflow : in std_logic
);
end wishbone_to_xil_fifo;
architecture RTL of wishbone_to_xil_fifo is
constant address_space_nbit : integer := MAX(nbit(WR_FIFO_SIZE), nbit(RD_FIFO_SIZE));
signal write_ack, read_ack : std_logic ;
signal gls_resetn : std_logic ;
signal control_latched : std_logic_vector(15 downto 0) ;
signal control_data, fifo_status : std_logic_vector(15 downto 0) ;
signal fifo_data : std_logic_vector(15 downto 0) ;
signal data_access : std_logic ;
signal control_space_data_spacen : std_logic ;
begin
rd_clk <= gls_clk ;
wr_clk <= gls_clk ;
gls_resetn <= NOT gls_reset ;
write_bloc : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
write_ack <= '0';
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then
write_ack <= '1';
else
write_ack <= '0';
end if;
end if;
end process write_bloc;
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
elsif rising_edge(gls_clk) then
control_latched <= control_data ;
if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' ) then
read_ack <= '1';
else
read_ack <= '0';
end if;
end if;
end process read_bloc;
wbs_ack <= read_ack or write_ack;
control_space_data_spacen <= wbs_address(address_space_nbit) ;
wbs_readdata <= control_latched when control_space_data_spacen = '1' else --data_access = '0' else
fifo_data ;
rd_en <= '1' when control_space_data_spacen = '0' and wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' and read_ack = '0' else
'0' ;
wr_en <= '1' when control_space_data_spacen = '0' and (wbs_strobe and wbs_write and wbs_cycle)= '1' and write_ack = '0' else
'0' ;
with conv_integer(wbs_address(address_space_nbit-1 downto 0)) select
control_data <= std_logic_vector(to_unsigned(RD_FIFO_SIZE, 16)) when 0,
std_logic_vector(to_unsigned(WR_FIFO_SIZE, 16)) when 1,
std_logic_vector(resize(unsigned(rd_data_count), 16)) when 2,
std_logic_vector(resize(unsigned(wr_data_count), 16)) when 3,
fifo_status when others;
fifo_status <= X"000" & empty & underflow & full & overflow ;
fifo_rst <= '1' when gls_reset = '1' else
'1' when control_space_data_spacen = '1' and (wbs_strobe and wbs_write and wbs_cycle)= '1' else
'0' ;
dout <= wbs_writedata ;
process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
fifo_data <= (others => '0');
elsif rising_edge(gls_clk) then
if control_space_data_spacen = '0' and wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' and read_ack = '0' then
fifo_data <= din ;
end if ;
end if;
end process;
end RTL;
|
architecture RTL of FIFO is
begin
FOR_LABEL : for i in 0 to 7 generate
end generate FOR_LABEL;
IF_LABEL : if a = '1' generate
end generate IF_LABEL;
CASE_LABEL : case data generate
end generate CASE_LABEL;
-- Violations below
FOR_LABEL : for i in 0 to 7 generate
end generate FOR_LABEL;
IF_LABEL : if a = '1' generate
end generate IF_LABEL1;
CASE_LABEL : case data generate
end generate CASE_LABEL;
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: tap_xilinx
-- File: tap_xilinx.vhd
-- Author: Edvin Catovic, Jiri Gaisler - Gaisler Research
-- Description: Xilinx TAP controllers wrappers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity virtex_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of virtex_tap is
component BSCAN_VIRTEX
port (CAPTURE : out STD_ULOGIC;
DRCK1 : out STD_ULOGIC;
DRCK2 : out STD_ULOGIC;
RESET : out STD_ULOGIC;
SEL1 : out STD_ULOGIC;
SEL2 : out STD_ULOGIC;
SHIFT : out STD_ULOGIC;
TDI : out STD_ULOGIC;
UPDATE : out STD_ULOGIC;
TDO1 : in STD_ULOGIC;
TDO2 : in STD_ULOGIC);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
begin
u0 : BSCAN_VIRTEX
port map (
DRCK1 => drck1,
DRCK2 => drck2,
RESET => tapo_rst,
SEL1 => sel1,
SEL2 => sel2,
SHIFT => tapo_shft,
TDI => tapo_tdi,
UPDATE => tapo_upd,
TDO1 => tapi_tdo1,
TDO2 => tapi_tdo2);
tapo_tck <= drck1 when sel1 = '1' else drck2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2; tapo_capt <= '0';
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity virtex2_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of virtex2_tap is
component BSCAN_VIRTEX2
port (CAPTURE : out STD_ULOGIC;
DRCK1 : out STD_ULOGIC;
DRCK2 : out STD_ULOGIC;
RESET : out STD_ULOGIC;
SEL1 : out STD_ULOGIC;
SEL2 : out STD_ULOGIC;
SHIFT : out STD_ULOGIC;
TDI : out STD_ULOGIC;
UPDATE : out STD_ULOGIC;
TDO1 : in STD_ULOGIC;
TDO2 : in STD_ULOGIC);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
begin
u0 : BSCAN_VIRTEX2
port map (CAPTURE => tapo_capt,
DRCK1 => drck1,
DRCK2 => drck2,
RESET => tapo_rst,
SEL1 => sel1,
SEL2 => sel2,
SHIFT => tapo_shft,
TDI => tapo_tdi,
UPDATE => tapo_upd,
TDO1 => tapi_tdo1,
TDO2 => tapi_tdo2);
tapo_tck <= drck1 when sel1 = '1' else drck2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BSCAN_SPARTAN3;
-- pragma translate_on
entity spartan3_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of spartan3_tap is
component BSCAN_SPARTAN3
port (CAPTURE : out STD_ULOGIC;
DRCK1 : out STD_ULOGIC;
DRCK2 : out STD_ULOGIC;
RESET : out STD_ULOGIC;
SEL1 : out STD_ULOGIC;
SEL2 : out STD_ULOGIC;
SHIFT : out STD_ULOGIC;
TDI : out STD_ULOGIC;
UPDATE : out STD_ULOGIC;
TDO1 : in STD_ULOGIC;
TDO2 : in STD_ULOGIC);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
begin
u0 : BSCAN_SPARTAN3
port map (CAPTURE => tapo_capt,
DRCK1 => drck1,
DRCK2 => drck2,
RESET => tapo_rst,
SEL1 => sel1,
SEL2 => sel2,
SHIFT => tapo_shft,
TDI => tapo_tdi,
UPDATE => tapo_upd,
TDO1 => tapi_tdo1,
TDO2 => tapi_tdo2);
tapo_tck <= drck1 when sel1 = '1' else drck2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BSCAN_VIRTEX4;
-- pragma translate_on
entity virtex4_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of virtex4_tap is
component BSCAN_VIRTEX4 generic ( JTAG_CHAIN : integer := 1);
port ( CAPTURE : out std_ulogic;
DRCK : out std_ulogic;
RESET : out std_ulogic;
SEL : out std_ulogic;
SHIFT : out std_ulogic;
TDI : out std_ulogic;
UPDATE : out std_ulogic;
TDO : in std_ulogic);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
signal capt1, capt2, rst1, rst2 : std_ulogic;
signal shift1, shift2, tdi1, tdi2 : std_ulogic;
signal update1, update2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
attribute dont_touch of u1 : label is true;
begin
u0 : BSCAN_VIRTEX4
generic map (JTAG_CHAIN => 1)
port map (
CAPTURE => capt1,
DRCK => drck1,
RESET => rst1,
SEL => sel1,
SHIFT => shift1,
TDI => tdi1,
UPDATE => update1,
TDO => tapi_tdo1
);
u1 : BSCAN_VIRTEX4
generic map (JTAG_CHAIN => 2)
port map (
CAPTURE => capt2,
DRCK => drck2,
RESET => rst2,
SEL => sel2,
SHIFT => shift2,
TDI => tdi2,
UPDATE => update2,
TDO => tapi_tdo2
);
tapo_capt <= capt1 when sel1 = '1' else capt2;
tapo_tck <= drck1 when sel1 = '1' else drck2;
tapo_rst <= rst1 when sel1 = '1' else rst2;
tapo_shft <= shift1 when sel1 = '1' else shift2;
tapo_tdi <= tdi1 when sel1 = '1' else tdi2;
tapo_upd <= update1 when sel1 ='1' else update2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BSCAN_VIRTEX5;
-- pragma translate_on
entity virtex5_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of virtex5_tap is
component BSCAN_VIRTEX5 generic ( JTAG_CHAIN : integer := 1);
port ( CAPTURE : out std_ulogic;
DRCK : out std_ulogic;
RESET : out std_ulogic;
SEL : out std_ulogic;
SHIFT : out std_ulogic;
TDI : out std_ulogic;
UPDATE : out std_ulogic;
TDO : in std_ulogic);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
signal capt1, capt2, rst1, rst2 : std_ulogic;
signal shift1, shift2, tdi1, tdi2 : std_ulogic;
signal update1, update2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
attribute dont_touch of u1 : label is true;
begin
u0 : BSCAN_VIRTEX5
generic map (JTAG_CHAIN => 1)
port map (
CAPTURE => capt1,
DRCK => drck1,
RESET => rst1,
SEL => sel1,
SHIFT => shift1,
TDI => tdi1,
UPDATE => update1,
TDO => tapi_tdo1
);
u1 : BSCAN_VIRTEX5
generic map (JTAG_CHAIN => 2)
port map (
CAPTURE => capt2,
DRCK => drck2,
RESET => rst2,
SEL => sel2,
SHIFT => shift2,
TDI => tdi2,
UPDATE => update2,
TDO => tapi_tdo2
);
tapo_capt <= capt1 when sel1 = '1' else capt2;
tapo_tck <= drck1 when sel1 = '1' else drck2;
tapo_rst <= rst1 when sel1 = '1' else rst2;
tapo_shft <= shift1 when sel1 = '1' else shift2;
tapo_tdi <= tdi1 when sel1 = '1' else tdi2;
tapo_upd <= update1 when sel1 ='1' else update2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity virtex6_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of virtex6_tap is
component BSCAN_VIRTEX6
generic (
DISABLE_JTAG : boolean := FALSE;
JTAG_CHAIN : integer := 1
);
port (
CAPTURE : out std_ulogic := 'H';
DRCK : out std_ulogic := 'H';
RESET : out std_ulogic := 'H';
RUNTEST : out std_ulogic := 'L';
SEL : out std_ulogic := 'L';
SHIFT : out std_ulogic := 'L';
TCK : out std_ulogic := 'L';
TDI : out std_ulogic := 'L';
TMS : out std_ulogic := 'L';
UPDATE : out std_ulogic := 'L';
TDO : in std_ulogic := 'X'
);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
signal capt1, capt2, rst1, rst2 : std_ulogic;
signal shift1, shift2, tdi1, tdi2 : std_ulogic;
signal update1, update2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
attribute dont_touch of u1 : label is true;
begin
u0 : BSCAN_VIRTEX6
generic map (JTAG_CHAIN => 1)
port map (
CAPTURE => capt1,
DRCK => drck1,
RESET => rst1,
SEL => sel1,
SHIFT => shift1,
TDI => tdi1,
UPDATE => update1,
TDO => tapi_tdo1,
TCK => tapo_tck
);
u1 : BSCAN_VIRTEX6
generic map (JTAG_CHAIN => 2)
port map (
CAPTURE => capt2,
DRCK => drck2,
RESET => rst2,
SEL => sel2,
SHIFT => shift2,
TDI => tdi2,
UPDATE => update2,
TDO => tapi_tdo2
);
tapo_capt <= capt1 when sel1 = '1' else capt2;
tapo_rst <= rst1 when sel1 = '1' else rst2;
tapo_shft <= shift1 when sel1 = '1' else shift2;
tapo_tdi <= tdi1 when sel1 = '1' else tdi2;
tapo_upd <= update1 when sel1 ='1' else update2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity spartan6_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of spartan6_tap is
component BSCAN_SPARTAN6
generic (
JTAG_CHAIN : integer := 1
);
port (
CAPTURE : out std_ulogic := 'H';
DRCK : out std_ulogic := 'H';
RESET : out std_ulogic := 'H';
RUNTEST : out std_ulogic := 'L';
SEL : out std_ulogic := 'L';
SHIFT : out std_ulogic := 'L';
TCK : out std_ulogic := 'L';
TDI : out std_ulogic := 'L';
TMS : out std_ulogic := 'L';
UPDATE : out std_ulogic := 'L';
TDO : in std_ulogic := 'X'
);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
signal capt1, capt2, rst1, rst2 : std_ulogic;
signal shift1, shift2, tdi1, tdi2 : std_ulogic;
signal update1, update2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
attribute dont_touch of u1 : label is true;
begin
u0 : BSCAN_SPARTAN6
generic map (JTAG_CHAIN => 1)
port map (
CAPTURE => capt1,
DRCK => drck1,
RESET => rst1,
SEL => sel1,
SHIFT => shift1,
TDI => tdi1,
UPDATE => update1,
TDO => tapi_tdo1,
TCK => tapo_tck
);
u1 : BSCAN_SPARTAN6
generic map (JTAG_CHAIN => 2)
port map (
CAPTURE => capt2,
DRCK => drck2,
RESET => rst2,
SEL => sel2,
SHIFT => shift2,
TDI => tdi2,
UPDATE => update2,
TDO => tapi_tdo2
);
tapo_capt <= capt1 when sel1 = '1' else capt2;
tapo_rst <= rst1 when sel1 = '1' else rst2;
tapo_shft <= shift1 when sel1 = '1' else shift2;
tapo_tdi <= tdi1 when sel1 = '1' else tdi2;
tapo_upd <= update1 when sel1 ='1' else update2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity virtex7_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of virtex7_tap is
component BSCANE2
generic (
DISABLE_JTAG : string := "FALSE";
JTAG_CHAIN : integer := 1
);
port (
CAPTURE : out std_ulogic := 'H';
DRCK : out std_ulogic := 'H';
RESET : out std_ulogic := 'H';
RUNTEST : out std_ulogic := 'L';
SEL : out std_ulogic := 'L';
SHIFT : out std_ulogic := 'L';
TCK : out std_ulogic := 'L';
TDI : out std_ulogic := 'L';
TMS : out std_ulogic := 'L';
UPDATE : out std_ulogic := 'L';
TDO : in std_ulogic := 'X'
);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
signal capt1, capt2, rst1, rst2 : std_ulogic;
signal shift1, shift2, tdi1, tdi2 : std_ulogic;
signal update1, update2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
attribute dont_touch of u1 : label is true;
begin
u0 : BSCANE2
generic map (JTAG_CHAIN => 1)
port map (
CAPTURE => capt1,
DRCK => drck1,
RESET => rst1,
SEL => sel1,
SHIFT => shift1,
TDI => tdi1,
UPDATE => update1,
TDO => tapi_tdo1,
TCK => tapo_tck
);
u1 : BSCANE2
generic map (JTAG_CHAIN => 2)
port map (
CAPTURE => capt2,
DRCK => drck2,
RESET => rst2,
SEL => sel2,
SHIFT => shift2,
TDI => tdi2,
UPDATE => update2,
TDO => tapi_tdo2
);
tapo_capt <= capt1 when sel1 = '1' else capt2;
tapo_rst <= rst1 when sel1 = '1' else rst2;
tapo_shft <= shift1 when sel1 = '1' else shift2;
tapo_tdi <= tdi1 when sel1 = '1' else tdi2;
tapo_upd <= update1 when sel1 ='1' else update2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity kintex7_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of kintex7_tap is
component BSCANE2
generic (
DISABLE_JTAG : string := "FALSE";
JTAG_CHAIN : integer := 1
);
port (
CAPTURE : out std_ulogic := 'H';
DRCK : out std_ulogic := 'H';
RESET : out std_ulogic := 'H';
RUNTEST : out std_ulogic := 'L';
SEL : out std_ulogic := 'L';
SHIFT : out std_ulogic := 'L';
TCK : out std_ulogic := 'L';
TDI : out std_ulogic := 'L';
TMS : out std_ulogic := 'L';
UPDATE : out std_ulogic := 'L';
TDO : in std_ulogic := 'X'
);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
signal capt1, capt2, rst1, rst2 : std_ulogic;
signal shift1, shift2, tdi1, tdi2 : std_ulogic;
signal update1, update2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
attribute dont_touch of u1 : label is true;
begin
u0 : BSCANE2
generic map (JTAG_CHAIN => 1)
port map (
CAPTURE => capt1,
DRCK => drck1,
RESET => rst1,
SEL => sel1,
SHIFT => shift1,
TDI => tdi1,
UPDATE => update1,
TDO => tapi_tdo1,
TCK => tapo_tck
);
u1 : BSCANE2
generic map (JTAG_CHAIN => 2)
port map (
CAPTURE => capt2,
DRCK => drck2,
RESET => rst2,
SEL => sel2,
SHIFT => shift2,
TDI => tdi2,
UPDATE => update2,
TDO => tapi_tdo2
);
tapo_capt <= capt1 when sel1 = '1' else capt2;
tapo_rst <= rst1 when sel1 = '1' else rst2;
tapo_shft <= shift1 when sel1 = '1' else shift2;
tapo_tdi <= tdi1 when sel1 = '1' else tdi2;
tapo_upd <= update1 when sel1 ='1' else update2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity artix7_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of artix7_tap is
component BSCANE2
generic (
DISABLE_JTAG : string := "FALSE";
JTAG_CHAIN : integer := 1
);
port (
CAPTURE : out std_ulogic := 'H';
DRCK : out std_ulogic := 'H';
RESET : out std_ulogic := 'H';
RUNTEST : out std_ulogic := 'L';
SEL : out std_ulogic := 'L';
SHIFT : out std_ulogic := 'L';
TCK : out std_ulogic := 'L';
TDI : out std_ulogic := 'L';
TMS : out std_ulogic := 'L';
UPDATE : out std_ulogic := 'L';
TDO : in std_ulogic := 'X'
);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
signal capt1, capt2, rst1, rst2 : std_ulogic;
signal shift1, shift2, tdi1, tdi2 : std_ulogic;
signal update1, update2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
attribute dont_touch of u1 : label is true;
begin
u0 : BSCANE2
generic map (JTAG_CHAIN => 1)
port map (
CAPTURE => capt1,
DRCK => drck1,
RESET => rst1,
SEL => sel1,
SHIFT => shift1,
TDI => tdi1,
UPDATE => update1,
TDO => tapi_tdo1,
TCK => tapo_tck
);
u1 : BSCANE2
generic map (JTAG_CHAIN => 2)
port map (
CAPTURE => capt2,
DRCK => drck2,
RESET => rst2,
SEL => sel2,
SHIFT => shift2,
TDI => tdi2,
UPDATE => update2,
TDO => tapi_tdo2
);
tapo_capt <= capt1 when sel1 = '1' else capt2;
tapo_rst <= rst1 when sel1 = '1' else rst2;
tapo_shft <= shift1 when sel1 = '1' else shift2;
tapo_tdi <= tdi1 when sel1 = '1' else tdi2;
tapo_upd <= update1 when sel1 ='1' else update2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1012.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p10n01i01012ent IS
port (p,q: in bit);
END c06s03b00x00p10n01i01012ent;
ARCHITECTURE c06s03b00x00p10n01i01012arch OF c06s03b00x00p10n01i01012ent IS
BEGIN
TESTING: PROCESS(c06s03b00x00p10n01i01012ent.p, c06s03b00x00p10n01i01012ent.q)
BEGIN
assert FALSE
report "***PASSED TEST: c06s03b00x00p10n01i01012"
severity NOTE;
END PROCESS TESTING;
END c06s03b00x00p10n01i01012arch;
|
architecture RTL of FIFO is
begin
process
begin
for_label : for index in 4 to 23 loop
end loop FOR_LABEL;
FOR_LABEL : for index in 4 to 23 loop
end loop FOR_LABEL;
For_label : for index in 4 to 23 loop
end loop FOR_LABEL;
end process;
end;
|
-- file dummy.vhd
package COMPONENTS is
component DUMMY_MODULE
port (I : in bit; O : out bit);
end component;
end package;
entity DUMMY_MODULE is
port (I: in bit; O: out bit);
end entity;
architecture RTL of DUMMY_MODULE is
begin
O <= I;
end architecture;
-- file dummy_top.vhd
library DUMMY;
use DUMMY.COMPONENTS.DUMMY_MODULE;
entity DUMMY_TOP is
port (I : in bit; O : out bit);
end entity;
architecture RTL of DUMMY_TOP is
begin
U: DUMMY_MODULE port map(I=>I, O=>O);
end architecture;
|
-- file dummy.vhd
package COMPONENTS is
component DUMMY_MODULE
port (I : in bit; O : out bit);
end component;
end package;
entity DUMMY_MODULE is
port (I: in bit; O: out bit);
end entity;
architecture RTL of DUMMY_MODULE is
begin
O <= I;
end architecture;
-- file dummy_top.vhd
library DUMMY;
use DUMMY.COMPONENTS.DUMMY_MODULE;
entity DUMMY_TOP is
port (I : in bit; O : out bit);
end entity;
architecture RTL of DUMMY_TOP is
begin
U: DUMMY_MODULE port map(I=>I, O=>O);
end architecture;
|
-- file dummy.vhd
package COMPONENTS is
component DUMMY_MODULE
port (I : in bit; O : out bit);
end component;
end package;
entity DUMMY_MODULE is
port (I: in bit; O: out bit);
end entity;
architecture RTL of DUMMY_MODULE is
begin
O <= I;
end architecture;
-- file dummy_top.vhd
library DUMMY;
use DUMMY.COMPONENTS.DUMMY_MODULE;
entity DUMMY_TOP is
port (I : in bit; O : out bit);
end entity;
architecture RTL of DUMMY_TOP is
begin
U: DUMMY_MODULE port map(I=>I, O=>O);
end architecture;
|
-- file dummy.vhd
package COMPONENTS is
component DUMMY_MODULE
port (I : in bit; O : out bit);
end component;
end package;
entity DUMMY_MODULE is
port (I: in bit; O: out bit);
end entity;
architecture RTL of DUMMY_MODULE is
begin
O <= I;
end architecture;
-- file dummy_top.vhd
library DUMMY;
use DUMMY.COMPONENTS.DUMMY_MODULE;
entity DUMMY_TOP is
port (I : in bit; O : out bit);
end entity;
architecture RTL of DUMMY_TOP is
begin
U: DUMMY_MODULE port map(I=>I, O=>O);
end architecture;
|
-- file dummy.vhd
package COMPONENTS is
component DUMMY_MODULE
port (I : in bit; O : out bit);
end component;
end package;
entity DUMMY_MODULE is
port (I: in bit; O: out bit);
end entity;
architecture RTL of DUMMY_MODULE is
begin
O <= I;
end architecture;
-- file dummy_top.vhd
library DUMMY;
use DUMMY.COMPONENTS.DUMMY_MODULE;
entity DUMMY_TOP is
port (I : in bit; O : out bit);
end entity;
architecture RTL of DUMMY_TOP is
begin
U: DUMMY_MODULE port map(I=>I, O=>O);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity interpolate is
generic(
interpolation_factor : integer := 8192;
output_width : integer := 24;
width : integer := 8
);
port(
clk : in std_logic;
rst : in std_logic;
input : in std_logic_vector(width - 1 downto 0);
input_stb : in std_logic;
input_ack : out std_logic;
output_0 : out std_logic_vector(output_width - 1 downto 0);
output_1 : out std_logic_vector(output_width - 1 downto 0);
output_2 : out std_logic_vector(output_width - 1 downto 0);
output_3 : out std_logic_vector(output_width - 1 downto 0);
output_4 : out std_logic_vector(output_width - 1 downto 0);
output_5 : out std_logic_vector(output_width - 1 downto 0);
output_6 : out std_logic_vector(output_width - 1 downto 0);
output_7 : out std_logic_vector(output_width - 1 downto 0)
);
end entity interpolate;
architecture rtl of interpolate is
signal count : integer range 0 to interpolation_factor - 1 := 0;
signal last_input : signed(output_width - 1 downto 0) := (others => '0');
signal delta : signed(output_width - 1 downto 0) := (others => '0');
signal delta_d1 : signed(output_width - 1 downto 0) := (others => '0');
signal delta_d2 : signed(output_width - 1 downto 0) := (others => '0');
signal delta_d3 : signed(output_width - 1 downto 0) := (others => '0');
signal accum : signed(output_width - 1 downto 0) := (others => '0');
signal tree_0 : signed(output_width - 1 downto 0) := (others => '0');
signal tree_1 : signed(output_width - 1 downto 0) := (others => '0');
signal tree_00 : signed(output_width - 1 downto 0) := (others => '0');
signal tree_01 : signed(output_width - 1 downto 0) := (others => '0');
signal tree_10 : signed(output_width - 1 downto 0) := (others => '0');
signal tree_11 : signed(output_width - 1 downto 0) := (others => '0');
signal tree_000 : signed(output_width - 1 downto 0) := (others => '0');
signal tree_001 : signed(output_width - 1 downto 0) := (others => '0');
signal tree_010 : signed(output_width - 1 downto 0) := (others => '0');
signal tree_011 : signed(output_width - 1 downto 0) := (others => '0');
signal tree_100 : signed(output_width - 1 downto 0) := (others => '0');
signal tree_101 : signed(output_width - 1 downto 0) := (others => '0');
signal tree_110 : signed(output_width - 1 downto 0) := (others => '0');
signal tree_111 : signed(output_width - 1 downto 0) := (others => '0');
begin
process
begin
wait until rising_edge(clk);
if count = 0 then
count <= interpolation_factor-1;
last_input <= resize(signed(input), output_width);
delta <= resize(signed(input), output_width) - last_input;
input_ack <= '1';
else
count <= count - 1;
input_ack <= '0';
end if;
delta_d1 <= delta;
delta_d2 <= delta_d1;
delta_d3 <= delta_d2;
accum <= accum + (delta(output_width-4 downto 0) & "000");
tree_0 <= accum;
tree_1 <= accum + (delta_d1(output_width-3 downto 0) & "00");
tree_00 <= tree_0;
tree_01 <= tree_0 + (delta_d2(output_width-2 downto 0) & '0');
tree_10 <= tree_1;
tree_11 <= tree_1 + (delta_d2(output_width-2 downto 0) & '0');
tree_000 <= tree_00;
tree_001 <= tree_00 + delta_d3;
tree_010 <= tree_01;
tree_011 <= tree_01 + delta_d3;
tree_100 <= tree_10;
tree_101 <= tree_10 + delta_d3;
tree_110 <= tree_11;
tree_111 <= tree_11 + delta_d3;
output_0 <= std_logic_vector(tree_000);
output_1 <= std_logic_vector(tree_001);
output_2 <= std_logic_vector(tree_010);
output_3 <= std_logic_vector(tree_011);
output_4 <= std_logic_vector(tree_100);
output_5 <= std_logic_vector(tree_101);
output_6 <= std_logic_vector(tree_110);
output_7 <= std_logic_vector(tree_111);
end process;
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity interpolate is
generic(
interpolation_factor : integer := 8192;
output_width : integer := 24;
width : integer := 8
);
port(
clk : in std_logic;
rst : in std_logic;
input : in std_logic_vector(width - 1 downto 0);
input_stb : in std_logic;
input_ack : out std_logic;
output_0 : out std_logic_vector(output_width - 1 downto 0);
output_1 : out std_logic_vector(output_width - 1 downto 0);
output_2 : out std_logic_vector(output_width - 1 downto 0);
output_3 : out std_logic_vector(output_width - 1 downto 0);
output_4 : out std_logic_vector(output_width - 1 downto 0);
output_5 : out std_logic_vector(output_width - 1 downto 0);
output_6 : out std_logic_vector(output_width - 1 downto 0);
output_7 : out std_logic_vector(output_width - 1 downto 0)
);
end entity interpolate;
architecture rtl of interpolate is
signal count : integer range 0 to interpolation_factor - 1 := 0;
signal last_input : signed(output_width - 1 downto 0) := (others => '0');
signal delta : signed(output_width - 1 downto 0) := (others => '0');
signal delta_d1 : signed(output_width - 1 downto 0) := (others => '0');
signal delta_d2 : signed(output_width - 1 downto 0) := (others => '0');
signal delta_d3 : signed(output_width - 1 downto 0) := (others => '0');
signal accum : signed(output_width - 1 downto 0) := (others => '0');
signal tree_0 : signed(output_width - 1 downto 0) := (others => '0');
signal tree_1 : signed(output_width - 1 downto 0) := (others => '0');
signal tree_00 : signed(output_width - 1 downto 0) := (others => '0');
signal tree_01 : signed(output_width - 1 downto 0) := (others => '0');
signal tree_10 : signed(output_width - 1 downto 0) := (others => '0');
signal tree_11 : signed(output_width - 1 downto 0) := (others => '0');
signal tree_000 : signed(output_width - 1 downto 0) := (others => '0');
signal tree_001 : signed(output_width - 1 downto 0) := (others => '0');
signal tree_010 : signed(output_width - 1 downto 0) := (others => '0');
signal tree_011 : signed(output_width - 1 downto 0) := (others => '0');
signal tree_100 : signed(output_width - 1 downto 0) := (others => '0');
signal tree_101 : signed(output_width - 1 downto 0) := (others => '0');
signal tree_110 : signed(output_width - 1 downto 0) := (others => '0');
signal tree_111 : signed(output_width - 1 downto 0) := (others => '0');
begin
process
begin
wait until rising_edge(clk);
if count = 0 then
count <= interpolation_factor-1;
last_input <= resize(signed(input), output_width);
delta <= resize(signed(input), output_width) - last_input;
input_ack <= '1';
else
count <= count - 1;
input_ack <= '0';
end if;
delta_d1 <= delta;
delta_d2 <= delta_d1;
delta_d3 <= delta_d2;
accum <= accum + (delta(output_width-4 downto 0) & "000");
tree_0 <= accum;
tree_1 <= accum + (delta_d1(output_width-3 downto 0) & "00");
tree_00 <= tree_0;
tree_01 <= tree_0 + (delta_d2(output_width-2 downto 0) & '0');
tree_10 <= tree_1;
tree_11 <= tree_1 + (delta_d2(output_width-2 downto 0) & '0');
tree_000 <= tree_00;
tree_001 <= tree_00 + delta_d3;
tree_010 <= tree_01;
tree_011 <= tree_01 + delta_d3;
tree_100 <= tree_10;
tree_101 <= tree_10 + delta_d3;
tree_110 <= tree_11;
tree_111 <= tree_11 + delta_d3;
output_0 <= std_logic_vector(tree_000);
output_1 <= std_logic_vector(tree_001);
output_2 <= std_logic_vector(tree_010);
output_3 <= std_logic_vector(tree_011);
output_4 <= std_logic_vector(tree_100);
output_5 <= std_logic_vector(tree_101);
output_6 <= std_logic_vector(tree_110);
output_7 <= std_logic_vector(tree_111);
end process;
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity interpolate is
generic(
interpolation_factor : integer := 8192;
output_width : integer := 24;
width : integer := 8
);
port(
clk : in std_logic;
rst : in std_logic;
input : in std_logic_vector(width - 1 downto 0);
input_stb : in std_logic;
input_ack : out std_logic;
output_0 : out std_logic_vector(output_width - 1 downto 0);
output_1 : out std_logic_vector(output_width - 1 downto 0);
output_2 : out std_logic_vector(output_width - 1 downto 0);
output_3 : out std_logic_vector(output_width - 1 downto 0);
output_4 : out std_logic_vector(output_width - 1 downto 0);
output_5 : out std_logic_vector(output_width - 1 downto 0);
output_6 : out std_logic_vector(output_width - 1 downto 0);
output_7 : out std_logic_vector(output_width - 1 downto 0)
);
end entity interpolate;
architecture rtl of interpolate is
signal count : integer range 0 to interpolation_factor - 1 := 0;
signal last_input : signed(output_width - 1 downto 0) := (others => '0');
signal delta : signed(output_width - 1 downto 0) := (others => '0');
signal delta_d1 : signed(output_width - 1 downto 0) := (others => '0');
signal delta_d2 : signed(output_width - 1 downto 0) := (others => '0');
signal delta_d3 : signed(output_width - 1 downto 0) := (others => '0');
signal accum : signed(output_width - 1 downto 0) := (others => '0');
signal tree_0 : signed(output_width - 1 downto 0) := (others => '0');
signal tree_1 : signed(output_width - 1 downto 0) := (others => '0');
signal tree_00 : signed(output_width - 1 downto 0) := (others => '0');
signal tree_01 : signed(output_width - 1 downto 0) := (others => '0');
signal tree_10 : signed(output_width - 1 downto 0) := (others => '0');
signal tree_11 : signed(output_width - 1 downto 0) := (others => '0');
signal tree_000 : signed(output_width - 1 downto 0) := (others => '0');
signal tree_001 : signed(output_width - 1 downto 0) := (others => '0');
signal tree_010 : signed(output_width - 1 downto 0) := (others => '0');
signal tree_011 : signed(output_width - 1 downto 0) := (others => '0');
signal tree_100 : signed(output_width - 1 downto 0) := (others => '0');
signal tree_101 : signed(output_width - 1 downto 0) := (others => '0');
signal tree_110 : signed(output_width - 1 downto 0) := (others => '0');
signal tree_111 : signed(output_width - 1 downto 0) := (others => '0');
begin
process
begin
wait until rising_edge(clk);
if count = 0 then
count <= interpolation_factor-1;
last_input <= resize(signed(input), output_width);
delta <= resize(signed(input), output_width) - last_input;
input_ack <= '1';
else
count <= count - 1;
input_ack <= '0';
end if;
delta_d1 <= delta;
delta_d2 <= delta_d1;
delta_d3 <= delta_d2;
accum <= accum + (delta(output_width-4 downto 0) & "000");
tree_0 <= accum;
tree_1 <= accum + (delta_d1(output_width-3 downto 0) & "00");
tree_00 <= tree_0;
tree_01 <= tree_0 + (delta_d2(output_width-2 downto 0) & '0');
tree_10 <= tree_1;
tree_11 <= tree_1 + (delta_d2(output_width-2 downto 0) & '0');
tree_000 <= tree_00;
tree_001 <= tree_00 + delta_d3;
tree_010 <= tree_01;
tree_011 <= tree_01 + delta_d3;
tree_100 <= tree_10;
tree_101 <= tree_10 + delta_d3;
tree_110 <= tree_11;
tree_111 <= tree_11 + delta_d3;
output_0 <= std_logic_vector(tree_000);
output_1 <= std_logic_vector(tree_001);
output_2 <= std_logic_vector(tree_010);
output_3 <= std_logic_vector(tree_011);
output_4 <= std_logic_vector(tree_100);
output_5 <= std_logic_vector(tree_101);
output_6 <= std_logic_vector(tree_110);
output_7 <= std_logic_vector(tree_111);
end process;
end rtl;
|
--------------------------------------------------------------------------------
-- Author: Parham Alvani (parham.alvani@gmail.com)
--
-- Create Date: 31-05-2016
-- Module Name: main.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity main is
port (clk, a, b : in std_logic;
output : out std_logic_vector (3 downto 0));
end entity;
architecture rtl of main is
component datapath
port (clk, ent, ext : in std_logic;
output : out std_logic_vector (3 downto 0));
end component;
component control
port (ent, ext : out std_logic;
a, b : in std_logic;
clk : in std_logic);
end component;
for all:control use entity work.control(rtl);
for all:datapath use entity work.datapath;
signal ent, ext : std_logic;
begin
ctrl : control port map (ent, ext, a, b, clk);
dp : datapath port map (clk, ent, ext, output);
end architecture;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_08_fg_08_10.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity fg_08_10 is
end entity fg_08_10;
architecture test of fg_08_10 is
-- code from book
function "<" ( a, b : bit_vector ) return boolean is
variable tmp1 : bit_vector(a'range) := a;
variable tmp2 : bit_vector(b'range) := b;
begin
tmp1(tmp1'left) := not tmp1(tmp1'left);
tmp2(tmp2'left) := not tmp2(tmp2'left);
return std.standard."<" ( tmp1, tmp2 );
end function "<";
-- end code from book
signal a, b : bit_vector(7 downto 0);
signal result : boolean;
begin
dut : result <= a < b;
stimulus : process is
begin
wait for 10 ns;
a <= X"02"; b <= X"04"; wait for 10 ns;
a <= X"02"; b <= X"02"; wait for 10 ns;
a <= X"02"; b <= X"01"; wait for 10 ns;
a <= X"02"; b <= X"FE"; wait for 10 ns;
a <= X"FE"; b <= X"02"; wait for 10 ns;
a <= X"FE"; b <= X"FE"; wait for 10 ns;
a <= X"FE"; b <= X"FC"; wait for 10 ns;
wait;
end process stimulus;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_08_fg_08_10.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity fg_08_10 is
end entity fg_08_10;
architecture test of fg_08_10 is
-- code from book
function "<" ( a, b : bit_vector ) return boolean is
variable tmp1 : bit_vector(a'range) := a;
variable tmp2 : bit_vector(b'range) := b;
begin
tmp1(tmp1'left) := not tmp1(tmp1'left);
tmp2(tmp2'left) := not tmp2(tmp2'left);
return std.standard."<" ( tmp1, tmp2 );
end function "<";
-- end code from book
signal a, b : bit_vector(7 downto 0);
signal result : boolean;
begin
dut : result <= a < b;
stimulus : process is
begin
wait for 10 ns;
a <= X"02"; b <= X"04"; wait for 10 ns;
a <= X"02"; b <= X"02"; wait for 10 ns;
a <= X"02"; b <= X"01"; wait for 10 ns;
a <= X"02"; b <= X"FE"; wait for 10 ns;
a <= X"FE"; b <= X"02"; wait for 10 ns;
a <= X"FE"; b <= X"FE"; wait for 10 ns;
a <= X"FE"; b <= X"FC"; wait for 10 ns;
wait;
end process stimulus;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_08_fg_08_10.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity fg_08_10 is
end entity fg_08_10;
architecture test of fg_08_10 is
-- code from book
function "<" ( a, b : bit_vector ) return boolean is
variable tmp1 : bit_vector(a'range) := a;
variable tmp2 : bit_vector(b'range) := b;
begin
tmp1(tmp1'left) := not tmp1(tmp1'left);
tmp2(tmp2'left) := not tmp2(tmp2'left);
return std.standard."<" ( tmp1, tmp2 );
end function "<";
-- end code from book
signal a, b : bit_vector(7 downto 0);
signal result : boolean;
begin
dut : result <= a < b;
stimulus : process is
begin
wait for 10 ns;
a <= X"02"; b <= X"04"; wait for 10 ns;
a <= X"02"; b <= X"02"; wait for 10 ns;
a <= X"02"; b <= X"01"; wait for 10 ns;
a <= X"02"; b <= X"FE"; wait for 10 ns;
a <= X"FE"; b <= X"02"; wait for 10 ns;
a <= X"FE"; b <= X"FE"; wait for 10 ns;
a <= X"FE"; b <= X"FC"; wait for 10 ns;
wait;
end process stimulus;
end architecture test;
|
-- $Id: sys_conf_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_w11a_n4 (for simulation)
--
-- Dependencies: -
-- Tool versions: xst 14.5-14.7; viv 2016.1-2018.3; ghdl 0.29-0.35
-- Revision History:
-- Date Rev Version Comment
-- 2019-04-28 1142 1.6.1 add sys_conf_ibd_m9312
-- 2019-02-09 1110 1.6 use typ for DL,PC,LP; add dz11,ibtst
-- 2018-09-22 1050 1.5.6 add sys_conf_dmpcnt
-- 2018-09-09 1044 1.5.5 use _cache_twidth TW=7 (32 kByte), timing issues
-- 2018-09-08 1043 1.5.3 add sys_conf_ibd_kw11p
-- 2017-04-22 884 1.5.2 re-enable dmcmon
-- 2017-01-29 847 1.5.1 add sys_conf_ibd_deuna
-- 2016-07-16 788 1.5 use cram_*delay functions to determine delays
-- 2016-06-18 775 1.4.5 use PLL for clkser_gentype
-- 2016-06-04 772 1.4.4 go for 80 MHz and 64 kB cache, best compromise
-- 2016-05-28 771 1.4.3 set dmcmon_awidth=0, useless without dmscnt
-- 2016-05-28 770 1.4.2 sys_conf_mem_losize now type natural
-- 2016-05-26 768 1.4.1 set dmscnt=0 (vivado fsm issue); TW=8 (@90 MHz)
-- 2016-03-28 755 1.4 use serport_2clock2 -> define clkser
-- 2016-03-22 750 1.3 add sys_conf_cache_twidth
-- 2016-03-13 742 1.2.2 add sysmon_bus
-- 2015-06-26 695 1.2.1 add sys_conf_(dmscnt|dmhbpt*|dmcmon*)
-- 2015-03-14 658 1.2 add sys_conf_ibd_* definitions
-- 2015-02-07 643 1.1 drop bram and minisys options
-- 2013-09-34 534 1.0 Initial version (cloned from _n3)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.nxcramlib.all;
package sys_conf is
-- configure clocks --------------------------------------------------------
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz
constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
-- dual clock design, clkser = 120 MHz
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "PLL";
-- configure rlink and hio interfaces --------------------------------------
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
-- configure memory controller ---------------------------------------------
-- now under derived constants
-- configure debug and monitoring units ------------------------------------
constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable
constant sys_conf_ibmon_awidth : integer := 9; -- use 0 to disable
constant sys_conf_ibtst : boolean := true;
constant sys_conf_dmscnt : boolean := false;
constant sys_conf_dmpcnt : boolean := true;
constant sys_conf_dmhbpt_nunit : integer := 2; -- use 0 to disable
constant sys_conf_dmcmon_awidth : integer := 8; -- use 0 to disable, 8 to use
constant sys_conf_rbd_sysmon : boolean := true; -- SYSMON(XADC)
-- configure w11 cpu core --------------------------------------------------
constant sys_conf_mem_losize : natural := 8#167777#; -- 4 MByte
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled
constant sys_conf_cache_twidth : integer := 7; -- 32kB cache
-- configure w11 system devices --------------------------------------------
-- configure character and communication devices
-- typ for DL,DZ,PC,LP: -1->none; 0->unbuffered; 4-7 buffered (typ=AWIDTH)
constant sys_conf_ibd_dl11_0 : integer := 6; -- 1st DL11
constant sys_conf_ibd_dl11_1 : integer := 6; -- 2nd DL11
constant sys_conf_ibd_dz11 : integer := 6; -- DZ11
constant sys_conf_ibd_pc11 : integer := 6; -- PC11
constant sys_conf_ibd_lp11 : integer := 7; -- LP11
constant sys_conf_ibd_deuna : boolean := true; -- DEUNA
-- configure mass storage devices
constant sys_conf_ibd_rk11 : boolean := true; -- RK11
constant sys_conf_ibd_rl11 : boolean := true; -- RL11
constant sys_conf_ibd_rhrp : boolean := true; -- RHRP
constant sys_conf_ibd_tm11 : boolean := true; -- TM11
-- configure other devices
constant sys_conf_ibd_iist : boolean := true; -- IIST
constant sys_conf_ibd_kw11p : boolean := true; -- KW11P
constant sys_conf_ibd_m9312 : boolean := true; -- M9312
-- derived constants =======================================================
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
-- configure memory controller ---------------------------------------------
constant sys_conf_memctl_read0delay : positive :=
cram_read0delay(sys_conf_clksys_mhz);
constant sys_conf_memctl_read1delay : positive :=
cram_read1delay(sys_conf_clksys_mhz);
constant sys_conf_memctl_writedelay : positive :=
cram_writedelay(sys_conf_clksys_mhz);
end package sys_conf;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc285.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b03x00p12n01i00285ent IS
END c03s01b03x00p12n01i00285ent;
ARCHITECTURE c03s01b03x00p12n01i00285arch OF c03s01b03x00p12n01i00285ent IS
type time is range 0 to 1E8 units
fs;
ps = 10 fs;
end units;
BEGIN
TESTING: PROCESS
variable i : integer;
BEGIN
i:=time'pos(ps);
assert NOT(i=10)
report "***PASSED TEST: c03s01b03x00p12n01i00285"
severity NOTE;
assert (i=10)
report "***FAILED TEST: c03s01b03x00p12n01i00285 - The position number of the value corresponding to a unit name is the number of the base units represented by that unit name."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b03x00p12n01i00285arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc285.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b03x00p12n01i00285ent IS
END c03s01b03x00p12n01i00285ent;
ARCHITECTURE c03s01b03x00p12n01i00285arch OF c03s01b03x00p12n01i00285ent IS
type time is range 0 to 1E8 units
fs;
ps = 10 fs;
end units;
BEGIN
TESTING: PROCESS
variable i : integer;
BEGIN
i:=time'pos(ps);
assert NOT(i=10)
report "***PASSED TEST: c03s01b03x00p12n01i00285"
severity NOTE;
assert (i=10)
report "***FAILED TEST: c03s01b03x00p12n01i00285 - The position number of the value corresponding to a unit name is the number of the base units represented by that unit name."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b03x00p12n01i00285arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc285.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b03x00p12n01i00285ent IS
END c03s01b03x00p12n01i00285ent;
ARCHITECTURE c03s01b03x00p12n01i00285arch OF c03s01b03x00p12n01i00285ent IS
type time is range 0 to 1E8 units
fs;
ps = 10 fs;
end units;
BEGIN
TESTING: PROCESS
variable i : integer;
BEGIN
i:=time'pos(ps);
assert NOT(i=10)
report "***PASSED TEST: c03s01b03x00p12n01i00285"
severity NOTE;
assert (i=10)
report "***FAILED TEST: c03s01b03x00p12n01i00285 - The position number of the value corresponding to a unit name is the number of the base units represented by that unit name."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b03x00p12n01i00285arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cpld_bridge_tb is
end;
architecture bench of cpld_bridge_tb is
signal cfg_act : std_logic := '0';
signal cfg_clk : std_logic := '0';
signal cfg_err : std_logic := '0';
signal cfg_rdy : std_logic := '0';
signal cfgd : std_logic_vector ( 15 downto 0 ) := (others => '0');
signal clk : std_logic := '0';
signal rx_tdata : std_logic_vector ( 31 downto 0 ) := (others => '0');
signal rx_tlast : std_logic := '0';
signal rx_tready : std_logic := '0';
signal rx_tvalid : std_logic := '0';
signal tx_tdata : std_logic_vector ( 31 downto 0 ) := (others => '0');
signal tx_tlast : std_logic := '0';
signal tx_tready : std_logic := '1';
signal tx_tvalid : std_logic := '0';
signal fpga_cmdl : std_logic := '0';
signal fpga_rdyl : std_logic := '0';
signal rst : std_logic := '0';
signal stat_oel : std_logic := '0';
constant clock_period : time := 10 ns;
constant cfg_clock_period : time := 10 ns;
signal stop_the_clocks : boolean := false;
type TestBenchState_t is (RESET, STATUS_REQUEST, STATUS_REQUEST2, FINISHED);
signal testBench_state : TestBenchState_t;
type APSCommand_t is record
ack : std_logic;
seq : std_logic;
sel : std_logic;
rw : std_logic;
cmd : std_logic_vector(3 downto 0);
mode : std_logic_vector(7 downto 0);
cnt : std_logic_vector(15 downto 0);
end record;
begin
uut : entity work.cpld_bridge
port map (
clk => clk,
rst => rst,
rx_tdata => rx_tdata,
rx_tlast => rx_tlast,
rx_tready => rx_tready,
rx_tvalid => rx_tvalid,
tx_tdata => tx_tdata,
tx_tlast => tx_tlast,
tx_tready => tx_tready,
tx_tvalid => tx_tvalid,
cfg_clk => cfg_clk,
cfg_act => cfg_act,
cfg_err => cfg_err,
cfg_rdy => cfg_rdy,
cfgd => cfgd,
fpga_cmdl => fpga_cmdl,
fpga_rdyl => fpga_rdyl,
stat_oel => stat_oel
);
clk <= not clk after clock_period / 2 when not stop_the_clocks;
cfg_clk <= not cfg_clk after cfg_clock_period / 2 when not stop_the_clocks;
stimulus : process
variable command_word : APSCommand_t := (ack => '0', seq => '0', sel => '0', rw => '0', cmd => (others => '0'), mode => (others => '0'), cnt => x"0000");
begin
wait until rising_edge(clk);
testBench_state <= RESET;
rst <= '1';
wait for 100ns;
rst <= '0';
wait for 100ns;
--Clock in a status request
wait until rising_edge(clk);
testBench_state <= STATUS_REQUEST;
command_word.rw := '1';
command_word.cmd := x"7";
command_word.sel := '1';
rx_tdata <= command_word.ack & command_word.seq & command_word.sel & command_word.rw & command_word.cmd & x"000010";
rx_tvalid <= '1';
rx_tlast <= '1';
wait until rising_edge(clk) and rx_tready = '1';
rx_tvalid <= '0';
rx_tlast <= '0';
wait until tx_tlast = '1';
--Clock in a 2nd status request
wait until rising_edge(clk);
testBench_state <= STATUS_REQUEST2;
rx_tdata <= command_word.ack & command_word.seq & command_word.sel & command_word.rw & command_word.cmd & x"000010";
rx_tvalid <= '1';
rx_tlast <= '1';
wait until rising_edge(clk) and rx_tready = '1';
rx_tvalid <= '0';
rx_tlast <= '0';
wait until tx_tlast = '1';
wait for 10ns;
stop_the_clocks <= true;
end process;
checking : process
begin
--First thing back in the status registers
--command word
wait until rising_edge(clk) and tx_tvalid = '1';
assert tx_tdata = x"97000010" report "Incorrect STATUS_REQUEST command word response";
--host firmware version
wait until rising_edge(clk) and tx_tvalid = '1';
assert tx_tdata = x"00000a01" report "Incorrect STATUS_REQUEST host firmware version";
--user firmware version
wait until rising_edge(clk) and tx_tvalid = '1';
assert tx_tdata = x"badda555" report "Incorrect STATUS_REQUEST user firmware version";
--config source
wait until rising_edge(clk) and tx_tvalid = '1';
assert tx_tdata = x"bbbbbbbb" report "Incorrect STATUS_REQUEST config source";
--user status
wait until rising_edge(clk) and tx_tvalid = '1';
assert tx_tdata = x"0ddba111" report "Incorrect STATUS_REQUEST user status";
--dac0 status, dac1 status, pll status, temperature
for ct in 1 to 4 loop
wait until rising_edge(clk) and tx_tvalid = '1';
assert tx_tdata = x"00000000" report "Incorrect STATUS_REQUEST dac0/dac1/pll status";
end loop;
--send pkt count
wait until rising_edge(clk) and tx_tvalid = '1';
assert tx_tdata = x"00000000" report "Incorrect STATUS_REQUEST send packet count";
--receive pkt count
wait until rising_edge(clk) and tx_tvalid = '1';
assert tx_tdata = x"00000001" report "Incorrect STATUS_REQUEST receive packet count";
--skip pkt count, dup pkt count, fcs error pkt count, overrun count
for ct in 1 to 4 loop
wait until rising_edge(clk) and tx_tvalid = '1';
assert tx_tdata = x"00000000" report "Incorrect STATUS_REQUEST skip/dup/fcs errors/overrun pkt count";
end loop;
--uptime
wait until rising_edge(clk) and tx_tvalid = '1';
assert tx_tdata = x"00000000" report "Incorrect STATUS_REQUEST uptime seconds";
wait until rising_edge(clk) and tx_tvalid = '1';
assert tx_tdata = x"000002b8" report "Incorrect STATUS_REQUEST updtime nanoseconds";
assert tx_tlast = '1' report "tlast did not go high when expected";
end process;
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2564.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b06x00p08n01i02564ent IS
END c07s03b06x00p08n01i02564ent;
ARCHITECTURE c07s03b06x00p08n01i02564arch OF c07s03b06x00p08n01i02564ent IS
BEGIN
TESTING: PROCESS
type LINK is access BIT_VECTOR;
variable HEAD : LINK := new BIT_VECTOR'("00110110") ;
variable TAIL : LINK;
BEGIN
TAIL := HEAD;
wait for 1 ns;
assert NOT( TAIL(3) = '1' )
report "***PASSED TEST: c07s03b06x00p08n01i02564"
severity NOTE;
assert ( TAIL(3) = '1' )
report "***FAILED TEST: c07s03b06x00p08n01i02564 - "
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b06x00p08n01i02564arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2564.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b06x00p08n01i02564ent IS
END c07s03b06x00p08n01i02564ent;
ARCHITECTURE c07s03b06x00p08n01i02564arch OF c07s03b06x00p08n01i02564ent IS
BEGIN
TESTING: PROCESS
type LINK is access BIT_VECTOR;
variable HEAD : LINK := new BIT_VECTOR'("00110110") ;
variable TAIL : LINK;
BEGIN
TAIL := HEAD;
wait for 1 ns;
assert NOT( TAIL(3) = '1' )
report "***PASSED TEST: c07s03b06x00p08n01i02564"
severity NOTE;
assert ( TAIL(3) = '1' )
report "***FAILED TEST: c07s03b06x00p08n01i02564 - "
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b06x00p08n01i02564arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2564.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b06x00p08n01i02564ent IS
END c07s03b06x00p08n01i02564ent;
ARCHITECTURE c07s03b06x00p08n01i02564arch OF c07s03b06x00p08n01i02564ent IS
BEGIN
TESTING: PROCESS
type LINK is access BIT_VECTOR;
variable HEAD : LINK := new BIT_VECTOR'("00110110") ;
variable TAIL : LINK;
BEGIN
TAIL := HEAD;
wait for 1 ns;
assert NOT( TAIL(3) = '1' )
report "***PASSED TEST: c07s03b06x00p08n01i02564"
severity NOTE;
assert ( TAIL(3) = '1' )
report "***FAILED TEST: c07s03b06x00p08n01i02564 - "
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b06x00p08n01i02564arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity h264_deblock_filter_core is
port(
clk : in std_logic;
rst : in std_logic;
is_chroma : in std_logic;
boundary_strength : in signed(8 downto 0);
p0 : in signed(8 downto 0);
p1 : in signed(8 downto 0);
p2 : in signed(8 downto 0);
p3 : in signed(8 downto 0);
q0 : in signed(8 downto 0);
q1 : in signed(8 downto 0);
q2 : in signed(8 downto 0);
q3 : in signed(8 downto 0);
alpha : in signed(8 downto 0);
beta : in signed(8 downto 0);
tc0 : in signed(8 downto 0);
p0_out : out signed(8 downto 0);
p1_out : out signed(8 downto 0);
p2_out : out signed(8 downto 0);
q0_out : out signed(8 downto 0);
q1_out : out signed(8 downto 0);
q2_out : out signed(8 downto 0)
);
end entity h264_deblock_filter_core;
architecture rtl of h264_deblock_filter_core is
signal normal_filter : boolean;
signal strong_filter : boolean;
signal ap, aq : boolean;
signal strong_filter_test : boolean;
signal basic_checks : boolean; -- and of three test always needed
signal extra_filter_normal_p : boolean;
signal extra_filter_normal_q : boolean;
signal p0_if_normal_filtd : signed(15 downto 0);
signal p1_if_normal_filtd : signed(15 downto 0);
signal q0_if_normal_filtd : signed(15 downto 0);
signal q1_if_normal_filtd : signed(15 downto 0);
signal p0_if_strong_filtd_0 : signed(15 downto 0);
signal p1_if_strong_filtd_0 : signed(15 downto 0);
signal p2_if_strong_filtd_0 : signed(15 downto 0);
signal q0_if_strong_filtd_0 : signed(15 downto 0);
signal q1_if_strong_filtd_0 : signed(15 downto 0);
signal q2_if_strong_filtd_0 : signed(15 downto 0);
signal p0_if_strong_filtd_1 : signed(15 downto 0);
signal p1_if_strong_filtd_1 : signed(15 downto 0);
signal p2_if_strong_filtd_1 : signed(15 downto 0);
signal q0_if_strong_filtd_1 : signed(15 downto 0);
signal q1_if_strong_filtd_1 : signed(15 downto 0);
signal q2_if_strong_filtd_1 : signed(15 downto 0);
signal p0_if_strong_filtd : signed(15 downto 0);
signal p1_if_strong_filtd : signed(15 downto 0);
signal p2_if_strong_filtd : signed(15 downto 0);
signal q0_if_strong_filtd : signed(15 downto 0);
signal q1_if_strong_filtd : signed(15 downto 0);
signal q2_if_strong_filtd : signed(15 downto 0);
signal delta_pre_clip : signed(15 downto 0);
signal delta : signed(15 downto 0);
signal p1_pre_clip_component : signed(15 downto 0);
signal q1_pre_clip_component : signed(15 downto 0);
signal p1_post_clip_component : signed(15 downto 0);
signal q1_post_clip_component : signed(15 downto 0);
signal tc0_prime : signed(8 downto 0);
begin
-- normal filtering
basic_checks <= (abs(p0-q0) < alpha) and
(abs(p1-p0) < beta ) and
(abs(q1-q0) < beta );
extra_filter_normal_p <= abs(p2-p0) < beta;
extra_filter_normal_q <= abs(q2-q0) < beta;
tc0_prime <= tc0 when not (extra_filter_normal_p or extra_filter_normal_q) else
tc0 + to_signed(1, 9) when extra_filter_normal_p xor extra_filter_normal_q else
tc0 + to_signed(2, 9);
delta_pre_clip <= shift_right((shift_left((("0000000"&q0) - ("0000000"&p0)) , 2) +
(("0000000"&p1) - ("0000000"&q1)) + (to_signed(4, 16))) , 3);
delta <= delta_pre_clip when delta_pre_clip > -tc0_prime and delta_pre_clip < tc0_prime else
"1111111"&(-tc0_prime) when delta_pre_clip < -tc0_prime else
"0000000"&tc0_prime;
p1_pre_clip_component <= shift_right((("0000000"&p2) + shift_right((("0000000"&p0) + ("0000000"&q0) + to_signed(1, 16)) , 1) - shift_left(("0000000"&p1) , 1)) , 1);
p1_post_clip_component <= p1_pre_clip_component when p1_pre_clip_component > -tc0 and p1_pre_clip_component < tc0 else
"1111111"&(-tc0) when p1_pre_clip_component < -tc0 else
"0000000"&tc0;
q1_pre_clip_component <= shift_right((("0000000"&q2) + shift_right((("0000000"&p0) + ("0000000"&q0) + to_signed(1, 16)) , 1) - shift_left(("0000000"&q1) , 1)) , 1);
q1_post_clip_component <= q1_pre_clip_component when q1_pre_clip_component > -tc0 and q1_pre_clip_component < tc0 else
"1111111"&(-tc0) when q1_pre_clip_component < -tc0 else
"0000000"&tc0;
p0_if_normal_filtd <= ("0000000"&p0) + delta;
p1_if_normal_filtd <= ("0000000"&p1) + p1_post_clip_component;
q0_if_normal_filtd <= ("0000000"&q0) - delta;
q1_if_normal_filtd <= ("0000000"&q1) + q1_post_clip_component;
normal_filter <= boundary_strength < to_signed(4, 9) and boundary_strength > to_signed(0, 9);
--strong filtering
ap <= extra_filter_normal_p;
aq <= extra_filter_normal_q;
strong_filter <= boundary_strength = to_signed(4, 9);
strong_filter_test <= (abs((X"0"&p0) - (X"0"&q0)) < (shift_right(X"0"&alpha, 2) + to_signed(2, 13))) and (is_chroma = '0');
p0_if_strong_filtd_0 <= shift_right(( shift_left("0000000"&p1, 1) + ("0000000"&p0) + ("0000000"&q1) + to_signed(2, 16) ) , 2);
p1_if_strong_filtd_0 <= "0000000"&p1;
p2_if_strong_filtd_0 <= "0000000"&p2;
q0_if_strong_filtd_0 <= shift_right(( shift_left("0000000"&q1, 1) + ("0000000"&q0) + ("0000000"&p1) + to_signed(2, 16) ) , 2);
q1_if_strong_filtd_0 <= "0000000"&q1;
q2_if_strong_filtd_0 <= "0000000"&q2;
p0_if_strong_filtd_1 <= shift_right((("0000000"&p2) + shift_left("0000000"&p1, 1) + shift_left("0000000"&p0,1) + shift_left("0000000"&q0,1) + ("0000000"&q1) + to_signed(4, 16) ), 3);
p1_if_strong_filtd_1 <= shift_right(( ("0000000"&p2) + ("0000000"&p1) + ("0000000"&p0) + ("0000000"&q0) + to_signed(2, 16) ), 2);
p2_if_strong_filtd_1 <= shift_right((shift_left("0000000"&p3, 1) + (to_signed(3, 7)*p2) + ("0000000"&p1) + ("0000000"&p0) + ("0000000"&q0) + to_signed(4, 16) ) , 3);
q0_if_strong_filtd_1 <= shift_right((("0000000"&q2) + shift_left("0000000"&q1, 1) + shift_left("0000000"&q0,1) + shift_left("0000000"&p0,1) + ("0000000"&p1) + to_signed(4, 16) ), 3);
q1_if_strong_filtd_1 <= shift_right(( ("0000000"&q2) + ("0000000"&q1) + ("0000000"&q0) + ("0000000"&p0) + to_signed(2, 16) ), 2);
q2_if_strong_filtd_1 <= shift_right((shift_left("0000000"&q3, 1) + (to_signed(3, 7)*q2) + ("0000000"&q1) + ("0000000"&q0) + ("0000000"&p0) + to_signed(4, 16) ) , 3);
p0_if_strong_filtd <= p0_if_strong_filtd_1 when strong_filter_test else p0_if_strong_filtd_0;
p1_if_strong_filtd <= p1_if_strong_filtd_1 when strong_filter_test else p1_if_strong_filtd_0;
p2_if_strong_filtd <= p2_if_strong_filtd_1 when strong_filter_test else p2_if_strong_filtd_0;
q0_if_strong_filtd <= q0_if_strong_filtd_1 when strong_filter_test else q0_if_strong_filtd_0;
q1_if_strong_filtd <= q1_if_strong_filtd_1 when strong_filter_test else q1_if_strong_filtd_0;
q2_if_strong_filtd <= q2_if_strong_filtd_1 when strong_filter_test else q2_if_strong_filtd_0;
-- output (will need modifing once strong filtering is built)
p0_out <= p0_if_normal_filtd(8 downto 0) when normal_filter and basic_checks else
p0_if_strong_filtd(8 downto 0) when strong_filter and basic_checks else
p0;
p1_out <= p1_if_normal_filtd(8 downto 0) when normal_filter and basic_checks and extra_filter_normal_p else
p1_if_strong_filtd(8 downto 0) when strong_filter and basic_checks else
p1;
p2_out <= p2_if_strong_filtd(8 downto 0) when strong_filter and basic_checks else p2;
q0_out <= q0_if_normal_filtd(8 downto 0) when normal_filter and basic_checks else
q0_if_strong_filtd(8 downto 0) when strong_filter and basic_checks else
q0;
q1_out <= q1_if_normal_filtd(8 downto 0) when normal_filter and basic_checks and extra_filter_normal_q else
q1_if_strong_filtd(8 downto 0) when strong_filter and basic_checks else
q1;
q2_out <= q2_if_strong_filtd(8 downto 0) when strong_filter and basic_checks else q2;
end architecture rtl; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity h264_deblock_filter_core is
port(
clk : in std_logic;
rst : in std_logic;
is_chroma : in std_logic;
boundary_strength : in signed(8 downto 0);
p0 : in signed(8 downto 0);
p1 : in signed(8 downto 0);
p2 : in signed(8 downto 0);
p3 : in signed(8 downto 0);
q0 : in signed(8 downto 0);
q1 : in signed(8 downto 0);
q2 : in signed(8 downto 0);
q3 : in signed(8 downto 0);
alpha : in signed(8 downto 0);
beta : in signed(8 downto 0);
tc0 : in signed(8 downto 0);
p0_out : out signed(8 downto 0);
p1_out : out signed(8 downto 0);
p2_out : out signed(8 downto 0);
q0_out : out signed(8 downto 0);
q1_out : out signed(8 downto 0);
q2_out : out signed(8 downto 0)
);
end entity h264_deblock_filter_core;
architecture rtl of h264_deblock_filter_core is
signal normal_filter : boolean;
signal strong_filter : boolean;
signal ap, aq : boolean;
signal strong_filter_test : boolean;
signal basic_checks : boolean; -- and of three test always needed
signal extra_filter_normal_p : boolean;
signal extra_filter_normal_q : boolean;
signal p0_if_normal_filtd : signed(15 downto 0);
signal p1_if_normal_filtd : signed(15 downto 0);
signal q0_if_normal_filtd : signed(15 downto 0);
signal q1_if_normal_filtd : signed(15 downto 0);
signal p0_if_strong_filtd_0 : signed(15 downto 0);
signal p1_if_strong_filtd_0 : signed(15 downto 0);
signal p2_if_strong_filtd_0 : signed(15 downto 0);
signal q0_if_strong_filtd_0 : signed(15 downto 0);
signal q1_if_strong_filtd_0 : signed(15 downto 0);
signal q2_if_strong_filtd_0 : signed(15 downto 0);
signal p0_if_strong_filtd_1 : signed(15 downto 0);
signal p1_if_strong_filtd_1 : signed(15 downto 0);
signal p2_if_strong_filtd_1 : signed(15 downto 0);
signal q0_if_strong_filtd_1 : signed(15 downto 0);
signal q1_if_strong_filtd_1 : signed(15 downto 0);
signal q2_if_strong_filtd_1 : signed(15 downto 0);
signal p0_if_strong_filtd : signed(15 downto 0);
signal p1_if_strong_filtd : signed(15 downto 0);
signal p2_if_strong_filtd : signed(15 downto 0);
signal q0_if_strong_filtd : signed(15 downto 0);
signal q1_if_strong_filtd : signed(15 downto 0);
signal q2_if_strong_filtd : signed(15 downto 0);
signal delta_pre_clip : signed(15 downto 0);
signal delta : signed(15 downto 0);
signal p1_pre_clip_component : signed(15 downto 0);
signal q1_pre_clip_component : signed(15 downto 0);
signal p1_post_clip_component : signed(15 downto 0);
signal q1_post_clip_component : signed(15 downto 0);
signal tc0_prime : signed(8 downto 0);
begin
-- normal filtering
basic_checks <= (abs(p0-q0) < alpha) and
(abs(p1-p0) < beta ) and
(abs(q1-q0) < beta );
extra_filter_normal_p <= abs(p2-p0) < beta;
extra_filter_normal_q <= abs(q2-q0) < beta;
tc0_prime <= tc0 when not (extra_filter_normal_p or extra_filter_normal_q) else
tc0 + to_signed(1, 9) when extra_filter_normal_p xor extra_filter_normal_q else
tc0 + to_signed(2, 9);
delta_pre_clip <= shift_right((shift_left((("0000000"&q0) - ("0000000"&p0)) , 2) +
(("0000000"&p1) - ("0000000"&q1)) + (to_signed(4, 16))) , 3);
delta <= delta_pre_clip when delta_pre_clip > -tc0_prime and delta_pre_clip < tc0_prime else
"1111111"&(-tc0_prime) when delta_pre_clip < -tc0_prime else
"0000000"&tc0_prime;
p1_pre_clip_component <= shift_right((("0000000"&p2) + shift_right((("0000000"&p0) + ("0000000"&q0) + to_signed(1, 16)) , 1) - shift_left(("0000000"&p1) , 1)) , 1);
p1_post_clip_component <= p1_pre_clip_component when p1_pre_clip_component > -tc0 and p1_pre_clip_component < tc0 else
"1111111"&(-tc0) when p1_pre_clip_component < -tc0 else
"0000000"&tc0;
q1_pre_clip_component <= shift_right((("0000000"&q2) + shift_right((("0000000"&p0) + ("0000000"&q0) + to_signed(1, 16)) , 1) - shift_left(("0000000"&q1) , 1)) , 1);
q1_post_clip_component <= q1_pre_clip_component when q1_pre_clip_component > -tc0 and q1_pre_clip_component < tc0 else
"1111111"&(-tc0) when q1_pre_clip_component < -tc0 else
"0000000"&tc0;
p0_if_normal_filtd <= ("0000000"&p0) + delta;
p1_if_normal_filtd <= ("0000000"&p1) + p1_post_clip_component;
q0_if_normal_filtd <= ("0000000"&q0) - delta;
q1_if_normal_filtd <= ("0000000"&q1) + q1_post_clip_component;
normal_filter <= boundary_strength < to_signed(4, 9) and boundary_strength > to_signed(0, 9);
--strong filtering
ap <= extra_filter_normal_p;
aq <= extra_filter_normal_q;
strong_filter <= boundary_strength = to_signed(4, 9);
strong_filter_test <= (abs((X"0"&p0) - (X"0"&q0)) < (shift_right(X"0"&alpha, 2) + to_signed(2, 13))) and (is_chroma = '0');
p0_if_strong_filtd_0 <= shift_right(( shift_left("0000000"&p1, 1) + ("0000000"&p0) + ("0000000"&q1) + to_signed(2, 16) ) , 2);
p1_if_strong_filtd_0 <= "0000000"&p1;
p2_if_strong_filtd_0 <= "0000000"&p2;
q0_if_strong_filtd_0 <= shift_right(( shift_left("0000000"&q1, 1) + ("0000000"&q0) + ("0000000"&p1) + to_signed(2, 16) ) , 2);
q1_if_strong_filtd_0 <= "0000000"&q1;
q2_if_strong_filtd_0 <= "0000000"&q2;
p0_if_strong_filtd_1 <= shift_right((("0000000"&p2) + shift_left("0000000"&p1, 1) + shift_left("0000000"&p0,1) + shift_left("0000000"&q0,1) + ("0000000"&q1) + to_signed(4, 16) ), 3);
p1_if_strong_filtd_1 <= shift_right(( ("0000000"&p2) + ("0000000"&p1) + ("0000000"&p0) + ("0000000"&q0) + to_signed(2, 16) ), 2);
p2_if_strong_filtd_1 <= shift_right((shift_left("0000000"&p3, 1) + (to_signed(3, 7)*p2) + ("0000000"&p1) + ("0000000"&p0) + ("0000000"&q0) + to_signed(4, 16) ) , 3);
q0_if_strong_filtd_1 <= shift_right((("0000000"&q2) + shift_left("0000000"&q1, 1) + shift_left("0000000"&q0,1) + shift_left("0000000"&p0,1) + ("0000000"&p1) + to_signed(4, 16) ), 3);
q1_if_strong_filtd_1 <= shift_right(( ("0000000"&q2) + ("0000000"&q1) + ("0000000"&q0) + ("0000000"&p0) + to_signed(2, 16) ), 2);
q2_if_strong_filtd_1 <= shift_right((shift_left("0000000"&q3, 1) + (to_signed(3, 7)*q2) + ("0000000"&q1) + ("0000000"&q0) + ("0000000"&p0) + to_signed(4, 16) ) , 3);
p0_if_strong_filtd <= p0_if_strong_filtd_1 when strong_filter_test else p0_if_strong_filtd_0;
p1_if_strong_filtd <= p1_if_strong_filtd_1 when strong_filter_test else p1_if_strong_filtd_0;
p2_if_strong_filtd <= p2_if_strong_filtd_1 when strong_filter_test else p2_if_strong_filtd_0;
q0_if_strong_filtd <= q0_if_strong_filtd_1 when strong_filter_test else q0_if_strong_filtd_0;
q1_if_strong_filtd <= q1_if_strong_filtd_1 when strong_filter_test else q1_if_strong_filtd_0;
q2_if_strong_filtd <= q2_if_strong_filtd_1 when strong_filter_test else q2_if_strong_filtd_0;
-- output (will need modifing once strong filtering is built)
p0_out <= p0_if_normal_filtd(8 downto 0) when normal_filter and basic_checks else
p0_if_strong_filtd(8 downto 0) when strong_filter and basic_checks else
p0;
p1_out <= p1_if_normal_filtd(8 downto 0) when normal_filter and basic_checks and extra_filter_normal_p else
p1_if_strong_filtd(8 downto 0) when strong_filter and basic_checks else
p1;
p2_out <= p2_if_strong_filtd(8 downto 0) when strong_filter and basic_checks else p2;
q0_out <= q0_if_normal_filtd(8 downto 0) when normal_filter and basic_checks else
q0_if_strong_filtd(8 downto 0) when strong_filter and basic_checks else
q0;
q1_out <= q1_if_normal_filtd(8 downto 0) when normal_filter and basic_checks and extra_filter_normal_q else
q1_if_strong_filtd(8 downto 0) when strong_filter and basic_checks else
q1;
q2_out <= q2_if_strong_filtd(8 downto 0) when strong_filter and basic_checks else q2;
end architecture rtl; |
-- File name: bus_test.vhd
-- Created: 2009-02-25
-- Author: Jevin Sweval
-- Lab Section: 337-02
-- Version: 1.0 Initial Design Entry
-- Description: block for testing bus stuff
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bus_test is
port (
clk : in std_logic;
nrst : in std_logic;
b : out unsigned(7 downto 0)
);
end bus_test;
architecture behavioral of bus_test is
signal n : unsigned(2 downto 0);
begin
process(clk, nrst)
begin
if (nrst='0') then
n <= (others => '0');
elsif (rising_edge(clk)) then
n <= n + 1;
end if;
end process;
process(n)
begin
case n is
when "001" => b <= to_unsigned(2, 8);
when others => b <= (others => 'Z');
end case;
end process;
process(n)
begin
case n is
when "011" => b <= to_unsigned(4, 8);
when others => b <= (others => 'Z');
end case;
end process;
process(n)
begin
case n is
when "001" => b <= (others => 'Z');
when "011" => b <= (others => 'Z');
when others => b <= to_unsigned(7, 8);
end case;
end process;
end behavioral;
|
-- megafunction wizard: %LPM_ROM%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: lpm_rom0.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY lpm_rom0 IS
PORT
(
address : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
inclock : IN STD_LOGIC := '1';
outclock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
);
END lpm_rom0;
ARCHITECTURE SYN OF lpm_rom0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (9 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_aclr_a : STRING;
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
clock0 : IN STD_LOGIC ;
clock1 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(9 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "lab10_1.mif",
intended_device_family => "Cyclone III",
lpm_type => "altsyncram",
numwords_a => 64,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK1",
widthad_a => 6,
width_a => 10,
width_byteena_a => 1
)
PORT MAP (
clock0 => inclock,
clock1 => outclock,
address_a => address,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "lab10_1.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "64"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "0"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "6"
-- Retrieval info: PRIVATE: WidthData NUMERIC "10"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "lab10_1.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "64"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK1"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "6"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 6 0 INPUT NODEFVAL address[5..0]
-- Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT VCC inclock
-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT NODEFVAL outclock
-- Retrieval info: USED_PORT: q 0 0 10 0 OUTPUT NODEFVAL q[9..0]
-- Retrieval info: CONNECT: @address_a 0 0 6 0 address 0 0 6 0
-- Retrieval info: CONNECT: q 0 0 10 0 @q_a 0 0 10 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 inclock 0 0 0 0
-- Retrieval info: CONNECT: @clock1 0 0 0 0 outclock 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom0_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom0_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom0_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
-------------------------------------------------------------------------------
-- $Id: pf_adder.vhd,v 1.1.2.1 2009/10/06 21:15:01 gburch Exp $
-------------------------------------------------------------------------------
-- pf_adder - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_adder.vhd
--
-- Description: Parameterized adder/subtractor for Mauna Loa Packet FIFO
-- vacancy calculation. This design has a combinational
-- output. The carry out is not used by the PFIFO so it has
-- been removed.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_adder.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1.2.1 $
-- Date: $Date: 2009/10/06 21:15:01 $
--
-- History:
-- DET 2001-08-30 First Version
-- - adapted from B Tise MicroBlaze timer counters
--
-- DET 2001-09-11
-- - Added the Rst input to the pf_adder_bit component
--
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.all;
library opb_v20_v1_10_d;
use opb_v20_v1_10_d.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_adder is
generic (
C_REGISTERED_RESULT : Boolean := false;
C_COUNT_WIDTH : integer := 10
);
port (
Clk : in std_logic;
Rst : in std_logic;
--Carry_Out : out std_logic;
Ain : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Bin : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Add_sub_n : in std_logic;
result_out : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end entity pf_adder;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_adder is
constant CY_START : integer := 1;
signal alu_cy : std_logic_vector(0 to C_COUNT_WIDTH);
signal iresult_out : std_logic_vector(0 to C_COUNT_WIDTH-1);
signal count_clock_en : std_logic;
--signal carry_active_high : std_logic;
begin -- VHDL_RTL
-----------------------------------------------------------------------------
-- Generate the Counter bits
-----------------------------------------------------------------------------
alu_cy(C_COUNT_WIDTH) <= not(Add_sub_n); -- initial carry-in to adder LSB
count_clock_en <= '1';
I_ADDSUB_GEN : for i in 0 to C_COUNT_WIDTH-1 generate
begin
Counter_Bit_I : entity opb_v20_v1_10_d.pf_adder_bit
Generic map(
C_REGISTERED_RESULT => C_REGISTERED_RESULT
)
port map (
Clk => Clk, -- [in]
Rst => Rst, -- [in]
Ain => Ain(i), -- [in]
Bin => Bin(i), -- [in]
Add_sub_n => Add_sub_n, -- [in]
Carry_In => alu_cy(i+CY_Start), -- [in]
Clock_Enable => count_clock_en, -- [in]
Result => iresult_out(i), -- [out]
Carry_Out => alu_cy(i+(1-CY_Start))); -- [out]
end generate I_ADDSUB_GEN;
result_out <= iresult_out;
end architecture implementation;
|
-------------------------------------------------------------------------------
-- $Id: pf_adder.vhd,v 1.1.2.1 2009/10/06 21:15:01 gburch Exp $
-------------------------------------------------------------------------------
-- pf_adder - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_adder.vhd
--
-- Description: Parameterized adder/subtractor for Mauna Loa Packet FIFO
-- vacancy calculation. This design has a combinational
-- output. The carry out is not used by the PFIFO so it has
-- been removed.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_adder.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1.2.1 $
-- Date: $Date: 2009/10/06 21:15:01 $
--
-- History:
-- DET 2001-08-30 First Version
-- - adapted from B Tise MicroBlaze timer counters
--
-- DET 2001-09-11
-- - Added the Rst input to the pf_adder_bit component
--
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.all;
library opb_v20_v1_10_d;
use opb_v20_v1_10_d.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_adder is
generic (
C_REGISTERED_RESULT : Boolean := false;
C_COUNT_WIDTH : integer := 10
);
port (
Clk : in std_logic;
Rst : in std_logic;
--Carry_Out : out std_logic;
Ain : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Bin : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Add_sub_n : in std_logic;
result_out : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end entity pf_adder;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_adder is
constant CY_START : integer := 1;
signal alu_cy : std_logic_vector(0 to C_COUNT_WIDTH);
signal iresult_out : std_logic_vector(0 to C_COUNT_WIDTH-1);
signal count_clock_en : std_logic;
--signal carry_active_high : std_logic;
begin -- VHDL_RTL
-----------------------------------------------------------------------------
-- Generate the Counter bits
-----------------------------------------------------------------------------
alu_cy(C_COUNT_WIDTH) <= not(Add_sub_n); -- initial carry-in to adder LSB
count_clock_en <= '1';
I_ADDSUB_GEN : for i in 0 to C_COUNT_WIDTH-1 generate
begin
Counter_Bit_I : entity opb_v20_v1_10_d.pf_adder_bit
Generic map(
C_REGISTERED_RESULT => C_REGISTERED_RESULT
)
port map (
Clk => Clk, -- [in]
Rst => Rst, -- [in]
Ain => Ain(i), -- [in]
Bin => Bin(i), -- [in]
Add_sub_n => Add_sub_n, -- [in]
Carry_In => alu_cy(i+CY_Start), -- [in]
Clock_Enable => count_clock_en, -- [in]
Result => iresult_out(i), -- [out]
Carry_Out => alu_cy(i+(1-CY_Start))); -- [out]
end generate I_ADDSUB_GEN;
result_out <= iresult_out;
end architecture implementation;
|
-- Copyright (c) 2016 Federico Madotto and Coline Doebelin
-- federico.madotto (at) gmail.com
-- coline.doebelin (at) gmail.com
-- https://github.com/fmadotto/DS_bitcoin_miner
-- nbits_register.vhd is part of DS_bitcoin_miner.
-- DS_bitcoin_miner is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- DS_bitcoin_miner is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all;
entity nbits_register is
generic (
n : natural := 32 -- input size (default is 32 bits)
);
port (
clk : in std_ulogic; -- clock
rstn : in std_ulogic; -- asynchronous active low reset
en : in std_ulogic; -- enable
d : in std_ulogic_vector(n-1 downto 0); -- data in
q : out std_ulogic_vector(n-1 downto 0) -- data out
);
end entity nbits_register;
architecture behav of nbits_register is
begin
process (clk, rstn) -- asynchronous reset
begin
if rstn = '0' then
q <= (others => '0'); -- clear output on reset
elsif clk'event and clk = '1' then
if en = '1' then -- data in is sampled on positive edge of clk if enabled
q <= d;
end if;
end if;
end process;
end architecture behav;
|
entity record2 is
end entity;
architecture test of record2 is
type rec is record
x, y : integer;
end record;
procedure set_to(variable r : inout rec;
constant n : in integer) is
begin
r.x := n;
r.y := r.x;
end procedure;
begin
process is
variable r : rec;
begin
set_to(r, 5);
assert r.x = 5;
assert r.y = 5;
wait;
end process;
end architecture;
|
entity record2 is
end entity;
architecture test of record2 is
type rec is record
x, y : integer;
end record;
procedure set_to(variable r : inout rec;
constant n : in integer) is
begin
r.x := n;
r.y := r.x;
end procedure;
begin
process is
variable r : rec;
begin
set_to(r, 5);
assert r.x = 5;
assert r.y = 5;
wait;
end process;
end architecture;
|
entity record2 is
end entity;
architecture test of record2 is
type rec is record
x, y : integer;
end record;
procedure set_to(variable r : inout rec;
constant n : in integer) is
begin
r.x := n;
r.y := r.x;
end procedure;
begin
process is
variable r : rec;
begin
set_to(r, 5);
assert r.x = 5;
assert r.y = 5;
wait;
end process;
end architecture;
|
entity record2 is
end entity;
architecture test of record2 is
type rec is record
x, y : integer;
end record;
procedure set_to(variable r : inout rec;
constant n : in integer) is
begin
r.x := n;
r.y := r.x;
end procedure;
begin
process is
variable r : rec;
begin
set_to(r, 5);
assert r.x = 5;
assert r.y = 5;
wait;
end process;
end architecture;
|
entity record2 is
end entity;
architecture test of record2 is
type rec is record
x, y : integer;
end record;
procedure set_to(variable r : inout rec;
constant n : in integer) is
begin
r.x := n;
r.y := r.x;
end procedure;
begin
process is
variable r : rec;
begin
set_to(r, 5);
assert r.x = 5;
assert r.y = 5;
wait;
end process;
end architecture;
|
library ieee;
library work;
library altera;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.altera_pll_top_pkg.all;
use altera.altera_syn_attributes.all;
entity hardheat_top is
generic
(
-- Number of bits in time-to-digital converter
TDC_N : positive := 12;
-- Number of bitshifts to left for the filter proportional coefficient
FILT_P_SHIFT_N : integer := 0;
-- Number of bitshifts to right for the filter integral coefficient
FILT_I_SHIFT_N : integer := -5;
-- Initial output value from the filter
FILT_INIT_OUT_VAL : positive := 2**11 - 1;
-- Filter output offset
FILT_OUT_OFFSET : natural := 2**21;
-- Filter output value clamping limit
FILT_OUT_LIM : positive := 2**22;
-- Number of bits in the phase accumulator
ACCUM_BITS_N : positive := 32;
-- Number of bits in the tuning word for the phase accumulator
ACCUM_WORD_N : positive := 23;
-- Number of bits in the deadtime counter
DT_N : positive := 16;
-- Amount of deadtime in clock cycles
DT_VAL : natural := 100;
-- Number of bits in the lock detector "locked" counter
LD_LOCK_N : positive := 20;
-- Number of bits in the lock detector "unlocked" counter
LD_ULOCK_N : positive := 16;
-- Phase difference value under which we are considered to be locked
LD_LOCK_LIMIT : natural := 100;
-- Temperature conversion interval in clock cycles
TEMP_CONV_D : natural := 100000000;
-- Delay between conversion command and reading in clock cycles
TEMP_CONV_CMD_D : natural := 75000000;
-- Number of clock cycles for 1us delay for the 1-wire module
TEMP_OW_US_D : positive := 100;
-- Number of bits in the temperature PWM controller
TEMP_PWM_N : positive := 12;
-- Minimum PWM level (duty cycle)
TEMP_PWM_MIN_LVL : natural := 2**12 / 5;
-- Output maximum duty cycle on enable, measured in PWM cycles!
TEMP_PWM_EN_ON_D : natural := 100000;
-- Number of bitshifts to left for the PID-filter proportional coeff
TEMP_P_SHIFT_N : integer := 4;
-- Number of bitshifts to right for the PID-filter integral coeff
TEMP_I_SHIFT_N : integer := -11;
-- PID input offset applied to the temperature sensor output
TEMP_SETPOINT : integer := 320;
DEBOUNCE_D : natural := 1000000;
DEBOUNCE_FF_N : natural := 5
);
port
(
clk_in : in std_logic;
reset_in : in std_logic;
ref_in : in std_logic;
sig_in : in std_logic;
ow_in : in std_logic;
mod_lvl_in : in std_logic_vector(2 downto 0);
ow_out : out std_logic;
ow_pullup_out : out std_logic;
sig_lh_out : out std_logic;
sig_ll_out : out std_logic;
sig_rh_out : out std_logic;
sig_rl_out : out std_logic;
lock_out : out std_logic;
pwm_out : out std_logic;
temp_err_out : out std_logic
);
end entity;
architecture rtl_top of hardheat_top is
attribute noprune : boolean;
attribute preserve : boolean;
attribute keep : boolean;
signal clk : std_logic;
attribute noprune of clk : signal is true;
attribute keep of clk : signal is true;
signal temp : signed(16 - 1 downto 0);
signal temp_f : std_logic;
attribute keep of temp : signal is true;
attribute keep of temp_f : signal is true;
attribute noprune of temp : signal is true;
attribute noprune of temp_f : signal is true;
attribute preserve of temp : signal is true;
signal pll_clk : std_logic;
signal pll_locked : std_logic;
signal reset : std_logic;
signal mod_lvl : std_logic_vector(mod_lvl_in'range);
signal mod_lvl_f : std_logic;
signal debounced_sws : std_logic_vector(mod_lvl_in'range);
begin
-- Main clock from PLL on the SoCkit board
pll_p: altera_pll_top
port map
(
refclk => clk_in,
rst => not reset_in,
outclk_0 => pll_clk,
locked => pll_locked
);
clk <= pll_clk;
reset <= not pll_locked;
-- Read modulation level state from switches, debounce
debouncing_p: for i in 0 to mod_lvl_in'high generate
debouncer_p: entity work.debounce(rtl)
generic map
(
DEBOUNCE_D => DEBOUNCE_D,
FLIPFLOPS_N => DEBOUNCE_FF_N
)
port map
(
clk => clk,
reset => reset,
sig_in => mod_lvl_in(i),
sig_out => debounced_sws(i)
);
end generate;
-- Change modulation level when debounced modulation level changes
mod_lvl_p: process(clk, reset)
variable state : std_logic_vector(mod_lvl_in'high downto 0);
begin
if reset = '1' then
state := (others => '1');
mod_lvl <= state;
mod_lvl_f <= '0';
elsif rising_edge(clk) then
mod_lvl_f <= '0';
if not debounced_sws = state then
state := debounced_sws;
mod_lvl <= state;
mod_lvl_f <= '1';
end if;
end if;
end process;
-- TODO: Sig is internally connected!
hardheat_p: entity work.hardheat(rtl)
generic map
(
TDC_N => TDC_N,
FILT_P_SHIFT_N => FILT_P_SHIFT_N,
FILT_I_SHIFT_N => FILT_I_SHIFT_N,
FILT_INIT_OUT_VAL => FILT_INIT_OUT_VAL,
FILT_OUT_OFFSET => FILT_OUT_OFFSET,
FILT_OUT_LIM => FILT_OUT_LIM,
ACCUM_BITS_N => ACCUM_BITS_N,
ACCUM_WORD_N => ACCUM_WORD_N,
LD_LOCK_N => LD_LOCK_N,
LD_ULOCK_N => LD_ULOCK_N,
LD_LOCK_LIMIT => LD_LOCK_LIMIT,
DT_N => DT_N,
DT_VAL => DT_VAL,
TEMP_CONV_D => TEMP_CONV_D,
TEMP_CONV_CMD_D => TEMP_CONV_CMD_D,
TEMP_OW_US_D => TEMP_OW_US_D,
TEMP_PWM_N => TEMP_PWM_N,
TEMP_PWM_MIN_LVL => TEMP_PWM_MIN_LVL,
TEMP_PWM_EN_ON_D => TEMP_PWM_EN_ON_D,
TEMP_P_SHIFT_N => TEMP_P_SHIFT_N,
TEMP_I_SHIFT_N => TEMP_I_SHIFT_N,
TEMP_SETPOINT => TEMP_SETPOINT
)
port map
(
clk => clk,
reset => reset,
ref_in => ref_in,
sig_in => sig_in,
mod_lvl_in => unsigned(mod_lvl),
mod_lvl_in_f => mod_lvl_f,
sig_lh_out => sig_lh_out,
sig_ll_out => sig_ll_out,
sig_rh_out => sig_rh_out,
sig_rl_out => sig_rl_out,
lock_out => lock_out,
ow_in => ow_in,
ow_out => ow_out,
ow_pullup_out => ow_pullup_out,
temp_out => temp,
temp_out_f => temp_f,
temp_err_out => temp_err_out,
pwm_out => pwm_out
);
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity prime is
port(
-- 32-bit input signal to test.
-- Should be registered in the circuit.
number: in std_logic_vector(31 downto 0);
-- Asynchronous reset when equal to '1'.
reset: in std_logic;
-- Is '1' when the data on 'input' is valid.
start: in std_logic;
-- Clock signal for the circuit.
clock: in std_logic;
-- Is '1' when the circuit completes a test for an input.
done: out std_logic;
-- Is '1' iff number is prime and
-- the signal is valid only when done='1'.
prime: out std_logicPas de NoSQL. Après plusieurs expériences avec MongoDB et CouchDB, je n’ai pas été convaincu que les bénéfices dépassaient le coût. Il faudrait un article complet là dessus (qu’on m’a d’ailleurs demandé).
);
component divi_combiner is
port (
dividend : in std_logic_vector(31 downto 0);
divisor : in std_logic_vector(31 downto 0);
quotient : out std_logic_vector(31 downto 0);
remainder : out std_logic_vector(31 downto 0)
);
end component;
component multi_combiner is
port (
operand1 : in std_logic_vector(31 downto 0);
operand2 : in std_logic_vector(31 downto 0);
product : out std_logic_vector(63 downto 0);
);
end component;
end entity;
architecture synth of prime is
type state is (s0, s1, s2, s3);
signal future_state, current_state : state;
signal counter : std_logic_vector(31 downto 0);
multi : multi_combiner port map (
operand1 => counter,
operand2 => counter,
product => product
);
divi : divi_combiner port map (
dividend => num,
divisor => counter,
remainder => remainder,
quotient => open
);
begin
state_switcher : process(clk, future_state, reset)
begin
if reset = '1' then
future_state <= s0;
num <= (others => '0');
elsif rising_edge(clk) then
current_state <= future_state;
end if;
end process;
state_handler : process(remainder, product)
begin
future_state <= current_state;
case current_state is
when s0 => -- Waiting for start = '1'
if start = '1' then
future_state <= s1;
num <= number;
counter <= conv_std_logic_vector(2, 32);
end if;
when s1 => -- Testing if prime
counter <= counter + 1;
if product > num then -- If we exceeded the square root
if remainder = 0 then
future_state <= s2;
else
future_state <= s3;
end if;
else -- If we have not reached the square root yet
if remainder = 0 then
future_state <= s2;
end if;
end if;
when s2 => -- Not prime
done <= '1';
prime <= '0';
when s3 => -- Prime
done <= '1';
prime <= '1';
when others => -- Default case
future_state <= s0;
end case;
end process;
end architecture ; -- synth |
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 214048)
`protect data_block
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`protect end_protected
|
library verilog;
use verilog.vl_types.all;
entity lab50_vlg_check_tst is
port(
led1 : in vl_logic_vector(7 downto 0);
led2 : in vl_logic_vector(7 downto 0);
lose : in vl_logic;
win : in vl_logic;
sampler_rx : in vl_logic
);
end lab50_vlg_check_tst;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:07:57 10/06/2010
-- Design Name:
-- Module Name: Cont0a23 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Cont0a23 is
port (
Load : in STD_LOGIC;
Enable : in STD_LOGIC;
Rst : in STD_LOGIC;
Clk : in STD_LOGIC;
ValorDec : in STD_LOGIC_VECTOR (3 downto 0);
ValorUni : in STD_LOGIC_VECTOR (3 downto 0);
Cuenta : out STD_LOGIC_VECTOR (7 downto 0));
end Cont0a23;
architecture Behavioral of Cont0a23 is
signal ContUni : STD_LOGIC_VECTOR (3 downto 0);
signal ContDec : STD_LOGIC_VECTOR (3 downto 0);
begin
--Contador de Unidades de Hora
process (Rst,Clk)
begin
if (Rst = '1') then
ContUni <= (others => '0');
elsif (rising_edge(Clk)) then
if (Load = '1') then
ContUni <= ValorUni;
elsif (Enable = '1') then
--El Contador de Unidades de Hora se reinicia a Cero cuando el
--Contador de Unidades de Hora vale 9 o cuando las hora vale 23
if ((ContUni = "1001") or (ContDec = "0010" and ContUni = "0011")) then
ContUni <= (others => '0');
else
ContUni <= ContUni + 1;
end if;
end if;
end if;
end process;
--Contador de Decenas de Hora
process (Rst,Clk)
begin
if (Rst = '1') then
ContDec <= (others => '0');
elsif (rising_edge(Clk)) then
if (Load = '1') then
ContDec <= ValorDec;
elsif (Enable = '1') then
--Las decenas de hora se reinician a Cero cuando la hora es 23 (formato militar)
if (ContDec = "0010" and ContUni = "0011") then
ContDec <= (others => '0');
--Solo incrementear la decenas de hora cuando las unidades de hora sean 9
elsif (ContUni = "1001") then
ContDec <= ContDec + 1;
end if;
end if;
end if;
end process;
--Agrupar en un solo bus
Cuenta <= ContDec & ContUni;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:07:57 10/06/2010
-- Design Name:
-- Module Name: Cont0a23 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Cont0a23 is
port (
Load : in STD_LOGIC;
Enable : in STD_LOGIC;
Rst : in STD_LOGIC;
Clk : in STD_LOGIC;
ValorDec : in STD_LOGIC_VECTOR (3 downto 0);
ValorUni : in STD_LOGIC_VECTOR (3 downto 0);
Cuenta : out STD_LOGIC_VECTOR (7 downto 0));
end Cont0a23;
architecture Behavioral of Cont0a23 is
signal ContUni : STD_LOGIC_VECTOR (3 downto 0);
signal ContDec : STD_LOGIC_VECTOR (3 downto 0);
begin
--Contador de Unidades de Hora
process (Rst,Clk)
begin
if (Rst = '1') then
ContUni <= (others => '0');
elsif (rising_edge(Clk)) then
if (Load = '1') then
ContUni <= ValorUni;
elsif (Enable = '1') then
--El Contador de Unidades de Hora se reinicia a Cero cuando el
--Contador de Unidades de Hora vale 9 o cuando las hora vale 23
if ((ContUni = "1001") or (ContDec = "0010" and ContUni = "0011")) then
ContUni <= (others => '0');
else
ContUni <= ContUni + 1;
end if;
end if;
end if;
end process;
--Contador de Decenas de Hora
process (Rst,Clk)
begin
if (Rst = '1') then
ContDec <= (others => '0');
elsif (rising_edge(Clk)) then
if (Load = '1') then
ContDec <= ValorDec;
elsif (Enable = '1') then
--Las decenas de hora se reinician a Cero cuando la hora es 23 (formato militar)
if (ContDec = "0010" and ContUni = "0011") then
ContDec <= (others => '0');
--Solo incrementear la decenas de hora cuando las unidades de hora sean 9
elsif (ContUni = "1001") then
ContDec <= ContDec + 1;
end if;
end if;
end if;
end process;
--Agrupar en un solo bus
Cuenta <= ContDec & ContUni;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:07:57 10/06/2010
-- Design Name:
-- Module Name: Cont0a23 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Cont0a23 is
port (
Load : in STD_LOGIC;
Enable : in STD_LOGIC;
Rst : in STD_LOGIC;
Clk : in STD_LOGIC;
ValorDec : in STD_LOGIC_VECTOR (3 downto 0);
ValorUni : in STD_LOGIC_VECTOR (3 downto 0);
Cuenta : out STD_LOGIC_VECTOR (7 downto 0));
end Cont0a23;
architecture Behavioral of Cont0a23 is
signal ContUni : STD_LOGIC_VECTOR (3 downto 0);
signal ContDec : STD_LOGIC_VECTOR (3 downto 0);
begin
--Contador de Unidades de Hora
process (Rst,Clk)
begin
if (Rst = '1') then
ContUni <= (others => '0');
elsif (rising_edge(Clk)) then
if (Load = '1') then
ContUni <= ValorUni;
elsif (Enable = '1') then
--El Contador de Unidades de Hora se reinicia a Cero cuando el
--Contador de Unidades de Hora vale 9 o cuando las hora vale 23
if ((ContUni = "1001") or (ContDec = "0010" and ContUni = "0011")) then
ContUni <= (others => '0');
else
ContUni <= ContUni + 1;
end if;
end if;
end if;
end process;
--Contador de Decenas de Hora
process (Rst,Clk)
begin
if (Rst = '1') then
ContDec <= (others => '0');
elsif (rising_edge(Clk)) then
if (Load = '1') then
ContDec <= ValorDec;
elsif (Enable = '1') then
--Las decenas de hora se reinician a Cero cuando la hora es 23 (formato militar)
if (ContDec = "0010" and ContUni = "0011") then
ContDec <= (others => '0');
--Solo incrementear la decenas de hora cuando las unidades de hora sean 9
elsif (ContUni = "1001") then
ContDec <= ContDec + 1;
end if;
end if;
end if;
end process;
--Agrupar en un solo bus
Cuenta <= ContDec & ContUni;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:07:57 10/06/2010
-- Design Name:
-- Module Name: Cont0a23 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Cont0a23 is
port (
Load : in STD_LOGIC;
Enable : in STD_LOGIC;
Rst : in STD_LOGIC;
Clk : in STD_LOGIC;
ValorDec : in STD_LOGIC_VECTOR (3 downto 0);
ValorUni : in STD_LOGIC_VECTOR (3 downto 0);
Cuenta : out STD_LOGIC_VECTOR (7 downto 0));
end Cont0a23;
architecture Behavioral of Cont0a23 is
signal ContUni : STD_LOGIC_VECTOR (3 downto 0);
signal ContDec : STD_LOGIC_VECTOR (3 downto 0);
begin
--Contador de Unidades de Hora
process (Rst,Clk)
begin
if (Rst = '1') then
ContUni <= (others => '0');
elsif (rising_edge(Clk)) then
if (Load = '1') then
ContUni <= ValorUni;
elsif (Enable = '1') then
--El Contador de Unidades de Hora se reinicia a Cero cuando el
--Contador de Unidades de Hora vale 9 o cuando las hora vale 23
if ((ContUni = "1001") or (ContDec = "0010" and ContUni = "0011")) then
ContUni <= (others => '0');
else
ContUni <= ContUni + 1;
end if;
end if;
end if;
end process;
--Contador de Decenas de Hora
process (Rst,Clk)
begin
if (Rst = '1') then
ContDec <= (others => '0');
elsif (rising_edge(Clk)) then
if (Load = '1') then
ContDec <= ValorDec;
elsif (Enable = '1') then
--Las decenas de hora se reinician a Cero cuando la hora es 23 (formato militar)
if (ContDec = "0010" and ContUni = "0011") then
ContDec <= (others => '0');
--Solo incrementear la decenas de hora cuando las unidades de hora sean 9
elsif (ContUni = "1001") then
ContDec <= ContDec + 1;
end if;
end if;
end if;
end process;
--Agrupar en un solo bus
Cuenta <= ContDec & ContUni;
end Behavioral;
|
architecture RTL of FIFO is
procedure proc_name (
constant a : in integer;
signal b : in std_logic;
variable c : in std_logic_vector(3 downto 0);
signal d : out std_logic) is
begin
end procedure proc_name;
procedure proc_name (
constant a : in integer;
signal b : in std_logic;
variable c : in std_logic_vector(3 downto 0);
signal d : out std_logic) is
begin
end procedure proc_name;
procedure proc_name (
constant a : in integer;
signal b : in std_logic;
variable c : in std_logic_vector(3 downto 0);
signal d : out std_logic) is
begin
end procedure proc_name;
begin
end architecture RTL;
|
-- NEED RESULT: ARCH00331: Component instantiated with no port or generic clause passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00331
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.6 (1)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00331(ARCH00331)
-- ENT00331_Test_Bench(ARCH00331_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00331 is
generic ( G : in Integer := 1987 ) ;
port ( P : in Time := 100 ns ) ;
end ENT00331 ;
architecture ARCH00331 of ENT00331 is
begin
process
begin
test_report ( "ARCH00331" ,
"Component instantiated with no port or generic clause" ,
(G = 1987) and (P = 100 ns) ) ;
wait ;
end process ;
end ARCH00331 ;
entity ENT00331_Test_Bench is
end ENT00331_Test_Bench ;
architecture ARCH00331_Test_Bench of ENT00331_Test_Bench is
begin
L1:
block
component UUT
generic ( G : in Integer := 1987 ) ;
port ( P : in Time := 100 ns ) ;
end component ;
for CIS1 : UUT use entity WORK.ENT00331 ( ARCH00331 ) ;
begin
CIS1 : UUT
generic map ( open )
port map ( open ) ;
end block L1 ;
end ARCH00331_Test_Bench ;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:02:12 09/08/2015
-- Design Name:
-- Module Name: D:/ProySisDigAva/Temp/P07_BinaryGray_Converter_Loops/BinaryGray_Converter_tb.vhd
-- Project Name: P07_BinaryGray_Converter_Loops
-- Target Device:
-- Tool versions:
-- Description: Testbench for Binary to Gray Converter
--
-- VHDL Test Bench Created by ISE for module: BinaryGray_Converter
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY BinaryGray_Converter_tb IS
END BinaryGray_Converter_tb;
ARCHITECTURE behavior OF BinaryGray_Converter_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT BinaryGray_Converter
PORT(
Bin : IN std_logic_vector(3 downto 0);
Gray : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal Bin : std_logic_vector(3 downto 0) := (others => '0');
--Outputs
signal Gray : std_logic_vector(3 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
-- constant <clock>_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: BinaryGray_Converter PORT MAP (
Bin => Bin,
Gray => Gray
);
-- Clock process definitions
-- <clock>_process :process
-- begin
-- <clock> <= '0';
-- wait for <clock>_period/2;
-- <clock> <= '1';
-- wait for <clock>_period/2;
-- end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
-- wait for <clock>_period*10;
-- insert stimulus here
Bin <= x"0"; wait for 100 ns;
Bin <= x"1"; wait for 100 ns;
Bin <= x"2"; wait for 100 ns;
Bin <= x"3"; wait for 100 ns;
Bin <= x"4"; wait for 100 ns;
Bin <= x"5"; wait for 100 ns;
Bin <= x"6"; wait for 100 ns;
Bin <= x"7"; wait for 100 ns;
Bin <= x"8"; wait for 100 ns;
Bin <= x"9"; wait for 100 ns;
Bin <= x"A"; wait for 100 ns;
Bin <= x"B"; wait for 100 ns;
Bin <= x"C"; wait for 100 ns;
Bin <= x"D"; wait for 100 ns;
Bin <= x"E"; wait for 100 ns;
Bin <= x"F"; wait for 100 ns;
wait;
end process;
END;
|
library verilog;
use verilog.vl_types.all;
entity alt_cal is
generic(
number_of_channels: integer := 1;
channel_address_width: integer := 1;
sim_model_mode : string := "TRUE";
lpm_type : string := "alt_cal";
lpm_hint : string := "UNUSED"
);
port(
busy : out vl_logic;
cal_error : out vl_logic_vector;
clock : in vl_logic;
dprio_addr : out vl_logic_vector(15 downto 0);
dprio_busy : in vl_logic;
dprio_datain : in vl_logic_vector(15 downto 0);
dprio_dataout : out vl_logic_vector(15 downto 0);
dprio_rden : out vl_logic;
dprio_wren : out vl_logic;
quad_addr : out vl_logic_vector(8 downto 0);
remap_addr : in vl_logic_vector(11 downto 0);
reset : in vl_logic;
retain_addr : out vl_logic_vector(0 downto 0);
start : in vl_logic;
transceiver_init: in vl_logic;
testbuses : in vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of number_of_channels : constant is 1;
attribute mti_svvh_generic_type of channel_address_width : constant is 1;
attribute mti_svvh_generic_type of sim_model_mode : constant is 1;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
attribute mti_svvh_generic_type of lpm_hint : constant is 1;
end alt_cal;
|
---------------------------------------------------------------------
-- Divider
--
-- Part of the LXP32 CPU
--
-- Copyright (c) 2016 by Alex I. Kuznetsov
--
-- Based on the NRD (Non Restoring Division) algorithm. Takes
-- 36 cycles to calculate quotient (37 for remainder).
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lxp32_divider is
port(
clk_i: in std_logic;
rst_i: in std_logic;
ce_i: in std_logic;
op1_i: in std_logic_vector(31 downto 0);
op2_i: in std_logic_vector(31 downto 0);
signed_i: in std_logic;
rem_i: in std_logic;
ce_o: out std_logic;
result_o: out std_logic_vector(31 downto 0)
);
end entity;
architecture rtl of lxp32_divider is
-- Complementor signals
signal compl_inv: std_logic;
signal compl_mux: std_logic_vector(31 downto 0);
signal compl_out: std_logic_vector(31 downto 0);
signal inv_res: std_logic;
-- Divider FSM signals
signal fsm_ce: std_logic:='0';
signal dividend: unsigned(31 downto 0);
signal divisor: unsigned(32 downto 0);
signal want_remainder: std_logic;
signal partial_remainder: unsigned(32 downto 0);
signal addend: unsigned(32 downto 0);
signal sum: unsigned(32 downto 0);
signal sum_positive: std_logic;
signal sum_subtract: std_logic;
signal cnt: integer range 0 to 34:=0;
signal ceo: std_logic:='0';
-- Output restoration signals
signal remainder_corrector: unsigned(31 downto 0);
signal remainder_corrector_1: std_logic;
signal remainder_pos: unsigned(31 downto 0);
signal result_pos: unsigned(31 downto 0);
begin
compl_inv<=op1_i(31) and signed_i when ce_i='1' else inv_res;
compl_mux<=op1_i when ce_i='1' else std_logic_vector(result_pos);
compl_op1_inst: entity work.lxp32_compl(rtl)
port map(
clk_i=>clk_i,
compl_i=>compl_inv,
d_i=>compl_mux,
d_o=>compl_out
);
process (clk_i) is
begin
if rising_edge(clk_i) then
if rst_i='1' then
fsm_ce<='0';
want_remainder<='-';
inv_res<='-';
else
fsm_ce<=ce_i;
if ce_i='1' then
want_remainder<=rem_i;
if rem_i='1' then
inv_res<=op1_i(31) and signed_i;
else
inv_res<=(op1_i(31) xor op2_i(31)) and signed_i;
end if;
end if;
end if;
end if;
end process;
-- Main adder/subtractor
addend_gen: for i in addend'range generate
addend(i)<=divisor(i) xor sum_subtract;
end generate;
sum<=partial_remainder+addend+(to_unsigned(0,32)&sum_subtract);
sum_positive<=not sum(32);
-- Divider state machine
process (clk_i) is
begin
if rising_edge(clk_i) then
if rst_i='1' then
cnt<=0;
ceo<='0';
divisor<=(others=>'-');
dividend<=(others=>'-');
partial_remainder<=(others=>'-');
sum_subtract<='-';
else
if cnt=1 then
ceo<='1';
else
ceo<='0';
end if;
if ce_i='1' then
divisor(31 downto 0)<=unsigned(op2_i);
divisor(32)<=op2_i(31) and signed_i;
end if;
if fsm_ce='1' then
dividend<=unsigned(compl_out(30 downto 0)&"0");
partial_remainder<=to_unsigned(0,32)&compl_out(31);
sum_subtract<=not divisor(32);
if want_remainder='1' then
cnt<=34;
else
cnt<=33;
end if;
else
partial_remainder<=sum(31 downto 0)÷nd(31);
sum_subtract<=sum_positive xor divisor(32);
dividend<=dividend(30 downto 0)&sum_positive;
if cnt>0 then
cnt<=cnt-1;
end if;
end if;
end if;
end if;
end process;
-- Output restoration circuit
process (clk_i) is
begin
if rising_edge(clk_i) then
for i in remainder_corrector'range loop
remainder_corrector(i)<=(divisor(i) xor divisor(32)) and not sum_positive;
end loop;
remainder_corrector_1<=divisor(32) and not sum_positive;
remainder_pos<=partial_remainder(32 downto 1)+remainder_corrector+
(to_unsigned(0,31)&remainder_corrector_1);
end if;
end process;
result_pos<=remainder_pos when want_remainder='1' else dividend;
result_o<=compl_out;
ce_o<=ceo;
end architecture;
|
library verilog;
use verilog.vl_types.all;
entity bus_slave_mux is
port(
s0_cs_n : in vl_logic;
s0_rd_data : in vl_logic_vector(31 downto 0);
s0_rdy_n : in vl_logic;
s1_cs_n : in vl_logic;
s1_rd_data : in vl_logic_vector(31 downto 0);
s1_rdy_n : in vl_logic;
s2_cs_n : in vl_logic;
s2_rd_data : in vl_logic_vector(31 downto 0);
s2_rdy_n : in vl_logic;
s3_cs_n : in vl_logic;
s3_rd_data : in vl_logic_vector(31 downto 0);
s3_rdy_n : in vl_logic;
s4_cs_n : in vl_logic;
s4_rd_data : in vl_logic_vector(31 downto 0);
s4_rdy_n : in vl_logic;
s5_cs_n : in vl_logic;
s5_rd_data : in vl_logic_vector(31 downto 0);
s5_rdy_n : in vl_logic;
s6_cs_n : in vl_logic;
s6_rd_data : in vl_logic_vector(31 downto 0);
s6_rdy_n : in vl_logic;
s7_cs_n : in vl_logic;
s7_rd_data : in vl_logic_vector(31 downto 0);
s7_rdy_n : in vl_logic;
m_rd_data : out vl_logic_vector(31 downto 0);
m_rdy_n : out vl_logic
);
end bus_slave_mux;
|
-------------------------------------------------------------------------------
--! @file PreProcessor.vhd
--! @brief Pre-processing unit for an authenticated encryption module.
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
--! SIPO used within this unit follows the following convention:
--! > Order in the test vector file (left to right): A(0) A(1) A(2) … A(N-1)
--! > Order at the SIPO input (time 0 to time N-1) : A(0) A(1) A(2) … A(N-1)
--! > Order at the SIPO output (left to right) : A(0) A(1) A(2) … A(N-1)
--! where A is a single I/O word.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.AEAD_pkg.all;
entity PreProcessor is
generic (
--! I/O size (bits)
G_W : integer := 32; --! Public data input
G_SW : integer := 32; --! Secret data input
--! Reset behavior
G_ASYNC_RSTN : boolean := False; --! Async active low reset
--! Special features activation
G_ENABLE_PAD : boolean := False; --! Enable padding
G_CIPH_EXP : boolean := False; --! Ciphertext expansion
G_REVERSE_CIPH : boolean := False; --! Reversed ciphertext
G_MERGE_TAG : boolean := False; --! Merge tag with data segment
--! Block size (bits)
G_ABLK_SIZE : integer := 128; --! Associated data
G_DBLK_SIZE : integer := 128; --! Data
G_KEY_SIZE : integer := 128; --! Key
--! The number of bits required to hold block size expressed in
--! bytes = log2_ceil(G_DBLK_SIZE/8)
G_LBS_BYTES : integer := 4;
--! Padding options
G_PAD_STYLE : integer := 0; --! Pad style
G_PAD_AD : integer := 1; --! Padding behavior for AD
G_PAD_D : integer := 1 --! Padding behavior for Data
);
port (
--! Global ports
clk : in std_logic;
rst : in std_logic;
--! Publica data ports
pdi_data : in std_logic_vector(G_W -1 downto 0);
pdi_valid : in std_logic;
pdi_ready : out std_logic;
--! Secret data ports
sdi_data : in std_logic_vector(G_SW -1 downto 0);
sdi_valid : in std_logic;
sdi_ready : out std_logic;
--! CipherCore
--! Key
key : out std_logic_vector(G_KEY_SIZE -1 downto 0);
key_ready : in std_logic;
key_valid : out std_logic;
key_update : out std_logic;
--! BDI
bdi : out std_logic_vector(G_DBLK_SIZE -1 downto 0);
decrypt : out std_logic;
bdi_ready : in std_logic;
bdi_valid : out std_logic;
bdi_type : out std_logic_vector(3 -1 downto 0);
bdi_partial : out std_logic;
bdi_eot : out std_logic;
bdi_eoi : out std_logic;
bdi_size : out std_logic_vector(G_LBS_BYTES+1-1 downto 0);
bdi_valid_bytes : out std_logic_vector(G_DBLK_SIZE/8-1 downto 0);
bdi_pad_loc : out std_logic_vector(G_DBLK_SIZE/8-1 downto 0);
--! CMD FIFO
cmd : out std_logic_vector(24 -1 downto 0);
cmd_ready : in std_logic;
cmd_valid : out std_logic
);
end entity PreProcessor;
architecture structure of PreProcessor is
constant DSIZE : integer := G_DBLK_SIZE;
constant ASIZE : integer := G_ABLK_SIZE;
constant WB : integer := G_W/8; --! Word bytes
constant LOG2_WB : integer := log2_ceil(WB);
constant LOG2_KEYBYTES : integer := log2_ceil(512/8);
constant CNT_AWORDS : integer := (G_ABLK_SIZE+(G_W-1))/G_W;
constant CNT_DWORDS : integer := (G_DBLK_SIZE+(G_W-1))/G_W;
constant CNT_KWORDS : integer := (G_KEY_SIZE+(G_SW-1))/G_SW;
constant A_EQ_D : boolean := (DSIZE = ASIZE);
constant P_IS_BUFFER : boolean := not (G_W = DSIZE);
constant S_IS_BUFFER : boolean := not (G_SW = G_KEY_SIZE);
--! =======================================================================
type t_lookup is array (0 to (WB-1))
of std_logic_vector(WB-1 downto 0);
function getVbytesLookup(size: integer) return t_lookup is
variable ret : t_lookup;
begin
for i in 0 to ((size/8)-1) loop
if (i = 0) then
ret(i) := (others => '0');
else
ret(i)(size/8-1 downto size/8-i) := (others => '1');
ret(i)(size/8-i-1 downto 0) := (others => '0');
end if;
end loop;
return ret;
end function getVbytesLookup;
function getPlocLookup(size: integer) return t_lookup is
variable ret : t_lookup;
begin
for i in 0 to ((size/8)-1) loop
ret(i) := (others => '0');
ret(i)((size/8-i)-1) := '1';
--ret(i) := (((size/8-i)-1) => '1', others => '0');
end loop;
return ret;
end function getPlocLookup;
constant VBYTES_LOOKUP : t_lookup := getVbytesLookup(G_W);
constant PLOC_LOOKUP : t_lookup := getPlocLookup(G_W);
--! =======================================================================
--! Control status registers
--! Public
signal sgmt_type : std_logic_vector(4 -1 downto 0);
signal sgmt_pt : std_logic;
signal sgmt_eoi : std_logic;
signal sgmt_eot : std_logic;
signal sgmt_lst : std_logic;
signal sgmt_len : std_logic_vector(16 -1 downto 0);
signal is_decrypt : std_logic;
--! Secret
signal reg_key_update : std_logic;
signal reg_key_valid : std_logic;
--! =======================================================================
--! Control signals
--! Pad
signal set_extra : std_logic;
signal set_req_pad : std_logic;
signal req_pad : std_logic;
signal is_extra : std_logic;
signal sel_pad : std_logic;
signal is_pad : std_logic;
signal en_len : std_logic;
signal en_zero : std_logic;
signal reg_sel_zero : std_logic;
--! Public
signal pdi_rdy : std_logic;
signal bdi_vld : std_logic;
signal set_key_upd : std_logic;
signal ld_sgmt_info : std_logic;
signal ld_ctr : std_logic;
signal en_ctr : std_logic;
signal en_ps : std_logic;
signal en_data : std_logic;
signal ctr : std_logic_vector
(log2_ceil(CNT_DWORDS)-1 downto 0);
signal sel_end : std_logic;
signal ld_end : std_logic;
--! (unused)
signal en_last_word : std_logic;
--! Secret
signal sdi_rdy : std_logic;
signal ld_ctr2 : std_logic;
signal ld_slen : std_logic;
signal en_ctr2 : std_logic;
signal en_slen : std_logic;
signal en_ss : std_logic;
signal en_key : std_logic;
signal slen : std_logic_vector(LOG2_KEYBYTES+1 -1 downto 0);
signal ctr2 : std_logic_vector
(log2_ceil(CNT_KWORDS)-1 downto 0);
--! Cmd
signal wr_cmd : std_logic;
--! =======================================================================
--! State
type t_ps is (S_WAIT_INSTR, S_WAIT_HDR, S_PREP, S_DATA, S_WAIT_READY);
type t_ss is (S_WAIT_INSTR, S_WAIT_HDR, S_DATA, S_WAIT_READY);
signal ps : t_ps; --! Public State
signal nps : t_ps; --! Next Public State
signal ss : t_ss; --! Next Secret State
signal nss : t_ss; --! Next Secret State
--! =======================================================================
--! Data padding
signal word_size : std_logic_vector(LOG2_WB -1 downto 0);
signal data : std_logic_vector(G_W -1 downto 0);
--! Incoming data word
signal pdata : std_logic_vector(G_W -1 downto 0);
signal vbytes : std_logic_vector(WB -1 downto 0);
signal ploc : std_logic_vector(WB -1 downto 0);
--! Additional padding selection when ASIZE /= DSIZE
signal pdata2 : std_logic_vector(G_W -1 downto 0);
signal vbytes2 : std_logic_vector(WB -1 downto 0);
signal ploc2 : std_logic_vector(WB -1 downto 0);
--! Output regs
--! Prep status
signal mux_vbytes : std_logic_vector(WB -1 downto 0);
signal mux_ploc : std_logic_vector(WB -1 downto 0);
signal mux_size : std_logic_vector(LOG2_WB+1 -1 downto 0);
signal size : std_logic_vector(LOG2_WB+1 -1 downto 0);
--! Status
signal reg_bdi_valid : std_logic;
signal reg_size : std_logic_vector(G_LBS_BYTES+1 -1 downto 0);
signal reg_vbytes : std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
signal reg_ploc : std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
--! Data / info
signal reg_key : std_logic_vector(G_KEY_SIZE -1 downto 0);
signal reg_data : std_logic_vector(G_DBLK_SIZE -1 downto 0);
--! =======================================================================
--! Signal aliases
signal p_instr_opcode : std_logic_vector(4 -1 downto 0);
signal p_sgmt_type : std_logic_vector(4 -1 downto 0);
signal p_sgmt_pt : std_logic;
signal p_sgmt_eoi : std_logic;
signal p_sgmt_eot : std_logic;
signal p_sgmt_lst : std_logic;
signal p_sgmt_len : std_logic_vector(16 -1 downto 0);
signal s_instr_opcode : std_logic_vector(4 -1 downto 0);
signal s_sgmt_type : std_logic_vector(4 -1 downto 0);
signal s_sgmt_eot : std_logic;
signal s_sgmt_lst : std_logic;
signal s_sgmt_len : std_logic_vector(LOG2_KEYBYTES+1 -1 downto 0);
begin
--! =======================================================================
--! Datapath (Core)
--! =======================================================================
data <= pdi_data when reg_sel_zero = '0' else (others => '0');
gPad0: if (not G_ENABLE_PAD) generate
pdata <= data;
end generate;
gPad1: if (G_ENABLE_PAD) generate
begin
gPadMode0: if (G_PAD_STYLE = 0) generate
pdata <= data;
end generate;
gPadMode1: if (G_PAD_STYLE = 1) generate
gLoop: for i in WB-1 downto 0 generate
pdata(i*8+7)
<= ploc(i) or data(i*8+7);
pdata(i*8+6 downto i*8)
<= data(i*8+6 downto i*8);
end generate;
end generate;
end generate;
mux_vbytes <= VBYTES_LOOKUP(to_integer(unsigned(word_size)))
when sel_pad = '1'
else (others => '1');
mux_ploc <= PLOC_LOOKUP(to_integer(unsigned(word_size)))
when (sel_pad = '1' and req_pad = '1')
else (others => '0');
mux_size <= '0' & word_size
when sel_pad = '1'
else (LOG2_WB => '1', others => '0');
process(clk)
begin
if rising_edge(clk) then
if (en_len = '1') then
vbytes <= mux_vbytes;
ploc <= mux_ploc;
size <= mux_size;
end if;
if (en_data = '1') then
if ((DSIZE > G_W) and (DSIZE MOD G_W) = 0) then
reg_data <= reg_data(DSIZE-G_W-1 downto 0) & pdata;
reg_vbytes<= reg_vbytes(DSIZE/8-WB-1 downto 0) & vbytes;
reg_ploc <= reg_ploc (DSIZE/8-WB-1 downto 0) & ploc;
elsif ((DSIZE MOD G_W) /= 0) then
if (en_last_word = '0') then
reg_data (DSIZE-1 downto (DSIZE MOD G_W )) <=
reg_data(DSIZE-G_W-1 downto (DSIZE MOD G_W))
& pdata2;
reg_vbytes(DSIZE/8-1 downto ((DSIZE/8) MOD WB)) <=
reg_vbytes(DSIZE/8-WB-1 downto ((DSIZE/8) MOD WB))
& vbytes2;
reg_ploc(DSIZE/8-1 downto ((DSIZE/8) MOD WB)) <=
reg_ploc(DSIZE/8-WB-1 downto ((DSIZE/8) MOD WB))
& ploc2;
else
reg_data ((DSIZE mod G_W)-1 downto 0) <=
pdata2(G_W -1 downto G_W /2);
reg_vbytes(((DSIZE/8) mod WB)-1 downto 0) <=
vbytes(WB-1 downto WB/2);
reg_ploc(((DSIZE/8) mod WB)-1 downto 0) <=
ploc2(WB-1 downto WB/2);
end if;
end if;
end if;
if (en_key = '1') then
if (G_SW < G_KEY_SIZE) then
reg_key <= reg_key(G_KEY_SIZE-G_SW-1 downto 0) & sdi_data;
end if;
end if;
end if;
end process;
--! =======================================================================
--! Registers with rst for controller and datapath
--! =======================================================================
gSyncRst:
if (not G_ASYNC_RSTN) generate
process(clk)
begin
if rising_edge(clk) then
if (rst = '1') then
--! Datapath
reg_size <= (others => '0');
reg_bdi_valid <= '0';
reg_key_update <= '0';
reg_key_valid <= '0';
--! Control
req_pad <= '0';
ps <= S_WAIT_INSTR;
ss <= S_WAIT_INSTR;
else
--! Datapath
if (en_data = '1') then
reg_size <= std_logic_vector(
unsigned(reg_size) + unsigned(size));
elsif (bdi_ready = '1') then
reg_size <= (others => '0');
end if;
--! BDI valid register
if (en_ps = '1' and nps = S_WAIT_READY) then
reg_bdi_valid <= '1';
elsif (reg_bdi_valid = '1' and bdi_ready = '1') then
reg_bdi_valid <= '0';
end if;
--! Key update register
if (set_key_upd = '1') then
reg_key_update <= '1';
elsif (key_ready = '1'
and ((S_IS_BUFFER and reg_key_valid = '1')
or (not S_IS_BUFFER and sdi_valid = '1')))
then
reg_key_update <= '0';
end if;
--! Key valid register
if (en_ss = '1' and nss = S_WAIT_READY) then
reg_key_valid <= '1';
elsif (key_ready = '1' and reg_key_valid = '1') then
reg_key_valid <= '0';
end if;
--! Control
if (set_req_pad = '1') then
req_pad <= '1';
elsif (en_len = '1' and sel_pad = '1')
or ps = S_WAIT_INSTR
then
req_pad <= '0';
end if;
if (en_ps = '1') then
ps <= nps;
end if;
if (en_ss = '1') then
ss <= nss;
end if;
end if;
end if;
end process;
end generate;
gAsyncRstn:
if (G_ASYNC_RSTN) generate
process(clk, rst)
begin
if (rst = '0') then
--! Datapath
reg_size <= (others => '0');
reg_bdi_valid <= '0';
reg_key_update <= '0';
reg_key_valid <= '0';
--! Control
req_pad <= '0';
ps <= S_WAIT_INSTR;
ss <= S_WAIT_INSTR;
elsif rising_edge(clk) then
--! Datapath
if (en_data = '1') then
reg_size <= std_logic_vector(
unsigned(reg_size) + unsigned(size));
elsif (bdi_ready = '1') then
reg_size <= (others => '0');
end if;
--! BDI valid register
if (en_ps = '1' and nps = S_WAIT_READY) then
reg_bdi_valid <= '1';
elsif (reg_bdi_valid = '1' and bdi_ready = '1') then
reg_bdi_valid <= '0';
end if;
--! Key update register
if (set_key_upd = '1') then
reg_key_update <= '1';
elsif (key_ready = '1'
and ((S_IS_BUFFER and reg_key_valid = '1')
or (not S_IS_BUFFER and sdi_valid = '1')))
then
reg_key_update <= '0';
end if;
--! Key valid register
if (en_ss = '1' and nss = S_WAIT_READY) then
reg_key_valid <= '1';
elsif (key_ready = '1' and reg_key_valid = '1') then
reg_key_valid <= '0';
end if;
--! Control
if (set_req_pad = '1') then
req_pad <= '1';
elsif (en_len = '1' and sel_pad = '1')
or ps = S_WAIT_INSTR
then
req_pad <= '0';
end if;
if (en_ps = '1') then
ps <= nps;
end if;
if (en_ss = '1') then
ss <= nss;
end if;
end if;
end process;
end generate;
--! =======================================================================
--! Datapath (Output)
--! =======================================================================
pdi_ready <= pdi_rdy;
sdi_ready <= sdi_rdy;
--! Public
decrypt <= is_decrypt;
gDsizeEq:
if (not P_IS_BUFFER) generate
bdi <= pdata;
bdi_vld <= pdi_valid when (ps = S_DATA) else '0';
bdi_type <= sgmt_type(3 downto 1);
gNotCiph:
if (not G_CIPH_EXP) generate
bdi_eot <= sgmt_eot
when (ps = S_DATA and unsigned(sgmt_len) = 0)
else '0';
bdi_eoi <= sgmt_eoi
when (ps = S_DATA and unsigned(sgmt_len) = 0)
else '0';
end generate;
gCiph:
if (G_CIPH_EXP) generate
bdi_eot <= sgmt_eot or sgmt_eoi
when (ps = S_DATA and unsigned(sgmt_len) = 0)
else '0';
bdi_eoi <= sgmt_lst
when (ps = S_DATA and unsigned(sgmt_len) = 0)
else '0';
bdi_partial <= sgmt_pt;
end generate;
bdi_size <= size;
bdi_valid_bytes <= vbytes;
bdi_pad_loc <= ploc;
end generate;
gDsizeNeq:
if (P_IS_BUFFER) generate
signal en_eoi_last : std_logic;
signal en_eot_last : std_logic;
begin
bdi <= reg_data;
bdi_vld <= reg_bdi_valid;
bdi_type <= sgmt_type(3 downto 1);
pEnd:
process(clk)
begin
if rising_edge(clk) then
if (ld_end = '1') then
if (not G_CIPH_EXP) then
bdi_eot <= sgmt_eot and sel_end;
bdi_eoi <= sgmt_eoi and sel_end;
else
bdi_eot <= (sgmt_eot or en_eot_last) and sel_end;
bdi_eoi <= (sgmt_eoi or en_eoi_last) and sel_end;
end if;
end if;
end if;
end process;
gCiph:
if (G_CIPH_EXP) generate
en_eot_last <= '1' when
((sgmt_eoi = '1' and sgmt_type = ST_NPUB)
or (sgmt_eoi = '1' and G_ENABLE_PAD
and sgmt_type(3 downto 2) = ST_A
and G_PAD_AD /= 2 and G_PAD_AD /= 4)
or (sgmt_eoi = '1' and G_ENABLE_PAD
and sgmt_type(3 downto 2) = ST_D
and G_PAD_D /= 2 and G_PAD_D /= 4))
else '0';
en_eoi_last <= '1' when en_eot_last = '1' and is_decrypt = '0'
else '0';
bdi_partial <= sgmt_pt;
end generate;
bdi_size <= reg_size;
bdi_valid_bytes <= reg_vbytes;
bdi_pad_loc <= reg_ploc;
end generate;
bdi_valid <= bdi_vld;
--! Secret
gTsizeEq:
if (S_IS_BUFFER) generate
key_valid <= reg_key_valid;
key <= reg_key;
end generate;
gTsizeNeq:
if (not S_IS_BUFFER) generate
key_valid <= sdi_valid when (ss = S_DATA) else '0';
key <= sdi_data;
end generate;
key_update <= reg_key_update;
--! CMD FIFO
cmd <= pdi_data(G_W-1 downto G_W-5) & '0'
& pdi_data(G_W-7 downto G_W-8)
& pdi_data(G_W-17 downto G_W-32);
cmd_valid <= wr_cmd;
--! =======================================================================
--! Control
--! =======================================================================
process(clk)
begin
if rising_edge(clk) then
--! Operation register
if (ps = S_WAIT_INSTR) then
is_decrypt <= p_instr_opcode(0);
end if;
--! Length register
if (ld_sgmt_info = '1') then
sgmt_type <= p_sgmt_type;
if (G_CIPH_EXP) then
sgmt_pt <= p_sgmt_pt;
end if;
sgmt_eoi <= p_sgmt_eoi;
sgmt_eot <= p_sgmt_eot;
sgmt_lst <= p_sgmt_lst;
sgmt_len <= p_sgmt_len;
else
if (en_len = '1') then
if (sel_pad = '1') then
sgmt_len <= (others => '0');
else
sgmt_len <= std_logic_vector(unsigned(sgmt_len)-WB);
end if;
end if;
end if;
--! Padding activation register
if (en_len = '1') then
is_pad <= sel_pad;
end if;
--! Select zero register
if (ld_sgmt_info = '1')
or (P_IS_BUFFER and not A_EQ_D
and bdi_ready = '1' and unsigned(sgmt_len) > 0)
then
reg_sel_zero <= '0';
elsif (unsigned(sgmt_len) = 0 and en_len = '1')
or (not A_EQ_D and en_zero = '1')
then
reg_sel_zero <= '1';
end if;
--! Secret length register
if (ld_slen = '1') then
slen <= s_sgmt_len;
elsif (en_slen = '1') then
slen <= std_logic_vector(unsigned(slen)-G_KEY_SIZE/8);
end if;
--! Extra block register
if (ld_sgmt_info = '1' or (bdi_ready = '1' and bdi_vld = '1')) then
is_extra <= '0';
elsif (set_extra = '1') then
is_extra <= '1';
end if;
--! Public data input counter register
if (ld_ctr = '1') then
ctr <= (others => '0');
elsif (en_ctr = '1') then
ctr <= std_logic_vector(unsigned(ctr) + 1);
end if;
--! Secret data input counter register
if (ld_ctr2 = '1') then
ctr2 <= (others => '0');
elsif (en_ctr2 = '1') then
ctr2 <= std_logic_vector(unsigned(ctr2) + 1);
end if;
end if;
end process;
sel_pad <= '1' when (unsigned(sgmt_len) < WB) else '0';
word_size <= sgmt_len(LOG2_WB-1 downto 0);
--! HDR Dissection
p_instr_opcode <= pdi_data(G_W-1 downto G_W-4);
p_sgmt_type <= pdi_data(G_W-1 downto G_W-4);
p_sgmt_pt <= pdi_data(G_W-5);
p_sgmt_eoi <= pdi_data(G_W-6);
p_sgmt_eot <= pdi_data(G_W-7);
p_sgmt_lst <= pdi_data(G_W-8);
p_sgmt_len <= pdi_data(G_W-17 downto G_W-32);
s_instr_opcode <= sdi_data(G_SW-1 downto G_SW-4);
s_sgmt_type <= sdi_data(G_SW-1 downto G_SW-4);
s_sgmt_eot <= sdi_data(G_SW-7);
s_sgmt_lst <= sdi_data(G_SW-8);
s_sgmt_len <= sdi_data(G_SW-32+LOG2_KEYBYTES downto G_SW-32);
gPdiComb:
process(ps, p_instr_opcode, pdi_valid,
sgmt_len, sgmt_type, sgmt_eot, sgmt_lst,
p_sgmt_eot, p_sgmt_type,
bdi_ready, cmd_ready, reg_sel_zero,
is_extra, ctr)
begin
nps <= ps;
pdi_rdy <= '1';
set_key_upd <= '0';
set_req_pad <= '0';
ld_sgmt_info <= '0';
if (P_IS_BUFFER) then
ld_end <= '0';
set_extra <= '0';
end if;
ld_ctr <= '0';
en_data <= '0';
en_ps <= '0';
en_len <= '0';
en_ctr <= '0';
en_zero <= '0';
wr_cmd <= '0';
case ps is
when S_WAIT_INSTR =>
ld_ctr <= '1';
if (p_instr_opcode(3 downto 1) = OP_ENCDEC) then
nps <= S_WAIT_HDR;
end if;
if (p_instr_opcode = OP_ACTKEY) then
set_key_upd <= '1';
end if;
if (cmd_ready = '0') then
pdi_rdy <= '0';
end if;
if (pdi_valid = '1') then
en_ps <= '1';
wr_cmd <= '1';
end if;
when S_WAIT_HDR =>
ld_sgmt_info <= '1';
nps <= S_PREP;
if (cmd_ready = '0') then
pdi_rdy <= '0';
end if;
if (pdi_valid = '1' and cmd_ready = '1') then
en_ps <= '1';
if (p_sgmt_type(3 downto 2) = ST_D
or p_sgmt_type(3 downto 1) = ST_NSEC)
then
wr_cmd <= '1';
end if;
end if;
if (G_ENABLE_PAD) then
if (p_sgmt_eot = '1') then
if (p_sgmt_type(3 downto 2) = ST_A and G_PAD_AD > 0)
or (p_sgmt_type(3 downto 2) = ST_D and G_PAD_D > 0)
then
set_req_pad <= '1';
end if;
end if;
end if;
when S_PREP =>
pdi_rdy <= '0';
--! state transition
if (unsigned(sgmt_len) = 0) then
if (G_ENABLE_PAD) and
--! Add a new block based on padding behavior
((sgmt_type(3 downto 2) = ST_A
and (G_PAD_AD = 2 or G_PAD_AD = 4))
or (sgmt_type(3 downto 2) = ST_D
and (G_PAD_D = 2 or G_PAD_D = 4)))
then
nps <= S_DATA;
else
if (sgmt_lst = '1') then
nps <= S_WAIT_INSTR;
else
nps <= S_WAIT_HDR;
end if;
end if;
else
nps <= S_DATA;
end if;
en_len <= '1';
en_ps <= '1';
when S_DATA =>
if (not P_IS_BUFFER) then
--! Without buffer
if (reg_sel_zero = '1'
or (not P_IS_BUFFER
and (pdi_valid = '0' or bdi_ready = '0')))
then
pdi_rdy <= '0';
end if;
if (unsigned(sgmt_len) = 0)
and not (req_pad = '1' and G_ENABLE_PAD
and ((sgmt_type(3 downto 2) = ST_A and G_PAD_AD > 2)
or (sgmt_type(3 downto 2) = ST_D and G_PAD_D > 2)))
then
if (sgmt_lst = '1') then
nps <= S_WAIT_INSTR;
else
nps <= S_WAIT_HDR;
end if;
end if;
else
--! With buffer
if (reg_sel_zero = '1') then
pdi_rdy <= '0';
end if;
if (unsigned(ctr) = CNT_DWORDS-1) then
nps <= S_WAIT_READY;
end if;
if (unsigned(ctr) = CNT_DWORDS-2) then
ld_end <= '1';
end if;
if (unsigned(sgmt_len) = WB and G_ENABLE_PAD
and sgmt_eot = '1'
and ((sgmt_type(3 downto 2) = ST_A and G_PAD_AD > 2)
or (sgmt_type(3 downto 2) = ST_D
and G_PAD_D > 2
and (not G_CIPH_EXP
or (G_CIPH_EXP and is_decrypt = '0')))))
then
if (A_EQ_D) then
if unsigned(ctr) = CNT_DWORDS-2 then
set_extra <= '1';
end if;
else
if ((sgmt_type(3 downto 2) = ST_A
and unsigned(ctr) = CNT_AWORDS-2)
or (sgmt_type(3 downto 2) = ST_D
and unsigned(ctr) = CNT_DWORDS-2))
then
set_extra <= '1';
end if;
end if;
end if;
--! if ASIZE < DSIZE
if (not A_EQ_D) then
if (sgmt_type(3 downto 2) = ST_A
and unsigned(ctr) >= CNT_AWORDS-1)
then
en_zero <= '1';
end if;
end if;
end if;
if (reg_sel_zero = '1'
or (pdi_valid = '1'
and (P_IS_BUFFER
or (not P_IS_BUFFER and bdi_ready = '1'))))
then
if (sgmt_type(3 downto 2) /= ST_A
and sgmt_type(3 downto 2) /= ST_D)
then
--! Not AD or D segment
if (P_IS_BUFFER) then
if (unsigned(ctr) /= CNT_DWORDS-1) then
en_len <= '1';
end if;
else
en_len <= '1';
end if;
else
--! AD or D segment
if (P_IS_BUFFER) then
if (A_EQ_D) then
if (unsigned(ctr) /= CNT_DWORDS-1) then
en_len <= '1';
end if;
else
if ((sgmt_type(3 downto 2) = ST_A
and unsigned(ctr) < CNT_AWORDS-1)
or (sgmt_type(3 downto 2) /= ST_A
and unsigned(ctr) /= CNT_DWORDS-1))
then
en_len <= '1';
end if;
end if;
else
en_len <= '1';
end if;
end if;
if (P_IS_BUFFER) then
en_ctr <= '1';
en_data <= '1';
end if;
en_ps <= '1';
end if;
when S_WAIT_READY =>
pdi_rdy <= '0';
ld_ctr <= '1';
if (unsigned(sgmt_len) = 0) then
if ((G_ENABLE_PAD and (G_PAD_AD > 2 or G_PAD_D > 2))
and is_extra = '1')
then
nps <= S_DATA;
else
if (sgmt_lst = '1') then
nps <= S_WAIT_INSTR;
else
nps <= S_WAIT_HDR;
end if;
end if;
else
nps <= S_DATA;
end if;
if (bdi_ready = '1') then
en_len <= '1';
en_ps <= '1';
end if;
end case;
end process;
sel_end <= '1' when (unsigned(sgmt_len) <= WB
and (is_extra = '0' and set_extra = '0'))
else '0';
gSdiComb:
process(ss, s_instr_opcode, sdi_valid, ctr2, key_ready, slen)
begin
nss <= ss;
sdi_rdy <= '0';
en_key <= '0';
ld_ctr2 <= '0';
ld_slen <= '0';
en_ctr2 <= '0';
en_slen <= '0';
en_ss <= '0';
case ss is
when S_WAIT_INSTR =>
ld_ctr2 <= '1';
sdi_rdy <= '1';
if (s_instr_opcode = OP_LDKEY) then
nss <= S_WAIT_HDR;
end if;
if (sdi_valid = '1') then
en_ss <= '1';
end if;
when S_WAIT_HDR =>
nss <= S_DATA;
ld_slen <= '1';
sdi_rdy <= '1';
if (sdi_valid = '1') then
en_ss <= '1';
end if;
when S_DATA =>
if (not S_IS_BUFFER) then
nss <= S_WAIT_INSTR;
if (sdi_valid = '1' and key_ready = '1') then
en_slen <= '1';
sdi_rdy <= '1';
if (unsigned(slen) = G_KEY_SIZE/8) then
en_ss <= '1';
end if;
end if;
else
sdi_rdy <= '1';
nss <= S_WAIT_READY;
if (sdi_valid = '1') then
en_ctr2 <= '1';
en_key <= '1';
if (unsigned(ctr2) = CNT_KWORDS-1) then
en_ss <= '1';
end if;
end if;
end if;
when S_WAIT_READY =>
if (unsigned(slen) = G_KEY_SIZE/8) then
nss <= S_WAIT_INSTR;
else
nss <= S_DATA;
end if;
ld_ctr2 <= '1';
if (key_ready = '1') then
en_ss <= '1';
en_slen <= '1';
end if;
end case;
end process;
end architecture structure;
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