content
stringlengths 1
1.04M
⌀ |
|---|
entity open_bot is
port (
i : in integer;
o : out integer;
v : out bit_vector(3 downto 0) := X"f" );
end entity;
architecture test of open_bot is
begin
v(1) <= '0';
process (i) is
begin
o <= i + 1;
end process;
end architecture;
-------------------------------------------------------------------------------
entity open_top is
end entity;
architecture test of open_top is
signal x : integer;
begin
uut: entity work.open_bot
port map ( x, open );
end architecture;
|
entity open_bot is
port (
i : in integer;
o : out integer;
v : out bit_vector(3 downto 0) := X"f" );
end entity;
architecture test of open_bot is
begin
v(1) <= '0';
process (i) is
begin
o <= i + 1;
end process;
end architecture;
-------------------------------------------------------------------------------
entity open_top is
end entity;
architecture test of open_top is
signal x : integer;
begin
uut: entity work.open_bot
port map ( x, open );
end architecture;
|
entity open_bot is
port (
i : in integer;
o : out integer;
v : out bit_vector(3 downto 0) := X"f" );
end entity;
architecture test of open_bot is
begin
v(1) <= '0';
process (i) is
begin
o <= i + 1;
end process;
end architecture;
-------------------------------------------------------------------------------
entity open_top is
end entity;
architecture test of open_top is
signal x : integer;
begin
uut: entity work.open_bot
port map ( x, open );
end architecture;
|
entity open_bot is
port (
i : in integer;
o : out integer;
v : out bit_vector(3 downto 0) := X"f" );
end entity;
architecture test of open_bot is
begin
v(1) <= '0';
process (i) is
begin
o <= i + 1;
end process;
end architecture;
-------------------------------------------------------------------------------
entity open_top is
end entity;
architecture test of open_top is
signal x : integer;
begin
uut: entity work.open_bot
port map ( x, open );
end architecture;
|
entity open_bot is
port (
i : in integer;
o : out integer;
v : out bit_vector(3 downto 0) := X"f" );
end entity;
architecture test of open_bot is
begin
v(1) <= '0';
process (i) is
begin
o <= i + 1;
end process;
end architecture;
-------------------------------------------------------------------------------
entity open_top is
end entity;
architecture test of open_top is
signal x : integer;
begin
uut: entity work.open_bot
port map ( x, open );
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.rtl_pack.all;
entity fifo is
generic (
depth_order_g : positive;
data_width_g : positive;
prefill_g : natural := 0);
port (
a_reset_i : in std_ulogic := '0';
a_clock_i : in std_ulogic;
a_full_o : out std_ulogic;
a_write_i : in std_ulogic := '1';
a_data_i : in std_ulogic_vector(data_width_g-1 downto 0);
b_reset_i : in std_ulogic := '0';
b_clock_i : in std_ulogic;
b_read_i : in std_ulogic := '1';
b_empty_o : out std_ulogic;
b_prefill_reached_o : out std_ulogic;
b_data_o : out std_ulogic_vector(data_width_g-1 downto 0));
constant check_prefill : boolean := check(prefill_g < 2**depth_order_g);
end;
library ieee;
use ieee.numeric_std.all;
library work;
use work.greycode_pack.all;
architecture rtl of fifo is
constant sync_stages_c : positive := 2;
-- Compensate for sync and pipeline delay.
-- This assumes that fifo will be written continuously, once writing started.
constant b_prefill_c : natural := maximum(prefill_g - sync_stages_c - 1, 1);
subtype address_t is greycode_t(depth_order_g-1 downto 0);
signal a_write_address, b_read_address : address_t := (others => '0');
signal b_prefill_reached : std_ulogic := '0';
signal b_write_address, a_read_address : address_t;
signal a_full, b_empty : std_ulogic;
signal b_next_read_address : address_t;
signal b_next_prefill_reached : std_ulogic;
signal async_fill : integer range 0 to 2**depth_order_g-1;
begin
dual_port_ram : entity work.dual_port_ram
generic map (
address_width_g => depth_order_g,
data_width_g => data_width_g)
port map (
a_clock_i => a_clock_i,
a_address_i => a_write_address,
a_write_i => a_write_i,
a_data_i => a_data_i,
b_clock_i => b_clock_i,
b_address_i => b_next_read_address,
b_read_i => '1',
b_data_o => b_data_o);
a_full <= to_stdulogic(a_write_address + 1 = a_read_address);
a_full_o <= a_full;
a_write : process(a_reset_i, a_clock_i)
begin
if a_reset_i = '1' then
a_write_address <= (others => '0');
elsif rising_edge(a_clock_i) then
assert (a_write_i and a_full) = '0' report "fifo: write full fifo";
if (a_write_i and not a_full) = '1' then
a_write_address <= a_write_address + 1;
end if;
end if;
end process;
sync_write_address_a_b : entity work.sync
generic map (
width_g => depth_order_g,
stages_g => sync_stages_c,
reset_value_g => '0')
port map (
reset_i => b_reset_i,
clock_i => b_clock_i,
data_i => a_write_address,
data_o => b_write_address);
b_empty <= to_stdulogic(b_read_address = b_write_address) or not b_prefill_reached;
b_next_read_address <= b_read_address + 1 when (b_read_i and not b_empty) = '1' else b_read_address;
b_next_prefill_reached <= b_prefill_reached or to_stdulogic(to_integer(unsigned(to_binary(b_write_address))) >= b_prefill_c);
-- Cannot only use equal, because values may be lost in the sync.
b_empty_o <= b_empty;
b_prefill_reached_o <= b_prefill_reached;
b_read_sync : process(b_reset_i, b_clock_i)
begin
if b_reset_i = '1' then
b_read_address <= (others => '0');
b_prefill_reached <= to_stdulogic(prefill_g = 0);
elsif rising_edge(b_clock_i) then
b_read_address <= b_next_read_address;
b_prefill_reached <= b_next_prefill_reached;
end if;
end process;
sync_read_address_b_a : entity work.sync
generic map (
width_g => depth_order_g,
reset_value_g => '0')
port map (
reset_i => a_reset_i,
clock_i => a_clock_i,
data_i => b_read_address,
data_o => a_read_address);
async_fill <= (to_integer(unsigned(to_binary(a_write_address))) - to_integer(unsigned(to_binary(b_read_address)))) mod 2**depth_order_g;
end; |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: decryption_mem_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY decryption_mem_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
CLKB_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE decryption_mem_synth_ARCH OF decryption_mem_synth IS
COMPONENT decryption_mem_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
RSTB : IN STD_LOGIC; --opt port
ADDRB : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL CLKB: STD_LOGIC := '0';
SIGNAL RSTB: STD_LOGIC := '0';
SIGNAL ADDRB: STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRB_R: STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTB: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL clkb_in_i: STD_LOGIC;
SIGNAL RESETB_SYNC_R1 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R2 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R3 : STD_LOGIC := '1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
-- clkb_buf: bufg
-- PORT map(
-- i => CLKB_IN,
-- o => clkb_in_i
-- );
clkb_in_i <= CLKB_IN;
CLKB <= clkb_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
RSTB <= RESETB_SYNC_R3 AFTER 50 ns;
PROCESS(clkb_in_i)
BEGIN
IF(RISING_EDGE(clkb_in_i)) THEN
RESETB_SYNC_R1 <= RESET_IN;
RESETB_SYNC_R2 <= RESETB_SYNC_R1;
RESETB_SYNC_R3 <= RESETB_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 8,
READ_WIDTH => 8 )
PORT MAP (
CLK => clkb_in_i,
RST => RSTB,
EN => CHECKER_EN_R,
DATA_IN => DOUTB,
STATUS => ISSUE_FLAG(0)
);
PROCESS(clkb_in_i)
BEGIN
IF(RISING_EDGE(clkb_in_i)) THEN
IF(RSTB='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLKA => clk_in_i,
CLKB => clkb_in_i,
RSTB => RSTB,
TB_RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
ADDRB => ADDRB,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ADDRB_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
ADDRB_R <= ADDRB AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: decryption_mem_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
CLKA => CLKA,
--Port B
RSTB => RSTB,
ADDRB => ADDRB_R,
DOUTB => DOUTB,
CLKB => CLKB
);
END ARCHITECTURE;
|
----------------------------------------------------------------------------------
-- spi_transmitter.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Takes 32bit (one sample) and sends it out on the SPI port.
-- End of transmission is signalled by taking back the busy flag.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity spi_transmitter is
port(
data : in std_logic_vector (31 downto 0);
tx_bytes : in integer range 0 to 4;
send : in std_logic;
clock : in std_logic;
sclk : in std_logic;
tx : out std_logic := '0';
cs : in std_logic;
busy: out std_logic := '0';
reset : in std_logic;
dataReady : out std_logic := '0'
);
end spi_transmitter;
architecture behavioral of spi_transmitter is
type states is (IDLE, START, WAIT_CS_LO, SEND_BITS, WAIT_CS_HI);
signal tx_buf : std_logic_vector (39 downto 0) := (others => '0');
signal bits : integer range 0 to 7;
signal bytes, end_byte : integer range 0 to 4;
signal rsync_sclk, rsync_cs : std_logic_vector(1 downto 0) := (others => '0');
signal state: states;
signal send_i: std_logic := '1';
signal timeout : std_logic_vector(31 downto 0) := (others => '0');
begin
process(clock)
begin
if rising_edge(clock) then
rsync_sclk <= rsync_sclk(0) & sclk;
rsync_cs <= rsync_cs(0) & cs;
case state is
when IDLE =>
if send = '1' then
state <= START;
busy <= '1';
dataReady <= '1';
end if;
tx_buf <= x"aa" & data(7 downto 0) & data(15 downto 8)
& data(23 downto 16) & data(31 downto 24);
end_byte <= tx_bytes;
bytes <= 0;
bits <= 0;
when START =>
-- tx starts at cs falling edge
--if rsync_cs = "10" then
-- timeout <= timeout +1;
-- if timeout = x"ffffffffff" then
-- timeout <= (others => '0');
-- state <= WAIT_CS_HI;
-- elsif rsync_cs = "10" or cs = '0' then
if reset = '1' then
state <= IDLE;
elsif rsync_cs = "10" or cs = '0' then
state <= WAIT_CS_LO;
tx <= tx_buf(39);
-- timeout <= (others => '0');
end if;
when WAIT_CS_LO =>
-- wait for cs before sending the next byte
if cs = '0' and rsync_sclk = "01" then
state <= SEND_BITS;
tx_buf <= tx_buf(38 downto 0) & '0';
bytes <= bytes + 1;
elsif bytes = end_byte+1 then
state <= WAIT_CS_HI;
dataReady <= '0';
end if;
tx <= tx_buf(39);
when SEND_BITS =>
-- If we are waiting more then 200ns then something is off. We have a 100Mhz clock so 0x14 is 200ns.
-- timeout <= timeout +1;
-- if timeout = x"0b" then
-- timeout <= (others => '0');
-- state <= START;
-- bits <= 0;
-- bytes <= bytes - 1;
-- -- transfer bits at rising edge of sclk
-- elsif rsync_sclk = "01" then
if reset = '1' then
state <= IDLE;
elsif rsync_sclk = "01" then
tx_buf <= tx_buf(38 downto 0) & '0';
bits <= bits + 1;
-- timeout <= (others => '0');
elsif bits = 7 then
state <= WAIT_CS_LO;
bits <= 0;
-- timeout <= (others => '0');
end if;
tx <= tx_buf(39);
when WAIT_CS_HI =>
-- tx stops until cs rising edge
-- if rsync_cs = "01" or cs = '0' then
state <= IDLE;
busy <= '0';
-- end if;
end case;
end if;
end process;
end behavioral;
|
----------------------------------------------------------------------------------
-- spi_transmitter.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Takes 32bit (one sample) and sends it out on the SPI port.
-- End of transmission is signalled by taking back the busy flag.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity spi_transmitter is
port(
data : in std_logic_vector (31 downto 0);
tx_bytes : in integer range 0 to 4;
send : in std_logic;
clock : in std_logic;
sclk : in std_logic;
tx : out std_logic := '0';
cs : in std_logic;
busy: out std_logic := '0';
reset : in std_logic;
dataReady : out std_logic := '0'
);
end spi_transmitter;
architecture behavioral of spi_transmitter is
type states is (IDLE, START, WAIT_CS_LO, SEND_BITS, WAIT_CS_HI);
signal tx_buf : std_logic_vector (39 downto 0) := (others => '0');
signal bits : integer range 0 to 7;
signal bytes, end_byte : integer range 0 to 4;
signal rsync_sclk, rsync_cs : std_logic_vector(1 downto 0) := (others => '0');
signal state: states;
signal send_i: std_logic := '1';
signal timeout : std_logic_vector(31 downto 0) := (others => '0');
begin
process(clock)
begin
if rising_edge(clock) then
rsync_sclk <= rsync_sclk(0) & sclk;
rsync_cs <= rsync_cs(0) & cs;
case state is
when IDLE =>
if send = '1' then
state <= START;
busy <= '1';
dataReady <= '1';
end if;
tx_buf <= x"aa" & data(7 downto 0) & data(15 downto 8)
& data(23 downto 16) & data(31 downto 24);
end_byte <= tx_bytes;
bytes <= 0;
bits <= 0;
when START =>
-- tx starts at cs falling edge
--if rsync_cs = "10" then
-- timeout <= timeout +1;
-- if timeout = x"ffffffffff" then
-- timeout <= (others => '0');
-- state <= WAIT_CS_HI;
-- elsif rsync_cs = "10" or cs = '0' then
if reset = '1' then
state <= IDLE;
elsif rsync_cs = "10" or cs = '0' then
state <= WAIT_CS_LO;
tx <= tx_buf(39);
-- timeout <= (others => '0');
end if;
when WAIT_CS_LO =>
-- wait for cs before sending the next byte
if cs = '0' and rsync_sclk = "01" then
state <= SEND_BITS;
tx_buf <= tx_buf(38 downto 0) & '0';
bytes <= bytes + 1;
elsif bytes = end_byte+1 then
state <= WAIT_CS_HI;
dataReady <= '0';
end if;
tx <= tx_buf(39);
when SEND_BITS =>
-- If we are waiting more then 200ns then something is off. We have a 100Mhz clock so 0x14 is 200ns.
-- timeout <= timeout +1;
-- if timeout = x"0b" then
-- timeout <= (others => '0');
-- state <= START;
-- bits <= 0;
-- bytes <= bytes - 1;
-- -- transfer bits at rising edge of sclk
-- elsif rsync_sclk = "01" then
if reset = '1' then
state <= IDLE;
elsif rsync_sclk = "01" then
tx_buf <= tx_buf(38 downto 0) & '0';
bits <= bits + 1;
-- timeout <= (others => '0');
elsif bits = 7 then
state <= WAIT_CS_LO;
bits <= 0;
-- timeout <= (others => '0');
end if;
tx <= tx_buf(39);
when WAIT_CS_HI =>
-- tx stops until cs rising edge
-- if rsync_cs = "01" or cs = '0' then
state <= IDLE;
busy <= '0';
-- end if;
end case;
end if;
end process;
end behavioral;
|
----------------------------------------------------------------------------------
-- spi_transmitter.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Takes 32bit (one sample) and sends it out on the SPI port.
-- End of transmission is signalled by taking back the busy flag.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity spi_transmitter is
port(
data : in std_logic_vector (31 downto 0);
tx_bytes : in integer range 0 to 4;
send : in std_logic;
clock : in std_logic;
sclk : in std_logic;
tx : out std_logic := '0';
cs : in std_logic;
busy: out std_logic := '0';
reset : in std_logic;
dataReady : out std_logic := '0'
);
end spi_transmitter;
architecture behavioral of spi_transmitter is
type states is (IDLE, START, WAIT_CS_LO, SEND_BITS, WAIT_CS_HI);
signal tx_buf : std_logic_vector (39 downto 0) := (others => '0');
signal bits : integer range 0 to 7;
signal bytes, end_byte : integer range 0 to 4;
signal rsync_sclk, rsync_cs : std_logic_vector(1 downto 0) := (others => '0');
signal state: states;
signal send_i: std_logic := '1';
signal timeout : std_logic_vector(31 downto 0) := (others => '0');
begin
process(clock)
begin
if rising_edge(clock) then
rsync_sclk <= rsync_sclk(0) & sclk;
rsync_cs <= rsync_cs(0) & cs;
case state is
when IDLE =>
if send = '1' then
state <= START;
busy <= '1';
dataReady <= '1';
end if;
tx_buf <= x"aa" & data(7 downto 0) & data(15 downto 8)
& data(23 downto 16) & data(31 downto 24);
end_byte <= tx_bytes;
bytes <= 0;
bits <= 0;
when START =>
-- tx starts at cs falling edge
--if rsync_cs = "10" then
-- timeout <= timeout +1;
-- if timeout = x"ffffffffff" then
-- timeout <= (others => '0');
-- state <= WAIT_CS_HI;
-- elsif rsync_cs = "10" or cs = '0' then
if reset = '1' then
state <= IDLE;
elsif rsync_cs = "10" or cs = '0' then
state <= WAIT_CS_LO;
tx <= tx_buf(39);
-- timeout <= (others => '0');
end if;
when WAIT_CS_LO =>
-- wait for cs before sending the next byte
if cs = '0' and rsync_sclk = "01" then
state <= SEND_BITS;
tx_buf <= tx_buf(38 downto 0) & '0';
bytes <= bytes + 1;
elsif bytes = end_byte+1 then
state <= WAIT_CS_HI;
dataReady <= '0';
end if;
tx <= tx_buf(39);
when SEND_BITS =>
-- If we are waiting more then 200ns then something is off. We have a 100Mhz clock so 0x14 is 200ns.
-- timeout <= timeout +1;
-- if timeout = x"0b" then
-- timeout <= (others => '0');
-- state <= START;
-- bits <= 0;
-- bytes <= bytes - 1;
-- -- transfer bits at rising edge of sclk
-- elsif rsync_sclk = "01" then
if reset = '1' then
state <= IDLE;
elsif rsync_sclk = "01" then
tx_buf <= tx_buf(38 downto 0) & '0';
bits <= bits + 1;
-- timeout <= (others => '0');
elsif bits = 7 then
state <= WAIT_CS_LO;
bits <= 0;
-- timeout <= (others => '0');
end if;
tx <= tx_buf(39);
when WAIT_CS_HI =>
-- tx stops until cs rising edge
-- if rsync_cs = "01" or cs = '0' then
state <= IDLE;
busy <= '0';
-- end if;
end case;
end if;
end process;
end behavioral;
|
----------------------------------------------------------------------------------
-- spi_transmitter.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Takes 32bit (one sample) and sends it out on the SPI port.
-- End of transmission is signalled by taking back the busy flag.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity spi_transmitter is
port(
data : in std_logic_vector (31 downto 0);
tx_bytes : in integer range 0 to 4;
send : in std_logic;
clock : in std_logic;
sclk : in std_logic;
tx : out std_logic := '0';
cs : in std_logic;
busy: out std_logic := '0';
reset : in std_logic;
dataReady : out std_logic := '0'
);
end spi_transmitter;
architecture behavioral of spi_transmitter is
type states is (IDLE, START, WAIT_CS_LO, SEND_BITS, WAIT_CS_HI);
signal tx_buf : std_logic_vector (39 downto 0) := (others => '0');
signal bits : integer range 0 to 7;
signal bytes, end_byte : integer range 0 to 4;
signal rsync_sclk, rsync_cs : std_logic_vector(1 downto 0) := (others => '0');
signal state: states;
signal send_i: std_logic := '1';
signal timeout : std_logic_vector(31 downto 0) := (others => '0');
begin
process(clock)
begin
if rising_edge(clock) then
rsync_sclk <= rsync_sclk(0) & sclk;
rsync_cs <= rsync_cs(0) & cs;
case state is
when IDLE =>
if send = '1' then
state <= START;
busy <= '1';
dataReady <= '1';
end if;
tx_buf <= x"aa" & data(7 downto 0) & data(15 downto 8)
& data(23 downto 16) & data(31 downto 24);
end_byte <= tx_bytes;
bytes <= 0;
bits <= 0;
when START =>
-- tx starts at cs falling edge
--if rsync_cs = "10" then
-- timeout <= timeout +1;
-- if timeout = x"ffffffffff" then
-- timeout <= (others => '0');
-- state <= WAIT_CS_HI;
-- elsif rsync_cs = "10" or cs = '0' then
if reset = '1' then
state <= IDLE;
elsif rsync_cs = "10" or cs = '0' then
state <= WAIT_CS_LO;
tx <= tx_buf(39);
-- timeout <= (others => '0');
end if;
when WAIT_CS_LO =>
-- wait for cs before sending the next byte
if cs = '0' and rsync_sclk = "01" then
state <= SEND_BITS;
tx_buf <= tx_buf(38 downto 0) & '0';
bytes <= bytes + 1;
elsif bytes = end_byte+1 then
state <= WAIT_CS_HI;
dataReady <= '0';
end if;
tx <= tx_buf(39);
when SEND_BITS =>
-- If we are waiting more then 200ns then something is off. We have a 100Mhz clock so 0x14 is 200ns.
-- timeout <= timeout +1;
-- if timeout = x"0b" then
-- timeout <= (others => '0');
-- state <= START;
-- bits <= 0;
-- bytes <= bytes - 1;
-- -- transfer bits at rising edge of sclk
-- elsif rsync_sclk = "01" then
if reset = '1' then
state <= IDLE;
elsif rsync_sclk = "01" then
tx_buf <= tx_buf(38 downto 0) & '0';
bits <= bits + 1;
-- timeout <= (others => '0');
elsif bits = 7 then
state <= WAIT_CS_LO;
bits <= 0;
-- timeout <= (others => '0');
end if;
tx <= tx_buf(39);
when WAIT_CS_HI =>
-- tx stops until cs rising edge
-- if rsync_cs = "01" or cs = '0' then
state <= IDLE;
busy <= '0';
-- end if;
end case;
end if;
end process;
end behavioral;
|
----------------------------------------------------------------------------------
-- spi_transmitter.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Takes 32bit (one sample) and sends it out on the SPI port.
-- End of transmission is signalled by taking back the busy flag.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity spi_transmitter is
port(
data : in std_logic_vector (31 downto 0);
tx_bytes : in integer range 0 to 4;
send : in std_logic;
clock : in std_logic;
sclk : in std_logic;
tx : out std_logic := '0';
cs : in std_logic;
busy: out std_logic := '0';
reset : in std_logic;
dataReady : out std_logic := '0'
);
end spi_transmitter;
architecture behavioral of spi_transmitter is
type states is (IDLE, START, WAIT_CS_LO, SEND_BITS, WAIT_CS_HI);
signal tx_buf : std_logic_vector (39 downto 0) := (others => '0');
signal bits : integer range 0 to 7;
signal bytes, end_byte : integer range 0 to 4;
signal rsync_sclk, rsync_cs : std_logic_vector(1 downto 0) := (others => '0');
signal state: states;
signal send_i: std_logic := '1';
signal timeout : std_logic_vector(31 downto 0) := (others => '0');
begin
process(clock)
begin
if rising_edge(clock) then
rsync_sclk <= rsync_sclk(0) & sclk;
rsync_cs <= rsync_cs(0) & cs;
case state is
when IDLE =>
if send = '1' then
state <= START;
busy <= '1';
dataReady <= '1';
end if;
tx_buf <= x"aa" & data(7 downto 0) & data(15 downto 8)
& data(23 downto 16) & data(31 downto 24);
end_byte <= tx_bytes;
bytes <= 0;
bits <= 0;
when START =>
-- tx starts at cs falling edge
--if rsync_cs = "10" then
-- timeout <= timeout +1;
-- if timeout = x"ffffffffff" then
-- timeout <= (others => '0');
-- state <= WAIT_CS_HI;
-- elsif rsync_cs = "10" or cs = '0' then
if reset = '1' then
state <= IDLE;
elsif rsync_cs = "10" or cs = '0' then
state <= WAIT_CS_LO;
tx <= tx_buf(39);
-- timeout <= (others => '0');
end if;
when WAIT_CS_LO =>
-- wait for cs before sending the next byte
if cs = '0' and rsync_sclk = "01" then
state <= SEND_BITS;
tx_buf <= tx_buf(38 downto 0) & '0';
bytes <= bytes + 1;
elsif bytes = end_byte+1 then
state <= WAIT_CS_HI;
dataReady <= '0';
end if;
tx <= tx_buf(39);
when SEND_BITS =>
-- If we are waiting more then 200ns then something is off. We have a 100Mhz clock so 0x14 is 200ns.
-- timeout <= timeout +1;
-- if timeout = x"0b" then
-- timeout <= (others => '0');
-- state <= START;
-- bits <= 0;
-- bytes <= bytes - 1;
-- -- transfer bits at rising edge of sclk
-- elsif rsync_sclk = "01" then
if reset = '1' then
state <= IDLE;
elsif rsync_sclk = "01" then
tx_buf <= tx_buf(38 downto 0) & '0';
bits <= bits + 1;
-- timeout <= (others => '0');
elsif bits = 7 then
state <= WAIT_CS_LO;
bits <= 0;
-- timeout <= (others => '0');
end if;
tx <= tx_buf(39);
when WAIT_CS_HI =>
-- tx stops until cs rising edge
-- if rsync_cs = "01" or cs = '0' then
state <= IDLE;
busy <= '0';
-- end if;
end case;
end if;
end process;
end behavioral;
|
----------------------------------------------------------------------------------
-- spi_transmitter.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Takes 32bit (one sample) and sends it out on the SPI port.
-- End of transmission is signalled by taking back the busy flag.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity spi_transmitter is
port(
data : in std_logic_vector (31 downto 0);
tx_bytes : in integer range 0 to 4;
send : in std_logic;
clock : in std_logic;
sclk : in std_logic;
tx : out std_logic := '0';
cs : in std_logic;
busy: out std_logic := '0';
reset : in std_logic;
dataReady : out std_logic := '0'
);
end spi_transmitter;
architecture behavioral of spi_transmitter is
type states is (IDLE, START, WAIT_CS_LO, SEND_BITS, WAIT_CS_HI);
signal tx_buf : std_logic_vector (39 downto 0) := (others => '0');
signal bits : integer range 0 to 7;
signal bytes, end_byte : integer range 0 to 4;
signal rsync_sclk, rsync_cs : std_logic_vector(1 downto 0) := (others => '0');
signal state: states;
signal send_i: std_logic := '1';
signal timeout : std_logic_vector(31 downto 0) := (others => '0');
begin
process(clock)
begin
if rising_edge(clock) then
rsync_sclk <= rsync_sclk(0) & sclk;
rsync_cs <= rsync_cs(0) & cs;
case state is
when IDLE =>
if send = '1' then
state <= START;
busy <= '1';
dataReady <= '1';
end if;
tx_buf <= x"aa" & data(7 downto 0) & data(15 downto 8)
& data(23 downto 16) & data(31 downto 24);
end_byte <= tx_bytes;
bytes <= 0;
bits <= 0;
when START =>
-- tx starts at cs falling edge
--if rsync_cs = "10" then
-- timeout <= timeout +1;
-- if timeout = x"ffffffffff" then
-- timeout <= (others => '0');
-- state <= WAIT_CS_HI;
-- elsif rsync_cs = "10" or cs = '0' then
if reset = '1' then
state <= IDLE;
elsif rsync_cs = "10" or cs = '0' then
state <= WAIT_CS_LO;
tx <= tx_buf(39);
-- timeout <= (others => '0');
end if;
when WAIT_CS_LO =>
-- wait for cs before sending the next byte
if cs = '0' and rsync_sclk = "01" then
state <= SEND_BITS;
tx_buf <= tx_buf(38 downto 0) & '0';
bytes <= bytes + 1;
elsif bytes = end_byte+1 then
state <= WAIT_CS_HI;
dataReady <= '0';
end if;
tx <= tx_buf(39);
when SEND_BITS =>
-- If we are waiting more then 200ns then something is off. We have a 100Mhz clock so 0x14 is 200ns.
-- timeout <= timeout +1;
-- if timeout = x"0b" then
-- timeout <= (others => '0');
-- state <= START;
-- bits <= 0;
-- bytes <= bytes - 1;
-- -- transfer bits at rising edge of sclk
-- elsif rsync_sclk = "01" then
if reset = '1' then
state <= IDLE;
elsif rsync_sclk = "01" then
tx_buf <= tx_buf(38 downto 0) & '0';
bits <= bits + 1;
-- timeout <= (others => '0');
elsif bits = 7 then
state <= WAIT_CS_LO;
bits <= 0;
-- timeout <= (others => '0');
end if;
tx <= tx_buf(39);
when WAIT_CS_HI =>
-- tx stops until cs rising edge
-- if rsync_cs = "01" or cs = '0' then
state <= IDLE;
busy <= '0';
-- end if;
end case;
end if;
end process;
end behavioral;
|
----------------------------------------------------------------------------------
-- spi_transmitter.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Takes 32bit (one sample) and sends it out on the SPI port.
-- End of transmission is signalled by taking back the busy flag.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity spi_transmitter is
port(
data : in std_logic_vector (31 downto 0);
tx_bytes : in integer range 0 to 4;
send : in std_logic;
clock : in std_logic;
sclk : in std_logic;
tx : out std_logic := '0';
cs : in std_logic;
busy: out std_logic := '0';
reset : in std_logic;
dataReady : out std_logic := '0'
);
end spi_transmitter;
architecture behavioral of spi_transmitter is
type states is (IDLE, START, WAIT_CS_LO, SEND_BITS, WAIT_CS_HI);
signal tx_buf : std_logic_vector (39 downto 0) := (others => '0');
signal bits : integer range 0 to 7;
signal bytes, end_byte : integer range 0 to 4;
signal rsync_sclk, rsync_cs : std_logic_vector(1 downto 0) := (others => '0');
signal state: states;
signal send_i: std_logic := '1';
signal timeout : std_logic_vector(31 downto 0) := (others => '0');
begin
process(clock)
begin
if rising_edge(clock) then
rsync_sclk <= rsync_sclk(0) & sclk;
rsync_cs <= rsync_cs(0) & cs;
case state is
when IDLE =>
if send = '1' then
state <= START;
busy <= '1';
dataReady <= '1';
end if;
tx_buf <= x"aa" & data(7 downto 0) & data(15 downto 8)
& data(23 downto 16) & data(31 downto 24);
end_byte <= tx_bytes;
bytes <= 0;
bits <= 0;
when START =>
-- tx starts at cs falling edge
--if rsync_cs = "10" then
-- timeout <= timeout +1;
-- if timeout = x"ffffffffff" then
-- timeout <= (others => '0');
-- state <= WAIT_CS_HI;
-- elsif rsync_cs = "10" or cs = '0' then
if reset = '1' then
state <= IDLE;
elsif rsync_cs = "10" or cs = '0' then
state <= WAIT_CS_LO;
tx <= tx_buf(39);
-- timeout <= (others => '0');
end if;
when WAIT_CS_LO =>
-- wait for cs before sending the next byte
if cs = '0' and rsync_sclk = "01" then
state <= SEND_BITS;
tx_buf <= tx_buf(38 downto 0) & '0';
bytes <= bytes + 1;
elsif bytes = end_byte+1 then
state <= WAIT_CS_HI;
dataReady <= '0';
end if;
tx <= tx_buf(39);
when SEND_BITS =>
-- If we are waiting more then 200ns then something is off. We have a 100Mhz clock so 0x14 is 200ns.
-- timeout <= timeout +1;
-- if timeout = x"0b" then
-- timeout <= (others => '0');
-- state <= START;
-- bits <= 0;
-- bytes <= bytes - 1;
-- -- transfer bits at rising edge of sclk
-- elsif rsync_sclk = "01" then
if reset = '1' then
state <= IDLE;
elsif rsync_sclk = "01" then
tx_buf <= tx_buf(38 downto 0) & '0';
bits <= bits + 1;
-- timeout <= (others => '0');
elsif bits = 7 then
state <= WAIT_CS_LO;
bits <= 0;
-- timeout <= (others => '0');
end if;
tx <= tx_buf(39);
when WAIT_CS_HI =>
-- tx stops until cs rising edge
-- if rsync_cs = "01" or cs = '0' then
state <= IDLE;
busy <= '0';
-- end if;
end case;
end if;
end process;
end behavioral;
|
----------------------------------------------------------------------------------
-- spi_transmitter.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Takes 32bit (one sample) and sends it out on the SPI port.
-- End of transmission is signalled by taking back the busy flag.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity spi_transmitter is
port(
data : in std_logic_vector (31 downto 0);
tx_bytes : in integer range 0 to 4;
send : in std_logic;
clock : in std_logic;
sclk : in std_logic;
tx : out std_logic := '0';
cs : in std_logic;
busy: out std_logic := '0';
reset : in std_logic;
dataReady : out std_logic := '0'
);
end spi_transmitter;
architecture behavioral of spi_transmitter is
type states is (IDLE, START, WAIT_CS_LO, SEND_BITS, WAIT_CS_HI);
signal tx_buf : std_logic_vector (39 downto 0) := (others => '0');
signal bits : integer range 0 to 7;
signal bytes, end_byte : integer range 0 to 4;
signal rsync_sclk, rsync_cs : std_logic_vector(1 downto 0) := (others => '0');
signal state: states;
signal send_i: std_logic := '1';
signal timeout : std_logic_vector(31 downto 0) := (others => '0');
begin
process(clock)
begin
if rising_edge(clock) then
rsync_sclk <= rsync_sclk(0) & sclk;
rsync_cs <= rsync_cs(0) & cs;
case state is
when IDLE =>
if send = '1' then
state <= START;
busy <= '1';
dataReady <= '1';
end if;
tx_buf <= x"aa" & data(7 downto 0) & data(15 downto 8)
& data(23 downto 16) & data(31 downto 24);
end_byte <= tx_bytes;
bytes <= 0;
bits <= 0;
when START =>
-- tx starts at cs falling edge
--if rsync_cs = "10" then
-- timeout <= timeout +1;
-- if timeout = x"ffffffffff" then
-- timeout <= (others => '0');
-- state <= WAIT_CS_HI;
-- elsif rsync_cs = "10" or cs = '0' then
if reset = '1' then
state <= IDLE;
elsif rsync_cs = "10" or cs = '0' then
state <= WAIT_CS_LO;
tx <= tx_buf(39);
-- timeout <= (others => '0');
end if;
when WAIT_CS_LO =>
-- wait for cs before sending the next byte
if cs = '0' and rsync_sclk = "01" then
state <= SEND_BITS;
tx_buf <= tx_buf(38 downto 0) & '0';
bytes <= bytes + 1;
elsif bytes = end_byte+1 then
state <= WAIT_CS_HI;
dataReady <= '0';
end if;
tx <= tx_buf(39);
when SEND_BITS =>
-- If we are waiting more then 200ns then something is off. We have a 100Mhz clock so 0x14 is 200ns.
-- timeout <= timeout +1;
-- if timeout = x"0b" then
-- timeout <= (others => '0');
-- state <= START;
-- bits <= 0;
-- bytes <= bytes - 1;
-- -- transfer bits at rising edge of sclk
-- elsif rsync_sclk = "01" then
if reset = '1' then
state <= IDLE;
elsif rsync_sclk = "01" then
tx_buf <= tx_buf(38 downto 0) & '0';
bits <= bits + 1;
-- timeout <= (others => '0');
elsif bits = 7 then
state <= WAIT_CS_LO;
bits <= 0;
-- timeout <= (others => '0');
end if;
tx <= tx_buf(39);
when WAIT_CS_HI =>
-- tx stops until cs rising edge
-- if rsync_cs = "01" or cs = '0' then
state <= IDLE;
busy <= '0';
-- end if;
end case;
end if;
end process;
end behavioral;
|
----------------------------------------------------------------------------------
-- spi_transmitter.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Takes 32bit (one sample) and sends it out on the SPI port.
-- End of transmission is signalled by taking back the busy flag.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity spi_transmitter is
port(
data : in std_logic_vector (31 downto 0);
tx_bytes : in integer range 0 to 4;
send : in std_logic;
clock : in std_logic;
sclk : in std_logic;
tx : out std_logic := '0';
cs : in std_logic;
busy: out std_logic := '0';
reset : in std_logic;
dataReady : out std_logic := '0'
);
end spi_transmitter;
architecture behavioral of spi_transmitter is
type states is (IDLE, START, WAIT_CS_LO, SEND_BITS, WAIT_CS_HI);
signal tx_buf : std_logic_vector (39 downto 0) := (others => '0');
signal bits : integer range 0 to 7;
signal bytes, end_byte : integer range 0 to 4;
signal rsync_sclk, rsync_cs : std_logic_vector(1 downto 0) := (others => '0');
signal state: states;
signal send_i: std_logic := '1';
signal timeout : std_logic_vector(31 downto 0) := (others => '0');
begin
process(clock)
begin
if rising_edge(clock) then
rsync_sclk <= rsync_sclk(0) & sclk;
rsync_cs <= rsync_cs(0) & cs;
case state is
when IDLE =>
if send = '1' then
state <= START;
busy <= '1';
dataReady <= '1';
end if;
tx_buf <= x"aa" & data(7 downto 0) & data(15 downto 8)
& data(23 downto 16) & data(31 downto 24);
end_byte <= tx_bytes;
bytes <= 0;
bits <= 0;
when START =>
-- tx starts at cs falling edge
--if rsync_cs = "10" then
-- timeout <= timeout +1;
-- if timeout = x"ffffffffff" then
-- timeout <= (others => '0');
-- state <= WAIT_CS_HI;
-- elsif rsync_cs = "10" or cs = '0' then
if reset = '1' then
state <= IDLE;
elsif rsync_cs = "10" or cs = '0' then
state <= WAIT_CS_LO;
tx <= tx_buf(39);
-- timeout <= (others => '0');
end if;
when WAIT_CS_LO =>
-- wait for cs before sending the next byte
if cs = '0' and rsync_sclk = "01" then
state <= SEND_BITS;
tx_buf <= tx_buf(38 downto 0) & '0';
bytes <= bytes + 1;
elsif bytes = end_byte+1 then
state <= WAIT_CS_HI;
dataReady <= '0';
end if;
tx <= tx_buf(39);
when SEND_BITS =>
-- If we are waiting more then 200ns then something is off. We have a 100Mhz clock so 0x14 is 200ns.
-- timeout <= timeout +1;
-- if timeout = x"0b" then
-- timeout <= (others => '0');
-- state <= START;
-- bits <= 0;
-- bytes <= bytes - 1;
-- -- transfer bits at rising edge of sclk
-- elsif rsync_sclk = "01" then
if reset = '1' then
state <= IDLE;
elsif rsync_sclk = "01" then
tx_buf <= tx_buf(38 downto 0) & '0';
bits <= bits + 1;
-- timeout <= (others => '0');
elsif bits = 7 then
state <= WAIT_CS_LO;
bits <= 0;
-- timeout <= (others => '0');
end if;
tx <= tx_buf(39);
when WAIT_CS_HI =>
-- tx stops until cs rising edge
-- if rsync_cs = "01" or cs = '0' then
state <= IDLE;
busy <= '0';
-- end if;
end case;
end if;
end process;
end behavioral;
|
----------------------------------------------------------------------------------
-- spi_transmitter.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Takes 32bit (one sample) and sends it out on the SPI port.
-- End of transmission is signalled by taking back the busy flag.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity spi_transmitter is
port(
data : in std_logic_vector (31 downto 0);
tx_bytes : in integer range 0 to 4;
send : in std_logic;
clock : in std_logic;
sclk : in std_logic;
tx : out std_logic := '0';
cs : in std_logic;
busy: out std_logic := '0';
reset : in std_logic;
dataReady : out std_logic := '0'
);
end spi_transmitter;
architecture behavioral of spi_transmitter is
type states is (IDLE, START, WAIT_CS_LO, SEND_BITS, WAIT_CS_HI);
signal tx_buf : std_logic_vector (39 downto 0) := (others => '0');
signal bits : integer range 0 to 7;
signal bytes, end_byte : integer range 0 to 4;
signal rsync_sclk, rsync_cs : std_logic_vector(1 downto 0) := (others => '0');
signal state: states;
signal send_i: std_logic := '1';
signal timeout : std_logic_vector(31 downto 0) := (others => '0');
begin
process(clock)
begin
if rising_edge(clock) then
rsync_sclk <= rsync_sclk(0) & sclk;
rsync_cs <= rsync_cs(0) & cs;
case state is
when IDLE =>
if send = '1' then
state <= START;
busy <= '1';
dataReady <= '1';
end if;
tx_buf <= x"aa" & data(7 downto 0) & data(15 downto 8)
& data(23 downto 16) & data(31 downto 24);
end_byte <= tx_bytes;
bytes <= 0;
bits <= 0;
when START =>
-- tx starts at cs falling edge
--if rsync_cs = "10" then
-- timeout <= timeout +1;
-- if timeout = x"ffffffffff" then
-- timeout <= (others => '0');
-- state <= WAIT_CS_HI;
-- elsif rsync_cs = "10" or cs = '0' then
if reset = '1' then
state <= IDLE;
elsif rsync_cs = "10" or cs = '0' then
state <= WAIT_CS_LO;
tx <= tx_buf(39);
-- timeout <= (others => '0');
end if;
when WAIT_CS_LO =>
-- wait for cs before sending the next byte
if cs = '0' and rsync_sclk = "01" then
state <= SEND_BITS;
tx_buf <= tx_buf(38 downto 0) & '0';
bytes <= bytes + 1;
elsif bytes = end_byte+1 then
state <= WAIT_CS_HI;
dataReady <= '0';
end if;
tx <= tx_buf(39);
when SEND_BITS =>
-- If we are waiting more then 200ns then something is off. We have a 100Mhz clock so 0x14 is 200ns.
-- timeout <= timeout +1;
-- if timeout = x"0b" then
-- timeout <= (others => '0');
-- state <= START;
-- bits <= 0;
-- bytes <= bytes - 1;
-- -- transfer bits at rising edge of sclk
-- elsif rsync_sclk = "01" then
if reset = '1' then
state <= IDLE;
elsif rsync_sclk = "01" then
tx_buf <= tx_buf(38 downto 0) & '0';
bits <= bits + 1;
-- timeout <= (others => '0');
elsif bits = 7 then
state <= WAIT_CS_LO;
bits <= 0;
-- timeout <= (others => '0');
end if;
tx <= tx_buf(39);
when WAIT_CS_HI =>
-- tx stops until cs rising edge
-- if rsync_cs = "01" or cs = '0' then
state <= IDLE;
busy <= '0';
-- end if;
end case;
end if;
end process;
end behavioral;
|
----------------------------------------------------------------------------------
-- spi_transmitter.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Takes 32bit (one sample) and sends it out on the SPI port.
-- End of transmission is signalled by taking back the busy flag.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity spi_transmitter is
port(
data : in std_logic_vector (31 downto 0);
tx_bytes : in integer range 0 to 4;
send : in std_logic;
clock : in std_logic;
sclk : in std_logic;
tx : out std_logic := '0';
cs : in std_logic;
busy: out std_logic := '0';
reset : in std_logic;
dataReady : out std_logic := '0'
);
end spi_transmitter;
architecture behavioral of spi_transmitter is
type states is (IDLE, START, WAIT_CS_LO, SEND_BITS, WAIT_CS_HI);
signal tx_buf : std_logic_vector (39 downto 0) := (others => '0');
signal bits : integer range 0 to 7;
signal bytes, end_byte : integer range 0 to 4;
signal rsync_sclk, rsync_cs : std_logic_vector(1 downto 0) := (others => '0');
signal state: states;
signal send_i: std_logic := '1';
signal timeout : std_logic_vector(31 downto 0) := (others => '0');
begin
process(clock)
begin
if rising_edge(clock) then
rsync_sclk <= rsync_sclk(0) & sclk;
rsync_cs <= rsync_cs(0) & cs;
case state is
when IDLE =>
if send = '1' then
state <= START;
busy <= '1';
dataReady <= '1';
end if;
tx_buf <= x"aa" & data(7 downto 0) & data(15 downto 8)
& data(23 downto 16) & data(31 downto 24);
end_byte <= tx_bytes;
bytes <= 0;
bits <= 0;
when START =>
-- tx starts at cs falling edge
--if rsync_cs = "10" then
-- timeout <= timeout +1;
-- if timeout = x"ffffffffff" then
-- timeout <= (others => '0');
-- state <= WAIT_CS_HI;
-- elsif rsync_cs = "10" or cs = '0' then
if reset = '1' then
state <= IDLE;
elsif rsync_cs = "10" or cs = '0' then
state <= WAIT_CS_LO;
tx <= tx_buf(39);
-- timeout <= (others => '0');
end if;
when WAIT_CS_LO =>
-- wait for cs before sending the next byte
if cs = '0' and rsync_sclk = "01" then
state <= SEND_BITS;
tx_buf <= tx_buf(38 downto 0) & '0';
bytes <= bytes + 1;
elsif bytes = end_byte+1 then
state <= WAIT_CS_HI;
dataReady <= '0';
end if;
tx <= tx_buf(39);
when SEND_BITS =>
-- If we are waiting more then 200ns then something is off. We have a 100Mhz clock so 0x14 is 200ns.
-- timeout <= timeout +1;
-- if timeout = x"0b" then
-- timeout <= (others => '0');
-- state <= START;
-- bits <= 0;
-- bytes <= bytes - 1;
-- -- transfer bits at rising edge of sclk
-- elsif rsync_sclk = "01" then
if reset = '1' then
state <= IDLE;
elsif rsync_sclk = "01" then
tx_buf <= tx_buf(38 downto 0) & '0';
bits <= bits + 1;
-- timeout <= (others => '0');
elsif bits = 7 then
state <= WAIT_CS_LO;
bits <= 0;
-- timeout <= (others => '0');
end if;
tx <= tx_buf(39);
when WAIT_CS_HI =>
-- tx stops until cs rising edge
-- if rsync_cs = "01" or cs = '0' then
state <= IDLE;
busy <= '0';
-- end if;
end case;
end if;
end process;
end behavioral;
|
----------------------------------------------------------------------------------
-- spi_transmitter.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Takes 32bit (one sample) and sends it out on the SPI port.
-- End of transmission is signalled by taking back the busy flag.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity spi_transmitter is
port(
data : in std_logic_vector (31 downto 0);
tx_bytes : in integer range 0 to 4;
send : in std_logic;
clock : in std_logic;
sclk : in std_logic;
tx : out std_logic := '0';
cs : in std_logic;
busy: out std_logic := '0';
reset : in std_logic;
dataReady : out std_logic := '0'
);
end spi_transmitter;
architecture behavioral of spi_transmitter is
type states is (IDLE, START, WAIT_CS_LO, SEND_BITS, WAIT_CS_HI);
signal tx_buf : std_logic_vector (39 downto 0) := (others => '0');
signal bits : integer range 0 to 7;
signal bytes, end_byte : integer range 0 to 4;
signal rsync_sclk, rsync_cs : std_logic_vector(1 downto 0) := (others => '0');
signal state: states;
signal send_i: std_logic := '1';
signal timeout : std_logic_vector(31 downto 0) := (others => '0');
begin
process(clock)
begin
if rising_edge(clock) then
rsync_sclk <= rsync_sclk(0) & sclk;
rsync_cs <= rsync_cs(0) & cs;
case state is
when IDLE =>
if send = '1' then
state <= START;
busy <= '1';
dataReady <= '1';
end if;
tx_buf <= x"aa" & data(7 downto 0) & data(15 downto 8)
& data(23 downto 16) & data(31 downto 24);
end_byte <= tx_bytes;
bytes <= 0;
bits <= 0;
when START =>
-- tx starts at cs falling edge
--if rsync_cs = "10" then
-- timeout <= timeout +1;
-- if timeout = x"ffffffffff" then
-- timeout <= (others => '0');
-- state <= WAIT_CS_HI;
-- elsif rsync_cs = "10" or cs = '0' then
if reset = '1' then
state <= IDLE;
elsif rsync_cs = "10" or cs = '0' then
state <= WAIT_CS_LO;
tx <= tx_buf(39);
-- timeout <= (others => '0');
end if;
when WAIT_CS_LO =>
-- wait for cs before sending the next byte
if cs = '0' and rsync_sclk = "01" then
state <= SEND_BITS;
tx_buf <= tx_buf(38 downto 0) & '0';
bytes <= bytes + 1;
elsif bytes = end_byte+1 then
state <= WAIT_CS_HI;
dataReady <= '0';
end if;
tx <= tx_buf(39);
when SEND_BITS =>
-- If we are waiting more then 200ns then something is off. We have a 100Mhz clock so 0x14 is 200ns.
-- timeout <= timeout +1;
-- if timeout = x"0b" then
-- timeout <= (others => '0');
-- state <= START;
-- bits <= 0;
-- bytes <= bytes - 1;
-- -- transfer bits at rising edge of sclk
-- elsif rsync_sclk = "01" then
if reset = '1' then
state <= IDLE;
elsif rsync_sclk = "01" then
tx_buf <= tx_buf(38 downto 0) & '0';
bits <= bits + 1;
-- timeout <= (others => '0');
elsif bits = 7 then
state <= WAIT_CS_LO;
bits <= 0;
-- timeout <= (others => '0');
end if;
tx <= tx_buf(39);
when WAIT_CS_HI =>
-- tx stops until cs rising edge
-- if rsync_cs = "01" or cs = '0' then
state <= IDLE;
busy <= '0';
-- end if;
end case;
end if;
end process;
end behavioral;
|
----------------------------------------------------------------------------------
-- spi_transmitter.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Takes 32bit (one sample) and sends it out on the SPI port.
-- End of transmission is signalled by taking back the busy flag.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity spi_transmitter is
port(
data : in std_logic_vector (31 downto 0);
tx_bytes : in integer range 0 to 4;
send : in std_logic;
clock : in std_logic;
sclk : in std_logic;
tx : out std_logic := '0';
cs : in std_logic;
busy: out std_logic := '0';
reset : in std_logic;
dataReady : out std_logic := '0'
);
end spi_transmitter;
architecture behavioral of spi_transmitter is
type states is (IDLE, START, WAIT_CS_LO, SEND_BITS, WAIT_CS_HI);
signal tx_buf : std_logic_vector (39 downto 0) := (others => '0');
signal bits : integer range 0 to 7;
signal bytes, end_byte : integer range 0 to 4;
signal rsync_sclk, rsync_cs : std_logic_vector(1 downto 0) := (others => '0');
signal state: states;
signal send_i: std_logic := '1';
signal timeout : std_logic_vector(31 downto 0) := (others => '0');
begin
process(clock)
begin
if rising_edge(clock) then
rsync_sclk <= rsync_sclk(0) & sclk;
rsync_cs <= rsync_cs(0) & cs;
case state is
when IDLE =>
if send = '1' then
state <= START;
busy <= '1';
dataReady <= '1';
end if;
tx_buf <= x"aa" & data(7 downto 0) & data(15 downto 8)
& data(23 downto 16) & data(31 downto 24);
end_byte <= tx_bytes;
bytes <= 0;
bits <= 0;
when START =>
-- tx starts at cs falling edge
--if rsync_cs = "10" then
-- timeout <= timeout +1;
-- if timeout = x"ffffffffff" then
-- timeout <= (others => '0');
-- state <= WAIT_CS_HI;
-- elsif rsync_cs = "10" or cs = '0' then
if reset = '1' then
state <= IDLE;
elsif rsync_cs = "10" or cs = '0' then
state <= WAIT_CS_LO;
tx <= tx_buf(39);
-- timeout <= (others => '0');
end if;
when WAIT_CS_LO =>
-- wait for cs before sending the next byte
if cs = '0' and rsync_sclk = "01" then
state <= SEND_BITS;
tx_buf <= tx_buf(38 downto 0) & '0';
bytes <= bytes + 1;
elsif bytes = end_byte+1 then
state <= WAIT_CS_HI;
dataReady <= '0';
end if;
tx <= tx_buf(39);
when SEND_BITS =>
-- If we are waiting more then 200ns then something is off. We have a 100Mhz clock so 0x14 is 200ns.
-- timeout <= timeout +1;
-- if timeout = x"0b" then
-- timeout <= (others => '0');
-- state <= START;
-- bits <= 0;
-- bytes <= bytes - 1;
-- -- transfer bits at rising edge of sclk
-- elsif rsync_sclk = "01" then
if reset = '1' then
state <= IDLE;
elsif rsync_sclk = "01" then
tx_buf <= tx_buf(38 downto 0) & '0';
bits <= bits + 1;
-- timeout <= (others => '0');
elsif bits = 7 then
state <= WAIT_CS_LO;
bits <= 0;
-- timeout <= (others => '0');
end if;
tx <= tx_buf(39);
when WAIT_CS_HI =>
-- tx stops until cs rising edge
-- if rsync_cs = "01" or cs = '0' then
state <= IDLE;
busy <= '0';
-- end if;
end case;
end if;
end process;
end behavioral;
|
entity wait3 is
end entity;
architecture test of wait3 is
signal x, y : bit;
begin
proc_a: process is
begin
wait for 1 ns;
x <= '1';
wait for 1 ns;
assert y = '1';
wait;
end process;
proc_b: process is
begin
wait on x;
assert x = '1';
assert now = 1 ns;
y <= '1';
wait;
end process;
end architecture;
|
entity wait3 is
end entity;
architecture test of wait3 is
signal x, y : bit;
begin
proc_a: process is
begin
wait for 1 ns;
x <= '1';
wait for 1 ns;
assert y = '1';
wait;
end process;
proc_b: process is
begin
wait on x;
assert x = '1';
assert now = 1 ns;
y <= '1';
wait;
end process;
end architecture;
|
entity wait3 is
end entity;
architecture test of wait3 is
signal x, y : bit;
begin
proc_a: process is
begin
wait for 1 ns;
x <= '1';
wait for 1 ns;
assert y = '1';
wait;
end process;
proc_b: process is
begin
wait on x;
assert x = '1';
assert now = 1 ns;
y <= '1';
wait;
end process;
end architecture;
|
entity wait3 is
end entity;
architecture test of wait3 is
signal x, y : bit;
begin
proc_a: process is
begin
wait for 1 ns;
x <= '1';
wait for 1 ns;
assert y = '1';
wait;
end process;
proc_b: process is
begin
wait on x;
assert x = '1';
assert now = 1 ns;
y <= '1';
wait;
end process;
end architecture;
|
entity wait3 is
end entity;
architecture test of wait3 is
signal x, y : bit;
begin
proc_a: process is
begin
wait for 1 ns;
x <= '1';
wait for 1 ns;
assert y = '1';
wait;
end process;
proc_b: process is
begin
wait on x;
assert x = '1';
assert now = 1 ns;
y <= '1';
wait;
end process;
end architecture;
|
-- NEED RESULT: ARCH00574: Can declare entities with same name as entities declared in a use'd pkg passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00574
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 10.4 (1)
--
-- DESIGN UNIT ORDERING:
--
-- PKG00574
-- PKG00574/BODY
-- ENT00574_Test_Bench(ARCH00574_Test_Bench)
--
-- REVISION HISTORY:
--
-- 19-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
package PKG00574 is
type T1 is (one, two, three, four) ;
type T2 is (one, two, three, four) ;
type T3 is (one, two, three, four) ;
type T4 is (one, two, three, four) ;
subtype S1 is INTEGER;
subtype S2 is INTEGER;
subtype S3 is INTEGER;
subtype S4 is INTEGER;
function F1 return REAL ;
function F2 return REAL ;
function F3 return REAL ;
function F4 return REAL ;
end PKG00574 ;
package body PKG00574 is
function F1 return REAL is begin
return 0.0; end;
function F2 return REAL is begin
return 0.0; end;
function F3 return REAL is begin
return 0.0; end;
function F4 return REAL is begin
return 0.0; end;
end PKG00574 ;
use WORK.STANDARD_TYPES.all ;
use WORK.PKG00574; use PKG00574.all;
entity ENT00574_Test_Bench is
end ENT00574_Test_Bench ;
architecture ARCH00574_Test_Bench of ENT00574_Test_Bench is begin
L_X_1 : block
type T1 is record -- should be able to define new type T1
TE : BOOLEAN;
end record;
subtype T2 is REAL range 0.0 to 256.0; -- ditto for subtype called T2
attribute T3 : PKG00574.T3 ; -- ditto for attribute called T3
signal T4 : PKG00574.T1; -- ditto for object called T4
type S1 is record -- should be able to define new type S1
SE : BOOLEAN;
end record;
subtype S2 is REAL range 0.0 to 256.0; -- ditto for subtype called S2
attribute S3 : PKG00574.T3 ; -- ditto for attribute called S3
signal S4 : PKG00574.T1; -- ditto for object called S4
type F1 is record -- should be able to define new type F1
FE : BOOLEAN;
end record;
subtype F2 is REAL range 0.0 to 256.0; -- ditto for subtype called F2
attribute F3 : PKG00574.T3 ; -- ditto for attribute called F3
signal F4 : PKG00574.T1; -- ditto for object called F4
begin
process
variable T1 : PKG00574.T1; -- ditto for object called T1
variable F1 : PKG00574.T1; -- ditto for object called F1
variable S1 : PKG00574.T1; -- ditto for object called S1
begin
test_report ( "ARCH00574" ,
"Can declare entities with same name as entities "&
"declared in a use'd pkg" ,
True ) ;
wait ;
end process;
end block;
end ARCH00574_Test_Bench ;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.cpu_defs.all;
entity luz_cpu_tb is end;
architecture luz_cpu_tb_arc of luz_cpu_tb is
constant RESET_ADDRESS: word := x"00000000";
signal clk: std_logic := '0';
signal reset_n: std_logic;
signal ack_i: std_logic;
signal cyc_o: std_logic;
signal stb_o: std_logic;
signal we_o: std_logic;
signal sel_o: std_logic_vector(3 downto 0);
signal adr_o: std_logic_vector(31 downto 0);
signal data_o: std_logic_vector(31 downto 0);
signal data_i: std_logic_vector(31 downto 0);
signal irq_i: std_logic_vector(31 downto 0);
signal halt: std_logic;
signal ifetch: std_logic;
begin
clk <= not clk after 13 ns;
reset_n <= '0', '1' after 100 ns;
process
begin
wait;
end process;
uut: entity work.luz_cpu(luz_cpu_arc)
generic map
(
RESET_ADDRESS => RESET_ADDRESS
)
port map
(
clk => clk,
reset_n => reset_n,
ack_i => ack_i,
cyc_o => cyc_o,
stb_o => stb_o,
we_o => we_o,
sel_o => sel_o,
adr_o => adr_o,
data_o => data_o,
data_i => data_i,
irq_i => irq_i,
halt => halt,
ifetch => ifetch
);
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.cpu_defs.all;
entity luz_cpu_tb is end;
architecture luz_cpu_tb_arc of luz_cpu_tb is
constant RESET_ADDRESS: word := x"00000000";
signal clk: std_logic := '0';
signal reset_n: std_logic;
signal ack_i: std_logic;
signal cyc_o: std_logic;
signal stb_o: std_logic;
signal we_o: std_logic;
signal sel_o: std_logic_vector(3 downto 0);
signal adr_o: std_logic_vector(31 downto 0);
signal data_o: std_logic_vector(31 downto 0);
signal data_i: std_logic_vector(31 downto 0);
signal irq_i: std_logic_vector(31 downto 0);
signal halt: std_logic;
signal ifetch: std_logic;
begin
clk <= not clk after 13 ns;
reset_n <= '0', '1' after 100 ns;
process
begin
wait;
end process;
uut: entity work.luz_cpu(luz_cpu_arc)
generic map
(
RESET_ADDRESS => RESET_ADDRESS
)
port map
(
clk => clk,
reset_n => reset_n,
ack_i => ack_i,
cyc_o => cyc_o,
stb_o => stb_o,
we_o => we_o,
sel_o => sel_o,
adr_o => adr_o,
data_o => data_o,
data_i => data_i,
irq_i => irq_i,
halt => halt,
ifetch => ifetch
);
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddrram
-- File: ddrram.vhd
-- Author: Magnus Hjorth, Aeroflex Gaisler
-- Description: Generic simulation model of DDR SDRAM (JESD79E)
------------------------------------------------------------------------------
--pragma translate_off
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdio.hread;
use grlib.stdlib.all;
entity ddrram is
generic (
width: integer := 32;
abits: integer range 12 to 14 := 12;
colbits: integer range 8 to 13 := 8;
rowbits: integer range 1 to 14 := 12;
implbanks: integer range 1 to 4 := 1;
fname: string;
lddelay: time := (0 ns);
speedbin: integer range 0 to 5 := 0; -- 0:DDR200,1:266,2:333,3:400C,4:400B,5:400A
density: integer range 0 to 3 := 0; -- 0:128Mbit 1:256Mbit 2:512Mbit 3:1Gbit / chip
igndqs: integer range 0 to 1 := 0
);
port (
ck: in std_ulogic;
cke: in std_ulogic;
csn: in std_ulogic;
rasn: in std_ulogic;
casn: in std_ulogic;
wen: in std_ulogic;
dm: in std_logic_vector(width/8-1 downto 0);
ba: in std_logic_vector(1 downto 0);
a: in std_logic_vector(abits-1 downto 0);
dq: inout std_logic_vector(width-1 downto 0);
dqs: inout std_logic_vector(width/8-1 downto 0)
);
end;
architecture sim of ddrram is
type moderegs is record
-- Mode register (0)
opmode: std_logic_vector(6 downto 0);
caslat: std_logic_vector(2 downto 0);
bt: std_ulogic;
blen: std_logic_vector(2 downto 0);
-- Extended mode register (1)
opmode1: std_logic_vector(10 downto 0);
res1: std_ulogic;
ds: std_ulogic;
dlldis: std_ulogic;
end record;
-- Mode registers as signal, useful for debugging
signal mr: moderegs;
-- Handshaking between command and DQ/DQS processes
signal read_en, write_en: boolean := false;
signal hcmode: boolean := false; -- Shift DQS/read data one cycle for CL=1.5/2.5
signal hcread_en: boolean := false; -- One cycle earlier for half-cycle mode read preamble gen
signal read_data, write_data: std_logic_vector(2*width-1 downto 0);
signal write_mask: std_logic_vector(width/4-1 downto 0);
signal initdone: boolean := false;
-- Small delta-t to adjust calculations for jitter tol.
constant deltat: time := 50 ps;
-- Timing parameters
constant tWR: time := 15 ns;
constant tMRD_ck: integer := 2;
type timetab is array (0 to 5) of time;
constant tRAS : timetab := (50 ns, 45 ns, 42 ns, 40 ns, 40 ns, 40 ns);
constant tRP : timetab := (20 ns, 20 ns, 18 ns, 18 ns, 15 ns, 15 ns);
constant tRCD: timetab := (20 ns, 20 ns, 18 ns, 18 ns, 15 ns, 15 ns);
constant tRRD: timetab := (15 ns, 15 ns, 12 ns, 10 ns, 10 ns, 10 ns);
constant tRFC_lt1G: timetab := (80 ns, 75 ns, 72 ns, 70 ns, 70 ns, 70 ns); --Assuming<1Gb
constant tRFC_mt1G: time := 120 ns;
function tRFC return time is
begin
if density < 3 then return tRFC_lt1G(speedbin);
else return tRFC_mt1G; end if;
end tRFC;
begin
-----------------------------------------------------------------------------
-- Init sequence checker
-----------------------------------------------------------------------------
initp: process
variable cyctr : integer := 0;
procedure checkcmd(crasn,ccasn,cwen: std_ulogic;
cba: std_logic_vector(1 downto 0);
a10,a8,a0: std_ulogic) is
begin
wait until rising_edge(ck);
cyctr := cyctr+1;
while cke='1' and (csn='1' or (rasn='1' and casn='1' and wen='1')) loop
wait until rising_edge(ck);
cyctr := cyctr+1;
end loop;
assert cke='1' and csn='0' and rasn=crasn and casn=ccasn and wen=cwen and
(cba="--" or cba=ba) and (a10='-' or a10=a(10)) and (a8='-' or a8=a(8)) and
(a0='-' or a0=a(0))
report "Wrong command during init sequence" severity warning;
end checkcmd;
begin
initdone <= false;
-- Allow cke to be X or U for a while during sim start
if is_x(cke) then
wait until not is_x(cke);
end if;
assert cke='0' report "CKE not deasserted on power-up" severity warning;
wait until cke/='0' for 200 us;
assert cke='0' report "CKE raised with less than 200 us init delay" severity warning;
wait until cke/='0' and rising_edge(ck);
assert cke='1' and (csn='1' or (rasn='1' and casn='1' and wen='1'));
-- Precharge all
checkcmd('0','1','0',"--",'1','-','-');
-- EMRS enable DLL
checkcmd('0','0','0',"01",'-','-','0');
-- MRS reset DLL
checkcmd('0','0','0',"00",'-','1','-');
cyctr := 0;
-- 200 cycle NOP
-- Precharge all
checkcmd('0','1','0',"--",'1','-','-');
assert cyctr >= 200
report "Command issued too quickly after DLL reset" severity warning;
-- 2 x auto refresh
checkcmd('0','0','1',"--",'-','-','-');
checkcmd('0','0','1',"--",'-','-','-');
-- MRS !reset DLL
checkcmd('0','0','0',"00",'-','0','-');
initdone <= true;
wait;
end process;
-----------------------------------------------------------------------------
-- Command state machine
-----------------------------------------------------------------------------
cmdp: process(ck)
subtype coldata is std_logic_vector(width-1 downto 0);
type coldata_arr is array(0 to implbanks*(2**(colbits+rowbits))-1) of coldata;
variable memdata: coldata_arr;
procedure load_srec is
file TCF : text open read_mode is fname;
variable L1: line;
variable CH : character;
variable rectype : std_logic_vector(3 downto 0);
variable recaddr : std_logic_vector(31 downto 0);
variable reclen : std_logic_vector(7 downto 0);
variable recdata : std_logic_vector(0 to 16*8-1);
variable col, coloffs, len: integer;
begin
L1:= new string'("");
while not endfile(TCF) loop
readline(TCF,L1);
if (L1'length /= 0) then
while (not (L1'length=0)) and (L1(L1'left) = ' ') loop
std.textio.read(L1,CH);
end loop;
if L1'length > 0 then
read(L1, ch);
if (ch = 'S') or (ch = 's') then
hread(L1, rectype);
hread(L1, reclen);
len := to_integer(unsigned(reclen))-1;
recaddr := (others => '0');
case rectype is
when "0001" => hread(L1, recaddr(15 downto 0)); len := len - 2;
when "0010" => hread(L1, recaddr(23 downto 0)); len := len - 3;
when "0011" => hread(L1, recaddr); len := len - 4;
when others => next;
end case;
hread(L1, recdata(0 to len*8-1));
col := to_integer(unsigned(recaddr(log2(width/8)+rowbits+colbits+1 downto log2(width/8))));
coloffs := 8*to_integer(unsigned(recaddr(log2(width/8)-1 downto 0)));
while len > width/8 loop
assert coloffs=0;
memdata(col) := recdata(0 to width-1);
col := col+1;
len := len-width/8;
recdata(0 to recdata'length-width-1) := recdata(width to recdata'length-1);
end loop;
memdata(col)(width-1-coloffs downto width-coloffs-len*8) := recdata(0 to len*8-1);
end if;
end if;
end if;
end loop;
end load_srec;
variable vmr: moderegs := ((others => '0'), "UUU", 'U', "UUU", (others => '0'), '0', '0', '0');
type bankstate is record
openrow: integer;
opentime: time;
closetime: time;
writetime: time;
autopch: integer;
end record;
type bankstate_arr is array(natural range <>) of bankstate;
variable banks: bankstate_arr(3 downto 0) := (others => (-1, 0 ns, 0 ns, 0 ns, -1));
type int_arr is array(natural range <>) of integer;
type dataacc is record
r,w: boolean;
col: int_arr(0 to 1);
bank: integer;
end record;
type dataacc_arr is array(natural range <>) of dataacc;
variable accpipe: dataacc_arr(0 to 9);
variable cmd: std_logic_vector(2 downto 0);
variable bank: integer;
variable colv: unsigned(a'high-1 downto 0);
variable alow: unsigned(2 downto 0);
variable col: integer;
variable prev_re, re: time;
variable blen: integer;
variable lastref: time := 0 ns;
variable i: integer;
variable b: boolean;
variable mrscount: integer := 0;
variable loaded: boolean := false;
procedure checktime(got, exp: time; gt: boolean; req: string) is
begin
assert (got + deltat > exp and gt) or (got-deltat < exp and not gt)
report (req & " violation, got: " & tost(got/(1 ps)) & " ps, exp: " & tost(exp/(1 ps)) & "ps")
severity warning;
end checktime;
begin
if rising_edge(ck) then
-- Update pipe regs
prev_re := re;
re := now;
accpipe(1 to accpipe'high) := accpipe(0 to accpipe'high-1);
accpipe(0).r:=false; accpipe(0).w:=false;
-- Main command handler
cmd := rasn & casn & wen;
if mrscount > 0 then
mrscount := mrscount-1;
assert cke='1' and (csn='1' or cmd="111") report "tMRS violation!" severity warning;
end if;
if cke='1' and csn='0' and cmd/="111" then
checktime(now-lastref, tRFC, true, "tRFC");
end if;
if cke='1' and csn='0' then
case cmd is
when "111" => -- NOP
when "011" => -- RAS
assert initdone report "Opening row before init sequence done!" severity warning;
bank := to_integer(unsigned(ba));
assert banks(bank).openrow < 0
report "Row already open" severity warning;
checktime(now-banks(bank).closetime, tRP(speedbin), true, "tRP");
for x in 0 to 3 loop
checktime(now-banks(x).opentime, tRRD(speedbin), true, "tRRD");
end loop;
banks(bank).openrow := to_integer(unsigned(a(rowbits-1 downto 0)));
banks(bank).opentime := now;
when "101" | "100" => -- Read/Write
bank := to_integer(unsigned(ba));
assert banks(bank).openrow >= 0
report "Row not open" severity error;
checktime(now-banks(bank).opentime, tRCD(speedbin), true, "tRCD");
for x in 0 to 3 loop
-- Xilinx V4 MIG controller issues multiple overlapping load commands
-- during calibration, therefore this assertion is bypassed before
-- load-delay has passed.
assert (not accpipe(x).r and not accpipe(x).w) or (now < lddelay);
end loop;
if cmd(0)='1' then accpipe(3).r:=true; else accpipe(3).w:=true; end if;
colv := unsigned(std_logic_vector'(a(a'high downto 11) & a(9 downto 0)));
case vmr.blen is
when "001" => blen := 2;
when "010" => blen := 4;
when "011" => blen := 8;
when others => assert false report "Invalid burst length setting in MR!" severity error;
end case;
alow := unsigned(a(2 downto 0));
for x in 0 to blen-1 loop
accpipe(3-x/2).bank := bank;
if cmd(0)='1' then accpipe(3-x/2).r:=true; else accpipe(3-x/2).w:=true; end if;
if vmr.bt='0' then -- Sequential
colv(log2(blen)-1 downto 0) := alow(log2(blen)-1 downto 0) + x;
else -- Interleaved
colv(log2(blen)-1 downto 0) := alow(log2(blen)-1 downto 0) xor to_unsigned(x,log2(blen));
end if;
col := to_integer(unsigned(ba))*(2**(colbits+rowbits)) +
banks(bank).openrow * (2**colbits) + to_integer(colv(colbits-1 downto 0));
accpipe(3-x/2).col(x mod 2) := col;
end loop;
-- Auto precharge
if a(10)='1' then
if cmd(0)='1' then
banks(bank).autopch := blen/2;
else
banks(bank).autopch := 1+blen/2 + (tWR-deltat+(re-prev_re))/(re-prev_re);
end if;
end if;
when "110" => -- Burst terminate
assert not accpipe(3).w
report "Burst terminate on write burst!" severity warning;
assert banks(accpipe(3).bank).autopch<0
report "Burst terminate on read with auto-precharge!" severity warning;
assert accpipe(3).r
report "Burst terminate with no effect!" severity warning;
for x in 3 downto 0 loop
accpipe(x).r := false;
accpipe(x).w := false;
end loop;
when "010" => -- Precharge
for x in 3 downto 0 loop
accpipe(x).r := false;
accpipe(x).w := false;
end loop;
for x in 0 to 3 loop
if a(10)='1' or ba=std_logic_vector(to_unsigned(x,2)) then
assert banks(x).autopch<0
report "Precharging bank that is auto-precharged" severity note;
assert a(10)='1' or banks(x).openrow>=0
report "Precharging single bank that is in idle state" severity note;
banks(x).autopch := 0; -- Handled below
end if;
end loop;
when "001" => -- Auto refresh
for x in 0 to 3 loop
assert banks(x).openrow < 0
report "Bank in wrong state for auto refresh!" severity warning;
checktime(now-banks(x).closetime, tRP(speedbin), true, "tRP");
end loop;
lastref := now;
when "000" => -- MRS
for x in 0 to 3 loop
checktime(now-banks(x).closetime, tRP(speedbin), true, "tRP");
end loop;
case ba is
when "00" =>
vmr.opmode(a'high-7 downto 0) := a(a'high downto 7);
vmr.caslat := a(6 downto 4);
vmr.bt := a(3);
vmr.blen := a(2 downto 0);
when "01" =>
vmr.opmode1(a'high-3 downto 0) := a(a'high downto 3);
vmr.res1 := a(2);
vmr.ds := a(1);
vmr.dlldis := a(0);
when others =>
assert false report ("MRS to invalid bank addr: " & std_logic'image(ba(1)) & std_logic'image(ba(0))) severity warning;
end case;
mrscount := tMRD_ck-1;
when others =>
assert false report ("Invalid command: " & std_logic'image(rasn) & std_logic'image(casn) & std_logic'image(wen)) severity warning;
end case;
end if;
-- Manual or auto precharge
for x in 0 to 3 loop
if banks(x).autopch=0 then
checktime(now-banks(x).writetime, tWR, true, "tWR");
checktime(now-banks(x).opentime, tRAS(speedbin), true, "tRAS");
banks(x).openrow := -1;
banks(x).closetime := now;
end if;
if banks(x).autopch >= 0 then
banks(x).autopch := banks(x).autopch - 1;
end if;
end loop;
-- Read/write management
if not loaded and lddelay < now then
load_srec;
loaded := true;
end if;
case vmr.caslat is
when "010" => i := 2; b:=false; -- CL2
when "011" => i := 3; b:=false; -- CL3
when "101" => i := 2; b:=true; -- CL1.5
when "110" => i := 3; b:=true; -- CL2.5
when others => i := 1;
end case;
hcmode <= b;
if b then hcread_en <= accpipe(1+i).r; else hcread_en <= false; end if;
if accpipe(2+i).r then
assert i>1 report "Incorrect CL setting!" severity warning;
read_en <= true;
-- print("Reading from col " & tost(accpipe(2+i).col(0)) & " and " & tost(accpipe(2+i).col(1)));
-- col0 <= accpipe(2+i).col(0); col1 <= accpipe(2+i).col(1);
read_data <= memdata(accpipe(2+i).col(0)) & memdata(accpipe(2+i).col(1));
else
read_en <= false;
end if;
write_en <= accpipe(3).w or accpipe(4).w;
if accpipe(5).w and write_mask/=(write_mask'range => '1') then
assert not is_x(write_mask) report "Write error";
for x in 0 to 1 loop
for b in width/8-1 downto 0 loop
if write_mask((1-x)*width/8+b)='0' then
memdata(accpipe(5).col(x))(8*b+7 downto 8*b) :=
write_data( (1-x)*width+b*8+7 downto (1-x)*width+b*8);
end if;
end loop;
end loop;
banks(accpipe(5).bank).writetime := now;
end if;
end if;
mr <= vmr;
end process;
-----------------------------------------------------------------------------
-- DQS/DQ handling and data sampling process
-----------------------------------------------------------------------------
dqproc: process
variable rdata: std_logic_vector(2*width-1 downto 0);
variable hdata: std_logic_vector(width-1 downto 0);
variable hmask: std_logic_vector(width/8-1 downto 0);
variable prevdqs: std_logic_vector(width/8-1 downto 0);
begin
dq <= (others => 'Z');
dqs <= (others => 'Z');
wait until (hcmode and hcread_en) or read_en or write_en;
assert not ((read_en or hcread_en) and write_en);
if (read_en or hcread_en) then
if hcmode then
wait until falling_edge(ck);
end if;
dqs <= (others => '0');
wait until falling_edge(ck);
while read_en loop
rdata := read_data;
if not hcmode then
wait until rising_edge(ck);
end if;
dqs <= (others => '1');
dq <= rdata(2*width-1 downto width);
if hcmode then
wait until rising_edge(ck);
else
wait until falling_edge(ck);
end if;
dqs <= (others => '0');
dq <= rdata(width-1 downto 0);
if hcmode then
wait until falling_edge(ck);
end if;
end loop;
if not hcmode then
wait until rising_edge(ck);
end if;
else
wait until falling_edge(ck);
assert to_X01(dqs)=(dqs'range => '0') or igndqs/=0;
while write_en loop
prevdqs := to_X01(dqs);
if igndqs /= 0 then
wait on ck,write_en;
else
wait until to_X01(dqs) /= prevdqs or not write_en or rising_edge(ck);
end if;
if rising_edge(ck) then
-- Just to make sure missing DQS is not undetected
write_data <= (others => 'X');
write_mask <= (others => 'X');
end if;
for x in dqs'range loop
if (igndqs=0 and prevdqs(x)='0' and to_X01(dqs(x))='1') or (igndqs/=0 and rising_edge(ck)) then
hdata(8*x+7 downto 8*x) := dq(8*x+7 downto 8*x);
hmask(x) := dm(x);
elsif (igndqs=0 and prevdqs(x)='1' and to_X01(dqs(x))='0') or (igndqs/=0 and falling_edge(ck)) then
write_data(width+8*x+7 downto width+8*x) <= hdata(8*x+7 downto 8*x);
write_data(8*x+7 downto 8*x) <= dq(8*x+7 downto 8*x);
write_mask(width/8+x) <= hmask(x);
write_mask(x) <= dm(x);
end if;
end loop;
end loop;
end if;
end process;
end;
-- pragma translate_on
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iopad_ds
-- File: iopad_ds.vhd
-- Author: Nils Johan Wessman - Gaisler Research
-- Description: differential io pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity iopad_ds is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0; term : integer := 0);
port (padp, padn : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of iopad_ds is
signal oen : std_ulogic;
begin
oen <= not en when oepol /= padoen_polarity(tech) else en;
gen0 : if has_ds_pads(tech) = 0 or
tech = axcel or tech = axdsp or tech = rhlib18t or
tech = ut25 or tech = ut130 generate
padp <= transport i
-- pragma translate_off
after 2 ns
-- pragma translate_on
when oen = '0' and slew = 0 else i when oen = '0'
-- pragma translate_off
else 'X' after 2 ns when is_x(oen)
-- pragma translate_on
else 'Z'
-- pragma translate_off
after 2 ns
-- pragma translate_on
;
padn <= transport not i
-- pragma translate_off
after 2 ns
-- pragma translate_on
when oen = '0' and slew = 0 else not i when oen = '0'
-- pragma translate_off
else 'X' after 2 ns when is_x(oen)
-- pragma translate_on
else 'Z'
-- pragma translate_off
after 2 ns
-- pragma translate_on
;
o <= to_X01(padp)
-- pragma translate_off
after 1 ns
-- pragma translate_on
;
end generate;
xcv : if is_unisim(tech) = 1 generate
x0 : unisim_iopad_ds generic map (level, slew, voltage, strength)
port map (padp, padn, i, oen, o);
end generate;
pa3 : if (tech = apa3) generate
x0 : apa3_iopad_ds generic map (level)
port map (padp, padn, i, oen, o);
end generate;
pa3e : if (tech = apa3e) generate
x0 : apa3e_iopad_ds generic map (level)
port map (padp, padn, i, oen, o);
end generate;
igl2 : if (tech = igloo2) or (tech = rtg4) generate
x0 : igloo2_iopad_ds port map (padp, padn, i, oen, o);
end generate;
pa3l : if (tech = apa3l) generate
x0 : apa3l_iopad_ds generic map (level)
port map (padp, padn, i, oen, o);
end generate;
fus : if (tech = actfus) generate
x0 : fusion_iopad_ds generic map (level)
port map (padp, padn, i, oen, o);
end generate;
n2x : if (tech = easic45) generate
x0 : n2x_iopad_ds generic map (level, slew, voltage, strength)
port map (padp, padn, i, oen, o);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity iopad_dsv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
padp, padn : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_ulogic;
o : out std_logic_vector(width-1 downto 0));
end;
architecture rtl of iopad_dsv is
begin
v : for j in width-1 downto 0 generate
x0 : iopad_ds generic map (tech, level, slew, voltage, strength, oepol)
port map (padp(j), padn(j), i(j), en, o(j));
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity iopad_dsvv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
padp, padn : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0));
end;
architecture rtl of iopad_dsvv is
begin
v : for j in width-1 downto 0 generate
x0 : iopad_ds generic map (tech, level, slew, voltage, strength, oepol)
port map (padp(j), padn(j), i(j), en(j), o(j));
end generate;
end;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
c9vsW5JBCvThyxOUH2PprRXrwDWuKZW/Q7qPv429HnbShw4Uk66yycd+J5tES7AzUCyGeanqADbi
t/NXtBFOdg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
THl1Z3bcMS4H5t6D0G+kJ/FC2Y9oXN8UuO5gTyqyx046tFrVCFbF7b10tz4zI+nryigVgXDuQjpn
REJa68sEKDIsGl5JYzOYVe9IZ30LgoXUIOey68bvuu3Fnu8lEQh/WChcCnbyekJTFEdRaUW6S2O+
5xce7Ha8Gv7YClnhp04=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
KL9gEW9UR9bJ2V+rRImGqHBVYgwBOrGPetNJZ9L5EOgu04h1LECL47Zq26De2Obbv4OkIEGfGFbZ
muWpwFGMSP/qDDeS04mLx/tWX4SnYgQRVyk8AGGlepDKbn1R0w9YaYChqwaqdh3fMk+xJZbtgoWp
4ejGlCOtRuSFxFcOTPGLnPLr5saG0n7SH0iOlkdKRcxP8k1FnXr8kYqxu6g0r1ZNWNYlDcRB7pBC
lrlL52/HTgYUGboGp0/wpS3BU8yKiMyKpm/Nc0Q701u3QL3zraihgQqtTSzkLZnBFXKNrCd6K2Zb
gw1krcKarckcDY4W+Jw/vlWaBMsrX/8GffFxsQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
I9+ICDzIgzYMfdI9n5+7cSfa+M9K8Q9HlZVHvp38kWsb+jUXV67Oh07GXgNqpn7RlOPdQSyhyXf6
AZH+fL8ycTHV0MoCLtaJieiw5P4E1Pm7Fdq2uCENFjt8u7I2RH9/lcoRh4KurkxCVCe86Dtk1oWB
bacFgZX+QZ+FCZn+6nI=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
pyasIdA/E1o2abIoUkxhLYQwvp5B9zIwQEm/+EGPR3u06a5SPM2I1E62WIwSJ7iN/bqdRmd03/xZ
zjSCCiFFaRUwQmJJ5xZcUnw15IQqIRd/WQQ56gktCUx2rEJwJ4BBJrhOQsbLLnEDNgJUxpYVfXAy
ix6G1h7tonYt5pC9K8hh3YN8608V5TRujBAEsLi+3lAMFCMgjGqgS6cpljhaHIjuKULPnRb7+Rll
fIJqbRqDAQ0ubxbSrdH7w8ZIqWH5mG/hnLBefDFlIZJh/pHjOIOLGPh9RyUn99n5SKT8NF75l8Mj
ggHTuLkcPsoN2kGMWMDxZ752vU2X39SpzveZtA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6000)
`protect data_block
TxmWdQtoCa72lA+PjmaVWNzez4mZxpW7I8VWfPbcGicMeEL2MwwAS4LUnoxwA9Uhmm5ot+LUjCmv
eDB7SAvMi2HMKnvkVOM6GyDSV3gAIeNsWXHPVpwGySt8l+veQ87+wCB2U0M2AjDDPy5G0YrHv7SV
3hwskYbNG5I35qHpm3MFyP0vEDTw2Fa861T3JSQElQvkHyiJtc1mCK8c+3Xwu2sX2tdUav9HJ/w9
ZeB6TCc1chmVdFw//m3On54B7bmWN9Zebwnw5VQGvAYNMLyudEgVjYJwsgwTfKt7pZ93DMozPsEb
mZW50l08EWStM63eu5CZx2XBarUhqb053q94CYABjIYCo57BhlAgWgkKSS2f5WQW0T4Jc3rrfKN3
sLKdFCmMZrqfr5pgPkkX+nvfqUlvDaNXr1tYdehUiUwQuHo0YktKmaf9b7G08xq2O+KihhDW8bJL
JxvKd5VOwLu5iT8eD4v22BpAwoc1xjn98yzfCmkC27huSSupAOcJw+AP5OFOkoRBWp079P45WQOz
o/hkgLdSsXaQUNYZhi2sEsKzRYQK+hrxajBLt5oHEBJbf7wIUiygAcdixuv12Dd/r5+WcBPm4SJO
EmUMYhUA15hnaNALn0dGvrSkIP5NslL6zWERTi9G/OFbUb1a799ztM/HsHegshJwRbCxHi2xIz16
z35IEn7CVUoWVCtQlpFDFlgUxi9BshVVTf/6EayE6uFNg6KX4HhvSmuwujoT0wRmbQZ3Ia7MGLGS
uyxfc7BJHDjz5MQ3coKQd51qJqfHTeRGTAeQ9SzqASPY8ebTFMlp1vqFRPbOq6KsrHx7WT75pRyg
8foHSrwUrb/E8FbwnLnYe9umPzKEjGCTo6eXMWpVIyglksrRWrHIM0OOlju1rUPs5g8RID/+aWQl
krguToDL3/FbiBN/OpIpzzDFYSMSIhrq7W2k0D6X90tLdM86lV4BCaIna6MHSucetYvc6zrnoGID
ZdXRDktS64+FUnZpecuBvQtan+SwG5Rvqymh0vB5LWrSR34biGzmqqTBL6p0TkGzPJUxr3lqAthc
KMtK1x/EDuNMioKMJR1MutrwOckHFMTYiwMKhxvYePPfxHJAgRzDfDBKJ9KWfOFooBxhHPeirSD7
ApSD9kcvPzrCWtqheCAAtKvcZP69vAN+sPL4o8f8ZwS4u3neFS/PPgIEyPAjOT3Rx+hphXuRbR0C
xcg9NF/xUbIz1a0O81Hw+8USWdyB4CQVxN5TGWS0eU0Pzoempf3cbN/Umb4Z+G4nc6TVnd8Gzb/m
jLUUtvYTa++9REXif4S6B/jCByLNDOxPQ28fB9svsp0vyMkxtzExcTVuuXpp4sLmoIH0UguSwDrE
x5YlFE3mWIf1OcehV2K2ErmJpe/bx8/yRbJ+kETpRKlv8D6XTVRQt+Vea+z/vp51qlFOXkOir/4z
HbT597Zit9GKjTATbsheBAZFsu2OizevmfFZYM2WDfnnUnMamAUqxaKqV8sBjWCkxt7aOfu6RZRK
yRL7SOf4zEEAFHMuE+GPm0rxk/sCx2m26oOMj8DaX8AQ/3s2oNdxQ2ddf9myEgQlGerb+eAV5o1a
5LqAFtKIk9Wa2pAmhmbxUpfE38EhmUl+234E/YoxdQLzujssw+CNBvGu8kay1h0rWYV33KjltIfQ
e7KSp27ixG50GEf69G4xAL3n1v6tR1ouThly320lFyJ3Wssf2xL8OdqYZSoLvRF/z5Km2UbN8C+7
b8ffHHM55SASUZgCBIzBG1crH+eNXgiO9efb0rlBQrssgT/gml39YobX1TcOcgos3QpPzFpHw6m7
nZtdH/d+GpWJzbnPCAuEPyDwb4nftuTZZeEacP2zZPvGGROsylXzm+/InIrEx2Ja3Pe03gKZ7kZI
MEAhq8wwkZ0DVk2WDBZxVi/MP0Bbu1xA2CYb9Q2ylABgnzj8gdvoi/JbROGOoF0aSyDWizHV76E4
w1W5PxM9E8680QSTHrxcNxNz0ZO0XGkV3wokatX/5drWMmp+l8vRqoY0zc5+XDjdNgmbt4Aet9cU
9c6Gu3Dz7tgMbXBJsu4EmdbZSNKQLto9ZAd1zOPonSwPo6bwiU+LqjOV94wy+eH4/jYjYrwJiHDM
HyNwJuLi+ht2lBMKmwj6gZG9yecfGBvmcchYOpnyXKAHrE4iJyQuqiqRgL8TOGuMS/BWEZoUV1xT
i+vQiLWtToNOm5bAPioM2s+TcGjzptmZQsmk/bK0sVLLcyXBBxlTMsYnpOl8TnUXNiBNSlg7yoDO
UFvNugB1iR9yTD4Qy+bX5OT2j0OaP1aSMr9OK3fYCxIfl9oUrqQAz1fRc7UOniKSxDClSdhrt/g3
2w+S2xLd1sPkJLh1Z042bk/BdmJgWwfvjpSdD9cA2H0bd9l6f1JmA+XOCcVm8aiqBP+AncvFZkNi
zTCIrFbLsPiUkIMQ8aGtWpFmxbJ/TFaR5RavOE77XkqCyfjvAS1CkGEmQPu45C3KNLMljHvoTGoM
K0WpaO6nYpRhoTp3pB/GFYZH7IyrzaWSCWGVDfmwl8kwuw077+RrBKytLdEvirocgA0XXTckkOP2
YlEVy4zWwy4ozYDcU3sZItQzhUk+XUAtuRyMYQaD+kMmv3R18LAiwcGKLZW5sHBT11dPSGdWpJPQ
JUoI6scMIZZkhWcAd6RdfSUidOpWtiNkDD3wRwbkGsFBwFVW3fXckKO7AQMpCwqeAZq7xzyIDvYO
wNsir/tIa51q0hqSvHP2aaht0TF52ZHQAl11hXQfGtlSMcfrCP3EXGW7Dyrjtk0bPO+U5jyHiztH
b6HKhOdFZarKHPuzQpOYGb4fVlcRAYz4ujhTcfBZOB50NCcympkfCerHKuQkjR7CtJCU/FuOJWqA
LJhIn6vd5ZBZsZKQZfz/Vfi4D8HtvIAg7efEMwCF4sZoWND5Q8XUITLBQ1vm38m7jGV5WooUzmA/
YYHZ5gNMKTNI2rjx6dOapKVN2kwpUgmnqIEw6NLjCZDHmJuvFzqFI6E12fndcObS1LF/VMSrKmhD
F0RLzCARmlpQ8YQaGv3aF/i+jmYcVLvf353fL9w1QVKn+8/5CDSVzjE423D4nIBfbngJneJS3+2z
duSI7FHGEzdj93raYGcZe43fEhZ1dIF9H50A84Rix/gVFWv3NhB/Tcjk2f8AmFp/M47dxGIRkmOX
EQj3EEWq0HXDR1iUyf6YMizK70jMfZ1r6iOGMZYy4g93/e3FBklX7CleETlXaDWS7BC243ka5P7M
jhlhSxTflKC6x9toDQDhWVTQOhN24qUSYugdEru8c0ju8NYZvhRSYvCgnPo5M6tq9hAZ+zBFGOgR
wA3czXQUG4Liq0Gt+Npgd9LUYwhQFo8ahyVu35826rbZybwbX3HGwBadXf5m+yGOmAKPzhu7h96x
FoFUeJKhCU6hlBeCj9IPG9Q+DiRvBBrlgGi/SsjEP5HYTGXP3XLdza4E5gaOqj1PBR/8S6e+NLA7
rQx4Omz8BVG+qVbNVkQpCN+ozDK4WK49yuLCyMWLl6SbOC05dZziMPbSP4IULW9bK/o/Sac8rZtn
QbhQojrvXv7qj6bzy9mUuWQHF8m0ZR9T2hqwAx0vVEpoWU2qRpp30md7+/4WU6ddq0mn3zNwdAa6
nhI/Qrga2D7peVuYaFKYg+iC9soZccRmUDVi5AepG8+oGRAEmvIadnS2Orz7J9PcDEaP7/wHqnkT
E4+0+OKo50zH7D9FmjY0+zhOkinkAmoxLI3koQz1AFVoYB3Oc4FJQ1mAjBn5RDxciAall4tcHmph
AHjIjF6/npOI9rqg9Kv3SYDhY8CgNSqexhQSyxe8FRwDncSGYRq9pdL/EepWjjkbvyAfAN296S3M
KggAEB+SdNHvqqstJFzRBc1LY8WkE8ouoHbxa97vRXY+hopaCl37NXjHDseFr9iZruDOXtGtPs5l
//oZT0Gd8qEzmegeShrQFplZCdGwtEHjMVaZOFcaoEri1SYCzZS8vFWuZ31NrfAzbR8yi/zay0qG
DgZ2iLXuVJWE0DwQ5GnozJl06xnXQiEnUhF3Av/XcnvLLupy3IwVDjcpAXsPQNpYgaNm8ZHiukYt
TjNlQxroJDKZKrBQTC7aTDeyTNAdBJfWQ1NWqryxz/tVKNHdHKNjdT5ubWF+moI/KkSkIv0mRI+f
4KJEL5pr3wdRXTuAhP+2qqEHmYoYNjfFikVfcZjHOeFwunZuIlbYHqaAR1zrI6D60OK/DHl6GzRO
7lhOolznbM00mA8FGOjesVn4WR79qgO7a6W78gkt4OJ5ukjp+CiX8uTm/NA//4Ep7QF6JdB9q0aS
7uYdsBb0qpSMfUiT/Ukq/OEbLHBCcTRq+9KqtZA10v0RytoU1K/qdfOhsgSwj89iQAYCmYHreNnH
Pk7yD1F+7ZAhRvP8GMu/DGcDO6d/+k2eACv9mZT5yr4xzskXlgzrdBCD36hL5KdZSP7IKNIHcHNl
DSW+wenxH1cxlfl5OMfZDkirH/RR1FQnuVJnngBYHPlv3JHuQUqE0ZF70K4hSKYYi3B6t/ldaCNh
WVGOdbM1SO4fwlxXL9M1AmCMX7zOaQi6EkXzzWvmaHmRtYeuvi1xX/byx+rII7a6qdzETqMkvlln
n/2UCz1AFSzQjVka0eJ3b9VVDJDQ4RQhQ15cM9IeCsvqxd2WlQCLXt08AUGfHZWCjHdzmmgkrlG3
e6pKulOVGc5VwSWWbnkxeqXfpzvVQN7XZeOboQn2IuyNvWkdNmqgn0tQhFNeIanvT/GiJ0HmBuMZ
9/65RLl7uMHcKe2Wr12VGmVDyDTNZfN5V4YZwESdWABbU6vztTH7VyNenpCD/ZFUbglx2Dc+7hyo
ljr3KnNPsq0hV/9wB5WoXClZxy1KSu2ofTRwfSQi7+G6AddDAeGKRl+oVQOvWevsUzoKJBpz2q8r
7aJoFF3U0JYvZVVFRRSw3SEVeG3hpUBcAQzJFFqLweGy2vP/FFryOcmCOC89TEVYMm5at/r4uGOY
gxSUhg6RaSAuxyQR+nKXbKjwJ0rA/P9lhNgMIQ8/lqKrWEINcwADetLUHzzwcq5cgnzq9SoKcKkg
PuSoKNIM7Zt2niydQCACx14PEB8696I+r77o8mWc1zwcMxHSk2C0WnQPAJo1iEIS/0WEJfUg+gGh
QXAe8iirvQme7pLOHHOuphtSfEqf6rXqQsFPj1zB16xcixO3lOJAdW6tjrN0/V8vrSlu3M1intJI
lX4cOJxn7cTy3UrPhSRsOxpQHhbofPKNNaQRPOfzImO8p4ldoWiNK9M2S0yUsln/61pJi7aigg1g
hM5OqMT4KwvBucdfSZDGJ8RpHmpHyBniIvzbbKyiumThPmNvL4H/0NbcQwjl4q1lZfeSoiuiW1YN
k2F+vHcbg+Lrmd14d3249JQ6wdOT2DsvRDDPFwhH9jn5K3DdeEVjJAeHoHnV7wAkZ4QvYIlzU8cC
s8wqUyhmDnKdF4nz3/HafVAoKzRxa8vJV9JaNzIpQa6R4PpMfK2xK23PY+dZbtXshrkNfEap5322
O5W+MaLd/jqts9orI2TZOiRAgYw4YYLoXN4GTjhx51xmj+7R7jHGCQqn6LrEVQyhWxPo+0ztK2QB
vEG3/ieXSJZbijN6TpTMQBH0CuL0uQqNBpgJJXPFWzGK87oQo7gkVY/iEfP+j2vhyl7WaagNDc+J
pZByqjDUoxq3/5pG2G4HFj/+wyIaJtre2+kfm7li5yy6yZC9H+q+85Q3ggS+owE4nuyURPbM/J8D
1Mkfer2p67WoF+l+njAuRp6nIde5H50jf+TlnFJ7dj7hXKPDUOIXEQc2KQ23bJNYbzs6/bpCUZLS
/KDNykC3mrPAuwkxnedbELLh5X9PhG+IQo4KBiLAYBLvpkwryx/+c6iWP0MdYwwWdQNlzjUb6zFZ
xtfyu5jynJuSOtUWBYgxnDL8gssrC7aKybNiwVC0iRGgFUtchhb4vCvFcdR63Coqvmn+IpGC1UDj
iDtZYnh/W6U3ZnueY16l0SbsW8B9iEzO6M/jhFmVOkG4tmmaS4IhIJoSJCu7LKYi/JKrnVUTgCS2
iRj9hq57hJie8ty8PgaUYvMtILC9g65OF0+m41kFH4V35QzagJIhWb/BQPSAezL4CPqcVfPjMifT
p6V2xXY3uUPVVAMbyUQTXe2hPWeem0gAVxx0A8OoTMz3oTY9Eg4y+KbM7rccywEmWVGqJU1/BA+5
hvkrvh9NOuCa+pc9W7WgIP4U4cUEgsKPae2Dz8D/izCVCT1Ffv+jwqjnK5wg4N6gEQmqvl9n7ME1
8IVw3qaE2GLoiA0EsN8SqeGDmQ5eOY0unGvarzyaJ9+DqjqMbZYO3bpr7sdB+ZwGKzBfxULPLKWh
qi4XbcaEpsyBC4uVVC4650BIUJ3LtsWoJ6WdHaDGRaiYCAaeTf5cs4tkZlZI7ND6XIT738HnO53P
raCskxAjLHW3pCT+na42X+Nc2zZCJktIjPV9vUvxlKup2OZxbVON8b5ddg20kSM3GCZcOlUjDWD4
hluKs6pY7/hpxVCoIZy1u1UqYeAknkKqlNrT+p7rjw9HfQS19efLUbcDODM4GZwtP1qijVXxVMzj
0dbD3fc/7lyRhY1gV4W/YP+y816lRKLfckhCtFB2ceq375fIds+HRqMQQp+3xGKPt1pgEX15V1ZO
4A409Mdqgn4D3cOSfo1SmgqHcTTT4qgIMT5rVACDk3DaHu8NYTJFWkM0uAm/W6CZyfty1/zirW5S
EBGBWTTk8QpMXaqtIT+SEVYj7PpGt4gCp0+Y1FjhP+JN6FgMKtM3aAjfK8+jn3lrCU9YB7WyFJ8O
pVupNv+2vuMSrmRx7tTcvD0NxtzU7UxQHWOTSRDA6cGh5Va3hdeDLiy9NQsdrF+C3XVnmMZveXak
hJXury9lmwuCsfX2YJcT4WxCshnMnptMoktyMixUIP6KKEn0S74GqhRvlWIbCOrsuR44vaGP9HfD
ylaPsFHGfzIMD30kRu981jBtX1v8bRK1Of9DoL9W4exb8ViaA37nsevcLAcBKeM5LnGAtmdUHkzg
8T7GEblSbuCRxdUxNWNj1LagRugvJ/ELYptjU3NcMVrfeWbsgEop7/6glwofBO5n3BlXe83qe6Uu
zLCt1RHh2XnO7lEF+K80CcufmJfgEgkFvwNIcJpkRHzrSucwXhoWWCseUMZ6pvwVpxpfpj7GLWRN
SO0Ai1D8D0AfWQxzQgoRty5Tx1TttNtufuTxV/TfXuKUWa+rbei7JuBL4gESmEOecV3+ngw0hNE0
2E8SQdT8JJnToRzCf3GQIBXLGmAQiTmhYhHRM7aZmCGe0mVYL/0b7cpQ5PQEObYKxSW0RdMQ3fXE
MGh3IJWIOVl3ANBxsPU+E3U7fVYc28LvTwNCzYeiW4cl4bp53f++fuNiRL+SSrRx5ysAFvor0ats
yma3/Fe4kaTOncKlcpI6vKXrW9MWrdTeJ1H2x0jYO84oIYtnO+hUpaf1HrmMAus03++llgiG+yIJ
3cpG4E+xFDgFs+MWKOL7+khzfpTmhw8x2LSoMnrq3Qjr8FcUKRTt+yJBELuPx/T/h18EK+gQScfT
cxrYLqP0ejDEemLcIjlxWn9DO/WeWw9Nu38d1ndQ44AJ2JcQ2LqbFPkejr8GkpeXaMnu8gZPoTL8
fx4lGaf27SCsX/h170tmL2QmMdVIwL8cfa75dINrKeThC9W5C4kDyrpKkisXL6hRQ9nUDYdILYk0
suWBz4K13fHx1xSQHIr2UslOri8bd06kcq48G7y+nLf+clQfBC0zwIx2dtUBn5aCm5jwlgpV0kRN
scCeSrGEa0QHnFgJLZUu1Y6j5XFP4j1/uAkLoJOmObyfWdTUL0yaBxM4mXcwbbzTPXLJX/AAExc1
WBEsjXGg0WY+usAtXZYXLtpJVzr7COG/ljnHPKTUB6WVgzL3yBR0JN+Y4TSaQHWH6IkMV8YLcg74
sw9b8HdOcw3ZViii0DP/
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
c9vsW5JBCvThyxOUH2PprRXrwDWuKZW/Q7qPv429HnbShw4Uk66yycd+J5tES7AzUCyGeanqADbi
t/NXtBFOdg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
THl1Z3bcMS4H5t6D0G+kJ/FC2Y9oXN8UuO5gTyqyx046tFrVCFbF7b10tz4zI+nryigVgXDuQjpn
REJa68sEKDIsGl5JYzOYVe9IZ30LgoXUIOey68bvuu3Fnu8lEQh/WChcCnbyekJTFEdRaUW6S2O+
5xce7Ha8Gv7YClnhp04=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
KL9gEW9UR9bJ2V+rRImGqHBVYgwBOrGPetNJZ9L5EOgu04h1LECL47Zq26De2Obbv4OkIEGfGFbZ
muWpwFGMSP/qDDeS04mLx/tWX4SnYgQRVyk8AGGlepDKbn1R0w9YaYChqwaqdh3fMk+xJZbtgoWp
4ejGlCOtRuSFxFcOTPGLnPLr5saG0n7SH0iOlkdKRcxP8k1FnXr8kYqxu6g0r1ZNWNYlDcRB7pBC
lrlL52/HTgYUGboGp0/wpS3BU8yKiMyKpm/Nc0Q701u3QL3zraihgQqtTSzkLZnBFXKNrCd6K2Zb
gw1krcKarckcDY4W+Jw/vlWaBMsrX/8GffFxsQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
I9+ICDzIgzYMfdI9n5+7cSfa+M9K8Q9HlZVHvp38kWsb+jUXV67Oh07GXgNqpn7RlOPdQSyhyXf6
AZH+fL8ycTHV0MoCLtaJieiw5P4E1Pm7Fdq2uCENFjt8u7I2RH9/lcoRh4KurkxCVCe86Dtk1oWB
bacFgZX+QZ+FCZn+6nI=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
pyasIdA/E1o2abIoUkxhLYQwvp5B9zIwQEm/+EGPR3u06a5SPM2I1E62WIwSJ7iN/bqdRmd03/xZ
zjSCCiFFaRUwQmJJ5xZcUnw15IQqIRd/WQQ56gktCUx2rEJwJ4BBJrhOQsbLLnEDNgJUxpYVfXAy
ix6G1h7tonYt5pC9K8hh3YN8608V5TRujBAEsLi+3lAMFCMgjGqgS6cpljhaHIjuKULPnRb7+Rll
fIJqbRqDAQ0ubxbSrdH7w8ZIqWH5mG/hnLBefDFlIZJh/pHjOIOLGPh9RyUn99n5SKT8NF75l8Mj
ggHTuLkcPsoN2kGMWMDxZ752vU2X39SpzveZtA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6000)
`protect data_block
TxmWdQtoCa72lA+PjmaVWNzez4mZxpW7I8VWfPbcGicMeEL2MwwAS4LUnoxwA9Uhmm5ot+LUjCmv
eDB7SAvMi2HMKnvkVOM6GyDSV3gAIeNsWXHPVpwGySt8l+veQ87+wCB2U0M2AjDDPy5G0YrHv7SV
3hwskYbNG5I35qHpm3MFyP0vEDTw2Fa861T3JSQElQvkHyiJtc1mCK8c+3Xwu2sX2tdUav9HJ/w9
ZeB6TCc1chmVdFw//m3On54B7bmWN9Zebwnw5VQGvAYNMLyudEgVjYJwsgwTfKt7pZ93DMozPsEb
mZW50l08EWStM63eu5CZx2XBarUhqb053q94CYABjIYCo57BhlAgWgkKSS2f5WQW0T4Jc3rrfKN3
sLKdFCmMZrqfr5pgPkkX+nvfqUlvDaNXr1tYdehUiUwQuHo0YktKmaf9b7G08xq2O+KihhDW8bJL
JxvKd5VOwLu5iT8eD4v22BpAwoc1xjn98yzfCmkC27huSSupAOcJw+AP5OFOkoRBWp079P45WQOz
o/hkgLdSsXaQUNYZhi2sEsKzRYQK+hrxajBLt5oHEBJbf7wIUiygAcdixuv12Dd/r5+WcBPm4SJO
EmUMYhUA15hnaNALn0dGvrSkIP5NslL6zWERTi9G/OFbUb1a799ztM/HsHegshJwRbCxHi2xIz16
z35IEn7CVUoWVCtQlpFDFlgUxi9BshVVTf/6EayE6uFNg6KX4HhvSmuwujoT0wRmbQZ3Ia7MGLGS
uyxfc7BJHDjz5MQ3coKQd51qJqfHTeRGTAeQ9SzqASPY8ebTFMlp1vqFRPbOq6KsrHx7WT75pRyg
8foHSrwUrb/E8FbwnLnYe9umPzKEjGCTo6eXMWpVIyglksrRWrHIM0OOlju1rUPs5g8RID/+aWQl
krguToDL3/FbiBN/OpIpzzDFYSMSIhrq7W2k0D6X90tLdM86lV4BCaIna6MHSucetYvc6zrnoGID
ZdXRDktS64+FUnZpecuBvQtan+SwG5Rvqymh0vB5LWrSR34biGzmqqTBL6p0TkGzPJUxr3lqAthc
KMtK1x/EDuNMioKMJR1MutrwOckHFMTYiwMKhxvYePPfxHJAgRzDfDBKJ9KWfOFooBxhHPeirSD7
ApSD9kcvPzrCWtqheCAAtKvcZP69vAN+sPL4o8f8ZwS4u3neFS/PPgIEyPAjOT3Rx+hphXuRbR0C
xcg9NF/xUbIz1a0O81Hw+8USWdyB4CQVxN5TGWS0eU0Pzoempf3cbN/Umb4Z+G4nc6TVnd8Gzb/m
jLUUtvYTa++9REXif4S6B/jCByLNDOxPQ28fB9svsp0vyMkxtzExcTVuuXpp4sLmoIH0UguSwDrE
x5YlFE3mWIf1OcehV2K2ErmJpe/bx8/yRbJ+kETpRKlv8D6XTVRQt+Vea+z/vp51qlFOXkOir/4z
HbT597Zit9GKjTATbsheBAZFsu2OizevmfFZYM2WDfnnUnMamAUqxaKqV8sBjWCkxt7aOfu6RZRK
yRL7SOf4zEEAFHMuE+GPm0rxk/sCx2m26oOMj8DaX8AQ/3s2oNdxQ2ddf9myEgQlGerb+eAV5o1a
5LqAFtKIk9Wa2pAmhmbxUpfE38EhmUl+234E/YoxdQLzujssw+CNBvGu8kay1h0rWYV33KjltIfQ
e7KSp27ixG50GEf69G4xAL3n1v6tR1ouThly320lFyJ3Wssf2xL8OdqYZSoLvRF/z5Km2UbN8C+7
b8ffHHM55SASUZgCBIzBG1crH+eNXgiO9efb0rlBQrssgT/gml39YobX1TcOcgos3QpPzFpHw6m7
nZtdH/d+GpWJzbnPCAuEPyDwb4nftuTZZeEacP2zZPvGGROsylXzm+/InIrEx2Ja3Pe03gKZ7kZI
MEAhq8wwkZ0DVk2WDBZxVi/MP0Bbu1xA2CYb9Q2ylABgnzj8gdvoi/JbROGOoF0aSyDWizHV76E4
w1W5PxM9E8680QSTHrxcNxNz0ZO0XGkV3wokatX/5drWMmp+l8vRqoY0zc5+XDjdNgmbt4Aet9cU
9c6Gu3Dz7tgMbXBJsu4EmdbZSNKQLto9ZAd1zOPonSwPo6bwiU+LqjOV94wy+eH4/jYjYrwJiHDM
HyNwJuLi+ht2lBMKmwj6gZG9yecfGBvmcchYOpnyXKAHrE4iJyQuqiqRgL8TOGuMS/BWEZoUV1xT
i+vQiLWtToNOm5bAPioM2s+TcGjzptmZQsmk/bK0sVLLcyXBBxlTMsYnpOl8TnUXNiBNSlg7yoDO
UFvNugB1iR9yTD4Qy+bX5OT2j0OaP1aSMr9OK3fYCxIfl9oUrqQAz1fRc7UOniKSxDClSdhrt/g3
2w+S2xLd1sPkJLh1Z042bk/BdmJgWwfvjpSdD9cA2H0bd9l6f1JmA+XOCcVm8aiqBP+AncvFZkNi
zTCIrFbLsPiUkIMQ8aGtWpFmxbJ/TFaR5RavOE77XkqCyfjvAS1CkGEmQPu45C3KNLMljHvoTGoM
K0WpaO6nYpRhoTp3pB/GFYZH7IyrzaWSCWGVDfmwl8kwuw077+RrBKytLdEvirocgA0XXTckkOP2
YlEVy4zWwy4ozYDcU3sZItQzhUk+XUAtuRyMYQaD+kMmv3R18LAiwcGKLZW5sHBT11dPSGdWpJPQ
JUoI6scMIZZkhWcAd6RdfSUidOpWtiNkDD3wRwbkGsFBwFVW3fXckKO7AQMpCwqeAZq7xzyIDvYO
wNsir/tIa51q0hqSvHP2aaht0TF52ZHQAl11hXQfGtlSMcfrCP3EXGW7Dyrjtk0bPO+U5jyHiztH
b6HKhOdFZarKHPuzQpOYGb4fVlcRAYz4ujhTcfBZOB50NCcympkfCerHKuQkjR7CtJCU/FuOJWqA
LJhIn6vd5ZBZsZKQZfz/Vfi4D8HtvIAg7efEMwCF4sZoWND5Q8XUITLBQ1vm38m7jGV5WooUzmA/
YYHZ5gNMKTNI2rjx6dOapKVN2kwpUgmnqIEw6NLjCZDHmJuvFzqFI6E12fndcObS1LF/VMSrKmhD
F0RLzCARmlpQ8YQaGv3aF/i+jmYcVLvf353fL9w1QVKn+8/5CDSVzjE423D4nIBfbngJneJS3+2z
duSI7FHGEzdj93raYGcZe43fEhZ1dIF9H50A84Rix/gVFWv3NhB/Tcjk2f8AmFp/M47dxGIRkmOX
EQj3EEWq0HXDR1iUyf6YMizK70jMfZ1r6iOGMZYy4g93/e3FBklX7CleETlXaDWS7BC243ka5P7M
jhlhSxTflKC6x9toDQDhWVTQOhN24qUSYugdEru8c0ju8NYZvhRSYvCgnPo5M6tq9hAZ+zBFGOgR
wA3czXQUG4Liq0Gt+Npgd9LUYwhQFo8ahyVu35826rbZybwbX3HGwBadXf5m+yGOmAKPzhu7h96x
FoFUeJKhCU6hlBeCj9IPG9Q+DiRvBBrlgGi/SsjEP5HYTGXP3XLdza4E5gaOqj1PBR/8S6e+NLA7
rQx4Omz8BVG+qVbNVkQpCN+ozDK4WK49yuLCyMWLl6SbOC05dZziMPbSP4IULW9bK/o/Sac8rZtn
QbhQojrvXv7qj6bzy9mUuWQHF8m0ZR9T2hqwAx0vVEpoWU2qRpp30md7+/4WU6ddq0mn3zNwdAa6
nhI/Qrga2D7peVuYaFKYg+iC9soZccRmUDVi5AepG8+oGRAEmvIadnS2Orz7J9PcDEaP7/wHqnkT
E4+0+OKo50zH7D9FmjY0+zhOkinkAmoxLI3koQz1AFVoYB3Oc4FJQ1mAjBn5RDxciAall4tcHmph
AHjIjF6/npOI9rqg9Kv3SYDhY8CgNSqexhQSyxe8FRwDncSGYRq9pdL/EepWjjkbvyAfAN296S3M
KggAEB+SdNHvqqstJFzRBc1LY8WkE8ouoHbxa97vRXY+hopaCl37NXjHDseFr9iZruDOXtGtPs5l
//oZT0Gd8qEzmegeShrQFplZCdGwtEHjMVaZOFcaoEri1SYCzZS8vFWuZ31NrfAzbR8yi/zay0qG
DgZ2iLXuVJWE0DwQ5GnozJl06xnXQiEnUhF3Av/XcnvLLupy3IwVDjcpAXsPQNpYgaNm8ZHiukYt
TjNlQxroJDKZKrBQTC7aTDeyTNAdBJfWQ1NWqryxz/tVKNHdHKNjdT5ubWF+moI/KkSkIv0mRI+f
4KJEL5pr3wdRXTuAhP+2qqEHmYoYNjfFikVfcZjHOeFwunZuIlbYHqaAR1zrI6D60OK/DHl6GzRO
7lhOolznbM00mA8FGOjesVn4WR79qgO7a6W78gkt4OJ5ukjp+CiX8uTm/NA//4Ep7QF6JdB9q0aS
7uYdsBb0qpSMfUiT/Ukq/OEbLHBCcTRq+9KqtZA10v0RytoU1K/qdfOhsgSwj89iQAYCmYHreNnH
Pk7yD1F+7ZAhRvP8GMu/DGcDO6d/+k2eACv9mZT5yr4xzskXlgzrdBCD36hL5KdZSP7IKNIHcHNl
DSW+wenxH1cxlfl5OMfZDkirH/RR1FQnuVJnngBYHPlv3JHuQUqE0ZF70K4hSKYYi3B6t/ldaCNh
WVGOdbM1SO4fwlxXL9M1AmCMX7zOaQi6EkXzzWvmaHmRtYeuvi1xX/byx+rII7a6qdzETqMkvlln
n/2UCz1AFSzQjVka0eJ3b9VVDJDQ4RQhQ15cM9IeCsvqxd2WlQCLXt08AUGfHZWCjHdzmmgkrlG3
e6pKulOVGc5VwSWWbnkxeqXfpzvVQN7XZeOboQn2IuyNvWkdNmqgn0tQhFNeIanvT/GiJ0HmBuMZ
9/65RLl7uMHcKe2Wr12VGmVDyDTNZfN5V4YZwESdWABbU6vztTH7VyNenpCD/ZFUbglx2Dc+7hyo
ljr3KnNPsq0hV/9wB5WoXClZxy1KSu2ofTRwfSQi7+G6AddDAeGKRl+oVQOvWevsUzoKJBpz2q8r
7aJoFF3U0JYvZVVFRRSw3SEVeG3hpUBcAQzJFFqLweGy2vP/FFryOcmCOC89TEVYMm5at/r4uGOY
gxSUhg6RaSAuxyQR+nKXbKjwJ0rA/P9lhNgMIQ8/lqKrWEINcwADetLUHzzwcq5cgnzq9SoKcKkg
PuSoKNIM7Zt2niydQCACx14PEB8696I+r77o8mWc1zwcMxHSk2C0WnQPAJo1iEIS/0WEJfUg+gGh
QXAe8iirvQme7pLOHHOuphtSfEqf6rXqQsFPj1zB16xcixO3lOJAdW6tjrN0/V8vrSlu3M1intJI
lX4cOJxn7cTy3UrPhSRsOxpQHhbofPKNNaQRPOfzImO8p4ldoWiNK9M2S0yUsln/61pJi7aigg1g
hM5OqMT4KwvBucdfSZDGJ8RpHmpHyBniIvzbbKyiumThPmNvL4H/0NbcQwjl4q1lZfeSoiuiW1YN
k2F+vHcbg+Lrmd14d3249JQ6wdOT2DsvRDDPFwhH9jn5K3DdeEVjJAeHoHnV7wAkZ4QvYIlzU8cC
s8wqUyhmDnKdF4nz3/HafVAoKzRxa8vJV9JaNzIpQa6R4PpMfK2xK23PY+dZbtXshrkNfEap5322
O5W+MaLd/jqts9orI2TZOiRAgYw4YYLoXN4GTjhx51xmj+7R7jHGCQqn6LrEVQyhWxPo+0ztK2QB
vEG3/ieXSJZbijN6TpTMQBH0CuL0uQqNBpgJJXPFWzGK87oQo7gkVY/iEfP+j2vhyl7WaagNDc+J
pZByqjDUoxq3/5pG2G4HFj/+wyIaJtre2+kfm7li5yy6yZC9H+q+85Q3ggS+owE4nuyURPbM/J8D
1Mkfer2p67WoF+l+njAuRp6nIde5H50jf+TlnFJ7dj7hXKPDUOIXEQc2KQ23bJNYbzs6/bpCUZLS
/KDNykC3mrPAuwkxnedbELLh5X9PhG+IQo4KBiLAYBLvpkwryx/+c6iWP0MdYwwWdQNlzjUb6zFZ
xtfyu5jynJuSOtUWBYgxnDL8gssrC7aKybNiwVC0iRGgFUtchhb4vCvFcdR63Coqvmn+IpGC1UDj
iDtZYnh/W6U3ZnueY16l0SbsW8B9iEzO6M/jhFmVOkG4tmmaS4IhIJoSJCu7LKYi/JKrnVUTgCS2
iRj9hq57hJie8ty8PgaUYvMtILC9g65OF0+m41kFH4V35QzagJIhWb/BQPSAezL4CPqcVfPjMifT
p6V2xXY3uUPVVAMbyUQTXe2hPWeem0gAVxx0A8OoTMz3oTY9Eg4y+KbM7rccywEmWVGqJU1/BA+5
hvkrvh9NOuCa+pc9W7WgIP4U4cUEgsKPae2Dz8D/izCVCT1Ffv+jwqjnK5wg4N6gEQmqvl9n7ME1
8IVw3qaE2GLoiA0EsN8SqeGDmQ5eOY0unGvarzyaJ9+DqjqMbZYO3bpr7sdB+ZwGKzBfxULPLKWh
qi4XbcaEpsyBC4uVVC4650BIUJ3LtsWoJ6WdHaDGRaiYCAaeTf5cs4tkZlZI7ND6XIT738HnO53P
raCskxAjLHW3pCT+na42X+Nc2zZCJktIjPV9vUvxlKup2OZxbVON8b5ddg20kSM3GCZcOlUjDWD4
hluKs6pY7/hpxVCoIZy1u1UqYeAknkKqlNrT+p7rjw9HfQS19efLUbcDODM4GZwtP1qijVXxVMzj
0dbD3fc/7lyRhY1gV4W/YP+y816lRKLfckhCtFB2ceq375fIds+HRqMQQp+3xGKPt1pgEX15V1ZO
4A409Mdqgn4D3cOSfo1SmgqHcTTT4qgIMT5rVACDk3DaHu8NYTJFWkM0uAm/W6CZyfty1/zirW5S
EBGBWTTk8QpMXaqtIT+SEVYj7PpGt4gCp0+Y1FjhP+JN6FgMKtM3aAjfK8+jn3lrCU9YB7WyFJ8O
pVupNv+2vuMSrmRx7tTcvD0NxtzU7UxQHWOTSRDA6cGh5Va3hdeDLiy9NQsdrF+C3XVnmMZveXak
hJXury9lmwuCsfX2YJcT4WxCshnMnptMoktyMixUIP6KKEn0S74GqhRvlWIbCOrsuR44vaGP9HfD
ylaPsFHGfzIMD30kRu981jBtX1v8bRK1Of9DoL9W4exb8ViaA37nsevcLAcBKeM5LnGAtmdUHkzg
8T7GEblSbuCRxdUxNWNj1LagRugvJ/ELYptjU3NcMVrfeWbsgEop7/6glwofBO5n3BlXe83qe6Uu
zLCt1RHh2XnO7lEF+K80CcufmJfgEgkFvwNIcJpkRHzrSucwXhoWWCseUMZ6pvwVpxpfpj7GLWRN
SO0Ai1D8D0AfWQxzQgoRty5Tx1TttNtufuTxV/TfXuKUWa+rbei7JuBL4gESmEOecV3+ngw0hNE0
2E8SQdT8JJnToRzCf3GQIBXLGmAQiTmhYhHRM7aZmCGe0mVYL/0b7cpQ5PQEObYKxSW0RdMQ3fXE
MGh3IJWIOVl3ANBxsPU+E3U7fVYc28LvTwNCzYeiW4cl4bp53f++fuNiRL+SSrRx5ysAFvor0ats
yma3/Fe4kaTOncKlcpI6vKXrW9MWrdTeJ1H2x0jYO84oIYtnO+hUpaf1HrmMAus03++llgiG+yIJ
3cpG4E+xFDgFs+MWKOL7+khzfpTmhw8x2LSoMnrq3Qjr8FcUKRTt+yJBELuPx/T/h18EK+gQScfT
cxrYLqP0ejDEemLcIjlxWn9DO/WeWw9Nu38d1ndQ44AJ2JcQ2LqbFPkejr8GkpeXaMnu8gZPoTL8
fx4lGaf27SCsX/h170tmL2QmMdVIwL8cfa75dINrKeThC9W5C4kDyrpKkisXL6hRQ9nUDYdILYk0
suWBz4K13fHx1xSQHIr2UslOri8bd06kcq48G7y+nLf+clQfBC0zwIx2dtUBn5aCm5jwlgpV0kRN
scCeSrGEa0QHnFgJLZUu1Y6j5XFP4j1/uAkLoJOmObyfWdTUL0yaBxM4mXcwbbzTPXLJX/AAExc1
WBEsjXGg0WY+usAtXZYXLtpJVzr7COG/ljnHPKTUB6WVgzL3yBR0JN+Y4TSaQHWH6IkMV8YLcg74
sw9b8HdOcw3ZViii0DP/
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
c9vsW5JBCvThyxOUH2PprRXrwDWuKZW/Q7qPv429HnbShw4Uk66yycd+J5tES7AzUCyGeanqADbi
t/NXtBFOdg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
THl1Z3bcMS4H5t6D0G+kJ/FC2Y9oXN8UuO5gTyqyx046tFrVCFbF7b10tz4zI+nryigVgXDuQjpn
REJa68sEKDIsGl5JYzOYVe9IZ30LgoXUIOey68bvuu3Fnu8lEQh/WChcCnbyekJTFEdRaUW6S2O+
5xce7Ha8Gv7YClnhp04=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
KL9gEW9UR9bJ2V+rRImGqHBVYgwBOrGPetNJZ9L5EOgu04h1LECL47Zq26De2Obbv4OkIEGfGFbZ
muWpwFGMSP/qDDeS04mLx/tWX4SnYgQRVyk8AGGlepDKbn1R0w9YaYChqwaqdh3fMk+xJZbtgoWp
4ejGlCOtRuSFxFcOTPGLnPLr5saG0n7SH0iOlkdKRcxP8k1FnXr8kYqxu6g0r1ZNWNYlDcRB7pBC
lrlL52/HTgYUGboGp0/wpS3BU8yKiMyKpm/Nc0Q701u3QL3zraihgQqtTSzkLZnBFXKNrCd6K2Zb
gw1krcKarckcDY4W+Jw/vlWaBMsrX/8GffFxsQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
I9+ICDzIgzYMfdI9n5+7cSfa+M9K8Q9HlZVHvp38kWsb+jUXV67Oh07GXgNqpn7RlOPdQSyhyXf6
AZH+fL8ycTHV0MoCLtaJieiw5P4E1Pm7Fdq2uCENFjt8u7I2RH9/lcoRh4KurkxCVCe86Dtk1oWB
bacFgZX+QZ+FCZn+6nI=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
pyasIdA/E1o2abIoUkxhLYQwvp5B9zIwQEm/+EGPR3u06a5SPM2I1E62WIwSJ7iN/bqdRmd03/xZ
zjSCCiFFaRUwQmJJ5xZcUnw15IQqIRd/WQQ56gktCUx2rEJwJ4BBJrhOQsbLLnEDNgJUxpYVfXAy
ix6G1h7tonYt5pC9K8hh3YN8608V5TRujBAEsLi+3lAMFCMgjGqgS6cpljhaHIjuKULPnRb7+Rll
fIJqbRqDAQ0ubxbSrdH7w8ZIqWH5mG/hnLBefDFlIZJh/pHjOIOLGPh9RyUn99n5SKT8NF75l8Mj
ggHTuLkcPsoN2kGMWMDxZ752vU2X39SpzveZtA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6000)
`protect data_block
TxmWdQtoCa72lA+PjmaVWNzez4mZxpW7I8VWfPbcGicMeEL2MwwAS4LUnoxwA9Uhmm5ot+LUjCmv
eDB7SAvMi2HMKnvkVOM6GyDSV3gAIeNsWXHPVpwGySt8l+veQ87+wCB2U0M2AjDDPy5G0YrHv7SV
3hwskYbNG5I35qHpm3MFyP0vEDTw2Fa861T3JSQElQvkHyiJtc1mCK8c+3Xwu2sX2tdUav9HJ/w9
ZeB6TCc1chmVdFw//m3On54B7bmWN9Zebwnw5VQGvAYNMLyudEgVjYJwsgwTfKt7pZ93DMozPsEb
mZW50l08EWStM63eu5CZx2XBarUhqb053q94CYABjIYCo57BhlAgWgkKSS2f5WQW0T4Jc3rrfKN3
sLKdFCmMZrqfr5pgPkkX+nvfqUlvDaNXr1tYdehUiUwQuHo0YktKmaf9b7G08xq2O+KihhDW8bJL
JxvKd5VOwLu5iT8eD4v22BpAwoc1xjn98yzfCmkC27huSSupAOcJw+AP5OFOkoRBWp079P45WQOz
o/hkgLdSsXaQUNYZhi2sEsKzRYQK+hrxajBLt5oHEBJbf7wIUiygAcdixuv12Dd/r5+WcBPm4SJO
EmUMYhUA15hnaNALn0dGvrSkIP5NslL6zWERTi9G/OFbUb1a799ztM/HsHegshJwRbCxHi2xIz16
z35IEn7CVUoWVCtQlpFDFlgUxi9BshVVTf/6EayE6uFNg6KX4HhvSmuwujoT0wRmbQZ3Ia7MGLGS
uyxfc7BJHDjz5MQ3coKQd51qJqfHTeRGTAeQ9SzqASPY8ebTFMlp1vqFRPbOq6KsrHx7WT75pRyg
8foHSrwUrb/E8FbwnLnYe9umPzKEjGCTo6eXMWpVIyglksrRWrHIM0OOlju1rUPs5g8RID/+aWQl
krguToDL3/FbiBN/OpIpzzDFYSMSIhrq7W2k0D6X90tLdM86lV4BCaIna6MHSucetYvc6zrnoGID
ZdXRDktS64+FUnZpecuBvQtan+SwG5Rvqymh0vB5LWrSR34biGzmqqTBL6p0TkGzPJUxr3lqAthc
KMtK1x/EDuNMioKMJR1MutrwOckHFMTYiwMKhxvYePPfxHJAgRzDfDBKJ9KWfOFooBxhHPeirSD7
ApSD9kcvPzrCWtqheCAAtKvcZP69vAN+sPL4o8f8ZwS4u3neFS/PPgIEyPAjOT3Rx+hphXuRbR0C
xcg9NF/xUbIz1a0O81Hw+8USWdyB4CQVxN5TGWS0eU0Pzoempf3cbN/Umb4Z+G4nc6TVnd8Gzb/m
jLUUtvYTa++9REXif4S6B/jCByLNDOxPQ28fB9svsp0vyMkxtzExcTVuuXpp4sLmoIH0UguSwDrE
x5YlFE3mWIf1OcehV2K2ErmJpe/bx8/yRbJ+kETpRKlv8D6XTVRQt+Vea+z/vp51qlFOXkOir/4z
HbT597Zit9GKjTATbsheBAZFsu2OizevmfFZYM2WDfnnUnMamAUqxaKqV8sBjWCkxt7aOfu6RZRK
yRL7SOf4zEEAFHMuE+GPm0rxk/sCx2m26oOMj8DaX8AQ/3s2oNdxQ2ddf9myEgQlGerb+eAV5o1a
5LqAFtKIk9Wa2pAmhmbxUpfE38EhmUl+234E/YoxdQLzujssw+CNBvGu8kay1h0rWYV33KjltIfQ
e7KSp27ixG50GEf69G4xAL3n1v6tR1ouThly320lFyJ3Wssf2xL8OdqYZSoLvRF/z5Km2UbN8C+7
b8ffHHM55SASUZgCBIzBG1crH+eNXgiO9efb0rlBQrssgT/gml39YobX1TcOcgos3QpPzFpHw6m7
nZtdH/d+GpWJzbnPCAuEPyDwb4nftuTZZeEacP2zZPvGGROsylXzm+/InIrEx2Ja3Pe03gKZ7kZI
MEAhq8wwkZ0DVk2WDBZxVi/MP0Bbu1xA2CYb9Q2ylABgnzj8gdvoi/JbROGOoF0aSyDWizHV76E4
w1W5PxM9E8680QSTHrxcNxNz0ZO0XGkV3wokatX/5drWMmp+l8vRqoY0zc5+XDjdNgmbt4Aet9cU
9c6Gu3Dz7tgMbXBJsu4EmdbZSNKQLto9ZAd1zOPonSwPo6bwiU+LqjOV94wy+eH4/jYjYrwJiHDM
HyNwJuLi+ht2lBMKmwj6gZG9yecfGBvmcchYOpnyXKAHrE4iJyQuqiqRgL8TOGuMS/BWEZoUV1xT
i+vQiLWtToNOm5bAPioM2s+TcGjzptmZQsmk/bK0sVLLcyXBBxlTMsYnpOl8TnUXNiBNSlg7yoDO
UFvNugB1iR9yTD4Qy+bX5OT2j0OaP1aSMr9OK3fYCxIfl9oUrqQAz1fRc7UOniKSxDClSdhrt/g3
2w+S2xLd1sPkJLh1Z042bk/BdmJgWwfvjpSdD9cA2H0bd9l6f1JmA+XOCcVm8aiqBP+AncvFZkNi
zTCIrFbLsPiUkIMQ8aGtWpFmxbJ/TFaR5RavOE77XkqCyfjvAS1CkGEmQPu45C3KNLMljHvoTGoM
K0WpaO6nYpRhoTp3pB/GFYZH7IyrzaWSCWGVDfmwl8kwuw077+RrBKytLdEvirocgA0XXTckkOP2
YlEVy4zWwy4ozYDcU3sZItQzhUk+XUAtuRyMYQaD+kMmv3R18LAiwcGKLZW5sHBT11dPSGdWpJPQ
JUoI6scMIZZkhWcAd6RdfSUidOpWtiNkDD3wRwbkGsFBwFVW3fXckKO7AQMpCwqeAZq7xzyIDvYO
wNsir/tIa51q0hqSvHP2aaht0TF52ZHQAl11hXQfGtlSMcfrCP3EXGW7Dyrjtk0bPO+U5jyHiztH
b6HKhOdFZarKHPuzQpOYGb4fVlcRAYz4ujhTcfBZOB50NCcympkfCerHKuQkjR7CtJCU/FuOJWqA
LJhIn6vd5ZBZsZKQZfz/Vfi4D8HtvIAg7efEMwCF4sZoWND5Q8XUITLBQ1vm38m7jGV5WooUzmA/
YYHZ5gNMKTNI2rjx6dOapKVN2kwpUgmnqIEw6NLjCZDHmJuvFzqFI6E12fndcObS1LF/VMSrKmhD
F0RLzCARmlpQ8YQaGv3aF/i+jmYcVLvf353fL9w1QVKn+8/5CDSVzjE423D4nIBfbngJneJS3+2z
duSI7FHGEzdj93raYGcZe43fEhZ1dIF9H50A84Rix/gVFWv3NhB/Tcjk2f8AmFp/M47dxGIRkmOX
EQj3EEWq0HXDR1iUyf6YMizK70jMfZ1r6iOGMZYy4g93/e3FBklX7CleETlXaDWS7BC243ka5P7M
jhlhSxTflKC6x9toDQDhWVTQOhN24qUSYugdEru8c0ju8NYZvhRSYvCgnPo5M6tq9hAZ+zBFGOgR
wA3czXQUG4Liq0Gt+Npgd9LUYwhQFo8ahyVu35826rbZybwbX3HGwBadXf5m+yGOmAKPzhu7h96x
FoFUeJKhCU6hlBeCj9IPG9Q+DiRvBBrlgGi/SsjEP5HYTGXP3XLdza4E5gaOqj1PBR/8S6e+NLA7
rQx4Omz8BVG+qVbNVkQpCN+ozDK4WK49yuLCyMWLl6SbOC05dZziMPbSP4IULW9bK/o/Sac8rZtn
QbhQojrvXv7qj6bzy9mUuWQHF8m0ZR9T2hqwAx0vVEpoWU2qRpp30md7+/4WU6ddq0mn3zNwdAa6
nhI/Qrga2D7peVuYaFKYg+iC9soZccRmUDVi5AepG8+oGRAEmvIadnS2Orz7J9PcDEaP7/wHqnkT
E4+0+OKo50zH7D9FmjY0+zhOkinkAmoxLI3koQz1AFVoYB3Oc4FJQ1mAjBn5RDxciAall4tcHmph
AHjIjF6/npOI9rqg9Kv3SYDhY8CgNSqexhQSyxe8FRwDncSGYRq9pdL/EepWjjkbvyAfAN296S3M
KggAEB+SdNHvqqstJFzRBc1LY8WkE8ouoHbxa97vRXY+hopaCl37NXjHDseFr9iZruDOXtGtPs5l
//oZT0Gd8qEzmegeShrQFplZCdGwtEHjMVaZOFcaoEri1SYCzZS8vFWuZ31NrfAzbR8yi/zay0qG
DgZ2iLXuVJWE0DwQ5GnozJl06xnXQiEnUhF3Av/XcnvLLupy3IwVDjcpAXsPQNpYgaNm8ZHiukYt
TjNlQxroJDKZKrBQTC7aTDeyTNAdBJfWQ1NWqryxz/tVKNHdHKNjdT5ubWF+moI/KkSkIv0mRI+f
4KJEL5pr3wdRXTuAhP+2qqEHmYoYNjfFikVfcZjHOeFwunZuIlbYHqaAR1zrI6D60OK/DHl6GzRO
7lhOolznbM00mA8FGOjesVn4WR79qgO7a6W78gkt4OJ5ukjp+CiX8uTm/NA//4Ep7QF6JdB9q0aS
7uYdsBb0qpSMfUiT/Ukq/OEbLHBCcTRq+9KqtZA10v0RytoU1K/qdfOhsgSwj89iQAYCmYHreNnH
Pk7yD1F+7ZAhRvP8GMu/DGcDO6d/+k2eACv9mZT5yr4xzskXlgzrdBCD36hL5KdZSP7IKNIHcHNl
DSW+wenxH1cxlfl5OMfZDkirH/RR1FQnuVJnngBYHPlv3JHuQUqE0ZF70K4hSKYYi3B6t/ldaCNh
WVGOdbM1SO4fwlxXL9M1AmCMX7zOaQi6EkXzzWvmaHmRtYeuvi1xX/byx+rII7a6qdzETqMkvlln
n/2UCz1AFSzQjVka0eJ3b9VVDJDQ4RQhQ15cM9IeCsvqxd2WlQCLXt08AUGfHZWCjHdzmmgkrlG3
e6pKulOVGc5VwSWWbnkxeqXfpzvVQN7XZeOboQn2IuyNvWkdNmqgn0tQhFNeIanvT/GiJ0HmBuMZ
9/65RLl7uMHcKe2Wr12VGmVDyDTNZfN5V4YZwESdWABbU6vztTH7VyNenpCD/ZFUbglx2Dc+7hyo
ljr3KnNPsq0hV/9wB5WoXClZxy1KSu2ofTRwfSQi7+G6AddDAeGKRl+oVQOvWevsUzoKJBpz2q8r
7aJoFF3U0JYvZVVFRRSw3SEVeG3hpUBcAQzJFFqLweGy2vP/FFryOcmCOC89TEVYMm5at/r4uGOY
gxSUhg6RaSAuxyQR+nKXbKjwJ0rA/P9lhNgMIQ8/lqKrWEINcwADetLUHzzwcq5cgnzq9SoKcKkg
PuSoKNIM7Zt2niydQCACx14PEB8696I+r77o8mWc1zwcMxHSk2C0WnQPAJo1iEIS/0WEJfUg+gGh
QXAe8iirvQme7pLOHHOuphtSfEqf6rXqQsFPj1zB16xcixO3lOJAdW6tjrN0/V8vrSlu3M1intJI
lX4cOJxn7cTy3UrPhSRsOxpQHhbofPKNNaQRPOfzImO8p4ldoWiNK9M2S0yUsln/61pJi7aigg1g
hM5OqMT4KwvBucdfSZDGJ8RpHmpHyBniIvzbbKyiumThPmNvL4H/0NbcQwjl4q1lZfeSoiuiW1YN
k2F+vHcbg+Lrmd14d3249JQ6wdOT2DsvRDDPFwhH9jn5K3DdeEVjJAeHoHnV7wAkZ4QvYIlzU8cC
s8wqUyhmDnKdF4nz3/HafVAoKzRxa8vJV9JaNzIpQa6R4PpMfK2xK23PY+dZbtXshrkNfEap5322
O5W+MaLd/jqts9orI2TZOiRAgYw4YYLoXN4GTjhx51xmj+7R7jHGCQqn6LrEVQyhWxPo+0ztK2QB
vEG3/ieXSJZbijN6TpTMQBH0CuL0uQqNBpgJJXPFWzGK87oQo7gkVY/iEfP+j2vhyl7WaagNDc+J
pZByqjDUoxq3/5pG2G4HFj/+wyIaJtre2+kfm7li5yy6yZC9H+q+85Q3ggS+owE4nuyURPbM/J8D
1Mkfer2p67WoF+l+njAuRp6nIde5H50jf+TlnFJ7dj7hXKPDUOIXEQc2KQ23bJNYbzs6/bpCUZLS
/KDNykC3mrPAuwkxnedbELLh5X9PhG+IQo4KBiLAYBLvpkwryx/+c6iWP0MdYwwWdQNlzjUb6zFZ
xtfyu5jynJuSOtUWBYgxnDL8gssrC7aKybNiwVC0iRGgFUtchhb4vCvFcdR63Coqvmn+IpGC1UDj
iDtZYnh/W6U3ZnueY16l0SbsW8B9iEzO6M/jhFmVOkG4tmmaS4IhIJoSJCu7LKYi/JKrnVUTgCS2
iRj9hq57hJie8ty8PgaUYvMtILC9g65OF0+m41kFH4V35QzagJIhWb/BQPSAezL4CPqcVfPjMifT
p6V2xXY3uUPVVAMbyUQTXe2hPWeem0gAVxx0A8OoTMz3oTY9Eg4y+KbM7rccywEmWVGqJU1/BA+5
hvkrvh9NOuCa+pc9W7WgIP4U4cUEgsKPae2Dz8D/izCVCT1Ffv+jwqjnK5wg4N6gEQmqvl9n7ME1
8IVw3qaE2GLoiA0EsN8SqeGDmQ5eOY0unGvarzyaJ9+DqjqMbZYO3bpr7sdB+ZwGKzBfxULPLKWh
qi4XbcaEpsyBC4uVVC4650BIUJ3LtsWoJ6WdHaDGRaiYCAaeTf5cs4tkZlZI7ND6XIT738HnO53P
raCskxAjLHW3pCT+na42X+Nc2zZCJktIjPV9vUvxlKup2OZxbVON8b5ddg20kSM3GCZcOlUjDWD4
hluKs6pY7/hpxVCoIZy1u1UqYeAknkKqlNrT+p7rjw9HfQS19efLUbcDODM4GZwtP1qijVXxVMzj
0dbD3fc/7lyRhY1gV4W/YP+y816lRKLfckhCtFB2ceq375fIds+HRqMQQp+3xGKPt1pgEX15V1ZO
4A409Mdqgn4D3cOSfo1SmgqHcTTT4qgIMT5rVACDk3DaHu8NYTJFWkM0uAm/W6CZyfty1/zirW5S
EBGBWTTk8QpMXaqtIT+SEVYj7PpGt4gCp0+Y1FjhP+JN6FgMKtM3aAjfK8+jn3lrCU9YB7WyFJ8O
pVupNv+2vuMSrmRx7tTcvD0NxtzU7UxQHWOTSRDA6cGh5Va3hdeDLiy9NQsdrF+C3XVnmMZveXak
hJXury9lmwuCsfX2YJcT4WxCshnMnptMoktyMixUIP6KKEn0S74GqhRvlWIbCOrsuR44vaGP9HfD
ylaPsFHGfzIMD30kRu981jBtX1v8bRK1Of9DoL9W4exb8ViaA37nsevcLAcBKeM5LnGAtmdUHkzg
8T7GEblSbuCRxdUxNWNj1LagRugvJ/ELYptjU3NcMVrfeWbsgEop7/6glwofBO5n3BlXe83qe6Uu
zLCt1RHh2XnO7lEF+K80CcufmJfgEgkFvwNIcJpkRHzrSucwXhoWWCseUMZ6pvwVpxpfpj7GLWRN
SO0Ai1D8D0AfWQxzQgoRty5Tx1TttNtufuTxV/TfXuKUWa+rbei7JuBL4gESmEOecV3+ngw0hNE0
2E8SQdT8JJnToRzCf3GQIBXLGmAQiTmhYhHRM7aZmCGe0mVYL/0b7cpQ5PQEObYKxSW0RdMQ3fXE
MGh3IJWIOVl3ANBxsPU+E3U7fVYc28LvTwNCzYeiW4cl4bp53f++fuNiRL+SSrRx5ysAFvor0ats
yma3/Fe4kaTOncKlcpI6vKXrW9MWrdTeJ1H2x0jYO84oIYtnO+hUpaf1HrmMAus03++llgiG+yIJ
3cpG4E+xFDgFs+MWKOL7+khzfpTmhw8x2LSoMnrq3Qjr8FcUKRTt+yJBELuPx/T/h18EK+gQScfT
cxrYLqP0ejDEemLcIjlxWn9DO/WeWw9Nu38d1ndQ44AJ2JcQ2LqbFPkejr8GkpeXaMnu8gZPoTL8
fx4lGaf27SCsX/h170tmL2QmMdVIwL8cfa75dINrKeThC9W5C4kDyrpKkisXL6hRQ9nUDYdILYk0
suWBz4K13fHx1xSQHIr2UslOri8bd06kcq48G7y+nLf+clQfBC0zwIx2dtUBn5aCm5jwlgpV0kRN
scCeSrGEa0QHnFgJLZUu1Y6j5XFP4j1/uAkLoJOmObyfWdTUL0yaBxM4mXcwbbzTPXLJX/AAExc1
WBEsjXGg0WY+usAtXZYXLtpJVzr7COG/ljnHPKTUB6WVgzL3yBR0JN+Y4TSaQHWH6IkMV8YLcg74
sw9b8HdOcw3ZViii0DP/
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
c9vsW5JBCvThyxOUH2PprRXrwDWuKZW/Q7qPv429HnbShw4Uk66yycd+J5tES7AzUCyGeanqADbi
t/NXtBFOdg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
THl1Z3bcMS4H5t6D0G+kJ/FC2Y9oXN8UuO5gTyqyx046tFrVCFbF7b10tz4zI+nryigVgXDuQjpn
REJa68sEKDIsGl5JYzOYVe9IZ30LgoXUIOey68bvuu3Fnu8lEQh/WChcCnbyekJTFEdRaUW6S2O+
5xce7Ha8Gv7YClnhp04=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
KL9gEW9UR9bJ2V+rRImGqHBVYgwBOrGPetNJZ9L5EOgu04h1LECL47Zq26De2Obbv4OkIEGfGFbZ
muWpwFGMSP/qDDeS04mLx/tWX4SnYgQRVyk8AGGlepDKbn1R0w9YaYChqwaqdh3fMk+xJZbtgoWp
4ejGlCOtRuSFxFcOTPGLnPLr5saG0n7SH0iOlkdKRcxP8k1FnXr8kYqxu6g0r1ZNWNYlDcRB7pBC
lrlL52/HTgYUGboGp0/wpS3BU8yKiMyKpm/Nc0Q701u3QL3zraihgQqtTSzkLZnBFXKNrCd6K2Zb
gw1krcKarckcDY4W+Jw/vlWaBMsrX/8GffFxsQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
I9+ICDzIgzYMfdI9n5+7cSfa+M9K8Q9HlZVHvp38kWsb+jUXV67Oh07GXgNqpn7RlOPdQSyhyXf6
AZH+fL8ycTHV0MoCLtaJieiw5P4E1Pm7Fdq2uCENFjt8u7I2RH9/lcoRh4KurkxCVCe86Dtk1oWB
bacFgZX+QZ+FCZn+6nI=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
pyasIdA/E1o2abIoUkxhLYQwvp5B9zIwQEm/+EGPR3u06a5SPM2I1E62WIwSJ7iN/bqdRmd03/xZ
zjSCCiFFaRUwQmJJ5xZcUnw15IQqIRd/WQQ56gktCUx2rEJwJ4BBJrhOQsbLLnEDNgJUxpYVfXAy
ix6G1h7tonYt5pC9K8hh3YN8608V5TRujBAEsLi+3lAMFCMgjGqgS6cpljhaHIjuKULPnRb7+Rll
fIJqbRqDAQ0ubxbSrdH7w8ZIqWH5mG/hnLBefDFlIZJh/pHjOIOLGPh9RyUn99n5SKT8NF75l8Mj
ggHTuLkcPsoN2kGMWMDxZ752vU2X39SpzveZtA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6000)
`protect data_block
TxmWdQtoCa72lA+PjmaVWNzez4mZxpW7I8VWfPbcGicMeEL2MwwAS4LUnoxwA9Uhmm5ot+LUjCmv
eDB7SAvMi2HMKnvkVOM6GyDSV3gAIeNsWXHPVpwGySt8l+veQ87+wCB2U0M2AjDDPy5G0YrHv7SV
3hwskYbNG5I35qHpm3MFyP0vEDTw2Fa861T3JSQElQvkHyiJtc1mCK8c+3Xwu2sX2tdUav9HJ/w9
ZeB6TCc1chmVdFw//m3On54B7bmWN9Zebwnw5VQGvAYNMLyudEgVjYJwsgwTfKt7pZ93DMozPsEb
mZW50l08EWStM63eu5CZx2XBarUhqb053q94CYABjIYCo57BhlAgWgkKSS2f5WQW0T4Jc3rrfKN3
sLKdFCmMZrqfr5pgPkkX+nvfqUlvDaNXr1tYdehUiUwQuHo0YktKmaf9b7G08xq2O+KihhDW8bJL
JxvKd5VOwLu5iT8eD4v22BpAwoc1xjn98yzfCmkC27huSSupAOcJw+AP5OFOkoRBWp079P45WQOz
o/hkgLdSsXaQUNYZhi2sEsKzRYQK+hrxajBLt5oHEBJbf7wIUiygAcdixuv12Dd/r5+WcBPm4SJO
EmUMYhUA15hnaNALn0dGvrSkIP5NslL6zWERTi9G/OFbUb1a799ztM/HsHegshJwRbCxHi2xIz16
z35IEn7CVUoWVCtQlpFDFlgUxi9BshVVTf/6EayE6uFNg6KX4HhvSmuwujoT0wRmbQZ3Ia7MGLGS
uyxfc7BJHDjz5MQ3coKQd51qJqfHTeRGTAeQ9SzqASPY8ebTFMlp1vqFRPbOq6KsrHx7WT75pRyg
8foHSrwUrb/E8FbwnLnYe9umPzKEjGCTo6eXMWpVIyglksrRWrHIM0OOlju1rUPs5g8RID/+aWQl
krguToDL3/FbiBN/OpIpzzDFYSMSIhrq7W2k0D6X90tLdM86lV4BCaIna6MHSucetYvc6zrnoGID
ZdXRDktS64+FUnZpecuBvQtan+SwG5Rvqymh0vB5LWrSR34biGzmqqTBL6p0TkGzPJUxr3lqAthc
KMtK1x/EDuNMioKMJR1MutrwOckHFMTYiwMKhxvYePPfxHJAgRzDfDBKJ9KWfOFooBxhHPeirSD7
ApSD9kcvPzrCWtqheCAAtKvcZP69vAN+sPL4o8f8ZwS4u3neFS/PPgIEyPAjOT3Rx+hphXuRbR0C
xcg9NF/xUbIz1a0O81Hw+8USWdyB4CQVxN5TGWS0eU0Pzoempf3cbN/Umb4Z+G4nc6TVnd8Gzb/m
jLUUtvYTa++9REXif4S6B/jCByLNDOxPQ28fB9svsp0vyMkxtzExcTVuuXpp4sLmoIH0UguSwDrE
x5YlFE3mWIf1OcehV2K2ErmJpe/bx8/yRbJ+kETpRKlv8D6XTVRQt+Vea+z/vp51qlFOXkOir/4z
HbT597Zit9GKjTATbsheBAZFsu2OizevmfFZYM2WDfnnUnMamAUqxaKqV8sBjWCkxt7aOfu6RZRK
yRL7SOf4zEEAFHMuE+GPm0rxk/sCx2m26oOMj8DaX8AQ/3s2oNdxQ2ddf9myEgQlGerb+eAV5o1a
5LqAFtKIk9Wa2pAmhmbxUpfE38EhmUl+234E/YoxdQLzujssw+CNBvGu8kay1h0rWYV33KjltIfQ
e7KSp27ixG50GEf69G4xAL3n1v6tR1ouThly320lFyJ3Wssf2xL8OdqYZSoLvRF/z5Km2UbN8C+7
b8ffHHM55SASUZgCBIzBG1crH+eNXgiO9efb0rlBQrssgT/gml39YobX1TcOcgos3QpPzFpHw6m7
nZtdH/d+GpWJzbnPCAuEPyDwb4nftuTZZeEacP2zZPvGGROsylXzm+/InIrEx2Ja3Pe03gKZ7kZI
MEAhq8wwkZ0DVk2WDBZxVi/MP0Bbu1xA2CYb9Q2ylABgnzj8gdvoi/JbROGOoF0aSyDWizHV76E4
w1W5PxM9E8680QSTHrxcNxNz0ZO0XGkV3wokatX/5drWMmp+l8vRqoY0zc5+XDjdNgmbt4Aet9cU
9c6Gu3Dz7tgMbXBJsu4EmdbZSNKQLto9ZAd1zOPonSwPo6bwiU+LqjOV94wy+eH4/jYjYrwJiHDM
HyNwJuLi+ht2lBMKmwj6gZG9yecfGBvmcchYOpnyXKAHrE4iJyQuqiqRgL8TOGuMS/BWEZoUV1xT
i+vQiLWtToNOm5bAPioM2s+TcGjzptmZQsmk/bK0sVLLcyXBBxlTMsYnpOl8TnUXNiBNSlg7yoDO
UFvNugB1iR9yTD4Qy+bX5OT2j0OaP1aSMr9OK3fYCxIfl9oUrqQAz1fRc7UOniKSxDClSdhrt/g3
2w+S2xLd1sPkJLh1Z042bk/BdmJgWwfvjpSdD9cA2H0bd9l6f1JmA+XOCcVm8aiqBP+AncvFZkNi
zTCIrFbLsPiUkIMQ8aGtWpFmxbJ/TFaR5RavOE77XkqCyfjvAS1CkGEmQPu45C3KNLMljHvoTGoM
K0WpaO6nYpRhoTp3pB/GFYZH7IyrzaWSCWGVDfmwl8kwuw077+RrBKytLdEvirocgA0XXTckkOP2
YlEVy4zWwy4ozYDcU3sZItQzhUk+XUAtuRyMYQaD+kMmv3R18LAiwcGKLZW5sHBT11dPSGdWpJPQ
JUoI6scMIZZkhWcAd6RdfSUidOpWtiNkDD3wRwbkGsFBwFVW3fXckKO7AQMpCwqeAZq7xzyIDvYO
wNsir/tIa51q0hqSvHP2aaht0TF52ZHQAl11hXQfGtlSMcfrCP3EXGW7Dyrjtk0bPO+U5jyHiztH
b6HKhOdFZarKHPuzQpOYGb4fVlcRAYz4ujhTcfBZOB50NCcympkfCerHKuQkjR7CtJCU/FuOJWqA
LJhIn6vd5ZBZsZKQZfz/Vfi4D8HtvIAg7efEMwCF4sZoWND5Q8XUITLBQ1vm38m7jGV5WooUzmA/
YYHZ5gNMKTNI2rjx6dOapKVN2kwpUgmnqIEw6NLjCZDHmJuvFzqFI6E12fndcObS1LF/VMSrKmhD
F0RLzCARmlpQ8YQaGv3aF/i+jmYcVLvf353fL9w1QVKn+8/5CDSVzjE423D4nIBfbngJneJS3+2z
duSI7FHGEzdj93raYGcZe43fEhZ1dIF9H50A84Rix/gVFWv3NhB/Tcjk2f8AmFp/M47dxGIRkmOX
EQj3EEWq0HXDR1iUyf6YMizK70jMfZ1r6iOGMZYy4g93/e3FBklX7CleETlXaDWS7BC243ka5P7M
jhlhSxTflKC6x9toDQDhWVTQOhN24qUSYugdEru8c0ju8NYZvhRSYvCgnPo5M6tq9hAZ+zBFGOgR
wA3czXQUG4Liq0Gt+Npgd9LUYwhQFo8ahyVu35826rbZybwbX3HGwBadXf5m+yGOmAKPzhu7h96x
FoFUeJKhCU6hlBeCj9IPG9Q+DiRvBBrlgGi/SsjEP5HYTGXP3XLdza4E5gaOqj1PBR/8S6e+NLA7
rQx4Omz8BVG+qVbNVkQpCN+ozDK4WK49yuLCyMWLl6SbOC05dZziMPbSP4IULW9bK/o/Sac8rZtn
QbhQojrvXv7qj6bzy9mUuWQHF8m0ZR9T2hqwAx0vVEpoWU2qRpp30md7+/4WU6ddq0mn3zNwdAa6
nhI/Qrga2D7peVuYaFKYg+iC9soZccRmUDVi5AepG8+oGRAEmvIadnS2Orz7J9PcDEaP7/wHqnkT
E4+0+OKo50zH7D9FmjY0+zhOkinkAmoxLI3koQz1AFVoYB3Oc4FJQ1mAjBn5RDxciAall4tcHmph
AHjIjF6/npOI9rqg9Kv3SYDhY8CgNSqexhQSyxe8FRwDncSGYRq9pdL/EepWjjkbvyAfAN296S3M
KggAEB+SdNHvqqstJFzRBc1LY8WkE8ouoHbxa97vRXY+hopaCl37NXjHDseFr9iZruDOXtGtPs5l
//oZT0Gd8qEzmegeShrQFplZCdGwtEHjMVaZOFcaoEri1SYCzZS8vFWuZ31NrfAzbR8yi/zay0qG
DgZ2iLXuVJWE0DwQ5GnozJl06xnXQiEnUhF3Av/XcnvLLupy3IwVDjcpAXsPQNpYgaNm8ZHiukYt
TjNlQxroJDKZKrBQTC7aTDeyTNAdBJfWQ1NWqryxz/tVKNHdHKNjdT5ubWF+moI/KkSkIv0mRI+f
4KJEL5pr3wdRXTuAhP+2qqEHmYoYNjfFikVfcZjHOeFwunZuIlbYHqaAR1zrI6D60OK/DHl6GzRO
7lhOolznbM00mA8FGOjesVn4WR79qgO7a6W78gkt4OJ5ukjp+CiX8uTm/NA//4Ep7QF6JdB9q0aS
7uYdsBb0qpSMfUiT/Ukq/OEbLHBCcTRq+9KqtZA10v0RytoU1K/qdfOhsgSwj89iQAYCmYHreNnH
Pk7yD1F+7ZAhRvP8GMu/DGcDO6d/+k2eACv9mZT5yr4xzskXlgzrdBCD36hL5KdZSP7IKNIHcHNl
DSW+wenxH1cxlfl5OMfZDkirH/RR1FQnuVJnngBYHPlv3JHuQUqE0ZF70K4hSKYYi3B6t/ldaCNh
WVGOdbM1SO4fwlxXL9M1AmCMX7zOaQi6EkXzzWvmaHmRtYeuvi1xX/byx+rII7a6qdzETqMkvlln
n/2UCz1AFSzQjVka0eJ3b9VVDJDQ4RQhQ15cM9IeCsvqxd2WlQCLXt08AUGfHZWCjHdzmmgkrlG3
e6pKulOVGc5VwSWWbnkxeqXfpzvVQN7XZeOboQn2IuyNvWkdNmqgn0tQhFNeIanvT/GiJ0HmBuMZ
9/65RLl7uMHcKe2Wr12VGmVDyDTNZfN5V4YZwESdWABbU6vztTH7VyNenpCD/ZFUbglx2Dc+7hyo
ljr3KnNPsq0hV/9wB5WoXClZxy1KSu2ofTRwfSQi7+G6AddDAeGKRl+oVQOvWevsUzoKJBpz2q8r
7aJoFF3U0JYvZVVFRRSw3SEVeG3hpUBcAQzJFFqLweGy2vP/FFryOcmCOC89TEVYMm5at/r4uGOY
gxSUhg6RaSAuxyQR+nKXbKjwJ0rA/P9lhNgMIQ8/lqKrWEINcwADetLUHzzwcq5cgnzq9SoKcKkg
PuSoKNIM7Zt2niydQCACx14PEB8696I+r77o8mWc1zwcMxHSk2C0WnQPAJo1iEIS/0WEJfUg+gGh
QXAe8iirvQme7pLOHHOuphtSfEqf6rXqQsFPj1zB16xcixO3lOJAdW6tjrN0/V8vrSlu3M1intJI
lX4cOJxn7cTy3UrPhSRsOxpQHhbofPKNNaQRPOfzImO8p4ldoWiNK9M2S0yUsln/61pJi7aigg1g
hM5OqMT4KwvBucdfSZDGJ8RpHmpHyBniIvzbbKyiumThPmNvL4H/0NbcQwjl4q1lZfeSoiuiW1YN
k2F+vHcbg+Lrmd14d3249JQ6wdOT2DsvRDDPFwhH9jn5K3DdeEVjJAeHoHnV7wAkZ4QvYIlzU8cC
s8wqUyhmDnKdF4nz3/HafVAoKzRxa8vJV9JaNzIpQa6R4PpMfK2xK23PY+dZbtXshrkNfEap5322
O5W+MaLd/jqts9orI2TZOiRAgYw4YYLoXN4GTjhx51xmj+7R7jHGCQqn6LrEVQyhWxPo+0ztK2QB
vEG3/ieXSJZbijN6TpTMQBH0CuL0uQqNBpgJJXPFWzGK87oQo7gkVY/iEfP+j2vhyl7WaagNDc+J
pZByqjDUoxq3/5pG2G4HFj/+wyIaJtre2+kfm7li5yy6yZC9H+q+85Q3ggS+owE4nuyURPbM/J8D
1Mkfer2p67WoF+l+njAuRp6nIde5H50jf+TlnFJ7dj7hXKPDUOIXEQc2KQ23bJNYbzs6/bpCUZLS
/KDNykC3mrPAuwkxnedbELLh5X9PhG+IQo4KBiLAYBLvpkwryx/+c6iWP0MdYwwWdQNlzjUb6zFZ
xtfyu5jynJuSOtUWBYgxnDL8gssrC7aKybNiwVC0iRGgFUtchhb4vCvFcdR63Coqvmn+IpGC1UDj
iDtZYnh/W6U3ZnueY16l0SbsW8B9iEzO6M/jhFmVOkG4tmmaS4IhIJoSJCu7LKYi/JKrnVUTgCS2
iRj9hq57hJie8ty8PgaUYvMtILC9g65OF0+m41kFH4V35QzagJIhWb/BQPSAezL4CPqcVfPjMifT
p6V2xXY3uUPVVAMbyUQTXe2hPWeem0gAVxx0A8OoTMz3oTY9Eg4y+KbM7rccywEmWVGqJU1/BA+5
hvkrvh9NOuCa+pc9W7WgIP4U4cUEgsKPae2Dz8D/izCVCT1Ffv+jwqjnK5wg4N6gEQmqvl9n7ME1
8IVw3qaE2GLoiA0EsN8SqeGDmQ5eOY0unGvarzyaJ9+DqjqMbZYO3bpr7sdB+ZwGKzBfxULPLKWh
qi4XbcaEpsyBC4uVVC4650BIUJ3LtsWoJ6WdHaDGRaiYCAaeTf5cs4tkZlZI7ND6XIT738HnO53P
raCskxAjLHW3pCT+na42X+Nc2zZCJktIjPV9vUvxlKup2OZxbVON8b5ddg20kSM3GCZcOlUjDWD4
hluKs6pY7/hpxVCoIZy1u1UqYeAknkKqlNrT+p7rjw9HfQS19efLUbcDODM4GZwtP1qijVXxVMzj
0dbD3fc/7lyRhY1gV4W/YP+y816lRKLfckhCtFB2ceq375fIds+HRqMQQp+3xGKPt1pgEX15V1ZO
4A409Mdqgn4D3cOSfo1SmgqHcTTT4qgIMT5rVACDk3DaHu8NYTJFWkM0uAm/W6CZyfty1/zirW5S
EBGBWTTk8QpMXaqtIT+SEVYj7PpGt4gCp0+Y1FjhP+JN6FgMKtM3aAjfK8+jn3lrCU9YB7WyFJ8O
pVupNv+2vuMSrmRx7tTcvD0NxtzU7UxQHWOTSRDA6cGh5Va3hdeDLiy9NQsdrF+C3XVnmMZveXak
hJXury9lmwuCsfX2YJcT4WxCshnMnptMoktyMixUIP6KKEn0S74GqhRvlWIbCOrsuR44vaGP9HfD
ylaPsFHGfzIMD30kRu981jBtX1v8bRK1Of9DoL9W4exb8ViaA37nsevcLAcBKeM5LnGAtmdUHkzg
8T7GEblSbuCRxdUxNWNj1LagRugvJ/ELYptjU3NcMVrfeWbsgEop7/6glwofBO5n3BlXe83qe6Uu
zLCt1RHh2XnO7lEF+K80CcufmJfgEgkFvwNIcJpkRHzrSucwXhoWWCseUMZ6pvwVpxpfpj7GLWRN
SO0Ai1D8D0AfWQxzQgoRty5Tx1TttNtufuTxV/TfXuKUWa+rbei7JuBL4gESmEOecV3+ngw0hNE0
2E8SQdT8JJnToRzCf3GQIBXLGmAQiTmhYhHRM7aZmCGe0mVYL/0b7cpQ5PQEObYKxSW0RdMQ3fXE
MGh3IJWIOVl3ANBxsPU+E3U7fVYc28LvTwNCzYeiW4cl4bp53f++fuNiRL+SSrRx5ysAFvor0ats
yma3/Fe4kaTOncKlcpI6vKXrW9MWrdTeJ1H2x0jYO84oIYtnO+hUpaf1HrmMAus03++llgiG+yIJ
3cpG4E+xFDgFs+MWKOL7+khzfpTmhw8x2LSoMnrq3Qjr8FcUKRTt+yJBELuPx/T/h18EK+gQScfT
cxrYLqP0ejDEemLcIjlxWn9DO/WeWw9Nu38d1ndQ44AJ2JcQ2LqbFPkejr8GkpeXaMnu8gZPoTL8
fx4lGaf27SCsX/h170tmL2QmMdVIwL8cfa75dINrKeThC9W5C4kDyrpKkisXL6hRQ9nUDYdILYk0
suWBz4K13fHx1xSQHIr2UslOri8bd06kcq48G7y+nLf+clQfBC0zwIx2dtUBn5aCm5jwlgpV0kRN
scCeSrGEa0QHnFgJLZUu1Y6j5XFP4j1/uAkLoJOmObyfWdTUL0yaBxM4mXcwbbzTPXLJX/AAExc1
WBEsjXGg0WY+usAtXZYXLtpJVzr7COG/ljnHPKTUB6WVgzL3yBR0JN+Y4TSaQHWH6IkMV8YLcg74
sw9b8HdOcw3ZViii0DP/
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
c9vsW5JBCvThyxOUH2PprRXrwDWuKZW/Q7qPv429HnbShw4Uk66yycd+J5tES7AzUCyGeanqADbi
t/NXtBFOdg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
THl1Z3bcMS4H5t6D0G+kJ/FC2Y9oXN8UuO5gTyqyx046tFrVCFbF7b10tz4zI+nryigVgXDuQjpn
REJa68sEKDIsGl5JYzOYVe9IZ30LgoXUIOey68bvuu3Fnu8lEQh/WChcCnbyekJTFEdRaUW6S2O+
5xce7Ha8Gv7YClnhp04=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
KL9gEW9UR9bJ2V+rRImGqHBVYgwBOrGPetNJZ9L5EOgu04h1LECL47Zq26De2Obbv4OkIEGfGFbZ
muWpwFGMSP/qDDeS04mLx/tWX4SnYgQRVyk8AGGlepDKbn1R0w9YaYChqwaqdh3fMk+xJZbtgoWp
4ejGlCOtRuSFxFcOTPGLnPLr5saG0n7SH0iOlkdKRcxP8k1FnXr8kYqxu6g0r1ZNWNYlDcRB7pBC
lrlL52/HTgYUGboGp0/wpS3BU8yKiMyKpm/Nc0Q701u3QL3zraihgQqtTSzkLZnBFXKNrCd6K2Zb
gw1krcKarckcDY4W+Jw/vlWaBMsrX/8GffFxsQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
I9+ICDzIgzYMfdI9n5+7cSfa+M9K8Q9HlZVHvp38kWsb+jUXV67Oh07GXgNqpn7RlOPdQSyhyXf6
AZH+fL8ycTHV0MoCLtaJieiw5P4E1Pm7Fdq2uCENFjt8u7I2RH9/lcoRh4KurkxCVCe86Dtk1oWB
bacFgZX+QZ+FCZn+6nI=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
pyasIdA/E1o2abIoUkxhLYQwvp5B9zIwQEm/+EGPR3u06a5SPM2I1E62WIwSJ7iN/bqdRmd03/xZ
zjSCCiFFaRUwQmJJ5xZcUnw15IQqIRd/WQQ56gktCUx2rEJwJ4BBJrhOQsbLLnEDNgJUxpYVfXAy
ix6G1h7tonYt5pC9K8hh3YN8608V5TRujBAEsLi+3lAMFCMgjGqgS6cpljhaHIjuKULPnRb7+Rll
fIJqbRqDAQ0ubxbSrdH7w8ZIqWH5mG/hnLBefDFlIZJh/pHjOIOLGPh9RyUn99n5SKT8NF75l8Mj
ggHTuLkcPsoN2kGMWMDxZ752vU2X39SpzveZtA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6000)
`protect data_block
TxmWdQtoCa72lA+PjmaVWNzez4mZxpW7I8VWfPbcGicMeEL2MwwAS4LUnoxwA9Uhmm5ot+LUjCmv
eDB7SAvMi2HMKnvkVOM6GyDSV3gAIeNsWXHPVpwGySt8l+veQ87+wCB2U0M2AjDDPy5G0YrHv7SV
3hwskYbNG5I35qHpm3MFyP0vEDTw2Fa861T3JSQElQvkHyiJtc1mCK8c+3Xwu2sX2tdUav9HJ/w9
ZeB6TCc1chmVdFw//m3On54B7bmWN9Zebwnw5VQGvAYNMLyudEgVjYJwsgwTfKt7pZ93DMozPsEb
mZW50l08EWStM63eu5CZx2XBarUhqb053q94CYABjIYCo57BhlAgWgkKSS2f5WQW0T4Jc3rrfKN3
sLKdFCmMZrqfr5pgPkkX+nvfqUlvDaNXr1tYdehUiUwQuHo0YktKmaf9b7G08xq2O+KihhDW8bJL
JxvKd5VOwLu5iT8eD4v22BpAwoc1xjn98yzfCmkC27huSSupAOcJw+AP5OFOkoRBWp079P45WQOz
o/hkgLdSsXaQUNYZhi2sEsKzRYQK+hrxajBLt5oHEBJbf7wIUiygAcdixuv12Dd/r5+WcBPm4SJO
EmUMYhUA15hnaNALn0dGvrSkIP5NslL6zWERTi9G/OFbUb1a799ztM/HsHegshJwRbCxHi2xIz16
z35IEn7CVUoWVCtQlpFDFlgUxi9BshVVTf/6EayE6uFNg6KX4HhvSmuwujoT0wRmbQZ3Ia7MGLGS
uyxfc7BJHDjz5MQ3coKQd51qJqfHTeRGTAeQ9SzqASPY8ebTFMlp1vqFRPbOq6KsrHx7WT75pRyg
8foHSrwUrb/E8FbwnLnYe9umPzKEjGCTo6eXMWpVIyglksrRWrHIM0OOlju1rUPs5g8RID/+aWQl
krguToDL3/FbiBN/OpIpzzDFYSMSIhrq7W2k0D6X90tLdM86lV4BCaIna6MHSucetYvc6zrnoGID
ZdXRDktS64+FUnZpecuBvQtan+SwG5Rvqymh0vB5LWrSR34biGzmqqTBL6p0TkGzPJUxr3lqAthc
KMtK1x/EDuNMioKMJR1MutrwOckHFMTYiwMKhxvYePPfxHJAgRzDfDBKJ9KWfOFooBxhHPeirSD7
ApSD9kcvPzrCWtqheCAAtKvcZP69vAN+sPL4o8f8ZwS4u3neFS/PPgIEyPAjOT3Rx+hphXuRbR0C
xcg9NF/xUbIz1a0O81Hw+8USWdyB4CQVxN5TGWS0eU0Pzoempf3cbN/Umb4Z+G4nc6TVnd8Gzb/m
jLUUtvYTa++9REXif4S6B/jCByLNDOxPQ28fB9svsp0vyMkxtzExcTVuuXpp4sLmoIH0UguSwDrE
x5YlFE3mWIf1OcehV2K2ErmJpe/bx8/yRbJ+kETpRKlv8D6XTVRQt+Vea+z/vp51qlFOXkOir/4z
HbT597Zit9GKjTATbsheBAZFsu2OizevmfFZYM2WDfnnUnMamAUqxaKqV8sBjWCkxt7aOfu6RZRK
yRL7SOf4zEEAFHMuE+GPm0rxk/sCx2m26oOMj8DaX8AQ/3s2oNdxQ2ddf9myEgQlGerb+eAV5o1a
5LqAFtKIk9Wa2pAmhmbxUpfE38EhmUl+234E/YoxdQLzujssw+CNBvGu8kay1h0rWYV33KjltIfQ
e7KSp27ixG50GEf69G4xAL3n1v6tR1ouThly320lFyJ3Wssf2xL8OdqYZSoLvRF/z5Km2UbN8C+7
b8ffHHM55SASUZgCBIzBG1crH+eNXgiO9efb0rlBQrssgT/gml39YobX1TcOcgos3QpPzFpHw6m7
nZtdH/d+GpWJzbnPCAuEPyDwb4nftuTZZeEacP2zZPvGGROsylXzm+/InIrEx2Ja3Pe03gKZ7kZI
MEAhq8wwkZ0DVk2WDBZxVi/MP0Bbu1xA2CYb9Q2ylABgnzj8gdvoi/JbROGOoF0aSyDWizHV76E4
w1W5PxM9E8680QSTHrxcNxNz0ZO0XGkV3wokatX/5drWMmp+l8vRqoY0zc5+XDjdNgmbt4Aet9cU
9c6Gu3Dz7tgMbXBJsu4EmdbZSNKQLto9ZAd1zOPonSwPo6bwiU+LqjOV94wy+eH4/jYjYrwJiHDM
HyNwJuLi+ht2lBMKmwj6gZG9yecfGBvmcchYOpnyXKAHrE4iJyQuqiqRgL8TOGuMS/BWEZoUV1xT
i+vQiLWtToNOm5bAPioM2s+TcGjzptmZQsmk/bK0sVLLcyXBBxlTMsYnpOl8TnUXNiBNSlg7yoDO
UFvNugB1iR9yTD4Qy+bX5OT2j0OaP1aSMr9OK3fYCxIfl9oUrqQAz1fRc7UOniKSxDClSdhrt/g3
2w+S2xLd1sPkJLh1Z042bk/BdmJgWwfvjpSdD9cA2H0bd9l6f1JmA+XOCcVm8aiqBP+AncvFZkNi
zTCIrFbLsPiUkIMQ8aGtWpFmxbJ/TFaR5RavOE77XkqCyfjvAS1CkGEmQPu45C3KNLMljHvoTGoM
K0WpaO6nYpRhoTp3pB/GFYZH7IyrzaWSCWGVDfmwl8kwuw077+RrBKytLdEvirocgA0XXTckkOP2
YlEVy4zWwy4ozYDcU3sZItQzhUk+XUAtuRyMYQaD+kMmv3R18LAiwcGKLZW5sHBT11dPSGdWpJPQ
JUoI6scMIZZkhWcAd6RdfSUidOpWtiNkDD3wRwbkGsFBwFVW3fXckKO7AQMpCwqeAZq7xzyIDvYO
wNsir/tIa51q0hqSvHP2aaht0TF52ZHQAl11hXQfGtlSMcfrCP3EXGW7Dyrjtk0bPO+U5jyHiztH
b6HKhOdFZarKHPuzQpOYGb4fVlcRAYz4ujhTcfBZOB50NCcympkfCerHKuQkjR7CtJCU/FuOJWqA
LJhIn6vd5ZBZsZKQZfz/Vfi4D8HtvIAg7efEMwCF4sZoWND5Q8XUITLBQ1vm38m7jGV5WooUzmA/
YYHZ5gNMKTNI2rjx6dOapKVN2kwpUgmnqIEw6NLjCZDHmJuvFzqFI6E12fndcObS1LF/VMSrKmhD
F0RLzCARmlpQ8YQaGv3aF/i+jmYcVLvf353fL9w1QVKn+8/5CDSVzjE423D4nIBfbngJneJS3+2z
duSI7FHGEzdj93raYGcZe43fEhZ1dIF9H50A84Rix/gVFWv3NhB/Tcjk2f8AmFp/M47dxGIRkmOX
EQj3EEWq0HXDR1iUyf6YMizK70jMfZ1r6iOGMZYy4g93/e3FBklX7CleETlXaDWS7BC243ka5P7M
jhlhSxTflKC6x9toDQDhWVTQOhN24qUSYugdEru8c0ju8NYZvhRSYvCgnPo5M6tq9hAZ+zBFGOgR
wA3czXQUG4Liq0Gt+Npgd9LUYwhQFo8ahyVu35826rbZybwbX3HGwBadXf5m+yGOmAKPzhu7h96x
FoFUeJKhCU6hlBeCj9IPG9Q+DiRvBBrlgGi/SsjEP5HYTGXP3XLdza4E5gaOqj1PBR/8S6e+NLA7
rQx4Omz8BVG+qVbNVkQpCN+ozDK4WK49yuLCyMWLl6SbOC05dZziMPbSP4IULW9bK/o/Sac8rZtn
QbhQojrvXv7qj6bzy9mUuWQHF8m0ZR9T2hqwAx0vVEpoWU2qRpp30md7+/4WU6ddq0mn3zNwdAa6
nhI/Qrga2D7peVuYaFKYg+iC9soZccRmUDVi5AepG8+oGRAEmvIadnS2Orz7J9PcDEaP7/wHqnkT
E4+0+OKo50zH7D9FmjY0+zhOkinkAmoxLI3koQz1AFVoYB3Oc4FJQ1mAjBn5RDxciAall4tcHmph
AHjIjF6/npOI9rqg9Kv3SYDhY8CgNSqexhQSyxe8FRwDncSGYRq9pdL/EepWjjkbvyAfAN296S3M
KggAEB+SdNHvqqstJFzRBc1LY8WkE8ouoHbxa97vRXY+hopaCl37NXjHDseFr9iZruDOXtGtPs5l
//oZT0Gd8qEzmegeShrQFplZCdGwtEHjMVaZOFcaoEri1SYCzZS8vFWuZ31NrfAzbR8yi/zay0qG
DgZ2iLXuVJWE0DwQ5GnozJl06xnXQiEnUhF3Av/XcnvLLupy3IwVDjcpAXsPQNpYgaNm8ZHiukYt
TjNlQxroJDKZKrBQTC7aTDeyTNAdBJfWQ1NWqryxz/tVKNHdHKNjdT5ubWF+moI/KkSkIv0mRI+f
4KJEL5pr3wdRXTuAhP+2qqEHmYoYNjfFikVfcZjHOeFwunZuIlbYHqaAR1zrI6D60OK/DHl6GzRO
7lhOolznbM00mA8FGOjesVn4WR79qgO7a6W78gkt4OJ5ukjp+CiX8uTm/NA//4Ep7QF6JdB9q0aS
7uYdsBb0qpSMfUiT/Ukq/OEbLHBCcTRq+9KqtZA10v0RytoU1K/qdfOhsgSwj89iQAYCmYHreNnH
Pk7yD1F+7ZAhRvP8GMu/DGcDO6d/+k2eACv9mZT5yr4xzskXlgzrdBCD36hL5KdZSP7IKNIHcHNl
DSW+wenxH1cxlfl5OMfZDkirH/RR1FQnuVJnngBYHPlv3JHuQUqE0ZF70K4hSKYYi3B6t/ldaCNh
WVGOdbM1SO4fwlxXL9M1AmCMX7zOaQi6EkXzzWvmaHmRtYeuvi1xX/byx+rII7a6qdzETqMkvlln
n/2UCz1AFSzQjVka0eJ3b9VVDJDQ4RQhQ15cM9IeCsvqxd2WlQCLXt08AUGfHZWCjHdzmmgkrlG3
e6pKulOVGc5VwSWWbnkxeqXfpzvVQN7XZeOboQn2IuyNvWkdNmqgn0tQhFNeIanvT/GiJ0HmBuMZ
9/65RLl7uMHcKe2Wr12VGmVDyDTNZfN5V4YZwESdWABbU6vztTH7VyNenpCD/ZFUbglx2Dc+7hyo
ljr3KnNPsq0hV/9wB5WoXClZxy1KSu2ofTRwfSQi7+G6AddDAeGKRl+oVQOvWevsUzoKJBpz2q8r
7aJoFF3U0JYvZVVFRRSw3SEVeG3hpUBcAQzJFFqLweGy2vP/FFryOcmCOC89TEVYMm5at/r4uGOY
gxSUhg6RaSAuxyQR+nKXbKjwJ0rA/P9lhNgMIQ8/lqKrWEINcwADetLUHzzwcq5cgnzq9SoKcKkg
PuSoKNIM7Zt2niydQCACx14PEB8696I+r77o8mWc1zwcMxHSk2C0WnQPAJo1iEIS/0WEJfUg+gGh
QXAe8iirvQme7pLOHHOuphtSfEqf6rXqQsFPj1zB16xcixO3lOJAdW6tjrN0/V8vrSlu3M1intJI
lX4cOJxn7cTy3UrPhSRsOxpQHhbofPKNNaQRPOfzImO8p4ldoWiNK9M2S0yUsln/61pJi7aigg1g
hM5OqMT4KwvBucdfSZDGJ8RpHmpHyBniIvzbbKyiumThPmNvL4H/0NbcQwjl4q1lZfeSoiuiW1YN
k2F+vHcbg+Lrmd14d3249JQ6wdOT2DsvRDDPFwhH9jn5K3DdeEVjJAeHoHnV7wAkZ4QvYIlzU8cC
s8wqUyhmDnKdF4nz3/HafVAoKzRxa8vJV9JaNzIpQa6R4PpMfK2xK23PY+dZbtXshrkNfEap5322
O5W+MaLd/jqts9orI2TZOiRAgYw4YYLoXN4GTjhx51xmj+7R7jHGCQqn6LrEVQyhWxPo+0ztK2QB
vEG3/ieXSJZbijN6TpTMQBH0CuL0uQqNBpgJJXPFWzGK87oQo7gkVY/iEfP+j2vhyl7WaagNDc+J
pZByqjDUoxq3/5pG2G4HFj/+wyIaJtre2+kfm7li5yy6yZC9H+q+85Q3ggS+owE4nuyURPbM/J8D
1Mkfer2p67WoF+l+njAuRp6nIde5H50jf+TlnFJ7dj7hXKPDUOIXEQc2KQ23bJNYbzs6/bpCUZLS
/KDNykC3mrPAuwkxnedbELLh5X9PhG+IQo4KBiLAYBLvpkwryx/+c6iWP0MdYwwWdQNlzjUb6zFZ
xtfyu5jynJuSOtUWBYgxnDL8gssrC7aKybNiwVC0iRGgFUtchhb4vCvFcdR63Coqvmn+IpGC1UDj
iDtZYnh/W6U3ZnueY16l0SbsW8B9iEzO6M/jhFmVOkG4tmmaS4IhIJoSJCu7LKYi/JKrnVUTgCS2
iRj9hq57hJie8ty8PgaUYvMtILC9g65OF0+m41kFH4V35QzagJIhWb/BQPSAezL4CPqcVfPjMifT
p6V2xXY3uUPVVAMbyUQTXe2hPWeem0gAVxx0A8OoTMz3oTY9Eg4y+KbM7rccywEmWVGqJU1/BA+5
hvkrvh9NOuCa+pc9W7WgIP4U4cUEgsKPae2Dz8D/izCVCT1Ffv+jwqjnK5wg4N6gEQmqvl9n7ME1
8IVw3qaE2GLoiA0EsN8SqeGDmQ5eOY0unGvarzyaJ9+DqjqMbZYO3bpr7sdB+ZwGKzBfxULPLKWh
qi4XbcaEpsyBC4uVVC4650BIUJ3LtsWoJ6WdHaDGRaiYCAaeTf5cs4tkZlZI7ND6XIT738HnO53P
raCskxAjLHW3pCT+na42X+Nc2zZCJktIjPV9vUvxlKup2OZxbVON8b5ddg20kSM3GCZcOlUjDWD4
hluKs6pY7/hpxVCoIZy1u1UqYeAknkKqlNrT+p7rjw9HfQS19efLUbcDODM4GZwtP1qijVXxVMzj
0dbD3fc/7lyRhY1gV4W/YP+y816lRKLfckhCtFB2ceq375fIds+HRqMQQp+3xGKPt1pgEX15V1ZO
4A409Mdqgn4D3cOSfo1SmgqHcTTT4qgIMT5rVACDk3DaHu8NYTJFWkM0uAm/W6CZyfty1/zirW5S
EBGBWTTk8QpMXaqtIT+SEVYj7PpGt4gCp0+Y1FjhP+JN6FgMKtM3aAjfK8+jn3lrCU9YB7WyFJ8O
pVupNv+2vuMSrmRx7tTcvD0NxtzU7UxQHWOTSRDA6cGh5Va3hdeDLiy9NQsdrF+C3XVnmMZveXak
hJXury9lmwuCsfX2YJcT4WxCshnMnptMoktyMixUIP6KKEn0S74GqhRvlWIbCOrsuR44vaGP9HfD
ylaPsFHGfzIMD30kRu981jBtX1v8bRK1Of9DoL9W4exb8ViaA37nsevcLAcBKeM5LnGAtmdUHkzg
8T7GEblSbuCRxdUxNWNj1LagRugvJ/ELYptjU3NcMVrfeWbsgEop7/6glwofBO5n3BlXe83qe6Uu
zLCt1RHh2XnO7lEF+K80CcufmJfgEgkFvwNIcJpkRHzrSucwXhoWWCseUMZ6pvwVpxpfpj7GLWRN
SO0Ai1D8D0AfWQxzQgoRty5Tx1TttNtufuTxV/TfXuKUWa+rbei7JuBL4gESmEOecV3+ngw0hNE0
2E8SQdT8JJnToRzCf3GQIBXLGmAQiTmhYhHRM7aZmCGe0mVYL/0b7cpQ5PQEObYKxSW0RdMQ3fXE
MGh3IJWIOVl3ANBxsPU+E3U7fVYc28LvTwNCzYeiW4cl4bp53f++fuNiRL+SSrRx5ysAFvor0ats
yma3/Fe4kaTOncKlcpI6vKXrW9MWrdTeJ1H2x0jYO84oIYtnO+hUpaf1HrmMAus03++llgiG+yIJ
3cpG4E+xFDgFs+MWKOL7+khzfpTmhw8x2LSoMnrq3Qjr8FcUKRTt+yJBELuPx/T/h18EK+gQScfT
cxrYLqP0ejDEemLcIjlxWn9DO/WeWw9Nu38d1ndQ44AJ2JcQ2LqbFPkejr8GkpeXaMnu8gZPoTL8
fx4lGaf27SCsX/h170tmL2QmMdVIwL8cfa75dINrKeThC9W5C4kDyrpKkisXL6hRQ9nUDYdILYk0
suWBz4K13fHx1xSQHIr2UslOri8bd06kcq48G7y+nLf+clQfBC0zwIx2dtUBn5aCm5jwlgpV0kRN
scCeSrGEa0QHnFgJLZUu1Y6j5XFP4j1/uAkLoJOmObyfWdTUL0yaBxM4mXcwbbzTPXLJX/AAExc1
WBEsjXGg0WY+usAtXZYXLtpJVzr7COG/ljnHPKTUB6WVgzL3yBR0JN+Y4TSaQHWH6IkMV8YLcg74
sw9b8HdOcw3ZViii0DP/
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
c9vsW5JBCvThyxOUH2PprRXrwDWuKZW/Q7qPv429HnbShw4Uk66yycd+J5tES7AzUCyGeanqADbi
t/NXtBFOdg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
THl1Z3bcMS4H5t6D0G+kJ/FC2Y9oXN8UuO5gTyqyx046tFrVCFbF7b10tz4zI+nryigVgXDuQjpn
REJa68sEKDIsGl5JYzOYVe9IZ30LgoXUIOey68bvuu3Fnu8lEQh/WChcCnbyekJTFEdRaUW6S2O+
5xce7Ha8Gv7YClnhp04=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
KL9gEW9UR9bJ2V+rRImGqHBVYgwBOrGPetNJZ9L5EOgu04h1LECL47Zq26De2Obbv4OkIEGfGFbZ
muWpwFGMSP/qDDeS04mLx/tWX4SnYgQRVyk8AGGlepDKbn1R0w9YaYChqwaqdh3fMk+xJZbtgoWp
4ejGlCOtRuSFxFcOTPGLnPLr5saG0n7SH0iOlkdKRcxP8k1FnXr8kYqxu6g0r1ZNWNYlDcRB7pBC
lrlL52/HTgYUGboGp0/wpS3BU8yKiMyKpm/Nc0Q701u3QL3zraihgQqtTSzkLZnBFXKNrCd6K2Zb
gw1krcKarckcDY4W+Jw/vlWaBMsrX/8GffFxsQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
I9+ICDzIgzYMfdI9n5+7cSfa+M9K8Q9HlZVHvp38kWsb+jUXV67Oh07GXgNqpn7RlOPdQSyhyXf6
AZH+fL8ycTHV0MoCLtaJieiw5P4E1Pm7Fdq2uCENFjt8u7I2RH9/lcoRh4KurkxCVCe86Dtk1oWB
bacFgZX+QZ+FCZn+6nI=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
pyasIdA/E1o2abIoUkxhLYQwvp5B9zIwQEm/+EGPR3u06a5SPM2I1E62WIwSJ7iN/bqdRmd03/xZ
zjSCCiFFaRUwQmJJ5xZcUnw15IQqIRd/WQQ56gktCUx2rEJwJ4BBJrhOQsbLLnEDNgJUxpYVfXAy
ix6G1h7tonYt5pC9K8hh3YN8608V5TRujBAEsLi+3lAMFCMgjGqgS6cpljhaHIjuKULPnRb7+Rll
fIJqbRqDAQ0ubxbSrdH7w8ZIqWH5mG/hnLBefDFlIZJh/pHjOIOLGPh9RyUn99n5SKT8NF75l8Mj
ggHTuLkcPsoN2kGMWMDxZ752vU2X39SpzveZtA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6000)
`protect data_block
TxmWdQtoCa72lA+PjmaVWNzez4mZxpW7I8VWfPbcGicMeEL2MwwAS4LUnoxwA9Uhmm5ot+LUjCmv
eDB7SAvMi2HMKnvkVOM6GyDSV3gAIeNsWXHPVpwGySt8l+veQ87+wCB2U0M2AjDDPy5G0YrHv7SV
3hwskYbNG5I35qHpm3MFyP0vEDTw2Fa861T3JSQElQvkHyiJtc1mCK8c+3Xwu2sX2tdUav9HJ/w9
ZeB6TCc1chmVdFw//m3On54B7bmWN9Zebwnw5VQGvAYNMLyudEgVjYJwsgwTfKt7pZ93DMozPsEb
mZW50l08EWStM63eu5CZx2XBarUhqb053q94CYABjIYCo57BhlAgWgkKSS2f5WQW0T4Jc3rrfKN3
sLKdFCmMZrqfr5pgPkkX+nvfqUlvDaNXr1tYdehUiUwQuHo0YktKmaf9b7G08xq2O+KihhDW8bJL
JxvKd5VOwLu5iT8eD4v22BpAwoc1xjn98yzfCmkC27huSSupAOcJw+AP5OFOkoRBWp079P45WQOz
o/hkgLdSsXaQUNYZhi2sEsKzRYQK+hrxajBLt5oHEBJbf7wIUiygAcdixuv12Dd/r5+WcBPm4SJO
EmUMYhUA15hnaNALn0dGvrSkIP5NslL6zWERTi9G/OFbUb1a799ztM/HsHegshJwRbCxHi2xIz16
z35IEn7CVUoWVCtQlpFDFlgUxi9BshVVTf/6EayE6uFNg6KX4HhvSmuwujoT0wRmbQZ3Ia7MGLGS
uyxfc7BJHDjz5MQ3coKQd51qJqfHTeRGTAeQ9SzqASPY8ebTFMlp1vqFRPbOq6KsrHx7WT75pRyg
8foHSrwUrb/E8FbwnLnYe9umPzKEjGCTo6eXMWpVIyglksrRWrHIM0OOlju1rUPs5g8RID/+aWQl
krguToDL3/FbiBN/OpIpzzDFYSMSIhrq7W2k0D6X90tLdM86lV4BCaIna6MHSucetYvc6zrnoGID
ZdXRDktS64+FUnZpecuBvQtan+SwG5Rvqymh0vB5LWrSR34biGzmqqTBL6p0TkGzPJUxr3lqAthc
KMtK1x/EDuNMioKMJR1MutrwOckHFMTYiwMKhxvYePPfxHJAgRzDfDBKJ9KWfOFooBxhHPeirSD7
ApSD9kcvPzrCWtqheCAAtKvcZP69vAN+sPL4o8f8ZwS4u3neFS/PPgIEyPAjOT3Rx+hphXuRbR0C
xcg9NF/xUbIz1a0O81Hw+8USWdyB4CQVxN5TGWS0eU0Pzoempf3cbN/Umb4Z+G4nc6TVnd8Gzb/m
jLUUtvYTa++9REXif4S6B/jCByLNDOxPQ28fB9svsp0vyMkxtzExcTVuuXpp4sLmoIH0UguSwDrE
x5YlFE3mWIf1OcehV2K2ErmJpe/bx8/yRbJ+kETpRKlv8D6XTVRQt+Vea+z/vp51qlFOXkOir/4z
HbT597Zit9GKjTATbsheBAZFsu2OizevmfFZYM2WDfnnUnMamAUqxaKqV8sBjWCkxt7aOfu6RZRK
yRL7SOf4zEEAFHMuE+GPm0rxk/sCx2m26oOMj8DaX8AQ/3s2oNdxQ2ddf9myEgQlGerb+eAV5o1a
5LqAFtKIk9Wa2pAmhmbxUpfE38EhmUl+234E/YoxdQLzujssw+CNBvGu8kay1h0rWYV33KjltIfQ
e7KSp27ixG50GEf69G4xAL3n1v6tR1ouThly320lFyJ3Wssf2xL8OdqYZSoLvRF/z5Km2UbN8C+7
b8ffHHM55SASUZgCBIzBG1crH+eNXgiO9efb0rlBQrssgT/gml39YobX1TcOcgos3QpPzFpHw6m7
nZtdH/d+GpWJzbnPCAuEPyDwb4nftuTZZeEacP2zZPvGGROsylXzm+/InIrEx2Ja3Pe03gKZ7kZI
MEAhq8wwkZ0DVk2WDBZxVi/MP0Bbu1xA2CYb9Q2ylABgnzj8gdvoi/JbROGOoF0aSyDWizHV76E4
w1W5PxM9E8680QSTHrxcNxNz0ZO0XGkV3wokatX/5drWMmp+l8vRqoY0zc5+XDjdNgmbt4Aet9cU
9c6Gu3Dz7tgMbXBJsu4EmdbZSNKQLto9ZAd1zOPonSwPo6bwiU+LqjOV94wy+eH4/jYjYrwJiHDM
HyNwJuLi+ht2lBMKmwj6gZG9yecfGBvmcchYOpnyXKAHrE4iJyQuqiqRgL8TOGuMS/BWEZoUV1xT
i+vQiLWtToNOm5bAPioM2s+TcGjzptmZQsmk/bK0sVLLcyXBBxlTMsYnpOl8TnUXNiBNSlg7yoDO
UFvNugB1iR9yTD4Qy+bX5OT2j0OaP1aSMr9OK3fYCxIfl9oUrqQAz1fRc7UOniKSxDClSdhrt/g3
2w+S2xLd1sPkJLh1Z042bk/BdmJgWwfvjpSdD9cA2H0bd9l6f1JmA+XOCcVm8aiqBP+AncvFZkNi
zTCIrFbLsPiUkIMQ8aGtWpFmxbJ/TFaR5RavOE77XkqCyfjvAS1CkGEmQPu45C3KNLMljHvoTGoM
K0WpaO6nYpRhoTp3pB/GFYZH7IyrzaWSCWGVDfmwl8kwuw077+RrBKytLdEvirocgA0XXTckkOP2
YlEVy4zWwy4ozYDcU3sZItQzhUk+XUAtuRyMYQaD+kMmv3R18LAiwcGKLZW5sHBT11dPSGdWpJPQ
JUoI6scMIZZkhWcAd6RdfSUidOpWtiNkDD3wRwbkGsFBwFVW3fXckKO7AQMpCwqeAZq7xzyIDvYO
wNsir/tIa51q0hqSvHP2aaht0TF52ZHQAl11hXQfGtlSMcfrCP3EXGW7Dyrjtk0bPO+U5jyHiztH
b6HKhOdFZarKHPuzQpOYGb4fVlcRAYz4ujhTcfBZOB50NCcympkfCerHKuQkjR7CtJCU/FuOJWqA
LJhIn6vd5ZBZsZKQZfz/Vfi4D8HtvIAg7efEMwCF4sZoWND5Q8XUITLBQ1vm38m7jGV5WooUzmA/
YYHZ5gNMKTNI2rjx6dOapKVN2kwpUgmnqIEw6NLjCZDHmJuvFzqFI6E12fndcObS1LF/VMSrKmhD
F0RLzCARmlpQ8YQaGv3aF/i+jmYcVLvf353fL9w1QVKn+8/5CDSVzjE423D4nIBfbngJneJS3+2z
duSI7FHGEzdj93raYGcZe43fEhZ1dIF9H50A84Rix/gVFWv3NhB/Tcjk2f8AmFp/M47dxGIRkmOX
EQj3EEWq0HXDR1iUyf6YMizK70jMfZ1r6iOGMZYy4g93/e3FBklX7CleETlXaDWS7BC243ka5P7M
jhlhSxTflKC6x9toDQDhWVTQOhN24qUSYugdEru8c0ju8NYZvhRSYvCgnPo5M6tq9hAZ+zBFGOgR
wA3czXQUG4Liq0Gt+Npgd9LUYwhQFo8ahyVu35826rbZybwbX3HGwBadXf5m+yGOmAKPzhu7h96x
FoFUeJKhCU6hlBeCj9IPG9Q+DiRvBBrlgGi/SsjEP5HYTGXP3XLdza4E5gaOqj1PBR/8S6e+NLA7
rQx4Omz8BVG+qVbNVkQpCN+ozDK4WK49yuLCyMWLl6SbOC05dZziMPbSP4IULW9bK/o/Sac8rZtn
QbhQojrvXv7qj6bzy9mUuWQHF8m0ZR9T2hqwAx0vVEpoWU2qRpp30md7+/4WU6ddq0mn3zNwdAa6
nhI/Qrga2D7peVuYaFKYg+iC9soZccRmUDVi5AepG8+oGRAEmvIadnS2Orz7J9PcDEaP7/wHqnkT
E4+0+OKo50zH7D9FmjY0+zhOkinkAmoxLI3koQz1AFVoYB3Oc4FJQ1mAjBn5RDxciAall4tcHmph
AHjIjF6/npOI9rqg9Kv3SYDhY8CgNSqexhQSyxe8FRwDncSGYRq9pdL/EepWjjkbvyAfAN296S3M
KggAEB+SdNHvqqstJFzRBc1LY8WkE8ouoHbxa97vRXY+hopaCl37NXjHDseFr9iZruDOXtGtPs5l
//oZT0Gd8qEzmegeShrQFplZCdGwtEHjMVaZOFcaoEri1SYCzZS8vFWuZ31NrfAzbR8yi/zay0qG
DgZ2iLXuVJWE0DwQ5GnozJl06xnXQiEnUhF3Av/XcnvLLupy3IwVDjcpAXsPQNpYgaNm8ZHiukYt
TjNlQxroJDKZKrBQTC7aTDeyTNAdBJfWQ1NWqryxz/tVKNHdHKNjdT5ubWF+moI/KkSkIv0mRI+f
4KJEL5pr3wdRXTuAhP+2qqEHmYoYNjfFikVfcZjHOeFwunZuIlbYHqaAR1zrI6D60OK/DHl6GzRO
7lhOolznbM00mA8FGOjesVn4WR79qgO7a6W78gkt4OJ5ukjp+CiX8uTm/NA//4Ep7QF6JdB9q0aS
7uYdsBb0qpSMfUiT/Ukq/OEbLHBCcTRq+9KqtZA10v0RytoU1K/qdfOhsgSwj89iQAYCmYHreNnH
Pk7yD1F+7ZAhRvP8GMu/DGcDO6d/+k2eACv9mZT5yr4xzskXlgzrdBCD36hL5KdZSP7IKNIHcHNl
DSW+wenxH1cxlfl5OMfZDkirH/RR1FQnuVJnngBYHPlv3JHuQUqE0ZF70K4hSKYYi3B6t/ldaCNh
WVGOdbM1SO4fwlxXL9M1AmCMX7zOaQi6EkXzzWvmaHmRtYeuvi1xX/byx+rII7a6qdzETqMkvlln
n/2UCz1AFSzQjVka0eJ3b9VVDJDQ4RQhQ15cM9IeCsvqxd2WlQCLXt08AUGfHZWCjHdzmmgkrlG3
e6pKulOVGc5VwSWWbnkxeqXfpzvVQN7XZeOboQn2IuyNvWkdNmqgn0tQhFNeIanvT/GiJ0HmBuMZ
9/65RLl7uMHcKe2Wr12VGmVDyDTNZfN5V4YZwESdWABbU6vztTH7VyNenpCD/ZFUbglx2Dc+7hyo
ljr3KnNPsq0hV/9wB5WoXClZxy1KSu2ofTRwfSQi7+G6AddDAeGKRl+oVQOvWevsUzoKJBpz2q8r
7aJoFF3U0JYvZVVFRRSw3SEVeG3hpUBcAQzJFFqLweGy2vP/FFryOcmCOC89TEVYMm5at/r4uGOY
gxSUhg6RaSAuxyQR+nKXbKjwJ0rA/P9lhNgMIQ8/lqKrWEINcwADetLUHzzwcq5cgnzq9SoKcKkg
PuSoKNIM7Zt2niydQCACx14PEB8696I+r77o8mWc1zwcMxHSk2C0WnQPAJo1iEIS/0WEJfUg+gGh
QXAe8iirvQme7pLOHHOuphtSfEqf6rXqQsFPj1zB16xcixO3lOJAdW6tjrN0/V8vrSlu3M1intJI
lX4cOJxn7cTy3UrPhSRsOxpQHhbofPKNNaQRPOfzImO8p4ldoWiNK9M2S0yUsln/61pJi7aigg1g
hM5OqMT4KwvBucdfSZDGJ8RpHmpHyBniIvzbbKyiumThPmNvL4H/0NbcQwjl4q1lZfeSoiuiW1YN
k2F+vHcbg+Lrmd14d3249JQ6wdOT2DsvRDDPFwhH9jn5K3DdeEVjJAeHoHnV7wAkZ4QvYIlzU8cC
s8wqUyhmDnKdF4nz3/HafVAoKzRxa8vJV9JaNzIpQa6R4PpMfK2xK23PY+dZbtXshrkNfEap5322
O5W+MaLd/jqts9orI2TZOiRAgYw4YYLoXN4GTjhx51xmj+7R7jHGCQqn6LrEVQyhWxPo+0ztK2QB
vEG3/ieXSJZbijN6TpTMQBH0CuL0uQqNBpgJJXPFWzGK87oQo7gkVY/iEfP+j2vhyl7WaagNDc+J
pZByqjDUoxq3/5pG2G4HFj/+wyIaJtre2+kfm7li5yy6yZC9H+q+85Q3ggS+owE4nuyURPbM/J8D
1Mkfer2p67WoF+l+njAuRp6nIde5H50jf+TlnFJ7dj7hXKPDUOIXEQc2KQ23bJNYbzs6/bpCUZLS
/KDNykC3mrPAuwkxnedbELLh5X9PhG+IQo4KBiLAYBLvpkwryx/+c6iWP0MdYwwWdQNlzjUb6zFZ
xtfyu5jynJuSOtUWBYgxnDL8gssrC7aKybNiwVC0iRGgFUtchhb4vCvFcdR63Coqvmn+IpGC1UDj
iDtZYnh/W6U3ZnueY16l0SbsW8B9iEzO6M/jhFmVOkG4tmmaS4IhIJoSJCu7LKYi/JKrnVUTgCS2
iRj9hq57hJie8ty8PgaUYvMtILC9g65OF0+m41kFH4V35QzagJIhWb/BQPSAezL4CPqcVfPjMifT
p6V2xXY3uUPVVAMbyUQTXe2hPWeem0gAVxx0A8OoTMz3oTY9Eg4y+KbM7rccywEmWVGqJU1/BA+5
hvkrvh9NOuCa+pc9W7WgIP4U4cUEgsKPae2Dz8D/izCVCT1Ffv+jwqjnK5wg4N6gEQmqvl9n7ME1
8IVw3qaE2GLoiA0EsN8SqeGDmQ5eOY0unGvarzyaJ9+DqjqMbZYO3bpr7sdB+ZwGKzBfxULPLKWh
qi4XbcaEpsyBC4uVVC4650BIUJ3LtsWoJ6WdHaDGRaiYCAaeTf5cs4tkZlZI7ND6XIT738HnO53P
raCskxAjLHW3pCT+na42X+Nc2zZCJktIjPV9vUvxlKup2OZxbVON8b5ddg20kSM3GCZcOlUjDWD4
hluKs6pY7/hpxVCoIZy1u1UqYeAknkKqlNrT+p7rjw9HfQS19efLUbcDODM4GZwtP1qijVXxVMzj
0dbD3fc/7lyRhY1gV4W/YP+y816lRKLfckhCtFB2ceq375fIds+HRqMQQp+3xGKPt1pgEX15V1ZO
4A409Mdqgn4D3cOSfo1SmgqHcTTT4qgIMT5rVACDk3DaHu8NYTJFWkM0uAm/W6CZyfty1/zirW5S
EBGBWTTk8QpMXaqtIT+SEVYj7PpGt4gCp0+Y1FjhP+JN6FgMKtM3aAjfK8+jn3lrCU9YB7WyFJ8O
pVupNv+2vuMSrmRx7tTcvD0NxtzU7UxQHWOTSRDA6cGh5Va3hdeDLiy9NQsdrF+C3XVnmMZveXak
hJXury9lmwuCsfX2YJcT4WxCshnMnptMoktyMixUIP6KKEn0S74GqhRvlWIbCOrsuR44vaGP9HfD
ylaPsFHGfzIMD30kRu981jBtX1v8bRK1Of9DoL9W4exb8ViaA37nsevcLAcBKeM5LnGAtmdUHkzg
8T7GEblSbuCRxdUxNWNj1LagRugvJ/ELYptjU3NcMVrfeWbsgEop7/6glwofBO5n3BlXe83qe6Uu
zLCt1RHh2XnO7lEF+K80CcufmJfgEgkFvwNIcJpkRHzrSucwXhoWWCseUMZ6pvwVpxpfpj7GLWRN
SO0Ai1D8D0AfWQxzQgoRty5Tx1TttNtufuTxV/TfXuKUWa+rbei7JuBL4gESmEOecV3+ngw0hNE0
2E8SQdT8JJnToRzCf3GQIBXLGmAQiTmhYhHRM7aZmCGe0mVYL/0b7cpQ5PQEObYKxSW0RdMQ3fXE
MGh3IJWIOVl3ANBxsPU+E3U7fVYc28LvTwNCzYeiW4cl4bp53f++fuNiRL+SSrRx5ysAFvor0ats
yma3/Fe4kaTOncKlcpI6vKXrW9MWrdTeJ1H2x0jYO84oIYtnO+hUpaf1HrmMAus03++llgiG+yIJ
3cpG4E+xFDgFs+MWKOL7+khzfpTmhw8x2LSoMnrq3Qjr8FcUKRTt+yJBELuPx/T/h18EK+gQScfT
cxrYLqP0ejDEemLcIjlxWn9DO/WeWw9Nu38d1ndQ44AJ2JcQ2LqbFPkejr8GkpeXaMnu8gZPoTL8
fx4lGaf27SCsX/h170tmL2QmMdVIwL8cfa75dINrKeThC9W5C4kDyrpKkisXL6hRQ9nUDYdILYk0
suWBz4K13fHx1xSQHIr2UslOri8bd06kcq48G7y+nLf+clQfBC0zwIx2dtUBn5aCm5jwlgpV0kRN
scCeSrGEa0QHnFgJLZUu1Y6j5XFP4j1/uAkLoJOmObyfWdTUL0yaBxM4mXcwbbzTPXLJX/AAExc1
WBEsjXGg0WY+usAtXZYXLtpJVzr7COG/ljnHPKTUB6WVgzL3yBR0JN+Y4TSaQHWH6IkMV8YLcg74
sw9b8HdOcw3ZViii0DP/
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
c9vsW5JBCvThyxOUH2PprRXrwDWuKZW/Q7qPv429HnbShw4Uk66yycd+J5tES7AzUCyGeanqADbi
t/NXtBFOdg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
THl1Z3bcMS4H5t6D0G+kJ/FC2Y9oXN8UuO5gTyqyx046tFrVCFbF7b10tz4zI+nryigVgXDuQjpn
REJa68sEKDIsGl5JYzOYVe9IZ30LgoXUIOey68bvuu3Fnu8lEQh/WChcCnbyekJTFEdRaUW6S2O+
5xce7Ha8Gv7YClnhp04=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
KL9gEW9UR9bJ2V+rRImGqHBVYgwBOrGPetNJZ9L5EOgu04h1LECL47Zq26De2Obbv4OkIEGfGFbZ
muWpwFGMSP/qDDeS04mLx/tWX4SnYgQRVyk8AGGlepDKbn1R0w9YaYChqwaqdh3fMk+xJZbtgoWp
4ejGlCOtRuSFxFcOTPGLnPLr5saG0n7SH0iOlkdKRcxP8k1FnXr8kYqxu6g0r1ZNWNYlDcRB7pBC
lrlL52/HTgYUGboGp0/wpS3BU8yKiMyKpm/Nc0Q701u3QL3zraihgQqtTSzkLZnBFXKNrCd6K2Zb
gw1krcKarckcDY4W+Jw/vlWaBMsrX/8GffFxsQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
I9+ICDzIgzYMfdI9n5+7cSfa+M9K8Q9HlZVHvp38kWsb+jUXV67Oh07GXgNqpn7RlOPdQSyhyXf6
AZH+fL8ycTHV0MoCLtaJieiw5P4E1Pm7Fdq2uCENFjt8u7I2RH9/lcoRh4KurkxCVCe86Dtk1oWB
bacFgZX+QZ+FCZn+6nI=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
pyasIdA/E1o2abIoUkxhLYQwvp5B9zIwQEm/+EGPR3u06a5SPM2I1E62WIwSJ7iN/bqdRmd03/xZ
zjSCCiFFaRUwQmJJ5xZcUnw15IQqIRd/WQQ56gktCUx2rEJwJ4BBJrhOQsbLLnEDNgJUxpYVfXAy
ix6G1h7tonYt5pC9K8hh3YN8608V5TRujBAEsLi+3lAMFCMgjGqgS6cpljhaHIjuKULPnRb7+Rll
fIJqbRqDAQ0ubxbSrdH7w8ZIqWH5mG/hnLBefDFlIZJh/pHjOIOLGPh9RyUn99n5SKT8NF75l8Mj
ggHTuLkcPsoN2kGMWMDxZ752vU2X39SpzveZtA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6000)
`protect data_block
TxmWdQtoCa72lA+PjmaVWNzez4mZxpW7I8VWfPbcGicMeEL2MwwAS4LUnoxwA9Uhmm5ot+LUjCmv
eDB7SAvMi2HMKnvkVOM6GyDSV3gAIeNsWXHPVpwGySt8l+veQ87+wCB2U0M2AjDDPy5G0YrHv7SV
3hwskYbNG5I35qHpm3MFyP0vEDTw2Fa861T3JSQElQvkHyiJtc1mCK8c+3Xwu2sX2tdUav9HJ/w9
ZeB6TCc1chmVdFw//m3On54B7bmWN9Zebwnw5VQGvAYNMLyudEgVjYJwsgwTfKt7pZ93DMozPsEb
mZW50l08EWStM63eu5CZx2XBarUhqb053q94CYABjIYCo57BhlAgWgkKSS2f5WQW0T4Jc3rrfKN3
sLKdFCmMZrqfr5pgPkkX+nvfqUlvDaNXr1tYdehUiUwQuHo0YktKmaf9b7G08xq2O+KihhDW8bJL
JxvKd5VOwLu5iT8eD4v22BpAwoc1xjn98yzfCmkC27huSSupAOcJw+AP5OFOkoRBWp079P45WQOz
o/hkgLdSsXaQUNYZhi2sEsKzRYQK+hrxajBLt5oHEBJbf7wIUiygAcdixuv12Dd/r5+WcBPm4SJO
EmUMYhUA15hnaNALn0dGvrSkIP5NslL6zWERTi9G/OFbUb1a799ztM/HsHegshJwRbCxHi2xIz16
z35IEn7CVUoWVCtQlpFDFlgUxi9BshVVTf/6EayE6uFNg6KX4HhvSmuwujoT0wRmbQZ3Ia7MGLGS
uyxfc7BJHDjz5MQ3coKQd51qJqfHTeRGTAeQ9SzqASPY8ebTFMlp1vqFRPbOq6KsrHx7WT75pRyg
8foHSrwUrb/E8FbwnLnYe9umPzKEjGCTo6eXMWpVIyglksrRWrHIM0OOlju1rUPs5g8RID/+aWQl
krguToDL3/FbiBN/OpIpzzDFYSMSIhrq7W2k0D6X90tLdM86lV4BCaIna6MHSucetYvc6zrnoGID
ZdXRDktS64+FUnZpecuBvQtan+SwG5Rvqymh0vB5LWrSR34biGzmqqTBL6p0TkGzPJUxr3lqAthc
KMtK1x/EDuNMioKMJR1MutrwOckHFMTYiwMKhxvYePPfxHJAgRzDfDBKJ9KWfOFooBxhHPeirSD7
ApSD9kcvPzrCWtqheCAAtKvcZP69vAN+sPL4o8f8ZwS4u3neFS/PPgIEyPAjOT3Rx+hphXuRbR0C
xcg9NF/xUbIz1a0O81Hw+8USWdyB4CQVxN5TGWS0eU0Pzoempf3cbN/Umb4Z+G4nc6TVnd8Gzb/m
jLUUtvYTa++9REXif4S6B/jCByLNDOxPQ28fB9svsp0vyMkxtzExcTVuuXpp4sLmoIH0UguSwDrE
x5YlFE3mWIf1OcehV2K2ErmJpe/bx8/yRbJ+kETpRKlv8D6XTVRQt+Vea+z/vp51qlFOXkOir/4z
HbT597Zit9GKjTATbsheBAZFsu2OizevmfFZYM2WDfnnUnMamAUqxaKqV8sBjWCkxt7aOfu6RZRK
yRL7SOf4zEEAFHMuE+GPm0rxk/sCx2m26oOMj8DaX8AQ/3s2oNdxQ2ddf9myEgQlGerb+eAV5o1a
5LqAFtKIk9Wa2pAmhmbxUpfE38EhmUl+234E/YoxdQLzujssw+CNBvGu8kay1h0rWYV33KjltIfQ
e7KSp27ixG50GEf69G4xAL3n1v6tR1ouThly320lFyJ3Wssf2xL8OdqYZSoLvRF/z5Km2UbN8C+7
b8ffHHM55SASUZgCBIzBG1crH+eNXgiO9efb0rlBQrssgT/gml39YobX1TcOcgos3QpPzFpHw6m7
nZtdH/d+GpWJzbnPCAuEPyDwb4nftuTZZeEacP2zZPvGGROsylXzm+/InIrEx2Ja3Pe03gKZ7kZI
MEAhq8wwkZ0DVk2WDBZxVi/MP0Bbu1xA2CYb9Q2ylABgnzj8gdvoi/JbROGOoF0aSyDWizHV76E4
w1W5PxM9E8680QSTHrxcNxNz0ZO0XGkV3wokatX/5drWMmp+l8vRqoY0zc5+XDjdNgmbt4Aet9cU
9c6Gu3Dz7tgMbXBJsu4EmdbZSNKQLto9ZAd1zOPonSwPo6bwiU+LqjOV94wy+eH4/jYjYrwJiHDM
HyNwJuLi+ht2lBMKmwj6gZG9yecfGBvmcchYOpnyXKAHrE4iJyQuqiqRgL8TOGuMS/BWEZoUV1xT
i+vQiLWtToNOm5bAPioM2s+TcGjzptmZQsmk/bK0sVLLcyXBBxlTMsYnpOl8TnUXNiBNSlg7yoDO
UFvNugB1iR9yTD4Qy+bX5OT2j0OaP1aSMr9OK3fYCxIfl9oUrqQAz1fRc7UOniKSxDClSdhrt/g3
2w+S2xLd1sPkJLh1Z042bk/BdmJgWwfvjpSdD9cA2H0bd9l6f1JmA+XOCcVm8aiqBP+AncvFZkNi
zTCIrFbLsPiUkIMQ8aGtWpFmxbJ/TFaR5RavOE77XkqCyfjvAS1CkGEmQPu45C3KNLMljHvoTGoM
K0WpaO6nYpRhoTp3pB/GFYZH7IyrzaWSCWGVDfmwl8kwuw077+RrBKytLdEvirocgA0XXTckkOP2
YlEVy4zWwy4ozYDcU3sZItQzhUk+XUAtuRyMYQaD+kMmv3R18LAiwcGKLZW5sHBT11dPSGdWpJPQ
JUoI6scMIZZkhWcAd6RdfSUidOpWtiNkDD3wRwbkGsFBwFVW3fXckKO7AQMpCwqeAZq7xzyIDvYO
wNsir/tIa51q0hqSvHP2aaht0TF52ZHQAl11hXQfGtlSMcfrCP3EXGW7Dyrjtk0bPO+U5jyHiztH
b6HKhOdFZarKHPuzQpOYGb4fVlcRAYz4ujhTcfBZOB50NCcympkfCerHKuQkjR7CtJCU/FuOJWqA
LJhIn6vd5ZBZsZKQZfz/Vfi4D8HtvIAg7efEMwCF4sZoWND5Q8XUITLBQ1vm38m7jGV5WooUzmA/
YYHZ5gNMKTNI2rjx6dOapKVN2kwpUgmnqIEw6NLjCZDHmJuvFzqFI6E12fndcObS1LF/VMSrKmhD
F0RLzCARmlpQ8YQaGv3aF/i+jmYcVLvf353fL9w1QVKn+8/5CDSVzjE423D4nIBfbngJneJS3+2z
duSI7FHGEzdj93raYGcZe43fEhZ1dIF9H50A84Rix/gVFWv3NhB/Tcjk2f8AmFp/M47dxGIRkmOX
EQj3EEWq0HXDR1iUyf6YMizK70jMfZ1r6iOGMZYy4g93/e3FBklX7CleETlXaDWS7BC243ka5P7M
jhlhSxTflKC6x9toDQDhWVTQOhN24qUSYugdEru8c0ju8NYZvhRSYvCgnPo5M6tq9hAZ+zBFGOgR
wA3czXQUG4Liq0Gt+Npgd9LUYwhQFo8ahyVu35826rbZybwbX3HGwBadXf5m+yGOmAKPzhu7h96x
FoFUeJKhCU6hlBeCj9IPG9Q+DiRvBBrlgGi/SsjEP5HYTGXP3XLdza4E5gaOqj1PBR/8S6e+NLA7
rQx4Omz8BVG+qVbNVkQpCN+ozDK4WK49yuLCyMWLl6SbOC05dZziMPbSP4IULW9bK/o/Sac8rZtn
QbhQojrvXv7qj6bzy9mUuWQHF8m0ZR9T2hqwAx0vVEpoWU2qRpp30md7+/4WU6ddq0mn3zNwdAa6
nhI/Qrga2D7peVuYaFKYg+iC9soZccRmUDVi5AepG8+oGRAEmvIadnS2Orz7J9PcDEaP7/wHqnkT
E4+0+OKo50zH7D9FmjY0+zhOkinkAmoxLI3koQz1AFVoYB3Oc4FJQ1mAjBn5RDxciAall4tcHmph
AHjIjF6/npOI9rqg9Kv3SYDhY8CgNSqexhQSyxe8FRwDncSGYRq9pdL/EepWjjkbvyAfAN296S3M
KggAEB+SdNHvqqstJFzRBc1LY8WkE8ouoHbxa97vRXY+hopaCl37NXjHDseFr9iZruDOXtGtPs5l
//oZT0Gd8qEzmegeShrQFplZCdGwtEHjMVaZOFcaoEri1SYCzZS8vFWuZ31NrfAzbR8yi/zay0qG
DgZ2iLXuVJWE0DwQ5GnozJl06xnXQiEnUhF3Av/XcnvLLupy3IwVDjcpAXsPQNpYgaNm8ZHiukYt
TjNlQxroJDKZKrBQTC7aTDeyTNAdBJfWQ1NWqryxz/tVKNHdHKNjdT5ubWF+moI/KkSkIv0mRI+f
4KJEL5pr3wdRXTuAhP+2qqEHmYoYNjfFikVfcZjHOeFwunZuIlbYHqaAR1zrI6D60OK/DHl6GzRO
7lhOolznbM00mA8FGOjesVn4WR79qgO7a6W78gkt4OJ5ukjp+CiX8uTm/NA//4Ep7QF6JdB9q0aS
7uYdsBb0qpSMfUiT/Ukq/OEbLHBCcTRq+9KqtZA10v0RytoU1K/qdfOhsgSwj89iQAYCmYHreNnH
Pk7yD1F+7ZAhRvP8GMu/DGcDO6d/+k2eACv9mZT5yr4xzskXlgzrdBCD36hL5KdZSP7IKNIHcHNl
DSW+wenxH1cxlfl5OMfZDkirH/RR1FQnuVJnngBYHPlv3JHuQUqE0ZF70K4hSKYYi3B6t/ldaCNh
WVGOdbM1SO4fwlxXL9M1AmCMX7zOaQi6EkXzzWvmaHmRtYeuvi1xX/byx+rII7a6qdzETqMkvlln
n/2UCz1AFSzQjVka0eJ3b9VVDJDQ4RQhQ15cM9IeCsvqxd2WlQCLXt08AUGfHZWCjHdzmmgkrlG3
e6pKulOVGc5VwSWWbnkxeqXfpzvVQN7XZeOboQn2IuyNvWkdNmqgn0tQhFNeIanvT/GiJ0HmBuMZ
9/65RLl7uMHcKe2Wr12VGmVDyDTNZfN5V4YZwESdWABbU6vztTH7VyNenpCD/ZFUbglx2Dc+7hyo
ljr3KnNPsq0hV/9wB5WoXClZxy1KSu2ofTRwfSQi7+G6AddDAeGKRl+oVQOvWevsUzoKJBpz2q8r
7aJoFF3U0JYvZVVFRRSw3SEVeG3hpUBcAQzJFFqLweGy2vP/FFryOcmCOC89TEVYMm5at/r4uGOY
gxSUhg6RaSAuxyQR+nKXbKjwJ0rA/P9lhNgMIQ8/lqKrWEINcwADetLUHzzwcq5cgnzq9SoKcKkg
PuSoKNIM7Zt2niydQCACx14PEB8696I+r77o8mWc1zwcMxHSk2C0WnQPAJo1iEIS/0WEJfUg+gGh
QXAe8iirvQme7pLOHHOuphtSfEqf6rXqQsFPj1zB16xcixO3lOJAdW6tjrN0/V8vrSlu3M1intJI
lX4cOJxn7cTy3UrPhSRsOxpQHhbofPKNNaQRPOfzImO8p4ldoWiNK9M2S0yUsln/61pJi7aigg1g
hM5OqMT4KwvBucdfSZDGJ8RpHmpHyBniIvzbbKyiumThPmNvL4H/0NbcQwjl4q1lZfeSoiuiW1YN
k2F+vHcbg+Lrmd14d3249JQ6wdOT2DsvRDDPFwhH9jn5K3DdeEVjJAeHoHnV7wAkZ4QvYIlzU8cC
s8wqUyhmDnKdF4nz3/HafVAoKzRxa8vJV9JaNzIpQa6R4PpMfK2xK23PY+dZbtXshrkNfEap5322
O5W+MaLd/jqts9orI2TZOiRAgYw4YYLoXN4GTjhx51xmj+7R7jHGCQqn6LrEVQyhWxPo+0ztK2QB
vEG3/ieXSJZbijN6TpTMQBH0CuL0uQqNBpgJJXPFWzGK87oQo7gkVY/iEfP+j2vhyl7WaagNDc+J
pZByqjDUoxq3/5pG2G4HFj/+wyIaJtre2+kfm7li5yy6yZC9H+q+85Q3ggS+owE4nuyURPbM/J8D
1Mkfer2p67WoF+l+njAuRp6nIde5H50jf+TlnFJ7dj7hXKPDUOIXEQc2KQ23bJNYbzs6/bpCUZLS
/KDNykC3mrPAuwkxnedbELLh5X9PhG+IQo4KBiLAYBLvpkwryx/+c6iWP0MdYwwWdQNlzjUb6zFZ
xtfyu5jynJuSOtUWBYgxnDL8gssrC7aKybNiwVC0iRGgFUtchhb4vCvFcdR63Coqvmn+IpGC1UDj
iDtZYnh/W6U3ZnueY16l0SbsW8B9iEzO6M/jhFmVOkG4tmmaS4IhIJoSJCu7LKYi/JKrnVUTgCS2
iRj9hq57hJie8ty8PgaUYvMtILC9g65OF0+m41kFH4V35QzagJIhWb/BQPSAezL4CPqcVfPjMifT
p6V2xXY3uUPVVAMbyUQTXe2hPWeem0gAVxx0A8OoTMz3oTY9Eg4y+KbM7rccywEmWVGqJU1/BA+5
hvkrvh9NOuCa+pc9W7WgIP4U4cUEgsKPae2Dz8D/izCVCT1Ffv+jwqjnK5wg4N6gEQmqvl9n7ME1
8IVw3qaE2GLoiA0EsN8SqeGDmQ5eOY0unGvarzyaJ9+DqjqMbZYO3bpr7sdB+ZwGKzBfxULPLKWh
qi4XbcaEpsyBC4uVVC4650BIUJ3LtsWoJ6WdHaDGRaiYCAaeTf5cs4tkZlZI7ND6XIT738HnO53P
raCskxAjLHW3pCT+na42X+Nc2zZCJktIjPV9vUvxlKup2OZxbVON8b5ddg20kSM3GCZcOlUjDWD4
hluKs6pY7/hpxVCoIZy1u1UqYeAknkKqlNrT+p7rjw9HfQS19efLUbcDODM4GZwtP1qijVXxVMzj
0dbD3fc/7lyRhY1gV4W/YP+y816lRKLfckhCtFB2ceq375fIds+HRqMQQp+3xGKPt1pgEX15V1ZO
4A409Mdqgn4D3cOSfo1SmgqHcTTT4qgIMT5rVACDk3DaHu8NYTJFWkM0uAm/W6CZyfty1/zirW5S
EBGBWTTk8QpMXaqtIT+SEVYj7PpGt4gCp0+Y1FjhP+JN6FgMKtM3aAjfK8+jn3lrCU9YB7WyFJ8O
pVupNv+2vuMSrmRx7tTcvD0NxtzU7UxQHWOTSRDA6cGh5Va3hdeDLiy9NQsdrF+C3XVnmMZveXak
hJXury9lmwuCsfX2YJcT4WxCshnMnptMoktyMixUIP6KKEn0S74GqhRvlWIbCOrsuR44vaGP9HfD
ylaPsFHGfzIMD30kRu981jBtX1v8bRK1Of9DoL9W4exb8ViaA37nsevcLAcBKeM5LnGAtmdUHkzg
8T7GEblSbuCRxdUxNWNj1LagRugvJ/ELYptjU3NcMVrfeWbsgEop7/6glwofBO5n3BlXe83qe6Uu
zLCt1RHh2XnO7lEF+K80CcufmJfgEgkFvwNIcJpkRHzrSucwXhoWWCseUMZ6pvwVpxpfpj7GLWRN
SO0Ai1D8D0AfWQxzQgoRty5Tx1TttNtufuTxV/TfXuKUWa+rbei7JuBL4gESmEOecV3+ngw0hNE0
2E8SQdT8JJnToRzCf3GQIBXLGmAQiTmhYhHRM7aZmCGe0mVYL/0b7cpQ5PQEObYKxSW0RdMQ3fXE
MGh3IJWIOVl3ANBxsPU+E3U7fVYc28LvTwNCzYeiW4cl4bp53f++fuNiRL+SSrRx5ysAFvor0ats
yma3/Fe4kaTOncKlcpI6vKXrW9MWrdTeJ1H2x0jYO84oIYtnO+hUpaf1HrmMAus03++llgiG+yIJ
3cpG4E+xFDgFs+MWKOL7+khzfpTmhw8x2LSoMnrq3Qjr8FcUKRTt+yJBELuPx/T/h18EK+gQScfT
cxrYLqP0ejDEemLcIjlxWn9DO/WeWw9Nu38d1ndQ44AJ2JcQ2LqbFPkejr8GkpeXaMnu8gZPoTL8
fx4lGaf27SCsX/h170tmL2QmMdVIwL8cfa75dINrKeThC9W5C4kDyrpKkisXL6hRQ9nUDYdILYk0
suWBz4K13fHx1xSQHIr2UslOri8bd06kcq48G7y+nLf+clQfBC0zwIx2dtUBn5aCm5jwlgpV0kRN
scCeSrGEa0QHnFgJLZUu1Y6j5XFP4j1/uAkLoJOmObyfWdTUL0yaBxM4mXcwbbzTPXLJX/AAExc1
WBEsjXGg0WY+usAtXZYXLtpJVzr7COG/ljnHPKTUB6WVgzL3yBR0JN+Y4TSaQHWH6IkMV8YLcg74
sw9b8HdOcw3ZViii0DP/
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
c9vsW5JBCvThyxOUH2PprRXrwDWuKZW/Q7qPv429HnbShw4Uk66yycd+J5tES7AzUCyGeanqADbi
t/NXtBFOdg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
THl1Z3bcMS4H5t6D0G+kJ/FC2Y9oXN8UuO5gTyqyx046tFrVCFbF7b10tz4zI+nryigVgXDuQjpn
REJa68sEKDIsGl5JYzOYVe9IZ30LgoXUIOey68bvuu3Fnu8lEQh/WChcCnbyekJTFEdRaUW6S2O+
5xce7Ha8Gv7YClnhp04=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
KL9gEW9UR9bJ2V+rRImGqHBVYgwBOrGPetNJZ9L5EOgu04h1LECL47Zq26De2Obbv4OkIEGfGFbZ
muWpwFGMSP/qDDeS04mLx/tWX4SnYgQRVyk8AGGlepDKbn1R0w9YaYChqwaqdh3fMk+xJZbtgoWp
4ejGlCOtRuSFxFcOTPGLnPLr5saG0n7SH0iOlkdKRcxP8k1FnXr8kYqxu6g0r1ZNWNYlDcRB7pBC
lrlL52/HTgYUGboGp0/wpS3BU8yKiMyKpm/Nc0Q701u3QL3zraihgQqtTSzkLZnBFXKNrCd6K2Zb
gw1krcKarckcDY4W+Jw/vlWaBMsrX/8GffFxsQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
I9+ICDzIgzYMfdI9n5+7cSfa+M9K8Q9HlZVHvp38kWsb+jUXV67Oh07GXgNqpn7RlOPdQSyhyXf6
AZH+fL8ycTHV0MoCLtaJieiw5P4E1Pm7Fdq2uCENFjt8u7I2RH9/lcoRh4KurkxCVCe86Dtk1oWB
bacFgZX+QZ+FCZn+6nI=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
pyasIdA/E1o2abIoUkxhLYQwvp5B9zIwQEm/+EGPR3u06a5SPM2I1E62WIwSJ7iN/bqdRmd03/xZ
zjSCCiFFaRUwQmJJ5xZcUnw15IQqIRd/WQQ56gktCUx2rEJwJ4BBJrhOQsbLLnEDNgJUxpYVfXAy
ix6G1h7tonYt5pC9K8hh3YN8608V5TRujBAEsLi+3lAMFCMgjGqgS6cpljhaHIjuKULPnRb7+Rll
fIJqbRqDAQ0ubxbSrdH7w8ZIqWH5mG/hnLBefDFlIZJh/pHjOIOLGPh9RyUn99n5SKT8NF75l8Mj
ggHTuLkcPsoN2kGMWMDxZ752vU2X39SpzveZtA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6000)
`protect data_block
TxmWdQtoCa72lA+PjmaVWNzez4mZxpW7I8VWfPbcGicMeEL2MwwAS4LUnoxwA9Uhmm5ot+LUjCmv
eDB7SAvMi2HMKnvkVOM6GyDSV3gAIeNsWXHPVpwGySt8l+veQ87+wCB2U0M2AjDDPy5G0YrHv7SV
3hwskYbNG5I35qHpm3MFyP0vEDTw2Fa861T3JSQElQvkHyiJtc1mCK8c+3Xwu2sX2tdUav9HJ/w9
ZeB6TCc1chmVdFw//m3On54B7bmWN9Zebwnw5VQGvAYNMLyudEgVjYJwsgwTfKt7pZ93DMozPsEb
mZW50l08EWStM63eu5CZx2XBarUhqb053q94CYABjIYCo57BhlAgWgkKSS2f5WQW0T4Jc3rrfKN3
sLKdFCmMZrqfr5pgPkkX+nvfqUlvDaNXr1tYdehUiUwQuHo0YktKmaf9b7G08xq2O+KihhDW8bJL
JxvKd5VOwLu5iT8eD4v22BpAwoc1xjn98yzfCmkC27huSSupAOcJw+AP5OFOkoRBWp079P45WQOz
o/hkgLdSsXaQUNYZhi2sEsKzRYQK+hrxajBLt5oHEBJbf7wIUiygAcdixuv12Dd/r5+WcBPm4SJO
EmUMYhUA15hnaNALn0dGvrSkIP5NslL6zWERTi9G/OFbUb1a799ztM/HsHegshJwRbCxHi2xIz16
z35IEn7CVUoWVCtQlpFDFlgUxi9BshVVTf/6EayE6uFNg6KX4HhvSmuwujoT0wRmbQZ3Ia7MGLGS
uyxfc7BJHDjz5MQ3coKQd51qJqfHTeRGTAeQ9SzqASPY8ebTFMlp1vqFRPbOq6KsrHx7WT75pRyg
8foHSrwUrb/E8FbwnLnYe9umPzKEjGCTo6eXMWpVIyglksrRWrHIM0OOlju1rUPs5g8RID/+aWQl
krguToDL3/FbiBN/OpIpzzDFYSMSIhrq7W2k0D6X90tLdM86lV4BCaIna6MHSucetYvc6zrnoGID
ZdXRDktS64+FUnZpecuBvQtan+SwG5Rvqymh0vB5LWrSR34biGzmqqTBL6p0TkGzPJUxr3lqAthc
KMtK1x/EDuNMioKMJR1MutrwOckHFMTYiwMKhxvYePPfxHJAgRzDfDBKJ9KWfOFooBxhHPeirSD7
ApSD9kcvPzrCWtqheCAAtKvcZP69vAN+sPL4o8f8ZwS4u3neFS/PPgIEyPAjOT3Rx+hphXuRbR0C
xcg9NF/xUbIz1a0O81Hw+8USWdyB4CQVxN5TGWS0eU0Pzoempf3cbN/Umb4Z+G4nc6TVnd8Gzb/m
jLUUtvYTa++9REXif4S6B/jCByLNDOxPQ28fB9svsp0vyMkxtzExcTVuuXpp4sLmoIH0UguSwDrE
x5YlFE3mWIf1OcehV2K2ErmJpe/bx8/yRbJ+kETpRKlv8D6XTVRQt+Vea+z/vp51qlFOXkOir/4z
HbT597Zit9GKjTATbsheBAZFsu2OizevmfFZYM2WDfnnUnMamAUqxaKqV8sBjWCkxt7aOfu6RZRK
yRL7SOf4zEEAFHMuE+GPm0rxk/sCx2m26oOMj8DaX8AQ/3s2oNdxQ2ddf9myEgQlGerb+eAV5o1a
5LqAFtKIk9Wa2pAmhmbxUpfE38EhmUl+234E/YoxdQLzujssw+CNBvGu8kay1h0rWYV33KjltIfQ
e7KSp27ixG50GEf69G4xAL3n1v6tR1ouThly320lFyJ3Wssf2xL8OdqYZSoLvRF/z5Km2UbN8C+7
b8ffHHM55SASUZgCBIzBG1crH+eNXgiO9efb0rlBQrssgT/gml39YobX1TcOcgos3QpPzFpHw6m7
nZtdH/d+GpWJzbnPCAuEPyDwb4nftuTZZeEacP2zZPvGGROsylXzm+/InIrEx2Ja3Pe03gKZ7kZI
MEAhq8wwkZ0DVk2WDBZxVi/MP0Bbu1xA2CYb9Q2ylABgnzj8gdvoi/JbROGOoF0aSyDWizHV76E4
w1W5PxM9E8680QSTHrxcNxNz0ZO0XGkV3wokatX/5drWMmp+l8vRqoY0zc5+XDjdNgmbt4Aet9cU
9c6Gu3Dz7tgMbXBJsu4EmdbZSNKQLto9ZAd1zOPonSwPo6bwiU+LqjOV94wy+eH4/jYjYrwJiHDM
HyNwJuLi+ht2lBMKmwj6gZG9yecfGBvmcchYOpnyXKAHrE4iJyQuqiqRgL8TOGuMS/BWEZoUV1xT
i+vQiLWtToNOm5bAPioM2s+TcGjzptmZQsmk/bK0sVLLcyXBBxlTMsYnpOl8TnUXNiBNSlg7yoDO
UFvNugB1iR9yTD4Qy+bX5OT2j0OaP1aSMr9OK3fYCxIfl9oUrqQAz1fRc7UOniKSxDClSdhrt/g3
2w+S2xLd1sPkJLh1Z042bk/BdmJgWwfvjpSdD9cA2H0bd9l6f1JmA+XOCcVm8aiqBP+AncvFZkNi
zTCIrFbLsPiUkIMQ8aGtWpFmxbJ/TFaR5RavOE77XkqCyfjvAS1CkGEmQPu45C3KNLMljHvoTGoM
K0WpaO6nYpRhoTp3pB/GFYZH7IyrzaWSCWGVDfmwl8kwuw077+RrBKytLdEvirocgA0XXTckkOP2
YlEVy4zWwy4ozYDcU3sZItQzhUk+XUAtuRyMYQaD+kMmv3R18LAiwcGKLZW5sHBT11dPSGdWpJPQ
JUoI6scMIZZkhWcAd6RdfSUidOpWtiNkDD3wRwbkGsFBwFVW3fXckKO7AQMpCwqeAZq7xzyIDvYO
wNsir/tIa51q0hqSvHP2aaht0TF52ZHQAl11hXQfGtlSMcfrCP3EXGW7Dyrjtk0bPO+U5jyHiztH
b6HKhOdFZarKHPuzQpOYGb4fVlcRAYz4ujhTcfBZOB50NCcympkfCerHKuQkjR7CtJCU/FuOJWqA
LJhIn6vd5ZBZsZKQZfz/Vfi4D8HtvIAg7efEMwCF4sZoWND5Q8XUITLBQ1vm38m7jGV5WooUzmA/
YYHZ5gNMKTNI2rjx6dOapKVN2kwpUgmnqIEw6NLjCZDHmJuvFzqFI6E12fndcObS1LF/VMSrKmhD
F0RLzCARmlpQ8YQaGv3aF/i+jmYcVLvf353fL9w1QVKn+8/5CDSVzjE423D4nIBfbngJneJS3+2z
duSI7FHGEzdj93raYGcZe43fEhZ1dIF9H50A84Rix/gVFWv3NhB/Tcjk2f8AmFp/M47dxGIRkmOX
EQj3EEWq0HXDR1iUyf6YMizK70jMfZ1r6iOGMZYy4g93/e3FBklX7CleETlXaDWS7BC243ka5P7M
jhlhSxTflKC6x9toDQDhWVTQOhN24qUSYugdEru8c0ju8NYZvhRSYvCgnPo5M6tq9hAZ+zBFGOgR
wA3czXQUG4Liq0Gt+Npgd9LUYwhQFo8ahyVu35826rbZybwbX3HGwBadXf5m+yGOmAKPzhu7h96x
FoFUeJKhCU6hlBeCj9IPG9Q+DiRvBBrlgGi/SsjEP5HYTGXP3XLdza4E5gaOqj1PBR/8S6e+NLA7
rQx4Omz8BVG+qVbNVkQpCN+ozDK4WK49yuLCyMWLl6SbOC05dZziMPbSP4IULW9bK/o/Sac8rZtn
QbhQojrvXv7qj6bzy9mUuWQHF8m0ZR9T2hqwAx0vVEpoWU2qRpp30md7+/4WU6ddq0mn3zNwdAa6
nhI/Qrga2D7peVuYaFKYg+iC9soZccRmUDVi5AepG8+oGRAEmvIadnS2Orz7J9PcDEaP7/wHqnkT
E4+0+OKo50zH7D9FmjY0+zhOkinkAmoxLI3koQz1AFVoYB3Oc4FJQ1mAjBn5RDxciAall4tcHmph
AHjIjF6/npOI9rqg9Kv3SYDhY8CgNSqexhQSyxe8FRwDncSGYRq9pdL/EepWjjkbvyAfAN296S3M
KggAEB+SdNHvqqstJFzRBc1LY8WkE8ouoHbxa97vRXY+hopaCl37NXjHDseFr9iZruDOXtGtPs5l
//oZT0Gd8qEzmegeShrQFplZCdGwtEHjMVaZOFcaoEri1SYCzZS8vFWuZ31NrfAzbR8yi/zay0qG
DgZ2iLXuVJWE0DwQ5GnozJl06xnXQiEnUhF3Av/XcnvLLupy3IwVDjcpAXsPQNpYgaNm8ZHiukYt
TjNlQxroJDKZKrBQTC7aTDeyTNAdBJfWQ1NWqryxz/tVKNHdHKNjdT5ubWF+moI/KkSkIv0mRI+f
4KJEL5pr3wdRXTuAhP+2qqEHmYoYNjfFikVfcZjHOeFwunZuIlbYHqaAR1zrI6D60OK/DHl6GzRO
7lhOolznbM00mA8FGOjesVn4WR79qgO7a6W78gkt4OJ5ukjp+CiX8uTm/NA//4Ep7QF6JdB9q0aS
7uYdsBb0qpSMfUiT/Ukq/OEbLHBCcTRq+9KqtZA10v0RytoU1K/qdfOhsgSwj89iQAYCmYHreNnH
Pk7yD1F+7ZAhRvP8GMu/DGcDO6d/+k2eACv9mZT5yr4xzskXlgzrdBCD36hL5KdZSP7IKNIHcHNl
DSW+wenxH1cxlfl5OMfZDkirH/RR1FQnuVJnngBYHPlv3JHuQUqE0ZF70K4hSKYYi3B6t/ldaCNh
WVGOdbM1SO4fwlxXL9M1AmCMX7zOaQi6EkXzzWvmaHmRtYeuvi1xX/byx+rII7a6qdzETqMkvlln
n/2UCz1AFSzQjVka0eJ3b9VVDJDQ4RQhQ15cM9IeCsvqxd2WlQCLXt08AUGfHZWCjHdzmmgkrlG3
e6pKulOVGc5VwSWWbnkxeqXfpzvVQN7XZeOboQn2IuyNvWkdNmqgn0tQhFNeIanvT/GiJ0HmBuMZ
9/65RLl7uMHcKe2Wr12VGmVDyDTNZfN5V4YZwESdWABbU6vztTH7VyNenpCD/ZFUbglx2Dc+7hyo
ljr3KnNPsq0hV/9wB5WoXClZxy1KSu2ofTRwfSQi7+G6AddDAeGKRl+oVQOvWevsUzoKJBpz2q8r
7aJoFF3U0JYvZVVFRRSw3SEVeG3hpUBcAQzJFFqLweGy2vP/FFryOcmCOC89TEVYMm5at/r4uGOY
gxSUhg6RaSAuxyQR+nKXbKjwJ0rA/P9lhNgMIQ8/lqKrWEINcwADetLUHzzwcq5cgnzq9SoKcKkg
PuSoKNIM7Zt2niydQCACx14PEB8696I+r77o8mWc1zwcMxHSk2C0WnQPAJo1iEIS/0WEJfUg+gGh
QXAe8iirvQme7pLOHHOuphtSfEqf6rXqQsFPj1zB16xcixO3lOJAdW6tjrN0/V8vrSlu3M1intJI
lX4cOJxn7cTy3UrPhSRsOxpQHhbofPKNNaQRPOfzImO8p4ldoWiNK9M2S0yUsln/61pJi7aigg1g
hM5OqMT4KwvBucdfSZDGJ8RpHmpHyBniIvzbbKyiumThPmNvL4H/0NbcQwjl4q1lZfeSoiuiW1YN
k2F+vHcbg+Lrmd14d3249JQ6wdOT2DsvRDDPFwhH9jn5K3DdeEVjJAeHoHnV7wAkZ4QvYIlzU8cC
s8wqUyhmDnKdF4nz3/HafVAoKzRxa8vJV9JaNzIpQa6R4PpMfK2xK23PY+dZbtXshrkNfEap5322
O5W+MaLd/jqts9orI2TZOiRAgYw4YYLoXN4GTjhx51xmj+7R7jHGCQqn6LrEVQyhWxPo+0ztK2QB
vEG3/ieXSJZbijN6TpTMQBH0CuL0uQqNBpgJJXPFWzGK87oQo7gkVY/iEfP+j2vhyl7WaagNDc+J
pZByqjDUoxq3/5pG2G4HFj/+wyIaJtre2+kfm7li5yy6yZC9H+q+85Q3ggS+owE4nuyURPbM/J8D
1Mkfer2p67WoF+l+njAuRp6nIde5H50jf+TlnFJ7dj7hXKPDUOIXEQc2KQ23bJNYbzs6/bpCUZLS
/KDNykC3mrPAuwkxnedbELLh5X9PhG+IQo4KBiLAYBLvpkwryx/+c6iWP0MdYwwWdQNlzjUb6zFZ
xtfyu5jynJuSOtUWBYgxnDL8gssrC7aKybNiwVC0iRGgFUtchhb4vCvFcdR63Coqvmn+IpGC1UDj
iDtZYnh/W6U3ZnueY16l0SbsW8B9iEzO6M/jhFmVOkG4tmmaS4IhIJoSJCu7LKYi/JKrnVUTgCS2
iRj9hq57hJie8ty8PgaUYvMtILC9g65OF0+m41kFH4V35QzagJIhWb/BQPSAezL4CPqcVfPjMifT
p6V2xXY3uUPVVAMbyUQTXe2hPWeem0gAVxx0A8OoTMz3oTY9Eg4y+KbM7rccywEmWVGqJU1/BA+5
hvkrvh9NOuCa+pc9W7WgIP4U4cUEgsKPae2Dz8D/izCVCT1Ffv+jwqjnK5wg4N6gEQmqvl9n7ME1
8IVw3qaE2GLoiA0EsN8SqeGDmQ5eOY0unGvarzyaJ9+DqjqMbZYO3bpr7sdB+ZwGKzBfxULPLKWh
qi4XbcaEpsyBC4uVVC4650BIUJ3LtsWoJ6WdHaDGRaiYCAaeTf5cs4tkZlZI7ND6XIT738HnO53P
raCskxAjLHW3pCT+na42X+Nc2zZCJktIjPV9vUvxlKup2OZxbVON8b5ddg20kSM3GCZcOlUjDWD4
hluKs6pY7/hpxVCoIZy1u1UqYeAknkKqlNrT+p7rjw9HfQS19efLUbcDODM4GZwtP1qijVXxVMzj
0dbD3fc/7lyRhY1gV4W/YP+y816lRKLfckhCtFB2ceq375fIds+HRqMQQp+3xGKPt1pgEX15V1ZO
4A409Mdqgn4D3cOSfo1SmgqHcTTT4qgIMT5rVACDk3DaHu8NYTJFWkM0uAm/W6CZyfty1/zirW5S
EBGBWTTk8QpMXaqtIT+SEVYj7PpGt4gCp0+Y1FjhP+JN6FgMKtM3aAjfK8+jn3lrCU9YB7WyFJ8O
pVupNv+2vuMSrmRx7tTcvD0NxtzU7UxQHWOTSRDA6cGh5Va3hdeDLiy9NQsdrF+C3XVnmMZveXak
hJXury9lmwuCsfX2YJcT4WxCshnMnptMoktyMixUIP6KKEn0S74GqhRvlWIbCOrsuR44vaGP9HfD
ylaPsFHGfzIMD30kRu981jBtX1v8bRK1Of9DoL9W4exb8ViaA37nsevcLAcBKeM5LnGAtmdUHkzg
8T7GEblSbuCRxdUxNWNj1LagRugvJ/ELYptjU3NcMVrfeWbsgEop7/6glwofBO5n3BlXe83qe6Uu
zLCt1RHh2XnO7lEF+K80CcufmJfgEgkFvwNIcJpkRHzrSucwXhoWWCseUMZ6pvwVpxpfpj7GLWRN
SO0Ai1D8D0AfWQxzQgoRty5Tx1TttNtufuTxV/TfXuKUWa+rbei7JuBL4gESmEOecV3+ngw0hNE0
2E8SQdT8JJnToRzCf3GQIBXLGmAQiTmhYhHRM7aZmCGe0mVYL/0b7cpQ5PQEObYKxSW0RdMQ3fXE
MGh3IJWIOVl3ANBxsPU+E3U7fVYc28LvTwNCzYeiW4cl4bp53f++fuNiRL+SSrRx5ysAFvor0ats
yma3/Fe4kaTOncKlcpI6vKXrW9MWrdTeJ1H2x0jYO84oIYtnO+hUpaf1HrmMAus03++llgiG+yIJ
3cpG4E+xFDgFs+MWKOL7+khzfpTmhw8x2LSoMnrq3Qjr8FcUKRTt+yJBELuPx/T/h18EK+gQScfT
cxrYLqP0ejDEemLcIjlxWn9DO/WeWw9Nu38d1ndQ44AJ2JcQ2LqbFPkejr8GkpeXaMnu8gZPoTL8
fx4lGaf27SCsX/h170tmL2QmMdVIwL8cfa75dINrKeThC9W5C4kDyrpKkisXL6hRQ9nUDYdILYk0
suWBz4K13fHx1xSQHIr2UslOri8bd06kcq48G7y+nLf+clQfBC0zwIx2dtUBn5aCm5jwlgpV0kRN
scCeSrGEa0QHnFgJLZUu1Y6j5XFP4j1/uAkLoJOmObyfWdTUL0yaBxM4mXcwbbzTPXLJX/AAExc1
WBEsjXGg0WY+usAtXZYXLtpJVzr7COG/ljnHPKTUB6WVgzL3yBR0JN+Y4TSaQHWH6IkMV8YLcg74
sw9b8HdOcw3ZViii0DP/
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
c9vsW5JBCvThyxOUH2PprRXrwDWuKZW/Q7qPv429HnbShw4Uk66yycd+J5tES7AzUCyGeanqADbi
t/NXtBFOdg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
THl1Z3bcMS4H5t6D0G+kJ/FC2Y9oXN8UuO5gTyqyx046tFrVCFbF7b10tz4zI+nryigVgXDuQjpn
REJa68sEKDIsGl5JYzOYVe9IZ30LgoXUIOey68bvuu3Fnu8lEQh/WChcCnbyekJTFEdRaUW6S2O+
5xce7Ha8Gv7YClnhp04=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
KL9gEW9UR9bJ2V+rRImGqHBVYgwBOrGPetNJZ9L5EOgu04h1LECL47Zq26De2Obbv4OkIEGfGFbZ
muWpwFGMSP/qDDeS04mLx/tWX4SnYgQRVyk8AGGlepDKbn1R0w9YaYChqwaqdh3fMk+xJZbtgoWp
4ejGlCOtRuSFxFcOTPGLnPLr5saG0n7SH0iOlkdKRcxP8k1FnXr8kYqxu6g0r1ZNWNYlDcRB7pBC
lrlL52/HTgYUGboGp0/wpS3BU8yKiMyKpm/Nc0Q701u3QL3zraihgQqtTSzkLZnBFXKNrCd6K2Zb
gw1krcKarckcDY4W+Jw/vlWaBMsrX/8GffFxsQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
I9+ICDzIgzYMfdI9n5+7cSfa+M9K8Q9HlZVHvp38kWsb+jUXV67Oh07GXgNqpn7RlOPdQSyhyXf6
AZH+fL8ycTHV0MoCLtaJieiw5P4E1Pm7Fdq2uCENFjt8u7I2RH9/lcoRh4KurkxCVCe86Dtk1oWB
bacFgZX+QZ+FCZn+6nI=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
pyasIdA/E1o2abIoUkxhLYQwvp5B9zIwQEm/+EGPR3u06a5SPM2I1E62WIwSJ7iN/bqdRmd03/xZ
zjSCCiFFaRUwQmJJ5xZcUnw15IQqIRd/WQQ56gktCUx2rEJwJ4BBJrhOQsbLLnEDNgJUxpYVfXAy
ix6G1h7tonYt5pC9K8hh3YN8608V5TRujBAEsLi+3lAMFCMgjGqgS6cpljhaHIjuKULPnRb7+Rll
fIJqbRqDAQ0ubxbSrdH7w8ZIqWH5mG/hnLBefDFlIZJh/pHjOIOLGPh9RyUn99n5SKT8NF75l8Mj
ggHTuLkcPsoN2kGMWMDxZ752vU2X39SpzveZtA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6000)
`protect data_block
TxmWdQtoCa72lA+PjmaVWNzez4mZxpW7I8VWfPbcGicMeEL2MwwAS4LUnoxwA9Uhmm5ot+LUjCmv
eDB7SAvMi2HMKnvkVOM6GyDSV3gAIeNsWXHPVpwGySt8l+veQ87+wCB2U0M2AjDDPy5G0YrHv7SV
3hwskYbNG5I35qHpm3MFyP0vEDTw2Fa861T3JSQElQvkHyiJtc1mCK8c+3Xwu2sX2tdUav9HJ/w9
ZeB6TCc1chmVdFw//m3On54B7bmWN9Zebwnw5VQGvAYNMLyudEgVjYJwsgwTfKt7pZ93DMozPsEb
mZW50l08EWStM63eu5CZx2XBarUhqb053q94CYABjIYCo57BhlAgWgkKSS2f5WQW0T4Jc3rrfKN3
sLKdFCmMZrqfr5pgPkkX+nvfqUlvDaNXr1tYdehUiUwQuHo0YktKmaf9b7G08xq2O+KihhDW8bJL
JxvKd5VOwLu5iT8eD4v22BpAwoc1xjn98yzfCmkC27huSSupAOcJw+AP5OFOkoRBWp079P45WQOz
o/hkgLdSsXaQUNYZhi2sEsKzRYQK+hrxajBLt5oHEBJbf7wIUiygAcdixuv12Dd/r5+WcBPm4SJO
EmUMYhUA15hnaNALn0dGvrSkIP5NslL6zWERTi9G/OFbUb1a799ztM/HsHegshJwRbCxHi2xIz16
z35IEn7CVUoWVCtQlpFDFlgUxi9BshVVTf/6EayE6uFNg6KX4HhvSmuwujoT0wRmbQZ3Ia7MGLGS
uyxfc7BJHDjz5MQ3coKQd51qJqfHTeRGTAeQ9SzqASPY8ebTFMlp1vqFRPbOq6KsrHx7WT75pRyg
8foHSrwUrb/E8FbwnLnYe9umPzKEjGCTo6eXMWpVIyglksrRWrHIM0OOlju1rUPs5g8RID/+aWQl
krguToDL3/FbiBN/OpIpzzDFYSMSIhrq7W2k0D6X90tLdM86lV4BCaIna6MHSucetYvc6zrnoGID
ZdXRDktS64+FUnZpecuBvQtan+SwG5Rvqymh0vB5LWrSR34biGzmqqTBL6p0TkGzPJUxr3lqAthc
KMtK1x/EDuNMioKMJR1MutrwOckHFMTYiwMKhxvYePPfxHJAgRzDfDBKJ9KWfOFooBxhHPeirSD7
ApSD9kcvPzrCWtqheCAAtKvcZP69vAN+sPL4o8f8ZwS4u3neFS/PPgIEyPAjOT3Rx+hphXuRbR0C
xcg9NF/xUbIz1a0O81Hw+8USWdyB4CQVxN5TGWS0eU0Pzoempf3cbN/Umb4Z+G4nc6TVnd8Gzb/m
jLUUtvYTa++9REXif4S6B/jCByLNDOxPQ28fB9svsp0vyMkxtzExcTVuuXpp4sLmoIH0UguSwDrE
x5YlFE3mWIf1OcehV2K2ErmJpe/bx8/yRbJ+kETpRKlv8D6XTVRQt+Vea+z/vp51qlFOXkOir/4z
HbT597Zit9GKjTATbsheBAZFsu2OizevmfFZYM2WDfnnUnMamAUqxaKqV8sBjWCkxt7aOfu6RZRK
yRL7SOf4zEEAFHMuE+GPm0rxk/sCx2m26oOMj8DaX8AQ/3s2oNdxQ2ddf9myEgQlGerb+eAV5o1a
5LqAFtKIk9Wa2pAmhmbxUpfE38EhmUl+234E/YoxdQLzujssw+CNBvGu8kay1h0rWYV33KjltIfQ
e7KSp27ixG50GEf69G4xAL3n1v6tR1ouThly320lFyJ3Wssf2xL8OdqYZSoLvRF/z5Km2UbN8C+7
b8ffHHM55SASUZgCBIzBG1crH+eNXgiO9efb0rlBQrssgT/gml39YobX1TcOcgos3QpPzFpHw6m7
nZtdH/d+GpWJzbnPCAuEPyDwb4nftuTZZeEacP2zZPvGGROsylXzm+/InIrEx2Ja3Pe03gKZ7kZI
MEAhq8wwkZ0DVk2WDBZxVi/MP0Bbu1xA2CYb9Q2ylABgnzj8gdvoi/JbROGOoF0aSyDWizHV76E4
w1W5PxM9E8680QSTHrxcNxNz0ZO0XGkV3wokatX/5drWMmp+l8vRqoY0zc5+XDjdNgmbt4Aet9cU
9c6Gu3Dz7tgMbXBJsu4EmdbZSNKQLto9ZAd1zOPonSwPo6bwiU+LqjOV94wy+eH4/jYjYrwJiHDM
HyNwJuLi+ht2lBMKmwj6gZG9yecfGBvmcchYOpnyXKAHrE4iJyQuqiqRgL8TOGuMS/BWEZoUV1xT
i+vQiLWtToNOm5bAPioM2s+TcGjzptmZQsmk/bK0sVLLcyXBBxlTMsYnpOl8TnUXNiBNSlg7yoDO
UFvNugB1iR9yTD4Qy+bX5OT2j0OaP1aSMr9OK3fYCxIfl9oUrqQAz1fRc7UOniKSxDClSdhrt/g3
2w+S2xLd1sPkJLh1Z042bk/BdmJgWwfvjpSdD9cA2H0bd9l6f1JmA+XOCcVm8aiqBP+AncvFZkNi
zTCIrFbLsPiUkIMQ8aGtWpFmxbJ/TFaR5RavOE77XkqCyfjvAS1CkGEmQPu45C3KNLMljHvoTGoM
K0WpaO6nYpRhoTp3pB/GFYZH7IyrzaWSCWGVDfmwl8kwuw077+RrBKytLdEvirocgA0XXTckkOP2
YlEVy4zWwy4ozYDcU3sZItQzhUk+XUAtuRyMYQaD+kMmv3R18LAiwcGKLZW5sHBT11dPSGdWpJPQ
JUoI6scMIZZkhWcAd6RdfSUidOpWtiNkDD3wRwbkGsFBwFVW3fXckKO7AQMpCwqeAZq7xzyIDvYO
wNsir/tIa51q0hqSvHP2aaht0TF52ZHQAl11hXQfGtlSMcfrCP3EXGW7Dyrjtk0bPO+U5jyHiztH
b6HKhOdFZarKHPuzQpOYGb4fVlcRAYz4ujhTcfBZOB50NCcympkfCerHKuQkjR7CtJCU/FuOJWqA
LJhIn6vd5ZBZsZKQZfz/Vfi4D8HtvIAg7efEMwCF4sZoWND5Q8XUITLBQ1vm38m7jGV5WooUzmA/
YYHZ5gNMKTNI2rjx6dOapKVN2kwpUgmnqIEw6NLjCZDHmJuvFzqFI6E12fndcObS1LF/VMSrKmhD
F0RLzCARmlpQ8YQaGv3aF/i+jmYcVLvf353fL9w1QVKn+8/5CDSVzjE423D4nIBfbngJneJS3+2z
duSI7FHGEzdj93raYGcZe43fEhZ1dIF9H50A84Rix/gVFWv3NhB/Tcjk2f8AmFp/M47dxGIRkmOX
EQj3EEWq0HXDR1iUyf6YMizK70jMfZ1r6iOGMZYy4g93/e3FBklX7CleETlXaDWS7BC243ka5P7M
jhlhSxTflKC6x9toDQDhWVTQOhN24qUSYugdEru8c0ju8NYZvhRSYvCgnPo5M6tq9hAZ+zBFGOgR
wA3czXQUG4Liq0Gt+Npgd9LUYwhQFo8ahyVu35826rbZybwbX3HGwBadXf5m+yGOmAKPzhu7h96x
FoFUeJKhCU6hlBeCj9IPG9Q+DiRvBBrlgGi/SsjEP5HYTGXP3XLdza4E5gaOqj1PBR/8S6e+NLA7
rQx4Omz8BVG+qVbNVkQpCN+ozDK4WK49yuLCyMWLl6SbOC05dZziMPbSP4IULW9bK/o/Sac8rZtn
QbhQojrvXv7qj6bzy9mUuWQHF8m0ZR9T2hqwAx0vVEpoWU2qRpp30md7+/4WU6ddq0mn3zNwdAa6
nhI/Qrga2D7peVuYaFKYg+iC9soZccRmUDVi5AepG8+oGRAEmvIadnS2Orz7J9PcDEaP7/wHqnkT
E4+0+OKo50zH7D9FmjY0+zhOkinkAmoxLI3koQz1AFVoYB3Oc4FJQ1mAjBn5RDxciAall4tcHmph
AHjIjF6/npOI9rqg9Kv3SYDhY8CgNSqexhQSyxe8FRwDncSGYRq9pdL/EepWjjkbvyAfAN296S3M
KggAEB+SdNHvqqstJFzRBc1LY8WkE8ouoHbxa97vRXY+hopaCl37NXjHDseFr9iZruDOXtGtPs5l
//oZT0Gd8qEzmegeShrQFplZCdGwtEHjMVaZOFcaoEri1SYCzZS8vFWuZ31NrfAzbR8yi/zay0qG
DgZ2iLXuVJWE0DwQ5GnozJl06xnXQiEnUhF3Av/XcnvLLupy3IwVDjcpAXsPQNpYgaNm8ZHiukYt
TjNlQxroJDKZKrBQTC7aTDeyTNAdBJfWQ1NWqryxz/tVKNHdHKNjdT5ubWF+moI/KkSkIv0mRI+f
4KJEL5pr3wdRXTuAhP+2qqEHmYoYNjfFikVfcZjHOeFwunZuIlbYHqaAR1zrI6D60OK/DHl6GzRO
7lhOolznbM00mA8FGOjesVn4WR79qgO7a6W78gkt4OJ5ukjp+CiX8uTm/NA//4Ep7QF6JdB9q0aS
7uYdsBb0qpSMfUiT/Ukq/OEbLHBCcTRq+9KqtZA10v0RytoU1K/qdfOhsgSwj89iQAYCmYHreNnH
Pk7yD1F+7ZAhRvP8GMu/DGcDO6d/+k2eACv9mZT5yr4xzskXlgzrdBCD36hL5KdZSP7IKNIHcHNl
DSW+wenxH1cxlfl5OMfZDkirH/RR1FQnuVJnngBYHPlv3JHuQUqE0ZF70K4hSKYYi3B6t/ldaCNh
WVGOdbM1SO4fwlxXL9M1AmCMX7zOaQi6EkXzzWvmaHmRtYeuvi1xX/byx+rII7a6qdzETqMkvlln
n/2UCz1AFSzQjVka0eJ3b9VVDJDQ4RQhQ15cM9IeCsvqxd2WlQCLXt08AUGfHZWCjHdzmmgkrlG3
e6pKulOVGc5VwSWWbnkxeqXfpzvVQN7XZeOboQn2IuyNvWkdNmqgn0tQhFNeIanvT/GiJ0HmBuMZ
9/65RLl7uMHcKe2Wr12VGmVDyDTNZfN5V4YZwESdWABbU6vztTH7VyNenpCD/ZFUbglx2Dc+7hyo
ljr3KnNPsq0hV/9wB5WoXClZxy1KSu2ofTRwfSQi7+G6AddDAeGKRl+oVQOvWevsUzoKJBpz2q8r
7aJoFF3U0JYvZVVFRRSw3SEVeG3hpUBcAQzJFFqLweGy2vP/FFryOcmCOC89TEVYMm5at/r4uGOY
gxSUhg6RaSAuxyQR+nKXbKjwJ0rA/P9lhNgMIQ8/lqKrWEINcwADetLUHzzwcq5cgnzq9SoKcKkg
PuSoKNIM7Zt2niydQCACx14PEB8696I+r77o8mWc1zwcMxHSk2C0WnQPAJo1iEIS/0WEJfUg+gGh
QXAe8iirvQme7pLOHHOuphtSfEqf6rXqQsFPj1zB16xcixO3lOJAdW6tjrN0/V8vrSlu3M1intJI
lX4cOJxn7cTy3UrPhSRsOxpQHhbofPKNNaQRPOfzImO8p4ldoWiNK9M2S0yUsln/61pJi7aigg1g
hM5OqMT4KwvBucdfSZDGJ8RpHmpHyBniIvzbbKyiumThPmNvL4H/0NbcQwjl4q1lZfeSoiuiW1YN
k2F+vHcbg+Lrmd14d3249JQ6wdOT2DsvRDDPFwhH9jn5K3DdeEVjJAeHoHnV7wAkZ4QvYIlzU8cC
s8wqUyhmDnKdF4nz3/HafVAoKzRxa8vJV9JaNzIpQa6R4PpMfK2xK23PY+dZbtXshrkNfEap5322
O5W+MaLd/jqts9orI2TZOiRAgYw4YYLoXN4GTjhx51xmj+7R7jHGCQqn6LrEVQyhWxPo+0ztK2QB
vEG3/ieXSJZbijN6TpTMQBH0CuL0uQqNBpgJJXPFWzGK87oQo7gkVY/iEfP+j2vhyl7WaagNDc+J
pZByqjDUoxq3/5pG2G4HFj/+wyIaJtre2+kfm7li5yy6yZC9H+q+85Q3ggS+owE4nuyURPbM/J8D
1Mkfer2p67WoF+l+njAuRp6nIde5H50jf+TlnFJ7dj7hXKPDUOIXEQc2KQ23bJNYbzs6/bpCUZLS
/KDNykC3mrPAuwkxnedbELLh5X9PhG+IQo4KBiLAYBLvpkwryx/+c6iWP0MdYwwWdQNlzjUb6zFZ
xtfyu5jynJuSOtUWBYgxnDL8gssrC7aKybNiwVC0iRGgFUtchhb4vCvFcdR63Coqvmn+IpGC1UDj
iDtZYnh/W6U3ZnueY16l0SbsW8B9iEzO6M/jhFmVOkG4tmmaS4IhIJoSJCu7LKYi/JKrnVUTgCS2
iRj9hq57hJie8ty8PgaUYvMtILC9g65OF0+m41kFH4V35QzagJIhWb/BQPSAezL4CPqcVfPjMifT
p6V2xXY3uUPVVAMbyUQTXe2hPWeem0gAVxx0A8OoTMz3oTY9Eg4y+KbM7rccywEmWVGqJU1/BA+5
hvkrvh9NOuCa+pc9W7WgIP4U4cUEgsKPae2Dz8D/izCVCT1Ffv+jwqjnK5wg4N6gEQmqvl9n7ME1
8IVw3qaE2GLoiA0EsN8SqeGDmQ5eOY0unGvarzyaJ9+DqjqMbZYO3bpr7sdB+ZwGKzBfxULPLKWh
qi4XbcaEpsyBC4uVVC4650BIUJ3LtsWoJ6WdHaDGRaiYCAaeTf5cs4tkZlZI7ND6XIT738HnO53P
raCskxAjLHW3pCT+na42X+Nc2zZCJktIjPV9vUvxlKup2OZxbVON8b5ddg20kSM3GCZcOlUjDWD4
hluKs6pY7/hpxVCoIZy1u1UqYeAknkKqlNrT+p7rjw9HfQS19efLUbcDODM4GZwtP1qijVXxVMzj
0dbD3fc/7lyRhY1gV4W/YP+y816lRKLfckhCtFB2ceq375fIds+HRqMQQp+3xGKPt1pgEX15V1ZO
4A409Mdqgn4D3cOSfo1SmgqHcTTT4qgIMT5rVACDk3DaHu8NYTJFWkM0uAm/W6CZyfty1/zirW5S
EBGBWTTk8QpMXaqtIT+SEVYj7PpGt4gCp0+Y1FjhP+JN6FgMKtM3aAjfK8+jn3lrCU9YB7WyFJ8O
pVupNv+2vuMSrmRx7tTcvD0NxtzU7UxQHWOTSRDA6cGh5Va3hdeDLiy9NQsdrF+C3XVnmMZveXak
hJXury9lmwuCsfX2YJcT4WxCshnMnptMoktyMixUIP6KKEn0S74GqhRvlWIbCOrsuR44vaGP9HfD
ylaPsFHGfzIMD30kRu981jBtX1v8bRK1Of9DoL9W4exb8ViaA37nsevcLAcBKeM5LnGAtmdUHkzg
8T7GEblSbuCRxdUxNWNj1LagRugvJ/ELYptjU3NcMVrfeWbsgEop7/6glwofBO5n3BlXe83qe6Uu
zLCt1RHh2XnO7lEF+K80CcufmJfgEgkFvwNIcJpkRHzrSucwXhoWWCseUMZ6pvwVpxpfpj7GLWRN
SO0Ai1D8D0AfWQxzQgoRty5Tx1TttNtufuTxV/TfXuKUWa+rbei7JuBL4gESmEOecV3+ngw0hNE0
2E8SQdT8JJnToRzCf3GQIBXLGmAQiTmhYhHRM7aZmCGe0mVYL/0b7cpQ5PQEObYKxSW0RdMQ3fXE
MGh3IJWIOVl3ANBxsPU+E3U7fVYc28LvTwNCzYeiW4cl4bp53f++fuNiRL+SSrRx5ysAFvor0ats
yma3/Fe4kaTOncKlcpI6vKXrW9MWrdTeJ1H2x0jYO84oIYtnO+hUpaf1HrmMAus03++llgiG+yIJ
3cpG4E+xFDgFs+MWKOL7+khzfpTmhw8x2LSoMnrq3Qjr8FcUKRTt+yJBELuPx/T/h18EK+gQScfT
cxrYLqP0ejDEemLcIjlxWn9DO/WeWw9Nu38d1ndQ44AJ2JcQ2LqbFPkejr8GkpeXaMnu8gZPoTL8
fx4lGaf27SCsX/h170tmL2QmMdVIwL8cfa75dINrKeThC9W5C4kDyrpKkisXL6hRQ9nUDYdILYk0
suWBz4K13fHx1xSQHIr2UslOri8bd06kcq48G7y+nLf+clQfBC0zwIx2dtUBn5aCm5jwlgpV0kRN
scCeSrGEa0QHnFgJLZUu1Y6j5XFP4j1/uAkLoJOmObyfWdTUL0yaBxM4mXcwbbzTPXLJX/AAExc1
WBEsjXGg0WY+usAtXZYXLtpJVzr7COG/ljnHPKTUB6WVgzL3yBR0JN+Y4TSaQHWH6IkMV8YLcg74
sw9b8HdOcw3ZViii0DP/
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
c9vsW5JBCvThyxOUH2PprRXrwDWuKZW/Q7qPv429HnbShw4Uk66yycd+J5tES7AzUCyGeanqADbi
t/NXtBFOdg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
THl1Z3bcMS4H5t6D0G+kJ/FC2Y9oXN8UuO5gTyqyx046tFrVCFbF7b10tz4zI+nryigVgXDuQjpn
REJa68sEKDIsGl5JYzOYVe9IZ30LgoXUIOey68bvuu3Fnu8lEQh/WChcCnbyekJTFEdRaUW6S2O+
5xce7Ha8Gv7YClnhp04=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
KL9gEW9UR9bJ2V+rRImGqHBVYgwBOrGPetNJZ9L5EOgu04h1LECL47Zq26De2Obbv4OkIEGfGFbZ
muWpwFGMSP/qDDeS04mLx/tWX4SnYgQRVyk8AGGlepDKbn1R0w9YaYChqwaqdh3fMk+xJZbtgoWp
4ejGlCOtRuSFxFcOTPGLnPLr5saG0n7SH0iOlkdKRcxP8k1FnXr8kYqxu6g0r1ZNWNYlDcRB7pBC
lrlL52/HTgYUGboGp0/wpS3BU8yKiMyKpm/Nc0Q701u3QL3zraihgQqtTSzkLZnBFXKNrCd6K2Zb
gw1krcKarckcDY4W+Jw/vlWaBMsrX/8GffFxsQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
I9+ICDzIgzYMfdI9n5+7cSfa+M9K8Q9HlZVHvp38kWsb+jUXV67Oh07GXgNqpn7RlOPdQSyhyXf6
AZH+fL8ycTHV0MoCLtaJieiw5P4E1Pm7Fdq2uCENFjt8u7I2RH9/lcoRh4KurkxCVCe86Dtk1oWB
bacFgZX+QZ+FCZn+6nI=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
pyasIdA/E1o2abIoUkxhLYQwvp5B9zIwQEm/+EGPR3u06a5SPM2I1E62WIwSJ7iN/bqdRmd03/xZ
zjSCCiFFaRUwQmJJ5xZcUnw15IQqIRd/WQQ56gktCUx2rEJwJ4BBJrhOQsbLLnEDNgJUxpYVfXAy
ix6G1h7tonYt5pC9K8hh3YN8608V5TRujBAEsLi+3lAMFCMgjGqgS6cpljhaHIjuKULPnRb7+Rll
fIJqbRqDAQ0ubxbSrdH7w8ZIqWH5mG/hnLBefDFlIZJh/pHjOIOLGPh9RyUn99n5SKT8NF75l8Mj
ggHTuLkcPsoN2kGMWMDxZ752vU2X39SpzveZtA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6000)
`protect data_block
TxmWdQtoCa72lA+PjmaVWNzez4mZxpW7I8VWfPbcGicMeEL2MwwAS4LUnoxwA9Uhmm5ot+LUjCmv
eDB7SAvMi2HMKnvkVOM6GyDSV3gAIeNsWXHPVpwGySt8l+veQ87+wCB2U0M2AjDDPy5G0YrHv7SV
3hwskYbNG5I35qHpm3MFyP0vEDTw2Fa861T3JSQElQvkHyiJtc1mCK8c+3Xwu2sX2tdUav9HJ/w9
ZeB6TCc1chmVdFw//m3On54B7bmWN9Zebwnw5VQGvAYNMLyudEgVjYJwsgwTfKt7pZ93DMozPsEb
mZW50l08EWStM63eu5CZx2XBarUhqb053q94CYABjIYCo57BhlAgWgkKSS2f5WQW0T4Jc3rrfKN3
sLKdFCmMZrqfr5pgPkkX+nvfqUlvDaNXr1tYdehUiUwQuHo0YktKmaf9b7G08xq2O+KihhDW8bJL
JxvKd5VOwLu5iT8eD4v22BpAwoc1xjn98yzfCmkC27huSSupAOcJw+AP5OFOkoRBWp079P45WQOz
o/hkgLdSsXaQUNYZhi2sEsKzRYQK+hrxajBLt5oHEBJbf7wIUiygAcdixuv12Dd/r5+WcBPm4SJO
EmUMYhUA15hnaNALn0dGvrSkIP5NslL6zWERTi9G/OFbUb1a799ztM/HsHegshJwRbCxHi2xIz16
z35IEn7CVUoWVCtQlpFDFlgUxi9BshVVTf/6EayE6uFNg6KX4HhvSmuwujoT0wRmbQZ3Ia7MGLGS
uyxfc7BJHDjz5MQ3coKQd51qJqfHTeRGTAeQ9SzqASPY8ebTFMlp1vqFRPbOq6KsrHx7WT75pRyg
8foHSrwUrb/E8FbwnLnYe9umPzKEjGCTo6eXMWpVIyglksrRWrHIM0OOlju1rUPs5g8RID/+aWQl
krguToDL3/FbiBN/OpIpzzDFYSMSIhrq7W2k0D6X90tLdM86lV4BCaIna6MHSucetYvc6zrnoGID
ZdXRDktS64+FUnZpecuBvQtan+SwG5Rvqymh0vB5LWrSR34biGzmqqTBL6p0TkGzPJUxr3lqAthc
KMtK1x/EDuNMioKMJR1MutrwOckHFMTYiwMKhxvYePPfxHJAgRzDfDBKJ9KWfOFooBxhHPeirSD7
ApSD9kcvPzrCWtqheCAAtKvcZP69vAN+sPL4o8f8ZwS4u3neFS/PPgIEyPAjOT3Rx+hphXuRbR0C
xcg9NF/xUbIz1a0O81Hw+8USWdyB4CQVxN5TGWS0eU0Pzoempf3cbN/Umb4Z+G4nc6TVnd8Gzb/m
jLUUtvYTa++9REXif4S6B/jCByLNDOxPQ28fB9svsp0vyMkxtzExcTVuuXpp4sLmoIH0UguSwDrE
x5YlFE3mWIf1OcehV2K2ErmJpe/bx8/yRbJ+kETpRKlv8D6XTVRQt+Vea+z/vp51qlFOXkOir/4z
HbT597Zit9GKjTATbsheBAZFsu2OizevmfFZYM2WDfnnUnMamAUqxaKqV8sBjWCkxt7aOfu6RZRK
yRL7SOf4zEEAFHMuE+GPm0rxk/sCx2m26oOMj8DaX8AQ/3s2oNdxQ2ddf9myEgQlGerb+eAV5o1a
5LqAFtKIk9Wa2pAmhmbxUpfE38EhmUl+234E/YoxdQLzujssw+CNBvGu8kay1h0rWYV33KjltIfQ
e7KSp27ixG50GEf69G4xAL3n1v6tR1ouThly320lFyJ3Wssf2xL8OdqYZSoLvRF/z5Km2UbN8C+7
b8ffHHM55SASUZgCBIzBG1crH+eNXgiO9efb0rlBQrssgT/gml39YobX1TcOcgos3QpPzFpHw6m7
nZtdH/d+GpWJzbnPCAuEPyDwb4nftuTZZeEacP2zZPvGGROsylXzm+/InIrEx2Ja3Pe03gKZ7kZI
MEAhq8wwkZ0DVk2WDBZxVi/MP0Bbu1xA2CYb9Q2ylABgnzj8gdvoi/JbROGOoF0aSyDWizHV76E4
w1W5PxM9E8680QSTHrxcNxNz0ZO0XGkV3wokatX/5drWMmp+l8vRqoY0zc5+XDjdNgmbt4Aet9cU
9c6Gu3Dz7tgMbXBJsu4EmdbZSNKQLto9ZAd1zOPonSwPo6bwiU+LqjOV94wy+eH4/jYjYrwJiHDM
HyNwJuLi+ht2lBMKmwj6gZG9yecfGBvmcchYOpnyXKAHrE4iJyQuqiqRgL8TOGuMS/BWEZoUV1xT
i+vQiLWtToNOm5bAPioM2s+TcGjzptmZQsmk/bK0sVLLcyXBBxlTMsYnpOl8TnUXNiBNSlg7yoDO
UFvNugB1iR9yTD4Qy+bX5OT2j0OaP1aSMr9OK3fYCxIfl9oUrqQAz1fRc7UOniKSxDClSdhrt/g3
2w+S2xLd1sPkJLh1Z042bk/BdmJgWwfvjpSdD9cA2H0bd9l6f1JmA+XOCcVm8aiqBP+AncvFZkNi
zTCIrFbLsPiUkIMQ8aGtWpFmxbJ/TFaR5RavOE77XkqCyfjvAS1CkGEmQPu45C3KNLMljHvoTGoM
K0WpaO6nYpRhoTp3pB/GFYZH7IyrzaWSCWGVDfmwl8kwuw077+RrBKytLdEvirocgA0XXTckkOP2
YlEVy4zWwy4ozYDcU3sZItQzhUk+XUAtuRyMYQaD+kMmv3R18LAiwcGKLZW5sHBT11dPSGdWpJPQ
JUoI6scMIZZkhWcAd6RdfSUidOpWtiNkDD3wRwbkGsFBwFVW3fXckKO7AQMpCwqeAZq7xzyIDvYO
wNsir/tIa51q0hqSvHP2aaht0TF52ZHQAl11hXQfGtlSMcfrCP3EXGW7Dyrjtk0bPO+U5jyHiztH
b6HKhOdFZarKHPuzQpOYGb4fVlcRAYz4ujhTcfBZOB50NCcympkfCerHKuQkjR7CtJCU/FuOJWqA
LJhIn6vd5ZBZsZKQZfz/Vfi4D8HtvIAg7efEMwCF4sZoWND5Q8XUITLBQ1vm38m7jGV5WooUzmA/
YYHZ5gNMKTNI2rjx6dOapKVN2kwpUgmnqIEw6NLjCZDHmJuvFzqFI6E12fndcObS1LF/VMSrKmhD
F0RLzCARmlpQ8YQaGv3aF/i+jmYcVLvf353fL9w1QVKn+8/5CDSVzjE423D4nIBfbngJneJS3+2z
duSI7FHGEzdj93raYGcZe43fEhZ1dIF9H50A84Rix/gVFWv3NhB/Tcjk2f8AmFp/M47dxGIRkmOX
EQj3EEWq0HXDR1iUyf6YMizK70jMfZ1r6iOGMZYy4g93/e3FBklX7CleETlXaDWS7BC243ka5P7M
jhlhSxTflKC6x9toDQDhWVTQOhN24qUSYugdEru8c0ju8NYZvhRSYvCgnPo5M6tq9hAZ+zBFGOgR
wA3czXQUG4Liq0Gt+Npgd9LUYwhQFo8ahyVu35826rbZybwbX3HGwBadXf5m+yGOmAKPzhu7h96x
FoFUeJKhCU6hlBeCj9IPG9Q+DiRvBBrlgGi/SsjEP5HYTGXP3XLdza4E5gaOqj1PBR/8S6e+NLA7
rQx4Omz8BVG+qVbNVkQpCN+ozDK4WK49yuLCyMWLl6SbOC05dZziMPbSP4IULW9bK/o/Sac8rZtn
QbhQojrvXv7qj6bzy9mUuWQHF8m0ZR9T2hqwAx0vVEpoWU2qRpp30md7+/4WU6ddq0mn3zNwdAa6
nhI/Qrga2D7peVuYaFKYg+iC9soZccRmUDVi5AepG8+oGRAEmvIadnS2Orz7J9PcDEaP7/wHqnkT
E4+0+OKo50zH7D9FmjY0+zhOkinkAmoxLI3koQz1AFVoYB3Oc4FJQ1mAjBn5RDxciAall4tcHmph
AHjIjF6/npOI9rqg9Kv3SYDhY8CgNSqexhQSyxe8FRwDncSGYRq9pdL/EepWjjkbvyAfAN296S3M
KggAEB+SdNHvqqstJFzRBc1LY8WkE8ouoHbxa97vRXY+hopaCl37NXjHDseFr9iZruDOXtGtPs5l
//oZT0Gd8qEzmegeShrQFplZCdGwtEHjMVaZOFcaoEri1SYCzZS8vFWuZ31NrfAzbR8yi/zay0qG
DgZ2iLXuVJWE0DwQ5GnozJl06xnXQiEnUhF3Av/XcnvLLupy3IwVDjcpAXsPQNpYgaNm8ZHiukYt
TjNlQxroJDKZKrBQTC7aTDeyTNAdBJfWQ1NWqryxz/tVKNHdHKNjdT5ubWF+moI/KkSkIv0mRI+f
4KJEL5pr3wdRXTuAhP+2qqEHmYoYNjfFikVfcZjHOeFwunZuIlbYHqaAR1zrI6D60OK/DHl6GzRO
7lhOolznbM00mA8FGOjesVn4WR79qgO7a6W78gkt4OJ5ukjp+CiX8uTm/NA//4Ep7QF6JdB9q0aS
7uYdsBb0qpSMfUiT/Ukq/OEbLHBCcTRq+9KqtZA10v0RytoU1K/qdfOhsgSwj89iQAYCmYHreNnH
Pk7yD1F+7ZAhRvP8GMu/DGcDO6d/+k2eACv9mZT5yr4xzskXlgzrdBCD36hL5KdZSP7IKNIHcHNl
DSW+wenxH1cxlfl5OMfZDkirH/RR1FQnuVJnngBYHPlv3JHuQUqE0ZF70K4hSKYYi3B6t/ldaCNh
WVGOdbM1SO4fwlxXL9M1AmCMX7zOaQi6EkXzzWvmaHmRtYeuvi1xX/byx+rII7a6qdzETqMkvlln
n/2UCz1AFSzQjVka0eJ3b9VVDJDQ4RQhQ15cM9IeCsvqxd2WlQCLXt08AUGfHZWCjHdzmmgkrlG3
e6pKulOVGc5VwSWWbnkxeqXfpzvVQN7XZeOboQn2IuyNvWkdNmqgn0tQhFNeIanvT/GiJ0HmBuMZ
9/65RLl7uMHcKe2Wr12VGmVDyDTNZfN5V4YZwESdWABbU6vztTH7VyNenpCD/ZFUbglx2Dc+7hyo
ljr3KnNPsq0hV/9wB5WoXClZxy1KSu2ofTRwfSQi7+G6AddDAeGKRl+oVQOvWevsUzoKJBpz2q8r
7aJoFF3U0JYvZVVFRRSw3SEVeG3hpUBcAQzJFFqLweGy2vP/FFryOcmCOC89TEVYMm5at/r4uGOY
gxSUhg6RaSAuxyQR+nKXbKjwJ0rA/P9lhNgMIQ8/lqKrWEINcwADetLUHzzwcq5cgnzq9SoKcKkg
PuSoKNIM7Zt2niydQCACx14PEB8696I+r77o8mWc1zwcMxHSk2C0WnQPAJo1iEIS/0WEJfUg+gGh
QXAe8iirvQme7pLOHHOuphtSfEqf6rXqQsFPj1zB16xcixO3lOJAdW6tjrN0/V8vrSlu3M1intJI
lX4cOJxn7cTy3UrPhSRsOxpQHhbofPKNNaQRPOfzImO8p4ldoWiNK9M2S0yUsln/61pJi7aigg1g
hM5OqMT4KwvBucdfSZDGJ8RpHmpHyBniIvzbbKyiumThPmNvL4H/0NbcQwjl4q1lZfeSoiuiW1YN
k2F+vHcbg+Lrmd14d3249JQ6wdOT2DsvRDDPFwhH9jn5K3DdeEVjJAeHoHnV7wAkZ4QvYIlzU8cC
s8wqUyhmDnKdF4nz3/HafVAoKzRxa8vJV9JaNzIpQa6R4PpMfK2xK23PY+dZbtXshrkNfEap5322
O5W+MaLd/jqts9orI2TZOiRAgYw4YYLoXN4GTjhx51xmj+7R7jHGCQqn6LrEVQyhWxPo+0ztK2QB
vEG3/ieXSJZbijN6TpTMQBH0CuL0uQqNBpgJJXPFWzGK87oQo7gkVY/iEfP+j2vhyl7WaagNDc+J
pZByqjDUoxq3/5pG2G4HFj/+wyIaJtre2+kfm7li5yy6yZC9H+q+85Q3ggS+owE4nuyURPbM/J8D
1Mkfer2p67WoF+l+njAuRp6nIde5H50jf+TlnFJ7dj7hXKPDUOIXEQc2KQ23bJNYbzs6/bpCUZLS
/KDNykC3mrPAuwkxnedbELLh5X9PhG+IQo4KBiLAYBLvpkwryx/+c6iWP0MdYwwWdQNlzjUb6zFZ
xtfyu5jynJuSOtUWBYgxnDL8gssrC7aKybNiwVC0iRGgFUtchhb4vCvFcdR63Coqvmn+IpGC1UDj
iDtZYnh/W6U3ZnueY16l0SbsW8B9iEzO6M/jhFmVOkG4tmmaS4IhIJoSJCu7LKYi/JKrnVUTgCS2
iRj9hq57hJie8ty8PgaUYvMtILC9g65OF0+m41kFH4V35QzagJIhWb/BQPSAezL4CPqcVfPjMifT
p6V2xXY3uUPVVAMbyUQTXe2hPWeem0gAVxx0A8OoTMz3oTY9Eg4y+KbM7rccywEmWVGqJU1/BA+5
hvkrvh9NOuCa+pc9W7WgIP4U4cUEgsKPae2Dz8D/izCVCT1Ffv+jwqjnK5wg4N6gEQmqvl9n7ME1
8IVw3qaE2GLoiA0EsN8SqeGDmQ5eOY0unGvarzyaJ9+DqjqMbZYO3bpr7sdB+ZwGKzBfxULPLKWh
qi4XbcaEpsyBC4uVVC4650BIUJ3LtsWoJ6WdHaDGRaiYCAaeTf5cs4tkZlZI7ND6XIT738HnO53P
raCskxAjLHW3pCT+na42X+Nc2zZCJktIjPV9vUvxlKup2OZxbVON8b5ddg20kSM3GCZcOlUjDWD4
hluKs6pY7/hpxVCoIZy1u1UqYeAknkKqlNrT+p7rjw9HfQS19efLUbcDODM4GZwtP1qijVXxVMzj
0dbD3fc/7lyRhY1gV4W/YP+y816lRKLfckhCtFB2ceq375fIds+HRqMQQp+3xGKPt1pgEX15V1ZO
4A409Mdqgn4D3cOSfo1SmgqHcTTT4qgIMT5rVACDk3DaHu8NYTJFWkM0uAm/W6CZyfty1/zirW5S
EBGBWTTk8QpMXaqtIT+SEVYj7PpGt4gCp0+Y1FjhP+JN6FgMKtM3aAjfK8+jn3lrCU9YB7WyFJ8O
pVupNv+2vuMSrmRx7tTcvD0NxtzU7UxQHWOTSRDA6cGh5Va3hdeDLiy9NQsdrF+C3XVnmMZveXak
hJXury9lmwuCsfX2YJcT4WxCshnMnptMoktyMixUIP6KKEn0S74GqhRvlWIbCOrsuR44vaGP9HfD
ylaPsFHGfzIMD30kRu981jBtX1v8bRK1Of9DoL9W4exb8ViaA37nsevcLAcBKeM5LnGAtmdUHkzg
8T7GEblSbuCRxdUxNWNj1LagRugvJ/ELYptjU3NcMVrfeWbsgEop7/6glwofBO5n3BlXe83qe6Uu
zLCt1RHh2XnO7lEF+K80CcufmJfgEgkFvwNIcJpkRHzrSucwXhoWWCseUMZ6pvwVpxpfpj7GLWRN
SO0Ai1D8D0AfWQxzQgoRty5Tx1TttNtufuTxV/TfXuKUWa+rbei7JuBL4gESmEOecV3+ngw0hNE0
2E8SQdT8JJnToRzCf3GQIBXLGmAQiTmhYhHRM7aZmCGe0mVYL/0b7cpQ5PQEObYKxSW0RdMQ3fXE
MGh3IJWIOVl3ANBxsPU+E3U7fVYc28LvTwNCzYeiW4cl4bp53f++fuNiRL+SSrRx5ysAFvor0ats
yma3/Fe4kaTOncKlcpI6vKXrW9MWrdTeJ1H2x0jYO84oIYtnO+hUpaf1HrmMAus03++llgiG+yIJ
3cpG4E+xFDgFs+MWKOL7+khzfpTmhw8x2LSoMnrq3Qjr8FcUKRTt+yJBELuPx/T/h18EK+gQScfT
cxrYLqP0ejDEemLcIjlxWn9DO/WeWw9Nu38d1ndQ44AJ2JcQ2LqbFPkejr8GkpeXaMnu8gZPoTL8
fx4lGaf27SCsX/h170tmL2QmMdVIwL8cfa75dINrKeThC9W5C4kDyrpKkisXL6hRQ9nUDYdILYk0
suWBz4K13fHx1xSQHIr2UslOri8bd06kcq48G7y+nLf+clQfBC0zwIx2dtUBn5aCm5jwlgpV0kRN
scCeSrGEa0QHnFgJLZUu1Y6j5XFP4j1/uAkLoJOmObyfWdTUL0yaBxM4mXcwbbzTPXLJX/AAExc1
WBEsjXGg0WY+usAtXZYXLtpJVzr7COG/ljnHPKTUB6WVgzL3yBR0JN+Y4TSaQHWH6IkMV8YLcg74
sw9b8HdOcw3ZViii0DP/
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
c9vsW5JBCvThyxOUH2PprRXrwDWuKZW/Q7qPv429HnbShw4Uk66yycd+J5tES7AzUCyGeanqADbi
t/NXtBFOdg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
THl1Z3bcMS4H5t6D0G+kJ/FC2Y9oXN8UuO5gTyqyx046tFrVCFbF7b10tz4zI+nryigVgXDuQjpn
REJa68sEKDIsGl5JYzOYVe9IZ30LgoXUIOey68bvuu3Fnu8lEQh/WChcCnbyekJTFEdRaUW6S2O+
5xce7Ha8Gv7YClnhp04=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
KL9gEW9UR9bJ2V+rRImGqHBVYgwBOrGPetNJZ9L5EOgu04h1LECL47Zq26De2Obbv4OkIEGfGFbZ
muWpwFGMSP/qDDeS04mLx/tWX4SnYgQRVyk8AGGlepDKbn1R0w9YaYChqwaqdh3fMk+xJZbtgoWp
4ejGlCOtRuSFxFcOTPGLnPLr5saG0n7SH0iOlkdKRcxP8k1FnXr8kYqxu6g0r1ZNWNYlDcRB7pBC
lrlL52/HTgYUGboGp0/wpS3BU8yKiMyKpm/Nc0Q701u3QL3zraihgQqtTSzkLZnBFXKNrCd6K2Zb
gw1krcKarckcDY4W+Jw/vlWaBMsrX/8GffFxsQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
I9+ICDzIgzYMfdI9n5+7cSfa+M9K8Q9HlZVHvp38kWsb+jUXV67Oh07GXgNqpn7RlOPdQSyhyXf6
AZH+fL8ycTHV0MoCLtaJieiw5P4E1Pm7Fdq2uCENFjt8u7I2RH9/lcoRh4KurkxCVCe86Dtk1oWB
bacFgZX+QZ+FCZn+6nI=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
pyasIdA/E1o2abIoUkxhLYQwvp5B9zIwQEm/+EGPR3u06a5SPM2I1E62WIwSJ7iN/bqdRmd03/xZ
zjSCCiFFaRUwQmJJ5xZcUnw15IQqIRd/WQQ56gktCUx2rEJwJ4BBJrhOQsbLLnEDNgJUxpYVfXAy
ix6G1h7tonYt5pC9K8hh3YN8608V5TRujBAEsLi+3lAMFCMgjGqgS6cpljhaHIjuKULPnRb7+Rll
fIJqbRqDAQ0ubxbSrdH7w8ZIqWH5mG/hnLBefDFlIZJh/pHjOIOLGPh9RyUn99n5SKT8NF75l8Mj
ggHTuLkcPsoN2kGMWMDxZ752vU2X39SpzveZtA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6000)
`protect data_block
TxmWdQtoCa72lA+PjmaVWNzez4mZxpW7I8VWfPbcGicMeEL2MwwAS4LUnoxwA9Uhmm5ot+LUjCmv
eDB7SAvMi2HMKnvkVOM6GyDSV3gAIeNsWXHPVpwGySt8l+veQ87+wCB2U0M2AjDDPy5G0YrHv7SV
3hwskYbNG5I35qHpm3MFyP0vEDTw2Fa861T3JSQElQvkHyiJtc1mCK8c+3Xwu2sX2tdUav9HJ/w9
ZeB6TCc1chmVdFw//m3On54B7bmWN9Zebwnw5VQGvAYNMLyudEgVjYJwsgwTfKt7pZ93DMozPsEb
mZW50l08EWStM63eu5CZx2XBarUhqb053q94CYABjIYCo57BhlAgWgkKSS2f5WQW0T4Jc3rrfKN3
sLKdFCmMZrqfr5pgPkkX+nvfqUlvDaNXr1tYdehUiUwQuHo0YktKmaf9b7G08xq2O+KihhDW8bJL
JxvKd5VOwLu5iT8eD4v22BpAwoc1xjn98yzfCmkC27huSSupAOcJw+AP5OFOkoRBWp079P45WQOz
o/hkgLdSsXaQUNYZhi2sEsKzRYQK+hrxajBLt5oHEBJbf7wIUiygAcdixuv12Dd/r5+WcBPm4SJO
EmUMYhUA15hnaNALn0dGvrSkIP5NslL6zWERTi9G/OFbUb1a799ztM/HsHegshJwRbCxHi2xIz16
z35IEn7CVUoWVCtQlpFDFlgUxi9BshVVTf/6EayE6uFNg6KX4HhvSmuwujoT0wRmbQZ3Ia7MGLGS
uyxfc7BJHDjz5MQ3coKQd51qJqfHTeRGTAeQ9SzqASPY8ebTFMlp1vqFRPbOq6KsrHx7WT75pRyg
8foHSrwUrb/E8FbwnLnYe9umPzKEjGCTo6eXMWpVIyglksrRWrHIM0OOlju1rUPs5g8RID/+aWQl
krguToDL3/FbiBN/OpIpzzDFYSMSIhrq7W2k0D6X90tLdM86lV4BCaIna6MHSucetYvc6zrnoGID
ZdXRDktS64+FUnZpecuBvQtan+SwG5Rvqymh0vB5LWrSR34biGzmqqTBL6p0TkGzPJUxr3lqAthc
KMtK1x/EDuNMioKMJR1MutrwOckHFMTYiwMKhxvYePPfxHJAgRzDfDBKJ9KWfOFooBxhHPeirSD7
ApSD9kcvPzrCWtqheCAAtKvcZP69vAN+sPL4o8f8ZwS4u3neFS/PPgIEyPAjOT3Rx+hphXuRbR0C
xcg9NF/xUbIz1a0O81Hw+8USWdyB4CQVxN5TGWS0eU0Pzoempf3cbN/Umb4Z+G4nc6TVnd8Gzb/m
jLUUtvYTa++9REXif4S6B/jCByLNDOxPQ28fB9svsp0vyMkxtzExcTVuuXpp4sLmoIH0UguSwDrE
x5YlFE3mWIf1OcehV2K2ErmJpe/bx8/yRbJ+kETpRKlv8D6XTVRQt+Vea+z/vp51qlFOXkOir/4z
HbT597Zit9GKjTATbsheBAZFsu2OizevmfFZYM2WDfnnUnMamAUqxaKqV8sBjWCkxt7aOfu6RZRK
yRL7SOf4zEEAFHMuE+GPm0rxk/sCx2m26oOMj8DaX8AQ/3s2oNdxQ2ddf9myEgQlGerb+eAV5o1a
5LqAFtKIk9Wa2pAmhmbxUpfE38EhmUl+234E/YoxdQLzujssw+CNBvGu8kay1h0rWYV33KjltIfQ
e7KSp27ixG50GEf69G4xAL3n1v6tR1ouThly320lFyJ3Wssf2xL8OdqYZSoLvRF/z5Km2UbN8C+7
b8ffHHM55SASUZgCBIzBG1crH+eNXgiO9efb0rlBQrssgT/gml39YobX1TcOcgos3QpPzFpHw6m7
nZtdH/d+GpWJzbnPCAuEPyDwb4nftuTZZeEacP2zZPvGGROsylXzm+/InIrEx2Ja3Pe03gKZ7kZI
MEAhq8wwkZ0DVk2WDBZxVi/MP0Bbu1xA2CYb9Q2ylABgnzj8gdvoi/JbROGOoF0aSyDWizHV76E4
w1W5PxM9E8680QSTHrxcNxNz0ZO0XGkV3wokatX/5drWMmp+l8vRqoY0zc5+XDjdNgmbt4Aet9cU
9c6Gu3Dz7tgMbXBJsu4EmdbZSNKQLto9ZAd1zOPonSwPo6bwiU+LqjOV94wy+eH4/jYjYrwJiHDM
HyNwJuLi+ht2lBMKmwj6gZG9yecfGBvmcchYOpnyXKAHrE4iJyQuqiqRgL8TOGuMS/BWEZoUV1xT
i+vQiLWtToNOm5bAPioM2s+TcGjzptmZQsmk/bK0sVLLcyXBBxlTMsYnpOl8TnUXNiBNSlg7yoDO
UFvNugB1iR9yTD4Qy+bX5OT2j0OaP1aSMr9OK3fYCxIfl9oUrqQAz1fRc7UOniKSxDClSdhrt/g3
2w+S2xLd1sPkJLh1Z042bk/BdmJgWwfvjpSdD9cA2H0bd9l6f1JmA+XOCcVm8aiqBP+AncvFZkNi
zTCIrFbLsPiUkIMQ8aGtWpFmxbJ/TFaR5RavOE77XkqCyfjvAS1CkGEmQPu45C3KNLMljHvoTGoM
K0WpaO6nYpRhoTp3pB/GFYZH7IyrzaWSCWGVDfmwl8kwuw077+RrBKytLdEvirocgA0XXTckkOP2
YlEVy4zWwy4ozYDcU3sZItQzhUk+XUAtuRyMYQaD+kMmv3R18LAiwcGKLZW5sHBT11dPSGdWpJPQ
JUoI6scMIZZkhWcAd6RdfSUidOpWtiNkDD3wRwbkGsFBwFVW3fXckKO7AQMpCwqeAZq7xzyIDvYO
wNsir/tIa51q0hqSvHP2aaht0TF52ZHQAl11hXQfGtlSMcfrCP3EXGW7Dyrjtk0bPO+U5jyHiztH
b6HKhOdFZarKHPuzQpOYGb4fVlcRAYz4ujhTcfBZOB50NCcympkfCerHKuQkjR7CtJCU/FuOJWqA
LJhIn6vd5ZBZsZKQZfz/Vfi4D8HtvIAg7efEMwCF4sZoWND5Q8XUITLBQ1vm38m7jGV5WooUzmA/
YYHZ5gNMKTNI2rjx6dOapKVN2kwpUgmnqIEw6NLjCZDHmJuvFzqFI6E12fndcObS1LF/VMSrKmhD
F0RLzCARmlpQ8YQaGv3aF/i+jmYcVLvf353fL9w1QVKn+8/5CDSVzjE423D4nIBfbngJneJS3+2z
duSI7FHGEzdj93raYGcZe43fEhZ1dIF9H50A84Rix/gVFWv3NhB/Tcjk2f8AmFp/M47dxGIRkmOX
EQj3EEWq0HXDR1iUyf6YMizK70jMfZ1r6iOGMZYy4g93/e3FBklX7CleETlXaDWS7BC243ka5P7M
jhlhSxTflKC6x9toDQDhWVTQOhN24qUSYugdEru8c0ju8NYZvhRSYvCgnPo5M6tq9hAZ+zBFGOgR
wA3czXQUG4Liq0Gt+Npgd9LUYwhQFo8ahyVu35826rbZybwbX3HGwBadXf5m+yGOmAKPzhu7h96x
FoFUeJKhCU6hlBeCj9IPG9Q+DiRvBBrlgGi/SsjEP5HYTGXP3XLdza4E5gaOqj1PBR/8S6e+NLA7
rQx4Omz8BVG+qVbNVkQpCN+ozDK4WK49yuLCyMWLl6SbOC05dZziMPbSP4IULW9bK/o/Sac8rZtn
QbhQojrvXv7qj6bzy9mUuWQHF8m0ZR9T2hqwAx0vVEpoWU2qRpp30md7+/4WU6ddq0mn3zNwdAa6
nhI/Qrga2D7peVuYaFKYg+iC9soZccRmUDVi5AepG8+oGRAEmvIadnS2Orz7J9PcDEaP7/wHqnkT
E4+0+OKo50zH7D9FmjY0+zhOkinkAmoxLI3koQz1AFVoYB3Oc4FJQ1mAjBn5RDxciAall4tcHmph
AHjIjF6/npOI9rqg9Kv3SYDhY8CgNSqexhQSyxe8FRwDncSGYRq9pdL/EepWjjkbvyAfAN296S3M
KggAEB+SdNHvqqstJFzRBc1LY8WkE8ouoHbxa97vRXY+hopaCl37NXjHDseFr9iZruDOXtGtPs5l
//oZT0Gd8qEzmegeShrQFplZCdGwtEHjMVaZOFcaoEri1SYCzZS8vFWuZ31NrfAzbR8yi/zay0qG
DgZ2iLXuVJWE0DwQ5GnozJl06xnXQiEnUhF3Av/XcnvLLupy3IwVDjcpAXsPQNpYgaNm8ZHiukYt
TjNlQxroJDKZKrBQTC7aTDeyTNAdBJfWQ1NWqryxz/tVKNHdHKNjdT5ubWF+moI/KkSkIv0mRI+f
4KJEL5pr3wdRXTuAhP+2qqEHmYoYNjfFikVfcZjHOeFwunZuIlbYHqaAR1zrI6D60OK/DHl6GzRO
7lhOolznbM00mA8FGOjesVn4WR79qgO7a6W78gkt4OJ5ukjp+CiX8uTm/NA//4Ep7QF6JdB9q0aS
7uYdsBb0qpSMfUiT/Ukq/OEbLHBCcTRq+9KqtZA10v0RytoU1K/qdfOhsgSwj89iQAYCmYHreNnH
Pk7yD1F+7ZAhRvP8GMu/DGcDO6d/+k2eACv9mZT5yr4xzskXlgzrdBCD36hL5KdZSP7IKNIHcHNl
DSW+wenxH1cxlfl5OMfZDkirH/RR1FQnuVJnngBYHPlv3JHuQUqE0ZF70K4hSKYYi3B6t/ldaCNh
WVGOdbM1SO4fwlxXL9M1AmCMX7zOaQi6EkXzzWvmaHmRtYeuvi1xX/byx+rII7a6qdzETqMkvlln
n/2UCz1AFSzQjVka0eJ3b9VVDJDQ4RQhQ15cM9IeCsvqxd2WlQCLXt08AUGfHZWCjHdzmmgkrlG3
e6pKulOVGc5VwSWWbnkxeqXfpzvVQN7XZeOboQn2IuyNvWkdNmqgn0tQhFNeIanvT/GiJ0HmBuMZ
9/65RLl7uMHcKe2Wr12VGmVDyDTNZfN5V4YZwESdWABbU6vztTH7VyNenpCD/ZFUbglx2Dc+7hyo
ljr3KnNPsq0hV/9wB5WoXClZxy1KSu2ofTRwfSQi7+G6AddDAeGKRl+oVQOvWevsUzoKJBpz2q8r
7aJoFF3U0JYvZVVFRRSw3SEVeG3hpUBcAQzJFFqLweGy2vP/FFryOcmCOC89TEVYMm5at/r4uGOY
gxSUhg6RaSAuxyQR+nKXbKjwJ0rA/P9lhNgMIQ8/lqKrWEINcwADetLUHzzwcq5cgnzq9SoKcKkg
PuSoKNIM7Zt2niydQCACx14PEB8696I+r77o8mWc1zwcMxHSk2C0WnQPAJo1iEIS/0WEJfUg+gGh
QXAe8iirvQme7pLOHHOuphtSfEqf6rXqQsFPj1zB16xcixO3lOJAdW6tjrN0/V8vrSlu3M1intJI
lX4cOJxn7cTy3UrPhSRsOxpQHhbofPKNNaQRPOfzImO8p4ldoWiNK9M2S0yUsln/61pJi7aigg1g
hM5OqMT4KwvBucdfSZDGJ8RpHmpHyBniIvzbbKyiumThPmNvL4H/0NbcQwjl4q1lZfeSoiuiW1YN
k2F+vHcbg+Lrmd14d3249JQ6wdOT2DsvRDDPFwhH9jn5K3DdeEVjJAeHoHnV7wAkZ4QvYIlzU8cC
s8wqUyhmDnKdF4nz3/HafVAoKzRxa8vJV9JaNzIpQa6R4PpMfK2xK23PY+dZbtXshrkNfEap5322
O5W+MaLd/jqts9orI2TZOiRAgYw4YYLoXN4GTjhx51xmj+7R7jHGCQqn6LrEVQyhWxPo+0ztK2QB
vEG3/ieXSJZbijN6TpTMQBH0CuL0uQqNBpgJJXPFWzGK87oQo7gkVY/iEfP+j2vhyl7WaagNDc+J
pZByqjDUoxq3/5pG2G4HFj/+wyIaJtre2+kfm7li5yy6yZC9H+q+85Q3ggS+owE4nuyURPbM/J8D
1Mkfer2p67WoF+l+njAuRp6nIde5H50jf+TlnFJ7dj7hXKPDUOIXEQc2KQ23bJNYbzs6/bpCUZLS
/KDNykC3mrPAuwkxnedbELLh5X9PhG+IQo4KBiLAYBLvpkwryx/+c6iWP0MdYwwWdQNlzjUb6zFZ
xtfyu5jynJuSOtUWBYgxnDL8gssrC7aKybNiwVC0iRGgFUtchhb4vCvFcdR63Coqvmn+IpGC1UDj
iDtZYnh/W6U3ZnueY16l0SbsW8B9iEzO6M/jhFmVOkG4tmmaS4IhIJoSJCu7LKYi/JKrnVUTgCS2
iRj9hq57hJie8ty8PgaUYvMtILC9g65OF0+m41kFH4V35QzagJIhWb/BQPSAezL4CPqcVfPjMifT
p6V2xXY3uUPVVAMbyUQTXe2hPWeem0gAVxx0A8OoTMz3oTY9Eg4y+KbM7rccywEmWVGqJU1/BA+5
hvkrvh9NOuCa+pc9W7WgIP4U4cUEgsKPae2Dz8D/izCVCT1Ffv+jwqjnK5wg4N6gEQmqvl9n7ME1
8IVw3qaE2GLoiA0EsN8SqeGDmQ5eOY0unGvarzyaJ9+DqjqMbZYO3bpr7sdB+ZwGKzBfxULPLKWh
qi4XbcaEpsyBC4uVVC4650BIUJ3LtsWoJ6WdHaDGRaiYCAaeTf5cs4tkZlZI7ND6XIT738HnO53P
raCskxAjLHW3pCT+na42X+Nc2zZCJktIjPV9vUvxlKup2OZxbVON8b5ddg20kSM3GCZcOlUjDWD4
hluKs6pY7/hpxVCoIZy1u1UqYeAknkKqlNrT+p7rjw9HfQS19efLUbcDODM4GZwtP1qijVXxVMzj
0dbD3fc/7lyRhY1gV4W/YP+y816lRKLfckhCtFB2ceq375fIds+HRqMQQp+3xGKPt1pgEX15V1ZO
4A409Mdqgn4D3cOSfo1SmgqHcTTT4qgIMT5rVACDk3DaHu8NYTJFWkM0uAm/W6CZyfty1/zirW5S
EBGBWTTk8QpMXaqtIT+SEVYj7PpGt4gCp0+Y1FjhP+JN6FgMKtM3aAjfK8+jn3lrCU9YB7WyFJ8O
pVupNv+2vuMSrmRx7tTcvD0NxtzU7UxQHWOTSRDA6cGh5Va3hdeDLiy9NQsdrF+C3XVnmMZveXak
hJXury9lmwuCsfX2YJcT4WxCshnMnptMoktyMixUIP6KKEn0S74GqhRvlWIbCOrsuR44vaGP9HfD
ylaPsFHGfzIMD30kRu981jBtX1v8bRK1Of9DoL9W4exb8ViaA37nsevcLAcBKeM5LnGAtmdUHkzg
8T7GEblSbuCRxdUxNWNj1LagRugvJ/ELYptjU3NcMVrfeWbsgEop7/6glwofBO5n3BlXe83qe6Uu
zLCt1RHh2XnO7lEF+K80CcufmJfgEgkFvwNIcJpkRHzrSucwXhoWWCseUMZ6pvwVpxpfpj7GLWRN
SO0Ai1D8D0AfWQxzQgoRty5Tx1TttNtufuTxV/TfXuKUWa+rbei7JuBL4gESmEOecV3+ngw0hNE0
2E8SQdT8JJnToRzCf3GQIBXLGmAQiTmhYhHRM7aZmCGe0mVYL/0b7cpQ5PQEObYKxSW0RdMQ3fXE
MGh3IJWIOVl3ANBxsPU+E3U7fVYc28LvTwNCzYeiW4cl4bp53f++fuNiRL+SSrRx5ysAFvor0ats
yma3/Fe4kaTOncKlcpI6vKXrW9MWrdTeJ1H2x0jYO84oIYtnO+hUpaf1HrmMAus03++llgiG+yIJ
3cpG4E+xFDgFs+MWKOL7+khzfpTmhw8x2LSoMnrq3Qjr8FcUKRTt+yJBELuPx/T/h18EK+gQScfT
cxrYLqP0ejDEemLcIjlxWn9DO/WeWw9Nu38d1ndQ44AJ2JcQ2LqbFPkejr8GkpeXaMnu8gZPoTL8
fx4lGaf27SCsX/h170tmL2QmMdVIwL8cfa75dINrKeThC9W5C4kDyrpKkisXL6hRQ9nUDYdILYk0
suWBz4K13fHx1xSQHIr2UslOri8bd06kcq48G7y+nLf+clQfBC0zwIx2dtUBn5aCm5jwlgpV0kRN
scCeSrGEa0QHnFgJLZUu1Y6j5XFP4j1/uAkLoJOmObyfWdTUL0yaBxM4mXcwbbzTPXLJX/AAExc1
WBEsjXGg0WY+usAtXZYXLtpJVzr7COG/ljnHPKTUB6WVgzL3yBR0JN+Y4TSaQHWH6IkMV8YLcg74
sw9b8HdOcw3ZViii0DP/
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
c9vsW5JBCvThyxOUH2PprRXrwDWuKZW/Q7qPv429HnbShw4Uk66yycd+J5tES7AzUCyGeanqADbi
t/NXtBFOdg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
THl1Z3bcMS4H5t6D0G+kJ/FC2Y9oXN8UuO5gTyqyx046tFrVCFbF7b10tz4zI+nryigVgXDuQjpn
REJa68sEKDIsGl5JYzOYVe9IZ30LgoXUIOey68bvuu3Fnu8lEQh/WChcCnbyekJTFEdRaUW6S2O+
5xce7Ha8Gv7YClnhp04=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
KL9gEW9UR9bJ2V+rRImGqHBVYgwBOrGPetNJZ9L5EOgu04h1LECL47Zq26De2Obbv4OkIEGfGFbZ
muWpwFGMSP/qDDeS04mLx/tWX4SnYgQRVyk8AGGlepDKbn1R0w9YaYChqwaqdh3fMk+xJZbtgoWp
4ejGlCOtRuSFxFcOTPGLnPLr5saG0n7SH0iOlkdKRcxP8k1FnXr8kYqxu6g0r1ZNWNYlDcRB7pBC
lrlL52/HTgYUGboGp0/wpS3BU8yKiMyKpm/Nc0Q701u3QL3zraihgQqtTSzkLZnBFXKNrCd6K2Zb
gw1krcKarckcDY4W+Jw/vlWaBMsrX/8GffFxsQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
I9+ICDzIgzYMfdI9n5+7cSfa+M9K8Q9HlZVHvp38kWsb+jUXV67Oh07GXgNqpn7RlOPdQSyhyXf6
AZH+fL8ycTHV0MoCLtaJieiw5P4E1Pm7Fdq2uCENFjt8u7I2RH9/lcoRh4KurkxCVCe86Dtk1oWB
bacFgZX+QZ+FCZn+6nI=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
pyasIdA/E1o2abIoUkxhLYQwvp5B9zIwQEm/+EGPR3u06a5SPM2I1E62WIwSJ7iN/bqdRmd03/xZ
zjSCCiFFaRUwQmJJ5xZcUnw15IQqIRd/WQQ56gktCUx2rEJwJ4BBJrhOQsbLLnEDNgJUxpYVfXAy
ix6G1h7tonYt5pC9K8hh3YN8608V5TRujBAEsLi+3lAMFCMgjGqgS6cpljhaHIjuKULPnRb7+Rll
fIJqbRqDAQ0ubxbSrdH7w8ZIqWH5mG/hnLBefDFlIZJh/pHjOIOLGPh9RyUn99n5SKT8NF75l8Mj
ggHTuLkcPsoN2kGMWMDxZ752vU2X39SpzveZtA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6000)
`protect data_block
TxmWdQtoCa72lA+PjmaVWNzez4mZxpW7I8VWfPbcGicMeEL2MwwAS4LUnoxwA9Uhmm5ot+LUjCmv
eDB7SAvMi2HMKnvkVOM6GyDSV3gAIeNsWXHPVpwGySt8l+veQ87+wCB2U0M2AjDDPy5G0YrHv7SV
3hwskYbNG5I35qHpm3MFyP0vEDTw2Fa861T3JSQElQvkHyiJtc1mCK8c+3Xwu2sX2tdUav9HJ/w9
ZeB6TCc1chmVdFw//m3On54B7bmWN9Zebwnw5VQGvAYNMLyudEgVjYJwsgwTfKt7pZ93DMozPsEb
mZW50l08EWStM63eu5CZx2XBarUhqb053q94CYABjIYCo57BhlAgWgkKSS2f5WQW0T4Jc3rrfKN3
sLKdFCmMZrqfr5pgPkkX+nvfqUlvDaNXr1tYdehUiUwQuHo0YktKmaf9b7G08xq2O+KihhDW8bJL
JxvKd5VOwLu5iT8eD4v22BpAwoc1xjn98yzfCmkC27huSSupAOcJw+AP5OFOkoRBWp079P45WQOz
o/hkgLdSsXaQUNYZhi2sEsKzRYQK+hrxajBLt5oHEBJbf7wIUiygAcdixuv12Dd/r5+WcBPm4SJO
EmUMYhUA15hnaNALn0dGvrSkIP5NslL6zWERTi9G/OFbUb1a799ztM/HsHegshJwRbCxHi2xIz16
z35IEn7CVUoWVCtQlpFDFlgUxi9BshVVTf/6EayE6uFNg6KX4HhvSmuwujoT0wRmbQZ3Ia7MGLGS
uyxfc7BJHDjz5MQ3coKQd51qJqfHTeRGTAeQ9SzqASPY8ebTFMlp1vqFRPbOq6KsrHx7WT75pRyg
8foHSrwUrb/E8FbwnLnYe9umPzKEjGCTo6eXMWpVIyglksrRWrHIM0OOlju1rUPs5g8RID/+aWQl
krguToDL3/FbiBN/OpIpzzDFYSMSIhrq7W2k0D6X90tLdM86lV4BCaIna6MHSucetYvc6zrnoGID
ZdXRDktS64+FUnZpecuBvQtan+SwG5Rvqymh0vB5LWrSR34biGzmqqTBL6p0TkGzPJUxr3lqAthc
KMtK1x/EDuNMioKMJR1MutrwOckHFMTYiwMKhxvYePPfxHJAgRzDfDBKJ9KWfOFooBxhHPeirSD7
ApSD9kcvPzrCWtqheCAAtKvcZP69vAN+sPL4o8f8ZwS4u3neFS/PPgIEyPAjOT3Rx+hphXuRbR0C
xcg9NF/xUbIz1a0O81Hw+8USWdyB4CQVxN5TGWS0eU0Pzoempf3cbN/Umb4Z+G4nc6TVnd8Gzb/m
jLUUtvYTa++9REXif4S6B/jCByLNDOxPQ28fB9svsp0vyMkxtzExcTVuuXpp4sLmoIH0UguSwDrE
x5YlFE3mWIf1OcehV2K2ErmJpe/bx8/yRbJ+kETpRKlv8D6XTVRQt+Vea+z/vp51qlFOXkOir/4z
HbT597Zit9GKjTATbsheBAZFsu2OizevmfFZYM2WDfnnUnMamAUqxaKqV8sBjWCkxt7aOfu6RZRK
yRL7SOf4zEEAFHMuE+GPm0rxk/sCx2m26oOMj8DaX8AQ/3s2oNdxQ2ddf9myEgQlGerb+eAV5o1a
5LqAFtKIk9Wa2pAmhmbxUpfE38EhmUl+234E/YoxdQLzujssw+CNBvGu8kay1h0rWYV33KjltIfQ
e7KSp27ixG50GEf69G4xAL3n1v6tR1ouThly320lFyJ3Wssf2xL8OdqYZSoLvRF/z5Km2UbN8C+7
b8ffHHM55SASUZgCBIzBG1crH+eNXgiO9efb0rlBQrssgT/gml39YobX1TcOcgos3QpPzFpHw6m7
nZtdH/d+GpWJzbnPCAuEPyDwb4nftuTZZeEacP2zZPvGGROsylXzm+/InIrEx2Ja3Pe03gKZ7kZI
MEAhq8wwkZ0DVk2WDBZxVi/MP0Bbu1xA2CYb9Q2ylABgnzj8gdvoi/JbROGOoF0aSyDWizHV76E4
w1W5PxM9E8680QSTHrxcNxNz0ZO0XGkV3wokatX/5drWMmp+l8vRqoY0zc5+XDjdNgmbt4Aet9cU
9c6Gu3Dz7tgMbXBJsu4EmdbZSNKQLto9ZAd1zOPonSwPo6bwiU+LqjOV94wy+eH4/jYjYrwJiHDM
HyNwJuLi+ht2lBMKmwj6gZG9yecfGBvmcchYOpnyXKAHrE4iJyQuqiqRgL8TOGuMS/BWEZoUV1xT
i+vQiLWtToNOm5bAPioM2s+TcGjzptmZQsmk/bK0sVLLcyXBBxlTMsYnpOl8TnUXNiBNSlg7yoDO
UFvNugB1iR9yTD4Qy+bX5OT2j0OaP1aSMr9OK3fYCxIfl9oUrqQAz1fRc7UOniKSxDClSdhrt/g3
2w+S2xLd1sPkJLh1Z042bk/BdmJgWwfvjpSdD9cA2H0bd9l6f1JmA+XOCcVm8aiqBP+AncvFZkNi
zTCIrFbLsPiUkIMQ8aGtWpFmxbJ/TFaR5RavOE77XkqCyfjvAS1CkGEmQPu45C3KNLMljHvoTGoM
K0WpaO6nYpRhoTp3pB/GFYZH7IyrzaWSCWGVDfmwl8kwuw077+RrBKytLdEvirocgA0XXTckkOP2
YlEVy4zWwy4ozYDcU3sZItQzhUk+XUAtuRyMYQaD+kMmv3R18LAiwcGKLZW5sHBT11dPSGdWpJPQ
JUoI6scMIZZkhWcAd6RdfSUidOpWtiNkDD3wRwbkGsFBwFVW3fXckKO7AQMpCwqeAZq7xzyIDvYO
wNsir/tIa51q0hqSvHP2aaht0TF52ZHQAl11hXQfGtlSMcfrCP3EXGW7Dyrjtk0bPO+U5jyHiztH
b6HKhOdFZarKHPuzQpOYGb4fVlcRAYz4ujhTcfBZOB50NCcympkfCerHKuQkjR7CtJCU/FuOJWqA
LJhIn6vd5ZBZsZKQZfz/Vfi4D8HtvIAg7efEMwCF4sZoWND5Q8XUITLBQ1vm38m7jGV5WooUzmA/
YYHZ5gNMKTNI2rjx6dOapKVN2kwpUgmnqIEw6NLjCZDHmJuvFzqFI6E12fndcObS1LF/VMSrKmhD
F0RLzCARmlpQ8YQaGv3aF/i+jmYcVLvf353fL9w1QVKn+8/5CDSVzjE423D4nIBfbngJneJS3+2z
duSI7FHGEzdj93raYGcZe43fEhZ1dIF9H50A84Rix/gVFWv3NhB/Tcjk2f8AmFp/M47dxGIRkmOX
EQj3EEWq0HXDR1iUyf6YMizK70jMfZ1r6iOGMZYy4g93/e3FBklX7CleETlXaDWS7BC243ka5P7M
jhlhSxTflKC6x9toDQDhWVTQOhN24qUSYugdEru8c0ju8NYZvhRSYvCgnPo5M6tq9hAZ+zBFGOgR
wA3czXQUG4Liq0Gt+Npgd9LUYwhQFo8ahyVu35826rbZybwbX3HGwBadXf5m+yGOmAKPzhu7h96x
FoFUeJKhCU6hlBeCj9IPG9Q+DiRvBBrlgGi/SsjEP5HYTGXP3XLdza4E5gaOqj1PBR/8S6e+NLA7
rQx4Omz8BVG+qVbNVkQpCN+ozDK4WK49yuLCyMWLl6SbOC05dZziMPbSP4IULW9bK/o/Sac8rZtn
QbhQojrvXv7qj6bzy9mUuWQHF8m0ZR9T2hqwAx0vVEpoWU2qRpp30md7+/4WU6ddq0mn3zNwdAa6
nhI/Qrga2D7peVuYaFKYg+iC9soZccRmUDVi5AepG8+oGRAEmvIadnS2Orz7J9PcDEaP7/wHqnkT
E4+0+OKo50zH7D9FmjY0+zhOkinkAmoxLI3koQz1AFVoYB3Oc4FJQ1mAjBn5RDxciAall4tcHmph
AHjIjF6/npOI9rqg9Kv3SYDhY8CgNSqexhQSyxe8FRwDncSGYRq9pdL/EepWjjkbvyAfAN296S3M
KggAEB+SdNHvqqstJFzRBc1LY8WkE8ouoHbxa97vRXY+hopaCl37NXjHDseFr9iZruDOXtGtPs5l
//oZT0Gd8qEzmegeShrQFplZCdGwtEHjMVaZOFcaoEri1SYCzZS8vFWuZ31NrfAzbR8yi/zay0qG
DgZ2iLXuVJWE0DwQ5GnozJl06xnXQiEnUhF3Av/XcnvLLupy3IwVDjcpAXsPQNpYgaNm8ZHiukYt
TjNlQxroJDKZKrBQTC7aTDeyTNAdBJfWQ1NWqryxz/tVKNHdHKNjdT5ubWF+moI/KkSkIv0mRI+f
4KJEL5pr3wdRXTuAhP+2qqEHmYoYNjfFikVfcZjHOeFwunZuIlbYHqaAR1zrI6D60OK/DHl6GzRO
7lhOolznbM00mA8FGOjesVn4WR79qgO7a6W78gkt4OJ5ukjp+CiX8uTm/NA//4Ep7QF6JdB9q0aS
7uYdsBb0qpSMfUiT/Ukq/OEbLHBCcTRq+9KqtZA10v0RytoU1K/qdfOhsgSwj89iQAYCmYHreNnH
Pk7yD1F+7ZAhRvP8GMu/DGcDO6d/+k2eACv9mZT5yr4xzskXlgzrdBCD36hL5KdZSP7IKNIHcHNl
DSW+wenxH1cxlfl5OMfZDkirH/RR1FQnuVJnngBYHPlv3JHuQUqE0ZF70K4hSKYYi3B6t/ldaCNh
WVGOdbM1SO4fwlxXL9M1AmCMX7zOaQi6EkXzzWvmaHmRtYeuvi1xX/byx+rII7a6qdzETqMkvlln
n/2UCz1AFSzQjVka0eJ3b9VVDJDQ4RQhQ15cM9IeCsvqxd2WlQCLXt08AUGfHZWCjHdzmmgkrlG3
e6pKulOVGc5VwSWWbnkxeqXfpzvVQN7XZeOboQn2IuyNvWkdNmqgn0tQhFNeIanvT/GiJ0HmBuMZ
9/65RLl7uMHcKe2Wr12VGmVDyDTNZfN5V4YZwESdWABbU6vztTH7VyNenpCD/ZFUbglx2Dc+7hyo
ljr3KnNPsq0hV/9wB5WoXClZxy1KSu2ofTRwfSQi7+G6AddDAeGKRl+oVQOvWevsUzoKJBpz2q8r
7aJoFF3U0JYvZVVFRRSw3SEVeG3hpUBcAQzJFFqLweGy2vP/FFryOcmCOC89TEVYMm5at/r4uGOY
gxSUhg6RaSAuxyQR+nKXbKjwJ0rA/P9lhNgMIQ8/lqKrWEINcwADetLUHzzwcq5cgnzq9SoKcKkg
PuSoKNIM7Zt2niydQCACx14PEB8696I+r77o8mWc1zwcMxHSk2C0WnQPAJo1iEIS/0WEJfUg+gGh
QXAe8iirvQme7pLOHHOuphtSfEqf6rXqQsFPj1zB16xcixO3lOJAdW6tjrN0/V8vrSlu3M1intJI
lX4cOJxn7cTy3UrPhSRsOxpQHhbofPKNNaQRPOfzImO8p4ldoWiNK9M2S0yUsln/61pJi7aigg1g
hM5OqMT4KwvBucdfSZDGJ8RpHmpHyBniIvzbbKyiumThPmNvL4H/0NbcQwjl4q1lZfeSoiuiW1YN
k2F+vHcbg+Lrmd14d3249JQ6wdOT2DsvRDDPFwhH9jn5K3DdeEVjJAeHoHnV7wAkZ4QvYIlzU8cC
s8wqUyhmDnKdF4nz3/HafVAoKzRxa8vJV9JaNzIpQa6R4PpMfK2xK23PY+dZbtXshrkNfEap5322
O5W+MaLd/jqts9orI2TZOiRAgYw4YYLoXN4GTjhx51xmj+7R7jHGCQqn6LrEVQyhWxPo+0ztK2QB
vEG3/ieXSJZbijN6TpTMQBH0CuL0uQqNBpgJJXPFWzGK87oQo7gkVY/iEfP+j2vhyl7WaagNDc+J
pZByqjDUoxq3/5pG2G4HFj/+wyIaJtre2+kfm7li5yy6yZC9H+q+85Q3ggS+owE4nuyURPbM/J8D
1Mkfer2p67WoF+l+njAuRp6nIde5H50jf+TlnFJ7dj7hXKPDUOIXEQc2KQ23bJNYbzs6/bpCUZLS
/KDNykC3mrPAuwkxnedbELLh5X9PhG+IQo4KBiLAYBLvpkwryx/+c6iWP0MdYwwWdQNlzjUb6zFZ
xtfyu5jynJuSOtUWBYgxnDL8gssrC7aKybNiwVC0iRGgFUtchhb4vCvFcdR63Coqvmn+IpGC1UDj
iDtZYnh/W6U3ZnueY16l0SbsW8B9iEzO6M/jhFmVOkG4tmmaS4IhIJoSJCu7LKYi/JKrnVUTgCS2
iRj9hq57hJie8ty8PgaUYvMtILC9g65OF0+m41kFH4V35QzagJIhWb/BQPSAezL4CPqcVfPjMifT
p6V2xXY3uUPVVAMbyUQTXe2hPWeem0gAVxx0A8OoTMz3oTY9Eg4y+KbM7rccywEmWVGqJU1/BA+5
hvkrvh9NOuCa+pc9W7WgIP4U4cUEgsKPae2Dz8D/izCVCT1Ffv+jwqjnK5wg4N6gEQmqvl9n7ME1
8IVw3qaE2GLoiA0EsN8SqeGDmQ5eOY0unGvarzyaJ9+DqjqMbZYO3bpr7sdB+ZwGKzBfxULPLKWh
qi4XbcaEpsyBC4uVVC4650BIUJ3LtsWoJ6WdHaDGRaiYCAaeTf5cs4tkZlZI7ND6XIT738HnO53P
raCskxAjLHW3pCT+na42X+Nc2zZCJktIjPV9vUvxlKup2OZxbVON8b5ddg20kSM3GCZcOlUjDWD4
hluKs6pY7/hpxVCoIZy1u1UqYeAknkKqlNrT+p7rjw9HfQS19efLUbcDODM4GZwtP1qijVXxVMzj
0dbD3fc/7lyRhY1gV4W/YP+y816lRKLfckhCtFB2ceq375fIds+HRqMQQp+3xGKPt1pgEX15V1ZO
4A409Mdqgn4D3cOSfo1SmgqHcTTT4qgIMT5rVACDk3DaHu8NYTJFWkM0uAm/W6CZyfty1/zirW5S
EBGBWTTk8QpMXaqtIT+SEVYj7PpGt4gCp0+Y1FjhP+JN6FgMKtM3aAjfK8+jn3lrCU9YB7WyFJ8O
pVupNv+2vuMSrmRx7tTcvD0NxtzU7UxQHWOTSRDA6cGh5Va3hdeDLiy9NQsdrF+C3XVnmMZveXak
hJXury9lmwuCsfX2YJcT4WxCshnMnptMoktyMixUIP6KKEn0S74GqhRvlWIbCOrsuR44vaGP9HfD
ylaPsFHGfzIMD30kRu981jBtX1v8bRK1Of9DoL9W4exb8ViaA37nsevcLAcBKeM5LnGAtmdUHkzg
8T7GEblSbuCRxdUxNWNj1LagRugvJ/ELYptjU3NcMVrfeWbsgEop7/6glwofBO5n3BlXe83qe6Uu
zLCt1RHh2XnO7lEF+K80CcufmJfgEgkFvwNIcJpkRHzrSucwXhoWWCseUMZ6pvwVpxpfpj7GLWRN
SO0Ai1D8D0AfWQxzQgoRty5Tx1TttNtufuTxV/TfXuKUWa+rbei7JuBL4gESmEOecV3+ngw0hNE0
2E8SQdT8JJnToRzCf3GQIBXLGmAQiTmhYhHRM7aZmCGe0mVYL/0b7cpQ5PQEObYKxSW0RdMQ3fXE
MGh3IJWIOVl3ANBxsPU+E3U7fVYc28LvTwNCzYeiW4cl4bp53f++fuNiRL+SSrRx5ysAFvor0ats
yma3/Fe4kaTOncKlcpI6vKXrW9MWrdTeJ1H2x0jYO84oIYtnO+hUpaf1HrmMAus03++llgiG+yIJ
3cpG4E+xFDgFs+MWKOL7+khzfpTmhw8x2LSoMnrq3Qjr8FcUKRTt+yJBELuPx/T/h18EK+gQScfT
cxrYLqP0ejDEemLcIjlxWn9DO/WeWw9Nu38d1ndQ44AJ2JcQ2LqbFPkejr8GkpeXaMnu8gZPoTL8
fx4lGaf27SCsX/h170tmL2QmMdVIwL8cfa75dINrKeThC9W5C4kDyrpKkisXL6hRQ9nUDYdILYk0
suWBz4K13fHx1xSQHIr2UslOri8bd06kcq48G7y+nLf+clQfBC0zwIx2dtUBn5aCm5jwlgpV0kRN
scCeSrGEa0QHnFgJLZUu1Y6j5XFP4j1/uAkLoJOmObyfWdTUL0yaBxM4mXcwbbzTPXLJX/AAExc1
WBEsjXGg0WY+usAtXZYXLtpJVzr7COG/ljnHPKTUB6WVgzL3yBR0JN+Y4TSaQHWH6IkMV8YLcg74
sw9b8HdOcw3ZViii0DP/
`protect end_protected
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity nfa_forward_buckets_if_async_fifo is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 3;
DEPTH : integer := 8);
port (
clk_w : in std_logic;
clk_r : in std_logic;
reset : in std_logic;
if_din : in std_logic_vector(DATA_WIDTH - 1 downto 0);
if_full_n : out std_logic;
if_write_ce: in std_logic;
if_write : in std_logic;
if_dout : out std_logic_vector(DATA_WIDTH - 1 downto 0);
if_empty_n : out std_logic;
if_read_ce : in std_logic;
if_read : in std_logic);
function calc_addr_width(x : integer) return integer is
begin
if (x < 1) then
return 1;
else
return x;
end if;
end function;
end entity;
architecture rtl of nfa_forward_buckets_if_async_fifo is
constant DEPTH_BITS : integer := calc_addr_width(ADDR_WIDTH);
constant REAL_DEPTH : integer := 2 ** DEPTH_BITS;
constant ALL_ONE : unsigned(DEPTH_BITS downto 0) := (others => '1');
constant MASK : std_logic_vector(DEPTH_BITS downto 0) := std_logic_vector(ALL_ONE sll (DEPTH_BITS - 1));
type memtype is array (0 to REAL_DEPTH - 1) of std_logic_vector(DATA_WIDTH - 1 downto 0);
signal mem : memtype;
signal full : std_logic := '0';
signal empty : std_logic := '1';
signal full_next : std_logic;
signal empty_next : std_logic;
signal wraddr_bin : std_logic_vector(DEPTH_BITS downto 0) := (others => '0');
signal rdaddr_bin : std_logic_vector(DEPTH_BITS downto 0) := (others => '0');
signal wraddr : std_logic_vector(DEPTH_BITS - 1 downto 0);
signal rdaddr : std_logic_vector(DEPTH_BITS - 1 downto 0);
signal wraddr_bin_next : std_logic_vector(DEPTH_BITS downto 0);
signal rdaddr_bin_next : std_logic_vector(DEPTH_BITS downto 0);
signal wraddr_gray_next : std_logic_vector(DEPTH_BITS downto 0);
signal rdaddr_gray_next : std_logic_vector(DEPTH_BITS downto 0);
signal wraddr_gray_sync0 : std_logic_vector(DEPTH_BITS downto 0) := (others => '0');
signal rdaddr_gray_sync0 : std_logic_vector(DEPTH_BITS downto 0) := (others => '0');
signal wraddr_gray_sync1 : std_logic_vector(DEPTH_BITS downto 0) := (others => '0');
signal rdaddr_gray_sync1 : std_logic_vector(DEPTH_BITS downto 0) := (others => '0');
signal wraddr_gray_sync2 : std_logic_vector(DEPTH_BITS downto 0) := (others => '0');
signal rdaddr_gray_sync2 : std_logic_vector(DEPTH_BITS downto 0) := (others => '0');
signal dout_buf : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
attribute ram_style : string;
attribute ram_style of mem : signal is "block";
begin
if_full_n <= not full;
if_empty_n <= not empty;
if_dout <= dout_buf;
full_next <= '1' when (wraddr_gray_next = (rdaddr_gray_sync2 xor MASK)) else '0';
empty_next <= '1' when (rdaddr_gray_next = wraddr_gray_sync2) else '0';
wraddr <= wraddr_bin(DEPTH_BITS - 1 downto 0);
rdaddr <= rdaddr_bin_next(DEPTH_BITS - 1 downto 0);
wraddr_bin_next <= std_logic_vector(unsigned(wraddr_bin) + 1) when (full = '0' and if_write = '1') else wraddr_bin;
rdaddr_bin_next <= std_logic_vector(unsigned(rdaddr_bin) + 1) when (empty = '0' and if_read = '1') else rdaddr_bin;
wraddr_gray_next <= wraddr_bin_next xor std_logic_vector(unsigned(wraddr_bin_next) srl 1);
rdaddr_gray_next <= rdaddr_bin_next xor std_logic_vector(unsigned(rdaddr_bin_next) srl 1);
-- full, wraddr_bin, wraddr_gray_sync0, rdaddr_gray_sync1, rdaddr_gray_sync2
-- @ clk_w domain
process(clk_w, reset) begin
if (reset = '1') then
full <= '0';
wraddr_bin <= (others => '0');
wraddr_gray_sync0 <= (others => '0');
rdaddr_gray_sync1 <= (others => '0');
rdaddr_gray_sync2 <= (others => '0');
elsif (clk_w'event and clk_w = '1' and if_write_ce = '1') then
full <= full_next;
wraddr_bin <= wraddr_bin_next;
wraddr_gray_sync0 <= wraddr_gray_next;
rdaddr_gray_sync1 <= rdaddr_gray_sync0;
rdaddr_gray_sync2 <= rdaddr_gray_sync1;
end if;
end process;
-- empty, rdaddr_bin, rdaddr_gray_sync0, wraddr_gray_sync1, wraddr_gray_sync2
-- @ clk_r domain
process(clk_r, reset) begin
if (reset = '1') then
empty <= '1';
rdaddr_bin <= (others => '0');
rdaddr_gray_sync0 <= (others => '0');
wraddr_gray_sync1 <= (others => '0');
wraddr_gray_sync2 <= (others => '0');
elsif (clk_r'event and clk_r = '1' and if_read_ce = '1') then
empty <= empty_next;
rdaddr_bin <= rdaddr_bin_next;
rdaddr_gray_sync0 <= rdaddr_gray_next;
wraddr_gray_sync1 <= wraddr_gray_sync0;
wraddr_gray_sync2 <= wraddr_gray_sync1;
end if;
end process;
-- write mem
process(clk_w) begin
if (clk_w'event and clk_w = '1' and if_write_ce = '1') then
if (full = '0' and if_write = '1') then
mem(to_integer(unsigned(wraddr))) <= if_din;
end if;
end if;
end process;
-- read mem
process(clk_r) begin
if (clk_r'event and clk_r = '1' and if_read_ce = '1') then
dout_buf <= mem(to_integer(unsigned(rdaddr)));
end if;
end process;
end architecture;
|
-- This file is automatically generated by a matlab script
--
-- Do not modify directly!
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_signed.all;
package sine_lut_pkg is
constant PHASE_WIDTH : integer := 12;
constant AMPL_WIDTH : integer := 12;
type lut_type is array(0 to 2**(PHASE_WIDTH-2)-1) of std_logic_vector(AMPL_WIDTH-1 downto 0);
constant sine_lut : lut_type := (
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(421,AMPL_WIDTH),
conv_std_logic_vector(424,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(439,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(467,AMPL_WIDTH),
conv_std_logic_vector(470,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(494,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(513,AMPL_WIDTH),
conv_std_logic_vector(516,AMPL_WIDTH),
conv_std_logic_vector(519,AMPL_WIDTH),
conv_std_logic_vector(522,AMPL_WIDTH),
conv_std_logic_vector(525,AMPL_WIDTH),
conv_std_logic_vector(528,AMPL_WIDTH),
conv_std_logic_vector(531,AMPL_WIDTH),
conv_std_logic_vector(534,AMPL_WIDTH),
conv_std_logic_vector(537,AMPL_WIDTH),
conv_std_logic_vector(540,AMPL_WIDTH),
conv_std_logic_vector(543,AMPL_WIDTH),
conv_std_logic_vector(546,AMPL_WIDTH),
conv_std_logic_vector(549,AMPL_WIDTH),
conv_std_logic_vector(552,AMPL_WIDTH),
conv_std_logic_vector(555,AMPL_WIDTH),
conv_std_logic_vector(558,AMPL_WIDTH),
conv_std_logic_vector(561,AMPL_WIDTH),
conv_std_logic_vector(564,AMPL_WIDTH),
conv_std_logic_vector(567,AMPL_WIDTH),
conv_std_logic_vector(570,AMPL_WIDTH),
conv_std_logic_vector(573,AMPL_WIDTH),
conv_std_logic_vector(576,AMPL_WIDTH),
conv_std_logic_vector(579,AMPL_WIDTH),
conv_std_logic_vector(582,AMPL_WIDTH),
conv_std_logic_vector(585,AMPL_WIDTH),
conv_std_logic_vector(588,AMPL_WIDTH),
conv_std_logic_vector(591,AMPL_WIDTH),
conv_std_logic_vector(594,AMPL_WIDTH),
conv_std_logic_vector(597,AMPL_WIDTH),
conv_std_logic_vector(600,AMPL_WIDTH),
conv_std_logic_vector(603,AMPL_WIDTH),
conv_std_logic_vector(606,AMPL_WIDTH),
conv_std_logic_vector(609,AMPL_WIDTH),
conv_std_logic_vector(612,AMPL_WIDTH),
conv_std_logic_vector(615,AMPL_WIDTH),
conv_std_logic_vector(618,AMPL_WIDTH),
conv_std_logic_vector(621,AMPL_WIDTH),
conv_std_logic_vector(624,AMPL_WIDTH),
conv_std_logic_vector(627,AMPL_WIDTH),
conv_std_logic_vector(630,AMPL_WIDTH),
conv_std_logic_vector(633,AMPL_WIDTH),
conv_std_logic_vector(636,AMPL_WIDTH),
conv_std_logic_vector(639,AMPL_WIDTH),
conv_std_logic_vector(642,AMPL_WIDTH),
conv_std_logic_vector(645,AMPL_WIDTH),
conv_std_logic_vector(648,AMPL_WIDTH),
conv_std_logic_vector(651,AMPL_WIDTH),
conv_std_logic_vector(654,AMPL_WIDTH),
conv_std_logic_vector(657,AMPL_WIDTH),
conv_std_logic_vector(660,AMPL_WIDTH),
conv_std_logic_vector(663,AMPL_WIDTH),
conv_std_logic_vector(666,AMPL_WIDTH),
conv_std_logic_vector(669,AMPL_WIDTH),
conv_std_logic_vector(672,AMPL_WIDTH),
conv_std_logic_vector(675,AMPL_WIDTH),
conv_std_logic_vector(678,AMPL_WIDTH),
conv_std_logic_vector(681,AMPL_WIDTH),
conv_std_logic_vector(684,AMPL_WIDTH),
conv_std_logic_vector(687,AMPL_WIDTH),
conv_std_logic_vector(690,AMPL_WIDTH),
conv_std_logic_vector(693,AMPL_WIDTH),
conv_std_logic_vector(696,AMPL_WIDTH),
conv_std_logic_vector(698,AMPL_WIDTH),
conv_std_logic_vector(701,AMPL_WIDTH),
conv_std_logic_vector(704,AMPL_WIDTH),
conv_std_logic_vector(707,AMPL_WIDTH),
conv_std_logic_vector(710,AMPL_WIDTH),
conv_std_logic_vector(713,AMPL_WIDTH),
conv_std_logic_vector(716,AMPL_WIDTH),
conv_std_logic_vector(719,AMPL_WIDTH),
conv_std_logic_vector(722,AMPL_WIDTH),
conv_std_logic_vector(725,AMPL_WIDTH),
conv_std_logic_vector(728,AMPL_WIDTH),
conv_std_logic_vector(731,AMPL_WIDTH),
conv_std_logic_vector(734,AMPL_WIDTH),
conv_std_logic_vector(737,AMPL_WIDTH),
conv_std_logic_vector(740,AMPL_WIDTH),
conv_std_logic_vector(743,AMPL_WIDTH),
conv_std_logic_vector(745,AMPL_WIDTH),
conv_std_logic_vector(748,AMPL_WIDTH),
conv_std_logic_vector(751,AMPL_WIDTH),
conv_std_logic_vector(754,AMPL_WIDTH),
conv_std_logic_vector(757,AMPL_WIDTH),
conv_std_logic_vector(760,AMPL_WIDTH),
conv_std_logic_vector(763,AMPL_WIDTH),
conv_std_logic_vector(766,AMPL_WIDTH),
conv_std_logic_vector(769,AMPL_WIDTH),
conv_std_logic_vector(772,AMPL_WIDTH),
conv_std_logic_vector(775,AMPL_WIDTH),
conv_std_logic_vector(778,AMPL_WIDTH),
conv_std_logic_vector(780,AMPL_WIDTH),
conv_std_logic_vector(783,AMPL_WIDTH),
conv_std_logic_vector(786,AMPL_WIDTH),
conv_std_logic_vector(789,AMPL_WIDTH),
conv_std_logic_vector(792,AMPL_WIDTH),
conv_std_logic_vector(795,AMPL_WIDTH),
conv_std_logic_vector(798,AMPL_WIDTH),
conv_std_logic_vector(801,AMPL_WIDTH),
conv_std_logic_vector(804,AMPL_WIDTH),
conv_std_logic_vector(807,AMPL_WIDTH),
conv_std_logic_vector(809,AMPL_WIDTH),
conv_std_logic_vector(812,AMPL_WIDTH),
conv_std_logic_vector(815,AMPL_WIDTH),
conv_std_logic_vector(818,AMPL_WIDTH),
conv_std_logic_vector(821,AMPL_WIDTH),
conv_std_logic_vector(824,AMPL_WIDTH),
conv_std_logic_vector(827,AMPL_WIDTH),
conv_std_logic_vector(830,AMPL_WIDTH),
conv_std_logic_vector(832,AMPL_WIDTH),
conv_std_logic_vector(835,AMPL_WIDTH),
conv_std_logic_vector(838,AMPL_WIDTH),
conv_std_logic_vector(841,AMPL_WIDTH),
conv_std_logic_vector(844,AMPL_WIDTH),
conv_std_logic_vector(847,AMPL_WIDTH),
conv_std_logic_vector(850,AMPL_WIDTH),
conv_std_logic_vector(852,AMPL_WIDTH),
conv_std_logic_vector(855,AMPL_WIDTH),
conv_std_logic_vector(858,AMPL_WIDTH),
conv_std_logic_vector(861,AMPL_WIDTH),
conv_std_logic_vector(864,AMPL_WIDTH),
conv_std_logic_vector(867,AMPL_WIDTH),
conv_std_logic_vector(870,AMPL_WIDTH),
conv_std_logic_vector(872,AMPL_WIDTH),
conv_std_logic_vector(875,AMPL_WIDTH),
conv_std_logic_vector(878,AMPL_WIDTH),
conv_std_logic_vector(881,AMPL_WIDTH),
conv_std_logic_vector(884,AMPL_WIDTH),
conv_std_logic_vector(887,AMPL_WIDTH),
conv_std_logic_vector(889,AMPL_WIDTH),
conv_std_logic_vector(892,AMPL_WIDTH),
conv_std_logic_vector(895,AMPL_WIDTH),
conv_std_logic_vector(898,AMPL_WIDTH),
conv_std_logic_vector(901,AMPL_WIDTH),
conv_std_logic_vector(903,AMPL_WIDTH),
conv_std_logic_vector(906,AMPL_WIDTH),
conv_std_logic_vector(909,AMPL_WIDTH),
conv_std_logic_vector(912,AMPL_WIDTH),
conv_std_logic_vector(915,AMPL_WIDTH),
conv_std_logic_vector(918,AMPL_WIDTH),
conv_std_logic_vector(920,AMPL_WIDTH),
conv_std_logic_vector(923,AMPL_WIDTH),
conv_std_logic_vector(926,AMPL_WIDTH),
conv_std_logic_vector(929,AMPL_WIDTH),
conv_std_logic_vector(932,AMPL_WIDTH),
conv_std_logic_vector(934,AMPL_WIDTH),
conv_std_logic_vector(937,AMPL_WIDTH),
conv_std_logic_vector(940,AMPL_WIDTH),
conv_std_logic_vector(943,AMPL_WIDTH),
conv_std_logic_vector(946,AMPL_WIDTH),
conv_std_logic_vector(948,AMPL_WIDTH),
conv_std_logic_vector(951,AMPL_WIDTH),
conv_std_logic_vector(954,AMPL_WIDTH),
conv_std_logic_vector(957,AMPL_WIDTH),
conv_std_logic_vector(959,AMPL_WIDTH),
conv_std_logic_vector(962,AMPL_WIDTH),
conv_std_logic_vector(965,AMPL_WIDTH),
conv_std_logic_vector(968,AMPL_WIDTH),
conv_std_logic_vector(970,AMPL_WIDTH),
conv_std_logic_vector(973,AMPL_WIDTH),
conv_std_logic_vector(976,AMPL_WIDTH),
conv_std_logic_vector(979,AMPL_WIDTH),
conv_std_logic_vector(982,AMPL_WIDTH),
conv_std_logic_vector(984,AMPL_WIDTH),
conv_std_logic_vector(987,AMPL_WIDTH),
conv_std_logic_vector(990,AMPL_WIDTH),
conv_std_logic_vector(993,AMPL_WIDTH),
conv_std_logic_vector(995,AMPL_WIDTH),
conv_std_logic_vector(998,AMPL_WIDTH),
conv_std_logic_vector(1001,AMPL_WIDTH),
conv_std_logic_vector(1003,AMPL_WIDTH),
conv_std_logic_vector(1006,AMPL_WIDTH),
conv_std_logic_vector(1009,AMPL_WIDTH),
conv_std_logic_vector(1012,AMPL_WIDTH),
conv_std_logic_vector(1014,AMPL_WIDTH),
conv_std_logic_vector(1017,AMPL_WIDTH),
conv_std_logic_vector(1020,AMPL_WIDTH),
conv_std_logic_vector(1023,AMPL_WIDTH),
conv_std_logic_vector(1025,AMPL_WIDTH),
conv_std_logic_vector(1028,AMPL_WIDTH),
conv_std_logic_vector(1031,AMPL_WIDTH),
conv_std_logic_vector(1033,AMPL_WIDTH),
conv_std_logic_vector(1036,AMPL_WIDTH),
conv_std_logic_vector(1039,AMPL_WIDTH),
conv_std_logic_vector(1042,AMPL_WIDTH),
conv_std_logic_vector(1044,AMPL_WIDTH),
conv_std_logic_vector(1047,AMPL_WIDTH),
conv_std_logic_vector(1050,AMPL_WIDTH),
conv_std_logic_vector(1052,AMPL_WIDTH),
conv_std_logic_vector(1055,AMPL_WIDTH),
conv_std_logic_vector(1058,AMPL_WIDTH),
conv_std_logic_vector(1060,AMPL_WIDTH),
conv_std_logic_vector(1063,AMPL_WIDTH),
conv_std_logic_vector(1066,AMPL_WIDTH),
conv_std_logic_vector(1068,AMPL_WIDTH),
conv_std_logic_vector(1071,AMPL_WIDTH),
conv_std_logic_vector(1074,AMPL_WIDTH),
conv_std_logic_vector(1077,AMPL_WIDTH),
conv_std_logic_vector(1079,AMPL_WIDTH),
conv_std_logic_vector(1082,AMPL_WIDTH),
conv_std_logic_vector(1085,AMPL_WIDTH),
conv_std_logic_vector(1087,AMPL_WIDTH),
conv_std_logic_vector(1090,AMPL_WIDTH),
conv_std_logic_vector(1092,AMPL_WIDTH),
conv_std_logic_vector(1095,AMPL_WIDTH),
conv_std_logic_vector(1098,AMPL_WIDTH),
conv_std_logic_vector(1100,AMPL_WIDTH),
conv_std_logic_vector(1103,AMPL_WIDTH),
conv_std_logic_vector(1106,AMPL_WIDTH),
conv_std_logic_vector(1108,AMPL_WIDTH),
conv_std_logic_vector(1111,AMPL_WIDTH),
conv_std_logic_vector(1114,AMPL_WIDTH),
conv_std_logic_vector(1116,AMPL_WIDTH),
conv_std_logic_vector(1119,AMPL_WIDTH),
conv_std_logic_vector(1122,AMPL_WIDTH),
conv_std_logic_vector(1124,AMPL_WIDTH),
conv_std_logic_vector(1127,AMPL_WIDTH),
conv_std_logic_vector(1129,AMPL_WIDTH),
conv_std_logic_vector(1132,AMPL_WIDTH),
conv_std_logic_vector(1135,AMPL_WIDTH),
conv_std_logic_vector(1137,AMPL_WIDTH),
conv_std_logic_vector(1140,AMPL_WIDTH),
conv_std_logic_vector(1142,AMPL_WIDTH),
conv_std_logic_vector(1145,AMPL_WIDTH),
conv_std_logic_vector(1148,AMPL_WIDTH),
conv_std_logic_vector(1150,AMPL_WIDTH),
conv_std_logic_vector(1153,AMPL_WIDTH),
conv_std_logic_vector(1155,AMPL_WIDTH),
conv_std_logic_vector(1158,AMPL_WIDTH),
conv_std_logic_vector(1161,AMPL_WIDTH),
conv_std_logic_vector(1163,AMPL_WIDTH),
conv_std_logic_vector(1166,AMPL_WIDTH),
conv_std_logic_vector(1168,AMPL_WIDTH),
conv_std_logic_vector(1171,AMPL_WIDTH),
conv_std_logic_vector(1174,AMPL_WIDTH),
conv_std_logic_vector(1176,AMPL_WIDTH),
conv_std_logic_vector(1179,AMPL_WIDTH),
conv_std_logic_vector(1181,AMPL_WIDTH),
conv_std_logic_vector(1184,AMPL_WIDTH),
conv_std_logic_vector(1186,AMPL_WIDTH),
conv_std_logic_vector(1189,AMPL_WIDTH),
conv_std_logic_vector(1191,AMPL_WIDTH),
conv_std_logic_vector(1194,AMPL_WIDTH),
conv_std_logic_vector(1197,AMPL_WIDTH),
conv_std_logic_vector(1199,AMPL_WIDTH),
conv_std_logic_vector(1202,AMPL_WIDTH),
conv_std_logic_vector(1204,AMPL_WIDTH),
conv_std_logic_vector(1207,AMPL_WIDTH),
conv_std_logic_vector(1209,AMPL_WIDTH),
conv_std_logic_vector(1212,AMPL_WIDTH),
conv_std_logic_vector(1214,AMPL_WIDTH),
conv_std_logic_vector(1217,AMPL_WIDTH),
conv_std_logic_vector(1219,AMPL_WIDTH),
conv_std_logic_vector(1222,AMPL_WIDTH),
conv_std_logic_vector(1224,AMPL_WIDTH),
conv_std_logic_vector(1227,AMPL_WIDTH),
conv_std_logic_vector(1229,AMPL_WIDTH),
conv_std_logic_vector(1232,AMPL_WIDTH),
conv_std_logic_vector(1234,AMPL_WIDTH),
conv_std_logic_vector(1237,AMPL_WIDTH),
conv_std_logic_vector(1239,AMPL_WIDTH),
conv_std_logic_vector(1242,AMPL_WIDTH),
conv_std_logic_vector(1244,AMPL_WIDTH),
conv_std_logic_vector(1247,AMPL_WIDTH),
conv_std_logic_vector(1249,AMPL_WIDTH),
conv_std_logic_vector(1252,AMPL_WIDTH),
conv_std_logic_vector(1254,AMPL_WIDTH),
conv_std_logic_vector(1257,AMPL_WIDTH),
conv_std_logic_vector(1259,AMPL_WIDTH),
conv_std_logic_vector(1262,AMPL_WIDTH),
conv_std_logic_vector(1264,AMPL_WIDTH),
conv_std_logic_vector(1267,AMPL_WIDTH),
conv_std_logic_vector(1269,AMPL_WIDTH),
conv_std_logic_vector(1272,AMPL_WIDTH),
conv_std_logic_vector(1274,AMPL_WIDTH),
conv_std_logic_vector(1277,AMPL_WIDTH),
conv_std_logic_vector(1279,AMPL_WIDTH),
conv_std_logic_vector(1282,AMPL_WIDTH),
conv_std_logic_vector(1284,AMPL_WIDTH),
conv_std_logic_vector(1286,AMPL_WIDTH),
conv_std_logic_vector(1289,AMPL_WIDTH),
conv_std_logic_vector(1291,AMPL_WIDTH),
conv_std_logic_vector(1294,AMPL_WIDTH),
conv_std_logic_vector(1296,AMPL_WIDTH),
conv_std_logic_vector(1299,AMPL_WIDTH),
conv_std_logic_vector(1301,AMPL_WIDTH),
conv_std_logic_vector(1303,AMPL_WIDTH),
conv_std_logic_vector(1306,AMPL_WIDTH),
conv_std_logic_vector(1308,AMPL_WIDTH),
conv_std_logic_vector(1311,AMPL_WIDTH),
conv_std_logic_vector(1313,AMPL_WIDTH),
conv_std_logic_vector(1316,AMPL_WIDTH),
conv_std_logic_vector(1318,AMPL_WIDTH),
conv_std_logic_vector(1320,AMPL_WIDTH),
conv_std_logic_vector(1323,AMPL_WIDTH),
conv_std_logic_vector(1325,AMPL_WIDTH),
conv_std_logic_vector(1328,AMPL_WIDTH),
conv_std_logic_vector(1330,AMPL_WIDTH),
conv_std_logic_vector(1332,AMPL_WIDTH),
conv_std_logic_vector(1335,AMPL_WIDTH),
conv_std_logic_vector(1337,AMPL_WIDTH),
conv_std_logic_vector(1339,AMPL_WIDTH),
conv_std_logic_vector(1342,AMPL_WIDTH),
conv_std_logic_vector(1344,AMPL_WIDTH),
conv_std_logic_vector(1347,AMPL_WIDTH),
conv_std_logic_vector(1349,AMPL_WIDTH),
conv_std_logic_vector(1351,AMPL_WIDTH),
conv_std_logic_vector(1354,AMPL_WIDTH),
conv_std_logic_vector(1356,AMPL_WIDTH),
conv_std_logic_vector(1358,AMPL_WIDTH),
conv_std_logic_vector(1361,AMPL_WIDTH),
conv_std_logic_vector(1363,AMPL_WIDTH),
conv_std_logic_vector(1365,AMPL_WIDTH),
conv_std_logic_vector(1368,AMPL_WIDTH),
conv_std_logic_vector(1370,AMPL_WIDTH),
conv_std_logic_vector(1372,AMPL_WIDTH),
conv_std_logic_vector(1375,AMPL_WIDTH),
conv_std_logic_vector(1377,AMPL_WIDTH),
conv_std_logic_vector(1379,AMPL_WIDTH),
conv_std_logic_vector(1382,AMPL_WIDTH),
conv_std_logic_vector(1384,AMPL_WIDTH),
conv_std_logic_vector(1386,AMPL_WIDTH),
conv_std_logic_vector(1389,AMPL_WIDTH),
conv_std_logic_vector(1391,AMPL_WIDTH),
conv_std_logic_vector(1393,AMPL_WIDTH),
conv_std_logic_vector(1395,AMPL_WIDTH),
conv_std_logic_vector(1398,AMPL_WIDTH),
conv_std_logic_vector(1400,AMPL_WIDTH),
conv_std_logic_vector(1402,AMPL_WIDTH),
conv_std_logic_vector(1405,AMPL_WIDTH),
conv_std_logic_vector(1407,AMPL_WIDTH),
conv_std_logic_vector(1409,AMPL_WIDTH),
conv_std_logic_vector(1411,AMPL_WIDTH),
conv_std_logic_vector(1414,AMPL_WIDTH),
conv_std_logic_vector(1416,AMPL_WIDTH),
conv_std_logic_vector(1418,AMPL_WIDTH),
conv_std_logic_vector(1421,AMPL_WIDTH),
conv_std_logic_vector(1423,AMPL_WIDTH),
conv_std_logic_vector(1425,AMPL_WIDTH),
conv_std_logic_vector(1427,AMPL_WIDTH),
conv_std_logic_vector(1430,AMPL_WIDTH),
conv_std_logic_vector(1432,AMPL_WIDTH),
conv_std_logic_vector(1434,AMPL_WIDTH),
conv_std_logic_vector(1436,AMPL_WIDTH),
conv_std_logic_vector(1439,AMPL_WIDTH),
conv_std_logic_vector(1441,AMPL_WIDTH),
conv_std_logic_vector(1443,AMPL_WIDTH),
conv_std_logic_vector(1445,AMPL_WIDTH),
conv_std_logic_vector(1447,AMPL_WIDTH),
conv_std_logic_vector(1450,AMPL_WIDTH),
conv_std_logic_vector(1452,AMPL_WIDTH),
conv_std_logic_vector(1454,AMPL_WIDTH),
conv_std_logic_vector(1456,AMPL_WIDTH),
conv_std_logic_vector(1459,AMPL_WIDTH),
conv_std_logic_vector(1461,AMPL_WIDTH),
conv_std_logic_vector(1463,AMPL_WIDTH),
conv_std_logic_vector(1465,AMPL_WIDTH),
conv_std_logic_vector(1467,AMPL_WIDTH),
conv_std_logic_vector(1469,AMPL_WIDTH),
conv_std_logic_vector(1472,AMPL_WIDTH),
conv_std_logic_vector(1474,AMPL_WIDTH),
conv_std_logic_vector(1476,AMPL_WIDTH),
conv_std_logic_vector(1478,AMPL_WIDTH),
conv_std_logic_vector(1480,AMPL_WIDTH),
conv_std_logic_vector(1483,AMPL_WIDTH),
conv_std_logic_vector(1485,AMPL_WIDTH),
conv_std_logic_vector(1487,AMPL_WIDTH),
conv_std_logic_vector(1489,AMPL_WIDTH),
conv_std_logic_vector(1491,AMPL_WIDTH),
conv_std_logic_vector(1493,AMPL_WIDTH),
conv_std_logic_vector(1495,AMPL_WIDTH),
conv_std_logic_vector(1498,AMPL_WIDTH),
conv_std_logic_vector(1500,AMPL_WIDTH),
conv_std_logic_vector(1502,AMPL_WIDTH),
conv_std_logic_vector(1504,AMPL_WIDTH),
conv_std_logic_vector(1506,AMPL_WIDTH),
conv_std_logic_vector(1508,AMPL_WIDTH),
conv_std_logic_vector(1510,AMPL_WIDTH),
conv_std_logic_vector(1513,AMPL_WIDTH),
conv_std_logic_vector(1515,AMPL_WIDTH),
conv_std_logic_vector(1517,AMPL_WIDTH),
conv_std_logic_vector(1519,AMPL_WIDTH),
conv_std_logic_vector(1521,AMPL_WIDTH),
conv_std_logic_vector(1523,AMPL_WIDTH),
conv_std_logic_vector(1525,AMPL_WIDTH),
conv_std_logic_vector(1527,AMPL_WIDTH),
conv_std_logic_vector(1529,AMPL_WIDTH),
conv_std_logic_vector(1531,AMPL_WIDTH),
conv_std_logic_vector(1533,AMPL_WIDTH),
conv_std_logic_vector(1536,AMPL_WIDTH),
conv_std_logic_vector(1538,AMPL_WIDTH),
conv_std_logic_vector(1540,AMPL_WIDTH),
conv_std_logic_vector(1542,AMPL_WIDTH),
conv_std_logic_vector(1544,AMPL_WIDTH),
conv_std_logic_vector(1546,AMPL_WIDTH),
conv_std_logic_vector(1548,AMPL_WIDTH),
conv_std_logic_vector(1550,AMPL_WIDTH),
conv_std_logic_vector(1552,AMPL_WIDTH),
conv_std_logic_vector(1554,AMPL_WIDTH),
conv_std_logic_vector(1556,AMPL_WIDTH),
conv_std_logic_vector(1558,AMPL_WIDTH),
conv_std_logic_vector(1560,AMPL_WIDTH),
conv_std_logic_vector(1562,AMPL_WIDTH),
conv_std_logic_vector(1564,AMPL_WIDTH),
conv_std_logic_vector(1566,AMPL_WIDTH),
conv_std_logic_vector(1568,AMPL_WIDTH),
conv_std_logic_vector(1570,AMPL_WIDTH),
conv_std_logic_vector(1572,AMPL_WIDTH),
conv_std_logic_vector(1574,AMPL_WIDTH),
conv_std_logic_vector(1576,AMPL_WIDTH),
conv_std_logic_vector(1578,AMPL_WIDTH),
conv_std_logic_vector(1580,AMPL_WIDTH),
conv_std_logic_vector(1582,AMPL_WIDTH),
conv_std_logic_vector(1584,AMPL_WIDTH),
conv_std_logic_vector(1586,AMPL_WIDTH),
conv_std_logic_vector(1588,AMPL_WIDTH),
conv_std_logic_vector(1590,AMPL_WIDTH),
conv_std_logic_vector(1592,AMPL_WIDTH),
conv_std_logic_vector(1594,AMPL_WIDTH),
conv_std_logic_vector(1596,AMPL_WIDTH),
conv_std_logic_vector(1598,AMPL_WIDTH),
conv_std_logic_vector(1600,AMPL_WIDTH),
conv_std_logic_vector(1602,AMPL_WIDTH),
conv_std_logic_vector(1604,AMPL_WIDTH),
conv_std_logic_vector(1606,AMPL_WIDTH),
conv_std_logic_vector(1608,AMPL_WIDTH),
conv_std_logic_vector(1610,AMPL_WIDTH),
conv_std_logic_vector(1612,AMPL_WIDTH),
conv_std_logic_vector(1614,AMPL_WIDTH),
conv_std_logic_vector(1616,AMPL_WIDTH),
conv_std_logic_vector(1618,AMPL_WIDTH),
conv_std_logic_vector(1620,AMPL_WIDTH),
conv_std_logic_vector(1621,AMPL_WIDTH),
conv_std_logic_vector(1623,AMPL_WIDTH),
conv_std_logic_vector(1625,AMPL_WIDTH),
conv_std_logic_vector(1627,AMPL_WIDTH),
conv_std_logic_vector(1629,AMPL_WIDTH),
conv_std_logic_vector(1631,AMPL_WIDTH),
conv_std_logic_vector(1633,AMPL_WIDTH),
conv_std_logic_vector(1635,AMPL_WIDTH),
conv_std_logic_vector(1637,AMPL_WIDTH),
conv_std_logic_vector(1639,AMPL_WIDTH),
conv_std_logic_vector(1640,AMPL_WIDTH),
conv_std_logic_vector(1642,AMPL_WIDTH),
conv_std_logic_vector(1644,AMPL_WIDTH),
conv_std_logic_vector(1646,AMPL_WIDTH),
conv_std_logic_vector(1648,AMPL_WIDTH),
conv_std_logic_vector(1650,AMPL_WIDTH),
conv_std_logic_vector(1652,AMPL_WIDTH),
conv_std_logic_vector(1653,AMPL_WIDTH),
conv_std_logic_vector(1655,AMPL_WIDTH),
conv_std_logic_vector(1657,AMPL_WIDTH),
conv_std_logic_vector(1659,AMPL_WIDTH),
conv_std_logic_vector(1661,AMPL_WIDTH),
conv_std_logic_vector(1663,AMPL_WIDTH),
conv_std_logic_vector(1665,AMPL_WIDTH),
conv_std_logic_vector(1666,AMPL_WIDTH),
conv_std_logic_vector(1668,AMPL_WIDTH),
conv_std_logic_vector(1670,AMPL_WIDTH),
conv_std_logic_vector(1672,AMPL_WIDTH),
conv_std_logic_vector(1674,AMPL_WIDTH),
conv_std_logic_vector(1675,AMPL_WIDTH),
conv_std_logic_vector(1677,AMPL_WIDTH),
conv_std_logic_vector(1679,AMPL_WIDTH),
conv_std_logic_vector(1681,AMPL_WIDTH),
conv_std_logic_vector(1683,AMPL_WIDTH),
conv_std_logic_vector(1684,AMPL_WIDTH),
conv_std_logic_vector(1686,AMPL_WIDTH),
conv_std_logic_vector(1688,AMPL_WIDTH),
conv_std_logic_vector(1690,AMPL_WIDTH),
conv_std_logic_vector(1691,AMPL_WIDTH),
conv_std_logic_vector(1693,AMPL_WIDTH),
conv_std_logic_vector(1695,AMPL_WIDTH),
conv_std_logic_vector(1697,AMPL_WIDTH),
conv_std_logic_vector(1699,AMPL_WIDTH),
conv_std_logic_vector(1700,AMPL_WIDTH),
conv_std_logic_vector(1702,AMPL_WIDTH),
conv_std_logic_vector(1704,AMPL_WIDTH),
conv_std_logic_vector(1705,AMPL_WIDTH),
conv_std_logic_vector(1707,AMPL_WIDTH),
conv_std_logic_vector(1709,AMPL_WIDTH),
conv_std_logic_vector(1711,AMPL_WIDTH),
conv_std_logic_vector(1712,AMPL_WIDTH),
conv_std_logic_vector(1714,AMPL_WIDTH),
conv_std_logic_vector(1716,AMPL_WIDTH),
conv_std_logic_vector(1718,AMPL_WIDTH),
conv_std_logic_vector(1719,AMPL_WIDTH),
conv_std_logic_vector(1721,AMPL_WIDTH),
conv_std_logic_vector(1723,AMPL_WIDTH),
conv_std_logic_vector(1724,AMPL_WIDTH),
conv_std_logic_vector(1726,AMPL_WIDTH),
conv_std_logic_vector(1728,AMPL_WIDTH),
conv_std_logic_vector(1729,AMPL_WIDTH),
conv_std_logic_vector(1731,AMPL_WIDTH),
conv_std_logic_vector(1733,AMPL_WIDTH),
conv_std_logic_vector(1734,AMPL_WIDTH),
conv_std_logic_vector(1736,AMPL_WIDTH),
conv_std_logic_vector(1738,AMPL_WIDTH),
conv_std_logic_vector(1739,AMPL_WIDTH),
conv_std_logic_vector(1741,AMPL_WIDTH),
conv_std_logic_vector(1743,AMPL_WIDTH),
conv_std_logic_vector(1744,AMPL_WIDTH),
conv_std_logic_vector(1746,AMPL_WIDTH),
conv_std_logic_vector(1748,AMPL_WIDTH),
conv_std_logic_vector(1749,AMPL_WIDTH),
conv_std_logic_vector(1751,AMPL_WIDTH),
conv_std_logic_vector(1753,AMPL_WIDTH),
conv_std_logic_vector(1754,AMPL_WIDTH),
conv_std_logic_vector(1756,AMPL_WIDTH),
conv_std_logic_vector(1757,AMPL_WIDTH),
conv_std_logic_vector(1759,AMPL_WIDTH),
conv_std_logic_vector(1761,AMPL_WIDTH),
conv_std_logic_vector(1762,AMPL_WIDTH),
conv_std_logic_vector(1764,AMPL_WIDTH),
conv_std_logic_vector(1765,AMPL_WIDTH),
conv_std_logic_vector(1767,AMPL_WIDTH),
conv_std_logic_vector(1769,AMPL_WIDTH),
conv_std_logic_vector(1770,AMPL_WIDTH),
conv_std_logic_vector(1772,AMPL_WIDTH),
conv_std_logic_vector(1773,AMPL_WIDTH),
conv_std_logic_vector(1775,AMPL_WIDTH),
conv_std_logic_vector(1776,AMPL_WIDTH),
conv_std_logic_vector(1778,AMPL_WIDTH),
conv_std_logic_vector(1780,AMPL_WIDTH),
conv_std_logic_vector(1781,AMPL_WIDTH),
conv_std_logic_vector(1783,AMPL_WIDTH),
conv_std_logic_vector(1784,AMPL_WIDTH),
conv_std_logic_vector(1786,AMPL_WIDTH),
conv_std_logic_vector(1787,AMPL_WIDTH),
conv_std_logic_vector(1789,AMPL_WIDTH),
conv_std_logic_vector(1790,AMPL_WIDTH),
conv_std_logic_vector(1792,AMPL_WIDTH),
conv_std_logic_vector(1793,AMPL_WIDTH),
conv_std_logic_vector(1795,AMPL_WIDTH),
conv_std_logic_vector(1796,AMPL_WIDTH),
conv_std_logic_vector(1798,AMPL_WIDTH),
conv_std_logic_vector(1799,AMPL_WIDTH),
conv_std_logic_vector(1801,AMPL_WIDTH),
conv_std_logic_vector(1802,AMPL_WIDTH),
conv_std_logic_vector(1804,AMPL_WIDTH),
conv_std_logic_vector(1805,AMPL_WIDTH),
conv_std_logic_vector(1807,AMPL_WIDTH),
conv_std_logic_vector(1808,AMPL_WIDTH),
conv_std_logic_vector(1810,AMPL_WIDTH),
conv_std_logic_vector(1811,AMPL_WIDTH),
conv_std_logic_vector(1813,AMPL_WIDTH),
conv_std_logic_vector(1814,AMPL_WIDTH),
conv_std_logic_vector(1816,AMPL_WIDTH),
conv_std_logic_vector(1817,AMPL_WIDTH),
conv_std_logic_vector(1818,AMPL_WIDTH),
conv_std_logic_vector(1820,AMPL_WIDTH),
conv_std_logic_vector(1821,AMPL_WIDTH),
conv_std_logic_vector(1823,AMPL_WIDTH),
conv_std_logic_vector(1824,AMPL_WIDTH),
conv_std_logic_vector(1826,AMPL_WIDTH),
conv_std_logic_vector(1827,AMPL_WIDTH),
conv_std_logic_vector(1828,AMPL_WIDTH),
conv_std_logic_vector(1830,AMPL_WIDTH),
conv_std_logic_vector(1831,AMPL_WIDTH),
conv_std_logic_vector(1833,AMPL_WIDTH),
conv_std_logic_vector(1834,AMPL_WIDTH),
conv_std_logic_vector(1835,AMPL_WIDTH),
conv_std_logic_vector(1837,AMPL_WIDTH),
conv_std_logic_vector(1838,AMPL_WIDTH),
conv_std_logic_vector(1840,AMPL_WIDTH),
conv_std_logic_vector(1841,AMPL_WIDTH),
conv_std_logic_vector(1842,AMPL_WIDTH),
conv_std_logic_vector(1844,AMPL_WIDTH),
conv_std_logic_vector(1845,AMPL_WIDTH),
conv_std_logic_vector(1846,AMPL_WIDTH),
conv_std_logic_vector(1848,AMPL_WIDTH),
conv_std_logic_vector(1849,AMPL_WIDTH),
conv_std_logic_vector(1850,AMPL_WIDTH),
conv_std_logic_vector(1852,AMPL_WIDTH),
conv_std_logic_vector(1853,AMPL_WIDTH),
conv_std_logic_vector(1854,AMPL_WIDTH),
conv_std_logic_vector(1856,AMPL_WIDTH),
conv_std_logic_vector(1857,AMPL_WIDTH),
conv_std_logic_vector(1858,AMPL_WIDTH),
conv_std_logic_vector(1860,AMPL_WIDTH),
conv_std_logic_vector(1861,AMPL_WIDTH),
conv_std_logic_vector(1862,AMPL_WIDTH),
conv_std_logic_vector(1864,AMPL_WIDTH),
conv_std_logic_vector(1865,AMPL_WIDTH),
conv_std_logic_vector(1866,AMPL_WIDTH),
conv_std_logic_vector(1868,AMPL_WIDTH),
conv_std_logic_vector(1869,AMPL_WIDTH),
conv_std_logic_vector(1870,AMPL_WIDTH),
conv_std_logic_vector(1871,AMPL_WIDTH),
conv_std_logic_vector(1873,AMPL_WIDTH),
conv_std_logic_vector(1874,AMPL_WIDTH),
conv_std_logic_vector(1875,AMPL_WIDTH),
conv_std_logic_vector(1876,AMPL_WIDTH),
conv_std_logic_vector(1878,AMPL_WIDTH),
conv_std_logic_vector(1879,AMPL_WIDTH),
conv_std_logic_vector(1880,AMPL_WIDTH),
conv_std_logic_vector(1881,AMPL_WIDTH),
conv_std_logic_vector(1883,AMPL_WIDTH),
conv_std_logic_vector(1884,AMPL_WIDTH),
conv_std_logic_vector(1885,AMPL_WIDTH),
conv_std_logic_vector(1886,AMPL_WIDTH),
conv_std_logic_vector(1888,AMPL_WIDTH),
conv_std_logic_vector(1889,AMPL_WIDTH),
conv_std_logic_vector(1890,AMPL_WIDTH),
conv_std_logic_vector(1891,AMPL_WIDTH),
conv_std_logic_vector(1892,AMPL_WIDTH),
conv_std_logic_vector(1894,AMPL_WIDTH),
conv_std_logic_vector(1895,AMPL_WIDTH),
conv_std_logic_vector(1896,AMPL_WIDTH),
conv_std_logic_vector(1897,AMPL_WIDTH),
conv_std_logic_vector(1898,AMPL_WIDTH),
conv_std_logic_vector(1899,AMPL_WIDTH),
conv_std_logic_vector(1901,AMPL_WIDTH),
conv_std_logic_vector(1902,AMPL_WIDTH),
conv_std_logic_vector(1903,AMPL_WIDTH),
conv_std_logic_vector(1904,AMPL_WIDTH),
conv_std_logic_vector(1905,AMPL_WIDTH),
conv_std_logic_vector(1906,AMPL_WIDTH),
conv_std_logic_vector(1908,AMPL_WIDTH),
conv_std_logic_vector(1909,AMPL_WIDTH),
conv_std_logic_vector(1910,AMPL_WIDTH),
conv_std_logic_vector(1911,AMPL_WIDTH),
conv_std_logic_vector(1912,AMPL_WIDTH),
conv_std_logic_vector(1913,AMPL_WIDTH),
conv_std_logic_vector(1914,AMPL_WIDTH),
conv_std_logic_vector(1915,AMPL_WIDTH),
conv_std_logic_vector(1917,AMPL_WIDTH),
conv_std_logic_vector(1918,AMPL_WIDTH),
conv_std_logic_vector(1919,AMPL_WIDTH),
conv_std_logic_vector(1920,AMPL_WIDTH),
conv_std_logic_vector(1921,AMPL_WIDTH),
conv_std_logic_vector(1922,AMPL_WIDTH),
conv_std_logic_vector(1923,AMPL_WIDTH),
conv_std_logic_vector(1924,AMPL_WIDTH),
conv_std_logic_vector(1925,AMPL_WIDTH),
conv_std_logic_vector(1926,AMPL_WIDTH),
conv_std_logic_vector(1927,AMPL_WIDTH),
conv_std_logic_vector(1928,AMPL_WIDTH),
conv_std_logic_vector(1929,AMPL_WIDTH),
conv_std_logic_vector(1930,AMPL_WIDTH),
conv_std_logic_vector(1932,AMPL_WIDTH),
conv_std_logic_vector(1933,AMPL_WIDTH),
conv_std_logic_vector(1934,AMPL_WIDTH),
conv_std_logic_vector(1935,AMPL_WIDTH),
conv_std_logic_vector(1936,AMPL_WIDTH),
conv_std_logic_vector(1937,AMPL_WIDTH),
conv_std_logic_vector(1938,AMPL_WIDTH),
conv_std_logic_vector(1939,AMPL_WIDTH),
conv_std_logic_vector(1940,AMPL_WIDTH),
conv_std_logic_vector(1941,AMPL_WIDTH),
conv_std_logic_vector(1942,AMPL_WIDTH),
conv_std_logic_vector(1943,AMPL_WIDTH),
conv_std_logic_vector(1944,AMPL_WIDTH),
conv_std_logic_vector(1945,AMPL_WIDTH),
conv_std_logic_vector(1946,AMPL_WIDTH),
conv_std_logic_vector(1947,AMPL_WIDTH),
conv_std_logic_vector(1948,AMPL_WIDTH),
conv_std_logic_vector(1949,AMPL_WIDTH),
conv_std_logic_vector(1950,AMPL_WIDTH),
conv_std_logic_vector(1950,AMPL_WIDTH),
conv_std_logic_vector(1951,AMPL_WIDTH),
conv_std_logic_vector(1952,AMPL_WIDTH),
conv_std_logic_vector(1953,AMPL_WIDTH),
conv_std_logic_vector(1954,AMPL_WIDTH),
conv_std_logic_vector(1955,AMPL_WIDTH),
conv_std_logic_vector(1956,AMPL_WIDTH),
conv_std_logic_vector(1957,AMPL_WIDTH),
conv_std_logic_vector(1958,AMPL_WIDTH),
conv_std_logic_vector(1959,AMPL_WIDTH),
conv_std_logic_vector(1960,AMPL_WIDTH),
conv_std_logic_vector(1961,AMPL_WIDTH),
conv_std_logic_vector(1962,AMPL_WIDTH),
conv_std_logic_vector(1962,AMPL_WIDTH),
conv_std_logic_vector(1963,AMPL_WIDTH),
conv_std_logic_vector(1964,AMPL_WIDTH),
conv_std_logic_vector(1965,AMPL_WIDTH),
conv_std_logic_vector(1966,AMPL_WIDTH),
conv_std_logic_vector(1967,AMPL_WIDTH),
conv_std_logic_vector(1968,AMPL_WIDTH),
conv_std_logic_vector(1969,AMPL_WIDTH),
conv_std_logic_vector(1969,AMPL_WIDTH),
conv_std_logic_vector(1970,AMPL_WIDTH),
conv_std_logic_vector(1971,AMPL_WIDTH),
conv_std_logic_vector(1972,AMPL_WIDTH),
conv_std_logic_vector(1973,AMPL_WIDTH),
conv_std_logic_vector(1974,AMPL_WIDTH),
conv_std_logic_vector(1975,AMPL_WIDTH),
conv_std_logic_vector(1975,AMPL_WIDTH),
conv_std_logic_vector(1976,AMPL_WIDTH),
conv_std_logic_vector(1977,AMPL_WIDTH),
conv_std_logic_vector(1978,AMPL_WIDTH),
conv_std_logic_vector(1979,AMPL_WIDTH),
conv_std_logic_vector(1979,AMPL_WIDTH),
conv_std_logic_vector(1980,AMPL_WIDTH),
conv_std_logic_vector(1981,AMPL_WIDTH),
conv_std_logic_vector(1982,AMPL_WIDTH),
conv_std_logic_vector(1983,AMPL_WIDTH),
conv_std_logic_vector(1983,AMPL_WIDTH),
conv_std_logic_vector(1984,AMPL_WIDTH),
conv_std_logic_vector(1985,AMPL_WIDTH),
conv_std_logic_vector(1986,AMPL_WIDTH),
conv_std_logic_vector(1986,AMPL_WIDTH),
conv_std_logic_vector(1987,AMPL_WIDTH),
conv_std_logic_vector(1988,AMPL_WIDTH),
conv_std_logic_vector(1989,AMPL_WIDTH),
conv_std_logic_vector(1989,AMPL_WIDTH),
conv_std_logic_vector(1990,AMPL_WIDTH),
conv_std_logic_vector(1991,AMPL_WIDTH),
conv_std_logic_vector(1992,AMPL_WIDTH),
conv_std_logic_vector(1992,AMPL_WIDTH),
conv_std_logic_vector(1993,AMPL_WIDTH),
conv_std_logic_vector(1994,AMPL_WIDTH),
conv_std_logic_vector(1994,AMPL_WIDTH),
conv_std_logic_vector(1995,AMPL_WIDTH),
conv_std_logic_vector(1996,AMPL_WIDTH),
conv_std_logic_vector(1997,AMPL_WIDTH),
conv_std_logic_vector(1997,AMPL_WIDTH),
conv_std_logic_vector(1998,AMPL_WIDTH),
conv_std_logic_vector(1999,AMPL_WIDTH),
conv_std_logic_vector(1999,AMPL_WIDTH),
conv_std_logic_vector(2000,AMPL_WIDTH),
conv_std_logic_vector(2001,AMPL_WIDTH),
conv_std_logic_vector(2001,AMPL_WIDTH),
conv_std_logic_vector(2002,AMPL_WIDTH),
conv_std_logic_vector(2003,AMPL_WIDTH),
conv_std_logic_vector(2003,AMPL_WIDTH),
conv_std_logic_vector(2004,AMPL_WIDTH),
conv_std_logic_vector(2005,AMPL_WIDTH),
conv_std_logic_vector(2005,AMPL_WIDTH),
conv_std_logic_vector(2006,AMPL_WIDTH),
conv_std_logic_vector(2006,AMPL_WIDTH),
conv_std_logic_vector(2007,AMPL_WIDTH),
conv_std_logic_vector(2008,AMPL_WIDTH),
conv_std_logic_vector(2008,AMPL_WIDTH),
conv_std_logic_vector(2009,AMPL_WIDTH),
conv_std_logic_vector(2009,AMPL_WIDTH),
conv_std_logic_vector(2010,AMPL_WIDTH),
conv_std_logic_vector(2011,AMPL_WIDTH),
conv_std_logic_vector(2011,AMPL_WIDTH),
conv_std_logic_vector(2012,AMPL_WIDTH),
conv_std_logic_vector(2012,AMPL_WIDTH),
conv_std_logic_vector(2013,AMPL_WIDTH),
conv_std_logic_vector(2014,AMPL_WIDTH),
conv_std_logic_vector(2014,AMPL_WIDTH),
conv_std_logic_vector(2015,AMPL_WIDTH),
conv_std_logic_vector(2015,AMPL_WIDTH),
conv_std_logic_vector(2016,AMPL_WIDTH),
conv_std_logic_vector(2016,AMPL_WIDTH),
conv_std_logic_vector(2017,AMPL_WIDTH),
conv_std_logic_vector(2017,AMPL_WIDTH),
conv_std_logic_vector(2018,AMPL_WIDTH),
conv_std_logic_vector(2018,AMPL_WIDTH),
conv_std_logic_vector(2019,AMPL_WIDTH),
conv_std_logic_vector(2019,AMPL_WIDTH),
conv_std_logic_vector(2020,AMPL_WIDTH),
conv_std_logic_vector(2021,AMPL_WIDTH),
conv_std_logic_vector(2021,AMPL_WIDTH),
conv_std_logic_vector(2022,AMPL_WIDTH),
conv_std_logic_vector(2022,AMPL_WIDTH),
conv_std_logic_vector(2022,AMPL_WIDTH),
conv_std_logic_vector(2023,AMPL_WIDTH),
conv_std_logic_vector(2023,AMPL_WIDTH),
conv_std_logic_vector(2024,AMPL_WIDTH),
conv_std_logic_vector(2024,AMPL_WIDTH),
conv_std_logic_vector(2025,AMPL_WIDTH),
conv_std_logic_vector(2025,AMPL_WIDTH),
conv_std_logic_vector(2026,AMPL_WIDTH),
conv_std_logic_vector(2026,AMPL_WIDTH),
conv_std_logic_vector(2027,AMPL_WIDTH),
conv_std_logic_vector(2027,AMPL_WIDTH),
conv_std_logic_vector(2028,AMPL_WIDTH),
conv_std_logic_vector(2028,AMPL_WIDTH),
conv_std_logic_vector(2028,AMPL_WIDTH),
conv_std_logic_vector(2029,AMPL_WIDTH),
conv_std_logic_vector(2029,AMPL_WIDTH),
conv_std_logic_vector(2030,AMPL_WIDTH),
conv_std_logic_vector(2030,AMPL_WIDTH),
conv_std_logic_vector(2030,AMPL_WIDTH),
conv_std_logic_vector(2031,AMPL_WIDTH),
conv_std_logic_vector(2031,AMPL_WIDTH),
conv_std_logic_vector(2032,AMPL_WIDTH),
conv_std_logic_vector(2032,AMPL_WIDTH),
conv_std_logic_vector(2032,AMPL_WIDTH),
conv_std_logic_vector(2033,AMPL_WIDTH),
conv_std_logic_vector(2033,AMPL_WIDTH),
conv_std_logic_vector(2033,AMPL_WIDTH),
conv_std_logic_vector(2034,AMPL_WIDTH),
conv_std_logic_vector(2034,AMPL_WIDTH),
conv_std_logic_vector(2035,AMPL_WIDTH),
conv_std_logic_vector(2035,AMPL_WIDTH),
conv_std_logic_vector(2035,AMPL_WIDTH),
conv_std_logic_vector(2036,AMPL_WIDTH),
conv_std_logic_vector(2036,AMPL_WIDTH),
conv_std_logic_vector(2036,AMPL_WIDTH),
conv_std_logic_vector(2037,AMPL_WIDTH),
conv_std_logic_vector(2037,AMPL_WIDTH),
conv_std_logic_vector(2037,AMPL_WIDTH),
conv_std_logic_vector(2037,AMPL_WIDTH),
conv_std_logic_vector(2038,AMPL_WIDTH),
conv_std_logic_vector(2038,AMPL_WIDTH),
conv_std_logic_vector(2038,AMPL_WIDTH),
conv_std_logic_vector(2039,AMPL_WIDTH),
conv_std_logic_vector(2039,AMPL_WIDTH),
conv_std_logic_vector(2039,AMPL_WIDTH),
conv_std_logic_vector(2039,AMPL_WIDTH),
conv_std_logic_vector(2040,AMPL_WIDTH),
conv_std_logic_vector(2040,AMPL_WIDTH),
conv_std_logic_vector(2040,AMPL_WIDTH),
conv_std_logic_vector(2040,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH)
);
end sine_lut_pkg;
package body sine_lut_pkg is
end sine_lut_pkg; |
-- This file is automatically generated by a matlab script
--
-- Do not modify directly!
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_signed.all;
package sine_lut_pkg is
constant PHASE_WIDTH : integer := 12;
constant AMPL_WIDTH : integer := 12;
type lut_type is array(0 to 2**(PHASE_WIDTH-2)-1) of std_logic_vector(AMPL_WIDTH-1 downto 0);
constant sine_lut : lut_type := (
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(421,AMPL_WIDTH),
conv_std_logic_vector(424,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(439,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(467,AMPL_WIDTH),
conv_std_logic_vector(470,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(494,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(513,AMPL_WIDTH),
conv_std_logic_vector(516,AMPL_WIDTH),
conv_std_logic_vector(519,AMPL_WIDTH),
conv_std_logic_vector(522,AMPL_WIDTH),
conv_std_logic_vector(525,AMPL_WIDTH),
conv_std_logic_vector(528,AMPL_WIDTH),
conv_std_logic_vector(531,AMPL_WIDTH),
conv_std_logic_vector(534,AMPL_WIDTH),
conv_std_logic_vector(537,AMPL_WIDTH),
conv_std_logic_vector(540,AMPL_WIDTH),
conv_std_logic_vector(543,AMPL_WIDTH),
conv_std_logic_vector(546,AMPL_WIDTH),
conv_std_logic_vector(549,AMPL_WIDTH),
conv_std_logic_vector(552,AMPL_WIDTH),
conv_std_logic_vector(555,AMPL_WIDTH),
conv_std_logic_vector(558,AMPL_WIDTH),
conv_std_logic_vector(561,AMPL_WIDTH),
conv_std_logic_vector(564,AMPL_WIDTH),
conv_std_logic_vector(567,AMPL_WIDTH),
conv_std_logic_vector(570,AMPL_WIDTH),
conv_std_logic_vector(573,AMPL_WIDTH),
conv_std_logic_vector(576,AMPL_WIDTH),
conv_std_logic_vector(579,AMPL_WIDTH),
conv_std_logic_vector(582,AMPL_WIDTH),
conv_std_logic_vector(585,AMPL_WIDTH),
conv_std_logic_vector(588,AMPL_WIDTH),
conv_std_logic_vector(591,AMPL_WIDTH),
conv_std_logic_vector(594,AMPL_WIDTH),
conv_std_logic_vector(597,AMPL_WIDTH),
conv_std_logic_vector(600,AMPL_WIDTH),
conv_std_logic_vector(603,AMPL_WIDTH),
conv_std_logic_vector(606,AMPL_WIDTH),
conv_std_logic_vector(609,AMPL_WIDTH),
conv_std_logic_vector(612,AMPL_WIDTH),
conv_std_logic_vector(615,AMPL_WIDTH),
conv_std_logic_vector(618,AMPL_WIDTH),
conv_std_logic_vector(621,AMPL_WIDTH),
conv_std_logic_vector(624,AMPL_WIDTH),
conv_std_logic_vector(627,AMPL_WIDTH),
conv_std_logic_vector(630,AMPL_WIDTH),
conv_std_logic_vector(633,AMPL_WIDTH),
conv_std_logic_vector(636,AMPL_WIDTH),
conv_std_logic_vector(639,AMPL_WIDTH),
conv_std_logic_vector(642,AMPL_WIDTH),
conv_std_logic_vector(645,AMPL_WIDTH),
conv_std_logic_vector(648,AMPL_WIDTH),
conv_std_logic_vector(651,AMPL_WIDTH),
conv_std_logic_vector(654,AMPL_WIDTH),
conv_std_logic_vector(657,AMPL_WIDTH),
conv_std_logic_vector(660,AMPL_WIDTH),
conv_std_logic_vector(663,AMPL_WIDTH),
conv_std_logic_vector(666,AMPL_WIDTH),
conv_std_logic_vector(669,AMPL_WIDTH),
conv_std_logic_vector(672,AMPL_WIDTH),
conv_std_logic_vector(675,AMPL_WIDTH),
conv_std_logic_vector(678,AMPL_WIDTH),
conv_std_logic_vector(681,AMPL_WIDTH),
conv_std_logic_vector(684,AMPL_WIDTH),
conv_std_logic_vector(687,AMPL_WIDTH),
conv_std_logic_vector(690,AMPL_WIDTH),
conv_std_logic_vector(693,AMPL_WIDTH),
conv_std_logic_vector(696,AMPL_WIDTH),
conv_std_logic_vector(698,AMPL_WIDTH),
conv_std_logic_vector(701,AMPL_WIDTH),
conv_std_logic_vector(704,AMPL_WIDTH),
conv_std_logic_vector(707,AMPL_WIDTH),
conv_std_logic_vector(710,AMPL_WIDTH),
conv_std_logic_vector(713,AMPL_WIDTH),
conv_std_logic_vector(716,AMPL_WIDTH),
conv_std_logic_vector(719,AMPL_WIDTH),
conv_std_logic_vector(722,AMPL_WIDTH),
conv_std_logic_vector(725,AMPL_WIDTH),
conv_std_logic_vector(728,AMPL_WIDTH),
conv_std_logic_vector(731,AMPL_WIDTH),
conv_std_logic_vector(734,AMPL_WIDTH),
conv_std_logic_vector(737,AMPL_WIDTH),
conv_std_logic_vector(740,AMPL_WIDTH),
conv_std_logic_vector(743,AMPL_WIDTH),
conv_std_logic_vector(745,AMPL_WIDTH),
conv_std_logic_vector(748,AMPL_WIDTH),
conv_std_logic_vector(751,AMPL_WIDTH),
conv_std_logic_vector(754,AMPL_WIDTH),
conv_std_logic_vector(757,AMPL_WIDTH),
conv_std_logic_vector(760,AMPL_WIDTH),
conv_std_logic_vector(763,AMPL_WIDTH),
conv_std_logic_vector(766,AMPL_WIDTH),
conv_std_logic_vector(769,AMPL_WIDTH),
conv_std_logic_vector(772,AMPL_WIDTH),
conv_std_logic_vector(775,AMPL_WIDTH),
conv_std_logic_vector(778,AMPL_WIDTH),
conv_std_logic_vector(780,AMPL_WIDTH),
conv_std_logic_vector(783,AMPL_WIDTH),
conv_std_logic_vector(786,AMPL_WIDTH),
conv_std_logic_vector(789,AMPL_WIDTH),
conv_std_logic_vector(792,AMPL_WIDTH),
conv_std_logic_vector(795,AMPL_WIDTH),
conv_std_logic_vector(798,AMPL_WIDTH),
conv_std_logic_vector(801,AMPL_WIDTH),
conv_std_logic_vector(804,AMPL_WIDTH),
conv_std_logic_vector(807,AMPL_WIDTH),
conv_std_logic_vector(809,AMPL_WIDTH),
conv_std_logic_vector(812,AMPL_WIDTH),
conv_std_logic_vector(815,AMPL_WIDTH),
conv_std_logic_vector(818,AMPL_WIDTH),
conv_std_logic_vector(821,AMPL_WIDTH),
conv_std_logic_vector(824,AMPL_WIDTH),
conv_std_logic_vector(827,AMPL_WIDTH),
conv_std_logic_vector(830,AMPL_WIDTH),
conv_std_logic_vector(832,AMPL_WIDTH),
conv_std_logic_vector(835,AMPL_WIDTH),
conv_std_logic_vector(838,AMPL_WIDTH),
conv_std_logic_vector(841,AMPL_WIDTH),
conv_std_logic_vector(844,AMPL_WIDTH),
conv_std_logic_vector(847,AMPL_WIDTH),
conv_std_logic_vector(850,AMPL_WIDTH),
conv_std_logic_vector(852,AMPL_WIDTH),
conv_std_logic_vector(855,AMPL_WIDTH),
conv_std_logic_vector(858,AMPL_WIDTH),
conv_std_logic_vector(861,AMPL_WIDTH),
conv_std_logic_vector(864,AMPL_WIDTH),
conv_std_logic_vector(867,AMPL_WIDTH),
conv_std_logic_vector(870,AMPL_WIDTH),
conv_std_logic_vector(872,AMPL_WIDTH),
conv_std_logic_vector(875,AMPL_WIDTH),
conv_std_logic_vector(878,AMPL_WIDTH),
conv_std_logic_vector(881,AMPL_WIDTH),
conv_std_logic_vector(884,AMPL_WIDTH),
conv_std_logic_vector(887,AMPL_WIDTH),
conv_std_logic_vector(889,AMPL_WIDTH),
conv_std_logic_vector(892,AMPL_WIDTH),
conv_std_logic_vector(895,AMPL_WIDTH),
conv_std_logic_vector(898,AMPL_WIDTH),
conv_std_logic_vector(901,AMPL_WIDTH),
conv_std_logic_vector(903,AMPL_WIDTH),
conv_std_logic_vector(906,AMPL_WIDTH),
conv_std_logic_vector(909,AMPL_WIDTH),
conv_std_logic_vector(912,AMPL_WIDTH),
conv_std_logic_vector(915,AMPL_WIDTH),
conv_std_logic_vector(918,AMPL_WIDTH),
conv_std_logic_vector(920,AMPL_WIDTH),
conv_std_logic_vector(923,AMPL_WIDTH),
conv_std_logic_vector(926,AMPL_WIDTH),
conv_std_logic_vector(929,AMPL_WIDTH),
conv_std_logic_vector(932,AMPL_WIDTH),
conv_std_logic_vector(934,AMPL_WIDTH),
conv_std_logic_vector(937,AMPL_WIDTH),
conv_std_logic_vector(940,AMPL_WIDTH),
conv_std_logic_vector(943,AMPL_WIDTH),
conv_std_logic_vector(946,AMPL_WIDTH),
conv_std_logic_vector(948,AMPL_WIDTH),
conv_std_logic_vector(951,AMPL_WIDTH),
conv_std_logic_vector(954,AMPL_WIDTH),
conv_std_logic_vector(957,AMPL_WIDTH),
conv_std_logic_vector(959,AMPL_WIDTH),
conv_std_logic_vector(962,AMPL_WIDTH),
conv_std_logic_vector(965,AMPL_WIDTH),
conv_std_logic_vector(968,AMPL_WIDTH),
conv_std_logic_vector(970,AMPL_WIDTH),
conv_std_logic_vector(973,AMPL_WIDTH),
conv_std_logic_vector(976,AMPL_WIDTH),
conv_std_logic_vector(979,AMPL_WIDTH),
conv_std_logic_vector(982,AMPL_WIDTH),
conv_std_logic_vector(984,AMPL_WIDTH),
conv_std_logic_vector(987,AMPL_WIDTH),
conv_std_logic_vector(990,AMPL_WIDTH),
conv_std_logic_vector(993,AMPL_WIDTH),
conv_std_logic_vector(995,AMPL_WIDTH),
conv_std_logic_vector(998,AMPL_WIDTH),
conv_std_logic_vector(1001,AMPL_WIDTH),
conv_std_logic_vector(1003,AMPL_WIDTH),
conv_std_logic_vector(1006,AMPL_WIDTH),
conv_std_logic_vector(1009,AMPL_WIDTH),
conv_std_logic_vector(1012,AMPL_WIDTH),
conv_std_logic_vector(1014,AMPL_WIDTH),
conv_std_logic_vector(1017,AMPL_WIDTH),
conv_std_logic_vector(1020,AMPL_WIDTH),
conv_std_logic_vector(1023,AMPL_WIDTH),
conv_std_logic_vector(1025,AMPL_WIDTH),
conv_std_logic_vector(1028,AMPL_WIDTH),
conv_std_logic_vector(1031,AMPL_WIDTH),
conv_std_logic_vector(1033,AMPL_WIDTH),
conv_std_logic_vector(1036,AMPL_WIDTH),
conv_std_logic_vector(1039,AMPL_WIDTH),
conv_std_logic_vector(1042,AMPL_WIDTH),
conv_std_logic_vector(1044,AMPL_WIDTH),
conv_std_logic_vector(1047,AMPL_WIDTH),
conv_std_logic_vector(1050,AMPL_WIDTH),
conv_std_logic_vector(1052,AMPL_WIDTH),
conv_std_logic_vector(1055,AMPL_WIDTH),
conv_std_logic_vector(1058,AMPL_WIDTH),
conv_std_logic_vector(1060,AMPL_WIDTH),
conv_std_logic_vector(1063,AMPL_WIDTH),
conv_std_logic_vector(1066,AMPL_WIDTH),
conv_std_logic_vector(1068,AMPL_WIDTH),
conv_std_logic_vector(1071,AMPL_WIDTH),
conv_std_logic_vector(1074,AMPL_WIDTH),
conv_std_logic_vector(1077,AMPL_WIDTH),
conv_std_logic_vector(1079,AMPL_WIDTH),
conv_std_logic_vector(1082,AMPL_WIDTH),
conv_std_logic_vector(1085,AMPL_WIDTH),
conv_std_logic_vector(1087,AMPL_WIDTH),
conv_std_logic_vector(1090,AMPL_WIDTH),
conv_std_logic_vector(1092,AMPL_WIDTH),
conv_std_logic_vector(1095,AMPL_WIDTH),
conv_std_logic_vector(1098,AMPL_WIDTH),
conv_std_logic_vector(1100,AMPL_WIDTH),
conv_std_logic_vector(1103,AMPL_WIDTH),
conv_std_logic_vector(1106,AMPL_WIDTH),
conv_std_logic_vector(1108,AMPL_WIDTH),
conv_std_logic_vector(1111,AMPL_WIDTH),
conv_std_logic_vector(1114,AMPL_WIDTH),
conv_std_logic_vector(1116,AMPL_WIDTH),
conv_std_logic_vector(1119,AMPL_WIDTH),
conv_std_logic_vector(1122,AMPL_WIDTH),
conv_std_logic_vector(1124,AMPL_WIDTH),
conv_std_logic_vector(1127,AMPL_WIDTH),
conv_std_logic_vector(1129,AMPL_WIDTH),
conv_std_logic_vector(1132,AMPL_WIDTH),
conv_std_logic_vector(1135,AMPL_WIDTH),
conv_std_logic_vector(1137,AMPL_WIDTH),
conv_std_logic_vector(1140,AMPL_WIDTH),
conv_std_logic_vector(1142,AMPL_WIDTH),
conv_std_logic_vector(1145,AMPL_WIDTH),
conv_std_logic_vector(1148,AMPL_WIDTH),
conv_std_logic_vector(1150,AMPL_WIDTH),
conv_std_logic_vector(1153,AMPL_WIDTH),
conv_std_logic_vector(1155,AMPL_WIDTH),
conv_std_logic_vector(1158,AMPL_WIDTH),
conv_std_logic_vector(1161,AMPL_WIDTH),
conv_std_logic_vector(1163,AMPL_WIDTH),
conv_std_logic_vector(1166,AMPL_WIDTH),
conv_std_logic_vector(1168,AMPL_WIDTH),
conv_std_logic_vector(1171,AMPL_WIDTH),
conv_std_logic_vector(1174,AMPL_WIDTH),
conv_std_logic_vector(1176,AMPL_WIDTH),
conv_std_logic_vector(1179,AMPL_WIDTH),
conv_std_logic_vector(1181,AMPL_WIDTH),
conv_std_logic_vector(1184,AMPL_WIDTH),
conv_std_logic_vector(1186,AMPL_WIDTH),
conv_std_logic_vector(1189,AMPL_WIDTH),
conv_std_logic_vector(1191,AMPL_WIDTH),
conv_std_logic_vector(1194,AMPL_WIDTH),
conv_std_logic_vector(1197,AMPL_WIDTH),
conv_std_logic_vector(1199,AMPL_WIDTH),
conv_std_logic_vector(1202,AMPL_WIDTH),
conv_std_logic_vector(1204,AMPL_WIDTH),
conv_std_logic_vector(1207,AMPL_WIDTH),
conv_std_logic_vector(1209,AMPL_WIDTH),
conv_std_logic_vector(1212,AMPL_WIDTH),
conv_std_logic_vector(1214,AMPL_WIDTH),
conv_std_logic_vector(1217,AMPL_WIDTH),
conv_std_logic_vector(1219,AMPL_WIDTH),
conv_std_logic_vector(1222,AMPL_WIDTH),
conv_std_logic_vector(1224,AMPL_WIDTH),
conv_std_logic_vector(1227,AMPL_WIDTH),
conv_std_logic_vector(1229,AMPL_WIDTH),
conv_std_logic_vector(1232,AMPL_WIDTH),
conv_std_logic_vector(1234,AMPL_WIDTH),
conv_std_logic_vector(1237,AMPL_WIDTH),
conv_std_logic_vector(1239,AMPL_WIDTH),
conv_std_logic_vector(1242,AMPL_WIDTH),
conv_std_logic_vector(1244,AMPL_WIDTH),
conv_std_logic_vector(1247,AMPL_WIDTH),
conv_std_logic_vector(1249,AMPL_WIDTH),
conv_std_logic_vector(1252,AMPL_WIDTH),
conv_std_logic_vector(1254,AMPL_WIDTH),
conv_std_logic_vector(1257,AMPL_WIDTH),
conv_std_logic_vector(1259,AMPL_WIDTH),
conv_std_logic_vector(1262,AMPL_WIDTH),
conv_std_logic_vector(1264,AMPL_WIDTH),
conv_std_logic_vector(1267,AMPL_WIDTH),
conv_std_logic_vector(1269,AMPL_WIDTH),
conv_std_logic_vector(1272,AMPL_WIDTH),
conv_std_logic_vector(1274,AMPL_WIDTH),
conv_std_logic_vector(1277,AMPL_WIDTH),
conv_std_logic_vector(1279,AMPL_WIDTH),
conv_std_logic_vector(1282,AMPL_WIDTH),
conv_std_logic_vector(1284,AMPL_WIDTH),
conv_std_logic_vector(1286,AMPL_WIDTH),
conv_std_logic_vector(1289,AMPL_WIDTH),
conv_std_logic_vector(1291,AMPL_WIDTH),
conv_std_logic_vector(1294,AMPL_WIDTH),
conv_std_logic_vector(1296,AMPL_WIDTH),
conv_std_logic_vector(1299,AMPL_WIDTH),
conv_std_logic_vector(1301,AMPL_WIDTH),
conv_std_logic_vector(1303,AMPL_WIDTH),
conv_std_logic_vector(1306,AMPL_WIDTH),
conv_std_logic_vector(1308,AMPL_WIDTH),
conv_std_logic_vector(1311,AMPL_WIDTH),
conv_std_logic_vector(1313,AMPL_WIDTH),
conv_std_logic_vector(1316,AMPL_WIDTH),
conv_std_logic_vector(1318,AMPL_WIDTH),
conv_std_logic_vector(1320,AMPL_WIDTH),
conv_std_logic_vector(1323,AMPL_WIDTH),
conv_std_logic_vector(1325,AMPL_WIDTH),
conv_std_logic_vector(1328,AMPL_WIDTH),
conv_std_logic_vector(1330,AMPL_WIDTH),
conv_std_logic_vector(1332,AMPL_WIDTH),
conv_std_logic_vector(1335,AMPL_WIDTH),
conv_std_logic_vector(1337,AMPL_WIDTH),
conv_std_logic_vector(1339,AMPL_WIDTH),
conv_std_logic_vector(1342,AMPL_WIDTH),
conv_std_logic_vector(1344,AMPL_WIDTH),
conv_std_logic_vector(1347,AMPL_WIDTH),
conv_std_logic_vector(1349,AMPL_WIDTH),
conv_std_logic_vector(1351,AMPL_WIDTH),
conv_std_logic_vector(1354,AMPL_WIDTH),
conv_std_logic_vector(1356,AMPL_WIDTH),
conv_std_logic_vector(1358,AMPL_WIDTH),
conv_std_logic_vector(1361,AMPL_WIDTH),
conv_std_logic_vector(1363,AMPL_WIDTH),
conv_std_logic_vector(1365,AMPL_WIDTH),
conv_std_logic_vector(1368,AMPL_WIDTH),
conv_std_logic_vector(1370,AMPL_WIDTH),
conv_std_logic_vector(1372,AMPL_WIDTH),
conv_std_logic_vector(1375,AMPL_WIDTH),
conv_std_logic_vector(1377,AMPL_WIDTH),
conv_std_logic_vector(1379,AMPL_WIDTH),
conv_std_logic_vector(1382,AMPL_WIDTH),
conv_std_logic_vector(1384,AMPL_WIDTH),
conv_std_logic_vector(1386,AMPL_WIDTH),
conv_std_logic_vector(1389,AMPL_WIDTH),
conv_std_logic_vector(1391,AMPL_WIDTH),
conv_std_logic_vector(1393,AMPL_WIDTH),
conv_std_logic_vector(1395,AMPL_WIDTH),
conv_std_logic_vector(1398,AMPL_WIDTH),
conv_std_logic_vector(1400,AMPL_WIDTH),
conv_std_logic_vector(1402,AMPL_WIDTH),
conv_std_logic_vector(1405,AMPL_WIDTH),
conv_std_logic_vector(1407,AMPL_WIDTH),
conv_std_logic_vector(1409,AMPL_WIDTH),
conv_std_logic_vector(1411,AMPL_WIDTH),
conv_std_logic_vector(1414,AMPL_WIDTH),
conv_std_logic_vector(1416,AMPL_WIDTH),
conv_std_logic_vector(1418,AMPL_WIDTH),
conv_std_logic_vector(1421,AMPL_WIDTH),
conv_std_logic_vector(1423,AMPL_WIDTH),
conv_std_logic_vector(1425,AMPL_WIDTH),
conv_std_logic_vector(1427,AMPL_WIDTH),
conv_std_logic_vector(1430,AMPL_WIDTH),
conv_std_logic_vector(1432,AMPL_WIDTH),
conv_std_logic_vector(1434,AMPL_WIDTH),
conv_std_logic_vector(1436,AMPL_WIDTH),
conv_std_logic_vector(1439,AMPL_WIDTH),
conv_std_logic_vector(1441,AMPL_WIDTH),
conv_std_logic_vector(1443,AMPL_WIDTH),
conv_std_logic_vector(1445,AMPL_WIDTH),
conv_std_logic_vector(1447,AMPL_WIDTH),
conv_std_logic_vector(1450,AMPL_WIDTH),
conv_std_logic_vector(1452,AMPL_WIDTH),
conv_std_logic_vector(1454,AMPL_WIDTH),
conv_std_logic_vector(1456,AMPL_WIDTH),
conv_std_logic_vector(1459,AMPL_WIDTH),
conv_std_logic_vector(1461,AMPL_WIDTH),
conv_std_logic_vector(1463,AMPL_WIDTH),
conv_std_logic_vector(1465,AMPL_WIDTH),
conv_std_logic_vector(1467,AMPL_WIDTH),
conv_std_logic_vector(1469,AMPL_WIDTH),
conv_std_logic_vector(1472,AMPL_WIDTH),
conv_std_logic_vector(1474,AMPL_WIDTH),
conv_std_logic_vector(1476,AMPL_WIDTH),
conv_std_logic_vector(1478,AMPL_WIDTH),
conv_std_logic_vector(1480,AMPL_WIDTH),
conv_std_logic_vector(1483,AMPL_WIDTH),
conv_std_logic_vector(1485,AMPL_WIDTH),
conv_std_logic_vector(1487,AMPL_WIDTH),
conv_std_logic_vector(1489,AMPL_WIDTH),
conv_std_logic_vector(1491,AMPL_WIDTH),
conv_std_logic_vector(1493,AMPL_WIDTH),
conv_std_logic_vector(1495,AMPL_WIDTH),
conv_std_logic_vector(1498,AMPL_WIDTH),
conv_std_logic_vector(1500,AMPL_WIDTH),
conv_std_logic_vector(1502,AMPL_WIDTH),
conv_std_logic_vector(1504,AMPL_WIDTH),
conv_std_logic_vector(1506,AMPL_WIDTH),
conv_std_logic_vector(1508,AMPL_WIDTH),
conv_std_logic_vector(1510,AMPL_WIDTH),
conv_std_logic_vector(1513,AMPL_WIDTH),
conv_std_logic_vector(1515,AMPL_WIDTH),
conv_std_logic_vector(1517,AMPL_WIDTH),
conv_std_logic_vector(1519,AMPL_WIDTH),
conv_std_logic_vector(1521,AMPL_WIDTH),
conv_std_logic_vector(1523,AMPL_WIDTH),
conv_std_logic_vector(1525,AMPL_WIDTH),
conv_std_logic_vector(1527,AMPL_WIDTH),
conv_std_logic_vector(1529,AMPL_WIDTH),
conv_std_logic_vector(1531,AMPL_WIDTH),
conv_std_logic_vector(1533,AMPL_WIDTH),
conv_std_logic_vector(1536,AMPL_WIDTH),
conv_std_logic_vector(1538,AMPL_WIDTH),
conv_std_logic_vector(1540,AMPL_WIDTH),
conv_std_logic_vector(1542,AMPL_WIDTH),
conv_std_logic_vector(1544,AMPL_WIDTH),
conv_std_logic_vector(1546,AMPL_WIDTH),
conv_std_logic_vector(1548,AMPL_WIDTH),
conv_std_logic_vector(1550,AMPL_WIDTH),
conv_std_logic_vector(1552,AMPL_WIDTH),
conv_std_logic_vector(1554,AMPL_WIDTH),
conv_std_logic_vector(1556,AMPL_WIDTH),
conv_std_logic_vector(1558,AMPL_WIDTH),
conv_std_logic_vector(1560,AMPL_WIDTH),
conv_std_logic_vector(1562,AMPL_WIDTH),
conv_std_logic_vector(1564,AMPL_WIDTH),
conv_std_logic_vector(1566,AMPL_WIDTH),
conv_std_logic_vector(1568,AMPL_WIDTH),
conv_std_logic_vector(1570,AMPL_WIDTH),
conv_std_logic_vector(1572,AMPL_WIDTH),
conv_std_logic_vector(1574,AMPL_WIDTH),
conv_std_logic_vector(1576,AMPL_WIDTH),
conv_std_logic_vector(1578,AMPL_WIDTH),
conv_std_logic_vector(1580,AMPL_WIDTH),
conv_std_logic_vector(1582,AMPL_WIDTH),
conv_std_logic_vector(1584,AMPL_WIDTH),
conv_std_logic_vector(1586,AMPL_WIDTH),
conv_std_logic_vector(1588,AMPL_WIDTH),
conv_std_logic_vector(1590,AMPL_WIDTH),
conv_std_logic_vector(1592,AMPL_WIDTH),
conv_std_logic_vector(1594,AMPL_WIDTH),
conv_std_logic_vector(1596,AMPL_WIDTH),
conv_std_logic_vector(1598,AMPL_WIDTH),
conv_std_logic_vector(1600,AMPL_WIDTH),
conv_std_logic_vector(1602,AMPL_WIDTH),
conv_std_logic_vector(1604,AMPL_WIDTH),
conv_std_logic_vector(1606,AMPL_WIDTH),
conv_std_logic_vector(1608,AMPL_WIDTH),
conv_std_logic_vector(1610,AMPL_WIDTH),
conv_std_logic_vector(1612,AMPL_WIDTH),
conv_std_logic_vector(1614,AMPL_WIDTH),
conv_std_logic_vector(1616,AMPL_WIDTH),
conv_std_logic_vector(1618,AMPL_WIDTH),
conv_std_logic_vector(1620,AMPL_WIDTH),
conv_std_logic_vector(1621,AMPL_WIDTH),
conv_std_logic_vector(1623,AMPL_WIDTH),
conv_std_logic_vector(1625,AMPL_WIDTH),
conv_std_logic_vector(1627,AMPL_WIDTH),
conv_std_logic_vector(1629,AMPL_WIDTH),
conv_std_logic_vector(1631,AMPL_WIDTH),
conv_std_logic_vector(1633,AMPL_WIDTH),
conv_std_logic_vector(1635,AMPL_WIDTH),
conv_std_logic_vector(1637,AMPL_WIDTH),
conv_std_logic_vector(1639,AMPL_WIDTH),
conv_std_logic_vector(1640,AMPL_WIDTH),
conv_std_logic_vector(1642,AMPL_WIDTH),
conv_std_logic_vector(1644,AMPL_WIDTH),
conv_std_logic_vector(1646,AMPL_WIDTH),
conv_std_logic_vector(1648,AMPL_WIDTH),
conv_std_logic_vector(1650,AMPL_WIDTH),
conv_std_logic_vector(1652,AMPL_WIDTH),
conv_std_logic_vector(1653,AMPL_WIDTH),
conv_std_logic_vector(1655,AMPL_WIDTH),
conv_std_logic_vector(1657,AMPL_WIDTH),
conv_std_logic_vector(1659,AMPL_WIDTH),
conv_std_logic_vector(1661,AMPL_WIDTH),
conv_std_logic_vector(1663,AMPL_WIDTH),
conv_std_logic_vector(1665,AMPL_WIDTH),
conv_std_logic_vector(1666,AMPL_WIDTH),
conv_std_logic_vector(1668,AMPL_WIDTH),
conv_std_logic_vector(1670,AMPL_WIDTH),
conv_std_logic_vector(1672,AMPL_WIDTH),
conv_std_logic_vector(1674,AMPL_WIDTH),
conv_std_logic_vector(1675,AMPL_WIDTH),
conv_std_logic_vector(1677,AMPL_WIDTH),
conv_std_logic_vector(1679,AMPL_WIDTH),
conv_std_logic_vector(1681,AMPL_WIDTH),
conv_std_logic_vector(1683,AMPL_WIDTH),
conv_std_logic_vector(1684,AMPL_WIDTH),
conv_std_logic_vector(1686,AMPL_WIDTH),
conv_std_logic_vector(1688,AMPL_WIDTH),
conv_std_logic_vector(1690,AMPL_WIDTH),
conv_std_logic_vector(1691,AMPL_WIDTH),
conv_std_logic_vector(1693,AMPL_WIDTH),
conv_std_logic_vector(1695,AMPL_WIDTH),
conv_std_logic_vector(1697,AMPL_WIDTH),
conv_std_logic_vector(1699,AMPL_WIDTH),
conv_std_logic_vector(1700,AMPL_WIDTH),
conv_std_logic_vector(1702,AMPL_WIDTH),
conv_std_logic_vector(1704,AMPL_WIDTH),
conv_std_logic_vector(1705,AMPL_WIDTH),
conv_std_logic_vector(1707,AMPL_WIDTH),
conv_std_logic_vector(1709,AMPL_WIDTH),
conv_std_logic_vector(1711,AMPL_WIDTH),
conv_std_logic_vector(1712,AMPL_WIDTH),
conv_std_logic_vector(1714,AMPL_WIDTH),
conv_std_logic_vector(1716,AMPL_WIDTH),
conv_std_logic_vector(1718,AMPL_WIDTH),
conv_std_logic_vector(1719,AMPL_WIDTH),
conv_std_logic_vector(1721,AMPL_WIDTH),
conv_std_logic_vector(1723,AMPL_WIDTH),
conv_std_logic_vector(1724,AMPL_WIDTH),
conv_std_logic_vector(1726,AMPL_WIDTH),
conv_std_logic_vector(1728,AMPL_WIDTH),
conv_std_logic_vector(1729,AMPL_WIDTH),
conv_std_logic_vector(1731,AMPL_WIDTH),
conv_std_logic_vector(1733,AMPL_WIDTH),
conv_std_logic_vector(1734,AMPL_WIDTH),
conv_std_logic_vector(1736,AMPL_WIDTH),
conv_std_logic_vector(1738,AMPL_WIDTH),
conv_std_logic_vector(1739,AMPL_WIDTH),
conv_std_logic_vector(1741,AMPL_WIDTH),
conv_std_logic_vector(1743,AMPL_WIDTH),
conv_std_logic_vector(1744,AMPL_WIDTH),
conv_std_logic_vector(1746,AMPL_WIDTH),
conv_std_logic_vector(1748,AMPL_WIDTH),
conv_std_logic_vector(1749,AMPL_WIDTH),
conv_std_logic_vector(1751,AMPL_WIDTH),
conv_std_logic_vector(1753,AMPL_WIDTH),
conv_std_logic_vector(1754,AMPL_WIDTH),
conv_std_logic_vector(1756,AMPL_WIDTH),
conv_std_logic_vector(1757,AMPL_WIDTH),
conv_std_logic_vector(1759,AMPL_WIDTH),
conv_std_logic_vector(1761,AMPL_WIDTH),
conv_std_logic_vector(1762,AMPL_WIDTH),
conv_std_logic_vector(1764,AMPL_WIDTH),
conv_std_logic_vector(1765,AMPL_WIDTH),
conv_std_logic_vector(1767,AMPL_WIDTH),
conv_std_logic_vector(1769,AMPL_WIDTH),
conv_std_logic_vector(1770,AMPL_WIDTH),
conv_std_logic_vector(1772,AMPL_WIDTH),
conv_std_logic_vector(1773,AMPL_WIDTH),
conv_std_logic_vector(1775,AMPL_WIDTH),
conv_std_logic_vector(1776,AMPL_WIDTH),
conv_std_logic_vector(1778,AMPL_WIDTH),
conv_std_logic_vector(1780,AMPL_WIDTH),
conv_std_logic_vector(1781,AMPL_WIDTH),
conv_std_logic_vector(1783,AMPL_WIDTH),
conv_std_logic_vector(1784,AMPL_WIDTH),
conv_std_logic_vector(1786,AMPL_WIDTH),
conv_std_logic_vector(1787,AMPL_WIDTH),
conv_std_logic_vector(1789,AMPL_WIDTH),
conv_std_logic_vector(1790,AMPL_WIDTH),
conv_std_logic_vector(1792,AMPL_WIDTH),
conv_std_logic_vector(1793,AMPL_WIDTH),
conv_std_logic_vector(1795,AMPL_WIDTH),
conv_std_logic_vector(1796,AMPL_WIDTH),
conv_std_logic_vector(1798,AMPL_WIDTH),
conv_std_logic_vector(1799,AMPL_WIDTH),
conv_std_logic_vector(1801,AMPL_WIDTH),
conv_std_logic_vector(1802,AMPL_WIDTH),
conv_std_logic_vector(1804,AMPL_WIDTH),
conv_std_logic_vector(1805,AMPL_WIDTH),
conv_std_logic_vector(1807,AMPL_WIDTH),
conv_std_logic_vector(1808,AMPL_WIDTH),
conv_std_logic_vector(1810,AMPL_WIDTH),
conv_std_logic_vector(1811,AMPL_WIDTH),
conv_std_logic_vector(1813,AMPL_WIDTH),
conv_std_logic_vector(1814,AMPL_WIDTH),
conv_std_logic_vector(1816,AMPL_WIDTH),
conv_std_logic_vector(1817,AMPL_WIDTH),
conv_std_logic_vector(1818,AMPL_WIDTH),
conv_std_logic_vector(1820,AMPL_WIDTH),
conv_std_logic_vector(1821,AMPL_WIDTH),
conv_std_logic_vector(1823,AMPL_WIDTH),
conv_std_logic_vector(1824,AMPL_WIDTH),
conv_std_logic_vector(1826,AMPL_WIDTH),
conv_std_logic_vector(1827,AMPL_WIDTH),
conv_std_logic_vector(1828,AMPL_WIDTH),
conv_std_logic_vector(1830,AMPL_WIDTH),
conv_std_logic_vector(1831,AMPL_WIDTH),
conv_std_logic_vector(1833,AMPL_WIDTH),
conv_std_logic_vector(1834,AMPL_WIDTH),
conv_std_logic_vector(1835,AMPL_WIDTH),
conv_std_logic_vector(1837,AMPL_WIDTH),
conv_std_logic_vector(1838,AMPL_WIDTH),
conv_std_logic_vector(1840,AMPL_WIDTH),
conv_std_logic_vector(1841,AMPL_WIDTH),
conv_std_logic_vector(1842,AMPL_WIDTH),
conv_std_logic_vector(1844,AMPL_WIDTH),
conv_std_logic_vector(1845,AMPL_WIDTH),
conv_std_logic_vector(1846,AMPL_WIDTH),
conv_std_logic_vector(1848,AMPL_WIDTH),
conv_std_logic_vector(1849,AMPL_WIDTH),
conv_std_logic_vector(1850,AMPL_WIDTH),
conv_std_logic_vector(1852,AMPL_WIDTH),
conv_std_logic_vector(1853,AMPL_WIDTH),
conv_std_logic_vector(1854,AMPL_WIDTH),
conv_std_logic_vector(1856,AMPL_WIDTH),
conv_std_logic_vector(1857,AMPL_WIDTH),
conv_std_logic_vector(1858,AMPL_WIDTH),
conv_std_logic_vector(1860,AMPL_WIDTH),
conv_std_logic_vector(1861,AMPL_WIDTH),
conv_std_logic_vector(1862,AMPL_WIDTH),
conv_std_logic_vector(1864,AMPL_WIDTH),
conv_std_logic_vector(1865,AMPL_WIDTH),
conv_std_logic_vector(1866,AMPL_WIDTH),
conv_std_logic_vector(1868,AMPL_WIDTH),
conv_std_logic_vector(1869,AMPL_WIDTH),
conv_std_logic_vector(1870,AMPL_WIDTH),
conv_std_logic_vector(1871,AMPL_WIDTH),
conv_std_logic_vector(1873,AMPL_WIDTH),
conv_std_logic_vector(1874,AMPL_WIDTH),
conv_std_logic_vector(1875,AMPL_WIDTH),
conv_std_logic_vector(1876,AMPL_WIDTH),
conv_std_logic_vector(1878,AMPL_WIDTH),
conv_std_logic_vector(1879,AMPL_WIDTH),
conv_std_logic_vector(1880,AMPL_WIDTH),
conv_std_logic_vector(1881,AMPL_WIDTH),
conv_std_logic_vector(1883,AMPL_WIDTH),
conv_std_logic_vector(1884,AMPL_WIDTH),
conv_std_logic_vector(1885,AMPL_WIDTH),
conv_std_logic_vector(1886,AMPL_WIDTH),
conv_std_logic_vector(1888,AMPL_WIDTH),
conv_std_logic_vector(1889,AMPL_WIDTH),
conv_std_logic_vector(1890,AMPL_WIDTH),
conv_std_logic_vector(1891,AMPL_WIDTH),
conv_std_logic_vector(1892,AMPL_WIDTH),
conv_std_logic_vector(1894,AMPL_WIDTH),
conv_std_logic_vector(1895,AMPL_WIDTH),
conv_std_logic_vector(1896,AMPL_WIDTH),
conv_std_logic_vector(1897,AMPL_WIDTH),
conv_std_logic_vector(1898,AMPL_WIDTH),
conv_std_logic_vector(1899,AMPL_WIDTH),
conv_std_logic_vector(1901,AMPL_WIDTH),
conv_std_logic_vector(1902,AMPL_WIDTH),
conv_std_logic_vector(1903,AMPL_WIDTH),
conv_std_logic_vector(1904,AMPL_WIDTH),
conv_std_logic_vector(1905,AMPL_WIDTH),
conv_std_logic_vector(1906,AMPL_WIDTH),
conv_std_logic_vector(1908,AMPL_WIDTH),
conv_std_logic_vector(1909,AMPL_WIDTH),
conv_std_logic_vector(1910,AMPL_WIDTH),
conv_std_logic_vector(1911,AMPL_WIDTH),
conv_std_logic_vector(1912,AMPL_WIDTH),
conv_std_logic_vector(1913,AMPL_WIDTH),
conv_std_logic_vector(1914,AMPL_WIDTH),
conv_std_logic_vector(1915,AMPL_WIDTH),
conv_std_logic_vector(1917,AMPL_WIDTH),
conv_std_logic_vector(1918,AMPL_WIDTH),
conv_std_logic_vector(1919,AMPL_WIDTH),
conv_std_logic_vector(1920,AMPL_WIDTH),
conv_std_logic_vector(1921,AMPL_WIDTH),
conv_std_logic_vector(1922,AMPL_WIDTH),
conv_std_logic_vector(1923,AMPL_WIDTH),
conv_std_logic_vector(1924,AMPL_WIDTH),
conv_std_logic_vector(1925,AMPL_WIDTH),
conv_std_logic_vector(1926,AMPL_WIDTH),
conv_std_logic_vector(1927,AMPL_WIDTH),
conv_std_logic_vector(1928,AMPL_WIDTH),
conv_std_logic_vector(1929,AMPL_WIDTH),
conv_std_logic_vector(1930,AMPL_WIDTH),
conv_std_logic_vector(1932,AMPL_WIDTH),
conv_std_logic_vector(1933,AMPL_WIDTH),
conv_std_logic_vector(1934,AMPL_WIDTH),
conv_std_logic_vector(1935,AMPL_WIDTH),
conv_std_logic_vector(1936,AMPL_WIDTH),
conv_std_logic_vector(1937,AMPL_WIDTH),
conv_std_logic_vector(1938,AMPL_WIDTH),
conv_std_logic_vector(1939,AMPL_WIDTH),
conv_std_logic_vector(1940,AMPL_WIDTH),
conv_std_logic_vector(1941,AMPL_WIDTH),
conv_std_logic_vector(1942,AMPL_WIDTH),
conv_std_logic_vector(1943,AMPL_WIDTH),
conv_std_logic_vector(1944,AMPL_WIDTH),
conv_std_logic_vector(1945,AMPL_WIDTH),
conv_std_logic_vector(1946,AMPL_WIDTH),
conv_std_logic_vector(1947,AMPL_WIDTH),
conv_std_logic_vector(1948,AMPL_WIDTH),
conv_std_logic_vector(1949,AMPL_WIDTH),
conv_std_logic_vector(1950,AMPL_WIDTH),
conv_std_logic_vector(1950,AMPL_WIDTH),
conv_std_logic_vector(1951,AMPL_WIDTH),
conv_std_logic_vector(1952,AMPL_WIDTH),
conv_std_logic_vector(1953,AMPL_WIDTH),
conv_std_logic_vector(1954,AMPL_WIDTH),
conv_std_logic_vector(1955,AMPL_WIDTH),
conv_std_logic_vector(1956,AMPL_WIDTH),
conv_std_logic_vector(1957,AMPL_WIDTH),
conv_std_logic_vector(1958,AMPL_WIDTH),
conv_std_logic_vector(1959,AMPL_WIDTH),
conv_std_logic_vector(1960,AMPL_WIDTH),
conv_std_logic_vector(1961,AMPL_WIDTH),
conv_std_logic_vector(1962,AMPL_WIDTH),
conv_std_logic_vector(1962,AMPL_WIDTH),
conv_std_logic_vector(1963,AMPL_WIDTH),
conv_std_logic_vector(1964,AMPL_WIDTH),
conv_std_logic_vector(1965,AMPL_WIDTH),
conv_std_logic_vector(1966,AMPL_WIDTH),
conv_std_logic_vector(1967,AMPL_WIDTH),
conv_std_logic_vector(1968,AMPL_WIDTH),
conv_std_logic_vector(1969,AMPL_WIDTH),
conv_std_logic_vector(1969,AMPL_WIDTH),
conv_std_logic_vector(1970,AMPL_WIDTH),
conv_std_logic_vector(1971,AMPL_WIDTH),
conv_std_logic_vector(1972,AMPL_WIDTH),
conv_std_logic_vector(1973,AMPL_WIDTH),
conv_std_logic_vector(1974,AMPL_WIDTH),
conv_std_logic_vector(1975,AMPL_WIDTH),
conv_std_logic_vector(1975,AMPL_WIDTH),
conv_std_logic_vector(1976,AMPL_WIDTH),
conv_std_logic_vector(1977,AMPL_WIDTH),
conv_std_logic_vector(1978,AMPL_WIDTH),
conv_std_logic_vector(1979,AMPL_WIDTH),
conv_std_logic_vector(1979,AMPL_WIDTH),
conv_std_logic_vector(1980,AMPL_WIDTH),
conv_std_logic_vector(1981,AMPL_WIDTH),
conv_std_logic_vector(1982,AMPL_WIDTH),
conv_std_logic_vector(1983,AMPL_WIDTH),
conv_std_logic_vector(1983,AMPL_WIDTH),
conv_std_logic_vector(1984,AMPL_WIDTH),
conv_std_logic_vector(1985,AMPL_WIDTH),
conv_std_logic_vector(1986,AMPL_WIDTH),
conv_std_logic_vector(1986,AMPL_WIDTH),
conv_std_logic_vector(1987,AMPL_WIDTH),
conv_std_logic_vector(1988,AMPL_WIDTH),
conv_std_logic_vector(1989,AMPL_WIDTH),
conv_std_logic_vector(1989,AMPL_WIDTH),
conv_std_logic_vector(1990,AMPL_WIDTH),
conv_std_logic_vector(1991,AMPL_WIDTH),
conv_std_logic_vector(1992,AMPL_WIDTH),
conv_std_logic_vector(1992,AMPL_WIDTH),
conv_std_logic_vector(1993,AMPL_WIDTH),
conv_std_logic_vector(1994,AMPL_WIDTH),
conv_std_logic_vector(1994,AMPL_WIDTH),
conv_std_logic_vector(1995,AMPL_WIDTH),
conv_std_logic_vector(1996,AMPL_WIDTH),
conv_std_logic_vector(1997,AMPL_WIDTH),
conv_std_logic_vector(1997,AMPL_WIDTH),
conv_std_logic_vector(1998,AMPL_WIDTH),
conv_std_logic_vector(1999,AMPL_WIDTH),
conv_std_logic_vector(1999,AMPL_WIDTH),
conv_std_logic_vector(2000,AMPL_WIDTH),
conv_std_logic_vector(2001,AMPL_WIDTH),
conv_std_logic_vector(2001,AMPL_WIDTH),
conv_std_logic_vector(2002,AMPL_WIDTH),
conv_std_logic_vector(2003,AMPL_WIDTH),
conv_std_logic_vector(2003,AMPL_WIDTH),
conv_std_logic_vector(2004,AMPL_WIDTH),
conv_std_logic_vector(2005,AMPL_WIDTH),
conv_std_logic_vector(2005,AMPL_WIDTH),
conv_std_logic_vector(2006,AMPL_WIDTH),
conv_std_logic_vector(2006,AMPL_WIDTH),
conv_std_logic_vector(2007,AMPL_WIDTH),
conv_std_logic_vector(2008,AMPL_WIDTH),
conv_std_logic_vector(2008,AMPL_WIDTH),
conv_std_logic_vector(2009,AMPL_WIDTH),
conv_std_logic_vector(2009,AMPL_WIDTH),
conv_std_logic_vector(2010,AMPL_WIDTH),
conv_std_logic_vector(2011,AMPL_WIDTH),
conv_std_logic_vector(2011,AMPL_WIDTH),
conv_std_logic_vector(2012,AMPL_WIDTH),
conv_std_logic_vector(2012,AMPL_WIDTH),
conv_std_logic_vector(2013,AMPL_WIDTH),
conv_std_logic_vector(2014,AMPL_WIDTH),
conv_std_logic_vector(2014,AMPL_WIDTH),
conv_std_logic_vector(2015,AMPL_WIDTH),
conv_std_logic_vector(2015,AMPL_WIDTH),
conv_std_logic_vector(2016,AMPL_WIDTH),
conv_std_logic_vector(2016,AMPL_WIDTH),
conv_std_logic_vector(2017,AMPL_WIDTH),
conv_std_logic_vector(2017,AMPL_WIDTH),
conv_std_logic_vector(2018,AMPL_WIDTH),
conv_std_logic_vector(2018,AMPL_WIDTH),
conv_std_logic_vector(2019,AMPL_WIDTH),
conv_std_logic_vector(2019,AMPL_WIDTH),
conv_std_logic_vector(2020,AMPL_WIDTH),
conv_std_logic_vector(2021,AMPL_WIDTH),
conv_std_logic_vector(2021,AMPL_WIDTH),
conv_std_logic_vector(2022,AMPL_WIDTH),
conv_std_logic_vector(2022,AMPL_WIDTH),
conv_std_logic_vector(2022,AMPL_WIDTH),
conv_std_logic_vector(2023,AMPL_WIDTH),
conv_std_logic_vector(2023,AMPL_WIDTH),
conv_std_logic_vector(2024,AMPL_WIDTH),
conv_std_logic_vector(2024,AMPL_WIDTH),
conv_std_logic_vector(2025,AMPL_WIDTH),
conv_std_logic_vector(2025,AMPL_WIDTH),
conv_std_logic_vector(2026,AMPL_WIDTH),
conv_std_logic_vector(2026,AMPL_WIDTH),
conv_std_logic_vector(2027,AMPL_WIDTH),
conv_std_logic_vector(2027,AMPL_WIDTH),
conv_std_logic_vector(2028,AMPL_WIDTH),
conv_std_logic_vector(2028,AMPL_WIDTH),
conv_std_logic_vector(2028,AMPL_WIDTH),
conv_std_logic_vector(2029,AMPL_WIDTH),
conv_std_logic_vector(2029,AMPL_WIDTH),
conv_std_logic_vector(2030,AMPL_WIDTH),
conv_std_logic_vector(2030,AMPL_WIDTH),
conv_std_logic_vector(2030,AMPL_WIDTH),
conv_std_logic_vector(2031,AMPL_WIDTH),
conv_std_logic_vector(2031,AMPL_WIDTH),
conv_std_logic_vector(2032,AMPL_WIDTH),
conv_std_logic_vector(2032,AMPL_WIDTH),
conv_std_logic_vector(2032,AMPL_WIDTH),
conv_std_logic_vector(2033,AMPL_WIDTH),
conv_std_logic_vector(2033,AMPL_WIDTH),
conv_std_logic_vector(2033,AMPL_WIDTH),
conv_std_logic_vector(2034,AMPL_WIDTH),
conv_std_logic_vector(2034,AMPL_WIDTH),
conv_std_logic_vector(2035,AMPL_WIDTH),
conv_std_logic_vector(2035,AMPL_WIDTH),
conv_std_logic_vector(2035,AMPL_WIDTH),
conv_std_logic_vector(2036,AMPL_WIDTH),
conv_std_logic_vector(2036,AMPL_WIDTH),
conv_std_logic_vector(2036,AMPL_WIDTH),
conv_std_logic_vector(2037,AMPL_WIDTH),
conv_std_logic_vector(2037,AMPL_WIDTH),
conv_std_logic_vector(2037,AMPL_WIDTH),
conv_std_logic_vector(2037,AMPL_WIDTH),
conv_std_logic_vector(2038,AMPL_WIDTH),
conv_std_logic_vector(2038,AMPL_WIDTH),
conv_std_logic_vector(2038,AMPL_WIDTH),
conv_std_logic_vector(2039,AMPL_WIDTH),
conv_std_logic_vector(2039,AMPL_WIDTH),
conv_std_logic_vector(2039,AMPL_WIDTH),
conv_std_logic_vector(2039,AMPL_WIDTH),
conv_std_logic_vector(2040,AMPL_WIDTH),
conv_std_logic_vector(2040,AMPL_WIDTH),
conv_std_logic_vector(2040,AMPL_WIDTH),
conv_std_logic_vector(2040,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH)
);
end sine_lut_pkg;
package body sine_lut_pkg is
end sine_lut_pkg; |
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
--Date : Tue Aug 2 21:54:54 2016
--Host : andrewandrepowell2-desktop running 64-bit Ubuntu 16.04 LTS
--Command : generate_target block_design_wrapper.bd
--Design : block_design_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity block_design_wrapper is
port (
AC_BCLK : out STD_LOGIC_VECTOR ( 0 to 0 );
AC_MCLK : out STD_LOGIC;
AC_MUTE_N : out STD_LOGIC;
AC_PBLRC : out STD_LOGIC_VECTOR ( 0 to 0 );
AC_RELRC : out STD_LOGIC_VECTOR ( 0 to 0 );
AC_SDATA_I : in STD_LOGIC;
AC_SDATA_O : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
ac_i2c_scl_io : inout STD_LOGIC;
ac_i2c_sda_io : inout STD_LOGIC;
mic_spi_io0_io : inout STD_LOGIC;
mic_spi_io1_io : inout STD_LOGIC;
mic_spi_sck_io : inout STD_LOGIC;
mic_spi_ss1_o : out STD_LOGIC;
mic_spi_ss2_o : out STD_LOGIC;
mic_spi_ss_io : inout STD_LOGIC
);
end block_design_wrapper;
architecture STRUCTURE of block_design_wrapper is
component block_design is
port (
DDR_cas_n : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
AC_I2C_sda_i : in STD_LOGIC;
AC_I2C_sda_o : out STD_LOGIC;
AC_I2C_sda_t : out STD_LOGIC;
AC_I2C_scl_i : in STD_LOGIC;
AC_I2C_scl_o : out STD_LOGIC;
AC_I2C_scl_t : out STD_LOGIC;
MIC_SPI_sck_i : in STD_LOGIC;
MIC_SPI_sck_o : out STD_LOGIC;
MIC_SPI_sck_t : out STD_LOGIC;
MIC_SPI_io0_i : in STD_LOGIC;
MIC_SPI_io0_o : out STD_LOGIC;
MIC_SPI_io0_t : out STD_LOGIC;
MIC_SPI_io1_i : in STD_LOGIC;
MIC_SPI_io1_o : out STD_LOGIC;
MIC_SPI_io1_t : out STD_LOGIC;
MIC_SPI_ss_i : in STD_LOGIC;
MIC_SPI_ss_o : out STD_LOGIC;
MIC_SPI_ss1_o : out STD_LOGIC;
MIC_SPI_ss2_o : out STD_LOGIC;
MIC_SPI_ss_t : out STD_LOGIC;
AC_RELRC : out STD_LOGIC_VECTOR ( 0 to 0 );
AC_PBLRC : out STD_LOGIC_VECTOR ( 0 to 0 );
AC_MCLK : out STD_LOGIC;
AC_SDATA_I : in STD_LOGIC;
AC_BCLK : out STD_LOGIC_VECTOR ( 0 to 0 );
AC_SDATA_O : out STD_LOGIC_VECTOR ( 0 to 0 );
AC_MUTE_N : out STD_LOGIC
);
end component block_design;
component IOBUF is
port (
I : in STD_LOGIC;
O : out STD_LOGIC;
T : in STD_LOGIC;
IO : inout STD_LOGIC
);
end component IOBUF;
signal ac_i2c_scl_i : STD_LOGIC;
signal ac_i2c_scl_o : STD_LOGIC;
signal ac_i2c_scl_t : STD_LOGIC;
signal ac_i2c_sda_i : STD_LOGIC;
signal ac_i2c_sda_o : STD_LOGIC;
signal ac_i2c_sda_t : STD_LOGIC;
signal mic_spi_io0_i : STD_LOGIC;
signal mic_spi_io0_o : STD_LOGIC;
signal mic_spi_io0_t : STD_LOGIC;
signal mic_spi_io1_i : STD_LOGIC;
signal mic_spi_io1_o : STD_LOGIC;
signal mic_spi_io1_t : STD_LOGIC;
signal mic_spi_sck_i : STD_LOGIC;
signal mic_spi_sck_o : STD_LOGIC;
signal mic_spi_sck_t : STD_LOGIC;
signal mic_spi_ss_i : STD_LOGIC;
signal mic_spi_ss_o : STD_LOGIC;
signal mic_spi_ss_t : STD_LOGIC;
begin
ac_i2c_scl_iobuf: component IOBUF
port map (
I => ac_i2c_scl_o,
IO => ac_i2c_scl_io,
O => ac_i2c_scl_i,
T => ac_i2c_scl_t
);
ac_i2c_sda_iobuf: component IOBUF
port map (
I => ac_i2c_sda_o,
IO => ac_i2c_sda_io,
O => ac_i2c_sda_i,
T => ac_i2c_sda_t
);
block_design_i: component block_design
port map (
AC_BCLK(0) => AC_BCLK(0),
AC_I2C_scl_i => ac_i2c_scl_i,
AC_I2C_scl_o => ac_i2c_scl_o,
AC_I2C_scl_t => ac_i2c_scl_t,
AC_I2C_sda_i => ac_i2c_sda_i,
AC_I2C_sda_o => ac_i2c_sda_o,
AC_I2C_sda_t => ac_i2c_sda_t,
AC_MCLK => AC_MCLK,
AC_MUTE_N => AC_MUTE_N,
AC_PBLRC(0) => AC_PBLRC(0),
AC_RELRC(0) => AC_RELRC(0),
AC_SDATA_I => AC_SDATA_I,
AC_SDATA_O(0) => AC_SDATA_O(0),
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
DDR_cas_n => DDR_cas_n,
DDR_ck_n => DDR_ck_n,
DDR_ck_p => DDR_ck_p,
DDR_cke => DDR_cke,
DDR_cs_n => DDR_cs_n,
DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_odt => DDR_odt,
DDR_ras_n => DDR_ras_n,
DDR_reset_n => DDR_reset_n,
DDR_we_n => DDR_we_n,
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
MIC_SPI_io0_i => mic_spi_io0_i,
MIC_SPI_io0_o => mic_spi_io0_o,
MIC_SPI_io0_t => mic_spi_io0_t,
MIC_SPI_io1_i => mic_spi_io1_i,
MIC_SPI_io1_o => mic_spi_io1_o,
MIC_SPI_io1_t => mic_spi_io1_t,
MIC_SPI_sck_i => mic_spi_sck_i,
MIC_SPI_sck_o => mic_spi_sck_o,
MIC_SPI_sck_t => mic_spi_sck_t,
MIC_SPI_ss1_o => mic_spi_ss1_o,
MIC_SPI_ss2_o => mic_spi_ss2_o,
MIC_SPI_ss_i => mic_spi_ss_i,
MIC_SPI_ss_o => mic_spi_ss_o,
MIC_SPI_ss_t => mic_spi_ss_t
);
mic_spi_io0_iobuf: component IOBUF
port map (
I => mic_spi_io0_o,
IO => mic_spi_io0_io,
O => mic_spi_io0_i,
T => mic_spi_io0_t
);
mic_spi_io1_iobuf: component IOBUF
port map (
I => mic_spi_io1_o,
IO => mic_spi_io1_io,
O => mic_spi_io1_i,
T => mic_spi_io1_t
);
mic_spi_sck_iobuf: component IOBUF
port map (
I => mic_spi_sck_o,
IO => mic_spi_sck_io,
O => mic_spi_sck_i,
T => mic_spi_sck_t
);
mic_spi_ss_iobuf: component IOBUF
port map (
I => mic_spi_ss_o,
IO => mic_spi_ss_io,
O => mic_spi_ss_i,
T => mic_spi_ss_t
);
end STRUCTURE;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity <<ENTITY_NAME>> is
port (<<IN_P>>: in <<type>>; <<OUT_P>>: out <<type>>);
end <<ENTITY_NAME>>;
architecture <<ARCH_TYPE>> of <<ENTITY_NAME>> is
<<DECL_COMPONENTS>>
<<DECL_SIGNALS>>
begin
-- Commands.
<<DECL_COMP_INSTANCES>>
end <<ARCH_TYPE>>;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity <<ENTITY_NAME>> is
port (<<IN_P>>: in <<type>>; <<OUT_P>>: out <<type>>);
end <<ENTITY_NAME>>;
architecture <<ARCH_TYPE>> of <<ENTITY_NAME>> is
<<DECL_COMPONENTS>>
<<DECL_SIGNALS>>
begin
-- Commands.
<<DECL_COMP_INSTANCES>>
end <<ARCH_TYPE>>;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity <<ENTITY_NAME>> is
port (<<IN_P>>: in <<type>>; <<OUT_P>>: out <<type>>);
end <<ENTITY_NAME>>;
architecture <<ARCH_TYPE>> of <<ENTITY_NAME>> is
<<DECL_COMPONENTS>>
<<DECL_SIGNALS>>
begin
-- Commands.
<<DECL_COMP_INSTANCES>>
end <<ARCH_TYPE>>;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity <<ENTITY_NAME>> is
port (<<IN_P>>: in <<type>>; <<OUT_P>>: out <<type>>);
end <<ENTITY_NAME>>;
architecture <<ARCH_TYPE>> of <<ENTITY_NAME>> is
<<DECL_COMPONENTS>>
<<DECL_SIGNALS>>
begin
-- Commands.
<<DECL_COMP_INSTANCES>>
end <<ARCH_TYPE>>;
|
-------------------------------------------------------------------------------
-- Title : Testbench for serialiser
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013 strongly-typed
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity serialiser_tb is
end serialiser_tb;
-------------------------------------------------------------------------------
architecture tb of serialiser_tb is
use work.utils_pkg.all;
-- Component generics
constant BITPATTERN_WIDTH : integer := 16;
-- Signals for component ports
signal pattern : std_logic_vector(BITPATTERN_WIDTH - 1 downto 0) := (others => '0');
signal bitstream : std_logic;
signal clk_bit : std_logic := '0';
signal clk : std_logic := '0';
begin -- tb
---------------------------------------------------------------------------
-- component instatiation
---------------------------------------------------------------------------
serialiser_1 : entity work.serialiser
generic map (
BITPATTERN_WIDTH => BITPATTERN_WIDTH)
port map (
pattern_in_p => pattern,
bitstream_out_p => bitstream,
clk_bit => clk_bit,
clk => clk);
-------------------------------------------------------------------------------
-- Stimuli
-------------------------------------------------------------------------------
-- clock generation, 50 MHz
clk <= not clk after 10 ns;
-- Bit clock
-- 50 MHz / 25000 = 2 kHz
-- For testbench 200 kHz
fractional_clock_divider_1 : entity work.fractional_clock_divider
generic map (
DIV => 250,
MUL => 1)
port map (
clk_out_p => clk_bit,
clk => clk);
pattern <= x"8000";
end tb;
|
-------------------------------------------------------------------------------
-- Title : Testbench for serialiser
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013 strongly-typed
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity serialiser_tb is
end serialiser_tb;
-------------------------------------------------------------------------------
architecture tb of serialiser_tb is
use work.utils_pkg.all;
-- Component generics
constant BITPATTERN_WIDTH : integer := 16;
-- Signals for component ports
signal pattern : std_logic_vector(BITPATTERN_WIDTH - 1 downto 0) := (others => '0');
signal bitstream : std_logic;
signal clk_bit : std_logic := '0';
signal clk : std_logic := '0';
begin -- tb
---------------------------------------------------------------------------
-- component instatiation
---------------------------------------------------------------------------
serialiser_1 : entity work.serialiser
generic map (
BITPATTERN_WIDTH => BITPATTERN_WIDTH)
port map (
pattern_in_p => pattern,
bitstream_out_p => bitstream,
clk_bit => clk_bit,
clk => clk);
-------------------------------------------------------------------------------
-- Stimuli
-------------------------------------------------------------------------------
-- clock generation, 50 MHz
clk <= not clk after 10 ns;
-- Bit clock
-- 50 MHz / 25000 = 2 kHz
-- For testbench 200 kHz
fractional_clock_divider_1 : entity work.fractional_clock_divider
generic map (
DIV => 250,
MUL => 1)
port map (
clk_out_p => clk_bit,
clk => clk);
pattern <= x"8000";
end tb;
|
-------------------------------------------------------------------------------
-- axi_datamover_wr_status_cntl.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_wr_status_cntl.vhd
--
-- Description:
-- This file implements the DataMover Master Write Status Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_11;
use axi_datamover_v5_1_11.axi_datamover_fifo;
-------------------------------------------------------------------------------
entity axi_datamover_wr_status_cntl is
generic (
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if the Indeterminate BTT Module is enabled
-- for use (outside of this module)
C_SF_BYTES_RCVD_WIDTH : Integer range 1 to 23 := 1;
-- Sets the width of the data2wsc_bytes_rcvd port used for
-- relaying the actual number of bytes received when Idet BTT is
-- enabled (C_ENABLE_INDET_BTT = 1)
C_STS_FIFO_DEPTH : Integer range 1 to 32 := 8;
-- Specifies the depth of the internal status queue fifo
C_STS_WIDTH : Integer range 8 to 32 := 8;
-- sets the width of the Status ports
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the Status reply
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA device family
);
port (
-- Clock and Reset inputs ------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------------
-- Soft Shutdown Control interface --------------------------------
--
rst2wsc_stop_request : in std_logic; --
-- Active high soft stop request to modules --
--
wsc2rst_stop_cmplt : Out std_logic; --
-- Active high indication that the Write status Controller --
-- has completed any pending transfers committed by the --
-- Address Controller after a stop has been requested by --
-- the Reset module. --
--
addr2wsc_addr_posted : In std_logic ; --
-- Indication from the Address Channel Controller to the --
-- write Status Controller that an address has been posted --
-- to the AXI Address Channel --
--------------------------------------------------------------------
-- Write Response Channel Interface -------------------------------
--
s2mm_bresp : In std_logic_vector(1 downto 0); --
-- The Write response value --
--
s2mm_bvalid : In std_logic ; --
-- Indication from the Write Response Channel that a new --
-- write status input is valid --
--
s2mm_bready : out std_logic ; --
-- Indication to the Write Response Channel that the --
-- Status module is ready for a new status input --
--------------------------------------------------------------------
-- Command Calculator Interface -------------------------------------
--
calc2wsc_calc_error : in std_logic ; --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
---------------------------------------------------------------------
-- Address Controller Status ----------------------------------------
--
addr2wsc_calc_error : In std_logic ; --
-- Indication from the Address Channel Controller that it --
-- has encountered a calculation error from the command --
-- Calculator --
--
addr2wsc_fifo_empty : In std_logic ; --
-- Indication from the Address Controller FIFO that it --
-- is empty (no commands pending) --
---------------------------------------------------------------------
-- Data Controller Status ---------------------------------------------------------
--
data2wsc_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The command tag --
--
data2wsc_calc_error : In std_logic ; --
-- Indication from the Data Channel Controller FIFO that it --
-- has encountered a Calculation error in the command pipe --
--
data2wsc_last_error : In std_logic ; --
-- Indication from the Write Data Channel Controller that a --
-- premature TLAST assertion was encountered on the incoming --
-- Stream Channel --
--
data2wsc_cmd_cmplt : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- corresponding status is the final status for a parent --
-- command fetched from the command FIFO --
--
data2wsc_valid : In std_logic ; --
-- Indication from the Data Channel Controller FIFO that it --
-- has a new tag/error status to transfer --
--
wsc2data_ready : out std_logic ; --
-- Indication to the Data Channel Controller FIFO that the --
-- Status module is ready for a new tag/error status input --
--
--
data2wsc_eop : In std_logic; --
-- Input from the Write Data Controller indicating that the --
-- associated command status also corresponds to a End of Packet --
-- marker for the input Stream. This is only used when Store and --
-- Forward is enabled in the S2MM. --
--
data2wsc_bytes_rcvd : In std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0); --
-- Input from the Write Data Controller indicating the actual --
-- number of bytes received from the Stream input for the --
-- corresponding command status. This is only used when Store and --
-- Forward is enabled in the S2MM. --
------------------------------------------------------------------------------------
-- Command/Status Interface --------------------------------------------------------
--
wsc2stat_status : Out std_logic_vector(C_STS_WIDTH-1 downto 0); --
-- Read Status value collected during a Read Data transfer --
-- Output to the Command/Status Module --
--
stat2wsc_status_ready : In std_logic; --
-- Input from the Command/Status Module indicating that the --
-- Status Reg/FIFO is Full and cannot accept more staus writes --
--
wsc2stat_status_valid : Out std_logic ; --
-- Control Signal to Write the Status value to the Status --
-- Reg/FIFO --
------------------------------------------------------------------------------------
-- Address and Data Controller Pipe halt --------------------------------
--
wsc2mstr_halt_pipe : Out std_logic --
-- Indication to Halt the Data and Address Command pipeline due --
-- to the Status pipe getting full at some point --
-------------------------------------------------------------------------
);
end entity axi_datamover_wr_status_cntl;
architecture implementation of axi_datamover_wr_status_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_cnt_width
--
-- Function Description:
-- Sets a count width based on a fifo depth. A depth of 4 or less
-- is a special case which requires a minimum count width of 3 bits.
--
-------------------------------------------------------------------
function funct_set_cnt_width (fifo_depth : integer) return integer is
Variable temp_cnt_width : Integer := 4;
begin
if (fifo_depth <= 4) then
temp_cnt_width := 3;
elsif (fifo_depth <= 8) then
temp_cnt_width := 4;
elsif (fifo_depth <= 16) then
temp_cnt_width := 5;
elsif (fifo_depth <= 32) then
temp_cnt_width := 6;
else -- fifo depth <= 64
temp_cnt_width := 7;
end if;
Return (temp_cnt_width);
end function funct_set_cnt_width;
-- Constant Declarations --------------------------------------------
Constant OKAY : std_logic_vector(1 downto 0) := "00";
Constant EXOKAY : std_logic_vector(1 downto 0) := "01";
Constant SLVERR : std_logic_vector(1 downto 0) := "10";
Constant DECERR : std_logic_vector(1 downto 0) := "11";
Constant STAT_RSVD : std_logic_vector(3 downto 0) := "0000";
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant STAT_REG_TAG_WIDTH : integer := 4;
Constant SYNC_FIFO_SELECT : integer := 0;
Constant SRL_FIFO_TYPE : integer := 2;
Constant DCNTL_SFIFO_DEPTH : integer := C_STS_FIFO_DEPTH;
Constant DCNTL_STATCNT_WIDTH : integer := funct_set_cnt_width(C_STS_FIFO_DEPTH);-- bits
Constant DCNTL_HALT_THRES : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(DCNTL_SFIFO_DEPTH-2,DCNTL_STATCNT_WIDTH);
Constant DCNTL_STATCNT_ZERO : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := (others => '0');
Constant DCNTL_STATCNT_MAX : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(DCNTL_SFIFO_DEPTH,DCNTL_STATCNT_WIDTH);
Constant DCNTL_STATCNT_ONE : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, DCNTL_STATCNT_WIDTH);
Constant WRESP_WIDTH : integer := 2;
Constant WRESP_SFIFO_WIDTH : integer := WRESP_WIDTH;
Constant WRESP_SFIFO_DEPTH : integer := DCNTL_SFIFO_DEPTH;
Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_STS_FIFO_DEPTH);-- bits
Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '0');
Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH);
Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '1');
-- Signal Declarations --------------------------------------------
signal sig_valid_status_rdy : std_logic := '0';
signal sig_decerr : std_logic := '0';
signal sig_slverr : std_logic := '0';
signal sig_coelsc_okay_reg : std_logic := '0';
signal sig_coelsc_interr_reg : std_logic := '0';
signal sig_coelsc_decerr_reg : std_logic := '0';
signal sig_coelsc_slverr_reg : std_logic := '0';
signal sig_coelsc_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_coelsc_reg : std_logic := '0';
signal sig_push_coelsc_reg : std_logic := '0';
signal sig_coelsc_reg_empty : std_logic := '0';
signal sig_coelsc_reg_full : std_logic := '0';
signal sig_tag2status : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data_err_reg : std_logic := '0';
signal sig_data_last_err_reg : std_logic := '0';
signal sig_data_cmd_cmplt_reg : std_logic := '0';
signal sig_bresp_reg : std_logic_vector(1 downto 0) := (others => '0');
signal sig_push_status : std_logic := '0';
Signal sig_status_push_ok : std_logic := '0';
signal sig_status_valid : std_logic := '0';
signal sig_wsc2data_ready : std_logic := '0';
signal sig_s2mm_bready : std_logic := '0';
signal sig_wresp_sfifo_in : std_logic_vector(WRESP_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_wresp_sfifo_out : std_logic_vector(WRESP_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_wresp_sfifo_wr_valid : std_logic := '0';
signal sig_wresp_sfifo_wr_ready : std_logic := '0';
signal sig_wresp_sfifo_wr_full : std_logic := '0';
signal sig_wresp_sfifo_rd_valid : std_logic := '0';
signal sig_wresp_sfifo_rd_ready : std_logic := '0';
signal sig_wresp_sfifo_rd_empty : std_logic := '0';
signal sig_halt_reg : std_logic := '0';
signal sig_halt_reg_dly1 : std_logic := '0';
signal sig_halt_reg_dly2 : std_logic := '0';
signal sig_halt_reg_dly3 : std_logic := '0';
signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted_cntr_eq_0 : std_logic := '0';
signal sig_addr_posted_cntr_eq_1 : std_logic := '0';
signal sig_addr_posted_cntr_max : std_logic := '0';
signal sig_decr_addr_posted_cntr : std_logic := '0';
signal sig_incr_addr_posted_cntr : std_logic := '0';
signal sig_no_posted_cmds : std_logic := '0';
signal sig_addr_posted : std_logic := '0';
signal sig_all_cmds_done : std_logic := '0';
signal sig_wsc2stat_status : std_logic_vector(C_STS_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_wr_valid : std_logic := '0';
signal sig_dcntl_sfifo_wr_ready : std_logic := '0';
signal sig_dcntl_sfifo_wr_full : std_logic := '0';
signal sig_dcntl_sfifo_rd_valid : std_logic := '0';
signal sig_dcntl_sfifo_rd_ready : std_logic := '0';
signal sig_dcntl_sfifo_rd_empty : std_logic := '0';
signal sig_wdc_statcnt : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_statcnt : std_logic := '0';
signal sig_decr_statcnt : std_logic := '0';
signal sig_statcnt_eq_max : std_logic := '0';
signal sig_statcnt_eq_0 : std_logic := '0';
signal sig_statcnt_gt_eq_thres : std_logic := '0';
signal sig_wdc_status_going_full : std_logic := '0';
begin --(architecture implementation)
-- Assign the ready output to the AXI Write Response Channel
s2mm_bready <= sig_s2mm_bready or
sig_halt_reg; -- force bready if a Halt is requested
-- Assign the ready output to the Data Controller status interface
wsc2data_ready <= sig_wsc2data_ready;
-- Assign the status valid output control to the Status FIFO
wsc2stat_status_valid <= sig_status_valid ;
-- Formulate the status output value to the Status FIFO
wsc2stat_status <= sig_wsc2stat_status;
-- Formulate the status write request signal
sig_status_valid <= sig_push_status;
-- Indicate the desire to push a coelesced status word
-- to the Status FIFO
sig_push_status <= sig_coelsc_reg_full;
-- Detect that a push of a new status word is completing
sig_status_push_ok <= sig_status_valid and
stat2wsc_status_ready;
sig_pop_coelsc_reg <= sig_status_push_ok;
-- Signal a halt to the execution pipe if new status
-- is valid but the Status FIFO is not accepting it or
-- the WDC Status FIFO is going full
wsc2mstr_halt_pipe <= (sig_status_valid and
not(stat2wsc_status_ready)) or
sig_wdc_status_going_full;
-- Monitor the Status capture registers to detect a
-- qualified Status set and push to the coelescing register
-- when available to do so
sig_push_coelsc_reg <= sig_valid_status_rdy and
sig_coelsc_reg_empty;
-- pre CR616212 sig_valid_status_rdy <= (sig_wresp_sfifo_rd_valid and
-- pre CR616212 sig_dcntl_sfifo_rd_valid) or
-- pre CR616212 (sig_data_err_reg and
-- pre CR616212 sig_dcntl_sfifo_rd_valid);
sig_valid_status_rdy <= (sig_wresp_sfifo_rd_valid and
sig_dcntl_sfifo_rd_valid) or
(sig_data_err_reg and
sig_dcntl_sfifo_rd_valid) or -- or Added for CR616212
(sig_data_last_err_reg and -- Added for CR616212
sig_dcntl_sfifo_rd_valid); -- Added for CR616212
-- Decode the AXI MMap Read Respose
sig_decerr <= '1'
When sig_bresp_reg = DECERR
Else '0';
sig_slverr <= '1'
When sig_bresp_reg = SLVERR
Else '0';
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_TAG_LE_STAT
--
-- If Generate Description:
-- Populates the TAG bits into the availble Status bits when
-- the TAG width is less than or equal to the available number
-- of bits in the Status word.
--
------------------------------------------------------------
GEN_TAG_LE_STAT : if (TAG_WIDTH <= STAT_REG_TAG_WIDTH) generate
-- local signals
signal lsig_temp_tag_small : std_logic_vector(STAT_REG_TAG_WIDTH-1 downto 0) := (others => '0');
begin
sig_tag2status <= lsig_temp_tag_small;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: POPULATE_SMALL_TAG
--
-- Process Description:
--
--
-------------------------------------------------------------
POPULATE_SMALL_TAG : process (sig_coelsc_tag_reg)
begin
-- Set default value
lsig_temp_tag_small <= (others => '0');
-- Now overload actual TAG bits
lsig_temp_tag_small(TAG_WIDTH-1 downto 0) <= sig_coelsc_tag_reg;
end process POPULATE_SMALL_TAG;
end generate GEN_TAG_LE_STAT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_TAG_GT_STAT
--
-- If Generate Description:
-- Populates the TAG bits into the availble Status bits when
-- the TAG width is greater than the available number of
-- bits in the Status word. The upper bits of the TAG are
-- clipped off (discarded).
--
------------------------------------------------------------
GEN_TAG_GT_STAT : if (TAG_WIDTH > STAT_REG_TAG_WIDTH) generate
-- local signals
signal lsig_temp_tag_big : std_logic_vector(STAT_REG_TAG_WIDTH-1 downto 0) := (others => '0');
begin
sig_tag2status <= lsig_temp_tag_big;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: POPULATE_BIG_TAG
--
-- Process Description:
--
--
-------------------------------------------------------------
POPULATE_SMALL_TAG : process (sig_coelsc_tag_reg)
begin
-- Set default value
lsig_temp_tag_big <= (others => '0');
-- Now overload actual TAG bits
lsig_temp_tag_big <= sig_coelsc_tag_reg(STAT_REG_TAG_WIDTH-1 downto 0);
end process POPULATE_SMALL_TAG;
end generate GEN_TAG_GT_STAT;
-------------------------------------------------------------------------
-- Write Response Channel input FIFO and logic
-- BRESP is the only fifo data
sig_wresp_sfifo_in <= s2mm_bresp;
-- The fifo output is already in the right format
sig_bresp_reg <= sig_wresp_sfifo_out;
-- Write Side assignments
sig_wresp_sfifo_wr_valid <= s2mm_bvalid;
sig_s2mm_bready <= sig_wresp_sfifo_wr_ready;
-- read Side ready assignment
sig_wresp_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_WRESP_STATUS_FIFO
--
-- Description:
-- Instance for the AXI Write Response FIFO
--
------------------------------------------------------------
I_WRESP_STATUS_FIFO : entity axi_datamover_v5_1_11.axi_datamover_fifo
generic map (
C_DWIDTH => WRESP_SFIFO_WIDTH ,
C_DEPTH => WRESP_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_wresp_sfifo_wr_valid ,
fifo_wr_tready => sig_wresp_sfifo_wr_ready ,
fifo_wr_tdata => sig_wresp_sfifo_in ,
fifo_wr_full => sig_wresp_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_wresp_sfifo_rd_valid ,
fifo_rd_tready => sig_wresp_sfifo_rd_ready ,
fifo_rd_tdata => sig_wresp_sfifo_out ,
fifo_rd_empty => sig_wresp_sfifo_rd_empty
);
-------- Write Data Controller Status FIFO Going Full Logic -------------
sig_incr_statcnt <= sig_dcntl_sfifo_wr_valid and
sig_dcntl_sfifo_wr_ready;
sig_decr_statcnt <= sig_dcntl_sfifo_rd_valid and
sig_dcntl_sfifo_rd_ready;
sig_statcnt_eq_max <= '1'
when (sig_wdc_statcnt = DCNTL_STATCNT_MAX)
Else '0';
sig_statcnt_eq_0 <= '1'
when (sig_wdc_statcnt = DCNTL_STATCNT_ZERO)
Else '0';
sig_statcnt_gt_eq_thres <= '1'
when (sig_wdc_statcnt >= DCNTL_HALT_THRES)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_WDC_GOING_FULL_FLOP
--
-- Process Description:
-- Implements a flop for the WDC Status FIFO going full flag.
--
-------------------------------------------------------------
IMP_WDC_GOING_FULL_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_wdc_status_going_full <= '0';
else
sig_wdc_status_going_full <= sig_statcnt_gt_eq_thres;
end if;
end if;
end process IMP_WDC_GOING_FULL_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DCNTL_FIFO_CNTR
--
-- Process Description:
-- Implements a simple counter keeping track of the number
-- of entries in the WDC Status FIFO. If the Status FIFO gets
-- too full, the S2MM Data Pipe has to be halted.
--
-------------------------------------------------------------
IMP_DCNTL_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_wdc_statcnt <= (others => '0');
elsif (sig_incr_statcnt = '1' and
sig_decr_statcnt = '0' and
sig_statcnt_eq_max = '0') then
sig_wdc_statcnt <= sig_wdc_statcnt + DCNTL_STATCNT_ONE;
elsif (sig_incr_statcnt = '0' and
sig_decr_statcnt = '1' and
sig_statcnt_eq_0 = '0') then
sig_wdc_statcnt <= sig_wdc_statcnt - DCNTL_STATCNT_ONE;
else
null; -- Hold current count value
end if;
end if;
end process IMP_DCNTL_FIFO_CNTR;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Implements the logic needed when Indeterminate BTT is
-- not enabled in the S2MM function.
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
-- Local Constants
Constant DCNTL_SFIFO_WIDTH : integer := STAT_REG_TAG_WIDTH+3;
Constant DCNTL_SFIFO_CMD_CMPLT_INDEX : integer := 0;
Constant DCNTL_SFIFO_TLAST_ERR_INDEX : integer := 1;
Constant DCNTL_SFIFO_CALC_ERR_INDEX : integer := 2;
Constant DCNTL_SFIFO_TAG_INDEX : integer := DCNTL_SFIFO_CALC_ERR_INDEX+1;
-- local signals
signal sig_dcntl_sfifo_in : std_logic_vector(DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_out : std_logic_vector(DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
begin
sig_wsc2stat_status <= sig_coelsc_okay_reg &
sig_coelsc_slverr_reg &
sig_coelsc_decerr_reg &
sig_coelsc_interr_reg &
sig_tag2status;
-----------------------------------------------------------------------------
-- Data Controller Status FIFO and Logic
-- Concatonate Input bits to build Dcntl fifo data word
sig_dcntl_sfifo_in <= data2wsc_tag & -- bit 3 to tag Width+2
data2wsc_calc_error & -- bit 2
data2wsc_last_error & -- bit 1
data2wsc_cmd_cmplt ; -- bit 0
-- Rip the DCntl fifo outputs back to constituant pieces
sig_data_tag_reg <= sig_dcntl_sfifo_out((DCNTL_SFIFO_TAG_INDEX+STAT_REG_TAG_WIDTH)-1 downto
DCNTL_SFIFO_TAG_INDEX);
sig_data_err_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_CALC_ERR_INDEX) ;
sig_data_last_err_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_TLAST_ERR_INDEX);
sig_data_cmd_cmplt_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_CMD_CMPLT_INDEX);
-- Data Control Valid/Ready assignments
sig_dcntl_sfifo_wr_valid <= data2wsc_valid ;
sig_wsc2data_ready <= sig_dcntl_sfifo_wr_ready;
-- read side ready assignment
sig_dcntl_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_DATA_CNTL_STATUS_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO
--
------------------------------------------------------------
I_DATA_CNTL_STATUS_FIFO : entity axi_datamover_v5_1_11.axi_datamover_fifo
generic map (
C_DWIDTH => DCNTL_SFIFO_WIDTH ,
C_DEPTH => DCNTL_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_dcntl_sfifo_wr_valid ,
fifo_wr_tready => sig_dcntl_sfifo_wr_ready ,
fifo_wr_tdata => sig_dcntl_sfifo_in ,
fifo_wr_full => sig_dcntl_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_dcntl_sfifo_rd_valid ,
fifo_rd_tready => sig_dcntl_sfifo_rd_ready ,
fifo_rd_tdata => sig_dcntl_sfifo_out ,
fifo_rd_empty => sig_dcntl_sfifo_rd_empty
);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: STATUS_COELESC_REG
--
-- Process Description:
-- Implement error status coelescing register.
-- Once a bit is set it will remain set until the overall
-- status is written to the Status FIFO.
-- Tag bits are just registered at each valid dbeat.
--
-------------------------------------------------------------
STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_pop_coelsc_reg = '1') then
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
sig_coelsc_reg_full <= '0';
sig_coelsc_reg_empty <= '1';
Elsif (sig_push_coelsc_reg = '1') Then
sig_coelsc_tag_reg <= sig_data_tag_reg;
sig_coelsc_interr_reg <= sig_data_err_reg or
sig_data_last_err_reg or
sig_coelsc_interr_reg;
sig_coelsc_decerr_reg <= not(sig_data_err_reg) and
(sig_decerr or
sig_coelsc_decerr_reg);
sig_coelsc_slverr_reg <= not(sig_data_err_reg) and
(sig_slverr or
sig_coelsc_slverr_reg);
sig_coelsc_okay_reg <= not(sig_decerr or
sig_coelsc_decerr_reg or
sig_slverr or
sig_coelsc_slverr_reg or
sig_data_err_reg or
sig_data_last_err_reg or
sig_coelsc_interr_reg
);
sig_coelsc_reg_full <= sig_data_cmd_cmplt_reg;
sig_coelsc_reg_empty <= not(sig_data_cmd_cmplt_reg);
else
null; -- hold current state
end if;
end if;
end process STATUS_COELESC_REG;
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ENABLE_INDET_BTT
--
-- If Generate Description:
-- Implements the logic needed when Indeterminate BTT is
-- enabled in the S2MM function. Primary difference is the
-- addition to the reported status of the End of Packet
-- marker (EOP) and the received byte count for the parent
-- command.
--
------------------------------------------------------------
GEN_ENABLE_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
-- Local Constants
Constant SF_DCNTL_SFIFO_WIDTH : integer := TAG_WIDTH +
C_SF_BYTES_RCVD_WIDTH + 3;
Constant SF_SFIFO_LS_TAG_INDEX : integer := 0;
Constant SF_SFIFO_MS_TAG_INDEX : integer := SF_SFIFO_LS_TAG_INDEX + (TAG_WIDTH-1);
Constant SF_SFIFO_CALC_ERR_INDEX : integer := SF_SFIFO_MS_TAG_INDEX+1;
Constant SF_SFIFO_CMD_CMPLT_INDEX : integer := SF_SFIFO_CALC_ERR_INDEX+1;
Constant SF_SFIFO_LS_BYTES_RCVD_INDEX : integer := SF_SFIFO_CMD_CMPLT_INDEX+1;
Constant SF_SFIFO_MS_BYTES_RCVD_INDEX : integer := SF_SFIFO_LS_BYTES_RCVD_INDEX+
(C_SF_BYTES_RCVD_WIDTH-1);
Constant SF_SFIFO_EOP_INDEX : integer := SF_SFIFO_MS_BYTES_RCVD_INDEX+1;
Constant BYTES_RCVD_FIELD_WIDTH : integer := 23;
-- local signals
signal sig_dcntl_sfifo_in : std_logic_vector(SF_DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_out : std_logic_vector(SF_DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_bytes_rcvd : std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_data_eop : std_logic := '0';
signal sig_coelsc_bytes_rcvd : std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_coelsc_eop : std_logic := '0';
signal sig_coelsc_bytes_rcvd_pad : std_logic_vector(BYTES_RCVD_FIELD_WIDTH-1 downto 0) := (others => '0');
begin
sig_wsc2stat_status <= sig_coelsc_eop &
sig_coelsc_bytes_rcvd_pad &
sig_coelsc_okay_reg &
sig_coelsc_slverr_reg &
sig_coelsc_decerr_reg &
sig_coelsc_interr_reg &
sig_tag2status;
-----------------------------------------------------------------------------
-- Data Controller Status FIFO and Logic
-- Concatonate Input bits to build Dcntl fifo input data word
sig_dcntl_sfifo_in <= data2wsc_eop & -- ms bit
data2wsc_bytes_rcvd & -- bit 7 to C_SF_BYTES_RCVD_WIDTH+7
data2wsc_cmd_cmplt & -- bit 6
data2wsc_calc_error & -- bit 4
data2wsc_tag; -- bits 0 to 3
-- Rip the DCntl fifo outputs back to constituant pieces
sig_data_eop <= sig_dcntl_sfifo_out(SF_SFIFO_EOP_INDEX);
sig_data_bytes_rcvd <= sig_dcntl_sfifo_out(SF_SFIFO_MS_BYTES_RCVD_INDEX downto
SF_SFIFO_LS_BYTES_RCVD_INDEX);
sig_data_cmd_cmplt_reg <= sig_dcntl_sfifo_out(SF_SFIFO_CMD_CMPLT_INDEX);
sig_data_err_reg <= sig_dcntl_sfifo_out(SF_SFIFO_CALC_ERR_INDEX);
sig_data_tag_reg <= sig_dcntl_sfifo_out(SF_SFIFO_MS_TAG_INDEX downto
SF_SFIFO_LS_TAG_INDEX) ;
-- Data Control Valid/Ready assignments
sig_dcntl_sfifo_wr_valid <= data2wsc_valid ;
sig_wsc2data_ready <= sig_dcntl_sfifo_wr_ready;
-- read side ready assignment
sig_dcntl_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_SF_DATA_CNTL_STATUS_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO when Store and
-- Forward is included.
--
------------------------------------------------------------
I_SF_DATA_CNTL_STATUS_FIFO : entity axi_datamover_v5_1_11.axi_datamover_fifo
generic map (
C_DWIDTH => SF_DCNTL_SFIFO_WIDTH ,
C_DEPTH => DCNTL_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_dcntl_sfifo_wr_valid ,
fifo_wr_tready => sig_dcntl_sfifo_wr_ready ,
fifo_wr_tdata => sig_dcntl_sfifo_in ,
fifo_wr_full => sig_dcntl_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_dcntl_sfifo_rd_valid ,
fifo_rd_tready => sig_dcntl_sfifo_rd_ready ,
fifo_rd_tdata => sig_dcntl_sfifo_out ,
fifo_rd_empty => sig_dcntl_sfifo_rd_empty
);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SF_STATUS_COELESC_REG
--
-- Process Description:
-- Implement error status coelescing register.
-- Once a bit is set it will remain set until the overall
-- status is written to the Status FIFO.
-- Tag bits are just registered at each valid dbeat.
--
-------------------------------------------------------------
SF_STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_pop_coelsc_reg = '1') then
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
sig_coelsc_bytes_rcvd <= (others => '0');
sig_coelsc_eop <= '0';
sig_coelsc_reg_full <= '0';
sig_coelsc_reg_empty <= '1';
Elsif (sig_push_coelsc_reg = '1') Then
sig_coelsc_tag_reg <= sig_data_tag_reg;
sig_coelsc_interr_reg <= sig_data_err_reg or
sig_coelsc_interr_reg;
sig_coelsc_decerr_reg <= not(sig_data_err_reg) and
(sig_decerr or
sig_coelsc_decerr_reg);
sig_coelsc_slverr_reg <= not(sig_data_err_reg) and
(sig_slverr or
sig_coelsc_slverr_reg);
sig_coelsc_okay_reg <= not(sig_decerr or
sig_coelsc_decerr_reg or
sig_slverr or
sig_coelsc_slverr_reg or
sig_data_err_reg or
sig_coelsc_interr_reg
);
sig_coelsc_bytes_rcvd <= sig_data_bytes_rcvd;
sig_coelsc_eop <= sig_data_eop;
sig_coelsc_reg_full <= sig_data_cmd_cmplt_reg;
sig_coelsc_reg_empty <= not(sig_data_cmd_cmplt_reg);
else
null; -- hold current state
end if;
end if;
end process SF_STATUS_COELESC_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: SF_GEN_PAD_BYTES_RCVD
--
-- If Generate Description:
-- Pad the bytes received value with zeros to fill in the
-- status field width.
--
--
------------------------------------------------------------
SF_GEN_PAD_BYTES_RCVD : if (C_SF_BYTES_RCVD_WIDTH < BYTES_RCVD_FIELD_WIDTH) generate
begin
sig_coelsc_bytes_rcvd_pad(BYTES_RCVD_FIELD_WIDTH-1 downto
C_SF_BYTES_RCVD_WIDTH) <= (others => '0');
sig_coelsc_bytes_rcvd_pad(C_SF_BYTES_RCVD_WIDTH-1 downto 0) <= sig_coelsc_bytes_rcvd;
end generate SF_GEN_PAD_BYTES_RCVD;
------------------------------------------------------------
-- If Generate
--
-- Label: SF_GEN_NO_PAD_BYTES_RCVD
--
-- If Generate Description:
-- No padding required for the bytes received value.
--
--
------------------------------------------------------------
SF_GEN_NO_PAD_BYTES_RCVD : if (C_SF_BYTES_RCVD_WIDTH = BYTES_RCVD_FIELD_WIDTH) generate
begin
sig_coelsc_bytes_rcvd_pad <= sig_coelsc_bytes_rcvd; -- no pad required
end generate SF_GEN_NO_PAD_BYTES_RCVD;
end generate GEN_ENABLE_INDET_BTT;
------- Soft Shutdown Logic -------------------------------
-- Address Posted Counter Logic ---------------------t-----------------
-- Supports soft shutdown by tracking when all commited Write
-- transfers to the AXI Bus have had corresponding Write Status
-- Reponses Received.
sig_addr_posted <= addr2wsc_addr_posted ;
sig_incr_addr_posted_cntr <= sig_addr_posted ;
sig_decr_addr_posted_cntr <= sig_s2mm_bready and
s2mm_bvalid ;
sig_addr_posted_cntr_eq_0 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ZERO)
Else '0';
sig_addr_posted_cntr_eq_1 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ONE)
Else '0';
sig_addr_posted_cntr_max <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_POSTED_FIFO_CNTR
--
-- Process Description:
-- This process implements a counter for the tracking
-- if an Address has been posted on the AXI address channel.
-- The counter is used to track flushing operations where all
-- transfers committed on the AXI Address Channel have to
-- be completed before a halt can occur.
-------------------------------------------------------------
IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_addr_posted_cntr <= ADDR_POSTED_ZERO;
elsif (sig_incr_addr_posted_cntr = '1' and
sig_decr_addr_posted_cntr = '0' and
sig_addr_posted_cntr_max = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ;
elsif (sig_incr_addr_posted_cntr = '0' and
sig_decr_addr_posted_cntr = '1' and
sig_addr_posted_cntr_eq_0 = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_POSTED_FIFO_CNTR;
wsc2rst_stop_cmplt <= sig_all_cmds_done;
sig_no_posted_cmds <= (sig_addr_posted_cntr_eq_0 and
not(addr2wsc_calc_error)) or
(sig_addr_posted_cntr_eq_1 and
addr2wsc_calc_error);
sig_all_cmds_done <= sig_no_posted_cmds and
sig_halt_reg_dly3;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG
--
-- Process Description:
-- Implements the flop for capturing the Halt request from
-- the Reset module.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg <= '0';
elsif (rst2wsc_stop_request = '1') then
sig_halt_reg <= '1';
else
null; -- Hold current State
end if;
end if;
end process IMP_HALT_REQ_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG_DLY
--
-- Process Description:
-- Implements the flops for delaying the halt request by 3
-- clocks to allow the Address Controller to halt before the
-- Data Contoller can safely indicate it has exhausted all
-- transfers committed to the AXI Address Channel by the Address
-- Controller.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG_DLY : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg_dly1 <= '0';
sig_halt_reg_dly2 <= '0';
sig_halt_reg_dly3 <= '0';
else
sig_halt_reg_dly1 <= sig_halt_reg;
sig_halt_reg_dly2 <= sig_halt_reg_dly1;
sig_halt_reg_dly3 <= sig_halt_reg_dly2;
end if;
end if;
end process IMP_HALT_REQ_REG_DLY;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_wr_status_cntl.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_wr_status_cntl.vhd
--
-- Description:
-- This file implements the DataMover Master Write Status Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_11;
use axi_datamover_v5_1_11.axi_datamover_fifo;
-------------------------------------------------------------------------------
entity axi_datamover_wr_status_cntl is
generic (
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if the Indeterminate BTT Module is enabled
-- for use (outside of this module)
C_SF_BYTES_RCVD_WIDTH : Integer range 1 to 23 := 1;
-- Sets the width of the data2wsc_bytes_rcvd port used for
-- relaying the actual number of bytes received when Idet BTT is
-- enabled (C_ENABLE_INDET_BTT = 1)
C_STS_FIFO_DEPTH : Integer range 1 to 32 := 8;
-- Specifies the depth of the internal status queue fifo
C_STS_WIDTH : Integer range 8 to 32 := 8;
-- sets the width of the Status ports
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the Status reply
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA device family
);
port (
-- Clock and Reset inputs ------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------------
-- Soft Shutdown Control interface --------------------------------
--
rst2wsc_stop_request : in std_logic; --
-- Active high soft stop request to modules --
--
wsc2rst_stop_cmplt : Out std_logic; --
-- Active high indication that the Write status Controller --
-- has completed any pending transfers committed by the --
-- Address Controller after a stop has been requested by --
-- the Reset module. --
--
addr2wsc_addr_posted : In std_logic ; --
-- Indication from the Address Channel Controller to the --
-- write Status Controller that an address has been posted --
-- to the AXI Address Channel --
--------------------------------------------------------------------
-- Write Response Channel Interface -------------------------------
--
s2mm_bresp : In std_logic_vector(1 downto 0); --
-- The Write response value --
--
s2mm_bvalid : In std_logic ; --
-- Indication from the Write Response Channel that a new --
-- write status input is valid --
--
s2mm_bready : out std_logic ; --
-- Indication to the Write Response Channel that the --
-- Status module is ready for a new status input --
--------------------------------------------------------------------
-- Command Calculator Interface -------------------------------------
--
calc2wsc_calc_error : in std_logic ; --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
---------------------------------------------------------------------
-- Address Controller Status ----------------------------------------
--
addr2wsc_calc_error : In std_logic ; --
-- Indication from the Address Channel Controller that it --
-- has encountered a calculation error from the command --
-- Calculator --
--
addr2wsc_fifo_empty : In std_logic ; --
-- Indication from the Address Controller FIFO that it --
-- is empty (no commands pending) --
---------------------------------------------------------------------
-- Data Controller Status ---------------------------------------------------------
--
data2wsc_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The command tag --
--
data2wsc_calc_error : In std_logic ; --
-- Indication from the Data Channel Controller FIFO that it --
-- has encountered a Calculation error in the command pipe --
--
data2wsc_last_error : In std_logic ; --
-- Indication from the Write Data Channel Controller that a --
-- premature TLAST assertion was encountered on the incoming --
-- Stream Channel --
--
data2wsc_cmd_cmplt : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- corresponding status is the final status for a parent --
-- command fetched from the command FIFO --
--
data2wsc_valid : In std_logic ; --
-- Indication from the Data Channel Controller FIFO that it --
-- has a new tag/error status to transfer --
--
wsc2data_ready : out std_logic ; --
-- Indication to the Data Channel Controller FIFO that the --
-- Status module is ready for a new tag/error status input --
--
--
data2wsc_eop : In std_logic; --
-- Input from the Write Data Controller indicating that the --
-- associated command status also corresponds to a End of Packet --
-- marker for the input Stream. This is only used when Store and --
-- Forward is enabled in the S2MM. --
--
data2wsc_bytes_rcvd : In std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0); --
-- Input from the Write Data Controller indicating the actual --
-- number of bytes received from the Stream input for the --
-- corresponding command status. This is only used when Store and --
-- Forward is enabled in the S2MM. --
------------------------------------------------------------------------------------
-- Command/Status Interface --------------------------------------------------------
--
wsc2stat_status : Out std_logic_vector(C_STS_WIDTH-1 downto 0); --
-- Read Status value collected during a Read Data transfer --
-- Output to the Command/Status Module --
--
stat2wsc_status_ready : In std_logic; --
-- Input from the Command/Status Module indicating that the --
-- Status Reg/FIFO is Full and cannot accept more staus writes --
--
wsc2stat_status_valid : Out std_logic ; --
-- Control Signal to Write the Status value to the Status --
-- Reg/FIFO --
------------------------------------------------------------------------------------
-- Address and Data Controller Pipe halt --------------------------------
--
wsc2mstr_halt_pipe : Out std_logic --
-- Indication to Halt the Data and Address Command pipeline due --
-- to the Status pipe getting full at some point --
-------------------------------------------------------------------------
);
end entity axi_datamover_wr_status_cntl;
architecture implementation of axi_datamover_wr_status_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_cnt_width
--
-- Function Description:
-- Sets a count width based on a fifo depth. A depth of 4 or less
-- is a special case which requires a minimum count width of 3 bits.
--
-------------------------------------------------------------------
function funct_set_cnt_width (fifo_depth : integer) return integer is
Variable temp_cnt_width : Integer := 4;
begin
if (fifo_depth <= 4) then
temp_cnt_width := 3;
elsif (fifo_depth <= 8) then
temp_cnt_width := 4;
elsif (fifo_depth <= 16) then
temp_cnt_width := 5;
elsif (fifo_depth <= 32) then
temp_cnt_width := 6;
else -- fifo depth <= 64
temp_cnt_width := 7;
end if;
Return (temp_cnt_width);
end function funct_set_cnt_width;
-- Constant Declarations --------------------------------------------
Constant OKAY : std_logic_vector(1 downto 0) := "00";
Constant EXOKAY : std_logic_vector(1 downto 0) := "01";
Constant SLVERR : std_logic_vector(1 downto 0) := "10";
Constant DECERR : std_logic_vector(1 downto 0) := "11";
Constant STAT_RSVD : std_logic_vector(3 downto 0) := "0000";
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant STAT_REG_TAG_WIDTH : integer := 4;
Constant SYNC_FIFO_SELECT : integer := 0;
Constant SRL_FIFO_TYPE : integer := 2;
Constant DCNTL_SFIFO_DEPTH : integer := C_STS_FIFO_DEPTH;
Constant DCNTL_STATCNT_WIDTH : integer := funct_set_cnt_width(C_STS_FIFO_DEPTH);-- bits
Constant DCNTL_HALT_THRES : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(DCNTL_SFIFO_DEPTH-2,DCNTL_STATCNT_WIDTH);
Constant DCNTL_STATCNT_ZERO : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := (others => '0');
Constant DCNTL_STATCNT_MAX : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(DCNTL_SFIFO_DEPTH,DCNTL_STATCNT_WIDTH);
Constant DCNTL_STATCNT_ONE : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, DCNTL_STATCNT_WIDTH);
Constant WRESP_WIDTH : integer := 2;
Constant WRESP_SFIFO_WIDTH : integer := WRESP_WIDTH;
Constant WRESP_SFIFO_DEPTH : integer := DCNTL_SFIFO_DEPTH;
Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_STS_FIFO_DEPTH);-- bits
Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '0');
Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH);
Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '1');
-- Signal Declarations --------------------------------------------
signal sig_valid_status_rdy : std_logic := '0';
signal sig_decerr : std_logic := '0';
signal sig_slverr : std_logic := '0';
signal sig_coelsc_okay_reg : std_logic := '0';
signal sig_coelsc_interr_reg : std_logic := '0';
signal sig_coelsc_decerr_reg : std_logic := '0';
signal sig_coelsc_slverr_reg : std_logic := '0';
signal sig_coelsc_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_coelsc_reg : std_logic := '0';
signal sig_push_coelsc_reg : std_logic := '0';
signal sig_coelsc_reg_empty : std_logic := '0';
signal sig_coelsc_reg_full : std_logic := '0';
signal sig_tag2status : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data_err_reg : std_logic := '0';
signal sig_data_last_err_reg : std_logic := '0';
signal sig_data_cmd_cmplt_reg : std_logic := '0';
signal sig_bresp_reg : std_logic_vector(1 downto 0) := (others => '0');
signal sig_push_status : std_logic := '0';
Signal sig_status_push_ok : std_logic := '0';
signal sig_status_valid : std_logic := '0';
signal sig_wsc2data_ready : std_logic := '0';
signal sig_s2mm_bready : std_logic := '0';
signal sig_wresp_sfifo_in : std_logic_vector(WRESP_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_wresp_sfifo_out : std_logic_vector(WRESP_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_wresp_sfifo_wr_valid : std_logic := '0';
signal sig_wresp_sfifo_wr_ready : std_logic := '0';
signal sig_wresp_sfifo_wr_full : std_logic := '0';
signal sig_wresp_sfifo_rd_valid : std_logic := '0';
signal sig_wresp_sfifo_rd_ready : std_logic := '0';
signal sig_wresp_sfifo_rd_empty : std_logic := '0';
signal sig_halt_reg : std_logic := '0';
signal sig_halt_reg_dly1 : std_logic := '0';
signal sig_halt_reg_dly2 : std_logic := '0';
signal sig_halt_reg_dly3 : std_logic := '0';
signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted_cntr_eq_0 : std_logic := '0';
signal sig_addr_posted_cntr_eq_1 : std_logic := '0';
signal sig_addr_posted_cntr_max : std_logic := '0';
signal sig_decr_addr_posted_cntr : std_logic := '0';
signal sig_incr_addr_posted_cntr : std_logic := '0';
signal sig_no_posted_cmds : std_logic := '0';
signal sig_addr_posted : std_logic := '0';
signal sig_all_cmds_done : std_logic := '0';
signal sig_wsc2stat_status : std_logic_vector(C_STS_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_wr_valid : std_logic := '0';
signal sig_dcntl_sfifo_wr_ready : std_logic := '0';
signal sig_dcntl_sfifo_wr_full : std_logic := '0';
signal sig_dcntl_sfifo_rd_valid : std_logic := '0';
signal sig_dcntl_sfifo_rd_ready : std_logic := '0';
signal sig_dcntl_sfifo_rd_empty : std_logic := '0';
signal sig_wdc_statcnt : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_statcnt : std_logic := '0';
signal sig_decr_statcnt : std_logic := '0';
signal sig_statcnt_eq_max : std_logic := '0';
signal sig_statcnt_eq_0 : std_logic := '0';
signal sig_statcnt_gt_eq_thres : std_logic := '0';
signal sig_wdc_status_going_full : std_logic := '0';
begin --(architecture implementation)
-- Assign the ready output to the AXI Write Response Channel
s2mm_bready <= sig_s2mm_bready or
sig_halt_reg; -- force bready if a Halt is requested
-- Assign the ready output to the Data Controller status interface
wsc2data_ready <= sig_wsc2data_ready;
-- Assign the status valid output control to the Status FIFO
wsc2stat_status_valid <= sig_status_valid ;
-- Formulate the status output value to the Status FIFO
wsc2stat_status <= sig_wsc2stat_status;
-- Formulate the status write request signal
sig_status_valid <= sig_push_status;
-- Indicate the desire to push a coelesced status word
-- to the Status FIFO
sig_push_status <= sig_coelsc_reg_full;
-- Detect that a push of a new status word is completing
sig_status_push_ok <= sig_status_valid and
stat2wsc_status_ready;
sig_pop_coelsc_reg <= sig_status_push_ok;
-- Signal a halt to the execution pipe if new status
-- is valid but the Status FIFO is not accepting it or
-- the WDC Status FIFO is going full
wsc2mstr_halt_pipe <= (sig_status_valid and
not(stat2wsc_status_ready)) or
sig_wdc_status_going_full;
-- Monitor the Status capture registers to detect a
-- qualified Status set and push to the coelescing register
-- when available to do so
sig_push_coelsc_reg <= sig_valid_status_rdy and
sig_coelsc_reg_empty;
-- pre CR616212 sig_valid_status_rdy <= (sig_wresp_sfifo_rd_valid and
-- pre CR616212 sig_dcntl_sfifo_rd_valid) or
-- pre CR616212 (sig_data_err_reg and
-- pre CR616212 sig_dcntl_sfifo_rd_valid);
sig_valid_status_rdy <= (sig_wresp_sfifo_rd_valid and
sig_dcntl_sfifo_rd_valid) or
(sig_data_err_reg and
sig_dcntl_sfifo_rd_valid) or -- or Added for CR616212
(sig_data_last_err_reg and -- Added for CR616212
sig_dcntl_sfifo_rd_valid); -- Added for CR616212
-- Decode the AXI MMap Read Respose
sig_decerr <= '1'
When sig_bresp_reg = DECERR
Else '0';
sig_slverr <= '1'
When sig_bresp_reg = SLVERR
Else '0';
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_TAG_LE_STAT
--
-- If Generate Description:
-- Populates the TAG bits into the availble Status bits when
-- the TAG width is less than or equal to the available number
-- of bits in the Status word.
--
------------------------------------------------------------
GEN_TAG_LE_STAT : if (TAG_WIDTH <= STAT_REG_TAG_WIDTH) generate
-- local signals
signal lsig_temp_tag_small : std_logic_vector(STAT_REG_TAG_WIDTH-1 downto 0) := (others => '0');
begin
sig_tag2status <= lsig_temp_tag_small;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: POPULATE_SMALL_TAG
--
-- Process Description:
--
--
-------------------------------------------------------------
POPULATE_SMALL_TAG : process (sig_coelsc_tag_reg)
begin
-- Set default value
lsig_temp_tag_small <= (others => '0');
-- Now overload actual TAG bits
lsig_temp_tag_small(TAG_WIDTH-1 downto 0) <= sig_coelsc_tag_reg;
end process POPULATE_SMALL_TAG;
end generate GEN_TAG_LE_STAT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_TAG_GT_STAT
--
-- If Generate Description:
-- Populates the TAG bits into the availble Status bits when
-- the TAG width is greater than the available number of
-- bits in the Status word. The upper bits of the TAG are
-- clipped off (discarded).
--
------------------------------------------------------------
GEN_TAG_GT_STAT : if (TAG_WIDTH > STAT_REG_TAG_WIDTH) generate
-- local signals
signal lsig_temp_tag_big : std_logic_vector(STAT_REG_TAG_WIDTH-1 downto 0) := (others => '0');
begin
sig_tag2status <= lsig_temp_tag_big;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: POPULATE_BIG_TAG
--
-- Process Description:
--
--
-------------------------------------------------------------
POPULATE_SMALL_TAG : process (sig_coelsc_tag_reg)
begin
-- Set default value
lsig_temp_tag_big <= (others => '0');
-- Now overload actual TAG bits
lsig_temp_tag_big <= sig_coelsc_tag_reg(STAT_REG_TAG_WIDTH-1 downto 0);
end process POPULATE_SMALL_TAG;
end generate GEN_TAG_GT_STAT;
-------------------------------------------------------------------------
-- Write Response Channel input FIFO and logic
-- BRESP is the only fifo data
sig_wresp_sfifo_in <= s2mm_bresp;
-- The fifo output is already in the right format
sig_bresp_reg <= sig_wresp_sfifo_out;
-- Write Side assignments
sig_wresp_sfifo_wr_valid <= s2mm_bvalid;
sig_s2mm_bready <= sig_wresp_sfifo_wr_ready;
-- read Side ready assignment
sig_wresp_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_WRESP_STATUS_FIFO
--
-- Description:
-- Instance for the AXI Write Response FIFO
--
------------------------------------------------------------
I_WRESP_STATUS_FIFO : entity axi_datamover_v5_1_11.axi_datamover_fifo
generic map (
C_DWIDTH => WRESP_SFIFO_WIDTH ,
C_DEPTH => WRESP_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_wresp_sfifo_wr_valid ,
fifo_wr_tready => sig_wresp_sfifo_wr_ready ,
fifo_wr_tdata => sig_wresp_sfifo_in ,
fifo_wr_full => sig_wresp_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_wresp_sfifo_rd_valid ,
fifo_rd_tready => sig_wresp_sfifo_rd_ready ,
fifo_rd_tdata => sig_wresp_sfifo_out ,
fifo_rd_empty => sig_wresp_sfifo_rd_empty
);
-------- Write Data Controller Status FIFO Going Full Logic -------------
sig_incr_statcnt <= sig_dcntl_sfifo_wr_valid and
sig_dcntl_sfifo_wr_ready;
sig_decr_statcnt <= sig_dcntl_sfifo_rd_valid and
sig_dcntl_sfifo_rd_ready;
sig_statcnt_eq_max <= '1'
when (sig_wdc_statcnt = DCNTL_STATCNT_MAX)
Else '0';
sig_statcnt_eq_0 <= '1'
when (sig_wdc_statcnt = DCNTL_STATCNT_ZERO)
Else '0';
sig_statcnt_gt_eq_thres <= '1'
when (sig_wdc_statcnt >= DCNTL_HALT_THRES)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_WDC_GOING_FULL_FLOP
--
-- Process Description:
-- Implements a flop for the WDC Status FIFO going full flag.
--
-------------------------------------------------------------
IMP_WDC_GOING_FULL_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_wdc_status_going_full <= '0';
else
sig_wdc_status_going_full <= sig_statcnt_gt_eq_thres;
end if;
end if;
end process IMP_WDC_GOING_FULL_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DCNTL_FIFO_CNTR
--
-- Process Description:
-- Implements a simple counter keeping track of the number
-- of entries in the WDC Status FIFO. If the Status FIFO gets
-- too full, the S2MM Data Pipe has to be halted.
--
-------------------------------------------------------------
IMP_DCNTL_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_wdc_statcnt <= (others => '0');
elsif (sig_incr_statcnt = '1' and
sig_decr_statcnt = '0' and
sig_statcnt_eq_max = '0') then
sig_wdc_statcnt <= sig_wdc_statcnt + DCNTL_STATCNT_ONE;
elsif (sig_incr_statcnt = '0' and
sig_decr_statcnt = '1' and
sig_statcnt_eq_0 = '0') then
sig_wdc_statcnt <= sig_wdc_statcnt - DCNTL_STATCNT_ONE;
else
null; -- Hold current count value
end if;
end if;
end process IMP_DCNTL_FIFO_CNTR;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Implements the logic needed when Indeterminate BTT is
-- not enabled in the S2MM function.
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
-- Local Constants
Constant DCNTL_SFIFO_WIDTH : integer := STAT_REG_TAG_WIDTH+3;
Constant DCNTL_SFIFO_CMD_CMPLT_INDEX : integer := 0;
Constant DCNTL_SFIFO_TLAST_ERR_INDEX : integer := 1;
Constant DCNTL_SFIFO_CALC_ERR_INDEX : integer := 2;
Constant DCNTL_SFIFO_TAG_INDEX : integer := DCNTL_SFIFO_CALC_ERR_INDEX+1;
-- local signals
signal sig_dcntl_sfifo_in : std_logic_vector(DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_out : std_logic_vector(DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
begin
sig_wsc2stat_status <= sig_coelsc_okay_reg &
sig_coelsc_slverr_reg &
sig_coelsc_decerr_reg &
sig_coelsc_interr_reg &
sig_tag2status;
-----------------------------------------------------------------------------
-- Data Controller Status FIFO and Logic
-- Concatonate Input bits to build Dcntl fifo data word
sig_dcntl_sfifo_in <= data2wsc_tag & -- bit 3 to tag Width+2
data2wsc_calc_error & -- bit 2
data2wsc_last_error & -- bit 1
data2wsc_cmd_cmplt ; -- bit 0
-- Rip the DCntl fifo outputs back to constituant pieces
sig_data_tag_reg <= sig_dcntl_sfifo_out((DCNTL_SFIFO_TAG_INDEX+STAT_REG_TAG_WIDTH)-1 downto
DCNTL_SFIFO_TAG_INDEX);
sig_data_err_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_CALC_ERR_INDEX) ;
sig_data_last_err_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_TLAST_ERR_INDEX);
sig_data_cmd_cmplt_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_CMD_CMPLT_INDEX);
-- Data Control Valid/Ready assignments
sig_dcntl_sfifo_wr_valid <= data2wsc_valid ;
sig_wsc2data_ready <= sig_dcntl_sfifo_wr_ready;
-- read side ready assignment
sig_dcntl_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_DATA_CNTL_STATUS_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO
--
------------------------------------------------------------
I_DATA_CNTL_STATUS_FIFO : entity axi_datamover_v5_1_11.axi_datamover_fifo
generic map (
C_DWIDTH => DCNTL_SFIFO_WIDTH ,
C_DEPTH => DCNTL_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_dcntl_sfifo_wr_valid ,
fifo_wr_tready => sig_dcntl_sfifo_wr_ready ,
fifo_wr_tdata => sig_dcntl_sfifo_in ,
fifo_wr_full => sig_dcntl_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_dcntl_sfifo_rd_valid ,
fifo_rd_tready => sig_dcntl_sfifo_rd_ready ,
fifo_rd_tdata => sig_dcntl_sfifo_out ,
fifo_rd_empty => sig_dcntl_sfifo_rd_empty
);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: STATUS_COELESC_REG
--
-- Process Description:
-- Implement error status coelescing register.
-- Once a bit is set it will remain set until the overall
-- status is written to the Status FIFO.
-- Tag bits are just registered at each valid dbeat.
--
-------------------------------------------------------------
STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_pop_coelsc_reg = '1') then
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
sig_coelsc_reg_full <= '0';
sig_coelsc_reg_empty <= '1';
Elsif (sig_push_coelsc_reg = '1') Then
sig_coelsc_tag_reg <= sig_data_tag_reg;
sig_coelsc_interr_reg <= sig_data_err_reg or
sig_data_last_err_reg or
sig_coelsc_interr_reg;
sig_coelsc_decerr_reg <= not(sig_data_err_reg) and
(sig_decerr or
sig_coelsc_decerr_reg);
sig_coelsc_slverr_reg <= not(sig_data_err_reg) and
(sig_slverr or
sig_coelsc_slverr_reg);
sig_coelsc_okay_reg <= not(sig_decerr or
sig_coelsc_decerr_reg or
sig_slverr or
sig_coelsc_slverr_reg or
sig_data_err_reg or
sig_data_last_err_reg or
sig_coelsc_interr_reg
);
sig_coelsc_reg_full <= sig_data_cmd_cmplt_reg;
sig_coelsc_reg_empty <= not(sig_data_cmd_cmplt_reg);
else
null; -- hold current state
end if;
end if;
end process STATUS_COELESC_REG;
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ENABLE_INDET_BTT
--
-- If Generate Description:
-- Implements the logic needed when Indeterminate BTT is
-- enabled in the S2MM function. Primary difference is the
-- addition to the reported status of the End of Packet
-- marker (EOP) and the received byte count for the parent
-- command.
--
------------------------------------------------------------
GEN_ENABLE_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
-- Local Constants
Constant SF_DCNTL_SFIFO_WIDTH : integer := TAG_WIDTH +
C_SF_BYTES_RCVD_WIDTH + 3;
Constant SF_SFIFO_LS_TAG_INDEX : integer := 0;
Constant SF_SFIFO_MS_TAG_INDEX : integer := SF_SFIFO_LS_TAG_INDEX + (TAG_WIDTH-1);
Constant SF_SFIFO_CALC_ERR_INDEX : integer := SF_SFIFO_MS_TAG_INDEX+1;
Constant SF_SFIFO_CMD_CMPLT_INDEX : integer := SF_SFIFO_CALC_ERR_INDEX+1;
Constant SF_SFIFO_LS_BYTES_RCVD_INDEX : integer := SF_SFIFO_CMD_CMPLT_INDEX+1;
Constant SF_SFIFO_MS_BYTES_RCVD_INDEX : integer := SF_SFIFO_LS_BYTES_RCVD_INDEX+
(C_SF_BYTES_RCVD_WIDTH-1);
Constant SF_SFIFO_EOP_INDEX : integer := SF_SFIFO_MS_BYTES_RCVD_INDEX+1;
Constant BYTES_RCVD_FIELD_WIDTH : integer := 23;
-- local signals
signal sig_dcntl_sfifo_in : std_logic_vector(SF_DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_out : std_logic_vector(SF_DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_bytes_rcvd : std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_data_eop : std_logic := '0';
signal sig_coelsc_bytes_rcvd : std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_coelsc_eop : std_logic := '0';
signal sig_coelsc_bytes_rcvd_pad : std_logic_vector(BYTES_RCVD_FIELD_WIDTH-1 downto 0) := (others => '0');
begin
sig_wsc2stat_status <= sig_coelsc_eop &
sig_coelsc_bytes_rcvd_pad &
sig_coelsc_okay_reg &
sig_coelsc_slverr_reg &
sig_coelsc_decerr_reg &
sig_coelsc_interr_reg &
sig_tag2status;
-----------------------------------------------------------------------------
-- Data Controller Status FIFO and Logic
-- Concatonate Input bits to build Dcntl fifo input data word
sig_dcntl_sfifo_in <= data2wsc_eop & -- ms bit
data2wsc_bytes_rcvd & -- bit 7 to C_SF_BYTES_RCVD_WIDTH+7
data2wsc_cmd_cmplt & -- bit 6
data2wsc_calc_error & -- bit 4
data2wsc_tag; -- bits 0 to 3
-- Rip the DCntl fifo outputs back to constituant pieces
sig_data_eop <= sig_dcntl_sfifo_out(SF_SFIFO_EOP_INDEX);
sig_data_bytes_rcvd <= sig_dcntl_sfifo_out(SF_SFIFO_MS_BYTES_RCVD_INDEX downto
SF_SFIFO_LS_BYTES_RCVD_INDEX);
sig_data_cmd_cmplt_reg <= sig_dcntl_sfifo_out(SF_SFIFO_CMD_CMPLT_INDEX);
sig_data_err_reg <= sig_dcntl_sfifo_out(SF_SFIFO_CALC_ERR_INDEX);
sig_data_tag_reg <= sig_dcntl_sfifo_out(SF_SFIFO_MS_TAG_INDEX downto
SF_SFIFO_LS_TAG_INDEX) ;
-- Data Control Valid/Ready assignments
sig_dcntl_sfifo_wr_valid <= data2wsc_valid ;
sig_wsc2data_ready <= sig_dcntl_sfifo_wr_ready;
-- read side ready assignment
sig_dcntl_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_SF_DATA_CNTL_STATUS_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO when Store and
-- Forward is included.
--
------------------------------------------------------------
I_SF_DATA_CNTL_STATUS_FIFO : entity axi_datamover_v5_1_11.axi_datamover_fifo
generic map (
C_DWIDTH => SF_DCNTL_SFIFO_WIDTH ,
C_DEPTH => DCNTL_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_dcntl_sfifo_wr_valid ,
fifo_wr_tready => sig_dcntl_sfifo_wr_ready ,
fifo_wr_tdata => sig_dcntl_sfifo_in ,
fifo_wr_full => sig_dcntl_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_dcntl_sfifo_rd_valid ,
fifo_rd_tready => sig_dcntl_sfifo_rd_ready ,
fifo_rd_tdata => sig_dcntl_sfifo_out ,
fifo_rd_empty => sig_dcntl_sfifo_rd_empty
);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SF_STATUS_COELESC_REG
--
-- Process Description:
-- Implement error status coelescing register.
-- Once a bit is set it will remain set until the overall
-- status is written to the Status FIFO.
-- Tag bits are just registered at each valid dbeat.
--
-------------------------------------------------------------
SF_STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_pop_coelsc_reg = '1') then
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
sig_coelsc_bytes_rcvd <= (others => '0');
sig_coelsc_eop <= '0';
sig_coelsc_reg_full <= '0';
sig_coelsc_reg_empty <= '1';
Elsif (sig_push_coelsc_reg = '1') Then
sig_coelsc_tag_reg <= sig_data_tag_reg;
sig_coelsc_interr_reg <= sig_data_err_reg or
sig_coelsc_interr_reg;
sig_coelsc_decerr_reg <= not(sig_data_err_reg) and
(sig_decerr or
sig_coelsc_decerr_reg);
sig_coelsc_slverr_reg <= not(sig_data_err_reg) and
(sig_slverr or
sig_coelsc_slverr_reg);
sig_coelsc_okay_reg <= not(sig_decerr or
sig_coelsc_decerr_reg or
sig_slverr or
sig_coelsc_slverr_reg or
sig_data_err_reg or
sig_coelsc_interr_reg
);
sig_coelsc_bytes_rcvd <= sig_data_bytes_rcvd;
sig_coelsc_eop <= sig_data_eop;
sig_coelsc_reg_full <= sig_data_cmd_cmplt_reg;
sig_coelsc_reg_empty <= not(sig_data_cmd_cmplt_reg);
else
null; -- hold current state
end if;
end if;
end process SF_STATUS_COELESC_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: SF_GEN_PAD_BYTES_RCVD
--
-- If Generate Description:
-- Pad the bytes received value with zeros to fill in the
-- status field width.
--
--
------------------------------------------------------------
SF_GEN_PAD_BYTES_RCVD : if (C_SF_BYTES_RCVD_WIDTH < BYTES_RCVD_FIELD_WIDTH) generate
begin
sig_coelsc_bytes_rcvd_pad(BYTES_RCVD_FIELD_WIDTH-1 downto
C_SF_BYTES_RCVD_WIDTH) <= (others => '0');
sig_coelsc_bytes_rcvd_pad(C_SF_BYTES_RCVD_WIDTH-1 downto 0) <= sig_coelsc_bytes_rcvd;
end generate SF_GEN_PAD_BYTES_RCVD;
------------------------------------------------------------
-- If Generate
--
-- Label: SF_GEN_NO_PAD_BYTES_RCVD
--
-- If Generate Description:
-- No padding required for the bytes received value.
--
--
------------------------------------------------------------
SF_GEN_NO_PAD_BYTES_RCVD : if (C_SF_BYTES_RCVD_WIDTH = BYTES_RCVD_FIELD_WIDTH) generate
begin
sig_coelsc_bytes_rcvd_pad <= sig_coelsc_bytes_rcvd; -- no pad required
end generate SF_GEN_NO_PAD_BYTES_RCVD;
end generate GEN_ENABLE_INDET_BTT;
------- Soft Shutdown Logic -------------------------------
-- Address Posted Counter Logic ---------------------t-----------------
-- Supports soft shutdown by tracking when all commited Write
-- transfers to the AXI Bus have had corresponding Write Status
-- Reponses Received.
sig_addr_posted <= addr2wsc_addr_posted ;
sig_incr_addr_posted_cntr <= sig_addr_posted ;
sig_decr_addr_posted_cntr <= sig_s2mm_bready and
s2mm_bvalid ;
sig_addr_posted_cntr_eq_0 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ZERO)
Else '0';
sig_addr_posted_cntr_eq_1 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ONE)
Else '0';
sig_addr_posted_cntr_max <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_POSTED_FIFO_CNTR
--
-- Process Description:
-- This process implements a counter for the tracking
-- if an Address has been posted on the AXI address channel.
-- The counter is used to track flushing operations where all
-- transfers committed on the AXI Address Channel have to
-- be completed before a halt can occur.
-------------------------------------------------------------
IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_addr_posted_cntr <= ADDR_POSTED_ZERO;
elsif (sig_incr_addr_posted_cntr = '1' and
sig_decr_addr_posted_cntr = '0' and
sig_addr_posted_cntr_max = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ;
elsif (sig_incr_addr_posted_cntr = '0' and
sig_decr_addr_posted_cntr = '1' and
sig_addr_posted_cntr_eq_0 = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_POSTED_FIFO_CNTR;
wsc2rst_stop_cmplt <= sig_all_cmds_done;
sig_no_posted_cmds <= (sig_addr_posted_cntr_eq_0 and
not(addr2wsc_calc_error)) or
(sig_addr_posted_cntr_eq_1 and
addr2wsc_calc_error);
sig_all_cmds_done <= sig_no_posted_cmds and
sig_halt_reg_dly3;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG
--
-- Process Description:
-- Implements the flop for capturing the Halt request from
-- the Reset module.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg <= '0';
elsif (rst2wsc_stop_request = '1') then
sig_halt_reg <= '1';
else
null; -- Hold current State
end if;
end if;
end process IMP_HALT_REQ_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG_DLY
--
-- Process Description:
-- Implements the flops for delaying the halt request by 3
-- clocks to allow the Address Controller to halt before the
-- Data Contoller can safely indicate it has exhausted all
-- transfers committed to the AXI Address Channel by the Address
-- Controller.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG_DLY : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg_dly1 <= '0';
sig_halt_reg_dly2 <= '0';
sig_halt_reg_dly3 <= '0';
else
sig_halt_reg_dly1 <= sig_halt_reg;
sig_halt_reg_dly2 <= sig_halt_reg_dly1;
sig_halt_reg_dly3 <= sig_halt_reg_dly2;
end if;
end if;
end process IMP_HALT_REQ_REG_DLY;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_wr_status_cntl.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_wr_status_cntl.vhd
--
-- Description:
-- This file implements the DataMover Master Write Status Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_11;
use axi_datamover_v5_1_11.axi_datamover_fifo;
-------------------------------------------------------------------------------
entity axi_datamover_wr_status_cntl is
generic (
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if the Indeterminate BTT Module is enabled
-- for use (outside of this module)
C_SF_BYTES_RCVD_WIDTH : Integer range 1 to 23 := 1;
-- Sets the width of the data2wsc_bytes_rcvd port used for
-- relaying the actual number of bytes received when Idet BTT is
-- enabled (C_ENABLE_INDET_BTT = 1)
C_STS_FIFO_DEPTH : Integer range 1 to 32 := 8;
-- Specifies the depth of the internal status queue fifo
C_STS_WIDTH : Integer range 8 to 32 := 8;
-- sets the width of the Status ports
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the Status reply
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA device family
);
port (
-- Clock and Reset inputs ------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------------
-- Soft Shutdown Control interface --------------------------------
--
rst2wsc_stop_request : in std_logic; --
-- Active high soft stop request to modules --
--
wsc2rst_stop_cmplt : Out std_logic; --
-- Active high indication that the Write status Controller --
-- has completed any pending transfers committed by the --
-- Address Controller after a stop has been requested by --
-- the Reset module. --
--
addr2wsc_addr_posted : In std_logic ; --
-- Indication from the Address Channel Controller to the --
-- write Status Controller that an address has been posted --
-- to the AXI Address Channel --
--------------------------------------------------------------------
-- Write Response Channel Interface -------------------------------
--
s2mm_bresp : In std_logic_vector(1 downto 0); --
-- The Write response value --
--
s2mm_bvalid : In std_logic ; --
-- Indication from the Write Response Channel that a new --
-- write status input is valid --
--
s2mm_bready : out std_logic ; --
-- Indication to the Write Response Channel that the --
-- Status module is ready for a new status input --
--------------------------------------------------------------------
-- Command Calculator Interface -------------------------------------
--
calc2wsc_calc_error : in std_logic ; --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
---------------------------------------------------------------------
-- Address Controller Status ----------------------------------------
--
addr2wsc_calc_error : In std_logic ; --
-- Indication from the Address Channel Controller that it --
-- has encountered a calculation error from the command --
-- Calculator --
--
addr2wsc_fifo_empty : In std_logic ; --
-- Indication from the Address Controller FIFO that it --
-- is empty (no commands pending) --
---------------------------------------------------------------------
-- Data Controller Status ---------------------------------------------------------
--
data2wsc_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The command tag --
--
data2wsc_calc_error : In std_logic ; --
-- Indication from the Data Channel Controller FIFO that it --
-- has encountered a Calculation error in the command pipe --
--
data2wsc_last_error : In std_logic ; --
-- Indication from the Write Data Channel Controller that a --
-- premature TLAST assertion was encountered on the incoming --
-- Stream Channel --
--
data2wsc_cmd_cmplt : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- corresponding status is the final status for a parent --
-- command fetched from the command FIFO --
--
data2wsc_valid : In std_logic ; --
-- Indication from the Data Channel Controller FIFO that it --
-- has a new tag/error status to transfer --
--
wsc2data_ready : out std_logic ; --
-- Indication to the Data Channel Controller FIFO that the --
-- Status module is ready for a new tag/error status input --
--
--
data2wsc_eop : In std_logic; --
-- Input from the Write Data Controller indicating that the --
-- associated command status also corresponds to a End of Packet --
-- marker for the input Stream. This is only used when Store and --
-- Forward is enabled in the S2MM. --
--
data2wsc_bytes_rcvd : In std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0); --
-- Input from the Write Data Controller indicating the actual --
-- number of bytes received from the Stream input for the --
-- corresponding command status. This is only used when Store and --
-- Forward is enabled in the S2MM. --
------------------------------------------------------------------------------------
-- Command/Status Interface --------------------------------------------------------
--
wsc2stat_status : Out std_logic_vector(C_STS_WIDTH-1 downto 0); --
-- Read Status value collected during a Read Data transfer --
-- Output to the Command/Status Module --
--
stat2wsc_status_ready : In std_logic; --
-- Input from the Command/Status Module indicating that the --
-- Status Reg/FIFO is Full and cannot accept more staus writes --
--
wsc2stat_status_valid : Out std_logic ; --
-- Control Signal to Write the Status value to the Status --
-- Reg/FIFO --
------------------------------------------------------------------------------------
-- Address and Data Controller Pipe halt --------------------------------
--
wsc2mstr_halt_pipe : Out std_logic --
-- Indication to Halt the Data and Address Command pipeline due --
-- to the Status pipe getting full at some point --
-------------------------------------------------------------------------
);
end entity axi_datamover_wr_status_cntl;
architecture implementation of axi_datamover_wr_status_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_cnt_width
--
-- Function Description:
-- Sets a count width based on a fifo depth. A depth of 4 or less
-- is a special case which requires a minimum count width of 3 bits.
--
-------------------------------------------------------------------
function funct_set_cnt_width (fifo_depth : integer) return integer is
Variable temp_cnt_width : Integer := 4;
begin
if (fifo_depth <= 4) then
temp_cnt_width := 3;
elsif (fifo_depth <= 8) then
temp_cnt_width := 4;
elsif (fifo_depth <= 16) then
temp_cnt_width := 5;
elsif (fifo_depth <= 32) then
temp_cnt_width := 6;
else -- fifo depth <= 64
temp_cnt_width := 7;
end if;
Return (temp_cnt_width);
end function funct_set_cnt_width;
-- Constant Declarations --------------------------------------------
Constant OKAY : std_logic_vector(1 downto 0) := "00";
Constant EXOKAY : std_logic_vector(1 downto 0) := "01";
Constant SLVERR : std_logic_vector(1 downto 0) := "10";
Constant DECERR : std_logic_vector(1 downto 0) := "11";
Constant STAT_RSVD : std_logic_vector(3 downto 0) := "0000";
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant STAT_REG_TAG_WIDTH : integer := 4;
Constant SYNC_FIFO_SELECT : integer := 0;
Constant SRL_FIFO_TYPE : integer := 2;
Constant DCNTL_SFIFO_DEPTH : integer := C_STS_FIFO_DEPTH;
Constant DCNTL_STATCNT_WIDTH : integer := funct_set_cnt_width(C_STS_FIFO_DEPTH);-- bits
Constant DCNTL_HALT_THRES : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(DCNTL_SFIFO_DEPTH-2,DCNTL_STATCNT_WIDTH);
Constant DCNTL_STATCNT_ZERO : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := (others => '0');
Constant DCNTL_STATCNT_MAX : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(DCNTL_SFIFO_DEPTH,DCNTL_STATCNT_WIDTH);
Constant DCNTL_STATCNT_ONE : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, DCNTL_STATCNT_WIDTH);
Constant WRESP_WIDTH : integer := 2;
Constant WRESP_SFIFO_WIDTH : integer := WRESP_WIDTH;
Constant WRESP_SFIFO_DEPTH : integer := DCNTL_SFIFO_DEPTH;
Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_STS_FIFO_DEPTH);-- bits
Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '0');
Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH);
Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '1');
-- Signal Declarations --------------------------------------------
signal sig_valid_status_rdy : std_logic := '0';
signal sig_decerr : std_logic := '0';
signal sig_slverr : std_logic := '0';
signal sig_coelsc_okay_reg : std_logic := '0';
signal sig_coelsc_interr_reg : std_logic := '0';
signal sig_coelsc_decerr_reg : std_logic := '0';
signal sig_coelsc_slverr_reg : std_logic := '0';
signal sig_coelsc_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_coelsc_reg : std_logic := '0';
signal sig_push_coelsc_reg : std_logic := '0';
signal sig_coelsc_reg_empty : std_logic := '0';
signal sig_coelsc_reg_full : std_logic := '0';
signal sig_tag2status : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data_err_reg : std_logic := '0';
signal sig_data_last_err_reg : std_logic := '0';
signal sig_data_cmd_cmplt_reg : std_logic := '0';
signal sig_bresp_reg : std_logic_vector(1 downto 0) := (others => '0');
signal sig_push_status : std_logic := '0';
Signal sig_status_push_ok : std_logic := '0';
signal sig_status_valid : std_logic := '0';
signal sig_wsc2data_ready : std_logic := '0';
signal sig_s2mm_bready : std_logic := '0';
signal sig_wresp_sfifo_in : std_logic_vector(WRESP_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_wresp_sfifo_out : std_logic_vector(WRESP_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_wresp_sfifo_wr_valid : std_logic := '0';
signal sig_wresp_sfifo_wr_ready : std_logic := '0';
signal sig_wresp_sfifo_wr_full : std_logic := '0';
signal sig_wresp_sfifo_rd_valid : std_logic := '0';
signal sig_wresp_sfifo_rd_ready : std_logic := '0';
signal sig_wresp_sfifo_rd_empty : std_logic := '0';
signal sig_halt_reg : std_logic := '0';
signal sig_halt_reg_dly1 : std_logic := '0';
signal sig_halt_reg_dly2 : std_logic := '0';
signal sig_halt_reg_dly3 : std_logic := '0';
signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted_cntr_eq_0 : std_logic := '0';
signal sig_addr_posted_cntr_eq_1 : std_logic := '0';
signal sig_addr_posted_cntr_max : std_logic := '0';
signal sig_decr_addr_posted_cntr : std_logic := '0';
signal sig_incr_addr_posted_cntr : std_logic := '0';
signal sig_no_posted_cmds : std_logic := '0';
signal sig_addr_posted : std_logic := '0';
signal sig_all_cmds_done : std_logic := '0';
signal sig_wsc2stat_status : std_logic_vector(C_STS_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_wr_valid : std_logic := '0';
signal sig_dcntl_sfifo_wr_ready : std_logic := '0';
signal sig_dcntl_sfifo_wr_full : std_logic := '0';
signal sig_dcntl_sfifo_rd_valid : std_logic := '0';
signal sig_dcntl_sfifo_rd_ready : std_logic := '0';
signal sig_dcntl_sfifo_rd_empty : std_logic := '0';
signal sig_wdc_statcnt : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_statcnt : std_logic := '0';
signal sig_decr_statcnt : std_logic := '0';
signal sig_statcnt_eq_max : std_logic := '0';
signal sig_statcnt_eq_0 : std_logic := '0';
signal sig_statcnt_gt_eq_thres : std_logic := '0';
signal sig_wdc_status_going_full : std_logic := '0';
begin --(architecture implementation)
-- Assign the ready output to the AXI Write Response Channel
s2mm_bready <= sig_s2mm_bready or
sig_halt_reg; -- force bready if a Halt is requested
-- Assign the ready output to the Data Controller status interface
wsc2data_ready <= sig_wsc2data_ready;
-- Assign the status valid output control to the Status FIFO
wsc2stat_status_valid <= sig_status_valid ;
-- Formulate the status output value to the Status FIFO
wsc2stat_status <= sig_wsc2stat_status;
-- Formulate the status write request signal
sig_status_valid <= sig_push_status;
-- Indicate the desire to push a coelesced status word
-- to the Status FIFO
sig_push_status <= sig_coelsc_reg_full;
-- Detect that a push of a new status word is completing
sig_status_push_ok <= sig_status_valid and
stat2wsc_status_ready;
sig_pop_coelsc_reg <= sig_status_push_ok;
-- Signal a halt to the execution pipe if new status
-- is valid but the Status FIFO is not accepting it or
-- the WDC Status FIFO is going full
wsc2mstr_halt_pipe <= (sig_status_valid and
not(stat2wsc_status_ready)) or
sig_wdc_status_going_full;
-- Monitor the Status capture registers to detect a
-- qualified Status set and push to the coelescing register
-- when available to do so
sig_push_coelsc_reg <= sig_valid_status_rdy and
sig_coelsc_reg_empty;
-- pre CR616212 sig_valid_status_rdy <= (sig_wresp_sfifo_rd_valid and
-- pre CR616212 sig_dcntl_sfifo_rd_valid) or
-- pre CR616212 (sig_data_err_reg and
-- pre CR616212 sig_dcntl_sfifo_rd_valid);
sig_valid_status_rdy <= (sig_wresp_sfifo_rd_valid and
sig_dcntl_sfifo_rd_valid) or
(sig_data_err_reg and
sig_dcntl_sfifo_rd_valid) or -- or Added for CR616212
(sig_data_last_err_reg and -- Added for CR616212
sig_dcntl_sfifo_rd_valid); -- Added for CR616212
-- Decode the AXI MMap Read Respose
sig_decerr <= '1'
When sig_bresp_reg = DECERR
Else '0';
sig_slverr <= '1'
When sig_bresp_reg = SLVERR
Else '0';
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_TAG_LE_STAT
--
-- If Generate Description:
-- Populates the TAG bits into the availble Status bits when
-- the TAG width is less than or equal to the available number
-- of bits in the Status word.
--
------------------------------------------------------------
GEN_TAG_LE_STAT : if (TAG_WIDTH <= STAT_REG_TAG_WIDTH) generate
-- local signals
signal lsig_temp_tag_small : std_logic_vector(STAT_REG_TAG_WIDTH-1 downto 0) := (others => '0');
begin
sig_tag2status <= lsig_temp_tag_small;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: POPULATE_SMALL_TAG
--
-- Process Description:
--
--
-------------------------------------------------------------
POPULATE_SMALL_TAG : process (sig_coelsc_tag_reg)
begin
-- Set default value
lsig_temp_tag_small <= (others => '0');
-- Now overload actual TAG bits
lsig_temp_tag_small(TAG_WIDTH-1 downto 0) <= sig_coelsc_tag_reg;
end process POPULATE_SMALL_TAG;
end generate GEN_TAG_LE_STAT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_TAG_GT_STAT
--
-- If Generate Description:
-- Populates the TAG bits into the availble Status bits when
-- the TAG width is greater than the available number of
-- bits in the Status word. The upper bits of the TAG are
-- clipped off (discarded).
--
------------------------------------------------------------
GEN_TAG_GT_STAT : if (TAG_WIDTH > STAT_REG_TAG_WIDTH) generate
-- local signals
signal lsig_temp_tag_big : std_logic_vector(STAT_REG_TAG_WIDTH-1 downto 0) := (others => '0');
begin
sig_tag2status <= lsig_temp_tag_big;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: POPULATE_BIG_TAG
--
-- Process Description:
--
--
-------------------------------------------------------------
POPULATE_SMALL_TAG : process (sig_coelsc_tag_reg)
begin
-- Set default value
lsig_temp_tag_big <= (others => '0');
-- Now overload actual TAG bits
lsig_temp_tag_big <= sig_coelsc_tag_reg(STAT_REG_TAG_WIDTH-1 downto 0);
end process POPULATE_SMALL_TAG;
end generate GEN_TAG_GT_STAT;
-------------------------------------------------------------------------
-- Write Response Channel input FIFO and logic
-- BRESP is the only fifo data
sig_wresp_sfifo_in <= s2mm_bresp;
-- The fifo output is already in the right format
sig_bresp_reg <= sig_wresp_sfifo_out;
-- Write Side assignments
sig_wresp_sfifo_wr_valid <= s2mm_bvalid;
sig_s2mm_bready <= sig_wresp_sfifo_wr_ready;
-- read Side ready assignment
sig_wresp_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_WRESP_STATUS_FIFO
--
-- Description:
-- Instance for the AXI Write Response FIFO
--
------------------------------------------------------------
I_WRESP_STATUS_FIFO : entity axi_datamover_v5_1_11.axi_datamover_fifo
generic map (
C_DWIDTH => WRESP_SFIFO_WIDTH ,
C_DEPTH => WRESP_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_wresp_sfifo_wr_valid ,
fifo_wr_tready => sig_wresp_sfifo_wr_ready ,
fifo_wr_tdata => sig_wresp_sfifo_in ,
fifo_wr_full => sig_wresp_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_wresp_sfifo_rd_valid ,
fifo_rd_tready => sig_wresp_sfifo_rd_ready ,
fifo_rd_tdata => sig_wresp_sfifo_out ,
fifo_rd_empty => sig_wresp_sfifo_rd_empty
);
-------- Write Data Controller Status FIFO Going Full Logic -------------
sig_incr_statcnt <= sig_dcntl_sfifo_wr_valid and
sig_dcntl_sfifo_wr_ready;
sig_decr_statcnt <= sig_dcntl_sfifo_rd_valid and
sig_dcntl_sfifo_rd_ready;
sig_statcnt_eq_max <= '1'
when (sig_wdc_statcnt = DCNTL_STATCNT_MAX)
Else '0';
sig_statcnt_eq_0 <= '1'
when (sig_wdc_statcnt = DCNTL_STATCNT_ZERO)
Else '0';
sig_statcnt_gt_eq_thres <= '1'
when (sig_wdc_statcnt >= DCNTL_HALT_THRES)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_WDC_GOING_FULL_FLOP
--
-- Process Description:
-- Implements a flop for the WDC Status FIFO going full flag.
--
-------------------------------------------------------------
IMP_WDC_GOING_FULL_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_wdc_status_going_full <= '0';
else
sig_wdc_status_going_full <= sig_statcnt_gt_eq_thres;
end if;
end if;
end process IMP_WDC_GOING_FULL_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DCNTL_FIFO_CNTR
--
-- Process Description:
-- Implements a simple counter keeping track of the number
-- of entries in the WDC Status FIFO. If the Status FIFO gets
-- too full, the S2MM Data Pipe has to be halted.
--
-------------------------------------------------------------
IMP_DCNTL_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_wdc_statcnt <= (others => '0');
elsif (sig_incr_statcnt = '1' and
sig_decr_statcnt = '0' and
sig_statcnt_eq_max = '0') then
sig_wdc_statcnt <= sig_wdc_statcnt + DCNTL_STATCNT_ONE;
elsif (sig_incr_statcnt = '0' and
sig_decr_statcnt = '1' and
sig_statcnt_eq_0 = '0') then
sig_wdc_statcnt <= sig_wdc_statcnt - DCNTL_STATCNT_ONE;
else
null; -- Hold current count value
end if;
end if;
end process IMP_DCNTL_FIFO_CNTR;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Implements the logic needed when Indeterminate BTT is
-- not enabled in the S2MM function.
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
-- Local Constants
Constant DCNTL_SFIFO_WIDTH : integer := STAT_REG_TAG_WIDTH+3;
Constant DCNTL_SFIFO_CMD_CMPLT_INDEX : integer := 0;
Constant DCNTL_SFIFO_TLAST_ERR_INDEX : integer := 1;
Constant DCNTL_SFIFO_CALC_ERR_INDEX : integer := 2;
Constant DCNTL_SFIFO_TAG_INDEX : integer := DCNTL_SFIFO_CALC_ERR_INDEX+1;
-- local signals
signal sig_dcntl_sfifo_in : std_logic_vector(DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_out : std_logic_vector(DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
begin
sig_wsc2stat_status <= sig_coelsc_okay_reg &
sig_coelsc_slverr_reg &
sig_coelsc_decerr_reg &
sig_coelsc_interr_reg &
sig_tag2status;
-----------------------------------------------------------------------------
-- Data Controller Status FIFO and Logic
-- Concatonate Input bits to build Dcntl fifo data word
sig_dcntl_sfifo_in <= data2wsc_tag & -- bit 3 to tag Width+2
data2wsc_calc_error & -- bit 2
data2wsc_last_error & -- bit 1
data2wsc_cmd_cmplt ; -- bit 0
-- Rip the DCntl fifo outputs back to constituant pieces
sig_data_tag_reg <= sig_dcntl_sfifo_out((DCNTL_SFIFO_TAG_INDEX+STAT_REG_TAG_WIDTH)-1 downto
DCNTL_SFIFO_TAG_INDEX);
sig_data_err_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_CALC_ERR_INDEX) ;
sig_data_last_err_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_TLAST_ERR_INDEX);
sig_data_cmd_cmplt_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_CMD_CMPLT_INDEX);
-- Data Control Valid/Ready assignments
sig_dcntl_sfifo_wr_valid <= data2wsc_valid ;
sig_wsc2data_ready <= sig_dcntl_sfifo_wr_ready;
-- read side ready assignment
sig_dcntl_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_DATA_CNTL_STATUS_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO
--
------------------------------------------------------------
I_DATA_CNTL_STATUS_FIFO : entity axi_datamover_v5_1_11.axi_datamover_fifo
generic map (
C_DWIDTH => DCNTL_SFIFO_WIDTH ,
C_DEPTH => DCNTL_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_dcntl_sfifo_wr_valid ,
fifo_wr_tready => sig_dcntl_sfifo_wr_ready ,
fifo_wr_tdata => sig_dcntl_sfifo_in ,
fifo_wr_full => sig_dcntl_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_dcntl_sfifo_rd_valid ,
fifo_rd_tready => sig_dcntl_sfifo_rd_ready ,
fifo_rd_tdata => sig_dcntl_sfifo_out ,
fifo_rd_empty => sig_dcntl_sfifo_rd_empty
);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: STATUS_COELESC_REG
--
-- Process Description:
-- Implement error status coelescing register.
-- Once a bit is set it will remain set until the overall
-- status is written to the Status FIFO.
-- Tag bits are just registered at each valid dbeat.
--
-------------------------------------------------------------
STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_pop_coelsc_reg = '1') then
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
sig_coelsc_reg_full <= '0';
sig_coelsc_reg_empty <= '1';
Elsif (sig_push_coelsc_reg = '1') Then
sig_coelsc_tag_reg <= sig_data_tag_reg;
sig_coelsc_interr_reg <= sig_data_err_reg or
sig_data_last_err_reg or
sig_coelsc_interr_reg;
sig_coelsc_decerr_reg <= not(sig_data_err_reg) and
(sig_decerr or
sig_coelsc_decerr_reg);
sig_coelsc_slverr_reg <= not(sig_data_err_reg) and
(sig_slverr or
sig_coelsc_slverr_reg);
sig_coelsc_okay_reg <= not(sig_decerr or
sig_coelsc_decerr_reg or
sig_slverr or
sig_coelsc_slverr_reg or
sig_data_err_reg or
sig_data_last_err_reg or
sig_coelsc_interr_reg
);
sig_coelsc_reg_full <= sig_data_cmd_cmplt_reg;
sig_coelsc_reg_empty <= not(sig_data_cmd_cmplt_reg);
else
null; -- hold current state
end if;
end if;
end process STATUS_COELESC_REG;
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ENABLE_INDET_BTT
--
-- If Generate Description:
-- Implements the logic needed when Indeterminate BTT is
-- enabled in the S2MM function. Primary difference is the
-- addition to the reported status of the End of Packet
-- marker (EOP) and the received byte count for the parent
-- command.
--
------------------------------------------------------------
GEN_ENABLE_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
-- Local Constants
Constant SF_DCNTL_SFIFO_WIDTH : integer := TAG_WIDTH +
C_SF_BYTES_RCVD_WIDTH + 3;
Constant SF_SFIFO_LS_TAG_INDEX : integer := 0;
Constant SF_SFIFO_MS_TAG_INDEX : integer := SF_SFIFO_LS_TAG_INDEX + (TAG_WIDTH-1);
Constant SF_SFIFO_CALC_ERR_INDEX : integer := SF_SFIFO_MS_TAG_INDEX+1;
Constant SF_SFIFO_CMD_CMPLT_INDEX : integer := SF_SFIFO_CALC_ERR_INDEX+1;
Constant SF_SFIFO_LS_BYTES_RCVD_INDEX : integer := SF_SFIFO_CMD_CMPLT_INDEX+1;
Constant SF_SFIFO_MS_BYTES_RCVD_INDEX : integer := SF_SFIFO_LS_BYTES_RCVD_INDEX+
(C_SF_BYTES_RCVD_WIDTH-1);
Constant SF_SFIFO_EOP_INDEX : integer := SF_SFIFO_MS_BYTES_RCVD_INDEX+1;
Constant BYTES_RCVD_FIELD_WIDTH : integer := 23;
-- local signals
signal sig_dcntl_sfifo_in : std_logic_vector(SF_DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_out : std_logic_vector(SF_DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_bytes_rcvd : std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_data_eop : std_logic := '0';
signal sig_coelsc_bytes_rcvd : std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_coelsc_eop : std_logic := '0';
signal sig_coelsc_bytes_rcvd_pad : std_logic_vector(BYTES_RCVD_FIELD_WIDTH-1 downto 0) := (others => '0');
begin
sig_wsc2stat_status <= sig_coelsc_eop &
sig_coelsc_bytes_rcvd_pad &
sig_coelsc_okay_reg &
sig_coelsc_slverr_reg &
sig_coelsc_decerr_reg &
sig_coelsc_interr_reg &
sig_tag2status;
-----------------------------------------------------------------------------
-- Data Controller Status FIFO and Logic
-- Concatonate Input bits to build Dcntl fifo input data word
sig_dcntl_sfifo_in <= data2wsc_eop & -- ms bit
data2wsc_bytes_rcvd & -- bit 7 to C_SF_BYTES_RCVD_WIDTH+7
data2wsc_cmd_cmplt & -- bit 6
data2wsc_calc_error & -- bit 4
data2wsc_tag; -- bits 0 to 3
-- Rip the DCntl fifo outputs back to constituant pieces
sig_data_eop <= sig_dcntl_sfifo_out(SF_SFIFO_EOP_INDEX);
sig_data_bytes_rcvd <= sig_dcntl_sfifo_out(SF_SFIFO_MS_BYTES_RCVD_INDEX downto
SF_SFIFO_LS_BYTES_RCVD_INDEX);
sig_data_cmd_cmplt_reg <= sig_dcntl_sfifo_out(SF_SFIFO_CMD_CMPLT_INDEX);
sig_data_err_reg <= sig_dcntl_sfifo_out(SF_SFIFO_CALC_ERR_INDEX);
sig_data_tag_reg <= sig_dcntl_sfifo_out(SF_SFIFO_MS_TAG_INDEX downto
SF_SFIFO_LS_TAG_INDEX) ;
-- Data Control Valid/Ready assignments
sig_dcntl_sfifo_wr_valid <= data2wsc_valid ;
sig_wsc2data_ready <= sig_dcntl_sfifo_wr_ready;
-- read side ready assignment
sig_dcntl_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_SF_DATA_CNTL_STATUS_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO when Store and
-- Forward is included.
--
------------------------------------------------------------
I_SF_DATA_CNTL_STATUS_FIFO : entity axi_datamover_v5_1_11.axi_datamover_fifo
generic map (
C_DWIDTH => SF_DCNTL_SFIFO_WIDTH ,
C_DEPTH => DCNTL_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_dcntl_sfifo_wr_valid ,
fifo_wr_tready => sig_dcntl_sfifo_wr_ready ,
fifo_wr_tdata => sig_dcntl_sfifo_in ,
fifo_wr_full => sig_dcntl_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_dcntl_sfifo_rd_valid ,
fifo_rd_tready => sig_dcntl_sfifo_rd_ready ,
fifo_rd_tdata => sig_dcntl_sfifo_out ,
fifo_rd_empty => sig_dcntl_sfifo_rd_empty
);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SF_STATUS_COELESC_REG
--
-- Process Description:
-- Implement error status coelescing register.
-- Once a bit is set it will remain set until the overall
-- status is written to the Status FIFO.
-- Tag bits are just registered at each valid dbeat.
--
-------------------------------------------------------------
SF_STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_pop_coelsc_reg = '1') then
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
sig_coelsc_bytes_rcvd <= (others => '0');
sig_coelsc_eop <= '0';
sig_coelsc_reg_full <= '0';
sig_coelsc_reg_empty <= '1';
Elsif (sig_push_coelsc_reg = '1') Then
sig_coelsc_tag_reg <= sig_data_tag_reg;
sig_coelsc_interr_reg <= sig_data_err_reg or
sig_coelsc_interr_reg;
sig_coelsc_decerr_reg <= not(sig_data_err_reg) and
(sig_decerr or
sig_coelsc_decerr_reg);
sig_coelsc_slverr_reg <= not(sig_data_err_reg) and
(sig_slverr or
sig_coelsc_slverr_reg);
sig_coelsc_okay_reg <= not(sig_decerr or
sig_coelsc_decerr_reg or
sig_slverr or
sig_coelsc_slverr_reg or
sig_data_err_reg or
sig_coelsc_interr_reg
);
sig_coelsc_bytes_rcvd <= sig_data_bytes_rcvd;
sig_coelsc_eop <= sig_data_eop;
sig_coelsc_reg_full <= sig_data_cmd_cmplt_reg;
sig_coelsc_reg_empty <= not(sig_data_cmd_cmplt_reg);
else
null; -- hold current state
end if;
end if;
end process SF_STATUS_COELESC_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: SF_GEN_PAD_BYTES_RCVD
--
-- If Generate Description:
-- Pad the bytes received value with zeros to fill in the
-- status field width.
--
--
------------------------------------------------------------
SF_GEN_PAD_BYTES_RCVD : if (C_SF_BYTES_RCVD_WIDTH < BYTES_RCVD_FIELD_WIDTH) generate
begin
sig_coelsc_bytes_rcvd_pad(BYTES_RCVD_FIELD_WIDTH-1 downto
C_SF_BYTES_RCVD_WIDTH) <= (others => '0');
sig_coelsc_bytes_rcvd_pad(C_SF_BYTES_RCVD_WIDTH-1 downto 0) <= sig_coelsc_bytes_rcvd;
end generate SF_GEN_PAD_BYTES_RCVD;
------------------------------------------------------------
-- If Generate
--
-- Label: SF_GEN_NO_PAD_BYTES_RCVD
--
-- If Generate Description:
-- No padding required for the bytes received value.
--
--
------------------------------------------------------------
SF_GEN_NO_PAD_BYTES_RCVD : if (C_SF_BYTES_RCVD_WIDTH = BYTES_RCVD_FIELD_WIDTH) generate
begin
sig_coelsc_bytes_rcvd_pad <= sig_coelsc_bytes_rcvd; -- no pad required
end generate SF_GEN_NO_PAD_BYTES_RCVD;
end generate GEN_ENABLE_INDET_BTT;
------- Soft Shutdown Logic -------------------------------
-- Address Posted Counter Logic ---------------------t-----------------
-- Supports soft shutdown by tracking when all commited Write
-- transfers to the AXI Bus have had corresponding Write Status
-- Reponses Received.
sig_addr_posted <= addr2wsc_addr_posted ;
sig_incr_addr_posted_cntr <= sig_addr_posted ;
sig_decr_addr_posted_cntr <= sig_s2mm_bready and
s2mm_bvalid ;
sig_addr_posted_cntr_eq_0 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ZERO)
Else '0';
sig_addr_posted_cntr_eq_1 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ONE)
Else '0';
sig_addr_posted_cntr_max <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_POSTED_FIFO_CNTR
--
-- Process Description:
-- This process implements a counter for the tracking
-- if an Address has been posted on the AXI address channel.
-- The counter is used to track flushing operations where all
-- transfers committed on the AXI Address Channel have to
-- be completed before a halt can occur.
-------------------------------------------------------------
IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_addr_posted_cntr <= ADDR_POSTED_ZERO;
elsif (sig_incr_addr_posted_cntr = '1' and
sig_decr_addr_posted_cntr = '0' and
sig_addr_posted_cntr_max = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ;
elsif (sig_incr_addr_posted_cntr = '0' and
sig_decr_addr_posted_cntr = '1' and
sig_addr_posted_cntr_eq_0 = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_POSTED_FIFO_CNTR;
wsc2rst_stop_cmplt <= sig_all_cmds_done;
sig_no_posted_cmds <= (sig_addr_posted_cntr_eq_0 and
not(addr2wsc_calc_error)) or
(sig_addr_posted_cntr_eq_1 and
addr2wsc_calc_error);
sig_all_cmds_done <= sig_no_posted_cmds and
sig_halt_reg_dly3;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG
--
-- Process Description:
-- Implements the flop for capturing the Halt request from
-- the Reset module.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg <= '0';
elsif (rst2wsc_stop_request = '1') then
sig_halt_reg <= '1';
else
null; -- Hold current State
end if;
end if;
end process IMP_HALT_REQ_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG_DLY
--
-- Process Description:
-- Implements the flops for delaying the halt request by 3
-- clocks to allow the Address Controller to halt before the
-- Data Contoller can safely indicate it has exhausted all
-- transfers committed to the AXI Address Channel by the Address
-- Controller.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG_DLY : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg_dly1 <= '0';
sig_halt_reg_dly2 <= '0';
sig_halt_reg_dly3 <= '0';
else
sig_halt_reg_dly1 <= sig_halt_reg;
sig_halt_reg_dly2 <= sig_halt_reg_dly1;
sig_halt_reg_dly3 <= sig_halt_reg_dly2;
end if;
end if;
end process IMP_HALT_REQ_REG_DLY;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_wr_status_cntl.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_wr_status_cntl.vhd
--
-- Description:
-- This file implements the DataMover Master Write Status Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_11;
use axi_datamover_v5_1_11.axi_datamover_fifo;
-------------------------------------------------------------------------------
entity axi_datamover_wr_status_cntl is
generic (
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if the Indeterminate BTT Module is enabled
-- for use (outside of this module)
C_SF_BYTES_RCVD_WIDTH : Integer range 1 to 23 := 1;
-- Sets the width of the data2wsc_bytes_rcvd port used for
-- relaying the actual number of bytes received when Idet BTT is
-- enabled (C_ENABLE_INDET_BTT = 1)
C_STS_FIFO_DEPTH : Integer range 1 to 32 := 8;
-- Specifies the depth of the internal status queue fifo
C_STS_WIDTH : Integer range 8 to 32 := 8;
-- sets the width of the Status ports
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the Status reply
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA device family
);
port (
-- Clock and Reset inputs ------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------------
-- Soft Shutdown Control interface --------------------------------
--
rst2wsc_stop_request : in std_logic; --
-- Active high soft stop request to modules --
--
wsc2rst_stop_cmplt : Out std_logic; --
-- Active high indication that the Write status Controller --
-- has completed any pending transfers committed by the --
-- Address Controller after a stop has been requested by --
-- the Reset module. --
--
addr2wsc_addr_posted : In std_logic ; --
-- Indication from the Address Channel Controller to the --
-- write Status Controller that an address has been posted --
-- to the AXI Address Channel --
--------------------------------------------------------------------
-- Write Response Channel Interface -------------------------------
--
s2mm_bresp : In std_logic_vector(1 downto 0); --
-- The Write response value --
--
s2mm_bvalid : In std_logic ; --
-- Indication from the Write Response Channel that a new --
-- write status input is valid --
--
s2mm_bready : out std_logic ; --
-- Indication to the Write Response Channel that the --
-- Status module is ready for a new status input --
--------------------------------------------------------------------
-- Command Calculator Interface -------------------------------------
--
calc2wsc_calc_error : in std_logic ; --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
---------------------------------------------------------------------
-- Address Controller Status ----------------------------------------
--
addr2wsc_calc_error : In std_logic ; --
-- Indication from the Address Channel Controller that it --
-- has encountered a calculation error from the command --
-- Calculator --
--
addr2wsc_fifo_empty : In std_logic ; --
-- Indication from the Address Controller FIFO that it --
-- is empty (no commands pending) --
---------------------------------------------------------------------
-- Data Controller Status ---------------------------------------------------------
--
data2wsc_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The command tag --
--
data2wsc_calc_error : In std_logic ; --
-- Indication from the Data Channel Controller FIFO that it --
-- has encountered a Calculation error in the command pipe --
--
data2wsc_last_error : In std_logic ; --
-- Indication from the Write Data Channel Controller that a --
-- premature TLAST assertion was encountered on the incoming --
-- Stream Channel --
--
data2wsc_cmd_cmplt : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- corresponding status is the final status for a parent --
-- command fetched from the command FIFO --
--
data2wsc_valid : In std_logic ; --
-- Indication from the Data Channel Controller FIFO that it --
-- has a new tag/error status to transfer --
--
wsc2data_ready : out std_logic ; --
-- Indication to the Data Channel Controller FIFO that the --
-- Status module is ready for a new tag/error status input --
--
--
data2wsc_eop : In std_logic; --
-- Input from the Write Data Controller indicating that the --
-- associated command status also corresponds to a End of Packet --
-- marker for the input Stream. This is only used when Store and --
-- Forward is enabled in the S2MM. --
--
data2wsc_bytes_rcvd : In std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0); --
-- Input from the Write Data Controller indicating the actual --
-- number of bytes received from the Stream input for the --
-- corresponding command status. This is only used when Store and --
-- Forward is enabled in the S2MM. --
------------------------------------------------------------------------------------
-- Command/Status Interface --------------------------------------------------------
--
wsc2stat_status : Out std_logic_vector(C_STS_WIDTH-1 downto 0); --
-- Read Status value collected during a Read Data transfer --
-- Output to the Command/Status Module --
--
stat2wsc_status_ready : In std_logic; --
-- Input from the Command/Status Module indicating that the --
-- Status Reg/FIFO is Full and cannot accept more staus writes --
--
wsc2stat_status_valid : Out std_logic ; --
-- Control Signal to Write the Status value to the Status --
-- Reg/FIFO --
------------------------------------------------------------------------------------
-- Address and Data Controller Pipe halt --------------------------------
--
wsc2mstr_halt_pipe : Out std_logic --
-- Indication to Halt the Data and Address Command pipeline due --
-- to the Status pipe getting full at some point --
-------------------------------------------------------------------------
);
end entity axi_datamover_wr_status_cntl;
architecture implementation of axi_datamover_wr_status_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_cnt_width
--
-- Function Description:
-- Sets a count width based on a fifo depth. A depth of 4 or less
-- is a special case which requires a minimum count width of 3 bits.
--
-------------------------------------------------------------------
function funct_set_cnt_width (fifo_depth : integer) return integer is
Variable temp_cnt_width : Integer := 4;
begin
if (fifo_depth <= 4) then
temp_cnt_width := 3;
elsif (fifo_depth <= 8) then
temp_cnt_width := 4;
elsif (fifo_depth <= 16) then
temp_cnt_width := 5;
elsif (fifo_depth <= 32) then
temp_cnt_width := 6;
else -- fifo depth <= 64
temp_cnt_width := 7;
end if;
Return (temp_cnt_width);
end function funct_set_cnt_width;
-- Constant Declarations --------------------------------------------
Constant OKAY : std_logic_vector(1 downto 0) := "00";
Constant EXOKAY : std_logic_vector(1 downto 0) := "01";
Constant SLVERR : std_logic_vector(1 downto 0) := "10";
Constant DECERR : std_logic_vector(1 downto 0) := "11";
Constant STAT_RSVD : std_logic_vector(3 downto 0) := "0000";
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant STAT_REG_TAG_WIDTH : integer := 4;
Constant SYNC_FIFO_SELECT : integer := 0;
Constant SRL_FIFO_TYPE : integer := 2;
Constant DCNTL_SFIFO_DEPTH : integer := C_STS_FIFO_DEPTH;
Constant DCNTL_STATCNT_WIDTH : integer := funct_set_cnt_width(C_STS_FIFO_DEPTH);-- bits
Constant DCNTL_HALT_THRES : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(DCNTL_SFIFO_DEPTH-2,DCNTL_STATCNT_WIDTH);
Constant DCNTL_STATCNT_ZERO : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := (others => '0');
Constant DCNTL_STATCNT_MAX : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(DCNTL_SFIFO_DEPTH,DCNTL_STATCNT_WIDTH);
Constant DCNTL_STATCNT_ONE : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, DCNTL_STATCNT_WIDTH);
Constant WRESP_WIDTH : integer := 2;
Constant WRESP_SFIFO_WIDTH : integer := WRESP_WIDTH;
Constant WRESP_SFIFO_DEPTH : integer := DCNTL_SFIFO_DEPTH;
Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_STS_FIFO_DEPTH);-- bits
Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '0');
Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH);
Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '1');
-- Signal Declarations --------------------------------------------
signal sig_valid_status_rdy : std_logic := '0';
signal sig_decerr : std_logic := '0';
signal sig_slverr : std_logic := '0';
signal sig_coelsc_okay_reg : std_logic := '0';
signal sig_coelsc_interr_reg : std_logic := '0';
signal sig_coelsc_decerr_reg : std_logic := '0';
signal sig_coelsc_slverr_reg : std_logic := '0';
signal sig_coelsc_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_coelsc_reg : std_logic := '0';
signal sig_push_coelsc_reg : std_logic := '0';
signal sig_coelsc_reg_empty : std_logic := '0';
signal sig_coelsc_reg_full : std_logic := '0';
signal sig_tag2status : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data_err_reg : std_logic := '0';
signal sig_data_last_err_reg : std_logic := '0';
signal sig_data_cmd_cmplt_reg : std_logic := '0';
signal sig_bresp_reg : std_logic_vector(1 downto 0) := (others => '0');
signal sig_push_status : std_logic := '0';
Signal sig_status_push_ok : std_logic := '0';
signal sig_status_valid : std_logic := '0';
signal sig_wsc2data_ready : std_logic := '0';
signal sig_s2mm_bready : std_logic := '0';
signal sig_wresp_sfifo_in : std_logic_vector(WRESP_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_wresp_sfifo_out : std_logic_vector(WRESP_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_wresp_sfifo_wr_valid : std_logic := '0';
signal sig_wresp_sfifo_wr_ready : std_logic := '0';
signal sig_wresp_sfifo_wr_full : std_logic := '0';
signal sig_wresp_sfifo_rd_valid : std_logic := '0';
signal sig_wresp_sfifo_rd_ready : std_logic := '0';
signal sig_wresp_sfifo_rd_empty : std_logic := '0';
signal sig_halt_reg : std_logic := '0';
signal sig_halt_reg_dly1 : std_logic := '0';
signal sig_halt_reg_dly2 : std_logic := '0';
signal sig_halt_reg_dly3 : std_logic := '0';
signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted_cntr_eq_0 : std_logic := '0';
signal sig_addr_posted_cntr_eq_1 : std_logic := '0';
signal sig_addr_posted_cntr_max : std_logic := '0';
signal sig_decr_addr_posted_cntr : std_logic := '0';
signal sig_incr_addr_posted_cntr : std_logic := '0';
signal sig_no_posted_cmds : std_logic := '0';
signal sig_addr_posted : std_logic := '0';
signal sig_all_cmds_done : std_logic := '0';
signal sig_wsc2stat_status : std_logic_vector(C_STS_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_wr_valid : std_logic := '0';
signal sig_dcntl_sfifo_wr_ready : std_logic := '0';
signal sig_dcntl_sfifo_wr_full : std_logic := '0';
signal sig_dcntl_sfifo_rd_valid : std_logic := '0';
signal sig_dcntl_sfifo_rd_ready : std_logic := '0';
signal sig_dcntl_sfifo_rd_empty : std_logic := '0';
signal sig_wdc_statcnt : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_statcnt : std_logic := '0';
signal sig_decr_statcnt : std_logic := '0';
signal sig_statcnt_eq_max : std_logic := '0';
signal sig_statcnt_eq_0 : std_logic := '0';
signal sig_statcnt_gt_eq_thres : std_logic := '0';
signal sig_wdc_status_going_full : std_logic := '0';
begin --(architecture implementation)
-- Assign the ready output to the AXI Write Response Channel
s2mm_bready <= sig_s2mm_bready or
sig_halt_reg; -- force bready if a Halt is requested
-- Assign the ready output to the Data Controller status interface
wsc2data_ready <= sig_wsc2data_ready;
-- Assign the status valid output control to the Status FIFO
wsc2stat_status_valid <= sig_status_valid ;
-- Formulate the status output value to the Status FIFO
wsc2stat_status <= sig_wsc2stat_status;
-- Formulate the status write request signal
sig_status_valid <= sig_push_status;
-- Indicate the desire to push a coelesced status word
-- to the Status FIFO
sig_push_status <= sig_coelsc_reg_full;
-- Detect that a push of a new status word is completing
sig_status_push_ok <= sig_status_valid and
stat2wsc_status_ready;
sig_pop_coelsc_reg <= sig_status_push_ok;
-- Signal a halt to the execution pipe if new status
-- is valid but the Status FIFO is not accepting it or
-- the WDC Status FIFO is going full
wsc2mstr_halt_pipe <= (sig_status_valid and
not(stat2wsc_status_ready)) or
sig_wdc_status_going_full;
-- Monitor the Status capture registers to detect a
-- qualified Status set and push to the coelescing register
-- when available to do so
sig_push_coelsc_reg <= sig_valid_status_rdy and
sig_coelsc_reg_empty;
-- pre CR616212 sig_valid_status_rdy <= (sig_wresp_sfifo_rd_valid and
-- pre CR616212 sig_dcntl_sfifo_rd_valid) or
-- pre CR616212 (sig_data_err_reg and
-- pre CR616212 sig_dcntl_sfifo_rd_valid);
sig_valid_status_rdy <= (sig_wresp_sfifo_rd_valid and
sig_dcntl_sfifo_rd_valid) or
(sig_data_err_reg and
sig_dcntl_sfifo_rd_valid) or -- or Added for CR616212
(sig_data_last_err_reg and -- Added for CR616212
sig_dcntl_sfifo_rd_valid); -- Added for CR616212
-- Decode the AXI MMap Read Respose
sig_decerr <= '1'
When sig_bresp_reg = DECERR
Else '0';
sig_slverr <= '1'
When sig_bresp_reg = SLVERR
Else '0';
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_TAG_LE_STAT
--
-- If Generate Description:
-- Populates the TAG bits into the availble Status bits when
-- the TAG width is less than or equal to the available number
-- of bits in the Status word.
--
------------------------------------------------------------
GEN_TAG_LE_STAT : if (TAG_WIDTH <= STAT_REG_TAG_WIDTH) generate
-- local signals
signal lsig_temp_tag_small : std_logic_vector(STAT_REG_TAG_WIDTH-1 downto 0) := (others => '0');
begin
sig_tag2status <= lsig_temp_tag_small;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: POPULATE_SMALL_TAG
--
-- Process Description:
--
--
-------------------------------------------------------------
POPULATE_SMALL_TAG : process (sig_coelsc_tag_reg)
begin
-- Set default value
lsig_temp_tag_small <= (others => '0');
-- Now overload actual TAG bits
lsig_temp_tag_small(TAG_WIDTH-1 downto 0) <= sig_coelsc_tag_reg;
end process POPULATE_SMALL_TAG;
end generate GEN_TAG_LE_STAT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_TAG_GT_STAT
--
-- If Generate Description:
-- Populates the TAG bits into the availble Status bits when
-- the TAG width is greater than the available number of
-- bits in the Status word. The upper bits of the TAG are
-- clipped off (discarded).
--
------------------------------------------------------------
GEN_TAG_GT_STAT : if (TAG_WIDTH > STAT_REG_TAG_WIDTH) generate
-- local signals
signal lsig_temp_tag_big : std_logic_vector(STAT_REG_TAG_WIDTH-1 downto 0) := (others => '0');
begin
sig_tag2status <= lsig_temp_tag_big;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: POPULATE_BIG_TAG
--
-- Process Description:
--
--
-------------------------------------------------------------
POPULATE_SMALL_TAG : process (sig_coelsc_tag_reg)
begin
-- Set default value
lsig_temp_tag_big <= (others => '0');
-- Now overload actual TAG bits
lsig_temp_tag_big <= sig_coelsc_tag_reg(STAT_REG_TAG_WIDTH-1 downto 0);
end process POPULATE_SMALL_TAG;
end generate GEN_TAG_GT_STAT;
-------------------------------------------------------------------------
-- Write Response Channel input FIFO and logic
-- BRESP is the only fifo data
sig_wresp_sfifo_in <= s2mm_bresp;
-- The fifo output is already in the right format
sig_bresp_reg <= sig_wresp_sfifo_out;
-- Write Side assignments
sig_wresp_sfifo_wr_valid <= s2mm_bvalid;
sig_s2mm_bready <= sig_wresp_sfifo_wr_ready;
-- read Side ready assignment
sig_wresp_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_WRESP_STATUS_FIFO
--
-- Description:
-- Instance for the AXI Write Response FIFO
--
------------------------------------------------------------
I_WRESP_STATUS_FIFO : entity axi_datamover_v5_1_11.axi_datamover_fifo
generic map (
C_DWIDTH => WRESP_SFIFO_WIDTH ,
C_DEPTH => WRESP_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_wresp_sfifo_wr_valid ,
fifo_wr_tready => sig_wresp_sfifo_wr_ready ,
fifo_wr_tdata => sig_wresp_sfifo_in ,
fifo_wr_full => sig_wresp_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_wresp_sfifo_rd_valid ,
fifo_rd_tready => sig_wresp_sfifo_rd_ready ,
fifo_rd_tdata => sig_wresp_sfifo_out ,
fifo_rd_empty => sig_wresp_sfifo_rd_empty
);
-------- Write Data Controller Status FIFO Going Full Logic -------------
sig_incr_statcnt <= sig_dcntl_sfifo_wr_valid and
sig_dcntl_sfifo_wr_ready;
sig_decr_statcnt <= sig_dcntl_sfifo_rd_valid and
sig_dcntl_sfifo_rd_ready;
sig_statcnt_eq_max <= '1'
when (sig_wdc_statcnt = DCNTL_STATCNT_MAX)
Else '0';
sig_statcnt_eq_0 <= '1'
when (sig_wdc_statcnt = DCNTL_STATCNT_ZERO)
Else '0';
sig_statcnt_gt_eq_thres <= '1'
when (sig_wdc_statcnt >= DCNTL_HALT_THRES)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_WDC_GOING_FULL_FLOP
--
-- Process Description:
-- Implements a flop for the WDC Status FIFO going full flag.
--
-------------------------------------------------------------
IMP_WDC_GOING_FULL_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_wdc_status_going_full <= '0';
else
sig_wdc_status_going_full <= sig_statcnt_gt_eq_thres;
end if;
end if;
end process IMP_WDC_GOING_FULL_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DCNTL_FIFO_CNTR
--
-- Process Description:
-- Implements a simple counter keeping track of the number
-- of entries in the WDC Status FIFO. If the Status FIFO gets
-- too full, the S2MM Data Pipe has to be halted.
--
-------------------------------------------------------------
IMP_DCNTL_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_wdc_statcnt <= (others => '0');
elsif (sig_incr_statcnt = '1' and
sig_decr_statcnt = '0' and
sig_statcnt_eq_max = '0') then
sig_wdc_statcnt <= sig_wdc_statcnt + DCNTL_STATCNT_ONE;
elsif (sig_incr_statcnt = '0' and
sig_decr_statcnt = '1' and
sig_statcnt_eq_0 = '0') then
sig_wdc_statcnt <= sig_wdc_statcnt - DCNTL_STATCNT_ONE;
else
null; -- Hold current count value
end if;
end if;
end process IMP_DCNTL_FIFO_CNTR;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Implements the logic needed when Indeterminate BTT is
-- not enabled in the S2MM function.
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
-- Local Constants
Constant DCNTL_SFIFO_WIDTH : integer := STAT_REG_TAG_WIDTH+3;
Constant DCNTL_SFIFO_CMD_CMPLT_INDEX : integer := 0;
Constant DCNTL_SFIFO_TLAST_ERR_INDEX : integer := 1;
Constant DCNTL_SFIFO_CALC_ERR_INDEX : integer := 2;
Constant DCNTL_SFIFO_TAG_INDEX : integer := DCNTL_SFIFO_CALC_ERR_INDEX+1;
-- local signals
signal sig_dcntl_sfifo_in : std_logic_vector(DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_out : std_logic_vector(DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
begin
sig_wsc2stat_status <= sig_coelsc_okay_reg &
sig_coelsc_slverr_reg &
sig_coelsc_decerr_reg &
sig_coelsc_interr_reg &
sig_tag2status;
-----------------------------------------------------------------------------
-- Data Controller Status FIFO and Logic
-- Concatonate Input bits to build Dcntl fifo data word
sig_dcntl_sfifo_in <= data2wsc_tag & -- bit 3 to tag Width+2
data2wsc_calc_error & -- bit 2
data2wsc_last_error & -- bit 1
data2wsc_cmd_cmplt ; -- bit 0
-- Rip the DCntl fifo outputs back to constituant pieces
sig_data_tag_reg <= sig_dcntl_sfifo_out((DCNTL_SFIFO_TAG_INDEX+STAT_REG_TAG_WIDTH)-1 downto
DCNTL_SFIFO_TAG_INDEX);
sig_data_err_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_CALC_ERR_INDEX) ;
sig_data_last_err_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_TLAST_ERR_INDEX);
sig_data_cmd_cmplt_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_CMD_CMPLT_INDEX);
-- Data Control Valid/Ready assignments
sig_dcntl_sfifo_wr_valid <= data2wsc_valid ;
sig_wsc2data_ready <= sig_dcntl_sfifo_wr_ready;
-- read side ready assignment
sig_dcntl_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_DATA_CNTL_STATUS_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO
--
------------------------------------------------------------
I_DATA_CNTL_STATUS_FIFO : entity axi_datamover_v5_1_11.axi_datamover_fifo
generic map (
C_DWIDTH => DCNTL_SFIFO_WIDTH ,
C_DEPTH => DCNTL_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_dcntl_sfifo_wr_valid ,
fifo_wr_tready => sig_dcntl_sfifo_wr_ready ,
fifo_wr_tdata => sig_dcntl_sfifo_in ,
fifo_wr_full => sig_dcntl_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_dcntl_sfifo_rd_valid ,
fifo_rd_tready => sig_dcntl_sfifo_rd_ready ,
fifo_rd_tdata => sig_dcntl_sfifo_out ,
fifo_rd_empty => sig_dcntl_sfifo_rd_empty
);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: STATUS_COELESC_REG
--
-- Process Description:
-- Implement error status coelescing register.
-- Once a bit is set it will remain set until the overall
-- status is written to the Status FIFO.
-- Tag bits are just registered at each valid dbeat.
--
-------------------------------------------------------------
STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_pop_coelsc_reg = '1') then
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
sig_coelsc_reg_full <= '0';
sig_coelsc_reg_empty <= '1';
Elsif (sig_push_coelsc_reg = '1') Then
sig_coelsc_tag_reg <= sig_data_tag_reg;
sig_coelsc_interr_reg <= sig_data_err_reg or
sig_data_last_err_reg or
sig_coelsc_interr_reg;
sig_coelsc_decerr_reg <= not(sig_data_err_reg) and
(sig_decerr or
sig_coelsc_decerr_reg);
sig_coelsc_slverr_reg <= not(sig_data_err_reg) and
(sig_slverr or
sig_coelsc_slverr_reg);
sig_coelsc_okay_reg <= not(sig_decerr or
sig_coelsc_decerr_reg or
sig_slverr or
sig_coelsc_slverr_reg or
sig_data_err_reg or
sig_data_last_err_reg or
sig_coelsc_interr_reg
);
sig_coelsc_reg_full <= sig_data_cmd_cmplt_reg;
sig_coelsc_reg_empty <= not(sig_data_cmd_cmplt_reg);
else
null; -- hold current state
end if;
end if;
end process STATUS_COELESC_REG;
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ENABLE_INDET_BTT
--
-- If Generate Description:
-- Implements the logic needed when Indeterminate BTT is
-- enabled in the S2MM function. Primary difference is the
-- addition to the reported status of the End of Packet
-- marker (EOP) and the received byte count for the parent
-- command.
--
------------------------------------------------------------
GEN_ENABLE_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
-- Local Constants
Constant SF_DCNTL_SFIFO_WIDTH : integer := TAG_WIDTH +
C_SF_BYTES_RCVD_WIDTH + 3;
Constant SF_SFIFO_LS_TAG_INDEX : integer := 0;
Constant SF_SFIFO_MS_TAG_INDEX : integer := SF_SFIFO_LS_TAG_INDEX + (TAG_WIDTH-1);
Constant SF_SFIFO_CALC_ERR_INDEX : integer := SF_SFIFO_MS_TAG_INDEX+1;
Constant SF_SFIFO_CMD_CMPLT_INDEX : integer := SF_SFIFO_CALC_ERR_INDEX+1;
Constant SF_SFIFO_LS_BYTES_RCVD_INDEX : integer := SF_SFIFO_CMD_CMPLT_INDEX+1;
Constant SF_SFIFO_MS_BYTES_RCVD_INDEX : integer := SF_SFIFO_LS_BYTES_RCVD_INDEX+
(C_SF_BYTES_RCVD_WIDTH-1);
Constant SF_SFIFO_EOP_INDEX : integer := SF_SFIFO_MS_BYTES_RCVD_INDEX+1;
Constant BYTES_RCVD_FIELD_WIDTH : integer := 23;
-- local signals
signal sig_dcntl_sfifo_in : std_logic_vector(SF_DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_out : std_logic_vector(SF_DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_bytes_rcvd : std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_data_eop : std_logic := '0';
signal sig_coelsc_bytes_rcvd : std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_coelsc_eop : std_logic := '0';
signal sig_coelsc_bytes_rcvd_pad : std_logic_vector(BYTES_RCVD_FIELD_WIDTH-1 downto 0) := (others => '0');
begin
sig_wsc2stat_status <= sig_coelsc_eop &
sig_coelsc_bytes_rcvd_pad &
sig_coelsc_okay_reg &
sig_coelsc_slverr_reg &
sig_coelsc_decerr_reg &
sig_coelsc_interr_reg &
sig_tag2status;
-----------------------------------------------------------------------------
-- Data Controller Status FIFO and Logic
-- Concatonate Input bits to build Dcntl fifo input data word
sig_dcntl_sfifo_in <= data2wsc_eop & -- ms bit
data2wsc_bytes_rcvd & -- bit 7 to C_SF_BYTES_RCVD_WIDTH+7
data2wsc_cmd_cmplt & -- bit 6
data2wsc_calc_error & -- bit 4
data2wsc_tag; -- bits 0 to 3
-- Rip the DCntl fifo outputs back to constituant pieces
sig_data_eop <= sig_dcntl_sfifo_out(SF_SFIFO_EOP_INDEX);
sig_data_bytes_rcvd <= sig_dcntl_sfifo_out(SF_SFIFO_MS_BYTES_RCVD_INDEX downto
SF_SFIFO_LS_BYTES_RCVD_INDEX);
sig_data_cmd_cmplt_reg <= sig_dcntl_sfifo_out(SF_SFIFO_CMD_CMPLT_INDEX);
sig_data_err_reg <= sig_dcntl_sfifo_out(SF_SFIFO_CALC_ERR_INDEX);
sig_data_tag_reg <= sig_dcntl_sfifo_out(SF_SFIFO_MS_TAG_INDEX downto
SF_SFIFO_LS_TAG_INDEX) ;
-- Data Control Valid/Ready assignments
sig_dcntl_sfifo_wr_valid <= data2wsc_valid ;
sig_wsc2data_ready <= sig_dcntl_sfifo_wr_ready;
-- read side ready assignment
sig_dcntl_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_SF_DATA_CNTL_STATUS_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO when Store and
-- Forward is included.
--
------------------------------------------------------------
I_SF_DATA_CNTL_STATUS_FIFO : entity axi_datamover_v5_1_11.axi_datamover_fifo
generic map (
C_DWIDTH => SF_DCNTL_SFIFO_WIDTH ,
C_DEPTH => DCNTL_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_dcntl_sfifo_wr_valid ,
fifo_wr_tready => sig_dcntl_sfifo_wr_ready ,
fifo_wr_tdata => sig_dcntl_sfifo_in ,
fifo_wr_full => sig_dcntl_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_dcntl_sfifo_rd_valid ,
fifo_rd_tready => sig_dcntl_sfifo_rd_ready ,
fifo_rd_tdata => sig_dcntl_sfifo_out ,
fifo_rd_empty => sig_dcntl_sfifo_rd_empty
);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SF_STATUS_COELESC_REG
--
-- Process Description:
-- Implement error status coelescing register.
-- Once a bit is set it will remain set until the overall
-- status is written to the Status FIFO.
-- Tag bits are just registered at each valid dbeat.
--
-------------------------------------------------------------
SF_STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_pop_coelsc_reg = '1') then
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
sig_coelsc_bytes_rcvd <= (others => '0');
sig_coelsc_eop <= '0';
sig_coelsc_reg_full <= '0';
sig_coelsc_reg_empty <= '1';
Elsif (sig_push_coelsc_reg = '1') Then
sig_coelsc_tag_reg <= sig_data_tag_reg;
sig_coelsc_interr_reg <= sig_data_err_reg or
sig_coelsc_interr_reg;
sig_coelsc_decerr_reg <= not(sig_data_err_reg) and
(sig_decerr or
sig_coelsc_decerr_reg);
sig_coelsc_slverr_reg <= not(sig_data_err_reg) and
(sig_slverr or
sig_coelsc_slverr_reg);
sig_coelsc_okay_reg <= not(sig_decerr or
sig_coelsc_decerr_reg or
sig_slverr or
sig_coelsc_slverr_reg or
sig_data_err_reg or
sig_coelsc_interr_reg
);
sig_coelsc_bytes_rcvd <= sig_data_bytes_rcvd;
sig_coelsc_eop <= sig_data_eop;
sig_coelsc_reg_full <= sig_data_cmd_cmplt_reg;
sig_coelsc_reg_empty <= not(sig_data_cmd_cmplt_reg);
else
null; -- hold current state
end if;
end if;
end process SF_STATUS_COELESC_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: SF_GEN_PAD_BYTES_RCVD
--
-- If Generate Description:
-- Pad the bytes received value with zeros to fill in the
-- status field width.
--
--
------------------------------------------------------------
SF_GEN_PAD_BYTES_RCVD : if (C_SF_BYTES_RCVD_WIDTH < BYTES_RCVD_FIELD_WIDTH) generate
begin
sig_coelsc_bytes_rcvd_pad(BYTES_RCVD_FIELD_WIDTH-1 downto
C_SF_BYTES_RCVD_WIDTH) <= (others => '0');
sig_coelsc_bytes_rcvd_pad(C_SF_BYTES_RCVD_WIDTH-1 downto 0) <= sig_coelsc_bytes_rcvd;
end generate SF_GEN_PAD_BYTES_RCVD;
------------------------------------------------------------
-- If Generate
--
-- Label: SF_GEN_NO_PAD_BYTES_RCVD
--
-- If Generate Description:
-- No padding required for the bytes received value.
--
--
------------------------------------------------------------
SF_GEN_NO_PAD_BYTES_RCVD : if (C_SF_BYTES_RCVD_WIDTH = BYTES_RCVD_FIELD_WIDTH) generate
begin
sig_coelsc_bytes_rcvd_pad <= sig_coelsc_bytes_rcvd; -- no pad required
end generate SF_GEN_NO_PAD_BYTES_RCVD;
end generate GEN_ENABLE_INDET_BTT;
------- Soft Shutdown Logic -------------------------------
-- Address Posted Counter Logic ---------------------t-----------------
-- Supports soft shutdown by tracking when all commited Write
-- transfers to the AXI Bus have had corresponding Write Status
-- Reponses Received.
sig_addr_posted <= addr2wsc_addr_posted ;
sig_incr_addr_posted_cntr <= sig_addr_posted ;
sig_decr_addr_posted_cntr <= sig_s2mm_bready and
s2mm_bvalid ;
sig_addr_posted_cntr_eq_0 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ZERO)
Else '0';
sig_addr_posted_cntr_eq_1 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ONE)
Else '0';
sig_addr_posted_cntr_max <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_POSTED_FIFO_CNTR
--
-- Process Description:
-- This process implements a counter for the tracking
-- if an Address has been posted on the AXI address channel.
-- The counter is used to track flushing operations where all
-- transfers committed on the AXI Address Channel have to
-- be completed before a halt can occur.
-------------------------------------------------------------
IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_addr_posted_cntr <= ADDR_POSTED_ZERO;
elsif (sig_incr_addr_posted_cntr = '1' and
sig_decr_addr_posted_cntr = '0' and
sig_addr_posted_cntr_max = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ;
elsif (sig_incr_addr_posted_cntr = '0' and
sig_decr_addr_posted_cntr = '1' and
sig_addr_posted_cntr_eq_0 = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_POSTED_FIFO_CNTR;
wsc2rst_stop_cmplt <= sig_all_cmds_done;
sig_no_posted_cmds <= (sig_addr_posted_cntr_eq_0 and
not(addr2wsc_calc_error)) or
(sig_addr_posted_cntr_eq_1 and
addr2wsc_calc_error);
sig_all_cmds_done <= sig_no_posted_cmds and
sig_halt_reg_dly3;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG
--
-- Process Description:
-- Implements the flop for capturing the Halt request from
-- the Reset module.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg <= '0';
elsif (rst2wsc_stop_request = '1') then
sig_halt_reg <= '1';
else
null; -- Hold current State
end if;
end if;
end process IMP_HALT_REQ_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG_DLY
--
-- Process Description:
-- Implements the flops for delaying the halt request by 3
-- clocks to allow the Address Controller to halt before the
-- Data Contoller can safely indicate it has exhausted all
-- transfers committed to the AXI Address Channel by the Address
-- Controller.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG_DLY : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg_dly1 <= '0';
sig_halt_reg_dly2 <= '0';
sig_halt_reg_dly3 <= '0';
else
sig_halt_reg_dly1 <= sig_halt_reg;
sig_halt_reg_dly2 <= sig_halt_reg_dly1;
sig_halt_reg_dly3 <= sig_halt_reg_dly2;
end if;
end if;
end process IMP_HALT_REQ_REG_DLY;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_wr_status_cntl.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_wr_status_cntl.vhd
--
-- Description:
-- This file implements the DataMover Master Write Status Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_11;
use axi_datamover_v5_1_11.axi_datamover_fifo;
-------------------------------------------------------------------------------
entity axi_datamover_wr_status_cntl is
generic (
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if the Indeterminate BTT Module is enabled
-- for use (outside of this module)
C_SF_BYTES_RCVD_WIDTH : Integer range 1 to 23 := 1;
-- Sets the width of the data2wsc_bytes_rcvd port used for
-- relaying the actual number of bytes received when Idet BTT is
-- enabled (C_ENABLE_INDET_BTT = 1)
C_STS_FIFO_DEPTH : Integer range 1 to 32 := 8;
-- Specifies the depth of the internal status queue fifo
C_STS_WIDTH : Integer range 8 to 32 := 8;
-- sets the width of the Status ports
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the Status reply
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA device family
);
port (
-- Clock and Reset inputs ------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------------
-- Soft Shutdown Control interface --------------------------------
--
rst2wsc_stop_request : in std_logic; --
-- Active high soft stop request to modules --
--
wsc2rst_stop_cmplt : Out std_logic; --
-- Active high indication that the Write status Controller --
-- has completed any pending transfers committed by the --
-- Address Controller after a stop has been requested by --
-- the Reset module. --
--
addr2wsc_addr_posted : In std_logic ; --
-- Indication from the Address Channel Controller to the --
-- write Status Controller that an address has been posted --
-- to the AXI Address Channel --
--------------------------------------------------------------------
-- Write Response Channel Interface -------------------------------
--
s2mm_bresp : In std_logic_vector(1 downto 0); --
-- The Write response value --
--
s2mm_bvalid : In std_logic ; --
-- Indication from the Write Response Channel that a new --
-- write status input is valid --
--
s2mm_bready : out std_logic ; --
-- Indication to the Write Response Channel that the --
-- Status module is ready for a new status input --
--------------------------------------------------------------------
-- Command Calculator Interface -------------------------------------
--
calc2wsc_calc_error : in std_logic ; --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
---------------------------------------------------------------------
-- Address Controller Status ----------------------------------------
--
addr2wsc_calc_error : In std_logic ; --
-- Indication from the Address Channel Controller that it --
-- has encountered a calculation error from the command --
-- Calculator --
--
addr2wsc_fifo_empty : In std_logic ; --
-- Indication from the Address Controller FIFO that it --
-- is empty (no commands pending) --
---------------------------------------------------------------------
-- Data Controller Status ---------------------------------------------------------
--
data2wsc_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The command tag --
--
data2wsc_calc_error : In std_logic ; --
-- Indication from the Data Channel Controller FIFO that it --
-- has encountered a Calculation error in the command pipe --
--
data2wsc_last_error : In std_logic ; --
-- Indication from the Write Data Channel Controller that a --
-- premature TLAST assertion was encountered on the incoming --
-- Stream Channel --
--
data2wsc_cmd_cmplt : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- corresponding status is the final status for a parent --
-- command fetched from the command FIFO --
--
data2wsc_valid : In std_logic ; --
-- Indication from the Data Channel Controller FIFO that it --
-- has a new tag/error status to transfer --
--
wsc2data_ready : out std_logic ; --
-- Indication to the Data Channel Controller FIFO that the --
-- Status module is ready for a new tag/error status input --
--
--
data2wsc_eop : In std_logic; --
-- Input from the Write Data Controller indicating that the --
-- associated command status also corresponds to a End of Packet --
-- marker for the input Stream. This is only used when Store and --
-- Forward is enabled in the S2MM. --
--
data2wsc_bytes_rcvd : In std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0); --
-- Input from the Write Data Controller indicating the actual --
-- number of bytes received from the Stream input for the --
-- corresponding command status. This is only used when Store and --
-- Forward is enabled in the S2MM. --
------------------------------------------------------------------------------------
-- Command/Status Interface --------------------------------------------------------
--
wsc2stat_status : Out std_logic_vector(C_STS_WIDTH-1 downto 0); --
-- Read Status value collected during a Read Data transfer --
-- Output to the Command/Status Module --
--
stat2wsc_status_ready : In std_logic; --
-- Input from the Command/Status Module indicating that the --
-- Status Reg/FIFO is Full and cannot accept more staus writes --
--
wsc2stat_status_valid : Out std_logic ; --
-- Control Signal to Write the Status value to the Status --
-- Reg/FIFO --
------------------------------------------------------------------------------------
-- Address and Data Controller Pipe halt --------------------------------
--
wsc2mstr_halt_pipe : Out std_logic --
-- Indication to Halt the Data and Address Command pipeline due --
-- to the Status pipe getting full at some point --
-------------------------------------------------------------------------
);
end entity axi_datamover_wr_status_cntl;
architecture implementation of axi_datamover_wr_status_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_cnt_width
--
-- Function Description:
-- Sets a count width based on a fifo depth. A depth of 4 or less
-- is a special case which requires a minimum count width of 3 bits.
--
-------------------------------------------------------------------
function funct_set_cnt_width (fifo_depth : integer) return integer is
Variable temp_cnt_width : Integer := 4;
begin
if (fifo_depth <= 4) then
temp_cnt_width := 3;
elsif (fifo_depth <= 8) then
temp_cnt_width := 4;
elsif (fifo_depth <= 16) then
temp_cnt_width := 5;
elsif (fifo_depth <= 32) then
temp_cnt_width := 6;
else -- fifo depth <= 64
temp_cnt_width := 7;
end if;
Return (temp_cnt_width);
end function funct_set_cnt_width;
-- Constant Declarations --------------------------------------------
Constant OKAY : std_logic_vector(1 downto 0) := "00";
Constant EXOKAY : std_logic_vector(1 downto 0) := "01";
Constant SLVERR : std_logic_vector(1 downto 0) := "10";
Constant DECERR : std_logic_vector(1 downto 0) := "11";
Constant STAT_RSVD : std_logic_vector(3 downto 0) := "0000";
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant STAT_REG_TAG_WIDTH : integer := 4;
Constant SYNC_FIFO_SELECT : integer := 0;
Constant SRL_FIFO_TYPE : integer := 2;
Constant DCNTL_SFIFO_DEPTH : integer := C_STS_FIFO_DEPTH;
Constant DCNTL_STATCNT_WIDTH : integer := funct_set_cnt_width(C_STS_FIFO_DEPTH);-- bits
Constant DCNTL_HALT_THRES : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(DCNTL_SFIFO_DEPTH-2,DCNTL_STATCNT_WIDTH);
Constant DCNTL_STATCNT_ZERO : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := (others => '0');
Constant DCNTL_STATCNT_MAX : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(DCNTL_SFIFO_DEPTH,DCNTL_STATCNT_WIDTH);
Constant DCNTL_STATCNT_ONE : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, DCNTL_STATCNT_WIDTH);
Constant WRESP_WIDTH : integer := 2;
Constant WRESP_SFIFO_WIDTH : integer := WRESP_WIDTH;
Constant WRESP_SFIFO_DEPTH : integer := DCNTL_SFIFO_DEPTH;
Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_STS_FIFO_DEPTH);-- bits
Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '0');
Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH);
Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '1');
-- Signal Declarations --------------------------------------------
signal sig_valid_status_rdy : std_logic := '0';
signal sig_decerr : std_logic := '0';
signal sig_slverr : std_logic := '0';
signal sig_coelsc_okay_reg : std_logic := '0';
signal sig_coelsc_interr_reg : std_logic := '0';
signal sig_coelsc_decerr_reg : std_logic := '0';
signal sig_coelsc_slverr_reg : std_logic := '0';
signal sig_coelsc_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_coelsc_reg : std_logic := '0';
signal sig_push_coelsc_reg : std_logic := '0';
signal sig_coelsc_reg_empty : std_logic := '0';
signal sig_coelsc_reg_full : std_logic := '0';
signal sig_tag2status : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data_err_reg : std_logic := '0';
signal sig_data_last_err_reg : std_logic := '0';
signal sig_data_cmd_cmplt_reg : std_logic := '0';
signal sig_bresp_reg : std_logic_vector(1 downto 0) := (others => '0');
signal sig_push_status : std_logic := '0';
Signal sig_status_push_ok : std_logic := '0';
signal sig_status_valid : std_logic := '0';
signal sig_wsc2data_ready : std_logic := '0';
signal sig_s2mm_bready : std_logic := '0';
signal sig_wresp_sfifo_in : std_logic_vector(WRESP_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_wresp_sfifo_out : std_logic_vector(WRESP_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_wresp_sfifo_wr_valid : std_logic := '0';
signal sig_wresp_sfifo_wr_ready : std_logic := '0';
signal sig_wresp_sfifo_wr_full : std_logic := '0';
signal sig_wresp_sfifo_rd_valid : std_logic := '0';
signal sig_wresp_sfifo_rd_ready : std_logic := '0';
signal sig_wresp_sfifo_rd_empty : std_logic := '0';
signal sig_halt_reg : std_logic := '0';
signal sig_halt_reg_dly1 : std_logic := '0';
signal sig_halt_reg_dly2 : std_logic := '0';
signal sig_halt_reg_dly3 : std_logic := '0';
signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted_cntr_eq_0 : std_logic := '0';
signal sig_addr_posted_cntr_eq_1 : std_logic := '0';
signal sig_addr_posted_cntr_max : std_logic := '0';
signal sig_decr_addr_posted_cntr : std_logic := '0';
signal sig_incr_addr_posted_cntr : std_logic := '0';
signal sig_no_posted_cmds : std_logic := '0';
signal sig_addr_posted : std_logic := '0';
signal sig_all_cmds_done : std_logic := '0';
signal sig_wsc2stat_status : std_logic_vector(C_STS_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_wr_valid : std_logic := '0';
signal sig_dcntl_sfifo_wr_ready : std_logic := '0';
signal sig_dcntl_sfifo_wr_full : std_logic := '0';
signal sig_dcntl_sfifo_rd_valid : std_logic := '0';
signal sig_dcntl_sfifo_rd_ready : std_logic := '0';
signal sig_dcntl_sfifo_rd_empty : std_logic := '0';
signal sig_wdc_statcnt : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_statcnt : std_logic := '0';
signal sig_decr_statcnt : std_logic := '0';
signal sig_statcnt_eq_max : std_logic := '0';
signal sig_statcnt_eq_0 : std_logic := '0';
signal sig_statcnt_gt_eq_thres : std_logic := '0';
signal sig_wdc_status_going_full : std_logic := '0';
begin --(architecture implementation)
-- Assign the ready output to the AXI Write Response Channel
s2mm_bready <= sig_s2mm_bready or
sig_halt_reg; -- force bready if a Halt is requested
-- Assign the ready output to the Data Controller status interface
wsc2data_ready <= sig_wsc2data_ready;
-- Assign the status valid output control to the Status FIFO
wsc2stat_status_valid <= sig_status_valid ;
-- Formulate the status output value to the Status FIFO
wsc2stat_status <= sig_wsc2stat_status;
-- Formulate the status write request signal
sig_status_valid <= sig_push_status;
-- Indicate the desire to push a coelesced status word
-- to the Status FIFO
sig_push_status <= sig_coelsc_reg_full;
-- Detect that a push of a new status word is completing
sig_status_push_ok <= sig_status_valid and
stat2wsc_status_ready;
sig_pop_coelsc_reg <= sig_status_push_ok;
-- Signal a halt to the execution pipe if new status
-- is valid but the Status FIFO is not accepting it or
-- the WDC Status FIFO is going full
wsc2mstr_halt_pipe <= (sig_status_valid and
not(stat2wsc_status_ready)) or
sig_wdc_status_going_full;
-- Monitor the Status capture registers to detect a
-- qualified Status set and push to the coelescing register
-- when available to do so
sig_push_coelsc_reg <= sig_valid_status_rdy and
sig_coelsc_reg_empty;
-- pre CR616212 sig_valid_status_rdy <= (sig_wresp_sfifo_rd_valid and
-- pre CR616212 sig_dcntl_sfifo_rd_valid) or
-- pre CR616212 (sig_data_err_reg and
-- pre CR616212 sig_dcntl_sfifo_rd_valid);
sig_valid_status_rdy <= (sig_wresp_sfifo_rd_valid and
sig_dcntl_sfifo_rd_valid) or
(sig_data_err_reg and
sig_dcntl_sfifo_rd_valid) or -- or Added for CR616212
(sig_data_last_err_reg and -- Added for CR616212
sig_dcntl_sfifo_rd_valid); -- Added for CR616212
-- Decode the AXI MMap Read Respose
sig_decerr <= '1'
When sig_bresp_reg = DECERR
Else '0';
sig_slverr <= '1'
When sig_bresp_reg = SLVERR
Else '0';
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_TAG_LE_STAT
--
-- If Generate Description:
-- Populates the TAG bits into the availble Status bits when
-- the TAG width is less than or equal to the available number
-- of bits in the Status word.
--
------------------------------------------------------------
GEN_TAG_LE_STAT : if (TAG_WIDTH <= STAT_REG_TAG_WIDTH) generate
-- local signals
signal lsig_temp_tag_small : std_logic_vector(STAT_REG_TAG_WIDTH-1 downto 0) := (others => '0');
begin
sig_tag2status <= lsig_temp_tag_small;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: POPULATE_SMALL_TAG
--
-- Process Description:
--
--
-------------------------------------------------------------
POPULATE_SMALL_TAG : process (sig_coelsc_tag_reg)
begin
-- Set default value
lsig_temp_tag_small <= (others => '0');
-- Now overload actual TAG bits
lsig_temp_tag_small(TAG_WIDTH-1 downto 0) <= sig_coelsc_tag_reg;
end process POPULATE_SMALL_TAG;
end generate GEN_TAG_LE_STAT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_TAG_GT_STAT
--
-- If Generate Description:
-- Populates the TAG bits into the availble Status bits when
-- the TAG width is greater than the available number of
-- bits in the Status word. The upper bits of the TAG are
-- clipped off (discarded).
--
------------------------------------------------------------
GEN_TAG_GT_STAT : if (TAG_WIDTH > STAT_REG_TAG_WIDTH) generate
-- local signals
signal lsig_temp_tag_big : std_logic_vector(STAT_REG_TAG_WIDTH-1 downto 0) := (others => '0');
begin
sig_tag2status <= lsig_temp_tag_big;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: POPULATE_BIG_TAG
--
-- Process Description:
--
--
-------------------------------------------------------------
POPULATE_SMALL_TAG : process (sig_coelsc_tag_reg)
begin
-- Set default value
lsig_temp_tag_big <= (others => '0');
-- Now overload actual TAG bits
lsig_temp_tag_big <= sig_coelsc_tag_reg(STAT_REG_TAG_WIDTH-1 downto 0);
end process POPULATE_SMALL_TAG;
end generate GEN_TAG_GT_STAT;
-------------------------------------------------------------------------
-- Write Response Channel input FIFO and logic
-- BRESP is the only fifo data
sig_wresp_sfifo_in <= s2mm_bresp;
-- The fifo output is already in the right format
sig_bresp_reg <= sig_wresp_sfifo_out;
-- Write Side assignments
sig_wresp_sfifo_wr_valid <= s2mm_bvalid;
sig_s2mm_bready <= sig_wresp_sfifo_wr_ready;
-- read Side ready assignment
sig_wresp_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_WRESP_STATUS_FIFO
--
-- Description:
-- Instance for the AXI Write Response FIFO
--
------------------------------------------------------------
I_WRESP_STATUS_FIFO : entity axi_datamover_v5_1_11.axi_datamover_fifo
generic map (
C_DWIDTH => WRESP_SFIFO_WIDTH ,
C_DEPTH => WRESP_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_wresp_sfifo_wr_valid ,
fifo_wr_tready => sig_wresp_sfifo_wr_ready ,
fifo_wr_tdata => sig_wresp_sfifo_in ,
fifo_wr_full => sig_wresp_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_wresp_sfifo_rd_valid ,
fifo_rd_tready => sig_wresp_sfifo_rd_ready ,
fifo_rd_tdata => sig_wresp_sfifo_out ,
fifo_rd_empty => sig_wresp_sfifo_rd_empty
);
-------- Write Data Controller Status FIFO Going Full Logic -------------
sig_incr_statcnt <= sig_dcntl_sfifo_wr_valid and
sig_dcntl_sfifo_wr_ready;
sig_decr_statcnt <= sig_dcntl_sfifo_rd_valid and
sig_dcntl_sfifo_rd_ready;
sig_statcnt_eq_max <= '1'
when (sig_wdc_statcnt = DCNTL_STATCNT_MAX)
Else '0';
sig_statcnt_eq_0 <= '1'
when (sig_wdc_statcnt = DCNTL_STATCNT_ZERO)
Else '0';
sig_statcnt_gt_eq_thres <= '1'
when (sig_wdc_statcnt >= DCNTL_HALT_THRES)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_WDC_GOING_FULL_FLOP
--
-- Process Description:
-- Implements a flop for the WDC Status FIFO going full flag.
--
-------------------------------------------------------------
IMP_WDC_GOING_FULL_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_wdc_status_going_full <= '0';
else
sig_wdc_status_going_full <= sig_statcnt_gt_eq_thres;
end if;
end if;
end process IMP_WDC_GOING_FULL_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DCNTL_FIFO_CNTR
--
-- Process Description:
-- Implements a simple counter keeping track of the number
-- of entries in the WDC Status FIFO. If the Status FIFO gets
-- too full, the S2MM Data Pipe has to be halted.
--
-------------------------------------------------------------
IMP_DCNTL_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_wdc_statcnt <= (others => '0');
elsif (sig_incr_statcnt = '1' and
sig_decr_statcnt = '0' and
sig_statcnt_eq_max = '0') then
sig_wdc_statcnt <= sig_wdc_statcnt + DCNTL_STATCNT_ONE;
elsif (sig_incr_statcnt = '0' and
sig_decr_statcnt = '1' and
sig_statcnt_eq_0 = '0') then
sig_wdc_statcnt <= sig_wdc_statcnt - DCNTL_STATCNT_ONE;
else
null; -- Hold current count value
end if;
end if;
end process IMP_DCNTL_FIFO_CNTR;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Implements the logic needed when Indeterminate BTT is
-- not enabled in the S2MM function.
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
-- Local Constants
Constant DCNTL_SFIFO_WIDTH : integer := STAT_REG_TAG_WIDTH+3;
Constant DCNTL_SFIFO_CMD_CMPLT_INDEX : integer := 0;
Constant DCNTL_SFIFO_TLAST_ERR_INDEX : integer := 1;
Constant DCNTL_SFIFO_CALC_ERR_INDEX : integer := 2;
Constant DCNTL_SFIFO_TAG_INDEX : integer := DCNTL_SFIFO_CALC_ERR_INDEX+1;
-- local signals
signal sig_dcntl_sfifo_in : std_logic_vector(DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_out : std_logic_vector(DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
begin
sig_wsc2stat_status <= sig_coelsc_okay_reg &
sig_coelsc_slverr_reg &
sig_coelsc_decerr_reg &
sig_coelsc_interr_reg &
sig_tag2status;
-----------------------------------------------------------------------------
-- Data Controller Status FIFO and Logic
-- Concatonate Input bits to build Dcntl fifo data word
sig_dcntl_sfifo_in <= data2wsc_tag & -- bit 3 to tag Width+2
data2wsc_calc_error & -- bit 2
data2wsc_last_error & -- bit 1
data2wsc_cmd_cmplt ; -- bit 0
-- Rip the DCntl fifo outputs back to constituant pieces
sig_data_tag_reg <= sig_dcntl_sfifo_out((DCNTL_SFIFO_TAG_INDEX+STAT_REG_TAG_WIDTH)-1 downto
DCNTL_SFIFO_TAG_INDEX);
sig_data_err_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_CALC_ERR_INDEX) ;
sig_data_last_err_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_TLAST_ERR_INDEX);
sig_data_cmd_cmplt_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_CMD_CMPLT_INDEX);
-- Data Control Valid/Ready assignments
sig_dcntl_sfifo_wr_valid <= data2wsc_valid ;
sig_wsc2data_ready <= sig_dcntl_sfifo_wr_ready;
-- read side ready assignment
sig_dcntl_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_DATA_CNTL_STATUS_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO
--
------------------------------------------------------------
I_DATA_CNTL_STATUS_FIFO : entity axi_datamover_v5_1_11.axi_datamover_fifo
generic map (
C_DWIDTH => DCNTL_SFIFO_WIDTH ,
C_DEPTH => DCNTL_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_dcntl_sfifo_wr_valid ,
fifo_wr_tready => sig_dcntl_sfifo_wr_ready ,
fifo_wr_tdata => sig_dcntl_sfifo_in ,
fifo_wr_full => sig_dcntl_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_dcntl_sfifo_rd_valid ,
fifo_rd_tready => sig_dcntl_sfifo_rd_ready ,
fifo_rd_tdata => sig_dcntl_sfifo_out ,
fifo_rd_empty => sig_dcntl_sfifo_rd_empty
);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: STATUS_COELESC_REG
--
-- Process Description:
-- Implement error status coelescing register.
-- Once a bit is set it will remain set until the overall
-- status is written to the Status FIFO.
-- Tag bits are just registered at each valid dbeat.
--
-------------------------------------------------------------
STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_pop_coelsc_reg = '1') then
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
sig_coelsc_reg_full <= '0';
sig_coelsc_reg_empty <= '1';
Elsif (sig_push_coelsc_reg = '1') Then
sig_coelsc_tag_reg <= sig_data_tag_reg;
sig_coelsc_interr_reg <= sig_data_err_reg or
sig_data_last_err_reg or
sig_coelsc_interr_reg;
sig_coelsc_decerr_reg <= not(sig_data_err_reg) and
(sig_decerr or
sig_coelsc_decerr_reg);
sig_coelsc_slverr_reg <= not(sig_data_err_reg) and
(sig_slverr or
sig_coelsc_slverr_reg);
sig_coelsc_okay_reg <= not(sig_decerr or
sig_coelsc_decerr_reg or
sig_slverr or
sig_coelsc_slverr_reg or
sig_data_err_reg or
sig_data_last_err_reg or
sig_coelsc_interr_reg
);
sig_coelsc_reg_full <= sig_data_cmd_cmplt_reg;
sig_coelsc_reg_empty <= not(sig_data_cmd_cmplt_reg);
else
null; -- hold current state
end if;
end if;
end process STATUS_COELESC_REG;
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ENABLE_INDET_BTT
--
-- If Generate Description:
-- Implements the logic needed when Indeterminate BTT is
-- enabled in the S2MM function. Primary difference is the
-- addition to the reported status of the End of Packet
-- marker (EOP) and the received byte count for the parent
-- command.
--
------------------------------------------------------------
GEN_ENABLE_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
-- Local Constants
Constant SF_DCNTL_SFIFO_WIDTH : integer := TAG_WIDTH +
C_SF_BYTES_RCVD_WIDTH + 3;
Constant SF_SFIFO_LS_TAG_INDEX : integer := 0;
Constant SF_SFIFO_MS_TAG_INDEX : integer := SF_SFIFO_LS_TAG_INDEX + (TAG_WIDTH-1);
Constant SF_SFIFO_CALC_ERR_INDEX : integer := SF_SFIFO_MS_TAG_INDEX+1;
Constant SF_SFIFO_CMD_CMPLT_INDEX : integer := SF_SFIFO_CALC_ERR_INDEX+1;
Constant SF_SFIFO_LS_BYTES_RCVD_INDEX : integer := SF_SFIFO_CMD_CMPLT_INDEX+1;
Constant SF_SFIFO_MS_BYTES_RCVD_INDEX : integer := SF_SFIFO_LS_BYTES_RCVD_INDEX+
(C_SF_BYTES_RCVD_WIDTH-1);
Constant SF_SFIFO_EOP_INDEX : integer := SF_SFIFO_MS_BYTES_RCVD_INDEX+1;
Constant BYTES_RCVD_FIELD_WIDTH : integer := 23;
-- local signals
signal sig_dcntl_sfifo_in : std_logic_vector(SF_DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_out : std_logic_vector(SF_DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_bytes_rcvd : std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_data_eop : std_logic := '0';
signal sig_coelsc_bytes_rcvd : std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_coelsc_eop : std_logic := '0';
signal sig_coelsc_bytes_rcvd_pad : std_logic_vector(BYTES_RCVD_FIELD_WIDTH-1 downto 0) := (others => '0');
begin
sig_wsc2stat_status <= sig_coelsc_eop &
sig_coelsc_bytes_rcvd_pad &
sig_coelsc_okay_reg &
sig_coelsc_slverr_reg &
sig_coelsc_decerr_reg &
sig_coelsc_interr_reg &
sig_tag2status;
-----------------------------------------------------------------------------
-- Data Controller Status FIFO and Logic
-- Concatonate Input bits to build Dcntl fifo input data word
sig_dcntl_sfifo_in <= data2wsc_eop & -- ms bit
data2wsc_bytes_rcvd & -- bit 7 to C_SF_BYTES_RCVD_WIDTH+7
data2wsc_cmd_cmplt & -- bit 6
data2wsc_calc_error & -- bit 4
data2wsc_tag; -- bits 0 to 3
-- Rip the DCntl fifo outputs back to constituant pieces
sig_data_eop <= sig_dcntl_sfifo_out(SF_SFIFO_EOP_INDEX);
sig_data_bytes_rcvd <= sig_dcntl_sfifo_out(SF_SFIFO_MS_BYTES_RCVD_INDEX downto
SF_SFIFO_LS_BYTES_RCVD_INDEX);
sig_data_cmd_cmplt_reg <= sig_dcntl_sfifo_out(SF_SFIFO_CMD_CMPLT_INDEX);
sig_data_err_reg <= sig_dcntl_sfifo_out(SF_SFIFO_CALC_ERR_INDEX);
sig_data_tag_reg <= sig_dcntl_sfifo_out(SF_SFIFO_MS_TAG_INDEX downto
SF_SFIFO_LS_TAG_INDEX) ;
-- Data Control Valid/Ready assignments
sig_dcntl_sfifo_wr_valid <= data2wsc_valid ;
sig_wsc2data_ready <= sig_dcntl_sfifo_wr_ready;
-- read side ready assignment
sig_dcntl_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_SF_DATA_CNTL_STATUS_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO when Store and
-- Forward is included.
--
------------------------------------------------------------
I_SF_DATA_CNTL_STATUS_FIFO : entity axi_datamover_v5_1_11.axi_datamover_fifo
generic map (
C_DWIDTH => SF_DCNTL_SFIFO_WIDTH ,
C_DEPTH => DCNTL_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_dcntl_sfifo_wr_valid ,
fifo_wr_tready => sig_dcntl_sfifo_wr_ready ,
fifo_wr_tdata => sig_dcntl_sfifo_in ,
fifo_wr_full => sig_dcntl_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_dcntl_sfifo_rd_valid ,
fifo_rd_tready => sig_dcntl_sfifo_rd_ready ,
fifo_rd_tdata => sig_dcntl_sfifo_out ,
fifo_rd_empty => sig_dcntl_sfifo_rd_empty
);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SF_STATUS_COELESC_REG
--
-- Process Description:
-- Implement error status coelescing register.
-- Once a bit is set it will remain set until the overall
-- status is written to the Status FIFO.
-- Tag bits are just registered at each valid dbeat.
--
-------------------------------------------------------------
SF_STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_pop_coelsc_reg = '1') then
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
sig_coelsc_bytes_rcvd <= (others => '0');
sig_coelsc_eop <= '0';
sig_coelsc_reg_full <= '0';
sig_coelsc_reg_empty <= '1';
Elsif (sig_push_coelsc_reg = '1') Then
sig_coelsc_tag_reg <= sig_data_tag_reg;
sig_coelsc_interr_reg <= sig_data_err_reg or
sig_coelsc_interr_reg;
sig_coelsc_decerr_reg <= not(sig_data_err_reg) and
(sig_decerr or
sig_coelsc_decerr_reg);
sig_coelsc_slverr_reg <= not(sig_data_err_reg) and
(sig_slverr or
sig_coelsc_slverr_reg);
sig_coelsc_okay_reg <= not(sig_decerr or
sig_coelsc_decerr_reg or
sig_slverr or
sig_coelsc_slverr_reg or
sig_data_err_reg or
sig_coelsc_interr_reg
);
sig_coelsc_bytes_rcvd <= sig_data_bytes_rcvd;
sig_coelsc_eop <= sig_data_eop;
sig_coelsc_reg_full <= sig_data_cmd_cmplt_reg;
sig_coelsc_reg_empty <= not(sig_data_cmd_cmplt_reg);
else
null; -- hold current state
end if;
end if;
end process SF_STATUS_COELESC_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: SF_GEN_PAD_BYTES_RCVD
--
-- If Generate Description:
-- Pad the bytes received value with zeros to fill in the
-- status field width.
--
--
------------------------------------------------------------
SF_GEN_PAD_BYTES_RCVD : if (C_SF_BYTES_RCVD_WIDTH < BYTES_RCVD_FIELD_WIDTH) generate
begin
sig_coelsc_bytes_rcvd_pad(BYTES_RCVD_FIELD_WIDTH-1 downto
C_SF_BYTES_RCVD_WIDTH) <= (others => '0');
sig_coelsc_bytes_rcvd_pad(C_SF_BYTES_RCVD_WIDTH-1 downto 0) <= sig_coelsc_bytes_rcvd;
end generate SF_GEN_PAD_BYTES_RCVD;
------------------------------------------------------------
-- If Generate
--
-- Label: SF_GEN_NO_PAD_BYTES_RCVD
--
-- If Generate Description:
-- No padding required for the bytes received value.
--
--
------------------------------------------------------------
SF_GEN_NO_PAD_BYTES_RCVD : if (C_SF_BYTES_RCVD_WIDTH = BYTES_RCVD_FIELD_WIDTH) generate
begin
sig_coelsc_bytes_rcvd_pad <= sig_coelsc_bytes_rcvd; -- no pad required
end generate SF_GEN_NO_PAD_BYTES_RCVD;
end generate GEN_ENABLE_INDET_BTT;
------- Soft Shutdown Logic -------------------------------
-- Address Posted Counter Logic ---------------------t-----------------
-- Supports soft shutdown by tracking when all commited Write
-- transfers to the AXI Bus have had corresponding Write Status
-- Reponses Received.
sig_addr_posted <= addr2wsc_addr_posted ;
sig_incr_addr_posted_cntr <= sig_addr_posted ;
sig_decr_addr_posted_cntr <= sig_s2mm_bready and
s2mm_bvalid ;
sig_addr_posted_cntr_eq_0 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ZERO)
Else '0';
sig_addr_posted_cntr_eq_1 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ONE)
Else '0';
sig_addr_posted_cntr_max <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_POSTED_FIFO_CNTR
--
-- Process Description:
-- This process implements a counter for the tracking
-- if an Address has been posted on the AXI address channel.
-- The counter is used to track flushing operations where all
-- transfers committed on the AXI Address Channel have to
-- be completed before a halt can occur.
-------------------------------------------------------------
IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_addr_posted_cntr <= ADDR_POSTED_ZERO;
elsif (sig_incr_addr_posted_cntr = '1' and
sig_decr_addr_posted_cntr = '0' and
sig_addr_posted_cntr_max = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ;
elsif (sig_incr_addr_posted_cntr = '0' and
sig_decr_addr_posted_cntr = '1' and
sig_addr_posted_cntr_eq_0 = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_POSTED_FIFO_CNTR;
wsc2rst_stop_cmplt <= sig_all_cmds_done;
sig_no_posted_cmds <= (sig_addr_posted_cntr_eq_0 and
not(addr2wsc_calc_error)) or
(sig_addr_posted_cntr_eq_1 and
addr2wsc_calc_error);
sig_all_cmds_done <= sig_no_posted_cmds and
sig_halt_reg_dly3;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG
--
-- Process Description:
-- Implements the flop for capturing the Halt request from
-- the Reset module.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg <= '0';
elsif (rst2wsc_stop_request = '1') then
sig_halt_reg <= '1';
else
null; -- Hold current State
end if;
end if;
end process IMP_HALT_REQ_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG_DLY
--
-- Process Description:
-- Implements the flops for delaying the halt request by 3
-- clocks to allow the Address Controller to halt before the
-- Data Contoller can safely indicate it has exhausted all
-- transfers committed to the AXI Address Channel by the Address
-- Controller.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG_DLY : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg_dly1 <= '0';
sig_halt_reg_dly2 <= '0';
sig_halt_reg_dly3 <= '0';
else
sig_halt_reg_dly1 <= sig_halt_reg;
sig_halt_reg_dly2 <= sig_halt_reg_dly1;
sig_halt_reg_dly3 <= sig_halt_reg_dly2;
end if;
end if;
end process IMP_HALT_REQ_REG_DLY;
end implementation;
|
-------------------------------------------------------------------------------
-- Title : Testbench for CORDIC module
-- Project :
-------------------------------------------------------------------------------
-- File : cordic_bench.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2014-03-21
-- Last update: 2014-03-31
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-03-21 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library std;
use std.textio.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity cordic_bench is
end entity cordic_bench;
architecture test of cordic_bench is
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
constant c_input_freq : real := 100.0e6;
constant c_clock_period : time := 1.0 sec /(2.0*c_input_freq);
constant c_cycles_to_reset : natural := 4;
signal clock : std_logic := '0';
signal rst_n : std_logic := '0';
constant c_width : natural := 24;
signal I_in : std_logic_vector(c_width-1 downto 0) := (others => '0');
signal Q_in : std_logic_vector(c_width-1 downto 0) := (others => '0');
signal mag_in : std_logic_vector(c_width-1 downto 0) := (others => '0');
signal phase_in : std_logic_vector(c_width-1 downto 0) := (others => '0');
signal I_out : std_logic_vector(c_width-1 downto 0);
signal Q_out : std_logic_vector(c_width-1 downto 0);
signal mag_out : std_logic_vector(c_width-1 downto 0);
signal phase_out : std_logic_vector(c_width-1 downto 0);
signal endoffile : std_logic := '0';
constant cordic_delay : natural := 27;
component cordic is
generic (
g_width : natural;
g_mode : string);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
I_i : in std_logic_vector(g_width-1 downto 0) := (others => '0');
Q_i : in std_logic_vector(g_width-1 downto 0) := (others => '0');
mag_i : in std_logic_vector(g_width-1 downto 0) := (others => '0');
phase_i : in std_logic_vector(g_width-1 downto 0) := (others => '0');
I_o : out std_logic_vector(g_width-1 downto 0);
Q_o : out std_logic_vector(g_width-1 downto 0);
mag_o : out std_logic_vector(g_width-1 downto 0);
phase_o : out std_logic_vector(g_width-1 downto 0));
end component cordic;
begin
clk_gen : process
begin
clock <= '0';
wait for c_clock_period;
clock <= '1';
wait for c_clock_period;
end process;
rst_gen : process(clock)
variable clock_count : natural := c_cycles_to_reset;
begin
if rising_edge(clock) and clock_count /= 0 then
clock_count := clock_count - 1;
if clock_count = 0 then
rst_n <= '1';
end if;
end if;
end process;
sample_read : process(clock)
file vect_file : text open read_mode is "vectoring_in.dat";
file rotate_file : text open read_mode is "rotating_in.dat";
variable cur_line : line;
variable datain1, datain2 : real;
begin
if rising_edge(clock) then
--Pick samples for vectoring mode
if not endfile(vect_file) then
readline(vect_file, cur_line);
read(cur_line, datain1);
I_in <= std_logic_vector(to_signed(integer(datain1*(2.0**(c_width-1))), c_width));
read(cur_line, datain2);
Q_in <= std_logic_vector(to_signed(integer(datain2*(2.0**(c_width-1))), c_width));
else
endoffile <= '1';
end if;
-- pick samples for rotation mode
if not endfile(rotate_file) then
readline(rotate_file, cur_line);
read(cur_line, datain1);
mag_in <= std_logic_vector(to_signed(integer(datain1*(2.0**(c_width-1))), c_width));
read(cur_line, datain2);
phase_in <= std_logic_vector(to_signed(integer(datain2*(2.0**(c_width-1))), c_width));
else
endoffile <= '1';
end if;
end if;
end process sample_read;
uut1 : cordic
generic map (
g_width => c_width,
g_mode => "rect_to_polar")
port map (
clk_i => clock,
rst_n_i => rst_n,
I_i => I_in,
Q_i => Q_in,
mag_o => mag_out,
phase_o => phase_out);
uut2 : cordic
generic map (
g_width => c_width,
g_mode => "polar_to_rect")
port map (
clk_i => clock,
rst_n_i => rst_n,
mag_i => mag_in,
phase_i => phase_in,
I_o => I_out,
Q_o => Q_out);
signal_write : process(clock)
file vect_file : text open write_mode is "vectoring_out.dat";
file rotate_file : text open write_mode is "rotating_out.dat";
variable cur_line : line;
variable mag, phase : integer;
variable I, Q : integer;
-- variable counter : natural = cordic_delay;
begin
if rising_edge(clock) then
if(endoffile = '0') then
mag := to_integer(unsigned(mag_out));
write(cur_line, mag);
write(cur_line, string'(" "));
phase := to_integer(signed(phase_out));
write(cur_line, phase);
writeline(vect_file, cur_line);
I := to_integer(signed(I_out));
write(cur_line, I);
write(cur_line, string'(" "));
Q := to_integer(signed(Q_out));
write(cur_line, Q);
writeline(rotate_file, cur_line);
else
assert (false) report "Input file finished." severity failure;
end if;
end if;
end process signal_write;
end architecture test;
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
--
-- Title : DCT
-- Design : MDCT Core
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : ROME.VHD
-- Created : Sat Mar 5 7:37 2006
--
--------------------------------------------------------------------------------
--
-- Description : ROM for DCT matrix constant cosine coefficients (even part)
--
--------------------------------------------------------------------------------
-- 5:0
-- 5:4 = select matrix row (1 out of 4)
-- 3:0 = select precomputed MAC ( 1 out of 16)
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_arith.all;
use WORK.MDCT_PKG.all;
entity ROME is
port(
addr : in STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
clk : in STD_LOGIC;
datao : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0)
);
end ROME;
architecture RTL of ROME is
type ROM_TYPE is array (0 to (2**ROMADDR_W)-1)
of STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
constant rom : ROM_TYPE :=
(
(others => '0'),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP+AP+AP,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( BM,ROMDATA_W ),
conv_std_logic_vector( CM,ROMDATA_W ),
conv_std_logic_vector( CM+BM,ROMDATA_W ),
conv_std_logic_vector( CP,ROMDATA_W ),
conv_std_logic_vector( CP+BM,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( BM,ROMDATA_W ),
conv_std_logic_vector( BP,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( BP+CM,ROMDATA_W ),
conv_std_logic_vector( CM,ROMDATA_W ),
conv_std_logic_vector( BP+CP,ROMDATA_W ),
conv_std_logic_vector( CP,ROMDATA_W ),
conv_std_logic_vector( BP,ROMDATA_W ),
(others => '0'),
(others => '0'),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AM,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( AM,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( AM+AM,ROMDATA_W ),
conv_std_logic_vector( AM,ROMDATA_W ),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( AP,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AM,ROMDATA_W ),
(others => '0'),
(others => '0'),
conv_std_logic_vector( CM,ROMDATA_W ),
conv_std_logic_vector( BP,ROMDATA_W ),
conv_std_logic_vector( BP+CM,ROMDATA_W ),
conv_std_logic_vector( BM,ROMDATA_W ),
conv_std_logic_vector( BM+CM,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( CM,ROMDATA_W ),
conv_std_logic_vector( CP,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( CP+BP,ROMDATA_W ),
conv_std_logic_vector( BP,ROMDATA_W ),
conv_std_logic_vector( CP+BM,ROMDATA_W ),
conv_std_logic_vector( BM,ROMDATA_W ),
conv_std_logic_vector( CP,ROMDATA_W ),
(others => '0')
);
begin
process(clk)
begin
if clk = '1' and clk'event then
datao <= rom(CONV_INTEGER(UNSIGNED(addr)) );
end if;
end process;
end RTL;
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
--
-- Title : DCT
-- Design : MDCT Core
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : ROME.VHD
-- Created : Sat Mar 5 7:37 2006
--
--------------------------------------------------------------------------------
--
-- Description : ROM for DCT matrix constant cosine coefficients (even part)
--
--------------------------------------------------------------------------------
-- 5:0
-- 5:4 = select matrix row (1 out of 4)
-- 3:0 = select precomputed MAC ( 1 out of 16)
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_arith.all;
use WORK.MDCT_PKG.all;
entity ROME is
port(
addr : in STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
clk : in STD_LOGIC;
datao : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0)
);
end ROME;
architecture RTL of ROME is
type ROM_TYPE is array (0 to (2**ROMADDR_W)-1)
of STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
constant rom : ROM_TYPE :=
(
(others => '0'),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP+AP+AP,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( BM,ROMDATA_W ),
conv_std_logic_vector( CM,ROMDATA_W ),
conv_std_logic_vector( CM+BM,ROMDATA_W ),
conv_std_logic_vector( CP,ROMDATA_W ),
conv_std_logic_vector( CP+BM,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( BM,ROMDATA_W ),
conv_std_logic_vector( BP,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( BP+CM,ROMDATA_W ),
conv_std_logic_vector( CM,ROMDATA_W ),
conv_std_logic_vector( BP+CP,ROMDATA_W ),
conv_std_logic_vector( CP,ROMDATA_W ),
conv_std_logic_vector( BP,ROMDATA_W ),
(others => '0'),
(others => '0'),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AM,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( AM,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( AM+AM,ROMDATA_W ),
conv_std_logic_vector( AM,ROMDATA_W ),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( AP,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AM,ROMDATA_W ),
(others => '0'),
(others => '0'),
conv_std_logic_vector( CM,ROMDATA_W ),
conv_std_logic_vector( BP,ROMDATA_W ),
conv_std_logic_vector( BP+CM,ROMDATA_W ),
conv_std_logic_vector( BM,ROMDATA_W ),
conv_std_logic_vector( BM+CM,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( CM,ROMDATA_W ),
conv_std_logic_vector( CP,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( CP+BP,ROMDATA_W ),
conv_std_logic_vector( BP,ROMDATA_W ),
conv_std_logic_vector( CP+BM,ROMDATA_W ),
conv_std_logic_vector( BM,ROMDATA_W ),
conv_std_logic_vector( CP,ROMDATA_W ),
(others => '0')
);
begin
process(clk)
begin
if clk = '1' and clk'event then
datao <= rom(CONV_INTEGER(UNSIGNED(addr)) );
end if;
end process;
end RTL;
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
--
-- Title : DCT
-- Design : MDCT Core
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : ROME.VHD
-- Created : Sat Mar 5 7:37 2006
--
--------------------------------------------------------------------------------
--
-- Description : ROM for DCT matrix constant cosine coefficients (even part)
--
--------------------------------------------------------------------------------
-- 5:0
-- 5:4 = select matrix row (1 out of 4)
-- 3:0 = select precomputed MAC ( 1 out of 16)
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_arith.all;
use WORK.MDCT_PKG.all;
entity ROME is
port(
addr : in STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
clk : in STD_LOGIC;
datao : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0)
);
end ROME;
architecture RTL of ROME is
type ROM_TYPE is array (0 to (2**ROMADDR_W)-1)
of STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
constant rom : ROM_TYPE :=
(
(others => '0'),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP+AP+AP,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( BM,ROMDATA_W ),
conv_std_logic_vector( CM,ROMDATA_W ),
conv_std_logic_vector( CM+BM,ROMDATA_W ),
conv_std_logic_vector( CP,ROMDATA_W ),
conv_std_logic_vector( CP+BM,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( BM,ROMDATA_W ),
conv_std_logic_vector( BP,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( BP+CM,ROMDATA_W ),
conv_std_logic_vector( CM,ROMDATA_W ),
conv_std_logic_vector( BP+CP,ROMDATA_W ),
conv_std_logic_vector( CP,ROMDATA_W ),
conv_std_logic_vector( BP,ROMDATA_W ),
(others => '0'),
(others => '0'),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AM,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( AM,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( AM+AM,ROMDATA_W ),
conv_std_logic_vector( AM,ROMDATA_W ),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( AP,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AM,ROMDATA_W ),
(others => '0'),
(others => '0'),
conv_std_logic_vector( CM,ROMDATA_W ),
conv_std_logic_vector( BP,ROMDATA_W ),
conv_std_logic_vector( BP+CM,ROMDATA_W ),
conv_std_logic_vector( BM,ROMDATA_W ),
conv_std_logic_vector( BM+CM,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( CM,ROMDATA_W ),
conv_std_logic_vector( CP,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( CP+BP,ROMDATA_W ),
conv_std_logic_vector( BP,ROMDATA_W ),
conv_std_logic_vector( CP+BM,ROMDATA_W ),
conv_std_logic_vector( BM,ROMDATA_W ),
conv_std_logic_vector( CP,ROMDATA_W ),
(others => '0')
);
begin
process(clk)
begin
if clk = '1' and clk'event then
datao <= rom(CONV_INTEGER(UNSIGNED(addr)) );
end if;
end process;
end RTL;
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
--
-- Title : DCT
-- Design : MDCT Core
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : ROME.VHD
-- Created : Sat Mar 5 7:37 2006
--
--------------------------------------------------------------------------------
--
-- Description : ROM for DCT matrix constant cosine coefficients (even part)
--
--------------------------------------------------------------------------------
-- 5:0
-- 5:4 = select matrix row (1 out of 4)
-- 3:0 = select precomputed MAC ( 1 out of 16)
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_arith.all;
use WORK.MDCT_PKG.all;
entity ROME is
port(
addr : in STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
clk : in STD_LOGIC;
datao : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0)
);
end ROME;
architecture RTL of ROME is
type ROM_TYPE is array (0 to (2**ROMADDR_W)-1)
of STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
constant rom : ROM_TYPE :=
(
(others => '0'),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP+AP+AP,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( BM,ROMDATA_W ),
conv_std_logic_vector( CM,ROMDATA_W ),
conv_std_logic_vector( CM+BM,ROMDATA_W ),
conv_std_logic_vector( CP,ROMDATA_W ),
conv_std_logic_vector( CP+BM,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( BM,ROMDATA_W ),
conv_std_logic_vector( BP,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( BP+CM,ROMDATA_W ),
conv_std_logic_vector( CM,ROMDATA_W ),
conv_std_logic_vector( BP+CP,ROMDATA_W ),
conv_std_logic_vector( CP,ROMDATA_W ),
conv_std_logic_vector( BP,ROMDATA_W ),
(others => '0'),
(others => '0'),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AM,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( AM,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( AM+AM,ROMDATA_W ),
conv_std_logic_vector( AM,ROMDATA_W ),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( AP,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AM,ROMDATA_W ),
(others => '0'),
(others => '0'),
conv_std_logic_vector( CM,ROMDATA_W ),
conv_std_logic_vector( BP,ROMDATA_W ),
conv_std_logic_vector( BP+CM,ROMDATA_W ),
conv_std_logic_vector( BM,ROMDATA_W ),
conv_std_logic_vector( BM+CM,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( CM,ROMDATA_W ),
conv_std_logic_vector( CP,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( CP+BP,ROMDATA_W ),
conv_std_logic_vector( BP,ROMDATA_W ),
conv_std_logic_vector( CP+BM,ROMDATA_W ),
conv_std_logic_vector( BM,ROMDATA_W ),
conv_std_logic_vector( CP,ROMDATA_W ),
(others => '0')
);
begin
process(clk)
begin
if clk = '1' and clk'event then
datao <= rom(CONV_INTEGER(UNSIGNED(addr)) );
end if;
end process;
end RTL;
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
--
-- Title : DCT
-- Design : MDCT Core
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : ROME.VHD
-- Created : Sat Mar 5 7:37 2006
--
--------------------------------------------------------------------------------
--
-- Description : ROM for DCT matrix constant cosine coefficients (even part)
--
--------------------------------------------------------------------------------
-- 5:0
-- 5:4 = select matrix row (1 out of 4)
-- 3:0 = select precomputed MAC ( 1 out of 16)
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_arith.all;
use WORK.MDCT_PKG.all;
entity ROME is
port(
addr : in STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
clk : in STD_LOGIC;
datao : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0)
);
end ROME;
architecture RTL of ROME is
type ROM_TYPE is array (0 to (2**ROMADDR_W)-1)
of STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
constant rom : ROM_TYPE :=
(
(others => '0'),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP+AP+AP,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( BM,ROMDATA_W ),
conv_std_logic_vector( CM,ROMDATA_W ),
conv_std_logic_vector( CM+BM,ROMDATA_W ),
conv_std_logic_vector( CP,ROMDATA_W ),
conv_std_logic_vector( CP+BM,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( BM,ROMDATA_W ),
conv_std_logic_vector( BP,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( BP+CM,ROMDATA_W ),
conv_std_logic_vector( CM,ROMDATA_W ),
conv_std_logic_vector( BP+CP,ROMDATA_W ),
conv_std_logic_vector( CP,ROMDATA_W ),
conv_std_logic_vector( BP,ROMDATA_W ),
(others => '0'),
(others => '0'),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AM,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( AM,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( AM+AM,ROMDATA_W ),
conv_std_logic_vector( AM,ROMDATA_W ),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( AP,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AM,ROMDATA_W ),
(others => '0'),
(others => '0'),
conv_std_logic_vector( CM,ROMDATA_W ),
conv_std_logic_vector( BP,ROMDATA_W ),
conv_std_logic_vector( BP+CM,ROMDATA_W ),
conv_std_logic_vector( BM,ROMDATA_W ),
conv_std_logic_vector( BM+CM,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( CM,ROMDATA_W ),
conv_std_logic_vector( CP,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( CP+BP,ROMDATA_W ),
conv_std_logic_vector( BP,ROMDATA_W ),
conv_std_logic_vector( CP+BM,ROMDATA_W ),
conv_std_logic_vector( BM,ROMDATA_W ),
conv_std_logic_vector( CP,ROMDATA_W ),
(others => '0')
);
begin
process(clk)
begin
if clk = '1' and clk'event then
datao <= rom(CONV_INTEGER(UNSIGNED(addr)) );
end if;
end process;
end RTL;
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
--
-- Title : DCT
-- Design : MDCT Core
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : ROME.VHD
-- Created : Sat Mar 5 7:37 2006
--
--------------------------------------------------------------------------------
--
-- Description : ROM for DCT matrix constant cosine coefficients (even part)
--
--------------------------------------------------------------------------------
-- 5:0
-- 5:4 = select matrix row (1 out of 4)
-- 3:0 = select precomputed MAC ( 1 out of 16)
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_arith.all;
use WORK.MDCT_PKG.all;
entity ROME is
port(
addr : in STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
clk : in STD_LOGIC;
datao : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0)
);
end ROME;
architecture RTL of ROME is
type ROM_TYPE is array (0 to (2**ROMADDR_W)-1)
of STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
constant rom : ROM_TYPE :=
(
(others => '0'),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP+AP+AP,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( BM,ROMDATA_W ),
conv_std_logic_vector( CM,ROMDATA_W ),
conv_std_logic_vector( CM+BM,ROMDATA_W ),
conv_std_logic_vector( CP,ROMDATA_W ),
conv_std_logic_vector( CP+BM,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( BM,ROMDATA_W ),
conv_std_logic_vector( BP,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( BP+CM,ROMDATA_W ),
conv_std_logic_vector( CM,ROMDATA_W ),
conv_std_logic_vector( BP+CP,ROMDATA_W ),
conv_std_logic_vector( CP,ROMDATA_W ),
conv_std_logic_vector( BP,ROMDATA_W ),
(others => '0'),
(others => '0'),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AM,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( AM,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( AM+AM,ROMDATA_W ),
conv_std_logic_vector( AM,ROMDATA_W ),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( AP,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AM,ROMDATA_W ),
(others => '0'),
(others => '0'),
conv_std_logic_vector( CM,ROMDATA_W ),
conv_std_logic_vector( BP,ROMDATA_W ),
conv_std_logic_vector( BP+CM,ROMDATA_W ),
conv_std_logic_vector( BM,ROMDATA_W ),
conv_std_logic_vector( BM+CM,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( CM,ROMDATA_W ),
conv_std_logic_vector( CP,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( CP+BP,ROMDATA_W ),
conv_std_logic_vector( BP,ROMDATA_W ),
conv_std_logic_vector( CP+BM,ROMDATA_W ),
conv_std_logic_vector( BM,ROMDATA_W ),
conv_std_logic_vector( CP,ROMDATA_W ),
(others => '0')
);
begin
process(clk)
begin
if clk = '1' and clk'event then
datao <= rom(CONV_INTEGER(UNSIGNED(addr)) );
end if;
end process;
end RTL;
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
--
-- Title : DCT
-- Design : MDCT Core
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : ROME.VHD
-- Created : Sat Mar 5 7:37 2006
--
--------------------------------------------------------------------------------
--
-- Description : ROM for DCT matrix constant cosine coefficients (even part)
--
--------------------------------------------------------------------------------
-- 5:0
-- 5:4 = select matrix row (1 out of 4)
-- 3:0 = select precomputed MAC ( 1 out of 16)
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_arith.all;
use WORK.MDCT_PKG.all;
entity ROME is
port(
addr : in STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
clk : in STD_LOGIC;
datao : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0)
);
end ROME;
architecture RTL of ROME is
type ROM_TYPE is array (0 to (2**ROMADDR_W)-1)
of STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
constant rom : ROM_TYPE :=
(
(others => '0'),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP+AP+AP,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( BM,ROMDATA_W ),
conv_std_logic_vector( CM,ROMDATA_W ),
conv_std_logic_vector( CM+BM,ROMDATA_W ),
conv_std_logic_vector( CP,ROMDATA_W ),
conv_std_logic_vector( CP+BM,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( BM,ROMDATA_W ),
conv_std_logic_vector( BP,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( BP+CM,ROMDATA_W ),
conv_std_logic_vector( CM,ROMDATA_W ),
conv_std_logic_vector( BP+CP,ROMDATA_W ),
conv_std_logic_vector( CP,ROMDATA_W ),
conv_std_logic_vector( BP,ROMDATA_W ),
(others => '0'),
(others => '0'),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AM,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( AM,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( AM+AM,ROMDATA_W ),
conv_std_logic_vector( AM,ROMDATA_W ),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( AP,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AM,ROMDATA_W ),
(others => '0'),
(others => '0'),
conv_std_logic_vector( CM,ROMDATA_W ),
conv_std_logic_vector( BP,ROMDATA_W ),
conv_std_logic_vector( BP+CM,ROMDATA_W ),
conv_std_logic_vector( BM,ROMDATA_W ),
conv_std_logic_vector( BM+CM,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( CM,ROMDATA_W ),
conv_std_logic_vector( CP,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( CP+BP,ROMDATA_W ),
conv_std_logic_vector( BP,ROMDATA_W ),
conv_std_logic_vector( CP+BM,ROMDATA_W ),
conv_std_logic_vector( BM,ROMDATA_W ),
conv_std_logic_vector( CP,ROMDATA_W ),
(others => '0')
);
begin
process(clk)
begin
if clk = '1' and clk'event then
datao <= rom(CONV_INTEGER(UNSIGNED(addr)) );
end if;
end process;
end RTL;
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
--
-- Title : DCT
-- Design : MDCT Core
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : ROME.VHD
-- Created : Sat Mar 5 7:37 2006
--
--------------------------------------------------------------------------------
--
-- Description : ROM for DCT matrix constant cosine coefficients (even part)
--
--------------------------------------------------------------------------------
-- 5:0
-- 5:4 = select matrix row (1 out of 4)
-- 3:0 = select precomputed MAC ( 1 out of 16)
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_arith.all;
use WORK.MDCT_PKG.all;
entity ROME is
port(
addr : in STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
clk : in STD_LOGIC;
datao : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0)
);
end ROME;
architecture RTL of ROME is
type ROM_TYPE is array (0 to (2**ROMADDR_W)-1)
of STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
constant rom : ROM_TYPE :=
(
(others => '0'),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP+AP+AP,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( BM,ROMDATA_W ),
conv_std_logic_vector( CM,ROMDATA_W ),
conv_std_logic_vector( CM+BM,ROMDATA_W ),
conv_std_logic_vector( CP,ROMDATA_W ),
conv_std_logic_vector( CP+BM,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( BM,ROMDATA_W ),
conv_std_logic_vector( BP,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( BP+CM,ROMDATA_W ),
conv_std_logic_vector( CM,ROMDATA_W ),
conv_std_logic_vector( BP+CP,ROMDATA_W ),
conv_std_logic_vector( CP,ROMDATA_W ),
conv_std_logic_vector( BP,ROMDATA_W ),
(others => '0'),
(others => '0'),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AM,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( AM,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( AM+AM,ROMDATA_W ),
conv_std_logic_vector( AM,ROMDATA_W ),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( AP,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AM,ROMDATA_W ),
(others => '0'),
(others => '0'),
conv_std_logic_vector( CM,ROMDATA_W ),
conv_std_logic_vector( BP,ROMDATA_W ),
conv_std_logic_vector( BP+CM,ROMDATA_W ),
conv_std_logic_vector( BM,ROMDATA_W ),
conv_std_logic_vector( BM+CM,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( CM,ROMDATA_W ),
conv_std_logic_vector( CP,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( CP+BP,ROMDATA_W ),
conv_std_logic_vector( BP,ROMDATA_W ),
conv_std_logic_vector( CP+BM,ROMDATA_W ),
conv_std_logic_vector( BM,ROMDATA_W ),
conv_std_logic_vector( CP,ROMDATA_W ),
(others => '0')
);
begin
process(clk)
begin
if clk = '1' and clk'event then
datao <= rom(CONV_INTEGER(UNSIGNED(addr)) );
end if;
end process;
end RTL;
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
--
-- Title : DCT
-- Design : MDCT Core
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : ROME.VHD
-- Created : Sat Mar 5 7:37 2006
--
--------------------------------------------------------------------------------
--
-- Description : ROM for DCT matrix constant cosine coefficients (even part)
--
--------------------------------------------------------------------------------
-- 5:0
-- 5:4 = select matrix row (1 out of 4)
-- 3:0 = select precomputed MAC ( 1 out of 16)
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_arith.all;
use WORK.MDCT_PKG.all;
entity ROME is
port(
addr : in STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
clk : in STD_LOGIC;
datao : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0)
);
end ROME;
architecture RTL of ROME is
type ROM_TYPE is array (0 to (2**ROMADDR_W)-1)
of STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
constant rom : ROM_TYPE :=
(
(others => '0'),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP+AP+AP,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( BM,ROMDATA_W ),
conv_std_logic_vector( CM,ROMDATA_W ),
conv_std_logic_vector( CM+BM,ROMDATA_W ),
conv_std_logic_vector( CP,ROMDATA_W ),
conv_std_logic_vector( CP+BM,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( BM,ROMDATA_W ),
conv_std_logic_vector( BP,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( BP+CM,ROMDATA_W ),
conv_std_logic_vector( CM,ROMDATA_W ),
conv_std_logic_vector( BP+CP,ROMDATA_W ),
conv_std_logic_vector( CP,ROMDATA_W ),
conv_std_logic_vector( BP,ROMDATA_W ),
(others => '0'),
(others => '0'),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AM,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( AM,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( AM+AM,ROMDATA_W ),
conv_std_logic_vector( AM,ROMDATA_W ),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( AP,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AM,ROMDATA_W ),
(others => '0'),
(others => '0'),
conv_std_logic_vector( CM,ROMDATA_W ),
conv_std_logic_vector( BP,ROMDATA_W ),
conv_std_logic_vector( BP+CM,ROMDATA_W ),
conv_std_logic_vector( BM,ROMDATA_W ),
conv_std_logic_vector( BM+CM,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( CM,ROMDATA_W ),
conv_std_logic_vector( CP,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( CP+BP,ROMDATA_W ),
conv_std_logic_vector( BP,ROMDATA_W ),
conv_std_logic_vector( CP+BM,ROMDATA_W ),
conv_std_logic_vector( BM,ROMDATA_W ),
conv_std_logic_vector( CP,ROMDATA_W ),
(others => '0')
);
begin
process(clk)
begin
if clk = '1' and clk'event then
datao <= rom(CONV_INTEGER(UNSIGNED(addr)) );
end if;
end process;
end RTL;
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
--
-- Title : DCT
-- Design : MDCT Core
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : ROME.VHD
-- Created : Sat Mar 5 7:37 2006
--
--------------------------------------------------------------------------------
--
-- Description : ROM for DCT matrix constant cosine coefficients (even part)
--
--------------------------------------------------------------------------------
-- 5:0
-- 5:4 = select matrix row (1 out of 4)
-- 3:0 = select precomputed MAC ( 1 out of 16)
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_arith.all;
use WORK.MDCT_PKG.all;
entity ROME is
port(
addr : in STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
clk : in STD_LOGIC;
datao : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0)
);
end ROME;
architecture RTL of ROME is
type ROM_TYPE is array (0 to (2**ROMADDR_W)-1)
of STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
constant rom : ROM_TYPE :=
(
(others => '0'),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP+AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP+AP+AP,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( BM,ROMDATA_W ),
conv_std_logic_vector( CM,ROMDATA_W ),
conv_std_logic_vector( CM+BM,ROMDATA_W ),
conv_std_logic_vector( CP,ROMDATA_W ),
conv_std_logic_vector( CP+BM,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( BM,ROMDATA_W ),
conv_std_logic_vector( BP,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( BP+CM,ROMDATA_W ),
conv_std_logic_vector( CM,ROMDATA_W ),
conv_std_logic_vector( BP+CP,ROMDATA_W ),
conv_std_logic_vector( CP,ROMDATA_W ),
conv_std_logic_vector( BP,ROMDATA_W ),
(others => '0'),
(others => '0'),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AM,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( AM,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( AM+AM,ROMDATA_W ),
conv_std_logic_vector( AM,ROMDATA_W ),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AP+AP,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( AP,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( AP,ROMDATA_W ),
conv_std_logic_vector( AM,ROMDATA_W ),
(others => '0'),
(others => '0'),
conv_std_logic_vector( CM,ROMDATA_W ),
conv_std_logic_vector( BP,ROMDATA_W ),
conv_std_logic_vector( BP+CM,ROMDATA_W ),
conv_std_logic_vector( BM,ROMDATA_W ),
conv_std_logic_vector( BM+CM,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( CM,ROMDATA_W ),
conv_std_logic_vector( CP,ROMDATA_W ),
(others => '0'),
conv_std_logic_vector( CP+BP,ROMDATA_W ),
conv_std_logic_vector( BP,ROMDATA_W ),
conv_std_logic_vector( CP+BM,ROMDATA_W ),
conv_std_logic_vector( BM,ROMDATA_W ),
conv_std_logic_vector( CP,ROMDATA_W ),
(others => '0')
);
begin
process(clk)
begin
if clk = '1' and clk'event then
datao <= rom(CONV_INTEGER(UNSIGNED(addr)) );
end if;
end process;
end RTL;
|
------------------------------------------------------------------------------
-- matrixmultiplier - entity/architecture pair
------------------------------------------------------------------------------
-- Filename: matrixmultiplier
-- Version: 2.00.a
-- Description: matrix multiplier(VHDL).
-- Date: Wed June 7 16:32:00 2013
-- VHDL Standard: VHDL'93
-- Author: Achim Loesch
------------------------------------------------------------------------------
-- Feel free to modify this file.
------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
------------------------------------------------------------------------------
-- Entity Section
------------------------------------------------------------------------------
entity matrixmultiplier is
generic (
G_LINE_LEN_MATRIX : integer := 128;
G_RAM_DATA_WIDTH : integer := 32;
G_RAM_SIZE_MATRIX_A_C : integer := 128;
G_RAM_ADDR_WIDTH_MATRIX_A_C : integer := 7;
G_RAM_SIZE_MATRIX_B : integer := 16384;
G_RAM_ADDR_WIDTH_MATRIX_B : integer := 14
);
port(
clk : in std_logic;
reset : in std_logic;
start : in std_logic;
done : out std_logic;
o_RAM_A_Addr : out std_logic_vector(0 to G_RAM_ADDR_WIDTH_MATRIX_A_C - 1);
i_RAM_A_Data : in std_logic_vector(0 to 31);
o_RAM_B_Addr : out std_logic_vector(0 to G_RAM_ADDR_WIDTH_MATRIX_B - 1);
i_RAM_B_Data : in std_logic_vector(0 to 31);
o_RAM_C_Addr : out std_logic_vector(0 to G_RAM_ADDR_WIDTH_MATRIX_A_C - 1);
o_RAM_C_Data : out std_logic_vector(0 to 31);
o_RAM_C_WE : out std_logic
);
end matrixmultiplier;
------------------------------------------------------------------------------
-- Architecture Section
------------------------------------------------------------------------------
architecture Behavioral of matrixmultiplier is
type STATE_TYPE is (
STATE_IDLE,
STATE_LOAD,
STATE_LOAD_WAIT,
STATE_SUM,
STATE_DELAY_1,
STATE_DELAY_2,
STATE_STORE,
STATE_STORE_WAIT,
STATE_FINISH_CYCLE
);
signal state : STATE_TYPE;
signal temp : std_logic_vector(0 to G_RAM_DATA_WIDTH-1);
signal prod,delay : std_logic_vector(0 to G_RAM_DATA_WIDTH-1);
begin
multiply : process(clk) is
variable j : integer := 0;
variable k : integer := 0;
begin
if (clk'event and clk = '1') then
if (reset = '1') then
done <= '0';
o_RAM_A_Addr <= (others=>'0');
o_RAM_B_Addr <= (others=>'0');
o_RAM_C_Addr <= (others=>'0');
o_RAM_C_Data <= (others=>'0');
o_RAM_C_WE <= '0';
state <= STATE_IDLE;
else
o_RAM_C_WE <= '0';
o_RAM_C_Data <= (others=>'0');
case state is
when STATE_IDLE =>
done <= '0';
if (start = '1') then
j := 0;
k := 0;
temp <= (others=>'0');
state <= STATE_LOAD;
end if;
when STATE_LOAD =>
o_RAM_A_Addr <= conv_std_logic_vector(integer(k), G_RAM_ADDR_WIDTH_MATRIX_A_C);
o_RAM_B_Addr <= conv_std_logic_vector(integer(k*G_LINE_LEN_MATRIX+j), G_RAM_ADDR_WIDTH_MATRIX_B);
k := k + 1;
state <= STATE_LOAD_WAIT;
when STATE_LOAD_WAIT =>
state <= STATE_DELAY_1;
when STATE_DELAY_1 =>
state <= STATE_DELAY_2;
when STATE_DELAY_2 =>
state <= STATE_SUM;
when STATE_SUM =>
temp <= temp + prod;
if (k = G_LINE_LEN_MATRIX) then
k := 0;
state <= STATE_STORE;
else
state <= STATE_LOAD;
end if;
when STATE_STORE =>
o_RAM_C_Addr <= conv_std_logic_vector(integer(j), G_RAM_ADDR_WIDTH_MATRIX_A_C);
o_RAM_C_WE <= '1';
o_RAM_C_Data <= temp;
state <= STATE_STORE_WAIT;
when STATE_STORE_WAIT =>
o_RAM_C_WE <= '0';
state <= STATE_FINISH_CYCLE;
when STATE_FINISH_CYCLE =>
j := j + 1;
if (j = G_LINE_LEN_MATRIX) then
j := 0;
done <= '1';
state <= STATE_IDLE;
else
temp <= (others => '0');
state <= STATE_LOAD;
end if;
end case;
end if;
end if;
end process;
process (clk)
begin
if clk'event and clk = '1' then
delay <= conv_std_logic_vector(signed(i_RAM_A_Data)*signed(i_RAM_B_Data),G_RAM_DATA_WIDTH);
prod <= delay;
end if;
end process;
end Behavioral;
|
------------------------------------------------------------------------------
-- matrixmultiplier - entity/architecture pair
------------------------------------------------------------------------------
-- Filename: matrixmultiplier
-- Version: 2.00.a
-- Description: matrix multiplier(VHDL).
-- Date: Wed June 7 16:32:00 2013
-- VHDL Standard: VHDL'93
-- Author: Achim Loesch
------------------------------------------------------------------------------
-- Feel free to modify this file.
------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
------------------------------------------------------------------------------
-- Entity Section
------------------------------------------------------------------------------
entity matrixmultiplier is
generic (
G_LINE_LEN_MATRIX : integer := 128;
G_RAM_DATA_WIDTH : integer := 32;
G_RAM_SIZE_MATRIX_A_C : integer := 128;
G_RAM_ADDR_WIDTH_MATRIX_A_C : integer := 7;
G_RAM_SIZE_MATRIX_B : integer := 16384;
G_RAM_ADDR_WIDTH_MATRIX_B : integer := 14
);
port(
clk : in std_logic;
reset : in std_logic;
start : in std_logic;
done : out std_logic;
o_RAM_A_Addr : out std_logic_vector(0 to G_RAM_ADDR_WIDTH_MATRIX_A_C - 1);
i_RAM_A_Data : in std_logic_vector(0 to 31);
o_RAM_B_Addr : out std_logic_vector(0 to G_RAM_ADDR_WIDTH_MATRIX_B - 1);
i_RAM_B_Data : in std_logic_vector(0 to 31);
o_RAM_C_Addr : out std_logic_vector(0 to G_RAM_ADDR_WIDTH_MATRIX_A_C - 1);
o_RAM_C_Data : out std_logic_vector(0 to 31);
o_RAM_C_WE : out std_logic
);
end matrixmultiplier;
------------------------------------------------------------------------------
-- Architecture Section
------------------------------------------------------------------------------
architecture Behavioral of matrixmultiplier is
type STATE_TYPE is (
STATE_IDLE,
STATE_LOAD,
STATE_LOAD_WAIT,
STATE_SUM,
STATE_DELAY_1,
STATE_DELAY_2,
STATE_STORE,
STATE_STORE_WAIT,
STATE_FINISH_CYCLE
);
signal state : STATE_TYPE;
signal temp : std_logic_vector(0 to G_RAM_DATA_WIDTH-1);
signal prod,delay : std_logic_vector(0 to G_RAM_DATA_WIDTH-1);
begin
multiply : process(clk) is
variable j : integer := 0;
variable k : integer := 0;
begin
if (clk'event and clk = '1') then
if (reset = '1') then
done <= '0';
o_RAM_A_Addr <= (others=>'0');
o_RAM_B_Addr <= (others=>'0');
o_RAM_C_Addr <= (others=>'0');
o_RAM_C_Data <= (others=>'0');
o_RAM_C_WE <= '0';
state <= STATE_IDLE;
else
o_RAM_C_WE <= '0';
o_RAM_C_Data <= (others=>'0');
case state is
when STATE_IDLE =>
done <= '0';
if (start = '1') then
j := 0;
k := 0;
temp <= (others=>'0');
state <= STATE_LOAD;
end if;
when STATE_LOAD =>
o_RAM_A_Addr <= conv_std_logic_vector(integer(k), G_RAM_ADDR_WIDTH_MATRIX_A_C);
o_RAM_B_Addr <= conv_std_logic_vector(integer(k*G_LINE_LEN_MATRIX+j), G_RAM_ADDR_WIDTH_MATRIX_B);
k := k + 1;
state <= STATE_LOAD_WAIT;
when STATE_LOAD_WAIT =>
state <= STATE_DELAY_1;
when STATE_DELAY_1 =>
state <= STATE_DELAY_2;
when STATE_DELAY_2 =>
state <= STATE_SUM;
when STATE_SUM =>
temp <= temp + prod;
if (k = G_LINE_LEN_MATRIX) then
k := 0;
state <= STATE_STORE;
else
state <= STATE_LOAD;
end if;
when STATE_STORE =>
o_RAM_C_Addr <= conv_std_logic_vector(integer(j), G_RAM_ADDR_WIDTH_MATRIX_A_C);
o_RAM_C_WE <= '1';
o_RAM_C_Data <= temp;
state <= STATE_STORE_WAIT;
when STATE_STORE_WAIT =>
o_RAM_C_WE <= '0';
state <= STATE_FINISH_CYCLE;
when STATE_FINISH_CYCLE =>
j := j + 1;
if (j = G_LINE_LEN_MATRIX) then
j := 0;
done <= '1';
state <= STATE_IDLE;
else
temp <= (others => '0');
state <= STATE_LOAD;
end if;
end case;
end if;
end if;
end process;
process (clk)
begin
if clk'event and clk = '1' then
delay <= conv_std_logic_vector(signed(i_RAM_A_Data)*signed(i_RAM_B_Data),G_RAM_DATA_WIDTH);
prod <= delay;
end if;
end process;
end Behavioral;
|
library verilog;
use verilog.vl_types.all;
entity decode_mmucheck is
port(
iPAGING_ENA : in vl_logic;
iKERNEL_ACCESS : in vl_logic;
iMMU_FLAGS : in vl_logic_vector(13 downto 0);
oIRQ40 : out vl_logic_vector(2 downto 0);
oIRQ41 : out vl_logic_vector(2 downto 0);
oIRQ42 : out vl_logic_vector(2 downto 0)
);
end decode_mmucheck;
|
library ieee;
use ieee.std_logic_1164.all;
entity e1 is
port(
r1: in real;
slv1: in std_logic_vector(7 downto 0);
sl1: in std_logic
);
end;
architecture a of e1 is
begin
end;
library ieee;
use ieee.std_logic_1164.all;
entity e2 is
begin
end;
architecture a of e2 is
constant r2: integer := 10e6;
signal slv2: std_logic_vector(7 downto 0);
signal sl2: std_logic;
begin
tx: entity work.e1
port map(
r1 => real(r2_wrong),
slv1 => slv2,
sl1 => sl2
);
end;
|
library ieee;
use ieee.std_logic_1164.all;
entity e1 is
port(
r1: in real;
slv1: in std_logic_vector(7 downto 0);
sl1: in std_logic
);
end;
architecture a of e1 is
begin
end;
library ieee;
use ieee.std_logic_1164.all;
entity e2 is
begin
end;
architecture a of e2 is
constant r2: integer := 10e6;
signal slv2: std_logic_vector(7 downto 0);
signal sl2: std_logic;
begin
tx: entity work.e1
port map(
r1 => real(r2_wrong),
slv1 => slv2,
sl1 => sl2
);
end;
|
library ieee;
use ieee.std_logic_1164.all;
entity e1 is
port(
r1: in real;
slv1: in std_logic_vector(7 downto 0);
sl1: in std_logic
);
end;
architecture a of e1 is
begin
end;
library ieee;
use ieee.std_logic_1164.all;
entity e2 is
begin
end;
architecture a of e2 is
constant r2: integer := 10e6;
signal slv2: std_logic_vector(7 downto 0);
signal sl2: std_logic;
begin
tx: entity work.e1
port map(
r1 => real(r2_wrong),
slv1 => slv2,
sl1 => sl2
);
end;
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 15:19:38 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ led_controller_design_led_controller_0_1_stub.vhdl
-- Design : led_controller_design_led_controller_0_1
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
LEDs_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_awready : out STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wready : out STD_LOGIC;
s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_bvalid : out STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_arvalid : in STD_LOGIC;
s00_axi_arready : out STD_LOGIC;
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "LEDs_out[7:0],s00_axi_awaddr[3:0],s00_axi_awprot[2:0],s00_axi_awvalid,s00_axi_awready,s00_axi_wdata[31:0],s00_axi_wstrb[3:0],s00_axi_wvalid,s00_axi_wready,s00_axi_bresp[1:0],s00_axi_bvalid,s00_axi_bready,s00_axi_araddr[3:0],s00_axi_arprot[2:0],s00_axi_arvalid,s00_axi_arready,s00_axi_rdata[31:0],s00_axi_rresp[1:0],s00_axi_rvalid,s00_axi_rready,s00_axi_aclk,s00_axi_aresetn";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "led_controller_v1_0,Vivado 2017.3";
begin
end;
|
architecture RTL of FIFO is
attribute coordinate of comp_1:component is (0.0, 17.5);
-- Violations below
attribute coordinate of comp_1:component is (0.0, 17.5);
attribute coordinate of comp_1:component is (0.0, 17.5);
begin
end architecture RTL;
|
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all;
ENTITY register_file IS
GENERIC(
register_size: INTEGER := 32 --MIPS register size is 32 bit
);
PORT(
-- ************** Do we need a standard enable input ? *****************
clock: IN STD_LOGIC;
rs: IN STD_LOGIC_VECTOR (4 downto 0); -- first source register
rt: IN STD_LOGIC_VECTOR (4 downto 0); -- second source register
write_enable: IN STD_LOGIC; -- signals that rd_data may be written into rd **********Unsure if neccessary*************
rd: IN STD_LOGIC_VECTOR (4 downto 0); -- destination register
rd_data: IN STD_LOGIC_VECTOR (31 downto 0); -- destination register data
writeToText: IN STD_LOGIC := '0';
ra_data: OUT STD_LOGIC_VECTOR (31 downto 0); -- data of register a
rb_data: OUT STD_LOGIC_VECTOR (31 downto 0) -- data of register b
);
END register_file;
ARCHITECTURE Behav OF register_file IS
TYPE registers IS ARRAY (0 to 31) OF STD_LOGIC_VECTOR(31 downto 0); -- MIPS has 32 registers. Size of data is 32 bits. => 32x32bits
SIGNAL register_store: registers := (OTHERS=> "00000000000000000000000000000000"); -- initialize all registers to 32 bits of 0.
BEGIN
PROCESS (clock)
BEGIN
IF (clock'event) THEN
ra_data <= register_store(to_integer(unsigned(rs))); -- data of ra is now the data associated with rs's register index in the register_store
rb_data <= register_store(to_integer(unsigned(rt)));
IF (write_enable = '1') THEN -- if write_enable is high, we have permission to update the data of rd
IF (to_integer(unsigned(rd)) = 0) THEN -- if we are trying to write to R0, then deny the write
NULL;
ELSE
register_store(to_integer(unsigned(rd))) <= rd_data; -- access the appropriate register in the register_store, and assign it rd_data
END IF;
END IF;
END IF;
END PROCESS;
process(writeToText)
file register_file : text open write_mode is "register_file.txt";
variable outLine : line;
variable rowLine : integer := 0;
variable test : std_logic_vector(31 downto 0) := "00100000000000010000000000000001";
begin
if writeToText = '1' then
while (rowLine < 32) loop
write(outLine, register_store(rowLine));
writeline(register_file, outLine);
rowLine := rowLine + 1;
end loop;
end if;
end process;
END Behav;
|
--!
--! Copyright 2019 Sergey Khabarov, sergeykhbr@gmail.com
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.types_mem.all;
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
entity axi4_rom is
generic (
memtech : integer := inferred;
async_reset : boolean := false;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
sim_hexfile : string
);
port (
clk : in std_logic;
nrst : in std_logic;
cfg : out axi4_slave_config_type;
i : in axi4_slave_in_type;
o : out axi4_slave_out_type
);
end;
architecture arch_axi4_rom of axi4_rom is
-- To avoid warning 'literal negative value' use -1048576 instead of 16#fff00000#
constant size_4kbytes : integer := -(xmask - 1048576);
constant abits : integer := 12 + log2(size_4kbytes);
constant xconfig : axi4_slave_config_type := (
descrtype => PNP_CFG_TYPE_SLAVE,
descrsize => PNP_CFG_SLAVE_DESCR_BYTES,
irq_idx => conv_std_logic_vector(0, 8),
xaddr => conv_std_logic_vector(xaddr, CFG_SYSBUS_CFG_ADDR_BITS),
xmask => conv_std_logic_vector(xmask, CFG_SYSBUS_CFG_ADDR_BITS),
vid => VENDOR_GNSSSENSOR,
did => GNSSSENSOR_ROM
);
signal raddr : global_addr_array_type;
signal rdata : std_logic_vector(CFG_SYSBUS_DATA_BITS-1 downto 0);
begin
cfg <= xconfig;
axi0 : axi4_slave generic map (
async_reset => async_reset
) port map (
i_clk => clk,
i_nrst => nrst,
i_xcfg => xconfig,
i_xslvi => i,
o_xslvo => o,
i_ready => '1',
i_rdata => rdata,
o_re => open,
o_r32 => open,
o_radr => raddr,
o_wadr => open,
o_we => open,
o_wstrb => open,
o_wdata => open
);
tech0 : Rom_tech generic map (
memtech => memtech,
abits => abits,
sim_hexfile => sim_hexfile
) port map (
clk => clk,
address => raddr,
data => rdata
);
end; |
-- opa: Open Processor Architecture
-- Copyright (C) 2014-2016 Wesley W. Terpstra
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- To apply the GPL to my VHDL, please follow these definitions:
-- Program - The entire collection of VHDL in this project and any
-- netlist or floorplan derived from it.
-- System Library - Any macro that translates directly to hardware
-- e.g. registers, IO pins, or memory blocks
--
-- My intent is that if you include OPA into your project, all of the HDL
-- and other design files that go into the same physical chip must also
-- be released under the GPL. If this does not cover your usage, then you
-- must consult me directly to receive the code under a different license.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.opa_pkg.all;
use work.opa_functions_pkg.all;
use work.opa_components_pkg.all;
entity opa_lfsr is
generic(
g_entropy : natural := 0;
g_bits : natural);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
random_o : out std_logic_vector(g_bits-1 downto 0));
end opa_lfsr;
architecture rtl of opa_lfsr is
-- We only want to work with trinomial irreducible polynomials
-- They build-up less xor chains when we do multiple shifts at once
constant c_size : natural := 18; -- Has a nice trionmial irreducible polynomial
constant c_tap : natural := 11; -- x^18 + x^11 + 1 is irreducible
signal r_reg : std_logic_vector(c_size-1 downto 0);
begin
main : process(clk_i, rst_n_i) is
variable result : std_logic_vector(r_reg'range);
begin
if rst_n_i = '0' then
r_reg <= (others => '1');
elsif rising_edge(clk_i) then
result := r_reg;
for i in 0 to g_bits-1 loop
result := result(result'high-1 downto result'low) & result(result'high);
result(c_tap) := result(c_tap) xor result(result'low);
end loop;
r_reg <= result;
end if;
end process;
random_o <= r_reg(random_o'range);
end rtl;
|
-- file: i_fetch_test_stream_instr_stream_pkg.vhd (just sws)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/27/2008
--
----------------------------------------------------------
--- EXPECTED RESULT
-- Physical register values changes as follows :
-- 32 => 00000010(h)
-- 33 => 00000020(h)
-- 34 => 00000030(h)
-- 35 => 00000040(h)
-- 36 => 00000050(h)
-- 37 => 00000060(h)
-- 38 => 00000070(h)
-- 39 => 00000080(h)
-- 40 => 00000001(h)
-- 41 => 00000002(h)
-- 42 => 000000B0(h)
-- 43 => 000000C0(h)
-- 44 => 000000D0(h)
-- 45 => 000000E0(h)
-- 46 => 000000F0(h)
-- 47 => 00000100(h)
------------------------------------------------------------------
library std, ieee;
use ieee.std_logic_1164.all;
package instr_stream_pkg is
constant DATA_WIDTH_CONSTANT : integer := 128; -- data width of of our cache
constant ADDR_WIDTH_CONSTANT : integer := 6; -- address width of our cache
-- type declarations
type mem_type is array (0 to (2**ADDR_WIDTH_CONSTANT)-1) of std_logic_vector((DATA_WIDTH_CONSTANT-1) downto 0);
signal mem : mem_type :=
(X"8C9E000C_8C9E0008_8C9E0004_8C9E0000", -- Loc 0C, 08, 04, 00
X"8C9E001C_8C9E0018_8C9E0014_8C9E0010", -- Loc 1C, 18, 14, 10
X"8C9E002C_8C9E0028_8C9E0024_8C9E0020", -- Loc 2C, 28, 24, 20
X"8C9E003C_8C9E0038_8C9E0034_8C9E0030", -- Loc 3C, 38, 34, 30
-- 16 sw instructions changing 16 locations with the content of $30 which is decimal 30 (1D hex)
-- "00000000000000000000000000011110", -- $30
-- Location:() | LW $30 ,0( $4) -- 8C9E0000
-- Location:() | LW $30 ,4( $4) -- 8C9E0004
X"00000020_00000020_00000020_00000020", --- Loc 4C, 48, 44, 40
X"00000020_00000020_00000020_00000020", -- Loc 5C, 58, 54, 50
X"00000020_00000020_00000020_00000020", -- Loc 6C, 68, 64, 60
X"00000020_00000020_00000020_00000020", -- Loc 7C, 78, 74, 70
-- similar lines as above which read a word from the memory,
-- increment it, and then store it back to the same location.
-- There is only a RAW hazard, but other cases of memory disambiguation are not covered here.
-- a bunch of NOP instructions (ADD $0 $0 $0) to fill the space
X"00000020_00000020_00000020_00000020", -- Loc 8C, 88, 84, 80
X"00000020_00000020_00000020_00000020", -- Loc 9C, 98, 94, 90
X"00000020_00000020_00000020_00000020", -- Loc AC, A8, A4, A0
X"00000020_00000020_00000020_00000020", -- Loc BC, B8, B4, B0
X"00000020_00000020_00000020_00000020", -- Loc CC, C8, C4, C0
X"00000020_00000020_00000020_00000020", -- Loc DC, D8, D4, D0
X"00000020_00000020_00000020_00000020", -- Loc EC, E8, E4, E0
X"00000020_00000020_00000020_00000020", -- Loc FC, F8, F4, F0
X"00000020_00000020_00000020_00000020", -- Loc 10C, 108, 104, 100
X"00000020_00000020_00000020_00000020", -- Loc 11C, 118, 114, 110
X"00000020_00000020_00000020_00000020", -- Loc 12C, 128, 124, 120
X"00000020_00000020_00000020_00000020", -- Loc 13C, 138, 134, 130
X"00000020_00000020_00000020_00000020", -- Loc 14C, 148, 144, 140
X"00000020_00000020_00000020_00000020", -- Loc 15C, 158, 154, 150
X"00000020_00000020_00000020_00000020", -- Loc 16C, 168, 164, 160
X"00000020_00000020_00000020_00000020", -- Loc 17C, 178, 174, 170
X"00000020_00000020_00000020_00000020", -- Loc 18C, 188, 184, 180
X"00000020_00000020_00000020_00000020", -- Loc 19C, 198, 194, 190
X"00000020_00000020_00000020_00000020", -- Loc 1AC, 1A8, 1A4, 1A0
X"00000020_00000020_00000020_00000020", -- Loc 1BC, 1B8, 1B4, 1B0
X"00000020_00000020_00000020_00000020", -- Loc 1CC, 1C8, 1C4, 1C0
X"00000020_00000020_00000020_00000020", -- Loc 1DC, 1D8, 1D4, 1D0
X"00000020_00000020_00000020_00000020", -- Loc 1EC, 1E8, 1E4, 1E0
X"00000020_00000020_00000020_00000020", -- Loc 1FC, 1F8, 1F4, 1F0
X"00000020_00000020_00000020_00000020", -- Loc 20C, 208, 204, 200
X"00000020_00000020_00000020_00000020", -- Loc 21C, 218, 214, 221
X"00000020_00000020_00000020_00000020", -- Loc 22C, 228, 224, 220
X"00000020_00000020_00000020_00000020", -- Loc 23C, 238, 234, 230
X"00000020_00000020_00000020_00000020", -- Loc 24C, 248, 244, 240
X"00000020_00000020_00000020_00000020", -- Loc 25C, 258, 254, 250
X"00000020_00000020_00000020_00000020", -- Loc 26C, 268, 264, 260
X"00000020_00000020_00000020_00000020", -- Loc 27C, 278, 274, 270
X"00000020_00000020_00000020_00000020", -- Loc 28C, 288, 284, 280
X"00000020_00000020_00000020_00000020", -- Loc 29C, 298, 294, 290
X"00000020_00000020_00000020_00000020", -- Loc 2AC, 2A8, 2A4, 2A0
X"00000020_00000020_00000020_00000020", -- Loc 2BC, 2B8, 2B4, 2B0
X"00000020_00000020_00000020_00000020", -- Loc 2CC, 2C8, 2C4, 2C0
X"00000020_00000020_00000020_00000020", -- Loc 2DC, 2D8, 2D4, 2D0
X"00000020_00000020_00000020_00000020", -- Loc 2EC, 2E8, 2E4, 2E0
X"00000020_00000020_00000020_00000020", -- Loc 2FC, 2F8, 2F4, 2F0
X"00000020_00000020_00000020_00000020", -- Loc 30C, 308, 304, 300
X"00000020_00000020_00000020_00000020", -- Loc 31C, 318, 314, 331
X"00000020_00000020_00000020_00000020", -- Loc 32C, 328, 324, 320
X"00000020_00000020_00000020_00000020", -- Loc 33C, 338, 334, 330
X"00000020_00000020_00000020_00000020", -- Loc 34C, 348, 344, 340
X"00000020_00000020_00000020_00000020", -- Loc 35C, 358, 354, 350
X"00000020_00000020_00000020_00000020", -- Loc 36C, 368, 364, 360
X"00000020_00000020_00000020_00000020", -- Loc 37C, 378, 374, 370
X"00000020_00000020_00000020_00000020", -- Loc 38C, 388, 384, 380
X"00000020_00000020_00000020_00000020", -- Loc 39C, 398, 394, 390
X"00000020_00000020_00000020_00000020", -- Loc 3AC, 3A8, 3A4, 3A0
X"00000020_00000020_00000020_00000020", -- Loc 3BC, 3B8, 3B4, 3B0
-- the last 16 instructions are looping jump instructions
X"080000F3_080000F2_080000F1_080000F0", -- Loc 3CC, 3C8, 3C4, 3C0
X"080000F7_080000F6_080000F5_080000F4", -- Loc 3DC, 3D8, 3D4, 3D0
X"080000FB_080000FA_080000F9_080000F8", -- Loc 3EC, 3E8, 3E4, 3E0
X"080000FF_080000FE_080000FD_080000FC" -- Loc 3FC, 3F8, 3F4, 3F0
) ;
-- the last 16 instructions are looping jump instructions
-- of the type: loop: j loop
-- This is to make sure that neither instruction fetching
-- nor instruction execution proceeds beyond the end of this memory.
-- Loc 3C0 -- 080000F0 => J 240
-- Loc 3C4 -- 080000F1 => J 241
-- Loc 3C8 -- 080000F2 => J 242
-- Loc 3CC -- 080000F3 => J 243
--
-- Loc 3D0 -- 080000F4 => J 244
-- Loc 3D4 -- 080000F5 => J 245
-- Loc 3D8 -- 080000F6 => J 246
-- Loc 3DC -- 080000F7 => J 247
--
-- Loc 3E0 -- 080000F8 => J 248
-- Loc 3E4 -- 080000F9 => J 249
-- Loc 3E8 -- 080000FA => J 250
-- Loc 3EC -- 080000FB => J 251
--
-- Loc 3F0 -- 080000FC => J 252
-- Loc 3F4 -- 080000FD => J 253
-- Loc 3F8 -- 080000FE => J 254
-- Loc 3FC -- 080000FF => J 255
end package instr_stream_pkg;
-- -- No need for a package body here
-- package body instr_stream_pkg is
--
-- end package body instr_stream_pkg;
|
-- file: i_fetch_test_stream_instr_stream_pkg.vhd (just sws)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/27/2008
--
----------------------------------------------------------
--- EXPECTED RESULT
-- Physical register values changes as follows :
-- 32 => 00000010(h)
-- 33 => 00000020(h)
-- 34 => 00000030(h)
-- 35 => 00000040(h)
-- 36 => 00000050(h)
-- 37 => 00000060(h)
-- 38 => 00000070(h)
-- 39 => 00000080(h)
-- 40 => 00000001(h)
-- 41 => 00000002(h)
-- 42 => 000000B0(h)
-- 43 => 000000C0(h)
-- 44 => 000000D0(h)
-- 45 => 000000E0(h)
-- 46 => 000000F0(h)
-- 47 => 00000100(h)
------------------------------------------------------------------
library std, ieee;
use ieee.std_logic_1164.all;
package instr_stream_pkg is
constant DATA_WIDTH_CONSTANT : integer := 128; -- data width of of our cache
constant ADDR_WIDTH_CONSTANT : integer := 6; -- address width of our cache
-- type declarations
type mem_type is array (0 to (2**ADDR_WIDTH_CONSTANT)-1) of std_logic_vector((DATA_WIDTH_CONSTANT-1) downto 0);
signal mem : mem_type :=
(X"8C9E000C_8C9E0008_8C9E0004_8C9E0000", -- Loc 0C, 08, 04, 00
X"8C9E001C_8C9E0018_8C9E0014_8C9E0010", -- Loc 1C, 18, 14, 10
X"8C9E002C_8C9E0028_8C9E0024_8C9E0020", -- Loc 2C, 28, 24, 20
X"8C9E003C_8C9E0038_8C9E0034_8C9E0030", -- Loc 3C, 38, 34, 30
-- 16 sw instructions changing 16 locations with the content of $30 which is decimal 30 (1D hex)
-- "00000000000000000000000000011110", -- $30
-- Location:() | LW $30 ,0( $4) -- 8C9E0000
-- Location:() | LW $30 ,4( $4) -- 8C9E0004
X"00000020_00000020_00000020_00000020", --- Loc 4C, 48, 44, 40
X"00000020_00000020_00000020_00000020", -- Loc 5C, 58, 54, 50
X"00000020_00000020_00000020_00000020", -- Loc 6C, 68, 64, 60
X"00000020_00000020_00000020_00000020", -- Loc 7C, 78, 74, 70
-- similar lines as above which read a word from the memory,
-- increment it, and then store it back to the same location.
-- There is only a RAW hazard, but other cases of memory disambiguation are not covered here.
-- a bunch of NOP instructions (ADD $0 $0 $0) to fill the space
X"00000020_00000020_00000020_00000020", -- Loc 8C, 88, 84, 80
X"00000020_00000020_00000020_00000020", -- Loc 9C, 98, 94, 90
X"00000020_00000020_00000020_00000020", -- Loc AC, A8, A4, A0
X"00000020_00000020_00000020_00000020", -- Loc BC, B8, B4, B0
X"00000020_00000020_00000020_00000020", -- Loc CC, C8, C4, C0
X"00000020_00000020_00000020_00000020", -- Loc DC, D8, D4, D0
X"00000020_00000020_00000020_00000020", -- Loc EC, E8, E4, E0
X"00000020_00000020_00000020_00000020", -- Loc FC, F8, F4, F0
X"00000020_00000020_00000020_00000020", -- Loc 10C, 108, 104, 100
X"00000020_00000020_00000020_00000020", -- Loc 11C, 118, 114, 110
X"00000020_00000020_00000020_00000020", -- Loc 12C, 128, 124, 120
X"00000020_00000020_00000020_00000020", -- Loc 13C, 138, 134, 130
X"00000020_00000020_00000020_00000020", -- Loc 14C, 148, 144, 140
X"00000020_00000020_00000020_00000020", -- Loc 15C, 158, 154, 150
X"00000020_00000020_00000020_00000020", -- Loc 16C, 168, 164, 160
X"00000020_00000020_00000020_00000020", -- Loc 17C, 178, 174, 170
X"00000020_00000020_00000020_00000020", -- Loc 18C, 188, 184, 180
X"00000020_00000020_00000020_00000020", -- Loc 19C, 198, 194, 190
X"00000020_00000020_00000020_00000020", -- Loc 1AC, 1A8, 1A4, 1A0
X"00000020_00000020_00000020_00000020", -- Loc 1BC, 1B8, 1B4, 1B0
X"00000020_00000020_00000020_00000020", -- Loc 1CC, 1C8, 1C4, 1C0
X"00000020_00000020_00000020_00000020", -- Loc 1DC, 1D8, 1D4, 1D0
X"00000020_00000020_00000020_00000020", -- Loc 1EC, 1E8, 1E4, 1E0
X"00000020_00000020_00000020_00000020", -- Loc 1FC, 1F8, 1F4, 1F0
X"00000020_00000020_00000020_00000020", -- Loc 20C, 208, 204, 200
X"00000020_00000020_00000020_00000020", -- Loc 21C, 218, 214, 221
X"00000020_00000020_00000020_00000020", -- Loc 22C, 228, 224, 220
X"00000020_00000020_00000020_00000020", -- Loc 23C, 238, 234, 230
X"00000020_00000020_00000020_00000020", -- Loc 24C, 248, 244, 240
X"00000020_00000020_00000020_00000020", -- Loc 25C, 258, 254, 250
X"00000020_00000020_00000020_00000020", -- Loc 26C, 268, 264, 260
X"00000020_00000020_00000020_00000020", -- Loc 27C, 278, 274, 270
X"00000020_00000020_00000020_00000020", -- Loc 28C, 288, 284, 280
X"00000020_00000020_00000020_00000020", -- Loc 29C, 298, 294, 290
X"00000020_00000020_00000020_00000020", -- Loc 2AC, 2A8, 2A4, 2A0
X"00000020_00000020_00000020_00000020", -- Loc 2BC, 2B8, 2B4, 2B0
X"00000020_00000020_00000020_00000020", -- Loc 2CC, 2C8, 2C4, 2C0
X"00000020_00000020_00000020_00000020", -- Loc 2DC, 2D8, 2D4, 2D0
X"00000020_00000020_00000020_00000020", -- Loc 2EC, 2E8, 2E4, 2E0
X"00000020_00000020_00000020_00000020", -- Loc 2FC, 2F8, 2F4, 2F0
X"00000020_00000020_00000020_00000020", -- Loc 30C, 308, 304, 300
X"00000020_00000020_00000020_00000020", -- Loc 31C, 318, 314, 331
X"00000020_00000020_00000020_00000020", -- Loc 32C, 328, 324, 320
X"00000020_00000020_00000020_00000020", -- Loc 33C, 338, 334, 330
X"00000020_00000020_00000020_00000020", -- Loc 34C, 348, 344, 340
X"00000020_00000020_00000020_00000020", -- Loc 35C, 358, 354, 350
X"00000020_00000020_00000020_00000020", -- Loc 36C, 368, 364, 360
X"00000020_00000020_00000020_00000020", -- Loc 37C, 378, 374, 370
X"00000020_00000020_00000020_00000020", -- Loc 38C, 388, 384, 380
X"00000020_00000020_00000020_00000020", -- Loc 39C, 398, 394, 390
X"00000020_00000020_00000020_00000020", -- Loc 3AC, 3A8, 3A4, 3A0
X"00000020_00000020_00000020_00000020", -- Loc 3BC, 3B8, 3B4, 3B0
-- the last 16 instructions are looping jump instructions
X"080000F3_080000F2_080000F1_080000F0", -- Loc 3CC, 3C8, 3C4, 3C0
X"080000F7_080000F6_080000F5_080000F4", -- Loc 3DC, 3D8, 3D4, 3D0
X"080000FB_080000FA_080000F9_080000F8", -- Loc 3EC, 3E8, 3E4, 3E0
X"080000FF_080000FE_080000FD_080000FC" -- Loc 3FC, 3F8, 3F4, 3F0
) ;
-- the last 16 instructions are looping jump instructions
-- of the type: loop: j loop
-- This is to make sure that neither instruction fetching
-- nor instruction execution proceeds beyond the end of this memory.
-- Loc 3C0 -- 080000F0 => J 240
-- Loc 3C4 -- 080000F1 => J 241
-- Loc 3C8 -- 080000F2 => J 242
-- Loc 3CC -- 080000F3 => J 243
--
-- Loc 3D0 -- 080000F4 => J 244
-- Loc 3D4 -- 080000F5 => J 245
-- Loc 3D8 -- 080000F6 => J 246
-- Loc 3DC -- 080000F7 => J 247
--
-- Loc 3E0 -- 080000F8 => J 248
-- Loc 3E4 -- 080000F9 => J 249
-- Loc 3E8 -- 080000FA => J 250
-- Loc 3EC -- 080000FB => J 251
--
-- Loc 3F0 -- 080000FC => J 252
-- Loc 3F4 -- 080000FD => J 253
-- Loc 3F8 -- 080000FE => J 254
-- Loc 3FC -- 080000FF => J 255
end package instr_stream_pkg;
-- -- No need for a package body here
-- package body instr_stream_pkg is
--
-- end package body instr_stream_pkg;
|
-- file: i_fetch_test_stream_instr_stream_pkg.vhd (just sws)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/27/2008
--
----------------------------------------------------------
--- EXPECTED RESULT
-- Physical register values changes as follows :
-- 32 => 00000010(h)
-- 33 => 00000020(h)
-- 34 => 00000030(h)
-- 35 => 00000040(h)
-- 36 => 00000050(h)
-- 37 => 00000060(h)
-- 38 => 00000070(h)
-- 39 => 00000080(h)
-- 40 => 00000001(h)
-- 41 => 00000002(h)
-- 42 => 000000B0(h)
-- 43 => 000000C0(h)
-- 44 => 000000D0(h)
-- 45 => 000000E0(h)
-- 46 => 000000F0(h)
-- 47 => 00000100(h)
------------------------------------------------------------------
library std, ieee;
use ieee.std_logic_1164.all;
package instr_stream_pkg is
constant DATA_WIDTH_CONSTANT : integer := 128; -- data width of of our cache
constant ADDR_WIDTH_CONSTANT : integer := 6; -- address width of our cache
-- type declarations
type mem_type is array (0 to (2**ADDR_WIDTH_CONSTANT)-1) of std_logic_vector((DATA_WIDTH_CONSTANT-1) downto 0);
signal mem : mem_type :=
(X"8C9E000C_8C9E0008_8C9E0004_8C9E0000", -- Loc 0C, 08, 04, 00
X"8C9E001C_8C9E0018_8C9E0014_8C9E0010", -- Loc 1C, 18, 14, 10
X"8C9E002C_8C9E0028_8C9E0024_8C9E0020", -- Loc 2C, 28, 24, 20
X"8C9E003C_8C9E0038_8C9E0034_8C9E0030", -- Loc 3C, 38, 34, 30
-- 16 sw instructions changing 16 locations with the content of $30 which is decimal 30 (1D hex)
-- "00000000000000000000000000011110", -- $30
-- Location:() | LW $30 ,0( $4) -- 8C9E0000
-- Location:() | LW $30 ,4( $4) -- 8C9E0004
X"00000020_00000020_00000020_00000020", --- Loc 4C, 48, 44, 40
X"00000020_00000020_00000020_00000020", -- Loc 5C, 58, 54, 50
X"00000020_00000020_00000020_00000020", -- Loc 6C, 68, 64, 60
X"00000020_00000020_00000020_00000020", -- Loc 7C, 78, 74, 70
-- similar lines as above which read a word from the memory,
-- increment it, and then store it back to the same location.
-- There is only a RAW hazard, but other cases of memory disambiguation are not covered here.
-- a bunch of NOP instructions (ADD $0 $0 $0) to fill the space
X"00000020_00000020_00000020_00000020", -- Loc 8C, 88, 84, 80
X"00000020_00000020_00000020_00000020", -- Loc 9C, 98, 94, 90
X"00000020_00000020_00000020_00000020", -- Loc AC, A8, A4, A0
X"00000020_00000020_00000020_00000020", -- Loc BC, B8, B4, B0
X"00000020_00000020_00000020_00000020", -- Loc CC, C8, C4, C0
X"00000020_00000020_00000020_00000020", -- Loc DC, D8, D4, D0
X"00000020_00000020_00000020_00000020", -- Loc EC, E8, E4, E0
X"00000020_00000020_00000020_00000020", -- Loc FC, F8, F4, F0
X"00000020_00000020_00000020_00000020", -- Loc 10C, 108, 104, 100
X"00000020_00000020_00000020_00000020", -- Loc 11C, 118, 114, 110
X"00000020_00000020_00000020_00000020", -- Loc 12C, 128, 124, 120
X"00000020_00000020_00000020_00000020", -- Loc 13C, 138, 134, 130
X"00000020_00000020_00000020_00000020", -- Loc 14C, 148, 144, 140
X"00000020_00000020_00000020_00000020", -- Loc 15C, 158, 154, 150
X"00000020_00000020_00000020_00000020", -- Loc 16C, 168, 164, 160
X"00000020_00000020_00000020_00000020", -- Loc 17C, 178, 174, 170
X"00000020_00000020_00000020_00000020", -- Loc 18C, 188, 184, 180
X"00000020_00000020_00000020_00000020", -- Loc 19C, 198, 194, 190
X"00000020_00000020_00000020_00000020", -- Loc 1AC, 1A8, 1A4, 1A0
X"00000020_00000020_00000020_00000020", -- Loc 1BC, 1B8, 1B4, 1B0
X"00000020_00000020_00000020_00000020", -- Loc 1CC, 1C8, 1C4, 1C0
X"00000020_00000020_00000020_00000020", -- Loc 1DC, 1D8, 1D4, 1D0
X"00000020_00000020_00000020_00000020", -- Loc 1EC, 1E8, 1E4, 1E0
X"00000020_00000020_00000020_00000020", -- Loc 1FC, 1F8, 1F4, 1F0
X"00000020_00000020_00000020_00000020", -- Loc 20C, 208, 204, 200
X"00000020_00000020_00000020_00000020", -- Loc 21C, 218, 214, 221
X"00000020_00000020_00000020_00000020", -- Loc 22C, 228, 224, 220
X"00000020_00000020_00000020_00000020", -- Loc 23C, 238, 234, 230
X"00000020_00000020_00000020_00000020", -- Loc 24C, 248, 244, 240
X"00000020_00000020_00000020_00000020", -- Loc 25C, 258, 254, 250
X"00000020_00000020_00000020_00000020", -- Loc 26C, 268, 264, 260
X"00000020_00000020_00000020_00000020", -- Loc 27C, 278, 274, 270
X"00000020_00000020_00000020_00000020", -- Loc 28C, 288, 284, 280
X"00000020_00000020_00000020_00000020", -- Loc 29C, 298, 294, 290
X"00000020_00000020_00000020_00000020", -- Loc 2AC, 2A8, 2A4, 2A0
X"00000020_00000020_00000020_00000020", -- Loc 2BC, 2B8, 2B4, 2B0
X"00000020_00000020_00000020_00000020", -- Loc 2CC, 2C8, 2C4, 2C0
X"00000020_00000020_00000020_00000020", -- Loc 2DC, 2D8, 2D4, 2D0
X"00000020_00000020_00000020_00000020", -- Loc 2EC, 2E8, 2E4, 2E0
X"00000020_00000020_00000020_00000020", -- Loc 2FC, 2F8, 2F4, 2F0
X"00000020_00000020_00000020_00000020", -- Loc 30C, 308, 304, 300
X"00000020_00000020_00000020_00000020", -- Loc 31C, 318, 314, 331
X"00000020_00000020_00000020_00000020", -- Loc 32C, 328, 324, 320
X"00000020_00000020_00000020_00000020", -- Loc 33C, 338, 334, 330
X"00000020_00000020_00000020_00000020", -- Loc 34C, 348, 344, 340
X"00000020_00000020_00000020_00000020", -- Loc 35C, 358, 354, 350
X"00000020_00000020_00000020_00000020", -- Loc 36C, 368, 364, 360
X"00000020_00000020_00000020_00000020", -- Loc 37C, 378, 374, 370
X"00000020_00000020_00000020_00000020", -- Loc 38C, 388, 384, 380
X"00000020_00000020_00000020_00000020", -- Loc 39C, 398, 394, 390
X"00000020_00000020_00000020_00000020", -- Loc 3AC, 3A8, 3A4, 3A0
X"00000020_00000020_00000020_00000020", -- Loc 3BC, 3B8, 3B4, 3B0
-- the last 16 instructions are looping jump instructions
X"080000F3_080000F2_080000F1_080000F0", -- Loc 3CC, 3C8, 3C4, 3C0
X"080000F7_080000F6_080000F5_080000F4", -- Loc 3DC, 3D8, 3D4, 3D0
X"080000FB_080000FA_080000F9_080000F8", -- Loc 3EC, 3E8, 3E4, 3E0
X"080000FF_080000FE_080000FD_080000FC" -- Loc 3FC, 3F8, 3F4, 3F0
) ;
-- the last 16 instructions are looping jump instructions
-- of the type: loop: j loop
-- This is to make sure that neither instruction fetching
-- nor instruction execution proceeds beyond the end of this memory.
-- Loc 3C0 -- 080000F0 => J 240
-- Loc 3C4 -- 080000F1 => J 241
-- Loc 3C8 -- 080000F2 => J 242
-- Loc 3CC -- 080000F3 => J 243
--
-- Loc 3D0 -- 080000F4 => J 244
-- Loc 3D4 -- 080000F5 => J 245
-- Loc 3D8 -- 080000F6 => J 246
-- Loc 3DC -- 080000F7 => J 247
--
-- Loc 3E0 -- 080000F8 => J 248
-- Loc 3E4 -- 080000F9 => J 249
-- Loc 3E8 -- 080000FA => J 250
-- Loc 3EC -- 080000FB => J 251
--
-- Loc 3F0 -- 080000FC => J 252
-- Loc 3F4 -- 080000FD => J 253
-- Loc 3F8 -- 080000FE => J 254
-- Loc 3FC -- 080000FF => J 255
end package instr_stream_pkg;
-- -- No need for a package body here
-- package body instr_stream_pkg is
--
-- end package body instr_stream_pkg;
|
--========================================================================
-- alu.vhd :: PDP-11 16-bit ALU
--
-- (c) Scott L. Baker, Sierra Circuit Design
--========================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use work.my_types.all;
entity ALU is
port (
COUT : out std_logic; -- carry out
ZERO : out std_logic; -- zero
OVFL : out std_logic; -- overflow
SIGN : out std_logic; -- sign bit
RBUS : out std_logic_vector(15 downto 0); -- result bus
A : in std_logic_vector(15 downto 0); -- operand A
B : in std_logic_vector(15 downto 0); -- operand B
OP : in ALU_OP_TYPE; -- micro op
BYTE_OP : in std_logic; -- 1=byte/0=word
DIV_OP : in std_logic; -- divide op
DIV_SBIT : in std_logic; -- divide sign bit
CIN : in std_logic -- carry in
);
end ALU;
architecture BEHAVIORAL of ALU is
--=================================================================
-- Types, component, and signal definitions
--=================================================================
--=================================================================
-- A input mux selects (buffer, invert, or supply a constant)
--=================================================================
type AMUX_SEL_TYPE is (
ALL_ZERO, -- all zeros
SWAP, -- swap bytes
BUF, -- buffer
INV -- invert
);
--=================================================================
-- B input mux selects (buffer, invert, or supply a constant)
--=================================================================
type BMUX_SEL_TYPE is (
ALL_ZERO, -- all zeros
TWO, -- two
MINUS1, -- all ones
MINUS2, -- minus two
BUF, -- buffer
INV -- invert
);
--=================================================================
-- Ouput mux selects ( xor, or, and, shift, or sum)
--=================================================================
type OMUX_SEL_TYPE is (
SEL_XOR, -- logical xor
SEL_OR, -- logical or
SEL_AND, -- logical and
SEL_SUM, -- arithmetic sum
SEL_ASL, -- arithmetic shift left
SEL_ASR, -- arithmetic shift right
SEL_LSR, -- logical shift right
SEL_ROR -- rotate right
);
-- ALU mux selects
signal ASEL : AMUX_SEL_TYPE;
signal BSEL : BMUX_SEL_TYPE;
signal RSEL : OMUX_SEL_TYPE;
-- ALU busses
signal AX : std_logic_vector(16 downto 0);
signal BX : std_logic_vector(16 downto 0);
signal AXB : std_logic_vector(16 downto 0);
signal SUM : std_logic_vector(16 downto 0);
signal RBI : std_logic_vector(15 downto 0);
-- propagate and generate
signal P : std_logic_vector(15 downto 0);
signal G : std_logic_vector(15 downto 0);
-- flags
signal V : std_logic; -- overflow
signal Z : std_logic; -- zero
signal N : std_logic; -- sign bit
-- internal carries
signal CO : std_logic;
signal CIN1 : std_logic;
signal CX : std_logic_vector(16 downto 0);
-- misc
signal ASE : std_logic_vector(8 downto 0);
signal BSE : std_logic_vector(8 downto 0);
begin
--================================================================
-- Start of the behavioral description
--================================================================
--====================
-- Opcode Decoding
--====================
OPCODE_DECODING:
process(OP, CIN)
begin
-- Default values
ASEL <= BUF;
BSEL <= BUF;
RSEL <= SEL_SUM;
CIN1 <= '0';
case OP is
when OP_ADD =>
-- A plus B
when OP_ADC =>
-- A plus Cin
BSEL <= ALL_ZERO;
CIN1 <= CIN;
when OP_SUBB =>
-- A minus B
BSEL <= INV;
CIN1 <= '1';
when OP_SUBA =>
-- B minus A
ASEL <= INV;
CIN1 <= '1';
when OP_SBC =>
-- A minus CIN
BSEL <= MINUS1;
CIN1 <= not CIN;
when OP_INCA1 =>
-- increment A
BSEL <= ALL_ZERO;
CIN1 <= '1';
when OP_INCA2 =>
-- increment A by 2
BSEL <= TWO;
CIN1 <= '0';
when OP_DECA1 =>
-- decrement A
BSEL <= MINUS1;
when OP_DECA2 =>
-- decrement A by 2
BSEL <= MINUS2;
when OP_INV =>
-- 1's complement A
ASEL <= INV;
BSEL <= ALL_ZERO;
RSEL <= SEL_OR;
when OP_NEG =>
-- 2's complement A
ASEL <= INV;
BSEL <= ALL_ZERO;
CIN1 <= '1';
when OP_AND =>
-- A and B
RSEL <= SEL_AND;
when OP_BIC =>
-- not A and B
ASEL <= INV;
RSEL <= SEL_AND;
when OP_CZC =>
-- A and not B
BSEL <= INV;
RSEL <= SEL_AND;
when OP_SZC =>
-- not A and B
ASEL <= INV;
RSEL <= SEL_AND;
when OP_OR =>
-- A or B
RSEL <= SEL_OR;
when OP_XOR =>
-- A xor B
RSEL <= SEL_XOR;
when OP_TA =>
-- transfer A
BSEL <= ALL_ZERO;
RSEL <= SEL_OR;
when OP_TB =>
-- transfer B
ASEL <= ALL_ZERO;
RSEL <= SEL_OR;
when OP_SWP =>
-- swap bytes of A
BSEL <= ALL_ZERO;
ASEL <= SWAP;
RSEL <= SEL_OR;
when OP_ASL =>
-- arithmetic shift left A
BSEL <= ALL_ZERO;
RSEL <= SEL_ASL;
when OP_LSR =>
-- logical shift right A
BSEL <= ALL_ZERO;
RSEL <= SEL_LSR;
when OP_ASR =>
-- logical shift right A
BSEL <= ALL_ZERO;
RSEL <= SEL_ASR;
when OP_ROR =>
-- rotate right A
BSEL <= ALL_ZERO;
RSEL <= SEL_ROR;
when OP_ONES =>
-- output all ones
ASEL <= ALL_ZERO;
BSEL <= MINUS1;
RSEL <= SEL_OR;
when others =>
-- output all zeros
ASEL <= ALL_ZERO;
BSEL <= ALL_ZERO;
RSEL <= SEL_OR;
end case;
end process;
BSE <= (others => B(7));
ASE <= (others => A(7));
--=========================
-- Operand A mux
--=========================
OPERAND_A_MUX:
process(ASEL, A, ASE, BYTE_OP)
begin
case ASEL is
when BUF =>
-- A
AX <= A(15) & A;
if (BYTE_OP = '1') then
AX <= ASE & A(7 downto 0);
end if;
when INV =>
-- not A
AX <= not (A(15) & A);
if (BYTE_OP = '1') then
AX <= not (ASE & A(7 downto 0));
end if;
when SWAP =>
-- swap bytes
AX <= '0' & A(7 downto 0) & A(15 downto 8);
when others =>
-- zero
AX <= (others => '0');
end case;
end process;
--=========================
-- Operand B mux
--=========================
OPERAND_B_MUX:
process(BSEL, B, BSE, BYTE_OP, DIV_OP, DIV_SBIT)
begin
case BSEL is
when MINUS1 =>
-- for decrement
BX <= (others => '1');
when MINUS2 =>
-- for decrement by 2
BX <= "11111111111111110";
when TWO =>
-- for increment by 2
BX <= "00000000000000010";
when BUF =>
-- B
BX <= B(15) & B;
if (BYTE_OP = '1') then
BX <= BSE & B(7 downto 0);
end if;
if (DIV_OP = '1') then
BX <= (DIV_SBIT or B(15)) & B;
end if;
when INV =>
-- not B
BX <= not(B(15) & B);
if (BYTE_OP = '1') then
BX <= not (BSE & B(7 downto 0));
end if;
when others =>
-- zero
BX <= (others => '0');
end case;
end process;
--================================================
-- ALU output mux
--================================================
ALU_OUTPUT_MUX:
process(RSEL, AXB, SUM, B, P, G, CX, BYTE_OP, DIV_OP, DIV_SBIT)
begin
case RSEL is
when SEL_ASL =>
-- arithmetic shift left
RBI <= P(14 downto 0) & '0';
CO <= P(15);
when SEL_LSR =>
-- logical shift right
RBI <= '0' & P(15 downto 1);
CO <= P(0);
when SEL_ASR =>
-- arithmetic shift right
RBI <= P(15) & P(15 downto 1);
CO <= P(0);
when SEL_ROR =>
-- right rotate
RBI <= P(0) & P(15 downto 1);
CO <= P(0);
when SEL_XOR =>
-- A xor B
RBI <= AXB(15 downto 0);
CO <= P(15);
when SEL_OR =>
-- A or B
RBI <= P(15 downto 0);
CO <= P(15);
when SEL_AND =>
-- A and B
RBI <= G(15 downto 0);
CO <= P(15);
when others =>
-- Arithmetic ops
RBI <= SUM(15 downto 0);
CO <= CX(16);
end case;
-- for byte operations
if (BYTE_OP = '1') then
CO <= CX(8);
end if;
-- for divide
if (DIV_OP = '1') then
CO <= CX(16) or DIV_SBIT;
end if;
end process;
RBUS <= RBI;
--=====================================
-- Propagate and Generate
--=====================================
G <= AX(15 downto 0) and BX(15 downto 0);
P <= AX(15 downto 0) or BX(15 downto 0);
--=====================================
-- carry look-ahead logic
--=====================================
CX(16) <= G(15) or (P(15) and CX(15));
CX(15) <= G(14) or (P(14) and CX(14));
CX(14) <= G(13) or (P(13) and CX(13));
CX(13) <= G(12) or (P(12) and CX(12));
CX(12) <= G(11) or (P(11) and CX(11));
CX(11) <= G(10) or (P(10) and CX(10));
CX(10) <= G(9) or (P(9) and CX(9));
CX(9) <= G(8) or (P(8) and CX(8));
CX(8) <= G(7) or (P(7) and CX(7));
CX(7) <= G(6) or (P(6) and CX(6));
CX(6) <= G(5) or (P(5) and CX(5));
CX(5) <= G(4) or (P(4) and CX(4));
CX(4) <= G(3) or (P(3) and CX(3));
CX(3) <= G(2) or (P(2) and CX(2));
CX(2) <= G(1) or (P(1) and CX(1));
CX(1) <= G(0) or (P(0) and CX(0));
CX(0) <= CIN1;
--=========================
-- ALU SUM
--=========================
AXB <= AX xor BX;
SUM <= CX xor AXB;
--=========================
-- Overflow flag
--=========================
OVERFLOW_FLAG:
process(BYTE_OP, A, RSEL, SUM)
begin
V <= '0';
if (RSEL = SEL_SUM) then
V <= SUM(16) xor SUM(15);
if (BYTE_OP = '1') then
V <= SUM(8) xor SUM(7);
end if;
end if;
-- for left shifts set when sign changes
if (RSEL = SEL_ASL) then
V <= A(15) xor SUM(14);
end if;
end process;
--=========================
-- Zero flag
--=========================
ZERO_FLAG:
process(BYTE_OP, RBI)
begin
Z <= (not(RBI(15) or RBI(14) or RBI(13) or RBI(12) or
RBI(11) or RBI(10) or RBI(9) or RBI(8) or
RBI(7) or RBI(6) or RBI(5) or RBI(4) or
RBI(3) or RBI(2) or RBI(1) or RBI(0)));
if (BYTE_OP = '1') then
Z <= (not(RBI(7) or RBI(6) or RBI(5) or RBI(4) or
RBI(3) or RBI(2) or RBI(1) or RBI(0)));
end if;
end process;
--=========================
-- Sign-bit Flag
--=========================
SIGN_FLAG:
process(BYTE_OP, RBI)
begin
N <= RBI(15);
if (BYTE_OP = '1') then
N <= RBI(7);
end if;
end process;
--=========================
-- Flags
--=========================
-- zero
ZERO <= Z;
-- carry out
COUT <= CO;
-- overflow
OVFL <= V;
-- sign
SIGN <= N;
end BEHAVIORAL;
|
--
-- Project: Aurora Module Generator version 2.4
--
-- Date: $Date: 2005/11/07 21:30:54 $
-- Tag: $Name: i+IP+98818 $
-- File: $RCSfile: rx_ll_ufc_datapath_vhd.ejava,v $
-- Rev: $Revision: 1.1.2.4 $
--
-- Company: Xilinx
-- Contributors: R. K. Awalt, B. L. Woodard, N. Gulstone
--
-- Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
-- INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
-- PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-- ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-- APPLICATION OR STANDARD, XILINX IS MAKING NO
-- REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-- FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
-- RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
-- REQUIRE FOR YOUR IMPLEMENTATION. XILINX
-- EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
-- RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
-- INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-- FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
-- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE.
--
-- (c) Copyright 2004 Xilinx, Inc.
-- All rights reserved.
--
--
-- RX_LL_UFC_DATAPATH
--
-- Author: Nigel Gulstone
-- Xilinx - Embedded Networking System Engineering Group
--
-- VHDL Translation: B. Woodard, N. Gulstone
--
-- Description: the RX_LL_UFC_DATAPATH module takes UFC data in Aurora format
-- and transforms it to LocalLink formatted data
--
-- This module supports 1 2-byte lane designs
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity RX_LL_UFC_DATAPATH is
port (
--Traffic Separator Interface
UFC_DATA : in std_logic_vector(0 to 15);
UFC_DATA_V : in std_logic;
UFC_MESSAGE_START : in std_logic;
UFC_START : in std_logic;
--LocalLink UFC Interface
UFC_RX_DATA : out std_logic_vector(0 to 15);
UFC_RX_REM : out std_logic;
UFC_RX_SRC_RDY_N : out std_logic;
UFC_RX_SOF_N : out std_logic;
UFC_RX_EOF_N : out std_logic;
--System Interface
USER_CLK : in std_logic;
RESET : in std_logic
);
end RX_LL_UFC_DATAPATH;
architecture RTL of RX_LL_UFC_DATAPATH is
-- Parameter Declarations --
constant DLY : time := 1 ns;
-- External Register Declarations --
signal UFC_RX_DATA_Buffer : std_logic_vector(0 to 15);
signal UFC_RX_REM_Buffer : std_logic;
signal UFC_RX_SRC_RDY_N_Buffer : std_logic;
signal UFC_RX_SOF_N_Buffer : std_logic;
signal UFC_RX_EOF_N_Buffer : std_logic;
-- Internal Register Declarations --
signal ufc_storage_data_r : std_logic_vector(0 to 15);
signal ufc_storage_v_r : std_logic;
signal ufc_start_r : std_logic;
signal ufc_start_delayed_r : std_logic;
begin
UFC_RX_DATA <= UFC_RX_DATA_Buffer;
UFC_RX_REM <= UFC_RX_REM_Buffer;
UFC_RX_SRC_RDY_N <= UFC_RX_SRC_RDY_N_Buffer;
UFC_RX_SOF_N <= UFC_RX_SOF_N_Buffer;
UFC_RX_EOF_N <= UFC_RX_EOF_N_Buffer;
-- Main Body of Code --
-- All input goes into a storage register before it is sent on to the output.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
ufc_storage_data_r <= UFC_DATA after DLY;
end if;
end process;
-- Keep track of whether or not there is data in storage.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
if (RESET = '1') then
ufc_storage_v_r <= '0' after DLY;
else
ufc_storage_v_r <= UFC_DATA_V after DLY;
end if;
end if;
end process;
-- Output data is registered.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
UFC_RX_DATA_Buffer <= ufc_storage_data_r after DLY;
end if;
end process;
-- Assert the UFC_RX_SRC_RDY_N signal when there is data in storage.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
if (RESET = '1') then
UFC_RX_SRC_RDY_N_Buffer <= '1' after DLY;
else
UFC_RX_SRC_RDY_N_Buffer <= not ufc_storage_v_r after DLY;
end if;
end if;
end process;
-- Hold start of frame until it can be asserted with data.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
ufc_start_r <= UFC_START after DLY;
ufc_start_delayed_r <= ufc_start_r after DLY;
end if;
end process;
-- Register the start of frame signal for use with the LocalLink output.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
UFC_RX_SOF_N_Buffer <= not ufc_start_delayed_r after DLY;
end if;
end process;
-- Assert EOF when the storage goes from full to empty.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
UFC_RX_EOF_N_Buffer <= not (not UFC_DATA_V and ufc_storage_v_r) after DLY;
end if;
end process;
-- REM is always high in the single lane case.
UFC_RX_REM_Buffer <= '1';
end RTL;
|
--
-- Project: Aurora Module Generator version 2.4
--
-- Date: $Date: 2005/11/07 21:30:54 $
-- Tag: $Name: i+IP+98818 $
-- File: $RCSfile: rx_ll_ufc_datapath_vhd.ejava,v $
-- Rev: $Revision: 1.1.2.4 $
--
-- Company: Xilinx
-- Contributors: R. K. Awalt, B. L. Woodard, N. Gulstone
--
-- Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
-- INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
-- PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-- ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-- APPLICATION OR STANDARD, XILINX IS MAKING NO
-- REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-- FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
-- RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
-- REQUIRE FOR YOUR IMPLEMENTATION. XILINX
-- EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
-- RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
-- INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-- FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
-- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE.
--
-- (c) Copyright 2004 Xilinx, Inc.
-- All rights reserved.
--
--
-- RX_LL_UFC_DATAPATH
--
-- Author: Nigel Gulstone
-- Xilinx - Embedded Networking System Engineering Group
--
-- VHDL Translation: B. Woodard, N. Gulstone
--
-- Description: the RX_LL_UFC_DATAPATH module takes UFC data in Aurora format
-- and transforms it to LocalLink formatted data
--
-- This module supports 1 2-byte lane designs
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity RX_LL_UFC_DATAPATH is
port (
--Traffic Separator Interface
UFC_DATA : in std_logic_vector(0 to 15);
UFC_DATA_V : in std_logic;
UFC_MESSAGE_START : in std_logic;
UFC_START : in std_logic;
--LocalLink UFC Interface
UFC_RX_DATA : out std_logic_vector(0 to 15);
UFC_RX_REM : out std_logic;
UFC_RX_SRC_RDY_N : out std_logic;
UFC_RX_SOF_N : out std_logic;
UFC_RX_EOF_N : out std_logic;
--System Interface
USER_CLK : in std_logic;
RESET : in std_logic
);
end RX_LL_UFC_DATAPATH;
architecture RTL of RX_LL_UFC_DATAPATH is
-- Parameter Declarations --
constant DLY : time := 1 ns;
-- External Register Declarations --
signal UFC_RX_DATA_Buffer : std_logic_vector(0 to 15);
signal UFC_RX_REM_Buffer : std_logic;
signal UFC_RX_SRC_RDY_N_Buffer : std_logic;
signal UFC_RX_SOF_N_Buffer : std_logic;
signal UFC_RX_EOF_N_Buffer : std_logic;
-- Internal Register Declarations --
signal ufc_storage_data_r : std_logic_vector(0 to 15);
signal ufc_storage_v_r : std_logic;
signal ufc_start_r : std_logic;
signal ufc_start_delayed_r : std_logic;
begin
UFC_RX_DATA <= UFC_RX_DATA_Buffer;
UFC_RX_REM <= UFC_RX_REM_Buffer;
UFC_RX_SRC_RDY_N <= UFC_RX_SRC_RDY_N_Buffer;
UFC_RX_SOF_N <= UFC_RX_SOF_N_Buffer;
UFC_RX_EOF_N <= UFC_RX_EOF_N_Buffer;
-- Main Body of Code --
-- All input goes into a storage register before it is sent on to the output.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
ufc_storage_data_r <= UFC_DATA after DLY;
end if;
end process;
-- Keep track of whether or not there is data in storage.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
if (RESET = '1') then
ufc_storage_v_r <= '0' after DLY;
else
ufc_storage_v_r <= UFC_DATA_V after DLY;
end if;
end if;
end process;
-- Output data is registered.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
UFC_RX_DATA_Buffer <= ufc_storage_data_r after DLY;
end if;
end process;
-- Assert the UFC_RX_SRC_RDY_N signal when there is data in storage.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
if (RESET = '1') then
UFC_RX_SRC_RDY_N_Buffer <= '1' after DLY;
else
UFC_RX_SRC_RDY_N_Buffer <= not ufc_storage_v_r after DLY;
end if;
end if;
end process;
-- Hold start of frame until it can be asserted with data.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
ufc_start_r <= UFC_START after DLY;
ufc_start_delayed_r <= ufc_start_r after DLY;
end if;
end process;
-- Register the start of frame signal for use with the LocalLink output.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
UFC_RX_SOF_N_Buffer <= not ufc_start_delayed_r after DLY;
end if;
end process;
-- Assert EOF when the storage goes from full to empty.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
UFC_RX_EOF_N_Buffer <= not (not UFC_DATA_V and ufc_storage_v_r) after DLY;
end if;
end process;
-- REM is always high in the single lane case.
UFC_RX_REM_Buffer <= '1';
end RTL;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:59:18 06/17/2009
-- Design Name:
-- Module Name: /home/jagron/uark_research/uark_ht_trunk/src/hardware/MyRepository/pcores/plb_cond_vars_v1_00_a/hdl/vhdl//user_logic_tb.vhd
-- Project Name: ise_proj
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: user_logic
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY user_logic_tb IS
END user_logic_tb;
ARCHITECTURE behavior OF user_logic_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT user_logic
PORT(
Soft_Reset : IN std_logic;
Reset_Done : OUT std_logic;
interrupts_in : in std_logic_vector(0 to 3);
Bus2IP_Clk : IN std_logic;
Bus2IP_Reset : IN std_logic;
Bus2IP_Addr : IN std_logic_vector(0 to 31);
Bus2IP_Data : IN std_logic_vector(0 to 31);
Bus2IP_BE : IN std_logic_vector(0 to 3);
Bus2IP_RdCE : IN std_logic_vector(0 to 4);
Bus2IP_WrCE : IN std_logic_vector(0 to 4);
IP2Bus_Data : OUT std_logic_vector(0 to 31);
IP2Bus_RdAck : OUT std_logic;
IP2Bus_WrAck : OUT std_logic;
IP2Bus_Error : OUT std_logic;
IP2Bus_MstRd_Req : OUT std_logic;
IP2Bus_MstWr_Req : OUT std_logic;
IP2Bus_Mst_Addr : OUT std_logic_vector(0 to 31);
IP2Bus_Mst_BE : OUT std_logic_vector(0 to 3);
IP2Bus_Mst_Lock : OUT std_logic;
IP2Bus_Mst_Reset : OUT std_logic;
Bus2IP_Mst_CmdAck : IN std_logic;
Bus2IP_Mst_Cmplt : IN std_logic;
Bus2IP_Mst_Error : IN std_logic;
Bus2IP_Mst_Rearbitrate : IN std_logic;
Bus2IP_Mst_Cmd_Timeout : IN std_logic;
Bus2IP_MstRd_d : IN std_logic_vector(0 to 31);
Bus2IP_MstRd_src_rdy_n : IN std_logic;
IP2Bus_MstWr_d : OUT std_logic_vector(0 to 31);
Bus2IP_MstWr_dst_rdy_n : IN std_logic
);
END COMPONENT;
--Inputs
signal Soft_Reset : std_logic := '0';
signal interrupts_in : std_logic_vector(0 to 3) := (others => '0');
signal Bus2IP_Clk : std_logic := '0';
signal Bus2IP_Reset : std_logic := '0';
signal Bus2IP_Addr : std_logic_vector(0 to 31) := (others => '0');
signal Bus2IP_Data : std_logic_vector(0 to 31) := (others => '0');
signal Bus2IP_BE : std_logic_vector(0 to 3) := (others => '0');
signal Bus2IP_RdCE : std_logic_vector(0 to 4) := (others => '0');
signal Bus2IP_WrCE : std_logic_vector(0 to 4) := (others => '0');
signal Bus2IP_Mst_CmdAck : std_logic := '0';
signal Bus2IP_Mst_Cmplt : std_logic := '0';
signal Bus2IP_Mst_Error : std_logic := '0';
signal Bus2IP_Mst_Rearbitrate : std_logic := '0';
signal Bus2IP_Mst_Cmd_Timeout : std_logic := '0';
signal Bus2IP_MstRd_d : std_logic_vector(0 to 31) := (others => '0');
signal Bus2IP_MstRd_src_rdy_n : std_logic := '0';
signal Bus2IP_MstWr_dst_rdy_n : std_logic := '0';
--Outputs
signal Reset_Done : std_logic;
signal IP2Bus_Data : std_logic_vector(0 to 31);
signal IP2Bus_RdAck : std_logic;
signal IP2Bus_WrAck : std_logic;
signal IP2Bus_Error : std_logic;
signal IP2Bus_MstRd_Req : std_logic;
signal IP2Bus_MstWr_Req : std_logic;
signal IP2Bus_Mst_Addr : std_logic_vector(0 to 31);
signal IP2Bus_Mst_BE : std_logic_vector(0 to 3);
signal IP2Bus_Mst_Lock : std_logic;
signal IP2Bus_Mst_Reset : std_logic;
signal IP2Bus_MstWr_d : std_logic_vector(0 to 31);
constant clock_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: user_logic PORT MAP (
Soft_Reset => Soft_Reset,
Reset_Done => Reset_Done,
interrupts_in => interrupts_in,
Bus2IP_Clk => Bus2IP_Clk,
Bus2IP_Reset => Bus2IP_Reset,
Bus2IP_Addr => Bus2IP_Addr,
Bus2IP_Data => Bus2IP_Data,
Bus2IP_BE => Bus2IP_BE,
Bus2IP_RdCE => Bus2IP_RdCE,
Bus2IP_WrCE => Bus2IP_WrCE,
IP2Bus_Data => IP2Bus_Data,
IP2Bus_RdAck => IP2Bus_RdAck,
IP2Bus_WrAck => IP2Bus_WrAck,
IP2Bus_Error => IP2Bus_Error,
IP2Bus_MstRd_Req => IP2Bus_MstRd_Req,
IP2Bus_MstWr_Req => IP2Bus_MstWr_Req,
IP2Bus_Mst_Addr => IP2Bus_Mst_Addr,
IP2Bus_Mst_BE => IP2Bus_Mst_BE,
IP2Bus_Mst_Lock => IP2Bus_Mst_Lock,
IP2Bus_Mst_Reset => IP2Bus_Mst_Reset,
Bus2IP_Mst_CmdAck => Bus2IP_Mst_CmdAck,
Bus2IP_Mst_Cmplt => Bus2IP_Mst_Cmplt,
Bus2IP_Mst_Error => Bus2IP_Mst_Error,
Bus2IP_Mst_Rearbitrate => Bus2IP_Mst_Rearbitrate,
Bus2IP_Mst_Cmd_Timeout => Bus2IP_Mst_Cmd_Timeout,
Bus2IP_MstRd_d => Bus2IP_MstRd_d,
Bus2IP_MstRd_src_rdy_n => Bus2IP_MstRd_src_rdy_n,
IP2Bus_MstWr_d => IP2Bus_MstWr_d,
Bus2IP_MstWr_dst_rdy_n => Bus2IP_MstWr_dst_rdy_n
);
Bus2IP_Clk_process :process
begin
Bus2IP_Clk <= '0';
wait for clock_period/2;
Bus2IP_Clk <= '1';
wait for clock_period/2;
end process;
ACK_proc : process
begin
wait until IP2Bus_MstRd_Req = '1';
Bus2IP_Mst_Cmplt <= '1';
Bus2IP_Mst_CmdAck <= '1';
wait until IP2Bus_MstRd_Req = '0';
Bus2IP_Mst_Cmplt <= '0';
Bus2IP_Mst_CmdAck <= '0';
wait for 5*clock_period;
end process;
-- Stimulus process
stim_proc: process
begin
wait for clock_period*10;
-- Reset the core
Soft_Reset <= '1';
wait until Reset_Done = '1';
wait for clock_period*5;
Soft_Reset <= '0';
wait for 5*clock_period;
-- Perform an ASSOC
Bus2IP_Addr <= x"11010300";
Bus2IP_RdCE <= (others => '1');
wait until IP2Bus_RdAck = '1';
Bus2IP_Addr <= (others => '0');
Bus2IP_RdCE <= (others => '0');
wait for 10*clock_period;
-- Perform an ASSOC
Bus2IP_Addr <= x"11010440";
Bus2IP_RdCE <= (others => '1');
wait until IP2Bus_RdAck = '1';
Bus2IP_Addr <= (others => '0');
Bus2IP_RdCE <= (others => '0');
wait for 10*clock_period;
-- Perform an ASSOC
Bus2IP_Addr <= x"11010580";
Bus2IP_RdCE <= (others => '1');
wait until IP2Bus_RdAck = '1';
Bus2IP_Addr <= (others => '0');
Bus2IP_RdCE <= (others => '0');
wait for 10*clock_period;
-- Perform an ASSOC
Bus2IP_Addr <= x"110109C0";
Bus2IP_RdCE <= (others => '1');
wait until IP2Bus_RdAck = '1';
Bus2IP_Addr <= (others => '0');
Bus2IP_RdCE <= (others => '0');
wait for 10*clock_period;
-- Cause interrupts
interrupts_in <= x"8";
wait for 100*clock_period;
interrupts_in <= interrupts_in - 1;
wait for 100*clock_period;
interrupts_in <= interrupts_in - 1;
wait for 100*clock_period;
interrupts_in <= interrupts_in - 1;
wait for 100*clock_period;
interrupts_in <= interrupts_in - 1;
wait for 100*clock_period;
interrupts_in <= interrupts_in - 1;
wait;
end process;
END;
|
-- -----------------------------------------------------------------------------
-- Title : Standard VITAL_Primitives Package
-- : $Revision$
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers : IEEE DASC Timing Working Group (TWG), PAR 1076.4
-- :
-- Purpose : This packages defines standard types, constants, functions
-- : and procedures for use in developing ASIC models.
-- : Specifically a set of logic primitives are defined.
-- :
-- Known Errors :
-- :
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the objects (types, subtypes, constants, functions,
-- : procedures ... etc.) that can be used by a user. The package
-- : body shall be considered the formal definition of the
-- : semantics of this package. Tool developers may choose to
-- : implement the package body in the most efficient manner
-- : available to them.
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Acknowledgments:
-- This code was originally developed under the "VHDL Initiative Toward ASIC
-- Libraries" (VITAL), an industry sponsored initiative. Technical
-- Director: William Billowitch, VHDL Technology Group; U.S. Coordinator:
-- Steve Schultz; Steering Committee Members: Victor Berman, Cadence Design
-- Systems; Oz Levia, Synopsys Inc.; Ray Ryan, Ryan & Ryan; Herman van Beek,
-- Texas Instruments; Victor Martin, Hewlett-Packard Company.
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Modification History :
-- ----------------------------------------------------------------------------
-- Version No:|Auth:| Mod.Date:| Changes Made:
-- v95.0 A | | 06/02/95 | Initial ballot draft 1995
-- ----------------------------------------------------------------------------
-- v95.3 | ddl | 09/24/96 | #236 - VitalTruthTable DataIn should be of
-- | | | of class SIGNAL (PROPOSED)
-- ----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
USE IEEE.VITAL_Timing.ALL;
PACKAGE VITAL_Primitives IS
-- ------------------------------------------------------------------------
-- Type and Subtype Declarations
-- ------------------------------------------------------------------------
-- For Truth and State Tables
SUBTYPE VitalTruthSymbolType IS VitalTableSymbolType RANGE 'X' TO 'Z';
SUBTYPE VitalStateSymbolType IS VitalTableSymbolType RANGE '/' TO 'S';
TYPE VitalTruthTableType IS ARRAY ( NATURAL RANGE <>, NATURAL RANGE <> )
OF VitalTruthSymbolType;
TYPE VitalStateTableType IS ARRAY ( NATURAL RANGE <>, NATURAL RANGE <> )
OF VitalStateSymbolType;
-- ---------------------------------
-- Default values used by primitives
-- ---------------------------------
CONSTANT VitalDefDelay01 : VitalDelayType01; -- Propagation delays
CONSTANT VitalDefDelay01Z : VitalDelayType01Z;
-- ------------------------------------------------------------------------
-- VITAL Primitives
--
-- The primitives packages contains a collections of common gates,
-- including AND, OR, XOR, NAND, NOR, XNOR, BUF, INV, MUX and DECODER
-- functions. In addition, for sequential devices, a STATE TABLE construct
-- is provided. For complex functions a modeler may wish to use either
-- a collection of connected VITAL primitives, or a TRUTH TABLE construct.
--
-- For each primitive a Function and Procedure is provided. The primitive
-- functions are provided to support behavioral modeling styles. The
-- primitive procedures are provided to support structural modeling styles.
--
-- The procedures wait internally for an event on an input signal, compute
-- the new result, perform glitch handling, schedule transaction on the
-- output signals, and wait for future input events. All of the functional
-- (logic) input or output parameters of the primitive procedures are
-- signals. All the other parameters are constants.
--
-- The procedure primitives are parameterized for separate path delays
-- from each input signal. All path delays default to 0 ns.
--
-- The sequential primitive functions compute the defined function and
-- return a value of type std_ulogic or std_logic_vector. All parameters
-- of the primitive functions are constants of mode IN.
--
-- The primitives are based on 1164 operators. The user may also elect to
-- express functions using the 1164 operators as well. These styles are
-- all equally acceptable methods for device modeling.
--
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: N-input logic device function calls:
-- VitalAND VitalOR VitalXOR
-- VitalNAND VitalNOR VitalXNOR
--
-- Description: The function calls return the evaluated logic function
-- corresponding to the function name.
--
-- Arguments:
--
-- IN Type Description
-- Data std_logic_vector The input signals for the n-bit
-- wide logic functions.
-- ResultMap VitalResultMapType The output signal strength
-- result map to modify default
-- result mapping.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic The evaluated logic function of
-- the n-bit wide primitives.
--
-- -------------------------------------------------------------------------
FUNCTION VitalAND (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNAND (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXNOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: N-input logic device concurrent procedure calls.
-- VitalAND VitalOR VitalXOR
-- VitalNAND VitalNOR VitalXNOR
--
-- Description: The procedure calls return the evaluated logic function
-- corresponding to the function name as a parameter to the
-- procedure. Propagation delay form data to q is a
-- a parameter to the procedure. A vector of delay values
-- for inputs to output are provided. It is noted that
-- limitations in SDF make the back annotation of the delay
-- array difficult.
--
-- Arguments:
--
-- IN Type Description
-- Data std_logic_vector The input signals for the n-
-- bit wide logic functions.
-- tpd_data_q VitalDelayArrayType01 The propagation delay from
-- the data inputs to the output
-- q.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic The output signal of the
-- evaluated logic function.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalAND (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNAND (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXNOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
-- -------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: 2,3 and 4 input logic device function calls.
--
-- VitalAND2 VitalOR2 VitalXOR2
-- VitalAND3 VitalOR3 VitalXOR3
-- VitalAND4 VitalOR4 VitalXOR4
--
-- VitalNAND2 VitalNOR2 VitalXNOR2
-- VitalNAND3 VitalNOR3 VitalXNOR3
-- VitalNAND4 VitalNOR4 VitalXNOR4
--
-- Description: The function calls return the evaluated 2, 3 or 4 input
-- logic function corresponding to the function name.
--
-- Arguments:
--
-- IN Type Description
-- a, b, c, d std_ulogic 2 input devices have a and b as
-- inputs. 3 input devices have a, b
-- and c as inputs. 4 input devices
-- have a, b, c and d as inputs.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic The result of the evaluated logic
-- function.
--
-- -------------------------------------------------------------------------
FUNCTION VitalAND2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNAND2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXNOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalAND3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNAND3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXNOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalAND4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNAND4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXNOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: 2, 3 and 4 input logic device concurrent procedure
-- calls.
--
-- VitalAND2 VitalOR2 VitalXOR2
-- VitalAND3 VitalOR3 VitalXOR3
-- VitalAND4 VitalOR4 VitalXOR4
--
-- VitalNAND2 VitalNOR2 VitalXNOR2
-- VitalNAND3 VitalNOR3 VitalXNOR3
-- VitalNAND4 VitalNOR4 VitalXNOR4
--
-- Description: The procedure calls return the evaluated logic function
-- corresponding to the function name as a parameter to the
-- procedure. Propagation delays from a and b to q are
-- a parameter to the procedure. The default propagation
-- delay is 0 ns.
--
-- Arguments:
--
-- IN Type Description
-- a, b, c, d std_ulogic 2 input devices have a and b as
-- inputs. 3 input devices have a, b
-- and c as inputs. 4 input devices
-- have a, b, c and d as inputs.
-- tpd_a_q VitalDelayType01 The propagation delay from the a
-- input to output q for 2, 3 and 4
-- input devices.
-- tpd_b_q VitalDelayType01 The propagation delay from the b
-- input to output q for 2, 3 and 4
-- input devices.
-- tpd_c_q VitalDelayType01 The propagation delay from the c
-- input to output q for 3 and 4 input
-- devices.
-- tpd_d_q VitalDelayType01 The propagation delay from the d
-- input to output q for 4 input
-- devices.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic The output signal of the evaluated
-- logic function.
--
-- Returns
-- none
-- -------------------------------------------------------------------------
PROCEDURE VitalAND2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNAND2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXNOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalAND3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNAND3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXNOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalAND4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNAND4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXNOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: Buffer logic device concurrent procedure calls.
--
-- Description: Four buffer sequential primitive function calls are
-- provided. One is a simple buffer and the others
-- offer high and low enables and the four permits
-- propagation of Z as shown below:
--
-- VitalBUF Standard non-inverting buffer
-- VitalBUFIF0 Non-inverting buffer with Enable low
-- VitalBUFIF1 Non-inverting buffer with Enable high
-- VitalIDENT Pass buffer capable of propagating Z
--
-- Arguments:
--
-- IN Type Description
-- Data std_ulogic Input to the buffers
-- Enable std_ulogic Enable for the enable high and low
-- buffers.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- simple buffer.
-- VitalResultZMapType The output signal strength result map
-- to modify default result mapping
-- which has high impedance capability
-- for the enable high, enable low and
-- identity buffers.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic The output signal of the evaluated
-- buffer function.
--
-- -------------------------------------------------------------------------
FUNCTION VitalBUF (
CONSTANT Data : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalBUFIF0 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
FUNCTION VitalBUFIF1 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
FUNCTION VitalIDENT (
CONSTANT Data : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: Buffer device procedure calls.
--
-- Description: Four buffer concurrent primitive procedure calls are
-- provided. One is a simple buffer and the others
-- offer high and low enables and the fourth permits
-- propagation of Z as shown below:
--
-- VitalBUF Standard non-inverting buffer
-- VitalBUFIF0 Non-inverting buffer with Enable low
-- VitalBUFIF1 Non-inverting buffer with Enable high
-- VitalIDENT Pass buffer capable of propagating Z
--
-- Arguments:
--
-- IN Type Description
-- a std_ulogic Input signal to the buffers
-- Enable std_ulogic Enable signal for the enable high and
-- low buffers.
-- tpd_a_q VitalDelayType01 Propagation delay from input to
-- output for the simple buffer.
-- VitalDelayType01Z Propagation delay from input to
-- to output for the enable high and low
-- and identity buffers.
-- tpd_enable_q VitalDelayType01Z Propagation delay from enable to
-- output for the enable high and low
-- buffers.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- simple buffer.
-- VitalResultZMapType The output signal strength result map
-- to modify default result mapping
-- which has high impedance capability
-- for the enable high, enable low and
-- identity buffers.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic Output of the buffers.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalBUF (
SIGNAL q : OUT std_ulogic;
SIGNAL a : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalBUFIF0 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap);
PROCEDURE VitalBUFIF1 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap);
PROCEDURE VitalIDENT (
SIGNAL q : OUT std_ulogic;
SIGNAL a : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap );
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: VitalINV, VitalINVIF0, VitalINVIF1
--
-- Description: Inverter functions which return the inverted signal
-- value. Inverters with enable low and high are provided
-- which can drive high impedance when inactive.
--
-- Arguments:
--
-- IN Type Description
-- Data std_ulogic Input to the inverter
-- Enable std_ulogic Enable to the enable high and low
-- inverters.
-- ResultMap VitalResultMap The output signal strength result map
-- to modify default result mapping for
-- simple inverter.
-- VitalResultZMapType The output signal strength result map
-- to modify default result mapping
-- which has high impedance capability
-- for the enable high, enable low
-- inverters.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic Output of the inverter
--
-- -------------------------------------------------------------------------
FUNCTION VitalINV (
CONSTANT Data : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalINVIF0 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
FUNCTION VitalINVIF1 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: VitalINV, VitalINVIF0, VitalINVIF1
--
-- Description: The concurrent primitive procedure calls implement a
-- signal inversion function. The output is a parameter to
-- the procedure. The path delay information is passed as
-- a parameter to the call.
--
-- Arguments:
--
-- IN Type Description
-- a std_ulogic Input signal for the simple inverter
-- Data std_ulogic Input signal for the enable high and
-- low inverters.
-- Enable std_ulogic Enable signal for the enable high and
-- low inverters.
-- tpd_a_q VitalDelayType01 Propagation delay from input a to
-- output q for the simple inverter.
-- tpd_data_q VitalDelayType01 Propagation delay from input data to
-- output q for the enable high and low
-- inverters.
-- tpd_enable_q VitalDelayType01Z Propagation delay from input enable
-- to output q for the enable high and
-- low inverters.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- simple inverter.
-- VitalResultZMapType The output signal strength result map
-- to modify default result mapping
-- which has high impedance capability
-- for the enable high, enable low
-- inverters.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic Output signal of the inverter.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalINV (
SIGNAL q : OUT std_ulogic;
SIGNAL a : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalINVIF0 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap);
PROCEDURE VitalINVIF1 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap);
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: VitalMUX, VitalMUX2, VitalMUX4, VitalMUX8
--
-- Description: The VitalMUX functions return the selected data bit
-- based on the value of dSelect. For MUX2, the function
-- returns data0 when dselect is 0 and returns data1 when
-- dselect is 1. When dselect is X, result is X for MUX2
-- when data0 /= data1. X propagation is reduced when the
-- dselect signal is X and both data signals are identical.
-- When this is the case, the result returned is the value
-- of the data signals.
--
-- For the N input device:
--
-- N must equal 2**(bits of dSelect)
--
-- Arguments:
--
-- IN Type Description
-- Data std_logic_vector Input signal for the N-bit, 4-bit and
-- 8-bit mux.
-- Data1,Data0 std_ulogic Input signals for the 2-bit mux.
-- dSelect std_ulogic Select signal for 2-bit mux
-- std_logic_vector2 Select signal for 4-bit mux
-- std_logic_vector3 Select signal for 8-bit mux
-- std_logic_vector Select signal for N-Bit mux
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- all muxes.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic The value of the selected bit is
-- returned.
--
-- -------------------------------------------------------------------------
FUNCTION VitalMUX (
CONSTANT Data : IN std_logic_vector;
CONSTANT dSelect : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalMUX2 (
CONSTANT Data1, Data0 : IN std_ulogic;
CONSTANT dSelect : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalMUX4 (
CONSTANT Data : IN std_logic_vector4;
CONSTANT dSelect : IN std_logic_vector2;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalMUX8 (
CONSTANT Data : IN std_logic_vector8;
CONSTANT dSelect : IN std_logic_vector3;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: VitalMUX, VitalMUX2, VitalMUX4, VitalMUX8
--
-- Description: The VitalMUX concurrent primitive procedures calls
-- return in the output q the value of the selected data
-- bit based on the value of dsel. For the two bit mux,
-- the data returned is either d0 or d1, the data input.
-- For 4, 8 and N-bit functions, data is the input and is
-- of type std_logic_vector. For the 2-bit mux, if d0 or
-- d1 are X, the output is X only when d0 do not equal d1.
-- When d0 and d1 are equal, the return value is this value
-- to reduce X propagation.
--
-- Propagation delay information is passed as a parameter
-- to the procedure call for delays from data to output and
-- select to output. For 2-bit muxes, the propagation
-- delays from data are provided for d0 and d1 to output.
--
--
-- Arguments:
--
-- IN Type Description
-- d1,d0 std_ulogic Input signals for the 2-bit mux.
-- Data std_logic_vector4 Input signals for the 4-bit mux.
-- std_logic_vector8 Input signals for the 8-bit mux.
-- std_logic_vector Input signals for the N-bit mux.
-- dsel std_ulogic Select signal for the 2-bit mux.
-- std_logic_vector2 Select signals for the 4-bit mux.
-- std_logic_vector3 Select signals for the 8-bit mux.
-- std_logic_vector Select signals for the N-bit mux.
-- tpd_d1_q VitalDelayType01 Propagation delay from input d1 to
-- output q for 2-bit mux.
-- tpd_d0_q VitalDelayType01 Propagation delay from input d0 to
-- output q for 2-bit mux.
-- tpd_data_q VitalDelayArrayType01 Propagation delay from input data
-- to output q for 4-bit, 8-bit and
-- N-bit muxes.
-- tpd_dsel_q VitalDelayType01 Propagation delay from input dsel
-- to output q for 2-bit mux.
-- VitalDelayArrayType01 Propagation delay from input dsel
-- to output q for 4-bit, 8-bit and
-- N-bit muxes.
-- ResultMap VitalResultMapType The output signal strength result
-- map to modify default result
-- mapping for all muxes.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic The value of the selected signal.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalMUX (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
SIGNAL dSel : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_dsel_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalMUX2 (
SIGNAL q : OUT std_ulogic;
SIGNAL d1, d0 : IN std_ulogic;
SIGNAL dSel : IN std_ulogic;
CONSTANT tpd_d1_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d0_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_dsel_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalMUX4 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector4;
SIGNAL dSel : IN std_logic_vector2;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_dsel_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalMUX8 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector8;
SIGNAL dSel : IN std_logic_vector3;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_dsel_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: VitalDECODER, VitalDECODER2, VitalDECODER4,
-- VitalDECODER8
--
-- Description: The VitalDECODER functions are the sequential primitive
-- calls for decoder logic. The functions are provided
-- for N, 2, 4 and 8-bit outputs.
--
-- The N-bit decoder is (2**(bits of data)) wide.
--
-- The VitalDECODER returns 0 if enable is 0.
-- The VitalDECODER returns the result bit set to 1 if
-- enable is 1. All other bits of returned result are
-- set to 0.
--
-- The returned array is in descending order:
-- (n-1 downto 0).
--
-- Arguments:
--
-- IN Type Description
-- Data std_ulogic Input signal for 2-bit decoder.
-- std_logic_vector2 Input signals for 4-bit decoder.
-- std_logic_vector3 Input signals for 8-bit decoder.
-- std_logic_vector Input signals for N-bit decoder.
-- Enable std_ulogic Enable input signal. The result is
-- output when enable is high.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- all output signals of the decoders.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_logic_vector2 The output of the 2-bit decoder.
-- std_logic_vector4 The output of the 4-bit decoder.
-- std_logic_vector8 The output of the 8-bit decoder.
-- std_logic_vector The output of the n-bit decoder.
--
-- -------------------------------------------------------------------------
FUNCTION VitalDECODER (
CONSTANT Data : IN std_logic_vector;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector;
FUNCTION VitalDECODER2 (
CONSTANT Data : IN std_ulogic;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector2;
FUNCTION VitalDECODER4 (
CONSTANT Data : IN std_logic_vector2;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector4;
FUNCTION VitalDECODER8 (
CONSTANT Data : IN std_logic_vector3;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector8;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: VitalDECODER, VitalDECODER2, VitalDECODER4,
-- VitalDECODER8
--
-- Description: The VitalDECODER procedures are the concurrent primitive
-- procedure calls for decoder functions. The procedures
-- are provided for N, 2, 4 and 8 outputs.
--
-- The N-bit decoder is (2**(bits of data)) wide.
--
-- The procedural form of the decoder is used for
-- distributed delay modeling. The delay information for
-- each path is passed as an argument to the procedure.
--
-- Result is set to 0 if enable is 0.
-- The result bit represented by data is set to 1 if
-- enable is 1. All other bits of result are set to 0.
--
-- The result array is in descending order: (n-1 downto 0).
--
-- For the N-bit decoder, the delay path is a vector of
-- delays from inputs to outputs.
--
-- Arguments:
--
-- IN Type Description
-- Data std_ulogic Input signal for 2-bit decoder.
-- std_logic_vector2 Input signals for 4-bit decoder.
-- std_logic_vector3 Input signals for 8-bit decoder.
-- std_logic_vector Input signals for N-bit decoder.
-- enable std_ulogic Enable input signal. The result is
-- output when enable is high.
-- tpd_data_q VitalDelayType01 Propagation delay from input data
-- to output q for 2-bit decoder.
-- VitalDelayArrayType01 Propagation delay from input data
-- to output q for 4, 8 and n-bit
-- decoders.
-- tpd_enable_q VitalDelayType01 Propagation delay from input enable
-- to output q for 2, 4, 8 and n-bit
-- decoders.
--
-- INOUT
-- none
--
-- OUT
-- q std_logic_vector2 Output signals for 2-bit decoder.
-- std_logic_vector4 Output signals for 4-bit decoder.
-- std_logic_vector8 Output signals for 8-bit decoder.
-- std_logic_vector Output signals for n-bit decoder.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalDECODER (
SIGNAL q : OUT std_logic_vector;
SIGNAL Data : IN std_logic_vector;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalDECODER2 (
SIGNAL q : OUT std_logic_vector2;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalDECODER4 (
SIGNAL q : OUT std_logic_vector4;
SIGNAL Data : IN std_logic_vector2;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalDECODER8 (
SIGNAL q : OUT std_logic_vector8;
SIGNAL Data : IN std_logic_vector3;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
-- -------------------------------------------------------------------------
-- Function Name: VitalTruthTable
--
-- Description: VitalTruthTable implements a truth table. Given
-- a set of inputs, a sequential search is performed
-- to match the input. If a match is found, the output
-- is set based on the contents of the CONSTANT TruthTable.
-- If there is no match, all X's are returned. There is
-- no limit to the size of the table.
--
-- There is a procedure and function for VitalTruthTable.
-- For each of these, a single value output (std_logic) and
-- a multi-value output (std_logic_vector) are provided.
--
-- The first dimension of the table is for number of
-- entries in the truth table and second dimension is for
-- the number of elements in a row. The number of inputs
-- in the row should be Data'LENGTH plus result'LENGTH.
--
-- Elements is a row will be interpreted as
-- Input(NumInputs - 1),.., Input(0),
-- Result(NumOutputs - 1),.., Result(0)
--
-- All inputs will be mapped to the X01 subtype
--
-- If the value of Result is not in the range 'X' to 'Z'
-- then an error will be reported. Also, the Result is
-- always given either as a 0, 1, X or Z value.
--
-- Arguments:
--
-- IN Type Description
-- TruthTable The input constant which defines the
-- behavior in truth table form.
-- DataIn The inputs to the truth table used to
-- perform input match to select
-- output(s) to value(s) to drive.
--
-- INOUT
-- none
--
-- OUT
-- Result std_logic Concurrent procedure version scalar
-- output.
-- std_logic_vector Concurrent procedure version vector
-- output.
--
-- Returns
-- Result std_logic Function version scalar output.
-- std_logic_vector Function version vector output.
--
-- -------------------------------------------------------------------------
FUNCTION VitalTruthTable (
CONSTANT TruthTable : IN VitalTruthTableType;
CONSTANT DataIn : IN std_logic_vector
) RETURN std_logic_vector;
FUNCTION VitalTruthTable (
CONSTANT TruthTable : IN VitalTruthTableType;
CONSTANT DataIn : IN std_logic_vector
) RETURN std_logic;
PROCEDURE VitalTruthTable (
SIGNAL Result : OUT std_logic_vector;
CONSTANT TruthTable : IN VitalTruthTableType;
SIGNAL DataIn : IN std_logic_vector -- IR#236
);
PROCEDURE VitalTruthTable (
SIGNAL Result : OUT std_logic;
CONSTANT TruthTable : IN VitalTruthTableType;
SIGNAL DataIn : IN std_logic_vector -- IR#236
);
-- -------------------------------------------------------------------------
--
-- Function Name: VitalStateTable
--
-- Description: VitalStateTable is a non-concurrent implementation of a
-- state machine (Moore Machine). It is used to model
-- sequential devices and devices with internal states.
--
-- The procedure takes the value of the state table
-- data set and performs a sequential search of the
-- CONSTANT StateTable until a match is found. Once a
-- match is found, the result of that match is applied
-- to Result. If there is no match, all X's are returned.
-- The resultant output becomes the input for the next
-- state.
--
-- The first dimension of the table is the number of
-- entries in the state table and second dimension is the
-- number of elements in a row of the table. The number of
-- inputs in the row should be DataIn'LENGTH. Result should
-- contain the current state (which will become the next
-- state) as well as the outputs
--
-- Elements is a row of the table will be interpreted as
-- Input(NumInputs-1),.., Input(0), State(NumStates-1),
-- ..., State(0),Output(NumOutputs-1),.., Output(0)
--
-- where State(numStates-1) DOWNTO State(0) represent the
-- present state and Output(NumOutputs - 1) DOWNTO
-- Outputs(NumOutputs - NumStates) represent the new
-- values of the state variables (i.e. the next state).
-- Also, Output(NumOutputs - NumStates - 1)
--
-- This procedure returns the next state and the new
-- outputs when a match is made between the present state
-- and present inputs and the state table. A search is
-- made starting at the top of the state table and
-- terminates with the first match. If no match is found
-- then the next state and new outputs are set to all 'X's.
--
-- (Asynchronous inputs (i.e. resets and clears) must be
-- handled by placing the corresponding entries at the top
-- of the table. )
--
-- All inputs will be mapped to the X01 subtype.
--
-- NOTE: Edge transitions should not be used as values
-- for the state variables in the present state
-- portion of the state table. The only valid
-- values that can be used for the present state
-- portion of the state table are:
-- 'X', '0', '1', 'B', '-'
--
-- Arguments:
--
-- IN Type Description
-- StateTable VitalStateTableType The input constant which defines
-- the behavior in state table form.
-- DataIn std_logic_vector The current state inputs to the
-- state table used to perform input
-- matches and transition
-- calculations.
-- NumStates NATURAL Number of state variables
--
-- INOUT
-- Result std_logic Output signal for scalar version of
-- the concurrent procedure call.
-- std_logic_vector Output signals for vector version
-- of the concurrent procedure call.
-- PreviousDataIn std_logic_vector The previous inputs and states used
-- in transition calculations and to
-- set outputs for steady state cases.
--
-- OUT
-- none
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalStateTable (
VARIABLE Result : INOUT std_logic_vector;
VARIABLE PreviousDataIn : INOUT std_logic_vector;
CONSTANT StateTable : IN VitalStateTableType;
CONSTANT DataIn : IN std_logic_vector;
CONSTANT NumStates : IN NATURAL
);
PROCEDURE VitalStateTable (
VARIABLE Result : INOUT std_logic;
VARIABLE PreviousDataIn : INOUT std_logic_vector;
CONSTANT StateTable : IN VitalStateTableType;
CONSTANT DataIn : IN std_logic_vector
);
PROCEDURE VitalStateTable (
SIGNAL Result : INOUT std_logic_vector;
CONSTANT StateTable : IN VitalStateTableType;
SIGNAL DataIn : IN std_logic_vector;
CONSTANT NumStates : IN NATURAL
);
PROCEDURE VitalStateTable (
SIGNAL Result : INOUT std_logic;
CONSTANT StateTable : IN VitalStateTableType;
SIGNAL DataIn : IN std_logic_vector
);
-- -------------------------------------------------------------------------
--
-- Function Name: VitalResolve
--
-- Description: VitalResolve takes a vector of signals and resolves
-- them to a std_ulogic value. This procedure can be used
-- to resolve multiple drivers in a single model.
--
-- Arguments:
--
-- IN Type Description
-- Data std_logic_vector Set of input signals which drive a
-- common signal.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic Output signal which is the resolved
-- value being driven by the collection of
-- input signals.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalResolve (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector); --IR236 4/2/98
END VITAL_Primitives;
|
-- -----------------------------------------------------------------------------
-- Title : Standard VITAL_Primitives Package
-- : $Revision$
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers : IEEE DASC Timing Working Group (TWG), PAR 1076.4
-- :
-- Purpose : This packages defines standard types, constants, functions
-- : and procedures for use in developing ASIC models.
-- : Specifically a set of logic primitives are defined.
-- :
-- Known Errors :
-- :
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the objects (types, subtypes, constants, functions,
-- : procedures ... etc.) that can be used by a user. The package
-- : body shall be considered the formal definition of the
-- : semantics of this package. Tool developers may choose to
-- : implement the package body in the most efficient manner
-- : available to them.
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Acknowledgments:
-- This code was originally developed under the "VHDL Initiative Toward ASIC
-- Libraries" (VITAL), an industry sponsored initiative. Technical
-- Director: William Billowitch, VHDL Technology Group; U.S. Coordinator:
-- Steve Schultz; Steering Committee Members: Victor Berman, Cadence Design
-- Systems; Oz Levia, Synopsys Inc.; Ray Ryan, Ryan & Ryan; Herman van Beek,
-- Texas Instruments; Victor Martin, Hewlett-Packard Company.
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Modification History :
-- ----------------------------------------------------------------------------
-- Version No:|Auth:| Mod.Date:| Changes Made:
-- v95.0 A | | 06/02/95 | Initial ballot draft 1995
-- ----------------------------------------------------------------------------
-- v95.3 | ddl | 09/24/96 | #236 - VitalTruthTable DataIn should be of
-- | | | of class SIGNAL (PROPOSED)
-- ----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
USE IEEE.VITAL_Timing.ALL;
PACKAGE VITAL_Primitives IS
-- ------------------------------------------------------------------------
-- Type and Subtype Declarations
-- ------------------------------------------------------------------------
-- For Truth and State Tables
SUBTYPE VitalTruthSymbolType IS VitalTableSymbolType RANGE 'X' TO 'Z';
SUBTYPE VitalStateSymbolType IS VitalTableSymbolType RANGE '/' TO 'S';
TYPE VitalTruthTableType IS ARRAY ( NATURAL RANGE <>, NATURAL RANGE <> )
OF VitalTruthSymbolType;
TYPE VitalStateTableType IS ARRAY ( NATURAL RANGE <>, NATURAL RANGE <> )
OF VitalStateSymbolType;
-- ---------------------------------
-- Default values used by primitives
-- ---------------------------------
CONSTANT VitalDefDelay01 : VitalDelayType01; -- Propagation delays
CONSTANT VitalDefDelay01Z : VitalDelayType01Z;
-- ------------------------------------------------------------------------
-- VITAL Primitives
--
-- The primitives packages contains a collections of common gates,
-- including AND, OR, XOR, NAND, NOR, XNOR, BUF, INV, MUX and DECODER
-- functions. In addition, for sequential devices, a STATE TABLE construct
-- is provided. For complex functions a modeler may wish to use either
-- a collection of connected VITAL primitives, or a TRUTH TABLE construct.
--
-- For each primitive a Function and Procedure is provided. The primitive
-- functions are provided to support behavioral modeling styles. The
-- primitive procedures are provided to support structural modeling styles.
--
-- The procedures wait internally for an event on an input signal, compute
-- the new result, perform glitch handling, schedule transaction on the
-- output signals, and wait for future input events. All of the functional
-- (logic) input or output parameters of the primitive procedures are
-- signals. All the other parameters are constants.
--
-- The procedure primitives are parameterized for separate path delays
-- from each input signal. All path delays default to 0 ns.
--
-- The sequential primitive functions compute the defined function and
-- return a value of type std_ulogic or std_logic_vector. All parameters
-- of the primitive functions are constants of mode IN.
--
-- The primitives are based on 1164 operators. The user may also elect to
-- express functions using the 1164 operators as well. These styles are
-- all equally acceptable methods for device modeling.
--
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: N-input logic device function calls:
-- VitalAND VitalOR VitalXOR
-- VitalNAND VitalNOR VitalXNOR
--
-- Description: The function calls return the evaluated logic function
-- corresponding to the function name.
--
-- Arguments:
--
-- IN Type Description
-- Data std_logic_vector The input signals for the n-bit
-- wide logic functions.
-- ResultMap VitalResultMapType The output signal strength
-- result map to modify default
-- result mapping.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic The evaluated logic function of
-- the n-bit wide primitives.
--
-- -------------------------------------------------------------------------
FUNCTION VitalAND (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNAND (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXNOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: N-input logic device concurrent procedure calls.
-- VitalAND VitalOR VitalXOR
-- VitalNAND VitalNOR VitalXNOR
--
-- Description: The procedure calls return the evaluated logic function
-- corresponding to the function name as a parameter to the
-- procedure. Propagation delay form data to q is a
-- a parameter to the procedure. A vector of delay values
-- for inputs to output are provided. It is noted that
-- limitations in SDF make the back annotation of the delay
-- array difficult.
--
-- Arguments:
--
-- IN Type Description
-- Data std_logic_vector The input signals for the n-
-- bit wide logic functions.
-- tpd_data_q VitalDelayArrayType01 The propagation delay from
-- the data inputs to the output
-- q.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic The output signal of the
-- evaluated logic function.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalAND (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNAND (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXNOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
-- -------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: 2,3 and 4 input logic device function calls.
--
-- VitalAND2 VitalOR2 VitalXOR2
-- VitalAND3 VitalOR3 VitalXOR3
-- VitalAND4 VitalOR4 VitalXOR4
--
-- VitalNAND2 VitalNOR2 VitalXNOR2
-- VitalNAND3 VitalNOR3 VitalXNOR3
-- VitalNAND4 VitalNOR4 VitalXNOR4
--
-- Description: The function calls return the evaluated 2, 3 or 4 input
-- logic function corresponding to the function name.
--
-- Arguments:
--
-- IN Type Description
-- a, b, c, d std_ulogic 2 input devices have a and b as
-- inputs. 3 input devices have a, b
-- and c as inputs. 4 input devices
-- have a, b, c and d as inputs.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic The result of the evaluated logic
-- function.
--
-- -------------------------------------------------------------------------
FUNCTION VitalAND2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNAND2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXNOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalAND3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNAND3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXNOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalAND4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNAND4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXNOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: 2, 3 and 4 input logic device concurrent procedure
-- calls.
--
-- VitalAND2 VitalOR2 VitalXOR2
-- VitalAND3 VitalOR3 VitalXOR3
-- VitalAND4 VitalOR4 VitalXOR4
--
-- VitalNAND2 VitalNOR2 VitalXNOR2
-- VitalNAND3 VitalNOR3 VitalXNOR3
-- VitalNAND4 VitalNOR4 VitalXNOR4
--
-- Description: The procedure calls return the evaluated logic function
-- corresponding to the function name as a parameter to the
-- procedure. Propagation delays from a and b to q are
-- a parameter to the procedure. The default propagation
-- delay is 0 ns.
--
-- Arguments:
--
-- IN Type Description
-- a, b, c, d std_ulogic 2 input devices have a and b as
-- inputs. 3 input devices have a, b
-- and c as inputs. 4 input devices
-- have a, b, c and d as inputs.
-- tpd_a_q VitalDelayType01 The propagation delay from the a
-- input to output q for 2, 3 and 4
-- input devices.
-- tpd_b_q VitalDelayType01 The propagation delay from the b
-- input to output q for 2, 3 and 4
-- input devices.
-- tpd_c_q VitalDelayType01 The propagation delay from the c
-- input to output q for 3 and 4 input
-- devices.
-- tpd_d_q VitalDelayType01 The propagation delay from the d
-- input to output q for 4 input
-- devices.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic The output signal of the evaluated
-- logic function.
--
-- Returns
-- none
-- -------------------------------------------------------------------------
PROCEDURE VitalAND2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNAND2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXNOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalAND3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNAND3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXNOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalAND4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNAND4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXNOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: Buffer logic device concurrent procedure calls.
--
-- Description: Four buffer sequential primitive function calls are
-- provided. One is a simple buffer and the others
-- offer high and low enables and the four permits
-- propagation of Z as shown below:
--
-- VitalBUF Standard non-inverting buffer
-- VitalBUFIF0 Non-inverting buffer with Enable low
-- VitalBUFIF1 Non-inverting buffer with Enable high
-- VitalIDENT Pass buffer capable of propagating Z
--
-- Arguments:
--
-- IN Type Description
-- Data std_ulogic Input to the buffers
-- Enable std_ulogic Enable for the enable high and low
-- buffers.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- simple buffer.
-- VitalResultZMapType The output signal strength result map
-- to modify default result mapping
-- which has high impedance capability
-- for the enable high, enable low and
-- identity buffers.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic The output signal of the evaluated
-- buffer function.
--
-- -------------------------------------------------------------------------
FUNCTION VitalBUF (
CONSTANT Data : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalBUFIF0 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
FUNCTION VitalBUFIF1 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
FUNCTION VitalIDENT (
CONSTANT Data : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: Buffer device procedure calls.
--
-- Description: Four buffer concurrent primitive procedure calls are
-- provided. One is a simple buffer and the others
-- offer high and low enables and the fourth permits
-- propagation of Z as shown below:
--
-- VitalBUF Standard non-inverting buffer
-- VitalBUFIF0 Non-inverting buffer with Enable low
-- VitalBUFIF1 Non-inverting buffer with Enable high
-- VitalIDENT Pass buffer capable of propagating Z
--
-- Arguments:
--
-- IN Type Description
-- a std_ulogic Input signal to the buffers
-- Enable std_ulogic Enable signal for the enable high and
-- low buffers.
-- tpd_a_q VitalDelayType01 Propagation delay from input to
-- output for the simple buffer.
-- VitalDelayType01Z Propagation delay from input to
-- to output for the enable high and low
-- and identity buffers.
-- tpd_enable_q VitalDelayType01Z Propagation delay from enable to
-- output for the enable high and low
-- buffers.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- simple buffer.
-- VitalResultZMapType The output signal strength result map
-- to modify default result mapping
-- which has high impedance capability
-- for the enable high, enable low and
-- identity buffers.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic Output of the buffers.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalBUF (
SIGNAL q : OUT std_ulogic;
SIGNAL a : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalBUFIF0 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap);
PROCEDURE VitalBUFIF1 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap);
PROCEDURE VitalIDENT (
SIGNAL q : OUT std_ulogic;
SIGNAL a : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap );
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: VitalINV, VitalINVIF0, VitalINVIF1
--
-- Description: Inverter functions which return the inverted signal
-- value. Inverters with enable low and high are provided
-- which can drive high impedance when inactive.
--
-- Arguments:
--
-- IN Type Description
-- Data std_ulogic Input to the inverter
-- Enable std_ulogic Enable to the enable high and low
-- inverters.
-- ResultMap VitalResultMap The output signal strength result map
-- to modify default result mapping for
-- simple inverter.
-- VitalResultZMapType The output signal strength result map
-- to modify default result mapping
-- which has high impedance capability
-- for the enable high, enable low
-- inverters.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic Output of the inverter
--
-- -------------------------------------------------------------------------
FUNCTION VitalINV (
CONSTANT Data : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalINVIF0 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
FUNCTION VitalINVIF1 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: VitalINV, VitalINVIF0, VitalINVIF1
--
-- Description: The concurrent primitive procedure calls implement a
-- signal inversion function. The output is a parameter to
-- the procedure. The path delay information is passed as
-- a parameter to the call.
--
-- Arguments:
--
-- IN Type Description
-- a std_ulogic Input signal for the simple inverter
-- Data std_ulogic Input signal for the enable high and
-- low inverters.
-- Enable std_ulogic Enable signal for the enable high and
-- low inverters.
-- tpd_a_q VitalDelayType01 Propagation delay from input a to
-- output q for the simple inverter.
-- tpd_data_q VitalDelayType01 Propagation delay from input data to
-- output q for the enable high and low
-- inverters.
-- tpd_enable_q VitalDelayType01Z Propagation delay from input enable
-- to output q for the enable high and
-- low inverters.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- simple inverter.
-- VitalResultZMapType The output signal strength result map
-- to modify default result mapping
-- which has high impedance capability
-- for the enable high, enable low
-- inverters.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic Output signal of the inverter.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalINV (
SIGNAL q : OUT std_ulogic;
SIGNAL a : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalINVIF0 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap);
PROCEDURE VitalINVIF1 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap);
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: VitalMUX, VitalMUX2, VitalMUX4, VitalMUX8
--
-- Description: The VitalMUX functions return the selected data bit
-- based on the value of dSelect. For MUX2, the function
-- returns data0 when dselect is 0 and returns data1 when
-- dselect is 1. When dselect is X, result is X for MUX2
-- when data0 /= data1. X propagation is reduced when the
-- dselect signal is X and both data signals are identical.
-- When this is the case, the result returned is the value
-- of the data signals.
--
-- For the N input device:
--
-- N must equal 2**(bits of dSelect)
--
-- Arguments:
--
-- IN Type Description
-- Data std_logic_vector Input signal for the N-bit, 4-bit and
-- 8-bit mux.
-- Data1,Data0 std_ulogic Input signals for the 2-bit mux.
-- dSelect std_ulogic Select signal for 2-bit mux
-- std_logic_vector2 Select signal for 4-bit mux
-- std_logic_vector3 Select signal for 8-bit mux
-- std_logic_vector Select signal for N-Bit mux
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- all muxes.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic The value of the selected bit is
-- returned.
--
-- -------------------------------------------------------------------------
FUNCTION VitalMUX (
CONSTANT Data : IN std_logic_vector;
CONSTANT dSelect : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalMUX2 (
CONSTANT Data1, Data0 : IN std_ulogic;
CONSTANT dSelect : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalMUX4 (
CONSTANT Data : IN std_logic_vector4;
CONSTANT dSelect : IN std_logic_vector2;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalMUX8 (
CONSTANT Data : IN std_logic_vector8;
CONSTANT dSelect : IN std_logic_vector3;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: VitalMUX, VitalMUX2, VitalMUX4, VitalMUX8
--
-- Description: The VitalMUX concurrent primitive procedures calls
-- return in the output q the value of the selected data
-- bit based on the value of dsel. For the two bit mux,
-- the data returned is either d0 or d1, the data input.
-- For 4, 8 and N-bit functions, data is the input and is
-- of type std_logic_vector. For the 2-bit mux, if d0 or
-- d1 are X, the output is X only when d0 do not equal d1.
-- When d0 and d1 are equal, the return value is this value
-- to reduce X propagation.
--
-- Propagation delay information is passed as a parameter
-- to the procedure call for delays from data to output and
-- select to output. For 2-bit muxes, the propagation
-- delays from data are provided for d0 and d1 to output.
--
--
-- Arguments:
--
-- IN Type Description
-- d1,d0 std_ulogic Input signals for the 2-bit mux.
-- Data std_logic_vector4 Input signals for the 4-bit mux.
-- std_logic_vector8 Input signals for the 8-bit mux.
-- std_logic_vector Input signals for the N-bit mux.
-- dsel std_ulogic Select signal for the 2-bit mux.
-- std_logic_vector2 Select signals for the 4-bit mux.
-- std_logic_vector3 Select signals for the 8-bit mux.
-- std_logic_vector Select signals for the N-bit mux.
-- tpd_d1_q VitalDelayType01 Propagation delay from input d1 to
-- output q for 2-bit mux.
-- tpd_d0_q VitalDelayType01 Propagation delay from input d0 to
-- output q for 2-bit mux.
-- tpd_data_q VitalDelayArrayType01 Propagation delay from input data
-- to output q for 4-bit, 8-bit and
-- N-bit muxes.
-- tpd_dsel_q VitalDelayType01 Propagation delay from input dsel
-- to output q for 2-bit mux.
-- VitalDelayArrayType01 Propagation delay from input dsel
-- to output q for 4-bit, 8-bit and
-- N-bit muxes.
-- ResultMap VitalResultMapType The output signal strength result
-- map to modify default result
-- mapping for all muxes.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic The value of the selected signal.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalMUX (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
SIGNAL dSel : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_dsel_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalMUX2 (
SIGNAL q : OUT std_ulogic;
SIGNAL d1, d0 : IN std_ulogic;
SIGNAL dSel : IN std_ulogic;
CONSTANT tpd_d1_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d0_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_dsel_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalMUX4 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector4;
SIGNAL dSel : IN std_logic_vector2;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_dsel_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalMUX8 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector8;
SIGNAL dSel : IN std_logic_vector3;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_dsel_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: VitalDECODER, VitalDECODER2, VitalDECODER4,
-- VitalDECODER8
--
-- Description: The VitalDECODER functions are the sequential primitive
-- calls for decoder logic. The functions are provided
-- for N, 2, 4 and 8-bit outputs.
--
-- The N-bit decoder is (2**(bits of data)) wide.
--
-- The VitalDECODER returns 0 if enable is 0.
-- The VitalDECODER returns the result bit set to 1 if
-- enable is 1. All other bits of returned result are
-- set to 0.
--
-- The returned array is in descending order:
-- (n-1 downto 0).
--
-- Arguments:
--
-- IN Type Description
-- Data std_ulogic Input signal for 2-bit decoder.
-- std_logic_vector2 Input signals for 4-bit decoder.
-- std_logic_vector3 Input signals for 8-bit decoder.
-- std_logic_vector Input signals for N-bit decoder.
-- Enable std_ulogic Enable input signal. The result is
-- output when enable is high.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- all output signals of the decoders.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_logic_vector2 The output of the 2-bit decoder.
-- std_logic_vector4 The output of the 4-bit decoder.
-- std_logic_vector8 The output of the 8-bit decoder.
-- std_logic_vector The output of the n-bit decoder.
--
-- -------------------------------------------------------------------------
FUNCTION VitalDECODER (
CONSTANT Data : IN std_logic_vector;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector;
FUNCTION VitalDECODER2 (
CONSTANT Data : IN std_ulogic;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector2;
FUNCTION VitalDECODER4 (
CONSTANT Data : IN std_logic_vector2;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector4;
FUNCTION VitalDECODER8 (
CONSTANT Data : IN std_logic_vector3;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector8;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: VitalDECODER, VitalDECODER2, VitalDECODER4,
-- VitalDECODER8
--
-- Description: The VitalDECODER procedures are the concurrent primitive
-- procedure calls for decoder functions. The procedures
-- are provided for N, 2, 4 and 8 outputs.
--
-- The N-bit decoder is (2**(bits of data)) wide.
--
-- The procedural form of the decoder is used for
-- distributed delay modeling. The delay information for
-- each path is passed as an argument to the procedure.
--
-- Result is set to 0 if enable is 0.
-- The result bit represented by data is set to 1 if
-- enable is 1. All other bits of result are set to 0.
--
-- The result array is in descending order: (n-1 downto 0).
--
-- For the N-bit decoder, the delay path is a vector of
-- delays from inputs to outputs.
--
-- Arguments:
--
-- IN Type Description
-- Data std_ulogic Input signal for 2-bit decoder.
-- std_logic_vector2 Input signals for 4-bit decoder.
-- std_logic_vector3 Input signals for 8-bit decoder.
-- std_logic_vector Input signals for N-bit decoder.
-- enable std_ulogic Enable input signal. The result is
-- output when enable is high.
-- tpd_data_q VitalDelayType01 Propagation delay from input data
-- to output q for 2-bit decoder.
-- VitalDelayArrayType01 Propagation delay from input data
-- to output q for 4, 8 and n-bit
-- decoders.
-- tpd_enable_q VitalDelayType01 Propagation delay from input enable
-- to output q for 2, 4, 8 and n-bit
-- decoders.
--
-- INOUT
-- none
--
-- OUT
-- q std_logic_vector2 Output signals for 2-bit decoder.
-- std_logic_vector4 Output signals for 4-bit decoder.
-- std_logic_vector8 Output signals for 8-bit decoder.
-- std_logic_vector Output signals for n-bit decoder.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalDECODER (
SIGNAL q : OUT std_logic_vector;
SIGNAL Data : IN std_logic_vector;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalDECODER2 (
SIGNAL q : OUT std_logic_vector2;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalDECODER4 (
SIGNAL q : OUT std_logic_vector4;
SIGNAL Data : IN std_logic_vector2;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalDECODER8 (
SIGNAL q : OUT std_logic_vector8;
SIGNAL Data : IN std_logic_vector3;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
-- -------------------------------------------------------------------------
-- Function Name: VitalTruthTable
--
-- Description: VitalTruthTable implements a truth table. Given
-- a set of inputs, a sequential search is performed
-- to match the input. If a match is found, the output
-- is set based on the contents of the CONSTANT TruthTable.
-- If there is no match, all X's are returned. There is
-- no limit to the size of the table.
--
-- There is a procedure and function for VitalTruthTable.
-- For each of these, a single value output (std_logic) and
-- a multi-value output (std_logic_vector) are provided.
--
-- The first dimension of the table is for number of
-- entries in the truth table and second dimension is for
-- the number of elements in a row. The number of inputs
-- in the row should be Data'LENGTH plus result'LENGTH.
--
-- Elements is a row will be interpreted as
-- Input(NumInputs - 1),.., Input(0),
-- Result(NumOutputs - 1),.., Result(0)
--
-- All inputs will be mapped to the X01 subtype
--
-- If the value of Result is not in the range 'X' to 'Z'
-- then an error will be reported. Also, the Result is
-- always given either as a 0, 1, X or Z value.
--
-- Arguments:
--
-- IN Type Description
-- TruthTable The input constant which defines the
-- behavior in truth table form.
-- DataIn The inputs to the truth table used to
-- perform input match to select
-- output(s) to value(s) to drive.
--
-- INOUT
-- none
--
-- OUT
-- Result std_logic Concurrent procedure version scalar
-- output.
-- std_logic_vector Concurrent procedure version vector
-- output.
--
-- Returns
-- Result std_logic Function version scalar output.
-- std_logic_vector Function version vector output.
--
-- -------------------------------------------------------------------------
FUNCTION VitalTruthTable (
CONSTANT TruthTable : IN VitalTruthTableType;
CONSTANT DataIn : IN std_logic_vector
) RETURN std_logic_vector;
FUNCTION VitalTruthTable (
CONSTANT TruthTable : IN VitalTruthTableType;
CONSTANT DataIn : IN std_logic_vector
) RETURN std_logic;
PROCEDURE VitalTruthTable (
SIGNAL Result : OUT std_logic_vector;
CONSTANT TruthTable : IN VitalTruthTableType;
SIGNAL DataIn : IN std_logic_vector -- IR#236
);
PROCEDURE VitalTruthTable (
SIGNAL Result : OUT std_logic;
CONSTANT TruthTable : IN VitalTruthTableType;
SIGNAL DataIn : IN std_logic_vector -- IR#236
);
-- -------------------------------------------------------------------------
--
-- Function Name: VitalStateTable
--
-- Description: VitalStateTable is a non-concurrent implementation of a
-- state machine (Moore Machine). It is used to model
-- sequential devices and devices with internal states.
--
-- The procedure takes the value of the state table
-- data set and performs a sequential search of the
-- CONSTANT StateTable until a match is found. Once a
-- match is found, the result of that match is applied
-- to Result. If there is no match, all X's are returned.
-- The resultant output becomes the input for the next
-- state.
--
-- The first dimension of the table is the number of
-- entries in the state table and second dimension is the
-- number of elements in a row of the table. The number of
-- inputs in the row should be DataIn'LENGTH. Result should
-- contain the current state (which will become the next
-- state) as well as the outputs
--
-- Elements is a row of the table will be interpreted as
-- Input(NumInputs-1),.., Input(0), State(NumStates-1),
-- ..., State(0),Output(NumOutputs-1),.., Output(0)
--
-- where State(numStates-1) DOWNTO State(0) represent the
-- present state and Output(NumOutputs - 1) DOWNTO
-- Outputs(NumOutputs - NumStates) represent the new
-- values of the state variables (i.e. the next state).
-- Also, Output(NumOutputs - NumStates - 1)
--
-- This procedure returns the next state and the new
-- outputs when a match is made between the present state
-- and present inputs and the state table. A search is
-- made starting at the top of the state table and
-- terminates with the first match. If no match is found
-- then the next state and new outputs are set to all 'X's.
--
-- (Asynchronous inputs (i.e. resets and clears) must be
-- handled by placing the corresponding entries at the top
-- of the table. )
--
-- All inputs will be mapped to the X01 subtype.
--
-- NOTE: Edge transitions should not be used as values
-- for the state variables in the present state
-- portion of the state table. The only valid
-- values that can be used for the present state
-- portion of the state table are:
-- 'X', '0', '1', 'B', '-'
--
-- Arguments:
--
-- IN Type Description
-- StateTable VitalStateTableType The input constant which defines
-- the behavior in state table form.
-- DataIn std_logic_vector The current state inputs to the
-- state table used to perform input
-- matches and transition
-- calculations.
-- NumStates NATURAL Number of state variables
--
-- INOUT
-- Result std_logic Output signal for scalar version of
-- the concurrent procedure call.
-- std_logic_vector Output signals for vector version
-- of the concurrent procedure call.
-- PreviousDataIn std_logic_vector The previous inputs and states used
-- in transition calculations and to
-- set outputs for steady state cases.
--
-- OUT
-- none
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalStateTable (
VARIABLE Result : INOUT std_logic_vector;
VARIABLE PreviousDataIn : INOUT std_logic_vector;
CONSTANT StateTable : IN VitalStateTableType;
CONSTANT DataIn : IN std_logic_vector;
CONSTANT NumStates : IN NATURAL
);
PROCEDURE VitalStateTable (
VARIABLE Result : INOUT std_logic;
VARIABLE PreviousDataIn : INOUT std_logic_vector;
CONSTANT StateTable : IN VitalStateTableType;
CONSTANT DataIn : IN std_logic_vector
);
PROCEDURE VitalStateTable (
SIGNAL Result : INOUT std_logic_vector;
CONSTANT StateTable : IN VitalStateTableType;
SIGNAL DataIn : IN std_logic_vector;
CONSTANT NumStates : IN NATURAL
);
PROCEDURE VitalStateTable (
SIGNAL Result : INOUT std_logic;
CONSTANT StateTable : IN VitalStateTableType;
SIGNAL DataIn : IN std_logic_vector
);
-- -------------------------------------------------------------------------
--
-- Function Name: VitalResolve
--
-- Description: VitalResolve takes a vector of signals and resolves
-- them to a std_ulogic value. This procedure can be used
-- to resolve multiple drivers in a single model.
--
-- Arguments:
--
-- IN Type Description
-- Data std_logic_vector Set of input signals which drive a
-- common signal.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic Output signal which is the resolved
-- value being driven by the collection of
-- input signals.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalResolve (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector); --IR236 4/2/98
END VITAL_Primitives;
|
-- -----------------------------------------------------------------------------
-- Title : Standard VITAL_Primitives Package
-- : $Revision$
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers : IEEE DASC Timing Working Group (TWG), PAR 1076.4
-- :
-- Purpose : This packages defines standard types, constants, functions
-- : and procedures for use in developing ASIC models.
-- : Specifically a set of logic primitives are defined.
-- :
-- Known Errors :
-- :
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the objects (types, subtypes, constants, functions,
-- : procedures ... etc.) that can be used by a user. The package
-- : body shall be considered the formal definition of the
-- : semantics of this package. Tool developers may choose to
-- : implement the package body in the most efficient manner
-- : available to them.
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Acknowledgments:
-- This code was originally developed under the "VHDL Initiative Toward ASIC
-- Libraries" (VITAL), an industry sponsored initiative. Technical
-- Director: William Billowitch, VHDL Technology Group; U.S. Coordinator:
-- Steve Schultz; Steering Committee Members: Victor Berman, Cadence Design
-- Systems; Oz Levia, Synopsys Inc.; Ray Ryan, Ryan & Ryan; Herman van Beek,
-- Texas Instruments; Victor Martin, Hewlett-Packard Company.
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Modification History :
-- ----------------------------------------------------------------------------
-- Version No:|Auth:| Mod.Date:| Changes Made:
-- v95.0 A | | 06/02/95 | Initial ballot draft 1995
-- ----------------------------------------------------------------------------
-- v95.3 | ddl | 09/24/96 | #236 - VitalTruthTable DataIn should be of
-- | | | of class SIGNAL (PROPOSED)
-- ----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
USE IEEE.VITAL_Timing.ALL;
PACKAGE VITAL_Primitives IS
-- ------------------------------------------------------------------------
-- Type and Subtype Declarations
-- ------------------------------------------------------------------------
-- For Truth and State Tables
SUBTYPE VitalTruthSymbolType IS VitalTableSymbolType RANGE 'X' TO 'Z';
SUBTYPE VitalStateSymbolType IS VitalTableSymbolType RANGE '/' TO 'S';
TYPE VitalTruthTableType IS ARRAY ( NATURAL RANGE <>, NATURAL RANGE <> )
OF VitalTruthSymbolType;
TYPE VitalStateTableType IS ARRAY ( NATURAL RANGE <>, NATURAL RANGE <> )
OF VitalStateSymbolType;
-- ---------------------------------
-- Default values used by primitives
-- ---------------------------------
CONSTANT VitalDefDelay01 : VitalDelayType01; -- Propagation delays
CONSTANT VitalDefDelay01Z : VitalDelayType01Z;
-- ------------------------------------------------------------------------
-- VITAL Primitives
--
-- The primitives packages contains a collections of common gates,
-- including AND, OR, XOR, NAND, NOR, XNOR, BUF, INV, MUX and DECODER
-- functions. In addition, for sequential devices, a STATE TABLE construct
-- is provided. For complex functions a modeler may wish to use either
-- a collection of connected VITAL primitives, or a TRUTH TABLE construct.
--
-- For each primitive a Function and Procedure is provided. The primitive
-- functions are provided to support behavioral modeling styles. The
-- primitive procedures are provided to support structural modeling styles.
--
-- The procedures wait internally for an event on an input signal, compute
-- the new result, perform glitch handling, schedule transaction on the
-- output signals, and wait for future input events. All of the functional
-- (logic) input or output parameters of the primitive procedures are
-- signals. All the other parameters are constants.
--
-- The procedure primitives are parameterized for separate path delays
-- from each input signal. All path delays default to 0 ns.
--
-- The sequential primitive functions compute the defined function and
-- return a value of type std_ulogic or std_logic_vector. All parameters
-- of the primitive functions are constants of mode IN.
--
-- The primitives are based on 1164 operators. The user may also elect to
-- express functions using the 1164 operators as well. These styles are
-- all equally acceptable methods for device modeling.
--
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: N-input logic device function calls:
-- VitalAND VitalOR VitalXOR
-- VitalNAND VitalNOR VitalXNOR
--
-- Description: The function calls return the evaluated logic function
-- corresponding to the function name.
--
-- Arguments:
--
-- IN Type Description
-- Data std_logic_vector The input signals for the n-bit
-- wide logic functions.
-- ResultMap VitalResultMapType The output signal strength
-- result map to modify default
-- result mapping.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic The evaluated logic function of
-- the n-bit wide primitives.
--
-- -------------------------------------------------------------------------
FUNCTION VitalAND (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNAND (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXNOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: N-input logic device concurrent procedure calls.
-- VitalAND VitalOR VitalXOR
-- VitalNAND VitalNOR VitalXNOR
--
-- Description: The procedure calls return the evaluated logic function
-- corresponding to the function name as a parameter to the
-- procedure. Propagation delay form data to q is a
-- a parameter to the procedure. A vector of delay values
-- for inputs to output are provided. It is noted that
-- limitations in SDF make the back annotation of the delay
-- array difficult.
--
-- Arguments:
--
-- IN Type Description
-- Data std_logic_vector The input signals for the n-
-- bit wide logic functions.
-- tpd_data_q VitalDelayArrayType01 The propagation delay from
-- the data inputs to the output
-- q.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic The output signal of the
-- evaluated logic function.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalAND (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNAND (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXNOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
-- -------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: 2,3 and 4 input logic device function calls.
--
-- VitalAND2 VitalOR2 VitalXOR2
-- VitalAND3 VitalOR3 VitalXOR3
-- VitalAND4 VitalOR4 VitalXOR4
--
-- VitalNAND2 VitalNOR2 VitalXNOR2
-- VitalNAND3 VitalNOR3 VitalXNOR3
-- VitalNAND4 VitalNOR4 VitalXNOR4
--
-- Description: The function calls return the evaluated 2, 3 or 4 input
-- logic function corresponding to the function name.
--
-- Arguments:
--
-- IN Type Description
-- a, b, c, d std_ulogic 2 input devices have a and b as
-- inputs. 3 input devices have a, b
-- and c as inputs. 4 input devices
-- have a, b, c and d as inputs.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic The result of the evaluated logic
-- function.
--
-- -------------------------------------------------------------------------
FUNCTION VitalAND2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNAND2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXNOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalAND3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNAND3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXNOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalAND4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNAND4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXNOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: 2, 3 and 4 input logic device concurrent procedure
-- calls.
--
-- VitalAND2 VitalOR2 VitalXOR2
-- VitalAND3 VitalOR3 VitalXOR3
-- VitalAND4 VitalOR4 VitalXOR4
--
-- VitalNAND2 VitalNOR2 VitalXNOR2
-- VitalNAND3 VitalNOR3 VitalXNOR3
-- VitalNAND4 VitalNOR4 VitalXNOR4
--
-- Description: The procedure calls return the evaluated logic function
-- corresponding to the function name as a parameter to the
-- procedure. Propagation delays from a and b to q are
-- a parameter to the procedure. The default propagation
-- delay is 0 ns.
--
-- Arguments:
--
-- IN Type Description
-- a, b, c, d std_ulogic 2 input devices have a and b as
-- inputs. 3 input devices have a, b
-- and c as inputs. 4 input devices
-- have a, b, c and d as inputs.
-- tpd_a_q VitalDelayType01 The propagation delay from the a
-- input to output q for 2, 3 and 4
-- input devices.
-- tpd_b_q VitalDelayType01 The propagation delay from the b
-- input to output q for 2, 3 and 4
-- input devices.
-- tpd_c_q VitalDelayType01 The propagation delay from the c
-- input to output q for 3 and 4 input
-- devices.
-- tpd_d_q VitalDelayType01 The propagation delay from the d
-- input to output q for 4 input
-- devices.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic The output signal of the evaluated
-- logic function.
--
-- Returns
-- none
-- -------------------------------------------------------------------------
PROCEDURE VitalAND2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNAND2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXNOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalAND3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNAND3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXNOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalAND4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNAND4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXNOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: Buffer logic device concurrent procedure calls.
--
-- Description: Four buffer sequential primitive function calls are
-- provided. One is a simple buffer and the others
-- offer high and low enables and the four permits
-- propagation of Z as shown below:
--
-- VitalBUF Standard non-inverting buffer
-- VitalBUFIF0 Non-inverting buffer with Enable low
-- VitalBUFIF1 Non-inverting buffer with Enable high
-- VitalIDENT Pass buffer capable of propagating Z
--
-- Arguments:
--
-- IN Type Description
-- Data std_ulogic Input to the buffers
-- Enable std_ulogic Enable for the enable high and low
-- buffers.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- simple buffer.
-- VitalResultZMapType The output signal strength result map
-- to modify default result mapping
-- which has high impedance capability
-- for the enable high, enable low and
-- identity buffers.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic The output signal of the evaluated
-- buffer function.
--
-- -------------------------------------------------------------------------
FUNCTION VitalBUF (
CONSTANT Data : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalBUFIF0 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
FUNCTION VitalBUFIF1 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
FUNCTION VitalIDENT (
CONSTANT Data : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: Buffer device procedure calls.
--
-- Description: Four buffer concurrent primitive procedure calls are
-- provided. One is a simple buffer and the others
-- offer high and low enables and the fourth permits
-- propagation of Z as shown below:
--
-- VitalBUF Standard non-inverting buffer
-- VitalBUFIF0 Non-inverting buffer with Enable low
-- VitalBUFIF1 Non-inverting buffer with Enable high
-- VitalIDENT Pass buffer capable of propagating Z
--
-- Arguments:
--
-- IN Type Description
-- a std_ulogic Input signal to the buffers
-- Enable std_ulogic Enable signal for the enable high and
-- low buffers.
-- tpd_a_q VitalDelayType01 Propagation delay from input to
-- output for the simple buffer.
-- VitalDelayType01Z Propagation delay from input to
-- to output for the enable high and low
-- and identity buffers.
-- tpd_enable_q VitalDelayType01Z Propagation delay from enable to
-- output for the enable high and low
-- buffers.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- simple buffer.
-- VitalResultZMapType The output signal strength result map
-- to modify default result mapping
-- which has high impedance capability
-- for the enable high, enable low and
-- identity buffers.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic Output of the buffers.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalBUF (
SIGNAL q : OUT std_ulogic;
SIGNAL a : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalBUFIF0 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap);
PROCEDURE VitalBUFIF1 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap);
PROCEDURE VitalIDENT (
SIGNAL q : OUT std_ulogic;
SIGNAL a : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap );
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: VitalINV, VitalINVIF0, VitalINVIF1
--
-- Description: Inverter functions which return the inverted signal
-- value. Inverters with enable low and high are provided
-- which can drive high impedance when inactive.
--
-- Arguments:
--
-- IN Type Description
-- Data std_ulogic Input to the inverter
-- Enable std_ulogic Enable to the enable high and low
-- inverters.
-- ResultMap VitalResultMap The output signal strength result map
-- to modify default result mapping for
-- simple inverter.
-- VitalResultZMapType The output signal strength result map
-- to modify default result mapping
-- which has high impedance capability
-- for the enable high, enable low
-- inverters.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic Output of the inverter
--
-- -------------------------------------------------------------------------
FUNCTION VitalINV (
CONSTANT Data : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalINVIF0 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
FUNCTION VitalINVIF1 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: VitalINV, VitalINVIF0, VitalINVIF1
--
-- Description: The concurrent primitive procedure calls implement a
-- signal inversion function. The output is a parameter to
-- the procedure. The path delay information is passed as
-- a parameter to the call.
--
-- Arguments:
--
-- IN Type Description
-- a std_ulogic Input signal for the simple inverter
-- Data std_ulogic Input signal for the enable high and
-- low inverters.
-- Enable std_ulogic Enable signal for the enable high and
-- low inverters.
-- tpd_a_q VitalDelayType01 Propagation delay from input a to
-- output q for the simple inverter.
-- tpd_data_q VitalDelayType01 Propagation delay from input data to
-- output q for the enable high and low
-- inverters.
-- tpd_enable_q VitalDelayType01Z Propagation delay from input enable
-- to output q for the enable high and
-- low inverters.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- simple inverter.
-- VitalResultZMapType The output signal strength result map
-- to modify default result mapping
-- which has high impedance capability
-- for the enable high, enable low
-- inverters.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic Output signal of the inverter.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalINV (
SIGNAL q : OUT std_ulogic;
SIGNAL a : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalINVIF0 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap);
PROCEDURE VitalINVIF1 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap);
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: VitalMUX, VitalMUX2, VitalMUX4, VitalMUX8
--
-- Description: The VitalMUX functions return the selected data bit
-- based on the value of dSelect. For MUX2, the function
-- returns data0 when dselect is 0 and returns data1 when
-- dselect is 1. When dselect is X, result is X for MUX2
-- when data0 /= data1. X propagation is reduced when the
-- dselect signal is X and both data signals are identical.
-- When this is the case, the result returned is the value
-- of the data signals.
--
-- For the N input device:
--
-- N must equal 2**(bits of dSelect)
--
-- Arguments:
--
-- IN Type Description
-- Data std_logic_vector Input signal for the N-bit, 4-bit and
-- 8-bit mux.
-- Data1,Data0 std_ulogic Input signals for the 2-bit mux.
-- dSelect std_ulogic Select signal for 2-bit mux
-- std_logic_vector2 Select signal for 4-bit mux
-- std_logic_vector3 Select signal for 8-bit mux
-- std_logic_vector Select signal for N-Bit mux
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- all muxes.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic The value of the selected bit is
-- returned.
--
-- -------------------------------------------------------------------------
FUNCTION VitalMUX (
CONSTANT Data : IN std_logic_vector;
CONSTANT dSelect : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalMUX2 (
CONSTANT Data1, Data0 : IN std_ulogic;
CONSTANT dSelect : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalMUX4 (
CONSTANT Data : IN std_logic_vector4;
CONSTANT dSelect : IN std_logic_vector2;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalMUX8 (
CONSTANT Data : IN std_logic_vector8;
CONSTANT dSelect : IN std_logic_vector3;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: VitalMUX, VitalMUX2, VitalMUX4, VitalMUX8
--
-- Description: The VitalMUX concurrent primitive procedures calls
-- return in the output q the value of the selected data
-- bit based on the value of dsel. For the two bit mux,
-- the data returned is either d0 or d1, the data input.
-- For 4, 8 and N-bit functions, data is the input and is
-- of type std_logic_vector. For the 2-bit mux, if d0 or
-- d1 are X, the output is X only when d0 do not equal d1.
-- When d0 and d1 are equal, the return value is this value
-- to reduce X propagation.
--
-- Propagation delay information is passed as a parameter
-- to the procedure call for delays from data to output and
-- select to output. For 2-bit muxes, the propagation
-- delays from data are provided for d0 and d1 to output.
--
--
-- Arguments:
--
-- IN Type Description
-- d1,d0 std_ulogic Input signals for the 2-bit mux.
-- Data std_logic_vector4 Input signals for the 4-bit mux.
-- std_logic_vector8 Input signals for the 8-bit mux.
-- std_logic_vector Input signals for the N-bit mux.
-- dsel std_ulogic Select signal for the 2-bit mux.
-- std_logic_vector2 Select signals for the 4-bit mux.
-- std_logic_vector3 Select signals for the 8-bit mux.
-- std_logic_vector Select signals for the N-bit mux.
-- tpd_d1_q VitalDelayType01 Propagation delay from input d1 to
-- output q for 2-bit mux.
-- tpd_d0_q VitalDelayType01 Propagation delay from input d0 to
-- output q for 2-bit mux.
-- tpd_data_q VitalDelayArrayType01 Propagation delay from input data
-- to output q for 4-bit, 8-bit and
-- N-bit muxes.
-- tpd_dsel_q VitalDelayType01 Propagation delay from input dsel
-- to output q for 2-bit mux.
-- VitalDelayArrayType01 Propagation delay from input dsel
-- to output q for 4-bit, 8-bit and
-- N-bit muxes.
-- ResultMap VitalResultMapType The output signal strength result
-- map to modify default result
-- mapping for all muxes.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic The value of the selected signal.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalMUX (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
SIGNAL dSel : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_dsel_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalMUX2 (
SIGNAL q : OUT std_ulogic;
SIGNAL d1, d0 : IN std_ulogic;
SIGNAL dSel : IN std_ulogic;
CONSTANT tpd_d1_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d0_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_dsel_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalMUX4 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector4;
SIGNAL dSel : IN std_logic_vector2;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_dsel_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalMUX8 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector8;
SIGNAL dSel : IN std_logic_vector3;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_dsel_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: VitalDECODER, VitalDECODER2, VitalDECODER4,
-- VitalDECODER8
--
-- Description: The VitalDECODER functions are the sequential primitive
-- calls for decoder logic. The functions are provided
-- for N, 2, 4 and 8-bit outputs.
--
-- The N-bit decoder is (2**(bits of data)) wide.
--
-- The VitalDECODER returns 0 if enable is 0.
-- The VitalDECODER returns the result bit set to 1 if
-- enable is 1. All other bits of returned result are
-- set to 0.
--
-- The returned array is in descending order:
-- (n-1 downto 0).
--
-- Arguments:
--
-- IN Type Description
-- Data std_ulogic Input signal for 2-bit decoder.
-- std_logic_vector2 Input signals for 4-bit decoder.
-- std_logic_vector3 Input signals for 8-bit decoder.
-- std_logic_vector Input signals for N-bit decoder.
-- Enable std_ulogic Enable input signal. The result is
-- output when enable is high.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- all output signals of the decoders.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_logic_vector2 The output of the 2-bit decoder.
-- std_logic_vector4 The output of the 4-bit decoder.
-- std_logic_vector8 The output of the 8-bit decoder.
-- std_logic_vector The output of the n-bit decoder.
--
-- -------------------------------------------------------------------------
FUNCTION VitalDECODER (
CONSTANT Data : IN std_logic_vector;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector;
FUNCTION VitalDECODER2 (
CONSTANT Data : IN std_ulogic;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector2;
FUNCTION VitalDECODER4 (
CONSTANT Data : IN std_logic_vector2;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector4;
FUNCTION VitalDECODER8 (
CONSTANT Data : IN std_logic_vector3;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector8;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: VitalDECODER, VitalDECODER2, VitalDECODER4,
-- VitalDECODER8
--
-- Description: The VitalDECODER procedures are the concurrent primitive
-- procedure calls for decoder functions. The procedures
-- are provided for N, 2, 4 and 8 outputs.
--
-- The N-bit decoder is (2**(bits of data)) wide.
--
-- The procedural form of the decoder is used for
-- distributed delay modeling. The delay information for
-- each path is passed as an argument to the procedure.
--
-- Result is set to 0 if enable is 0.
-- The result bit represented by data is set to 1 if
-- enable is 1. All other bits of result are set to 0.
--
-- The result array is in descending order: (n-1 downto 0).
--
-- For the N-bit decoder, the delay path is a vector of
-- delays from inputs to outputs.
--
-- Arguments:
--
-- IN Type Description
-- Data std_ulogic Input signal for 2-bit decoder.
-- std_logic_vector2 Input signals for 4-bit decoder.
-- std_logic_vector3 Input signals for 8-bit decoder.
-- std_logic_vector Input signals for N-bit decoder.
-- enable std_ulogic Enable input signal. The result is
-- output when enable is high.
-- tpd_data_q VitalDelayType01 Propagation delay from input data
-- to output q for 2-bit decoder.
-- VitalDelayArrayType01 Propagation delay from input data
-- to output q for 4, 8 and n-bit
-- decoders.
-- tpd_enable_q VitalDelayType01 Propagation delay from input enable
-- to output q for 2, 4, 8 and n-bit
-- decoders.
--
-- INOUT
-- none
--
-- OUT
-- q std_logic_vector2 Output signals for 2-bit decoder.
-- std_logic_vector4 Output signals for 4-bit decoder.
-- std_logic_vector8 Output signals for 8-bit decoder.
-- std_logic_vector Output signals for n-bit decoder.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalDECODER (
SIGNAL q : OUT std_logic_vector;
SIGNAL Data : IN std_logic_vector;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalDECODER2 (
SIGNAL q : OUT std_logic_vector2;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalDECODER4 (
SIGNAL q : OUT std_logic_vector4;
SIGNAL Data : IN std_logic_vector2;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalDECODER8 (
SIGNAL q : OUT std_logic_vector8;
SIGNAL Data : IN std_logic_vector3;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
-- -------------------------------------------------------------------------
-- Function Name: VitalTruthTable
--
-- Description: VitalTruthTable implements a truth table. Given
-- a set of inputs, a sequential search is performed
-- to match the input. If a match is found, the output
-- is set based on the contents of the CONSTANT TruthTable.
-- If there is no match, all X's are returned. There is
-- no limit to the size of the table.
--
-- There is a procedure and function for VitalTruthTable.
-- For each of these, a single value output (std_logic) and
-- a multi-value output (std_logic_vector) are provided.
--
-- The first dimension of the table is for number of
-- entries in the truth table and second dimension is for
-- the number of elements in a row. The number of inputs
-- in the row should be Data'LENGTH plus result'LENGTH.
--
-- Elements is a row will be interpreted as
-- Input(NumInputs - 1),.., Input(0),
-- Result(NumOutputs - 1),.., Result(0)
--
-- All inputs will be mapped to the X01 subtype
--
-- If the value of Result is not in the range 'X' to 'Z'
-- then an error will be reported. Also, the Result is
-- always given either as a 0, 1, X or Z value.
--
-- Arguments:
--
-- IN Type Description
-- TruthTable The input constant which defines the
-- behavior in truth table form.
-- DataIn The inputs to the truth table used to
-- perform input match to select
-- output(s) to value(s) to drive.
--
-- INOUT
-- none
--
-- OUT
-- Result std_logic Concurrent procedure version scalar
-- output.
-- std_logic_vector Concurrent procedure version vector
-- output.
--
-- Returns
-- Result std_logic Function version scalar output.
-- std_logic_vector Function version vector output.
--
-- -------------------------------------------------------------------------
FUNCTION VitalTruthTable (
CONSTANT TruthTable : IN VitalTruthTableType;
CONSTANT DataIn : IN std_logic_vector
) RETURN std_logic_vector;
FUNCTION VitalTruthTable (
CONSTANT TruthTable : IN VitalTruthTableType;
CONSTANT DataIn : IN std_logic_vector
) RETURN std_logic;
PROCEDURE VitalTruthTable (
SIGNAL Result : OUT std_logic_vector;
CONSTANT TruthTable : IN VitalTruthTableType;
SIGNAL DataIn : IN std_logic_vector -- IR#236
);
PROCEDURE VitalTruthTable (
SIGNAL Result : OUT std_logic;
CONSTANT TruthTable : IN VitalTruthTableType;
SIGNAL DataIn : IN std_logic_vector -- IR#236
);
-- -------------------------------------------------------------------------
--
-- Function Name: VitalStateTable
--
-- Description: VitalStateTable is a non-concurrent implementation of a
-- state machine (Moore Machine). It is used to model
-- sequential devices and devices with internal states.
--
-- The procedure takes the value of the state table
-- data set and performs a sequential search of the
-- CONSTANT StateTable until a match is found. Once a
-- match is found, the result of that match is applied
-- to Result. If there is no match, all X's are returned.
-- The resultant output becomes the input for the next
-- state.
--
-- The first dimension of the table is the number of
-- entries in the state table and second dimension is the
-- number of elements in a row of the table. The number of
-- inputs in the row should be DataIn'LENGTH. Result should
-- contain the current state (which will become the next
-- state) as well as the outputs
--
-- Elements is a row of the table will be interpreted as
-- Input(NumInputs-1),.., Input(0), State(NumStates-1),
-- ..., State(0),Output(NumOutputs-1),.., Output(0)
--
-- where State(numStates-1) DOWNTO State(0) represent the
-- present state and Output(NumOutputs - 1) DOWNTO
-- Outputs(NumOutputs - NumStates) represent the new
-- values of the state variables (i.e. the next state).
-- Also, Output(NumOutputs - NumStates - 1)
--
-- This procedure returns the next state and the new
-- outputs when a match is made between the present state
-- and present inputs and the state table. A search is
-- made starting at the top of the state table and
-- terminates with the first match. If no match is found
-- then the next state and new outputs are set to all 'X's.
--
-- (Asynchronous inputs (i.e. resets and clears) must be
-- handled by placing the corresponding entries at the top
-- of the table. )
--
-- All inputs will be mapped to the X01 subtype.
--
-- NOTE: Edge transitions should not be used as values
-- for the state variables in the present state
-- portion of the state table. The only valid
-- values that can be used for the present state
-- portion of the state table are:
-- 'X', '0', '1', 'B', '-'
--
-- Arguments:
--
-- IN Type Description
-- StateTable VitalStateTableType The input constant which defines
-- the behavior in state table form.
-- DataIn std_logic_vector The current state inputs to the
-- state table used to perform input
-- matches and transition
-- calculations.
-- NumStates NATURAL Number of state variables
--
-- INOUT
-- Result std_logic Output signal for scalar version of
-- the concurrent procedure call.
-- std_logic_vector Output signals for vector version
-- of the concurrent procedure call.
-- PreviousDataIn std_logic_vector The previous inputs and states used
-- in transition calculations and to
-- set outputs for steady state cases.
--
-- OUT
-- none
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalStateTable (
VARIABLE Result : INOUT std_logic_vector;
VARIABLE PreviousDataIn : INOUT std_logic_vector;
CONSTANT StateTable : IN VitalStateTableType;
CONSTANT DataIn : IN std_logic_vector;
CONSTANT NumStates : IN NATURAL
);
PROCEDURE VitalStateTable (
VARIABLE Result : INOUT std_logic;
VARIABLE PreviousDataIn : INOUT std_logic_vector;
CONSTANT StateTable : IN VitalStateTableType;
CONSTANT DataIn : IN std_logic_vector
);
PROCEDURE VitalStateTable (
SIGNAL Result : INOUT std_logic_vector;
CONSTANT StateTable : IN VitalStateTableType;
SIGNAL DataIn : IN std_logic_vector;
CONSTANT NumStates : IN NATURAL
);
PROCEDURE VitalStateTable (
SIGNAL Result : INOUT std_logic;
CONSTANT StateTable : IN VitalStateTableType;
SIGNAL DataIn : IN std_logic_vector
);
-- -------------------------------------------------------------------------
--
-- Function Name: VitalResolve
--
-- Description: VitalResolve takes a vector of signals and resolves
-- them to a std_ulogic value. This procedure can be used
-- to resolve multiple drivers in a single model.
--
-- Arguments:
--
-- IN Type Description
-- Data std_logic_vector Set of input signals which drive a
-- common signal.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic Output signal which is the resolved
-- value being driven by the collection of
-- input signals.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalResolve (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector); --IR236 4/2/98
END VITAL_Primitives;
|
-- -----------------------------------------------------------------------------
-- Title : Standard VITAL_Primitives Package
-- : $Revision$
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers : IEEE DASC Timing Working Group (TWG), PAR 1076.4
-- :
-- Purpose : This packages defines standard types, constants, functions
-- : and procedures for use in developing ASIC models.
-- : Specifically a set of logic primitives are defined.
-- :
-- Known Errors :
-- :
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the objects (types, subtypes, constants, functions,
-- : procedures ... etc.) that can be used by a user. The package
-- : body shall be considered the formal definition of the
-- : semantics of this package. Tool developers may choose to
-- : implement the package body in the most efficient manner
-- : available to them.
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Acknowledgments:
-- This code was originally developed under the "VHDL Initiative Toward ASIC
-- Libraries" (VITAL), an industry sponsored initiative. Technical
-- Director: William Billowitch, VHDL Technology Group; U.S. Coordinator:
-- Steve Schultz; Steering Committee Members: Victor Berman, Cadence Design
-- Systems; Oz Levia, Synopsys Inc.; Ray Ryan, Ryan & Ryan; Herman van Beek,
-- Texas Instruments; Victor Martin, Hewlett-Packard Company.
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Modification History :
-- ----------------------------------------------------------------------------
-- Version No:|Auth:| Mod.Date:| Changes Made:
-- v95.0 A | | 06/02/95 | Initial ballot draft 1995
-- ----------------------------------------------------------------------------
-- v95.3 | ddl | 09/24/96 | #236 - VitalTruthTable DataIn should be of
-- | | | of class SIGNAL (PROPOSED)
-- ----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
USE IEEE.VITAL_Timing.ALL;
PACKAGE VITAL_Primitives IS
-- ------------------------------------------------------------------------
-- Type and Subtype Declarations
-- ------------------------------------------------------------------------
-- For Truth and State Tables
SUBTYPE VitalTruthSymbolType IS VitalTableSymbolType RANGE 'X' TO 'Z';
SUBTYPE VitalStateSymbolType IS VitalTableSymbolType RANGE '/' TO 'S';
TYPE VitalTruthTableType IS ARRAY ( NATURAL RANGE <>, NATURAL RANGE <> )
OF VitalTruthSymbolType;
TYPE VitalStateTableType IS ARRAY ( NATURAL RANGE <>, NATURAL RANGE <> )
OF VitalStateSymbolType;
-- ---------------------------------
-- Default values used by primitives
-- ---------------------------------
CONSTANT VitalDefDelay01 : VitalDelayType01; -- Propagation delays
CONSTANT VitalDefDelay01Z : VitalDelayType01Z;
-- ------------------------------------------------------------------------
-- VITAL Primitives
--
-- The primitives packages contains a collections of common gates,
-- including AND, OR, XOR, NAND, NOR, XNOR, BUF, INV, MUX and DECODER
-- functions. In addition, for sequential devices, a STATE TABLE construct
-- is provided. For complex functions a modeler may wish to use either
-- a collection of connected VITAL primitives, or a TRUTH TABLE construct.
--
-- For each primitive a Function and Procedure is provided. The primitive
-- functions are provided to support behavioral modeling styles. The
-- primitive procedures are provided to support structural modeling styles.
--
-- The procedures wait internally for an event on an input signal, compute
-- the new result, perform glitch handling, schedule transaction on the
-- output signals, and wait for future input events. All of the functional
-- (logic) input or output parameters of the primitive procedures are
-- signals. All the other parameters are constants.
--
-- The procedure primitives are parameterized for separate path delays
-- from each input signal. All path delays default to 0 ns.
--
-- The sequential primitive functions compute the defined function and
-- return a value of type std_ulogic or std_logic_vector. All parameters
-- of the primitive functions are constants of mode IN.
--
-- The primitives are based on 1164 operators. The user may also elect to
-- express functions using the 1164 operators as well. These styles are
-- all equally acceptable methods for device modeling.
--
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: N-input logic device function calls:
-- VitalAND VitalOR VitalXOR
-- VitalNAND VitalNOR VitalXNOR
--
-- Description: The function calls return the evaluated logic function
-- corresponding to the function name.
--
-- Arguments:
--
-- IN Type Description
-- Data std_logic_vector The input signals for the n-bit
-- wide logic functions.
-- ResultMap VitalResultMapType The output signal strength
-- result map to modify default
-- result mapping.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic The evaluated logic function of
-- the n-bit wide primitives.
--
-- -------------------------------------------------------------------------
FUNCTION VitalAND (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNAND (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXNOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: N-input logic device concurrent procedure calls.
-- VitalAND VitalOR VitalXOR
-- VitalNAND VitalNOR VitalXNOR
--
-- Description: The procedure calls return the evaluated logic function
-- corresponding to the function name as a parameter to the
-- procedure. Propagation delay form data to q is a
-- a parameter to the procedure. A vector of delay values
-- for inputs to output are provided. It is noted that
-- limitations in SDF make the back annotation of the delay
-- array difficult.
--
-- Arguments:
--
-- IN Type Description
-- Data std_logic_vector The input signals for the n-
-- bit wide logic functions.
-- tpd_data_q VitalDelayArrayType01 The propagation delay from
-- the data inputs to the output
-- q.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic The output signal of the
-- evaluated logic function.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalAND (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNAND (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXNOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
-- -------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: 2,3 and 4 input logic device function calls.
--
-- VitalAND2 VitalOR2 VitalXOR2
-- VitalAND3 VitalOR3 VitalXOR3
-- VitalAND4 VitalOR4 VitalXOR4
--
-- VitalNAND2 VitalNOR2 VitalXNOR2
-- VitalNAND3 VitalNOR3 VitalXNOR3
-- VitalNAND4 VitalNOR4 VitalXNOR4
--
-- Description: The function calls return the evaluated 2, 3 or 4 input
-- logic function corresponding to the function name.
--
-- Arguments:
--
-- IN Type Description
-- a, b, c, d std_ulogic 2 input devices have a and b as
-- inputs. 3 input devices have a, b
-- and c as inputs. 4 input devices
-- have a, b, c and d as inputs.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic The result of the evaluated logic
-- function.
--
-- -------------------------------------------------------------------------
FUNCTION VitalAND2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNAND2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXNOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalAND3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNAND3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXNOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalAND4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNAND4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXNOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: 2, 3 and 4 input logic device concurrent procedure
-- calls.
--
-- VitalAND2 VitalOR2 VitalXOR2
-- VitalAND3 VitalOR3 VitalXOR3
-- VitalAND4 VitalOR4 VitalXOR4
--
-- VitalNAND2 VitalNOR2 VitalXNOR2
-- VitalNAND3 VitalNOR3 VitalXNOR3
-- VitalNAND4 VitalNOR4 VitalXNOR4
--
-- Description: The procedure calls return the evaluated logic function
-- corresponding to the function name as a parameter to the
-- procedure. Propagation delays from a and b to q are
-- a parameter to the procedure. The default propagation
-- delay is 0 ns.
--
-- Arguments:
--
-- IN Type Description
-- a, b, c, d std_ulogic 2 input devices have a and b as
-- inputs. 3 input devices have a, b
-- and c as inputs. 4 input devices
-- have a, b, c and d as inputs.
-- tpd_a_q VitalDelayType01 The propagation delay from the a
-- input to output q for 2, 3 and 4
-- input devices.
-- tpd_b_q VitalDelayType01 The propagation delay from the b
-- input to output q for 2, 3 and 4
-- input devices.
-- tpd_c_q VitalDelayType01 The propagation delay from the c
-- input to output q for 3 and 4 input
-- devices.
-- tpd_d_q VitalDelayType01 The propagation delay from the d
-- input to output q for 4 input
-- devices.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic The output signal of the evaluated
-- logic function.
--
-- Returns
-- none
-- -------------------------------------------------------------------------
PROCEDURE VitalAND2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNAND2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXNOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalAND3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNAND3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXNOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalAND4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNAND4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXNOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: Buffer logic device concurrent procedure calls.
--
-- Description: Four buffer sequential primitive function calls are
-- provided. One is a simple buffer and the others
-- offer high and low enables and the four permits
-- propagation of Z as shown below:
--
-- VitalBUF Standard non-inverting buffer
-- VitalBUFIF0 Non-inverting buffer with Enable low
-- VitalBUFIF1 Non-inverting buffer with Enable high
-- VitalIDENT Pass buffer capable of propagating Z
--
-- Arguments:
--
-- IN Type Description
-- Data std_ulogic Input to the buffers
-- Enable std_ulogic Enable for the enable high and low
-- buffers.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- simple buffer.
-- VitalResultZMapType The output signal strength result map
-- to modify default result mapping
-- which has high impedance capability
-- for the enable high, enable low and
-- identity buffers.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic The output signal of the evaluated
-- buffer function.
--
-- -------------------------------------------------------------------------
FUNCTION VitalBUF (
CONSTANT Data : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalBUFIF0 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
FUNCTION VitalBUFIF1 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
FUNCTION VitalIDENT (
CONSTANT Data : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: Buffer device procedure calls.
--
-- Description: Four buffer concurrent primitive procedure calls are
-- provided. One is a simple buffer and the others
-- offer high and low enables and the fourth permits
-- propagation of Z as shown below:
--
-- VitalBUF Standard non-inverting buffer
-- VitalBUFIF0 Non-inverting buffer with Enable low
-- VitalBUFIF1 Non-inverting buffer with Enable high
-- VitalIDENT Pass buffer capable of propagating Z
--
-- Arguments:
--
-- IN Type Description
-- a std_ulogic Input signal to the buffers
-- Enable std_ulogic Enable signal for the enable high and
-- low buffers.
-- tpd_a_q VitalDelayType01 Propagation delay from input to
-- output for the simple buffer.
-- VitalDelayType01Z Propagation delay from input to
-- to output for the enable high and low
-- and identity buffers.
-- tpd_enable_q VitalDelayType01Z Propagation delay from enable to
-- output for the enable high and low
-- buffers.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- simple buffer.
-- VitalResultZMapType The output signal strength result map
-- to modify default result mapping
-- which has high impedance capability
-- for the enable high, enable low and
-- identity buffers.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic Output of the buffers.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalBUF (
SIGNAL q : OUT std_ulogic;
SIGNAL a : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalBUFIF0 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap);
PROCEDURE VitalBUFIF1 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap);
PROCEDURE VitalIDENT (
SIGNAL q : OUT std_ulogic;
SIGNAL a : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap );
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: VitalINV, VitalINVIF0, VitalINVIF1
--
-- Description: Inverter functions which return the inverted signal
-- value. Inverters with enable low and high are provided
-- which can drive high impedance when inactive.
--
-- Arguments:
--
-- IN Type Description
-- Data std_ulogic Input to the inverter
-- Enable std_ulogic Enable to the enable high and low
-- inverters.
-- ResultMap VitalResultMap The output signal strength result map
-- to modify default result mapping for
-- simple inverter.
-- VitalResultZMapType The output signal strength result map
-- to modify default result mapping
-- which has high impedance capability
-- for the enable high, enable low
-- inverters.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic Output of the inverter
--
-- -------------------------------------------------------------------------
FUNCTION VitalINV (
CONSTANT Data : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalINVIF0 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
FUNCTION VitalINVIF1 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: VitalINV, VitalINVIF0, VitalINVIF1
--
-- Description: The concurrent primitive procedure calls implement a
-- signal inversion function. The output is a parameter to
-- the procedure. The path delay information is passed as
-- a parameter to the call.
--
-- Arguments:
--
-- IN Type Description
-- a std_ulogic Input signal for the simple inverter
-- Data std_ulogic Input signal for the enable high and
-- low inverters.
-- Enable std_ulogic Enable signal for the enable high and
-- low inverters.
-- tpd_a_q VitalDelayType01 Propagation delay from input a to
-- output q for the simple inverter.
-- tpd_data_q VitalDelayType01 Propagation delay from input data to
-- output q for the enable high and low
-- inverters.
-- tpd_enable_q VitalDelayType01Z Propagation delay from input enable
-- to output q for the enable high and
-- low inverters.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- simple inverter.
-- VitalResultZMapType The output signal strength result map
-- to modify default result mapping
-- which has high impedance capability
-- for the enable high, enable low
-- inverters.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic Output signal of the inverter.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalINV (
SIGNAL q : OUT std_ulogic;
SIGNAL a : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalINVIF0 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap);
PROCEDURE VitalINVIF1 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap);
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: VitalMUX, VitalMUX2, VitalMUX4, VitalMUX8
--
-- Description: The VitalMUX functions return the selected data bit
-- based on the value of dSelect. For MUX2, the function
-- returns data0 when dselect is 0 and returns data1 when
-- dselect is 1. When dselect is X, result is X for MUX2
-- when data0 /= data1. X propagation is reduced when the
-- dselect signal is X and both data signals are identical.
-- When this is the case, the result returned is the value
-- of the data signals.
--
-- For the N input device:
--
-- N must equal 2**(bits of dSelect)
--
-- Arguments:
--
-- IN Type Description
-- Data std_logic_vector Input signal for the N-bit, 4-bit and
-- 8-bit mux.
-- Data1,Data0 std_ulogic Input signals for the 2-bit mux.
-- dSelect std_ulogic Select signal for 2-bit mux
-- std_logic_vector2 Select signal for 4-bit mux
-- std_logic_vector3 Select signal for 8-bit mux
-- std_logic_vector Select signal for N-Bit mux
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- all muxes.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic The value of the selected bit is
-- returned.
--
-- -------------------------------------------------------------------------
FUNCTION VitalMUX (
CONSTANT Data : IN std_logic_vector;
CONSTANT dSelect : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalMUX2 (
CONSTANT Data1, Data0 : IN std_ulogic;
CONSTANT dSelect : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalMUX4 (
CONSTANT Data : IN std_logic_vector4;
CONSTANT dSelect : IN std_logic_vector2;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalMUX8 (
CONSTANT Data : IN std_logic_vector8;
CONSTANT dSelect : IN std_logic_vector3;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: VitalMUX, VitalMUX2, VitalMUX4, VitalMUX8
--
-- Description: The VitalMUX concurrent primitive procedures calls
-- return in the output q the value of the selected data
-- bit based on the value of dsel. For the two bit mux,
-- the data returned is either d0 or d1, the data input.
-- For 4, 8 and N-bit functions, data is the input and is
-- of type std_logic_vector. For the 2-bit mux, if d0 or
-- d1 are X, the output is X only when d0 do not equal d1.
-- When d0 and d1 are equal, the return value is this value
-- to reduce X propagation.
--
-- Propagation delay information is passed as a parameter
-- to the procedure call for delays from data to output and
-- select to output. For 2-bit muxes, the propagation
-- delays from data are provided for d0 and d1 to output.
--
--
-- Arguments:
--
-- IN Type Description
-- d1,d0 std_ulogic Input signals for the 2-bit mux.
-- Data std_logic_vector4 Input signals for the 4-bit mux.
-- std_logic_vector8 Input signals for the 8-bit mux.
-- std_logic_vector Input signals for the N-bit mux.
-- dsel std_ulogic Select signal for the 2-bit mux.
-- std_logic_vector2 Select signals for the 4-bit mux.
-- std_logic_vector3 Select signals for the 8-bit mux.
-- std_logic_vector Select signals for the N-bit mux.
-- tpd_d1_q VitalDelayType01 Propagation delay from input d1 to
-- output q for 2-bit mux.
-- tpd_d0_q VitalDelayType01 Propagation delay from input d0 to
-- output q for 2-bit mux.
-- tpd_data_q VitalDelayArrayType01 Propagation delay from input data
-- to output q for 4-bit, 8-bit and
-- N-bit muxes.
-- tpd_dsel_q VitalDelayType01 Propagation delay from input dsel
-- to output q for 2-bit mux.
-- VitalDelayArrayType01 Propagation delay from input dsel
-- to output q for 4-bit, 8-bit and
-- N-bit muxes.
-- ResultMap VitalResultMapType The output signal strength result
-- map to modify default result
-- mapping for all muxes.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic The value of the selected signal.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalMUX (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
SIGNAL dSel : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_dsel_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalMUX2 (
SIGNAL q : OUT std_ulogic;
SIGNAL d1, d0 : IN std_ulogic;
SIGNAL dSel : IN std_ulogic;
CONSTANT tpd_d1_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d0_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_dsel_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalMUX4 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector4;
SIGNAL dSel : IN std_logic_vector2;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_dsel_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalMUX8 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector8;
SIGNAL dSel : IN std_logic_vector3;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_dsel_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: VitalDECODER, VitalDECODER2, VitalDECODER4,
-- VitalDECODER8
--
-- Description: The VitalDECODER functions are the sequential primitive
-- calls for decoder logic. The functions are provided
-- for N, 2, 4 and 8-bit outputs.
--
-- The N-bit decoder is (2**(bits of data)) wide.
--
-- The VitalDECODER returns 0 if enable is 0.
-- The VitalDECODER returns the result bit set to 1 if
-- enable is 1. All other bits of returned result are
-- set to 0.
--
-- The returned array is in descending order:
-- (n-1 downto 0).
--
-- Arguments:
--
-- IN Type Description
-- Data std_ulogic Input signal for 2-bit decoder.
-- std_logic_vector2 Input signals for 4-bit decoder.
-- std_logic_vector3 Input signals for 8-bit decoder.
-- std_logic_vector Input signals for N-bit decoder.
-- Enable std_ulogic Enable input signal. The result is
-- output when enable is high.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- all output signals of the decoders.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_logic_vector2 The output of the 2-bit decoder.
-- std_logic_vector4 The output of the 4-bit decoder.
-- std_logic_vector8 The output of the 8-bit decoder.
-- std_logic_vector The output of the n-bit decoder.
--
-- -------------------------------------------------------------------------
FUNCTION VitalDECODER (
CONSTANT Data : IN std_logic_vector;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector;
FUNCTION VitalDECODER2 (
CONSTANT Data : IN std_ulogic;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector2;
FUNCTION VitalDECODER4 (
CONSTANT Data : IN std_logic_vector2;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector4;
FUNCTION VitalDECODER8 (
CONSTANT Data : IN std_logic_vector3;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector8;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: VitalDECODER, VitalDECODER2, VitalDECODER4,
-- VitalDECODER8
--
-- Description: The VitalDECODER procedures are the concurrent primitive
-- procedure calls for decoder functions. The procedures
-- are provided for N, 2, 4 and 8 outputs.
--
-- The N-bit decoder is (2**(bits of data)) wide.
--
-- The procedural form of the decoder is used for
-- distributed delay modeling. The delay information for
-- each path is passed as an argument to the procedure.
--
-- Result is set to 0 if enable is 0.
-- The result bit represented by data is set to 1 if
-- enable is 1. All other bits of result are set to 0.
--
-- The result array is in descending order: (n-1 downto 0).
--
-- For the N-bit decoder, the delay path is a vector of
-- delays from inputs to outputs.
--
-- Arguments:
--
-- IN Type Description
-- Data std_ulogic Input signal for 2-bit decoder.
-- std_logic_vector2 Input signals for 4-bit decoder.
-- std_logic_vector3 Input signals for 8-bit decoder.
-- std_logic_vector Input signals for N-bit decoder.
-- enable std_ulogic Enable input signal. The result is
-- output when enable is high.
-- tpd_data_q VitalDelayType01 Propagation delay from input data
-- to output q for 2-bit decoder.
-- VitalDelayArrayType01 Propagation delay from input data
-- to output q for 4, 8 and n-bit
-- decoders.
-- tpd_enable_q VitalDelayType01 Propagation delay from input enable
-- to output q for 2, 4, 8 and n-bit
-- decoders.
--
-- INOUT
-- none
--
-- OUT
-- q std_logic_vector2 Output signals for 2-bit decoder.
-- std_logic_vector4 Output signals for 4-bit decoder.
-- std_logic_vector8 Output signals for 8-bit decoder.
-- std_logic_vector Output signals for n-bit decoder.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalDECODER (
SIGNAL q : OUT std_logic_vector;
SIGNAL Data : IN std_logic_vector;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalDECODER2 (
SIGNAL q : OUT std_logic_vector2;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalDECODER4 (
SIGNAL q : OUT std_logic_vector4;
SIGNAL Data : IN std_logic_vector2;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalDECODER8 (
SIGNAL q : OUT std_logic_vector8;
SIGNAL Data : IN std_logic_vector3;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
-- -------------------------------------------------------------------------
-- Function Name: VitalTruthTable
--
-- Description: VitalTruthTable implements a truth table. Given
-- a set of inputs, a sequential search is performed
-- to match the input. If a match is found, the output
-- is set based on the contents of the CONSTANT TruthTable.
-- If there is no match, all X's are returned. There is
-- no limit to the size of the table.
--
-- There is a procedure and function for VitalTruthTable.
-- For each of these, a single value output (std_logic) and
-- a multi-value output (std_logic_vector) are provided.
--
-- The first dimension of the table is for number of
-- entries in the truth table and second dimension is for
-- the number of elements in a row. The number of inputs
-- in the row should be Data'LENGTH plus result'LENGTH.
--
-- Elements is a row will be interpreted as
-- Input(NumInputs - 1),.., Input(0),
-- Result(NumOutputs - 1),.., Result(0)
--
-- All inputs will be mapped to the X01 subtype
--
-- If the value of Result is not in the range 'X' to 'Z'
-- then an error will be reported. Also, the Result is
-- always given either as a 0, 1, X or Z value.
--
-- Arguments:
--
-- IN Type Description
-- TruthTable The input constant which defines the
-- behavior in truth table form.
-- DataIn The inputs to the truth table used to
-- perform input match to select
-- output(s) to value(s) to drive.
--
-- INOUT
-- none
--
-- OUT
-- Result std_logic Concurrent procedure version scalar
-- output.
-- std_logic_vector Concurrent procedure version vector
-- output.
--
-- Returns
-- Result std_logic Function version scalar output.
-- std_logic_vector Function version vector output.
--
-- -------------------------------------------------------------------------
FUNCTION VitalTruthTable (
CONSTANT TruthTable : IN VitalTruthTableType;
CONSTANT DataIn : IN std_logic_vector
) RETURN std_logic_vector;
FUNCTION VitalTruthTable (
CONSTANT TruthTable : IN VitalTruthTableType;
CONSTANT DataIn : IN std_logic_vector
) RETURN std_logic;
PROCEDURE VitalTruthTable (
SIGNAL Result : OUT std_logic_vector;
CONSTANT TruthTable : IN VitalTruthTableType;
SIGNAL DataIn : IN std_logic_vector -- IR#236
);
PROCEDURE VitalTruthTable (
SIGNAL Result : OUT std_logic;
CONSTANT TruthTable : IN VitalTruthTableType;
SIGNAL DataIn : IN std_logic_vector -- IR#236
);
-- -------------------------------------------------------------------------
--
-- Function Name: VitalStateTable
--
-- Description: VitalStateTable is a non-concurrent implementation of a
-- state machine (Moore Machine). It is used to model
-- sequential devices and devices with internal states.
--
-- The procedure takes the value of the state table
-- data set and performs a sequential search of the
-- CONSTANT StateTable until a match is found. Once a
-- match is found, the result of that match is applied
-- to Result. If there is no match, all X's are returned.
-- The resultant output becomes the input for the next
-- state.
--
-- The first dimension of the table is the number of
-- entries in the state table and second dimension is the
-- number of elements in a row of the table. The number of
-- inputs in the row should be DataIn'LENGTH. Result should
-- contain the current state (which will become the next
-- state) as well as the outputs
--
-- Elements is a row of the table will be interpreted as
-- Input(NumInputs-1),.., Input(0), State(NumStates-1),
-- ..., State(0),Output(NumOutputs-1),.., Output(0)
--
-- where State(numStates-1) DOWNTO State(0) represent the
-- present state and Output(NumOutputs - 1) DOWNTO
-- Outputs(NumOutputs - NumStates) represent the new
-- values of the state variables (i.e. the next state).
-- Also, Output(NumOutputs - NumStates - 1)
--
-- This procedure returns the next state and the new
-- outputs when a match is made between the present state
-- and present inputs and the state table. A search is
-- made starting at the top of the state table and
-- terminates with the first match. If no match is found
-- then the next state and new outputs are set to all 'X's.
--
-- (Asynchronous inputs (i.e. resets and clears) must be
-- handled by placing the corresponding entries at the top
-- of the table. )
--
-- All inputs will be mapped to the X01 subtype.
--
-- NOTE: Edge transitions should not be used as values
-- for the state variables in the present state
-- portion of the state table. The only valid
-- values that can be used for the present state
-- portion of the state table are:
-- 'X', '0', '1', 'B', '-'
--
-- Arguments:
--
-- IN Type Description
-- StateTable VitalStateTableType The input constant which defines
-- the behavior in state table form.
-- DataIn std_logic_vector The current state inputs to the
-- state table used to perform input
-- matches and transition
-- calculations.
-- NumStates NATURAL Number of state variables
--
-- INOUT
-- Result std_logic Output signal for scalar version of
-- the concurrent procedure call.
-- std_logic_vector Output signals for vector version
-- of the concurrent procedure call.
-- PreviousDataIn std_logic_vector The previous inputs and states used
-- in transition calculations and to
-- set outputs for steady state cases.
--
-- OUT
-- none
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalStateTable (
VARIABLE Result : INOUT std_logic_vector;
VARIABLE PreviousDataIn : INOUT std_logic_vector;
CONSTANT StateTable : IN VitalStateTableType;
CONSTANT DataIn : IN std_logic_vector;
CONSTANT NumStates : IN NATURAL
);
PROCEDURE VitalStateTable (
VARIABLE Result : INOUT std_logic;
VARIABLE PreviousDataIn : INOUT std_logic_vector;
CONSTANT StateTable : IN VitalStateTableType;
CONSTANT DataIn : IN std_logic_vector
);
PROCEDURE VitalStateTable (
SIGNAL Result : INOUT std_logic_vector;
CONSTANT StateTable : IN VitalStateTableType;
SIGNAL DataIn : IN std_logic_vector;
CONSTANT NumStates : IN NATURAL
);
PROCEDURE VitalStateTable (
SIGNAL Result : INOUT std_logic;
CONSTANT StateTable : IN VitalStateTableType;
SIGNAL DataIn : IN std_logic_vector
);
-- -------------------------------------------------------------------------
--
-- Function Name: VitalResolve
--
-- Description: VitalResolve takes a vector of signals and resolves
-- them to a std_ulogic value. This procedure can be used
-- to resolve multiple drivers in a single model.
--
-- Arguments:
--
-- IN Type Description
-- Data std_logic_vector Set of input signals which drive a
-- common signal.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic Output signal which is the resolved
-- value being driven by the collection of
-- input signals.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalResolve (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector); --IR236 4/2/98
END VITAL_Primitives;
|
-- -----------------------------------------------------------------------------
-- Title : Standard VITAL_Primitives Package
-- : $Revision$
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers : IEEE DASC Timing Working Group (TWG), PAR 1076.4
-- :
-- Purpose : This packages defines standard types, constants, functions
-- : and procedures for use in developing ASIC models.
-- : Specifically a set of logic primitives are defined.
-- :
-- Known Errors :
-- :
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the objects (types, subtypes, constants, functions,
-- : procedures ... etc.) that can be used by a user. The package
-- : body shall be considered the formal definition of the
-- : semantics of this package. Tool developers may choose to
-- : implement the package body in the most efficient manner
-- : available to them.
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Acknowledgments:
-- This code was originally developed under the "VHDL Initiative Toward ASIC
-- Libraries" (VITAL), an industry sponsored initiative. Technical
-- Director: William Billowitch, VHDL Technology Group; U.S. Coordinator:
-- Steve Schultz; Steering Committee Members: Victor Berman, Cadence Design
-- Systems; Oz Levia, Synopsys Inc.; Ray Ryan, Ryan & Ryan; Herman van Beek,
-- Texas Instruments; Victor Martin, Hewlett-Packard Company.
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Modification History :
-- ----------------------------------------------------------------------------
-- Version No:|Auth:| Mod.Date:| Changes Made:
-- v95.0 A | | 06/02/95 | Initial ballot draft 1995
-- ----------------------------------------------------------------------------
-- v95.3 | ddl | 09/24/96 | #236 - VitalTruthTable DataIn should be of
-- | | | of class SIGNAL (PROPOSED)
-- ----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
USE IEEE.VITAL_Timing.ALL;
PACKAGE VITAL_Primitives IS
-- ------------------------------------------------------------------------
-- Type and Subtype Declarations
-- ------------------------------------------------------------------------
-- For Truth and State Tables
SUBTYPE VitalTruthSymbolType IS VitalTableSymbolType RANGE 'X' TO 'Z';
SUBTYPE VitalStateSymbolType IS VitalTableSymbolType RANGE '/' TO 'S';
TYPE VitalTruthTableType IS ARRAY ( NATURAL RANGE <>, NATURAL RANGE <> )
OF VitalTruthSymbolType;
TYPE VitalStateTableType IS ARRAY ( NATURAL RANGE <>, NATURAL RANGE <> )
OF VitalStateSymbolType;
-- ---------------------------------
-- Default values used by primitives
-- ---------------------------------
CONSTANT VitalDefDelay01 : VitalDelayType01; -- Propagation delays
CONSTANT VitalDefDelay01Z : VitalDelayType01Z;
-- ------------------------------------------------------------------------
-- VITAL Primitives
--
-- The primitives packages contains a collections of common gates,
-- including AND, OR, XOR, NAND, NOR, XNOR, BUF, INV, MUX and DECODER
-- functions. In addition, for sequential devices, a STATE TABLE construct
-- is provided. For complex functions a modeler may wish to use either
-- a collection of connected VITAL primitives, or a TRUTH TABLE construct.
--
-- For each primitive a Function and Procedure is provided. The primitive
-- functions are provided to support behavioral modeling styles. The
-- primitive procedures are provided to support structural modeling styles.
--
-- The procedures wait internally for an event on an input signal, compute
-- the new result, perform glitch handling, schedule transaction on the
-- output signals, and wait for future input events. All of the functional
-- (logic) input or output parameters of the primitive procedures are
-- signals. All the other parameters are constants.
--
-- The procedure primitives are parameterized for separate path delays
-- from each input signal. All path delays default to 0 ns.
--
-- The sequential primitive functions compute the defined function and
-- return a value of type std_ulogic or std_logic_vector. All parameters
-- of the primitive functions are constants of mode IN.
--
-- The primitives are based on 1164 operators. The user may also elect to
-- express functions using the 1164 operators as well. These styles are
-- all equally acceptable methods for device modeling.
--
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: N-input logic device function calls:
-- VitalAND VitalOR VitalXOR
-- VitalNAND VitalNOR VitalXNOR
--
-- Description: The function calls return the evaluated logic function
-- corresponding to the function name.
--
-- Arguments:
--
-- IN Type Description
-- Data std_logic_vector The input signals for the n-bit
-- wide logic functions.
-- ResultMap VitalResultMapType The output signal strength
-- result map to modify default
-- result mapping.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic The evaluated logic function of
-- the n-bit wide primitives.
--
-- -------------------------------------------------------------------------
FUNCTION VitalAND (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNAND (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXNOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: N-input logic device concurrent procedure calls.
-- VitalAND VitalOR VitalXOR
-- VitalNAND VitalNOR VitalXNOR
--
-- Description: The procedure calls return the evaluated logic function
-- corresponding to the function name as a parameter to the
-- procedure. Propagation delay form data to q is a
-- a parameter to the procedure. A vector of delay values
-- for inputs to output are provided. It is noted that
-- limitations in SDF make the back annotation of the delay
-- array difficult.
--
-- Arguments:
--
-- IN Type Description
-- Data std_logic_vector The input signals for the n-
-- bit wide logic functions.
-- tpd_data_q VitalDelayArrayType01 The propagation delay from
-- the data inputs to the output
-- q.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic The output signal of the
-- evaluated logic function.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalAND (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNAND (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXNOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
-- -------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: 2,3 and 4 input logic device function calls.
--
-- VitalAND2 VitalOR2 VitalXOR2
-- VitalAND3 VitalOR3 VitalXOR3
-- VitalAND4 VitalOR4 VitalXOR4
--
-- VitalNAND2 VitalNOR2 VitalXNOR2
-- VitalNAND3 VitalNOR3 VitalXNOR3
-- VitalNAND4 VitalNOR4 VitalXNOR4
--
-- Description: The function calls return the evaluated 2, 3 or 4 input
-- logic function corresponding to the function name.
--
-- Arguments:
--
-- IN Type Description
-- a, b, c, d std_ulogic 2 input devices have a and b as
-- inputs. 3 input devices have a, b
-- and c as inputs. 4 input devices
-- have a, b, c and d as inputs.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic The result of the evaluated logic
-- function.
--
-- -------------------------------------------------------------------------
FUNCTION VitalAND2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNAND2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXNOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalAND3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNAND3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXNOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalAND4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNAND4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXNOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: 2, 3 and 4 input logic device concurrent procedure
-- calls.
--
-- VitalAND2 VitalOR2 VitalXOR2
-- VitalAND3 VitalOR3 VitalXOR3
-- VitalAND4 VitalOR4 VitalXOR4
--
-- VitalNAND2 VitalNOR2 VitalXNOR2
-- VitalNAND3 VitalNOR3 VitalXNOR3
-- VitalNAND4 VitalNOR4 VitalXNOR4
--
-- Description: The procedure calls return the evaluated logic function
-- corresponding to the function name as a parameter to the
-- procedure. Propagation delays from a and b to q are
-- a parameter to the procedure. The default propagation
-- delay is 0 ns.
--
-- Arguments:
--
-- IN Type Description
-- a, b, c, d std_ulogic 2 input devices have a and b as
-- inputs. 3 input devices have a, b
-- and c as inputs. 4 input devices
-- have a, b, c and d as inputs.
-- tpd_a_q VitalDelayType01 The propagation delay from the a
-- input to output q for 2, 3 and 4
-- input devices.
-- tpd_b_q VitalDelayType01 The propagation delay from the b
-- input to output q for 2, 3 and 4
-- input devices.
-- tpd_c_q VitalDelayType01 The propagation delay from the c
-- input to output q for 3 and 4 input
-- devices.
-- tpd_d_q VitalDelayType01 The propagation delay from the d
-- input to output q for 4 input
-- devices.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic The output signal of the evaluated
-- logic function.
--
-- Returns
-- none
-- -------------------------------------------------------------------------
PROCEDURE VitalAND2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNAND2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXNOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalAND3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNAND3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXNOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalAND4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNAND4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXNOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: Buffer logic device concurrent procedure calls.
--
-- Description: Four buffer sequential primitive function calls are
-- provided. One is a simple buffer and the others
-- offer high and low enables and the four permits
-- propagation of Z as shown below:
--
-- VitalBUF Standard non-inverting buffer
-- VitalBUFIF0 Non-inverting buffer with Enable low
-- VitalBUFIF1 Non-inverting buffer with Enable high
-- VitalIDENT Pass buffer capable of propagating Z
--
-- Arguments:
--
-- IN Type Description
-- Data std_ulogic Input to the buffers
-- Enable std_ulogic Enable for the enable high and low
-- buffers.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- simple buffer.
-- VitalResultZMapType The output signal strength result map
-- to modify default result mapping
-- which has high impedance capability
-- for the enable high, enable low and
-- identity buffers.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic The output signal of the evaluated
-- buffer function.
--
-- -------------------------------------------------------------------------
FUNCTION VitalBUF (
CONSTANT Data : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalBUFIF0 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
FUNCTION VitalBUFIF1 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
FUNCTION VitalIDENT (
CONSTANT Data : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: Buffer device procedure calls.
--
-- Description: Four buffer concurrent primitive procedure calls are
-- provided. One is a simple buffer and the others
-- offer high and low enables and the fourth permits
-- propagation of Z as shown below:
--
-- VitalBUF Standard non-inverting buffer
-- VitalBUFIF0 Non-inverting buffer with Enable low
-- VitalBUFIF1 Non-inverting buffer with Enable high
-- VitalIDENT Pass buffer capable of propagating Z
--
-- Arguments:
--
-- IN Type Description
-- a std_ulogic Input signal to the buffers
-- Enable std_ulogic Enable signal for the enable high and
-- low buffers.
-- tpd_a_q VitalDelayType01 Propagation delay from input to
-- output for the simple buffer.
-- VitalDelayType01Z Propagation delay from input to
-- to output for the enable high and low
-- and identity buffers.
-- tpd_enable_q VitalDelayType01Z Propagation delay from enable to
-- output for the enable high and low
-- buffers.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- simple buffer.
-- VitalResultZMapType The output signal strength result map
-- to modify default result mapping
-- which has high impedance capability
-- for the enable high, enable low and
-- identity buffers.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic Output of the buffers.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalBUF (
SIGNAL q : OUT std_ulogic;
SIGNAL a : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalBUFIF0 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap);
PROCEDURE VitalBUFIF1 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap);
PROCEDURE VitalIDENT (
SIGNAL q : OUT std_ulogic;
SIGNAL a : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap );
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: VitalINV, VitalINVIF0, VitalINVIF1
--
-- Description: Inverter functions which return the inverted signal
-- value. Inverters with enable low and high are provided
-- which can drive high impedance when inactive.
--
-- Arguments:
--
-- IN Type Description
-- Data std_ulogic Input to the inverter
-- Enable std_ulogic Enable to the enable high and low
-- inverters.
-- ResultMap VitalResultMap The output signal strength result map
-- to modify default result mapping for
-- simple inverter.
-- VitalResultZMapType The output signal strength result map
-- to modify default result mapping
-- which has high impedance capability
-- for the enable high, enable low
-- inverters.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic Output of the inverter
--
-- -------------------------------------------------------------------------
FUNCTION VitalINV (
CONSTANT Data : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalINVIF0 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
FUNCTION VitalINVIF1 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: VitalINV, VitalINVIF0, VitalINVIF1
--
-- Description: The concurrent primitive procedure calls implement a
-- signal inversion function. The output is a parameter to
-- the procedure. The path delay information is passed as
-- a parameter to the call.
--
-- Arguments:
--
-- IN Type Description
-- a std_ulogic Input signal for the simple inverter
-- Data std_ulogic Input signal for the enable high and
-- low inverters.
-- Enable std_ulogic Enable signal for the enable high and
-- low inverters.
-- tpd_a_q VitalDelayType01 Propagation delay from input a to
-- output q for the simple inverter.
-- tpd_data_q VitalDelayType01 Propagation delay from input data to
-- output q for the enable high and low
-- inverters.
-- tpd_enable_q VitalDelayType01Z Propagation delay from input enable
-- to output q for the enable high and
-- low inverters.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- simple inverter.
-- VitalResultZMapType The output signal strength result map
-- to modify default result mapping
-- which has high impedance capability
-- for the enable high, enable low
-- inverters.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic Output signal of the inverter.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalINV (
SIGNAL q : OUT std_ulogic;
SIGNAL a : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalINVIF0 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap);
PROCEDURE VitalINVIF1 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap);
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: VitalMUX, VitalMUX2, VitalMUX4, VitalMUX8
--
-- Description: The VitalMUX functions return the selected data bit
-- based on the value of dSelect. For MUX2, the function
-- returns data0 when dselect is 0 and returns data1 when
-- dselect is 1. When dselect is X, result is X for MUX2
-- when data0 /= data1. X propagation is reduced when the
-- dselect signal is X and both data signals are identical.
-- When this is the case, the result returned is the value
-- of the data signals.
--
-- For the N input device:
--
-- N must equal 2**(bits of dSelect)
--
-- Arguments:
--
-- IN Type Description
-- Data std_logic_vector Input signal for the N-bit, 4-bit and
-- 8-bit mux.
-- Data1,Data0 std_ulogic Input signals for the 2-bit mux.
-- dSelect std_ulogic Select signal for 2-bit mux
-- std_logic_vector2 Select signal for 4-bit mux
-- std_logic_vector3 Select signal for 8-bit mux
-- std_logic_vector Select signal for N-Bit mux
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- all muxes.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic The value of the selected bit is
-- returned.
--
-- -------------------------------------------------------------------------
FUNCTION VitalMUX (
CONSTANT Data : IN std_logic_vector;
CONSTANT dSelect : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalMUX2 (
CONSTANT Data1, Data0 : IN std_ulogic;
CONSTANT dSelect : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalMUX4 (
CONSTANT Data : IN std_logic_vector4;
CONSTANT dSelect : IN std_logic_vector2;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalMUX8 (
CONSTANT Data : IN std_logic_vector8;
CONSTANT dSelect : IN std_logic_vector3;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: VitalMUX, VitalMUX2, VitalMUX4, VitalMUX8
--
-- Description: The VitalMUX concurrent primitive procedures calls
-- return in the output q the value of the selected data
-- bit based on the value of dsel. For the two bit mux,
-- the data returned is either d0 or d1, the data input.
-- For 4, 8 and N-bit functions, data is the input and is
-- of type std_logic_vector. For the 2-bit mux, if d0 or
-- d1 are X, the output is X only when d0 do not equal d1.
-- When d0 and d1 are equal, the return value is this value
-- to reduce X propagation.
--
-- Propagation delay information is passed as a parameter
-- to the procedure call for delays from data to output and
-- select to output. For 2-bit muxes, the propagation
-- delays from data are provided for d0 and d1 to output.
--
--
-- Arguments:
--
-- IN Type Description
-- d1,d0 std_ulogic Input signals for the 2-bit mux.
-- Data std_logic_vector4 Input signals for the 4-bit mux.
-- std_logic_vector8 Input signals for the 8-bit mux.
-- std_logic_vector Input signals for the N-bit mux.
-- dsel std_ulogic Select signal for the 2-bit mux.
-- std_logic_vector2 Select signals for the 4-bit mux.
-- std_logic_vector3 Select signals for the 8-bit mux.
-- std_logic_vector Select signals for the N-bit mux.
-- tpd_d1_q VitalDelayType01 Propagation delay from input d1 to
-- output q for 2-bit mux.
-- tpd_d0_q VitalDelayType01 Propagation delay from input d0 to
-- output q for 2-bit mux.
-- tpd_data_q VitalDelayArrayType01 Propagation delay from input data
-- to output q for 4-bit, 8-bit and
-- N-bit muxes.
-- tpd_dsel_q VitalDelayType01 Propagation delay from input dsel
-- to output q for 2-bit mux.
-- VitalDelayArrayType01 Propagation delay from input dsel
-- to output q for 4-bit, 8-bit and
-- N-bit muxes.
-- ResultMap VitalResultMapType The output signal strength result
-- map to modify default result
-- mapping for all muxes.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic The value of the selected signal.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalMUX (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
SIGNAL dSel : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_dsel_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalMUX2 (
SIGNAL q : OUT std_ulogic;
SIGNAL d1, d0 : IN std_ulogic;
SIGNAL dSel : IN std_ulogic;
CONSTANT tpd_d1_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d0_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_dsel_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalMUX4 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector4;
SIGNAL dSel : IN std_logic_vector2;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_dsel_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalMUX8 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector8;
SIGNAL dSel : IN std_logic_vector3;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_dsel_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: VitalDECODER, VitalDECODER2, VitalDECODER4,
-- VitalDECODER8
--
-- Description: The VitalDECODER functions are the sequential primitive
-- calls for decoder logic. The functions are provided
-- for N, 2, 4 and 8-bit outputs.
--
-- The N-bit decoder is (2**(bits of data)) wide.
--
-- The VitalDECODER returns 0 if enable is 0.
-- The VitalDECODER returns the result bit set to 1 if
-- enable is 1. All other bits of returned result are
-- set to 0.
--
-- The returned array is in descending order:
-- (n-1 downto 0).
--
-- Arguments:
--
-- IN Type Description
-- Data std_ulogic Input signal for 2-bit decoder.
-- std_logic_vector2 Input signals for 4-bit decoder.
-- std_logic_vector3 Input signals for 8-bit decoder.
-- std_logic_vector Input signals for N-bit decoder.
-- Enable std_ulogic Enable input signal. The result is
-- output when enable is high.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- all output signals of the decoders.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_logic_vector2 The output of the 2-bit decoder.
-- std_logic_vector4 The output of the 4-bit decoder.
-- std_logic_vector8 The output of the 8-bit decoder.
-- std_logic_vector The output of the n-bit decoder.
--
-- -------------------------------------------------------------------------
FUNCTION VitalDECODER (
CONSTANT Data : IN std_logic_vector;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector;
FUNCTION VitalDECODER2 (
CONSTANT Data : IN std_ulogic;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector2;
FUNCTION VitalDECODER4 (
CONSTANT Data : IN std_logic_vector2;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector4;
FUNCTION VitalDECODER8 (
CONSTANT Data : IN std_logic_vector3;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector8;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: VitalDECODER, VitalDECODER2, VitalDECODER4,
-- VitalDECODER8
--
-- Description: The VitalDECODER procedures are the concurrent primitive
-- procedure calls for decoder functions. The procedures
-- are provided for N, 2, 4 and 8 outputs.
--
-- The N-bit decoder is (2**(bits of data)) wide.
--
-- The procedural form of the decoder is used for
-- distributed delay modeling. The delay information for
-- each path is passed as an argument to the procedure.
--
-- Result is set to 0 if enable is 0.
-- The result bit represented by data is set to 1 if
-- enable is 1. All other bits of result are set to 0.
--
-- The result array is in descending order: (n-1 downto 0).
--
-- For the N-bit decoder, the delay path is a vector of
-- delays from inputs to outputs.
--
-- Arguments:
--
-- IN Type Description
-- Data std_ulogic Input signal for 2-bit decoder.
-- std_logic_vector2 Input signals for 4-bit decoder.
-- std_logic_vector3 Input signals for 8-bit decoder.
-- std_logic_vector Input signals for N-bit decoder.
-- enable std_ulogic Enable input signal. The result is
-- output when enable is high.
-- tpd_data_q VitalDelayType01 Propagation delay from input data
-- to output q for 2-bit decoder.
-- VitalDelayArrayType01 Propagation delay from input data
-- to output q for 4, 8 and n-bit
-- decoders.
-- tpd_enable_q VitalDelayType01 Propagation delay from input enable
-- to output q for 2, 4, 8 and n-bit
-- decoders.
--
-- INOUT
-- none
--
-- OUT
-- q std_logic_vector2 Output signals for 2-bit decoder.
-- std_logic_vector4 Output signals for 4-bit decoder.
-- std_logic_vector8 Output signals for 8-bit decoder.
-- std_logic_vector Output signals for n-bit decoder.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalDECODER (
SIGNAL q : OUT std_logic_vector;
SIGNAL Data : IN std_logic_vector;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalDECODER2 (
SIGNAL q : OUT std_logic_vector2;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalDECODER4 (
SIGNAL q : OUT std_logic_vector4;
SIGNAL Data : IN std_logic_vector2;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalDECODER8 (
SIGNAL q : OUT std_logic_vector8;
SIGNAL Data : IN std_logic_vector3;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
-- -------------------------------------------------------------------------
-- Function Name: VitalTruthTable
--
-- Description: VitalTruthTable implements a truth table. Given
-- a set of inputs, a sequential search is performed
-- to match the input. If a match is found, the output
-- is set based on the contents of the CONSTANT TruthTable.
-- If there is no match, all X's are returned. There is
-- no limit to the size of the table.
--
-- There is a procedure and function for VitalTruthTable.
-- For each of these, a single value output (std_logic) and
-- a multi-value output (std_logic_vector) are provided.
--
-- The first dimension of the table is for number of
-- entries in the truth table and second dimension is for
-- the number of elements in a row. The number of inputs
-- in the row should be Data'LENGTH plus result'LENGTH.
--
-- Elements is a row will be interpreted as
-- Input(NumInputs - 1),.., Input(0),
-- Result(NumOutputs - 1),.., Result(0)
--
-- All inputs will be mapped to the X01 subtype
--
-- If the value of Result is not in the range 'X' to 'Z'
-- then an error will be reported. Also, the Result is
-- always given either as a 0, 1, X or Z value.
--
-- Arguments:
--
-- IN Type Description
-- TruthTable The input constant which defines the
-- behavior in truth table form.
-- DataIn The inputs to the truth table used to
-- perform input match to select
-- output(s) to value(s) to drive.
--
-- INOUT
-- none
--
-- OUT
-- Result std_logic Concurrent procedure version scalar
-- output.
-- std_logic_vector Concurrent procedure version vector
-- output.
--
-- Returns
-- Result std_logic Function version scalar output.
-- std_logic_vector Function version vector output.
--
-- -------------------------------------------------------------------------
FUNCTION VitalTruthTable (
CONSTANT TruthTable : IN VitalTruthTableType;
CONSTANT DataIn : IN std_logic_vector
) RETURN std_logic_vector;
FUNCTION VitalTruthTable (
CONSTANT TruthTable : IN VitalTruthTableType;
CONSTANT DataIn : IN std_logic_vector
) RETURN std_logic;
PROCEDURE VitalTruthTable (
SIGNAL Result : OUT std_logic_vector;
CONSTANT TruthTable : IN VitalTruthTableType;
SIGNAL DataIn : IN std_logic_vector -- IR#236
);
PROCEDURE VitalTruthTable (
SIGNAL Result : OUT std_logic;
CONSTANT TruthTable : IN VitalTruthTableType;
SIGNAL DataIn : IN std_logic_vector -- IR#236
);
-- -------------------------------------------------------------------------
--
-- Function Name: VitalStateTable
--
-- Description: VitalStateTable is a non-concurrent implementation of a
-- state machine (Moore Machine). It is used to model
-- sequential devices and devices with internal states.
--
-- The procedure takes the value of the state table
-- data set and performs a sequential search of the
-- CONSTANT StateTable until a match is found. Once a
-- match is found, the result of that match is applied
-- to Result. If there is no match, all X's are returned.
-- The resultant output becomes the input for the next
-- state.
--
-- The first dimension of the table is the number of
-- entries in the state table and second dimension is the
-- number of elements in a row of the table. The number of
-- inputs in the row should be DataIn'LENGTH. Result should
-- contain the current state (which will become the next
-- state) as well as the outputs
--
-- Elements is a row of the table will be interpreted as
-- Input(NumInputs-1),.., Input(0), State(NumStates-1),
-- ..., State(0),Output(NumOutputs-1),.., Output(0)
--
-- where State(numStates-1) DOWNTO State(0) represent the
-- present state and Output(NumOutputs - 1) DOWNTO
-- Outputs(NumOutputs - NumStates) represent the new
-- values of the state variables (i.e. the next state).
-- Also, Output(NumOutputs - NumStates - 1)
--
-- This procedure returns the next state and the new
-- outputs when a match is made between the present state
-- and present inputs and the state table. A search is
-- made starting at the top of the state table and
-- terminates with the first match. If no match is found
-- then the next state and new outputs are set to all 'X's.
--
-- (Asynchronous inputs (i.e. resets and clears) must be
-- handled by placing the corresponding entries at the top
-- of the table. )
--
-- All inputs will be mapped to the X01 subtype.
--
-- NOTE: Edge transitions should not be used as values
-- for the state variables in the present state
-- portion of the state table. The only valid
-- values that can be used for the present state
-- portion of the state table are:
-- 'X', '0', '1', 'B', '-'
--
-- Arguments:
--
-- IN Type Description
-- StateTable VitalStateTableType The input constant which defines
-- the behavior in state table form.
-- DataIn std_logic_vector The current state inputs to the
-- state table used to perform input
-- matches and transition
-- calculations.
-- NumStates NATURAL Number of state variables
--
-- INOUT
-- Result std_logic Output signal for scalar version of
-- the concurrent procedure call.
-- std_logic_vector Output signals for vector version
-- of the concurrent procedure call.
-- PreviousDataIn std_logic_vector The previous inputs and states used
-- in transition calculations and to
-- set outputs for steady state cases.
--
-- OUT
-- none
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalStateTable (
VARIABLE Result : INOUT std_logic_vector;
VARIABLE PreviousDataIn : INOUT std_logic_vector;
CONSTANT StateTable : IN VitalStateTableType;
CONSTANT DataIn : IN std_logic_vector;
CONSTANT NumStates : IN NATURAL
);
PROCEDURE VitalStateTable (
VARIABLE Result : INOUT std_logic;
VARIABLE PreviousDataIn : INOUT std_logic_vector;
CONSTANT StateTable : IN VitalStateTableType;
CONSTANT DataIn : IN std_logic_vector
);
PROCEDURE VitalStateTable (
SIGNAL Result : INOUT std_logic_vector;
CONSTANT StateTable : IN VitalStateTableType;
SIGNAL DataIn : IN std_logic_vector;
CONSTANT NumStates : IN NATURAL
);
PROCEDURE VitalStateTable (
SIGNAL Result : INOUT std_logic;
CONSTANT StateTable : IN VitalStateTableType;
SIGNAL DataIn : IN std_logic_vector
);
-- -------------------------------------------------------------------------
--
-- Function Name: VitalResolve
--
-- Description: VitalResolve takes a vector of signals and resolves
-- them to a std_ulogic value. This procedure can be used
-- to resolve multiple drivers in a single model.
--
-- Arguments:
--
-- IN Type Description
-- Data std_logic_vector Set of input signals which drive a
-- common signal.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic Output signal which is the resolved
-- value being driven by the collection of
-- input signals.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalResolve (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector); --IR236 4/2/98
END VITAL_Primitives;
|
-- -----------------------------------------------------------------------------
-- Title : Standard VITAL_Primitives Package
-- : $Revision$
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers : IEEE DASC Timing Working Group (TWG), PAR 1076.4
-- :
-- Purpose : This packages defines standard types, constants, functions
-- : and procedures for use in developing ASIC models.
-- : Specifically a set of logic primitives are defined.
-- :
-- Known Errors :
-- :
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the objects (types, subtypes, constants, functions,
-- : procedures ... etc.) that can be used by a user. The package
-- : body shall be considered the formal definition of the
-- : semantics of this package. Tool developers may choose to
-- : implement the package body in the most efficient manner
-- : available to them.
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Acknowledgments:
-- This code was originally developed under the "VHDL Initiative Toward ASIC
-- Libraries" (VITAL), an industry sponsored initiative. Technical
-- Director: William Billowitch, VHDL Technology Group; U.S. Coordinator:
-- Steve Schultz; Steering Committee Members: Victor Berman, Cadence Design
-- Systems; Oz Levia, Synopsys Inc.; Ray Ryan, Ryan & Ryan; Herman van Beek,
-- Texas Instruments; Victor Martin, Hewlett-Packard Company.
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Modification History :
-- ----------------------------------------------------------------------------
-- Version No:|Auth:| Mod.Date:| Changes Made:
-- v95.0 A | | 06/02/95 | Initial ballot draft 1995
-- ----------------------------------------------------------------------------
-- v95.3 | ddl | 09/24/96 | #236 - VitalTruthTable DataIn should be of
-- | | | of class SIGNAL (PROPOSED)
-- ----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
USE IEEE.VITAL_Timing.ALL;
PACKAGE VITAL_Primitives IS
-- ------------------------------------------------------------------------
-- Type and Subtype Declarations
-- ------------------------------------------------------------------------
-- For Truth and State Tables
SUBTYPE VitalTruthSymbolType IS VitalTableSymbolType RANGE 'X' TO 'Z';
SUBTYPE VitalStateSymbolType IS VitalTableSymbolType RANGE '/' TO 'S';
TYPE VitalTruthTableType IS ARRAY ( NATURAL RANGE <>, NATURAL RANGE <> )
OF VitalTruthSymbolType;
TYPE VitalStateTableType IS ARRAY ( NATURAL RANGE <>, NATURAL RANGE <> )
OF VitalStateSymbolType;
-- ---------------------------------
-- Default values used by primitives
-- ---------------------------------
CONSTANT VitalDefDelay01 : VitalDelayType01; -- Propagation delays
CONSTANT VitalDefDelay01Z : VitalDelayType01Z;
-- ------------------------------------------------------------------------
-- VITAL Primitives
--
-- The primitives packages contains a collections of common gates,
-- including AND, OR, XOR, NAND, NOR, XNOR, BUF, INV, MUX and DECODER
-- functions. In addition, for sequential devices, a STATE TABLE construct
-- is provided. For complex functions a modeler may wish to use either
-- a collection of connected VITAL primitives, or a TRUTH TABLE construct.
--
-- For each primitive a Function and Procedure is provided. The primitive
-- functions are provided to support behavioral modeling styles. The
-- primitive procedures are provided to support structural modeling styles.
--
-- The procedures wait internally for an event on an input signal, compute
-- the new result, perform glitch handling, schedule transaction on the
-- output signals, and wait for future input events. All of the functional
-- (logic) input or output parameters of the primitive procedures are
-- signals. All the other parameters are constants.
--
-- The procedure primitives are parameterized for separate path delays
-- from each input signal. All path delays default to 0 ns.
--
-- The sequential primitive functions compute the defined function and
-- return a value of type std_ulogic or std_logic_vector. All parameters
-- of the primitive functions are constants of mode IN.
--
-- The primitives are based on 1164 operators. The user may also elect to
-- express functions using the 1164 operators as well. These styles are
-- all equally acceptable methods for device modeling.
--
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: N-input logic device function calls:
-- VitalAND VitalOR VitalXOR
-- VitalNAND VitalNOR VitalXNOR
--
-- Description: The function calls return the evaluated logic function
-- corresponding to the function name.
--
-- Arguments:
--
-- IN Type Description
-- Data std_logic_vector The input signals for the n-bit
-- wide logic functions.
-- ResultMap VitalResultMapType The output signal strength
-- result map to modify default
-- result mapping.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic The evaluated logic function of
-- the n-bit wide primitives.
--
-- -------------------------------------------------------------------------
FUNCTION VitalAND (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNAND (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXNOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: N-input logic device concurrent procedure calls.
-- VitalAND VitalOR VitalXOR
-- VitalNAND VitalNOR VitalXNOR
--
-- Description: The procedure calls return the evaluated logic function
-- corresponding to the function name as a parameter to the
-- procedure. Propagation delay form data to q is a
-- a parameter to the procedure. A vector of delay values
-- for inputs to output are provided. It is noted that
-- limitations in SDF make the back annotation of the delay
-- array difficult.
--
-- Arguments:
--
-- IN Type Description
-- Data std_logic_vector The input signals for the n-
-- bit wide logic functions.
-- tpd_data_q VitalDelayArrayType01 The propagation delay from
-- the data inputs to the output
-- q.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic The output signal of the
-- evaluated logic function.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalAND (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNAND (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXNOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
-- -------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: 2,3 and 4 input logic device function calls.
--
-- VitalAND2 VitalOR2 VitalXOR2
-- VitalAND3 VitalOR3 VitalXOR3
-- VitalAND4 VitalOR4 VitalXOR4
--
-- VitalNAND2 VitalNOR2 VitalXNOR2
-- VitalNAND3 VitalNOR3 VitalXNOR3
-- VitalNAND4 VitalNOR4 VitalXNOR4
--
-- Description: The function calls return the evaluated 2, 3 or 4 input
-- logic function corresponding to the function name.
--
-- Arguments:
--
-- IN Type Description
-- a, b, c, d std_ulogic 2 input devices have a and b as
-- inputs. 3 input devices have a, b
-- and c as inputs. 4 input devices
-- have a, b, c and d as inputs.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic The result of the evaluated logic
-- function.
--
-- -------------------------------------------------------------------------
FUNCTION VitalAND2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNAND2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXNOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalAND3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNAND3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXNOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalAND4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNAND4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXNOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: 2, 3 and 4 input logic device concurrent procedure
-- calls.
--
-- VitalAND2 VitalOR2 VitalXOR2
-- VitalAND3 VitalOR3 VitalXOR3
-- VitalAND4 VitalOR4 VitalXOR4
--
-- VitalNAND2 VitalNOR2 VitalXNOR2
-- VitalNAND3 VitalNOR3 VitalXNOR3
-- VitalNAND4 VitalNOR4 VitalXNOR4
--
-- Description: The procedure calls return the evaluated logic function
-- corresponding to the function name as a parameter to the
-- procedure. Propagation delays from a and b to q are
-- a parameter to the procedure. The default propagation
-- delay is 0 ns.
--
-- Arguments:
--
-- IN Type Description
-- a, b, c, d std_ulogic 2 input devices have a and b as
-- inputs. 3 input devices have a, b
-- and c as inputs. 4 input devices
-- have a, b, c and d as inputs.
-- tpd_a_q VitalDelayType01 The propagation delay from the a
-- input to output q for 2, 3 and 4
-- input devices.
-- tpd_b_q VitalDelayType01 The propagation delay from the b
-- input to output q for 2, 3 and 4
-- input devices.
-- tpd_c_q VitalDelayType01 The propagation delay from the c
-- input to output q for 3 and 4 input
-- devices.
-- tpd_d_q VitalDelayType01 The propagation delay from the d
-- input to output q for 4 input
-- devices.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic The output signal of the evaluated
-- logic function.
--
-- Returns
-- none
-- -------------------------------------------------------------------------
PROCEDURE VitalAND2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNAND2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXNOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalAND3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNAND3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXNOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalAND4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNAND4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXNOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: Buffer logic device concurrent procedure calls.
--
-- Description: Four buffer sequential primitive function calls are
-- provided. One is a simple buffer and the others
-- offer high and low enables and the four permits
-- propagation of Z as shown below:
--
-- VitalBUF Standard non-inverting buffer
-- VitalBUFIF0 Non-inverting buffer with Enable low
-- VitalBUFIF1 Non-inverting buffer with Enable high
-- VitalIDENT Pass buffer capable of propagating Z
--
-- Arguments:
--
-- IN Type Description
-- Data std_ulogic Input to the buffers
-- Enable std_ulogic Enable for the enable high and low
-- buffers.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- simple buffer.
-- VitalResultZMapType The output signal strength result map
-- to modify default result mapping
-- which has high impedance capability
-- for the enable high, enable low and
-- identity buffers.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic The output signal of the evaluated
-- buffer function.
--
-- -------------------------------------------------------------------------
FUNCTION VitalBUF (
CONSTANT Data : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalBUFIF0 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
FUNCTION VitalBUFIF1 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
FUNCTION VitalIDENT (
CONSTANT Data : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: Buffer device procedure calls.
--
-- Description: Four buffer concurrent primitive procedure calls are
-- provided. One is a simple buffer and the others
-- offer high and low enables and the fourth permits
-- propagation of Z as shown below:
--
-- VitalBUF Standard non-inverting buffer
-- VitalBUFIF0 Non-inverting buffer with Enable low
-- VitalBUFIF1 Non-inverting buffer with Enable high
-- VitalIDENT Pass buffer capable of propagating Z
--
-- Arguments:
--
-- IN Type Description
-- a std_ulogic Input signal to the buffers
-- Enable std_ulogic Enable signal for the enable high and
-- low buffers.
-- tpd_a_q VitalDelayType01 Propagation delay from input to
-- output for the simple buffer.
-- VitalDelayType01Z Propagation delay from input to
-- to output for the enable high and low
-- and identity buffers.
-- tpd_enable_q VitalDelayType01Z Propagation delay from enable to
-- output for the enable high and low
-- buffers.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- simple buffer.
-- VitalResultZMapType The output signal strength result map
-- to modify default result mapping
-- which has high impedance capability
-- for the enable high, enable low and
-- identity buffers.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic Output of the buffers.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalBUF (
SIGNAL q : OUT std_ulogic;
SIGNAL a : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalBUFIF0 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap);
PROCEDURE VitalBUFIF1 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap);
PROCEDURE VitalIDENT (
SIGNAL q : OUT std_ulogic;
SIGNAL a : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap );
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: VitalINV, VitalINVIF0, VitalINVIF1
--
-- Description: Inverter functions which return the inverted signal
-- value. Inverters with enable low and high are provided
-- which can drive high impedance when inactive.
--
-- Arguments:
--
-- IN Type Description
-- Data std_ulogic Input to the inverter
-- Enable std_ulogic Enable to the enable high and low
-- inverters.
-- ResultMap VitalResultMap The output signal strength result map
-- to modify default result mapping for
-- simple inverter.
-- VitalResultZMapType The output signal strength result map
-- to modify default result mapping
-- which has high impedance capability
-- for the enable high, enable low
-- inverters.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic Output of the inverter
--
-- -------------------------------------------------------------------------
FUNCTION VitalINV (
CONSTANT Data : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalINVIF0 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
FUNCTION VitalINVIF1 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: VitalINV, VitalINVIF0, VitalINVIF1
--
-- Description: The concurrent primitive procedure calls implement a
-- signal inversion function. The output is a parameter to
-- the procedure. The path delay information is passed as
-- a parameter to the call.
--
-- Arguments:
--
-- IN Type Description
-- a std_ulogic Input signal for the simple inverter
-- Data std_ulogic Input signal for the enable high and
-- low inverters.
-- Enable std_ulogic Enable signal for the enable high and
-- low inverters.
-- tpd_a_q VitalDelayType01 Propagation delay from input a to
-- output q for the simple inverter.
-- tpd_data_q VitalDelayType01 Propagation delay from input data to
-- output q for the enable high and low
-- inverters.
-- tpd_enable_q VitalDelayType01Z Propagation delay from input enable
-- to output q for the enable high and
-- low inverters.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- simple inverter.
-- VitalResultZMapType The output signal strength result map
-- to modify default result mapping
-- which has high impedance capability
-- for the enable high, enable low
-- inverters.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic Output signal of the inverter.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalINV (
SIGNAL q : OUT std_ulogic;
SIGNAL a : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalINVIF0 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap);
PROCEDURE VitalINVIF1 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap);
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: VitalMUX, VitalMUX2, VitalMUX4, VitalMUX8
--
-- Description: The VitalMUX functions return the selected data bit
-- based on the value of dSelect. For MUX2, the function
-- returns data0 when dselect is 0 and returns data1 when
-- dselect is 1. When dselect is X, result is X for MUX2
-- when data0 /= data1. X propagation is reduced when the
-- dselect signal is X and both data signals are identical.
-- When this is the case, the result returned is the value
-- of the data signals.
--
-- For the N input device:
--
-- N must equal 2**(bits of dSelect)
--
-- Arguments:
--
-- IN Type Description
-- Data std_logic_vector Input signal for the N-bit, 4-bit and
-- 8-bit mux.
-- Data1,Data0 std_ulogic Input signals for the 2-bit mux.
-- dSelect std_ulogic Select signal for 2-bit mux
-- std_logic_vector2 Select signal for 4-bit mux
-- std_logic_vector3 Select signal for 8-bit mux
-- std_logic_vector Select signal for N-Bit mux
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- all muxes.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic The value of the selected bit is
-- returned.
--
-- -------------------------------------------------------------------------
FUNCTION VitalMUX (
CONSTANT Data : IN std_logic_vector;
CONSTANT dSelect : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalMUX2 (
CONSTANT Data1, Data0 : IN std_ulogic;
CONSTANT dSelect : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalMUX4 (
CONSTANT Data : IN std_logic_vector4;
CONSTANT dSelect : IN std_logic_vector2;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalMUX8 (
CONSTANT Data : IN std_logic_vector8;
CONSTANT dSelect : IN std_logic_vector3;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: VitalMUX, VitalMUX2, VitalMUX4, VitalMUX8
--
-- Description: The VitalMUX concurrent primitive procedures calls
-- return in the output q the value of the selected data
-- bit based on the value of dsel. For the two bit mux,
-- the data returned is either d0 or d1, the data input.
-- For 4, 8 and N-bit functions, data is the input and is
-- of type std_logic_vector. For the 2-bit mux, if d0 or
-- d1 are X, the output is X only when d0 do not equal d1.
-- When d0 and d1 are equal, the return value is this value
-- to reduce X propagation.
--
-- Propagation delay information is passed as a parameter
-- to the procedure call for delays from data to output and
-- select to output. For 2-bit muxes, the propagation
-- delays from data are provided for d0 and d1 to output.
--
--
-- Arguments:
--
-- IN Type Description
-- d1,d0 std_ulogic Input signals for the 2-bit mux.
-- Data std_logic_vector4 Input signals for the 4-bit mux.
-- std_logic_vector8 Input signals for the 8-bit mux.
-- std_logic_vector Input signals for the N-bit mux.
-- dsel std_ulogic Select signal for the 2-bit mux.
-- std_logic_vector2 Select signals for the 4-bit mux.
-- std_logic_vector3 Select signals for the 8-bit mux.
-- std_logic_vector Select signals for the N-bit mux.
-- tpd_d1_q VitalDelayType01 Propagation delay from input d1 to
-- output q for 2-bit mux.
-- tpd_d0_q VitalDelayType01 Propagation delay from input d0 to
-- output q for 2-bit mux.
-- tpd_data_q VitalDelayArrayType01 Propagation delay from input data
-- to output q for 4-bit, 8-bit and
-- N-bit muxes.
-- tpd_dsel_q VitalDelayType01 Propagation delay from input dsel
-- to output q for 2-bit mux.
-- VitalDelayArrayType01 Propagation delay from input dsel
-- to output q for 4-bit, 8-bit and
-- N-bit muxes.
-- ResultMap VitalResultMapType The output signal strength result
-- map to modify default result
-- mapping for all muxes.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic The value of the selected signal.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalMUX (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
SIGNAL dSel : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_dsel_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalMUX2 (
SIGNAL q : OUT std_ulogic;
SIGNAL d1, d0 : IN std_ulogic;
SIGNAL dSel : IN std_ulogic;
CONSTANT tpd_d1_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d0_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_dsel_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalMUX4 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector4;
SIGNAL dSel : IN std_logic_vector2;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_dsel_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalMUX8 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector8;
SIGNAL dSel : IN std_logic_vector3;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_dsel_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: VitalDECODER, VitalDECODER2, VitalDECODER4,
-- VitalDECODER8
--
-- Description: The VitalDECODER functions are the sequential primitive
-- calls for decoder logic. The functions are provided
-- for N, 2, 4 and 8-bit outputs.
--
-- The N-bit decoder is (2**(bits of data)) wide.
--
-- The VitalDECODER returns 0 if enable is 0.
-- The VitalDECODER returns the result bit set to 1 if
-- enable is 1. All other bits of returned result are
-- set to 0.
--
-- The returned array is in descending order:
-- (n-1 downto 0).
--
-- Arguments:
--
-- IN Type Description
-- Data std_ulogic Input signal for 2-bit decoder.
-- std_logic_vector2 Input signals for 4-bit decoder.
-- std_logic_vector3 Input signals for 8-bit decoder.
-- std_logic_vector Input signals for N-bit decoder.
-- Enable std_ulogic Enable input signal. The result is
-- output when enable is high.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- all output signals of the decoders.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_logic_vector2 The output of the 2-bit decoder.
-- std_logic_vector4 The output of the 4-bit decoder.
-- std_logic_vector8 The output of the 8-bit decoder.
-- std_logic_vector The output of the n-bit decoder.
--
-- -------------------------------------------------------------------------
FUNCTION VitalDECODER (
CONSTANT Data : IN std_logic_vector;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector;
FUNCTION VitalDECODER2 (
CONSTANT Data : IN std_ulogic;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector2;
FUNCTION VitalDECODER4 (
CONSTANT Data : IN std_logic_vector2;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector4;
FUNCTION VitalDECODER8 (
CONSTANT Data : IN std_logic_vector3;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector8;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: VitalDECODER, VitalDECODER2, VitalDECODER4,
-- VitalDECODER8
--
-- Description: The VitalDECODER procedures are the concurrent primitive
-- procedure calls for decoder functions. The procedures
-- are provided for N, 2, 4 and 8 outputs.
--
-- The N-bit decoder is (2**(bits of data)) wide.
--
-- The procedural form of the decoder is used for
-- distributed delay modeling. The delay information for
-- each path is passed as an argument to the procedure.
--
-- Result is set to 0 if enable is 0.
-- The result bit represented by data is set to 1 if
-- enable is 1. All other bits of result are set to 0.
--
-- The result array is in descending order: (n-1 downto 0).
--
-- For the N-bit decoder, the delay path is a vector of
-- delays from inputs to outputs.
--
-- Arguments:
--
-- IN Type Description
-- Data std_ulogic Input signal for 2-bit decoder.
-- std_logic_vector2 Input signals for 4-bit decoder.
-- std_logic_vector3 Input signals for 8-bit decoder.
-- std_logic_vector Input signals for N-bit decoder.
-- enable std_ulogic Enable input signal. The result is
-- output when enable is high.
-- tpd_data_q VitalDelayType01 Propagation delay from input data
-- to output q for 2-bit decoder.
-- VitalDelayArrayType01 Propagation delay from input data
-- to output q for 4, 8 and n-bit
-- decoders.
-- tpd_enable_q VitalDelayType01 Propagation delay from input enable
-- to output q for 2, 4, 8 and n-bit
-- decoders.
--
-- INOUT
-- none
--
-- OUT
-- q std_logic_vector2 Output signals for 2-bit decoder.
-- std_logic_vector4 Output signals for 4-bit decoder.
-- std_logic_vector8 Output signals for 8-bit decoder.
-- std_logic_vector Output signals for n-bit decoder.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalDECODER (
SIGNAL q : OUT std_logic_vector;
SIGNAL Data : IN std_logic_vector;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalDECODER2 (
SIGNAL q : OUT std_logic_vector2;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalDECODER4 (
SIGNAL q : OUT std_logic_vector4;
SIGNAL Data : IN std_logic_vector2;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalDECODER8 (
SIGNAL q : OUT std_logic_vector8;
SIGNAL Data : IN std_logic_vector3;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
-- -------------------------------------------------------------------------
-- Function Name: VitalTruthTable
--
-- Description: VitalTruthTable implements a truth table. Given
-- a set of inputs, a sequential search is performed
-- to match the input. If a match is found, the output
-- is set based on the contents of the CONSTANT TruthTable.
-- If there is no match, all X's are returned. There is
-- no limit to the size of the table.
--
-- There is a procedure and function for VitalTruthTable.
-- For each of these, a single value output (std_logic) and
-- a multi-value output (std_logic_vector) are provided.
--
-- The first dimension of the table is for number of
-- entries in the truth table and second dimension is for
-- the number of elements in a row. The number of inputs
-- in the row should be Data'LENGTH plus result'LENGTH.
--
-- Elements is a row will be interpreted as
-- Input(NumInputs - 1),.., Input(0),
-- Result(NumOutputs - 1),.., Result(0)
--
-- All inputs will be mapped to the X01 subtype
--
-- If the value of Result is not in the range 'X' to 'Z'
-- then an error will be reported. Also, the Result is
-- always given either as a 0, 1, X or Z value.
--
-- Arguments:
--
-- IN Type Description
-- TruthTable The input constant which defines the
-- behavior in truth table form.
-- DataIn The inputs to the truth table used to
-- perform input match to select
-- output(s) to value(s) to drive.
--
-- INOUT
-- none
--
-- OUT
-- Result std_logic Concurrent procedure version scalar
-- output.
-- std_logic_vector Concurrent procedure version vector
-- output.
--
-- Returns
-- Result std_logic Function version scalar output.
-- std_logic_vector Function version vector output.
--
-- -------------------------------------------------------------------------
FUNCTION VitalTruthTable (
CONSTANT TruthTable : IN VitalTruthTableType;
CONSTANT DataIn : IN std_logic_vector
) RETURN std_logic_vector;
FUNCTION VitalTruthTable (
CONSTANT TruthTable : IN VitalTruthTableType;
CONSTANT DataIn : IN std_logic_vector
) RETURN std_logic;
PROCEDURE VitalTruthTable (
SIGNAL Result : OUT std_logic_vector;
CONSTANT TruthTable : IN VitalTruthTableType;
SIGNAL DataIn : IN std_logic_vector -- IR#236
);
PROCEDURE VitalTruthTable (
SIGNAL Result : OUT std_logic;
CONSTANT TruthTable : IN VitalTruthTableType;
SIGNAL DataIn : IN std_logic_vector -- IR#236
);
-- -------------------------------------------------------------------------
--
-- Function Name: VitalStateTable
--
-- Description: VitalStateTable is a non-concurrent implementation of a
-- state machine (Moore Machine). It is used to model
-- sequential devices and devices with internal states.
--
-- The procedure takes the value of the state table
-- data set and performs a sequential search of the
-- CONSTANT StateTable until a match is found. Once a
-- match is found, the result of that match is applied
-- to Result. If there is no match, all X's are returned.
-- The resultant output becomes the input for the next
-- state.
--
-- The first dimension of the table is the number of
-- entries in the state table and second dimension is the
-- number of elements in a row of the table. The number of
-- inputs in the row should be DataIn'LENGTH. Result should
-- contain the current state (which will become the next
-- state) as well as the outputs
--
-- Elements is a row of the table will be interpreted as
-- Input(NumInputs-1),.., Input(0), State(NumStates-1),
-- ..., State(0),Output(NumOutputs-1),.., Output(0)
--
-- where State(numStates-1) DOWNTO State(0) represent the
-- present state and Output(NumOutputs - 1) DOWNTO
-- Outputs(NumOutputs - NumStates) represent the new
-- values of the state variables (i.e. the next state).
-- Also, Output(NumOutputs - NumStates - 1)
--
-- This procedure returns the next state and the new
-- outputs when a match is made between the present state
-- and present inputs and the state table. A search is
-- made starting at the top of the state table and
-- terminates with the first match. If no match is found
-- then the next state and new outputs are set to all 'X's.
--
-- (Asynchronous inputs (i.e. resets and clears) must be
-- handled by placing the corresponding entries at the top
-- of the table. )
--
-- All inputs will be mapped to the X01 subtype.
--
-- NOTE: Edge transitions should not be used as values
-- for the state variables in the present state
-- portion of the state table. The only valid
-- values that can be used for the present state
-- portion of the state table are:
-- 'X', '0', '1', 'B', '-'
--
-- Arguments:
--
-- IN Type Description
-- StateTable VitalStateTableType The input constant which defines
-- the behavior in state table form.
-- DataIn std_logic_vector The current state inputs to the
-- state table used to perform input
-- matches and transition
-- calculations.
-- NumStates NATURAL Number of state variables
--
-- INOUT
-- Result std_logic Output signal for scalar version of
-- the concurrent procedure call.
-- std_logic_vector Output signals for vector version
-- of the concurrent procedure call.
-- PreviousDataIn std_logic_vector The previous inputs and states used
-- in transition calculations and to
-- set outputs for steady state cases.
--
-- OUT
-- none
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalStateTable (
VARIABLE Result : INOUT std_logic_vector;
VARIABLE PreviousDataIn : INOUT std_logic_vector;
CONSTANT StateTable : IN VitalStateTableType;
CONSTANT DataIn : IN std_logic_vector;
CONSTANT NumStates : IN NATURAL
);
PROCEDURE VitalStateTable (
VARIABLE Result : INOUT std_logic;
VARIABLE PreviousDataIn : INOUT std_logic_vector;
CONSTANT StateTable : IN VitalStateTableType;
CONSTANT DataIn : IN std_logic_vector
);
PROCEDURE VitalStateTable (
SIGNAL Result : INOUT std_logic_vector;
CONSTANT StateTable : IN VitalStateTableType;
SIGNAL DataIn : IN std_logic_vector;
CONSTANT NumStates : IN NATURAL
);
PROCEDURE VitalStateTable (
SIGNAL Result : INOUT std_logic;
CONSTANT StateTable : IN VitalStateTableType;
SIGNAL DataIn : IN std_logic_vector
);
-- -------------------------------------------------------------------------
--
-- Function Name: VitalResolve
--
-- Description: VitalResolve takes a vector of signals and resolves
-- them to a std_ulogic value. This procedure can be used
-- to resolve multiple drivers in a single model.
--
-- Arguments:
--
-- IN Type Description
-- Data std_logic_vector Set of input signals which drive a
-- common signal.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic Output signal which is the resolved
-- value being driven by the collection of
-- input signals.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalResolve (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector); --IR236 4/2/98
END VITAL_Primitives;
|
-- -----------------------------------------------------------------------------
-- Title : Standard VITAL_Primitives Package
-- : $Revision$
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers : IEEE DASC Timing Working Group (TWG), PAR 1076.4
-- :
-- Purpose : This packages defines standard types, constants, functions
-- : and procedures for use in developing ASIC models.
-- : Specifically a set of logic primitives are defined.
-- :
-- Known Errors :
-- :
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the objects (types, subtypes, constants, functions,
-- : procedures ... etc.) that can be used by a user. The package
-- : body shall be considered the formal definition of the
-- : semantics of this package. Tool developers may choose to
-- : implement the package body in the most efficient manner
-- : available to them.
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Acknowledgments:
-- This code was originally developed under the "VHDL Initiative Toward ASIC
-- Libraries" (VITAL), an industry sponsored initiative. Technical
-- Director: William Billowitch, VHDL Technology Group; U.S. Coordinator:
-- Steve Schultz; Steering Committee Members: Victor Berman, Cadence Design
-- Systems; Oz Levia, Synopsys Inc.; Ray Ryan, Ryan & Ryan; Herman van Beek,
-- Texas Instruments; Victor Martin, Hewlett-Packard Company.
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Modification History :
-- ----------------------------------------------------------------------------
-- Version No:|Auth:| Mod.Date:| Changes Made:
-- v95.0 A | | 06/02/95 | Initial ballot draft 1995
-- ----------------------------------------------------------------------------
-- v95.3 | ddl | 09/24/96 | #236 - VitalTruthTable DataIn should be of
-- | | | of class SIGNAL (PROPOSED)
-- ----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
USE IEEE.VITAL_Timing.ALL;
PACKAGE VITAL_Primitives IS
-- ------------------------------------------------------------------------
-- Type and Subtype Declarations
-- ------------------------------------------------------------------------
-- For Truth and State Tables
SUBTYPE VitalTruthSymbolType IS VitalTableSymbolType RANGE 'X' TO 'Z';
SUBTYPE VitalStateSymbolType IS VitalTableSymbolType RANGE '/' TO 'S';
TYPE VitalTruthTableType IS ARRAY ( NATURAL RANGE <>, NATURAL RANGE <> )
OF VitalTruthSymbolType;
TYPE VitalStateTableType IS ARRAY ( NATURAL RANGE <>, NATURAL RANGE <> )
OF VitalStateSymbolType;
-- ---------------------------------
-- Default values used by primitives
-- ---------------------------------
CONSTANT VitalDefDelay01 : VitalDelayType01; -- Propagation delays
CONSTANT VitalDefDelay01Z : VitalDelayType01Z;
-- ------------------------------------------------------------------------
-- VITAL Primitives
--
-- The primitives packages contains a collections of common gates,
-- including AND, OR, XOR, NAND, NOR, XNOR, BUF, INV, MUX and DECODER
-- functions. In addition, for sequential devices, a STATE TABLE construct
-- is provided. For complex functions a modeler may wish to use either
-- a collection of connected VITAL primitives, or a TRUTH TABLE construct.
--
-- For each primitive a Function and Procedure is provided. The primitive
-- functions are provided to support behavioral modeling styles. The
-- primitive procedures are provided to support structural modeling styles.
--
-- The procedures wait internally for an event on an input signal, compute
-- the new result, perform glitch handling, schedule transaction on the
-- output signals, and wait for future input events. All of the functional
-- (logic) input or output parameters of the primitive procedures are
-- signals. All the other parameters are constants.
--
-- The procedure primitives are parameterized for separate path delays
-- from each input signal. All path delays default to 0 ns.
--
-- The sequential primitive functions compute the defined function and
-- return a value of type std_ulogic or std_logic_vector. All parameters
-- of the primitive functions are constants of mode IN.
--
-- The primitives are based on 1164 operators. The user may also elect to
-- express functions using the 1164 operators as well. These styles are
-- all equally acceptable methods for device modeling.
--
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: N-input logic device function calls:
-- VitalAND VitalOR VitalXOR
-- VitalNAND VitalNOR VitalXNOR
--
-- Description: The function calls return the evaluated logic function
-- corresponding to the function name.
--
-- Arguments:
--
-- IN Type Description
-- Data std_logic_vector The input signals for the n-bit
-- wide logic functions.
-- ResultMap VitalResultMapType The output signal strength
-- result map to modify default
-- result mapping.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic The evaluated logic function of
-- the n-bit wide primitives.
--
-- -------------------------------------------------------------------------
FUNCTION VitalAND (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNAND (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXNOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: N-input logic device concurrent procedure calls.
-- VitalAND VitalOR VitalXOR
-- VitalNAND VitalNOR VitalXNOR
--
-- Description: The procedure calls return the evaluated logic function
-- corresponding to the function name as a parameter to the
-- procedure. Propagation delay form data to q is a
-- a parameter to the procedure. A vector of delay values
-- for inputs to output are provided. It is noted that
-- limitations in SDF make the back annotation of the delay
-- array difficult.
--
-- Arguments:
--
-- IN Type Description
-- Data std_logic_vector The input signals for the n-
-- bit wide logic functions.
-- tpd_data_q VitalDelayArrayType01 The propagation delay from
-- the data inputs to the output
-- q.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic The output signal of the
-- evaluated logic function.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalAND (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNAND (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXNOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
-- -------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: 2,3 and 4 input logic device function calls.
--
-- VitalAND2 VitalOR2 VitalXOR2
-- VitalAND3 VitalOR3 VitalXOR3
-- VitalAND4 VitalOR4 VitalXOR4
--
-- VitalNAND2 VitalNOR2 VitalXNOR2
-- VitalNAND3 VitalNOR3 VitalXNOR3
-- VitalNAND4 VitalNOR4 VitalXNOR4
--
-- Description: The function calls return the evaluated 2, 3 or 4 input
-- logic function corresponding to the function name.
--
-- Arguments:
--
-- IN Type Description
-- a, b, c, d std_ulogic 2 input devices have a and b as
-- inputs. 3 input devices have a, b
-- and c as inputs. 4 input devices
-- have a, b, c and d as inputs.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic The result of the evaluated logic
-- function.
--
-- -------------------------------------------------------------------------
FUNCTION VitalAND2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNAND2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXNOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalAND3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNAND3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXNOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalAND4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNAND4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXNOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: 2, 3 and 4 input logic device concurrent procedure
-- calls.
--
-- VitalAND2 VitalOR2 VitalXOR2
-- VitalAND3 VitalOR3 VitalXOR3
-- VitalAND4 VitalOR4 VitalXOR4
--
-- VitalNAND2 VitalNOR2 VitalXNOR2
-- VitalNAND3 VitalNOR3 VitalXNOR3
-- VitalNAND4 VitalNOR4 VitalXNOR4
--
-- Description: The procedure calls return the evaluated logic function
-- corresponding to the function name as a parameter to the
-- procedure. Propagation delays from a and b to q are
-- a parameter to the procedure. The default propagation
-- delay is 0 ns.
--
-- Arguments:
--
-- IN Type Description
-- a, b, c, d std_ulogic 2 input devices have a and b as
-- inputs. 3 input devices have a, b
-- and c as inputs. 4 input devices
-- have a, b, c and d as inputs.
-- tpd_a_q VitalDelayType01 The propagation delay from the a
-- input to output q for 2, 3 and 4
-- input devices.
-- tpd_b_q VitalDelayType01 The propagation delay from the b
-- input to output q for 2, 3 and 4
-- input devices.
-- tpd_c_q VitalDelayType01 The propagation delay from the c
-- input to output q for 3 and 4 input
-- devices.
-- tpd_d_q VitalDelayType01 The propagation delay from the d
-- input to output q for 4 input
-- devices.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic The output signal of the evaluated
-- logic function.
--
-- Returns
-- none
-- -------------------------------------------------------------------------
PROCEDURE VitalAND2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNAND2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXNOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalAND3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNAND3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXNOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalAND4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNAND4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXNOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: Buffer logic device concurrent procedure calls.
--
-- Description: Four buffer sequential primitive function calls are
-- provided. One is a simple buffer and the others
-- offer high and low enables and the four permits
-- propagation of Z as shown below:
--
-- VitalBUF Standard non-inverting buffer
-- VitalBUFIF0 Non-inverting buffer with Enable low
-- VitalBUFIF1 Non-inverting buffer with Enable high
-- VitalIDENT Pass buffer capable of propagating Z
--
-- Arguments:
--
-- IN Type Description
-- Data std_ulogic Input to the buffers
-- Enable std_ulogic Enable for the enable high and low
-- buffers.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- simple buffer.
-- VitalResultZMapType The output signal strength result map
-- to modify default result mapping
-- which has high impedance capability
-- for the enable high, enable low and
-- identity buffers.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic The output signal of the evaluated
-- buffer function.
--
-- -------------------------------------------------------------------------
FUNCTION VitalBUF (
CONSTANT Data : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalBUFIF0 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
FUNCTION VitalBUFIF1 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
FUNCTION VitalIDENT (
CONSTANT Data : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: Buffer device procedure calls.
--
-- Description: Four buffer concurrent primitive procedure calls are
-- provided. One is a simple buffer and the others
-- offer high and low enables and the fourth permits
-- propagation of Z as shown below:
--
-- VitalBUF Standard non-inverting buffer
-- VitalBUFIF0 Non-inverting buffer with Enable low
-- VitalBUFIF1 Non-inverting buffer with Enable high
-- VitalIDENT Pass buffer capable of propagating Z
--
-- Arguments:
--
-- IN Type Description
-- a std_ulogic Input signal to the buffers
-- Enable std_ulogic Enable signal for the enable high and
-- low buffers.
-- tpd_a_q VitalDelayType01 Propagation delay from input to
-- output for the simple buffer.
-- VitalDelayType01Z Propagation delay from input to
-- to output for the enable high and low
-- and identity buffers.
-- tpd_enable_q VitalDelayType01Z Propagation delay from enable to
-- output for the enable high and low
-- buffers.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- simple buffer.
-- VitalResultZMapType The output signal strength result map
-- to modify default result mapping
-- which has high impedance capability
-- for the enable high, enable low and
-- identity buffers.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic Output of the buffers.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalBUF (
SIGNAL q : OUT std_ulogic;
SIGNAL a : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalBUFIF0 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap);
PROCEDURE VitalBUFIF1 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap);
PROCEDURE VitalIDENT (
SIGNAL q : OUT std_ulogic;
SIGNAL a : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap );
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: VitalINV, VitalINVIF0, VitalINVIF1
--
-- Description: Inverter functions which return the inverted signal
-- value. Inverters with enable low and high are provided
-- which can drive high impedance when inactive.
--
-- Arguments:
--
-- IN Type Description
-- Data std_ulogic Input to the inverter
-- Enable std_ulogic Enable to the enable high and low
-- inverters.
-- ResultMap VitalResultMap The output signal strength result map
-- to modify default result mapping for
-- simple inverter.
-- VitalResultZMapType The output signal strength result map
-- to modify default result mapping
-- which has high impedance capability
-- for the enable high, enable low
-- inverters.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic Output of the inverter
--
-- -------------------------------------------------------------------------
FUNCTION VitalINV (
CONSTANT Data : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalINVIF0 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
FUNCTION VitalINVIF1 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: VitalINV, VitalINVIF0, VitalINVIF1
--
-- Description: The concurrent primitive procedure calls implement a
-- signal inversion function. The output is a parameter to
-- the procedure. The path delay information is passed as
-- a parameter to the call.
--
-- Arguments:
--
-- IN Type Description
-- a std_ulogic Input signal for the simple inverter
-- Data std_ulogic Input signal for the enable high and
-- low inverters.
-- Enable std_ulogic Enable signal for the enable high and
-- low inverters.
-- tpd_a_q VitalDelayType01 Propagation delay from input a to
-- output q for the simple inverter.
-- tpd_data_q VitalDelayType01 Propagation delay from input data to
-- output q for the enable high and low
-- inverters.
-- tpd_enable_q VitalDelayType01Z Propagation delay from input enable
-- to output q for the enable high and
-- low inverters.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- simple inverter.
-- VitalResultZMapType The output signal strength result map
-- to modify default result mapping
-- which has high impedance capability
-- for the enable high, enable low
-- inverters.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic Output signal of the inverter.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalINV (
SIGNAL q : OUT std_ulogic;
SIGNAL a : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalINVIF0 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap);
PROCEDURE VitalINVIF1 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap);
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: VitalMUX, VitalMUX2, VitalMUX4, VitalMUX8
--
-- Description: The VitalMUX functions return the selected data bit
-- based on the value of dSelect. For MUX2, the function
-- returns data0 when dselect is 0 and returns data1 when
-- dselect is 1. When dselect is X, result is X for MUX2
-- when data0 /= data1. X propagation is reduced when the
-- dselect signal is X and both data signals are identical.
-- When this is the case, the result returned is the value
-- of the data signals.
--
-- For the N input device:
--
-- N must equal 2**(bits of dSelect)
--
-- Arguments:
--
-- IN Type Description
-- Data std_logic_vector Input signal for the N-bit, 4-bit and
-- 8-bit mux.
-- Data1,Data0 std_ulogic Input signals for the 2-bit mux.
-- dSelect std_ulogic Select signal for 2-bit mux
-- std_logic_vector2 Select signal for 4-bit mux
-- std_logic_vector3 Select signal for 8-bit mux
-- std_logic_vector Select signal for N-Bit mux
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- all muxes.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic The value of the selected bit is
-- returned.
--
-- -------------------------------------------------------------------------
FUNCTION VitalMUX (
CONSTANT Data : IN std_logic_vector;
CONSTANT dSelect : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalMUX2 (
CONSTANT Data1, Data0 : IN std_ulogic;
CONSTANT dSelect : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalMUX4 (
CONSTANT Data : IN std_logic_vector4;
CONSTANT dSelect : IN std_logic_vector2;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalMUX8 (
CONSTANT Data : IN std_logic_vector8;
CONSTANT dSelect : IN std_logic_vector3;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: VitalMUX, VitalMUX2, VitalMUX4, VitalMUX8
--
-- Description: The VitalMUX concurrent primitive procedures calls
-- return in the output q the value of the selected data
-- bit based on the value of dsel. For the two bit mux,
-- the data returned is either d0 or d1, the data input.
-- For 4, 8 and N-bit functions, data is the input and is
-- of type std_logic_vector. For the 2-bit mux, if d0 or
-- d1 are X, the output is X only when d0 do not equal d1.
-- When d0 and d1 are equal, the return value is this value
-- to reduce X propagation.
--
-- Propagation delay information is passed as a parameter
-- to the procedure call for delays from data to output and
-- select to output. For 2-bit muxes, the propagation
-- delays from data are provided for d0 and d1 to output.
--
--
-- Arguments:
--
-- IN Type Description
-- d1,d0 std_ulogic Input signals for the 2-bit mux.
-- Data std_logic_vector4 Input signals for the 4-bit mux.
-- std_logic_vector8 Input signals for the 8-bit mux.
-- std_logic_vector Input signals for the N-bit mux.
-- dsel std_ulogic Select signal for the 2-bit mux.
-- std_logic_vector2 Select signals for the 4-bit mux.
-- std_logic_vector3 Select signals for the 8-bit mux.
-- std_logic_vector Select signals for the N-bit mux.
-- tpd_d1_q VitalDelayType01 Propagation delay from input d1 to
-- output q for 2-bit mux.
-- tpd_d0_q VitalDelayType01 Propagation delay from input d0 to
-- output q for 2-bit mux.
-- tpd_data_q VitalDelayArrayType01 Propagation delay from input data
-- to output q for 4-bit, 8-bit and
-- N-bit muxes.
-- tpd_dsel_q VitalDelayType01 Propagation delay from input dsel
-- to output q for 2-bit mux.
-- VitalDelayArrayType01 Propagation delay from input dsel
-- to output q for 4-bit, 8-bit and
-- N-bit muxes.
-- ResultMap VitalResultMapType The output signal strength result
-- map to modify default result
-- mapping for all muxes.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic The value of the selected signal.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalMUX (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
SIGNAL dSel : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_dsel_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalMUX2 (
SIGNAL q : OUT std_ulogic;
SIGNAL d1, d0 : IN std_ulogic;
SIGNAL dSel : IN std_ulogic;
CONSTANT tpd_d1_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d0_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_dsel_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalMUX4 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector4;
SIGNAL dSel : IN std_logic_vector2;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_dsel_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalMUX8 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector8;
SIGNAL dSel : IN std_logic_vector3;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_dsel_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: VitalDECODER, VitalDECODER2, VitalDECODER4,
-- VitalDECODER8
--
-- Description: The VitalDECODER functions are the sequential primitive
-- calls for decoder logic. The functions are provided
-- for N, 2, 4 and 8-bit outputs.
--
-- The N-bit decoder is (2**(bits of data)) wide.
--
-- The VitalDECODER returns 0 if enable is 0.
-- The VitalDECODER returns the result bit set to 1 if
-- enable is 1. All other bits of returned result are
-- set to 0.
--
-- The returned array is in descending order:
-- (n-1 downto 0).
--
-- Arguments:
--
-- IN Type Description
-- Data std_ulogic Input signal for 2-bit decoder.
-- std_logic_vector2 Input signals for 4-bit decoder.
-- std_logic_vector3 Input signals for 8-bit decoder.
-- std_logic_vector Input signals for N-bit decoder.
-- Enable std_ulogic Enable input signal. The result is
-- output when enable is high.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- all output signals of the decoders.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_logic_vector2 The output of the 2-bit decoder.
-- std_logic_vector4 The output of the 4-bit decoder.
-- std_logic_vector8 The output of the 8-bit decoder.
-- std_logic_vector The output of the n-bit decoder.
--
-- -------------------------------------------------------------------------
FUNCTION VitalDECODER (
CONSTANT Data : IN std_logic_vector;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector;
FUNCTION VitalDECODER2 (
CONSTANT Data : IN std_ulogic;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector2;
FUNCTION VitalDECODER4 (
CONSTANT Data : IN std_logic_vector2;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector4;
FUNCTION VitalDECODER8 (
CONSTANT Data : IN std_logic_vector3;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector8;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: VitalDECODER, VitalDECODER2, VitalDECODER4,
-- VitalDECODER8
--
-- Description: The VitalDECODER procedures are the concurrent primitive
-- procedure calls for decoder functions. The procedures
-- are provided for N, 2, 4 and 8 outputs.
--
-- The N-bit decoder is (2**(bits of data)) wide.
--
-- The procedural form of the decoder is used for
-- distributed delay modeling. The delay information for
-- each path is passed as an argument to the procedure.
--
-- Result is set to 0 if enable is 0.
-- The result bit represented by data is set to 1 if
-- enable is 1. All other bits of result are set to 0.
--
-- The result array is in descending order: (n-1 downto 0).
--
-- For the N-bit decoder, the delay path is a vector of
-- delays from inputs to outputs.
--
-- Arguments:
--
-- IN Type Description
-- Data std_ulogic Input signal for 2-bit decoder.
-- std_logic_vector2 Input signals for 4-bit decoder.
-- std_logic_vector3 Input signals for 8-bit decoder.
-- std_logic_vector Input signals for N-bit decoder.
-- enable std_ulogic Enable input signal. The result is
-- output when enable is high.
-- tpd_data_q VitalDelayType01 Propagation delay from input data
-- to output q for 2-bit decoder.
-- VitalDelayArrayType01 Propagation delay from input data
-- to output q for 4, 8 and n-bit
-- decoders.
-- tpd_enable_q VitalDelayType01 Propagation delay from input enable
-- to output q for 2, 4, 8 and n-bit
-- decoders.
--
-- INOUT
-- none
--
-- OUT
-- q std_logic_vector2 Output signals for 2-bit decoder.
-- std_logic_vector4 Output signals for 4-bit decoder.
-- std_logic_vector8 Output signals for 8-bit decoder.
-- std_logic_vector Output signals for n-bit decoder.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalDECODER (
SIGNAL q : OUT std_logic_vector;
SIGNAL Data : IN std_logic_vector;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalDECODER2 (
SIGNAL q : OUT std_logic_vector2;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalDECODER4 (
SIGNAL q : OUT std_logic_vector4;
SIGNAL Data : IN std_logic_vector2;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalDECODER8 (
SIGNAL q : OUT std_logic_vector8;
SIGNAL Data : IN std_logic_vector3;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
-- -------------------------------------------------------------------------
-- Function Name: VitalTruthTable
--
-- Description: VitalTruthTable implements a truth table. Given
-- a set of inputs, a sequential search is performed
-- to match the input. If a match is found, the output
-- is set based on the contents of the CONSTANT TruthTable.
-- If there is no match, all X's are returned. There is
-- no limit to the size of the table.
--
-- There is a procedure and function for VitalTruthTable.
-- For each of these, a single value output (std_logic) and
-- a multi-value output (std_logic_vector) are provided.
--
-- The first dimension of the table is for number of
-- entries in the truth table and second dimension is for
-- the number of elements in a row. The number of inputs
-- in the row should be Data'LENGTH plus result'LENGTH.
--
-- Elements is a row will be interpreted as
-- Input(NumInputs - 1),.., Input(0),
-- Result(NumOutputs - 1),.., Result(0)
--
-- All inputs will be mapped to the X01 subtype
--
-- If the value of Result is not in the range 'X' to 'Z'
-- then an error will be reported. Also, the Result is
-- always given either as a 0, 1, X or Z value.
--
-- Arguments:
--
-- IN Type Description
-- TruthTable The input constant which defines the
-- behavior in truth table form.
-- DataIn The inputs to the truth table used to
-- perform input match to select
-- output(s) to value(s) to drive.
--
-- INOUT
-- none
--
-- OUT
-- Result std_logic Concurrent procedure version scalar
-- output.
-- std_logic_vector Concurrent procedure version vector
-- output.
--
-- Returns
-- Result std_logic Function version scalar output.
-- std_logic_vector Function version vector output.
--
-- -------------------------------------------------------------------------
FUNCTION VitalTruthTable (
CONSTANT TruthTable : IN VitalTruthTableType;
CONSTANT DataIn : IN std_logic_vector
) RETURN std_logic_vector;
FUNCTION VitalTruthTable (
CONSTANT TruthTable : IN VitalTruthTableType;
CONSTANT DataIn : IN std_logic_vector
) RETURN std_logic;
PROCEDURE VitalTruthTable (
SIGNAL Result : OUT std_logic_vector;
CONSTANT TruthTable : IN VitalTruthTableType;
SIGNAL DataIn : IN std_logic_vector -- IR#236
);
PROCEDURE VitalTruthTable (
SIGNAL Result : OUT std_logic;
CONSTANT TruthTable : IN VitalTruthTableType;
SIGNAL DataIn : IN std_logic_vector -- IR#236
);
-- -------------------------------------------------------------------------
--
-- Function Name: VitalStateTable
--
-- Description: VitalStateTable is a non-concurrent implementation of a
-- state machine (Moore Machine). It is used to model
-- sequential devices and devices with internal states.
--
-- The procedure takes the value of the state table
-- data set and performs a sequential search of the
-- CONSTANT StateTable until a match is found. Once a
-- match is found, the result of that match is applied
-- to Result. If there is no match, all X's are returned.
-- The resultant output becomes the input for the next
-- state.
--
-- The first dimension of the table is the number of
-- entries in the state table and second dimension is the
-- number of elements in a row of the table. The number of
-- inputs in the row should be DataIn'LENGTH. Result should
-- contain the current state (which will become the next
-- state) as well as the outputs
--
-- Elements is a row of the table will be interpreted as
-- Input(NumInputs-1),.., Input(0), State(NumStates-1),
-- ..., State(0),Output(NumOutputs-1),.., Output(0)
--
-- where State(numStates-1) DOWNTO State(0) represent the
-- present state and Output(NumOutputs - 1) DOWNTO
-- Outputs(NumOutputs - NumStates) represent the new
-- values of the state variables (i.e. the next state).
-- Also, Output(NumOutputs - NumStates - 1)
--
-- This procedure returns the next state and the new
-- outputs when a match is made between the present state
-- and present inputs and the state table. A search is
-- made starting at the top of the state table and
-- terminates with the first match. If no match is found
-- then the next state and new outputs are set to all 'X's.
--
-- (Asynchronous inputs (i.e. resets and clears) must be
-- handled by placing the corresponding entries at the top
-- of the table. )
--
-- All inputs will be mapped to the X01 subtype.
--
-- NOTE: Edge transitions should not be used as values
-- for the state variables in the present state
-- portion of the state table. The only valid
-- values that can be used for the present state
-- portion of the state table are:
-- 'X', '0', '1', 'B', '-'
--
-- Arguments:
--
-- IN Type Description
-- StateTable VitalStateTableType The input constant which defines
-- the behavior in state table form.
-- DataIn std_logic_vector The current state inputs to the
-- state table used to perform input
-- matches and transition
-- calculations.
-- NumStates NATURAL Number of state variables
--
-- INOUT
-- Result std_logic Output signal for scalar version of
-- the concurrent procedure call.
-- std_logic_vector Output signals for vector version
-- of the concurrent procedure call.
-- PreviousDataIn std_logic_vector The previous inputs and states used
-- in transition calculations and to
-- set outputs for steady state cases.
--
-- OUT
-- none
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalStateTable (
VARIABLE Result : INOUT std_logic_vector;
VARIABLE PreviousDataIn : INOUT std_logic_vector;
CONSTANT StateTable : IN VitalStateTableType;
CONSTANT DataIn : IN std_logic_vector;
CONSTANT NumStates : IN NATURAL
);
PROCEDURE VitalStateTable (
VARIABLE Result : INOUT std_logic;
VARIABLE PreviousDataIn : INOUT std_logic_vector;
CONSTANT StateTable : IN VitalStateTableType;
CONSTANT DataIn : IN std_logic_vector
);
PROCEDURE VitalStateTable (
SIGNAL Result : INOUT std_logic_vector;
CONSTANT StateTable : IN VitalStateTableType;
SIGNAL DataIn : IN std_logic_vector;
CONSTANT NumStates : IN NATURAL
);
PROCEDURE VitalStateTable (
SIGNAL Result : INOUT std_logic;
CONSTANT StateTable : IN VitalStateTableType;
SIGNAL DataIn : IN std_logic_vector
);
-- -------------------------------------------------------------------------
--
-- Function Name: VitalResolve
--
-- Description: VitalResolve takes a vector of signals and resolves
-- them to a std_ulogic value. This procedure can be used
-- to resolve multiple drivers in a single model.
--
-- Arguments:
--
-- IN Type Description
-- Data std_logic_vector Set of input signals which drive a
-- common signal.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic Output signal which is the resolved
-- value being driven by the collection of
-- input signals.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalResolve (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector); --IR236 4/2/98
END VITAL_Primitives;
|
-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 7.1 Build 156 04/30/2007
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
package cycloneiii_atom_pack is
function str_to_bin (lut_mask : string ) return std_logic_vector;
function product(list : std_logic_vector) return std_logic ;
function alt_conv_integer(arg : in std_logic_vector) return integer;
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
-- default control options
-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent;
-- change default delay type to Transport : for spr 68748
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
-- output strength mapping
-- UX01ZWHL-
CONSTANT PullUp : VitalOutputMapType := "UX01HX01X";
CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X";
CONSTANT PullDown : VitalOutputMapType := "UX01LX01X";
-- primitive result strength mapping
CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' );
CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' );
CONSTANT L : VitalTableSymbolType := '0';
CONSTANT H : VitalTableSymbolType := '1';
CONSTANT x : VitalTableSymbolType := '-';
CONSTANT S : VitalTableSymbolType := 'S';
CONSTANT R : VitalTableSymbolType := '/';
CONSTANT U : VitalTableSymbolType := 'X';
CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
-- Declare array types for CAM_SLICE
TYPE cycloneiii_mem_data IS ARRAY (0 to 31) of STD_LOGIC_VECTOR (31 downto 0);
function int2str( value : integer ) return string;
function map_x_to_0 (value : std_logic) return std_logic;
function SelectDelay (CONSTANT Paths: IN VitalPathArray01Type) return TIME;
end cycloneiii_atom_pack;
library IEEE;
use IEEE.std_logic_1164.all;
package body cycloneiii_atom_pack is
type masklength is array (4 downto 1) of std_logic_vector(3 downto 0);
function str_to_bin (lut_mask : string) return std_logic_vector is
variable slice : masklength := (OTHERS => "0000");
variable mask : std_logic_vector(15 downto 0);
begin
for i in 1 to lut_mask'length loop
case lut_mask(i) is
when '0' => slice(i) := "0000";
when '1' => slice(i) := "0001";
when '2' => slice(i) := "0010";
when '3' => slice(i) := "0011";
when '4' => slice(i) := "0100";
when '5' => slice(i) := "0101";
when '6' => slice(i) := "0110";
when '7' => slice(i) := "0111";
when '8' => slice(i) := "1000";
when '9' => slice(i) := "1001";
when 'a' => slice(i) := "1010";
when 'A' => slice(i) := "1010";
when 'b' => slice(i) := "1011";
when 'B' => slice(i) := "1011";
when 'c' => slice(i) := "1100";
when 'C' => slice(i) := "1100";
when 'd' => slice(i) := "1101";
when 'D' => slice(i) := "1101";
when 'e' => slice(i) := "1110";
when 'E' => slice(i) := "1110";
when others => slice(i) := "1111";
end case;
end loop;
mask := (slice(1) & slice(2) & slice(3) & slice(4));
return (mask);
end str_to_bin;
function product (list: std_logic_vector) return std_logic is
begin
for i in 0 to 31 loop
if list(i) = '0' then
return ('0');
end if;
end loop;
return ('1');
end product;
function alt_conv_integer(arg : in std_logic_vector) return integer is
variable result : integer;
begin
result := 0;
for i in arg'range loop
if arg(i) = '1' then
result := result + 2**i;
end if;
end loop;
return result;
end alt_conv_integer;
function int2str( value : integer ) return string is
variable ivalue,index : integer;
variable digit : integer;
variable line_no: string(8 downto 1) := " ";
begin
ivalue := value;
index := 1;
if (ivalue = 0) then
line_no := " 0";
end if;
while (ivalue > 0) loop
digit := ivalue MOD 10;
ivalue := ivalue/10;
case digit is
when 0 =>
line_no(index) := '0';
when 1 =>
line_no(index) := '1';
when 2 =>
line_no(index) := '2';
when 3 =>
line_no(index) := '3';
when 4 =>
line_no(index) := '4';
when 5 =>
line_no(index) := '5';
when 6 =>
line_no(index) := '6';
when 7 =>
line_no(index) := '7';
when 8 =>
line_no(index) := '8';
when 9 =>
line_no(index) := '9';
when others =>
ASSERT FALSE
REPORT "Illegal number!"
SEVERITY ERROR;
end case;
index := index + 1;
end loop;
return line_no;
end;
function map_x_to_0 (value : std_logic) return std_logic is
begin
if (Is_X (value) = TRUE) then
return '0';
else
return value;
end if;
end;
function SelectDelay (CONSTANT Paths : IN VitalPathArray01Type) return TIME IS
variable Temp : TIME;
variable TransitionTime : TIME := TIME'HIGH;
variable PathDelay : TIME := TIME'HIGH;
begin
for i IN Paths'RANGE loop
next when not Paths(i).PathCondition;
next when Paths(i).InputChangeTime > TransitionTime;
Temp := Paths(i).PathDelay(tr01);
if Paths(i).InputChangeTime < TransitionTime then
PathDelay := Temp;
else
if Temp < PathDelay then
PathDelay := Temp;
end if;
end if;
TransitionTime := Paths(i).InputChangeTime;
end loop;
return PathDelay;
end;
end cycloneiii_atom_pack;
Library ieee;
use ieee.std_logic_1164.all;
Package cycloneiii_pllpack is
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer);
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
m : out integer;
n : out integer );
function gcd (X: integer; Y: integer) return integer;
function count_digit (X: integer) return integer;
function scale_num (X: integer; Y: integer) return integer;
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer) return integer;
function output_counter_value (clk_divide: integer; clk_mult : integer ;
M: integer; N: integer ) return integer;
function counter_mode (duty_cycle: integer; output_counter_value: integer) return string;
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer;
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer;
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function counter_time_delay ( clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer;
function get_phase_degree (phase_shift: integer; clk_period: integer) return integer;
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer;
function counter_ph (tap_phase: integer; m : integer; n: integer) return integer;
function ph_adjust (tap_phase: integer; ph_base : integer) return integer;
function translate_string (mode : string) return string;
function str2int (s : string) return integer;
function dqs_str2int (s : string) return integer;
end cycloneiii_pllpack;
package body cycloneiii_pllpack is
-- finds the closest integer fraction of a given pair of numerator and denominator.
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer) is
constant MAX_ITER : integer := 20;
type INT_ARRAY is array ((MAX_ITER-1) downto 0) of integer;
variable quotient_array : INT_ARRAY;
variable int_loop_iter : integer;
variable int_quot : integer;
variable m_value : integer;
variable d_value : integer;
variable old_m_value : integer;
variable swap : integer;
variable loop_iter : integer;
variable num : integer;
variable den : integer;
variable i_max_iter : integer;
begin
loop_iter := 0;
if (numerator = 0) then
num := 1;
else
num := numerator;
end if;
if (denominator = 0) then
den := 1;
else
den := denominator;
end if;
i_max_iter := max_iter;
while (loop_iter < i_max_iter) loop
int_quot := num / den;
quotient_array(loop_iter) := int_quot;
num := num - (den*int_quot);
loop_iter := loop_iter+1;
if ((num = 0) or (max_denom /= -1) or (loop_iter = i_max_iter)) then
-- calculate the numerator and denominator if there is a restriction on the
-- max denom value or if the loop is ending
m_value := 0;
d_value := 1;
-- get the rounded value at this stage for the remaining fraction
if (den /= 0) then
m_value := (2*num/den);
end if;
-- calculate the fraction numerator and denominator at this stage
for int_loop_iter in (loop_iter-1) downto 0 loop
if (m_value = 0) then
m_value := quotient_array(int_loop_iter);
d_value := 1;
else
old_m_value := m_value;
m_value := (quotient_array(int_loop_iter)*m_value) + d_value;
d_value := old_m_value;
end if;
end loop;
-- if the denominator is less than the maximum denom_value or if there is no restriction save it
if ((d_value <= max_denom) or (max_denom = -1)) then
if ((m_value = 0) or (d_value = 0)) then
fraction_num := numerator;
fraction_div := denominator;
else
fraction_num := m_value;
fraction_div := d_value;
end if;
end if;
-- end the loop if the denomitor has overflown or the numerator is zero (no remainder during this round)
if (((d_value > max_denom) and (max_denom /= -1)) or (num = 0)) then
i_max_iter := loop_iter;
end if;
end if;
-- swap the numerator and denominator for the next round
swap := den;
den := num;
num := swap;
end loop;
end find_simple_integer_fraction;
-- find the M and N values for Manual phase based on the following 5 criterias:
-- 1. The PFD frequency (i.e. Fin / N) must be in the range 5 MHz to 720 MHz
-- 2. The VCO frequency (i.e. Fin * M / N) must be in the range 300 MHz to 1300 MHz
-- 3. M is less than 512
-- 4. N is less than 512
-- 5. It's the smallest M/N which satisfies all the above constraints, and is within 2ps
-- of the desired vco-phase-shift-step
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
m : out integer;
n : out integer ) is
constant MAX_M : integer := 511;
constant MAX_N : integer := 511;
constant MAX_PFD : integer := 720;
constant MIN_PFD : integer := 5;
constant MAX_VCO : integer := 1300;
constant MIN_VCO : integer := 300;
variable vco_period : integer;
variable pfd_freq : integer;
variable vco_freq : integer;
variable vco_ps_step_value : integer;
variable i_m : integer;
variable i_n : integer;
variable i_pre_m : integer;
variable i_pre_n : integer;
variable i_max_iter : integer;
variable loop_iter : integer;
begin
loop_iter := 0;
i_max_iter := MAX_N;
vco_period := vco_phase_shift_step * 8;
while (loop_iter < i_max_iter) loop
loop_iter := loop_iter+1;
i_pre_m := i_m;
i_pre_n := i_n;
find_simple_integer_fraction(inclock_period, vco_period,
loop_iter, i_m, i_n);
if (((clk0_div * i_m) rem (clk0_mult * i_n) /= 0) or
((clk1_div * i_m) rem (clk1_mult * i_n) /= 0) or
((clk2_div * i_m) rem (clk2_mult * i_n) /= 0) or
((clk3_div * i_m) rem (clk3_mult * i_n) /= 0) or
((clk4_div * i_m) rem (clk4_mult * i_n) /= 0) or
((clk5_div * i_m) rem (clk5_mult * i_n) /= 0) or
((clk6_div * i_m) rem (clk6_mult * i_n) /= 0) or
((clk7_div * i_m) rem (clk7_mult * i_n) /= 0) or
((clk8_div * i_m) rem (clk8_mult * i_n) /= 0) or
((clk9_div * i_m) rem (clk9_mult * i_n) /= 0) )
then
if (loop_iter = 1)
then
n := 1;
m := lcm (clk0_mult, clk1_mult, clk2_mult, clk3_mult,
clk4_mult, clk5_mult, clk6_mult,
clk7_mult, clk8_mult, clk9_mult, inclock_period);
else
m := i_pre_m;
n := i_pre_n;
end if;
i_max_iter := loop_iter;
else
m := i_m;
n := i_n;
end if;
pfd_freq := 1000000 / (inclock_period * i_n);
vco_freq := (1000000 * i_m) / (inclock_period * i_n);
vco_ps_step_value := (inclock_period * i_n) / (8 * i_m);
if ( (i_m < max_m) and (i_n < max_n) and (pfd_freq >= min_pfd) and (pfd_freq <= max_pfd) and
(vco_freq >= min_vco) and (vco_freq <= max_vco) and
(abs(vco_ps_step_value - vco_phase_shift_step) <= 2) )
then
i_max_iter := loop_iter;
end if;
end loop;
end find_m_and_n_4_manual_phase;
-- find the greatest common denominator of X and Y
function gcd (X: integer; Y: integer) return integer is
variable L, S, R, G : integer := 1;
begin
if (X < Y) then -- find which is smaller.
S := X;
L := Y;
else
S := Y;
L := X;
end if;
R := S;
while ( R > 1) loop
S := L;
L := R;
R := S rem L; -- divide bigger number by smaller.
-- remainder becomes smaller number.
end loop;
if (R = 0) then -- if evenly divisible then L is gcd else it is 1.
G := L;
else
G := R;
end if;
return G;
end gcd;
-- count the number of digits in the given integer
function count_digit (X: integer)
return integer is
variable count, result: integer := 0;
begin
result := X;
while (result /= 0) loop
result := (result / 10);
count := count + 1;
end loop;
return count;
end count_digit;
-- reduce the given huge number to Y significant digits
function scale_num (X: integer; Y: integer)
return integer is
variable count : integer := 0;
variable lc, fac_ten, result: integer := 1;
begin
count := count_digit(X);
for lc in 1 to (count-Y) loop
fac_ten := fac_ten * 10;
end loop;
result := (X / fac_ten);
return result;
end scale_num;
-- find the least common multiple of A1 to A10
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer)
return integer is
variable M1, M2, M3, M4, M5 , M6, M7, M8, M9, R: integer := 1;
begin
M1 := (A1 * A2)/gcd(A1, A2);
M2 := (M1 * A3)/gcd(M1, A3);
M3 := (M2 * A4)/gcd(M2, A4);
M4 := (M3 * A5)/gcd(M3, A5);
M5 := (M4 * A6)/gcd(M4, A6);
M6 := (M5 * A7)/gcd(M5, A7);
M7 := (M6 * A8)/gcd(M6, A8);
M8 := (M7 * A9)/gcd(M7, A9);
M9 := (M8 * A10)/gcd(M8, A10);
if (M9 < 3) then
R := 10;
elsif ((M9 <= 10) and (M9 >= 3)) then
R := 4 * M9;
elsif (M9 > 1000) then
R := scale_num(M9,3);
else
R := M9 ;
end if;
return R;
end lcm;
-- find the factor of division of the output clock frequency compared to the VCO
function output_counter_value (clk_divide: integer; clk_mult: integer ;
M: integer; N: integer ) return integer is
variable R: integer := 1;
begin
R := (clk_divide * M)/(clk_mult * N);
return R;
end output_counter_value;
-- find the mode of each PLL counter - bypass, even or odd
function counter_mode (duty_cycle: integer; output_counter_value: integer)
return string is
variable R: string (1 to 6) := " ";
variable counter_value: integer := 1;
begin
counter_value := (2*duty_cycle*output_counter_value)/100;
if output_counter_value = 1 then
R := "bypass";
elsif (counter_value REM 2) = 0 then
R := " even";
else
R := " odd";
end if;
return R;
end counter_mode;
-- find the number of VCO clock cycles to hold the output clock high
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer is
variable R: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value *2)/100 ;
if (half_cycle_high REM 2 = 0) then
R := half_cycle_high/2 ;
else
R := (half_cycle_high/2) + 1;
end if;
return R;
end;
-- find the number of VCO clock cycles to hold the output clock low
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer is
variable R, R1: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value*2)/100 ;
if (half_cycle_high REM 2 = 0) then
R1 := half_cycle_high/2 ;
else
R1 := (half_cycle_high/2) + 1;
end if;
R := output_counter_value - R1;
return R;
end;
-- find the smallest time delay amongst t1 to t10
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 > 0) then return m9; else return 0; end if;
end;
-- find the numerically largest negative number, and return its absolute value
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 < 0) then return (0 - m9); else return 0; end if;
end;
-- adjust the phase (tap_phase) with the largest negative number (ph_base)
function ph_adjust (tap_phase: integer; ph_base : integer) return integer is
begin
return (tap_phase + ph_base);
end;
-- find the time delay for each PLL counter
function counter_time_delay (clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer is
variable R: integer := 0;
begin
R := clk_time_delay + m_time_delay - n_time_delay;
return R;
end;
-- calculate the given phase shift (in ps) in terms of degrees
function get_phase_degree (phase_shift: integer; clk_period: integer)
return integer is
variable result: integer := 0;
begin
result := ( phase_shift * 360 ) / clk_period;
-- to round up the calculation result
if (result > 0) then
result := result + 1;
elsif (result < 0) then
result := result - 1;
else
result := 0;
end if;
return result;
end;
-- find the number of VCO clock cycles to wait initially before the first rising
-- edge of the output clock
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer is
variable R: integer;
variable R1: real;
begin
R1 := (real(abs(tap_phase)) * real(m))/(360.0 * real(n)) + 0.5;
-- Note NCSim VHDL had problem in rounding up for 0.5 - 0.99.
-- This checking will ensure that the rounding up is done.
if (R1 >= 0.5) and (R1 <= 1.0) then
R1 := 1.0;
end if;
R := integer(R1);
return R;
end;
-- find which VCO phase tap (0 to 7) to align the rising edge of the output clock to
function counter_ph (tap_phase: integer; m: integer; n: integer) return integer is
variable R: integer := 0;
begin
-- 0.5 is added for proper rounding of the tap_phase.
R := (integer(real(tap_phase * m / n)+ 0.5) REM 360)/45;
return R;
end;
-- convert given string to length 6 by padding with spaces
function translate_string (mode : string) return string is
variable new_mode : string (1 to 6) := " ";
begin
if (mode = "bypass") then
new_mode := "bypass";
elsif (mode = "even") then
new_mode := " even";
elsif (mode = "odd") then
new_mode := " odd";
end if;
return new_mode;
end;
function str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "i n string parameter! "
SEVERITY ERROR;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
newdigit := newdigit * 10 + digit;
end loop;
return (sign*newdigit);
end;
function dqs_str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
variable err : boolean := false;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & " in string parameter! "
SEVERITY ERROR;
err := true;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
-- set error flag
err := true;
end case;
if (err) then
err := false;
else
newdigit := newdigit * 10 + digit;
end if;
end loop;
return (sign*newdigit);
end;
end cycloneiii_pllpack;
--
--
-- DFFE Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_dffe is
generic(
TimingChecksOn: Boolean := True;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
port(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC;
CLRN : in STD_LOGIC;
PRN : in STD_LOGIC;
CLK : in STD_LOGIC;
ENA : in STD_LOGIC);
attribute VITAL_LEVEL0 of cycloneiii_dffe : entity is TRUE;
end cycloneiii_dffe;
-- architecture body --
architecture behave of cycloneiii_dffe is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal D_ipd : STD_ULOGIC := 'U';
signal CLRN_ipd : STD_ULOGIC := 'U';
signal PRN_ipd : STD_ULOGIC := 'U';
signal CLK_ipd : STD_ULOGIC := 'U';
signal ENA_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (D_ipd, D, tipd_D);
VitalWireDelay (CLRN_ipd, CLRN, tipd_CLRN);
VitalWireDelay (PRN_ipd, PRN, tipd_PRN);
VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (D_ipd, CLRN_ipd, PRN_ipd, CLK_ipd, ENA_ipd)
-- timing check results
VARIABLE Tviol_D_CLK : STD_ULOGIC := '0';
VARIABLE Tviol_ENA_CLK : STD_ULOGIC := '0';
VARIABLE TimingData_D_CLK : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_ENA_CLK : VitalTimingDataType := VitalTimingDataInit;
-- functionality results
VARIABLE Violation : STD_ULOGIC := '0';
VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 7);
VARIABLE D_delayed : STD_ULOGIC := 'U';
VARIABLE CLK_delayed : STD_ULOGIC := 'U';
VARIABLE ENA_delayed : STD_ULOGIC := 'U';
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => '0');
-- output glitch detection variables
VARIABLE Q_VitalGlitchData : VitalGlitchDataType;
CONSTANT dffe_Q_tab : VitalStateTableType := (
( L, L, x, x, x, x, x, x, x, L ),
( L, H, L, H, H, x, x, H, x, H ),
( L, H, L, H, x, L, x, H, x, H ),
( L, H, L, x, H, H, x, H, x, H ),
( L, H, H, x, x, x, H, x, x, S ),
( L, H, x, x, x, x, L, x, x, H ),
( L, H, x, x, x, x, H, L, x, S ),
( L, x, L, L, L, x, H, H, x, L ),
( L, x, L, L, x, L, H, H, x, L ),
( L, x, L, x, L, H, H, H, x, L ),
( L, x, x, x, x, x, x, x, x, S ));
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_D_CLK,
TimingData => TimingData_D_CLK,
TestSignal => D_ipd,
TestSignalName => "D",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_D_CLK_noedge_posedge,
SetupLow => tsetup_D_CLK_noedge_posedge,
HoldHigh => thold_D_CLK_noedge_posedge,
HoldLow => thold_D_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) OR ( (NOT ENA_ipd) )) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ENA_CLK,
TimingData => TimingData_ENA_CLK,
TestSignal => ENA_ipd,
TestSignalName => "ENA",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ENA_CLK_noedge_posedge,
SetupLow => tsetup_ENA_CLK_noedge_posedge,
HoldHigh => thold_ENA_CLK_noedge_posedge,
HoldLow => thold_ENA_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
-------------------------
-- Functionality Section
-------------------------
Violation := Tviol_D_CLK or Tviol_ENA_CLK;
VitalStateTable(
StateTable => dffe_Q_tab,
DataIn => (
Violation, CLRN_ipd, CLK_delayed, Results(1), D_delayed, ENA_delayed, PRN_ipd, CLK_ipd),
Result => Results,
NumStates => 1,
PreviousDataIn => PrevData_Q);
D_delayed := D_ipd;
CLK_delayed := CLK_ipd;
ENA_delayed := ENA_ipd;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Q,
OutSignalName => "Q",
OutTemp => Results(1),
Paths => ( 0 => (PRN_ipd'last_event, tpd_PRN_Q_negedge, TRUE),
1 => (CLRN_ipd'last_event, tpd_CLRN_Q_negedge, TRUE),
2 => (CLK_ipd'last_event, tpd_CLK_Q_posedge, TRUE)),
GlitchData => Q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--
--
-- cycloneiii_mux21 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_mux21 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic);
attribute VITAL_LEVEL0 of cycloneiii_mux21 : entity is TRUE;
end cycloneiii_mux21;
architecture AltVITAL of cycloneiii_mux21 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal A_ipd, B_ipd, S_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (A_ipd, A, tipd_A);
VitalWireDelay (B_ipd, B, tipd_B);
VitalWireDelay (S_ipd, S, tipd_S);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (A_ipd, B_ipd, S_ipd)
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if (S_ipd = '1') then
tmp_MO := B_ipd;
else
tmp_MO := A_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (A_ipd'last_event, tpd_A_MO, TRUE),
1 => (B_ipd'last_event, tpd_B_MO, TRUE),
2 => (S_ipd'last_event, tpd_S_MO, TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- cycloneiii_mux41 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_mux41 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN0_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN1_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN2_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN3_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_IN0 : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01;
tipd_IN2 : VitalDelayType01 := DefPropDelay01;
tipd_IN3 : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01)
);
port (
IN0 : in std_logic := '0';
IN1 : in std_logic := '0';
IN2 : in std_logic := '0';
IN3 : in std_logic := '0';
S : in std_logic_vector(1 downto 0) := (OTHERS => '0');
MO : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_mux41 : entity is TRUE;
end cycloneiii_mux41;
architecture AltVITAL of cycloneiii_mux41 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd : std_logic;
signal S_ipd : std_logic_vector(1 downto 0);
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN0_ipd, IN0, tipd_IN0);
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
VitalWireDelay (IN2_ipd, IN2, tipd_IN2);
VitalWireDelay (IN3_ipd, IN3, tipd_IN3);
VitalWireDelay (S_ipd(0), S(0), tipd_S(0));
VitalWireDelay (S_ipd(1), S(1), tipd_S(1));
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd, S_ipd(0), S_ipd(1))
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if ((S_ipd(1) = '1') AND (S_ipd(0) = '1')) then
tmp_MO := IN3_ipd;
elsif ((S_ipd(1) = '1') AND (S_ipd(0) = '0')) then
tmp_MO := IN2_ipd;
elsif ((S_ipd(1) = '0') AND (S_ipd(0) = '1')) then
tmp_MO := IN1_ipd;
else
tmp_MO := IN0_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (IN0_ipd'last_event, tpd_IN0_MO, TRUE),
1 => (IN1_ipd'last_event, tpd_IN1_MO, TRUE),
2 => (IN2_ipd'last_event, tpd_IN2_MO, TRUE),
3 => (IN3_ipd'last_event, tpd_IN3_MO, TRUE),
4 => (S_ipd(0)'last_event, tpd_S_MO(0), TRUE),
5 => (S_ipd(1)'last_event, tpd_S_MO(1), TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- cycloneiii_and1 Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.cycloneiii_atom_pack.all;
-- entity declaration --
entity cycloneiii_and1 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01);
port(
Y : out STD_LOGIC;
IN1 : in STD_LOGIC);
attribute VITAL_LEVEL0 of cycloneiii_and1 : entity is TRUE;
end cycloneiii_and1;
-- architecture body --
architecture AltVITAL of cycloneiii_and1 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
SIGNAL IN1_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN1_ipd)
-- functionality results
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
ALIAS Y_zd : STD_ULOGIC is Results(1);
-- output glitch detection variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
begin
-------------------------
-- Functionality Section
-------------------------
Y_zd := TO_X01(IN1_ipd);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (0 => (IN1_ipd'last_event, tpd_IN1_Y, TRUE)),
GlitchData => Y_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_lcell_comb
--
-- Description : Cyclone II LCELL_COMB VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_lcell_comb is
generic (
lut_mask : std_logic_vector(15 downto 0) := (OTHERS => '1');
sum_lutc_input : string := "datac";
dont_touch : string := "off";
lpm_type : string := "cycloneiii_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '1';
datab : in std_logic := '1';
datac : in std_logic := '1';
datad : in std_logic := '1';
cin : in std_logic := '0';
combout : out std_logic;
cout : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_lcell_comb : entity is TRUE;
end cycloneiii_lcell_comb;
architecture vital_lcell_comb of cycloneiii_lcell_comb is
attribute VITAL_LEVEL0 of vital_lcell_comb : architecture is TRUE;
signal dataa_ipd : std_logic;
signal datab_ipd : std_logic;
signal datac_ipd : std_logic;
signal datad_ipd : std_logic;
signal cin_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (dataa_ipd, dataa, tipd_dataa);
VitalWireDelay (datab_ipd, datab, tipd_datab);
VitalWireDelay (datac_ipd, datac, tipd_datac);
VitalWireDelay (datad_ipd, datad, tipd_datad);
VitalWireDelay (cin_ipd, cin, tipd_cin);
end block;
VITALtiming : process(dataa_ipd, datab_ipd, datac_ipd, datad_ipd,
cin_ipd)
variable combout_VitalGlitchData : VitalGlitchDataType;
variable cout_VitalGlitchData : VitalGlitchDataType;
-- output variables
variable combout_tmp : std_logic;
variable cout_tmp : std_logic;
begin
-- lut_mask_var := lut_mask;
------------------------
-- Timing Check Section
------------------------
if (sum_lutc_input = "datac") then
-- combout
combout_tmp := VitalMUX(data => lut_mask,
dselect => (datad_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
elsif (sum_lutc_input = "cin") then
-- combout
combout_tmp := VitalMUX(data => lut_mask,
dselect => (datad_ipd,
cin_ipd,
datab_ipd,
dataa_ipd));
end if;
-- cout
cout_tmp := VitalMUX(data => lut_mask,
dselect => ('0',
cin_ipd,
datab_ipd,
dataa_ipd));
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => combout,
OutSignalName => "COMBOUT",
OutTemp => combout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_combout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_combout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_combout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_combout, TRUE),
4 => (cin_ipd'last_event, tpd_cin_combout, TRUE)),
GlitchData => combout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => cout,
OutSignalName => "COUT",
OutTemp => cout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_cout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_cout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_cout, TRUE),
4 => (cin_ipd'last_event, tpd_cin_cout, TRUE)),
GlitchData => cout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_comb;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_routing_wire
--
-- Description : Cyclone III Routing Wire VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_routing_wire is
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_routing_wire : entity is TRUE;
end cycloneiii_routing_wire;
ARCHITECTURE behave of cycloneiii_routing_wire is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal datain_ipd : std_logic;
signal datainglitch_inert : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process(datain_ipd, datainglitch_inert)
variable datain_inert_VitalGlitchData : VitalGlitchDataType;
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => datainglitch_inert,
OutSignalName => "datainglitch_inert",
OutTemp => datain_ipd,
Paths => (1 => (datain_ipd'last_event, tpd_datainglitch_dataout, TRUE)),
GlitchData => datain_inert_VitalGlitchData,
Mode => VitalInertial,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => datainglitch_inert,
Paths => (1 => (datain_ipd'last_event, tpd_datain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiii_mn_cntr
--
-- Description : Timing simulation model for the M and N counter. This is a
-- common model for the input counter and the loop feedback
-- counter of the Cyclone III PLL.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY cycloneiii_mn_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END cycloneiii_mn_cntr;
ARCHITECTURE behave of cycloneiii_mn_cntr is
begin
process (clk, reset)
variable count : integer := 1;
variable first_rising_edge : boolean := true;
variable tmp_cout : std_logic;
begin
if (reset = '1') then
count := 1;
tmp_cout := '0';
first_rising_edge := true;
elsif (clk'event) then
if (clk = '1' and first_rising_edge) then
first_rising_edge := false;
tmp_cout := clk;
elsif (not first_rising_edge) then
if (count < modulus) then
count := count + 1;
else
count := 1;
tmp_cout := not tmp_cout;
end if;
end if;
end if;
cout <= transport tmp_cout after time_delay * 1 ps;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiii_scale_cntr
--
-- Description : Timing simulation model for the output scale-down counters.
-- This is a common model for the C0, C1, C2, C3, C4 and C5
-- output counters of the Cyclone III PLL.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY cycloneiii_scale_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
ph_tap : IN integer := 0;
cout : OUT std_logic
);
END cycloneiii_scale_cntr;
ARCHITECTURE behave of cycloneiii_scale_cntr is
begin
process (clk, reset)
variable tmp_cout : std_logic := '0';
variable count : integer := 1;
variable output_shift_count : integer := 1;
variable first_rising_edge : boolean := false;
begin
if (reset = '1') then
count := 1;
output_shift_count := 1;
tmp_cout := '0';
first_rising_edge := false;
elsif (clk'event) then
if (mode = " off") then
tmp_cout := '0';
elsif (mode = "bypass") then
tmp_cout := clk;
first_rising_edge := true;
elsif (not first_rising_edge) then
if (clk = '1') then
if (output_shift_count = initial) then
tmp_cout := clk;
first_rising_edge := true;
else
output_shift_count := output_shift_count + 1;
end if;
end if;
elsif (output_shift_count < initial) then
if (clk = '1') then
output_shift_count := output_shift_count + 1;
end if;
else
count := count + 1;
if (mode = " even" and (count = (high*2) + 1)) then
tmp_cout := '0';
elsif (mode = " odd" and (count = high*2)) then
tmp_cout := '0';
elsif (count = (high + low)*2 + 1) then
tmp_cout := '1';
count := 1; -- reset count
end if;
end if;
end if;
cout <= transport tmp_cout;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiii_pll_reg
--
-- Description : Simulation model for a simple DFF.
-- This is required for the generation of the bit slip-signals.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY cycloneiii_pll_reg is
PORT( clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
end cycloneiii_pll_reg;
ARCHITECTURE behave of cycloneiii_pll_reg is
begin
process (clk, prn, clrn)
variable q_reg : std_logic := '0';
begin
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk'event and clk = '1' and (ena = '1')) then
q_reg := D;
end if;
Q <= q_reg;
end process;
end behave;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiii_pll
--
-- Description : Timing simulation model for the Cyclone III PLL.
-- In the functional mode, it is also the model for the altpll
-- megafunction.
--
-- Limitations : Does not support Spread Spectrum and Bandwidth.
--
-- Outputs : Up to 10 output clocks, each defined by its own set of
-- parameters. Locked output (active high) indicates when the
-- PLL locks. clkbad and activeclock are used for
-- clock switchover to indicate which input clock has gone
-- bad, when the clock switchover initiates and which input
-- clock is being used as the reference, respectively.
-- scandataout is the data output of the serial scan chain.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE STD.TEXTIO.all;
USE work.cycloneiii_atom_pack.all;
USE work.cycloneiii_pllpack.all;
USE work.cycloneiii_mn_cntr;
USE work.cycloneiii_scale_cntr;
USE work.cycloneiii_dffe;
USE work.cycloneiii_pll_reg;
-- New Features : The list below outlines key new features in CYCLONEIII:
-- 1. Dynamic Phase Reconfiguration
-- 2. Dynamic PLL Reconfiguration (different protocol)
-- 3. More output counters
ENTITY cycloneiii_pll is
GENERIC (
operation_mode : string := "normal";
pll_type : string := "auto"; -- AUTO/FAST/ENHANCED/LEFT_RIGHT/TOP_BOTTOM
compensate_clock : string := "clock0";
inclk0_input_frequency : integer := 0;
inclk1_input_frequency : integer := 0;
self_reset_on_loss_lock : string := "off";
switch_over_type : string := "auto";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "off";
bandwidth : integer := 0;
bandwidth_type : string := "auto";
use_dc_coupling : string := "false";
lock_c : integer := 4;
sim_gate_lock_device_behavior : string := "off";
lock_high : integer := 0;
lock_low : integer := 0;
lock_window_ui : string := "0.05";
lock_window : time := 5 ps;
test_bypass_lock_detect : string := "off";
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 0;
clk0_divide_by : integer := 0;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 0;
clk1_divide_by : integer := 0;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 0;
clk2_divide_by : integer := 0;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 0;
clk3_divide_by : integer := 0;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 0;
clk4_divide_by : integer := 0;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
-- ADVANCED USER PARAMETERS
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "unused";
clk1_counter : string := "unused";
clk2_counter : string := "unused";
clk3_counter : string := "unused";
clk4_counter : string := "unused";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
m_test_source : integer := -1;
c0_test_source : integer := -1;
c1_test_source : integer := -1;
c2_test_source : integer := -1;
c3_test_source : integer := -1;
c4_test_source : integer := -1;
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
vco_post_scale : integer := 1;
vco_frequency_control : string := "auto";
vco_phase_shift_step : integer := 0;
charge_pump_current : integer := 10;
loop_filter_r : string := "1.0";
loop_filter_c : integer := 0;
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
lpm_type : string := "cycloneiii_pll";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
-- Test only
init_block_reset_a_count : integer := 1;
init_block_reset_b_count : integer := 1;
charge_pump_current_bits : integer := 0;
lock_window_ui_bits : integer := 0;
loop_filter_c_bits : integer := 0;
loop_filter_r_bits : integer := 0;
test_counter_c0_delay_chain_bits : integer := 0;
test_counter_c1_delay_chain_bits : integer := 0;
test_counter_c2_delay_chain_bits : integer := 0;
test_counter_c3_delay_chain_bits : integer := 0;
test_counter_c4_delay_chain_bits : integer := 0;
test_counter_c5_delay_chain_bits : integer := 0;
test_counter_m_delay_chain_bits : integer := 0;
test_counter_n_delay_chain_bits : integer := 0;
test_feedback_comp_delay_chain_bits : integer := 0;
test_input_comp_delay_chain_bits : integer := 0;
test_volt_reg_output_mode_bits : integer := 0;
test_volt_reg_output_voltage_bits : integer := 0;
test_volt_reg_test_mode : string := "false";
vco_range_detector_high_bits : integer := 0;
vco_range_detector_low_bits : integer := 0;
-- Simulation only generics
family_name : string := "Cyclone III";
-- VITAL generics
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanclkena : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_configupdate : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01;
tipd_phaseupdown : VitalDelayType01 := DefPropDelay01;
tipd_phasecounterselect : VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phasestep : VitalDelayType01 := DefPropDelay01;
tsetup_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
use_vco_bypass : string := "false"
);
PORT
(
inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
fbout : out std_logic;
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
scanclkena : in std_logic := '0';
configupdate : in std_logic := '0';
clk : out std_logic_vector(4 downto 0);
phasecounterselect : in std_logic_vector(2 downto 0) := "000";
phaseupdown : in std_logic := '0';
phasestep : in std_logic := '0';
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
phasedone : out std_logic;
vcooverrange : out std_logic;
vcounderrange : out std_logic
);
END cycloneiii_pll;
ARCHITECTURE vital_pll of cycloneiii_pll is
TYPE int_array is ARRAY(NATURAL RANGE <>) of integer;
TYPE str_array is ARRAY(NATURAL RANGE <>) of string(1 to 6);
TYPE str_array1 is ARRAY(NATURAL RANGE <>) of string(1 to 9);
TYPE std_logic_array is ARRAY(NATURAL RANGE <>) of std_logic;
-- internal advanced parameter signals
signal i_vco_min : integer;
signal i_vco_max : integer;
signal i_vco_center : integer;
signal i_pfd_min : integer;
signal i_pfd_max : integer;
signal c_ph_val : int_array(0 to 4) := (OTHERS => 0);
signal c_ph_val_tmp : int_array(0 to 4) := (OTHERS => 0);
signal c_high_val : int_array(0 to 4) := (OTHERS => 1);
signal c_low_val : int_array(0 to 4) := (OTHERS => 1);
signal c_initial_val : int_array(0 to 4) := (OTHERS => 1);
signal c_mode_val : str_array(0 to 4);
-- old values
signal c_high_val_old : int_array(0 to 4) := (OTHERS => 1);
signal c_low_val_old : int_array(0 to 4) := (OTHERS => 1);
signal c_ph_val_old : int_array(0 to 4) := (OTHERS => 0);
signal c_mode_val_old : str_array(0 to 4);
-- hold registers
signal c_high_val_hold : int_array(0 to 4) := (OTHERS => 1);
signal c_low_val_hold : int_array(0 to 4) := (OTHERS => 1);
signal c_ph_val_hold : int_array(0 to 4) := (OTHERS => 0);
signal c_mode_val_hold : str_array(0 to 4);
-- temp registers
signal sig_c_ph_val_tmp : int_array(0 to 4) := (OTHERS => 0);
signal c_ph_val_orig : int_array(0 to 4) := (OTHERS => 0);
signal real_lock_high : integer := 0;
signal i_clk4_counter : integer := 4;
signal i_clk3_counter : integer := 3;
signal i_clk2_counter : integer := 2;
signal i_clk1_counter : integer := 1;
signal i_clk0_counter : integer := 0;
signal i_charge_pump_current : integer;
signal i_loop_filter_r : integer;
-- end internal advanced parameter signals
-- CONSTANTS
CONSTANT SCAN_CHAIN : integer := 144;
CONSTANT GPP_SCAN_CHAIN : integer := 234;
CONSTANT FAST_SCAN_CHAIN : integer := 180;
CONSTANT cntrs : str_array(4 downto 0) := (" C4", " C3", " C2", " C1", " C0");
CONSTANT ss_cntrs : str_array(0 to 3) := (" M", " M2", " N", " N2");
CONSTANT loop_filter_c_arr : int_array(0 to 3) := (0,0,0,0);
CONSTANT fpll_loop_filter_c_arr : int_array(0 to 3) := (0,0,0,0);
CONSTANT charge_pump_curr_arr : int_array(0 to 15) := (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0);
CONSTANT num_phase_taps : integer := 8;
-- signals
signal vcc : std_logic := '1';
signal fbclk : std_logic;
signal refclk : std_logic;
signal vco_over : std_logic := '0';
signal vco_under : std_logic := '1';
signal pll_locked : boolean := false;
signal c_clk : std_logic_array(0 to 4);
signal vco_out : std_logic_vector(7 downto 0) := (OTHERS => '0');
-- signals to assign values to counter params
signal m_val : integer := 1;
signal n_val : integer := 1;
signal m_ph_val : integer := 0;
signal m_ph_initial : integer := 0;
signal m_ph_val_tmp : integer := 0;
signal m_initial_val : integer := m_initial;
signal m_mode_val : string(1 to 6) := " ";
signal n_mode_val : string(1 to 6) := " ";
signal lfc_val : integer := 0;
signal cp_curr_val : integer := 0;
signal lfr_val : string(1 to 2) := " ";
signal cp_curr_old_bit_setting : std_logic_vector(14 to 16) := (OTHERS => '0');
signal cp_curr_val_bit_setting : std_logic_vector(14 to 16) := (OTHERS => '0');
signal lfr_old_bit_setting : std_logic_vector(3 to 7) := (OTHERS => '0');
signal lfr_val_bit_setting : std_logic_vector(3 to 7) := (OTHERS => '0');
signal lfc_old_bit_setting : std_logic_vector(1 to 2) := (OTHERS => '0');
signal lfc_val_bit_setting : std_logic_vector(1 to 2) := (OTHERS => '0');
signal pll_reconfig_display_full_setting : boolean := FALSE; -- display full setting, change to true
-- old values
signal m_val_old : integer := 1;
signal n_val_old : integer := 1;
signal m_mode_val_old : string(1 to 6) := " ";
signal n_mode_val_old : string(1 to 6) := " ";
signal m_ph_val_old : integer := 0;
signal lfc_old : integer := 0;
signal cp_curr_old : integer := 0;
signal lfr_old : string(1 to 2) := " ";
signal num_output_cntrs : integer := 5;
signal scanclk_period : time := 1 ps;
signal scan_data : std_logic_vector(0 to 143) := (OTHERS => '0');
signal clk_pfd : std_logic_vector(0 to 4);
signal clk0_tmp : std_logic;
signal clk1_tmp : std_logic;
signal clk2_tmp : std_logic;
signal clk3_tmp : std_logic;
signal clk4_tmp : std_logic;
signal update_conf_latches : std_logic := '0';
signal update_conf_latches_reg : std_logic := '0';
signal clkin : std_logic := '0';
signal gate_locked : std_logic := '0';
signal pfd_locked : std_logic := '0';
signal lock : std_logic := '0';
signal about_to_lock : boolean := false;
signal reconfig_err : boolean := false;
signal inclk_c0 : std_logic;
signal inclk_c1 : std_logic;
signal inclk_c2 : std_logic;
signal inclk_c3 : std_logic;
signal inclk_c4 : std_logic;
signal inclk_m : std_logic;
signal devpor : std_logic;
signal devclrn : std_logic;
signal inclk0_ipd : std_logic;
signal inclk1_ipd : std_logic;
signal pfdena_ipd : std_logic;
signal areset_ipd : std_logic;
signal fbin_ipd : std_logic;
signal scanclk_ipd : std_logic;
signal scanclkena_ipd, scanclkena_reg : std_logic;
signal scandata_ipd : std_logic;
signal clkswitch_ipd : std_logic;
signal phasecounterselect_ipd : std_logic_vector(2 downto 0);
signal phaseupdown_ipd : std_logic;
signal phasestep_ipd : std_logic;
signal configupdate_ipd : std_logic;
-- registered signals
signal sig_offset : time := 0 ps;
signal sig_refclk_time : time := 0 ps;
signal sig_fbclk_period : time := 0 ps;
signal sig_vco_period_was_phase_adjusted : boolean := false;
signal sig_phase_adjust_was_scheduled : boolean := false;
signal sig_stop_vco : std_logic := '0';
signal sig_m_times_vco_period : time := 0 ps;
signal sig_new_m_times_vco_period : time := 0 ps;
signal sig_got_refclk_posedge : boolean := false;
signal sig_got_fbclk_posedge : boolean := false;
signal sig_got_second_refclk : boolean := false;
signal m_delay : integer := 0;
signal n_delay : integer := 0;
signal inclk1_tmp : std_logic := '0';
signal reset_low : std_logic := '0';
-- Phase Reconfig
SIGNAL phasecounterselect_reg : std_logic_vector(2 DOWNTO 0);
SIGNAL phaseupdown_reg : std_logic := '0';
SIGNAL phasestep_reg : std_logic := '0';
SIGNAL phasestep_high_count : integer := 0;
SIGNAL update_phase : std_logic := '0';
signal scandataout_tmp : std_logic := '0';
signal scandata_in : std_logic := '0';
signal scandata_out : std_logic := '0';
signal scandone_tmp : std_logic := '1';
signal initiate_reconfig : std_logic := '0';
signal sig_refclk_period : time := (inclk0_input_frequency * 1 ps) * n;
signal schedule_vco : std_logic := '0';
signal areset_ena_sig : std_logic := '0';
signal pll_in_test_mode : boolean := false;
signal inclk_c_from_vco : std_logic_array(0 to 4);
signal inclk_m_from_vco : std_logic;
COMPONENT cycloneiii_mn_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END COMPONENT;
COMPONENT cycloneiii_scale_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
ph_tap : IN integer := 0
);
END COMPONENT;
COMPONENT cycloneiii_dffe
GENERIC(
TimingChecksOn: Boolean := true;
InstancePath: STRING := "*";
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
COMPONENT cycloneiii_pll_reg
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (inclk0_ipd, inclk(0), tipd_inclk(0));
VitalWireDelay (inclk1_ipd, inclk(1), tipd_inclk(1));
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (pfdena_ipd, pfdena, tipd_pfdena);
VitalWireDelay (scanclk_ipd, scanclk, tipd_scanclk);
VitalWireDelay (scanclkena_ipd, scanclkena, tipd_scanclkena);
VitalWireDelay (scandata_ipd, scandata, tipd_scandata);
VitalWireDelay (configupdate_ipd, configupdate, tipd_configupdate);
VitalWireDelay (clkswitch_ipd, clkswitch, tipd_clkswitch);
VitalWireDelay (phaseupdown_ipd, phaseupdown, tipd_phaseupdown);
VitalWireDelay (phasestep_ipd, phasestep, tipd_phasestep);
VitalWireDelay (phasecounterselect_ipd(0), phasecounterselect(0), tipd_phasecounterselect(0));
VitalWireDelay (phasecounterselect_ipd(1), phasecounterselect(1), tipd_phasecounterselect(1));
VitalWireDelay (phasecounterselect_ipd(2), phasecounterselect(2), tipd_phasecounterselect(2));
end block;
inclk_m <= fbclk when m_test_source = 0 else
refclk when m_test_source = 1 else
inclk_m_from_vco;
areset_ena_sig <= areset_ipd or sig_stop_vco;
pll_in_test_mode <= true when (m_test_source /= -1 or c0_test_source /= -1 or
c1_test_source /= -1 or c2_test_source /= -1 or
c3_test_source /= -1 or c4_test_source /= -1)
else false;
real_lock_high <= lock_high WHEN (sim_gate_lock_device_behavior = "on") ELSE 0;
m1 : cycloneiii_mn_cntr
port map ( clk => inclk_m,
reset => areset_ena_sig,
cout => fbclk,
initial_value => m_initial_val,
modulus => m_val,
time_delay => m_delay
);
-- add delta delay to inclk1 to ensure inclk0 and inclk1 are processed
-- in different simulation deltas.
inclk1_tmp <= inclk1_ipd;
process (inclk0_ipd, inclk1_tmp, clkswitch_ipd)
variable input_value : std_logic := '0';
variable current_clock : integer := 0;
variable clk0_count, clk1_count : integer := 0;
variable clk0_is_bad, clk1_is_bad : std_logic := '0';
variable primary_clk_is_bad : boolean := false;
variable current_clk_is_bad : boolean := false;
variable got_curr_clk_falling_edge_after_clkswitch : boolean := false;
variable switch_over_count : integer := 0;
variable active_clock : std_logic := '0';
variable external_switch : boolean := false;
begin
if (now = 0 ps) then
if (switch_over_type = "manual" and clkswitch_ipd = '1') then
current_clock := 1;
active_clock := '1';
end if;
end if;
if (clkswitch_ipd'event and clkswitch_ipd = '1' and switch_over_type = "auto") then
external_switch := true;
elsif (switch_over_type = "manual") then
if (clkswitch_ipd'event and clkswitch_ipd = '1') then
if (current_clock = 0) then
current_clock := 1;
active_clock := '1';
clkin <= transport inclk1_tmp;
elsif (current_clock = 1) then
current_clock := 0;
active_clock := '0';
clkin <= transport inclk0_ipd;
end if;
end if;
end if;
-- save the current inclk event value
if (inclk0_ipd'event) then
input_value := inclk0_ipd;
elsif (inclk1_tmp'event) then
input_value := inclk1_tmp;
end if;
-- check if either input clk is bad
if (inclk0_ipd'event and inclk0_ipd = '1') then
clk0_count := clk0_count + 1;
clk0_is_bad := '0';
clk1_count := 0;
if (clk0_count > 2) then
-- no event on other clk for 2 cycles
clk1_is_bad := '1';
if (current_clock = 1) then
current_clk_is_bad := true;
end if;
end if;
end if;
if (inclk1_tmp'event and inclk1_tmp = '1') then
clk1_count := clk1_count + 1;
clk1_is_bad := '0';
clk0_count := 0;
if (clk1_count > 2) then
-- no event on other clk for 2 cycles
clk0_is_bad := '1';
if (current_clock = 0) then
current_clk_is_bad := true;
end if;
end if;
end if;
-- check if the bad clk is the primary clock
if (clk0_is_bad = '1') then
primary_clk_is_bad := true;
else
primary_clk_is_bad := false;
end if;
-- actual switching
if (inclk0_ipd'event and current_clock = 0) then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk0_ipd = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk0_ipd;
end if;
else
clkin <= transport inclk0_ipd;
end if;
elsif (inclk1_tmp'event and current_clock = 1) then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk1_tmp = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk1_tmp;
end if;
else
clkin <= transport inclk1_tmp;
end if;
else
if (input_value = '1' and enable_switch_over_counter = "on" and primary_clk_is_bad) then
switch_over_count := switch_over_count + 1;
end if;
if (input_value = '0') then
if (external_switch and (got_curr_clk_falling_edge_after_clkswitch or current_clk_is_bad)) or (primary_clk_is_bad and clkswitch_ipd /= '1' and (enable_switch_over_counter = "off" or switch_over_count = switch_over_counter)) then
got_curr_clk_falling_edge_after_clkswitch := false;
if (current_clock = 0) then
current_clock := 1;
else
current_clock := 0;
end if;
active_clock := not active_clock;
switch_over_count := 0;
external_switch := false;
current_clk_is_bad := false;
end if;
end if;
end if;
-- schedule outputs
clkbad(0) <= clk0_is_bad;
clkbad(1) <= clk1_is_bad;
activeclock <= active_clock;
end process;
n1 : cycloneiii_mn_cntr
port map (
clk => clkin,
reset => areset_ipd,
cout => refclk,
initial_value => n_val,
modulus => n_val);
inclk_c0 <= refclk when c0_test_source = 1 else
fbclk when c0_test_source = 0 else
inclk_c_from_vco(0);
c0 : cycloneiii_scale_cntr
port map (
clk => inclk_c0,
reset => areset_ena_sig,
cout => c_clk(0),
initial => c_initial_val(0),
high => c_high_val(0),
low => c_low_val(0),
mode => c_mode_val(0),
ph_tap => c_ph_val(0));
inclk_c1 <= refclk when c1_test_source = 1 else
fbclk when c1_test_source = 0 else
c_clk(0) when c1_use_casc_in = "on" else
inclk_c_from_vco(1);
c1 : cycloneiii_scale_cntr
port map (
clk => inclk_c1,
reset => areset_ena_sig,
cout => c_clk(1),
initial => c_initial_val(1),
high => c_high_val(1),
low => c_low_val(1),
mode => c_mode_val(1),
ph_tap => c_ph_val(1));
inclk_c2 <= refclk when c2_test_source = 1 else
fbclk when c2_test_source = 0 else
c_clk(1) when c2_use_casc_in = "on" else
inclk_c_from_vco(2);
c2 : cycloneiii_scale_cntr
port map (
clk => inclk_c2,
reset => areset_ena_sig,
cout => c_clk(2),
initial => c_initial_val(2),
high => c_high_val(2),
low => c_low_val(2),
mode => c_mode_val(2),
ph_tap => c_ph_val(2));
inclk_c3 <= refclk when c3_test_source = 1 else
fbclk when c3_test_source = 0 else
c_clk(2) when c3_use_casc_in = "on" else
inclk_c_from_vco(3);
c3 : cycloneiii_scale_cntr
port map (
clk => inclk_c3,
reset => areset_ena_sig,
cout => c_clk(3),
initial => c_initial_val(3),
high => c_high_val(3),
low => c_low_val(3),
mode => c_mode_val(3),
ph_tap => c_ph_val(3));
inclk_c4 <= refclk when c4_test_source = 1 else
fbclk when c4_test_source = 0 else
c_clk(3) when (c4_use_casc_in = "on") else
inclk_c_from_vco(4);
c4 : cycloneiii_scale_cntr
port map (
clk => inclk_c4,
reset => areset_ena_sig,
cout => c_clk(4),
initial => c_initial_val(4),
high => c_high_val(4),
low => c_low_val(4),
mode => c_mode_val(4),
ph_tap => c_ph_val(4));
process(inclk_c0, inclk_c1, areset_ipd, sig_stop_vco)
variable c0_got_first_rising_edge : boolean := false;
variable c0_count : integer := 2;
variable c0_initial_count : integer := 1;
variable c0_tmp, c1_tmp : std_logic := '0';
variable c1_got_first_rising_edge : boolean := false;
variable c1_count : integer := 2;
variable c1_initial_count : integer := 1;
begin
if (areset_ipd = '1' or sig_stop_vco = '1') then
c0_count := 2;
c1_count := 2;
c0_initial_count := 1;
c1_initial_count := 1;
c0_got_first_rising_edge := false;
c1_got_first_rising_edge := false;
else
if (not c0_got_first_rising_edge) then
if (inclk_c0'event and inclk_c0 = '1') then
if (c0_initial_count = c_initial_val(0)) then
c0_got_first_rising_edge := true;
else
c0_initial_count := c0_initial_count + 1;
end if;
end if;
elsif (inclk_c0'event) then
c0_count := c0_count + 1;
if (c0_count = (c_high_val(0) + c_low_val(0)) * 2) then
c0_count := 1;
end if;
end if;
if (inclk_c0'event and inclk_c0 = '0') then
if (c0_count = 1) then
c0_tmp := '1';
c0_got_first_rising_edge := false;
else
c0_tmp := '0';
end if;
end if;
if (not c1_got_first_rising_edge) then
if (inclk_c1'event and inclk_c1 = '1') then
if (c1_initial_count = c_initial_val(1)) then
c1_got_first_rising_edge := true;
else
c1_initial_count := c1_initial_count + 1;
end if;
end if;
elsif (inclk_c1'event) then
c1_count := c1_count + 1;
if (c1_count = (c_high_val(1) + c_low_val(1)) * 2) then
c1_count := 1;
end if;
end if;
if (inclk_c1'event and inclk_c1 = '0') then
if (c1_count = 1) then
c1_tmp := '1';
c1_got_first_rising_edge := false;
else
c1_tmp := '0';
end if;
end if;
end if;
end process;
locked <= pfd_locked WHEN (test_bypass_lock_detect = "on") ELSE
lock;
process (scandone_tmp)
variable buf : line;
begin
if (scandone_tmp'event and scandone_tmp = '1') then
if (reconfig_err = false) then
ASSERT false REPORT "PLL Reprogramming completed with the following values (Values in parantheses indicate values before reprogramming) :" severity note;
write (buf, string'(" N modulus = "));
write (buf, n_val);
write (buf, string'(" ( "));
write (buf, n_val_old);
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" M modulus = "));
write (buf, m_val);
write (buf, string'(" ( "));
write (buf, m_val_old);
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" M ph_tap = "));
write (buf, m_ph_val);
write (buf, string'(" ( "));
write (buf, m_ph_val_old);
write (buf, string'(" )"));
writeline (output, buf);
for i in 0 to (num_output_cntrs-1) loop
write (buf, cntrs(i));
write (buf, string'(" : high = "));
write (buf, c_high_val(i));
write (buf, string'(" ("));
write (buf, c_high_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , low = "));
write (buf, c_low_val(i));
write (buf, string'(" ("));
write (buf, c_low_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , mode = "));
write (buf, c_mode_val(i));
write (buf, string'(" ("));
write (buf, c_mode_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , phase tap = "));
write (buf, c_ph_val(i));
write (buf, string'(" ("));
write (buf, c_ph_val_old(i));
write (buf, string'(") "));
writeline(output, buf);
end loop;
IF (pll_reconfig_display_full_setting) THEN
write (buf, string'(" Charge Pump Current (uA) = "));
write (buf, cp_curr_val);
write (buf, string'(" ( "));
write (buf, cp_curr_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Capacitor (pF) = "));
write (buf, lfc_val);
write (buf, string'(" ( "));
write (buf, lfc_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Resistor (Kohm) = "));
write (buf, lfr_val);
write (buf, string'(" ( "));
write (buf, lfr_old);
write (buf, string'(" ) "));
writeline (output, buf);
ELSE
write (buf, string'(" Charge Pump Current (bit setting) = "));
write (buf, alt_conv_integer(cp_curr_val_bit_setting));
write (buf, string'(" ( "));
write (buf, alt_conv_integer(cp_curr_old_bit_setting));
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Capacitor (bit setting) = "));
write (buf, alt_conv_integer(lfc_val_bit_setting));
write (buf, string'(" ( "));
write (buf, alt_conv_integer(lfc_old_bit_setting));
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Resistor (bit setting) = "));
write (buf, alt_conv_integer(lfr_val_bit_setting));
write (buf, string'(" ( "));
write (buf, alt_conv_integer(lfr_old_bit_setting));
write (buf, string'(" ) "));
writeline (output, buf);
END IF;
cp_curr_old_bit_setting <= cp_curr_val_bit_setting;
lfc_old_bit_setting <= lfc_val_bit_setting;
lfr_old_bit_setting <= lfr_val_bit_setting;
else ASSERT false REPORT "Errors were encountered during PLL reprogramming. Please refer to error/warning messages above." severity warning;
end if;
end if;
end process;
update_conf_latches <= configupdate_ipd;
process (scandone_tmp,areset_ipd,update_conf_latches, c_clk(0), c_clk(1), c_clk(2), c_clk(3), c_clk(4), vco_out, fbclk, scanclk_ipd)
variable init : boolean := true;
variable low, high : std_logic_vector(7 downto 0);
variable low_fast, high_fast : std_logic_vector(3 downto 0);
variable mode : string(1 to 6) := "bypass";
variable is_error : boolean := false;
variable m_tmp, n_tmp : std_logic_vector(8 downto 0);
variable lfr_val_tmp : string(1 to 2) := " ";
variable c_high_val_tmp,c_hval : int_array(0 to 4) := (OTHERS => 1);
variable c_low_val_tmp,c_lval : int_array(0 to 4) := (OTHERS => 1);
variable c_mode_val_tmp : str_array(0 to 4);
variable m_val_tmp : integer := 0;
variable c0_rising_edge_transfer_done : boolean := false;
variable c1_rising_edge_transfer_done : boolean := false;
variable c2_rising_edge_transfer_done : boolean := false;
variable c3_rising_edge_transfer_done : boolean := false;
variable c4_rising_edge_transfer_done : boolean := false;
-- variables for scaling of multiply_by and divide_by values
variable i_clk0_mult_by : integer := 1;
variable i_clk0_div_by : integer := 1;
variable i_clk1_mult_by : integer := 1;
variable i_clk1_div_by : integer := 1;
variable i_clk2_mult_by : integer := 1;
variable i_clk2_div_by : integer := 1;
variable i_clk3_mult_by : integer := 1;
variable i_clk3_div_by : integer := 1;
variable i_clk4_mult_by : integer := 1;
variable i_clk4_div_by : integer := 1;
variable max_d_value : integer := 1;
variable new_multiplier : integer := 1;
-- internal variables for storing the phase shift number.(used in lvds mode only)
variable i_clk0_phase_shift : integer := 1;
variable i_clk1_phase_shift : integer := 1;
variable i_clk2_phase_shift : integer := 1;
-- user to advanced variables
variable max_neg_abs : integer := 0;
variable i_m_initial : integer;
variable i_m : integer := 1;
variable i_n : integer := 1;
variable i_c_high : int_array(0 to 4);
variable i_c_low : int_array(0 to 4);
variable i_c_initial : int_array(0 to 4);
variable i_c_ph : int_array(0 to 4);
variable i_c_mode : str_array(0 to 4);
variable i_m_ph : integer;
variable output_count : integer;
variable new_divisor : integer;
variable clk0_cntr : string(1 to 6) := " c0";
variable clk1_cntr : string(1 to 6) := " c1";
variable clk2_cntr : string(1 to 6) := " c2";
variable clk3_cntr : string(1 to 6) := " c3";
variable clk4_cntr : string(1 to 6) := " c4";
variable fbk_cntr : string(1 to 2);
variable fbk_cntr_index : integer;
variable start_bit : integer;
variable quiet_time : time := 0 ps;
variable slowest_clk_old : time := 0 ps;
variable slowest_clk_new : time := 0 ps;
variable i : integer := 0;
variable j : integer := 0;
variable scanread_active_edge : time := 0 ps;
variable got_first_scanclk : boolean := false;
variable scanclk_last_rising_edge : time := 0 ps;
variable current_scan_data : std_logic_vector(0 to 143) := (OTHERS => '0');
variable index : integer := 0;
variable Tviol_scandata_scanclk : std_ulogic := '0';
variable TimingData_scandata_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_scanclkena_scanclk : std_ulogic := '0';
variable TimingData_scanclkena_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable scan_chain_length : integer := GPP_SCAN_CHAIN;
variable tmp_rem : integer := 0;
variable scanclk_cycles : integer := 0;
variable lfc_tmp : std_logic_vector(1 downto 0);
variable lfr_tmp : std_logic_vector(5 downto 0);
variable lfr_int : integer := 0;
variable n_hi,n_lo,m_hi,m_lo : std_logic_vector(7 downto 0);
variable buf : line;
variable buf_scan_data : STD_LOGIC_VECTOR(0 TO 1) := (OTHERS => '0');
variable buf_scan_data_2 : STD_LOGIC_VECTOR(0 TO 2) := (OTHERS => '0');
function slowest_clk (
C0 : integer; C0_mode : string(1 to 6);
C1 : integer; C1_mode : string(1 to 6);
C2 : integer; C2_mode : string(1 to 6);
C3 : integer; C3_mode : string(1 to 6);
C4 : integer; C4_mode : string(1 to 6);
C5 : integer; C5_mode : string(1 to 6);
C6 : integer; C6_mode : string(1 to 6);
C7 : integer; C7_mode : string(1 to 6);
C8 : integer; C8_mode : string(1 to 6);
C9 : integer; C9_mode : string(1 to 6);
refclk : time; m_mod : integer) return time is
variable max_modulus : integer := 1;
variable q_period : time := 0 ps;
variable refclk_int : integer := 0;
begin
if (C0_mode /= "bypass" and C0_mode /= " off") then
max_modulus := C0;
end if;
if (C1 > max_modulus and C1_mode /= "bypass" and C1_mode /= " off") then
max_modulus := C1;
end if;
if (C2 > max_modulus and C2_mode /= "bypass" and C2_mode /= " off") then
max_modulus := C2;
end if;
if (C3 > max_modulus and C3_mode /= "bypass" and C3_mode /= " off") then
max_modulus := C3;
end if;
if (C4 > max_modulus and C4_mode /= "bypass" and C4_mode /= " off") then
max_modulus := C4;
end if;
if (C5 > max_modulus and C5_mode /= "bypass" and C5_mode /= " off") then
max_modulus := C5;
end if;
if (C6 > max_modulus and C6_mode /= "bypass" and C6_mode /= " off") then
max_modulus := C6;
end if;
if (C7 > max_modulus and C7_mode /= "bypass" and C7_mode /= " off") then
max_modulus := C7;
end if;
if (C8 > max_modulus and C8_mode /= "bypass" and C8_mode /= " off") then
max_modulus := C8;
end if;
if (C9 > max_modulus and C9_mode /= "bypass" and C9_mode /= " off") then
max_modulus := C9;
end if;
refclk_int := refclk / 1 ps;
if (m_mod /= 0) then
q_period := (refclk_int * max_modulus / m_mod) * 1 ps;
end if;
return (2*q_period);
end slowest_clk;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function extract_cntr_string (arg:string) return string is
variable str : string(1 to 6) := " c0";
begin
if (arg = "c0") then
str := " c0";
elsif (arg = "c1") then
str := " c1";
elsif (arg = "c2") then
str := " c2";
elsif (arg = "c3") then
str := " c3";
elsif (arg = "c4") then
str := " c4";
elsif (arg = "c5") then
str := " c5";
elsif (arg = "c6") then
str := " c6";
elsif (arg = "c7") then
str := " c7";
elsif (arg = "c8") then
str := " c8";
elsif (arg = "c9") then
str := " c9";
else str := " c0";
end if;
return str;
end extract_cntr_string;
function extract_cntr_index (arg:string) return integer is
variable index : integer := 0;
begin
if (arg(6) = '0') then
index := 0;
elsif (arg(6) = '1') then
index := 1;
elsif (arg(6) = '2') then
index := 2;
elsif (arg(6) = '3') then
index := 3;
elsif (arg(6) = '4') then
index := 4;
elsif (arg(6) = '5') then
index := 5;
elsif (arg(6) = '6') then
index := 6;
elsif (arg(6) = '7') then
index := 7;
elsif (arg(6) = '8') then
index := 8;
else index := 9;
end if;
return index;
end extract_cntr_index;
begin
IF (areset_ipd'EVENT AND areset_ipd = '1') then
c_ph_val <= i_c_ph;
END IF;
if (init) then
if (m = 0) then
clk4_cntr := " c4";
clk3_cntr := " c3";
clk2_cntr := " c2";
clk1_cntr := " c1";
clk0_cntr := " c0";
else
clk4_cntr := extract_cntr_string(clk4_counter);
clk3_cntr := extract_cntr_string(clk3_counter);
clk2_cntr := extract_cntr_string(clk2_counter);
clk1_cntr := extract_cntr_string(clk1_counter);
clk0_cntr := extract_cntr_string(clk0_counter);
end if;
i_clk0_counter <= extract_cntr_index(clk0_cntr);
i_clk1_counter <= extract_cntr_index(clk1_cntr);
i_clk2_counter <= extract_cntr_index(clk2_cntr);
i_clk3_counter <= extract_cntr_index(clk3_cntr);
i_clk4_counter <= extract_cntr_index(clk4_cntr);
if (m = 0) then -- convert user parameters to advanced
-- set the limit of the divide_by value that can be returned by
-- the following function.
max_d_value := 500;
-- scale down the multiply_by and divide_by values provided by the design
-- before attempting to use them in the calculations below
find_simple_integer_fraction(clk0_multiply_by, clk0_divide_by,
max_d_value, i_clk0_mult_by, i_clk0_div_by);
find_simple_integer_fraction(clk1_multiply_by, clk1_divide_by,
max_d_value, i_clk1_mult_by, i_clk1_div_by);
find_simple_integer_fraction(clk2_multiply_by, clk2_divide_by,
max_d_value, i_clk2_mult_by, i_clk2_div_by);
find_simple_integer_fraction(clk3_multiply_by, clk3_divide_by,
max_d_value, i_clk3_mult_by, i_clk3_div_by);
find_simple_integer_fraction(clk4_multiply_by, clk4_divide_by,
max_d_value, i_clk4_mult_by, i_clk4_div_by);
if (vco_frequency_control = "manual_phase") then
find_m_and_n_4_manual_phase(inclk0_input_frequency, vco_phase_shift_step,
i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by,
1,1,1,1,1,
i_clk0_div_by, i_clk1_div_by,
i_clk2_div_by, i_clk3_div_by,
i_clk4_div_by,
1,1,1,1,1,
i_m, i_n);
elsif (((pll_type = "fast") or (pll_type = "lvds") OR (pll_type = "left_right")) and ((vco_multiply_by /= 0) and (vco_divide_by /= 0))) then
i_n := vco_divide_by;
i_m := vco_multiply_by;
else
i_n := 1;
if (((pll_type = "fast") or (pll_type = "left_right")) and (compensate_clock = "lvdsclk")) then
i_m := i_clk0_mult_by;
else
i_m := lcm (i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by,
1,1,1,1,1,
inclk0_input_frequency);
end if;
end if;
if (pll_type = "flvds") then
-- Need to readjust phase shift values when the clock multiply value has been readjusted.
new_multiplier := clk0_multiply_by / i_clk0_mult_by;
i_clk0_phase_shift := str2int(clk0_phase_shift) * new_multiplier;
i_clk1_phase_shift := str2int(clk1_phase_shift) * new_multiplier;
i_clk2_phase_shift := str2int(clk2_phase_shift) * new_multiplier;
else
i_clk0_phase_shift := str2int(clk0_phase_shift);
i_clk1_phase_shift := str2int(clk1_phase_shift);
i_clk2_phase_shift := str2int(clk2_phase_shift);
end if;
max_neg_abs := maxnegabs(i_clk0_phase_shift,
i_clk1_phase_shift,
i_clk2_phase_shift,
str2int(clk3_phase_shift),
str2int(clk4_phase_shift),
0,
0,
0,
0,
0
);
i_m_ph := counter_ph(get_phase_degree(max_neg_abs,inclk0_input_frequency), i_m, i_n);
i_c_ph(0) := counter_ph(get_phase_degree(ph_adjust(i_clk0_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(1) := counter_ph(get_phase_degree(ph_adjust(i_clk1_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(2) := counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(3) := counter_ph(get_phase_degree(ph_adjust(str2int(clk3_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(4) := counter_ph(get_phase_degree(ph_adjust(str2int(clk4_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_high(0) := counter_high(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_high(1) := counter_high(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_high(2) := counter_high(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_high(3) := counter_high(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_high(4) := counter_high(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_c_low(0) := counter_low(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_low(1) := counter_low(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_low(2) := counter_low(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_low(3) := counter_low(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_low(4) := counter_low(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_m_initial := counter_initial(get_phase_degree(max_neg_abs, inclk0_input_frequency), i_m,i_n);
i_c_initial(0) := counter_initial(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(1) := counter_initial(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(2) := counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(3) := counter_initial(get_phase_degree(ph_adjust(str2int(clk3_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(4) := counter_initial(get_phase_degree(ph_adjust(str2int(clk4_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_mode(0) := counter_mode(clk0_duty_cycle, output_counter_value(i_clk0_div_by, i_clk0_mult_by, i_m, i_n));
i_c_mode(1) := counter_mode(clk1_duty_cycle, output_counter_value(i_clk1_div_by, i_clk1_mult_by, i_m, i_n));
i_c_mode(2) := counter_mode(clk2_duty_cycle, output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n));
i_c_mode(3) := counter_mode(clk3_duty_cycle, output_counter_value(i_clk3_div_by, i_clk3_mult_by, i_m, i_n));
i_c_mode(4) := counter_mode(clk4_duty_cycle, output_counter_value(i_clk4_div_by, i_clk4_mult_by, i_m, i_n));
else -- m /= 0
i_n := n;
i_m := m;
i_m_initial := m_initial;
i_m_ph := m_ph;
i_c_ph(0) := c0_ph;
i_c_ph(1) := c1_ph;
i_c_ph(2) := c2_ph;
i_c_ph(3) := c3_ph;
i_c_ph(4) := c4_ph;
i_c_high(0) := c0_high;
i_c_high(1) := c1_high;
i_c_high(2) := c2_high;
i_c_high(3) := c3_high;
i_c_high(4) := c4_high;
i_c_low(0) := c0_low;
i_c_low(1) := c1_low;
i_c_low(2) := c2_low;
i_c_low(3) := c3_low;
i_c_low(4) := c4_low;
i_c_initial(0) := c0_initial;
i_c_initial(1) := c1_initial;
i_c_initial(2) := c2_initial;
i_c_initial(3) := c3_initial;
i_c_initial(4) := c4_initial;
i_c_mode(0) := translate_string(c0_mode);
i_c_mode(1) := translate_string(c1_mode);
i_c_mode(2) := translate_string(c2_mode);
i_c_mode(3) := translate_string(c3_mode);
i_c_mode(4) := translate_string(c4_mode);
end if; -- user to advanced conversion.
m_initial_val <= i_m_initial;
n_val <= i_n;
m_val <= i_m;
if (i_m = 1) then
m_mode_val <= "bypass";
else
m_mode_val <= " ";
end if;
if (i_n = 1) then
n_mode_val <= "bypass";
else
n_mode_val <= " ";
end if;
m_ph_val <= i_m_ph;
m_ph_initial <= i_m_ph;
m_val_tmp := i_m;
for i in 0 to 4 loop
if (i_c_mode(i) = "bypass") then
if (pll_type = "fast" or pll_type = "lvds" OR (pll_type = "left_right")) then
i_c_high(i) := 16;
i_c_low(i) := 16;
else
i_c_high(i) := 256;
i_c_low(i) := 256;
end if;
end if;
c_ph_val(i) <= i_c_ph(i);
c_initial_val(i) <= i_c_initial(i);
c_high_val(i) <= i_c_high(i);
c_low_val(i) <= i_c_low(i);
c_mode_val(i) <= i_c_mode(i);
c_high_val_tmp(i) := i_c_high(i);
c_hval(i) := i_c_high(i);
c_low_val_tmp(i) := i_c_low(i);
c_lval(i) := i_c_low(i);
c_mode_val_tmp(i) := i_c_mode(i);
c_ph_val_orig(i) <= i_c_ph(i);
c_high_val_hold(i) <= i_c_high(i);
c_low_val_hold(i) <= i_c_low(i);
c_mode_val_hold(i) <= i_c_mode(i);
end loop;
scan_chain_length := SCAN_CHAIN;
num_output_cntrs <= 5;
init := false;
elsif (scandone_tmp'EVENT AND scandone_tmp = '1') then
c0_rising_edge_transfer_done := false;
c1_rising_edge_transfer_done := false;
c2_rising_edge_transfer_done := false;
c3_rising_edge_transfer_done := false;
c4_rising_edge_transfer_done := false;
update_conf_latches_reg <= '0';
elsif (update_conf_latches'event and update_conf_latches = '1') then
initiate_reconfig <= '1';
elsif (areset_ipd'event AND areset_ipd = '1') then
if (scandone_tmp = '0') then scandone_tmp <= '1' AFTER scanclk_period; end if;
elsif (scanclk_ipd'event and scanclk_ipd = '1') then
IF (initiate_reconfig = '1') THEN
initiate_reconfig <= '0';
ASSERT false REPORT "PLL Reprogramming Initiated" severity note;
update_conf_latches_reg <= update_conf_latches;
reconfig_err <= false;
scandone_tmp <= '0';
cp_curr_old <= cp_curr_val;
lfc_old <= lfc_val;
lfr_old <= lfr_val;
-- LF unused : bit 0,1
-- LF Capacitance : bits 2,3 : all values are legal
buf_scan_data := scan_data(2 TO 3);
IF ((pll_type = "fast") OR (pll_type = "lvds") OR (pll_type = "left_right")) THEN
lfc_val <= fpll_loop_filter_c_arr(alt_conv_integer(buf_scan_data));
ELSE
lfc_val <= loop_filter_c_arr(alt_conv_integer(buf_scan_data));
END IF;
-- LF Resistance : bits 4-8
-- valid values - 00000,00100,10000,10100,11000,11011,11100,11110
IF (scan_data(4 TO 8) = "00000") THEN
lfr_val <= "20";
ELSIF (scan_data(4 TO 8) = "00100") THEN
lfr_val <= "16";
ELSIF (scan_data(4 TO 8) = "10000") THEN
lfr_val <= "12";
ELSIF (scan_data(4 TO 8) = "10100") THEN
lfr_val <= "08";
ELSIF (scan_data(4 TO 8) = "11000") THEN
lfr_val <= "06";
ELSIF (scan_data(4 TO 8) = "11011") THEN
lfr_val <= "04";
ELSIF (scan_data(4 TO 8) = "11100") THEN
lfr_val <= "02";
ELSE
lfr_val <= "01";
END IF;
IF (NOT (((scan_data(4 TO 8) = "00000") OR (scan_data(4 TO 8) = "00100")) OR ((scan_data(4 TO 8) = "10000") OR (scan_data(4 TO 8) = "10100")) OR ((scan_data(4 TO 8) = "11000") OR (scan_data(4 TO 8) = "11011")) OR ((scan_data(4 TO 8) = "11100") OR (scan_data(4 TO 8) = "11110")))) THEN
WRITE(buf, string'("Illegal bit settings for Loop Filter Resistance. Legal bit values range from 000000 to 001111, 011000 to 011111, 101000 to 101111 and 111000 to 111111. Reconfiguration may not work."));
writeline(output,buf);
reconfig_err <= TRUE;
END IF;
-- CP
-- Bit 9 : CRBYPASS
-- Bit 10-14 : unused
-- Bits 15-17 : all values are legal
buf_scan_data_2 := scan_data(15 TO 17);
cp_curr_val <= charge_pump_curr_arr(alt_conv_integer(buf_scan_data_2));
-- save old values for display info.
cp_curr_val_bit_setting <= scan_data(15 TO 17);
lfc_val_bit_setting <= scan_data(2 TO 3);
lfr_val_bit_setting <= scan_data(4 TO 8);
m_val_old <= m_val;
n_val_old <= n_val;
m_mode_val_old <= m_mode_val;
n_mode_val_old <= n_mode_val;
WHILE (i < num_output_cntrs) LOOP
c_high_val_old(i) <= c_high_val(i);
c_low_val_old(i) <= c_low_val(i);
c_mode_val_old(i) <= c_mode_val(i);
i := i + 1;
END LOOP;
-- M counter
-- 1. Mode - bypass (bit 18)
IF (scan_data(18) = '1') THEN
m_mode_val <= "bypass";
-- 3. Mode - odd/even (bit 27)
ELSIF (scan_data(27) = '1') THEN
m_mode_val <= " odd";
ELSE
m_mode_val <= " even";
END IF;
-- 2. High (bit 19-26)
m_hi := scan_data(19 TO 26);
-- 4. Low (bit 28-35)
m_lo := scan_data(28 TO 35);
-- N counter
-- 1. Mode - bypass (bit 36)
IF (scan_data(36) = '1') THEN
n_mode_val <= "bypass";
-- 3. Mode - odd/even (bit 45)
ELSIF (scan_data(45) = '1') THEN
n_mode_val <= " odd";
ELSE
n_mode_val <= " even";
END IF;
-- 2. High (bit 37-44)
n_hi := scan_data(37 TO 44);
-- 4. Low (bit 46-53)
n_lo := scan_data(46 TO 53);
-- C counters (start bit 54) bit 1:mode(bypass),bit 2-9:high,bit 10:mode(odd/even),bit 11-18:low
i := 0;
WHILE (i < num_output_cntrs) LOOP
-- 1. Mode - bypass
IF (scan_data(54 + i * 18 + 0) = '1') THEN
c_mode_val_tmp(i) := "bypass";
-- 3. Mode - odd/even
ELSIF (scan_data(54 + i * 18 + 9) = '1') THEN
c_mode_val_tmp(i) := " odd";
ELSE
c_mode_val_tmp(i) := " even";
END IF;
-- 2. Hi
high := scan_data(54 + i * 18 + 1 TO 54 + i * 18 + 8);
c_hval(i) := alt_conv_integer(high);
IF (c_hval(i) /= 0) THEN
c_high_val_tmp(i) := c_hval(i);
END IF;
-- 4. Low
low := scan_data(54 + i * 18 + 10 TO 54 + i * 18 + 17);
c_lval(i) := alt_conv_integer(low);
IF (c_lval(i) /= 0) THEN
c_low_val_tmp(i) := c_lval(i);
END IF;
i := i + 1;
END LOOP;
-- Legality Checks
-- M counter value
IF ((m_hi /= m_lo) AND (scan_data(18) /= '1')) THEN
reconfig_err <= TRUE;
WRITE(buf,string'("Warning : The M counter of the " & family_name & " Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work"));
writeline(output, buf);
ELSIF (m_hi /= "00000000") THEN
m_val_tmp := alt_conv_integer(m_hi) + alt_conv_integer(m_lo);
END IF;
-- N counter value
IF ((n_hi /= n_lo) AND (scan_data(36) /= '1')) THEN
reconfig_err <= TRUE;
WRITE(buf,string'("Warning : The N counter of the " & family_name & " Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work"));
writeline(output, buf);
ELSIF (n_hi /= "00000000") THEN
n_val <= alt_conv_integer(n_hi) + alt_conv_integer(n_lo);
END IF;
-- TODO : Give warnings/errors in the following cases?
-- 1. Illegal counter values (error)
-- 2. Change of mode (warning)
-- 3. Only 50% duty cycle allowed for M counter (odd mode - hi-lo=1,even - hi-lo=0)
END IF;
end if;
if (fbclk'event and fbclk = '1') then
m_val <= m_val_tmp;
end if;
if (update_conf_latches_reg = '1') then
if (scanclk_ipd'event and scanclk_ipd = '1') then
c0_rising_edge_transfer_done := true;
c_high_val(0) <= c_high_val_tmp(0);
c_mode_val(0) <= c_mode_val_tmp(0);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c1_rising_edge_transfer_done := true;
c_high_val(1) <= c_high_val_tmp(1);
c_mode_val(1) <= c_mode_val_tmp(1);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c2_rising_edge_transfer_done := true;
c_high_val(2) <= c_high_val_tmp(2);
c_mode_val(2) <= c_mode_val_tmp(2);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(3) <= c_high_val_tmp(3);
c_mode_val(3) <= c_mode_val_tmp(3);
c3_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(4) <= c_high_val_tmp(4);
c_mode_val(4) <= c_mode_val_tmp(4);
c4_rising_edge_transfer_done := true;
end if;
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c0_rising_edge_transfer_done) then
c_low_val(0) <= c_low_val_tmp(0);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c1_rising_edge_transfer_done) then
c_low_val(1) <= c_low_val_tmp(1);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c2_rising_edge_transfer_done) then
c_low_val(2) <= c_low_val_tmp(2);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c3_rising_edge_transfer_done) then
c_low_val(3) <= c_low_val_tmp(3);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c4_rising_edge_transfer_done) then
c_low_val(4) <= c_low_val_tmp(4);
end if;
if (update_phase = '1') then
if (vco_out(0)'event and vco_out(0) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 0) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 0) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(1)'event and vco_out(1) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 1) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 1) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(2)'event and vco_out(2) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 2) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 2) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(3)'event and vco_out(3) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 3) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 3) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(4)'event and vco_out(4) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 4) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 4) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(5)'event and vco_out(5) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 5) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 5) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(6)'event and vco_out(6) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 6) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 6) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(7)'event and vco_out(7) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 7) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 7) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
end if;
if (vco_out(0)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 0) then
inclk_c_from_vco(i) <= vco_out(0);
end if;
end loop;
if (m_ph_val = 0) then
inclk_m_from_vco <= vco_out(0);
end if;
end if;
if (vco_out(1)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 1) then
inclk_c_from_vco(i) <= vco_out(1);
end if;
end loop;
if (m_ph_val = 1) then
inclk_m_from_vco <= vco_out(1);
end if;
end if;
if (vco_out(2)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 2) then
inclk_c_from_vco(i) <= vco_out(2);
end if;
end loop;
if (m_ph_val = 2) then
inclk_m_from_vco <= vco_out(2);
end if;
end if;
if (vco_out(3)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 3) then
inclk_c_from_vco(i) <= vco_out(3);
end if;
end loop;
if (m_ph_val = 3) then
inclk_m_from_vco <= vco_out(3);
end if;
end if;
if (vco_out(4)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 4) then
inclk_c_from_vco(i) <= vco_out(4);
end if;
end loop;
if (m_ph_val = 4) then
inclk_m_from_vco <= vco_out(4);
end if;
end if;
if (vco_out(5)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 5) then
inclk_c_from_vco(i) <= vco_out(5);
end if;
end loop;
if (m_ph_val = 5) then
inclk_m_from_vco <= vco_out(5);
end if;
end if;
if (vco_out(6)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 6) then
inclk_c_from_vco(i) <= vco_out(6);
end if;
end loop;
if (m_ph_val = 6) then
inclk_m_from_vco <= vco_out(6);
end if;
end if;
if (vco_out(7)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 7) then
inclk_c_from_vco(i) <= vco_out(7);
end if;
end loop;
if (m_ph_val = 7) then
inclk_m_from_vco <= vco_out(7);
end if;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_scandata_scanclk,
TimingData => TimingData_scandata_scanclk,
TestSignal => scandata_ipd,
TestSignalName => "scandata",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scandata_scanclk_noedge_negedge,
SetupLow => tsetup_scandata_scanclk_noedge_negedge,
HoldHigh => thold_scandata_scanclk_noedge_negedge,
HoldLow => thold_scandata_scanclk_noedge_negedge,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/cycloneiii_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_scanclkena_scanclk,
TimingData => TimingData_scanclkena_scanclk,
TestSignal => scanclkena_ipd,
TestSignalName => "scanclkena",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scanclkena_scanclk_noedge_negedge,
SetupLow => tsetup_scanclkena_scanclk_noedge_negedge,
HoldHigh => thold_scanclkena_scanclk_noedge_negedge,
HoldLow => thold_scanclkena_scanclk_noedge_negedge,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/cycloneiii_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (scanclk_ipd'event AND scanclk_ipd = '0' AND now > 0 ps) then
scanclkena_reg <= scanclkena_ipd;
if (scanclkena_reg = '1') then
scandata_in <= scandata_ipd;
scandata_out <= scandataout_tmp;
end if;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1' and now > 0 ps) then
if (got_first_scanclk) then
scanclk_period <= now - scanclk_last_rising_edge;
else
got_first_scanclk := true;
end if;
if (scanclkena_reg = '1') then
for j in scan_chain_length - 1 downto 1 loop
scan_data(j) <= scan_data(j-1);
end loop;
scan_data(0) <= scandata_in;
end if;
scanclk_last_rising_edge := now;
end if;
end process;
-- PLL Phase Reconfiguration
PROCESS(scanclk_ipd, areset_ipd,phasestep_ipd)
VARIABLE i : INTEGER := 0;
VARIABLE c_ph : INTEGER := 0;
VARIABLE m_ph : INTEGER := 0;
VARIABLE select_counter : INTEGER := 0;
BEGIN
IF (NOW = 0 ps) THEN
m_ph_val_tmp <= m_ph_initial;
END IF;
-- Latch phase enable (same as phasestep) on neg edge of scan clock
IF (scanclk_ipd'EVENT AND scanclk_ipd = '0') THEN
phasestep_reg <= phasestep_ipd;
END IF;
IF (phasestep_ipd'EVENT and phasestep_ipd = '1') THEN
IF (update_phase = '0') THEN
phasestep_high_count <= 0; -- phase adjustments must be 1 cycle apart
-- if not, next phasestep cycle is skipped
END IF;
END IF;
-- revert counter phase tap values to POF programmed values
-- if PLL is reset
IF (areset_ipd'EVENT AND areset_ipd = '1') then
c_ph_val_tmp <= c_ph_val_orig;
m_ph_val_tmp <= m_ph_initial;
END IF;
IF (scanclk_ipd'EVENT AND scanclk_ipd = '1') THEN
IF (phasestep_reg = '1') THEN
IF (phasestep_high_count = 1) THEN
phasecounterselect_reg <= phasecounterselect_ipd;
phaseupdown_reg <= phaseupdown_ipd;
-- start reconfiguration
IF (phasecounterselect_ipd < "111") THEN -- no counters selected
IF (phasecounterselect_ipd = "000") THEN
WHILE (i < num_output_cntrs) LOOP
c_ph := c_ph_val(i);
IF (phaseupdown_ipd = '1') THEN
c_ph := (c_ph + 1) mod num_phase_taps;
ELSIF (c_ph = 0) THEN
c_ph := num_phase_taps - 1;
ELSE
c_ph := (c_ph - 1) mod num_phase_taps;
END IF;
c_ph_val_tmp(i) <= c_ph;
i := i + 1;
END LOOP;
ELSIF (phasecounterselect_ipd = "001") THEN
m_ph := m_ph_val;
IF (phaseupdown_ipd = '1') THEN
m_ph := (m_ph + 1) mod num_phase_taps;
ELSIF (m_ph = 0) THEN
m_ph := num_phase_taps - 1;
ELSE
m_ph := (m_ph - 1) mod num_phase_taps;
END IF;
m_ph_val_tmp <= m_ph;
ELSE
select_counter := alt_conv_integer(phasecounterselect_ipd) - 2;
c_ph := c_ph_val(select_counter);
IF (phaseupdown_ipd = '1') THEN
c_ph := (c_ph + 1) mod num_phase_taps;
ELSIF (c_ph = 0) THEN
c_ph := num_phase_taps - 1;
ELSE
c_ph := (c_ph - 1) mod num_phase_taps;
END IF;
c_ph_val_tmp(select_counter) <= c_ph;
END IF;
update_phase <= '1','0' AFTER (0.5 * scanclk_period);
END IF;
END IF;
phasestep_high_count <= phasestep_high_count + 1;
END IF;
END IF;
END PROCESS;
scandataout_tmp <= scan_data(SCAN_CHAIN - 2);
process (schedule_vco, areset_ipd, pfdena_ipd, refclk, fbclk)
variable sched_time : time := 0 ps;
TYPE time_array is ARRAY (0 to 7) of time;
variable init : boolean := true;
variable refclk_period : time;
variable m_times_vco_period : time;
variable new_m_times_vco_period : time;
variable phase_shift : time_array := (OTHERS => 0 ps);
variable last_phase_shift : time_array := (OTHERS => 0 ps);
variable l_index : integer := 1;
variable cycle_to_adjust : integer := 0;
variable stop_vco : boolean := false;
variable locked_tmp : std_logic := '0';
variable pll_is_locked : boolean := false;
variable cycles_pfd_low : integer := 0;
variable cycles_pfd_high : integer := 0;
variable cycles_to_lock : integer := 0;
variable cycles_to_unlock : integer := 0;
variable got_first_refclk : boolean := false;
variable got_second_refclk : boolean := false;
variable got_first_fbclk : boolean := false;
variable refclk_time : time := 0 ps;
variable fbclk_time : time := 0 ps;
variable first_fbclk_time : time := 0 ps;
variable fbclk_period : time := 0 ps;
variable first_schedule : boolean := true;
variable vco_val : std_logic := '0';
variable vco_period_was_phase_adjusted : boolean := false;
variable phase_adjust_was_scheduled : boolean := false;
variable loop_xplier : integer;
variable loop_initial : integer := 0;
variable loop_ph : integer := 0;
variable loop_time_delay : integer := 0;
variable initial_delay : time := 0 ps;
variable vco_per : time;
variable tmp_rem : integer;
variable my_rem : integer;
variable fbk_phase : integer := 0;
variable pull_back_M : integer := 0;
variable total_pull_back : integer := 0;
variable fbk_delay : integer := 0;
variable offset : time := 0 ps;
variable tmp_vco_per : integer := 0;
variable high_time : time;
variable low_time : time;
variable got_refclk_posedge : boolean := false;
variable got_fbclk_posedge : boolean := false;
variable inclk_out_of_range : boolean := false;
variable no_warn : boolean := false;
variable ext_fbk_cntr_modulus : integer := 1;
variable init_clks : boolean := true;
variable pll_is_in_reset : boolean := false;
variable buf : line;
begin
if (init) then
-- jump-start the VCO
-- add 1 ps delay to ensure all signals are updated to initial
-- values
schedule_vco <= transport not schedule_vco after 1 ps;
init := false;
end if;
if (schedule_vco'event) then
if (init_clks) then
refclk_period := inclk0_input_frequency * n_val * 1 ps;
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
init_clks := false;
end if;
sched_time := 0 ps;
for i in 0 to 7 loop
last_phase_shift(i) := phase_shift(i);
end loop;
cycle_to_adjust := 0;
l_index := 1;
m_times_vco_period := new_m_times_vco_period;
end if;
-- areset was asserted
if (areset_ipd'event and areset_ipd = '1') then
assert false report family_name & " PLL was reset" severity note;
-- reset lock parameters
pll_is_locked := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
end if;
if (schedule_vco'event and (areset_ipd = '1' or stop_vco)) then
if (areset_ipd = '1') then
pll_is_in_reset := true;
end if;
-- drop VCO taps to 0
for i in 0 to 7 loop
vco_out(i) <= transport '0' after last_phase_shift(i);
phase_shift(i) := 0 ps;
last_phase_shift(i) := 0 ps;
end loop;
-- reset lock parameters
pll_is_locked := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
got_first_refclk := false;
got_second_refclk := false;
refclk_time := 0 ps;
got_first_fbclk := false;
fbclk_time := 0 ps;
first_fbclk_time := 0 ps;
fbclk_period := 0 ps;
first_schedule := true;
vco_val := '0';
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
elsif ((schedule_vco'event or areset_ipd'event) and areset_ipd = '0' and (not stop_vco) and now > 0 ps) then
-- note areset deassert time
-- note it as refclk_time to prevent false triggering
-- of stop_vco after areset
if (areset_ipd'event and areset_ipd = '0' and pll_is_in_reset) then
refclk_time := now;
pll_is_in_reset := false;
locked_tmp := '0';
end if;
-- calculate loop_xplier : this will be different from m_val
-- in external_feedback_mode
loop_xplier := m_val;
loop_initial := m_initial_val - 1;
loop_ph := m_ph_val;
-- convert initial value to delay
initial_delay := (loop_initial * m_times_vco_period)/loop_xplier;
-- convert loop ph_tap to delay
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
tmp_vco_per := (m_times_vco_period/1 ps) / loop_xplier;
if (my_rem /= 0) then
tmp_vco_per := tmp_vco_per + 1;
end if;
fbk_phase := (loop_ph * tmp_vco_per)/8;
pull_back_M := initial_delay/1 ps + fbk_phase;
total_pull_back := pull_back_M;
if (simulation_type = "timing") then
total_pull_back := total_pull_back + pll_compensation_delay;
end if;
while (total_pull_back > refclk_period/1 ps) loop
total_pull_back := total_pull_back - refclk_period/1 ps;
end loop;
if (total_pull_back > 0) then
offset := refclk_period - (total_pull_back * 1 ps);
end if;
fbk_delay := total_pull_back - fbk_phase;
if (fbk_delay < 0) then
offset := offset - (fbk_phase * 1 ps);
fbk_delay := total_pull_back;
end if;
-- assign m_delay
m_delay <= transport fbk_delay after 1 ps;
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
for i in 1 to loop_xplier loop
-- adjust cycles
tmp_vco_per := (m_times_vco_period/1 ps)/loop_xplier;
if (my_rem /= 0 and l_index <= my_rem) then
tmp_rem := (loop_xplier * l_index) rem my_rem;
cycle_to_adjust := (loop_xplier * l_index) / my_rem;
if (tmp_rem /= 0) then
cycle_to_adjust := cycle_to_adjust + 1;
end if;
end if;
if (cycle_to_adjust = i) then
tmp_vco_per := tmp_vco_per + 1;
l_index := l_index + 1;
end if;
-- calculate high and low periods
vco_per := tmp_vco_per * 1 ps;
high_time := (tmp_vco_per/2) * 1 ps;
if (tmp_vco_per rem 2 /= 0) then
high_time := high_time + 1 ps;
end if;
low_time := vco_per - high_time;
-- schedule the rising and falling edges
for j in 1 to 2 loop
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule the phase taps
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
if (first_schedule) then
vco_out(k) <= transport vco_val after (sched_time + phase_shift(k));
else
vco_out(k) <= transport vco_val after (sched_time + last_phase_shift(k));
end if;
end loop;
end loop;
end loop;
-- schedule once more
if (first_schedule) then
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule the phase taps
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
vco_out(k) <= transport vco_val after (sched_time + phase_shift(k));
end loop;
first_schedule := false;
end if;
schedule_vco <= transport not schedule_vco after sched_time;
if (vco_period_was_phase_adjusted) then
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := true;
vco_per := m_times_vco_period/loop_xplier;
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
end loop;
end if;
end if;
-- Bypass lock detect
if (refclk'event and refclk = '1' and areset_ipd = '0') then
if (test_bypass_lock_detect = "on") then
if (pfdena_ipd = '1') then
cycles_pfd_low := 0;
if (pfd_locked = '0') then
if (cycles_pfd_high = lock_high) then
assert false report family_name & " PLL locked in test mode on PFD enable assertion.";
pfd_locked <= '1';
end if;
cycles_pfd_high := cycles_pfd_high + 1;
end if;
end if;
if (pfdena_ipd = '0') then
cycles_pfd_high := 0;
if (pfd_locked = '1') then
if (cycles_pfd_low = lock_low) then
assert false report family_name & " PLL lost lock in test mode on PFD enable de-assertion.";
pfd_locked <= '0';
end if;
cycles_pfd_low := cycles_pfd_low + 1;
end if;
end if;
end if;
if (refclk'event and refclk = '1' and areset_ipd = '0') then
got_refclk_posedge := true;
if (not got_first_refclk) then
got_first_refclk := true;
else
got_second_refclk := true;
refclk_period := now - refclk_time;
-- check if incoming freq. will cause VCO range to be
-- exceeded
if ( (vco_max /= 0 and vco_min /= 0 and pfdena_ipd = '1') and
(((refclk_period/1 ps)/loop_xplier > vco_max) or
((refclk_period/1 ps)/loop_xplier < vco_min)) ) then
if (pll_is_locked) then
if ((refclk_period/1 ps)/loop_xplier > vco_max) then
assert false report "Input clock freq. is over VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_over <= '1';
end if;
if ((refclk_period/1 ps)/loop_xplier < vco_min) then
assert false report "Input clock freq. is under VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_under <= '1';
end if;
if (inclk_out_of_range) then
pll_is_locked := false;
locked_tmp := '0';
cycles_to_lock := 0;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
assert false report family_name & " PLL lost lock." severity note;
end if;
elsif (not no_warn) then
if ((refclk_period/1 ps)/loop_xplier > vco_max) then
assert false report "Input clock freq. is over VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_over <= '1';
end if;
if ((refclk_period/1 ps)/loop_xplier < vco_min) then
assert false report "Input clock freq. is under VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_under <= '1';
end if;
assert false report " Input clock freq. is not within VCO range : " & family_name & " PLL may not lock. Please use the correct frequency." severity warning;
no_warn := true;
end if;
inclk_out_of_range := true;
else
vco_over <= '0';
vco_under <= '0';
inclk_out_of_range := false;
end if;
end if;
end if;
if (stop_vco) then
stop_vco := false;
schedule_vco <= not schedule_vco;
end if;
refclk_time := now;
else
got_refclk_posedge := false;
end if;
-- Update M counter value on feedback clock edge
if (fbclk'event and fbclk = '1') then
got_fbclk_posedge := true;
if (not got_first_fbclk) then
got_first_fbclk := true;
else
fbclk_period := now - fbclk_time;
end if;
-- need refclk_period here, so initialized to proper value above
if ( ( (now - refclk_time > 1.5 * refclk_period) and pfdena_ipd = '1' and pll_is_locked) or ( (now - refclk_time > 5 * refclk_period) and pfdena_ipd = '1') ) then
stop_vco := true;
-- reset
got_first_refclk := false;
got_first_fbclk := false;
got_second_refclk := false;
if (pll_is_locked) then
pll_is_locked := false;
locked_tmp := '0';
assert false report family_name & " PLL lost lock due to loss of input clock" severity note;
end if;
cycles_to_lock := 0;
cycles_to_unlock := 0;
first_schedule := true;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
end if;
fbclk_time := now;
else
got_fbclk_posedge := false;
end if;
if ((got_refclk_posedge or got_fbclk_posedge) and got_second_refclk and pfdena_ipd = '1' and (not inclk_out_of_range)) then
-- now we know actual incoming period
if ( abs(fbclk_time - refclk_time) <= 5 ps or
(got_first_fbclk and abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5 ps)) then
-- considered in phase
if (cycles_to_lock = real_lock_high) then
if (not pll_is_locked) then
assert false report family_name & " PLL locked to incoming clock" severity note;
end if;
pll_is_locked := true;
locked_tmp := '1';
cycles_to_unlock := 0;
end if;
-- increment lock counter only if second part of above
-- time check is NOT true
if (not(abs(refclk_period - abs(fbclk_time - refclk_time)) <= lock_window)) then
cycles_to_lock := cycles_to_lock + 1;
end if;
-- adjust m_times_vco_period
new_m_times_vco_period := refclk_period;
else
-- if locked, begin unlock
if (pll_is_locked) then
cycles_to_unlock := cycles_to_unlock + 1;
if (cycles_to_unlock = lock_low) then
pll_is_locked := false;
locked_tmp := '0';
cycles_to_lock := 0;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
assert false report family_name & " PLL lost lock." severity note;
end if;
end if;
if ( abs(refclk_period - fbclk_period) <= 2 ps ) then
-- frequency is still good
if (now = fbclk_time and (not phase_adjust_was_scheduled)) then
if ( abs(fbclk_time - refclk_time) > refclk_period/2) then
new_m_times_vco_period := m_times_vco_period + (refclk_period - abs(fbclk_time - refclk_time));
vco_period_was_phase_adjusted := true;
else
new_m_times_vco_period := m_times_vco_period - abs(fbclk_time - refclk_time);
vco_period_was_phase_adjusted := true;
end if;
end if;
else
phase_adjust_was_scheduled := false;
new_m_times_vco_period := refclk_period;
end if;
end if;
end if;
if (pfdena_ipd = '0') then
if (pll_is_locked) then
locked_tmp := 'X';
end if;
pll_is_locked := false;
cycles_to_lock := 0;
end if;
-- give message only at time of deassertion
if (pfdena_ipd'event and pfdena_ipd = '0') then
assert false report "PFDENA deasserted." severity note;
elsif (pfdena_ipd'event and pfdena_ipd = '1') then
got_first_refclk := false;
got_second_refclk := false;
refclk_time := now;
end if;
if (reconfig_err) then
lock <= '0';
else
lock <= locked_tmp;
end if;
-- signal to calculate quiet_time
sig_refclk_period <= refclk_period;
if (stop_vco = true) then
sig_stop_vco <= '1';
else
sig_stop_vco <= '0';
end if;
pll_locked <= pll_is_locked;
end process;
clk0_tmp <= c_clk(i_clk0_counter);
clk_pfd(0) <= clk0_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(0) <= clk_pfd(0) WHEN (test_bypass_lock_detect = "on") ELSE
clk0_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else
'X';
clk1_tmp <= c_clk(i_clk1_counter);
clk_pfd(1) <= clk1_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(1) <= clk_pfd(1) WHEN (test_bypass_lock_detect = "on") ELSE
clk1_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk2_tmp <= c_clk(i_clk2_counter);
clk_pfd(2) <= clk2_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(2) <= clk_pfd(2) WHEN (test_bypass_lock_detect = "on") ELSE
clk2_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk3_tmp <= c_clk(i_clk3_counter);
clk_pfd(3) <= clk3_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(3) <= clk_pfd(3) WHEN (test_bypass_lock_detect = "on") ELSE
clk3_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk4_tmp <= c_clk(i_clk4_counter);
clk_pfd(4) <= clk4_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(4) <= clk_pfd(4) WHEN (test_bypass_lock_detect = "on") ELSE
clk4_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
scandataout <= scandata_out;
scandone <= NOT scandone_tmp;
phasedone <= NOT update_phase;
end vital_pll;
-- END ARCHITECTURE VITAL_PLL
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_ff
--
-- Description : Cyclone III FF VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
use work.cycloneiii_and1;
entity cycloneiii_ff is
generic (
power_up : string := "low";
x_on_violation : string := "on";
lpm_type : string := "cycloneiii_ff";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
clrn : in std_logic := '1';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
asdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_ff : entity is TRUE;
end cycloneiii_ff;
architecture vital_lcell_ff of cycloneiii_ff is
attribute VITAL_LEVEL0 of vital_lcell_ff : architecture is TRUE;
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal d_dly : std_logic;
signal asdata_ipd : std_logic;
signal asdata_dly : std_logic;
signal asdata_dly1 : std_logic;
signal sclr_ipd : std_logic;
signal sload_ipd : std_logic;
signal clrn_ipd : std_logic;
signal aload_ipd : std_logic;
signal ena_ipd : std_logic;
component cycloneiii_and1
generic (XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01
);
port (Y : out STD_LOGIC;
IN1 : in STD_LOGIC
);
end component;
begin
ddelaybuffer: cycloneiii_and1
port map(IN1 => d_ipd,
Y => d_dly);
asdatadelaybuffer: cycloneiii_and1
port map(IN1 => asdata_ipd,
Y => asdata_dly);
asdatadelaybuffer1: cycloneiii_and1
port map(IN1 => asdata_dly,
Y => asdata_dly1);
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (asdata_ipd, asdata, tipd_asdata);
VitalWireDelay (sclr_ipd, sclr, tipd_sclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
VitalWireDelay (clrn_ipd, clrn, tipd_clrn);
VitalWireDelay (aload_ipd, aload, tipd_aload);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process (clk_ipd, d_dly, asdata_dly1,
sclr_ipd, sload_ipd, clrn_ipd, aload_ipd,
ena_ipd, devclrn, devpor)
variable Tviol_d_clk : std_ulogic := '0';
variable Tviol_asdata_clk : std_ulogic := '0';
variable Tviol_sclr_clk : std_ulogic := '0';
variable Tviol_sload_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_asdata_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sclr_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable iq : std_logic := '0';
variable idata: std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
if (now = 0 ns) then
if (power_up = "low") then
iq := '0';
elsif (power_up = "high") then
iq := '1';
end if;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(sload_ipd) OR
(sclr_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_asdata_clk,
TimingData => TimingData_asdata_clk,
TestSignal => asdata_ipd,
TestSignalName => "ASDATA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_asdata_clk_noedge_posedge,
SetupLow => tsetup_asdata_clk_noedge_posedge,
HoldHigh => thold_asdata_clk_noedge_posedge,
HoldLow => thold_asdata_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT sload_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sclr_clk,
TimingData => TimingData_sclr_clk,
TestSignal => sclr_ipd,
TestSignalName => "SCLR",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sclr_clk_noedge_posedge,
SetupLow => tsetup_sclr_clk_noedge_posedge,
HoldHigh => thold_sclr_clk_noedge_posedge,
HoldLow => thold_sclr_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
violation := Tviol_d_clk or Tviol_asdata_clk or
Tviol_sclr_clk or Tviol_sload_clk or Tviol_ena_clk;
if ((devpor = '0') or (devclrn = '0') or (clrn_ipd = '1')) then
iq := '0';
elsif (aload_ipd = '1') then
iq := asdata_dly1;
elsif (violation = 'X' and x_on_violation = "on") then
iq := 'X';
elsif clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' then
if (ena_ipd = '1') then
if (sclr_ipd = '1') then
iq := '0';
elsif (sload_ipd = '1') then
iq := asdata_dly1;
else
iq := d_dly;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => iq,
Paths => (0 => (clrn_ipd'last_event, tpd_clrn_q_posedge, TRUE),
1 => (aload_ipd'last_event, tpd_aload_q_posedge, TRUE),
2 => (asdata_ipd'last_event, tpd_asdata_q, TRUE),
3 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_ff;
----------------------------------------------------------------------------
-- Module Name : cycloneiii_ram_register
-- Description : Register module for RAM inputs/outputs
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_ram_register IS
GENERIC (
width : INTEGER := 1;
preset : STD_LOGIC := '0';
tipd_d : VitalDelayArrayType01(143 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_stall : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpw_ena_posedge : VitalDelayType := DefPulseWdthCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
stall : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END cycloneiii_ram_register;
ARCHITECTURE reg_arch OF cycloneiii_ram_register IS
SIGNAL d_ipd : STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
SIGNAL clk_ipd : STD_LOGIC;
SIGNAL ena_ipd : STD_LOGIC;
SIGNAL aclr_ipd : STD_LOGIC;
SIGNAL stall_ipd : STD_LOGIC;
BEGIN
WireDelay : BLOCK
BEGIN
loopbits : FOR i in d'RANGE GENERATE
VitalWireDelay (d_ipd(i), d(i), tipd_d(i));
END GENERATE;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (stall_ipd, stall, tipd_stall);
END BLOCK;
-- REMCYCLONEIII PROCESS (d_ipd,ena_ipd,clk_ipd,aclr_ipd,devclrn,devpor)
PROCESS (d_ipd,ena_ipd,stall_ipd,clk_ipd,aclr_ipd,devclrn,devpor)
VARIABLE Tviol_clk_ena : STD_ULOGIC := '0';
VARIABLE Tviol_clk_aclr : STD_ULOGIC := '0';
VARIABLE Tviol_data_clk : STD_ULOGIC := '0';
VARIABLE TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_stall : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_aclr : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
VARIABLE Tviol_ena : STD_ULOGIC := '0';
VARIABLE PeriodData_ena : VitalPeriodDataType := VitalPeriodDataInit;
VARIABLE q_VitalGlitchDataArray : VitalGlitchDataArrayType(143 downto 0);
VARIABLE CQDelay : TIME := 0 ns;
VARIABLE q_reg : STD_LOGIC_VECTOR(width - 1 DOWNTO 0) := (OTHERS => preset);
BEGIN
IF (aclr_ipd = '1' OR devclrn = '0' OR devpor = '0') THEN
q_reg := (OTHERS => preset);
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1' AND stall_ipd = '0') THEN
q_reg := d_ipd;
END IF;
-- Timing checks
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_stall,
TestSignal => stall_ipd,
TestSignalName => "stall",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_stall_clk_noedge_posedge,
SetupLow => tsetup_stall_clk_noedge_posedge,
HoldHigh => thold_stall_clk_noedge_posedge,
HoldLow => thold_stall_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_aclr,
TimingData => TimingData_clk_aclr,
TestSignal => aclr_ipd,
TestSignalName => "aclr",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_aclr_clk_noedge_posedge,
SetupLow => tsetup_aclr_clk_noedge_posedge,
HoldHigh => thold_aclr_clk_noedge_posedge,
HoldLow => thold_aclr_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_data_clk,
TimingData => TimingData_data_clk,
TestSignal => d_ipd,
TestSignalName => "data",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalPeriodPulseCheck (
Violation => Tviol_ena,
PeriodData => PeriodData_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
PulseWidthHigh => tpw_ena_posedge,
HeaderMsg => "/RAM Register VitalPeriodPulseCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
-- Path Delay Selection
CQDelay := SelectDelay (
Paths => (
(0 => (clk_ipd'LAST_EVENT,tpd_clk_q_posedge,TRUE),
1 => (aclr_ipd'LAST_EVENT,tpd_aclr_q_posedge,TRUE))
)
);
q <= TRANSPORT q_reg AFTER CQDelay;
END PROCESS;
aclrout <= aclr_ipd;
END reg_arch;
----------------------------------------------------------------------------
-- Module Name : cycloneiii_ram_pulse_generator
-- Description : Generate pulse to initiate memory read/write operations
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_ram_pulse_generator IS
GENERIC (
tipd_clk : VitalDelayType01 := (0.5 ns,0.5 ns);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tpd_clk_pulse_posedge : VitalDelayType01 := DefPropDelay01
);
PORT (
clk,ena : IN STD_LOGIC;
delaywrite : IN STD_LOGIC := '0';
pulse,cycle : OUT STD_LOGIC
);
ATTRIBUTE VITAL_Level0 OF cycloneiii_ram_pulse_generator:ENTITY IS TRUE;
END cycloneiii_ram_pulse_generator;
ARCHITECTURE pgen_arch OF cycloneiii_ram_pulse_generator IS
ATTRIBUTE VITAL_Level0 OF pgen_arch:ARCHITECTURE IS TRUE;
SIGNAL clk_ipd,ena_ipd : STD_LOGIC;
SIGNAL state : STD_LOGIC;
BEGIN
WireDelay : BLOCK
BEGIN
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
END BLOCK;
PROCESS (clk_ipd,state)
BEGIN
IF (state = '1' AND state'EVENT) THEN
state <= '0';
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1') THEN
IF (delaywrite = '1') THEN
state <= '1' AFTER 1 NS; -- delayed write
ELSE
state <= '1';
END IF;
END IF;
END PROCESS;
PathDelay : PROCESS
VARIABLE pulse_VitalGlitchData : VitalGlitchDataType;
BEGIN
WAIT UNTIL state'EVENT;
VitalPathDelay01 (
OutSignal => pulse,
OutSignalName => "pulse",
OutTemp => state,
Paths => (0 => (clk_ipd'LAST_EVENT,tpd_clk_pulse_posedge,TRUE)),
GlitchData => pulse_VitalGlitchData,
Mode => DefGlitchMode,
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks
);
END PROCESS;
cycle <= clk_ipd;
END pgen_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.cycloneiii_atom_pack.all;
USE work.cycloneiii_ram_register;
USE work.cycloneiii_ram_pulse_generator;
ENTITY cycloneiii_ram_block IS
GENERIC (
-- -------- GLOBAL PARAMETERS ---------
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
port_a_address_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_read_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_address_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_write_enable_clock: STRING := "clock1";
port_b_read_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
port_a_read_during_write_mode : STRING := "new_data_no_nbe_read";
port_b_read_during_write_mode : STRING := "new_data_no_nbe_read";
power_up_uninitialized : STRING := "false";
port_b_byte_size : INTEGER := 0;
port_a_byte_size : INTEGER := 0;
safe_write : STRING := "err_on_2clk";
init_file_restructured : STRING := "unused";
lpm_type : string := "cycloneiii_ram_block";
lpm_hint : string := "true";
clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_output_clock_enable : STRING := "none"; -- ena0,none
clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_output_clock_enable : STRING := "none"; -- ena1,none
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
mem_init2 : BIT_VECTOR := X"0";
mem_init3 : BIT_VECTOR := X"0";
mem_init4 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
-- -------- PORT DECLARATIONS ---------
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portare : IN STD_LOGIC := '1';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbwe : IN STD_LOGIC := '0';
portbre : IN STD_LOGIC := '1';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
ena2 : IN STD_LOGIC := '1';
ena3 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portaaddrstall : IN STD_LOGIC := '0';
portbaddrstall : IN STD_LOGIC := '0';
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END cycloneiii_ram_block;
ARCHITECTURE block_arch OF cycloneiii_ram_block IS
COMPONENT cycloneiii_ram_pulse_generator
PORT (
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
delaywrite : IN STD_LOGIC := '0';
pulse : OUT STD_LOGIC;
cycle : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT cycloneiii_ram_register
GENERIC (
preset : STD_LOGIC := '0';
width : integer := 1
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
ena : IN STD_LOGIC;
stall : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END COMPONENT;
FUNCTION cond (condition : BOOLEAN;CONSTANT a,b : INTEGER) RETURN INTEGER IS
VARIABLE c: INTEGER;
BEGIN
IF (condition) THEN c := a; ELSE c := b; END IF;
RETURN c;
END;
SUBTYPE port_type IS BOOLEAN;
CONSTANT primary : port_type := TRUE;
CONSTANT secondary : port_type := FALSE;
CONSTANT primary_port_is_a : BOOLEAN := (port_b_data_width <= port_a_data_width);
CONSTANT primary_port_is_b : BOOLEAN := NOT primary_port_is_a;
CONSTANT mode_is_rom : BOOLEAN := (operation_mode = "rom");
CONSTANT mode_is_sp : BOOLEAN := (operation_mode = "single_port");
CONSTANT mode_is_dp : BOOLEAN := (operation_mode = "dual_port");
CONSTANT mode_is_bdp : BOOLEAN := (operation_mode = "bidir_dual_port");
CONSTANT wired_mode : BOOLEAN := (port_a_address_width = port_b_address_width) AND (port_a_address_width = 1)
AND (port_a_data_width /= port_b_data_width);
CONSTANT num_cols : INTEGER := cond(mode_is_rom OR mode_is_sp,1,
cond(wired_mode,2,2 ** (ABS(port_b_address_width - port_a_address_width))));
CONSTANT data_width : INTEGER := cond(primary_port_is_a,port_a_data_width,port_b_data_width);
CONSTANT data_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_data_width,port_b_data_width);
CONSTANT address_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_a,port_a_address_width,port_b_address_width);
CONSTANT address_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_address_width,port_b_address_width);
CONSTANT byte_size_a : INTEGER := port_a_data_width / port_a_byte_enable_mask_width;
CONSTANT byte_size_b : INTEGER := port_b_data_width / port_b_byte_enable_mask_width;
CONSTANT out_a_is_reg : BOOLEAN := (port_a_data_out_clock /= "none" AND port_a_data_out_clock /= "UNUSED");
CONSTANT out_b_is_reg : BOOLEAN := (port_b_data_out_clock /= "none" AND port_b_data_out_clock /= "UNUSED");
CONSTANT bytes_a_disabled : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT bytes_b_disabled : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT ram_type : BOOLEAN := FALSE;
TYPE bool_to_std_logic_map IS ARRAY(TRUE DOWNTO FALSE) OF STD_LOGIC;
CONSTANT bool_to_std_logic : bool_to_std_logic_map := ('1','0');
-- Hardware write modes
CONSTANT dual_clock : BOOLEAN := (operation_mode = "dual_port" OR
operation_mode = "bidir_dual_port") AND
(port_b_address_clock = "clock1");
CONSTANT both_new_data_same_port : BOOLEAN := (
((port_a_read_during_write_mode = "new_data_no_nbe_read") OR
(port_a_read_during_write_mode = "dont_care")) AND
((port_b_read_during_write_mode = "new_data_no_nbe_read") OR
(port_b_read_during_write_mode = "dont_care"))
);
SIGNAL hw_write_mode_a : STRING(3 DOWNTO 1);
SIGNAL hw_write_mode_b : STRING(3 DOWNTO 1);
SIGNAL delay_write_pulse_a : STD_LOGIC ;
SIGNAL delay_write_pulse_b : STD_LOGIC ;
CONSTANT be_mask_write_a : BOOLEAN := (port_a_read_during_write_mode = "new_data_with_nbe_read");
CONSTANT be_mask_write_b : BOOLEAN := (port_b_read_during_write_mode = "new_data_with_nbe_read");
CONSTANT old_data_write_a : BOOLEAN := (port_a_read_during_write_mode = "old_data");
CONSTANT old_data_write_b : BOOLEAN := (port_b_read_during_write_mode = "old_data");
SIGNAL read_before_write_a : BOOLEAN;
SIGNAL read_before_write_b : BOOLEAN;
-- -------- internal signals ---------
-- clock / clock enable
SIGNAL clk_a_in,clk_b_in : STD_LOGIC;
SIGNAL clk_a_byteena,clk_b_byteena : STD_LOGIC;
SIGNAL clk_a_out,clk_b_out : STD_LOGIC;
SIGNAL clkena_a_out,clkena_b_out : STD_LOGIC;
SIGNAL clkena_out_c0, clkena_out_c1 : STD_LOGIC;
SIGNAL write_cycle_a,write_cycle_b : STD_LOGIC;
SIGNAL clk_a_rena, clk_a_wena : STD_LOGIC;
SIGNAL clk_a_core : STD_LOGIC;
SIGNAL clk_b_rena, clk_b_wena : STD_LOGIC;
SIGNAL clk_b_core : STD_LOGIC;
SUBTYPE one_bit_bus_type IS STD_LOGIC_VECTOR(0 DOWNTO 0);
-- asynch clear
TYPE clear_mode_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
TYPE clear_vec_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL datain_a_clr,datain_b_clr : STD_LOGIC;
SIGNAL dataout_a_clr,dataout_b_clr : STD_LOGIC;
SIGNAL dataout_a_clr_reg, dataout_b_clr_reg : STD_LOGIC;
SIGNAL dataout_a_clr_reg_in, dataout_b_clr_reg_in : one_bit_bus_type;
SIGNAL dataout_a_clr_reg_out, dataout_b_clr_reg_out : one_bit_bus_type;
SIGNAL dataout_a_clr_reg_latch, dataout_b_clr_reg_latch : STD_LOGIC;
SIGNAL dataout_a_clr_reg_latch_in, dataout_b_clr_reg_latch_in : one_bit_bus_type;
SIGNAL dataout_a_clr_reg_latch_out, dataout_b_clr_reg_latch_out : one_bit_bus_type;
SIGNAL addr_a_clr,addr_b_clr : STD_LOGIC;
SIGNAL byteena_a_clr,byteena_b_clr : STD_LOGIC;
SIGNAL we_a_clr,re_a_clr,we_b_clr,re_b_clr : STD_LOGIC;
SIGNAL datain_a_clr_in,datain_b_clr_in : STD_LOGIC;
SIGNAL addr_a_clr_in,addr_b_clr_in : STD_LOGIC;
SIGNAL byteena_a_clr_in,byteena_b_clr_in : STD_LOGIC;
SIGNAL we_a_clr_in,re_a_clr_in,we_b_clr_in,re_b_clr_in : STD_LOGIC;
SIGNAL mem_invalidate,mem_invalidate_loc,read_latch_invalidate : clear_mode_type;
SIGNAL clear_asserted_during_write : clear_vec_type;
-- port A registers
SIGNAL we_a_reg : STD_LOGIC;
SIGNAL re_a_reg : STD_LOGIC;
SIGNAL we_a_reg_in,we_a_reg_out : one_bit_bus_type;
SIGNAL re_a_reg_in,re_a_reg_out : one_bit_bus_type;
SIGNAL addr_a_reg : STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0);
SIGNAL datain_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL byteena_a_reg : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width- 1 DOWNTO 0);
-- port B registers
SIGNAL we_b_reg, re_b_reg : STD_LOGIC;
SIGNAL re_b_reg_in,re_b_reg_out,we_b_reg_in,we_b_reg_out : one_bit_bus_type;
SIGNAL addr_b_reg : STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0);
SIGNAL datain_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL byteena_b_reg : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width- 1 DOWNTO 0);
-- pulses
TYPE pulse_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL write_pulse,read_pulse,read_pulse_feedthru : pulse_vec;
SIGNAL rw_pulse : pulse_vec;
SIGNAL wpgen_a_clk,wpgen_a_clkena,wpgen_b_clk,wpgen_b_clkena : STD_LOGIC;
SIGNAL rpgen_a_clkena,rpgen_b_clkena : STD_LOGIC;
SIGNAL ftpgen_a_clkena,ftpgen_b_clkena : STD_LOGIC;
SIGNAL rwpgen_a_clkena,rwpgen_b_clkena : STD_LOGIC;
-- registered address
SIGNAL addr_prime_reg,addr_sec_reg : INTEGER;
-- input/output
SIGNAL datain_prime_reg,dataout_prime : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
SIGNAL datain_sec_reg,dataout_sec : STD_LOGIC_VECTOR(data_unit_width - 1 DOWNTO 0);
-- overlapping location write
SIGNAL dual_write : BOOLEAN;
-- byte enable mask write
TYPE be_mask_write_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
SIGNAL be_mask_write : be_mask_write_vec;
-- memory core
SUBTYPE mem_word_type IS STD_LOGIC_VECTOR (data_width - 1 DOWNTO 0);
SUBTYPE mem_col_type IS STD_LOGIC_VECTOR (data_unit_width - 1 DOWNTO 0);
TYPE mem_row_type IS ARRAY (num_cols - 1 DOWNTO 0) OF mem_col_type;
TYPE mem_type IS ARRAY ((2 ** address_unit_width) - 1 DOWNTO 0) OF mem_row_type;
SIGNAL mem : mem_type;
SIGNAL init_mem : BOOLEAN := FALSE;
CONSTANT mem_x : mem_type := (OTHERS => (OTHERS => (OTHERS => 'X')));
CONSTANT row_x : mem_row_type := (OTHERS => (OTHERS => 'X'));
CONSTANT col_x : mem_col_type := (OTHERS => 'X');
SIGNAL mem_data : mem_row_type;
SIGNAL mem_unit_data : mem_col_type;
-- latches
TYPE read_latch_rec IS RECORD
prime : mem_row_type;
sec : mem_col_type;
END RECORD;
SIGNAL read_latch : read_latch_rec;
-- (row,column) coordinates
SIGNAL row_sec,col_sec : INTEGER;
-- byte enable
TYPE mask_type IS (normal,inverse);
TYPE mask_prime_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_word_type;
TYPE mask_sec_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_col_type;
TYPE mask_rec IS RECORD
prime : mask_prime_type;
sec : mask_sec_type;
END RECORD;
SIGNAL mask_vector : mask_rec;
SIGNAL mask_vector_common : mem_col_type;
FUNCTION get_mask(
b_ena : IN STD_LOGIC_VECTOR;
mode : port_type;
CONSTANT b_ena_width ,byte_size: INTEGER
) RETURN mask_rec IS
VARIABLE l : INTEGER;
VARIABLE mask : mask_rec := (
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X')),
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X'))
);
BEGIN
FOR l in 0 TO b_ena_width - 1 LOOP
IF (b_ena(l) = '0') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.prime(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.sec(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
END IF;
ELSIF (b_ena(l) = 'X' OR b_ena(l) = 'U') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
END IF;
END IF;
END LOOP;
RETURN mask;
END get_mask;
-- port active for read/write
SIGNAL active_a_core_in_vec,active_b_core_in_vec,active_a_core_out,active_b_core_out : one_bit_bus_type;
SIGNAL active_a_in,active_b_in : STD_LOGIC;
SIGNAL active_write_a : BOOLEAN;
SIGNAL active_write_b : BOOLEAN;
SIGNAL active_b_in_c0,active_b_core_in_c0,active_b_in_c1,active_b_core_in_c1 : STD_LOGIC;
SIGNAL active_a_core_in,active_b_core_in : STD_LOGIC;
SIGNAL active_a_core, active_b_core : BOOLEAN;
SIGNAL wire_vcc : STD_LOGIC := '1';
SIGNAL wire_gnd : STD_LOGIC := '0';
BEGIN
-- memory initialization
init_mem <= TRUE;
-- hardware write modes
hw_write_mode_a <= "R+W" WHEN ((port_a_read_during_write_mode = "old_data") OR
(port_a_read_during_write_mode = "new_data_with_nbe_read")) ELSE
" FW" WHEN (dual_clock OR (
mixed_port_feed_through_mode = "dont_care" AND
both_new_data_same_port
)) ELSE
" DW";
hw_write_mode_b <= "R+W" WHEN ((port_b_read_during_write_mode = "old_data") OR
(port_b_read_during_write_mode = "new_data_with_nbe_read")) ELSE
" FW" WHEN (dual_clock OR (
mixed_port_feed_through_mode = "dont_care" AND
both_new_data_same_port
)) ELSE
" DW";
delay_write_pulse_a <= '1' WHEN (hw_write_mode_a /= " FW") ELSE '0';
delay_write_pulse_b <= '1' WHEN (hw_write_mode_b /= " FW") ELSE '0' ;
read_before_write_a <= (hw_write_mode_a = "R+W");
read_before_write_b <= (hw_write_mode_b = "R+W");
-- -------- core logic ---------------
clk_a_in <= clk0;
clk_a_wena <= '0' WHEN (port_a_write_enable_clock = "none") ELSE clk_a_in;
clk_a_rena <= '0' WHEN (port_a_read_enable_clock = "none") ELSE clk_a_in;
clk_a_byteena <= '0' WHEN (port_a_byte_enable_clock = "none" OR port_a_byte_enable_clock = "UNUSED") ELSE clk_a_in;
clk_a_out <= '0' WHEN (port_a_data_out_clock = "none" OR port_a_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_a_data_out_clock = "clock0") ELSE clk1;
clk_b_in <= clk0 WHEN (port_b_address_clock = "clock0") ELSE clk1;
clk_b_byteena <= '0' WHEN (port_b_byte_enable_clock = "none" OR port_b_byte_enable_clock = "UNUSED") ELSE
clk0 WHEN (port_b_byte_enable_clock = "clock0") ELSE clk1;
clk_b_wena <= '0' WHEN (port_b_write_enable_clock = "none") ELSE
clk0 WHEN (port_b_write_enable_clock = "clock0") ELSE
clk1;
clk_b_rena <= '0' WHEN (port_b_read_enable_clock = "none") ELSE
clk0 WHEN (port_b_read_enable_clock = "clock0") ELSE
clk1;
clk_b_out <= '0' WHEN (port_b_data_out_clock = "none" OR port_b_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_b_data_out_clock = "clock0") ELSE clk1;
addr_a_clr_in <= '0' WHEN (port_a_address_clear = "none" OR port_a_address_clear = "UNUSED") ELSE clr0;
addr_b_clr_in <= '0' WHEN (port_b_address_clear = "none" OR port_b_address_clear = "UNUSED") ELSE
clr0 WHEN (port_b_address_clear = "clear0") ELSE clr1;
datain_a_clr_in <= '0';
datain_b_clr_in <= '0';
dataout_a_clr_reg <= '0' WHEN (port_a_data_out_clear = "none" OR port_a_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_a_data_out_clear = "clear0") ELSE clr1;
dataout_a_clr <= dataout_a_clr_reg WHEN (port_a_data_out_clock = "none" OR port_a_data_out_clock = "UNUSED") ELSE
'0';
dataout_b_clr_reg <= '0' WHEN (port_b_data_out_clear = "none" OR port_b_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_b_data_out_clear = "clear0") ELSE clr1;
dataout_b_clr <= dataout_b_clr_reg WHEN (port_b_data_out_clock = "none" OR port_b_data_out_clock = "UNUSED") ELSE
'0';
byteena_a_clr_in <= '0';
byteena_b_clr_in <= '0';
we_a_clr_in <= '0';
re_a_clr_in <= '0';
we_b_clr_in <= '0';
re_b_clr_in <= '0';
active_a_in <= '1' WHEN (clk0_input_clock_enable = "none") ELSE
ena0 WHEN (clk0_input_clock_enable = "ena0") ELSE
ena2;
active_a_core_in <= '1' WHEN (clk0_core_clock_enable = "none") ELSE
ena0 WHEN (clk0_core_clock_enable = "ena0") ELSE
ena2;
be_mask_write(primary_port_is_a) <= be_mask_write_a;
be_mask_write(primary_port_is_b) <= be_mask_write_b;
active_b_in_c0 <= '1' WHEN (clk0_input_clock_enable = "none") ELSE
ena0 WHEN (clk0_input_clock_enable = "ena0") ELSE
ena2;
active_b_in_c1 <= '1' WHEN (clk1_input_clock_enable = "none") ELSE
ena1 WHEN (clk1_input_clock_enable = "ena1") ELSE
ena3;
active_b_in <= active_b_in_c0 WHEN (port_b_address_clock = "clock0") ELSE active_b_in_c1;
active_b_core_in_c0 <= '1' WHEN (clk0_core_clock_enable = "none") ELSE
ena0 WHEN (clk0_core_clock_enable = "ena0") ELSE
ena2;
active_b_core_in_c1 <= '1' WHEN (clk1_core_clock_enable = "none") ELSE
ena1 WHEN (clk1_core_clock_enable = "ena1") ELSE
ena3;
active_b_core_in <= active_b_core_in_c0 WHEN (port_b_address_clock = "clock0") ELSE active_b_core_in_c1;
active_write_a <= (byteena_a_reg /= bytes_a_disabled);
active_write_b <= (byteena_b_reg /= bytes_b_disabled);
-- Store core clock enable value for delayed write
-- port A core active
active_a_core_in_vec(0) <= active_a_core_in;
active_core_port_a : cycloneiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_a_core_in_vec,
clk => clk_a_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
ena => wire_vcc,
stall => wire_gnd,
q => active_a_core_out
);
active_a_core <= (active_a_core_out(0) = '1');
-- port B core active
active_b_core_in_vec(0) <= active_b_core_in;
active_core_port_b : cycloneiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_b_core_in_vec,
clk => clk_b_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
ena => wire_vcc,
stall => wire_gnd,
q => active_b_core_out
);
active_b_core <= (active_b_core_out(0) = '1');
-- ------ A input registers
-- write enable
we_a_reg_in(0) <= '0' WHEN mode_is_rom ELSE portawe;
we_a_register : cycloneiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => we_a_reg_in,
clk => clk_a_wena,
aclr => we_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => we_a_reg_out,
aclrout => we_a_clr
);
we_a_reg <= we_a_reg_out(0);
-- read enable
re_a_reg_in(0) <= portare;
re_a_register : cycloneiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => re_a_reg_in,
clk => clk_a_rena,
aclr => re_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => re_a_reg_out,
aclrout => re_a_clr
);
re_a_reg <= re_a_reg_out(0);
-- address
addr_a_register : cycloneiii_ram_register
GENERIC MAP ( width => port_a_address_width )
PORT MAP (
d => portaaddr,
clk => clk_a_in,
aclr => addr_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => portaaddrstall,
ena => active_a_in,
q => addr_a_reg,
aclrout => addr_a_clr
);
-- data
datain_a_register : cycloneiii_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => portadatain,
clk => clk_a_in,
aclr => datain_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => datain_a_reg,
aclrout => datain_a_clr
);
-- byte enable
byteena_a_register : cycloneiii_ram_register
GENERIC MAP (
width => port_a_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portabyteenamasks,
clk => clk_a_byteena,
aclr => byteena_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => byteena_a_reg,
aclrout => byteena_a_clr
);
-- ------ B input registers
-- read enable
re_b_reg_in(0) <= portbre;
re_b_register : cycloneiii_ram_register
GENERIC MAP (
width => 1
)
PORT MAP (
d => re_b_reg_in,
clk => clk_b_in,
aclr => re_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => re_b_reg_out,
aclrout => re_b_clr
);
re_b_reg <= re_b_reg_out(0);
-- write enable
we_b_reg_in(0) <= portbwe;
we_b_register : cycloneiii_ram_register
GENERIC MAP (
width => 1
)
PORT MAP (
d => we_b_reg_in,
clk => clk_b_in,
aclr => we_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => we_b_reg_out,
aclrout => we_b_clr
);
we_b_reg <= we_b_reg_out(0);
-- address
addr_b_register : cycloneiii_ram_register
GENERIC MAP ( width => port_b_address_width )
PORT MAP (
d => portbaddr,
clk => clk_b_in,
aclr => addr_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => portbaddrstall,
ena => active_b_in,
q => addr_b_reg,
aclrout => addr_b_clr
);
-- data
datain_b_register : cycloneiii_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => portbdatain,
clk => clk_b_in,
aclr => datain_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => datain_b_reg,
aclrout => datain_b_clr
);
-- byte enable
byteena_b_register : cycloneiii_ram_register
GENERIC MAP (
width => port_b_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portbbyteenamasks,
clk => clk_b_byteena,
aclr => byteena_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => byteena_b_reg,
aclrout => byteena_b_clr
);
datain_prime_reg <= datain_a_reg WHEN primary_port_is_a ELSE datain_b_reg;
addr_prime_reg <= alt_conv_integer(addr_a_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_b_reg);
datain_sec_reg <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
datain_b_reg WHEN primary_port_is_a ELSE datain_a_reg;
addr_sec_reg <= alt_conv_integer(addr_b_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_a_reg);
-- Write pulse generation
wpgen_a_clk <= clk_a_in;
wpgen_a_clkena <= '1' WHEN (active_a_core AND active_write_a AND (we_a_reg = '1')) ELSE '0';
wpgen_a : cycloneiii_ram_pulse_generator
PORT MAP (
clk => wpgen_a_clk,
ena => wpgen_a_clkena,
delaywrite => delay_write_pulse_a,
pulse => write_pulse(primary_port_is_a),
cycle => write_cycle_a
);
wpgen_b_clk <= clk_b_in;
wpgen_b_clkena <= '1' WHEN (active_b_core AND active_write_b AND mode_is_bdp AND (we_b_reg = '1')) ELSE '0';
wpgen_b : cycloneiii_ram_pulse_generator
PORT MAP (
clk => wpgen_b_clk,
ena => wpgen_b_clkena,
delaywrite => delay_write_pulse_b,
pulse => write_pulse(primary_port_is_b),
cycle => write_cycle_b
);
-- Read pulse generation
rpgen_a_clkena <= '1' WHEN (active_a_core AND (re_a_reg = '1') AND (we_a_reg = '0') AND (dataout_a_clr = '0')) ELSE '0';
rpgen_a : cycloneiii_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => rpgen_a_clkena,
cycle => clk_a_core,
pulse => read_pulse(primary_port_is_a)
);
rpgen_b_clkena <= '1' WHEN ((mode_is_dp OR mode_is_bdp) AND active_b_core AND (re_b_reg = '1') AND (we_b_reg = '0') AND (dataout_b_clr = '0')) ELSE '0';
rpgen_b : cycloneiii_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => rpgen_b_clkena,
cycle => clk_b_core,
pulse => read_pulse(primary_port_is_b)
);
-- Read-during-Write pulse generation
rwpgen_a_clkena <= '1' WHEN (active_a_core AND (re_a_reg = '1') AND (we_a_reg = '1') AND read_before_write_a AND (dataout_a_clr = '0')) ELSE '0';
rwpgen_a : cycloneiii_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => rwpgen_a_clkena,
pulse => rw_pulse(primary_port_is_a)
);
rwpgen_b_clkena <= '1' WHEN (active_b_core AND mode_is_bdp AND (re_b_reg = '1') AND (we_b_reg = '1') AND read_before_write_b AND (dataout_b_clr = '0')) ELSE '0';
rwpgen_b : cycloneiii_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => rwpgen_b_clkena,
pulse => rw_pulse(primary_port_is_b)
);
-- Create internal masks for byte enable processing
mask_create : PROCESS (byteena_a_reg,byteena_b_reg)
VARIABLE mask : mask_rec;
BEGIN
IF (byteena_a_reg'EVENT) THEN
mask := get_mask(byteena_a_reg,primary_port_is_a,port_a_byte_enable_mask_width,byte_size_a);
IF (primary_port_is_a) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
IF (byteena_b_reg'EVENT) THEN
mask := get_mask(byteena_b_reg,primary_port_is_b,port_b_byte_enable_mask_width,byte_size_b);
IF (primary_port_is_b) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
END PROCESS mask_create;
-- (row,col) coordinates
row_sec <= addr_sec_reg / num_cols;
col_sec <= addr_sec_reg mod num_cols;
mem_rw : PROCESS (init_mem,
write_pulse,read_pulse,read_pulse_feedthru,
rw_pulse,
dataout_a_clr, dataout_b_clr,
mem_invalidate,mem_invalidate_loc,read_latch_invalidate)
-- mem init
TYPE rw_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
VARIABLE addr_range_init,row,col,index : INTEGER;
VARIABLE mem_init_std : STD_LOGIC_VECTOR((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
VARIABLE mem_val : mem_type;
-- read/write
VARIABLE mem_data_p : mem_row_type;
VARIABLE row_prime,col_prime : INTEGER;
VARIABLE access_same_location : BOOLEAN;
VARIABLE read_during_write : rw_type;
BEGIN
-- Latch Clear
IF (dataout_a_clr'EVENT AND dataout_a_clr = '1') THEN
IF (primary_port_is_a) THEN
read_latch.prime <= (OTHERS => (OTHERS => '0'));
dataout_prime <= (OTHERS => '0');
ELSE
read_latch.sec <= (OTHERS => '0');
dataout_sec <= (OTHERS => '0');
END IF;
END IF;
IF (dataout_b_clr'EVENT AND dataout_b_clr = '1') THEN
IF (primary_port_is_b) THEN
read_latch.prime <= (OTHERS => (OTHERS => '0'));
dataout_prime <= (OTHERS => '0');
ELSE
read_latch.sec <= (OTHERS => '0');
dataout_sec <= (OTHERS => '0');
END IF;
END IF;
read_during_write := (FALSE,FALSE);
-- Memory initialization
IF (init_mem'EVENT) THEN
-- Initialize output latches to 0
IF (primary_port_is_a) THEN
dataout_prime <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_sec <= (OTHERS => '0'); END IF;
ELSE
dataout_sec <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_prime <= (OTHERS => '0'); END IF;
END IF;
IF (power_up_uninitialized = "false" AND (NOT ram_type)) THEN
mem_val := (OTHERS => (OTHERS => (OTHERS => '0')));
END IF;
IF (primary_port_is_a) THEN
addr_range_init := port_a_last_address - port_a_first_address + 1;
ELSE
addr_range_init := port_b_last_address - port_b_first_address + 1;
END IF;
IF (init_file_layout = "port_a" OR init_file_layout = "port_b") THEN
mem_init_std := to_stdlogicvector(mem_init4 & mem_init3 & mem_init2 & mem_init1 & mem_init0)((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
FOR row IN 0 TO addr_range_init - 1 LOOP
FOR col IN 0 to num_cols - 1 LOOP
index := row * data_width;
mem_val(row)(col) := mem_init_std(index + (col+1)*data_unit_width -1 DOWNTO
index + col*data_unit_width);
END LOOP;
END LOOP;
END IF;
mem <= mem_val;
END IF;
access_same_location := (mode_is_dp OR mode_is_bdp) AND (addr_prime_reg = row_sec);
-- Read before Write stage 1 : read data from memory
-- Read before Write stage 2 : send data to output
IF (rw_pulse(primary)'EVENT) THEN
IF (rw_pulse(primary) = '1') THEN
read_latch.prime <= mem(addr_prime_reg);
ELSE
IF (be_mask_write(primary)) THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = 'X') THEN
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END IF;
END LOOP;
ELSE
FOR i IN 0 TO data_width - 1 LOOP
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END LOOP;
END IF;
END IF;
END IF;
IF (rw_pulse(secondary)'EVENT) THEN
IF (rw_pulse(secondary) = '1') THEN
read_latch.sec <= mem(row_sec)(col_sec);
ELSE
IF (be_mask_write(secondary)) THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = 'X') THEN
dataout_sec(i) <= read_latch.sec(i);
END IF;
END LOOP;
ELSE
dataout_sec <= read_latch.sec;
END IF;
END IF;
END IF;
-- Write stage 1 : X to buffer
-- Write stage 2 : actual data to memory
IF (write_pulse(primary)'EVENT) THEN
IF (write_pulse(primary) = '1') THEN
mem_data_p := mem(addr_prime_reg);
FOR i IN 0 TO num_cols - 1 LOOP
mem_data_p(i) := mem_data_p(i) XOR
mask_vector.prime(inverse)((i + 1)*data_unit_width - 1 DOWNTO i*data_unit_width);
END LOOP;
read_during_write(secondary) := (access_same_location AND read_pulse(secondary)'EVENT AND read_pulse(secondary) = '1');
IF (read_during_write(secondary)) THEN
read_latch.sec <= mem_data_p(col_sec);
ELSE
mem_data <= mem_data_p;
END IF;
ELSIF (clear_asserted_during_write(primary) /= '1') THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = '0') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= datain_prime_reg(i);
ELSIF (mask_vector.prime(inverse)(i) = 'X') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
IF (write_pulse(secondary)'EVENT) THEN
IF (write_pulse(secondary) = '1') THEN
read_during_write(primary) := (access_same_location AND read_pulse(primary)'EVENT AND read_pulse(primary) = '1');
IF (read_during_write(primary)) THEN
read_latch.prime <= mem(addr_prime_reg);
read_latch.prime(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
ELSE
mem_unit_data <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
END IF;
IF (access_same_location AND write_pulse(primary)'EVENT AND write_pulse(primary) = '1') THEN
mask_vector_common <=
mask_vector.prime(inverse)(((col_sec + 1)* data_unit_width - 1) DOWNTO col_sec*data_unit_width) AND
mask_vector.sec(inverse);
dual_write <= TRUE;
END IF;
ELSIF (clear_asserted_during_write(secondary) /= '1') THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = '0') THEN
mem(row_sec)(col_sec)(i) <= datain_sec_reg(i);
ELSIF (mask_vector.sec(inverse)(i) = 'X') THEN
mem(row_sec)(col_sec)(i) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
-- Simultaneous write
IF (dual_write AND write_pulse = "00") THEN
mem(row_sec)(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector_common;
dual_write <= FALSE;
END IF;
-- Read stage 1 : read data
-- Read stage 2 : send data to output
IF ((NOT read_during_write(primary)) AND read_pulse(primary)'EVENT) THEN
IF (read_pulse(primary) = '1') THEN
read_latch.prime <= mem(addr_prime_reg);
IF (access_same_location AND write_pulse(secondary) = '1') THEN
read_latch.prime(col_sec) <= mem_unit_data;
END IF;
ELSE
FOR i IN 0 TO data_width - 1 LOOP
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END LOOP;
END IF;
END IF;
IF ((NOT read_during_write(secondary)) AND read_pulse(secondary)'EVENT) THEN
IF (read_pulse(secondary) = '1') THEN
IF (access_same_location AND write_pulse(primary) = '1') THEN
read_latch.sec <= mem_data(col_sec);
ELSE
read_latch.sec <= mem(row_sec)(col_sec);
END IF;
ELSE
dataout_sec <= read_latch.sec;
END IF;
END IF;
-- Same port feed thru
IF (read_pulse_feedthru(primary)'EVENT AND read_pulse_feedthru(primary) = '0') THEN
IF (be_mask_write(primary)) THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = '0') THEN
dataout_prime(i) <= datain_prime_reg(i);
END IF;
END LOOP;
ELSE
dataout_prime <= datain_prime_reg XOR mask_vector.prime(normal);
END IF;
END IF;
IF (read_pulse_feedthru(secondary)'EVENT AND read_pulse_feedthru(secondary) = '0') THEN
IF (be_mask_write(secondary)) THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = '0') THEN
dataout_sec(i) <= datain_sec_reg(i);
END IF;
END LOOP;
ELSE
dataout_sec <= datain_sec_reg XOR mask_vector.sec(normal);
END IF;
END IF;
-- Async clear
IF (mem_invalidate'EVENT) THEN
IF (mem_invalidate(primary) = TRUE OR mem_invalidate(secondary) = TRUE) THEN
mem <= mem_x;
END IF;
END IF;
IF (mem_invalidate_loc'EVENT) THEN
IF (mem_invalidate_loc(primary)) THEN mem(addr_prime_reg) <= row_x; END IF;
IF (mem_invalidate_loc(secondary)) THEN mem(row_sec)(col_sec) <= col_x; END IF;
END IF;
IF (read_latch_invalidate'EVENT) THEN
IF (read_latch_invalidate(primary)) THEN
read_latch.prime <= row_x;
END IF;
IF (read_latch_invalidate(secondary)) THEN
read_latch.sec <= col_x;
END IF;
END IF;
END PROCESS mem_rw;
-- Same port feed through
ftpgen_a_clkena <= '1' WHEN (active_a_core AND (NOT mode_is_dp) AND (NOT old_data_write_a) AND (we_a_reg = '1') AND (re_a_reg = '1') AND (dataout_a_clr = '0')) ELSE '0';
ftpgen_a : cycloneiii_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => ftpgen_a_clkena,
pulse => read_pulse_feedthru(primary_port_is_a)
);
ftpgen_b_clkena <= '1' WHEN (active_b_core AND mode_is_bdp AND (NOT old_data_write_b) AND (we_b_reg = '1') AND (re_b_reg = '1') AND (dataout_b_clr = '0')) ELSE '0';
ftpgen_b : cycloneiii_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => ftpgen_b_clkena,
pulse => read_pulse_feedthru(primary_port_is_b)
);
-- Asynch clear events
clear_a : PROCESS(addr_a_clr,we_a_clr,datain_a_clr)
BEGIN
IF (addr_a_clr'EVENT AND addr_a_clr = '1') THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF (active_a_core AND re_a_reg = '1' AND dataout_a_clr = '0' AND dataout_a_clr_reg_latch = '0') THEN
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((we_a_clr'EVENT AND we_a_clr = '1') OR (datain_a_clr'EVENT AND datain_a_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_a;
clear_b : PROCESS(addr_b_clr,we_b_clr,datain_b_clr)
BEGIN
IF (addr_b_clr'EVENT AND addr_b_clr = '1') THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (we_b_reg = '1')) THEN
mem_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF ((mode_is_dp OR mode_is_bdp) AND active_b_core AND re_b_reg = '1' AND dataout_b_clr = '0' AND dataout_b_clr_reg_latch = '0') THEN
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((we_b_clr'EVENT AND we_b_clr = '1') OR (datain_b_clr'EVENT AND datain_b_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (we_b_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_b;
-- Clear mux registers (Latch Clear)
-- Port A output register clear
dataout_a_clr_reg_latch_in(0) <= dataout_a_clr;
aclr_a_mux_register : cycloneiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => dataout_a_clr_reg_latch_in,
clk => clk_a_core,
aclr => wire_gnd,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => wire_vcc,
q => dataout_a_clr_reg_latch_out
);
dataout_a_clr_reg_latch <= dataout_a_clr_reg_latch_out(0);
-- Port B output register clear
dataout_b_clr_reg_latch_in(0) <= dataout_b_clr;
aclr_b_mux_register : cycloneiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => dataout_b_clr_reg_latch_in,
clk => clk_b_core,
aclr => wire_gnd,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => wire_vcc,
q => dataout_b_clr_reg_latch_out
);
dataout_b_clr_reg_latch <= dataout_b_clr_reg_latch_out(0);
-- ------ Output registers
clkena_out_c0 <= '1' WHEN (clk0_output_clock_enable = "none") ELSE ena0;
clkena_out_c1 <= '1' WHEN (clk1_output_clock_enable = "none") ELSE ena1;
clkena_a_out <= clkena_out_c0 WHEN (port_a_data_out_clock = "clock0") ELSE clkena_out_c1;
clkena_b_out <= clkena_out_c0 WHEN (port_b_data_out_clock = "clock0") ELSE clkena_out_c1;
dataout_a <= dataout_prime WHEN primary_port_is_a ELSE dataout_sec;
dataout_b <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
dataout_prime WHEN primary_port_is_b ELSE dataout_sec;
dataout_a_register : cycloneiii_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => dataout_a,
clk => clk_a_out,
aclr => dataout_a_clr_reg,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => clkena_a_out,
q => dataout_a_reg
);
dataout_b_register : cycloneiii_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => dataout_b,
clk => clk_b_out,
aclr => dataout_b_clr_reg,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => clkena_b_out,
q => dataout_b_reg
);
portadataout <= dataout_a_reg WHEN out_a_is_reg ELSE dataout_a;
portbdataout <= dataout_b_reg WHEN out_b_is_reg ELSE dataout_b;
END block_arch;
-----------------------------------------------------------------------
--
-- Module Name : cycloneiii_mac_data_reg
--
-- Description : Simulation model for the data input register of
-- Cyclone II MAC_MULT
--
-----------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_mac_data_reg IS
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_data : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tsetup_data_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_data_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_aclr_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
data_width : integer := 18
);
PORT (
-- INPUT PORTS
clk : IN std_logic;
data : IN std_logic_vector(17 DOWNTO 0);
ena : IN std_logic;
aclr : IN std_logic;
-- OUTPUT PORTS
dataout : OUT std_logic_vector(17 DOWNTO 0)
);
END cycloneiii_mac_data_reg;
ARCHITECTURE vital_cycloneiii_mac_data_reg OF cycloneiii_mac_data_reg IS
SIGNAL data_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL aclr_ipd : std_logic;
SIGNAL clk_ipd : std_logic;
SIGNAL ena_ipd : std_logic;
SIGNAL dataout_tmp : std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
BEGIN
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
g1 : for i in data'range generate
VitalWireDelay (data_ipd(i), data(i), tipd_data(i));
end generate;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process (clk_ipd, aclr_ipd, data_ipd)
variable Tviol_data_clk : std_ulogic := '0';
variable TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_data_clk,
TimingData => TimingData_data_clk,
TestSignal => data,
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_data_clk_noedge_posedge,
SetupLow => tsetup_data_clk_noedge_posedge,
HoldHigh => thold_data_clk_noedge_posedge,
HoldLow => thold_data_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MAC_DATA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01(aclr) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MAC_DATA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (aclr_ipd = '1') then
dataout_tmp <= (OTHERS => '0');
elsif (clk_ipd'event and clk_ipd = '1' and (ena_ipd = '1')) then
dataout_tmp <= data_ipd;
end if;
end process;
----------------------
-- Path Delay Section
----------------------
PathDelay : block
begin
g1 : for i in dataout_tmp'range generate
VITALtiming : process (dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (OutSignal => dataout(i),
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp(i),
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn);
end process;
end generate;
end block;
END vital_cycloneiii_mac_data_reg;
--------------------------------------------------------------------
--
-- Module Name : cycloneiii_mac_sign_reg
--
-- Description : Simulation model for the sign input register of
-- Cyclone II MAC_MULT
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_mac_sign_reg IS
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
-- INPUT PORTS
clk : IN std_logic;
d : IN std_logic;
ena : IN std_logic;
aclr : IN std_logic;
-- OUTPUT PORTS
q : OUT std_logic
);
END cycloneiii_mac_sign_reg;
ARCHITECTURE cycloneiii_mac_sign_reg OF cycloneiii_mac_sign_reg IS
signal d_ipd : std_logic;
signal clk_ipd : std_logic;
signal aclr_ipd : std_logic;
signal ena_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process (clk_ipd, aclr_ipd)
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable q_reg : std_logic := '0';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/SIGN_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01(aclr) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/SIGN_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (aclr_ipd = '1') then
q_reg := '0';
elsif (clk_ipd'event and clk_ipd = '1' and (ena_ipd = '1')) then
q_reg := d_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_reg,
Paths => (0 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
END cycloneiii_mac_sign_reg;
--------------------------------------------------------------------
--
-- Module Name : cycloneiii_mac_mult_internal
--
-- Description : Cyclone II MAC_MULT_INTERNAL VHDL simulation model
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_mac_mult_internal IS
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_dataa : VitalDelayArrayType01(17 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(17 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_signa : VitalDelayType01 := DefPropDelay01;
tipd_signb : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datab_dataout : VitalDelayType01 := DefPropDelay01;
tpd_signa_dataout : VitalDelayType01 := DefPropDelay01;
tpd_signb_dataout : VitalDelayType01 := DefPropDelay01;
dataa_width : integer := 18;
datab_width : integer := 18
);
PORT (
dataa : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
datab : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0)
);
END cycloneiii_mac_mult_internal;
ARCHITECTURE vital_cycloneiii_mac_mult_internal OF cycloneiii_mac_mult_internal IS
-- Internal variables
SIGNAL dataa_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL datab_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL signa_ipd : std_logic;
SIGNAL signb_ipd : std_logic;
-- padding with 1's for input negation
SIGNAL reg_aclr : std_logic;
SIGNAL dataout_tmp : STD_LOGIC_VECTOR (dataa_width + datab_width downto 0) := (others => '0');
BEGIN
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
g1 : for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
end generate;
g2 : for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
end generate;
VitalWireDelay (signa_ipd, signa, tipd_signa);
VitalWireDelay (signb_ipd, signb, tipd_signb);
end block;
VITALtiming : process(dataa_ipd, datab_ipd, signa_ipd, signb_ipd)
begin
if((signa_ipd = '0') and (signb_ipd = '1')) then
dataout_tmp <=
unsigned(dataa_ipd(dataa_width-1 downto 0)) *
signed(datab_ipd(datab_width-1 downto 0));
elsif((signa_ipd = '1') and (signb_ipd = '0')) then
dataout_tmp <=
signed(dataa_ipd(dataa_width-1 downto 0)) *
unsigned(datab_ipd(datab_width-1 downto 0));
elsif((signa_ipd = '1') and (signb_ipd = '1')) then
dataout_tmp(dataout'range) <=
signed(dataa_ipd(dataa_width-1 downto 0)) *
signed(datab_ipd(datab_width-1 downto 0));
else --((signa_ipd = '0') and (signb_ipd = '0')) then
dataout_tmp(dataout'range) <=
unsigned(dataa_ipd(dataa_width-1 downto 0)) *
unsigned(datab_ipd(datab_width-1 downto 0));
end if;
end process;
----------------------
-- Path Delay Section
----------------------
PathDelay : block
begin
g1 : for i in dataout'range generate
VITALtiming : process (dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_dataout, TRUE),
2 => (signa'last_event, tpd_signa_dataout, TRUE),
3 => (signb'last_event, tpd_signb_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE );
end process;
end generate;
end block;
END vital_cycloneiii_mac_mult_internal;
--------------------------------------------------------------------
--
-- Module Name : cycloneiii_mac_mult
--
-- Description : Cyclone II MAC_MULT VHDL simulation model
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.cycloneiii_atom_pack.all;
USE work.cycloneiii_mac_data_reg;
USE work.cycloneiii_mac_sign_reg;
USE work.cycloneiii_mac_mult_internal;
ENTITY cycloneiii_mac_mult IS
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
lpm_hint : string := "true";
lpm_type : string := "cycloneiii_mac_mult"
);
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (OTHERS => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
ena : IN std_logic := '0';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END cycloneiii_mac_mult;
ARCHITECTURE vital_cycloneiii_mac_mult OF cycloneiii_mac_mult IS
COMPONENT cycloneiii_mac_data_reg
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_data : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tsetup_data_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_data_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_aclr_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
data_width : integer := 18
);
PORT (
-- INPUT PORTS
clk : IN std_logic;
data : IN std_logic_vector(17 DOWNTO 0);
ena : IN std_logic;
aclr : IN std_logic;
-- OUTPUT PORTS
dataout : OUT std_logic_vector(17 DOWNTO 0)
);
END COMPONENT;
COMPONENT cycloneiii_mac_sign_reg
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
-- INPUT PORTS
clk : IN std_logic;
d : IN std_logic;
ena : IN std_logic;
aclr : IN std_logic;
-- OUTPUT PORTS
q : OUT std_logic
);
END COMPONENT;
COMPONENT cycloneiii_mac_mult_internal
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_dataa : VitalDelayArrayType01(17 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(17 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_signa : VitalDelayType01 := DefPropDelay01;
tipd_signb : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datab_dataout : VitalDelayType01 := DefPropDelay01;
tpd_signa_dataout : VitalDelayType01 := DefPropDelay01;
tpd_signb_dataout : VitalDelayType01 := DefPropDelay01;
dataa_width : integer := 18;
datab_width : integer := 18
);
PORT (
dataa : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
datab : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0)
);
END COMPONENT;
-- Internal variables
SIGNAL dataa_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL datab_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL idataa_reg : std_logic_vector(17 DOWNTO 0); -- optional register for dataa input
SIGNAL idatab_reg : std_logic_vector(17 DOWNTO 0); -- optional register for datab input
SIGNAL isigna_reg : std_logic; -- optional register for signa input
SIGNAL isignb_reg : std_logic; -- optional register for signb input
SIGNAL idataa_int : std_logic_vector(17 DOWNTO 0); -- dataa as seen by the multiplier input
SIGNAL idatab_int : std_logic_vector(17 DOWNTO 0); -- datab as seen by the multiplier input
SIGNAL isigna_int : std_logic; -- signa as seen by the multiplier input
SIGNAL isignb_int : std_logic; -- signb as seen by the multiplier input
-- padding with 1's for input negation
SIGNAL reg_aclr : std_logic;
SIGNAL dataout_tmp : STD_LOGIC_VECTOR (dataa_width + datab_width downto 0) := (others => '0');
BEGIN
---------------------
-- INPUT PATH DELAYs
---------------------
reg_aclr <= (NOT devpor) OR (NOT devclrn) OR (aclr) ;
-- padding input data to full bus width
dataa_ipd(dataa_width-1 downto 0) <= dataa;
datab_ipd(datab_width-1 downto 0) <= datab;
-- Optional input registers for dataa,b and signa,b
dataa_reg : cycloneiii_mac_data_reg
GENERIC MAP (
data_width => dataa_width)
PORT MAP (
clk => clk,
data => dataa_ipd,
ena => ena,
aclr => reg_aclr,
dataout => idataa_reg);
datab_reg : cycloneiii_mac_data_reg
GENERIC MAP (
data_width => datab_width)
PORT MAP (
clk => clk,
data => datab_ipd,
ena => ena,
aclr => reg_aclr,
dataout => idatab_reg);
signa_reg : cycloneiii_mac_sign_reg
PORT MAP (
clk => clk,
d => signa,
ena => ena,
aclr => reg_aclr,
q => isigna_reg);
signb_reg : cycloneiii_mac_sign_reg
PORT MAP (
clk => clk,
d => signb,
ena => ena,
aclr => reg_aclr,
q => isignb_reg);
idataa_int <= dataa_ipd WHEN (dataa_clock = "none") ELSE idataa_reg;
idatab_int <= datab_ipd WHEN (datab_clock = "none") ELSE idatab_reg;
isigna_int <= signa WHEN (signa_clock = "none") ELSE isigna_reg;
isignb_int <= signb WHEN (signb_clock = "none") ELSE isignb_reg;
mac_multiply : cycloneiii_mac_mult_internal
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width
)
PORT MAP (
dataa => idataa_int,
datab => idatab_int,
signa => isigna_int,
signb => isignb_int,
dataout => dataout
);
END vital_cycloneiii_mac_mult;
--------------------------------------------------------------------
--
-- Module Name : cycloneiii_mac_out
--
-- Description : Cyclone II MAC_OUT VHDL simulation model
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_mac_out IS
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_dataa : VitalDelayArrayType01(35 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout : VitalDelayType01 := DefPropDelay01;
tpd_aclr_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_dataa_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dataa_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
dataa_width : integer := 1;
output_clock : string := "none";
lpm_hint : string := "true";
lpm_type : string := "cycloneiii_mac_out");
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
ena : IN std_logic := '1';
dataout : OUT std_logic_vector(dataa_width-1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END cycloneiii_mac_out;
ARCHITECTURE vital_cycloneiii_mac_out OF cycloneiii_mac_out IS
-- internal variables
SIGNAL dataa_ipd : std_logic_vector(dataa'range);
SIGNAL clk_ipd : std_logic;
SIGNAL aclr_ipd : std_logic;
SIGNAL ena_ipd : std_logic;
-- optional register
SIGNAL use_reg : std_logic;
SIGNAL dataout_tmp : std_logic_vector(dataout'range) := (OTHERS => '0');
BEGIN
---------------------
-- PATH DELAYs
---------------------
WireDelay : block
begin
g1 : for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
VITALtiming : process (clk_ipd, aclr_ipd, dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp(i),
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge, use_reg = '1'),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge, use_reg = '1'),
2 => (dataa_ipd(i)'last_event, tpd_dataa_dataout, use_reg = '0')),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end generate;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
use_reg <= '1' WHEN (output_clock /= "none") ELSE '0';
VITALtiming : process (clk_ipd, aclr_ipd, dataa_ipd)
variable Tviol_dataa_clk : std_ulogic := '0';
variable TimingData_dataa_clk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_dataa_clk,
TimingData => TimingData_dataa_clk,
TestSignal => dataa,
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_dataa_clk_noedge_posedge,
SetupLow => tsetup_dataa_clk_noedge_posedge,
HoldHigh => thold_dataa_clk_noedge_posedge,
HoldLow => thold_dataa_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr) OR (NOT use_reg) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MAC_DATA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr) OR
(NOT use_reg)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MAC_DATA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (use_reg = '0') then
dataout_tmp <= dataa_ipd;
else
if (aclr_ipd = '1') then
dataout_tmp <= (OTHERS => '0');
elsif (clk_ipd'event and clk_ipd = '1' and (ena_ipd = '1')) then
dataout_tmp <= dataa_ipd;
end if;
end if;
end process;
END vital_cycloneiii_mac_out;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_io_ibuf
--
-- Description : Cyclone III IO Ibuf VHDL simulation model
--
--
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_io_ibuf IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_ibar : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_ibar_o : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
differential_mode : string := "false";
bus_hold : string := "false";
lpm_type : string := "cycloneiii_io_ibuf"
);
PORT (
i : IN std_logic := '0';
ibar : IN std_logic := '0';
o : OUT std_logic
);
END cycloneiii_io_ibuf;
ARCHITECTURE arch OF cycloneiii_io_ibuf IS
SIGNAL i_ipd : std_logic := '0';
SIGNAL ibar_ipd : std_logic := '0';
SIGNAL o_tmp : std_logic;
SIGNAL out_tmp : std_logic;
SIGNAL prev_value : std_logic := '0';
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
VitalWireDelay (ibar_ipd, ibar, tipd_ibar);
end block;
PROCESS(i_ipd, ibar_ipd)
BEGIN
IF (differential_mode = "false") THEN
IF (i_ipd = '1') THEN
o_tmp <= '1';
prev_value <= '1';
ELSIF (i_ipd = '0') THEN
o_tmp <= '0';
prev_value <= '0';
ELSE
o_tmp <= i_ipd;
END IF;
ELSE
IF (( i_ipd = '0' ) and (ibar_ipd = '1')) then
o_tmp <= '0';
ELSIF (( i_ipd = '1' ) and (ibar_ipd = '0')) then
o_tmp <= '1';
ELSIF((( i_ipd = '1' ) and (ibar_ipd = '1')) or (( i_ipd = '0' ) and (ibar_ipd = '0')))then
o_tmp <= 'X';
ELSE
o_tmp <= 'X';
END IF;
END IF;
END PROCESS;
out_tmp <= prev_value when (bus_hold = "true") else o_tmp;
----------------------
-- Path Delay Section
----------------------
PROCESS( out_tmp)
variable output_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => out_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE),
1 => (ibar_ipd'last_event, tpd_ibar_o, TRUE)),
GlitchData => output_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_io_obuf
--
-- Description : Cyclone III IO Obuf VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_io_obuf IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_oe_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
tpd_oe_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
open_drain_output : string := "false";
bus_hold : string := "false";
lpm_type : string := "cycloneiii_io_obuf"
);
PORT (
i : IN std_logic := '0';
oe : IN std_logic := '1';
seriesterminationcontrol : IN std_logic_vector(15 DOWNTO 0) := (others => '0');
devoe : IN std_logic := '1';
o : OUT std_logic;
obar : OUT std_logic
);
END cycloneiii_io_obuf;
ARCHITECTURE arch OF cycloneiii_io_obuf IS
--INTERNAL Signals
SIGNAL i_ipd : std_logic := '0';
SIGNAL oe_ipd : std_logic := '0';
SIGNAL out_tmp : std_logic := 'Z';
SIGNAL out_tmp_bar : std_logic;
SIGNAL prev_value : std_logic := '0';
SIGNAL o_tmp : std_logic;
SIGNAL obar_tmp : std_logic;
SIGNAL o_tmp1 : std_logic;
SIGNAL obar_tmp1 : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
VitalWireDelay (oe_ipd, oe, tipd_oe);
end block;
PROCESS( i_ipd, oe_ipd)
BEGIN
IF (oe_ipd = '1') THEN
IF (open_drain_output = "true") THEN
IF (i_ipd = '0') THEN
out_tmp <= '0';
out_tmp_bar <= '1';
prev_value <= '0';
ELSE
out_tmp <= 'Z';
out_tmp_bar <= 'Z';
END IF;
ELSE
IF (i_ipd = '0') THEN
out_tmp <= '0';
out_tmp_bar <= '1';
prev_value <= '0';
ELSE
IF (i_ipd = '1') THEN
out_tmp <= '1';
out_tmp_bar <= '0';
prev_value <= '1';
ELSE
out_tmp <= i_ipd;
out_tmp_bar <= i_ipd;
END IF;
END IF;
END IF;
ELSE
IF (oe_ipd = '0') THEN
out_tmp <= 'Z';
out_tmp_bar <= 'Z';
ELSE
out_tmp <= 'X';
out_tmp_bar <= 'X';
END IF;
END IF;
END PROCESS;
o_tmp1 <= prev_value WHEN (bus_hold = "true") ELSE out_tmp;
obar_tmp1 <= NOT prev_value WHEN (bus_hold = "true") ELSE out_tmp_bar;
o_tmp <= o_tmp1 WHEN (devoe = '1') ELSE 'Z';
obar_tmp <= obar_tmp1 WHEN (devoe = '1') ELSE 'Z';
---------------------
-- Path Delay Section
----------------------
PROCESS( o_tmp,obar_tmp)
variable o_VitalGlitchData : VitalGlitchDataType;
variable obar_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => o_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE),
1 => (oe_ipd'last_event, tpd_oe_o, TRUE)),
GlitchData => o_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => obar,
OutSignalName => "obar",
OutTemp => obar_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_obar, TRUE),
1 => (oe_ipd'last_event, tpd_oe_obar, TRUE)),
GlitchData => obar_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_ddio_oe
--
-- Description : Cyclone III DDIO_OE VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY altera;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use altera.altera_primitives_components.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_ddio_oe IS
generic(
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "cycloneiii_ddio_oe"
);
PORT (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END cycloneiii_ddio_oe;
ARCHITECTURE arch OF cycloneiii_ddio_oe IS
component cycloneiii_mux21
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01
);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic
);
end component;
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
--Internal Signals
SIGNAL oe_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '0';
SIGNAL areset_ipd : std_logic := '0';
SIGNAL sreset_ipd : std_logic := '0';
SIGNAL ddioreg_aclr : std_logic;
SIGNAL ddioreg_prn : std_logic;
SIGNAL ddioreg_adatasdata : std_logic;
SIGNAL ddioreg_sclr : std_logic;
SIGNAL ddioreg_sload : std_logic;
SIGNAL dfflo_tmp : std_logic;
SIGNAL dffhi_tmp : std_logic;
signal nclk : std_logic;
signal dataout_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (oe_ipd, oe, tipd_oe);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
end block;
nclk <= NOT clk_ipd;
PROCESS
BEGIN
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
IF (async_mode = "clear") THEN
ddioreg_aclr <= NOT areset_ipd;
ddioreg_prn <= '1';
ELSIF (async_mode = "preset") THEN
ddioreg_aclr <= '1';
ddioreg_prn <= NOT areset_ipd;
ELSE
ddioreg_aclr <= '1';
ddioreg_prn <= '1';
END IF;
IF (sync_mode = "clear") THEN
ddioreg_adatasdata <= '0';
ddioreg_sclr <= sreset_ipd;
ddioreg_sload <= '0';
ELSIF (sync_mode = "preset") THEN
ddioreg_adatasdata <= '1';
ddioreg_sclr <= '0';
ddioreg_sload <= sreset_ipd;
ELSE
ddioreg_adatasdata <= '0';
ddioreg_sclr <= '0';
ddioreg_sload <= '0';
END IF;
END PROCESS;
ddioreg_hi : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => oe_ipd,
clk => clk_ipd,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dffhi_tmp,
devpor => devpor,
devclrn => devclrn
);
--DDIO Low Register
ddioreg_lo : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => dffhi_tmp,
clk => nclk,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dfflo_tmp,
devpor => devpor,
devclrn => devclrn
);
--registered output
or_gate : cycloneiii_mux21
port map (
A => dffhi_tmp,
B => dfflo_tmp,
S => dfflo_tmp,
MO => dataout
);
dfflo <= dfflo_tmp ;
dffhi <= dffhi_tmp ;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_ddio_out
--
-- Description : Cyclone III DDIO_OUT VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY altera;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use altera.altera_primitives_components.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_ddio_out IS
generic(
tipd_datainlo : VitalDelayType01 := DefPropDelay01;
tipd_datainhi : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "cycloneiii_ddio_out"
);
PORT (
datainlo : IN std_logic := '0';
datainhi : IN std_logic := '0';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic ;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END cycloneiii_ddio_out;
ARCHITECTURE arch OF cycloneiii_ddio_out IS
component cycloneiii_mux21
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01
);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic
);
end component;
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
--Internal Signals
SIGNAL datainlo_ipd : std_logic := '0';
SIGNAL datainhi_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '0';
SIGNAL areset_ipd : std_logic := '0';
SIGNAL sreset_ipd : std_logic := '0';
SIGNAL ddioreg_aclr : std_logic;
SIGNAL ddioreg_prn : std_logic;
SIGNAL ddioreg_adatasdata : std_logic;
SIGNAL ddioreg_sclr : std_logic;
SIGNAL ddioreg_sload : std_logic;
SIGNAL dfflo_tmp : std_logic;
SIGNAL dffhi_tmp : std_logic;
SIGNAL dataout_tmp : std_logic;
Signal mux_sel : std_logic;
Signal mux_lo : std_logic;
Signal sel_mux_lo_in : std_logic;
Signal sel_mux_select : std_logic;
signal clk1 : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (datainlo_ipd, datainlo, tipd_datainlo);
VitalWireDelay (datainhi_ipd, datainhi, tipd_datainhi);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
end block;
PROCESS
BEGIN
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
IF (async_mode = "clear") THEN
ddioreg_aclr <= NOT areset_ipd;
ddioreg_prn <= '1';
ELSIF (async_mode = "preset") THEN
ddioreg_aclr <= '1';
ddioreg_prn <= NOT areset_ipd;
ELSE
ddioreg_aclr <= '1';
ddioreg_prn <= '1';
END IF;
IF (sync_mode = "clear") THEN
ddioreg_adatasdata <= '0';
ddioreg_sclr <= sreset_ipd;
ddioreg_sload <= '0';
ELSIF (sync_mode = "preset") THEN
ddioreg_adatasdata <= '1';
ddioreg_sclr <= '0';
ddioreg_sload <= sreset_ipd;
ELSE
ddioreg_adatasdata <= '0';
ddioreg_sclr <= '0';
ddioreg_sload <= '0';
END IF;
END PROCESS;
process(clk_ipd)
begin
clk1 <= clk_ipd;
end process;
--DDIO OE Register
ddioreg_hi : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => datainhi,
clk => clk_ipd,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dffhi_tmp,
devpor => devpor,
devclrn => devclrn
);
--DDIO Low Register
ddioreg_lo : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => datainlo,
clk => clk_ipd,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dfflo_tmp,
devpor => devpor,
devclrn => devclrn
);
mux_sel <= clk1;
mux_lo <= dfflo_tmp;
sel_mux_lo_in <= dfflo_tmp;
sel_mux_select <= mux_sel;
sel_mux : cycloneiii_mux21
port map (
A => sel_mux_lo_in,
B => dffhi_tmp,
S => sel_mux_select,
MO => dataout
);
dfflo <= dfflo_tmp;
dffhi <= dffhi_tmp;
END arch;
----------------------------------------------------------------------------
-- Module Name : cycloneiii_io_pad
-- Description : Simulation model for cycloneiii IO pad
----------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
ENTITY cycloneiii_io_pad IS
GENERIC (
lpm_type : string := "cycloneiii_io_pad");
PORT (
--INPUT PORTS
padin : IN std_logic := '0'; -- Input Pad
--OUTPUT PORTS
padout : OUT std_logic); -- Output Pad
END cycloneiii_io_pad;
ARCHITECTURE arch OF cycloneiii_io_pad IS
BEGIN
padout <= padin;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiii_ena_reg
--
-- Description : Simulation model for a simple DFF.
-- This is used for the gated clock generation
-- Powers upto 1.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_ena_reg is
generic (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_ena_reg : entity is TRUE;
end cycloneiii_ena_reg;
ARCHITECTURE behave of cycloneiii_ena_reg is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal d_ipd : std_logic;
signal clk_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (clk_ipd, clk, tipd_clk);
end block;
VITALtiming : process (clk_ipd, prn, clrn)
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable q_reg : std_logic := '1';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((clrn) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/cycloneiii_ena_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk_ipd'event and clk_ipd = '1' and (ena = '1')) then
q_reg := d_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_reg,
Paths => (0 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- VHDL Simulation Model for Cyclone III CLKCTRL Atom
--
--/////////////////////////////////////////////////////////////////////////////
--
--
-- CYCLONEII_CLKCTRL Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
use work.cycloneiii_ena_reg;
entity cycloneiii_clkctrl is
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "cycloneiii_clkctrl";
ena_register_mode : STRING := "Falling Edge";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
outclk : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_clkctrl : entity is TRUE;
end cycloneiii_clkctrl;
architecture vital_clkctrl of cycloneiii_clkctrl is
attribute VITAL_LEVEL0 of vital_clkctrl : architecture is TRUE;
component cycloneiii_ena_reg
generic (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
end component;
signal inclk_ipd : std_logic_vector(3 downto 0);
signal clkselect_ipd : std_logic_vector(1 downto 0);
signal ena_ipd : std_logic;
signal clkmux_out : std_logic;
signal clkmux_out_inv : std_logic;
signal cereg_clr : std_logic;
signal cereg1_out : std_logic;
signal cereg2_out : std_logic;
signal ena_out : std_logic;
signal vcc : std_logic := '1';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (inclk_ipd(0), inclk(0), tipd_inclk(0));
VitalWireDelay (inclk_ipd(1), inclk(1), tipd_inclk(1));
VitalWireDelay (inclk_ipd(2), inclk(2), tipd_inclk(2));
VitalWireDelay (inclk_ipd(3), inclk(3), tipd_inclk(3));
VitalWireDelay (clkselect_ipd(0), clkselect(0), tipd_clkselect(0));
VitalWireDelay (clkselect_ipd(1), clkselect(1), tipd_clkselect(1));
end block;
process(inclk_ipd, clkselect_ipd)
variable tmp : std_logic;
begin
if (clkselect_ipd = "11") then
tmp := inclk_ipd(3);
elsif (clkselect_ipd = "10") then
tmp := inclk_ipd(2);
elsif (clkselect_ipd = "01") then
tmp := inclk_ipd(1);
else
tmp := inclk_ipd(0);
end if;
clkmux_out <= tmp;
clkmux_out_inv <= NOT tmp;
end process;
extena0_reg : cycloneiii_ena_reg
port map (
clk => clkmux_out_inv,
ena => vcc,
d => ena_ipd,
clrn => vcc,
prn => devpor,
q => cereg1_out
);
extena1_reg : cycloneiii_ena_reg
port map (
clk => clkmux_out_inv,
ena => vcc,
d => cereg1_out,
clrn => vcc,
prn => devpor,
q => cereg2_out
);
ena_out <= cereg1_out WHEN (ena_register_mode = "falling edge") ELSE
ena_ipd WHEN (ena_register_mode = "none") ELSE cereg2_out;
outclk <= ena_out AND clkmux_out;
end vital_clkctrl;
--
--
-- CYCLONEIII_RUBLOCK Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_rublock is
generic
(
sim_init_config : string := "factory";
sim_init_watchdog_value : integer := 0;
sim_init_status : integer := 0;
lpm_type : string := "cycloneiii_rublock"
);
port
(
clk : in std_logic;
shiftnld : in std_logic;
captnupdt : in std_logic;
regin : in std_logic;
rsttimer : in std_logic;
rconfig : in std_logic;
regout : out std_logic
);
end cycloneiii_rublock;
architecture architecture_rublock of cycloneiii_rublock is
begin
end architecture_rublock;
--
--
-- CYCLONEIII_APFCONTROLLER Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_apfcontroller is
generic
(
lpm_type: string := "cycloneiii_apfcontroller"
);
port
(
usermode : out std_logic;
nceout : out std_logic
);
end cycloneiii_apfcontroller;
architecture architecture_apfcontroller of cycloneiii_apfcontroller is
begin
end architecture_apfcontroller;
--------------------------------------------------------------------
--
-- Module Name : cycloneiii_termination
--
-- Description : Cyclone III Termination Atom VHDL simulation model
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY cycloneiii_termination IS
GENERIC (
pullup_control_to_core: string := "false";
power_down : string := "true";
test_mode : string := "false";
left_shift_termination_code : string := "false";
pullup_adder : integer := 0;
pulldown_adder : integer := 0;
clock_divide_by : integer := 32; -- 1, 4, 32
runtime_control : string := "false";
shift_vref_rup : string := "true";
shift_vref_rdn : string := "true";
shifted_vref_control : string := "true";
lpm_type : string := "cycloneiii_termination");
PORT (
rup : IN std_logic := '0';
rdn : IN std_logic := '0';
terminationclock : IN std_logic := '0';
terminationclear : IN std_logic := '0';
devpor : IN std_logic := '1';
devclrn : IN std_logic := '1';
comparatorprobe : OUT std_logic;
terminationcontrolprobe : OUT std_logic;
calibrationdone : OUT std_logic;
terminationcontrol : OUT std_logic_vector(15 DOWNTO 0));
END cycloneiii_termination;
ARCHITECTURE cycloneiii_termination_arch OF cycloneiii_termination IS
SIGNAL rup_compout : std_logic := '0';
SIGNAL rdn_compout : std_logic := '1';
BEGIN
calibrationdone <= '1'; -- power-up calibration status
comparatorprobe <= rup_compout WHEN (pullup_control_to_core = "true") ELSE rdn_compout;
rup_compout <= rup;
rdn_compout <= not rdn;
END cycloneiii_termination_arch;
-------------------------------------------------------------------
--
-- Entity Name : cycloneiii_jtag
--
-- Description : Cyclone III JTAG VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_jtag is
generic (
lpm_type : string := "cycloneiii_jtag"
);
port (
tms : in std_logic;
tck : in std_logic;
tdi : in std_logic;
tdoutap : in std_logic;
tdouser : in std_logic;
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
end cycloneiii_jtag;
architecture architecture_jtag of cycloneiii_jtag is
begin
end architecture_jtag;
-------------------------------------------------------------------
--
-- Entity Name : cycloneiii_crcblock
--
-- Description : Cyclone III CRCBLOCK VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_crcblock is
generic (
oscillator_divider : integer := 1;
lpm_type : string := "cycloneiii_crcblock"
);
port (
clk : in std_logic;
shiftnld : in std_logic;
ldsrc : in std_logic;
crcerror : out std_logic;
regout : out std_logic
);
end cycloneiii_crcblock;
architecture architecture_crcblock of cycloneiii_crcblock is
begin
end architecture_crcblock;
--
--
-- CYCLONEIII_OSCILLATOR Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_oscillator is
generic
(
lpm_type: string := "cycloneiii_oscillator"
);
port
(
oscena : in std_logic;
clkout : out std_logic
);
end cycloneiii_oscillator;
architecture architecture_oscillator of cycloneiii_oscillator is
begin
end architecture_oscillator;
|
-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 7.1 Build 156 04/30/2007
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
package cycloneiii_atom_pack is
function str_to_bin (lut_mask : string ) return std_logic_vector;
function product(list : std_logic_vector) return std_logic ;
function alt_conv_integer(arg : in std_logic_vector) return integer;
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
-- default control options
-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent;
-- change default delay type to Transport : for spr 68748
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
-- output strength mapping
-- UX01ZWHL-
CONSTANT PullUp : VitalOutputMapType := "UX01HX01X";
CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X";
CONSTANT PullDown : VitalOutputMapType := "UX01LX01X";
-- primitive result strength mapping
CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' );
CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' );
CONSTANT L : VitalTableSymbolType := '0';
CONSTANT H : VitalTableSymbolType := '1';
CONSTANT x : VitalTableSymbolType := '-';
CONSTANT S : VitalTableSymbolType := 'S';
CONSTANT R : VitalTableSymbolType := '/';
CONSTANT U : VitalTableSymbolType := 'X';
CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
-- Declare array types for CAM_SLICE
TYPE cycloneiii_mem_data IS ARRAY (0 to 31) of STD_LOGIC_VECTOR (31 downto 0);
function int2str( value : integer ) return string;
function map_x_to_0 (value : std_logic) return std_logic;
function SelectDelay (CONSTANT Paths: IN VitalPathArray01Type) return TIME;
end cycloneiii_atom_pack;
library IEEE;
use IEEE.std_logic_1164.all;
package body cycloneiii_atom_pack is
type masklength is array (4 downto 1) of std_logic_vector(3 downto 0);
function str_to_bin (lut_mask : string) return std_logic_vector is
variable slice : masklength := (OTHERS => "0000");
variable mask : std_logic_vector(15 downto 0);
begin
for i in 1 to lut_mask'length loop
case lut_mask(i) is
when '0' => slice(i) := "0000";
when '1' => slice(i) := "0001";
when '2' => slice(i) := "0010";
when '3' => slice(i) := "0011";
when '4' => slice(i) := "0100";
when '5' => slice(i) := "0101";
when '6' => slice(i) := "0110";
when '7' => slice(i) := "0111";
when '8' => slice(i) := "1000";
when '9' => slice(i) := "1001";
when 'a' => slice(i) := "1010";
when 'A' => slice(i) := "1010";
when 'b' => slice(i) := "1011";
when 'B' => slice(i) := "1011";
when 'c' => slice(i) := "1100";
when 'C' => slice(i) := "1100";
when 'd' => slice(i) := "1101";
when 'D' => slice(i) := "1101";
when 'e' => slice(i) := "1110";
when 'E' => slice(i) := "1110";
when others => slice(i) := "1111";
end case;
end loop;
mask := (slice(1) & slice(2) & slice(3) & slice(4));
return (mask);
end str_to_bin;
function product (list: std_logic_vector) return std_logic is
begin
for i in 0 to 31 loop
if list(i) = '0' then
return ('0');
end if;
end loop;
return ('1');
end product;
function alt_conv_integer(arg : in std_logic_vector) return integer is
variable result : integer;
begin
result := 0;
for i in arg'range loop
if arg(i) = '1' then
result := result + 2**i;
end if;
end loop;
return result;
end alt_conv_integer;
function int2str( value : integer ) return string is
variable ivalue,index : integer;
variable digit : integer;
variable line_no: string(8 downto 1) := " ";
begin
ivalue := value;
index := 1;
if (ivalue = 0) then
line_no := " 0";
end if;
while (ivalue > 0) loop
digit := ivalue MOD 10;
ivalue := ivalue/10;
case digit is
when 0 =>
line_no(index) := '0';
when 1 =>
line_no(index) := '1';
when 2 =>
line_no(index) := '2';
when 3 =>
line_no(index) := '3';
when 4 =>
line_no(index) := '4';
when 5 =>
line_no(index) := '5';
when 6 =>
line_no(index) := '6';
when 7 =>
line_no(index) := '7';
when 8 =>
line_no(index) := '8';
when 9 =>
line_no(index) := '9';
when others =>
ASSERT FALSE
REPORT "Illegal number!"
SEVERITY ERROR;
end case;
index := index + 1;
end loop;
return line_no;
end;
function map_x_to_0 (value : std_logic) return std_logic is
begin
if (Is_X (value) = TRUE) then
return '0';
else
return value;
end if;
end;
function SelectDelay (CONSTANT Paths : IN VitalPathArray01Type) return TIME IS
variable Temp : TIME;
variable TransitionTime : TIME := TIME'HIGH;
variable PathDelay : TIME := TIME'HIGH;
begin
for i IN Paths'RANGE loop
next when not Paths(i).PathCondition;
next when Paths(i).InputChangeTime > TransitionTime;
Temp := Paths(i).PathDelay(tr01);
if Paths(i).InputChangeTime < TransitionTime then
PathDelay := Temp;
else
if Temp < PathDelay then
PathDelay := Temp;
end if;
end if;
TransitionTime := Paths(i).InputChangeTime;
end loop;
return PathDelay;
end;
end cycloneiii_atom_pack;
Library ieee;
use ieee.std_logic_1164.all;
Package cycloneiii_pllpack is
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer);
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
m : out integer;
n : out integer );
function gcd (X: integer; Y: integer) return integer;
function count_digit (X: integer) return integer;
function scale_num (X: integer; Y: integer) return integer;
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer) return integer;
function output_counter_value (clk_divide: integer; clk_mult : integer ;
M: integer; N: integer ) return integer;
function counter_mode (duty_cycle: integer; output_counter_value: integer) return string;
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer;
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer;
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function counter_time_delay ( clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer;
function get_phase_degree (phase_shift: integer; clk_period: integer) return integer;
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer;
function counter_ph (tap_phase: integer; m : integer; n: integer) return integer;
function ph_adjust (tap_phase: integer; ph_base : integer) return integer;
function translate_string (mode : string) return string;
function str2int (s : string) return integer;
function dqs_str2int (s : string) return integer;
end cycloneiii_pllpack;
package body cycloneiii_pllpack is
-- finds the closest integer fraction of a given pair of numerator and denominator.
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer) is
constant MAX_ITER : integer := 20;
type INT_ARRAY is array ((MAX_ITER-1) downto 0) of integer;
variable quotient_array : INT_ARRAY;
variable int_loop_iter : integer;
variable int_quot : integer;
variable m_value : integer;
variable d_value : integer;
variable old_m_value : integer;
variable swap : integer;
variable loop_iter : integer;
variable num : integer;
variable den : integer;
variable i_max_iter : integer;
begin
loop_iter := 0;
if (numerator = 0) then
num := 1;
else
num := numerator;
end if;
if (denominator = 0) then
den := 1;
else
den := denominator;
end if;
i_max_iter := max_iter;
while (loop_iter < i_max_iter) loop
int_quot := num / den;
quotient_array(loop_iter) := int_quot;
num := num - (den*int_quot);
loop_iter := loop_iter+1;
if ((num = 0) or (max_denom /= -1) or (loop_iter = i_max_iter)) then
-- calculate the numerator and denominator if there is a restriction on the
-- max denom value or if the loop is ending
m_value := 0;
d_value := 1;
-- get the rounded value at this stage for the remaining fraction
if (den /= 0) then
m_value := (2*num/den);
end if;
-- calculate the fraction numerator and denominator at this stage
for int_loop_iter in (loop_iter-1) downto 0 loop
if (m_value = 0) then
m_value := quotient_array(int_loop_iter);
d_value := 1;
else
old_m_value := m_value;
m_value := (quotient_array(int_loop_iter)*m_value) + d_value;
d_value := old_m_value;
end if;
end loop;
-- if the denominator is less than the maximum denom_value or if there is no restriction save it
if ((d_value <= max_denom) or (max_denom = -1)) then
if ((m_value = 0) or (d_value = 0)) then
fraction_num := numerator;
fraction_div := denominator;
else
fraction_num := m_value;
fraction_div := d_value;
end if;
end if;
-- end the loop if the denomitor has overflown or the numerator is zero (no remainder during this round)
if (((d_value > max_denom) and (max_denom /= -1)) or (num = 0)) then
i_max_iter := loop_iter;
end if;
end if;
-- swap the numerator and denominator for the next round
swap := den;
den := num;
num := swap;
end loop;
end find_simple_integer_fraction;
-- find the M and N values for Manual phase based on the following 5 criterias:
-- 1. The PFD frequency (i.e. Fin / N) must be in the range 5 MHz to 720 MHz
-- 2. The VCO frequency (i.e. Fin * M / N) must be in the range 300 MHz to 1300 MHz
-- 3. M is less than 512
-- 4. N is less than 512
-- 5. It's the smallest M/N which satisfies all the above constraints, and is within 2ps
-- of the desired vco-phase-shift-step
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
m : out integer;
n : out integer ) is
constant MAX_M : integer := 511;
constant MAX_N : integer := 511;
constant MAX_PFD : integer := 720;
constant MIN_PFD : integer := 5;
constant MAX_VCO : integer := 1300;
constant MIN_VCO : integer := 300;
variable vco_period : integer;
variable pfd_freq : integer;
variable vco_freq : integer;
variable vco_ps_step_value : integer;
variable i_m : integer;
variable i_n : integer;
variable i_pre_m : integer;
variable i_pre_n : integer;
variable i_max_iter : integer;
variable loop_iter : integer;
begin
loop_iter := 0;
i_max_iter := MAX_N;
vco_period := vco_phase_shift_step * 8;
while (loop_iter < i_max_iter) loop
loop_iter := loop_iter+1;
i_pre_m := i_m;
i_pre_n := i_n;
find_simple_integer_fraction(inclock_period, vco_period,
loop_iter, i_m, i_n);
if (((clk0_div * i_m) rem (clk0_mult * i_n) /= 0) or
((clk1_div * i_m) rem (clk1_mult * i_n) /= 0) or
((clk2_div * i_m) rem (clk2_mult * i_n) /= 0) or
((clk3_div * i_m) rem (clk3_mult * i_n) /= 0) or
((clk4_div * i_m) rem (clk4_mult * i_n) /= 0) or
((clk5_div * i_m) rem (clk5_mult * i_n) /= 0) or
((clk6_div * i_m) rem (clk6_mult * i_n) /= 0) or
((clk7_div * i_m) rem (clk7_mult * i_n) /= 0) or
((clk8_div * i_m) rem (clk8_mult * i_n) /= 0) or
((clk9_div * i_m) rem (clk9_mult * i_n) /= 0) )
then
if (loop_iter = 1)
then
n := 1;
m := lcm (clk0_mult, clk1_mult, clk2_mult, clk3_mult,
clk4_mult, clk5_mult, clk6_mult,
clk7_mult, clk8_mult, clk9_mult, inclock_period);
else
m := i_pre_m;
n := i_pre_n;
end if;
i_max_iter := loop_iter;
else
m := i_m;
n := i_n;
end if;
pfd_freq := 1000000 / (inclock_period * i_n);
vco_freq := (1000000 * i_m) / (inclock_period * i_n);
vco_ps_step_value := (inclock_period * i_n) / (8 * i_m);
if ( (i_m < max_m) and (i_n < max_n) and (pfd_freq >= min_pfd) and (pfd_freq <= max_pfd) and
(vco_freq >= min_vco) and (vco_freq <= max_vco) and
(abs(vco_ps_step_value - vco_phase_shift_step) <= 2) )
then
i_max_iter := loop_iter;
end if;
end loop;
end find_m_and_n_4_manual_phase;
-- find the greatest common denominator of X and Y
function gcd (X: integer; Y: integer) return integer is
variable L, S, R, G : integer := 1;
begin
if (X < Y) then -- find which is smaller.
S := X;
L := Y;
else
S := Y;
L := X;
end if;
R := S;
while ( R > 1) loop
S := L;
L := R;
R := S rem L; -- divide bigger number by smaller.
-- remainder becomes smaller number.
end loop;
if (R = 0) then -- if evenly divisible then L is gcd else it is 1.
G := L;
else
G := R;
end if;
return G;
end gcd;
-- count the number of digits in the given integer
function count_digit (X: integer)
return integer is
variable count, result: integer := 0;
begin
result := X;
while (result /= 0) loop
result := (result / 10);
count := count + 1;
end loop;
return count;
end count_digit;
-- reduce the given huge number to Y significant digits
function scale_num (X: integer; Y: integer)
return integer is
variable count : integer := 0;
variable lc, fac_ten, result: integer := 1;
begin
count := count_digit(X);
for lc in 1 to (count-Y) loop
fac_ten := fac_ten * 10;
end loop;
result := (X / fac_ten);
return result;
end scale_num;
-- find the least common multiple of A1 to A10
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer)
return integer is
variable M1, M2, M3, M4, M5 , M6, M7, M8, M9, R: integer := 1;
begin
M1 := (A1 * A2)/gcd(A1, A2);
M2 := (M1 * A3)/gcd(M1, A3);
M3 := (M2 * A4)/gcd(M2, A4);
M4 := (M3 * A5)/gcd(M3, A5);
M5 := (M4 * A6)/gcd(M4, A6);
M6 := (M5 * A7)/gcd(M5, A7);
M7 := (M6 * A8)/gcd(M6, A8);
M8 := (M7 * A9)/gcd(M7, A9);
M9 := (M8 * A10)/gcd(M8, A10);
if (M9 < 3) then
R := 10;
elsif ((M9 <= 10) and (M9 >= 3)) then
R := 4 * M9;
elsif (M9 > 1000) then
R := scale_num(M9,3);
else
R := M9 ;
end if;
return R;
end lcm;
-- find the factor of division of the output clock frequency compared to the VCO
function output_counter_value (clk_divide: integer; clk_mult: integer ;
M: integer; N: integer ) return integer is
variable R: integer := 1;
begin
R := (clk_divide * M)/(clk_mult * N);
return R;
end output_counter_value;
-- find the mode of each PLL counter - bypass, even or odd
function counter_mode (duty_cycle: integer; output_counter_value: integer)
return string is
variable R: string (1 to 6) := " ";
variable counter_value: integer := 1;
begin
counter_value := (2*duty_cycle*output_counter_value)/100;
if output_counter_value = 1 then
R := "bypass";
elsif (counter_value REM 2) = 0 then
R := " even";
else
R := " odd";
end if;
return R;
end counter_mode;
-- find the number of VCO clock cycles to hold the output clock high
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer is
variable R: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value *2)/100 ;
if (half_cycle_high REM 2 = 0) then
R := half_cycle_high/2 ;
else
R := (half_cycle_high/2) + 1;
end if;
return R;
end;
-- find the number of VCO clock cycles to hold the output clock low
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer is
variable R, R1: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value*2)/100 ;
if (half_cycle_high REM 2 = 0) then
R1 := half_cycle_high/2 ;
else
R1 := (half_cycle_high/2) + 1;
end if;
R := output_counter_value - R1;
return R;
end;
-- find the smallest time delay amongst t1 to t10
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 > 0) then return m9; else return 0; end if;
end;
-- find the numerically largest negative number, and return its absolute value
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 < 0) then return (0 - m9); else return 0; end if;
end;
-- adjust the phase (tap_phase) with the largest negative number (ph_base)
function ph_adjust (tap_phase: integer; ph_base : integer) return integer is
begin
return (tap_phase + ph_base);
end;
-- find the time delay for each PLL counter
function counter_time_delay (clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer is
variable R: integer := 0;
begin
R := clk_time_delay + m_time_delay - n_time_delay;
return R;
end;
-- calculate the given phase shift (in ps) in terms of degrees
function get_phase_degree (phase_shift: integer; clk_period: integer)
return integer is
variable result: integer := 0;
begin
result := ( phase_shift * 360 ) / clk_period;
-- to round up the calculation result
if (result > 0) then
result := result + 1;
elsif (result < 0) then
result := result - 1;
else
result := 0;
end if;
return result;
end;
-- find the number of VCO clock cycles to wait initially before the first rising
-- edge of the output clock
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer is
variable R: integer;
variable R1: real;
begin
R1 := (real(abs(tap_phase)) * real(m))/(360.0 * real(n)) + 0.5;
-- Note NCSim VHDL had problem in rounding up for 0.5 - 0.99.
-- This checking will ensure that the rounding up is done.
if (R1 >= 0.5) and (R1 <= 1.0) then
R1 := 1.0;
end if;
R := integer(R1);
return R;
end;
-- find which VCO phase tap (0 to 7) to align the rising edge of the output clock to
function counter_ph (tap_phase: integer; m: integer; n: integer) return integer is
variable R: integer := 0;
begin
-- 0.5 is added for proper rounding of the tap_phase.
R := (integer(real(tap_phase * m / n)+ 0.5) REM 360)/45;
return R;
end;
-- convert given string to length 6 by padding with spaces
function translate_string (mode : string) return string is
variable new_mode : string (1 to 6) := " ";
begin
if (mode = "bypass") then
new_mode := "bypass";
elsif (mode = "even") then
new_mode := " even";
elsif (mode = "odd") then
new_mode := " odd";
end if;
return new_mode;
end;
function str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "i n string parameter! "
SEVERITY ERROR;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
newdigit := newdigit * 10 + digit;
end loop;
return (sign*newdigit);
end;
function dqs_str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
variable err : boolean := false;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & " in string parameter! "
SEVERITY ERROR;
err := true;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
-- set error flag
err := true;
end case;
if (err) then
err := false;
else
newdigit := newdigit * 10 + digit;
end if;
end loop;
return (sign*newdigit);
end;
end cycloneiii_pllpack;
--
--
-- DFFE Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_dffe is
generic(
TimingChecksOn: Boolean := True;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
port(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC;
CLRN : in STD_LOGIC;
PRN : in STD_LOGIC;
CLK : in STD_LOGIC;
ENA : in STD_LOGIC);
attribute VITAL_LEVEL0 of cycloneiii_dffe : entity is TRUE;
end cycloneiii_dffe;
-- architecture body --
architecture behave of cycloneiii_dffe is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal D_ipd : STD_ULOGIC := 'U';
signal CLRN_ipd : STD_ULOGIC := 'U';
signal PRN_ipd : STD_ULOGIC := 'U';
signal CLK_ipd : STD_ULOGIC := 'U';
signal ENA_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (D_ipd, D, tipd_D);
VitalWireDelay (CLRN_ipd, CLRN, tipd_CLRN);
VitalWireDelay (PRN_ipd, PRN, tipd_PRN);
VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (D_ipd, CLRN_ipd, PRN_ipd, CLK_ipd, ENA_ipd)
-- timing check results
VARIABLE Tviol_D_CLK : STD_ULOGIC := '0';
VARIABLE Tviol_ENA_CLK : STD_ULOGIC := '0';
VARIABLE TimingData_D_CLK : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_ENA_CLK : VitalTimingDataType := VitalTimingDataInit;
-- functionality results
VARIABLE Violation : STD_ULOGIC := '0';
VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 7);
VARIABLE D_delayed : STD_ULOGIC := 'U';
VARIABLE CLK_delayed : STD_ULOGIC := 'U';
VARIABLE ENA_delayed : STD_ULOGIC := 'U';
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => '0');
-- output glitch detection variables
VARIABLE Q_VitalGlitchData : VitalGlitchDataType;
CONSTANT dffe_Q_tab : VitalStateTableType := (
( L, L, x, x, x, x, x, x, x, L ),
( L, H, L, H, H, x, x, H, x, H ),
( L, H, L, H, x, L, x, H, x, H ),
( L, H, L, x, H, H, x, H, x, H ),
( L, H, H, x, x, x, H, x, x, S ),
( L, H, x, x, x, x, L, x, x, H ),
( L, H, x, x, x, x, H, L, x, S ),
( L, x, L, L, L, x, H, H, x, L ),
( L, x, L, L, x, L, H, H, x, L ),
( L, x, L, x, L, H, H, H, x, L ),
( L, x, x, x, x, x, x, x, x, S ));
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_D_CLK,
TimingData => TimingData_D_CLK,
TestSignal => D_ipd,
TestSignalName => "D",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_D_CLK_noedge_posedge,
SetupLow => tsetup_D_CLK_noedge_posedge,
HoldHigh => thold_D_CLK_noedge_posedge,
HoldLow => thold_D_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) OR ( (NOT ENA_ipd) )) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ENA_CLK,
TimingData => TimingData_ENA_CLK,
TestSignal => ENA_ipd,
TestSignalName => "ENA",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ENA_CLK_noedge_posedge,
SetupLow => tsetup_ENA_CLK_noedge_posedge,
HoldHigh => thold_ENA_CLK_noedge_posedge,
HoldLow => thold_ENA_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
-------------------------
-- Functionality Section
-------------------------
Violation := Tviol_D_CLK or Tviol_ENA_CLK;
VitalStateTable(
StateTable => dffe_Q_tab,
DataIn => (
Violation, CLRN_ipd, CLK_delayed, Results(1), D_delayed, ENA_delayed, PRN_ipd, CLK_ipd),
Result => Results,
NumStates => 1,
PreviousDataIn => PrevData_Q);
D_delayed := D_ipd;
CLK_delayed := CLK_ipd;
ENA_delayed := ENA_ipd;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Q,
OutSignalName => "Q",
OutTemp => Results(1),
Paths => ( 0 => (PRN_ipd'last_event, tpd_PRN_Q_negedge, TRUE),
1 => (CLRN_ipd'last_event, tpd_CLRN_Q_negedge, TRUE),
2 => (CLK_ipd'last_event, tpd_CLK_Q_posedge, TRUE)),
GlitchData => Q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--
--
-- cycloneiii_mux21 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_mux21 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic);
attribute VITAL_LEVEL0 of cycloneiii_mux21 : entity is TRUE;
end cycloneiii_mux21;
architecture AltVITAL of cycloneiii_mux21 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal A_ipd, B_ipd, S_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (A_ipd, A, tipd_A);
VitalWireDelay (B_ipd, B, tipd_B);
VitalWireDelay (S_ipd, S, tipd_S);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (A_ipd, B_ipd, S_ipd)
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if (S_ipd = '1') then
tmp_MO := B_ipd;
else
tmp_MO := A_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (A_ipd'last_event, tpd_A_MO, TRUE),
1 => (B_ipd'last_event, tpd_B_MO, TRUE),
2 => (S_ipd'last_event, tpd_S_MO, TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- cycloneiii_mux41 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_mux41 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN0_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN1_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN2_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN3_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_IN0 : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01;
tipd_IN2 : VitalDelayType01 := DefPropDelay01;
tipd_IN3 : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01)
);
port (
IN0 : in std_logic := '0';
IN1 : in std_logic := '0';
IN2 : in std_logic := '0';
IN3 : in std_logic := '0';
S : in std_logic_vector(1 downto 0) := (OTHERS => '0');
MO : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_mux41 : entity is TRUE;
end cycloneiii_mux41;
architecture AltVITAL of cycloneiii_mux41 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd : std_logic;
signal S_ipd : std_logic_vector(1 downto 0);
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN0_ipd, IN0, tipd_IN0);
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
VitalWireDelay (IN2_ipd, IN2, tipd_IN2);
VitalWireDelay (IN3_ipd, IN3, tipd_IN3);
VitalWireDelay (S_ipd(0), S(0), tipd_S(0));
VitalWireDelay (S_ipd(1), S(1), tipd_S(1));
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd, S_ipd(0), S_ipd(1))
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if ((S_ipd(1) = '1') AND (S_ipd(0) = '1')) then
tmp_MO := IN3_ipd;
elsif ((S_ipd(1) = '1') AND (S_ipd(0) = '0')) then
tmp_MO := IN2_ipd;
elsif ((S_ipd(1) = '0') AND (S_ipd(0) = '1')) then
tmp_MO := IN1_ipd;
else
tmp_MO := IN0_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (IN0_ipd'last_event, tpd_IN0_MO, TRUE),
1 => (IN1_ipd'last_event, tpd_IN1_MO, TRUE),
2 => (IN2_ipd'last_event, tpd_IN2_MO, TRUE),
3 => (IN3_ipd'last_event, tpd_IN3_MO, TRUE),
4 => (S_ipd(0)'last_event, tpd_S_MO(0), TRUE),
5 => (S_ipd(1)'last_event, tpd_S_MO(1), TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- cycloneiii_and1 Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.cycloneiii_atom_pack.all;
-- entity declaration --
entity cycloneiii_and1 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01);
port(
Y : out STD_LOGIC;
IN1 : in STD_LOGIC);
attribute VITAL_LEVEL0 of cycloneiii_and1 : entity is TRUE;
end cycloneiii_and1;
-- architecture body --
architecture AltVITAL of cycloneiii_and1 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
SIGNAL IN1_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN1_ipd)
-- functionality results
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
ALIAS Y_zd : STD_ULOGIC is Results(1);
-- output glitch detection variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
begin
-------------------------
-- Functionality Section
-------------------------
Y_zd := TO_X01(IN1_ipd);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (0 => (IN1_ipd'last_event, tpd_IN1_Y, TRUE)),
GlitchData => Y_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_lcell_comb
--
-- Description : Cyclone II LCELL_COMB VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_lcell_comb is
generic (
lut_mask : std_logic_vector(15 downto 0) := (OTHERS => '1');
sum_lutc_input : string := "datac";
dont_touch : string := "off";
lpm_type : string := "cycloneiii_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '1';
datab : in std_logic := '1';
datac : in std_logic := '1';
datad : in std_logic := '1';
cin : in std_logic := '0';
combout : out std_logic;
cout : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_lcell_comb : entity is TRUE;
end cycloneiii_lcell_comb;
architecture vital_lcell_comb of cycloneiii_lcell_comb is
attribute VITAL_LEVEL0 of vital_lcell_comb : architecture is TRUE;
signal dataa_ipd : std_logic;
signal datab_ipd : std_logic;
signal datac_ipd : std_logic;
signal datad_ipd : std_logic;
signal cin_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (dataa_ipd, dataa, tipd_dataa);
VitalWireDelay (datab_ipd, datab, tipd_datab);
VitalWireDelay (datac_ipd, datac, tipd_datac);
VitalWireDelay (datad_ipd, datad, tipd_datad);
VitalWireDelay (cin_ipd, cin, tipd_cin);
end block;
VITALtiming : process(dataa_ipd, datab_ipd, datac_ipd, datad_ipd,
cin_ipd)
variable combout_VitalGlitchData : VitalGlitchDataType;
variable cout_VitalGlitchData : VitalGlitchDataType;
-- output variables
variable combout_tmp : std_logic;
variable cout_tmp : std_logic;
begin
-- lut_mask_var := lut_mask;
------------------------
-- Timing Check Section
------------------------
if (sum_lutc_input = "datac") then
-- combout
combout_tmp := VitalMUX(data => lut_mask,
dselect => (datad_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
elsif (sum_lutc_input = "cin") then
-- combout
combout_tmp := VitalMUX(data => lut_mask,
dselect => (datad_ipd,
cin_ipd,
datab_ipd,
dataa_ipd));
end if;
-- cout
cout_tmp := VitalMUX(data => lut_mask,
dselect => ('0',
cin_ipd,
datab_ipd,
dataa_ipd));
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => combout,
OutSignalName => "COMBOUT",
OutTemp => combout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_combout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_combout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_combout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_combout, TRUE),
4 => (cin_ipd'last_event, tpd_cin_combout, TRUE)),
GlitchData => combout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => cout,
OutSignalName => "COUT",
OutTemp => cout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_cout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_cout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_cout, TRUE),
4 => (cin_ipd'last_event, tpd_cin_cout, TRUE)),
GlitchData => cout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_comb;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_routing_wire
--
-- Description : Cyclone III Routing Wire VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_routing_wire is
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_routing_wire : entity is TRUE;
end cycloneiii_routing_wire;
ARCHITECTURE behave of cycloneiii_routing_wire is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal datain_ipd : std_logic;
signal datainglitch_inert : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process(datain_ipd, datainglitch_inert)
variable datain_inert_VitalGlitchData : VitalGlitchDataType;
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => datainglitch_inert,
OutSignalName => "datainglitch_inert",
OutTemp => datain_ipd,
Paths => (1 => (datain_ipd'last_event, tpd_datainglitch_dataout, TRUE)),
GlitchData => datain_inert_VitalGlitchData,
Mode => VitalInertial,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => datainglitch_inert,
Paths => (1 => (datain_ipd'last_event, tpd_datain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiii_mn_cntr
--
-- Description : Timing simulation model for the M and N counter. This is a
-- common model for the input counter and the loop feedback
-- counter of the Cyclone III PLL.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY cycloneiii_mn_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END cycloneiii_mn_cntr;
ARCHITECTURE behave of cycloneiii_mn_cntr is
begin
process (clk, reset)
variable count : integer := 1;
variable first_rising_edge : boolean := true;
variable tmp_cout : std_logic;
begin
if (reset = '1') then
count := 1;
tmp_cout := '0';
first_rising_edge := true;
elsif (clk'event) then
if (clk = '1' and first_rising_edge) then
first_rising_edge := false;
tmp_cout := clk;
elsif (not first_rising_edge) then
if (count < modulus) then
count := count + 1;
else
count := 1;
tmp_cout := not tmp_cout;
end if;
end if;
end if;
cout <= transport tmp_cout after time_delay * 1 ps;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiii_scale_cntr
--
-- Description : Timing simulation model for the output scale-down counters.
-- This is a common model for the C0, C1, C2, C3, C4 and C5
-- output counters of the Cyclone III PLL.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY cycloneiii_scale_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
ph_tap : IN integer := 0;
cout : OUT std_logic
);
END cycloneiii_scale_cntr;
ARCHITECTURE behave of cycloneiii_scale_cntr is
begin
process (clk, reset)
variable tmp_cout : std_logic := '0';
variable count : integer := 1;
variable output_shift_count : integer := 1;
variable first_rising_edge : boolean := false;
begin
if (reset = '1') then
count := 1;
output_shift_count := 1;
tmp_cout := '0';
first_rising_edge := false;
elsif (clk'event) then
if (mode = " off") then
tmp_cout := '0';
elsif (mode = "bypass") then
tmp_cout := clk;
first_rising_edge := true;
elsif (not first_rising_edge) then
if (clk = '1') then
if (output_shift_count = initial) then
tmp_cout := clk;
first_rising_edge := true;
else
output_shift_count := output_shift_count + 1;
end if;
end if;
elsif (output_shift_count < initial) then
if (clk = '1') then
output_shift_count := output_shift_count + 1;
end if;
else
count := count + 1;
if (mode = " even" and (count = (high*2) + 1)) then
tmp_cout := '0';
elsif (mode = " odd" and (count = high*2)) then
tmp_cout := '0';
elsif (count = (high + low)*2 + 1) then
tmp_cout := '1';
count := 1; -- reset count
end if;
end if;
end if;
cout <= transport tmp_cout;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiii_pll_reg
--
-- Description : Simulation model for a simple DFF.
-- This is required for the generation of the bit slip-signals.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY cycloneiii_pll_reg is
PORT( clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
end cycloneiii_pll_reg;
ARCHITECTURE behave of cycloneiii_pll_reg is
begin
process (clk, prn, clrn)
variable q_reg : std_logic := '0';
begin
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk'event and clk = '1' and (ena = '1')) then
q_reg := D;
end if;
Q <= q_reg;
end process;
end behave;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiii_pll
--
-- Description : Timing simulation model for the Cyclone III PLL.
-- In the functional mode, it is also the model for the altpll
-- megafunction.
--
-- Limitations : Does not support Spread Spectrum and Bandwidth.
--
-- Outputs : Up to 10 output clocks, each defined by its own set of
-- parameters. Locked output (active high) indicates when the
-- PLL locks. clkbad and activeclock are used for
-- clock switchover to indicate which input clock has gone
-- bad, when the clock switchover initiates and which input
-- clock is being used as the reference, respectively.
-- scandataout is the data output of the serial scan chain.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE STD.TEXTIO.all;
USE work.cycloneiii_atom_pack.all;
USE work.cycloneiii_pllpack.all;
USE work.cycloneiii_mn_cntr;
USE work.cycloneiii_scale_cntr;
USE work.cycloneiii_dffe;
USE work.cycloneiii_pll_reg;
-- New Features : The list below outlines key new features in CYCLONEIII:
-- 1. Dynamic Phase Reconfiguration
-- 2. Dynamic PLL Reconfiguration (different protocol)
-- 3. More output counters
ENTITY cycloneiii_pll is
GENERIC (
operation_mode : string := "normal";
pll_type : string := "auto"; -- AUTO/FAST/ENHANCED/LEFT_RIGHT/TOP_BOTTOM
compensate_clock : string := "clock0";
inclk0_input_frequency : integer := 0;
inclk1_input_frequency : integer := 0;
self_reset_on_loss_lock : string := "off";
switch_over_type : string := "auto";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "off";
bandwidth : integer := 0;
bandwidth_type : string := "auto";
use_dc_coupling : string := "false";
lock_c : integer := 4;
sim_gate_lock_device_behavior : string := "off";
lock_high : integer := 0;
lock_low : integer := 0;
lock_window_ui : string := "0.05";
lock_window : time := 5 ps;
test_bypass_lock_detect : string := "off";
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 0;
clk0_divide_by : integer := 0;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 0;
clk1_divide_by : integer := 0;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 0;
clk2_divide_by : integer := 0;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 0;
clk3_divide_by : integer := 0;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 0;
clk4_divide_by : integer := 0;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
-- ADVANCED USER PARAMETERS
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "unused";
clk1_counter : string := "unused";
clk2_counter : string := "unused";
clk3_counter : string := "unused";
clk4_counter : string := "unused";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
m_test_source : integer := -1;
c0_test_source : integer := -1;
c1_test_source : integer := -1;
c2_test_source : integer := -1;
c3_test_source : integer := -1;
c4_test_source : integer := -1;
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
vco_post_scale : integer := 1;
vco_frequency_control : string := "auto";
vco_phase_shift_step : integer := 0;
charge_pump_current : integer := 10;
loop_filter_r : string := "1.0";
loop_filter_c : integer := 0;
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
lpm_type : string := "cycloneiii_pll";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
-- Test only
init_block_reset_a_count : integer := 1;
init_block_reset_b_count : integer := 1;
charge_pump_current_bits : integer := 0;
lock_window_ui_bits : integer := 0;
loop_filter_c_bits : integer := 0;
loop_filter_r_bits : integer := 0;
test_counter_c0_delay_chain_bits : integer := 0;
test_counter_c1_delay_chain_bits : integer := 0;
test_counter_c2_delay_chain_bits : integer := 0;
test_counter_c3_delay_chain_bits : integer := 0;
test_counter_c4_delay_chain_bits : integer := 0;
test_counter_c5_delay_chain_bits : integer := 0;
test_counter_m_delay_chain_bits : integer := 0;
test_counter_n_delay_chain_bits : integer := 0;
test_feedback_comp_delay_chain_bits : integer := 0;
test_input_comp_delay_chain_bits : integer := 0;
test_volt_reg_output_mode_bits : integer := 0;
test_volt_reg_output_voltage_bits : integer := 0;
test_volt_reg_test_mode : string := "false";
vco_range_detector_high_bits : integer := 0;
vco_range_detector_low_bits : integer := 0;
-- Simulation only generics
family_name : string := "Cyclone III";
-- VITAL generics
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanclkena : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_configupdate : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01;
tipd_phaseupdown : VitalDelayType01 := DefPropDelay01;
tipd_phasecounterselect : VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phasestep : VitalDelayType01 := DefPropDelay01;
tsetup_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
use_vco_bypass : string := "false"
);
PORT
(
inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
fbout : out std_logic;
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
scanclkena : in std_logic := '0';
configupdate : in std_logic := '0';
clk : out std_logic_vector(4 downto 0);
phasecounterselect : in std_logic_vector(2 downto 0) := "000";
phaseupdown : in std_logic := '0';
phasestep : in std_logic := '0';
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
phasedone : out std_logic;
vcooverrange : out std_logic;
vcounderrange : out std_logic
);
END cycloneiii_pll;
ARCHITECTURE vital_pll of cycloneiii_pll is
TYPE int_array is ARRAY(NATURAL RANGE <>) of integer;
TYPE str_array is ARRAY(NATURAL RANGE <>) of string(1 to 6);
TYPE str_array1 is ARRAY(NATURAL RANGE <>) of string(1 to 9);
TYPE std_logic_array is ARRAY(NATURAL RANGE <>) of std_logic;
-- internal advanced parameter signals
signal i_vco_min : integer;
signal i_vco_max : integer;
signal i_vco_center : integer;
signal i_pfd_min : integer;
signal i_pfd_max : integer;
signal c_ph_val : int_array(0 to 4) := (OTHERS => 0);
signal c_ph_val_tmp : int_array(0 to 4) := (OTHERS => 0);
signal c_high_val : int_array(0 to 4) := (OTHERS => 1);
signal c_low_val : int_array(0 to 4) := (OTHERS => 1);
signal c_initial_val : int_array(0 to 4) := (OTHERS => 1);
signal c_mode_val : str_array(0 to 4);
-- old values
signal c_high_val_old : int_array(0 to 4) := (OTHERS => 1);
signal c_low_val_old : int_array(0 to 4) := (OTHERS => 1);
signal c_ph_val_old : int_array(0 to 4) := (OTHERS => 0);
signal c_mode_val_old : str_array(0 to 4);
-- hold registers
signal c_high_val_hold : int_array(0 to 4) := (OTHERS => 1);
signal c_low_val_hold : int_array(0 to 4) := (OTHERS => 1);
signal c_ph_val_hold : int_array(0 to 4) := (OTHERS => 0);
signal c_mode_val_hold : str_array(0 to 4);
-- temp registers
signal sig_c_ph_val_tmp : int_array(0 to 4) := (OTHERS => 0);
signal c_ph_val_orig : int_array(0 to 4) := (OTHERS => 0);
signal real_lock_high : integer := 0;
signal i_clk4_counter : integer := 4;
signal i_clk3_counter : integer := 3;
signal i_clk2_counter : integer := 2;
signal i_clk1_counter : integer := 1;
signal i_clk0_counter : integer := 0;
signal i_charge_pump_current : integer;
signal i_loop_filter_r : integer;
-- end internal advanced parameter signals
-- CONSTANTS
CONSTANT SCAN_CHAIN : integer := 144;
CONSTANT GPP_SCAN_CHAIN : integer := 234;
CONSTANT FAST_SCAN_CHAIN : integer := 180;
CONSTANT cntrs : str_array(4 downto 0) := (" C4", " C3", " C2", " C1", " C0");
CONSTANT ss_cntrs : str_array(0 to 3) := (" M", " M2", " N", " N2");
CONSTANT loop_filter_c_arr : int_array(0 to 3) := (0,0,0,0);
CONSTANT fpll_loop_filter_c_arr : int_array(0 to 3) := (0,0,0,0);
CONSTANT charge_pump_curr_arr : int_array(0 to 15) := (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0);
CONSTANT num_phase_taps : integer := 8;
-- signals
signal vcc : std_logic := '1';
signal fbclk : std_logic;
signal refclk : std_logic;
signal vco_over : std_logic := '0';
signal vco_under : std_logic := '1';
signal pll_locked : boolean := false;
signal c_clk : std_logic_array(0 to 4);
signal vco_out : std_logic_vector(7 downto 0) := (OTHERS => '0');
-- signals to assign values to counter params
signal m_val : integer := 1;
signal n_val : integer := 1;
signal m_ph_val : integer := 0;
signal m_ph_initial : integer := 0;
signal m_ph_val_tmp : integer := 0;
signal m_initial_val : integer := m_initial;
signal m_mode_val : string(1 to 6) := " ";
signal n_mode_val : string(1 to 6) := " ";
signal lfc_val : integer := 0;
signal cp_curr_val : integer := 0;
signal lfr_val : string(1 to 2) := " ";
signal cp_curr_old_bit_setting : std_logic_vector(14 to 16) := (OTHERS => '0');
signal cp_curr_val_bit_setting : std_logic_vector(14 to 16) := (OTHERS => '0');
signal lfr_old_bit_setting : std_logic_vector(3 to 7) := (OTHERS => '0');
signal lfr_val_bit_setting : std_logic_vector(3 to 7) := (OTHERS => '0');
signal lfc_old_bit_setting : std_logic_vector(1 to 2) := (OTHERS => '0');
signal lfc_val_bit_setting : std_logic_vector(1 to 2) := (OTHERS => '0');
signal pll_reconfig_display_full_setting : boolean := FALSE; -- display full setting, change to true
-- old values
signal m_val_old : integer := 1;
signal n_val_old : integer := 1;
signal m_mode_val_old : string(1 to 6) := " ";
signal n_mode_val_old : string(1 to 6) := " ";
signal m_ph_val_old : integer := 0;
signal lfc_old : integer := 0;
signal cp_curr_old : integer := 0;
signal lfr_old : string(1 to 2) := " ";
signal num_output_cntrs : integer := 5;
signal scanclk_period : time := 1 ps;
signal scan_data : std_logic_vector(0 to 143) := (OTHERS => '0');
signal clk_pfd : std_logic_vector(0 to 4);
signal clk0_tmp : std_logic;
signal clk1_tmp : std_logic;
signal clk2_tmp : std_logic;
signal clk3_tmp : std_logic;
signal clk4_tmp : std_logic;
signal update_conf_latches : std_logic := '0';
signal update_conf_latches_reg : std_logic := '0';
signal clkin : std_logic := '0';
signal gate_locked : std_logic := '0';
signal pfd_locked : std_logic := '0';
signal lock : std_logic := '0';
signal about_to_lock : boolean := false;
signal reconfig_err : boolean := false;
signal inclk_c0 : std_logic;
signal inclk_c1 : std_logic;
signal inclk_c2 : std_logic;
signal inclk_c3 : std_logic;
signal inclk_c4 : std_logic;
signal inclk_m : std_logic;
signal devpor : std_logic;
signal devclrn : std_logic;
signal inclk0_ipd : std_logic;
signal inclk1_ipd : std_logic;
signal pfdena_ipd : std_logic;
signal areset_ipd : std_logic;
signal fbin_ipd : std_logic;
signal scanclk_ipd : std_logic;
signal scanclkena_ipd, scanclkena_reg : std_logic;
signal scandata_ipd : std_logic;
signal clkswitch_ipd : std_logic;
signal phasecounterselect_ipd : std_logic_vector(2 downto 0);
signal phaseupdown_ipd : std_logic;
signal phasestep_ipd : std_logic;
signal configupdate_ipd : std_logic;
-- registered signals
signal sig_offset : time := 0 ps;
signal sig_refclk_time : time := 0 ps;
signal sig_fbclk_period : time := 0 ps;
signal sig_vco_period_was_phase_adjusted : boolean := false;
signal sig_phase_adjust_was_scheduled : boolean := false;
signal sig_stop_vco : std_logic := '0';
signal sig_m_times_vco_period : time := 0 ps;
signal sig_new_m_times_vco_period : time := 0 ps;
signal sig_got_refclk_posedge : boolean := false;
signal sig_got_fbclk_posedge : boolean := false;
signal sig_got_second_refclk : boolean := false;
signal m_delay : integer := 0;
signal n_delay : integer := 0;
signal inclk1_tmp : std_logic := '0';
signal reset_low : std_logic := '0';
-- Phase Reconfig
SIGNAL phasecounterselect_reg : std_logic_vector(2 DOWNTO 0);
SIGNAL phaseupdown_reg : std_logic := '0';
SIGNAL phasestep_reg : std_logic := '0';
SIGNAL phasestep_high_count : integer := 0;
SIGNAL update_phase : std_logic := '0';
signal scandataout_tmp : std_logic := '0';
signal scandata_in : std_logic := '0';
signal scandata_out : std_logic := '0';
signal scandone_tmp : std_logic := '1';
signal initiate_reconfig : std_logic := '0';
signal sig_refclk_period : time := (inclk0_input_frequency * 1 ps) * n;
signal schedule_vco : std_logic := '0';
signal areset_ena_sig : std_logic := '0';
signal pll_in_test_mode : boolean := false;
signal inclk_c_from_vco : std_logic_array(0 to 4);
signal inclk_m_from_vco : std_logic;
COMPONENT cycloneiii_mn_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END COMPONENT;
COMPONENT cycloneiii_scale_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
ph_tap : IN integer := 0
);
END COMPONENT;
COMPONENT cycloneiii_dffe
GENERIC(
TimingChecksOn: Boolean := true;
InstancePath: STRING := "*";
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
COMPONENT cycloneiii_pll_reg
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (inclk0_ipd, inclk(0), tipd_inclk(0));
VitalWireDelay (inclk1_ipd, inclk(1), tipd_inclk(1));
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (pfdena_ipd, pfdena, tipd_pfdena);
VitalWireDelay (scanclk_ipd, scanclk, tipd_scanclk);
VitalWireDelay (scanclkena_ipd, scanclkena, tipd_scanclkena);
VitalWireDelay (scandata_ipd, scandata, tipd_scandata);
VitalWireDelay (configupdate_ipd, configupdate, tipd_configupdate);
VitalWireDelay (clkswitch_ipd, clkswitch, tipd_clkswitch);
VitalWireDelay (phaseupdown_ipd, phaseupdown, tipd_phaseupdown);
VitalWireDelay (phasestep_ipd, phasestep, tipd_phasestep);
VitalWireDelay (phasecounterselect_ipd(0), phasecounterselect(0), tipd_phasecounterselect(0));
VitalWireDelay (phasecounterselect_ipd(1), phasecounterselect(1), tipd_phasecounterselect(1));
VitalWireDelay (phasecounterselect_ipd(2), phasecounterselect(2), tipd_phasecounterselect(2));
end block;
inclk_m <= fbclk when m_test_source = 0 else
refclk when m_test_source = 1 else
inclk_m_from_vco;
areset_ena_sig <= areset_ipd or sig_stop_vco;
pll_in_test_mode <= true when (m_test_source /= -1 or c0_test_source /= -1 or
c1_test_source /= -1 or c2_test_source /= -1 or
c3_test_source /= -1 or c4_test_source /= -1)
else false;
real_lock_high <= lock_high WHEN (sim_gate_lock_device_behavior = "on") ELSE 0;
m1 : cycloneiii_mn_cntr
port map ( clk => inclk_m,
reset => areset_ena_sig,
cout => fbclk,
initial_value => m_initial_val,
modulus => m_val,
time_delay => m_delay
);
-- add delta delay to inclk1 to ensure inclk0 and inclk1 are processed
-- in different simulation deltas.
inclk1_tmp <= inclk1_ipd;
process (inclk0_ipd, inclk1_tmp, clkswitch_ipd)
variable input_value : std_logic := '0';
variable current_clock : integer := 0;
variable clk0_count, clk1_count : integer := 0;
variable clk0_is_bad, clk1_is_bad : std_logic := '0';
variable primary_clk_is_bad : boolean := false;
variable current_clk_is_bad : boolean := false;
variable got_curr_clk_falling_edge_after_clkswitch : boolean := false;
variable switch_over_count : integer := 0;
variable active_clock : std_logic := '0';
variable external_switch : boolean := false;
begin
if (now = 0 ps) then
if (switch_over_type = "manual" and clkswitch_ipd = '1') then
current_clock := 1;
active_clock := '1';
end if;
end if;
if (clkswitch_ipd'event and clkswitch_ipd = '1' and switch_over_type = "auto") then
external_switch := true;
elsif (switch_over_type = "manual") then
if (clkswitch_ipd'event and clkswitch_ipd = '1') then
if (current_clock = 0) then
current_clock := 1;
active_clock := '1';
clkin <= transport inclk1_tmp;
elsif (current_clock = 1) then
current_clock := 0;
active_clock := '0';
clkin <= transport inclk0_ipd;
end if;
end if;
end if;
-- save the current inclk event value
if (inclk0_ipd'event) then
input_value := inclk0_ipd;
elsif (inclk1_tmp'event) then
input_value := inclk1_tmp;
end if;
-- check if either input clk is bad
if (inclk0_ipd'event and inclk0_ipd = '1') then
clk0_count := clk0_count + 1;
clk0_is_bad := '0';
clk1_count := 0;
if (clk0_count > 2) then
-- no event on other clk for 2 cycles
clk1_is_bad := '1';
if (current_clock = 1) then
current_clk_is_bad := true;
end if;
end if;
end if;
if (inclk1_tmp'event and inclk1_tmp = '1') then
clk1_count := clk1_count + 1;
clk1_is_bad := '0';
clk0_count := 0;
if (clk1_count > 2) then
-- no event on other clk for 2 cycles
clk0_is_bad := '1';
if (current_clock = 0) then
current_clk_is_bad := true;
end if;
end if;
end if;
-- check if the bad clk is the primary clock
if (clk0_is_bad = '1') then
primary_clk_is_bad := true;
else
primary_clk_is_bad := false;
end if;
-- actual switching
if (inclk0_ipd'event and current_clock = 0) then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk0_ipd = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk0_ipd;
end if;
else
clkin <= transport inclk0_ipd;
end if;
elsif (inclk1_tmp'event and current_clock = 1) then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk1_tmp = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk1_tmp;
end if;
else
clkin <= transport inclk1_tmp;
end if;
else
if (input_value = '1' and enable_switch_over_counter = "on" and primary_clk_is_bad) then
switch_over_count := switch_over_count + 1;
end if;
if (input_value = '0') then
if (external_switch and (got_curr_clk_falling_edge_after_clkswitch or current_clk_is_bad)) or (primary_clk_is_bad and clkswitch_ipd /= '1' and (enable_switch_over_counter = "off" or switch_over_count = switch_over_counter)) then
got_curr_clk_falling_edge_after_clkswitch := false;
if (current_clock = 0) then
current_clock := 1;
else
current_clock := 0;
end if;
active_clock := not active_clock;
switch_over_count := 0;
external_switch := false;
current_clk_is_bad := false;
end if;
end if;
end if;
-- schedule outputs
clkbad(0) <= clk0_is_bad;
clkbad(1) <= clk1_is_bad;
activeclock <= active_clock;
end process;
n1 : cycloneiii_mn_cntr
port map (
clk => clkin,
reset => areset_ipd,
cout => refclk,
initial_value => n_val,
modulus => n_val);
inclk_c0 <= refclk when c0_test_source = 1 else
fbclk when c0_test_source = 0 else
inclk_c_from_vco(0);
c0 : cycloneiii_scale_cntr
port map (
clk => inclk_c0,
reset => areset_ena_sig,
cout => c_clk(0),
initial => c_initial_val(0),
high => c_high_val(0),
low => c_low_val(0),
mode => c_mode_val(0),
ph_tap => c_ph_val(0));
inclk_c1 <= refclk when c1_test_source = 1 else
fbclk when c1_test_source = 0 else
c_clk(0) when c1_use_casc_in = "on" else
inclk_c_from_vco(1);
c1 : cycloneiii_scale_cntr
port map (
clk => inclk_c1,
reset => areset_ena_sig,
cout => c_clk(1),
initial => c_initial_val(1),
high => c_high_val(1),
low => c_low_val(1),
mode => c_mode_val(1),
ph_tap => c_ph_val(1));
inclk_c2 <= refclk when c2_test_source = 1 else
fbclk when c2_test_source = 0 else
c_clk(1) when c2_use_casc_in = "on" else
inclk_c_from_vco(2);
c2 : cycloneiii_scale_cntr
port map (
clk => inclk_c2,
reset => areset_ena_sig,
cout => c_clk(2),
initial => c_initial_val(2),
high => c_high_val(2),
low => c_low_val(2),
mode => c_mode_val(2),
ph_tap => c_ph_val(2));
inclk_c3 <= refclk when c3_test_source = 1 else
fbclk when c3_test_source = 0 else
c_clk(2) when c3_use_casc_in = "on" else
inclk_c_from_vco(3);
c3 : cycloneiii_scale_cntr
port map (
clk => inclk_c3,
reset => areset_ena_sig,
cout => c_clk(3),
initial => c_initial_val(3),
high => c_high_val(3),
low => c_low_val(3),
mode => c_mode_val(3),
ph_tap => c_ph_val(3));
inclk_c4 <= refclk when c4_test_source = 1 else
fbclk when c4_test_source = 0 else
c_clk(3) when (c4_use_casc_in = "on") else
inclk_c_from_vco(4);
c4 : cycloneiii_scale_cntr
port map (
clk => inclk_c4,
reset => areset_ena_sig,
cout => c_clk(4),
initial => c_initial_val(4),
high => c_high_val(4),
low => c_low_val(4),
mode => c_mode_val(4),
ph_tap => c_ph_val(4));
process(inclk_c0, inclk_c1, areset_ipd, sig_stop_vco)
variable c0_got_first_rising_edge : boolean := false;
variable c0_count : integer := 2;
variable c0_initial_count : integer := 1;
variable c0_tmp, c1_tmp : std_logic := '0';
variable c1_got_first_rising_edge : boolean := false;
variable c1_count : integer := 2;
variable c1_initial_count : integer := 1;
begin
if (areset_ipd = '1' or sig_stop_vco = '1') then
c0_count := 2;
c1_count := 2;
c0_initial_count := 1;
c1_initial_count := 1;
c0_got_first_rising_edge := false;
c1_got_first_rising_edge := false;
else
if (not c0_got_first_rising_edge) then
if (inclk_c0'event and inclk_c0 = '1') then
if (c0_initial_count = c_initial_val(0)) then
c0_got_first_rising_edge := true;
else
c0_initial_count := c0_initial_count + 1;
end if;
end if;
elsif (inclk_c0'event) then
c0_count := c0_count + 1;
if (c0_count = (c_high_val(0) + c_low_val(0)) * 2) then
c0_count := 1;
end if;
end if;
if (inclk_c0'event and inclk_c0 = '0') then
if (c0_count = 1) then
c0_tmp := '1';
c0_got_first_rising_edge := false;
else
c0_tmp := '0';
end if;
end if;
if (not c1_got_first_rising_edge) then
if (inclk_c1'event and inclk_c1 = '1') then
if (c1_initial_count = c_initial_val(1)) then
c1_got_first_rising_edge := true;
else
c1_initial_count := c1_initial_count + 1;
end if;
end if;
elsif (inclk_c1'event) then
c1_count := c1_count + 1;
if (c1_count = (c_high_val(1) + c_low_val(1)) * 2) then
c1_count := 1;
end if;
end if;
if (inclk_c1'event and inclk_c1 = '0') then
if (c1_count = 1) then
c1_tmp := '1';
c1_got_first_rising_edge := false;
else
c1_tmp := '0';
end if;
end if;
end if;
end process;
locked <= pfd_locked WHEN (test_bypass_lock_detect = "on") ELSE
lock;
process (scandone_tmp)
variable buf : line;
begin
if (scandone_tmp'event and scandone_tmp = '1') then
if (reconfig_err = false) then
ASSERT false REPORT "PLL Reprogramming completed with the following values (Values in parantheses indicate values before reprogramming) :" severity note;
write (buf, string'(" N modulus = "));
write (buf, n_val);
write (buf, string'(" ( "));
write (buf, n_val_old);
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" M modulus = "));
write (buf, m_val);
write (buf, string'(" ( "));
write (buf, m_val_old);
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" M ph_tap = "));
write (buf, m_ph_val);
write (buf, string'(" ( "));
write (buf, m_ph_val_old);
write (buf, string'(" )"));
writeline (output, buf);
for i in 0 to (num_output_cntrs-1) loop
write (buf, cntrs(i));
write (buf, string'(" : high = "));
write (buf, c_high_val(i));
write (buf, string'(" ("));
write (buf, c_high_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , low = "));
write (buf, c_low_val(i));
write (buf, string'(" ("));
write (buf, c_low_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , mode = "));
write (buf, c_mode_val(i));
write (buf, string'(" ("));
write (buf, c_mode_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , phase tap = "));
write (buf, c_ph_val(i));
write (buf, string'(" ("));
write (buf, c_ph_val_old(i));
write (buf, string'(") "));
writeline(output, buf);
end loop;
IF (pll_reconfig_display_full_setting) THEN
write (buf, string'(" Charge Pump Current (uA) = "));
write (buf, cp_curr_val);
write (buf, string'(" ( "));
write (buf, cp_curr_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Capacitor (pF) = "));
write (buf, lfc_val);
write (buf, string'(" ( "));
write (buf, lfc_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Resistor (Kohm) = "));
write (buf, lfr_val);
write (buf, string'(" ( "));
write (buf, lfr_old);
write (buf, string'(" ) "));
writeline (output, buf);
ELSE
write (buf, string'(" Charge Pump Current (bit setting) = "));
write (buf, alt_conv_integer(cp_curr_val_bit_setting));
write (buf, string'(" ( "));
write (buf, alt_conv_integer(cp_curr_old_bit_setting));
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Capacitor (bit setting) = "));
write (buf, alt_conv_integer(lfc_val_bit_setting));
write (buf, string'(" ( "));
write (buf, alt_conv_integer(lfc_old_bit_setting));
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Resistor (bit setting) = "));
write (buf, alt_conv_integer(lfr_val_bit_setting));
write (buf, string'(" ( "));
write (buf, alt_conv_integer(lfr_old_bit_setting));
write (buf, string'(" ) "));
writeline (output, buf);
END IF;
cp_curr_old_bit_setting <= cp_curr_val_bit_setting;
lfc_old_bit_setting <= lfc_val_bit_setting;
lfr_old_bit_setting <= lfr_val_bit_setting;
else ASSERT false REPORT "Errors were encountered during PLL reprogramming. Please refer to error/warning messages above." severity warning;
end if;
end if;
end process;
update_conf_latches <= configupdate_ipd;
process (scandone_tmp,areset_ipd,update_conf_latches, c_clk(0), c_clk(1), c_clk(2), c_clk(3), c_clk(4), vco_out, fbclk, scanclk_ipd)
variable init : boolean := true;
variable low, high : std_logic_vector(7 downto 0);
variable low_fast, high_fast : std_logic_vector(3 downto 0);
variable mode : string(1 to 6) := "bypass";
variable is_error : boolean := false;
variable m_tmp, n_tmp : std_logic_vector(8 downto 0);
variable lfr_val_tmp : string(1 to 2) := " ";
variable c_high_val_tmp,c_hval : int_array(0 to 4) := (OTHERS => 1);
variable c_low_val_tmp,c_lval : int_array(0 to 4) := (OTHERS => 1);
variable c_mode_val_tmp : str_array(0 to 4);
variable m_val_tmp : integer := 0;
variable c0_rising_edge_transfer_done : boolean := false;
variable c1_rising_edge_transfer_done : boolean := false;
variable c2_rising_edge_transfer_done : boolean := false;
variable c3_rising_edge_transfer_done : boolean := false;
variable c4_rising_edge_transfer_done : boolean := false;
-- variables for scaling of multiply_by and divide_by values
variable i_clk0_mult_by : integer := 1;
variable i_clk0_div_by : integer := 1;
variable i_clk1_mult_by : integer := 1;
variable i_clk1_div_by : integer := 1;
variable i_clk2_mult_by : integer := 1;
variable i_clk2_div_by : integer := 1;
variable i_clk3_mult_by : integer := 1;
variable i_clk3_div_by : integer := 1;
variable i_clk4_mult_by : integer := 1;
variable i_clk4_div_by : integer := 1;
variable max_d_value : integer := 1;
variable new_multiplier : integer := 1;
-- internal variables for storing the phase shift number.(used in lvds mode only)
variable i_clk0_phase_shift : integer := 1;
variable i_clk1_phase_shift : integer := 1;
variable i_clk2_phase_shift : integer := 1;
-- user to advanced variables
variable max_neg_abs : integer := 0;
variable i_m_initial : integer;
variable i_m : integer := 1;
variable i_n : integer := 1;
variable i_c_high : int_array(0 to 4);
variable i_c_low : int_array(0 to 4);
variable i_c_initial : int_array(0 to 4);
variable i_c_ph : int_array(0 to 4);
variable i_c_mode : str_array(0 to 4);
variable i_m_ph : integer;
variable output_count : integer;
variable new_divisor : integer;
variable clk0_cntr : string(1 to 6) := " c0";
variable clk1_cntr : string(1 to 6) := " c1";
variable clk2_cntr : string(1 to 6) := " c2";
variable clk3_cntr : string(1 to 6) := " c3";
variable clk4_cntr : string(1 to 6) := " c4";
variable fbk_cntr : string(1 to 2);
variable fbk_cntr_index : integer;
variable start_bit : integer;
variable quiet_time : time := 0 ps;
variable slowest_clk_old : time := 0 ps;
variable slowest_clk_new : time := 0 ps;
variable i : integer := 0;
variable j : integer := 0;
variable scanread_active_edge : time := 0 ps;
variable got_first_scanclk : boolean := false;
variable scanclk_last_rising_edge : time := 0 ps;
variable current_scan_data : std_logic_vector(0 to 143) := (OTHERS => '0');
variable index : integer := 0;
variable Tviol_scandata_scanclk : std_ulogic := '0';
variable TimingData_scandata_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_scanclkena_scanclk : std_ulogic := '0';
variable TimingData_scanclkena_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable scan_chain_length : integer := GPP_SCAN_CHAIN;
variable tmp_rem : integer := 0;
variable scanclk_cycles : integer := 0;
variable lfc_tmp : std_logic_vector(1 downto 0);
variable lfr_tmp : std_logic_vector(5 downto 0);
variable lfr_int : integer := 0;
variable n_hi,n_lo,m_hi,m_lo : std_logic_vector(7 downto 0);
variable buf : line;
variable buf_scan_data : STD_LOGIC_VECTOR(0 TO 1) := (OTHERS => '0');
variable buf_scan_data_2 : STD_LOGIC_VECTOR(0 TO 2) := (OTHERS => '0');
function slowest_clk (
C0 : integer; C0_mode : string(1 to 6);
C1 : integer; C1_mode : string(1 to 6);
C2 : integer; C2_mode : string(1 to 6);
C3 : integer; C3_mode : string(1 to 6);
C4 : integer; C4_mode : string(1 to 6);
C5 : integer; C5_mode : string(1 to 6);
C6 : integer; C6_mode : string(1 to 6);
C7 : integer; C7_mode : string(1 to 6);
C8 : integer; C8_mode : string(1 to 6);
C9 : integer; C9_mode : string(1 to 6);
refclk : time; m_mod : integer) return time is
variable max_modulus : integer := 1;
variable q_period : time := 0 ps;
variable refclk_int : integer := 0;
begin
if (C0_mode /= "bypass" and C0_mode /= " off") then
max_modulus := C0;
end if;
if (C1 > max_modulus and C1_mode /= "bypass" and C1_mode /= " off") then
max_modulus := C1;
end if;
if (C2 > max_modulus and C2_mode /= "bypass" and C2_mode /= " off") then
max_modulus := C2;
end if;
if (C3 > max_modulus and C3_mode /= "bypass" and C3_mode /= " off") then
max_modulus := C3;
end if;
if (C4 > max_modulus and C4_mode /= "bypass" and C4_mode /= " off") then
max_modulus := C4;
end if;
if (C5 > max_modulus and C5_mode /= "bypass" and C5_mode /= " off") then
max_modulus := C5;
end if;
if (C6 > max_modulus and C6_mode /= "bypass" and C6_mode /= " off") then
max_modulus := C6;
end if;
if (C7 > max_modulus and C7_mode /= "bypass" and C7_mode /= " off") then
max_modulus := C7;
end if;
if (C8 > max_modulus and C8_mode /= "bypass" and C8_mode /= " off") then
max_modulus := C8;
end if;
if (C9 > max_modulus and C9_mode /= "bypass" and C9_mode /= " off") then
max_modulus := C9;
end if;
refclk_int := refclk / 1 ps;
if (m_mod /= 0) then
q_period := (refclk_int * max_modulus / m_mod) * 1 ps;
end if;
return (2*q_period);
end slowest_clk;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function extract_cntr_string (arg:string) return string is
variable str : string(1 to 6) := " c0";
begin
if (arg = "c0") then
str := " c0";
elsif (arg = "c1") then
str := " c1";
elsif (arg = "c2") then
str := " c2";
elsif (arg = "c3") then
str := " c3";
elsif (arg = "c4") then
str := " c4";
elsif (arg = "c5") then
str := " c5";
elsif (arg = "c6") then
str := " c6";
elsif (arg = "c7") then
str := " c7";
elsif (arg = "c8") then
str := " c8";
elsif (arg = "c9") then
str := " c9";
else str := " c0";
end if;
return str;
end extract_cntr_string;
function extract_cntr_index (arg:string) return integer is
variable index : integer := 0;
begin
if (arg(6) = '0') then
index := 0;
elsif (arg(6) = '1') then
index := 1;
elsif (arg(6) = '2') then
index := 2;
elsif (arg(6) = '3') then
index := 3;
elsif (arg(6) = '4') then
index := 4;
elsif (arg(6) = '5') then
index := 5;
elsif (arg(6) = '6') then
index := 6;
elsif (arg(6) = '7') then
index := 7;
elsif (arg(6) = '8') then
index := 8;
else index := 9;
end if;
return index;
end extract_cntr_index;
begin
IF (areset_ipd'EVENT AND areset_ipd = '1') then
c_ph_val <= i_c_ph;
END IF;
if (init) then
if (m = 0) then
clk4_cntr := " c4";
clk3_cntr := " c3";
clk2_cntr := " c2";
clk1_cntr := " c1";
clk0_cntr := " c0";
else
clk4_cntr := extract_cntr_string(clk4_counter);
clk3_cntr := extract_cntr_string(clk3_counter);
clk2_cntr := extract_cntr_string(clk2_counter);
clk1_cntr := extract_cntr_string(clk1_counter);
clk0_cntr := extract_cntr_string(clk0_counter);
end if;
i_clk0_counter <= extract_cntr_index(clk0_cntr);
i_clk1_counter <= extract_cntr_index(clk1_cntr);
i_clk2_counter <= extract_cntr_index(clk2_cntr);
i_clk3_counter <= extract_cntr_index(clk3_cntr);
i_clk4_counter <= extract_cntr_index(clk4_cntr);
if (m = 0) then -- convert user parameters to advanced
-- set the limit of the divide_by value that can be returned by
-- the following function.
max_d_value := 500;
-- scale down the multiply_by and divide_by values provided by the design
-- before attempting to use them in the calculations below
find_simple_integer_fraction(clk0_multiply_by, clk0_divide_by,
max_d_value, i_clk0_mult_by, i_clk0_div_by);
find_simple_integer_fraction(clk1_multiply_by, clk1_divide_by,
max_d_value, i_clk1_mult_by, i_clk1_div_by);
find_simple_integer_fraction(clk2_multiply_by, clk2_divide_by,
max_d_value, i_clk2_mult_by, i_clk2_div_by);
find_simple_integer_fraction(clk3_multiply_by, clk3_divide_by,
max_d_value, i_clk3_mult_by, i_clk3_div_by);
find_simple_integer_fraction(clk4_multiply_by, clk4_divide_by,
max_d_value, i_clk4_mult_by, i_clk4_div_by);
if (vco_frequency_control = "manual_phase") then
find_m_and_n_4_manual_phase(inclk0_input_frequency, vco_phase_shift_step,
i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by,
1,1,1,1,1,
i_clk0_div_by, i_clk1_div_by,
i_clk2_div_by, i_clk3_div_by,
i_clk4_div_by,
1,1,1,1,1,
i_m, i_n);
elsif (((pll_type = "fast") or (pll_type = "lvds") OR (pll_type = "left_right")) and ((vco_multiply_by /= 0) and (vco_divide_by /= 0))) then
i_n := vco_divide_by;
i_m := vco_multiply_by;
else
i_n := 1;
if (((pll_type = "fast") or (pll_type = "left_right")) and (compensate_clock = "lvdsclk")) then
i_m := i_clk0_mult_by;
else
i_m := lcm (i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by,
1,1,1,1,1,
inclk0_input_frequency);
end if;
end if;
if (pll_type = "flvds") then
-- Need to readjust phase shift values when the clock multiply value has been readjusted.
new_multiplier := clk0_multiply_by / i_clk0_mult_by;
i_clk0_phase_shift := str2int(clk0_phase_shift) * new_multiplier;
i_clk1_phase_shift := str2int(clk1_phase_shift) * new_multiplier;
i_clk2_phase_shift := str2int(clk2_phase_shift) * new_multiplier;
else
i_clk0_phase_shift := str2int(clk0_phase_shift);
i_clk1_phase_shift := str2int(clk1_phase_shift);
i_clk2_phase_shift := str2int(clk2_phase_shift);
end if;
max_neg_abs := maxnegabs(i_clk0_phase_shift,
i_clk1_phase_shift,
i_clk2_phase_shift,
str2int(clk3_phase_shift),
str2int(clk4_phase_shift),
0,
0,
0,
0,
0
);
i_m_ph := counter_ph(get_phase_degree(max_neg_abs,inclk0_input_frequency), i_m, i_n);
i_c_ph(0) := counter_ph(get_phase_degree(ph_adjust(i_clk0_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(1) := counter_ph(get_phase_degree(ph_adjust(i_clk1_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(2) := counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(3) := counter_ph(get_phase_degree(ph_adjust(str2int(clk3_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(4) := counter_ph(get_phase_degree(ph_adjust(str2int(clk4_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_high(0) := counter_high(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_high(1) := counter_high(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_high(2) := counter_high(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_high(3) := counter_high(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_high(4) := counter_high(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_c_low(0) := counter_low(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_low(1) := counter_low(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_low(2) := counter_low(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_low(3) := counter_low(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_low(4) := counter_low(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_m_initial := counter_initial(get_phase_degree(max_neg_abs, inclk0_input_frequency), i_m,i_n);
i_c_initial(0) := counter_initial(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(1) := counter_initial(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(2) := counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(3) := counter_initial(get_phase_degree(ph_adjust(str2int(clk3_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(4) := counter_initial(get_phase_degree(ph_adjust(str2int(clk4_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_mode(0) := counter_mode(clk0_duty_cycle, output_counter_value(i_clk0_div_by, i_clk0_mult_by, i_m, i_n));
i_c_mode(1) := counter_mode(clk1_duty_cycle, output_counter_value(i_clk1_div_by, i_clk1_mult_by, i_m, i_n));
i_c_mode(2) := counter_mode(clk2_duty_cycle, output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n));
i_c_mode(3) := counter_mode(clk3_duty_cycle, output_counter_value(i_clk3_div_by, i_clk3_mult_by, i_m, i_n));
i_c_mode(4) := counter_mode(clk4_duty_cycle, output_counter_value(i_clk4_div_by, i_clk4_mult_by, i_m, i_n));
else -- m /= 0
i_n := n;
i_m := m;
i_m_initial := m_initial;
i_m_ph := m_ph;
i_c_ph(0) := c0_ph;
i_c_ph(1) := c1_ph;
i_c_ph(2) := c2_ph;
i_c_ph(3) := c3_ph;
i_c_ph(4) := c4_ph;
i_c_high(0) := c0_high;
i_c_high(1) := c1_high;
i_c_high(2) := c2_high;
i_c_high(3) := c3_high;
i_c_high(4) := c4_high;
i_c_low(0) := c0_low;
i_c_low(1) := c1_low;
i_c_low(2) := c2_low;
i_c_low(3) := c3_low;
i_c_low(4) := c4_low;
i_c_initial(0) := c0_initial;
i_c_initial(1) := c1_initial;
i_c_initial(2) := c2_initial;
i_c_initial(3) := c3_initial;
i_c_initial(4) := c4_initial;
i_c_mode(0) := translate_string(c0_mode);
i_c_mode(1) := translate_string(c1_mode);
i_c_mode(2) := translate_string(c2_mode);
i_c_mode(3) := translate_string(c3_mode);
i_c_mode(4) := translate_string(c4_mode);
end if; -- user to advanced conversion.
m_initial_val <= i_m_initial;
n_val <= i_n;
m_val <= i_m;
if (i_m = 1) then
m_mode_val <= "bypass";
else
m_mode_val <= " ";
end if;
if (i_n = 1) then
n_mode_val <= "bypass";
else
n_mode_val <= " ";
end if;
m_ph_val <= i_m_ph;
m_ph_initial <= i_m_ph;
m_val_tmp := i_m;
for i in 0 to 4 loop
if (i_c_mode(i) = "bypass") then
if (pll_type = "fast" or pll_type = "lvds" OR (pll_type = "left_right")) then
i_c_high(i) := 16;
i_c_low(i) := 16;
else
i_c_high(i) := 256;
i_c_low(i) := 256;
end if;
end if;
c_ph_val(i) <= i_c_ph(i);
c_initial_val(i) <= i_c_initial(i);
c_high_val(i) <= i_c_high(i);
c_low_val(i) <= i_c_low(i);
c_mode_val(i) <= i_c_mode(i);
c_high_val_tmp(i) := i_c_high(i);
c_hval(i) := i_c_high(i);
c_low_val_tmp(i) := i_c_low(i);
c_lval(i) := i_c_low(i);
c_mode_val_tmp(i) := i_c_mode(i);
c_ph_val_orig(i) <= i_c_ph(i);
c_high_val_hold(i) <= i_c_high(i);
c_low_val_hold(i) <= i_c_low(i);
c_mode_val_hold(i) <= i_c_mode(i);
end loop;
scan_chain_length := SCAN_CHAIN;
num_output_cntrs <= 5;
init := false;
elsif (scandone_tmp'EVENT AND scandone_tmp = '1') then
c0_rising_edge_transfer_done := false;
c1_rising_edge_transfer_done := false;
c2_rising_edge_transfer_done := false;
c3_rising_edge_transfer_done := false;
c4_rising_edge_transfer_done := false;
update_conf_latches_reg <= '0';
elsif (update_conf_latches'event and update_conf_latches = '1') then
initiate_reconfig <= '1';
elsif (areset_ipd'event AND areset_ipd = '1') then
if (scandone_tmp = '0') then scandone_tmp <= '1' AFTER scanclk_period; end if;
elsif (scanclk_ipd'event and scanclk_ipd = '1') then
IF (initiate_reconfig = '1') THEN
initiate_reconfig <= '0';
ASSERT false REPORT "PLL Reprogramming Initiated" severity note;
update_conf_latches_reg <= update_conf_latches;
reconfig_err <= false;
scandone_tmp <= '0';
cp_curr_old <= cp_curr_val;
lfc_old <= lfc_val;
lfr_old <= lfr_val;
-- LF unused : bit 0,1
-- LF Capacitance : bits 2,3 : all values are legal
buf_scan_data := scan_data(2 TO 3);
IF ((pll_type = "fast") OR (pll_type = "lvds") OR (pll_type = "left_right")) THEN
lfc_val <= fpll_loop_filter_c_arr(alt_conv_integer(buf_scan_data));
ELSE
lfc_val <= loop_filter_c_arr(alt_conv_integer(buf_scan_data));
END IF;
-- LF Resistance : bits 4-8
-- valid values - 00000,00100,10000,10100,11000,11011,11100,11110
IF (scan_data(4 TO 8) = "00000") THEN
lfr_val <= "20";
ELSIF (scan_data(4 TO 8) = "00100") THEN
lfr_val <= "16";
ELSIF (scan_data(4 TO 8) = "10000") THEN
lfr_val <= "12";
ELSIF (scan_data(4 TO 8) = "10100") THEN
lfr_val <= "08";
ELSIF (scan_data(4 TO 8) = "11000") THEN
lfr_val <= "06";
ELSIF (scan_data(4 TO 8) = "11011") THEN
lfr_val <= "04";
ELSIF (scan_data(4 TO 8) = "11100") THEN
lfr_val <= "02";
ELSE
lfr_val <= "01";
END IF;
IF (NOT (((scan_data(4 TO 8) = "00000") OR (scan_data(4 TO 8) = "00100")) OR ((scan_data(4 TO 8) = "10000") OR (scan_data(4 TO 8) = "10100")) OR ((scan_data(4 TO 8) = "11000") OR (scan_data(4 TO 8) = "11011")) OR ((scan_data(4 TO 8) = "11100") OR (scan_data(4 TO 8) = "11110")))) THEN
WRITE(buf, string'("Illegal bit settings for Loop Filter Resistance. Legal bit values range from 000000 to 001111, 011000 to 011111, 101000 to 101111 and 111000 to 111111. Reconfiguration may not work."));
writeline(output,buf);
reconfig_err <= TRUE;
END IF;
-- CP
-- Bit 9 : CRBYPASS
-- Bit 10-14 : unused
-- Bits 15-17 : all values are legal
buf_scan_data_2 := scan_data(15 TO 17);
cp_curr_val <= charge_pump_curr_arr(alt_conv_integer(buf_scan_data_2));
-- save old values for display info.
cp_curr_val_bit_setting <= scan_data(15 TO 17);
lfc_val_bit_setting <= scan_data(2 TO 3);
lfr_val_bit_setting <= scan_data(4 TO 8);
m_val_old <= m_val;
n_val_old <= n_val;
m_mode_val_old <= m_mode_val;
n_mode_val_old <= n_mode_val;
WHILE (i < num_output_cntrs) LOOP
c_high_val_old(i) <= c_high_val(i);
c_low_val_old(i) <= c_low_val(i);
c_mode_val_old(i) <= c_mode_val(i);
i := i + 1;
END LOOP;
-- M counter
-- 1. Mode - bypass (bit 18)
IF (scan_data(18) = '1') THEN
m_mode_val <= "bypass";
-- 3. Mode - odd/even (bit 27)
ELSIF (scan_data(27) = '1') THEN
m_mode_val <= " odd";
ELSE
m_mode_val <= " even";
END IF;
-- 2. High (bit 19-26)
m_hi := scan_data(19 TO 26);
-- 4. Low (bit 28-35)
m_lo := scan_data(28 TO 35);
-- N counter
-- 1. Mode - bypass (bit 36)
IF (scan_data(36) = '1') THEN
n_mode_val <= "bypass";
-- 3. Mode - odd/even (bit 45)
ELSIF (scan_data(45) = '1') THEN
n_mode_val <= " odd";
ELSE
n_mode_val <= " even";
END IF;
-- 2. High (bit 37-44)
n_hi := scan_data(37 TO 44);
-- 4. Low (bit 46-53)
n_lo := scan_data(46 TO 53);
-- C counters (start bit 54) bit 1:mode(bypass),bit 2-9:high,bit 10:mode(odd/even),bit 11-18:low
i := 0;
WHILE (i < num_output_cntrs) LOOP
-- 1. Mode - bypass
IF (scan_data(54 + i * 18 + 0) = '1') THEN
c_mode_val_tmp(i) := "bypass";
-- 3. Mode - odd/even
ELSIF (scan_data(54 + i * 18 + 9) = '1') THEN
c_mode_val_tmp(i) := " odd";
ELSE
c_mode_val_tmp(i) := " even";
END IF;
-- 2. Hi
high := scan_data(54 + i * 18 + 1 TO 54 + i * 18 + 8);
c_hval(i) := alt_conv_integer(high);
IF (c_hval(i) /= 0) THEN
c_high_val_tmp(i) := c_hval(i);
END IF;
-- 4. Low
low := scan_data(54 + i * 18 + 10 TO 54 + i * 18 + 17);
c_lval(i) := alt_conv_integer(low);
IF (c_lval(i) /= 0) THEN
c_low_val_tmp(i) := c_lval(i);
END IF;
i := i + 1;
END LOOP;
-- Legality Checks
-- M counter value
IF ((m_hi /= m_lo) AND (scan_data(18) /= '1')) THEN
reconfig_err <= TRUE;
WRITE(buf,string'("Warning : The M counter of the " & family_name & " Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work"));
writeline(output, buf);
ELSIF (m_hi /= "00000000") THEN
m_val_tmp := alt_conv_integer(m_hi) + alt_conv_integer(m_lo);
END IF;
-- N counter value
IF ((n_hi /= n_lo) AND (scan_data(36) /= '1')) THEN
reconfig_err <= TRUE;
WRITE(buf,string'("Warning : The N counter of the " & family_name & " Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work"));
writeline(output, buf);
ELSIF (n_hi /= "00000000") THEN
n_val <= alt_conv_integer(n_hi) + alt_conv_integer(n_lo);
END IF;
-- TODO : Give warnings/errors in the following cases?
-- 1. Illegal counter values (error)
-- 2. Change of mode (warning)
-- 3. Only 50% duty cycle allowed for M counter (odd mode - hi-lo=1,even - hi-lo=0)
END IF;
end if;
if (fbclk'event and fbclk = '1') then
m_val <= m_val_tmp;
end if;
if (update_conf_latches_reg = '1') then
if (scanclk_ipd'event and scanclk_ipd = '1') then
c0_rising_edge_transfer_done := true;
c_high_val(0) <= c_high_val_tmp(0);
c_mode_val(0) <= c_mode_val_tmp(0);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c1_rising_edge_transfer_done := true;
c_high_val(1) <= c_high_val_tmp(1);
c_mode_val(1) <= c_mode_val_tmp(1);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c2_rising_edge_transfer_done := true;
c_high_val(2) <= c_high_val_tmp(2);
c_mode_val(2) <= c_mode_val_tmp(2);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(3) <= c_high_val_tmp(3);
c_mode_val(3) <= c_mode_val_tmp(3);
c3_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(4) <= c_high_val_tmp(4);
c_mode_val(4) <= c_mode_val_tmp(4);
c4_rising_edge_transfer_done := true;
end if;
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c0_rising_edge_transfer_done) then
c_low_val(0) <= c_low_val_tmp(0);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c1_rising_edge_transfer_done) then
c_low_val(1) <= c_low_val_tmp(1);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c2_rising_edge_transfer_done) then
c_low_val(2) <= c_low_val_tmp(2);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c3_rising_edge_transfer_done) then
c_low_val(3) <= c_low_val_tmp(3);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c4_rising_edge_transfer_done) then
c_low_val(4) <= c_low_val_tmp(4);
end if;
if (update_phase = '1') then
if (vco_out(0)'event and vco_out(0) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 0) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 0) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(1)'event and vco_out(1) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 1) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 1) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(2)'event and vco_out(2) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 2) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 2) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(3)'event and vco_out(3) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 3) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 3) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(4)'event and vco_out(4) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 4) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 4) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(5)'event and vco_out(5) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 5) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 5) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(6)'event and vco_out(6) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 6) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 6) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(7)'event and vco_out(7) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 7) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 7) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
end if;
if (vco_out(0)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 0) then
inclk_c_from_vco(i) <= vco_out(0);
end if;
end loop;
if (m_ph_val = 0) then
inclk_m_from_vco <= vco_out(0);
end if;
end if;
if (vco_out(1)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 1) then
inclk_c_from_vco(i) <= vco_out(1);
end if;
end loop;
if (m_ph_val = 1) then
inclk_m_from_vco <= vco_out(1);
end if;
end if;
if (vco_out(2)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 2) then
inclk_c_from_vco(i) <= vco_out(2);
end if;
end loop;
if (m_ph_val = 2) then
inclk_m_from_vco <= vco_out(2);
end if;
end if;
if (vco_out(3)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 3) then
inclk_c_from_vco(i) <= vco_out(3);
end if;
end loop;
if (m_ph_val = 3) then
inclk_m_from_vco <= vco_out(3);
end if;
end if;
if (vco_out(4)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 4) then
inclk_c_from_vco(i) <= vco_out(4);
end if;
end loop;
if (m_ph_val = 4) then
inclk_m_from_vco <= vco_out(4);
end if;
end if;
if (vco_out(5)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 5) then
inclk_c_from_vco(i) <= vco_out(5);
end if;
end loop;
if (m_ph_val = 5) then
inclk_m_from_vco <= vco_out(5);
end if;
end if;
if (vco_out(6)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 6) then
inclk_c_from_vco(i) <= vco_out(6);
end if;
end loop;
if (m_ph_val = 6) then
inclk_m_from_vco <= vco_out(6);
end if;
end if;
if (vco_out(7)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 7) then
inclk_c_from_vco(i) <= vco_out(7);
end if;
end loop;
if (m_ph_val = 7) then
inclk_m_from_vco <= vco_out(7);
end if;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_scandata_scanclk,
TimingData => TimingData_scandata_scanclk,
TestSignal => scandata_ipd,
TestSignalName => "scandata",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scandata_scanclk_noedge_negedge,
SetupLow => tsetup_scandata_scanclk_noedge_negedge,
HoldHigh => thold_scandata_scanclk_noedge_negedge,
HoldLow => thold_scandata_scanclk_noedge_negedge,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/cycloneiii_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_scanclkena_scanclk,
TimingData => TimingData_scanclkena_scanclk,
TestSignal => scanclkena_ipd,
TestSignalName => "scanclkena",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scanclkena_scanclk_noedge_negedge,
SetupLow => tsetup_scanclkena_scanclk_noedge_negedge,
HoldHigh => thold_scanclkena_scanclk_noedge_negedge,
HoldLow => thold_scanclkena_scanclk_noedge_negedge,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/cycloneiii_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (scanclk_ipd'event AND scanclk_ipd = '0' AND now > 0 ps) then
scanclkena_reg <= scanclkena_ipd;
if (scanclkena_reg = '1') then
scandata_in <= scandata_ipd;
scandata_out <= scandataout_tmp;
end if;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1' and now > 0 ps) then
if (got_first_scanclk) then
scanclk_period <= now - scanclk_last_rising_edge;
else
got_first_scanclk := true;
end if;
if (scanclkena_reg = '1') then
for j in scan_chain_length - 1 downto 1 loop
scan_data(j) <= scan_data(j-1);
end loop;
scan_data(0) <= scandata_in;
end if;
scanclk_last_rising_edge := now;
end if;
end process;
-- PLL Phase Reconfiguration
PROCESS(scanclk_ipd, areset_ipd,phasestep_ipd)
VARIABLE i : INTEGER := 0;
VARIABLE c_ph : INTEGER := 0;
VARIABLE m_ph : INTEGER := 0;
VARIABLE select_counter : INTEGER := 0;
BEGIN
IF (NOW = 0 ps) THEN
m_ph_val_tmp <= m_ph_initial;
END IF;
-- Latch phase enable (same as phasestep) on neg edge of scan clock
IF (scanclk_ipd'EVENT AND scanclk_ipd = '0') THEN
phasestep_reg <= phasestep_ipd;
END IF;
IF (phasestep_ipd'EVENT and phasestep_ipd = '1') THEN
IF (update_phase = '0') THEN
phasestep_high_count <= 0; -- phase adjustments must be 1 cycle apart
-- if not, next phasestep cycle is skipped
END IF;
END IF;
-- revert counter phase tap values to POF programmed values
-- if PLL is reset
IF (areset_ipd'EVENT AND areset_ipd = '1') then
c_ph_val_tmp <= c_ph_val_orig;
m_ph_val_tmp <= m_ph_initial;
END IF;
IF (scanclk_ipd'EVENT AND scanclk_ipd = '1') THEN
IF (phasestep_reg = '1') THEN
IF (phasestep_high_count = 1) THEN
phasecounterselect_reg <= phasecounterselect_ipd;
phaseupdown_reg <= phaseupdown_ipd;
-- start reconfiguration
IF (phasecounterselect_ipd < "111") THEN -- no counters selected
IF (phasecounterselect_ipd = "000") THEN
WHILE (i < num_output_cntrs) LOOP
c_ph := c_ph_val(i);
IF (phaseupdown_ipd = '1') THEN
c_ph := (c_ph + 1) mod num_phase_taps;
ELSIF (c_ph = 0) THEN
c_ph := num_phase_taps - 1;
ELSE
c_ph := (c_ph - 1) mod num_phase_taps;
END IF;
c_ph_val_tmp(i) <= c_ph;
i := i + 1;
END LOOP;
ELSIF (phasecounterselect_ipd = "001") THEN
m_ph := m_ph_val;
IF (phaseupdown_ipd = '1') THEN
m_ph := (m_ph + 1) mod num_phase_taps;
ELSIF (m_ph = 0) THEN
m_ph := num_phase_taps - 1;
ELSE
m_ph := (m_ph - 1) mod num_phase_taps;
END IF;
m_ph_val_tmp <= m_ph;
ELSE
select_counter := alt_conv_integer(phasecounterselect_ipd) - 2;
c_ph := c_ph_val(select_counter);
IF (phaseupdown_ipd = '1') THEN
c_ph := (c_ph + 1) mod num_phase_taps;
ELSIF (c_ph = 0) THEN
c_ph := num_phase_taps - 1;
ELSE
c_ph := (c_ph - 1) mod num_phase_taps;
END IF;
c_ph_val_tmp(select_counter) <= c_ph;
END IF;
update_phase <= '1','0' AFTER (0.5 * scanclk_period);
END IF;
END IF;
phasestep_high_count <= phasestep_high_count + 1;
END IF;
END IF;
END PROCESS;
scandataout_tmp <= scan_data(SCAN_CHAIN - 2);
process (schedule_vco, areset_ipd, pfdena_ipd, refclk, fbclk)
variable sched_time : time := 0 ps;
TYPE time_array is ARRAY (0 to 7) of time;
variable init : boolean := true;
variable refclk_period : time;
variable m_times_vco_period : time;
variable new_m_times_vco_period : time;
variable phase_shift : time_array := (OTHERS => 0 ps);
variable last_phase_shift : time_array := (OTHERS => 0 ps);
variable l_index : integer := 1;
variable cycle_to_adjust : integer := 0;
variable stop_vco : boolean := false;
variable locked_tmp : std_logic := '0';
variable pll_is_locked : boolean := false;
variable cycles_pfd_low : integer := 0;
variable cycles_pfd_high : integer := 0;
variable cycles_to_lock : integer := 0;
variable cycles_to_unlock : integer := 0;
variable got_first_refclk : boolean := false;
variable got_second_refclk : boolean := false;
variable got_first_fbclk : boolean := false;
variable refclk_time : time := 0 ps;
variable fbclk_time : time := 0 ps;
variable first_fbclk_time : time := 0 ps;
variable fbclk_period : time := 0 ps;
variable first_schedule : boolean := true;
variable vco_val : std_logic := '0';
variable vco_period_was_phase_adjusted : boolean := false;
variable phase_adjust_was_scheduled : boolean := false;
variable loop_xplier : integer;
variable loop_initial : integer := 0;
variable loop_ph : integer := 0;
variable loop_time_delay : integer := 0;
variable initial_delay : time := 0 ps;
variable vco_per : time;
variable tmp_rem : integer;
variable my_rem : integer;
variable fbk_phase : integer := 0;
variable pull_back_M : integer := 0;
variable total_pull_back : integer := 0;
variable fbk_delay : integer := 0;
variable offset : time := 0 ps;
variable tmp_vco_per : integer := 0;
variable high_time : time;
variable low_time : time;
variable got_refclk_posedge : boolean := false;
variable got_fbclk_posedge : boolean := false;
variable inclk_out_of_range : boolean := false;
variable no_warn : boolean := false;
variable ext_fbk_cntr_modulus : integer := 1;
variable init_clks : boolean := true;
variable pll_is_in_reset : boolean := false;
variable buf : line;
begin
if (init) then
-- jump-start the VCO
-- add 1 ps delay to ensure all signals are updated to initial
-- values
schedule_vco <= transport not schedule_vco after 1 ps;
init := false;
end if;
if (schedule_vco'event) then
if (init_clks) then
refclk_period := inclk0_input_frequency * n_val * 1 ps;
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
init_clks := false;
end if;
sched_time := 0 ps;
for i in 0 to 7 loop
last_phase_shift(i) := phase_shift(i);
end loop;
cycle_to_adjust := 0;
l_index := 1;
m_times_vco_period := new_m_times_vco_period;
end if;
-- areset was asserted
if (areset_ipd'event and areset_ipd = '1') then
assert false report family_name & " PLL was reset" severity note;
-- reset lock parameters
pll_is_locked := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
end if;
if (schedule_vco'event and (areset_ipd = '1' or stop_vco)) then
if (areset_ipd = '1') then
pll_is_in_reset := true;
end if;
-- drop VCO taps to 0
for i in 0 to 7 loop
vco_out(i) <= transport '0' after last_phase_shift(i);
phase_shift(i) := 0 ps;
last_phase_shift(i) := 0 ps;
end loop;
-- reset lock parameters
pll_is_locked := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
got_first_refclk := false;
got_second_refclk := false;
refclk_time := 0 ps;
got_first_fbclk := false;
fbclk_time := 0 ps;
first_fbclk_time := 0 ps;
fbclk_period := 0 ps;
first_schedule := true;
vco_val := '0';
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
elsif ((schedule_vco'event or areset_ipd'event) and areset_ipd = '0' and (not stop_vco) and now > 0 ps) then
-- note areset deassert time
-- note it as refclk_time to prevent false triggering
-- of stop_vco after areset
if (areset_ipd'event and areset_ipd = '0' and pll_is_in_reset) then
refclk_time := now;
pll_is_in_reset := false;
locked_tmp := '0';
end if;
-- calculate loop_xplier : this will be different from m_val
-- in external_feedback_mode
loop_xplier := m_val;
loop_initial := m_initial_val - 1;
loop_ph := m_ph_val;
-- convert initial value to delay
initial_delay := (loop_initial * m_times_vco_period)/loop_xplier;
-- convert loop ph_tap to delay
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
tmp_vco_per := (m_times_vco_period/1 ps) / loop_xplier;
if (my_rem /= 0) then
tmp_vco_per := tmp_vco_per + 1;
end if;
fbk_phase := (loop_ph * tmp_vco_per)/8;
pull_back_M := initial_delay/1 ps + fbk_phase;
total_pull_back := pull_back_M;
if (simulation_type = "timing") then
total_pull_back := total_pull_back + pll_compensation_delay;
end if;
while (total_pull_back > refclk_period/1 ps) loop
total_pull_back := total_pull_back - refclk_period/1 ps;
end loop;
if (total_pull_back > 0) then
offset := refclk_period - (total_pull_back * 1 ps);
end if;
fbk_delay := total_pull_back - fbk_phase;
if (fbk_delay < 0) then
offset := offset - (fbk_phase * 1 ps);
fbk_delay := total_pull_back;
end if;
-- assign m_delay
m_delay <= transport fbk_delay after 1 ps;
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
for i in 1 to loop_xplier loop
-- adjust cycles
tmp_vco_per := (m_times_vco_period/1 ps)/loop_xplier;
if (my_rem /= 0 and l_index <= my_rem) then
tmp_rem := (loop_xplier * l_index) rem my_rem;
cycle_to_adjust := (loop_xplier * l_index) / my_rem;
if (tmp_rem /= 0) then
cycle_to_adjust := cycle_to_adjust + 1;
end if;
end if;
if (cycle_to_adjust = i) then
tmp_vco_per := tmp_vco_per + 1;
l_index := l_index + 1;
end if;
-- calculate high and low periods
vco_per := tmp_vco_per * 1 ps;
high_time := (tmp_vco_per/2) * 1 ps;
if (tmp_vco_per rem 2 /= 0) then
high_time := high_time + 1 ps;
end if;
low_time := vco_per - high_time;
-- schedule the rising and falling edges
for j in 1 to 2 loop
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule the phase taps
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
if (first_schedule) then
vco_out(k) <= transport vco_val after (sched_time + phase_shift(k));
else
vco_out(k) <= transport vco_val after (sched_time + last_phase_shift(k));
end if;
end loop;
end loop;
end loop;
-- schedule once more
if (first_schedule) then
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule the phase taps
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
vco_out(k) <= transport vco_val after (sched_time + phase_shift(k));
end loop;
first_schedule := false;
end if;
schedule_vco <= transport not schedule_vco after sched_time;
if (vco_period_was_phase_adjusted) then
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := true;
vco_per := m_times_vco_period/loop_xplier;
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
end loop;
end if;
end if;
-- Bypass lock detect
if (refclk'event and refclk = '1' and areset_ipd = '0') then
if (test_bypass_lock_detect = "on") then
if (pfdena_ipd = '1') then
cycles_pfd_low := 0;
if (pfd_locked = '0') then
if (cycles_pfd_high = lock_high) then
assert false report family_name & " PLL locked in test mode on PFD enable assertion.";
pfd_locked <= '1';
end if;
cycles_pfd_high := cycles_pfd_high + 1;
end if;
end if;
if (pfdena_ipd = '0') then
cycles_pfd_high := 0;
if (pfd_locked = '1') then
if (cycles_pfd_low = lock_low) then
assert false report family_name & " PLL lost lock in test mode on PFD enable de-assertion.";
pfd_locked <= '0';
end if;
cycles_pfd_low := cycles_pfd_low + 1;
end if;
end if;
end if;
if (refclk'event and refclk = '1' and areset_ipd = '0') then
got_refclk_posedge := true;
if (not got_first_refclk) then
got_first_refclk := true;
else
got_second_refclk := true;
refclk_period := now - refclk_time;
-- check if incoming freq. will cause VCO range to be
-- exceeded
if ( (vco_max /= 0 and vco_min /= 0 and pfdena_ipd = '1') and
(((refclk_period/1 ps)/loop_xplier > vco_max) or
((refclk_period/1 ps)/loop_xplier < vco_min)) ) then
if (pll_is_locked) then
if ((refclk_period/1 ps)/loop_xplier > vco_max) then
assert false report "Input clock freq. is over VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_over <= '1';
end if;
if ((refclk_period/1 ps)/loop_xplier < vco_min) then
assert false report "Input clock freq. is under VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_under <= '1';
end if;
if (inclk_out_of_range) then
pll_is_locked := false;
locked_tmp := '0';
cycles_to_lock := 0;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
assert false report family_name & " PLL lost lock." severity note;
end if;
elsif (not no_warn) then
if ((refclk_period/1 ps)/loop_xplier > vco_max) then
assert false report "Input clock freq. is over VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_over <= '1';
end if;
if ((refclk_period/1 ps)/loop_xplier < vco_min) then
assert false report "Input clock freq. is under VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_under <= '1';
end if;
assert false report " Input clock freq. is not within VCO range : " & family_name & " PLL may not lock. Please use the correct frequency." severity warning;
no_warn := true;
end if;
inclk_out_of_range := true;
else
vco_over <= '0';
vco_under <= '0';
inclk_out_of_range := false;
end if;
end if;
end if;
if (stop_vco) then
stop_vco := false;
schedule_vco <= not schedule_vco;
end if;
refclk_time := now;
else
got_refclk_posedge := false;
end if;
-- Update M counter value on feedback clock edge
if (fbclk'event and fbclk = '1') then
got_fbclk_posedge := true;
if (not got_first_fbclk) then
got_first_fbclk := true;
else
fbclk_period := now - fbclk_time;
end if;
-- need refclk_period here, so initialized to proper value above
if ( ( (now - refclk_time > 1.5 * refclk_period) and pfdena_ipd = '1' and pll_is_locked) or ( (now - refclk_time > 5 * refclk_period) and pfdena_ipd = '1') ) then
stop_vco := true;
-- reset
got_first_refclk := false;
got_first_fbclk := false;
got_second_refclk := false;
if (pll_is_locked) then
pll_is_locked := false;
locked_tmp := '0';
assert false report family_name & " PLL lost lock due to loss of input clock" severity note;
end if;
cycles_to_lock := 0;
cycles_to_unlock := 0;
first_schedule := true;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
end if;
fbclk_time := now;
else
got_fbclk_posedge := false;
end if;
if ((got_refclk_posedge or got_fbclk_posedge) and got_second_refclk and pfdena_ipd = '1' and (not inclk_out_of_range)) then
-- now we know actual incoming period
if ( abs(fbclk_time - refclk_time) <= 5 ps or
(got_first_fbclk and abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5 ps)) then
-- considered in phase
if (cycles_to_lock = real_lock_high) then
if (not pll_is_locked) then
assert false report family_name & " PLL locked to incoming clock" severity note;
end if;
pll_is_locked := true;
locked_tmp := '1';
cycles_to_unlock := 0;
end if;
-- increment lock counter only if second part of above
-- time check is NOT true
if (not(abs(refclk_period - abs(fbclk_time - refclk_time)) <= lock_window)) then
cycles_to_lock := cycles_to_lock + 1;
end if;
-- adjust m_times_vco_period
new_m_times_vco_period := refclk_period;
else
-- if locked, begin unlock
if (pll_is_locked) then
cycles_to_unlock := cycles_to_unlock + 1;
if (cycles_to_unlock = lock_low) then
pll_is_locked := false;
locked_tmp := '0';
cycles_to_lock := 0;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
assert false report family_name & " PLL lost lock." severity note;
end if;
end if;
if ( abs(refclk_period - fbclk_period) <= 2 ps ) then
-- frequency is still good
if (now = fbclk_time and (not phase_adjust_was_scheduled)) then
if ( abs(fbclk_time - refclk_time) > refclk_period/2) then
new_m_times_vco_period := m_times_vco_period + (refclk_period - abs(fbclk_time - refclk_time));
vco_period_was_phase_adjusted := true;
else
new_m_times_vco_period := m_times_vco_period - abs(fbclk_time - refclk_time);
vco_period_was_phase_adjusted := true;
end if;
end if;
else
phase_adjust_was_scheduled := false;
new_m_times_vco_period := refclk_period;
end if;
end if;
end if;
if (pfdena_ipd = '0') then
if (pll_is_locked) then
locked_tmp := 'X';
end if;
pll_is_locked := false;
cycles_to_lock := 0;
end if;
-- give message only at time of deassertion
if (pfdena_ipd'event and pfdena_ipd = '0') then
assert false report "PFDENA deasserted." severity note;
elsif (pfdena_ipd'event and pfdena_ipd = '1') then
got_first_refclk := false;
got_second_refclk := false;
refclk_time := now;
end if;
if (reconfig_err) then
lock <= '0';
else
lock <= locked_tmp;
end if;
-- signal to calculate quiet_time
sig_refclk_period <= refclk_period;
if (stop_vco = true) then
sig_stop_vco <= '1';
else
sig_stop_vco <= '0';
end if;
pll_locked <= pll_is_locked;
end process;
clk0_tmp <= c_clk(i_clk0_counter);
clk_pfd(0) <= clk0_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(0) <= clk_pfd(0) WHEN (test_bypass_lock_detect = "on") ELSE
clk0_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else
'X';
clk1_tmp <= c_clk(i_clk1_counter);
clk_pfd(1) <= clk1_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(1) <= clk_pfd(1) WHEN (test_bypass_lock_detect = "on") ELSE
clk1_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk2_tmp <= c_clk(i_clk2_counter);
clk_pfd(2) <= clk2_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(2) <= clk_pfd(2) WHEN (test_bypass_lock_detect = "on") ELSE
clk2_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk3_tmp <= c_clk(i_clk3_counter);
clk_pfd(3) <= clk3_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(3) <= clk_pfd(3) WHEN (test_bypass_lock_detect = "on") ELSE
clk3_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk4_tmp <= c_clk(i_clk4_counter);
clk_pfd(4) <= clk4_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(4) <= clk_pfd(4) WHEN (test_bypass_lock_detect = "on") ELSE
clk4_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
scandataout <= scandata_out;
scandone <= NOT scandone_tmp;
phasedone <= NOT update_phase;
end vital_pll;
-- END ARCHITECTURE VITAL_PLL
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_ff
--
-- Description : Cyclone III FF VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
use work.cycloneiii_and1;
entity cycloneiii_ff is
generic (
power_up : string := "low";
x_on_violation : string := "on";
lpm_type : string := "cycloneiii_ff";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
clrn : in std_logic := '1';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
asdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_ff : entity is TRUE;
end cycloneiii_ff;
architecture vital_lcell_ff of cycloneiii_ff is
attribute VITAL_LEVEL0 of vital_lcell_ff : architecture is TRUE;
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal d_dly : std_logic;
signal asdata_ipd : std_logic;
signal asdata_dly : std_logic;
signal asdata_dly1 : std_logic;
signal sclr_ipd : std_logic;
signal sload_ipd : std_logic;
signal clrn_ipd : std_logic;
signal aload_ipd : std_logic;
signal ena_ipd : std_logic;
component cycloneiii_and1
generic (XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01
);
port (Y : out STD_LOGIC;
IN1 : in STD_LOGIC
);
end component;
begin
ddelaybuffer: cycloneiii_and1
port map(IN1 => d_ipd,
Y => d_dly);
asdatadelaybuffer: cycloneiii_and1
port map(IN1 => asdata_ipd,
Y => asdata_dly);
asdatadelaybuffer1: cycloneiii_and1
port map(IN1 => asdata_dly,
Y => asdata_dly1);
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (asdata_ipd, asdata, tipd_asdata);
VitalWireDelay (sclr_ipd, sclr, tipd_sclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
VitalWireDelay (clrn_ipd, clrn, tipd_clrn);
VitalWireDelay (aload_ipd, aload, tipd_aload);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process (clk_ipd, d_dly, asdata_dly1,
sclr_ipd, sload_ipd, clrn_ipd, aload_ipd,
ena_ipd, devclrn, devpor)
variable Tviol_d_clk : std_ulogic := '0';
variable Tviol_asdata_clk : std_ulogic := '0';
variable Tviol_sclr_clk : std_ulogic := '0';
variable Tviol_sload_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_asdata_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sclr_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable iq : std_logic := '0';
variable idata: std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
if (now = 0 ns) then
if (power_up = "low") then
iq := '0';
elsif (power_up = "high") then
iq := '1';
end if;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(sload_ipd) OR
(sclr_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_asdata_clk,
TimingData => TimingData_asdata_clk,
TestSignal => asdata_ipd,
TestSignalName => "ASDATA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_asdata_clk_noedge_posedge,
SetupLow => tsetup_asdata_clk_noedge_posedge,
HoldHigh => thold_asdata_clk_noedge_posedge,
HoldLow => thold_asdata_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT sload_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sclr_clk,
TimingData => TimingData_sclr_clk,
TestSignal => sclr_ipd,
TestSignalName => "SCLR",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sclr_clk_noedge_posedge,
SetupLow => tsetup_sclr_clk_noedge_posedge,
HoldHigh => thold_sclr_clk_noedge_posedge,
HoldLow => thold_sclr_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
violation := Tviol_d_clk or Tviol_asdata_clk or
Tviol_sclr_clk or Tviol_sload_clk or Tviol_ena_clk;
if ((devpor = '0') or (devclrn = '0') or (clrn_ipd = '1')) then
iq := '0';
elsif (aload_ipd = '1') then
iq := asdata_dly1;
elsif (violation = 'X' and x_on_violation = "on") then
iq := 'X';
elsif clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' then
if (ena_ipd = '1') then
if (sclr_ipd = '1') then
iq := '0';
elsif (sload_ipd = '1') then
iq := asdata_dly1;
else
iq := d_dly;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => iq,
Paths => (0 => (clrn_ipd'last_event, tpd_clrn_q_posedge, TRUE),
1 => (aload_ipd'last_event, tpd_aload_q_posedge, TRUE),
2 => (asdata_ipd'last_event, tpd_asdata_q, TRUE),
3 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_ff;
----------------------------------------------------------------------------
-- Module Name : cycloneiii_ram_register
-- Description : Register module for RAM inputs/outputs
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_ram_register IS
GENERIC (
width : INTEGER := 1;
preset : STD_LOGIC := '0';
tipd_d : VitalDelayArrayType01(143 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_stall : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpw_ena_posedge : VitalDelayType := DefPulseWdthCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
stall : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END cycloneiii_ram_register;
ARCHITECTURE reg_arch OF cycloneiii_ram_register IS
SIGNAL d_ipd : STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
SIGNAL clk_ipd : STD_LOGIC;
SIGNAL ena_ipd : STD_LOGIC;
SIGNAL aclr_ipd : STD_LOGIC;
SIGNAL stall_ipd : STD_LOGIC;
BEGIN
WireDelay : BLOCK
BEGIN
loopbits : FOR i in d'RANGE GENERATE
VitalWireDelay (d_ipd(i), d(i), tipd_d(i));
END GENERATE;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (stall_ipd, stall, tipd_stall);
END BLOCK;
-- REMCYCLONEIII PROCESS (d_ipd,ena_ipd,clk_ipd,aclr_ipd,devclrn,devpor)
PROCESS (d_ipd,ena_ipd,stall_ipd,clk_ipd,aclr_ipd,devclrn,devpor)
VARIABLE Tviol_clk_ena : STD_ULOGIC := '0';
VARIABLE Tviol_clk_aclr : STD_ULOGIC := '0';
VARIABLE Tviol_data_clk : STD_ULOGIC := '0';
VARIABLE TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_stall : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_aclr : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
VARIABLE Tviol_ena : STD_ULOGIC := '0';
VARIABLE PeriodData_ena : VitalPeriodDataType := VitalPeriodDataInit;
VARIABLE q_VitalGlitchDataArray : VitalGlitchDataArrayType(143 downto 0);
VARIABLE CQDelay : TIME := 0 ns;
VARIABLE q_reg : STD_LOGIC_VECTOR(width - 1 DOWNTO 0) := (OTHERS => preset);
BEGIN
IF (aclr_ipd = '1' OR devclrn = '0' OR devpor = '0') THEN
q_reg := (OTHERS => preset);
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1' AND stall_ipd = '0') THEN
q_reg := d_ipd;
END IF;
-- Timing checks
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_stall,
TestSignal => stall_ipd,
TestSignalName => "stall",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_stall_clk_noedge_posedge,
SetupLow => tsetup_stall_clk_noedge_posedge,
HoldHigh => thold_stall_clk_noedge_posedge,
HoldLow => thold_stall_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_aclr,
TimingData => TimingData_clk_aclr,
TestSignal => aclr_ipd,
TestSignalName => "aclr",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_aclr_clk_noedge_posedge,
SetupLow => tsetup_aclr_clk_noedge_posedge,
HoldHigh => thold_aclr_clk_noedge_posedge,
HoldLow => thold_aclr_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_data_clk,
TimingData => TimingData_data_clk,
TestSignal => d_ipd,
TestSignalName => "data",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalPeriodPulseCheck (
Violation => Tviol_ena,
PeriodData => PeriodData_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
PulseWidthHigh => tpw_ena_posedge,
HeaderMsg => "/RAM Register VitalPeriodPulseCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
-- Path Delay Selection
CQDelay := SelectDelay (
Paths => (
(0 => (clk_ipd'LAST_EVENT,tpd_clk_q_posedge,TRUE),
1 => (aclr_ipd'LAST_EVENT,tpd_aclr_q_posedge,TRUE))
)
);
q <= TRANSPORT q_reg AFTER CQDelay;
END PROCESS;
aclrout <= aclr_ipd;
END reg_arch;
----------------------------------------------------------------------------
-- Module Name : cycloneiii_ram_pulse_generator
-- Description : Generate pulse to initiate memory read/write operations
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_ram_pulse_generator IS
GENERIC (
tipd_clk : VitalDelayType01 := (0.5 ns,0.5 ns);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tpd_clk_pulse_posedge : VitalDelayType01 := DefPropDelay01
);
PORT (
clk,ena : IN STD_LOGIC;
delaywrite : IN STD_LOGIC := '0';
pulse,cycle : OUT STD_LOGIC
);
ATTRIBUTE VITAL_Level0 OF cycloneiii_ram_pulse_generator:ENTITY IS TRUE;
END cycloneiii_ram_pulse_generator;
ARCHITECTURE pgen_arch OF cycloneiii_ram_pulse_generator IS
ATTRIBUTE VITAL_Level0 OF pgen_arch:ARCHITECTURE IS TRUE;
SIGNAL clk_ipd,ena_ipd : STD_LOGIC;
SIGNAL state : STD_LOGIC;
BEGIN
WireDelay : BLOCK
BEGIN
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
END BLOCK;
PROCESS (clk_ipd,state)
BEGIN
IF (state = '1' AND state'EVENT) THEN
state <= '0';
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1') THEN
IF (delaywrite = '1') THEN
state <= '1' AFTER 1 NS; -- delayed write
ELSE
state <= '1';
END IF;
END IF;
END PROCESS;
PathDelay : PROCESS
VARIABLE pulse_VitalGlitchData : VitalGlitchDataType;
BEGIN
WAIT UNTIL state'EVENT;
VitalPathDelay01 (
OutSignal => pulse,
OutSignalName => "pulse",
OutTemp => state,
Paths => (0 => (clk_ipd'LAST_EVENT,tpd_clk_pulse_posedge,TRUE)),
GlitchData => pulse_VitalGlitchData,
Mode => DefGlitchMode,
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks
);
END PROCESS;
cycle <= clk_ipd;
END pgen_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.cycloneiii_atom_pack.all;
USE work.cycloneiii_ram_register;
USE work.cycloneiii_ram_pulse_generator;
ENTITY cycloneiii_ram_block IS
GENERIC (
-- -------- GLOBAL PARAMETERS ---------
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
port_a_address_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_read_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_address_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_write_enable_clock: STRING := "clock1";
port_b_read_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
port_a_read_during_write_mode : STRING := "new_data_no_nbe_read";
port_b_read_during_write_mode : STRING := "new_data_no_nbe_read";
power_up_uninitialized : STRING := "false";
port_b_byte_size : INTEGER := 0;
port_a_byte_size : INTEGER := 0;
safe_write : STRING := "err_on_2clk";
init_file_restructured : STRING := "unused";
lpm_type : string := "cycloneiii_ram_block";
lpm_hint : string := "true";
clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_output_clock_enable : STRING := "none"; -- ena0,none
clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_output_clock_enable : STRING := "none"; -- ena1,none
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
mem_init2 : BIT_VECTOR := X"0";
mem_init3 : BIT_VECTOR := X"0";
mem_init4 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
-- -------- PORT DECLARATIONS ---------
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portare : IN STD_LOGIC := '1';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbwe : IN STD_LOGIC := '0';
portbre : IN STD_LOGIC := '1';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
ena2 : IN STD_LOGIC := '1';
ena3 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portaaddrstall : IN STD_LOGIC := '0';
portbaddrstall : IN STD_LOGIC := '0';
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END cycloneiii_ram_block;
ARCHITECTURE block_arch OF cycloneiii_ram_block IS
COMPONENT cycloneiii_ram_pulse_generator
PORT (
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
delaywrite : IN STD_LOGIC := '0';
pulse : OUT STD_LOGIC;
cycle : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT cycloneiii_ram_register
GENERIC (
preset : STD_LOGIC := '0';
width : integer := 1
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
ena : IN STD_LOGIC;
stall : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END COMPONENT;
FUNCTION cond (condition : BOOLEAN;CONSTANT a,b : INTEGER) RETURN INTEGER IS
VARIABLE c: INTEGER;
BEGIN
IF (condition) THEN c := a; ELSE c := b; END IF;
RETURN c;
END;
SUBTYPE port_type IS BOOLEAN;
CONSTANT primary : port_type := TRUE;
CONSTANT secondary : port_type := FALSE;
CONSTANT primary_port_is_a : BOOLEAN := (port_b_data_width <= port_a_data_width);
CONSTANT primary_port_is_b : BOOLEAN := NOT primary_port_is_a;
CONSTANT mode_is_rom : BOOLEAN := (operation_mode = "rom");
CONSTANT mode_is_sp : BOOLEAN := (operation_mode = "single_port");
CONSTANT mode_is_dp : BOOLEAN := (operation_mode = "dual_port");
CONSTANT mode_is_bdp : BOOLEAN := (operation_mode = "bidir_dual_port");
CONSTANT wired_mode : BOOLEAN := (port_a_address_width = port_b_address_width) AND (port_a_address_width = 1)
AND (port_a_data_width /= port_b_data_width);
CONSTANT num_cols : INTEGER := cond(mode_is_rom OR mode_is_sp,1,
cond(wired_mode,2,2 ** (ABS(port_b_address_width - port_a_address_width))));
CONSTANT data_width : INTEGER := cond(primary_port_is_a,port_a_data_width,port_b_data_width);
CONSTANT data_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_data_width,port_b_data_width);
CONSTANT address_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_a,port_a_address_width,port_b_address_width);
CONSTANT address_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_address_width,port_b_address_width);
CONSTANT byte_size_a : INTEGER := port_a_data_width / port_a_byte_enable_mask_width;
CONSTANT byte_size_b : INTEGER := port_b_data_width / port_b_byte_enable_mask_width;
CONSTANT out_a_is_reg : BOOLEAN := (port_a_data_out_clock /= "none" AND port_a_data_out_clock /= "UNUSED");
CONSTANT out_b_is_reg : BOOLEAN := (port_b_data_out_clock /= "none" AND port_b_data_out_clock /= "UNUSED");
CONSTANT bytes_a_disabled : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT bytes_b_disabled : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT ram_type : BOOLEAN := FALSE;
TYPE bool_to_std_logic_map IS ARRAY(TRUE DOWNTO FALSE) OF STD_LOGIC;
CONSTANT bool_to_std_logic : bool_to_std_logic_map := ('1','0');
-- Hardware write modes
CONSTANT dual_clock : BOOLEAN := (operation_mode = "dual_port" OR
operation_mode = "bidir_dual_port") AND
(port_b_address_clock = "clock1");
CONSTANT both_new_data_same_port : BOOLEAN := (
((port_a_read_during_write_mode = "new_data_no_nbe_read") OR
(port_a_read_during_write_mode = "dont_care")) AND
((port_b_read_during_write_mode = "new_data_no_nbe_read") OR
(port_b_read_during_write_mode = "dont_care"))
);
SIGNAL hw_write_mode_a : STRING(3 DOWNTO 1);
SIGNAL hw_write_mode_b : STRING(3 DOWNTO 1);
SIGNAL delay_write_pulse_a : STD_LOGIC ;
SIGNAL delay_write_pulse_b : STD_LOGIC ;
CONSTANT be_mask_write_a : BOOLEAN := (port_a_read_during_write_mode = "new_data_with_nbe_read");
CONSTANT be_mask_write_b : BOOLEAN := (port_b_read_during_write_mode = "new_data_with_nbe_read");
CONSTANT old_data_write_a : BOOLEAN := (port_a_read_during_write_mode = "old_data");
CONSTANT old_data_write_b : BOOLEAN := (port_b_read_during_write_mode = "old_data");
SIGNAL read_before_write_a : BOOLEAN;
SIGNAL read_before_write_b : BOOLEAN;
-- -------- internal signals ---------
-- clock / clock enable
SIGNAL clk_a_in,clk_b_in : STD_LOGIC;
SIGNAL clk_a_byteena,clk_b_byteena : STD_LOGIC;
SIGNAL clk_a_out,clk_b_out : STD_LOGIC;
SIGNAL clkena_a_out,clkena_b_out : STD_LOGIC;
SIGNAL clkena_out_c0, clkena_out_c1 : STD_LOGIC;
SIGNAL write_cycle_a,write_cycle_b : STD_LOGIC;
SIGNAL clk_a_rena, clk_a_wena : STD_LOGIC;
SIGNAL clk_a_core : STD_LOGIC;
SIGNAL clk_b_rena, clk_b_wena : STD_LOGIC;
SIGNAL clk_b_core : STD_LOGIC;
SUBTYPE one_bit_bus_type IS STD_LOGIC_VECTOR(0 DOWNTO 0);
-- asynch clear
TYPE clear_mode_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
TYPE clear_vec_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL datain_a_clr,datain_b_clr : STD_LOGIC;
SIGNAL dataout_a_clr,dataout_b_clr : STD_LOGIC;
SIGNAL dataout_a_clr_reg, dataout_b_clr_reg : STD_LOGIC;
SIGNAL dataout_a_clr_reg_in, dataout_b_clr_reg_in : one_bit_bus_type;
SIGNAL dataout_a_clr_reg_out, dataout_b_clr_reg_out : one_bit_bus_type;
SIGNAL dataout_a_clr_reg_latch, dataout_b_clr_reg_latch : STD_LOGIC;
SIGNAL dataout_a_clr_reg_latch_in, dataout_b_clr_reg_latch_in : one_bit_bus_type;
SIGNAL dataout_a_clr_reg_latch_out, dataout_b_clr_reg_latch_out : one_bit_bus_type;
SIGNAL addr_a_clr,addr_b_clr : STD_LOGIC;
SIGNAL byteena_a_clr,byteena_b_clr : STD_LOGIC;
SIGNAL we_a_clr,re_a_clr,we_b_clr,re_b_clr : STD_LOGIC;
SIGNAL datain_a_clr_in,datain_b_clr_in : STD_LOGIC;
SIGNAL addr_a_clr_in,addr_b_clr_in : STD_LOGIC;
SIGNAL byteena_a_clr_in,byteena_b_clr_in : STD_LOGIC;
SIGNAL we_a_clr_in,re_a_clr_in,we_b_clr_in,re_b_clr_in : STD_LOGIC;
SIGNAL mem_invalidate,mem_invalidate_loc,read_latch_invalidate : clear_mode_type;
SIGNAL clear_asserted_during_write : clear_vec_type;
-- port A registers
SIGNAL we_a_reg : STD_LOGIC;
SIGNAL re_a_reg : STD_LOGIC;
SIGNAL we_a_reg_in,we_a_reg_out : one_bit_bus_type;
SIGNAL re_a_reg_in,re_a_reg_out : one_bit_bus_type;
SIGNAL addr_a_reg : STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0);
SIGNAL datain_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL byteena_a_reg : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width- 1 DOWNTO 0);
-- port B registers
SIGNAL we_b_reg, re_b_reg : STD_LOGIC;
SIGNAL re_b_reg_in,re_b_reg_out,we_b_reg_in,we_b_reg_out : one_bit_bus_type;
SIGNAL addr_b_reg : STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0);
SIGNAL datain_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL byteena_b_reg : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width- 1 DOWNTO 0);
-- pulses
TYPE pulse_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL write_pulse,read_pulse,read_pulse_feedthru : pulse_vec;
SIGNAL rw_pulse : pulse_vec;
SIGNAL wpgen_a_clk,wpgen_a_clkena,wpgen_b_clk,wpgen_b_clkena : STD_LOGIC;
SIGNAL rpgen_a_clkena,rpgen_b_clkena : STD_LOGIC;
SIGNAL ftpgen_a_clkena,ftpgen_b_clkena : STD_LOGIC;
SIGNAL rwpgen_a_clkena,rwpgen_b_clkena : STD_LOGIC;
-- registered address
SIGNAL addr_prime_reg,addr_sec_reg : INTEGER;
-- input/output
SIGNAL datain_prime_reg,dataout_prime : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
SIGNAL datain_sec_reg,dataout_sec : STD_LOGIC_VECTOR(data_unit_width - 1 DOWNTO 0);
-- overlapping location write
SIGNAL dual_write : BOOLEAN;
-- byte enable mask write
TYPE be_mask_write_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
SIGNAL be_mask_write : be_mask_write_vec;
-- memory core
SUBTYPE mem_word_type IS STD_LOGIC_VECTOR (data_width - 1 DOWNTO 0);
SUBTYPE mem_col_type IS STD_LOGIC_VECTOR (data_unit_width - 1 DOWNTO 0);
TYPE mem_row_type IS ARRAY (num_cols - 1 DOWNTO 0) OF mem_col_type;
TYPE mem_type IS ARRAY ((2 ** address_unit_width) - 1 DOWNTO 0) OF mem_row_type;
SIGNAL mem : mem_type;
SIGNAL init_mem : BOOLEAN := FALSE;
CONSTANT mem_x : mem_type := (OTHERS => (OTHERS => (OTHERS => 'X')));
CONSTANT row_x : mem_row_type := (OTHERS => (OTHERS => 'X'));
CONSTANT col_x : mem_col_type := (OTHERS => 'X');
SIGNAL mem_data : mem_row_type;
SIGNAL mem_unit_data : mem_col_type;
-- latches
TYPE read_latch_rec IS RECORD
prime : mem_row_type;
sec : mem_col_type;
END RECORD;
SIGNAL read_latch : read_latch_rec;
-- (row,column) coordinates
SIGNAL row_sec,col_sec : INTEGER;
-- byte enable
TYPE mask_type IS (normal,inverse);
TYPE mask_prime_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_word_type;
TYPE mask_sec_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_col_type;
TYPE mask_rec IS RECORD
prime : mask_prime_type;
sec : mask_sec_type;
END RECORD;
SIGNAL mask_vector : mask_rec;
SIGNAL mask_vector_common : mem_col_type;
FUNCTION get_mask(
b_ena : IN STD_LOGIC_VECTOR;
mode : port_type;
CONSTANT b_ena_width ,byte_size: INTEGER
) RETURN mask_rec IS
VARIABLE l : INTEGER;
VARIABLE mask : mask_rec := (
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X')),
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X'))
);
BEGIN
FOR l in 0 TO b_ena_width - 1 LOOP
IF (b_ena(l) = '0') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.prime(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.sec(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
END IF;
ELSIF (b_ena(l) = 'X' OR b_ena(l) = 'U') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
END IF;
END IF;
END LOOP;
RETURN mask;
END get_mask;
-- port active for read/write
SIGNAL active_a_core_in_vec,active_b_core_in_vec,active_a_core_out,active_b_core_out : one_bit_bus_type;
SIGNAL active_a_in,active_b_in : STD_LOGIC;
SIGNAL active_write_a : BOOLEAN;
SIGNAL active_write_b : BOOLEAN;
SIGNAL active_b_in_c0,active_b_core_in_c0,active_b_in_c1,active_b_core_in_c1 : STD_LOGIC;
SIGNAL active_a_core_in,active_b_core_in : STD_LOGIC;
SIGNAL active_a_core, active_b_core : BOOLEAN;
SIGNAL wire_vcc : STD_LOGIC := '1';
SIGNAL wire_gnd : STD_LOGIC := '0';
BEGIN
-- memory initialization
init_mem <= TRUE;
-- hardware write modes
hw_write_mode_a <= "R+W" WHEN ((port_a_read_during_write_mode = "old_data") OR
(port_a_read_during_write_mode = "new_data_with_nbe_read")) ELSE
" FW" WHEN (dual_clock OR (
mixed_port_feed_through_mode = "dont_care" AND
both_new_data_same_port
)) ELSE
" DW";
hw_write_mode_b <= "R+W" WHEN ((port_b_read_during_write_mode = "old_data") OR
(port_b_read_during_write_mode = "new_data_with_nbe_read")) ELSE
" FW" WHEN (dual_clock OR (
mixed_port_feed_through_mode = "dont_care" AND
both_new_data_same_port
)) ELSE
" DW";
delay_write_pulse_a <= '1' WHEN (hw_write_mode_a /= " FW") ELSE '0';
delay_write_pulse_b <= '1' WHEN (hw_write_mode_b /= " FW") ELSE '0' ;
read_before_write_a <= (hw_write_mode_a = "R+W");
read_before_write_b <= (hw_write_mode_b = "R+W");
-- -------- core logic ---------------
clk_a_in <= clk0;
clk_a_wena <= '0' WHEN (port_a_write_enable_clock = "none") ELSE clk_a_in;
clk_a_rena <= '0' WHEN (port_a_read_enable_clock = "none") ELSE clk_a_in;
clk_a_byteena <= '0' WHEN (port_a_byte_enable_clock = "none" OR port_a_byte_enable_clock = "UNUSED") ELSE clk_a_in;
clk_a_out <= '0' WHEN (port_a_data_out_clock = "none" OR port_a_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_a_data_out_clock = "clock0") ELSE clk1;
clk_b_in <= clk0 WHEN (port_b_address_clock = "clock0") ELSE clk1;
clk_b_byteena <= '0' WHEN (port_b_byte_enable_clock = "none" OR port_b_byte_enable_clock = "UNUSED") ELSE
clk0 WHEN (port_b_byte_enable_clock = "clock0") ELSE clk1;
clk_b_wena <= '0' WHEN (port_b_write_enable_clock = "none") ELSE
clk0 WHEN (port_b_write_enable_clock = "clock0") ELSE
clk1;
clk_b_rena <= '0' WHEN (port_b_read_enable_clock = "none") ELSE
clk0 WHEN (port_b_read_enable_clock = "clock0") ELSE
clk1;
clk_b_out <= '0' WHEN (port_b_data_out_clock = "none" OR port_b_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_b_data_out_clock = "clock0") ELSE clk1;
addr_a_clr_in <= '0' WHEN (port_a_address_clear = "none" OR port_a_address_clear = "UNUSED") ELSE clr0;
addr_b_clr_in <= '0' WHEN (port_b_address_clear = "none" OR port_b_address_clear = "UNUSED") ELSE
clr0 WHEN (port_b_address_clear = "clear0") ELSE clr1;
datain_a_clr_in <= '0';
datain_b_clr_in <= '0';
dataout_a_clr_reg <= '0' WHEN (port_a_data_out_clear = "none" OR port_a_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_a_data_out_clear = "clear0") ELSE clr1;
dataout_a_clr <= dataout_a_clr_reg WHEN (port_a_data_out_clock = "none" OR port_a_data_out_clock = "UNUSED") ELSE
'0';
dataout_b_clr_reg <= '0' WHEN (port_b_data_out_clear = "none" OR port_b_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_b_data_out_clear = "clear0") ELSE clr1;
dataout_b_clr <= dataout_b_clr_reg WHEN (port_b_data_out_clock = "none" OR port_b_data_out_clock = "UNUSED") ELSE
'0';
byteena_a_clr_in <= '0';
byteena_b_clr_in <= '0';
we_a_clr_in <= '0';
re_a_clr_in <= '0';
we_b_clr_in <= '0';
re_b_clr_in <= '0';
active_a_in <= '1' WHEN (clk0_input_clock_enable = "none") ELSE
ena0 WHEN (clk0_input_clock_enable = "ena0") ELSE
ena2;
active_a_core_in <= '1' WHEN (clk0_core_clock_enable = "none") ELSE
ena0 WHEN (clk0_core_clock_enable = "ena0") ELSE
ena2;
be_mask_write(primary_port_is_a) <= be_mask_write_a;
be_mask_write(primary_port_is_b) <= be_mask_write_b;
active_b_in_c0 <= '1' WHEN (clk0_input_clock_enable = "none") ELSE
ena0 WHEN (clk0_input_clock_enable = "ena0") ELSE
ena2;
active_b_in_c1 <= '1' WHEN (clk1_input_clock_enable = "none") ELSE
ena1 WHEN (clk1_input_clock_enable = "ena1") ELSE
ena3;
active_b_in <= active_b_in_c0 WHEN (port_b_address_clock = "clock0") ELSE active_b_in_c1;
active_b_core_in_c0 <= '1' WHEN (clk0_core_clock_enable = "none") ELSE
ena0 WHEN (clk0_core_clock_enable = "ena0") ELSE
ena2;
active_b_core_in_c1 <= '1' WHEN (clk1_core_clock_enable = "none") ELSE
ena1 WHEN (clk1_core_clock_enable = "ena1") ELSE
ena3;
active_b_core_in <= active_b_core_in_c0 WHEN (port_b_address_clock = "clock0") ELSE active_b_core_in_c1;
active_write_a <= (byteena_a_reg /= bytes_a_disabled);
active_write_b <= (byteena_b_reg /= bytes_b_disabled);
-- Store core clock enable value for delayed write
-- port A core active
active_a_core_in_vec(0) <= active_a_core_in;
active_core_port_a : cycloneiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_a_core_in_vec,
clk => clk_a_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
ena => wire_vcc,
stall => wire_gnd,
q => active_a_core_out
);
active_a_core <= (active_a_core_out(0) = '1');
-- port B core active
active_b_core_in_vec(0) <= active_b_core_in;
active_core_port_b : cycloneiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_b_core_in_vec,
clk => clk_b_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
ena => wire_vcc,
stall => wire_gnd,
q => active_b_core_out
);
active_b_core <= (active_b_core_out(0) = '1');
-- ------ A input registers
-- write enable
we_a_reg_in(0) <= '0' WHEN mode_is_rom ELSE portawe;
we_a_register : cycloneiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => we_a_reg_in,
clk => clk_a_wena,
aclr => we_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => we_a_reg_out,
aclrout => we_a_clr
);
we_a_reg <= we_a_reg_out(0);
-- read enable
re_a_reg_in(0) <= portare;
re_a_register : cycloneiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => re_a_reg_in,
clk => clk_a_rena,
aclr => re_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => re_a_reg_out,
aclrout => re_a_clr
);
re_a_reg <= re_a_reg_out(0);
-- address
addr_a_register : cycloneiii_ram_register
GENERIC MAP ( width => port_a_address_width )
PORT MAP (
d => portaaddr,
clk => clk_a_in,
aclr => addr_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => portaaddrstall,
ena => active_a_in,
q => addr_a_reg,
aclrout => addr_a_clr
);
-- data
datain_a_register : cycloneiii_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => portadatain,
clk => clk_a_in,
aclr => datain_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => datain_a_reg,
aclrout => datain_a_clr
);
-- byte enable
byteena_a_register : cycloneiii_ram_register
GENERIC MAP (
width => port_a_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portabyteenamasks,
clk => clk_a_byteena,
aclr => byteena_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => byteena_a_reg,
aclrout => byteena_a_clr
);
-- ------ B input registers
-- read enable
re_b_reg_in(0) <= portbre;
re_b_register : cycloneiii_ram_register
GENERIC MAP (
width => 1
)
PORT MAP (
d => re_b_reg_in,
clk => clk_b_in,
aclr => re_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => re_b_reg_out,
aclrout => re_b_clr
);
re_b_reg <= re_b_reg_out(0);
-- write enable
we_b_reg_in(0) <= portbwe;
we_b_register : cycloneiii_ram_register
GENERIC MAP (
width => 1
)
PORT MAP (
d => we_b_reg_in,
clk => clk_b_in,
aclr => we_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => we_b_reg_out,
aclrout => we_b_clr
);
we_b_reg <= we_b_reg_out(0);
-- address
addr_b_register : cycloneiii_ram_register
GENERIC MAP ( width => port_b_address_width )
PORT MAP (
d => portbaddr,
clk => clk_b_in,
aclr => addr_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => portbaddrstall,
ena => active_b_in,
q => addr_b_reg,
aclrout => addr_b_clr
);
-- data
datain_b_register : cycloneiii_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => portbdatain,
clk => clk_b_in,
aclr => datain_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => datain_b_reg,
aclrout => datain_b_clr
);
-- byte enable
byteena_b_register : cycloneiii_ram_register
GENERIC MAP (
width => port_b_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portbbyteenamasks,
clk => clk_b_byteena,
aclr => byteena_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => byteena_b_reg,
aclrout => byteena_b_clr
);
datain_prime_reg <= datain_a_reg WHEN primary_port_is_a ELSE datain_b_reg;
addr_prime_reg <= alt_conv_integer(addr_a_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_b_reg);
datain_sec_reg <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
datain_b_reg WHEN primary_port_is_a ELSE datain_a_reg;
addr_sec_reg <= alt_conv_integer(addr_b_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_a_reg);
-- Write pulse generation
wpgen_a_clk <= clk_a_in;
wpgen_a_clkena <= '1' WHEN (active_a_core AND active_write_a AND (we_a_reg = '1')) ELSE '0';
wpgen_a : cycloneiii_ram_pulse_generator
PORT MAP (
clk => wpgen_a_clk,
ena => wpgen_a_clkena,
delaywrite => delay_write_pulse_a,
pulse => write_pulse(primary_port_is_a),
cycle => write_cycle_a
);
wpgen_b_clk <= clk_b_in;
wpgen_b_clkena <= '1' WHEN (active_b_core AND active_write_b AND mode_is_bdp AND (we_b_reg = '1')) ELSE '0';
wpgen_b : cycloneiii_ram_pulse_generator
PORT MAP (
clk => wpgen_b_clk,
ena => wpgen_b_clkena,
delaywrite => delay_write_pulse_b,
pulse => write_pulse(primary_port_is_b),
cycle => write_cycle_b
);
-- Read pulse generation
rpgen_a_clkena <= '1' WHEN (active_a_core AND (re_a_reg = '1') AND (we_a_reg = '0') AND (dataout_a_clr = '0')) ELSE '0';
rpgen_a : cycloneiii_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => rpgen_a_clkena,
cycle => clk_a_core,
pulse => read_pulse(primary_port_is_a)
);
rpgen_b_clkena <= '1' WHEN ((mode_is_dp OR mode_is_bdp) AND active_b_core AND (re_b_reg = '1') AND (we_b_reg = '0') AND (dataout_b_clr = '0')) ELSE '0';
rpgen_b : cycloneiii_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => rpgen_b_clkena,
cycle => clk_b_core,
pulse => read_pulse(primary_port_is_b)
);
-- Read-during-Write pulse generation
rwpgen_a_clkena <= '1' WHEN (active_a_core AND (re_a_reg = '1') AND (we_a_reg = '1') AND read_before_write_a AND (dataout_a_clr = '0')) ELSE '0';
rwpgen_a : cycloneiii_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => rwpgen_a_clkena,
pulse => rw_pulse(primary_port_is_a)
);
rwpgen_b_clkena <= '1' WHEN (active_b_core AND mode_is_bdp AND (re_b_reg = '1') AND (we_b_reg = '1') AND read_before_write_b AND (dataout_b_clr = '0')) ELSE '0';
rwpgen_b : cycloneiii_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => rwpgen_b_clkena,
pulse => rw_pulse(primary_port_is_b)
);
-- Create internal masks for byte enable processing
mask_create : PROCESS (byteena_a_reg,byteena_b_reg)
VARIABLE mask : mask_rec;
BEGIN
IF (byteena_a_reg'EVENT) THEN
mask := get_mask(byteena_a_reg,primary_port_is_a,port_a_byte_enable_mask_width,byte_size_a);
IF (primary_port_is_a) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
IF (byteena_b_reg'EVENT) THEN
mask := get_mask(byteena_b_reg,primary_port_is_b,port_b_byte_enable_mask_width,byte_size_b);
IF (primary_port_is_b) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
END PROCESS mask_create;
-- (row,col) coordinates
row_sec <= addr_sec_reg / num_cols;
col_sec <= addr_sec_reg mod num_cols;
mem_rw : PROCESS (init_mem,
write_pulse,read_pulse,read_pulse_feedthru,
rw_pulse,
dataout_a_clr, dataout_b_clr,
mem_invalidate,mem_invalidate_loc,read_latch_invalidate)
-- mem init
TYPE rw_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
VARIABLE addr_range_init,row,col,index : INTEGER;
VARIABLE mem_init_std : STD_LOGIC_VECTOR((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
VARIABLE mem_val : mem_type;
-- read/write
VARIABLE mem_data_p : mem_row_type;
VARIABLE row_prime,col_prime : INTEGER;
VARIABLE access_same_location : BOOLEAN;
VARIABLE read_during_write : rw_type;
BEGIN
-- Latch Clear
IF (dataout_a_clr'EVENT AND dataout_a_clr = '1') THEN
IF (primary_port_is_a) THEN
read_latch.prime <= (OTHERS => (OTHERS => '0'));
dataout_prime <= (OTHERS => '0');
ELSE
read_latch.sec <= (OTHERS => '0');
dataout_sec <= (OTHERS => '0');
END IF;
END IF;
IF (dataout_b_clr'EVENT AND dataout_b_clr = '1') THEN
IF (primary_port_is_b) THEN
read_latch.prime <= (OTHERS => (OTHERS => '0'));
dataout_prime <= (OTHERS => '0');
ELSE
read_latch.sec <= (OTHERS => '0');
dataout_sec <= (OTHERS => '0');
END IF;
END IF;
read_during_write := (FALSE,FALSE);
-- Memory initialization
IF (init_mem'EVENT) THEN
-- Initialize output latches to 0
IF (primary_port_is_a) THEN
dataout_prime <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_sec <= (OTHERS => '0'); END IF;
ELSE
dataout_sec <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_prime <= (OTHERS => '0'); END IF;
END IF;
IF (power_up_uninitialized = "false" AND (NOT ram_type)) THEN
mem_val := (OTHERS => (OTHERS => (OTHERS => '0')));
END IF;
IF (primary_port_is_a) THEN
addr_range_init := port_a_last_address - port_a_first_address + 1;
ELSE
addr_range_init := port_b_last_address - port_b_first_address + 1;
END IF;
IF (init_file_layout = "port_a" OR init_file_layout = "port_b") THEN
mem_init_std := to_stdlogicvector(mem_init4 & mem_init3 & mem_init2 & mem_init1 & mem_init0)((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
FOR row IN 0 TO addr_range_init - 1 LOOP
FOR col IN 0 to num_cols - 1 LOOP
index := row * data_width;
mem_val(row)(col) := mem_init_std(index + (col+1)*data_unit_width -1 DOWNTO
index + col*data_unit_width);
END LOOP;
END LOOP;
END IF;
mem <= mem_val;
END IF;
access_same_location := (mode_is_dp OR mode_is_bdp) AND (addr_prime_reg = row_sec);
-- Read before Write stage 1 : read data from memory
-- Read before Write stage 2 : send data to output
IF (rw_pulse(primary)'EVENT) THEN
IF (rw_pulse(primary) = '1') THEN
read_latch.prime <= mem(addr_prime_reg);
ELSE
IF (be_mask_write(primary)) THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = 'X') THEN
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END IF;
END LOOP;
ELSE
FOR i IN 0 TO data_width - 1 LOOP
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END LOOP;
END IF;
END IF;
END IF;
IF (rw_pulse(secondary)'EVENT) THEN
IF (rw_pulse(secondary) = '1') THEN
read_latch.sec <= mem(row_sec)(col_sec);
ELSE
IF (be_mask_write(secondary)) THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = 'X') THEN
dataout_sec(i) <= read_latch.sec(i);
END IF;
END LOOP;
ELSE
dataout_sec <= read_latch.sec;
END IF;
END IF;
END IF;
-- Write stage 1 : X to buffer
-- Write stage 2 : actual data to memory
IF (write_pulse(primary)'EVENT) THEN
IF (write_pulse(primary) = '1') THEN
mem_data_p := mem(addr_prime_reg);
FOR i IN 0 TO num_cols - 1 LOOP
mem_data_p(i) := mem_data_p(i) XOR
mask_vector.prime(inverse)((i + 1)*data_unit_width - 1 DOWNTO i*data_unit_width);
END LOOP;
read_during_write(secondary) := (access_same_location AND read_pulse(secondary)'EVENT AND read_pulse(secondary) = '1');
IF (read_during_write(secondary)) THEN
read_latch.sec <= mem_data_p(col_sec);
ELSE
mem_data <= mem_data_p;
END IF;
ELSIF (clear_asserted_during_write(primary) /= '1') THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = '0') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= datain_prime_reg(i);
ELSIF (mask_vector.prime(inverse)(i) = 'X') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
IF (write_pulse(secondary)'EVENT) THEN
IF (write_pulse(secondary) = '1') THEN
read_during_write(primary) := (access_same_location AND read_pulse(primary)'EVENT AND read_pulse(primary) = '1');
IF (read_during_write(primary)) THEN
read_latch.prime <= mem(addr_prime_reg);
read_latch.prime(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
ELSE
mem_unit_data <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
END IF;
IF (access_same_location AND write_pulse(primary)'EVENT AND write_pulse(primary) = '1') THEN
mask_vector_common <=
mask_vector.prime(inverse)(((col_sec + 1)* data_unit_width - 1) DOWNTO col_sec*data_unit_width) AND
mask_vector.sec(inverse);
dual_write <= TRUE;
END IF;
ELSIF (clear_asserted_during_write(secondary) /= '1') THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = '0') THEN
mem(row_sec)(col_sec)(i) <= datain_sec_reg(i);
ELSIF (mask_vector.sec(inverse)(i) = 'X') THEN
mem(row_sec)(col_sec)(i) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
-- Simultaneous write
IF (dual_write AND write_pulse = "00") THEN
mem(row_sec)(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector_common;
dual_write <= FALSE;
END IF;
-- Read stage 1 : read data
-- Read stage 2 : send data to output
IF ((NOT read_during_write(primary)) AND read_pulse(primary)'EVENT) THEN
IF (read_pulse(primary) = '1') THEN
read_latch.prime <= mem(addr_prime_reg);
IF (access_same_location AND write_pulse(secondary) = '1') THEN
read_latch.prime(col_sec) <= mem_unit_data;
END IF;
ELSE
FOR i IN 0 TO data_width - 1 LOOP
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END LOOP;
END IF;
END IF;
IF ((NOT read_during_write(secondary)) AND read_pulse(secondary)'EVENT) THEN
IF (read_pulse(secondary) = '1') THEN
IF (access_same_location AND write_pulse(primary) = '1') THEN
read_latch.sec <= mem_data(col_sec);
ELSE
read_latch.sec <= mem(row_sec)(col_sec);
END IF;
ELSE
dataout_sec <= read_latch.sec;
END IF;
END IF;
-- Same port feed thru
IF (read_pulse_feedthru(primary)'EVENT AND read_pulse_feedthru(primary) = '0') THEN
IF (be_mask_write(primary)) THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = '0') THEN
dataout_prime(i) <= datain_prime_reg(i);
END IF;
END LOOP;
ELSE
dataout_prime <= datain_prime_reg XOR mask_vector.prime(normal);
END IF;
END IF;
IF (read_pulse_feedthru(secondary)'EVENT AND read_pulse_feedthru(secondary) = '0') THEN
IF (be_mask_write(secondary)) THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = '0') THEN
dataout_sec(i) <= datain_sec_reg(i);
END IF;
END LOOP;
ELSE
dataout_sec <= datain_sec_reg XOR mask_vector.sec(normal);
END IF;
END IF;
-- Async clear
IF (mem_invalidate'EVENT) THEN
IF (mem_invalidate(primary) = TRUE OR mem_invalidate(secondary) = TRUE) THEN
mem <= mem_x;
END IF;
END IF;
IF (mem_invalidate_loc'EVENT) THEN
IF (mem_invalidate_loc(primary)) THEN mem(addr_prime_reg) <= row_x; END IF;
IF (mem_invalidate_loc(secondary)) THEN mem(row_sec)(col_sec) <= col_x; END IF;
END IF;
IF (read_latch_invalidate'EVENT) THEN
IF (read_latch_invalidate(primary)) THEN
read_latch.prime <= row_x;
END IF;
IF (read_latch_invalidate(secondary)) THEN
read_latch.sec <= col_x;
END IF;
END IF;
END PROCESS mem_rw;
-- Same port feed through
ftpgen_a_clkena <= '1' WHEN (active_a_core AND (NOT mode_is_dp) AND (NOT old_data_write_a) AND (we_a_reg = '1') AND (re_a_reg = '1') AND (dataout_a_clr = '0')) ELSE '0';
ftpgen_a : cycloneiii_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => ftpgen_a_clkena,
pulse => read_pulse_feedthru(primary_port_is_a)
);
ftpgen_b_clkena <= '1' WHEN (active_b_core AND mode_is_bdp AND (NOT old_data_write_b) AND (we_b_reg = '1') AND (re_b_reg = '1') AND (dataout_b_clr = '0')) ELSE '0';
ftpgen_b : cycloneiii_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => ftpgen_b_clkena,
pulse => read_pulse_feedthru(primary_port_is_b)
);
-- Asynch clear events
clear_a : PROCESS(addr_a_clr,we_a_clr,datain_a_clr)
BEGIN
IF (addr_a_clr'EVENT AND addr_a_clr = '1') THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF (active_a_core AND re_a_reg = '1' AND dataout_a_clr = '0' AND dataout_a_clr_reg_latch = '0') THEN
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((we_a_clr'EVENT AND we_a_clr = '1') OR (datain_a_clr'EVENT AND datain_a_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_a;
clear_b : PROCESS(addr_b_clr,we_b_clr,datain_b_clr)
BEGIN
IF (addr_b_clr'EVENT AND addr_b_clr = '1') THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (we_b_reg = '1')) THEN
mem_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF ((mode_is_dp OR mode_is_bdp) AND active_b_core AND re_b_reg = '1' AND dataout_b_clr = '0' AND dataout_b_clr_reg_latch = '0') THEN
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((we_b_clr'EVENT AND we_b_clr = '1') OR (datain_b_clr'EVENT AND datain_b_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (we_b_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_b;
-- Clear mux registers (Latch Clear)
-- Port A output register clear
dataout_a_clr_reg_latch_in(0) <= dataout_a_clr;
aclr_a_mux_register : cycloneiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => dataout_a_clr_reg_latch_in,
clk => clk_a_core,
aclr => wire_gnd,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => wire_vcc,
q => dataout_a_clr_reg_latch_out
);
dataout_a_clr_reg_latch <= dataout_a_clr_reg_latch_out(0);
-- Port B output register clear
dataout_b_clr_reg_latch_in(0) <= dataout_b_clr;
aclr_b_mux_register : cycloneiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => dataout_b_clr_reg_latch_in,
clk => clk_b_core,
aclr => wire_gnd,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => wire_vcc,
q => dataout_b_clr_reg_latch_out
);
dataout_b_clr_reg_latch <= dataout_b_clr_reg_latch_out(0);
-- ------ Output registers
clkena_out_c0 <= '1' WHEN (clk0_output_clock_enable = "none") ELSE ena0;
clkena_out_c1 <= '1' WHEN (clk1_output_clock_enable = "none") ELSE ena1;
clkena_a_out <= clkena_out_c0 WHEN (port_a_data_out_clock = "clock0") ELSE clkena_out_c1;
clkena_b_out <= clkena_out_c0 WHEN (port_b_data_out_clock = "clock0") ELSE clkena_out_c1;
dataout_a <= dataout_prime WHEN primary_port_is_a ELSE dataout_sec;
dataout_b <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
dataout_prime WHEN primary_port_is_b ELSE dataout_sec;
dataout_a_register : cycloneiii_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => dataout_a,
clk => clk_a_out,
aclr => dataout_a_clr_reg,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => clkena_a_out,
q => dataout_a_reg
);
dataout_b_register : cycloneiii_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => dataout_b,
clk => clk_b_out,
aclr => dataout_b_clr_reg,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => clkena_b_out,
q => dataout_b_reg
);
portadataout <= dataout_a_reg WHEN out_a_is_reg ELSE dataout_a;
portbdataout <= dataout_b_reg WHEN out_b_is_reg ELSE dataout_b;
END block_arch;
-----------------------------------------------------------------------
--
-- Module Name : cycloneiii_mac_data_reg
--
-- Description : Simulation model for the data input register of
-- Cyclone II MAC_MULT
--
-----------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_mac_data_reg IS
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_data : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tsetup_data_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_data_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_aclr_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
data_width : integer := 18
);
PORT (
-- INPUT PORTS
clk : IN std_logic;
data : IN std_logic_vector(17 DOWNTO 0);
ena : IN std_logic;
aclr : IN std_logic;
-- OUTPUT PORTS
dataout : OUT std_logic_vector(17 DOWNTO 0)
);
END cycloneiii_mac_data_reg;
ARCHITECTURE vital_cycloneiii_mac_data_reg OF cycloneiii_mac_data_reg IS
SIGNAL data_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL aclr_ipd : std_logic;
SIGNAL clk_ipd : std_logic;
SIGNAL ena_ipd : std_logic;
SIGNAL dataout_tmp : std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
BEGIN
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
g1 : for i in data'range generate
VitalWireDelay (data_ipd(i), data(i), tipd_data(i));
end generate;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process (clk_ipd, aclr_ipd, data_ipd)
variable Tviol_data_clk : std_ulogic := '0';
variable TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_data_clk,
TimingData => TimingData_data_clk,
TestSignal => data,
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_data_clk_noedge_posedge,
SetupLow => tsetup_data_clk_noedge_posedge,
HoldHigh => thold_data_clk_noedge_posedge,
HoldLow => thold_data_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MAC_DATA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01(aclr) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MAC_DATA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (aclr_ipd = '1') then
dataout_tmp <= (OTHERS => '0');
elsif (clk_ipd'event and clk_ipd = '1' and (ena_ipd = '1')) then
dataout_tmp <= data_ipd;
end if;
end process;
----------------------
-- Path Delay Section
----------------------
PathDelay : block
begin
g1 : for i in dataout_tmp'range generate
VITALtiming : process (dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (OutSignal => dataout(i),
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp(i),
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn);
end process;
end generate;
end block;
END vital_cycloneiii_mac_data_reg;
--------------------------------------------------------------------
--
-- Module Name : cycloneiii_mac_sign_reg
--
-- Description : Simulation model for the sign input register of
-- Cyclone II MAC_MULT
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_mac_sign_reg IS
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
-- INPUT PORTS
clk : IN std_logic;
d : IN std_logic;
ena : IN std_logic;
aclr : IN std_logic;
-- OUTPUT PORTS
q : OUT std_logic
);
END cycloneiii_mac_sign_reg;
ARCHITECTURE cycloneiii_mac_sign_reg OF cycloneiii_mac_sign_reg IS
signal d_ipd : std_logic;
signal clk_ipd : std_logic;
signal aclr_ipd : std_logic;
signal ena_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process (clk_ipd, aclr_ipd)
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable q_reg : std_logic := '0';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/SIGN_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01(aclr) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/SIGN_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (aclr_ipd = '1') then
q_reg := '0';
elsif (clk_ipd'event and clk_ipd = '1' and (ena_ipd = '1')) then
q_reg := d_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_reg,
Paths => (0 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
END cycloneiii_mac_sign_reg;
--------------------------------------------------------------------
--
-- Module Name : cycloneiii_mac_mult_internal
--
-- Description : Cyclone II MAC_MULT_INTERNAL VHDL simulation model
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_mac_mult_internal IS
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_dataa : VitalDelayArrayType01(17 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(17 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_signa : VitalDelayType01 := DefPropDelay01;
tipd_signb : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datab_dataout : VitalDelayType01 := DefPropDelay01;
tpd_signa_dataout : VitalDelayType01 := DefPropDelay01;
tpd_signb_dataout : VitalDelayType01 := DefPropDelay01;
dataa_width : integer := 18;
datab_width : integer := 18
);
PORT (
dataa : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
datab : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0)
);
END cycloneiii_mac_mult_internal;
ARCHITECTURE vital_cycloneiii_mac_mult_internal OF cycloneiii_mac_mult_internal IS
-- Internal variables
SIGNAL dataa_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL datab_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL signa_ipd : std_logic;
SIGNAL signb_ipd : std_logic;
-- padding with 1's for input negation
SIGNAL reg_aclr : std_logic;
SIGNAL dataout_tmp : STD_LOGIC_VECTOR (dataa_width + datab_width downto 0) := (others => '0');
BEGIN
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
g1 : for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
end generate;
g2 : for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
end generate;
VitalWireDelay (signa_ipd, signa, tipd_signa);
VitalWireDelay (signb_ipd, signb, tipd_signb);
end block;
VITALtiming : process(dataa_ipd, datab_ipd, signa_ipd, signb_ipd)
begin
if((signa_ipd = '0') and (signb_ipd = '1')) then
dataout_tmp <=
unsigned(dataa_ipd(dataa_width-1 downto 0)) *
signed(datab_ipd(datab_width-1 downto 0));
elsif((signa_ipd = '1') and (signb_ipd = '0')) then
dataout_tmp <=
signed(dataa_ipd(dataa_width-1 downto 0)) *
unsigned(datab_ipd(datab_width-1 downto 0));
elsif((signa_ipd = '1') and (signb_ipd = '1')) then
dataout_tmp(dataout'range) <=
signed(dataa_ipd(dataa_width-1 downto 0)) *
signed(datab_ipd(datab_width-1 downto 0));
else --((signa_ipd = '0') and (signb_ipd = '0')) then
dataout_tmp(dataout'range) <=
unsigned(dataa_ipd(dataa_width-1 downto 0)) *
unsigned(datab_ipd(datab_width-1 downto 0));
end if;
end process;
----------------------
-- Path Delay Section
----------------------
PathDelay : block
begin
g1 : for i in dataout'range generate
VITALtiming : process (dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_dataout, TRUE),
2 => (signa'last_event, tpd_signa_dataout, TRUE),
3 => (signb'last_event, tpd_signb_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE );
end process;
end generate;
end block;
END vital_cycloneiii_mac_mult_internal;
--------------------------------------------------------------------
--
-- Module Name : cycloneiii_mac_mult
--
-- Description : Cyclone II MAC_MULT VHDL simulation model
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.cycloneiii_atom_pack.all;
USE work.cycloneiii_mac_data_reg;
USE work.cycloneiii_mac_sign_reg;
USE work.cycloneiii_mac_mult_internal;
ENTITY cycloneiii_mac_mult IS
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
lpm_hint : string := "true";
lpm_type : string := "cycloneiii_mac_mult"
);
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (OTHERS => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
ena : IN std_logic := '0';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END cycloneiii_mac_mult;
ARCHITECTURE vital_cycloneiii_mac_mult OF cycloneiii_mac_mult IS
COMPONENT cycloneiii_mac_data_reg
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_data : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tsetup_data_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_data_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_aclr_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
data_width : integer := 18
);
PORT (
-- INPUT PORTS
clk : IN std_logic;
data : IN std_logic_vector(17 DOWNTO 0);
ena : IN std_logic;
aclr : IN std_logic;
-- OUTPUT PORTS
dataout : OUT std_logic_vector(17 DOWNTO 0)
);
END COMPONENT;
COMPONENT cycloneiii_mac_sign_reg
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
-- INPUT PORTS
clk : IN std_logic;
d : IN std_logic;
ena : IN std_logic;
aclr : IN std_logic;
-- OUTPUT PORTS
q : OUT std_logic
);
END COMPONENT;
COMPONENT cycloneiii_mac_mult_internal
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_dataa : VitalDelayArrayType01(17 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(17 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_signa : VitalDelayType01 := DefPropDelay01;
tipd_signb : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datab_dataout : VitalDelayType01 := DefPropDelay01;
tpd_signa_dataout : VitalDelayType01 := DefPropDelay01;
tpd_signb_dataout : VitalDelayType01 := DefPropDelay01;
dataa_width : integer := 18;
datab_width : integer := 18
);
PORT (
dataa : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
datab : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0)
);
END COMPONENT;
-- Internal variables
SIGNAL dataa_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL datab_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL idataa_reg : std_logic_vector(17 DOWNTO 0); -- optional register for dataa input
SIGNAL idatab_reg : std_logic_vector(17 DOWNTO 0); -- optional register for datab input
SIGNAL isigna_reg : std_logic; -- optional register for signa input
SIGNAL isignb_reg : std_logic; -- optional register for signb input
SIGNAL idataa_int : std_logic_vector(17 DOWNTO 0); -- dataa as seen by the multiplier input
SIGNAL idatab_int : std_logic_vector(17 DOWNTO 0); -- datab as seen by the multiplier input
SIGNAL isigna_int : std_logic; -- signa as seen by the multiplier input
SIGNAL isignb_int : std_logic; -- signb as seen by the multiplier input
-- padding with 1's for input negation
SIGNAL reg_aclr : std_logic;
SIGNAL dataout_tmp : STD_LOGIC_VECTOR (dataa_width + datab_width downto 0) := (others => '0');
BEGIN
---------------------
-- INPUT PATH DELAYs
---------------------
reg_aclr <= (NOT devpor) OR (NOT devclrn) OR (aclr) ;
-- padding input data to full bus width
dataa_ipd(dataa_width-1 downto 0) <= dataa;
datab_ipd(datab_width-1 downto 0) <= datab;
-- Optional input registers for dataa,b and signa,b
dataa_reg : cycloneiii_mac_data_reg
GENERIC MAP (
data_width => dataa_width)
PORT MAP (
clk => clk,
data => dataa_ipd,
ena => ena,
aclr => reg_aclr,
dataout => idataa_reg);
datab_reg : cycloneiii_mac_data_reg
GENERIC MAP (
data_width => datab_width)
PORT MAP (
clk => clk,
data => datab_ipd,
ena => ena,
aclr => reg_aclr,
dataout => idatab_reg);
signa_reg : cycloneiii_mac_sign_reg
PORT MAP (
clk => clk,
d => signa,
ena => ena,
aclr => reg_aclr,
q => isigna_reg);
signb_reg : cycloneiii_mac_sign_reg
PORT MAP (
clk => clk,
d => signb,
ena => ena,
aclr => reg_aclr,
q => isignb_reg);
idataa_int <= dataa_ipd WHEN (dataa_clock = "none") ELSE idataa_reg;
idatab_int <= datab_ipd WHEN (datab_clock = "none") ELSE idatab_reg;
isigna_int <= signa WHEN (signa_clock = "none") ELSE isigna_reg;
isignb_int <= signb WHEN (signb_clock = "none") ELSE isignb_reg;
mac_multiply : cycloneiii_mac_mult_internal
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width
)
PORT MAP (
dataa => idataa_int,
datab => idatab_int,
signa => isigna_int,
signb => isignb_int,
dataout => dataout
);
END vital_cycloneiii_mac_mult;
--------------------------------------------------------------------
--
-- Module Name : cycloneiii_mac_out
--
-- Description : Cyclone II MAC_OUT VHDL simulation model
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_mac_out IS
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_dataa : VitalDelayArrayType01(35 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout : VitalDelayType01 := DefPropDelay01;
tpd_aclr_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_dataa_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dataa_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
dataa_width : integer := 1;
output_clock : string := "none";
lpm_hint : string := "true";
lpm_type : string := "cycloneiii_mac_out");
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
ena : IN std_logic := '1';
dataout : OUT std_logic_vector(dataa_width-1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END cycloneiii_mac_out;
ARCHITECTURE vital_cycloneiii_mac_out OF cycloneiii_mac_out IS
-- internal variables
SIGNAL dataa_ipd : std_logic_vector(dataa'range);
SIGNAL clk_ipd : std_logic;
SIGNAL aclr_ipd : std_logic;
SIGNAL ena_ipd : std_logic;
-- optional register
SIGNAL use_reg : std_logic;
SIGNAL dataout_tmp : std_logic_vector(dataout'range) := (OTHERS => '0');
BEGIN
---------------------
-- PATH DELAYs
---------------------
WireDelay : block
begin
g1 : for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
VITALtiming : process (clk_ipd, aclr_ipd, dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp(i),
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge, use_reg = '1'),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge, use_reg = '1'),
2 => (dataa_ipd(i)'last_event, tpd_dataa_dataout, use_reg = '0')),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end generate;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
use_reg <= '1' WHEN (output_clock /= "none") ELSE '0';
VITALtiming : process (clk_ipd, aclr_ipd, dataa_ipd)
variable Tviol_dataa_clk : std_ulogic := '0';
variable TimingData_dataa_clk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_dataa_clk,
TimingData => TimingData_dataa_clk,
TestSignal => dataa,
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_dataa_clk_noedge_posedge,
SetupLow => tsetup_dataa_clk_noedge_posedge,
HoldHigh => thold_dataa_clk_noedge_posedge,
HoldLow => thold_dataa_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr) OR (NOT use_reg) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MAC_DATA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr) OR
(NOT use_reg)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MAC_DATA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (use_reg = '0') then
dataout_tmp <= dataa_ipd;
else
if (aclr_ipd = '1') then
dataout_tmp <= (OTHERS => '0');
elsif (clk_ipd'event and clk_ipd = '1' and (ena_ipd = '1')) then
dataout_tmp <= dataa_ipd;
end if;
end if;
end process;
END vital_cycloneiii_mac_out;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_io_ibuf
--
-- Description : Cyclone III IO Ibuf VHDL simulation model
--
--
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_io_ibuf IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_ibar : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_ibar_o : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
differential_mode : string := "false";
bus_hold : string := "false";
lpm_type : string := "cycloneiii_io_ibuf"
);
PORT (
i : IN std_logic := '0';
ibar : IN std_logic := '0';
o : OUT std_logic
);
END cycloneiii_io_ibuf;
ARCHITECTURE arch OF cycloneiii_io_ibuf IS
SIGNAL i_ipd : std_logic := '0';
SIGNAL ibar_ipd : std_logic := '0';
SIGNAL o_tmp : std_logic;
SIGNAL out_tmp : std_logic;
SIGNAL prev_value : std_logic := '0';
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
VitalWireDelay (ibar_ipd, ibar, tipd_ibar);
end block;
PROCESS(i_ipd, ibar_ipd)
BEGIN
IF (differential_mode = "false") THEN
IF (i_ipd = '1') THEN
o_tmp <= '1';
prev_value <= '1';
ELSIF (i_ipd = '0') THEN
o_tmp <= '0';
prev_value <= '0';
ELSE
o_tmp <= i_ipd;
END IF;
ELSE
IF (( i_ipd = '0' ) and (ibar_ipd = '1')) then
o_tmp <= '0';
ELSIF (( i_ipd = '1' ) and (ibar_ipd = '0')) then
o_tmp <= '1';
ELSIF((( i_ipd = '1' ) and (ibar_ipd = '1')) or (( i_ipd = '0' ) and (ibar_ipd = '0')))then
o_tmp <= 'X';
ELSE
o_tmp <= 'X';
END IF;
END IF;
END PROCESS;
out_tmp <= prev_value when (bus_hold = "true") else o_tmp;
----------------------
-- Path Delay Section
----------------------
PROCESS( out_tmp)
variable output_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => out_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE),
1 => (ibar_ipd'last_event, tpd_ibar_o, TRUE)),
GlitchData => output_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_io_obuf
--
-- Description : Cyclone III IO Obuf VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_io_obuf IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_oe_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
tpd_oe_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
open_drain_output : string := "false";
bus_hold : string := "false";
lpm_type : string := "cycloneiii_io_obuf"
);
PORT (
i : IN std_logic := '0';
oe : IN std_logic := '1';
seriesterminationcontrol : IN std_logic_vector(15 DOWNTO 0) := (others => '0');
devoe : IN std_logic := '1';
o : OUT std_logic;
obar : OUT std_logic
);
END cycloneiii_io_obuf;
ARCHITECTURE arch OF cycloneiii_io_obuf IS
--INTERNAL Signals
SIGNAL i_ipd : std_logic := '0';
SIGNAL oe_ipd : std_logic := '0';
SIGNAL out_tmp : std_logic := 'Z';
SIGNAL out_tmp_bar : std_logic;
SIGNAL prev_value : std_logic := '0';
SIGNAL o_tmp : std_logic;
SIGNAL obar_tmp : std_logic;
SIGNAL o_tmp1 : std_logic;
SIGNAL obar_tmp1 : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
VitalWireDelay (oe_ipd, oe, tipd_oe);
end block;
PROCESS( i_ipd, oe_ipd)
BEGIN
IF (oe_ipd = '1') THEN
IF (open_drain_output = "true") THEN
IF (i_ipd = '0') THEN
out_tmp <= '0';
out_tmp_bar <= '1';
prev_value <= '0';
ELSE
out_tmp <= 'Z';
out_tmp_bar <= 'Z';
END IF;
ELSE
IF (i_ipd = '0') THEN
out_tmp <= '0';
out_tmp_bar <= '1';
prev_value <= '0';
ELSE
IF (i_ipd = '1') THEN
out_tmp <= '1';
out_tmp_bar <= '0';
prev_value <= '1';
ELSE
out_tmp <= i_ipd;
out_tmp_bar <= i_ipd;
END IF;
END IF;
END IF;
ELSE
IF (oe_ipd = '0') THEN
out_tmp <= 'Z';
out_tmp_bar <= 'Z';
ELSE
out_tmp <= 'X';
out_tmp_bar <= 'X';
END IF;
END IF;
END PROCESS;
o_tmp1 <= prev_value WHEN (bus_hold = "true") ELSE out_tmp;
obar_tmp1 <= NOT prev_value WHEN (bus_hold = "true") ELSE out_tmp_bar;
o_tmp <= o_tmp1 WHEN (devoe = '1') ELSE 'Z';
obar_tmp <= obar_tmp1 WHEN (devoe = '1') ELSE 'Z';
---------------------
-- Path Delay Section
----------------------
PROCESS( o_tmp,obar_tmp)
variable o_VitalGlitchData : VitalGlitchDataType;
variable obar_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => o_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE),
1 => (oe_ipd'last_event, tpd_oe_o, TRUE)),
GlitchData => o_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => obar,
OutSignalName => "obar",
OutTemp => obar_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_obar, TRUE),
1 => (oe_ipd'last_event, tpd_oe_obar, TRUE)),
GlitchData => obar_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_ddio_oe
--
-- Description : Cyclone III DDIO_OE VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY altera;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use altera.altera_primitives_components.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_ddio_oe IS
generic(
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "cycloneiii_ddio_oe"
);
PORT (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END cycloneiii_ddio_oe;
ARCHITECTURE arch OF cycloneiii_ddio_oe IS
component cycloneiii_mux21
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01
);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic
);
end component;
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
--Internal Signals
SIGNAL oe_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '0';
SIGNAL areset_ipd : std_logic := '0';
SIGNAL sreset_ipd : std_logic := '0';
SIGNAL ddioreg_aclr : std_logic;
SIGNAL ddioreg_prn : std_logic;
SIGNAL ddioreg_adatasdata : std_logic;
SIGNAL ddioreg_sclr : std_logic;
SIGNAL ddioreg_sload : std_logic;
SIGNAL dfflo_tmp : std_logic;
SIGNAL dffhi_tmp : std_logic;
signal nclk : std_logic;
signal dataout_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (oe_ipd, oe, tipd_oe);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
end block;
nclk <= NOT clk_ipd;
PROCESS
BEGIN
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
IF (async_mode = "clear") THEN
ddioreg_aclr <= NOT areset_ipd;
ddioreg_prn <= '1';
ELSIF (async_mode = "preset") THEN
ddioreg_aclr <= '1';
ddioreg_prn <= NOT areset_ipd;
ELSE
ddioreg_aclr <= '1';
ddioreg_prn <= '1';
END IF;
IF (sync_mode = "clear") THEN
ddioreg_adatasdata <= '0';
ddioreg_sclr <= sreset_ipd;
ddioreg_sload <= '0';
ELSIF (sync_mode = "preset") THEN
ddioreg_adatasdata <= '1';
ddioreg_sclr <= '0';
ddioreg_sload <= sreset_ipd;
ELSE
ddioreg_adatasdata <= '0';
ddioreg_sclr <= '0';
ddioreg_sload <= '0';
END IF;
END PROCESS;
ddioreg_hi : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => oe_ipd,
clk => clk_ipd,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dffhi_tmp,
devpor => devpor,
devclrn => devclrn
);
--DDIO Low Register
ddioreg_lo : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => dffhi_tmp,
clk => nclk,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dfflo_tmp,
devpor => devpor,
devclrn => devclrn
);
--registered output
or_gate : cycloneiii_mux21
port map (
A => dffhi_tmp,
B => dfflo_tmp,
S => dfflo_tmp,
MO => dataout
);
dfflo <= dfflo_tmp ;
dffhi <= dffhi_tmp ;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_ddio_out
--
-- Description : Cyclone III DDIO_OUT VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY altera;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use altera.altera_primitives_components.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_ddio_out IS
generic(
tipd_datainlo : VitalDelayType01 := DefPropDelay01;
tipd_datainhi : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "cycloneiii_ddio_out"
);
PORT (
datainlo : IN std_logic := '0';
datainhi : IN std_logic := '0';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic ;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END cycloneiii_ddio_out;
ARCHITECTURE arch OF cycloneiii_ddio_out IS
component cycloneiii_mux21
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01
);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic
);
end component;
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
--Internal Signals
SIGNAL datainlo_ipd : std_logic := '0';
SIGNAL datainhi_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '0';
SIGNAL areset_ipd : std_logic := '0';
SIGNAL sreset_ipd : std_logic := '0';
SIGNAL ddioreg_aclr : std_logic;
SIGNAL ddioreg_prn : std_logic;
SIGNAL ddioreg_adatasdata : std_logic;
SIGNAL ddioreg_sclr : std_logic;
SIGNAL ddioreg_sload : std_logic;
SIGNAL dfflo_tmp : std_logic;
SIGNAL dffhi_tmp : std_logic;
SIGNAL dataout_tmp : std_logic;
Signal mux_sel : std_logic;
Signal mux_lo : std_logic;
Signal sel_mux_lo_in : std_logic;
Signal sel_mux_select : std_logic;
signal clk1 : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (datainlo_ipd, datainlo, tipd_datainlo);
VitalWireDelay (datainhi_ipd, datainhi, tipd_datainhi);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
end block;
PROCESS
BEGIN
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
IF (async_mode = "clear") THEN
ddioreg_aclr <= NOT areset_ipd;
ddioreg_prn <= '1';
ELSIF (async_mode = "preset") THEN
ddioreg_aclr <= '1';
ddioreg_prn <= NOT areset_ipd;
ELSE
ddioreg_aclr <= '1';
ddioreg_prn <= '1';
END IF;
IF (sync_mode = "clear") THEN
ddioreg_adatasdata <= '0';
ddioreg_sclr <= sreset_ipd;
ddioreg_sload <= '0';
ELSIF (sync_mode = "preset") THEN
ddioreg_adatasdata <= '1';
ddioreg_sclr <= '0';
ddioreg_sload <= sreset_ipd;
ELSE
ddioreg_adatasdata <= '0';
ddioreg_sclr <= '0';
ddioreg_sload <= '0';
END IF;
END PROCESS;
process(clk_ipd)
begin
clk1 <= clk_ipd;
end process;
--DDIO OE Register
ddioreg_hi : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => datainhi,
clk => clk_ipd,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dffhi_tmp,
devpor => devpor,
devclrn => devclrn
);
--DDIO Low Register
ddioreg_lo : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => datainlo,
clk => clk_ipd,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dfflo_tmp,
devpor => devpor,
devclrn => devclrn
);
mux_sel <= clk1;
mux_lo <= dfflo_tmp;
sel_mux_lo_in <= dfflo_tmp;
sel_mux_select <= mux_sel;
sel_mux : cycloneiii_mux21
port map (
A => sel_mux_lo_in,
B => dffhi_tmp,
S => sel_mux_select,
MO => dataout
);
dfflo <= dfflo_tmp;
dffhi <= dffhi_tmp;
END arch;
----------------------------------------------------------------------------
-- Module Name : cycloneiii_io_pad
-- Description : Simulation model for cycloneiii IO pad
----------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
ENTITY cycloneiii_io_pad IS
GENERIC (
lpm_type : string := "cycloneiii_io_pad");
PORT (
--INPUT PORTS
padin : IN std_logic := '0'; -- Input Pad
--OUTPUT PORTS
padout : OUT std_logic); -- Output Pad
END cycloneiii_io_pad;
ARCHITECTURE arch OF cycloneiii_io_pad IS
BEGIN
padout <= padin;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiii_ena_reg
--
-- Description : Simulation model for a simple DFF.
-- This is used for the gated clock generation
-- Powers upto 1.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_ena_reg is
generic (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_ena_reg : entity is TRUE;
end cycloneiii_ena_reg;
ARCHITECTURE behave of cycloneiii_ena_reg is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal d_ipd : std_logic;
signal clk_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (clk_ipd, clk, tipd_clk);
end block;
VITALtiming : process (clk_ipd, prn, clrn)
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable q_reg : std_logic := '1';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((clrn) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/cycloneiii_ena_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk_ipd'event and clk_ipd = '1' and (ena = '1')) then
q_reg := d_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_reg,
Paths => (0 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- VHDL Simulation Model for Cyclone III CLKCTRL Atom
--
--/////////////////////////////////////////////////////////////////////////////
--
--
-- CYCLONEII_CLKCTRL Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
use work.cycloneiii_ena_reg;
entity cycloneiii_clkctrl is
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "cycloneiii_clkctrl";
ena_register_mode : STRING := "Falling Edge";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
outclk : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_clkctrl : entity is TRUE;
end cycloneiii_clkctrl;
architecture vital_clkctrl of cycloneiii_clkctrl is
attribute VITAL_LEVEL0 of vital_clkctrl : architecture is TRUE;
component cycloneiii_ena_reg
generic (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
end component;
signal inclk_ipd : std_logic_vector(3 downto 0);
signal clkselect_ipd : std_logic_vector(1 downto 0);
signal ena_ipd : std_logic;
signal clkmux_out : std_logic;
signal clkmux_out_inv : std_logic;
signal cereg_clr : std_logic;
signal cereg1_out : std_logic;
signal cereg2_out : std_logic;
signal ena_out : std_logic;
signal vcc : std_logic := '1';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (inclk_ipd(0), inclk(0), tipd_inclk(0));
VitalWireDelay (inclk_ipd(1), inclk(1), tipd_inclk(1));
VitalWireDelay (inclk_ipd(2), inclk(2), tipd_inclk(2));
VitalWireDelay (inclk_ipd(3), inclk(3), tipd_inclk(3));
VitalWireDelay (clkselect_ipd(0), clkselect(0), tipd_clkselect(0));
VitalWireDelay (clkselect_ipd(1), clkselect(1), tipd_clkselect(1));
end block;
process(inclk_ipd, clkselect_ipd)
variable tmp : std_logic;
begin
if (clkselect_ipd = "11") then
tmp := inclk_ipd(3);
elsif (clkselect_ipd = "10") then
tmp := inclk_ipd(2);
elsif (clkselect_ipd = "01") then
tmp := inclk_ipd(1);
else
tmp := inclk_ipd(0);
end if;
clkmux_out <= tmp;
clkmux_out_inv <= NOT tmp;
end process;
extena0_reg : cycloneiii_ena_reg
port map (
clk => clkmux_out_inv,
ena => vcc,
d => ena_ipd,
clrn => vcc,
prn => devpor,
q => cereg1_out
);
extena1_reg : cycloneiii_ena_reg
port map (
clk => clkmux_out_inv,
ena => vcc,
d => cereg1_out,
clrn => vcc,
prn => devpor,
q => cereg2_out
);
ena_out <= cereg1_out WHEN (ena_register_mode = "falling edge") ELSE
ena_ipd WHEN (ena_register_mode = "none") ELSE cereg2_out;
outclk <= ena_out AND clkmux_out;
end vital_clkctrl;
--
--
-- CYCLONEIII_RUBLOCK Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_rublock is
generic
(
sim_init_config : string := "factory";
sim_init_watchdog_value : integer := 0;
sim_init_status : integer := 0;
lpm_type : string := "cycloneiii_rublock"
);
port
(
clk : in std_logic;
shiftnld : in std_logic;
captnupdt : in std_logic;
regin : in std_logic;
rsttimer : in std_logic;
rconfig : in std_logic;
regout : out std_logic
);
end cycloneiii_rublock;
architecture architecture_rublock of cycloneiii_rublock is
begin
end architecture_rublock;
--
--
-- CYCLONEIII_APFCONTROLLER Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_apfcontroller is
generic
(
lpm_type: string := "cycloneiii_apfcontroller"
);
port
(
usermode : out std_logic;
nceout : out std_logic
);
end cycloneiii_apfcontroller;
architecture architecture_apfcontroller of cycloneiii_apfcontroller is
begin
end architecture_apfcontroller;
--------------------------------------------------------------------
--
-- Module Name : cycloneiii_termination
--
-- Description : Cyclone III Termination Atom VHDL simulation model
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY cycloneiii_termination IS
GENERIC (
pullup_control_to_core: string := "false";
power_down : string := "true";
test_mode : string := "false";
left_shift_termination_code : string := "false";
pullup_adder : integer := 0;
pulldown_adder : integer := 0;
clock_divide_by : integer := 32; -- 1, 4, 32
runtime_control : string := "false";
shift_vref_rup : string := "true";
shift_vref_rdn : string := "true";
shifted_vref_control : string := "true";
lpm_type : string := "cycloneiii_termination");
PORT (
rup : IN std_logic := '0';
rdn : IN std_logic := '0';
terminationclock : IN std_logic := '0';
terminationclear : IN std_logic := '0';
devpor : IN std_logic := '1';
devclrn : IN std_logic := '1';
comparatorprobe : OUT std_logic;
terminationcontrolprobe : OUT std_logic;
calibrationdone : OUT std_logic;
terminationcontrol : OUT std_logic_vector(15 DOWNTO 0));
END cycloneiii_termination;
ARCHITECTURE cycloneiii_termination_arch OF cycloneiii_termination IS
SIGNAL rup_compout : std_logic := '0';
SIGNAL rdn_compout : std_logic := '1';
BEGIN
calibrationdone <= '1'; -- power-up calibration status
comparatorprobe <= rup_compout WHEN (pullup_control_to_core = "true") ELSE rdn_compout;
rup_compout <= rup;
rdn_compout <= not rdn;
END cycloneiii_termination_arch;
-------------------------------------------------------------------
--
-- Entity Name : cycloneiii_jtag
--
-- Description : Cyclone III JTAG VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_jtag is
generic (
lpm_type : string := "cycloneiii_jtag"
);
port (
tms : in std_logic;
tck : in std_logic;
tdi : in std_logic;
tdoutap : in std_logic;
tdouser : in std_logic;
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
end cycloneiii_jtag;
architecture architecture_jtag of cycloneiii_jtag is
begin
end architecture_jtag;
-------------------------------------------------------------------
--
-- Entity Name : cycloneiii_crcblock
--
-- Description : Cyclone III CRCBLOCK VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_crcblock is
generic (
oscillator_divider : integer := 1;
lpm_type : string := "cycloneiii_crcblock"
);
port (
clk : in std_logic;
shiftnld : in std_logic;
ldsrc : in std_logic;
crcerror : out std_logic;
regout : out std_logic
);
end cycloneiii_crcblock;
architecture architecture_crcblock of cycloneiii_crcblock is
begin
end architecture_crcblock;
--
--
-- CYCLONEIII_OSCILLATOR Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_oscillator is
generic
(
lpm_type: string := "cycloneiii_oscillator"
);
port
(
oscena : in std_logic;
clkout : out std_logic
);
end cycloneiii_oscillator;
architecture architecture_oscillator of cycloneiii_oscillator is
begin
end architecture_oscillator;
|
--------------------------------------------------------------------------------
-- File name: gen_utils.vhd
--------------------------------------------------------------------------------
-- Copyright (C) 1996, 1998, 2001 Free Model Foundry; http://eda.org/fmf/
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License version 2 as
-- published by the Free Software Foundation.
--
-- MODIFICATION HISTORY:
--
-- version: | author: | mod date: | changes made:
-- V1.0 R. Steele 96 SEP 26 Initial release
-- V1.1 REV3 97 Feb 27 Added Xon and MsgOn generics
-- V1.2 R. Steele 97 APR 16 Changed wired-or to wired-and
-- V1.3 R. Steele 97 APR 16 Added diff. receiver table
-- V1.4 R. Munden 98 APR 13 Added GenParity and CheckParity
-- V1.5 R. Munden 01 NOV 24 Added UnitDelay01ZX
--
--------------------------------------------------------------------------------
LIBRARY IEEE; USE IEEE.std_Logic_1164.ALL;
USE IEEE.VITAL_primitives.ALL;
USE IEEE.VITAL_timing.ALL;
PACKAGE gen_utils IS
----------------------------------------------------------------------------
-- Result map for Wired-and output values (open collector)
----------------------------------------------------------------------------
CONSTANT STD_wired_and_rmap : VitalResultMapType := ('U','X','0','Z');
----------------------------------------------------------------------------
-- Table for computing a single signal from a differential receiver input
-- pair.
----------------------------------------------------------------------------
CONSTANT diff_rec_tab : VitalStateTableType := (
------INPUTS--|-PREV-|-OUTPUT----
-- A ANeg | Aint | Aint' --
--------------|------|-----------
( 'X', '-', '-', 'X'), -- A unknown
( '-', 'X', '-', 'X'), -- A unknown
( '1', '-', 'X', '1'), -- Recover from 'X'
( '0', '-', 'X', '0'), -- Recover from 'X'
( '/', '0', '0', '1'), -- valid diff. rising edge
( '1', '\', '0', '1'), -- valid diff. rising edge
( '\', '1', '1', '0'), -- valid diff. falling edge
( '0', '/', '1', '0'), -- valid diff. falling edge
( '-', '-', '-', 'S') -- default
); -- end of VitalStateTableType definition
----------------------------------------------------------------------------
-- Default Constants
----------------------------------------------------------------------------
CONSTANT UnitDelay : VitalDelayType := 1 ns;
CONSTANT UnitDelay01 : VitalDelayType01 := (1 ns, 1 ns);
CONSTANT UnitDelay01Z : VitalDelayType01Z := (others => 1 ns);
CONSTANT UnitDelay01ZX : VitalDelayType01ZX := (others => 1 ns);
CONSTANT DefaultInstancePath : STRING := "*";
CONSTANT DefaultTimingChecks : BOOLEAN := FALSE;
CONSTANT DefaultTimingModel : STRING := "UNIT";
CONSTANT DefaultXon : BOOLEAN := TRUE;
CONSTANT DefaultMsgOn : BOOLEAN := TRUE;
-- Older VITAL generic being phased out
CONSTANT DefaultXGeneration : BOOLEAN := TRUE;
-------------------------------------------------------------------
-- Generate Parity for each 8-bit in 9th bit
-------------------------------------------------------------------
FUNCTION GenParity
(Data : in std_logic_vector; -- Data
ODDEVEN : in std_logic; -- ODD (1) / EVEN(0)
SIZE : in POSITIVE) -- Bit Size
RETURN std_logic_vector;
-------------------------------------------------------------------
-- Check Parity for each 8-bit in 9th bit
-------------------------------------------------------------------
FUNCTION CheckParity
(Data : in std_logic_vector; -- Data
ODDEVEN : in std_logic; -- ODD (1) / EVEN(0)
SIZE : in POSITIVE) -- Bit Size
RETURN std_logic; -- '0' - Parity Error
END gen_utils;
PACKAGE BODY gen_utils IS
function XOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 403
variable result: STD_LOGIC;
begin
result := '0';
for i in ARG'range loop
result := result xor ARG(i);
end loop;
return result;
end;
-------------------------------------------------------------------
-- Generate Parity for each 8-bit in 9th bit
-------------------------------------------------------------------
FUNCTION GenParity
(Data : in std_logic_vector; -- Data
ODDEVEN : in std_logic; -- ODD (1) / EVEN(0)
SIZE : in POSITIVE) -- Bit Size
RETURN std_logic_vector
IS
VARIABLE I: NATURAL;
VARIABLE Result: std_logic_vector (Data'Length - 1 DOWNTO 0);
BEGIN
I := 0;
WHILE (I < SIZE) LOOP
Result(I+7 DOWNTO I) := Data(I+7 downto I);
Result(I+8) := XOR_REDUCE( Data(I+7 downto I) ) XOR ODDEVEN;
I := I + 9;
END LOOP;
RETURN Result;
END GenParity;
-------------------------------------------------------------------
-- Check Parity for each 8-bit in 9th bit
-------------------------------------------------------------------
FUNCTION CheckParity
(Data : in std_logic_vector; -- Data
ODDEVEN : in std_logic; -- ODD (1) / EVEN(0)
SIZE : in POSITIVE) -- Bit Size
RETURN std_logic -- '0' - Parity Error
IS
VARIABLE I: NATURAL;
VARIABLE Result: std_logic;
BEGIN
I := 0; Result := '1';
WHILE (I < SIZE) LOOP
Result := Result AND
NOT (XOR_REDUCE( Data(I+8 downto I) ) XOR ODDEVEN);
I := I + 9;
END LOOP;
RETURN Result;
END CheckParity;
END gen_utils;
|
--------------------------------------------------------------------------------
-- File name: gen_utils.vhd
--------------------------------------------------------------------------------
-- Copyright (C) 1996, 1998, 2001 Free Model Foundry; http://eda.org/fmf/
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License version 2 as
-- published by the Free Software Foundation.
--
-- MODIFICATION HISTORY:
--
-- version: | author: | mod date: | changes made:
-- V1.0 R. Steele 96 SEP 26 Initial release
-- V1.1 REV3 97 Feb 27 Added Xon and MsgOn generics
-- V1.2 R. Steele 97 APR 16 Changed wired-or to wired-and
-- V1.3 R. Steele 97 APR 16 Added diff. receiver table
-- V1.4 R. Munden 98 APR 13 Added GenParity and CheckParity
-- V1.5 R. Munden 01 NOV 24 Added UnitDelay01ZX
--
--------------------------------------------------------------------------------
LIBRARY IEEE; USE IEEE.std_Logic_1164.ALL;
USE IEEE.VITAL_primitives.ALL;
USE IEEE.VITAL_timing.ALL;
PACKAGE gen_utils IS
----------------------------------------------------------------------------
-- Result map for Wired-and output values (open collector)
----------------------------------------------------------------------------
CONSTANT STD_wired_and_rmap : VitalResultMapType := ('U','X','0','Z');
----------------------------------------------------------------------------
-- Table for computing a single signal from a differential receiver input
-- pair.
----------------------------------------------------------------------------
CONSTANT diff_rec_tab : VitalStateTableType := (
------INPUTS--|-PREV-|-OUTPUT----
-- A ANeg | Aint | Aint' --
--------------|------|-----------
( 'X', '-', '-', 'X'), -- A unknown
( '-', 'X', '-', 'X'), -- A unknown
( '1', '-', 'X', '1'), -- Recover from 'X'
( '0', '-', 'X', '0'), -- Recover from 'X'
( '/', '0', '0', '1'), -- valid diff. rising edge
( '1', '\', '0', '1'), -- valid diff. rising edge
( '\', '1', '1', '0'), -- valid diff. falling edge
( '0', '/', '1', '0'), -- valid diff. falling edge
( '-', '-', '-', 'S') -- default
); -- end of VitalStateTableType definition
----------------------------------------------------------------------------
-- Default Constants
----------------------------------------------------------------------------
CONSTANT UnitDelay : VitalDelayType := 1 ns;
CONSTANT UnitDelay01 : VitalDelayType01 := (1 ns, 1 ns);
CONSTANT UnitDelay01Z : VitalDelayType01Z := (others => 1 ns);
CONSTANT UnitDelay01ZX : VitalDelayType01ZX := (others => 1 ns);
CONSTANT DefaultInstancePath : STRING := "*";
CONSTANT DefaultTimingChecks : BOOLEAN := FALSE;
CONSTANT DefaultTimingModel : STRING := "UNIT";
CONSTANT DefaultXon : BOOLEAN := TRUE;
CONSTANT DefaultMsgOn : BOOLEAN := TRUE;
-- Older VITAL generic being phased out
CONSTANT DefaultXGeneration : BOOLEAN := TRUE;
-------------------------------------------------------------------
-- Generate Parity for each 8-bit in 9th bit
-------------------------------------------------------------------
FUNCTION GenParity
(Data : in std_logic_vector; -- Data
ODDEVEN : in std_logic; -- ODD (1) / EVEN(0)
SIZE : in POSITIVE) -- Bit Size
RETURN std_logic_vector;
-------------------------------------------------------------------
-- Check Parity for each 8-bit in 9th bit
-------------------------------------------------------------------
FUNCTION CheckParity
(Data : in std_logic_vector; -- Data
ODDEVEN : in std_logic; -- ODD (1) / EVEN(0)
SIZE : in POSITIVE) -- Bit Size
RETURN std_logic; -- '0' - Parity Error
END gen_utils;
PACKAGE BODY gen_utils IS
function XOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 403
variable result: STD_LOGIC;
begin
result := '0';
for i in ARG'range loop
result := result xor ARG(i);
end loop;
return result;
end;
-------------------------------------------------------------------
-- Generate Parity for each 8-bit in 9th bit
-------------------------------------------------------------------
FUNCTION GenParity
(Data : in std_logic_vector; -- Data
ODDEVEN : in std_logic; -- ODD (1) / EVEN(0)
SIZE : in POSITIVE) -- Bit Size
RETURN std_logic_vector
IS
VARIABLE I: NATURAL;
VARIABLE Result: std_logic_vector (Data'Length - 1 DOWNTO 0);
BEGIN
I := 0;
WHILE (I < SIZE) LOOP
Result(I+7 DOWNTO I) := Data(I+7 downto I);
Result(I+8) := XOR_REDUCE( Data(I+7 downto I) ) XOR ODDEVEN;
I := I + 9;
END LOOP;
RETURN Result;
END GenParity;
-------------------------------------------------------------------
-- Check Parity for each 8-bit in 9th bit
-------------------------------------------------------------------
FUNCTION CheckParity
(Data : in std_logic_vector; -- Data
ODDEVEN : in std_logic; -- ODD (1) / EVEN(0)
SIZE : in POSITIVE) -- Bit Size
RETURN std_logic -- '0' - Parity Error
IS
VARIABLE I: NATURAL;
VARIABLE Result: std_logic;
BEGIN
I := 0; Result := '1';
WHILE (I < SIZE) LOOP
Result := Result AND
NOT (XOR_REDUCE( Data(I+8 downto I) ) XOR ODDEVEN);
I := I + 9;
END LOOP;
RETURN Result;
END CheckParity;
END gen_utils;
|
--------------------------------------------------------------------------------
-- File name: gen_utils.vhd
--------------------------------------------------------------------------------
-- Copyright (C) 1996, 1998, 2001 Free Model Foundry; http://eda.org/fmf/
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License version 2 as
-- published by the Free Software Foundation.
--
-- MODIFICATION HISTORY:
--
-- version: | author: | mod date: | changes made:
-- V1.0 R. Steele 96 SEP 26 Initial release
-- V1.1 REV3 97 Feb 27 Added Xon and MsgOn generics
-- V1.2 R. Steele 97 APR 16 Changed wired-or to wired-and
-- V1.3 R. Steele 97 APR 16 Added diff. receiver table
-- V1.4 R. Munden 98 APR 13 Added GenParity and CheckParity
-- V1.5 R. Munden 01 NOV 24 Added UnitDelay01ZX
--
--------------------------------------------------------------------------------
LIBRARY IEEE; USE IEEE.std_Logic_1164.ALL;
USE IEEE.VITAL_primitives.ALL;
USE IEEE.VITAL_timing.ALL;
PACKAGE gen_utils IS
----------------------------------------------------------------------------
-- Result map for Wired-and output values (open collector)
----------------------------------------------------------------------------
CONSTANT STD_wired_and_rmap : VitalResultMapType := ('U','X','0','Z');
----------------------------------------------------------------------------
-- Table for computing a single signal from a differential receiver input
-- pair.
----------------------------------------------------------------------------
CONSTANT diff_rec_tab : VitalStateTableType := (
------INPUTS--|-PREV-|-OUTPUT----
-- A ANeg | Aint | Aint' --
--------------|------|-----------
( 'X', '-', '-', 'X'), -- A unknown
( '-', 'X', '-', 'X'), -- A unknown
( '1', '-', 'X', '1'), -- Recover from 'X'
( '0', '-', 'X', '0'), -- Recover from 'X'
( '/', '0', '0', '1'), -- valid diff. rising edge
( '1', '\', '0', '1'), -- valid diff. rising edge
( '\', '1', '1', '0'), -- valid diff. falling edge
( '0', '/', '1', '0'), -- valid diff. falling edge
( '-', '-', '-', 'S') -- default
); -- end of VitalStateTableType definition
----------------------------------------------------------------------------
-- Default Constants
----------------------------------------------------------------------------
CONSTANT UnitDelay : VitalDelayType := 1 ns;
CONSTANT UnitDelay01 : VitalDelayType01 := (1 ns, 1 ns);
CONSTANT UnitDelay01Z : VitalDelayType01Z := (others => 1 ns);
CONSTANT UnitDelay01ZX : VitalDelayType01ZX := (others => 1 ns);
CONSTANT DefaultInstancePath : STRING := "*";
CONSTANT DefaultTimingChecks : BOOLEAN := FALSE;
CONSTANT DefaultTimingModel : STRING := "UNIT";
CONSTANT DefaultXon : BOOLEAN := TRUE;
CONSTANT DefaultMsgOn : BOOLEAN := TRUE;
-- Older VITAL generic being phased out
CONSTANT DefaultXGeneration : BOOLEAN := TRUE;
-------------------------------------------------------------------
-- Generate Parity for each 8-bit in 9th bit
-------------------------------------------------------------------
FUNCTION GenParity
(Data : in std_logic_vector; -- Data
ODDEVEN : in std_logic; -- ODD (1) / EVEN(0)
SIZE : in POSITIVE) -- Bit Size
RETURN std_logic_vector;
-------------------------------------------------------------------
-- Check Parity for each 8-bit in 9th bit
-------------------------------------------------------------------
FUNCTION CheckParity
(Data : in std_logic_vector; -- Data
ODDEVEN : in std_logic; -- ODD (1) / EVEN(0)
SIZE : in POSITIVE) -- Bit Size
RETURN std_logic; -- '0' - Parity Error
END gen_utils;
PACKAGE BODY gen_utils IS
function XOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 403
variable result: STD_LOGIC;
begin
result := '0';
for i in ARG'range loop
result := result xor ARG(i);
end loop;
return result;
end;
-------------------------------------------------------------------
-- Generate Parity for each 8-bit in 9th bit
-------------------------------------------------------------------
FUNCTION GenParity
(Data : in std_logic_vector; -- Data
ODDEVEN : in std_logic; -- ODD (1) / EVEN(0)
SIZE : in POSITIVE) -- Bit Size
RETURN std_logic_vector
IS
VARIABLE I: NATURAL;
VARIABLE Result: std_logic_vector (Data'Length - 1 DOWNTO 0);
BEGIN
I := 0;
WHILE (I < SIZE) LOOP
Result(I+7 DOWNTO I) := Data(I+7 downto I);
Result(I+8) := XOR_REDUCE( Data(I+7 downto I) ) XOR ODDEVEN;
I := I + 9;
END LOOP;
RETURN Result;
END GenParity;
-------------------------------------------------------------------
-- Check Parity for each 8-bit in 9th bit
-------------------------------------------------------------------
FUNCTION CheckParity
(Data : in std_logic_vector; -- Data
ODDEVEN : in std_logic; -- ODD (1) / EVEN(0)
SIZE : in POSITIVE) -- Bit Size
RETURN std_logic -- '0' - Parity Error
IS
VARIABLE I: NATURAL;
VARIABLE Result: std_logic;
BEGIN
I := 0; Result := '1';
WHILE (I < SIZE) LOOP
Result := Result AND
NOT (XOR_REDUCE( Data(I+8 downto I) ) XOR ODDEVEN);
I := I + 9;
END LOOP;
RETURN Result;
END CheckParity;
END gen_utils;
|
--------------------------------------------------------------------------------
-- File name: gen_utils.vhd
--------------------------------------------------------------------------------
-- Copyright (C) 1996, 1998, 2001 Free Model Foundry; http://eda.org/fmf/
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License version 2 as
-- published by the Free Software Foundation.
--
-- MODIFICATION HISTORY:
--
-- version: | author: | mod date: | changes made:
-- V1.0 R. Steele 96 SEP 26 Initial release
-- V1.1 REV3 97 Feb 27 Added Xon and MsgOn generics
-- V1.2 R. Steele 97 APR 16 Changed wired-or to wired-and
-- V1.3 R. Steele 97 APR 16 Added diff. receiver table
-- V1.4 R. Munden 98 APR 13 Added GenParity and CheckParity
-- V1.5 R. Munden 01 NOV 24 Added UnitDelay01ZX
--
--------------------------------------------------------------------------------
LIBRARY IEEE; USE IEEE.std_Logic_1164.ALL;
USE IEEE.VITAL_primitives.ALL;
USE IEEE.VITAL_timing.ALL;
PACKAGE gen_utils IS
----------------------------------------------------------------------------
-- Result map for Wired-and output values (open collector)
----------------------------------------------------------------------------
CONSTANT STD_wired_and_rmap : VitalResultMapType := ('U','X','0','Z');
----------------------------------------------------------------------------
-- Table for computing a single signal from a differential receiver input
-- pair.
----------------------------------------------------------------------------
CONSTANT diff_rec_tab : VitalStateTableType := (
------INPUTS--|-PREV-|-OUTPUT----
-- A ANeg | Aint | Aint' --
--------------|------|-----------
( 'X', '-', '-', 'X'), -- A unknown
( '-', 'X', '-', 'X'), -- A unknown
( '1', '-', 'X', '1'), -- Recover from 'X'
( '0', '-', 'X', '0'), -- Recover from 'X'
( '/', '0', '0', '1'), -- valid diff. rising edge
( '1', '\', '0', '1'), -- valid diff. rising edge
( '\', '1', '1', '0'), -- valid diff. falling edge
( '0', '/', '1', '0'), -- valid diff. falling edge
( '-', '-', '-', 'S') -- default
); -- end of VitalStateTableType definition
----------------------------------------------------------------------------
-- Default Constants
----------------------------------------------------------------------------
CONSTANT UnitDelay : VitalDelayType := 1 ns;
CONSTANT UnitDelay01 : VitalDelayType01 := (1 ns, 1 ns);
CONSTANT UnitDelay01Z : VitalDelayType01Z := (others => 1 ns);
CONSTANT UnitDelay01ZX : VitalDelayType01ZX := (others => 1 ns);
CONSTANT DefaultInstancePath : STRING := "*";
CONSTANT DefaultTimingChecks : BOOLEAN := FALSE;
CONSTANT DefaultTimingModel : STRING := "UNIT";
CONSTANT DefaultXon : BOOLEAN := TRUE;
CONSTANT DefaultMsgOn : BOOLEAN := TRUE;
-- Older VITAL generic being phased out
CONSTANT DefaultXGeneration : BOOLEAN := TRUE;
-------------------------------------------------------------------
-- Generate Parity for each 8-bit in 9th bit
-------------------------------------------------------------------
FUNCTION GenParity
(Data : in std_logic_vector; -- Data
ODDEVEN : in std_logic; -- ODD (1) / EVEN(0)
SIZE : in POSITIVE) -- Bit Size
RETURN std_logic_vector;
-------------------------------------------------------------------
-- Check Parity for each 8-bit in 9th bit
-------------------------------------------------------------------
FUNCTION CheckParity
(Data : in std_logic_vector; -- Data
ODDEVEN : in std_logic; -- ODD (1) / EVEN(0)
SIZE : in POSITIVE) -- Bit Size
RETURN std_logic; -- '0' - Parity Error
END gen_utils;
PACKAGE BODY gen_utils IS
function XOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 403
variable result: STD_LOGIC;
begin
result := '0';
for i in ARG'range loop
result := result xor ARG(i);
end loop;
return result;
end;
-------------------------------------------------------------------
-- Generate Parity for each 8-bit in 9th bit
-------------------------------------------------------------------
FUNCTION GenParity
(Data : in std_logic_vector; -- Data
ODDEVEN : in std_logic; -- ODD (1) / EVEN(0)
SIZE : in POSITIVE) -- Bit Size
RETURN std_logic_vector
IS
VARIABLE I: NATURAL;
VARIABLE Result: std_logic_vector (Data'Length - 1 DOWNTO 0);
BEGIN
I := 0;
WHILE (I < SIZE) LOOP
Result(I+7 DOWNTO I) := Data(I+7 downto I);
Result(I+8) := XOR_REDUCE( Data(I+7 downto I) ) XOR ODDEVEN;
I := I + 9;
END LOOP;
RETURN Result;
END GenParity;
-------------------------------------------------------------------
-- Check Parity for each 8-bit in 9th bit
-------------------------------------------------------------------
FUNCTION CheckParity
(Data : in std_logic_vector; -- Data
ODDEVEN : in std_logic; -- ODD (1) / EVEN(0)
SIZE : in POSITIVE) -- Bit Size
RETURN std_logic -- '0' - Parity Error
IS
VARIABLE I: NATURAL;
VARIABLE Result: std_logic;
BEGIN
I := 0; Result := '1';
WHILE (I < SIZE) LOOP
Result := Result AND
NOT (XOR_REDUCE( Data(I+8 downto I) ) XOR ODDEVEN);
I := I + 9;
END LOOP;
RETURN Result;
END CheckParity;
END gen_utils;
|
--------------------------------------------------------------------------------
-- File name: gen_utils.vhd
--------------------------------------------------------------------------------
-- Copyright (C) 1996, 1998, 2001 Free Model Foundry; http://eda.org/fmf/
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License version 2 as
-- published by the Free Software Foundation.
--
-- MODIFICATION HISTORY:
--
-- version: | author: | mod date: | changes made:
-- V1.0 R. Steele 96 SEP 26 Initial release
-- V1.1 REV3 97 Feb 27 Added Xon and MsgOn generics
-- V1.2 R. Steele 97 APR 16 Changed wired-or to wired-and
-- V1.3 R. Steele 97 APR 16 Added diff. receiver table
-- V1.4 R. Munden 98 APR 13 Added GenParity and CheckParity
-- V1.5 R. Munden 01 NOV 24 Added UnitDelay01ZX
--
--------------------------------------------------------------------------------
LIBRARY IEEE; USE IEEE.std_Logic_1164.ALL;
USE IEEE.VITAL_primitives.ALL;
USE IEEE.VITAL_timing.ALL;
PACKAGE gen_utils IS
----------------------------------------------------------------------------
-- Result map for Wired-and output values (open collector)
----------------------------------------------------------------------------
CONSTANT STD_wired_and_rmap : VitalResultMapType := ('U','X','0','Z');
----------------------------------------------------------------------------
-- Table for computing a single signal from a differential receiver input
-- pair.
----------------------------------------------------------------------------
CONSTANT diff_rec_tab : VitalStateTableType := (
------INPUTS--|-PREV-|-OUTPUT----
-- A ANeg | Aint | Aint' --
--------------|------|-----------
( 'X', '-', '-', 'X'), -- A unknown
( '-', 'X', '-', 'X'), -- A unknown
( '1', '-', 'X', '1'), -- Recover from 'X'
( '0', '-', 'X', '0'), -- Recover from 'X'
( '/', '0', '0', '1'), -- valid diff. rising edge
( '1', '\', '0', '1'), -- valid diff. rising edge
( '\', '1', '1', '0'), -- valid diff. falling edge
( '0', '/', '1', '0'), -- valid diff. falling edge
( '-', '-', '-', 'S') -- default
); -- end of VitalStateTableType definition
----------------------------------------------------------------------------
-- Default Constants
----------------------------------------------------------------------------
CONSTANT UnitDelay : VitalDelayType := 1 ns;
CONSTANT UnitDelay01 : VitalDelayType01 := (1 ns, 1 ns);
CONSTANT UnitDelay01Z : VitalDelayType01Z := (others => 1 ns);
CONSTANT UnitDelay01ZX : VitalDelayType01ZX := (others => 1 ns);
CONSTANT DefaultInstancePath : STRING := "*";
CONSTANT DefaultTimingChecks : BOOLEAN := FALSE;
CONSTANT DefaultTimingModel : STRING := "UNIT";
CONSTANT DefaultXon : BOOLEAN := TRUE;
CONSTANT DefaultMsgOn : BOOLEAN := TRUE;
-- Older VITAL generic being phased out
CONSTANT DefaultXGeneration : BOOLEAN := TRUE;
-------------------------------------------------------------------
-- Generate Parity for each 8-bit in 9th bit
-------------------------------------------------------------------
FUNCTION GenParity
(Data : in std_logic_vector; -- Data
ODDEVEN : in std_logic; -- ODD (1) / EVEN(0)
SIZE : in POSITIVE) -- Bit Size
RETURN std_logic_vector;
-------------------------------------------------------------------
-- Check Parity for each 8-bit in 9th bit
-------------------------------------------------------------------
FUNCTION CheckParity
(Data : in std_logic_vector; -- Data
ODDEVEN : in std_logic; -- ODD (1) / EVEN(0)
SIZE : in POSITIVE) -- Bit Size
RETURN std_logic; -- '0' - Parity Error
END gen_utils;
PACKAGE BODY gen_utils IS
function XOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 403
variable result: STD_LOGIC;
begin
result := '0';
for i in ARG'range loop
result := result xor ARG(i);
end loop;
return result;
end;
-------------------------------------------------------------------
-- Generate Parity for each 8-bit in 9th bit
-------------------------------------------------------------------
FUNCTION GenParity
(Data : in std_logic_vector; -- Data
ODDEVEN : in std_logic; -- ODD (1) / EVEN(0)
SIZE : in POSITIVE) -- Bit Size
RETURN std_logic_vector
IS
VARIABLE I: NATURAL;
VARIABLE Result: std_logic_vector (Data'Length - 1 DOWNTO 0);
BEGIN
I := 0;
WHILE (I < SIZE) LOOP
Result(I+7 DOWNTO I) := Data(I+7 downto I);
Result(I+8) := XOR_REDUCE( Data(I+7 downto I) ) XOR ODDEVEN;
I := I + 9;
END LOOP;
RETURN Result;
END GenParity;
-------------------------------------------------------------------
-- Check Parity for each 8-bit in 9th bit
-------------------------------------------------------------------
FUNCTION CheckParity
(Data : in std_logic_vector; -- Data
ODDEVEN : in std_logic; -- ODD (1) / EVEN(0)
SIZE : in POSITIVE) -- Bit Size
RETURN std_logic -- '0' - Parity Error
IS
VARIABLE I: NATURAL;
VARIABLE Result: std_logic;
BEGIN
I := 0; Result := '1';
WHILE (I < SIZE) LOOP
Result := Result AND
NOT (XOR_REDUCE( Data(I+8 downto I) ) XOR ODDEVEN);
I := I + 9;
END LOOP;
RETURN Result;
END CheckParity;
END gen_utils;
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.