Newsgroup: it.hobby.elettronica.digitale
Titolo: Codice x ST6

Salve,
Avrei bisogno di effettuare una divisione a 24 bit con l' ST6 con
risultato su tre byte come nell'esempio
sotto riportato:
           byte1  byte2  byte3  :    dividendo
           byteA byteB  byteC =      divisore
       --------------------------
           res1   res2     res3  risultato (il resto non lo considero)
Grazie in anticipo a chiunque possa aiutarmi.
Saluti   Massimiliano.

;+-----------------------------------------------------------------------+
;|                      SGS THOMSON Microelectronics                     |
;|                                                                       |
;| ST6 Software Library:   DIV_24.ASM                                    |
;| ---------------------   ----------   Revision:       0.01             |
;|                                      Date:           2nd Sept 93      |
;|                                      Author:         David Lamb       |
;|                                                                       |
;| Description                                                           |
;| -----------                                                           |
;| 24 bit by pseudo-24 bit divide routine, developed as a benchmark      |
;| routine only.                                                         |
;|                                                                       |
;| This routine assumes that the denominator is held in D1/D2/D3 and     |
;| the numerator is held in PN1/PN2/PN3. The result appears in registers |
;| N3/N4/N5/N6.                                                          |
;|                                                                       |
;| The routine is actually a 24/16 bit divide. If the most significant   |
;| byte of the 24 bit denominator is non-zero, the two upper bytes are   |
;| used. If the most significant byte is zero, the two lower bytes are   |
;| used.                                                                 |
;|                                                                       |
;| Worst Case Timings (including setup and return)                       |
;| -----------------------------------------------                       |
;| 33 loop (MS byte of denominator non-zero) divide: 1225 instr. cycles  |
;| 41 loop (MS byte of denominator = zero)   divide: 1489 instr. cycles  |
;|                                                                       |
;| At 8MHz oscillator frequency, 1 instruction cycle is 1.625us.         |
;| therefore 33 loop divide = 1.99 ms (approx)                           |
;|           41 loop divide = 2.42 ms (approx)                           |
;|                                                                       |
;| Principle of Operation                                                |
;| ----------------------                                                |
;| The numerator is shifted, bit by bit, past the denominator. At each   |
;| step, the denominator is subtracted from the numerator (16 bit sub).  |
;| If the numerator is smaller than the denominator, the carry flag is   |
;| set, and is shifted into the lsb of the extended numerator.           |
;| If the numerator is larger than, or equal to, the denominator, the    |
;| carry flag is reset, and is shifted into the lsb of the extended      |
;| numerator. Additionally, the most significant 16 bits of the extended |
;| numerator are replaced with the result of the subtraction.            |
;| Finally, the 4 byte result (N3..N6) is complemented, as the sense of  |
;| the carry flag is opposite to the required result.                    |
;|                                                                       |
;|                  Shift numerator LEFT across denominator              |
;|        <------    <------    <------    <------    <------    <---    |
;|   +-----+    +-----+    +-----+    +-----+    +-----+    +-----+      |
;|   |  N1 |    |  N2 |    |  N3 |    |  N4 |    |  N5 |    |  N6 | [CY] |
;|   +-----+    +-----+    +-----+    +-----+    +-----+    +-----+      |
;|                           PN1        PN2        PN3                   |
;|      |          |       \___________________________/                 |
;|      |          |         original 24 bit numerator                   |
;|      |          |                                                     |
;|   +-----+    +-----+                                                  |
;|   | D1  |    | D2  | --> 16 bit denominator                           |
;|   +-----+    +-----+                                                  |
;|                                                                       |
;|      Subtraction                                                      |
;|                                                                       |
;|              NOTE: THIS ROUTINE HAS NOT BEEN FULLY TESTED             |
;+-----------------------------------------------------------------------+
        .DISPLAY ""
        .DISPLAY " DIV_24 "
        .DISPLAY " ------ "
        .DISPLAY ""
;+-----------------------------------------------------------------------+
;+-----------------------------------------------------------------------+
;+-------------------------------+
;| assembler / linker directives |
;+-------------------------------+
        .PP_ON                          ;enable linker
        .W_ON                           ;enable data ROM windowing
        .DP_ON                          ;enable data space paging
;+------------------------+
;| data space definitions |
;+------------------------+
; general purpose definitions
A               .DEF 0FFH,0FFH,0FFH,M   ;accumulator
X               .DEF 080H,0FFH,0FFH     ;index register
Y               .DEF 081H,0FFH,0FFH     ;index register
V               .DEF 082H,0FFH,0FFH     ;short access register
W               .DEF 083H,0FFH,0FFH     ;short access register
;numerator definitions
N1              .DEF 084H,0FFH,0FFH,M           ;numerator working
registers
N2              .DEF 085H,0FFH,0FFH,M
N3              .DEF 086H,0FFH,0FFH,M
N4              .DEF 087H,0FFH,0FFH,M
N5              .DEF 088H,0FFH,0FFH,M
N6              .DEF 089H,0FFH,0FFH,M
;denominator definitions
D1              .DEF 08AH,0FFH,0FFH             ;denominator registers
D2              .DEF 08BH,0FFH,0FFH
D3              .DEF 08CH,0FFH,0FFH
;operation counter
COUNTER         .DEF 08DH,0FFH,0FFH             ;loop counter for divide
cycle
;temporary storage
TEMP            .DEF 08EH,0FFH,0FFH             ;general purpose storage
;parameter passing
PN1             .DEF 090H,0FFH,0FFH,M           ;numerator registers
PN2             .DEF 091H,0FFH,0FFH,M
PN3             .DEF 092H,0FFH,0FFH,M
;management
DIV_FLGS        .DEF 093H,0FFH,0FFH             ;program control flags
BORROW          .EQU 00H
;+------------+
;| CODE SPACE |
;+------------+
        .SECTION 1
RESTART:
; Initialize registers
        LD   A,PN3                      ;transfer numerator into working
regs.
        LD   N5,A
        LD   A,PN2
        LD   N4,A
        LD   A,PN1
        LD   N3,A
        CLR  N1                         ;intialize remaining numerator
regs.
        CLR  N2
        CLR  N6
        LDI  COUNTER,#33                ;operations count for
                                        ;24 bit denominator
;initialise carry
        ADDI A,#0FFH                    ;alternative way of setting carry
;copy denominator into working regs.
        LD   A,D2                       ;initialize denominator working
regs.
        LD   W,A
        LD   A,D1
        LD   V,A
; check denominator MS byte for non-zero
        LD   A,V
        JRNZ DIV_LOOP
; if MS byte is zero, use lower bytes
        LD   A,W
        LD   V,A
        LD   A,D3
        LD   W,A
        LDI  COUNTER,#41                ;operations count for
                                        ;16 bit denominator
DIV_LOOP:
;ripple through numerator
        LD   A,N6
        RLC  A
        LD   N6,A
        LD   A,N5
        RLC  A
        LD   N5,A
        LD   A,N4
        RLC  A
        LD   N4,A
        LD   A,N3
        RLC  A
        LD   N3,A
        LD   A,N2
        RLC  A
        LD   N2,A
        LD   A,N1
        RLC  A
        LD   N1,A
; Now subtract denominator from most significant 16 bits of extended
; numerator.
SUB_16:
        RES  BORROW,DIV_FLGS                    ;clear borrow flag
        LD   A,N2                               ;get lower byte
        SUB  A,W                                ;subtract denominator
        LD   TEMP,A                             ;keep copy of result
        LD   A,N1                               ;get upper byte
        JRNC SUB_MSB                            ;jump if prev. subtract OK
        SET  BORROW,DIV_FLGS                    ;indicate borrow
SUB_MSB:
        SUB  A,V                                ;subtract denominator
        JRC  END_SUB                            ;jump if denom. > numer.
        JRR  BORROW,DIV_FLGS,SM_100             ;jump if no borrow
        SUBI A,#01h                             ;account for borrow
        JRC  END_SUB                            ;jump if denom > numer.
SM_100: LD   N1,A                               ;update numerator
        LD   A,TEMP
        LD   N2,A
END_SUB:
        DEC  COUNTER                            ;decrement loop counter
        JRZ  DONE                               ;done?
        JP   DIV_LOOP                           ;no, next loop
DONE:
;complement result
        LD   A,N6
        COM  A
        LD   N6,A
        LD   A,N5
        COM  A
        LD   N5,A
        LD   A,N4
        COM  A
        LD   N4,A
        LD   A,N3
        COM  A
        LD   N3,A
END_D24:
        STOP                    ;replace with RET if used as subroutine
;+-----------------------------------------------------------------------+
;+-----------------------------------------------------------------------+
;+---------+
;| VECTORS |
;+---------+
        .SECTION 32             ;vector space
        .BLOCK 0Eh              ;reserve space for interrupt vectors
        JP   RESTART            ;reset vector
.END
Massimiliano - IW2KJJ ha scritto:

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