hdl/modules/position_calc/*/virtex6: major bug fix

This patch fixes a major bug introduced in the last
big change (from commit f809ea80e0 to commit 843c8ceb4f).

* Change Delta-Sigma FIFO to Standard FIFO, instead
  of FWFT FIFO

* Only read from FIFO when not empty, as required by
  Sysgen. Otherwise, it gives an error.
hdl/modules/position_calc/*/artix7: add artix7 files and major bug fix

This introduces the latest changes from commit
f809ea80e0 to commit 843c8ceb4f to artix7 FPGAs.

This patch also fixes a major bug introduced in the last
big change (f809ea80e0 to commit 843c8ceb4f).

* Change Delta-Sigma FIFO to Standard FIFO, instead
  of FWFT FIFO

* Only read from FIFO when not empty, as required by
  Sysgen. Otherwise, it gives an error.
models/*: new sysgen model to match latest fixes