Verify that llvm can generate the prefetchw instruction when the CPU is
Atom Silvermont.

Patch by Sriram Murali.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190957 91177308-0d34-0410-b5e6-96231b3b80d8
Attempt to fix llvm-ppc64-linux2 buildbot failure by adding
-march=x86 to SLM test.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190958 91177308-0d34-0410-b5e6-96231b3b80d8
Debug info: Get rid of the VLA indirection hack in FastISel.
Use the DIVariable::isIndirect() flag set by the frontend instead of
guessing whether to set the machine location's indirection bit.
Paired commit with CFE.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190961 91177308-0d34-0410-b5e6-96231b3b80d8
Fix two issues regarding Got pointer (GP) setup.
1) make sure that the first two instructions of the sequence cannot
separate from each other. The linker requires that they be sequential.
If they get separated, it can still work but it will not work in all
cases because the first of the instructions mostly involves the hi part
of the pc relative offset and that part changes slowly. You would have
to be at the right boundary for this to matter.
2) make sure that this sequence begins  on a longword boundary. 
There appears to be a bug in binutils which makes some of these calculations
get messed up if the instruction sequence does not begin on a longword
boundary. This is being investigated with the appropriate binutils folks.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190966 91177308-0d34-0410-b5e6-96231b3b80d8
whitespace

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190973 91177308-0d34-0410-b5e6-96231b3b80d8
Encapsulate PassManager debug flags to avoid static init and cxa_exit.

This puts all the global PassManager debugging flags, like
-print-after-all and -time-passes, behind a managed static. This
eliminates their static initializers and, more importantly, exit-time
destructors.

The only behavioral change I anticipate is that tools need to
initialize the PassManager before parsing the command line in order to
export these options, which makes sense. Tools that already initialize
the standard passes (opt/llc) don't need to do anything new.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190974 91177308-0d34-0410-b5e6-96231b3b80d8
Revert "Encapsulate PassManager debug flags to avoid static init and cxa_exit."

Working on a better solution to this.

This reverts commit 7d4e9934e7ca83094c5cf41346966c8350179ff2.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190990 91177308-0d34-0410-b5e6-96231b3b80d8
X86: FrameIndex addressing modes do have a base register.

When selecting the DAG (add (WrapperRIP ...), (FrameIndex ...)), X86 code had
spotted the FrameIndex possibility and was working out whether it could fold
the WrapperRIP into this.

The test for forming a %rip version is notionally whether we already have a
base or index register (%rip precludes both), but we were forgetting to account
for the register that would be inserted later to access the frame.

rdar://problem/15024520

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190995 91177308-0d34-0410-b5e6-96231b3b80d8
[ARMv8] Add support for the v8 cryptography extensions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190996 91177308-0d34-0410-b5e6-96231b3b80d8
[NVPTX] Support constant vector globals

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190997 91177308-0d34-0410-b5e6-96231b3b80d8
[NVPTX] Make constant vector test case endian-independent

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190998 91177308-0d34-0410-b5e6-96231b3b80d8
DAGCombiner: Don't fold vector muls with constants that look like a splat of a power of 2 but differ in bit width.

PR17283.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191000 91177308-0d34-0410-b5e6-96231b3b80d8
[msan] Wrap indirect functions.

Adds a flag to the MemorySanitizer pass that enables runtime rewriting of
indirect calls. This is part of MSanDR implementation and is needed to return
control to the DynamiRio-based helper tool on transition between instrumented
and non-instrumented modules. Disabled by default.


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Include an LLVM-vs2012_xp toolset in the MSBuild integration

Patch by Paul Hampson!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191010 91177308-0d34-0410-b5e6-96231b3b80d8
  Add function DominatorTree::getDescendants(). 

  As its name suggests, this function will return all basic blocks
dominated by a given block.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191014 91177308-0d34-0410-b5e6-96231b3b80d8
msbuild: Set _MSC_VER to match the CRT we're using

Various Windows SDK headers use _MSC_VER values to figure out what
version of the VC++ headers they're using, in particular for SAL macros.

Patch by Paul Hampson!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191015 91177308-0d34-0410-b5e6-96231b3b80d8
GVN proceeds in the presence of dead code.

This is how it ignores the dead code:
1) When a dead branch target, say block B, is identified, all the
    blocks dominated by B is dead as well.

2) The PHIs of those blocks in dominance-frontier(B) is updated such
   that the operands corresponding to dead predecessors are replaced
   by "UndefVal".

   Using lattice's jargon, the "UndefVal" is the "Top" in essence.
   Phi node like this "phi(v1 bb1, undef xx)" will be optimized into
   "v1" if v1 is constant, or v1 is an instruction which dominate this
   PHI node.

3) When analyzing the availability of a load L, all dead mem-ops which
   L depends on disguise as a load which evaluate exactly same value as L.

4) The dead mem-ops will be materialized as "UndefVal" during code motion.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191017 91177308-0d34-0410-b5e6-96231b3b80d8
Fix a typo and simplify a boolean expression.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191018 91177308-0d34-0410-b5e6-96231b3b80d8
Remove unnecessary conditional operators performing bool->bool conversion.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191020 91177308-0d34-0410-b5e6-96231b3b80d8
X86 horizontal vector reduction cost model

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