OMAPDSS: DSSCOMP: efficiency improvement.

This change adds 3 local caches of objects, which are used at each flip buffer
action. In original variant kzalloc()/kfree() functions are called each time
dsscomp_gralloc_queue() function is called. This meens that slab|slob|slub
common cache is used at each frame draw action. Call to kzalloc()/kfree()
result in synchronization with other code, which uses common cache, and can
result in dips in FPS, when other code allocates/frees memory.
This change improves reliability, autonomy and efficiency of DSSCOMP module.

Change-Id: Id50778f4579309fb71318a32820b9d6441a6dac1
Signed-off-by: Mykhailo Denysiuk <x0172934@ti.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
OMAP4: PM: OPP/Clock: Add virtual clocks for high IVA OPPs support

To get correct frequencies for IVA OPP higher than OPP100
IVA DPLL should be reconfigured.
Tesla is also supplied from the same IVA DPLL, so frequency on DSP
should be reconfigured together with IVAHD frequency.

This is achieved by adding virtual clocks for IVA and DSP.
Main logic is implemented in IVA virtual clock which sets
frequency for both IVAHD and DSP.
DSP virtual clock is just a dummy clock and it do nothing.

Necessary DSP OPP is set via IVA virtual clock by using DVFS framework feature:
if device on which OPP is set is not the primary device in voltage domain,
then constraint to the same OPP is set for primary device.
In case of DSP the primary device is IVAHD.

If switching to the lower OPP will cause IVA DPLL scaling up,
then frequency of IVA and DSP should be scaled down before DPLL.

Change-Id: I1b229f1d52f0f8bfa4f65f08221df1e1ba6194bc
[jagadeeshwar.reddy@ti.com: original patch author for 4430]
Signed-off-by: Jagadeeshwar Reddy <jagadeeshwar.reddy@ti.com>
[taras@ti.com: modified and extended for all OMAP44xx]
Signed-off-by: Taras Kondratiuk <taras@ti.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>

Signed-off-by: Dan Trifan <jimsth@gmail.com>
OMAP: clock: Add dummy round_rate and set_rate functions

Add functions which are going to be used by dummy virtual clocks:
long clk_dummy_round_rate(struct clk *clk, unsigned long rate)
int clk_dummy_set_rate(struct clk *clk, unsigned long rate)

Change-Id: I9bb1e886888a117548d62ef2edd9598bce2723e6
Signed-off-by: Taras Kondratiuk <taras@ti.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
OMAP4: clock: Add 'virt_lcd_pclk' clock

Add virtual LCD pixel clock which is going to be used for DSS OPPs

Change-Id: Ia42668873d4dbe75deef22e97cec449a00f987d0
Signed-off-by: Vitaly Chernooky <vitaly.chernooky@ti.com>
Signed-off-by: Taras Kondratiuk <taras@ti.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
OMAP4: OPP: Add DSS OPPs

To generate pixel clock rate higher than 93MHz
DSS has to scale VDD_CORE to at least OPP100 level.

This patch adds two DSS OPPs, for DSS to be able
to control minimum VDD_CORE level.

Change-Id: I98eab1c3b56fcf41026b742cb43c8155b68dd5c4
Signed-off-by: Taras Kondratiuk <taras@ti.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>

Conflicts:
	arch/arm/mach-omap2/opp4xxx_data.c

Signed-off-by: Dan Trifan <jimsth@gmail.com>
OMAP4: PM: Handle LPDDR CLK IO errata during suspend/idle

There is a HW bug in CMD PHY which gives ISO signals as same for
both PADn and PADp on differential IO pad, because of which IO
leaks higher as pull controls are differential internally and
pull value does not match A value.
Though there is no functionality impact due to this bug, it is
seen that by disabling the pulls there is a savings ~500uA in
OSWR, but draws ~300uA more during OFF mode.

To save power during both idle/suspend following approach taken:
 1) Enable WA during boot-up.
 2) Disable WA while attempting suspend and enable during resume.

CDDS no: OMAP4460-1.0BUG00291
(OMAP official errata ID yet to be available).

Change-Id: Ic39f17be50ff602c71e714b05af3811b35c1a67f
Reported-by: Logan Lee <hklee@ti.com>
Signed-off-by: Shashi Shekar B.S. <shashi.shekar@ti.com>
Signed-off-by: Ambresh K <ambresh@ti.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
OMAPDSS: DSS: Scale DSS OPP according to pixel clock rate

Before enabling pixel clock DSS should set its OPP
for OPP framework to set correct VDD_CORE voltage level.

When pixel clock is disabled DSS can set the lowest OPP.

Change-Id: Ia1459614ae306dba9b048b149e474442e2880bba
Signed-off-by: Taras Kondratiuk <taras@ti.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>

Conflicts:
	drivers/video/omap2/dss/dsi.c

Signed-off-by: Dan Trifan <jimsth@gmail.com>
OMAP4460: TWL/TPS data: update retention voltages to spec rev 0.3

Update retention voltages from Operating Conditions Data Manual
Addendum Revision 0.3 (August 2011).

OFF voltage is also updated as per requirement of 4460 OFF mode
conditions.

Change-Id: I558f0a483911b2616d0a19f9272a03258e35904a
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>

Conflicts:
	arch/arm/mach-omap2/omap_twl.c

Signed-off-by: Dan Trifan <jimsth@gmail.com>
OMAPDSS: DISPC: Pipe threshold sizes power optimization.

This patch changes the calculation of thresholds and sets low
threshold to half of buffer size for OMAP4. The memory will
able to sleep between transactions to dss because dss will
read by big chunks.

boype: Also removed dispc_calculate_threshold function, as it is no longer used.

Backport from TI omapzoom kernel 3.4 repo, based upon:
http://git.omapzoom.org/?p=kernel/omap.git;a=commit;h=cd99eb345e1ad26ffbc665f46ea917dad762937b

Signed-off-by: Dan Trifan <jimsth@gmail.com>
OMAPDSS: drop small YUV encoded frames on OMAP44xx

OMAP44xx has hardware limitation: in stall mode, when the frame pixel size
is less than output SyncFifo depth(16), DISPC hangs without sending any data.
Simple workaround is to drop such frame, as cases when YUV frames of this size
are very rare.

Change-Id: I31dc262b07a52b66209c093f136ad2bac66f9439
Signed-off-by: Sergiy Kibrik <sergiy.kibrik@globallogic.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
OMAP4460: add Reverse Body-Bias support to ABB LDO

On 4460 all OPPs have pre-determined states for VDD_MPU's ABB LDO,
except for OPP_TURBO.  OPP_TURBO may require bypass, FBB or RBB
depending on a combination of characterisation data blown into eFuse
register CONTROL_STD_FUSE_OPP_DPLL_1.

Bits 18 & 19 of that register signify DPLL_MPU trim (see
arch/arm/mach-omap2/omap4-trim-quirks.c).  OPP_TURBO might put MPU's ABB
LDO into bypass or FBB based on this value.

Bit 20 siginifies if RBB should be enabled.  If set it will always
override the values from bits 18 & 19.

The table below captures the valid combinations:

Bit 18 | Bit 19 | Bit 20 | ABB type
0        0        0        bypass
0        1        0        bypass  (invalid combo)
1        0        0        FBB     (2.4GHz DPLL_MPU)
1        1        0        FBB     (3GHz DPLL_MPU)
0        0        1        RBB
0        1        1        RBB     (invalid combo)
1        0        1        RBB     (2.4GHz DPLL_MPU)
1        1        1        RBB     (3GHz DPLL_MPU)

This patch introduces ABB type detection into the ABB init code and
makes a few changes to the ABB programming code to allow for RBB (which
was previously unsupported).

This patch also changes OPP_TURBO's default abb_type to FAST_OPP (FBB)
by default.  This tiny optimization benefits production silicon by
removing one PRCM register write from the ABB initialization code for
the common case where the DPLL_MPU trim values are blown in and the
silicon is weak or nominal (uses FBB at OPP_TURBO).

Change-Id: I73973ddbb77dd89a7e2809bc56d935767f20a5d8
Signed-off-by: Mike Turquette <mturquette@ti.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>

Conflicts:
	arch/arm/mach-omap2/opp4xxx_data.c

Signed-off-by: Dan Trifan <jimsth@gmail.com>
OMAP4460: OPP: Move ABB update for MPU OPP turbo to OPP init code

Initially ABB type update was implemented in ABB init code.
This leads to a voltage values duplication.
This patch moves ABB type detection into the OPP init code.

Change-Id: I6140dff1be0f2b9e667160da957c8e1dbabf3e8f
[taras@ti.com: remove previous implementation]
Signed-off-by: Taras Kondratiuk <taras@ti.com>
[nm@ti.com: movement of code to central opp update]
Signed-off-by: Nishanth Menon <nm@ti.com>
[mturquette@ti.com: original author]
Signed-off-by: Mike Turquette <mturquette@ti.com>

Signed-off-by: Dan Trifan <jimsth@gmail.com>

Conflicts:
	arch/arm/mach-omap2/ldo.c
	arch/arm/mach-omap2/opp4xxx_data.c

Signed-off-by: Dan Trifan <jimsth@gmail.com>
panel-s6e8aa0: fix slightly inaccurate pixel clock

Signed-off-by: Dan Trifan <jimsth@gmail.com>
OMAPDSS: DISPC: fix pclk divisor limits

According to TRM, minimal pixel clock divisor value can be 1.
Fix corresponding checks, as high resolution panels use undivided
pixel clock frequency.

Also certain scaler unit constraint must be met: in case DISPC_CLK
and pixel clock frequencies are equal, set IPC to work on rising edge.

Change-Id: Iabeac2ad81f6909213cb81f4e16b1d0762369b53
Signed-off-by: Sergiy Kibrik <sergiy.kibrik@globallogic.com>
Signed-off-by: Lajos Molnar <lajos@ti.com>
Signed-off-by: Dima Svetlov <svetlov@ti.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
OMAPDSS: DISPC: more precise scale limits checking

Use division with rounding-up when checking if maximum downscale ratio
was reached. This allows to avoid SYNC_LOST errors in case when small
amount of extra pixels or lines (usually 1-3) not taken into account

Change-Id: Id8f88c64671146a64738cfd820378bb7a28c1455
Signed-off-by: Sergiy Kibrik <sergiy.kibrik@globallogic.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
Add assembler versions of AES and SHA1 for ARM platforms.  This has provided
up to a 50% improvement in IPsec/TCP throughout for tunnels using AES128/SHA1.

Signed-off-by: Dan Trifan <jimsth@gmail.com>
ARMv7: Flush the vectors page using the base address

ARMv7: Flush the vectors page using the base address

With the domains removal patch, the vectors page is populated using the
kernel linear mapping address. However, the flush_icache_range()
function must be called on the high vectors address because the I-cache
is allowed to have aliases (or can even be ASID-tagged VIVT). Note that
on ARMv7 processors the D-cache is non-aliasing.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: stable@vger.kernel.org
Signed-off-by: Dan Trifan <jimsth@gmail.com>
OMAP: EMIF: fix LP_MODE_PWR_DN value definition

OMAP: EMIF: fix LP_MODE_PWR_DN value definition

According to TRM the EMIF Power-down mode is identified
by value 0x4 (EMIF_PWR_MGMT_CTRL.REG_LP_MODE)

Change-Id: I4d9b9534dea27ab4619af5b6d78de8ab14f0fead
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
OMAP4: PM: fix overconsumption on OFF mode

The wrong value of CM_L3INIT_CLKSTCTRL.CLKTRCTRL = 2 (SW_WKUP)
has been stored in SAR during omap4_sar_save() execution and
causes power over consumption on OFF mode due to C2C operation.
It happens because the L3INIT CD need to be enabled during
omap4_sar_save() execution for proper USBHOST module context storing.

Problematic use case:
1) OMAP goes to sleep,
2) modem wakeup the C2C, the EMIF but the MPU is still sleeping
(as expected)
3) Modem release all his constraints, C2C is turned to OFF.
4) but OMAP never reach again OFF while we don't wakeup the CPU
(by a keypress for example), sys_clk is already ON and voltages
are not equal to 0. (OPP 50 for CORE_3 and retention voltages
for both VCORE1 and VCORE2).

As WA overwrite CM_L3INIT_CLKSTCTRL.CLKTRCTRL = 0x1 (SW_SLEEP).

Change-Id: I2e453c07f61bab28a7213dd66044fd41a021961b
Signed-off-by: Arthur Cassegrain <a-cassegrain@ti.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>

Patch Set 1

Signed-off-by: Dan Trifan <jimsth@gmail.com>
HSMMC:Set disable timeout to 1ms

The disable timeout is reduced from 100ms to 1ms in order
to obtain aggressive power saving.

Cherry picked from p-android-omap-2.6.35 commit ID:
50df9d10a9b33c82ad02003686050b12b03d4dfe

Change-Id: Ieaa47d51396e7b92f6c1ba71e62900c58a05a26c
Signed-off-by: Madhusudhan Chikkature <madhu.cr@ti.com>
Signed-off-by: Viswanath Puttagunta <vishp@ti.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>