disas: Disassemble all ppc insns for the host

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Use TCGReg everywhere

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Introduce and use tcg_out_rlw

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Introduce and use tcg_out_ext32u

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Introduce and use tcg_out_shli64

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Introduce and use tcg_out_shri64

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Cleanup tcg_out_movi

The test for using movi32 was sub-optimal for TCG_TYPE_I32, comparing
a signed 32-bit quantity against an unsigned 32-bit quantity.

When possible, use addi+oris for 32-bit unsigned constants.  Otherwise,
standardize on addi+oris+ori instead of addis+ori+rldicl.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Introduce and use TAI and SAI

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Rearrange integer constant constraints

We'll need a zero, and Z makes more sense for that.  Make sure we
have a full compliment of signed and unsigned 16 and 32-bit tests.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Improve constant add and sub ops.

Use SUBFIC to implement subtraction with constant op1.  Improve constant
addition -- previously we'd emit useless addis with 0.  Use new constraints
to force the driver to pull full 64-bit constants into a register.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Tidy or and xor patterns.

Handle constants in common code; we'll want to reuse that later.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Improve and_i32 with constant

Use RLWINM

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Improve and_i64 with constant

Use RLDICL and RLDICR.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Streamline qemu_ld/st insn selection

Using a table to look up insns of the right width and sign.
Include support for the Power 2.05 LDBRX and STDBRX insns
included in e.g. Power6.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Implement rotates

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Implement bswap16 and bswap32

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Implement bswap64

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Implement compound logicals

Mostly copied from the ppc32 port.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Implement deposit

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Use I constraint for mul

The mul_i32 pattern was loading non-16-bit constants into a register,
when we can get the middle-end to do that for us.  The mul_i64 pattern
was not considering that MULLI takes 64-bit inputs.

Signed-off-by: Richard Henderson <rth@twiddle.net>