Update gitignore for synthesis dir
pcie_fpga: Update PCIe core for Kintex7 to v1.9.
Change BAR sizes to match Artix and Virtex versions.
Update Kintex7 TOP and UCF file for wider PCIe link.
Backport some changes to TOP file for easier instantiation.
pcie_fpga: change prog_full threshold values for FIFOs.
This change is needed because we have to accomodate for long pipeline
stages in firmware. Otherwise we risk data corruption or lost packets.
pcie_fpga: Fix DDR write path signals.
In case of back to back transactions on m_axis interface, a situation
could occur when some signals weren't updated quick enough which
resulted in missing/corrupt date being written to onboard DDR memory.
Also, for DDRs_Control.vhd, introduce ADDR_WIDTH generic as a better way
of determining address width/position instead of relying
DDR_DQ/DDR_PAYLOAD constants.
pcie_fpga: Update ddr_transact to instantiate new generic for control module.
pcie_fpga: Fix access to DDR memory arbiter.
Old scheme could cause deadlock in some specific conditions.
pcie_fpga: Fix handling last word in a TLP when
throttling mechanism is active.
With old scheme last word could be lost, which caused havoc in DDR
writing state machine because whole FIFO data was shifted.
Symptoms were visible when DDR FIFO was getting full and incoming TLP
stream could have random stalls.
Also cleanup some dead code.
pcie_fpga: Fix TLP dispatching state machine when throttling mechanism
is active.
Also, cleanup some dead code.
pcie_fpga: Fix timeout signals for MRd requests.
Assert given *_timeout signal only when accessing relevant resource.
pcie_fpga: Increase timeout for wishbone requests.
More relaxed timeout handling is especially needed in situations when
Wishbone slave is forwarding requests to I2C, SPI etc., because of large
roundtrip latency.