FPGA: The second receive channel has been made fully independent.

Some registries require changes in HOST code.
FPGA: The second transmit channel was added.

Some registries require changes in HOST code.
FPGA: Control logic for dual channel SRAM FIFO was fixed.
ZPU: Memory map has been changed according dual channel implementation.
ZPU: Add support for the second UDP Tx stream to ZPU and to fw_common.h.
Host: Fixes for dual-channel support.
Host: Fix rx/tx_fe_corrections() to support multiple daughter boards on UmTRX.
Host: Fix tcxo-dac setting in dual-channel configuration.
Host: Fix indentation and add a comment to umtrx_impl.cpp.
Host: Indentation fix in umtrx_impl.cpp.
Host: Fix Tx DSP registers - they were accidentially swapped.
Host: Fix IQ muxer settings in dual-channel case.
Host: Create rx/tx codec paths in the property tree for both channels.
Host: Set correct register number for the Rx DSP/frontend muxer.
Host: Add a comment regarding IQ mux selection logic in umtrx_impl::update_rx_subdev_spec().
FPGA: Dual channel mode (TX) was fixed.
FPGA: Multiplexer for the RX and TX frontends was added.

This was done due to the fact that the host can be able to work in dual channel mode.
FPGA: Work of each DSP channel's is indicated by separate LED's

LED A - Indicates the transmit status of the first transmit channel (LMS1)
LED C - Indicates the receive status of the first receive channel (LMS1)
LED E - Indicates the transmit status of the second transmit channel (LMS2)
LED B - Indicates the receive status of the second receive channel (LMS2)