exynos: Enable mmc for snow

Snow has an internal eMMC and an external SD card. Enable these in the
device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
video: exynos_fb: Add the missing #else clause

This patch fixes a bug introduced while adding DT support
to Exynos FIMD driver:

	commit c23f3157d69bbb6c044256870f745f195b12431e
	Author: Ajay Kumar <ajaykumar.rs@samsung.com>
	Date:   Thu Feb 21 23:53:01 2013 +0000

	    video: exynos_fb: add DT support for FIMD driver

Even though this part of code was missing, things were working
fine on Exynos5250 because, samsung_get_base_fimd() used
to give the correct base address for Exynos5250 FIMD.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Acked-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
pxa: add support for palmtreo680 board

This patch adds support for the Palm Treo 680 smartphone.  A quick overview of
u-boot implementation on the treo 680...

The treo 680 has a Diskonchip G4 nand flash chip.  This device has a 2k region
that maps to the system bus at the reset vector in a NOR-like fashion so that it
can be used as the boot device.  The phone is shipped with this 2k region
configured as write-protected (can't be modified) and programmed with an initial
program loader (IPL).  At power-up, this IPL loads the contents of two flash
blocks to SDRAM and jumps to it.  The capacity of the two blocks is not large
enough to hold all of u-boot, so a u-boot SPL is used.  To conserve flash space,
these two blocks and the necessary number of subsequent blocks are programmed
with a concatenated spl + u-boot image.  That way, the IPL will also load a
portion of u-boot proper, and when the spl runs, it relocates the portion of
u-boot that the IPL has already loaded, and then resumes loading the remaining
part of u-boot before jumping to it.

The default_environment is used (CONFIG_ENV_IS_NOWHERE) because I didn't think
that having a writable environment was worth the cost of a flash block, although
adding it would be straightforward.  I abuse the CONFIG_EXTRA_ENV_SETTINGS
option to specify the usbtty for the console (CONFIG_SYS_CONSOLE_IS_IN_ENV).

Support for the LCD is included, but currently it is only useful for displaying
the u-boot splash screen.  But if u-boot is built without the usbtty console, it
does display the auto-boot progress nicely.

Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
pxa: palmtreo680 flash programming utility

This adds a userspace linux utility that writes the u-boot image to an mtd
partition on the docg4 nand flash.

A special utility is required to do this because u-boot is partially loaded by
an initial program loader (IPL) that is permanently programmed to the boot
region of the flash.  This IPL expects the image to be written in a unique
format. The characteristics of this format can be summarized as follows:
  - Flash blocks to be loaded must have a magic number in the oob bytes of the
    first page of the block.
  - Each page must be written redundantly in the subsequent page.
  - The integrated flash controller's "reliable mode" is used, requiring that
    alternate 2k regions (4 pages) are skipped when writing.
For these reasons, a u-boot image can not be written using nandwrite from
mtd-utils.

Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
pxa: turn icache off in cpu_init_crit()

The comment in the low-level initialization function cpu_init_crit() says that
the caches are being disabled, but (oddly) the icache is actually turned on.
This is probably not a good idea prior to relocating code, so this patch turns
it off.  Tested on the pxa270.

Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
pxa: use -mcpu=xscale compiler option

Pass '-mcpu=xscale' to the compiler instead of march and mtune.  This will cause
gcc to define the __XSCALE__ macro.

Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
pxa: fix memory coherency problem after relocation

On the xscale, the icache must be invalidated and the write buffers drained
after writing code over the data bus, even if the caches are disabled.  Tested
on the pxa270.

Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
EXYNOS5: I2C: Add FDT and non-FDT support for I2C

This patch updates the function board_i2c_init() to add support for both
FDT and non-FDT for I2C, and initialise the I2C channels.

Signed-off-by: Amar <amarendra.xt@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
exynos: Adjust the starting MIF voltage to 1.05v

Some Exynos5250 silicon may require 1.05v on the MIF to be stable, so to be
safe we can default to 1.05v instead of 1.00v. This can be set optimally later
in the boot process by the kernel.

The 0x6 value for 1.05v comes from the MAX77686 datasheet.

Signed-off-by: Bernie Thompson <bhthompson@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
EXYNOS5: FDT: Add compatible strings for Serial

Add required compatible information for s5p serial driver

Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
EXYNOS5: FDT: Add serial device node values

This patch adds the device node required for serial driver

Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
S5P: Serial: Add fdt support to driver

This patch adds FDT support to the serial s5p driver.
At present disabling the serial console (from the device tree) crashes
U-Boot. Add checks for this case, so that execution can continue without
a serial console.
It also enables the serial_s5p driver recognize the silent_console option.

Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Gabe Black <gabeblack@google.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
CONFIG: EXYNOS5: Enable silent console

This patch enables CONFIG_SILENT_CONSOLE for EXYNOS5.
This patch also removes the hardcoding of UART port from
exynos5250 config.

Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
gpio: s3c2440_gpio: Fix wrong writel arguments

Current code had writel arguments the wrong way around, fix it.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
gpio: s5p_gpio: Call s5p_gpio_set_value() instead of open-code

Call s5p_gpio_set_value() to avoid code duplication.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Add support for Wandboard Quad

Add support for the Quad version of Wandboard; fix compile warning resulting
from having 2G of memory.

Signed-off-by: Tapani Utriainen <tapani@technexion.com>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Stefano Babic <sbabic@denx.de>
spi: mxc_spi: Fix pre and post divider calculation

Fix two issues with the calculation of pre_div and post_div:

1. pre_div: While the calculation of pre_div looks correct, to set the
CONREG[15-12] bits pre_div needs to be decremented by 1:

The i.MX 6Dual/6Quad Applications Processor Reference Manual (IMX6DQRM
Rev. 0, 11/2012) states:

CONREG[15-12]: PRE_DIVIDER
0000 Divide by 1
0001 Divide by 2
0010 Divide by 3
...
1101 Divide by 14
1110 Divide by 15
1111 Divide by 16

I.e. if we want to divide by 2, we have to write 1 to CONREG[15-12].

2. In case the post divider becomes necessary, pre_div will be divided by
16. So set pre_div to 16, too. And not 15.

Both issues above are tested using the following examples:

clk_src = 60000000 (60MHz, default i.MX6 ECSPI clock)

a) max_hz == 23000000 (23MHz, max i.MX6 ECSPI read clock)

-> pre_div =  3 (divide by 3 => CONREG[15-12] == 2)
-> post_div = 0 (divide by 1 => CONREG[11- 8] == 0)
               => 60MHz / 3 = 20MHz SPI clock

b) max_hz == 2000000 (2MHz)

-> pre_div =  16 (divide by 16 => CONREG[15-12] == 15)
-> post_div = 1  (divide by  2 => CONREG[11- 8] == 1)
               => 60MHz / 32 = 1.875MHz SPI clock

c) max_hz == 1000000 (1MHz)

-> pre_div =  16 (divide by 16 => CONREG[15-12] == 15)
-> post_div = 2  (divide by  4 => CONREG[11- 8] == 2)
               => 60MHz / 64 = 937.5kHz SPI clock

d) max_hz == 500000 (500kHz)

-> pre_div =  16 (divide by 16 => CONREG[15-12] == 15)
-> post_div = 3  (divide by  8 => CONREG[11- 8] == 3)
               => 60MHz / 128 = 468.75kHz SPI clock

Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
spi: mxc_spi: Update pre and post divider algorithm

The spi clock divisor is of the form x * (2**y),  or  x  << y, where x is
1 to 16, and y is 0 to 15. Note the similarity with floating point numbers.
Convert the desired divisor to the smallest number which is >= desired divisor,
and can be represented in this form. The previous algorithm chose a divisor
which could be almost twice as large as needed.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
dwc_ahsata: Allow use with dcache enabled

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
imx6: fix GPR2 wrong definition

Signed-off-by: Pierre Aubert <p.aubert@staubli.com>
CC: Stefano Babic <sbabic@denx.de>
Acked-by: Dirk Behme <dirk.behme@gmail.com>