Squashed commit of the following:

commit 64fb45202f1aa539efd6804420d65513de4a3740
Author: mrg666 <drgungor@hotmail.com>
Date:   Tue Jul 16 11:07:56 2013 -0400

    workqueue: backport from Linux 3.6.11

    to get the following patches by Tejun Heo that improves the latency of cpu
    hotplug events.
    workqueue: simplify CPU hotplug code
    workqueue: remove CPU offline trustee
    workqueue: don't butcher idle workers on an offline CPU
    workqueue: reimplement CPU online rebinding to handle idle workers
    https://wiki.linaro.org/WorkingGroups/PowerManagement/Doc/Hotplug#Workqueue

    Thanks to johnnyslt for fixes in msm_watchdog.c and restart.c

    Conflicts:
    	arch/arm/mach-msm/msm_watchdog.c
    	arch/arm/mach-msm/restart.c

commit a959f8f5997247b358e5d5aa21dfd53e1bf244f4
Author: mrg666 <drgungor@hotmail.com>
Date:   Tue Jun 11 18:52:21 2013 -0400

    ARM: 7668/1: fix memset-related crashes caused by recent GCC (4.7.2) optimizations
    Recent GCC versions (e.g. GCC-4.7.2) perform optimizations based on
    assumptions about the implementation of memset and similar functions.
    The current ARM optimized memset code does not return the value of
    its first argument, as is usually expected from standard implementations.

    For instance in the following function:

    void debug_mutex_lock_common(struct mutex *lock, struct mutex_waiter *waiter)
    {
    	memset(waiter, MUTEX_DEBUG_INIT, sizeof(*waiter));
    	waiter->magic = waiter;
    	INIT_LIST_HEAD(&waiter->list);
    }

    compiled as:

    800554d0 <debug_mutex_lock_common>:
    800554d0:       e92d4008        push    {r3, lr}
    800554d4:       e1a00001        mov     r0, r1
    800554d8:       e3a02010        mov     r2, #16 ; 0x10
    800554dc:       e3a01011        mov     r1, #17 ; 0x11
    800554e0:       eb04426e        bl      80165ea0 <memset>
    800554e4:       e1a03000        mov     r3, r0
    800554e8:       e583000c        str     r0, [r3, #12]
    800554ec:       e5830000        str     r0, [r3]
    800554f0:       e5830004        str     r0, [r3, #4]
    800554f4:       e8bd8008        pop     {r3, pc}

    GCC assumes memset returns the value of pointer 'waiter' in register r0; causing
    register/memory corruptions.

    This patch fixes the return value of the assembly version of memset.
    It adds a 'mov' instruction and merges an additional load+store into
    existing load/store instructions.
    For ease of review, here is a breakdown of the patch into 4 simple steps:

    Step 1
    ======
    Perform the following substitutions:
    ip -> r8, then
    r0 -> ip,
    and insert 'mov ip, r0' as the first statement of the function.
    At this point, we have a memset() implementation returning the proper result,
    but corrupting r8 on some paths (the ones that were using ip).

    Step 2
    ======
    Make sure r8 is saved and restored when (! CALGN(1)+0) == 1:

    save r8:
    -       str     lr, [sp, #-4]!
    +       stmfd   sp!, {r8, lr}

    and restore r8 on both exit paths:
    -       ldmeqfd sp!, {pc}               @ Now <64 bytes to go.
    +       ldmeqfd sp!, {r8, pc}           @ Now <64 bytes to go.
    (...)
            tst     r2, #16
            stmneia ip!, {r1, r3, r8, lr}
    -       ldr     lr, [sp], #4
    +       ldmfd   sp!, {r8, lr}

    Step 3
    ======
    Make sure r8 is saved and restored when (! CALGN(1)+0) == 0:

    save r8:
    -       stmfd   sp!, {r4-r7, lr}
    +       stmfd   sp!, {r4-r8, lr}

    and restore r8 on both exit paths:
            bgt     3b
    -       ldmeqfd sp!, {r4-r7, pc}
    +       ldmeqfd sp!, {r4-r8, pc}
    (...)
            tst     r2, #16
            stmneia ip!, {r4-r7}
    -       ldmfd   sp!, {r4-r7, lr}
    +       ldmfd   sp!, {r4-r8, lr}

    Step 4
    ======
    Rewrite register list "r4-r7, r8" as "r4-r8".

    Signed-off-by: Ivan Djelic <ivan.djelic@parrot.com>
    Reviewed-by: Nicolas Pitre <nico@linaro.org>
    Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
    Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
    ___________________

    ARM: 7670/1: fix the memset fix
    Commit 455bd4c430b0 ("ARM: 7668/1: fix memset-related crashes caused by
    recent GCC (4.7.2) optimizations") attempted to fix a compliance issue
    with the memset return value.  However the memset itself became broken
    by that patch for misaligned pointers.

    This fixes the above by branching over the entry code from the
    misaligned fixup code to avoid reloading the original pointer.

    Also, because the function entry alignment is wrong in the Thumb mode
    compilation, that fixup code is moved to the end.

    While at it, the entry instructions are slightly reworked to help dual
    issue pipelines.

    Signed-off-by: Nicolas Pitre <nico@linaro.org>
    Tested-by: Alexander Holler <holler@ahsoftware.de>
    Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

commit e653ee638fab51bdf4616a58c6d1fb1997400e94
Author: mrg666 <drgungor@hotmail.com>
Date:   Tue Jun 11 09:07:44 2013 -0400

    ARM: 7660/1: tlb: add branch predictor maintenance operations
    The ARM architecture requires explicit branch predictor maintenance
    when updating an instruction stream for a given virtual address. In
    reality, this isn't so much of a burden because the branch predictor
    is flushed during the cache maintenance required to make the new
    instructions visible to the I-side of the processor.

    However, there are still some cases where explicit flushing is required,
    so add a local_bp_flush_all operation to deal with this.

    Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
    Signed-off-by: Will Deacon <will.deacon@arm.com>
    Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
    ____________

    ARM: tlbflush: remove ARMv3 support
    We no longer support any ARMv3 platforms, so remove the old tlbflushing
    code.

    Signed-off-by: Will Deacon <will.deacon@arm.com>
    _____________

    ARM: Remove support for ARMv3 ARM610 and ARM710 CPUs
    This patch removes support for ARMv3 CPUs, which haven't worked properly
    for quite some time (see the FIXME comment in arch/arm/mm/fault.c).  The
    only V3 parts left is the cache model for ARMv3, which is needed for some
    odd reason by ARM740T CPUs, and being able to build with -march=armv3,
    which is required for the RiscPC platform due to its bus structure.

    Acked-by: Will Deacon <will.deacon@arm.com>
    Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
    Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
    ________________

    ARM: Optimize multi-CPU tlb flushing a little more
    The compiler does not conditionalize the assembly instructions for
    the tlb operations, which leads to sub-optimal code being generated
    when building a kernel for multiple CPUs.

    We can tweak things fairly simply as the code fragment below shows:

        17f8:       e3120001        tst     r2, #1  ; 0x1
    ...
        1800:       0a000000        beq     1808 <handle_pte_fault+0x194>
        1804:       ee061f10        mcr     15, 0, r1, cr6, cr0, {0}
        1808:       e3120004        tst     r2, #4  ; 0x4
        180c:       0a000000        beq     1814 <handle_pte_fault+0x1a0>
        1810:       ee081f36        mcr     15, 0, r1, cr8, cr6, {1}
    becomes:
        17f0:       e3120001        tst     r2, #1  ; 0x1
        17f4:       1e063f10        mcrne   15, 0, r3, cr6, cr0, {0}
        17f8:       e3120004        tst     r2, #4  ; 0x4
        17fc:       1e083f36        mcrne   15, 0, r3, cr8, cr6, {1}

    Overall, for Realview with V6 and V7 CPUs configured:

       text    data     bss     dec     hex filename
    4153998  207340 5371036 9732374  948116 ../build/realview/vmlinux.before
    4153366  207332 5371036 9731734  947e96 ../build/realview/vmlinux.after

    Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
    _____________

    ARM: 7076/1: LPAE: Add (pte|pmd)val_t type definitions as u32
    This patch defines the (pte|pmd)val_t as u32 and changes the page table
    types to be based on these. The PMD bits are converted to the
    corresponding type using the _AT macro.

    The flush_pmd_entry/clean_pmd_entry argument was changed to (void *) to
    allow them to be used with both PGD and PMD pointers and avoid code
    duplication.

    Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
    Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
    ______________

    ARM: btc: avoid invalidating the branch target cache on kernel TLB maintanence
    Kernel space needs very little in the way of BTC maintanence as most
    mappings which are created and destroyed are non-executable, and so
    could never enter the instruction stream.

    The case which does warrant BTC maintanence is when a module is loaded.
    This creates a new executable mapping, but at that point the pages have
    not been initialized with code and data, so at that point they contain
    unpredictable information.  Invalidating the BTC at this stage serves
    little useful purpose.

    Before we execute module code, we call flush_icache_range(), which deals
    with the BTC maintanence requirements.  This ensures that we have a BTC
    maintanence operation before we execute code via the newly created
    mapping.

    Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
    ____________

    backported from Linux 3.10-rc5 by mrg666

    Conflicts:
    	arch/arm/include/asm/mach/map.h
    	arch/arm/include/asm/tlbflush.h

commit 0ec467ed427961c39b1dfa20dc139708bd36e1f8
Author: mrg666 <drgungor@hotmail.com>
Date:   Thu Mar 21 15:13:30 2013 -0400

    clean up dead ARM code - part of it was missing already
    _________
    ARM: mm: Remove SW emulation for ARM domain manager

    8x50 is no longer supported in the msm-3.4 kernel, so remove this
    feature.

    Change-Id: I2156ef22cca82d3cce6a7d39e366b93cab32f811
    Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

    Conflicts:
    	arch/arm/mm/fault.c

commit 35f22acb4d4a4f7114690b763d213e6ec6713913
Author: mrg666 <drgungor@hotmail.com>
Date:   Thu Mar 21 14:56:47 2013 -0400

    ARM: Fix deadlock scenario with smp_send_stop()

    If one process calls sys_reboot and that process then stops other
    CPUs while those CPUs are within a spin_lock() region we can
    potentially encounter a deadlock scenario like below.

    CPU 0                   CPU 1
    -----                   -----
                            spin_lock(my_lock)
    smp_send_stop()
     send_IPI               handle_IPI()
                             disable_preemption/irqs
                              while(1);
     <PREEMPT>
    spin_lock(my_lock) <--- Waits forever

    We shouldn't attempt to run any other tasks after we send a stop
    IPI to a CPU so disable preemption so that this task runs to
    completion.

    Change-Id: I528af0b4448433bd9d6ca12d6a0e2c422a55d4be
    CRs-Fixed: 396169
    Reported-by: Sundarajan Srinivasan <sundaraj@codeaurora.com>
    Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

commit ca2f6694e71166b89e3d26ddbbe06b7bd67ca0df
Author: mrg666 <drgungor@hotmail.com>
Date:   Thu Mar 21 14:53:54 2013 -0400

    ARM: Fix negative idle stats for offline cpu

    We see negative idle stats because of cpu dying without
    cleaning up idle entry statistics. When a cpu is offline,
    the most immediate thing you'd want to do is just call
    into cpu_die() and not waste time calling notifier(IDLE_START).

    CRs-Fixed: 414554
    Change-Id: Iadc6a3ca39997e0ccf65d2a29b004e24b1b211a1
    Signed-off-by: Srivatsa Vaddagiri <vatsa@codeaurora.org>
    Signed-off-by: Taniya Das <tdas@codeaurora.org>

commit c1cbb0e92e504cfc443f70c4e3dedf9179935538
Author: mrg666 <drgungor@hotmail.com>
Date:   Fri May 3 15:49:54 2013 -0400

    mmc: core: Fix NULL pointer dereference

    mmc_signal_sdio_irq() should only be called when the function
    driver registers for IRQ notification. In case, if any host
    driver recieves a spurious interrupt and call mmc_signal_sdio_irq(),
    ignore waking up uninitialized sdio irq thread.

    CRs-Fixed: 472609
    Change-Id: I831717fe80918538a18cc1f2300fe7fe2817c70f
    Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
    Signed-off-by: Krishna Konda <kkonda@codeaurora.org>

commit fa1f93db66f19a36b0e9ae0b948689c7126e1461
Author: Nicolas Pitre <nicolas.pitre@linaro.org>
Date:   Thu Nov 8 19:54:11 2012 +0100

    ARM: 7574/1: kernel/process.c: include idmap.h instead of redeclaring setup_mm_for_reboot()

    Signed-off-by: Nicolas Pitre <nico@linaro.org>
    Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

commit 6d243106ddbe06f532463549238ecf022b10c4e8
Author: Russell King <rmk+kernel@arm.linux.org.uk>
Date:   Tue Nov 1 10:15:27 2011 +0000

    ARM: restart: remove argument to setup_mm_for_reboot()

    setup_mm_for_reboot() doesn't make use of its argument, so remove it.

    Acked-by: Nicolas Pitre <nico@linaro.org>
    Acked-by: Will Deacon <will.deacon@arm.com>
    Acked-by: H Hartley Sweeten <hsweeten@visionengravers.com>
    Acked-by: Tony Lindgren <tony@atomide.com>
    Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

commit 1d11cb29ec565b99d0e77a4581363f50eb549dea
Author: Jamie Iles <jamie@jamieiles.com>
Date:   Sat Oct 8 11:20:42 2011 +0100

    ARM: 7115/4: move __exception and friends to asm/exception.h

    The definition of __exception_irq_entry for
    CONFIG_FUNCTION_GRAPH_TRACER=y needs linux/ftrace.h, but this creates a
    circular dependency with it's current home in asm/system.h. Create
    asm/exception.h and update all current users.

    v4:	- rebase to rmk/for-next
    v3:	- remove redundant includes of linux/ftrace.h
    v2:	- document the usage restricitions of __exception*

    Cc: Zoltan Devai <zdevai@gmail.com>
    Signed-off-by: Jamie Iles <jamie@jamieiles.com>
    Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

    Conflicts:
    	arch/arm/include/asm/system.h
    	arch/arm/kernel/smp.c

    Conflicts:
    	arch/arm/include/asm/system.h

commit a25b2e864ba613153a53bdf13468fde6d37274e2
Author: Will Deacon <will.deacon@arm.com>
Date:   Wed Nov 23 12:26:25 2011 +0000

    ARM: SMP: use idmap_pgd for mapping MMU enable during secondary booting

    The ARM SMP booting code allocates a temporary set of page tables
    containing an identity mapping of the kernel image and provides this
    to secondary CPUs for initial booting.

    In reality, we only need to include the __turn_mmu_on function in the
    identity mapping since the rest of the kernel is executing from virtual
    addresses after this point.

    This patch adds __turn_mmu_on to the .idmap.text section, allowing the
    SMP booting code to use the idmap_pgd directly and not have to populate
    its own set of page table.

    As a result of this patch, we can make the identity_mapping_add function
    static (since it is only used within mm/idmap.c) and also remove the
    identity_mapping_del function. The identity map population is moved to
    an early initcall so that it is setup in time for secondary CPU bringup.

    Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
    Signed-off-by: Will Deacon <will.deacon@arm.com>

    Conflicts:
    	arch/arm/kernel/smp.c

    Conflicts:
    	arch/arm/kernel/smp.c

commit 6514fdae0d8a8a1f0d33534d871520de20ebdc63
Author: Will Deacon <will.deacon@arm.com>
Date:   Fri Sep 30 11:43:29 2011 +0100

    ARM: idmap: populate identity map pgd at init time using .init.text

    When disabling and re-enabling the MMU, it is necessary to take out an
    identity mapping for the code that manipulates the SCTLR in order to
    avoid it disappearing from under our feet. This is useful when soft
    rebooting and returning from CPU suspend.

    This patch allocates a set of page tables during boot and populates them
    with an identity mapping for the .idmap.text section. This means that
    users of the identity map do not need to manage their own pgd and can
    instead annotate their functions with __idmap or, in the case of assembly
    code, place them in the correct section.

    Acked-by: Dave Martin <dave.martin@linaro.org>
    Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
    Tested-by: Lorenzo Pieralisi <Lorenzo.Pieralisi@arm.com>
    Signed-off-by: Will Deacon <will.deacon@arm.com>

    Conflicts:
    	arch/arm/kernel/smp.c

    Conflicts:
    	arch/arm/kernel/smp.c

commit d9511029c22012882475181531e55bf589c8a4f9
Author: Will Deacon <will.deacon@arm.com>
Date:   Tue Nov 22 17:30:28 2011 +0000

    ARM: LPAE: add ISBs around MMU enabling code

    Before we enable the MMU, we must ensure that the TTBR registers contain
    sane values. After the MMU has been enabled, we jump to the *virtual*
    address of the following function, so we also need to ensure that the
    SCTLR write has taken effect.

    This patch adds ISB instructions around the SCTLR write to ensure the
    visibility of the above.

    Signed-off-by: Will Deacon <will.deacon@arm.com>
    Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

commit b9709cfbd6d1b937bfe97af15ffb606310adf15f
Author: Will Deacon <will.deacon@arm.com>
Date:   Tue Nov 15 11:11:19 2011 +0000

    ARM: suspend: use idmap_pgd instead of suspend_pgd

    The ARM CPU suspend code requires cpu_resume_mmu to be identity mapped
    in order to re-enable the MMU when coming out of suspend. Currently,
    this is accomplished by maintaining a suspend_pgd with the relevant
    mapping put in place at init time.

    This patch replaces the use of suspend_pgd with the new idmap_pgd.
    cpu_resume_mmu is placed in the .idmap.text section so that it is
    included in the identity map.

    Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
    Acked-by: Dave Martin <dave.martin@linaro.org>
    Tested-by: Lorenzo Pieralisi <Lorenzo.Pieralisi@arm.com>
    Signed-off-by: Will Deacon <will.deacon@arm.com>

commit a25b37539955cacddb055d9df0832c45b8604dbd
Author: Russell King <rmk+kernel@arm.linux.org.uk>
Date:   Thu Sep 1 11:52:33 2011 +0100

    ARM: pm: convert some assembly to C

    Convert some of the sleep.S guts to C code, which makes it easier to
    use our macros and to add L2 cache handling.  We provide a helper
    function, __cpu_suspend_save(), which deals with saving the common
    state, setting up for resume, and flushing caches.

    The remainder left as assembly code is the saving of the CPU general
    purpose registers, and allocating space on the stack to save the CPU
    specific registers and resume state.

    Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
    Tested-by: Shawn Guo <shawn.guo@linaro.org>
    Tested-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
    Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

    Conflicts:
    	arch/arm/include/asm/proc-fns.h

commit 8156a6562b2de9057d4f1984ec4f660bf4746dd9
Author: Russell King <rmk+kernel@arm.linux.org.uk>
Date:   Wed Aug 31 23:26:18 2011 +0100

    ARM: pm: get rid of cpu_resume_turn_mmu_on

    We don't require cpu_resume_turn_mmu_on as we can combine the ldr
    instruction with the following code provided we ensure that
    cpu_resume_mmu is aligned for older CPUs.  Note that we also align
    to a 32-byte boundary to ensure that the code can't cross a section
    boundary.

    Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
    Tested-by: Shawn Guo <shawn.guo@linaro.org>
    Tested-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
    Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

commit 8a4bc7df7482d5b54d00ded020d8587950444e2c
Author: Nicolas Pitre <nicolas.pitre@linaro.org>
Date:   Mon Oct 24 13:30:32 2011 +0100

    ARM: 7139/1: fix compilation with CONFIG_ARM_ATAG_DTB_COMPAT and large TEXT_OFFSET

    If TEXT_OFFSET is too large (e.g. like on MSM) the resulting immediate
    argument gets wider than 8 bits.

    Noticed by David Brown <davidb@codeaurora.org>

    Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
    Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

    Conflicts:
    	arch/arm/boot/compressed/head.S

commit 1f6fe4c6c295a7299a536d1ced82ebf8bd6d95b1
Author: mrg666 <drgungor@hotmail.com>
Date:   Sun Mar 3 16:02:04 2013 -0500

    revert ARM: mm: update __v7_setup() to the new LoUIS cache maintenance API

commit c2e7aa83773e3afb42a9cbca2a977f6f7aa34acd
Author: Dave Martin <dave.martin@linaro.org>
Date:   Tue Oct 16 11:54:00 2012 +0100

    ARM: 7553/1: proc-v7: Ensure correct instruction set after cpu_reset

    Because mov pc,<Rn> never switches instruction set when executed in
    Thumb code, Thumb-2 kernels will silently execute the target code
    after cpu_reset as Thumb code, even if the passed code pointer
    denotes ARM (bit 0 clear).

    This patch uses bx instead, ensuring the correct instruction set
    for the target code.

    Thumb code in the kernel is not supported prior to ARMv7, so other
    CPUs are not affected.

    Signed-off-by: Dave Martin <dave.martin@linaro.org>
    Acked-by: Will Deacon <will.deacon@arm.com>
    Acked-by: Nicolas Pitre <nico@linaro.org>
    Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

    Conflicts:
    	arch/arm/mm/proc-v7.S

commit ac339e64965d7af4d9bf99d08373f69a35d41f82
Author: Santosh Shilimkar <santosh.shilimkar@ti.com>
Date:   Mon Sep 10 15:07:26 2012 +0530

    ARM: mm: update __v7_setup() to the new LoUIS cache maintenance API

    The ARMv7 processor setup function __v7_setup() cleans and invalidates the
    CPU cache before enabling MMU to start the CPU with a clean CPU local cache.

    But on ARMv7 architectures like Cortex-[A15/A8], this code will end
    up flushing the L2 caches(up to level of Coherency) which is undesirable
    and expensive. The setup functions are used in the CPU hotplug scenario too
    and hence flushing all cache levels should be avoided.

    This patch replaces the cache flushing call with the newly introduced
    v7 dcache LoUIS API where only cache levels up to LoUIS are cleaned and
    invalidated when a processors executes __v7_setup which is the expected
    behavior.

    For processors like A9 and A5 where the L2 cache is an outer one the
    behavior should be unchanged.

    Reviewed-by: Nicolas Pitre <nico@linaro.org>
    Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
    Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
    Tested-by: Shawn Guo <shawn.guo@linaro.org>

commit aa384ce63075663572fec75adeefea17b9628e73
Author: Dave Martin <dave.martin@linaro.org>
Date:   Thu Dec 8 13:41:06 2011 +0100

    ARM: 7197/1: errata: Remove SMP dependency for erratum 751472

    Activation conditions for a workaround should not be encoded in the
    workaround's direct dependencies if this makes otherwise reasonable
    configuration choices impossible.

    This patches uses the SMP/UP patching facilities instead to compile
    out the workaround if the configuration means that it is definitely
    not needed.

    This means that configs for buggy silicon can simply select
    ARM_ERRATA_751472, without preventing a UP kernel from being built
    or duplicatiing knowledge about when to activate the workaround.
    This seems the correct way to do things, because the erratum is a
    property of the silicon, irrespective of what the kernel config
    happens to be.

    Signed-off-by: Dave Martin <dave.martin@linaro.org>
    Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

commit e788e2bc1e9433265acb5722ad047a93983fbbe1
Author: Will Deacon <will.deacon@arm.com>
Date:   Tue Nov 15 13:25:04 2011 +0000

    ARM: proc-*.S: place cpu_reset functions into .idmap.text section

    The CPU reset functions disable the MMU and therefore must be executed
    with an identity mapping in place.

    This patch places the CPU reset functions into the .idmap.text section,
    causing the idmap code to include them as part of the identity mapping.

    Acked-by: Dave Martin <dave.martin@linaro.org>
    Signed-off-by: Will Deacon <will.deacon@arm.com>

commit 403a13a571767f33cd38a22568808026e6037526
Author: Russell King <rmk+kernel@arm.linux.org.uk>
Date:   Sun Aug 28 10:30:34 2011 +0100

    ARM: pm: no need to save/restore context ID register

    There is no need to save and restore the context ID register on ARMv6
    and ARMv7 with a temporary page table as we write the context ID
    register when we switch back to the real page tables for the thread.

    Moreover, the temporary page tables do not contain any non-global
    mappings, so the context ID value should not be used.  To be safe,
    initialize the register to a reserved context ID value.

    Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
    Tested-by: Shawn Guo <shawn.guo@linaro.org>
    Tested-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
    Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

commit 7c0060da8d5ec502c9ab3123f6fcd010a78dcbbd
Author: Russell King <rmk+kernel@arm.linux.org.uk>
Date:   Sat Aug 27 22:39:09 2011 +0100

    ARM: pm: only use preallocated page table during resume

    Only use the preallocated page table during the resume, not while
    suspending.  This avoids the overhead of having to switch unnecessarily
    to the resume page table in the suspend path.

    Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
    Tested-by: Shawn Guo <shawn.guo@linaro.org>
    Tested-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
    Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

    Conflicts:
    	arch/arm/mm/proc-sa1100.S
    	arch/arm/mm/proc-xsc3.S

commit 1331e9cd75d08e9e422a98c784dbecaf4306e771
Author: Russell King <rmk+kernel@arm.linux.org.uk>
Date:   Fri Aug 26 20:28:52 2011 +0100

    ARM: pm: preallocate a page table for suspend/resume

    Preallocate a page table and setup an identity mapping for the MMU
    enable code.  This means we don't have to "borrow" a page table to
    do this, avoiding complexities with L2 cache coherency.

    Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
    Tested-by: Shawn Guo <shawn.guo@linaro.org>
    Tested-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
    Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

    Conflicts:
    	arch/arm/include/asm/suspend.h
    	arch/arm/kernel/sleep.S
    	arch/arm/mm/proc-v6.S
    	arch/arm/mm/proc-v7.S
    adapted to HTC kernel by mrg666

commit 51efeabcf5ad430b3d3fbea78b305d89394a7fbe
Author: mrg666 <drgungor@hotmail.com>
Date:   Sun Mar 3 15:00:05 2013 -0500

    ARM: 7066/1: proc-v7: disable SCTLR.TE when disabling MMU
    cpu_v7_reset disables the MMU and then branches to the provided address.
    On Thumb-2 kernels, we should take care to clear the Thumb Exception
    enable bit in the System Control Register, otherwise this may wreak
    havok in the code to which we are branching (for example, an ARM kernel
    image via kexec).

    Reviewed-by: Dave Martin <dave.martin@linaro.org>
    Signed-off-by: Will Deacon <will.deacon@arm.com>
    Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
    ++++++++++++

    ARM: pm: some ARMv7 requires a dsb in resume to ensure correctness
    Add a dsb after the isb to ensure that the previous writes to the
    CP15 registers take effect before we enable the MMU.

    Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

    ++++++++++++

    ARM: pm: avoid writing the auxillary control register for ARMv7
    For ARMv7 kernels running in the non-secure world, writing to the
    auxillary control register causes an abort, so we must avoid directly
    writing the auxillary control register.  If the ACR has already been
    reinitialized by SoC code, don't try to restore it.

    Conflicts:
    	arch/arm/mm/proc-v7.S

commit cd389f6a0779933da50cced88f01e33c53a805fa
Author: viresh kumar <viresh.kumar@linaro.org>
Date:   Wed Oct 31 10:40:42 2012 +0100

    ARM: 7569/1: mm: uninitialized warning corrections

    The variables here are really not used uninitialized.

    arch/arm/mm/alignment.c: In function 'do_alignment':
    arch/arm/mm/alignment.c:327:15: warning: 'offset.un' may be used uninitialized in this function [-Wmaybe-uninitialized]
    arch/arm/mm/alignment.c:748:21: note: 'offset.un' was declared here

    Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
    Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

commit 904e8afb97fae38fae3b04e50f1db4eae5c75caf
Author: Nicolas Pitre <nicolas.pitre@linaro.org>
Date:   Mon Dec 3 21:13:03 2012 +0100

    ARM: 7590/1: /proc/interrupts: limit the display of IPIs to online CPUs only

    This is what is done for the regular interrupts in kernel/irqs/proc.c
    already, before calling arch_show_interrupts().  Not doing so for the
    IPIs causes the column headers not to match with the content whenever
    some CPUs are offline.

    Signed-off-by: Nicolas Pitre <nico@linaro.org>
    Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

commit 4409e7fdc0f8a21c7b95db0125dbce923efe6d3a
Author: Will Deacon <will.deacon@arm.com>
Date:   Tue Dec 4 12:56:44 2012 +0100

    ARM: 7592/1: nommu: prevent generation of kernel unaligned memory accesses

    Recent ARMv7 toolchains assume that unaligned memory accesses will not
    fault and will instead be handled by the processor.

    For the nommu case (without an MPU), memory will be treated as
    strongly-ordered and therefore unaligned accesses may fault regardless
    of the SCTLR.A setting.

    This patch passes -mno-unaligned-access to GCC when compiling for nommu
    targets, preventing the generation of unaligned memory access in the
    kernel.

    Acked-by: Nicolas Pitre <nico@linaro.org>
    Tested-by: Jonathan Austin <jonathan.austin@arm.com>
    Signed-off-by: Will Deacon <will.deacon@arm.com>
    Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

commit 47e38a78a2a6ca154b282a5cded306a4f2a6514d
Author: mrg666 <drgungor@hotmail.com>
Date:   Sat Mar 2 15:19:46 2013 -0500

    ARM: 7641/1: memory: fix broken mmap by ensuring TASK_UNMAPPED_BASE is aligned
    We have received multiple reports of mmap failures when running with a
    2:2 vm split. These manifest as either -EINVAL with a non page-aligned
    address (ending 0xaaa) or a SEGV, depending on the application. The
    issue is commonly observed in children of make, which appears to use
    bottom-up mmap (assumedly because it changes the stack rlimit).

    Further investigation reveals that this regression was triggered by
    394ef6403abc ("mm: use vm_unmapped_area() on arm architecture"), whereby
    TASK_UNMAPPED_BASE is no longer page-aligned for bottom-up mmap, causing
    get_unmapped_area to choke on misaligned addressed.

    This patch fixes the problem by defining TASK_UNMAPPED_BASE in terms of
    TASK_SIZE and explicitly aligns the result to 16M, matching the other
    end of the heap.

    Acked-by: Nicolas Pitre <nico@linaro.org>
    Reported-by: Steve Capper <steve.capper@arm.com>
    Reported-by: Jean-Francois Moine <moinejf@free.fr>
    Reported-by: Christoffer Dall <cdall@cs.columbia.edu>
    Signed-off-by: Will Deacon <will.deacon@arm.com>
    Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

commit a736d6f86308614e1d55d603e6a748902e8e53bd
Author: mrg666 <drgungor@hotmail.com>
Date:   Sat Mar 2 13:36:55 2013 -0500

    ARM: 7494/1: use generic termios.h
    As pointed out by Arnd Bergmann, this fixes a couple of issues but will
    increase code size:

    The original macro user_termio_to_kernel_termios was not endian safe. It
    used an unsigned short ptr to access the low bits in a 32-bit word.

    Both user_termio_to_kernel_termios and kernel_termios_to_user_termio are
    missing error checking on put_user/get_user and copy_to/from_user.

    Signed-off-by: Rob Herring <rob.herring@calxeda.com>
    Reviewed-by: Nicolas Pitre <nico@linaro.org>
    Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
    Reviewed-by: Arnd Bergmann <arnd@arndb.de>
    Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

commit d7875e1aef927ef73185e575e6e104a2d7c634cf
Author: mrg666 <drgungor@hotmail.com>
Date:   Sat Mar 2 01:18:20 2013 -0500

    ARM: 7493/1: use generic unaligned.h
    This moves ARM over to the asm-generic/unaligned.h header. This has the
    benefit of better code generated especially for ARMv7 on gcc 4.7+
    compilers.

    As Arnd Bergmann, points out: The asm-generic version uses the "struct"
    version for native-endian unaligned access and the "byteshift" version
    for the opposite endianess. The current ARM version however uses the
    "byteshift" implementation for both.

    Thanks to Nicolas Pitre for the excellent analysis:

    Test case:

    int foo (int *x) { return get_unaligned(x); }
    long long bar (long long *x) { return get_unaligned(x); }

    With the current ARM version:

    foo:
    	ldrb	r3, [r0, #2]	@ zero_extendqisi2	@ MEM[(const u8 *)x_1(D) + 2B], MEM[(const u8 *)x_1(D) + 2B]
    	ldrb	r1, [r0, #1]	@ zero_extendqisi2	@ MEM[(const u8 *)x_1(D) + 1B], MEM[(const u8 *)x_1(D) + 1B]
    	ldrb	r2, [r0, #0]	@ zero_extendqisi2	@ MEM[(const u8 *)x_1(D)], MEM[(const u8 *)x_1(D)]
    	mov	r3, r3, asl #16	@ tmp154, MEM[(const u8 *)x_1(D) + 2B],
    	ldrb	r0, [r0, #3]	@ zero_extendqisi2	@ MEM[(const u8 *)x_1(D) + 3B], MEM[(const u8 *)x_1(D) + 3B]
    	orr	r3, r3, r1, asl #8	@, tmp155, tmp154, MEM[(const u8 *)x_1(D) + 1B],
    	orr	r3, r3, r2	@ tmp157, tmp155, MEM[(const u8 *)x_1(D)]
    	orr	r0, r3, r0, asl #24	@,, tmp157, MEM[(const u8 *)x_1(D) + 3B],
    	bx	lr	@

    bar:
    	stmfd	sp!, {r4, r5, r6, r7}	@,
    	mov	r2, #0	@ tmp184,
    	ldrb	r5, [r0, #6]	@ zero_extendqisi2	@ MEM[(const u8 *)x_1(D) + 6B], MEM[(const u8 *)x_1(D) + 6B]
    	ldrb	r4, [r0, #5]	@ zero_extendqisi2	@ MEM[(const u8 *)x_1(D) + 5B], MEM[(const u8 *)x_1(D) + 5B]
    	ldrb	ip, [r0, #2]	@ zero_extendqisi2	@ MEM[(const u8 *)x_1(D) + 2B], MEM[(const u8 *)x_1(D) + 2B]
    	ldrb	r1, [r0, #4]	@ zero_extendqisi2	@ MEM[(const u8 *)x_1(D) + 4B], MEM[(const u8 *)x_1(D) + 4B]
    	mov	r5, r5, asl #16	@ tmp175, MEM[(const u8 *)x_1(D) + 6B],
    	ldrb	r7, [r0, #1]	@ zero_extendqisi2	@ MEM[(const u8 *)x_1(D) + 1B], MEM[(const u8 *)x_1(D) + 1B]
    	orr	r5, r5, r4, asl #8	@, tmp176, tmp175, MEM[(const u8 *)x_1(D) + 5B],
    	ldrb	r6, [r0, #7]	@ zero_extendqisi2	@ MEM[(const u8 *)x_1(D) + 7B], MEM[(const u8 *)x_1(D) + 7B]
    	orr	r5, r5, r1	@ tmp178, tmp176, MEM[(const u8 *)x_1(D) + 4B]
    	ldrb	r4, [r0, #0]	@ zero_extendqisi2	@ MEM[(const u8 *)x_1(D)], MEM[(const u8 *)x_1(D)]
    	mov	ip, ip, asl #16	@ tmp188, MEM[(const u8 *)x_1(D) + 2B],
    	ldrb	r1, [r0, #3]	@ zero_extendqisi2	@ MEM[(const u8 *)x_1(D) + 3B], MEM[(const u8 *)x_1(D) + 3B]
    	orr	ip, ip, r7, asl #8	@, tmp189, tmp188, MEM[(const u8 *)x_1(D) + 1B],
    	orr	r3, r5, r6, asl #24	@,, tmp178, MEM[(const u8 *)x_1(D) + 7B],
    	orr	ip, ip, r4	@ tmp191, tmp189, MEM[(const u8 *)x_1(D)]
    	orr	ip, ip, r1, asl #24	@, tmp194, tmp191, MEM[(const u8 *)x_1(D) + 3B],
    	mov	r1, r3	@,
    	orr	r0, r2, ip	@ tmp171, tmp184, tmp194
    	ldmfd	sp!, {r4, r5, r6, r7}
    	bx	lr

    In both cases the code is slightly suboptimal.  One may wonder why
    wasting r2 with the constant 0 in the second case for example.  And all
    the mov's could be folded in subsequent orr's, etc.

    Now with the asm-generic version:

    foo:
    	ldr	r0, [r0, #0]	@ unaligned	@,* x
    	bx	lr	@

    bar:
    	mov	r3, r0	@ x, x
    	ldr	r0, [r0, #0]	@ unaligned	@,* x
    	ldr	r1, [r3, #4]	@ unaligned	@,
    	bx	lr	@

    This is way better of course, but only because this was compiled for
    ARMv7. In this case the compiler knows that the hardware can do
    unaligned word access.  This isn't that obvious for foo(), but if we
    remove the get_unaligned() from bar as follows:

    long long bar (long long *x) {return *x; }

    then the resulting code is:

    bar:
    	ldmia	r0, {r0, r1}	@ x,,
    	bx	lr	@

    So this proves that the presumed aligned vs unaligned cases does have
    influence on the instructions the compiler may use and that the above
    unaligned code results are not just an accident.

    Still... this isn't fully conclusive without at least looking at the
    resulting assembly fron a pre ARMv6 compilation.  Let's see with an
    ARMv5 target:

    foo:
    	ldrb	r3, [r0, #0]	@ zero_extendqisi2	@ tmp139,* x
    	ldrb	r1, [r0, #1]	@ zero_extendqisi2	@ tmp140,
    	ldrb	r2, [r0, #2]	@ zero_extendqisi2	@ tmp143,
    	ldrb	r0, [r0, #3]	@ zero_extendqisi2	@ tmp146,
    	orr	r3, r3, r1, asl #8	@, tmp142, tmp139, tmp140,
    	orr	r3, r3, r2, asl #16	@, tmp145, tmp142, tmp143,
    	orr	r0, r3, r0, asl #24	@,, tmp145, tmp146,
    	bx	lr	@

    bar:
    	stmfd	sp!, {r4, r5, r6, r7}	@,
    	ldrb	r2, [r0, #0]	@ zero_extendqisi2	@ tmp139,* x
    	ldrb	r7, [r0, #1]	@ zero_extendqisi2	@ tmp140,
    	ldrb	r3, [r0, #4]	@ zero_extendqisi2	@ tmp149,
    	ldrb	r6, [r0, #5]	@ zero_extendqisi2	@ tmp150,
    	ldrb	r5, [r0, #2]	@ zero_extendqisi2	@ tmp143,
    	ldrb	r4, [r0, #6]	@ zero_extendqisi2	@ tmp153,
    	ldrb	r1, [r0, #7]	@ zero_extendqisi2	@ tmp156,
    	ldrb	ip, [r0, #3]	@ zero_extendqisi2	@ tmp146,
    	orr	r2, r2, r7, asl #8	@, tmp142, tmp139, tmp140,
    	orr	r3, r3, r6, asl #8	@, tmp152, tmp149, tmp150,
    	orr	r2, r2, r5, asl #16	@, tmp145, tmp142, tmp143,
    	orr	r3, r3, r4, asl #16	@, tmp155, tmp152, tmp153,
    	orr	r0, r2, ip, asl #24	@,, tmp145, tmp146,
    	orr	r1, r3, r1, asl #24	@,, tmp155, tmp156,
    	ldmfd	sp!, {r4, r5, r6, r7}
    	bx	lr

    Compared to the initial results, this is really nicely optimized and I
    couldn't do much better if I were to hand code it myself.

    Signed-off-by: Rob Herring <rob.herring@calxeda.com>
    Reviewed-by: Nicolas Pitre <nico@linaro.org>
    Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
    Reviewed-by: Arnd Bergmann <arnd@arndb.de>
    Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

commit a1918aeb9d365636b5ebdec3859620b6171345d7
Author: mrg666 <drgungor@hotmail.com>
Date:   Sat Mar 2 01:13:49 2013 -0500

    adapt previous backport

    Conflicts:
    	arch/arm/include/asm/delay.h

commit d05769a261159de9ca2cfb0155d71275351d4395
Author: mrg666 <drgungor@hotmail.com>
Date:   Sat Mar 2 00:13:51 2013 -0500

    ARM: 7491/1: use generic version of identical asm headers
    Inspired by the AArgh64 claim that it should be separate from ARM and one
    reason was being able to use more asm-generic headers. Doing a diff of
    arch/arm/include/asm and include/asm-generic there are numerous asm
    headers which are functionally identical to their asm-generic counterparts.
    Delete the ARM version and use the generic ones.

    Signed-off-by: Rob Herring <rob.herring@calxeda.com>
    Reviewed-by: Nicolas Pitre <nico@linaro.org>
    Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
    Reviewed-by: Arnd Bergmann <arnd@arndb.de>
    Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

commit e0f574bf316e858f5812c9144f693e99afea6b85
Author: mrg666 <drgungor@hotmail.com>
Date:   Fri Mar 1 23:59:26 2013 -0500

    fix ARM: 7587/1: ...

commit 676efa0b40b4b2604dee92c178f65dc5b6c4cb8f
Author: Stephen Boyd <sboyd@codeaurora.org>
Date:   Tue Jul 26 18:45:54 2011 +0100

    ARM: 7006/1: Migrate to asm-generic wrapper support

    With d8ecc5c (kbuild: asm-generic support, 2011-04-27) we can
    remove a handful of asm-generic wrappers in ARM code. Since the
    generic version of sizes.h doesn't contain SZ_48M, we replace
    the 4 users of SZ_48M with the equivalent SZ_32M + SZ_16M.

    Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
    Cc: Imre Kaloz <kaloz@openwrt.org>
    Acked-by: Krzysztof Halasa <khc@pm.waw.pl>
    Cc: Eric Miao <eric.y.miao@gmail.com>
    Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

    Conflicts:
    	arch/arm/include/asm/percpu.h
    	arch/arm/include/asm/sizes.h

commit b10f7380695d7123ce9dc5574411d229b12f0346
Author: mrg666 <drgungor@hotmail.com>
Date:   Fri Mar 1 23:35:07 2013 -0500

    revert ARM:7500/1 ...

commit 7511c66e75bb219869c50b8702eec63bbe6ba64f
Author: Will Deacon <will.deacon@arm.com>
Date:   Fri Aug 24 15:18:45 2012 +0100

    ARM: 7500/1: io: avoid writeback addressing modes for __raw_ accessors

    Data aborts taken to hyp mode do not provide a valid instruction
    syndrome field in the HSR if the faulting instruction is a memory
    access using a writeback addressing mode.

    For hypervisors emulating MMIO accesses to virtual peripherals, taking
    such an exception requires disassembling the faulting instruction in
    order to determine the behaviour of the access. Since this requires
    manually walking the two stages of translation, the world must be
    stopped to prevent races against page aging in the guest, where the
    first-stage translation is invalidated after the hypervisor has
    translated to an IPA and the physical page is reused for something else.

    This patch avoids taking this heavy performance penalty when running
    Linux as a guest by ensuring that our I/O accessors do not make use of
    writeback addressing modes.

    Cc: Marc Zyngier <marc.zyngier@arm.com>
    Reviewed-by: Arnd Bergmann <arnd@arndb.de>
    Reviewed-by: Nicolas Pitre <nico@linaro.org>
    Signed-off-by: Will Deacon <will.deacon@arm.com>
    Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

    Conflicts:
    	arch/arm/include/asm/io.h

commit 2e86beffdd0441fb36e8da26e69dd8a964bdae1e
Author: Jonathan Austin <Jonathan.Austin@arm.com>
Date:   Thu Aug 23 14:02:59 2012 +0100

    ARM: 7499/1: mm: Fix vmalloc overlap check for !HIGHMEM

    With !HIGHMEM, sanity_check_meminfo checks for banks that completely or
    partially overlap the vmalloc region. The test for partial overlap checks
    __va(bank->start + bank->size) > vmalloc_min. This is not appropriate if
    there is a non-linear translation between virtual and physical addresses,
    as bank->start + bank->size is actually in the bank following the one being
    interrogated.

    In most cases, even when using SPARSEMEM, this is not problematic as the
    subsequent bank will start at a higher va than the one in question. However
    if the physical to virtual address conversion is not monotonic increasing,
    the incorrect test could result in a bank not being truncated when it
    should be.

    This patch ensures we perform the va-pa conversion on memory from the
    bank we are interested in, not the following one.

    Reported-by: ??? (Steve) <zhanzhenbo@gmail.com>
    Signed-off-by: Jonathan Austin <jonathan.austin@arm.com>
    Acked-by: Nicolas Pitre <nico@linaro.org>
    Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

commit 2dbb1bf27ae739858db9e6ca64fb92cc8c0fab04
Author: mrg666 <drgungor@hotmail.com>
Date:   Fri Mar 1 21:07:55 2013 -0500

    sched: Cleanup cpu_active madness
    Stepan found:

    CPU0		CPUn

    _cpu_up()
      __cpu_up()

    		boostrap()
    		  notify_cpu_starting()
    		  set_cpu_online()
    		  while (!cpu_active())
    		    cpu_relax()

    <PREEMPT-out>

    smp_call_function(.wait=1)
      /* we find cpu_online() is true */
      arch_send_call_function_ipi_mask()

      /* wait-forever-more */

    <PREEMPT-in>
    		  local_irq_enable()

      cpu_notify(CPU_ONLINE)
        sched_cpu_active()
          set_cpu_active()

    Now the purpose of cpu_active is mostly with bringing down a cpu, where
    we mark it !active to avoid the load-balancer from moving tasks to it
    while we tear down the cpu. This is required because we only update the
    sched_domain tree after we brought the cpu-down. And this is needed so
    that some tasks can still run while we bring it down, we just don't want
    new tasks to appear.

    On cpu-up however the sched_domain tree doesn't yet include the new cpu,
    so its invisible to the load-balancer, regardless of the active state.
    So instead of setting the active state after we boot the new cpu (and
    consequently having to wait for it before enabling interrupts) set the
    cpu active before we set it online and avoid the whole mess.

    Reported-by: Stepan Moskovchenko <stepanm@codeaurora.org>
    Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
    Acked-by: Thomas Gleixner <tglx@linutronix.de>
    Link: http://lkml.kernel.org/r/1323965362.18942.71.camel@twins
    Signed-off-by: Ingo Molnar <mingo@elte.hu>

    adapted for 3.0 by mrg666 (only for arm)

    Conflicts:
    	arch/arm/kernel/smp.c

commit 00b900964c7758679e0d6dd21df5880cd89ed93e
Author: mrg666 <drgungor@hotmail.com>
Date:   Fri Mar 1 20:54:26 2013 -0500

    fix the previous commit properly

commit 011e8571e323c090bd8cf4260cadf96ea7ec5827
Author: mrg666 <drgungor@hotmail.com>
Date:   Fri Mar 1 20:44:04 2013 -0500

    fix previous commit for gcc implicit declaration warning

commit ae7f41b9ffa6dbaae15a3addd89d9142a0e09d83
Author: mrg666 <drgungor@hotmail.com>
Date:   Fri Mar 1 20:37:58 2013 -0500

    ARM: 7124/1: smp: Add a localtimer handler callable from C code
    In order to be able to handle localtimer directly from C code instead of
    assembly code, introduce handle_local_timer(), which is modeled after
    handle_IRQ().

    Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
    Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

commit d9339cc6148a6d3f5639f7ccfc8dc0634732f3c3
Author: mrg666 <drgungor@hotmail.com>
Date:   Fri Mar 1 20:17:20 2013 -0500

    ARM: 7587/1: implement optimized percpu variable access
    Use the previously unused TPIDRPRW register to store percpu offsets.
    TPIDRPRW is only accessible in PL1, so it can only be used in the kernel.

    This replaces 2 loads with a mrc instruction for each percpu variable
    access. With hackbench, the performance improvement is 1.4% on Cortex-A9
    (highbank). Taking an average of 30 runs of "hackbench -l 1000" yields:

    Before: 6.2191
    After: 6.1348

    Will Deacon reported similar delta on v6 with 11MPCore.

    The asm "memory clobber" are needed here to ensure the percpu offset
    gets reloaded. Testing by Will found that this would not happen in
    __schedule() which is a bit of a special case as preemption is disabled
    but the execution can move cores.

    Signed-off-by: Rob Herring <rob.herring@calxeda.com>
    Acked-by: Will Deacon <will.deacon@arm.com>
    Acked-by: Nicolas Pitre <nico@linaro.org>

    adapted by mrg666 for 3.0 kernel

commit ffb8750845d27d5f8a9dd5a7c063af677e86a6b0
Author: mrg666 <drgungor@hotmail.com>
Date:   Fri Mar 1 09:17:03 2013 -0500

    ARM: smp: Fix cpu_up() racing with sys_reboot

    Nothing stops a process from hotplugging in a CPU concurrently
    with a sys_reboot() call. In such a situation we could have
    ipi_cpu_stop() mark a cpu as 'offline' and _cpu_up() ignore the
    fact that the CPU is not really offline and call the
    CPU_UP_PREPARE notifier. When this happens stop_machine code will
    complain that the cpu thread already exists and BUG_ON().

    CPU0                      CPU1

    sys_reboot()
     kernel_restart()
      machine_restart()
       machine_shutdown()
        smp_send_stop()
        ...                   ipi_cpu_stop()
                               set_cpu_online(1, false)
                                local_irq_disable()
                                 while(1)
        <PREEMPT>
    cpu_up()
     _cpu_up()
       if (!cpu_online(1))
        __cpu_notify(CPU_UP_PREPARE...)

    cpu_stop_cpu_callback()
      BUG_ON(stopper->thread)

    This is easily reproducible by hotplugging in and out in a tight
    loop while also rebooting.

    Since the CPU is not really offline and hasn't gone through the
    proper steps to be marked as such, let's mark the CPU as inactive.
    This is just as easily testable as online and avoids any possibility
    of _cpu_up() trying to bring the CPU back online when it never was
    offline to begin with.

    Change-Id: Ia1daea407220578d4212ef6c65c4be837ca370fd
    Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

commit fa45f488742c594a9affbb4bad476f57f1c78d06
Author: mrg666 <drgungor@hotmail.com>
Date:   Tue Jun 11 08:55:20 2013 -0400

    smp: introduce a generic on_each_cpu_mask() function
    We have lots of infrastructure in place to partition multi-core systems
    such that we have a group of CPUs that are dedicated to specific task:
    cgroups, scheduler and interrupt affinity, and cpuisol= boot parameter.
    Still, kernel code will at times interrupt all CPUs in the system via IPIs
    for various needs.  These IPIs are useful and cannot be avoided
    altogether, but in certain cases it is possible to interrupt only specific
    CPUs that have useful work to do and not the entire system.

    This patch set, inspired by discussions with Peter Zijlstra and Frederic
    Weisbecker when testing the nohz task patch set, is a first stab at trying
    to explore doing this by locating the places where such global IPI calls
    are being made and turning the global IPI into an IPI for a specific group
    of CPUs.  The purpose of the patch set is to get feedback if this is the
    right way to go for dealing with this issue and indeed, if the issue is
    even worth dealing with at all.  Based on the feedback from this patch set
    I plan to offer further patches that address similar issue in other code
    paths.

    This patch creates an on_each_cpu_mask() and on_each_cpu_cond()
    infrastructure API (the former derived from existing arch specific
    versions in Tile and Arm) and uses them to turn several global IPI
    invocation to per CPU group invocations.

    Core kernel:

    on_each_cpu_mask() calls a function on processors specified by cpumask,
    which may or may not include the local processor.

    You must not call this function with disabled interrupts or from a
    hardware interrupt handler or from a bottom half handler.

    arch/arm:

    Note that the generic version is a little different then the Arm one:

    1. It has the mask as first parameter
    2. It calls the function on the calling CPU with interrupts disabled,
       but this should be OK since the function is called on the other CPUs
       with interrupts disabled anyway.

    arch/tile:

    The API is the same as the tile private one, but the generic version
    also calls the function on the with interrupts disabled in UP case

    This is OK since the function is called on the other CPUs
    with interrupts disabled.

    Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com>
    Reviewed-by: Christoph Lameter <cl@linux.com>
    Acked-by: Chris Metcalf <cmetcalf@tilera.com>
    Acked-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
    Cc: Frederic Weisbecker <fweisbec@gmail.com>
    Cc: Russell King <linux@arm.linux.org.uk>
    Cc: Pekka Enberg <penberg@kernel.org>
    Cc: Matt Mackall <mpm@selenic.com>
    Cc: Rik van Riel <riel@redhat.com>
    Cc: Andi Kleen <andi@firstfloor.org>
    Cc: Sasha Levin <levinsasha928@gmail.com>
    Cc: Mel Gorman <mel@csn.ul.ie>
    Cc: Alexander Viro <viro@zeniv.linux.org.uk>
    Cc: Avi Kivity <avi@redhat.com>
    Acked-by: Michal Nazarewicz <mina86@mina86.org>
    Cc: Kosaki Motohiro <kosaki.motohiro@gmail.com>
    Cc: Milton Miller <miltonm@bga.com>
    Cc: Russell King <linux@arm.linux.org.uk>
    Acked-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
    Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
    Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

commit 565bab65d288aa5ecc40eb24be071dcb73511fa9
Author: mrg666 <drgungor@hotmail.com>
Date:   Mon Jun 10 21:19:16 2013 -0400

    iarch: Cleanup enable/disable_hlt
    enable/disable_hlt() does not need to be exported and can be killed on
    architectures which do not use it at all.

    Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
    Cc: Linus Torvalds <torvalds@linux-foundation.org>
    Cc: Rusty Russell <rusty@rustcorp.com.au>
    Cc: Paul McKenney <paulmck@linux.vnet.ibm.com>
    Cc: Peter Zijlstra <peterz@infradead.org>
    Reviewed-by: Cc: Srivatsa S. Bhat <srivatsa.bhat@linux.vnet.ibm.com>
    Cc: Magnus Damm <magnus.damm@gmail.com>
    Link: http://lkml.kernel.org/r/20130321215233.377959540@linutronix.de
    Signed-off-by: Thomas Gleixner <tglx@linutronix.de>

commit 9674f55960bf69f5f8386e6569507f459f0feeff
Author: mrg666 <drgungor@hotmail.com>
Date:   Mon Jun 10 11:16:51 2013 -0400

    arch, mm: Remove tlb_fast_mode()
    Since the introduction of preemptible mmu_gather TLB fast mode has been
    broken. TLB fast mode relies on there being absolutely no concurrency;
    it frees pages first and invalidates TLBs later.

    However now we can get concurrency and stuff goes *bang*.

    This patch removes all tlb_fast_mode() code; it was found the better
    option vs trying to patch the hole by entangling tlb invalidation with
    the scheduler.

    Cc: Thomas Gleixner <tglx@linutronix.de>
    Cc: Russell King <linux@arm.linux.org.uk>
    Cc: Tony Luck <tony.luck@intel.com>
    Reported-by: Max Filippov <jcmvbkbc@gmail.com>
    Signed-off-by: Peter Zijlstra <peterz@infradead.org>
    Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
    ____________________

    x86-32: Fix possible incomplete TLB invalidate with PAE pagetables
    This patch attempts to fix:

    	https://bugzilla.kernel.org/show_bug.cgi?id=56461

    The symptom is a crash and messages like this:

    	chrome: Corrupted page table at address 34a03000
    	*pdpt = 0000000000000000 *pde = 0000000000000000
    	Bad pagetable: 000f [#1] PREEMPT SMP

    Ingo guesses this got introduced by commit 611ae8e3f520 ("x86/tlb:
    enable tlb flush range support for x86") since that code started to free
    unused pagetables.

    On x86-32 PAE kernels, that new code has the potential to free an entire
    PMD page and will clear one of the four page-directory-pointer-table
    (aka pgd_t entries).

    The hardware aggressively "caches" these top-level entries and invlpg
    does not actually affect the CPU's copy.  If we clear one we *HAVE* to
    do a full TLB flush, otherwise we might continue using a freed pmd page.
    (note, we do this properly on the population side in pud_populate()).

    This patch tracks whenever we clear one of these entries in the 'struct
    mmu_gather', and ensures that we follow up with a full tlb flush.

    BTW, I disassembled and checked that:

    	if (tlb->fullmm == 0)
    and
    	if (!tlb->fullmm && !tlb->need_flush_all)

    generate essentially the same code, so there should be zero impact there
    to the !PAE case.

    Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
    Cc: Peter Anvin <hpa@zytor.com>
    Cc: Ingo Molnar <mingo@kernel.org>
    Cc: Artem S Tashkinov <t.artem@mailcity.com>
    Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

commit 59938edfc9b38bb36aba8b8434e33c9b82156a35
Author: mrg666 <drgungor@hotmail.com>
Date:   Tue Jun 18 11:48:47 2013 -0400

    ARM: perf: simplify __hw_perf_event_init err handling
    Currently __hw_perf_event_init has an err variable that's ignored right
    until the end, where it's initialised, conditionally set, and then used
    as a boolean flag deciding whether to return another error code.

    This patch removes the err variable and simplifies the associated error
    handling logic.

    Signed-off-by: Mark Rutland <mark.rutland@arm.com>
    Signed-off-by: Will Deacon <will.deacon@arm.com>
    ______________

    ARM: 7664/1: perf: remove erroneous semicolon from event initialisation
    Commit 9dcbf466559f ("ARM: perf: simplify __hw_perf_event_init err
    handling") tidied up the error handling code for perf event
    initialisation on ARM, but a copy-and-paste error left a dangling
    semicolon at the end of an if statement.

    This patch removes the broken semicolon, restoring the old group
    validation semantics.

    Cc: Mark Rutland <mark.rutland@arm.com>
    Acked-by: Dirk Behme <dirk.behme@gmail.com>
    Signed-off-by: Chen Gang <gang.chen@asianux.com>
    Signed-off-by: Will Deacon <will.deacon@arm.com>
    Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

commit d696d8b79dad60b37917172f1804b428cf5cf60f
Author: mrg666 <drgungor@hotmail.com>
Date:   Mon Aug 5 21:40:07 2013 -0400

    staging: android: logger: Correct write offset reset on error
    commit 72bb99cfe9c57d2044445fb34bbc95b4c0bae6f2 upstream.

    In the situation that a writer fails to copy data from userspace it will reset
    the write offset to the value it had before it went to sleep. This discarding
    any messages written while aquiring the mutex.

    Therefore the reset offset needs to be retrieved after acquiring the mutex.

    Cc: Android Kernel Team <kernel-team@android.com>
    Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

commit 0c5a51958f5cbe5816a5bed5c064d746e4e714a9
Author: mrg666 <drgungor@hotmail.com>
Date:   Tue Aug 6 09:10:57 2013 -0400

    writeback: Fix occasional slow sync(1)
    In case when system contains no dirty pages, wakeup_flusher_threads()
    will submit WB_SYNC_NONE writeback for 0 pages so wb_writeback() exits
    immediately without doing anything. Thus sync(1) will write all the
    dirty inodes from a WB_SYNC_ALL writeback pass which is slow.

    Fix the problem by using get_nr_dirty_pages() in
    wakeup_flusher_threads() instead of calculating number of dirty pages
    manually. That function also takes number of dirty inodes into account.

    CC: stable@vger.kernel.org
    Reported-by: Paul Taysom <taysom@chromium.org>
    Signed-off-by: Jan Kara <jack@suse.cz>

commit 572a5bba375facc0f31d34decdcd72829c56c938
Author: mrg666 <drgungor@hotmail.com>
Date:   Thu Sep 12 17:39:28 2013 -0400

    workqueue: cond_resched() after processing each work item
    commit b22ce2785d97423846206cceec4efee0c4afd980 upstream.

    If !PREEMPT, a kworker running work items back to back can hog CPU.
    This becomes dangerous when a self-requeueing work item which is
    waiting for something to happen races against stop_machine.  Such
    self-requeueing work item would requeue itself indefinitely hogging
    the kworker and CPU it's running on while stop_machine would wait for
    that CPU to enter stop_machine while preventing anything else from
    happening on all other CPUs.  The two would deadlock.

    Jamie Liu reports that this deadlock scenario exists around
    scsi_requeue_run_queue() and libata port multiplier support, where one
    port may exclude command processing from other ports.  With the right
    timing, scsi_requeue_run_queue() can end up requeueing itself trying
    to execute an IO which is asked to be retried while another device has
    an exclusive access, which in turn can't make forward progress due to
    stop_machine.

    Fix it by invoking cond_resched() after executing each work item.

    Signed-off-by: Tejun Heo <tj@kernel.org>
    Reported-by: Jamie Liu <jamieliu@google.com>
    References: http://thread.gmane.org/gmane.linux.kernel/1552567
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

commit 0aa0c915c134dc10f4d6de2ddbe1938c6a377e5c
Author: mrg666 <drgungor@hotmail.com>
Date:   Wed Aug 7 11:11:48 2013 -0400

    ARM: 7743/1: compressed/head.S: work around new binutils warning
    commit da94a829305f1c217cfdf6771cb1faca0917e3b9 upstream.

    In August 2012, Matthew Gretton-Dann checked a change into binutils
    labelled "Error on obsolete & warn on deprecated registers", apparently as
    part of ARMv8 support. Apparently, this was supposed to emit the message
    "Warning: This coprocessor register access is deprecated in ARMv8" when
    using certain mcr/mrc instructions and building for ARMv8. Unfortunately,
    the message that is actually emitted appears to be '(null)', which is
    less helpful in comparison.

    Even more unfortunately, this is biting us on every single kernel
    build with a new gas, because arch/arm/boot/compressed/head.S and some
    other files in that directory are built with -march=all since kernel
    commit 80cec14a8 "[ARM] Add -march=all to assembly file build in
    arch/arm/boot/compressed" back in v2.6.28.

    This patch reverts Russell's nice solution and instead marks the head.S
    file to be built for armv7-a, which fortunately lets us build all
    instructions in that file without warnings even on the broken binutils.

    Without this patch, building anything results in:

    arch/arm/boot/compressed/head.S: Assembler messages:
    arch/arm/boot/compressed/head.S:565: Warning: (null)
    arch/arm/boot/compressed/head.S:676: Warning: (null)
    arch/arm/boot/compressed/head.S:698: Warning: (null)
    arch/arm/boot/compressed/head.S:722: Warning: (null)
    arch/arm/boot/compressed/head.S:726: Warning: (null)
    arch/arm/boot/compressed/head.S:957: Warning: (null)
    arch/arm/boot/compressed/head.S:996: Warning: (null)
    arch/arm/boot/compressed/head.S:997: Warning: (null)
    arch/arm/boot/compressed/head.S:1027: Warning: (null)
    arch/arm/boot/compressed/head.S:1035: Warning: (null)
    arch/arm/boot/compressed/head.S:1046: Warning: (null)
    arch/arm/boot/compressed/head.S:1060: Warning: (null)
    arch/arm/boot/compressed/head.S:1092: Warning: (null)
    arch/arm/boot/compressed/head.S:1094: Warning: (null)
    arch/arm/boot/compressed/head.S:1095: Warning: (null)
    arch/arm/boot/compressed/head.S:1102: Warning: (null)
    arch/arm/boot/compressed/head.S:1134: Warning: (null)

    Signed-off-by: Arnd Bergmann <arnd@arndb.de>
    Cc: Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
    Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

    adapted from Linux 3.9.6 by mrg666

    Conflicts:
    	arch/arm/boot/compressed/Makefile

    Conflicts:
    	arch/arm/boot/compressed/Makefile

commit 2d2d5a0dead23dca6ce2db5e1cd0d45e80fbb427
Author: mrg666 <drgungor@hotmail.com>
Date:   Wed Aug 7 10:14:20 2013 -0400

    ARM: 7755/1: handle user space mapped pages in flush_kernel_dcache_page
    commit 1bc39742aab09248169ef9d3727c9def3528b3f3 upstream.

    Commit f8b63c1 made flush_kernel_dcache_page a no-op assuming that
    the pages it needs to handle are kernel mapped only.  However, for
    example when doing direct I/O, pages with user space mappings may
    occur.

    Thus, continue to do lazy flushing if there are no user space
    mappings.  Otherwise, flush the kernel cache lines directly.

    Signed-off-by: Simon Baatz <gmbnomis@gmail.com>
    Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
    Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

    adapted from Linux 3.9.9 by mrg666

commit 05396c8b979470322b714a04f662b517075856f9
Author: mrg666 <drgungor@hotmail.com>
Date:   Tue Aug 6 11:19:26 2013 -0400

    ARM: 7791/1: a.out: remove partial a.out support
    a.out support on ARM requires that argc, argv and envp are passed in
    r0-r2 respectively, which requires hacking load_aout_binary to
    prevent argc being clobbered by the return code. Whilst mainline kernels
    do set the registers up in start_thread, the aout loader has never
    carried the hack in mainline.

    Initialising the registers in this way actually goes against the libc
    expectations for ELF binaries, where argc, argv and envp are passed on
    the stack, with r0 being used to hold a pointer to an exit function for
    cleaning up after the dynamic linker if required. If the pointer is
    NULL, then it is ignored. When execing an ELF binary, Linux currently
    zeroes r0, then sets it to argc and then finally clobbers it with the
    return value of the execve syscall, so we actually end up with:

    	r0 = 0
    	stack[0] = argc
    	r1 = stack[1] = argv
    	r2 = stack[2] = envp

    libc treats r1 and r2 as undefined. The clobbering of r0 by sys_execve
    works for user-spawned threads, but when executing an ELF binary from a
    kernel thread (via call_usermodehelper), the execve is performed on the
    ret_from_fork path, which restores r0 from the saved pt_regs, resulting
    in argc being presented to the C library. This has horrible consequences
    when the application exits, since we have an exit function registered
    using argc, resulting in a jump to hyperspace.

    This patch solves the problem by removing the partial a.out support from
    arch/arm/ altogether.

    Cc: <stable@vger.kernel.org>
    Cc: Ashish Sangwan <ashishsangwan2@gmail.com>
    Signed-off-by: Will Deacon <will.deacon@arm.com>
    Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

    adapted from Linux 3.11-rc4 by mrg666

    Conflicts:
    	arch/arm/Kconfig
    	arch/arm/configs/pyramid_defconfig
    	arch/arm/configs/sultan_defconfig

commit c2f43df758197ce438ae38664bd0174355e07741
Author: mrg666 <drgungor@hotmail.com>
Date:   Tue Aug 6 10:54:34 2013 -0400

    ARM: 7803/1: Fix deadlock scenario with smp_send_stop()
    If one process calls sys_reboot and that process then stops other
    CPUs while those CPUs are within a spin_lock() region we can
    potentially encounter a deadlock scenario like below.

    CPU 0                   CPU 1
    -----                   -----
                            spin_lock(my_lock)
    smp_send_stop()
     <send IPI>             handle_IPI()
                             disable_preemption/irqs
                              while(1);
     <PREEMPT>
    spin_lock(my_lock) <--- Waits forever

    We shouldn't attempt to run any other tasks after we send a stop
    IPI to a CPU so disable preemption so that this task runs to
    completion. We use local_irq_disable() here for cross-arch
    consistency with x86.

    Reported-by: Sundarajan Srinivasan <sundaraj@codeaurora.com>
    Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
    Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

    adapted from Linux 3.11-rc4 by mrg666

commit 750ee8166b2ce870c0d7f9671e8df1649f4a40ee
Author: Sultanxda <sultanxda@gmail.com>
Date:   Thu Oct 17 17:47:14 2013 -0700

    bcmdhd: update from sultan-kernel-bruce-linaro3

commit 631f5d64f6d68ca472b49fc922ceea59f0f4937d
Author: Sultanxda <sultanxda@gmail.com>
Date:   Thu Oct 17 17:43:19 2013 -0700

    Defconfig: disable DEBUG_BUGVERBOSE and OABI_COMPAT