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701176

|digital-logic|frequency|ttl|function-generator|

<p>I'm getting a base-10 vibe from your question.</p> <p>I suggest a top-oscillator, maybe crystal based, at some multiple of 10 frequency, with a cascade of dividers after it. You can buy complete oscillators, or you can buy a ceramic or crystal resonator, and wrap it round a logic gate (with a couple of small Cs and a big R) to make an oscillator. For the chain of dividers, I suggest something like 74xx390 dividers, these contain two /2 and two /5 dividers, for a total division of /100 per package. Select which output you need with jumpers.</p> <p>Far simpler is an MCU board, perhaps an Arduino, and program the appropriate divider.</p>

<p>What is the simplest circuit that can be used to generate a 5V TTL signal with fixed frequencies such as 0.5Hz, 1Hz, 50Hz, 100Hz, 500Hz, 1kHz, 5kHz, 10kHz..?</p>

What is a simple circuit to generate TTL signal with fixed frequencies?

2024-02-12T15:14:47.583

701183

|diodes|

<p>The parts are likely to be fuses due to the 00.0 ohm. Also - the case is transparent as this will allow a visual indication if it is fused or not.</p>

<p>I searched with google images, guesses, every way I could. Is it a diode? Light bulb? The package says 2-0q0887.</p> <p>The best I can figure it may be a germanium diode. An ohmmeter reads 00.0.</p> <p>It is red on one end and purple on the other.</p> <p><a href="https://i.stack.imgur.com/bmkgV.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/bmkgV.jpg" alt="enter image description here" /></a></p>

Are these germanium diodes?

2024-02-12T15:38:06.443

701185

|analog|bjt|current-sensing|

<p>Below is what I think is the general idea of this type of circuit (clickable link). <a href="https://falstad.com/circuit/circuitjs.html?ctz=CQAgjCAMB0l3BWcMBMcUHYMGZIA4UA2ATmIxGwBYQlLsaBTAWjDACgAlcS61lcMPz5QRlSOH7ip0BGwDu3XoPAZCAyWwBOITEOW6Va6ewVhVhi2jzh5OjEPMGrNhdgQO1Y8WaO23HuwCUNgAXHXwdFF5HKJEWOJgEYjx3PEFCQjTKNGJkcQATBgAzAEMAVwAbENCdMUjqJ1jxeOJoHnxKYgQ8SEE8LFymRPtKDOyovDcEQggwOBBC0srqhSjxFFjnDepIWy3NiJRpqD3D458dY93TRzqLo99te-PzLxE5%20D37WvXvh5PtE5jgZsNgjBRcLtAd9QWoDG9xKC4LYLnR%20PDsBobp5MYoQGiTlwwDx8bjhASpPjKdSZHs8NZYRC1IzgmFGezMkz3lAZAgMEl%20YRsBh8ERsBBhgh3N0wFKZShxXkFsVylU-Jz-BRORT1dYCRisVqGWgjTp6ScAJZU7yvQjRcEwQicfF2iydNQXSl1ak82QKShgOHmsHWFDm65u%20aoslffhvA0uM0MsGBLm7AAeFAQv1yCGJZrj4RAAHsAG4MTQAYzKmk0DAAdiEADoAZ2LZRCAAcO2xM2AUwrvEKdKD8UWAIrsTNh9G43C5BW0CfBTPYHoUOhU8hUTwT7BaCzCC6eigR4-6b7CDP4ubhWiUcjOBriCrFkr5XtJ8BUDe8YVjk0OBbBsWzYNdLhAAAxCURH4eJX3fVtq1rBtqiAA" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/82eEK.png" alt="aaa" /></a></p> <p>When the V drop across the 30ohm and R_sens are equal, then Q1 and Q2 are in balance, and about 1mA comes out of Q2's collector. The the open-collector output at Q3 is normally on in this case. It's also normally on when there isn't any V drop in Rsens.</p> <p>As load increases beyond that balance point, larger V drop across R_sens gradually reduces Q2's Vbe, Q2 current falls, and eventually Q3's open-collector output turns off.</p> <p>The 30 ohm isn't really necessary but lets you add an offset to the balance point, i.e. change the threshold without having to play with the typical load in Q1 and Q2.</p> <p>The top 3.3k resistor is possibly redundant, but in case a large reverse load current flows, it should limit current thru Q2 into Q3's base.</p> <p>Finally, depending on how it's set up, this concept might not be the best when applied as an overcurrent circuit (vs when applied within a feedback loop), because Q2 could be saturated in the normal-load condition, so it mightn't be fast enough turning off the output.</p>

<p>I'm trying to adapt a current limiter design that I found, and I'm having trouble understanding the &quot;current sense&quot; part of it.</p> <p>The current sensing is implemented using a shunt resistor, which is then measured using a current mirror using the circuit below.</p> <p><img src="https://i.stack.imgur.com/smCat.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fsmCat.png">simulate this circuit</a> &ndash; Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a>}</p> <p>The designated output nodes (<em>OUTA</em>, <em>OUTB</em>) are then fed into a simple amplifier, which in turn drives the a high-side PMOS FET gate (<em>GATE</em>).</p> <p>In theory this circuit should allow current to pass up-to a limit that is set by <em>RL</em>, and afterwards put the high-side FET into linear region to limit the current.</p> <p>I'm trying to understand how the current sense part of this circuit works, and how one would analyze and select the resistor values for a given current limit, input voltage, etc.</p> <p>Most of the designs for current sensing using a current mirror I've seen employ a emitter resistor on Q1 (e.g. <a href="https://electronics.stackexchange.com/questions/681464/pnp-bjt-current-mirror-across-shunt-resistor-used-as-current-meter">1</a>), which is used to set the quiescent current based on the maximum sense voltage deviation, but this design does not have this so I'm having trouble to start with the analysis.</p> <p>Any pointers would be highly appreciated.</p> <p>EDIT: updated schematics to fix gate short and provide easy simulation</p>

Understanding current sense circuit

2024-02-12T16:28:04.540

701187

|adc|esp8266|infrared|phototransistor|tcrt5000|

<p>Your second schematic would work, but the transistor in the sensor has a saturation voltage of 0.4 V at full reflection. So this way the usable ADC range would be 0.4 to 1 V.</p> <p>If you put the divider in the emitter path you can use the full ADC range.</p> <p>A small capacitor will suppress RF noise from wiring.</p> <p><img src="https://i.stack.imgur.com/AHIbe.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fAHIbe.png">simulate this circuit</a> &ndash; Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a>}</p>

<p>I have a circuit with a TCRT5000 that lets me detect proximity since the reflected IR rays will make the photo sensitive transistor conductive and will pull down the voltage below the 10kΩ resistor, which is pin 1 of the TCRT5000.</p> <p><a href="https://i.stack.imgur.com/ZHFe9.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/ZHFe9.png" alt="enter image description here" /></a></p> <p>This works fine.</p> <p>Now I would like to read that voltage using an ESP07 which can, according to the <a href="https://docs.ai-thinker.com/_media/esp8266/docs/esp-07s_product_specification_en.pdf" rel="nofollow noreferrer">datasheet</a> only detect voltages from 0-1V on its ADC pin.</p> <p>To split down the voltage I would naturally use a voltage divider with 220kΩ and 100kΩ so my new schematic would look like so:</p> <p><a href="https://i.stack.imgur.com/UohGB.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/UohGB.png" alt="enter image description here" /></a>.</p> <p>In a way, the 10kOhm resistor &quot;sort-of-shorts&quot; the path from the ADC to 3V3 which obviously defeats the purpose of the whole operation.</p> <p>Can I just remove R3 and let the voltage on the ADC &quot;start&quot; at 1V and let it be pulled down further as IR is reflected by an approaching object?</p> <p>Like so:</p> <p><a href="https://i.stack.imgur.com/oALkV.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/oALkV.png" alt="enter image description here" /></a></p>

TCRT5000 combined with ESP8266 ADC voltage divider

2024-02-12T16:33:04.477

701195

|magnetics|

<p>The tugging of a tiny magnet will be uncomfortable and perhaps painful, but the magnet shouldn't get ripped out of the finger. There may be internal bleeding due to the magnet motion ripping the nearby capillaries. Wrapping the finger tightly would reduce the range of motion of the magnet, and thus discomfort.</p> <p>How tiny should the magnet be? That requires experimentation - yes, unfortunately. People's pain tolerance varies, so one person may experience way more discomfort than another with a magnet of the same size. It's a tradeoff between sensitivity to magnetic fields and magnetic fields making one feel pain.</p> <p>Cooked is off the menu, it'll be served raw. There's not enough RF energy density for a tiny magnet to do much RF absorption.</p>

<p>A few years ago in the biohacking community there was a phase where people (mostly engineers) were having small magnets embedded in a fingertip in order to sense magnetic fields. I was slightly tempted at the time but never had the procedure. Since that time I have had an MRI scan. The question is the obvious one - what would happen when finger meets a 2T field?</p> <p>Depending on alignment the finger would be either repelled, attracted or possibly rotated into alignment. I imagine it would be rather unpleasant, but how unpleasant? Just a tugging sensation or the finger magnet doing an impression of &quot;Alien&quot; and bursting out of the skin?</p> <p>And what of the RF excitation? The magnet would probably not make a good antenna, but I'm not sure. Do we add &quot;cooked&quot; to the menu?</p>

Finger magnets and MRI

2024-02-12T17:21:15.327

701221

|pcb|pcb-design|transformer|raspberry-pi|poe|

<blockquote> <p>Is this the best route to isolating the signals and providing proper polarity to my transformer?</p> </blockquote> <p>Yes, the design looks good.</p> <p>The design looks fine, you have the rectifier diodes in the right location, and each POE pair can have the voltage reversed and it will still reach your DC/DC converter. The snubbers also look correct.</p> <p>I am not sure how your ground is for the 'chassis ground' but this can also be tied back to the data pairs, this may not be possible on an RPI due to the headers. It's not necessary, just makes things a little nicer.<br /> <a href="https://i.stack.imgur.com/6ou8Z.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/6ou8Z.png" alt="enter image description here" /></a> Source: <a href="https://www.ti.com/lit/an/slua469/slua469.pdf?ts=1708510994552&amp;ref_url=https%253A%252F%252Fwww.google.com%252F" rel="nofollow noreferrer">https://www.ti.com/lit/an/slua469/slua469.pdf?ts=1708510994552&amp;ref_url=https%253A%252F%252Fwww.google.com%252F</a></p> <p>You also say you have isolation, this is useful if you need to be absolutely 802.3af or at compliant but not necessary if you just want to power a device.</p>

<p><em><strong>Am I doing the signal rectification properly for the POE application using the Diodes on the RPI 4B 4 pin header?</strong></em></p> <p>I have attached images of my design, as I am trying to use a Raspberry PI 4B with POE (Power Over Ethernet). I have essentially built a custom hat while taking advantage of the internal Raspberry PI POE twisted pair transformer output 4 pin header. I used a diode array as a rectifier. This is my first time implementing anything of this nature, and I am fairly new to PCB design.</p> <p>Is this the best route to isolating the signals and providing proper polarity to my transformer? I have tried really hard to understand the nature of the pi as well, and it seems a constant 57V is supplied on one of the four pins, while one other provides the respective Earth Ground.</p> <p>I found <a href="https://electronics.stackexchange.com/questions/552505/ag9205s-poe-pd-module-and-raspberry-pi">other examples</a> showing the need for a rectifier on the output 4 pin provided by the PI. Here is the established understanding of the <a href="https://di-marco.net/docs/n0d3-b0x_v2/pi_poe/" rel="nofollow noreferrer">provided 4 pin header</a>.</p> <p>I really would like peace of mind that this design that I have created will work for all Pi 4Bs, as I have actually already failed designing one POE device due to an issue with grounding and not following proper keep out areas for isolation (I think).</p> <p>The 57V measured signal is isolated and supplied to the <a href="https://www.mouser.com/datasheet/2/447/KEM_FB0002_Z_PWZ-3316852.pdf" rel="nofollow noreferrer">Ferrite Beads</a>, passing through the <a href="https://www.mouser.com/datasheet/2/597/xal50xx-270657.pdf" rel="nofollow noreferrer">Inductor (XAL5050-103MEC)</a>, then to our <a href="https://www.coilcraft.com/getmedia/fe569a42-533f-4322-ab3b-764883f54979/fct1xxm22sl.pdf" rel="nofollow noreferrer">5V-out 25W FCT1-50M22SL POE Forward Transformer</a>. Further, the PGND signal is isolated from my signal ground post transformer through three 1n/2000V 2000V X7R Capacitor connections. The POE IC is the <a href="https://www.mouser.com/datasheet/2/277/MP8009GV_Z-2946113.pdf" rel="nofollow noreferrer">MP8009GV</a></p> <p><a href="https://i.stack.imgur.com/OSfIc.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/OSfIc.png" alt="enter image description here" /></a><a href="https://i.stack.imgur.com/gURoB.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/gURoB.png" alt="enter image description here" /></a></p>

Raspberry Pi 4B POE Rectifier Circuit recommendation

2024-02-12T21:45:02.710

701225

|operational-amplifier|loop-gain|

<p>You've grounded both inputs to the 741, which means it <em>is</em> operating open-loop. It's a simulation so there's not even any resistance (not that it would matter that much with the resistor values shown).</p> <p><a href="https://i.stack.imgur.com/OIK8Z.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/OIK8Z.png" alt="enter image description here" /></a></p> <p>So you're getting the offset voltage multiplied by the open-loop gain (the negative of that, in fact, the way we usually define it).</p> <p>If you short the other end of the 1kΩ resistor to ground you'll get -100 times the offset voltage at the output (which should not cause the amplifier to rail).</p> <p>If you short the feedback resistor (but not the 1kΩ resistor) you'll the negative of the offset voltage at the output.</p> <p>An &quot;ideal&quot; op-amp with inputs shorted has an indeterminate output. The gain is infinite and the offset voltage is zero, and <span class="math-container">\$0 \cdot \infty\$</span> is indeterminate.</p>

<p>The circuit in my figure is an inverting amplifier with a gain of -100.</p> <p><a href="https://i.stack.imgur.com/H0lkz.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/H0lkz.png" alt="enter image description here" /></a></p> <p>My instructor asked me to ground the inputs to see what would happen and discuss what should happen for an ideal op-amp. In an ideal op-amp, I think there would be no problem, because the inputs should have equal voltage anyway. So the output would be 0V.</p> <p><a href="https://i.stack.imgur.com/DWO8o.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/DWO8o.png" alt="enter image description here" /></a></p> <p>In a non-ideal op-amp, I know that there exists an offset voltage. By grounding the input, I somehow cause the output to saturate to 14 V DC. But I don't understand the mechanism behind this saturation.</p> <p>I did some reading and found that when an op-amp is operating in open loop mode, then if both inputs are grounded, the input offset voltage will be multiplied by the full open loop gain.</p> <p>Based on the comments I've received, I can understand how grounding R2 effectively nullifies my feedback, because the &quot;-&quot; input on the op-amp doesn't feel the feedback. Thus I'm effectively operating in open loop mode, and the input offset voltage is multiplied by the open loop gain.</p>

Why am I getting a nonzero voltage out of this inverting amplifier op-amp when I ground the input?

2024-02-12T22:11:35.607

701235

|shift-register|74hc595|bascom|

<p>Many thanks to all those who responded.</p> <p>I have carefully checked the hardware and discovered cold solders on the 74HC595s.</p> <p>So I re-soldered and cleaned them, and at first the outputs started to activate, not in logical order, but after reviewing my code, there was a small error, but I managed it.</p>

<p>I'm migrating a code made in Bascom from a fully functional hardware to a C language (XC8) Through two 74HC595. They increase to 16 digital outputs.</p> <p><a href="https://i.stack.imgur.com/x6xrA.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/x6xrA.png" alt="enter image description here" /></a></p> <p>The way they do it is like this</p> <p><a href="https://i.stack.imgur.com/vDUMs.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/vDUMs.png" alt="enter image description here" /></a></p> <p>I have made my code, but it doesn't work, that is, I send some value to either of the two 74HC595s, but their outputs are always at logical zero.</p> <p>So I turned to the logic analyzer to see what's going on, and apparently the time diagram is fine.</p> <p>In the following image I send 0x80 to the first 74HC595, and 0x03 to the other.</p> <p><a href="https://i.stack.imgur.com/62SGb.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/62SGb.png" alt="enter image description here" /></a></p> <p>I suspect that perhaps between both bytes (0x80 and 0x03) there must perhaps be a pause or something, but I can't find what the timing diagram of two or more 74HC595s connected in cascade looks like.</p> <p>Any comment or suggestion is welcome.</p>

Problem using two 74HC595 to create a 16-bit output

2024-02-12T23:44:28.580

701263

|microcontroller|ac|dc|noise|resistance|

<p>Using shielded cables fixed the problem, I will include an image of the results when I collect enough data.</p> <p>As promised, here is a sample of the data after shielding:</p> <p><a href="https://i.stack.imgur.com/cEwS8.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/cEwS8.png" alt="enter image description here" /></a></p>

<p>I built a small system to monitor wood drying. The idea is to turn on exhaust or circulation fans (230V-AC) based on the absolute humidity and ambient temperature (respectively) of a small drying chamber.</p> <p>To monitor the progress of the drying, I built a small DC circuit based on voltage dividers to get the resistance of the wood inside; this can be converted to moisture content level in %.</p> <p>Currently, I am noticing that the measurements are working fine when the fans are off, but that is a very narrow window of time (check plots). Based on this, I am setting the relays of the fans as high or low.</p> <p>The moisture content measurements are having abrupt jumps and drops which happen when the exhaust or circulation fans are being turned on and off.</p> <p><a href="https://i.stack.imgur.com/bPDfD.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/bPDfD.png" alt="Plot of moisture content on the first plot, fans on the last two" /></a></p> <p>I did not filter mains frequency from the signals yet, I wanted to ask here to get more insight into this problem and hopefully get some nice either signal processing or electric circuit design answers.</p> <p>Circuit for those who asked:</p> <p><a href="https://i.stack.imgur.com/sa7xB.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/sa7xB.png" alt="Circuit" /></a></p>

Unstable to do resistance measurements due to electric fans

2024-02-13T08:23:26.643

701281

|integrated-circuit|iot|

<p>Active current tells you how much the device draws from it's power supply when on and active, through Vcc. As opposed to the standby current when the device is in shutdown.<p> The maximum wiper current is given as 4.4mA, with a 10s pulse of of 8.8mA, so no it cannot handle 200+ mA.</p>

<p>The <a href="https://www.renesas.com/us/en/document/dst/x9c102-x9c103-x9c104-x9c503-datasheet?language=en?language=en" rel="nofollow noreferrer">datasheet of the X9C103</a> says that the maximum active current is 3mA. Is it the maximum current that can run through the potentiometer? Actually, I am not clear about the term 'active current'. Can it withstand 200-300mA of current?</p> <p>Is there any other digital potentiometer that can withstand higher currents?</p> <p>Edit: The reason I am asking this is because I am trying to build a setup which will automatically vary the load of a solar cell to measure its current and voltage and draw I-V curve in real time. The cell I am using has rated maximum current of 160mA. That's why I need a digital potentiometer with higher current capacity. Any idea on how this can be done is highly appreciated.</p>

How much current can the X9C103/X9C103S digital potentiometer handle?

2024-02-13T11:36:19.943

701297

|diodes|relay|raspberry-pi|circuit-protection|solenoid|

<p>The photograph and the pictorial do not tally.</p> <p>The photograph shows the flyback diode wrongly wired across the power supply terminals.</p> <p>The corresponding schematic is as follows.</p> <p><a href="https://i.stack.imgur.com/verMj.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/verMj.png" alt="enter image description here" /></a></p> <p>On the other hand the pictorial shows the flyback diode correctly wired across the valve solenoid.</p> <p>Here's the appropriate schematic.</p> <p><a href="https://i.stack.imgur.com/SvT6o.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/SvT6o.png" alt="enter image description here" /></a></p> <p>With the flyback diode wired across the valve solenoid, there should be no spark when it is de-energised by opening the relay contact or by disconnecting the wire.</p>

<p>As a student, I'm currently working on a science project where I intend to connect a 12V, 2A solenoid valve to a relay and subsequently to a Raspberry Pi Pico. The solenoid valve is powered by a 12V, 5A source. Despite installing two 1N4001 flyback diodes, I'm still experiencing sparking issues with the solenoid valve.</p> <p>I've verified that the flyback 1N4001 diodes are functioning properly. Upon watching videos of others facing similar issues, I've noticed that the sparks I'm experiencing are larger than theirs.</p> <p>For my project, the valve needs to be open for a few seconds and then closed again.</p> <p>Could anyone please provide insights into why this issue might be occurring, what I can do to mitigate it, and if there are any alternative solutions I could explore?</p> <p><a href="https://www.amazon.de/dp/B01MS7H1ZP/ref=pe_27091401_487027711_TE_SCE_dp_i1" rel="nofollow noreferrer">The valve I am using.</a></p> <p>Sparks:</p> <p><a href="https://i.stack.imgur.com/O48Lf.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/O48Lf.png" alt="enter image description here" /></a></p> <p>Circuit diagram:</p> <p><a href="https://i.stack.imgur.com/pGols.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/pGols.png" alt="enter image description here" /></a></p>

Issue with solenoid valve sparks despite using two 1N4001 flyback diodes

2024-02-13T13:56:12.703

701308

|555|

<p>This is typical of a polarized capacitor connected with the wrong polarity. It works initially, but fails after some time.</p>

<p>I'm trying to follow <a href="https://eater.net/8bit/clock" rel="nofollow noreferrer">Ben Eaters clock module design</a> using the NE555 timer in astable configuration - basically right now to only flash an LED. I think the design is basically what is shown also in the datasheet.</p> <p>I'm fairly confident that I've copied the circuit exactly from the design but my 555 behaves erraticly and slows down over time. I have already tried to replace the 555 timer, but the result is the same. I've tried a 5V USB power bank, a 5V phone charger and also my 5V bench power supply - same results.</p> <ol> <li>After connecting the power supply, the LED blinks as expected with a fixed on/off time</li> <li>After 2-3 minutes, the LED blinking starts to be erratic, sometimes taking longer, sometimes faster</li> <li>After another 2-3 minutes, the LED blinking stops completely or blinks only occasionally - the LED is always on.</li> </ol> <p>This is my adapted schematic from the Ben Eater circuit - compared to the original it has R2 100k instead of a potentiometer and adds 340 ohm current limiting R3 in series with an LED:</p> <p><a href="https://i.stack.imgur.com/HMSjs.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/HMSjs.jpg" alt="Schematic" /></a></p> <p>By now I'm fairly certain that it must have something to do with the 1uF capacitor. If I take it out and replace it with a new one, the LED blinks again as expected. I've now tried it with three capacitors and they all eventually lead to the same erratic behavior. If I leave the circuit unplugged for a couple of minutes, it recovers and works again as expected.</p> <p>The 1uF capacitors are fairly old - I bought a box of different capacitors ~10 years ago. They are all unused and were stored at normal room temperatures. I know that electrolytic capacitors can dry out, but is that really an explanation for my observation? If that is so, shouldn't I expect basically all modern electronic devices to stop working after ~10 years? I've measured the capacitor with my multimeter and it shows 980nF, which is within the expected tolerance.</p> <p>I have access to an oscilloscope, but I don't really know what I should look for. Measuring at the 555 output, I see that it reflects what the LED shows and measuring at the 1uF capacitor, I see that it doesn't discharge anymore when it is in the stuck state.</p>

NE555 slows down - bad capacitor?

2024-02-13T14:47:29.817

701316

|mosfet|

<p>Thanks for the update. I now want to see inside the motor to compare new brush vs old brush. Your conclusion seems logical, but the same as all the comments here. Brush motors generate noise from the commutation of the brushes.</p> <p>I have seen motors with capacitors soldered between the motor case (chassis) and the positive lead of the motor and the same thing on the negative side. The capacitor acts as a short at high frequencies, so when the motor generates noise it will be clamped (shorted) to ground (case) before travelling on the motor wires that go to the MOSFET.</p>

<p>Another &quot;Arduino &amp; MOSFET&quot; question. I can't figure this one out. I've blown through 4 Nanos in the past week. The circuit works fine for several motor cycles, then the uC just completely dies.</p> <p>I've checked every single point with my oscilloscope, and I can't find any voltages that would damage the Arduino. The 5 V power supply remains steady with the motor on/off, the GPIO pin never exceeds 5 V. Motor voltage spikes are eliminated with the flywheel diode.</p> <p>I've rebuilt the circuit entirely three times, taking painstaking care each time to connect it properly. I've tried this circuit with an IRLZ44N and a DMN3023L-7. With both setups, after a few motor cycles, the Nano is completely fried.</p> <p>I'm just driving one of these simple <a href="https://rads.stackoverflow.com/amzn/click/com/B072R57C56" rel="nofollow noreferrer" rel="nofollow noreferrer">geared DC motors</a>. I'm at a complete loss, I don't even know what to check.</p> <p>Gate resistor - check. Soft start - check. Flyback diode - check. TTL FET - check. WTF!? Here's the circuit:</p> <p><strong>Edit #1:</strong> C1 is not the root problem. The first two circuits blew up, so I added C1 hoping a soft start might help, which it clearly didn't. The FET still works perfectly fine. I can turn the motor on/off by connecting the gate to 5 V. I quickly switched 5 V to the gate from my PSU with the oscope attached to the gate, and monitored the voltage. It never strayed from 0-5 V.</p> <p>My 5 V reg &amp; Nano are connected to ground. It was wrong of me to assume this was known. R2 is 100 kΩ</p> <p><a href="https://i.stack.imgur.com/95U8T.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/95U8T.png" alt="enter image description here" /></a></p> <p><strong>Edit #2</strong> You can now see the circuit. 12 V comes in from a Amazon nameless adapter. The 12 V stays constant, no spikes, dips, or crazy Vpps. In the shown circuit, I'm using the Nano's built-in vreg, but in the upper left hand of the last photo, you can see my older circuit where I was using a dedicated 5 V reg, so that's not the problem. Note the kapton tape on both the circuit board and drain tab #4 of the TO-220, it's not shorted to anything.</p> <p><a href="https://i.stack.imgur.com/zl1bu.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/zl1bu.jpg" alt="enter image description here" /></a></p> <p><a href="https://i.stack.imgur.com/0wMHR.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/0wMHR.jpg" alt="enter image description here" /></a></p> <p><a href="https://i.stack.imgur.com/il3D4.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/il3D4.jpg" alt="enter image description here" /></a></p> <p><strong>Edit #3! The CULPRIT!</strong> So as it turns out, I bought a new oscilloscope the other day and was misusing it, as well as my power supply is quite good and the circuit is significantly more stable on the power supply than the power brick. Scoped properly, and using the crappy power brick, enjoy the lovely waveforms:</p> <p><a href="https://i.stack.imgur.com/e5DhE.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/e5DhE.png" alt="enter image description here" /></a></p> <p>From about half hour of testing, I was able to measure:</p> <ul> <li>Up to 12V on the MCU pin (BLU)</li> <li>Up to 20V on the 12V line (YEL)</li> <li>Up to 10V on the 5V (PRP)</li> </ul> <p>Thanks everybody for the suggestions so far, we now empirical data regarding the problem. Thus far suggestions have been:</p> <ul> <li>Soft start with PWM rather than a boring RC circuit</li> <li>Twisted motor wire pairs</li> <li>Flyback diode as close to the motor as possible</li> <li>Extra (bulk?) capacitance on the 12V input.</li> <li>Zener to the gate/mcu pin to clamp it at 5V</li> <li>Lowpass filter before the Vreg (not a fan because of inline R)</li> </ul> <p>Other than getting to work, having fun, and testing for myself, which area should my focus be on? How important is soft start? Are there other standard boiler plate methods to involve?</p> <p><strong>Edit #4: It works?</strong></p> <p>3 simple changes were added to the circuit. I added a 0.1uF bypass cap on the 12 &amp; 5V lines, as well as a 150uF (the largest I had in the shop atm) on the 12V. The motor is switching happily away. I also spent a while probing with a far away GND vs a very close one and noticed the huge difference on the scope. With a far away GND, I saw voltages up to +12V on my GPIO, but with a close ground, that was reduced to +7V and less noisey. I also learned that most of the noise I was seeing was occurring 20ms after the switching event, and with my previous trigger options, I was completely missing it. With a good ground, I removed each component at a time testing along the way, hoping to see which part made the biggest difference. Nothing changed, and I got back down to the original circuit, and <em>now it's magically working with no issues</em>. Literally everything is exactly the same as yesterday when I posted this, out of desperation I even coiled the motor wires like in the photo I posted - still works. My only logical conclusion is that the motor when brand new was causing tons of noise due to new brushes, and now that it has been running for several minutes, the brushes wore in creating a better contact, less sparks, EMI etc. Am I crazy for thinking this? Either way, I'm completely pissed I didn't get see differences as I added in the capacitors.</p> <p>Thank you for al the comments! I learned a lot, and the most valuable takeaway had nothing to do with a motor or mosfet, it was my oscope and probe. Sorry for the terrible ending to this story.</p> <p>Cheers,</p>

Blowing up Arduinos with a MOSFET and motor

2024-02-13T15:48:28.910

701335

|charger|isolation|floating|shock|

<blockquote> <p>If I touch the output connector while standing on the ground (i am at earth potential), will I get a shock? I think yes, because the output voltage is floating and has an arbitrary voltage relative to earth? So if I touch it I can get shocked for a slight moment while the potentials are equalizing?</p> </blockquote> <p>You might think a relatively isolated output like that has a few tens of pF, or perhaps 100 or 200 pF to ground, which if charged would give you a brief tingle. It's worse than that, because for EMC reasons, switch mode PSUs like that tend to have a small capacitor (with up to possibly nF value) between the input and output side, to attenuate SMPS-induced electromagnetic emissions. So you will get a continuous tingle.</p> <blockquote> <p>Is this dangerous?</p> </blockquote> <p>It should not be. The device will likely be double-insulated. That aforementioned EMI capacitor should be Y-class, which is a fail-open device.</p> <p>However, were two things to go wrong in the PSU and the output to become live with a low impedance, then touching it would not be as safe as not touching it.</p> <blockquote> <p>Can you prevent this by connecting mains earth to ground on the secondary side? By doing so, I am introducing the risk of an earth loop and polluting the output voltage?</p> </blockquote> <p>This should be fine. The tingle current introduced by that EMI capacitor will now be shorted to mains earth ground. The output voltage should remain as good as you would expect a SMPS output to be, which can be fairly dirty in the case of a cheap USB charger supply.</p>

<p>A USB charger is usually galvanically isolated from mains for safety reasons.</p> <ol> <li><p>If I touch the output connector while standing on the ground (i am at earth potential), will I get a shock? I think yes, because the output voltage is floating and has an arbitrary voltage relative to earth? So if I touch it I can get shocked for a slight moment while the potentials are equalizing?</p> </li> <li><p>Is this dangerous?</p> </li> <li><p>Can you prevent this by connecting mains earth to ground on the secondary side? By doing so, I am introducing the risk of an earth loop and polluting the output voltage?</p> </li> </ol>

Floating output voltage in USB chargers?

2024-02-13T19:15:36.430

701336

|kirchhoffs-laws|basic|ohms-law|

<p>Your &quot;wrong&quot; equation <span class="math-container">\$120V = I_0\times 10\$</span> is wrong because:</p> <ul> <li><p>Ohm's law relates the current through a resistance R to the voltage across that <em>same</em> resistance R. Perhaps what you've done there is try to relate current through a resistor with voltage across a completely different element, the voltage source.</p> </li> <li><p>If this was an attempt at applying KVL, then it's incorrect. KVL is all about travelling around a loop of things with potential differences across them, &quot;accumulating&quot; any and all changes in potential that you encounter as you go. However, the loop must be complete, and you must end up back where you started. You always ending up at the same potential you started with, for a net change of zero volts. It's like walking in a big loop around town, wherein you may climb hills, and walk down steps, but when you get back to where you started, you must always end up at the same elevation as when you left.</p> </li> </ul> <p>I'll redraw the circuit with some extra annotations, to aid my explanations:</p> <p><img src="https://i.stack.imgur.com/TCpFy.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fTCpFy.png">simulate this circuit</a> &ndash; Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a>}</p> <p>If your equation <span class="math-container">\$120V = I_0\times 10\$</span> is an application Ohm's law, it's wrong because <span class="math-container">\$I_0\times 10\$</span> is the potential difference across resistor R1, <em>not</em> voltage source V1. The correct equation would be:</p> <p><span class="math-container">$$ V_{R1} = I_0 \times R_1 $$</span></p> <p>If that wasn't the mistake you made, then the equation must be an attempt at applying KVL, which you have misunderstood. Let me rewrite your incorrect equation, to put all non-zero terms on one side:</p> <p><span class="math-container">$$ \overbrace{120V}^{volts} - \overbrace{I_0 \cdot 10}^{volts} = \overbrace{0V}^{volts} $$</span></p> <p>That equation <em>seems</em> to be KVL, since all terms, both left and right of the &quot;=&quot;, have unit &quot;Volts&quot;. Indeed, all terms in such &quot;sums of terms&quot; must all have the same units anyway, because as you've been told a million times, you can't add or compare apples and oranges.</p> <p>However, it is stating that if you journey from node to node, starting at A, jumping over the source V1 to B, and then across resistance R1 to C, you will observe a <em>total</em> change of potential of 0V. That may (coincidentally) be true in some circumstances (it's not true here), but <em><strong>it's not KVL</strong></em>.</p> <p>For it to be KVL you must travel around a <em>complete loop</em>, arriving back where you started. You went from A to C, but to apply KVL you must go from A to A. From A, jumping over V1, you encounter a rise of 120V. Jumping over R1, you encounter a fall in potential, and finally, jumping across R2 you will encounter another fall. You're now back at A, for a total change of zero volts:</p> <p><span class="math-container">$$ +120V - V_{R1} - V_{R2} = 0V $$</span></p> <p>Of course, now you can substitute voltage terms with expressions resulting from Ohm's law:</p> <p><span class="math-container">$$ +120V - I_0R_1 - I_2R_2 = 0V $$</span></p> <p>That is the complete and correct application of KVL.</p> <p>As a final note, to help hammer the idea home, take a look at what happens if <span class="math-container">\$R_2 = 0\Omega\$</span>:</p> <p><span class="math-container">$$ \begin{aligned} +120V - I_0R_1 - I_2\times 0 &amp;= 0V \\ \\ +120V - I_0R_1 &amp;= 0V \\ \\ +120V &amp;= I_0R_1 \end{aligned} $$</span></p> <p>Now that's the erroneous equation you started with. This would be true if <span class="math-container">\$R_2 = 0\Omega\$</span>, or in other words, if R1 were connected directly in parallel with source V1.</p>

<p>I'm solving this circuit using Ohm's law and Kirchhoff's laws:</p> <p><a href="https://i.stack.imgur.com/Xlnv9.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/Xlnv9.png" alt="circuit diagram" /></a></p> <p>I solved the circuit correctly the second time.</p> <p>Equation A: <span class="math-container">$$I_1-I_0-6=0$$</span></p> <p>Equation B: <span class="math-container">$$-120\ \mathrm{V}+I_0\cdot 10+I_1\cdot 50 = 0$$</span> and when solved, the system of equations comes out to I₀ = -3 A and I₁ = 3 A.</p> <p>Once I understood the right way to solve the problem, the setup and math was fine to me. However, the first time I tried to solve the problem, I attempted: <span class="math-container">$$120\ \mathrm{V}=I_0\cdot 10$$</span> because using Ohm's law in this way made sense to me. Clearly though, its wrong, and I'm not sure what I'm misunderstanding when it comes to using these laws. My thinking is that Ohm's law directly applied wouldn't work because of the returning current of 6 A, and/or because of the current split at the first node. But I can't reconcile the second one in my head, since the split occurs after the circuit element and (in my understanding) wouldn't affect that resistor. What am I missing? How was I wrong?</p> <p>I want to apply these equations surely and correctly, knowing why, and not just because I know its what I should do. It's not the setup of the correct formula that eggs me, I'm just missing some very basic understanding of how circuits work.</p>

Confused about usage of Ohm's law & Kirchhoff's laws to solve a circuit

2024-02-13T19:16:50.097

701390

|i2c|esp32|

<p>The ADC is missing power supplies.</p> <p>You can fix the schematics and order new PCBs. Or fix the PCB with hobby knife and jumper wires.</p> <p>Or replace the incorrectly connected caps with short circuits for a quick fix.</p>

<p>I'm working on a design that uses a watchdog, temp humidity sensors, and an ADC, all on an I2C bus.</p> <p>We spent the day trying to debug why, after about 20 minutes, the I2C bus signals failed, and all the data became corrupted.</p> <p>We have tried changes to the pull-up resistors, 2.1 kΩ, 4.7 kΩ, and 10 kΩ, and checked the addresses. Yet each time we think we are making progress, after about 20 minutes, the readings go from good signals to a saw tooth wave. I've never seen anything like this before. A hardware reset doesn't fix the issue; only a full power cycle, and then it works again.</p> <p>Does anyone recommend what we can try next to find the root cause?</p> <p>Good data from I2C bus (with 10 kΩ pull-ups): <a href="https://i.stack.imgur.com/qproe.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/qproe.png" alt="Working 12c Bus with 10k Pull Ups" /></a></p> <p>Bad data after 20 minutes from the I2C bus: <a href="https://i.stack.imgur.com/DPcd9.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/DPcd9.png" alt="After 20 minutes saw tooth wave" /></a></p> <p>Close-up of working I2C bus waveforms (with 2.1 kΩ pull-ups): <a href="https://i.stack.imgur.com/ye7Kc.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/ye7Kc.png" alt="Close-up working waveform of the clock and the data races with 2.1 kΩ" /></a></p> <p>Bad data sawtooth closeup: <a href="https://i.stack.imgur.com/TU2Sp.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/TU2Sp.png" alt="Close-up of broken saw tooth waveform for data and clock" /></a></p> <p>I2C sensors schematic: <a href="https://i.stack.imgur.com/Em8TQ.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/Em8TQ.png" alt="I2C Sensors Schematic" /></a></p> <p>This is the sensors and how they are wired; everything works; we can read from the ADS, HDC, and Watchdog/RTC to get data and set values. Then, randomly, it crashes, and we have no idea why. We can't tell if it's something with the ESP32-S3 or the PCBA hardware.</p>

I2C issues with ESP32-S3 and 3 separate sensors

2024-02-14T06:51:40.070

701398

|operational-amplifier|simulation|stability|transimpedance-amplifier|tina|

<p>I haven't looked at the datasheet, but I wouldn't be surprised if the loop gain changes due a different common-mode input voltage. They will define how hard you drive the differential input stage (the overdrive voltage) and this can change the small signal parameters of your input stage, such as the transconductance.</p> <p>As far as I know there exists a &quot;Boyle&quot; macromodel for op-amps which typically includes an actual transistor input-stage, so changes in common-mode voltage can be reflected on the simulations.</p> <p>The input stage is a great contributor to all the open-loop voltage gain, as such, it also dominates the noise performance of the op-amp.</p> <p>The question is, does this variation in the low-frequency open-loop gain be tolerated by your design? Does a 20dB decrease of gain at those low frequencies important to you?</p> <p>EDIT: On a second thought, perhaps 20dB might be a bit too much of a variation for an op-amp. Maybe there's something not properly model. However, I think you should be able to account for this in your design.</p>

<p>I am working on a photodiode transimpedance amplifier based on an <a href="https://www.ti.com/lit/ds/symlink/opa2374.pdf" rel="nofollow noreferrer">OPA2374</a> and decided to simulate it in TINA TI.</p> <p>However, several unexpected issues arose.</p> <ol> <li>AOL and GBW product vary significantly with input common-mode voltage and supply voltage</li> <li>Degraded stability when photodiode generates a DC current</li> </ol> <p>Here I do a sweep of the input DC offset (so as to not saturate at the negative power supply) and plot the open loop gain of the op-amp.</p> <p>This is the schematic I used: <a href="https://i.stack.imgur.com/IviSD.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/IviSD.png" alt="enter image description here" /></a></p> <p>And these are the results: <a href="https://i.stack.imgur.com/U0CWy.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/U0CWy.jpg" alt="enter image description here" /></a></p> <p>Similar results are obtained when sweeping the negative voltage supply: <a href="https://i.stack.imgur.com/LEbXe.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/LEbXe.png" alt="enter image description here" /></a></p> <p>I must stress that all the ranges I swept through are well within the input common-mode range and supply voltage ranges for the OPA2374.</p> <p>Also, as a further sanity check, I redid the circuit with all the test fixtures and the same op-amp macromodel in LTspice. The results and behavior were identical.</p> <p>However, when changing just the op-amp to one already present in the LTspice device library, I could not observe any variation when doing sweeps of either DC offset or supply voltage.</p> <p>What's happening here? Is this a case of a misbehaving op-amp model or something else?</p>

Transimpedance amplifier: weird simulation results

2024-02-14T08:27:56.550

701400

|circuit-analysis|circuit-design|analog|filter|camera|

<p>Given the presence of the two 1000 ohm resistors (yellow boxes) in the supply feed (R29 and L4): -</p> <p><a href="https://i.stack.imgur.com/SRO0U.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/SRO0U.png" alt="enter image description here" /></a></p> <p>………I think it's fairly irrelevant having resistors in parallel with L10 and L2 but, they will reduce the Q of the inductors because you can <strong>transform</strong> a parallel RL to a series RL if you know the operating frequency at which they are to be used: -</p> <p><a href="https://i.stack.imgur.com/cb99F.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/cb99F.png" alt="enter image description here" /></a></p> <p>Image from <a href="https://www.emcourse.com/converting-parallel-rl-circuits-their-easier-work-series-equivalents.html" rel="nofollow noreferrer">here</a>.</p> <p>And, once you have the equivalent series circuit, it's easy to see how Q is reduced. Fairly irrelevant for your interface but, nevertheless, that is by-the-by.</p>

<p>The below image is taken from <a href="https://www.ti.com/lit/ug/snlu135b/snlu135b.pdf" rel="nofollow noreferrer">DS90UB913A-CXEVM Serializer Board Schematic</a>. T he complete schematic is on page 21. The PoC network is enclosed in an orange box. You can see that two resistors (R28,R71) are connected in parallel with inductors. They are used to lower the Q.</p> <p>I have some questions regarding this circuit.</p> <ol> <li>How do R28 and R71 reduce the Q?</li> <li>How should I design the PoC network?</li> <li>Do we need 50 Ohm connectors for DOUT0+ and DOUT0-</li> </ol> <p><a href="https://i.stack.imgur.com/BCmCH.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/BCmCH.png" alt="enter image description here" /></a></p>

Power over coax circuit clarification needed

2024-02-14T08:33:15.417

701409

|identification|sot23|

<p>This is a <a href="https://assets.nexperia.com/documents/data-sheet/PBSS4240DPN.pdf" rel="nofollow noreferrer">PBSS4240DPN</a> (SOT457 in reality) from NXP/Nexperia. Marking code &quot;M3&quot;.</p> <p>36 is the datecode, t is the assembly location code.</p> <p><a href="https://jlcpcb.com/partdetail/Nexperia-PBSS4240DPN115/C503568" rel="nofollow noreferrer">picture from LCSC</a> <a href="https://i.stack.imgur.com/JnTfn.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/JnTfn.jpg" alt="picture from LCSC" /></a></p>

<p>Help me identify the component on the board labeled <strong>M3 36 t</strong> .</p> <p>I have a Siemens KTP600 HMI under repair (reason: it does not turn on). I found that an element was missing on the board (highlighted in a red circle). After inspecting the working board of the same HMI, I found out that there should be an element marked 'M3 36 t' (highlighted in a yellow circle). But I couldn't find this element by marking.</p> <p><a href="https://i.stack.imgur.com/f6PUZ.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/f6PUZ.jpg" alt="enter image description here" /></a></p> <p>Marking: <strong>M3 36 t</strong><br /> Case: <strong>SOT-23-6</strong> or <strong>TSOT-23-6</strong></p> <p><a href="https://i.stack.imgur.com/p9uGJ.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/p9uGJ.jpg" alt="enter image description here" /></a></p>

What is this component? Marked 'M3 36 t' (Case: SOT-23-6)

2024-02-14T09:24:47.170

701427

|fpga|verilog|simulation|xilinx|vivado|

<p>You should connect the <code>inout</code> ports to signals declared as <code>wire</code>, then drive the wires from the signals declared as <code>reg</code>. Here is a self-contained example:</p> <pre><code>module design_1_wrapper (inout FIXED_IO_ps_clk, FIXED_IO_ps_porb); endmodule module tb; reg tb_clk, tb_reset; wire io_clk = tb_clk; wire io_reset = tb_reset; design_1_wrapper design_1_i ( .FIXED_IO_ps_clk (io_clk), .FIXED_IO_ps_porb(io_reset) ); always #5 tb_clk = ~tb_clk; initial begin tb_clk = 0; tb_reset = 0; #40; tb_reset = 1; #500 $finish; end endmodule </code></pre> <p>When a design has an <code>inout</code> port, the testbench typically will have one <code>reg</code> and one <code>wire</code> for that port.</p>

<p>I’m following a guide (Here is the link to the guide: <a href="https://www.hackster.io/whitney-knitter/dsp-for-fpga-using-xilinx-dds-with-custom-fir-f82447" rel="nofollow noreferrer">https://www.hackster.io/whitney-knitter/dsp-for-fpga-using-xilinx-dds-with-custom-fir-f82447</a>) for implementing a custom FIR filter in Vivado and encountered a discrepancy between my approach and the guide, particularly regarding signal types and simulation initiation. The guide doesn't appear to use inout signals or wire types in the testbench, which contrasts with my current setup where Vivado generated a wrapper (design_1_wrapper) with inout ports, necessitating wire types for connection.</p> <p>Goal: Understand how to initiate simulation for a custom FIR filter design accurately, mirroring the guide's approach without explicitly using inout signals in the testbench.</p> <p>Issue: My simulation setup involves inout ports, leading to complications not evident in the guide. Specifically, the guide's testbench directly uses reg types for clock and reset signals:</p> <pre><code>fir_design fir_design_i( .clk(clk), .reset(reset) ); </code></pre> <p>However, in my wrapper (design_1_wrapper), generated by Vivado, I find only inout ports, which has led me to use wire types due to Vivado's inout signal requirements with strange names like FIXED_IO_ps_clk, FIXED_IO_ps_porb did she just rename those? :</p> <pre><code>design_1_wrapper design_1_i( .FIXED_IO_ps_clk(tb_clk), .FIXED_IO_ps_porb(tb_reset) ); </code></pre> <p>This adjustment has introduced errors and confusion about the correct simulation setup.</p> <p>Questions:</p> <p>How does the guide initiate simulation without addressing inout signals, and how can I replicate this in my setup? Could the issue stem from my selection of the top module or the way I've generated the wrapper? How should the top module or wrapper be configured to avoid complications with inout signals for simulation (if that was the problem)?</p> <p>Attempts &amp; Issues:</p> <p>I've closely followed the guide for implementing a custom FIR filter in Vivado. However, my simulation doesn't start as expected due to inout ports in the auto-generated wrapper, which contrasts with the guide's direct use of reg types for clock and reset. Following toolic's advice, I tried connecting inout ports to wire types, driven by reg signals, but encountered errors: [VRFC 10-426] cannot find port reset on this module [VRFC 10-2063] Module &lt;design_1&gt; not found... I'm puzzled by how the guide initiates simulation without these inout issues. Could my problem be related to the top module selection or wrapper generation? Insights or clarifications on aligning my setup with the guide would be invaluable.</p> <p>Understanding the guide's methodology for simulation initiation and how it avoids complexities with inout signals would greatly assist me in progressing with my project. Any insights or clarifications would be immensely appreciated.</p> <p>update: Thank you for the guidance, @toolic. Based on your advice, I've updated my original question with a simplified version of my issue to make it more clear and self-contained. I hope this helps in providing any further insights you might have.</p>

How to Start Simulation (in specific turtorial) in Vivado with Custom FIR Using Xilinx DDS?

2024-02-14T13:47:20.977

701433

|switch-mode-power-supply|efficiency|gan|

<p>GaN HEMT heterojunction JFETs have an attractive FOM of die size (and thus gate charge) to breakdown voltage for a given Rds(on) so they are good for high voltage at high frequency.</p> <p>FETs have a <em>die area</em> that roughly scales with breakdown voltage <em>squared</em> for a given Rds(on). The wide bandgap semiconductors have a higher critical field Ec, however. So the advantage over Si MOSFETs is pronounced at high voltages, and can make up for the other disadvantages in some applications.</p> <p>They are majority carrier devices so don't have reverse recovery losses, however reverse conduction voltage (and thus conduction losses in reverse) will be relatively high.</p> <p>They are also expensive compared to silicon devices (generally built on a silicon substrate plus GaN/AlGaN layers).</p> <p>So high voltage and high frequency at moderate power levels are their niche.</p>

<p>Is it possible to achieve a better efficiency with GaN rather than Si at low voltage (&lt;~ 20V)</p> <p>I mean GaN is known for having low parasitic capacitors and so it allows to have low switching losses. But at low voltage, the switching losses are not so important compared to higher voltage (&gt; 100V). The Rds(on) of GaN is better than Si but not so much and so the conduction losses are almost the same. So is it really relevant to use GaN at low voltage?</p> <p>I added one Si <a href="https://www.infineon.com/dgdl/Infineon-BSZ034N04LS-DataSheet-v02_03-EN.pdf?fileId=db3a304342371bb001424c3fe5bc7083" rel="nofollow noreferrer">MOSFET</a> and a GaN <a href="https://epc-co.com/epc/Portals/0/epc/documents/datasheets/EPC2055_datasheet.pdf" rel="nofollow noreferrer">HEMT</a> for making the comparaison easier. They seems to be comparable.</p> <p>GaN is obviously better than Si but the question is how many points of efficiency you will obtain for a low voltage application.</p>

GaN @ low voltage

2024-02-14T15:41:18.170

701437

|layout|thermal|heatsink|via|pad|

<p>Common, I don't think I would say so. &quot;Viable&quot;, yes.</p> <p>QFNs tend to have reasonable thermal performance through the top (packaging plastic is a pretty mediocre thermal conductor, but it's thin), so you see gap pads on top of them, from time to time.</p> <p>Bottom is less common I would say, in part because once the heat is into the board, it spreads out reasonably effectively into the inner layers. First, if inner-top is GND, the plane spreads out heat by direct conduction; in combination with the bottom pour (if applicable; it doesn't need to be an &quot;identical pad&quot;, it can be any random solder-masked polygon, or left off entirely if not required), the inner-bottom layer (usually VCC plane) is sandwiched, so has excellent thermal conductivity as well; or perhaps you're using a sig-GND-GND-sig stackup instead and both planes are directly connected. And needless to say, multi<em>ier</em>-layer boards are even more conductive, regardless of plane assignment.</p> <p>Thus, the board itself is an effective heatsink, and I would not at all mind running a device such as pictured, up to several watts, in an otherwise very ordinary build (normal commercial sort of product, no stringent limits on ambient or device temperature, single board much larger than the chip, still air or minor ventilation).</p> <p>A very compact design, or with tighter temperature specs (say an ambient up to 60°C with a chip limit of 85°C), or higher power levels (5, 10W might be the practical limit here), would benefit from thermal pads top and bottom. Such a heatsinking solution will be more onerous, as you most likely can't simply place elements at will, but must integrate them into the design. Pretty quickly beyond here, one would run into package limits, and a device with exposed metal/die surface would be required, with a greased joint or high-K gap pad to heatsink/heat pipe. Such packages are common in computing: advanced integrated regulators, CPUs/GPUs, etc. Heat sunk through the board again becomes less important then; so, it's kind of a narrow range (of ratings or products) where this approach would be preferable.</p>

<p>If a VQFN package (below) has a thermal pad and thermal vias beneath it, the bottom layer should have an identical pad to act as a heat sink.</p> <p>Is it typical to surface mount a heatsink on the bottom-side thermal pad, over the thermal vias, (assumably using plugged and capped vias)?</p> <p><a href="https://i.stack.imgur.com/CsZNe.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/CsZNe.png" alt="enter image description here" /></a></p> <p>Linked question: <a href="https://electronics.stackexchange.com/questions/701436/ic-thermal-pad-duplicate-zone-in-inner-layers-also">IC thermal pad: Duplicate zone in inner layers also?</a></p>

IC thermal pad: Place heat sink directly over bottom-side thermal pad and thermal vias

2024-02-14T15:54:08.777

701445

|operational-amplifier|oscillator|square|

<p>I tried your circuit in the CircuitLab simulator and it basically works.</p> <p>Because the typical NPN transistor allows only a reverse Vbe of around -5 V I changed the supply configuration. The H-bridge should run with 10 V, so I created a split supply of +/- 5 V to feed it and use the same supply for the OpAmps.</p> <p>With this modification the output voltages of OA1 (DRV_1) and OA3 (DRV_2) cannot go below -5 V and so Vbe stays within useful limits.</p> <p>I removed the diode at the output of OA2 because this would affect correct current measurements through R8.</p> <p>There was an excessive inductive kickback voltage and to catch this I added D1-D4.</p> <p>There are short periods during takeover where Q2 and Q4 are both conducting, but this is not dramatic.</p> <p>This is not a good solution but shows, that the general idea of your circuit is OK. Using PNP transistors at the high side could improve the symmetry and takeover.</p> <p><img src="https://i.stack.imgur.com/MbcS8.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fMbcS8.png">simulate this circuit</a> &ndash; Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a>}</p> <p><strong>Added</strong></p> <p>This approach uses PNP transistors at the low side (Q2 and Q4). This avoids the issue with large negative Vbe for higher supply voltages and produces less critical takeover because a shoot through is not possible.</p> <p>The split supply must use equal voltages because the trigger level of OA1 depends on this symmetry. If V1 and V2 would be different, the threshold voltages at IN+ would be different as well.</p> <p>I added a little imbalance with R16, R17 and R18 to help the oscillation startup. A real world circuit would not need this because real OpAmps always have some offset voltages.</p> <p><img src="https://i.stack.imgur.com/5NC7u.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2f5NC7u.png">simulate this circuit</a>}</p>

<p>I am trying to make a self oscillating fluxgate transformer using an LR oscillator with an op-amp. I replaced the op amp with a square wave generator and the h bridge worked fine but when using op amp it doesn't work.</p> <p>Circuit schematic:</p> <p><a href="https://i.stack.imgur.com/gNc5Q.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/gNc5Q.png" alt="enter image description here" /></a></p> <p>Transient response:</p> <p><a href="https://i.stack.imgur.com/SCV2o.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/SCV2o.png" alt="the " /></a></p> <p>Vno14 is output of U2 and Vn007 is at the non-inverting terminal of U2.</p> <p>I am using the H-bridge configuration as the op-amp can't output a high current. I initially designed the transistor bases for measuring a current of 0.5 A. I found this type of current clamp meter has good accuracy, but there's only one research paper I found on the internet and I can't access it.</p> <p>Functional parts are:</p> <p>LR type oscillator,H-bridge with op-amp, non-inverting op-amp with unity gain for current sense resistor R8.</p> <p>Why isnt the output of U2 oscillating? What am I doing wrong?</p> <p>I am expecting a sawtooth waveform with peaks of +- 0.5A in l1 showing charging and discharging of inductor. When I replaced the opamp u2 with just a square wave generator and ran the h bridge worked fine but on connecting the opamp it didn't oscillate.</p>

Problem with LR oscillator

2024-02-14T16:48:32.503

701449

|analog|integrated-circuit|current-source|dac|

<p>Switching off capacitor-charging current by opening the current mirror leg is not a good solution, considering that the CM frequency response might be poor and you might want the charging current to be precise at any moment of time. So, you better use current steering to have a copy of charging current from your current mirror and then control your charging current from outside your precise current mirror (Iload is a network with Vcap; while switching off charging, you can also disconnect the M3/M5 gates).</p> <p><a href="https://i.stack.imgur.com/EacnK.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/EacnK.png" alt="basic current steering circuit" /></a></p> <p>As for current mirror designs aimed at achieving a large IREF range, enhanced output impedance, and high output swing, the recommendation may depend on your project goals and technology used. General ideas are like this: use cascode architecture to increase the output impedance or maybe introduce source degeneration via ohmic MOS transistors.</p> <p>An idiomatic low-voltage cascode current mirror solution looks like this:</p> <p><a href="https://i.stack.imgur.com/syBER.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/syBER.png" alt="wide swing current mirror" /></a></p> <p>Biasing the CM with Ibias minimizes the systematic error of current copying; the closer Vbias to the M5 drain voltage, the more accurate is the equality of Iref and Iload, but the exact equality Vbias = V(M5d) disables the cascode, and it is the designer job to find optimum.</p>

<p>I'm trying to design a current source to charge a capacitor (10pF) in the context of IC, with quite a small voltage headroom (1.5V). I started with the basic current mirror, as shown below. M3 acts like a switch, controlling when to start/stop charging.</p> <p>This works fine when the voltage on the capacitor (call it Vcap) is not too high, because as Vcap rises, Vsd of M2 decrease, and M2 gradually enters triode region, sourcing less current than IREF.</p> <p>Now I'd like to make IREF adjustable. Ideally to adjust it from 1uA to 10uA (quite a large range). I tried by directly changing the value of IREF, but the error becomes very large.</p> <p>I'm wondering if there are any methods for designing a current source/current mirror/DAC that can achieve this output dynamic range (and have a large output impedance at the same time)?</p> <p><a href="https://i.stack.imgur.com/VGwlmm.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/VGwlmm.png" alt="enter image description here" /></a></p>

How to increase the output range of a current source?

2024-02-14T17:40:21.947

701457

|ac|short-circuit|emi-filtering|gfci|

<p>Your DC resistance meter is not seeing the same impedance as the AC supply the capacitors are allowing some AC leakage to ground which is tripping the GFCI.</p> <p>As Tim has so eloquently explained the capacitors are there for noise reduction. Helping to reduce noise transmitted to the printer and to the mains supply from the printer.</p> <p>Try connecting the printer without the capacitors. If you do not notice any effects due to noise on other equipment in the house or the printer leave them out.</p>

<p>I'm trying to repair a very old printer (circa 1980). When I plugged it in, the GFCI outlet protection immediately tripped, even with the printer turned off.</p> <p>The hot side of the cord is connected to the on/off switch (and is wired correctly), so the only failure path seems to be the 0.1uF X capacitor connected from hot-to-ground before the switch (note that it's an X, not a Y capacitor here). The configuration seems odd to me, because there is <em>another</em> X capacitor, same value, connecting neutral-to-ground. Setup looks like this. It's an AC linear power supply circuit, and not much else is going on on the primary side of the transformer:</p> <p><a href="https://i.stack.imgur.com/MDkqd.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/MDkqd.jpg" alt="enter image description here" /></a></p> <p>I assumed age failure in the safety cap(s), so I first disconnected the first one (hot to ground) and powered on the device and didn't trip the GFCI, and appeared to switch on correctly.</p> <p>So I replaced both the X caps with new X2 caps at 0.1uF, but the hell of it is, the original problem came back: immediate GFCI fault on plugging it in. The cord itself is fine, and an ohmmeter finds expected open circuit between all the relevant terminals (i.e., there's no obvious dead short between hot and neutral or hot and ground).</p> <p>I am not looking for specific help debugging my printer per se-- I suppose it could be various things. (Though if the pattern of behavior here seems immediately suggestive to someone I'd love to hear that too.)</p> <p>But I would like to understand what the arrangement of two X caps from each side of the AC to ground is intending to do? I haven't seen that before and I'm having trouble reasoning about it. I'm hoping that comprehend what I'm looking at will help me troubleshoot smartly.</p>

Two X capacitors from lines to ground- why? GFCI fault, even after replacement

2024-02-14T19:26:28.717

701464

|accelerometer|nucleo|

<p>Well it seems that the project that I am using is not very flexible and is created for 4G scale only. I managed to trace where the value is being read and found this :</p> <pre><code>acc_out-&gt;x = (float)data.data.acc_x * 0.122f / 1000.0f; acc_out-&gt;y = (float)data.data.acc_y * 0.122f / 1000.0f; acc_out-&gt;z = (float)data.data.acc_z * 0.122f / 1000.0f; </code></pre> <p>After some investigation on datasheet I came along with this table: <a href="https://i.stack.imgur.com/ryeoa.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/ryeoa.png" alt="enter image description here" /></a></p> <p>Then after some reverse calculations I can now say that this was the problem. Since my sensor is using 16 bit for data output, max number is 65536 for selected scale (let's use +/-2G for this explanation), since sensor output is signed number, we get 65536 / 2 = 3278 to represent +2 G, other half is for negative values. Since Earth gravitational force is 1G, I should read 32768 / 2 = 16384 value (32768 is 2G, then 1G is calculated this way), then multiplying it by 0.061 (from the table) and dividing by 1000 gives me: 16384 * 0.061 / 1000 = 0.999 G. Since I changed the Scale and left sensitivity value the same, I got wrongly parsed data.</p>

<p>I am using X-NUCLEO-IKS01A3 Shield for my NUCLEO-F401RE platform.</p> <p>I want to get accelerometer readings so I am using LSM6DSO IMU sensor for that. I tried creating some functions to easily control Scale and ODR parameters, but I spotted quite odd behavior of this sensor.</p> <p>When I am setting scale to +/- 2G I get a reading of 2 on Z axis, when I set Scale to +/- 4G, I get reading of 1, when I set it to +/- 8 G, I get 0.5. Why is that?</p> <p>Shouldn't I get 1 on all scales on Z axis ? It is earth gravitational force, which is 1 G, so why am I getting scaled readings?</p> <p>As I understand, smaller scale factor let's me get more precise data, larger scale parameter makes it less sensitive, but extends the range.</p>

Accelerometer Scale parameter

2024-02-14T20:13:04.420

701466

|dc-dc-converter|buck|

<p>Just to illustrate the Tim Williams comment. Below is an example from TI part with embedded inductor. Please note the number and spectrum of capacitors on input and output: <a href="https://i.stack.imgur.com/0a9t9.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/0a9t9.png" alt="enter image description here" /></a> You should practice something similar.</p>

<p>Relevant TI forum post with no resolution: <a href="https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/794597/lm5088-clicking-noise-when-power-is-applied-to-the-dc-dc-converter" rel="nofollow noreferrer">here</a>.</p> <p>I am using an <a href="https://aosmd.com/sites/default/files/res/datasheets/AOZ2264NQI-11.pdf" rel="nofollow noreferrer">AOZ2264NQI-11</a> chip to convert 24 V down to 12 V. I originally designed this circuit for use with an <a href="https://aosmd.com/sites/default/files/res/datasheets/AOZ2261NQI-12.pdf" rel="nofollow noreferrer">AOZ2261NQI-12</a> chip, which has an identical footprint/pinout and a mostly identical application circuit (for more info read my <a href="https://electronics.stackexchange.com/questions/699883/buck-regulators-feedback-voltage-far-lower-than-expected">previous question</a>). I switched to the new chip to get the higher current output capability, 15 A vs 8 A.</p> <p>The problem I am seeing - or rather, hearing - is that once the load reaches ~2.5-3 A, the circuit begins to make an audible clicking noise. The noise is relatively loud and occurs roughly every 1.2 seconds, although it becomes more frequent as a higher load is applied. By the time the load hits ~8 A, the noise is frequent enough to be more of a hum. I haven't captured that behavior yet so I couldn't give a frequency but I am working on it.</p> <p>When I first tested these PCBs with the lower-current chip, I also experienced the clicking but much less often. It would sometimes occur at a load of between 5.5-6 A, with roughly the same frequency.</p> <p>I am including the schematic, layout, and captures of relevant voltages when clicking: V_IN, V_LX, V_OUT, and V_PROJ, which is just the load voltage and differs from V_OUT because there is a 0.03 Ω current sensing resistor in line with the load. Note: I am using a 100 kΩ resistor for R_OCS, not the 20 kΩ value in the EDA snips.</p> <p><a href="https://i.stack.imgur.com/m5pBU.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/m5pBU.png" alt="Schematic" /></a></p> <p><a href="https://i.stack.imgur.com/ZXc6x.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/ZXc6x.png" alt="Layout" /></a></p> <p><a href="https://i.stack.imgur.com/wsxzi.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/wsxzi.jpg" alt="Clicking Zoomed Out" /></a></p> <p><a href="https://i.stack.imgur.com/ZMXmT.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/ZMXmT.jpg" alt="Clicking Start" /></a></p> <p><a href="https://i.stack.imgur.com/TdAx6.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/TdAx6.jpg" alt="Output Resuming" /></a></p> <p>My next step is to examine the EN, PGOOD, and BST lines, and try to capture the clicking frequency at higher loads. I suppose I have two main questions:</p> <ol> <li>What buck regulator shutdown behavior causes an audible clicking? I don't believe it is thermal shutdown, using an IR gun the chip package sits at around 33°C even at higher loads.</li> <li>Why would the higher-current chip have this behavior at a lower load than the other chip? Apart from the R_OCS value, the passive calculations are identical.</li> </ol>

DC/DC buck regulator regularly emits an audible clicking noise

2024-02-14T20:37:12.937

701470

|radar|

<p>You’re right. We don’t need super high frequencies, it just is cheapest that way. With lower frequencies you need bigger antennas, very low noise (potentially cryogenically cooled) preamplifiers to get enough sensitivity to detect the very weak signal, and/or high transmitter output (needs licensing or an anechoic chamber), and so on.</p> <p>If you had a little X-band transmitter somewhere near the NRAO dish and shot a bullet away from the transmitter, they’d have no trouble plotting the Doppler shift for you. The hourly operating cost for that place is a wee high for personal budgets though :)</p>

<p>I'm trying to build a DIY tool to measure the speed of something moving very fast in a straight line, e.g. a bullet exiting the barrel of a rifle, based on the Doppler effect.</p> <p>I've looked for several Doppler radar modules online, but most of them state a maximum speed detection of 150-350 mph (that is ~67 to ~156 m/s), which is way under your typical rifle bullet moving at 700-1000 m/s.</p> <p>Commercial products built specifically for that purpose (measuring the speed of a bullet) state a frequency of ~120 GHz. I'd like to understand why such a high frequency is needed.</p> <p>I can understand why a &quot;too low&quot; frequency, let's say 100 Hz, would be an issue:</p> <ul> <li>The bullet is moving at 1000 m/s</li> <li>To detect the waves bouncing back, the bullet must not be too far from the radar, let's say 1 m at most</li> <li>So if the frequency is 100 Hz, we'll probably miss the bullet because in 0.01s (1 / 100 Hz) the bullet could already be 10 m away (1000 * 0.01 / 1), exceeding our given 1 m detection range.</li> </ul> <p>However, with the same reasoning, a few KHz would be more than enough to measure the speed of the bullet.</p> <p>Why, in reality, do we need much higher frequencies such as 120 GHz to measure the speed of a bullet? Is there a formula to calculate the required frequency?</p>

How to determine the Doppler radar frequency required to measure an object moving at a given speed

2024-02-14T21:38:27.987

701478

|mains|charging|homework|

<p>To add to @russellMcMahon's answer, one major problem with putting loads in series vs. in parallel is that in series, the voltage is split between them, proportionally to their resistance. So if you put a 50 watt incandescent light in series with a 25 watt one (which is twice the resistance), the 50 watt bulb would get 1/3 of the mains voltage (80 volts) and the 25 watt bulb would get 2/3 (160 volts).</p> <p>Clearly, neither bulb is getting 240 volts and worse, each is getting a different voltage.</p>

<p>I'd like to understand if charging multiple devices using the 240 V line's main power plugs forms a series or parallel circuit.</p>

Charging a mobile phone and laptop using wall plug - Series or parallel circuit?

2024-02-14T22:22:20.043

701498

|transistors|mosfet|maximum-ratings|

<p>As the datasheet says +/-30V between gate and source, absolute maximum. 4V to 5V is perfectly fine. As is +/-10V.</p> <p>However it's a bit <em>low</em> to be guaranteed to switch 200mA. The part is specified with 4.5V at only 75mA. You should use guaranteed characteristics, not 'typical'.</p> <p>Unless you need low gate charge for some reason, it would probably be better to use a higher performance logic-level MOSFET (most are SMT in packages like SOT23), such as the <a href="https://aosmd.com/sites/default/files/res/datasheets/AO3400.pdf" rel="noreferrer">AO3400</a>, which has an on resistance of only 0.033Ω maximum with 4.5V in and switching 5A vs. 5.3Ω at 75mA. At 200mA the voltage drop of a 2N7000 could be greater than 1V, causing the part to get hot and further increasing the resistance.</p> <p>In any case use a pull-down on the gate. 10k to 100kΩ is fine.</p>

<p><a href="https://ww1.microchip.com/downloads/en/devicedoc/2n7000-n-channel-enhancement-mode-vertical-dmos-fet-data-sheet-20005695a.pdf" rel="nofollow noreferrer">Here is the datasheet of the 2N7000 transistor</a>. I need to use it in a circuit where an Arduino will provide the gate terminal with 4.7-5 V and the transistor needs to withstand 200 mA current.</p> <p>It seems the transistor will withstand the current, but can it tolerate the gate voltage?</p>

Can a 2N7000 transistor withstand 4.7-5 V gate voltage?

2024-02-15T03:51:38.703

701512

|led-driver|

<p>The datasheet doesn't seem to do much to help the designer does, it? The way these guys use just two pins to set LED current and provide a convenient voltage reference is clever, and flexible, but you have to decide how to exploit that yourself. You have a few approaches to choose from.</p> <h3>Do what they do on page 8</h3> <p>This is the same schematic as the one on page 8 of the datasheet, redrawn and annotated to make it easier to explain:</p> <p><img src="https://i.stack.imgur.com/B2dNY.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fB2dNY.png">simulate this circuit</a> &ndash; Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a>}</p> <p>Here they ground the low-potential side of the voltage reference (REFADJ), so that the high-potential end (REFOUT) is fixed at +1.25V.</p> <p>That places fixed potentials of +1.25V and 0V at the two ends of the internal resistor divider (with a total resistance of 10kΩ), which will become the threshold levels at which LEDs will illuminate. If R2 were absent, the divider alone would draw:</p> <p><span class="math-container">$$ I_{REF} = I_{DIV} = \frac{1.25V}{10k\Omega} = 125\mu A $$</span></p> <p>If R2 is present, then total reference current becomes:</p> <p><span class="math-container">$$ \begin{aligned} I_{REF} &amp;= I_{DIV} + I_2 \\ \\ &amp;= 125\mu A + \frac{1.25V}{R_2} \\ \\ \end{aligned} $$</span></p> <p>We are told that LED current (in each individual LED, not total current) <span class="math-container">\$I_{LED}\$</span> is:</p> <p><span class="math-container">$$ I_{LED} = 10 \times I_{REF} $$</span></p> <p>In this configuration, therefore, you can't have less than 1.25mA in each LED, but you can have more, by including R2.</p> <h3>Do what they do on page 9</h3> <p>On page 9, the voltage across R1 is always 1.25V, and so it's trivial to control the current through R1:</p> <p><img src="https://i.stack.imgur.com/1j7zr.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2f1j7zr.png">simulate this circuit</a>}</p> <p>By Ohm's law:</p> <p><span class="math-container">$$ I_{REF} = I_{R1} = \frac{V_{R1}}{R_1} = \frac{1.25V}{R_1} $$</span></p> <p>The above relationship will be true regardless of what you connect to <span class="math-container">\$V_{OUT}\$</span> (within reason), and so R1 is so <em>sole arbiter</em> of that current. Again, LED current is ten times that:</p> <p><span class="math-container">$$ \begin{aligned} I_{LED} &amp;= 10 \times I_{REF} \\ \\ &amp;= 10 \times \frac{1.25V}{R_1} \\ \\ &amp;= \frac{12.5V}{R_1} \\ \\ R_1 &amp;= \frac{12.5V}{I_{LED}} \end{aligned} $$</span></p> <p>So, for example, if you require each LED (when lit) to pass <span class="math-container">\$I_{LED} = 5m A\$</span>, then:</p> <p><span class="math-container">$$ R_1 = \frac{12.5V}{5mA} = 2.5k\Omega $$</span></p> <p>It's still necessary to know <span class="math-container">\$I_{REF}\$</span>, for later:</p> <p><span class="math-container">$$ I_{REF} = \frac{1.25V}{2.5k\Omega} = 500\mu A $$</span></p> <p>We will also need <span class="math-container">\$I_{ADJ}\$</span>, which is found in the datasheet:</p> <p><span class="math-container">$$ I_{ADJ} = 75\mu A $$</span></p> <p>We are obliged to install R2, to sink both currents <span class="math-container">\$I_{REF}\$</span> and <span class="math-container">\$I_{ADJ}\$</span>. Since <span class="math-container">\$I_{REF}\$</span> and <span class="math-container">\$I_{ADJ}\$</span> are both constant, whatever resistance R2 that you use will conveniently develop a steady &quot;reference&quot; potential <span class="math-container">\$V_{OUT}\$</span>.</p> <p>In my circuit above I've taken advantage of this, by using the IC's own internal resistor divider as R2. In other words, R2 is 10kΩ here. Consequently, the two currents <span class="math-container">\$I_{REF}\$</span> and <span class="math-container">\$I_{ADJ}\$</span> both pass through it, and <span class="math-container">\$V_{OUT}\$</span> becomes:</p> <p><span class="math-container">$$ V_{OUT} = (I_{REF} + I_{ADJ}) \times 10k\Omega = 5.75V $$</span></p> <h3>Do your own thing</h3> <p>Let's say you want 1mA LED current. That poses some problems for connecting the internal divider as R2, because that divider's resistance is prohibitively small, at 10kΩ.</p> <p>Nothing's stopping you from deriving your own low-impedance sources of top and bottom potentials for that divider, but you'll need to get creative. One way might be as follows (that's a bad pun, you'll get it in a moment):</p> <p><img src="https://i.stack.imgur.com/JrR2n.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fJrR2n.png">simulate this circuit</a>}</p> <p>Firstly, find R1:</p> <p><span class="math-container">$$ R_1 = \frac{12.5V}{I_{LED}} = \frac{12.5V}{1mA} = 12.5k\Omega $$</span></p> <p>This will set <span class="math-container">\$I_{REF}\$</span> to one-tenth of LED current:</p> <p><span class="math-container">$$ I_{REF} = \frac{1.25V}{12.5k\Omega} = 100\mu A $$</span></p> <p>I've chosen for the sum R2 + R3 to equal 28.6kΩ. By Ohm's law that makes <span class="math-container">\$V_Y\$</span>:</p> <p><span class="math-container">$$ V_Y = (I_{REF} + I_{ADJ}) \times 28.6k\Omega = +5.0V $$</span></p> <p>I'm still taking advantage of the internal reference to obtain this, avoiding the need for a separate reference IC. Then I divide that potential even further, using R2 and R3 to obtain +1V:</p> <p><span class="math-container">$$ V_X = V_Y\frac{5.8k\Omega}{5.8k\Omega+22.8k\Omega} = +1V $$</span></p> <p>You can see why it might be difficult to employ the IC's internal 10kΩ chain in the place of R2 and/or R3 here, since its developed voltage would be too small. Also, I can't simply connect that internal divider directly to Y and X, so I use a couple of voltage followers to buffer those potentials, and take responsibility for divider current.</p> <p>Now I have an LM3914 that will illuminate LEDs with 1mA each, in response to some input potential between +1V and +5V.</p>

<p>I would like to try out the <a href="https://www.ti.com/lit/ds/symlink/lm3914.pdf?ts=1707915876350&amp;ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252Fde-de%252FLM3914" rel="nofollow noreferrer">LM3914</a>, but I could use some help in understanding how to calculate the current limiting resistor.</p> <p>I am referring to page 9 of the datasheet:</p> <p>Do I need to modify the reference output voltage with a voltage divider in order to limit the current or I can just use one resistor to ground at pin7?</p> <p>Also on page 2 it says Iled=12.5/R1. Shouldn't it be R1+R2? Where does 12.5 come from?</p> <p>On top of all that: a current ~10 times higher will be drawn by each lighted LED, and current drawn by the internal 10-resistor divider, as well as by the external current and voltage-setting divider should be included in calculating LED drive current.</p> <p>I found it a bit confusing. I need a good and understandable explanation.</p>

LM3914 Bar/Dot display driver

2024-02-15T06:50:46.850

701527

|microcontroller|transistors|stm32|gpio|

<p>To &quot;is my schematic correct&quot;...</p> <p>The below circuit is wrong. First, Q1 will try short out the rail when PB5 is driven HIGH. Second, Q1's base is a diode to GND so Q1 will try to clamp PB5 to 0.6..0.8 V when PB5 is driving HIGH and this may well damage Q1 and the MCU.</p> <p><a href="https://i.stack.imgur.com/Dcxsim.png" rel="noreferrer"><img src="https://i.stack.imgur.com/Dcxsim.png" alt="enter image description here" /></a></p> <p>Instead, use the following circuit. I imagine you wanted Q1 to switch a load and your schematic describes that load as an LED.</p> <p>R2 limits the current into the Q1 base when PB5 is driving HIGH. The current will be sufficient to switch Q1 on and sink around 2.9 mA through the LED and R3, assuming a 1.6 V LED drop and Q1 Vce(on) of 0.3 V.</p> <p>When the MCU is first powered on and/or reset, PB5 and the rest of its GPIO pins will configured as inputs. When inputs, the GPIO will output an 'input pin leakage current' which can be enough to switch on Q1. R1 is a pull down resistor that drains this current to GND and ensures Q1 is off. When the software has configured PB5 as an output and is driving the Q1 base HIGH or LOW, R1 is no longer needed so a high-value resistor is used that will draw little current from the HIGH PB5 voltage. Unless the circuit must be very power-efficient, this R1 current when PB5 is HIGH is negligible.</p> <p><img src="https://i.stack.imgur.com/NWk1xm.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fNWk1xm.png">simulate this circuit</a> &ndash; Schematic created using <a href="https://www.circuitlab.com/" rel="noreferrer">CircuitLab</a>}</p>

<p><a href="https://i.stack.imgur.com/Ts1iz.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/Ts1iz.png" alt="enter image description here" /></a></p> <p>Can I control any transistor (NPN/PNP) using a GPIO pin of my MCU? Is my above schematic correct?</p> <hr /> <p><strong>EDIT 15/02/24: A REVISED SCHEMATIC, AFTER THE ANSWERS</strong></p> <p>Is the revised schematic below now correct? My connection is: MCU_GPIO to Q1_b and Q1_c end with 5 V and there is a trim pot so I can control the intensity of the LED and I want to turn the LED on and off using the MCU.</p> <p>Read <a href="https://www.electronics-tutorials.ws/transistor/tran_4" rel="nofollow noreferrer">this</a> for some more detailed explanation.</p> <p><a href="https://i.stack.imgur.com/OZXpm.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/OZXpm.png" alt="enter image description here" /></a>T</p>

Can I control any transistor (NPN/PNP) using a GPIO pin of my MCU? Is my schematic correct?

2024-02-15T09:50:17.843

701533

|analog|feedback|common-mode|offset|source-follower|

<ol> <li>When you add resistors at the output of your amplifier, you're forcing the amplifier to drive not only the &quot;real&quot; load (another amplifier, an ADC, etc), but also these resistors. But you can't avoid using them because CMFB is a must in a fully-diff opamp. This can be a problem because your amplifier might not have enough capability to provide current for that extra load, and as such, it can cause gain reduction, increased distortion, etc.</li> </ol> <p>Adding a voltage buffer relieves the output from having to drive these resistors.</p> <ol start="2"> <li>you need to rephrase this question. However, it sounds like you don't understand why adding the third buffer would help compensate for the offsets introduced by the first 2. If I understood correctly, then simple answer is that the output buffers, being simple common-drain stages, shift down the output voltage by <span class="math-container">\$V_{GS}\$</span>. Therefore, you have the following expression going into the error amplifier:</li> </ol> <p><span class="math-container">$$ V_{cm} = \frac{(V_{o1}-V_{GS})+(V_{o2}-V_{GS})}{2} $$</span></p> <p>Assuming everything has settled, the output is simply <span class="math-container">\$V_{o,average}-V_{GS}\$</span>. If the other (+) input of your error amplifier is simply <span class="math-container">\$V_{cm}\$</span>, then, this error amplifier will do whatever it takes to equalize it's inputs. Since one input is at <span class="math-container">\$V_{o,average}-V_{GS}\$</span>, it will try to get rid of that <span class="math-container">\$V_{GS}\$</span> term. The only way to do that is to raise the outputs driving the buffers by said voltage. Therefore, you have an offset.</p> <p>Including that same <span class="math-container">\$V_{GS}\$</span> term at the (-) terminal is the only way out to get rid of this offset.</p> <ol start="3"> <li>The common-drain buffers need to comply with their <span class="math-container">\$V_{DS}\$</span> being larger than <span class="math-container">\$V_{GS}-V_{th}\$</span>; you may remember this as the saturation condition for MOS transistor.</li> </ol> <p><span class="math-container">\$V_{GS}=V_{G}-V_{S}\$</span> and <span class="math-container">\$V_{G}\$</span> is now that output of your amplifier. If this large, you may drive your buffers out of saturation thus rendering your CMFB loop useless. That's why the headroom of your output amplifier is limited; unless you use a larger VDD for your buffers, thus increasing its linear range larger than that of the amplifier. Sometimes, this is possible within an IC, sometimes not.</p>

<p>I am currently reading chapter 12, &quot;The Common-mode Feedback Circuit&quot; in <em>Analysis and Design of Analog Integrated Circuits</em> by Gray and Hurst.</p> <p>Page 815, gives the following statement for improvement of the resistive output loading of a common mode feedback (CMFB) circuit.</p> <p>The following figure 12.17 is the CMFB circuit after improvement, the previous figure 12.16 is the CMFB circuit before improvement.</p> <blockquote> <p>To avoid this resistive output loading, voltage buffers can be added between the op-amp outputs and the Rcs resistors. Source followers are used as buffers in Fig. 12.17. One potential problem is that each source follower introduces a DC offset of VGS between its input and output. To avoid a shift in the CM operating point caused by these offsets, voltage VCM can be buffered by an identical source follower so that the op-amp output voltages and VCM experience equal offsets. However, these offsets limit the op-amp output swing since each source-follower transistor that connects to an op-amp output must remain in the active region over the entire output voltage swing.</p> </blockquote> <p>Fig12.16:</p> <p><a href="https://i.stack.imgur.com/WZQdJ.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/WZQdJ.png" alt="Fig12.16" /></a></p> <p>Fig12.17:</p> <p><a href="https://i.stack.imgur.com/nhXIU.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/nhXIU.png" alt="Fig12.17" /></a></p> <ol> <li> <blockquote> <p>To avoid this resistive output loading, voltage buffers can be added between the op-amp outputs and the Rcs resistors. Source followers are used as buffers in Fig. 12.17</p> </blockquote> </li> </ol> <p>Does this mean that the voltage sensing circuit in the previous Fig. 12.16 has too high of an output impedance? Therefore, we employ a source follower as a voltage buffer to achieve a lower output impedance for the sensing circuit?</p> <ol start="2"> <li> <blockquote> <p>To avoid a shift in the CM operating point caused by these offsets, voltage VCM can be buffered by an identical source follower so that the op-amp output voltages and VCM experience equal offsets.</p> </blockquote> </li> </ol> <p>Why can we avoid a shift in the CM operating point by buffering VCM to let op-amp output voltages and VCM experience equal offsets?</p> <ol start="3"> <li>Why will the offset of a source-followe which is connected to the output of the opamp as a voltage buffer limit the op-amp output swing？</li> </ol>

Why will the offset of a source-follower which is connected to the output of an opamp as a voltage buffer limit the op-amp output swing?

2024-02-15T10:45:48.907

701543

|code|nxp|pmsm|z-transform|discrete|

<p>Re-examining the problem, I came to a solution very similar to the previous ones: <a href="https://i.stack.imgur.com/TKaHn.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/TKaHn.png" alt="enter image description here" /></a></p>

<p>I am researching about sensorless control of PMSM, and currently looking at how to implement the algorithm into code. From this link <a href="https://community.nxp.com/t5/Model-Based-Design-Toolbox-MBDT/Module-9-Position-Observer-Part-2-2/m-p/748340" rel="nofollow noreferrer">Module 9: Position Observer (Part 2/2)</a>. I encountered the equations shown below:</p> <p><a href="https://i.stack.imgur.com/dA7nN.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/dA7nN.png" alt="eq19" /></a></p> <p>How did the author come from above equation to the solution below? (from Eq. 17 to Eq.19), which solves for i_gamma, i_delta</p> <p><a href="https://i.stack.imgur.com/57IrO.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/57IrO.png" alt="Eq18" /></a></p> <p>With SISO system I know we can use z transform to derive difference equation which can be implemented in code. However, as this appears to be a MIMO system, I don't know what theory and tool for solving s-domain to the discrete-time domain in this case.</p> <p>I would greatly appreciate any explanation or references to related materials.</p>

Converting PMSM motor differential equation to difference equation/discrete-time implementation

2024-02-15T12:29:10.600

701544

|identification|datasheet|

<p>If it's an audio amplifier it might be the <a href="https://eu.mouser.com/datasheet/2/302/TDA1516BQ-843523.pdf" rel="nofollow noreferrer">TDA1516BQ</a>: -</p> <p><a href="https://i.stack.imgur.com/nqAeR.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/nqAeR.png" alt="enter image description here" /></a></p> <p>Image taken from <a href="https://www.ebay.co.uk/itm/395125198565?chn=ps&amp;_ul=GB&amp;_trkparms=ispr%3D1&amp;amdata=enc%3A1fL3dQxkTTQyN31pcuXM7qw93&amp;norover=1&amp;mkevt=1&amp;mkrid=710-134428-41853-0&amp;mkcid=2&amp;mkscid=101&amp;itemid=395125198565&amp;targetid=1647205089720&amp;device=c&amp;mktype=pla&amp;googleloc=9046470&amp;poi=&amp;campaignid=19926849521&amp;mkgroupid=147378848803&amp;rlsatarget=pla-1647205089720&amp;abcId=9311021&amp;merchantid=5309806263&amp;gclid=CjwKCAiAibeuBhAAEiwAiXBoJHxchjEMYhHDAGtzdrznR6VJVLLvAggrv0iydioCMEUmmMjKIxo-PRoCM-UQAvD_BwE" rel="nofollow noreferrer">gleeBay</a></p> <p>A lot of audio amplifiers begin with the letters TDA so it's worth searching for any that don't have a protruding heatsink, have decent sized mounting slots and, have 13 electrical pins arranged down the bottom edge.</p> <p>I advise you to check the pin functions and see if they align with sensible components on the PCB. Also check power supply rails are correct too.</p>

<p>I got this amplifier for a (glas)fiber switch. My guess is that this is originally an audio amplifier. Unfortunately the company that made the PCB obscured the part with a laser engraver. I only removed the name of the company from the pictures.</p> <p>Does anyone know this part?</p> <p>The reason why i want to know the part better is that i can improve the parameter to fit the switch or replace it with an other suitable one</p> <p><a href="https://i.stack.imgur.com/2HdOO.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/2HdOO.jpg" alt="enter image description here" /></a> <a href="https://i.stack.imgur.com/TPSK6.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/TPSK6.jpg" alt="enter image description here" /></a></p>

Looking for an obscured amplifier

2024-02-15T12:33:05.330

701556

|rf|inductor|amplitude-modulation|

<blockquote> <p><em>Finally, I disconnected the scope and R1 from the circuit, and used the scope to generate an RF signal at f0 through a long wire antenna. I then measured the amplitude V induced across the tank circuit at a short distance (4 inches) from the antenna.</em></p> </blockquote> <p>At circa 40 kHz a monopole antenna would need to be nearly 2 km long to generate a reasonable magnetic field. What you are generating is a decent electric field (in the near-field) that capacitively couples to both coils about the same. This is not the way to test a loop-stick antenna vs drum core.</p>

<p>In response to answers from my previous question, I compared the ability of a tank circuit to receive signals when the inductor was a loopstick vs a choke.</p> <p>The inductor was either a) a choke with Lc=0.54mH (R=3.2ohms) (as in figure 1), or b) a loopstick with Ll=0.6mH (R=8.3 ohms)) (Figure 3, from a radio clock).</p> <p><strong>Finding f0</strong>. A sinusoidal 1V (p2p) signal from a signal generator was injected across the whole circuit shown in Figure 2. The frequency was adusted to maximise the voltage across the tank circuit, to find the resonant frequency, which was found to be f0=40kHz (for both the choke and the loopstick).</p> <p>As an aside: The measured p2p amplitude across the tank circuit at f0 was 57mV, so that</p> <p>57mV/1000mV = Z/(Z+20k),</p> <p>so, solving for Z yields Z = 1200 ohms at f0.</p> <p>Finally, I disconnected the scope and R1 from the circuit, and used the scope to generate an RF signal at f0 through a long wire antenna. I then measured the amplitude V induced across the tank circuit at a short distance (4 inches) from the antenna.</p> <p>Result: With the loopstick, Vl = 4mV, whereas with the choke, Vc = 3mV.</p> <p>This seems to suggest that both the choke and the loospstick are almost equaly good (bad) at converting the RF signal into voltage.</p> <p>What am I missing? Are the results for the choke and loopstick similar because the circuit is recording a ceiling/floor effect (ie it is a rubbish circuit)?</p> <p><a href="https://i.stack.imgur.com/OWTa8.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/OWTa8.jpg" alt="enter image description here" /></a> Figure 1. Picture of a (very) spare choke, with the plastic coating removed (I managed to break the wires inside in the process of removing the plastic). The material at both ends (caps) of the coiled wire is magnetic (ferrite?).</p> <p><a href="https://i.stack.imgur.com/uFhv0.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/uFhv0.jpg" alt="enter image description here" /></a> Figure 2. Circuit used to estimate resonant frequency f0 and impedance Z of tank circuit at resonant frequency f0.</p> <p><a href="https://i.stack.imgur.com/GgfOy.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/GgfOy.jpg" alt="enter image description here" /></a> Figure 3. Loopstick used to replace choke in tank circuit.</p>

Why do loopsticks and chokes receive RFs equally well?

2024-02-15T14:01:31.383

701573

|fpga|verilog|intel-fpga|synthesis|stratix-series-fpga|

<p>Let's just derive the circuit ourselves. The key is to break the operation on the input integers down into smaller pieces.</p> <p>Given two numbers, for example <code>234</code> and <code>125</code>, you can immediately tell that <code>234</code> is larger by just looking at their first digits. Any number of the form <code>2xx</code> is always larger than one of the form <code>1xx</code>.</p> <p>Only when the first digits are identical do we need to look at the others. For example, let's take <code>148</code> and <code>125</code>. The first digits are identical, so we move on to the second digits. Here, the digit &quot;4&quot; is greater than &quot;2&quot;, so we can conclude that <code>148 &gt; 125</code> without needing to check the last digit at all.</p> <p>This is called a lexicographic comparison, and it's the key to implementing magnitude comparators in hardware.</p> <p>Let's apply this to our <code>A[15:0] &gt;= B[15:0]</code> operation, which is the same as <code>A[15:0] &lt; B[15:0]</code> inverted. Using 5-input LUTs, we can process 2 bits at a time, using 4 of the available LUT inputs.</p> <p>We'll start with the topmost two bits. There are essentially three cases:</p> <ol> <li>If <code>A[15:14] &lt; B[15:14]</code> is true, <code>A[15:0] &lt; B[15:0]</code> must also be true. The entire comparison should output 1.</li> <li>If, on the other hand, <code>A[15:14] &gt; B[15:14]</code> is true, then <code>A[15:0] &gt; B[15:0]</code> is also definitely true. The entire comparison should output 0.</li> <li>Lastly, if <code>A[15:14] == B[15:14]</code> is true, we need to look at the other bits (13 and downwards).</li> </ol> <p>Case 1 and 2 are easy, only case 3 is a bit more difficult. We need to forward the result from the comparisons of the other bits... But luckily we've only used 4 LUT inputs so far, which means that we have one to spare that we can use for this purpose!</p> <p>In the end, it boils down to the following pseudocode:</p> <pre><code>inputs: a[1:0], b[1:0], lessthan_in outputs: lessthan_out if (a &lt; b) lessthan_out = 1; else if (a &gt; b) lessthan_out = 0; else lessthan_out = lessthan_in </code></pre> <p>Since this block of logic only has 5 inputs and 1 output, you can map it onto a single LUT5 by evaluating it for all possible input values. (There are only 32 of them.) Now all you have to do is to repeat this for the other bit positions and chain the resulting (identical) LUTs together. In the end, you can compare two 16-bit values with eight LUT5 instances using this scheme.</p> <blockquote> <p>I can see that in the technology viewer it is using 4 or 5 primitives with 4 inputs to calculate the inequality - meaning it's probably using 2 logic cells.</p> </blockquote> <p>Note that this is wrong, given that it would mean there are only 20 inputs in total across all those primitives, which is insufficient to process two 16-bit integers (32 bits total). The eight LUT5s from the solution I presented have 40 inputs in total, meaning there's only an overhead of 8 inputs. This is the best you can do with 5-input primitives.</p> <p>The only case where Quartus might be able to compare two 16-bit values with less than eight LUT5 instances is when some of the bits are constant. (I.e. you're not using the full range of a 16-bit integer, or skipping some values with a counter, etc)</p> <p>For example, if you compare a 16-bit value to another one that only has 8 bits, you need four of the previously mentioned LUT5 instances to compare the lower 8 bits. For the upper 8 bits of the 16-bit operand, you only have to check that they're zero. You can use two LUT5s for that, with each of them checking four bits at a time, as in the following pseudocode:</p> <pre><code>inputs: a[3:0], lessthan_in outputs: lessthan_out if (a &gt; 0) lessthan_out = 0; else lessthan_out = lessthan_in; </code></pre> <p>In total, the circuit will look as follows, from LSB to MSB:</p> <pre><code> 0 -&gt; COMP2 -&gt; COMP2 -&gt; COMP2 -&gt; COMP2 -&gt; ZERO4 -&gt; ZERO4 -&gt; output bits# [1:0] [3:2] [5:4] [7:6] [11:8] [15:12] </code></pre> <p>Each of the &quot;COMP2&quot; blocks takes as input two bits from A and B respectively, and each of the &quot;ZERO4&quot; blocks takes four bits from the 16-bit-wide A. The arrows between the blocks represent the &quot;lessthan&quot; inputs and outputs of the blocks, which chain them together.</p>

<p>From curiosity and to understand the cost of the operator I often using in FPGA design.</p> <p>Let's assume I am doing the following equation in Verilog:</p> <pre><code>OUT = A[15:0] &gt;= B[15:0]; </code></pre> <p>How will the FPGA implement this operator? Will it just use a LUT? I don't understand how a LUT solves this logic.</p> <p>More specifically if relevant I am using Quartus and Stratix10 FPGA.</p> <p>This is what the RTL Viewer shows:</p> <p><a href="https://i.stack.imgur.com/4NHwk.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/4NHwk.png" alt="enter image description here" /></a></p> <p>This is what the Technology Map Viewer shows:</p> <p><a href="https://i.stack.imgur.com/eaHqt.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/eaHqt.png" alt="enter image description here" /></a></p> <p>I would like to understand how it is actually fitted into a Stratix10 logic cell:</p> <p><a href="https://i.stack.imgur.com/2C2UC.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/2C2UC.png" alt="enter image description here" /></a></p> <p>What I understand:</p> <p>I can see that in the technology viewer it is using 4 or 5 primitives with 4 inputs to calculate the inequality - meaning it's probably using 2 logic cells.</p> <p>I can't imagine what the logic inside the LUT looks like.</p>

How do FPGAs implement the inequality operator?

2024-02-15T15:46:48.760

701577

|led|circuitlab|

<p>I imported SPICE models and everything worked!</p> <p>Had to replace LM302H-EVO with LM301H_ONE model to approximate performance, but this seems acceptable.</p> <p>Here's a link to my new circuit v4, which closely replicates the Samsung Horticultural Gen2 module.</p> <p><a href="https://www.circuitlab.com/circuit/3c2g8eszq896/gen2-repo-v4/" rel="nofollow noreferrer"><img src="https://www.circuitlab.com/circuit/3c2g8eszq896/screenshot/540x405/" alt="CircuitLab Schematic 3c2g8eszq896" /></a></p>

<p>After running DC Simulation in CircuitLab, I get this error message:</p> <p>&quot;Error building graph: non-finite value.&quot;</p> <p>What is going on? I'm new at this, so anything could be wrong. First, to address and correct errors, I added SPICE values to all the LEDs, which cleared all errors but this one.</p> <p>Here's the circuit:</p> <p><a href="https://www.circuitlab.com/circuit/3av343hdmban/gen2-repro/" rel="nofollow noreferrer"><img src="https://www.circuitlab.com/circuit/3av343hdmban/screenshot/540x405/" alt="CircuitLab Schematic 3av343hdmban" /></a></p> <p>Edit updated 11:53EST 2/15/24:</p> <p>Tried advice from &quot;Andy aka&quot; and removed the voltmeters and ampmeters from the circuit. Same error result:</p> <p><a href="https://www.circuitlab.com/circuit/4ddq42b2r54j/gen2-repro-v2/" rel="nofollow noreferrer"><img src="https://www.circuitlab.com/circuit/4ddq42b2r54j/screenshot/540x405/" alt="CircuitLab Schematic 4ddq42b2r54j" /></a></p> <p>Thanks for the suggestion, Andy! Any help appreciated!</p>

Help "Non-finite value" Circuit Lab Error

2024-02-15T16:20:23.820

701588

|operational-amplifier|led|led-driver|single-supply-op-amp|

<p>LM358 has no trouble operating its inputs near 0V, so it's not an input common mode range problem, unless you're not really using LM358.</p> <p>All opamps have a little bit of offset voltage. In your circuit's case, if the offset voltage is the &quot;right&quot; polarity, it will be applied to the output which means a non-zero current will flow through the LED even if input voltage is zero.</p> <p>In addition if your control voltage source has high output impedance, the small input current of the opamp can add some more offset.</p> <p>The simplest solution is to wire a resistor in parallel with the LED.</p> <p>First measure voltage across the 1k resistor when the LED should be off. Suppose it's 1mV, this means there is 1µA through the LED. At this current its Vf should be around 1-1.3V so... pick a resistor that will take this 1µA current at this voltage, say 1Megohm, and wire it across the LED. Adjust the numbers according to what you measure on the resistor.</p>

<p>I am working on my project's visual indicator part.</p> <p>Everything woks as expected, but LED shines dimly when connected in feedback loop and with no control signal. Shining is barely visible, but it is still there. I want it to be connected in feedback loop because this way I get LED response I need (I use low control voltage). Is it possible to lower op-amps output voltage a little bit using this configuration?</p> <p><a href="https://i.stack.imgur.com/8lU33.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/8lU33.png" alt="enter image description here" /></a></p>

LED in op-amp`s feedback loop shines dimly. How to eliminate this?

2024-02-15T18:28:26.643

701607

|resistors|

<p>Yes, they're still used in some applications. That particular part could be used as an adjustable load in the low hundreds of watts, however for a maximum of about 155VDC or 155VAC RMS. In fact, I rather suspect the oddball 71Ω standard value was chosen to be useful on 120VAC/60Hz North American mains voltage.</p> <p>They would not be all that useful for lower voltages such as 24V (maximum power only 53W so most of the capacity would be wasted). A lower element resistance would be indicated for such applications.</p>

<p>I have many different large wire wound resistors. Are they still in use? It is 71.0 Ohms, tests at 72.3. Are they obsolete?<a href="https://i.stack.imgur.com/44H6e.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/44H6e.jpg" alt="enter image description here" /></a></p> <p><a href="https://i.stack.imgur.com/67FO9.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/67FO9.jpg" alt="enter image description here" /></a></p> <p><a href="https://i.stack.imgur.com/JifVg.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/JifVg.jpg" alt="enter image description here" /></a> <a href="https://i.stack.imgur.com/gYnRW.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/gYnRW.jpg" alt="enter image description here" /></a></p>

Are large scale wire wound resistors used?

2024-02-15T20:28:49.990

701613

|raspberry-pi|automotive|

<p>This is a known issue with these Raspberry Pis. The standard fix to this is to cut the 5V line in the cable.</p> <p>If you don't want to alter or damage the cable, you can buy a USB extension cable and cut the 5 V wire in that.</p> <p>I have also seen solutions where they simply place a small piece of electrical tape over the 5 V contact on the USB port before plugging in the cable.</p> <p>Alternatively, you could place a Schottky diode on the 5 V line, allowing the Pi to power the USB peripheral but not allow back-feeding.</p>

<p>I'm running a Rasberry PI 4 in my car to read values from the ODB2 Port.</p> <p>Below is the diagram of my setup.</p> <p><a href="https://i.stack.imgur.com/xHbtu.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/xHbtu.png" alt="enter image description here" /></a></p> <p>The PI is powered via the Cigarette Port using a 12v to USB charger that has an On/Off button attached.</p> <p>My problem is that when USB charger is turned off the Raspberry PI still turns on boots up when I turn the car on but I get the low power warning on the PI4. I suspect its receiving power from the ODB2 Port via the USB A port. Even thou the documentation states you cannot power the PI from the USB A ports.</p> <p>If I physically unplug the cable from the charger or the ODB2 port that PI looses power.</p> <p>Is it possible to avoid this happening and would it cause any problems if I run the setup like this?</p>

Raspberry PI powered via USB A in car when using ODB2 Port

2024-02-15T21:35:10.213

701621

|power-electronics|switch-mode-power-supply|inductor|buck|

<ol> <li><p>There are some hints in TI patents such as <a href="https://patentimages.storage.googleapis.com/99/96/2a/75c8c6d7e5ee23/US20180082930A1.pdf" rel="noreferrer">this</a> one. Looks like most of the volume of the converter <em>is</em> the inductor.</p> </li> <li><p>They need a certain volume of ferrite and more space for the copper winding to meet specifications (saturation current, inductance and DCR, for example).</p> </li> <li><p>Usually the cost is much, much lower if you can afford the space. If cost is of no concern you can use whatever you like.</p> </li> <li><p>High frequencies (500kHz to 2MHz) mean the inductors can be lower value, all other things being equal.</p> </li> </ol>

<p><a href="https://www.ti.com/lit/ds/symlink/tpsm843b22e.pdf?ts=1707985406865&amp;ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FTPSM843B22E" rel="noreferrer">This</a> 20 A buck regulator module from TI is 6.5x7.5x4 mm and has an internal 330 nH inductor.</p> <p><a href="https://cps.coilcraft.com/en-us/products/power/shielded-inductors/molded-inductors/pya/ms512pya/?skuId=38483" rel="noreferrer">This</a> 6.5x6.5x3.1 mm 330 nH inductor from Coilcraft has an RMS current rating of 18.8 A and is the smallest I could find on their website at that inductance.</p> <p>I have a couple of questions:</p> <ol> <li>How does TI manage to fit the inductor inside the package?</li> <li>Why are standalone inductors so big?</li> <li>What is the point of using a buck regulator without an integrated inductor?</li> <li>How does TI get the module to work with what seems like a really low inductance?</li> </ol>

How do buck regulator modules with integrated inductors manage to be so small?

2024-02-15T22:08:58.207

701627

|power|amplifier|rf|radio|class-e|

<p>There are good VHF RF transistors commercial available on internet. For example a 2N4427T RF transistor. Cascode amplifier are well suggested for amplifying high frequencies with small signal.</p> <p>I calculated my own design at given tool link:</p> <p><a href="https://www.utmel.com/tools/bjt-cascode-amplifier-calculator?id=34" rel="nofollow noreferrer">https://www.utmel.com/tools/bjt-cascode-amplifier-calculator?id=34</a></p> <p>I have also simulated on LTSpice a working cascode amplifier. You will see the high power gain at output. The picture is below:</p> <p>Violetta is input R7 power Yellow is output R8 power. <a href="https://i.stack.imgur.com/Vz3ri.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/Vz3ri.png" alt="circuit" /></a></p> <p>I hope it helps others, too.</p>

<p>I am studying RF amplifiers. Most of the time, when I simulate several BJT amplifiers at a very high frequency, I do not get a good voltage or current gain. I have heard of Miller effect. What does it do and how can I design against this effect? Class E amplifier should be good one, but all I need is how to think about high frequency amplification. There are many web sites on internet, they are useless, too. They do not give the information to make and keep it simple.</p> <p>Can you give me an example, how to design simply a VHF amplification?</p> <p>Edit:</p> <p>I am interested in electronics, but I am not academically educated.</p>

How can VHF signal be amplified with respective gain by simple BJT circuit design?

2024-02-15T23:29:41.403

701641

|digital-logic|logic-gates|

<blockquote> <p>I noticed that the XOR gate seems overly complex</p> </blockquote> <p>At the most basic level, every gate implements a truth table. So, at a minimum, you could just have a programmable truth table, and you can get any gate you want. All you need then is a multiplexer:</p> <p><img src="https://i.stack.imgur.com/ewlsG.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fewlsG.png">simulate this circuit</a> &ndash; Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a>}</p> <p>As shown, the gate is configured to be an AND gate. The inputs 0-3 to the multiplexer are related to output values in the rows of a truth table. So, take the output column from a truth table, stick it into the circuit above, and you have a gate or any other logic function according to that truth table.</p> <p>It is not particularly complicated to have a simple diode-transistor implementation of such a mux.</p> <p>The 4-input multiplexer connects output to one of the inputs that are attached to either supply rail, so it always regenerates the signal.</p> <p>With two inverters added, you can use a 2:1 mux instead:</p> <p><img src="https://i.stack.imgur.com/5jaBO.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2f5jaBO.png">simulate this circuit</a>}</p> <p>With a 4:1 mux, we had 4 inputs, and 2 choices of signals to feed to each input - VCC or GND (logic high or low). 2^4=16 possible gates.</p> <p>With a 2:1 mux, we have 2 inputs, and 4 choices of signals to feed to each input: VCC, GND, IN1, not(IN1). 4^2=16 possible gates.</p> <p>As shown, the configuration for both mux-gates is that of an AND gate.</p> <p>Inverters are easy, and a 2:1 mux is not particularly hard either :)</p> <hr /> <p>If I were you, I'd use off-the-shelf CD4000-series gates that you can buy from major vendors (DigiKey, Mouser, etc.), and also directly from TI (Texas Instruments), in either DIP or surface-mount packages. Every common chip in that family that has 14 or 16 pins is still available in DIP, brand new!</p> <p>Below is the collection of the basic gates from the 4000 series, drawn myself. CD4049, CD4050, CD40109, CD4504 are level translators and you wouldn't need them. The processor made of these can be tuned for clock rate vs. supply voltage, just like desktop CPUs, and for the same reason. The higher the voltage, the faster it can go. CD4000-family can be slow and sip power at 3V, or rather zippy at 15V. With the chips of recent manufacture (last 15 years or so), peak speed is between 12V and 15V, with minimum gains from 12V up.</p> <p><a href="https://i.stack.imgur.com/ru1FL.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/ru1FL.jpg" alt="enter image description here" /></a> <a href="https://i.stack.imgur.com/MVhd2.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/MVhd2.jpg" alt="enter image description here" /></a> <a href="https://i.stack.imgur.com/iMJ64.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/iMJ64.jpg" alt="enter image description here" /></a></p> <p>Not shown is the 8-input CD4048 configurable expandable gate that can be configured to be the gate of your choice :)</p> <p>The reference for the entire CD4000 family that TI still makes, and a few interesting but obsolete parts in that family, in high-rez PDF and in Goodnotes format, are here:</p> <p><a href="https://hackaday.io/project/191205-4000-series-logic-reference-cards" rel="nofollow noreferrer">CD4000 Logic Reference Cards</a>.</p>

<p>I am very new to electrical engineering.</p> <p>But I am working on a hyper reduced fully functional RISC architecture. This is mostly finished, I have a compiler for it and the emulator is not fully complete yet but it seems to be fully functional, it is limited to 16 instructions with 1 of them reserved for extended instructions such as interrupt calls.</p> <p>When working on silicon design (Not really on the silicon phase yet but circuit design) I noticed that the XOR gate seems overly complex.</p> <p>Why would this not work:</p> <p><img src="https://i.stack.imgur.com/T3nCC.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fT3nCC.png">simulate this circuit</a> &ndash; Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a>}</p> <p>I was was led to believe that the resistors were required for high frequencies to drain the circuit before next clock pulse.</p> <p>I am new to this so if this is horribly wrong please correct me.</p>

3 transistor XOR gate

2024-02-16T04:11:41.497

701643

|brushless-dc-motor|motor-controller|connecting|

<p>yes both are same you can go ahead with this</p>

<p>I have a BLDC motor with Hall connections Hu, Hv, Hw and U, V, W. I am looking at a driver for the BLDC motor, but the driver has hall connections HA, HB and HC. Are Hu, Hv, Hw and HA, HB, and HC the same? Can I use this driver to run my BLDC motor?</p>

Suitable driver for BLDC motor

2024-02-16T04:30:00.173

701648

|mosfet|mosfet-driver|

<p>R4 is fine with 10K (you can go as high as 50K). The problem is with R5. Resistors to ground should be at least 100K. In this case Q3 Gate is not fully on because too much voltage drop through R5. Some current remains at Q1A and Q1B Gates which are not fully turned off. When MOSFET 's are not fully on or not fully off, they tend to heat a lot because their resistance Rdson is much higher.</p> <p>Another possible problem is that 18V is too high for the gates. Usually gates can support up to 20V but maybe not with these models or the 18V is not exactly 18V all the time. I would reduce the voltage down to 15V to make sure.</p> <p>There could other reasons. But without the schematic of the entire circuit, it's hard to say which ones.</p> <p>EDITUM:</p> <blockquote> <p>Blockquote Should there be a discharge resistor similar to R5 (for Q3) that discharges any voltage build-up by Q1 internal capacitor?</p> </blockquote> <p>There should be a discharge (pull down) resistor if &quot;18V&quot; could become high impedance, e.g. physically disconnected. If &quot;18V&quot; is always either 18V or 0V (open drain, connected to GND...) then it's not theoricaly necessary. Still even in this case it can be useful to add one to make sure the gate is stable at start up or in case of malfunction. Having the gate floating, in itself, will not damage the MOSFET but could cause over heating because the gate will be between on and off many times, and it will wear it out.</p> <p>With R4 at 10K and a pull down resistor of 100K, the voltage will be reduce by 10% and will be safer to use on the gate.</p>

<p>I have a device designed by a more experienced peer of mine. The peer left, and the problem lands on me. <a href="https://i.stack.imgur.com/JxGI7.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/JxGI7.png" alt="enter image description here" /></a></p> <p>The Mosfet Q1, often got killed (failed to switch on), and the fix was simply replacing it till now.</p> <p>Recently I smelled the Mosfet overheated and the pcb got toasted in the Drain 1 area. My guess is that the 10k resistor R4 is too high, result Q1 not fully open/close, and the internal resistance got very large, it began to self-charge/discharge... <a href="https://i.stack.imgur.com/uG14j.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/uG14j.jpg" alt="enter image description here" /></a></p> <p>The ENable is on by default, when off, 18v turns the gates on/off...</p> <ol> <li><p>So how do I find a right gate resistor? I found this formula: Rgate=Vgate/(Imax) I assume Vgate=18v, but which one is Imax in the <a href="https://www.vishay.com/docs/76453/sqj570ep.pdf" rel="nofollow noreferrer">datasheet</a>? the Gate resistance in page 2, is that mosfet internal resistance or recommend external Gate resistor I'm looking for?</p> </li> <li><p>should there be a discharge resister similar to R3 (for Q3) that discharge any voltage build up by Q1 internal capacitor?</p> </li> </ol> <p>Thank you all, still learning</p>

Overheating MOSFET fix, find right gate resistor

2024-02-16T05:36:54.813

701652

|switch-mode-power-supply|dc-dc-converter|filter|design|

<blockquote> <p>If I am right, is there anything specific I need to take care of before using the filter in my SMPS?</p> </blockquote> <p>You are correct in that they are used to balance the voltage on the capacitors. This is important for keeping the voltage on each capacitor within its specs, even when they may differ in leakage current.</p> <p>Additionally they are used as <a href="https://en.wikipedia.org/wiki/Bleeder_resistor" rel="nofollow noreferrer">bleeder resistors</a> for the capacitors. They drain the charge when power is disconnected, to avoid giving shocks to anyone opening the enclosure.</p> <p>In the design, you should take into account:</p> <ul> <li>Dissipated power and the power rating of the resistors.</li> <li>Voltage rating of the resistors.</li> <li>Leakage current tolerance of the capacitors, the resistors must bleed enough current to keep the capacitors balanced.</li> <li>Time it takes to bleed off the voltage on disconnect (should be faster than the time it takes to open the enclosure).</li> <li>Creepage and clearance distances required vs. the contact spacing of the resistors.</li> </ul> <p>I would aim for a 2x safety margin on all of these, as it doesn't affect the cost much.</p> <p>Using a TVS or varistor in parallel with each capacitor can provide extra protection against voltage spikes and end-of-life changes in leakage current. Otherwise you may end up with higher than expected leakage in one capacitor causing overvoltage arc fault in the other capacitor.</p>

<p>I have been trying to choose the input capacitors for an SMPS and have noticed resistors being used in parallel with the polarized capacitors.</p> <p>Since these designs are for an 800 V system, I am assuming the resistors are there to keep the voltage level across the capacitors divided and help in filtering the high frequency noises.</p> <p>If I am right, is there anything specific I need to take care of before using the filter in my SMPS?</p> <p><a href="https://i.stack.imgur.com/OQWPV.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/OQWPV.png" alt="enter image description here" /></a></p>

Parallel resistors with polarised capacitor

2024-02-16T06:07:22.640

701661

|mosfet|small-signal|bulk-capacitor|

<p>If it's connected to ground/VDD in the original schematic, then it's grounded in an AC analysis because we assume ground/VDD to be a DC constant voltage.</p> <p>Small-signal analysis is about slopes, and slope of a fixed DC voltage is 0.</p>

<p>This the circuit. The bulk is connected to ground in DC.</p> <p>Is the bulk grounded in small AC signal analysis (V_b = 0)?</p> <p><a href="https://i.stack.imgur.com/8c828.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/8c828.png" alt="enter image description here" /></a></p> <p><a href="https://i.stack.imgur.com/8tsv2.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/8tsv2.png" alt="enter image description here" /></a></p> <p>How about for PMOS? When the bulk of PMOS is connected to VDD, is the bulk grounded in small AC signal analysis (V_b = 0)?</p>

Is the bulk grounded in small AC signal analysis?

2024-02-16T08:18:14.020

701662

|bias|fet|saturation|

<blockquote> <p><em>Suppose I want a FET in saturation acting as a high-side switch</em></p> </blockquote> <p>_{I'm assuming that &quot;FET&quot; means an enhancement mode MOSFET (commonly used as a high-side switch). I'm also assuming that when you refer to a high-side switch, you are using an appropriate gate-source driver circuit.}</p> <p>Biasing is used to set a quiescent current from drain to source. If you want a MOSFET to act like a switch, you don't want any gate/base signal present when you want the device to be &quot;off&quot; so, no, in your application, MOSFETs don't need to be biased.</p>

<p>From my knowledge, BJTs need to be biased to control its linearity and gain, usually with resistors on the base and collector. Suppose I want a FET in saturation acting as a high-side switch.</p> <p>Do FETs need to be biased? If so, why? (assume n-channel enhancement)</p>

Do FETs need to be biased?

2024-02-16T08:28:17.913

701669

|switching|

<blockquote> <p><em>When the display connector is detached, I can see the drain going high and low, but going low takes 3 ms.</em></p> </blockquote> <p>When the MOSFET isn't activated it acts like an open circuit so, the time it takes for the output voltage to discharge is largely determined by the input resistance of the oscilloscope probe (possibly 1 MΩ to 10 MΩ).</p> <p>3 ms sounds very reasonable under these circumstances.</p> <blockquote> <p><em>When I attach the display connector to the display it seems I can't drive the pin low anymore.</em></p> </blockquote> <p>Let's me be clear; the MOSFET can only pull that pin to a high-state. In other words it cannot drive that line low so, if there is an internal pull-up resistor in the display, the pin will remain high.</p> <blockquote> <p><em>The previous version of this PCB just had IO4 connected directly to display.pin12. It had some quirks, but worked fine.</em></p> </blockquote> <p>That confirms my suspicion; you should probably use an external pull-up and low-side N channel MOSFET or, stick with the IO pin driving it directly.</p> <blockquote> <p><em>the same problem happens also on the 5 V MOSFET which has this schematic</em></p> </blockquote> <p>Following a discussion in comments with @6v6gt, it appears that the ESP32 is powered from 3.3 volts. This means that it can never properly deactivate MOSFET Q1 because its source is at 5 volts (leaving 1.7 volts from gate to source). This is enough to keep the MOSFET at least partially activated. You should look for a circuit change to fix this.</p>

<p>I've been using the FDN304P coupled with an ESP32 to cut 3.3 V or 5 V with this circuit.</p> <p>I'll focus on the 3.3 V MOSFET.</p> <p>Schematic:</p> <p><a href="https://i.stack.imgur.com/fEYUl.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/fEYUl.jpg" alt="enter image description here" /></a></p> <p>PCB layout:</p> <p><a href="https://i.stack.imgur.com/J0FCT.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/J0FCT.png" alt="enter image description here" /></a></p> <p><strong>The problem</strong></p> <p>When the display connector is detached, I can see the drain going high and low, but going low takes 3 ms.</p> <p>CH1 is IO4, CH2 is display.pin12:</p> <p><a href="https://i.stack.imgur.com/lXr90.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/lXr90.png" alt="enter image description here" /></a></p> <p><a href="https://i.stack.imgur.com/ut997.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/ut997.png" alt="enter image description here" /></a></p> <p>NOTICE: the time divider.</p> <p>When I attach the display connector to the display it seems I can't drive the pin low anymore.</p> <p><a href="https://i.stack.imgur.com/K0eHY.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/K0eHY.png" alt="enter image description here" /></a></p> <p>It just always stay high.</p> <p>There must be something on the other side keeping pin12 high, but I'm not sure what.</p> <p>Here is a pic:</p> <p><a href="https://i.stack.imgur.com/1sM2h.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/1sM2h.png" alt="enter image description here" /></a></p> <hr /> <p>The previous version of this PCB just had IO4 connected directly to display.pin12. It had some quirks, but worked fine.</p> <p>Anyway, the same problem happens also on the 5 V MOSFET which has this schematic. That leads me to think I'm doing something wrong.</p> <p><a href="https://i.stack.imgur.com/zaFMq.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/zaFMq.png" alt="enter image description here" /></a></p>

Why isn't this P-MOSFET switch circuit working?

2024-02-16T09:35:37.300

701672

|mosfet|bulk-capacitor|

<p>Your Eq. 1 does not hold because it assumes the body terminal is disconnected. In other words, you are not including current flow from the body terminal to ground when writing KCL. Since this current is not known a priori, writing KCL at the body node is not useful for standard nodal analysis because it requires you to introduce an additional unknown.</p> <p>All you need to do is write KCL at the source and drain nodes. You will then have two equations that can be solved for the unknown voltages. I don't know how exactly you got Eq. 2 but it doesn't look like either of those equations.</p>

<p>This is the circuit:</p> <p><a href="https://i.stack.imgur.com/vo608.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/vo608.png" alt="enter image description here" /></a></p> <p><a href="https://i.stack.imgur.com/ruLy5.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/ruLy5.png" alt="enter image description here" /></a></p> <p>KCL at bulk:</p> <p><span class="math-container">$$V_{out} s C_{bd} + V_{in} s C_{gb} = - V_S s C_{bs} \tag{1}$$</span></p> <p>Does this equation work in this case?</p> <p>KCL at Gate.</p> <p><span class="math-container">$$(V_{in} - V_S) g_m - V_S g_{mb} + \frac{V_{out} - V_S} {r_{ds}} + V_{out} s C_{bd} + (V_{out} - V_{in}) s C_{gd} = - \frac{V_{out}} {R_D} \tag{2}$$</span></p> <p>KCL at Source. <span class="math-container">$$(V_{in} - V_S) s C_{gs} + \frac{V_{out} - V_S} {r_{ds}} + (V_{in} - V_S) g_m - V_S g_{mb} - V_S s C_{bs} + (V_{in} - V_S) s C_{gs}= \frac{V_S} {R_S} \tag{3}$$</span></p> <p>We have two unkown variables <span class="math-container">\$V_S\$</span> and <span class="math-container">\$V_{out}\$</span>. At the same time, we also have two equations (1) and (2) here. So we can solve this equation without writing more equation. It looks like <span class="math-container">\$V_{out}\$</span> doesn't depend on <span class="math-container">\$R_S\$</span>.</p>

KCL at bulk in CMOS

2024-02-16T10:01:56.110

701681

|transistors|cmos|diagram|

<p>Q16 is a triode region transitor, i.e. a resistor, implementing a resistor. This allows tracking of the Q7's gm.</p> <p>Q6&amp;7 do amplify the signal.</p> <p>They're assuming a unit transistor of W/L ratio, but they're not saying what's this base ratio. All we know is that they are scaled by those numbers, e.g 300*W/L. Apparently they're also using the same length, but this doesn't necessarily mean they're using the minimum length available in the technology.</p>

<p><a href="https://i.stack.imgur.com/CwEp9.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/CwEp9.png" alt="Image from PDF" /></a></p> <p>Taken from: Analysis and Design of Analog Integrated Circuits, 4th Edition by Paul R. Gray , Paul J. Hurst, Stephen H. Lewis, Robert G. Meyer. Page unknown.</p> <p>Hi. I am studying about MOSFETs and I am trying to understand what each component does in this circuit. I am having trouble however with transistor Q16. From left to right, we have a cascode current mirror, the differential pMOS pair with its tail, the capacitor for the feedback effect and a voltage follower Q8 in the output biased by the current mirror Q7&amp;Q9. Now, Q16 confuses me. It looks like a common gate amplifier but I am not sure what it does for this circuit. So my questions are:</p> <ol> <li>Do the Q6 and Q7 transistors amplify the signal?</li> <li>What is the use of the Q16 transistor?</li> <li>What do the numbers on each transistor mean? I think this is the W of the MOS but what are the units? Given the technology (CMOS 1.2μm, 5 Volt, 1 poly, 3 metals) I have L as 1.2μm, right? Is the W in μm as well?</li> </ol> <p>Thanks!</p>

Having trouble understanding a basic MOS OpAmp diagram

2024-02-16T10:44:19.483

701696

|transistors|analog|integrated-circuit|leakage-current|cadence|

<p>Well, that's not surprising, because you also increased the width by a factor of 10x, which will, most likely, dominate the leakage compared to the reduction that could be provided by the length increase alone.</p>

<p>I'm trying to understand the leakage current characteristics of a 130nm PDK in Cadence. I set up a testbench by grounding the gate and source terminals of a nmos FET, and setting the drain voltage to a constant (200mV). For a very small size (W/L = 300n/150n), there's about 0.5pA flowing into the drain, and as I increase the drain voltage, the drain current increases linearly. I checked the Ron value through a DC simulation, and Ron is around 600G ohm (200mV/600G = 0.33pA, not too much difference).</p> <p>I found many posts saying that increasing channel length reduces leakage current. So I increased the W/L to (3000n/1500n). However, the drain current now is 10 times higher.</p> <p>Is this the right way to measure the leakage current? If not, what is this current I'm looking at?</p>

Is this the leakage current of a MOSFET?

2024-02-16T12:34:50.577

701705

|resistors|resistance|

<p>You put the part number into your search engine and hope to get a result, preferably a manufacturer data sheet for the given part series.</p> <p>For the Ohmite part 210-100M-40, you will find that it is a 50 ohm 100W part.</p>

<p>I am trying to understand how to figure a resistors wattage based on label.<a href="https://i.stack.imgur.com/oBYPb.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/oBYPb.jpg" alt="enter image description here" /></a></p> <p><a href="https://i.stack.imgur.com/6QaVT.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/6QaVT.jpg" alt="enter image description here" /></a></p>

HOW TO FIGURE RESISTOR WATTAGE

2024-02-16T14:47:32.913

701710

|volume|flow-sensor|

<p><span class="math-container">\$ f = 2.5 \times Q\$</span> where <span class="math-container">\$f\$</span> is the frequency and <span class="math-container">\$Q\$</span> is the flow rate in L/min.</p> <p>So if Q = 1 L/min, f = 2.5 Hz which results in 150 pulses for a 1 L flow.</p>

<p>I have a system thet consists of a pump to move the fluid and a solenoid valve to allow the liquid to pass through.</p> <p>I have a flow sensor that has the following characteristics:</p> <p>F = (2.5* Q), Q=L/Min</p> <p>Where Q is the flow rate in liters per minute, and F is the frequency of the signal generated by the sensor in Hz.</p> <p>According to this, the flow would be:</p> <p>Q = L / 60[s].</p> <p>So:</p> <p>F = 2.5*L/60[s].</p> <p>The frequency would be the square signal pulses (P) that occur in 1 second, therefore:</p> <p>P/[s] = L / 24[s] ( 2.5/60 = 1/24)</p> <p>Therefore:</p> <p>L = 24P.</p> <p>Using a pulse counter, I count 24 pulses to obtain one liter (obviously activating and deactivating the pump and the solenoid valve), but the volume obtained is very small.</p> <p><strong>So, in my calculations, something is wrong.</strong></p> <p>Any comment or suggestion is welcome.</p>

Trying to use a flow meter to measure volume

2024-02-16T15:16:08.460

701717

|pcb|circuit-design|zener|

<p>When in doubt, always refer to the <a href="https://www.diodes.com/assets/Datasheets/ds18004.pdf" rel="nofollow noreferrer">data sheet</a> numbers: -</p> <p><a href="https://i.stack.imgur.com/VFs7J.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/VFs7J.png" alt="enter image description here" /></a></p> <p>As you can see, the test current that establishes the Zener voltage (typically 8.2 volts) is 5 mA and, the 700 nA figure refers to the leakage current when only 5 volts is applied.</p> <p>Yes, the table in your question is in error.</p>

<p>What is the point of Zener Diode Current? I have to replace this <a href="https://www.mouser.com/datasheet/2/115/ds18004-1142534.pdf" rel="nofollow noreferrer">BZT52C8V2-7</a> Zener Diode with the current version <a href="https://www.mouser.com/datasheet/2/115/DIOD_S_A0003550684_1-2542352.pdf" rel="nofollow noreferrer">BZT52C8V2-7-F</a> and the Zener Current is 700 nA vs the previous 5mA. What effects would lowering my Zener current have on the circuit and how would I fix this if this would cause an issue?<a href="https://i.stack.imgur.com/EaVGZ.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/EaVGZ.png" alt="enter image description here" /></a></p>

Zener Diode Current Explanation

2024-02-16T16:08:37.340

701734

|switching|

<p>I'm lazy. For this kind of thing, I just grab a chip from my drawer of TC1411s. Lots of other &quot;gate driver&quot; ICs that you could use...</p>

<p>I am using an ESP32 and I want to cut power to a 5 V component which should draw around 80 mA.</p> <p>On my board I have 5 V, so I created two designs:</p> <p>The first one uses an NPN transistor + P-mosfet -&gt; <a href="http://tinyurl.com/275dh5fz" rel="nofollow noreferrer">simulation on Falstad</a></p> <p>The second one uses an N-MOSFET + P-MOSFET -&gt; <a href="http://tinyurl.com/258jal98" rel="nofollow noreferrer">simulation on Falstad</a></p> <p>Both, to the best of my knowledge, seem to do the job.</p> <p>The transistor solution seems to rely heavily on the value of the two resistors on the left. How do I properly size those?</p>

Best circuit to drive +5 V from 3.3 V IC

2024-02-16T18:14:03.700

701735

|diy|powermosfet|to220|

<blockquote> <p>The G and S leads would be bent (slightly) to clear the heatsink.</p> </blockquote> <p>Just a caution, do this carefully, as bending the leads against the body will stress them quite a lot. Get a pair of thin-jaw needle-nose pliers and grasp at the base of the pin, then bend against that. That'll be a safe way to straighten the pins out (or bend them wherever else you need).</p> <p>And then tacking on extension leads of solid wire or whatever to reach the board, is a fine strategy here.</p> <blockquote> <ol> <li>Will the TO-263 case withstand the mounting pressure?</li> </ol> </blockquote> <p>I don't see why not; it's made of the same solid encapsulant as anything else.</p> <blockquote> <ol start="2"> <li>The drain lead is ~1.5 mm long, barely enough lead to solder it seems. Is this too short?</li> </ol> </blockquote> <p>I'd probably avoid using the pin nub, just because it's short and small, prone to breaking, and may have encapsulation on it making soldering difficult.</p> <p>You can just as well lap a wire on the top side of the tab; enough sticks out to solder onto, and the wire length likely doesn't make a difference here (I might be concerned if this was an SMPS). There is some risk of solder flowing around the backside of the tab; avoid getting flux here, and if it ends up lumpy (mind that the native tin plating (when applicable) may itself flow on heating), you can always file or lap the surface flat/smooth again. (If using a file, use a fine flat type; if lapping, use a medium stone that's known to be reasonably flat, or the old wet-or-dry sandpaper on plate glass or the like.) Not that it'll make much of a problem with the Sil-Pads there, really just as long as it's not blobby, it'll be fine.</p> <blockquote> <ol start="3"> <li>Has anyone tried out the above setup or similar and had success?</li> </ol> </blockquote> <p>I can't say I've seen many D(2)PAKs used in maximal power dissipation setups (i.e., they're rated more or less identical as TO-220s, nevermind they're almost always surface-mounted making this spec useless), but aside from the hand work to fit them here, I don't see why not.</p> <p>And it doesn't sound like this is a very powerful application anyway.</p> <blockquote> <ol start="4"> <li>Any obvious limitations that would make this venture too risky?</li> </ol> </blockquote> <p>Not really, other than the jankiness of the solution, which I suppose you're already aware of. I would prefer finding a substitute; but I appreciate that may be easier said than done, or beside the point (&quot;rolling&quot; different types), and in any case isn't the object of this question, so that's fine.</p>

<p>I’m trying to repair an amp where the power MOSFETS (HUF76639) are no longer available in a TO-220 package. They’re currently available in TO-263 package. I’m thinking of adapting the TO-263 package as a solution. The setup is pressing the TO-263s against a vertical heatsink with a bar, insulated by Sil-pad. See photo belows. The G and S leads would be bent (slightly) to clear the heatsink. A 21 AWG wires would be soldered from the leads to the board. Wires would be used to alleviate mechanical stress (between the board and TO-263) on the soldered connections. The questions/concerns I’m running into are</p> <ol> <li>Will the TO-263 case withstand the mounting pressure?</li> <li>The drain lead is ~1.5 mm long, barely enough lead to solder it seems. Is this too short?</li> <li>Has anyone tried out the above setup or similar and had success?</li> <li>Any obvious limitations that would make this venture too risky?</li> </ol> <p>The power MOSFETs on this amp usually stay below 50C. See links for TO-263 and TO-220 case specs. I couldn’t find a datasheet on the TO-263 case mounting pressure. I’m guessing is doesn’t exist since the package is designed to solder onto a board.</p> <p><a href="https://i.stack.imgur.com/cmJMg.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/cmJMg.jpg" alt="enter image description here" /></a></p> <p>[<img src="https://i.stack.imgur.com/XLtFX.jpg" alt="Solder wires to leads][1]" /></p> <p><a href="https://www.onsemi.com/pdf/datasheet/huf76639s3s-d.pdf" rel="nofollow noreferrer">Device - HUF76639S3</a></p> <p><a href="https://www.infineon.com/dgdl/Infineon-Infineon-AN2006_12_Mounting_Considerations_TO220_FullPAK-AN-v2.1-en.pdf-ApplicationNotes-v02_01-EN.pdf?fileId=db3a304320896aa201208a8b700d0029#:%7E:text=The%20recommended%20mounting%20torque%20is,screws%20should%20not%20be%20used.&amp;text=Clip%20mounting%20ensures%20that%20force,and%20thermal%20contact%20is%20good.&amp;text=There%20are%20a%20number%20of,in%20an%20extruded%20heat%20sink." rel="nofollow noreferrer">TO-220 Mount Pressure</a></p> <p><a href="https://www.infineon.com/cms/en/product/packages/PG-TO263/PG-TO263-3-2/" rel="nofollow noreferrer">TO-263 Package</a></p> <p><a href="https://www.infineon.com/cms/en/product/packages/PG-TO220/PG-TO220-3-1/" rel="nofollow noreferrer">TO-220 Package</a></p> <p><a href="https://i.stack.imgur.com/aUuYF.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/aUuYF.jpg" alt="Donor legs held in place from TO-220 package" /></a></p> <p><a href="https://i.stack.imgur.com/ijalR.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/ijalR.jpg" alt="TO-263 with transplanted legs and interconnect for center pin" /></a></p> <p>I used this Molex connector as a sort of cast form soldering the leg to the middle pin, and to align the other two legs for soldering. <a href="https://www.mouser.com/ProductDetail/Molex/560124-0101-Cut-Strip?qs=1YYxJJMLJH1jZhYDkeoY4Q%3D%3D" rel="nofollow noreferrer">https://www.mouser.com/ProductDetail/Molex/560124-0101-Cut-Strip?qs=1YYxJJMLJH1jZhYDkeoY4Q%3D%3D</a></p> <p>So far so good after 1 week. Heat cycling is my main concern.</p> <p><a href="https://i.stack.imgur.com/sTo22.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/sTo22.jpg" alt="enter image description here" /></a></p>

Converting TO-263 to TO-220?

2024-02-16T18:14:33.743

701771

|voltage-regulator|triac|bridge-rectifier|

<p>@Transistor's answer identified that the circuit provides a rapid reset of C1 which it does.</p> <p>I will address that the circuit also provides a mechanism to guarantee that the reset voltage is 0V across the timing capacitor for both positive and negative half cycles.</p> <p>The circuit is reminiscent of a solid state analog switch (Figure 1) used in rf circuits mainly. It can be used for audio if a loud pop can be tolerated during seitching.</p> <p>The dc voltage drop from a to c will be zero even when the on voltage is applied to Vswitch. The circuit switches on with a positive voltage on Vswitch.</p> <p><img src="https://i.stack.imgur.com/sdzid.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fsdzid.png">simulate this circuit</a> &ndash; Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a>}</p> <p>Applying this topology to the ciruit in the OP reveals the circuit in figure 3.</p> <ol> <li>While the triac is conducting, the voltage across the circuit is essentially zero. The diodes D1 and D4 will reverse biased while Node 2 is positive preventing access to Node 1. If Node 2 is negative then diodes D2 and D3 will prevent access to Node 1. Node 2 will be at a voltage (say its negative) below which the diac is off. This voltage (from <span class="math-container">\$\pm\$</span> 5 to 10V) is uncertain and the discharge rate without the diodes is slow.</li> <li>To provide accurate timing based on the R1,R2,C1 series string, the voltage across the capacitor must be set to zero each half cycle. The diode circuit forces this to happen.</li> <li>At the end of the current half cycle the triac turns off allowing the voltage across the circuit to increase (positive in this example) The voltage at Node 2 is still negative but slowly rising to zero. The voltage across at Nodes 3 and 4 are increasing at the line voltage rate. D2 and D4 will be reverse biased. D1 (Node 2 voltage is still negative) and D3 will conduct.</li> <li>This is the important point. The voltage across the diodes will be equal and opposite, <strong>forcing the capacitor voltage to 0v</strong>. The charging current is though R3, D1 and C1.</li> <li>Once at zero volts, the capacitor will charge through R1 and R2. D3 will remain at 0.6V so D1 becomes reverse biased allowing the timing charge to continue from 0V.</li> <li>On the negative half-cycle, Node 2 starts as a positive voltage and is discharged to zero through R4 and D2. D1 and D3 will be reverse biased.</li> </ol> <p><img src="https://i.stack.imgur.com/q3zrK.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fq3zrK.png">simulate this circuit</a>}</p>

<p>Recently I purchased a TRIAC-based mains regulator and took a look inside. It's a very typical TRIAC regulator, except it contains a bridge rectifier (DB207S), the purpose of which is not clear to me at all. Can anyone enlighten me? What are <code>R4</code>, <code>R5</code> and <code>BR1</code> for?</p> <p>Regulator schematic (load not shown): <img src="https://i.stack.imgur.com/lhKDX.png" alt="1" /></p>

What is a bridge rectifier doing in this TRIAC regulator?

2024-02-16T23:53:13.970

701775

|microcontroller|integrated-circuit|pic|embedded|c|

<p>I ended up changing to a <a href="https://ww1.microchip.com/downloads/aemDocuments/documents/MCU08/ProductDocuments/DataSheets/40001799F.pdf" rel="nofollow noreferrer">PIC16F18313</a> instead, but I hope the below details are useful for anyone with the same issue.</p> <p>There are two problems with the original code. The MSSP module is never assigned to any external pins and the <code>_i2c_wait()</code> function is incorrect.</p> <p>To fix the pin assignment issue, the MSSP module is assigned pins RA1 and RA2 using the peripheral pin select module. Both the input and output to the MSSP module must be selected with the PPS module.</p> <pre><code>SSP1CLKPPS = 0x1; /* RA1-&gt;MSSP1:SCL1 */ RA1PPS = 24; /* RA1-&gt;MSSP1:SCL1 */ SSP1DATPPS = 0x2; /* RA2-&gt;MSSP1:SDA1 */ RA2PPS = 25; /* RA2-&gt;MSSP1:SDA1 */ </code></pre> <p>The _i2c_wait() function must monitor the SSP1IF flag. <em>It is not sufficient to monitor whether the bits set in the</em> <code>SSP1CON2</code> <em>register have been cleared.</em></p> <p>The only way to know if the action you have requested has been sent to the bus is to enable the SSP1 interrupt flag bit and poll it.</p> <p><strong>Enable interrupt:</strong></p> <p><code>PIE1bits.SSP1IE = 1; /* Enable SSP1 interrupt */</code></p> <p><strong>Wait for bus action to be completed:</strong></p> <pre><code>void _i2c_wait(void) { while(!PIR1bits.SSP1IF); /* Wait for interrupt generation by MSSP. */ PIR1bits.SSP1IF = 0; /* Clear interrupt bit */ } </code></pre> <p>As a clarification, it is not necessary to implement an ISR, but the MSSP module must be able to set the interrupt flag bits. The global interrupt enable bit also need not be set.</p>

<p>I am trying to implement a basic I2C Master write sequence for a <a href="https://ww1.microchip.com/downloads/aemDocuments/documents/OTH/ProductDocuments/DataSheets/PIC12LF1822-16LF1823-Data-Sheet-40001413F.pdf" rel="nofollow noreferrer">PIC12F1822</a> Microcontroller. I am programming the device using the PICKit 3 programmer.</p> <p>I have heavily simplified the code to isolate the problem, however I cannot seem to narrow down the solution.</p> <p><strong>What I expect to happen:</strong></p> <ol> <li>The bus lines are initially low, where TRISA = 0.</li> <li>The TRISA1 and TRISA2 are set to 1 and the MSSP module is enabled in I2C mode, bringing the SDA/SCL lines high.</li> <li>A start condition occurs, followed by data, then a stop condition.</li> <li>TRISA1 and TRISA2 are set to 0, causing the SDA/SCL lines to go low.</li> <li>A 50ms pause occurs, before starting from step 1.</li> </ol> <p><strong>What actually happens:</strong></p> <p>The SDA/SCL lines are low, then go high for a short duration, before going low again. There is no start condition, data or stop condition.</p> <p><strong>What I have tried:</strong></p> <p>I have tried different methods of addressing the MSSP registers, (i.e. SSP1CON2 = 0x01 instead of SEN = 1), and the debugger shows the SFRs are written to correctly.</p> <p>I have provided logic analyser output below to illustrate the problem. The two peaks are ~50ms apart, and the SDA and SCL peaks begin at identical points in time. I have observed no bus capacitance issues when using an oscilloscope.</p> <p>I am a PIC novice (though have a decent amount of experience on other platforms), and suspect that I have simply omitted a register set somewhere. Anyway, this issue is driving me nuts, and I would very much appreciate anyone who might help!</p> <p><strong>The code:</strong></p> <pre><code>#include &quot;config_bits.h&quot; #include &lt;xc.h&gt; #define _XTAL_FREQ 4000000 /* Clock frequency */ void _i2c_wait(void) { /* Wait for transmission to finish OR Wait for start/stop condition clear */ while(SSP1STAT &amp; 0x04 || SSP1CON2 &amp; 0x1F); } void main(void) { /* --- Config --- */ /* Disable Watchdog Timer */ WDTCON = 0; /* Set up Internal 4MHz HF osc */ OSCCON = 0b01101010; /* Disable ADC */ ANSELA = 0; WPUA = 0; uint8_t data = 115; while(1) { TRISA = 0x06; /* Enable RA1 and RA2 as input */ SSP1CON1 = 0b00101000; /* Enable MSSP, Enable I2C with 7-bit addresses */ SSP1CON2 = 0; /* Disable general call interrupt */ SSP1STAT = 0; SSP1ADD = 0x09; /* Divide 4MHz clock to 100kHz */ /* Send start condition */ SEN = 1; _i2c_wait(); PIR1bits.SSP1IF = 0; /* Write data, wait until finished */ SSP1BUF = data; _i2c_wait(); /* Send stop condition */ PEN = 1; _i2c_wait(); SSP1CON1 = 0; /* Disables I2C pins */ TRISA = ~0x06; __delay_ms(50); } return; } </code></pre> <p><strong>Logic Analyser Output:</strong></p> <p><a href="https://i.stack.imgur.com/gLIyb.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/gLIyb.png" alt="Logic Analyser Output" /></a></p> <p><strong>Config Bits:</strong></p> <pre><code>// CONFIG 1 Here are my configuration bits: #pragma config FOSC = INTOSC // Oscillator Selection (INTOSC oscillator: I/O function on CLKIN pin) #pragma config WDTE = OFF // Watchdog Timer Enable (WDT disabled) #pragma config PWRTE = OFF // Power-up Timer Enable (PWRT disabled) #pragma config MCLRE = ON // MCLR Pin Function Select (MCLR/VPP pin function is MCLR) #pragma config CP = OFF // Flash Program Memory Code Protection (Program memory code protection is disabled) #pragma config CPD = OFF // Data Memory Code Protection (Data memory code protection is disabled) #pragma config BOREN = ON // Brown-out Reset Enable (Brown-out Reset enabled) #pragma config CLKOUTEN = OFF // Clock Out Enable (CLKOUT function is disabled. I/O or oscillator function on the CLKOUT pin) #pragma config IESO = OFF // Internal/External Switchover (Internal/External Switchover mode is enabled) #pragma config FCMEN = ON // Fail-Safe Clock Monitor Enable (Fail-Safe Clock Monitor is enabled) // CONFIG2 #pragma config WRT = OFF // Flash Memory Self-Write Protection (Write protection off) #pragma config PLLEN = OFF // PLL Enable (4x PLL enabled) #pragma config STVREN = ON // Stack Overflow/Underflow Reset Enable (Stack Overflow or Underflow will cause a Reset) #pragma config BORV = LO // Brown-out Reset Voltage Selection (Brown-out Reset Voltage (Vbor), low trip point selected.) #pragma config DEBUG = OFF // In-Circuit Debugger Mode (In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger) #pragma config LVP = ON // Low-Voltage Programming Enable (Low-voltage programming enabled) </code></pre>

Why is no data written to the I2C bus using this PIC12LF1822 code?

2024-02-17T02:48:52.193

701776

|computer-architecture|

<p>This one is easy. It says <em>&quot;(b) In a memory location associated with the call, so that a different location is used when the subroutine <strong>is called from different places</strong>&quot;</em>.</p> <p>In the case of recursion, successive calls may come from the <em><strong>same place</strong></em>.</p> <h3>added</h3> <p>No one said that the machine architecture for <em>case (b)</em> makes a lot of sense or is an easy one to construct and make functional.</p> <p>But suppose there exists a special 8-bit return address key register called X0 that the return instruction uses and suppose a call instruction performs the following steps:</p> <ol> <li><p>TEMP = HASH8(subroutine address, call instruction address)</p> <p>Here, HASH8 is some hardware block that generates an 8-bit hash code from the 16-bit subroutine address and the 16-bit target address of the call instruction.</p> <p>It is assumed to be <em>unlikely</em> that the same HASH8 generates unwanted collisions (given whatever justification someone comes up with.)</p> <p>However, the same call located at the same instruction address making a call to the same subroutine <em><strong>will</strong></em> produce the same HASH8.</p> </li> <li><p>R[TEMP]= 16-bit return address from call</p> <p>R[] is a 16-bit wide data memory with an 8-bit address.</p> </li> <li><p>X[TEMP]= X0</p> <p>X[] is an 8-bit wide data memory with an 8-bit address.</p> </li> <li><p>X0 = TEMP</p> </li> <li><p>PC = 16-bit address of called subroutine</p> </li> </ol> <p>Suppose the return instruction performs:</p> <ol> <li><p>TEMP = X0</p> </li> <li><p>X0 = X[TEMP]</p> </li> <li><p>PC = R[TEMP]</p> </li> </ol> <p>Don't ask me why anyone would do it this way. I just made it up. But it does match <em>case (b)</em> in your example.</p> <p>Hopefully, now you can see the problem with recursion in a situation posed by <em>case (b)</em>.</p> <p>By the way, the HP21xx series of CPUs would literally <em><strong>blow away</strong></em> the first address of any called subroutine with the return address of the caller. (No stacks here!) A subroutine would look something like this:</p> <pre><code>FDATE NOP This location gets overwritten with return address of caller. LDA FILE# Subroutine always starts here. SSA,RSS . . . JMP FDATE,I Return from call. </code></pre> <p>All calls blow away the first address with the return address and then always start the subroutine at addr+1.</p> <p>Now, that certainly doesn't support recursion!</p>

<p>My text (<em>Computer Organization and Embedded Systems</em>, 6e, by Hamacher et al.) poses the following:</p> <blockquote> <p>Consider the following possibilities for saving the return address of a subroutine:<br /> (a) In a processor register<br /> (b) In a memory location associated with the call, so that a different location is used when the subroutine is called from different places<br /> (c) On a stack</p> </blockquote> <p>and says that the answer options are:</p> <blockquote> <p>(a) Neither nesting nor recursion are supported.<br /> (b) Nesting is supported, because different Call instructions will save the return address at different memory locations. Recursion is not supported.<br /> (c) Both nesting and recursion are supported.</p> </blockquote> <p>I cannot understand the comment regarding (b).</p> <p>Suppose our solution was (a).</p> <p>This works for a case where we go &quot;one level deep&quot; but if we nest or recurse then everything except the very last calling function will have the correct returning address clobbered. No problem.</p> <p>But what of (b)? Is the proposition that every subroutine call would cause the address of the next instruction after the call to be stored somewhere which is a (injective) function of the memory address of the call? If so, where does the problem arise with recursion? I think maybe I'm not getting my arms around even what we're talking about when we say &quot;memory location associated with the call&quot;.</p>

Why does saving addresses on a stack give us the only way out for both nesting and "recursing" subroutines?

2024-02-17T03:47:09.007

701806

|arduino|uart|serial|esp32|flash|

<p>The TXD pin on Arduino is MCU TXD out to RXD of PC.</p> <p>You need to connect the TXD output of ESP32 to TXD pin of Arduino in order for the PC to receive data.</p> <p>So connect TXD to TXD and RXD to RXD.</p> <p>The UNO R3 has 1k protection resistors so connecting 5V logic output to 3.3V logic input should not do damage, but it is not ideal. The 5V logic input should detect 3.3V logic output properly as the R3 uses ATMega16U2 as USB serial adapter IC.</p>

<p>I'm looking for help to upload from Arduino IDE into an ESP32-CAM module, without an FTDI programmer or shield.</p> <h1>Context</h1> <p>I've got a couple of ESP32-CAM modules with an associated ESP32-CAM-MB shield for programming via micro USB. Unfortunately the CH340-based programmer is not recognized by Windows. I know there are drivers around, but for security reasons I don't want to install random drivers downloaded from the Internet. I appreciate I'm maybe making my life harder here, but I'm strict about security, and I also like to learn.</p> <p>The next popular option would be an FTDI programmer, but I'm afraid I'd end up in the same situation with missing drivers.</p> <p>So my current strategy would be to use another board. I have some Arduino Uno R3 or ESP32-WROOM; I know the Arduino works so I'd like to try that one.</p> <h1>What I've tried</h1> <h2>ESP32-CAM-MB shield</h2> <p>The shield doesn't show up in Device Manager in Windows.</p> <h2>Arduino UART</h2> <ul> <li>Connect Arduino and ESP32-CAM: Tx-&gt;Rx and Rx-&gt;Tx, for Serial connection, and 5V and GND for power.</li> <li>Jumper on ESP32-CAM module between IO0 and GND to allow flashing.</li> <li>With or without jumper on Arduino RESET-GND, to pin Reset down, as I understand this may help prevent the Arduino from running. Although I'm not sure, I couldn't find any documentation about this.</li> </ul> <p><em>Edit:</em> Like this: <img src="https://technoreview85.com/wp-content/uploads/2019/08/web2-1024x608.jpg" alt="this" />.</p> <p>Setting transfer rate to 115200 baud.</p> <p>When trying in Arduino IDE, I get the same Connection timeout error (error 2). It seems nothing happens. I've tried pressing the Boot button too, without success.</p> <p>I've looked at other questions here, and online tutorials, but in general either they cover generic UART transfer (not for programming), or they are very vague and don't explain <em>why</em> the steps are needed, which makes it hard to debug what goes wrong. In particular I couldn't find a single resource confirming that this setup is even possible, and how the Arduino will understand that it needs to forward what it receives from USB over to UART to the ESP32, but I saw several tutorials saying it &quot;just works&quot;. So any help or hint, link at resources or docs, would be much appreciated.</p>

ESP32-CAM flash via UART

2024-02-17T11:24:38.290

701815

|multiplexer|

<h2>Issues with schematic in the question</h2> <p>The schematic in the question shows:</p> <ol> <li>3.3 V connected to the <code>V+</code> pin of the <a href="https://www.analog.com/en/products/max4644.html" rel="nofollow noreferrer">MAX4644</a>.</li> <li>5 V connected to the <code>NC</code> pin of the MAX4644</li> </ol> <p>I.e. the voltage on the <code>NC</code> pin is greater than that on <code>V+</code> pin by 1.7 V. From the ABSOLUTE MAXIMUM RATINGS of the <a href="https://www.analog.com/media/en/technical-documentation/data-sheets/MAX4644.pdf" rel="nofollow noreferrer">datasheet</a> this is not allowed, and will cause the internal ESD diodes to conduct:</p> <p><a href="https://i.stack.imgur.com/17jsd.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/17jsd.png" alt="enter image description here" /></a></p> <p>Also, the maximum continuous current of the MAX4644 is ±20mA which is less than the 80 mA current draw of the load.</p> <h2>Consider a Load Switch, instead of an Analog Switch</h2> <p>The question considers an <em>Analog Switch</em> which is not really intended to power loads.</p> <p>A <em>Load Switch</em> is probably a better option. TI (for example) provide a range of <em>Load Switch</em> devices, with different number of channels, maximum current and maximum voltages. <a href="https://www.ti.com/power-management/power-switches/load-switches/products.html#480=1%3B1&amp;1685=0.08%3B0.5&amp;" rel="nofollow noreferrer">Load switches</a> is the list filtered for:</p> <ul> <li>A single channel</li> <li>Maximum current in the range 0.08 A to 0.5 A</li> </ul> <p>For which at the time of answering there are 13 products matching the selection.</p> <p>Picked the <a href="https://www.ti.com/product/TPS22948" rel="nofollow noreferrer">TPS22948 5.5-V, 240-mA Current Limited Load Switch with Reverse Current Blocking</a> as an example, which has the following characteristics which should be meet the requirements in the question:</p> <ol> <li>Input operating voltage range 2.5 V to 5.5 V</li> <li>Maximum current of 240 mA</li> <li>ON-Resistance (RON): 450 mΩ (max -40°C to 85°C), so drops a maximum of 36 mV at 80 mA.</li> <li>The TPS22948 <a href="https://www.ti.com/lit/ds/symlink/tps22948.pdf" rel="nofollow noreferrer">datasheet</a> shows the V_IH ON Pin High Voltage Range min 1 V. This is compatible with a 3.3 V GPIO from the ESP32; the ESP32 <a href="https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf" rel="nofollow noreferrer">datasheet</a> shows V_OH High-level output voltage as 0.8×VDD.</li> <li>6-Pin SC-70 package, so similar to the 6 pin SOT23 package of the MAX4644EUT.</li> <li>When power is first applied, a smart pull down is used to keep the ON pin from floating until system sequencing is complete.</li> </ol>

<p>I've a module that operates at +5V.</p> <p>Instead of using 2x MOSFET or transistor + MOSFET to drive the MODULE.VCCIN either +5v / gnd, can I use the MAX4644 instead?</p> <p><img src="https://i.stack.imgur.com/qGoBp.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fqGoBp.png">simulate this circuit</a> &ndash; Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a>}</p> <p>In this schematic I would drive either NO or NC to COM by using an ESP32.IO pin.</p> <p>Edit: the 5V module is going to draw 80mA. If max is not right is there an IC much like this one that i could use within datasheet spec?</p>

Can I use MAX4644EUT to drive pin high or low?

2024-02-17T14:02:19.730

701827

|mosfet|capacitor|spice|parasitic-capacitance|

<p>First, to make things easier, I reconstructed your LTspice schematic such that both versions you are trying to compare are within the same simulation. That way you can probe both outputs at the same time and compare the results more easily. I've included the text of my <code>.asc</code> file below if you want to run it yourself.</p> <p><em>NOTE: Be careful when copying large blocks of schematic over like this. You have to be aware that even though reference designators will be changed on the copies of components, node labels WILL NOT. So you have to edit the node labels on the copy if you don't want those nodes to be shorted together.</em> <a href="https://i.stack.imgur.com/ZDJ5I.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/ZDJ5I.png" alt="enter image description here" /></a></p> <pre><code>Version 4 SHEET 1 1076 1044 WIRE -224 16 -368 16 WIRE 32 16 -224 16 WIRE 1008 16 864 16 WIRE -368 32 -368 16 WIRE 864 32 864 16 WIRE 864 128 864 112 WIRE 864 128 720 128 WIRE 864 144 864 128 WIRE 928 144 864 144 WIRE -368 160 -368 112 WIRE -304 160 -368 160 WIRE -368 176 -368 160 WIRE -368 176 -384 176 WIRE 720 176 720 128 WIRE 864 176 864 144 WIRE 864 176 848 176 WIRE 912 176 864 176 WIRE -368 208 -368 176 WIRE 864 208 864 176 WIRE 912 208 912 176 WIRE 944 208 912 208 WIRE 1056 208 1008 208 WIRE -240 256 -368 256 WIRE 32 256 32 16 WIRE 192 256 192 208 WIRE 352 256 352 208 WIRE 1056 256 1056 208 WIRE 1056 256 864 256 WIRE -608 288 -656 288 WIRE -576 288 -608 288 WIRE -464 288 -464 176 WIRE -464 288 -496 288 WIRE -416 288 -464 288 WIRE 608 288 592 288 WIRE 720 288 720 240 WIRE 720 288 688 288 WIRE 768 288 768 176 WIRE 768 288 720 288 WIRE 816 288 768 288 WIRE -656 320 -656 288 WIRE -368 320 -368 304 WIRE -352 320 -368 320 WIRE -368 336 -368 320 WIRE 768 352 768 288 WIRE 864 352 864 304 WIRE 864 352 832 352 WIRE 896 352 864 352 WIRE 944 352 896 352 WIRE 1056 352 1056 256 WIRE 1056 352 1008 352 WIRE 864 400 864 352 WIRE 1056 400 1056 352 WIRE -656 432 -656 400 WIRE -368 432 -368 416 WIRE -368 432 -656 432 WIRE -240 432 -240 256 WIRE -240 432 -368 432 WIRE 32 432 32 336 WIRE 32 432 -240 432 WIRE 192 432 192 336 WIRE 192 432 32 432 WIRE 352 432 352 336 WIRE 352 432 192 432 WIRE 896 432 896 352 WIRE 928 432 896 432 WIRE -656 448 -656 432 WIRE 864 496 864 480 FLAG -656 448 0 FLAG -224 16 VDD FLAG -464 288 VG1 FLAG -304 160 VO1 IOPIN -304 160 Out FLAG 192 208 Vicm FLAG 352 208 Vid FLAG -608 288 VIN FLAG -352 320 VS1 IOPIN -352 320 Out FLAG 1008 16 VDD FLAG 768 288 VG2 FLAG 928 144 VO2 IOPIN 928 144 Out FLAG 592 288 VIN FLAG 1056 400 0 FLAG 864 496 0 FLAG 928 432 VS2 IOPIN 928 432 Out SYMBOL nmos4 -416 208 R0 WINDOW 3 56 60 Left 2 SYMATTR Value NMOS-SH1 SYMATTR InstName M1 SYMATTR Value2 l=1u w=12.35u ad=6.2p as=6.2p pd=13.4u ps=13.4u SYMBOL voltage 32 240 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName VDD SYMATTR Value 1.2 SYMBOL voltage 192 240 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName Vicm SYMATTR Value 0.69 SYMBOL voltage 352 240 R0 WINDOW 3 24 152 Left 2 WINDOW 123 24 124 Left 2 WINDOW 39 0 0 Left 0 SYMATTR Value 0 SYMATTR Value2 AC 1 SYMATTR InstName Vid SYMBOL bv -656 304 R0 WINDOW 0 -86 24 Left 2 SYMATTR InstName VIN1 SYMATTR Value V=V(Vicm)+V(Vid) SYMBOL res -368 160 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName Rf1 SYMATTR Value 10k SYMBOL res -384 16 R0 SYMATTR InstName RD1 SYMATTR Value 1k SYMBOL res -480 272 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName RG1 SYMATTR Value 1k SYMBOL res -384 320 R0 SYMATTR InstName RS1 SYMATTR Value 1k SYMBOL nmos4 816 208 R0 WINDOW 3 56 60 Left 2 SYMATTR Value NMOS-SH2 SYMATTR InstName M2 SYMATTR Value2 l=1u w=12.35u ad=6.2p as=6.2p pd=13.4u ps=13.4u SYMBOL res 864 160 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName Rf2 SYMATTR Value 10k SYMBOL res 848 16 R0 SYMATTR InstName RD2 SYMATTR Value 1k SYMBOL res 880 496 R180 WINDOW 0 36 76 Left 2 WINDOW 3 36 40 Left 2 SYMATTR InstName RS2 SYMATTR Value 1k SYMBOL cap 832 336 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName Cgs SYMATTR Value 74.68e-15 SYMBOL cap 704 176 R0 WINDOW 0 -30 6 Left 2 WINDOW 3 -86 51 Left 2 SYMATTR InstName Cgd SYMATTR Value 3.58e-15 SYMBOL res 704 272 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName RG2 SYMATTR Value 1k SYMBOL cap 1008 192 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName Cbd SYMATTR Value 2.16e-14 SYMBOL cap 1008 336 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName Cbs SYMATTR Value 3.19e-14 TEXT -528 -152 Left 2 !.MODEL NMOS-SH1 nmos(kp=180u,vto=0.4, lambda = {0.1/1}, gamma = 0.5, phi = 0.7\n+TOX=4.0n CGSO=0.29n CGBO=0 CGDO=0.29n CJ=3.65m CJSW=0.79n) TEXT -496 -184 Left 2 ;M1: l=1u w=12.35u ad=6.2p as=6.2p pd=13.4u ps=13.4u TEXT -688 48 Left 2 !.op\n.ac oct 10 100MEG 100G TEXT -688 24 Left 2 !;tf V(VO) Vid TEXT -688 0 Left 2 !;dc VDD 0 1.8 0.01 TEXT -528 -80 Left 2 !.MODEL NMOS-SH2 nmos(kp=180u,vto=0.4, lambda = {0.1/1}, gamma = 0.5, phi = 0.7) </code></pre> <hr /> <p>I spent several hours looking for what could be the discrepancy between the plots and couldn't find it. I've included a photo below from page 213 of <a href="https://books.google.com/books/about/Semiconductor_Device_Modeling_with_SPICE.html?id=_QZTAAAAMAAJ" rel="nofollow noreferrer">Semiconductor Device Modeling with SPICE</a>, which shows the small signal model for the Level 1/2/3 SPICE MOSFET. As long as your <code>RD</code> (drain resistance) and <code>RS</code> (source resistance) parameters are zero (and they are), your external capacitor version should match the internal capacitor one.</p> <p><a href="https://i.stack.imgur.com/cb7I0.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/cb7I0.jpg" alt="enter image description here" /></a></p> <p>Just for a sanity check I ran this simulation in various versions of LTspice which all produced the same results. I also ran it in <a href="https://ngspice.sourceforge.io/" rel="nofollow noreferrer">ngspice</a> and this is where it gets interesting. It produced results where the plots line up exactly on top of each other, which is what you would expect. Easiest way to run this is to put the below netlist into a file and drag/drop that file onto <code>ngspice.exe</code>.</p> <p><a href="https://i.stack.imgur.com/w23Cq.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/w23Cq.png" alt="enter image description here" /></a></p> <pre><code>* small signal MOSFET capacitance test M1 VO1 VG1 VS1 0 NMOS-SH1 l=1u w=12.35u ad=6.2p as=6.2p pd=13.4u ps=13.4u VDD VDD 0 1.2 Vicm Vicm 0 0.69 Vid Vid 0 0 AC 1 B§VIN1 VIN 0 V=V(Vicm)+V(Vid) Rf1 VO1 VG1 10k RD1 VDD VO1 1k RG1 VG1 VIN 1k RS1 VS1 0 1k M2 VO2 VG2 VS2 0 NMOS-SH2 l=1u w=12.35u ad=6.2p as=6.2p pd=13.4u ps=13.4u Rf2 VO2 VG2 10k RD2 VDD VO2 1k RS2 0 VS2 1k Cgs VS2 VG2 74.68e-15 Cgd VO2 VG2 3.58e-15 RG2 VG2 VIN 1k Cbd 0 VO2 2.16e-14 Cbs 0 VS2 3.19e-14 .MODEL NMOS-SH1 nmos(kp=180u,vto=0.4, lambda = {0.1/1}, gamma = 0.5, phi = 0.7 +TOX=4.0n CGSO=0.29n CGBO=0 CGDO=0.29n CJ=3.65m CJSW=0.79n) .ac oct 10 100MEG 100G .MODEL NMOS-SH2 nmos(kp=180u,vto=0.4, lambda = {0.1/1}, gamma = 0.5, phi = 0.7) .control run plot vdb(vo1), vdb(vo2) .endc </code></pre> <hr /> <p>There's definitely something going on here. I suggest emailing <code>LTspice@analog.com</code> and bringing this to their attention in case it's a bug of some kind. You can also try running it by the people over at the <a href="https://groups.io/g/LTspice" rel="nofollow noreferrer">LTspice Google Groups</a>. They know a lot of the inner workings of LTspice, short of knowing the actual source code.</p>

<p>This is a circuit which has parasitic capacitors:</p> <p><a href="https://i.stack.imgur.com/yWa5B.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/yWa5B.png" alt="enter image description here" /></a></p> <pre><code>--- MOSFET Transistors --- Name: m1 Model: nmos-sh Id: 6.91e-05 Vgs: 6.58e-01 Vds: 1.03e+00 Vbs: -6.91e-02 Vth: 4.20e-01 Vdsat: 2.37e-01 Gm: 5.82e-04 Gds: 6.27e-06 Gmb: 1.66e-04 Cbd: 2.16e-14 Cbs: 3.19e-14 Cgsov: 3.58e-15 Cgdov: 3.58e-15 Cgbov: 0.00e+00 Cgs: 7.11e-14 Cgd: 0.00e+00 Cgb: 0.00e+00 </code></pre> <pre><code>Version 4 SHEET 1 936 680 WIRE 224 160 80 160 WIRE 480 160 224 160 WIRE 80 176 80 160 WIRE 80 304 80 256 WIRE 144 304 80 304 WIRE 80 320 80 304 WIRE 80 320 64 320 WIRE 80 352 80 320 WIRE 144 400 80 400 WIRE 640 400 640 352 WIRE 800 400 800 352 WIRE -160 432 -208 432 WIRE -128 432 -160 432 WIRE -16 432 -16 320 WIRE -16 432 -48 432 WIRE 32 432 -16 432 WIRE 480 432 480 160 WIRE 80 464 80 448 WIRE 96 464 80 464 WIRE 80 480 80 464 WIRE -208 624 -208 512 WIRE 80 624 80 560 WIRE 80 624 -208 624 WIRE 144 624 144 400 WIRE 144 624 80 624 WIRE 480 624 480 512 WIRE 480 624 144 624 WIRE 640 624 640 480 WIRE 640 624 480 624 WIRE 800 624 800 480 WIRE 800 624 640 624 WIRE -208 640 -208 624 FLAG -208 640 0 FLAG 224 160 VDD FLAG -16 432 VG FLAG 144 304 VO IOPIN 144 304 Out FLAG 640 352 Vicm FLAG 800 352 Vid FLAG -160 432 VIN FLAG 96 464 VS IOPIN 96 464 Out SYMBOL nmos4 32 352 R0 WINDOW 3 56 60 Left 2 SYMATTR Value NMOS-SH SYMATTR InstName M1 SYMATTR Value2 l=1u w=12.35u ad=6.2p as=6.2p pd=13.4u ps=13.4u SYMBOL voltage 480 416 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName VDD SYMATTR Value 1.2 SYMBOL voltage 640 384 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName Vicm SYMATTR Value 0.69 SYMBOL voltage 800 384 R0 WINDOW 3 24 152 Left 2 WINDOW 123 24 124 Left 2 WINDOW 39 0 0 Left 0 SYMATTR Value 0 SYMATTR Value2 AC 1 SYMATTR InstName Vid SYMBOL bv -208 416 R0 WINDOW 0 -60 23 Left 2 SYMATTR InstName VIN1 SYMATTR Value V=V(Vicm)+V(Vid) SYMBOL res 80 304 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName Rf1 SYMATTR Value 10k SYMBOL res 64 160 R0 SYMATTR InstName RD SYMATTR Value 1k SYMBOL res -32 416 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName RG SYMATTR Value 1k SYMBOL res 64 464 R0 SYMATTR InstName RS SYMATTR Value 1k TEXT -80 -8 Left 2 !.MODEL PMOS-SH pmos(kp=45u,vto=-0.42, lambda = {0.1/1}, gamma = 0.5, phi = 0.7\n+TOX=4.0n CGSO=0.28n CGBO=0 CGDO=0.28n CJ=1.38m CJSW=1.44n) TEXT -80 48 Left 2 !.MODEL NMOS-SH nmos(kp=180u,vto=0.4, lambda = {0.1/1}, gamma = 0.5, phi = 0.7\n+TOX=4.0n CGSO=0.29n CGBO=0 CGDO=0.29n CJ=3.65m CJSW=0.79n) TEXT -48 -40 Left 2 ;M1: l=1u w=12.35u ad=6.2p as=6.2p pd=13.4u ps=13.4u TEXT -240 192 Left 2 !.op\n.ac oct 10 100MEG 100G TEXT -240 168 Left 2 !;tf V(VO) Vid TEXT -240 144 Left 2 !;dc VDD 0 1.8 0.01 </code></pre> <p>AC frequency analysis:</p> <p><a href="https://i.stack.imgur.com/hBgKB.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/hBgKB.png" alt="enter image description here" /></a></p> <p><a href="https://i.stack.imgur.com/OO4Se.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/OO4Se.png" alt="enter image description here" /></a></p> <p>I tried to build an equivalent circuit in SPICE with external capacitors.</p> <p><a href="https://i.stack.imgur.com/GuciB.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/GuciB.png" alt="enter image description here" /></a></p> <pre><code>Version 4 SHEET 1 880 680 WIRE -64 -64 -208 -64 WIRE 192 -64 -64 -64 WIRE -208 -48 -208 -64 WIRE -208 80 -208 32 WIRE -208 80 -352 80 WIRE -144 80 -208 80 WIRE -352 96 -352 80 WIRE -208 96 -208 80 WIRE -208 96 -224 96 WIRE -208 112 -208 96 WIRE -144 112 -208 112 WIRE -208 128 -208 112 WIRE -144 176 -208 176 WIRE -80 176 -144 176 WIRE 352 176 352 128 WIRE 512 176 512 128 WIRE -80 192 -80 176 WIRE -448 208 -496 208 WIRE -352 208 -352 160 WIRE -352 208 -368 208 WIRE -304 208 -304 96 WIRE -304 208 -352 208 WIRE -256 208 -304 208 WIRE 192 208 192 -64 WIRE -304 256 -304 208 WIRE -208 256 -208 224 WIRE -208 256 -240 256 WIRE -112 256 -208 256 WIRE -80 256 -112 256 WIRE -208 288 -208 256 WIRE -112 288 -112 256 WIRE -496 400 -496 288 WIRE -208 400 -208 368 WIRE -208 400 -496 400 WIRE -144 400 -144 176 WIRE -144 400 -208 400 WIRE 192 400 192 288 WIRE 192 400 -144 400 WIRE 352 400 352 256 WIRE 352 400 192 400 WIRE 512 400 512 256 WIRE 512 400 352 400 WIRE -496 416 -496 400 FLAG -496 416 0 FLAG -64 -64 VDD FLAG -304 208 VG FLAG -144 80 VO IOPIN -144 80 Out FLAG 352 128 Vicm FLAG 512 128 Vid FLAG -496 208 VIN FLAG -112 288 VS IOPIN -112 288 Out SYMBOL nmos4 -256 128 R0 WINDOW 3 56 60 Left 2 SYMATTR Value NMOS-SH SYMATTR InstName M1 SYMATTR Value2 l=1u w=12.35u ad=6.2p as=6.2p pd=13.4u ps=13.4u SYMBOL voltage 192 192 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName VDD SYMATTR Value 1.2 SYMBOL voltage 352 160 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName Vicm SYMATTR Value 0.69 SYMBOL voltage 512 160 R0 WINDOW 3 24 152 Left 2 WINDOW 123 24 124 Left 2 WINDOW 39 0 0 Left 0 SYMATTR Value 0 SYMATTR Value2 AC 1 SYMATTR InstName Vid SYMBOL bv -496 192 R0 WINDOW 0 -91 59 Left 2 WINDOW 3 -132 101 Left 2 SYMATTR InstName VIN1 SYMATTR Value V=V(Vicm)+V(Vid) SYMBOL res -208 80 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName Rf SYMATTR Value 10k SYMBOL res -224 -64 R0 SYMATTR InstName RD SYMATTR Value 1k SYMBOL res -352 192 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName RG SYMATTR Value 1k SYMBOL res -224 272 R0 SYMATTR InstName RS SYMATTR Value 1k SYMBOL cap -240 240 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName Cgs SYMATTR Value 74.68e-15 SYMBOL cap -160 112 R0 WINDOW 0 -30 12 Left 2 WINDOW 3 38 32 Left 2 SYMATTR InstName Cbd SYMATTR Value 2.16e-14 SYMBOL cap -368 96 R0 WINDOW 0 -31 6 Left 2 WINDOW 3 -36 53 Left 2 SYMATTR InstName Cgd SYMATTR Value 3.58e-15 SYMBOL cap -96 192 R0 SYMATTR InstName Cbs SYMATTR Value 3.19e-14 TEXT -528 -32 Left 2 !.op\n.ac oct 10 100MEG 100G TEXT -528 -56 Left 2 !;tf V(VO) Vid TEXT -528 -80 Left 2 !;dc VDD 0 1.8 0.01 TEXT -384 -184 Left 2 !.MODEL PMOS-SH pmos(kp=45u,vto=-0.42, lambda = {0.14/1}, gamma = 0.5, phi = 0.7) TEXT -384 -152 Left 2 !.MODEL NMOS-SH nmos(kp=180u,vto=0.4, lambda = {0.1/1}, gamma = 0.5, phi = 0.7) TEXT -352 -216 Left 2 ;M1: l=1u w=12.35u ad=6.2p as=6.2p pd=13.4u ps=13.4u </code></pre> <p>AC frequency analysis:</p> <p><a href="https://i.stack.imgur.com/XwaOu.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/XwaOu.png" alt="enter image description here" /></a></p> <p><a href="https://i.stack.imgur.com/iqnu1.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/iqnu1.png" alt="enter image description here" /></a></p> <p>Why do this two circuits differ?</p>

Replacing MOS parasitic cap with external cap. Why does it differ from internal?

2024-02-17T15:35:47.497

701847

|digital-logic|verilog|simulation|flipflop|vivado|

<p>A couple of issues.</p> <p>Use only blocking assignments in making assignments to your clock; do not use nonblocking.</p> <p>Waveforms do not always give you a good pitcure of exactly when assignments are made in each region of the Verilog event scheduler. It's hard to see if values are coming in before or after the clock edge. In your case <code>req_i</code> is being set before the <code>posedge clk</code> (because you used an NBA to assign the clk) and you are seeing the updated value of <code>ack</code> after the clock edge.</p> <p>It is a better practice to offset your stimulus by a few ns or use the negedge of the clock. Or make sure both TB and DUT use the same clock, use NBA assignments to ALL sequential signals.</p>

<p>Code for a counters Verilog file: (Go to: <code>THE LINE OF ISSUE</code>)</p> <pre><code>module atomic_counters ( input wire clk, input wire reset, input wire trig_i, input wire req_i, input wire atomic_i, output wire ack_o, output wire[31:0] count_o ); wire [63:0] count; // -------------------------------------------------------- // DO NOT CHANGE ANYTHING HERE // -------------------------------------------------------- reg [63:0] count_q; always @(posedge clk or posedge reset) if (reset) count_q[63:0] &lt;= 64'h0; else count_q[63:0] &lt;= count; // -------------------------------------------------------- // Write your logic here reg [63:0] counter; reg [31:0] counter_32_upp; reg [31:0] counter_32_low; reg state; reg ack; reg ack1; reg reset_ff; reg reset_ff1; reg low_or_high; localparam FIRST = 1'd0; localparam SECOND = 1'd1; assign ack_o = ack; assign count_o = counter[31:0]; always @(posedge clk or posedge reset) begin if (reset) begin ack &lt;= 0; ack1 &lt;= 0; end else begin ack &lt;= req_i; // THE LINE OF ISSUE ack1 &lt;= ack; end end endmodule </code></pre> <p>Code for the testbench:</p> <pre><code>module counters_tb_verilog(); `define TC1 reg clk; reg reset; reg trig_i; reg req_i; reg atomic_i; reg tc1_or_tc2; wire ack_o; wire [31:0] count_o; atomic_counters ac ( .clk ( clk ), .reset ( reset ), .trig_i ( trig_i ), .req_i ( req_i ), .atomic_i ( atomic_i ), .ack_o ( ack_o ), .count_o ( count_o ) ); always #5 clk &lt;= ~clk; // Commeting due to sim error /* `ifdef TC1 assign ac.count = 32'h0; `elsif TC2 assign ac.count = 32'hfff_ffff5; `endif */ assign ac.count = (tc1_or_tc2) ? 32'hfff_ffff5 : 32'h0; task test_case_1(); begin #15; trig_i &lt;= 1; #100; trig_i &lt;= 0; #50; req_i = 1; atomic_i &lt;= 1; #10; req_i = 0; atomic_i &lt;= 0; #10; trig_i &lt;= 1; #80; req_i = 1; #10; atomic_i &lt;= 1; #10; atomic_i &lt;= 0; #10; req_i = 0; #50; $stop; end endtask initial begin clk &lt;= 1; reset &lt;= 1; trig_i &lt;= 0; req_i &lt;= 0; atomic_i &lt;= 0; tc1_or_tc2 &lt;= 0; #15; reset &lt;= 0; tc1_or_tc2 &lt;= 0; test_case_1(); end endmodule </code></pre> <p>Waveform of the simulation:</p> <p>If we focus on the &quot;line of the issue&quot;:</p> <pre><code>ack &lt;= req_i; </code></pre> <p>Ideally, <code>ack</code> should take the value of <code>req_i</code> at the occurrence of next timing event (in this case, the next <code>posedge</code> of <code>clk</code>, but I see that <code>ack</code> is readily getting the value of <code>req_i</code> without any delay. If you see <code>ack1</code>, it gets the value of <code>ack</code> as expected (after a clock cycle delay), but this should also have been the case for <code>ack</code>, right?</p> <p>Is this because the <code>req_i</code> is assigned its values from a Verilog <code>task</code>? Is there any missing piece in the Verilog event scheduler/stratified event queue, which I'm not aware of?</p> <p><a href="https://i.stack.imgur.com/sZRmi.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/sZRmi.png" alt="sim_wave" /></a></p>

Why non-blocking assignments in Verilog sometimes do not provide a clock cycle delay?

2024-02-17T18:33:38.743

701861

|voltage|operational-amplifier|circuits|

<p>It does not work if supplies have no common ground reference with the voltage you want to measure.</p> <p>So what you built does not match the schematic that was drawn.</p>

<p>I am trying to make a simple non inverting amplifier using an <a href="https://www.ti.com/lit/ds/symlink/lm358.pdf" rel="nofollow noreferrer">LM358P</a>.</p> <p>I have run into a problem: the output voltage is 0. I have tried both amplifiers on the chip.</p> <p>I have listed the pin configuration below:</p> <p>Pin 8: Positive input of 5.8 V<br /> Pin 4: Negative input of 5.8 V<br /> Pin 3: Positive input of 1.8 V, negative to -ve rail on breadboard.<br /> Pin 2: Resistor 1 to ground<br /> Pin 2: Resistor 2 to pin 1 (output)<br /> Pin 1: Voltage out</p> <p>The voltage output is 0, measuring from pin 1 to -ve rail.</p> <p>What am I doing wrong?</p> <p><a href="https://i.stack.imgur.com/2Uf55.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/2Uf55.png" alt="Circuit Lab" /></a></p> <p><a href="https://i.stack.imgur.com/hYTvM.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/hYTvM.jpg" alt="Bread board" /></a></p>

LM358P not functioning as a non-inverting amplifier

2024-02-17T19:52:07.300

701862

|rf|

<p>Current as in &quot;still currently made&quot;? Almost certainly no, unless it's a military part still used by the military. Then it may not be made, but is still stocked somewhere, and would have a NSN issued. You can look up NSN numbers by manufacturer AFAIK.</p> <p>But it could be easily enough reproduced. It looks like a part designed for use with aviation radios, or military radios. The wire terminals on the side facing the viewer are hermetic. The connector looks like it is at least waterproof. The connector on top of the filter is still made. There's nothing too &quot;old&quot; about the overall style, but there just may not be any application for this filter anymore.</p> <p>Aviation radio hardware has advanced quite a bit since this filter was introduced probably 50+ years ago. If this is an aviation filter, it probably still flies in some old planes, so if you talked to companies that specialize in old aviation radio gear repair, perhaps someone there could tell you exactly where it was used.</p> <p>You could use a RLC meter to try and characterize it at least a bit without destroying it. For a full characterization, a network analyzer would be needed, with appropriate fixtures.</p>

<p>I cannot find any information on this RF Filter, any help would be appreciated. Is this style still in use? type rf2168 rating #1 Is it Aviation related?</p> <p><a href="https://i.stack.imgur.com/gfmwm.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/gfmwm.jpg" alt="enter image description here" /></a></p>

Is this RF Filter still current?

2024-02-17T20:00:22.463

701864

|circuit-design|diodes|voltage-regulator|usb-c|

<p>The 5V rail is only feeding the 3.3V regulator that has a low dropout of about 1V, and the neopixels which work down to 3.7V. Any silicon diode rated for 1000mA minimum will do the job. A 1N4001 (SMD variant is called M1) will do the job just fine, as will do any higher diode in the 1N4001/M1 series, up to 7, i.e. up to 1N4007 or M7. The lower the number, the lower the reverse voltage rating, but all of them are much higher than your application requires, so 1N4001 or M1 will be perfect.</p> <p>The reworked schematic, with <strong>necessary Neopixel level translation added</strong> is here: <a href="https://oshwlab.com/kuba2/701486" rel="nofollow noreferrer">https://oshwlab.com/kuba2/701486</a>. I've updated the answer to the question that has the schematic image included as well.</p> <p>You'd still need to match the reference designators and footprints to the specific parts you've used in the project, I only matched the major part numbers and footprints, not designators etc.</p>

<p>I am making a circuit in which there will be a 12-30 V input reduced to 5 V and a USB-C port.</p> <p>I wanted to know which diode to use to avoid backfeeding the 5 V into the USB-C port. The diode should be capable of passing at least 500 mA from the USB-C port. The purpose of using the USB-C port while the 12-30V is connected is for debugging and the diode will also help prevent someone from blowing up their computer from backfeeding.Please do not focus on the other issues as I have already posted other questions about them.</p> <p>Additionally, any insights into potential issues or best practices would be appreciated.</p> <p>Schematics: <a href="https://i.stack.imgur.com/a8zsX.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/a8zsX.png" alt="Schematics" /></a></p>

Selecting a diode to prevent backfeeding from 5 V to USB-C port

2024-02-17T20:22:09.400

701868

|ac|relay|wiring|

<p><img src="https://i.stack.imgur.com/4A8H7.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2f4A8H7.png">simulate this circuit</a> &ndash; Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a>}</p> <p><em>Figure 1. As specified.</em></p> <p><img src="https://i.stack.imgur.com/20kGI.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2f20kGI.png">simulate this circuit</a>}</p> <p><em>Figure 2. A more typical wiring solution.</em></p>

<p>Got the following relay Taiss/AC 220V (YJ2N-LY AC 220V) A picture and a wiring diagram are below. Given:</p> <ul> <li>AC 230v constant L input</li> <li>AC 230v signal L input</li> <li>N input ,</li> </ul> <p>How should I wire the relay to get 2 L and N outputs (2*[L+N] wires), one of which is based on NC logic and another one is NO?</p> <p><a href="https://i.stack.imgur.com/O0NpT.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/O0NpT.png" alt="wiring" /></a></p> <p><a href="https://i.stack.imgur.com/kXAZe.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/kXAZe.png" alt="relay" /></a></p> <p>Source: <a href="http://www.yjele.com/en/soft/20210217144608300.pdf" rel="nofollow noreferrer">http://www.yjele.com/en/soft/20210217144608300.pdf</a></p> <p>Product image: <a href="https://www.desertcart.com/products/137738157-taiss-ac-220-v-coil-electromagnetic-power-relay-5-a-2-dpt-8-pins-2-no-2-nc-my-2-nj-hh-52-p-with-yjf-08-a-e-socket-base-quality-assurance-for-2-years-yj-2-n-gs" rel="nofollow noreferrer">https://www.desertcart.com/products/137738157-taiss-ac-220-v-coil-electromagnetic-power-relay-5-a-2-dpt-8-pins-2-no-2-nc-my-2-nj-hh-52-p-with-yjf-08-a-e-socket-base-quality-assurance-for-2-years-yj-2-n-gs</a></p>

Need help with AC relay wiring

2024-02-17T20:25:48.783

701875

|integrated-circuit|

<blockquote> <p>Can I install other similar looking IC or also maybe directly solder some wires somehow to make the board circuit close.</p> </blockquote> <p>The circuit isn't permanently closed. It closes and opens at a rate of several 10s of kHz, and the closing and opening periods are not arbitrary but are controlled by the chip. The circuit is a switching power supply. If the switch is permanently closed with a wire, the primary transformer winding will burn out, so you'll just do more damage.</p> <p>These supply control chips are almost always victims of some other part having failed. <strong>Burned-out parts have failed, but not all failed parts are burned out!</strong></p> <p>Without proper tools and know-how, you won't be able to diagnose this board. You may look for a skilled electronics repair person. A few of the good ones have YouTube channels, so if you happen to be in the same area, or are willing to ship the board out for repair, there certainly are skilled people who will fix it for you for less than it'd have cost to buy a new appliance.</p> <p>You can also check if this board is available as a replacement part.</p>

<p>An integrated circuit has blown and how can I workaround that. Can I install other similar looking IC or also maybe directly solder some wires somehow to make the board circuit close.</p> <p><a href="https://i.stack.imgur.com/WWBaZ.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/WWBaZ.jpg" alt="enter image description here" /></a></p>

Electrolux Induction Stove Board IC bricked and 1 Resistor too

2024-02-17T20:50:24.347

701882

|gpio|

<p>While technically not standardized, if you want something to connect to the wildly popular Arduino/Beaglebone/Raspberry/Dragonboard 410c/MX8M boards using their idea of GPIO, you're looking for 0.1&quot; / <a href="https://eu.mouser.com/c/connectors/headers-wire-housings/?pitch=2.54%20mm" rel="nofollow noreferrer">2.54mm pitch headers</a>.</p> <p>This has been a popular size since before IDE / Parallel ATA. If you do not have a good reason to pick anything else, I'd stick with those.</p>

<p>If were to make my own microcontroller board, something similar to the Texas Instrument MSP430 Launchpads, what types of pins can I use for the GPIO male header pins to solder to the board?</p> <p>Do they need to be made of special material or have special specifications?</p> <p>Note that I am not including the emulator area, only the microcontroller area of the board.</p> <p>I was looking through the Mouser website and I do not see anything under the label GPIO pins. I do see however &quot;terminal pins&quot; sold individually and &quot;male headers&quot; sold in as two rows of ten attached together, but nothing specifically indicating a row of ten &quot;GPIO pins.&quot; And they do not specify as to whether these are even supposed to be used with solder or just for solderless applications. Is there some type of substitute I can use?</p>

If making your own microcontroller board, what types of pins may be used as GPIO pins?

2024-02-17T21:36:16.193

701883

|pic|uart|sim800|

<p>Most likely there is a race condition between the code you have listed and the IIC code that you did not list. I assume the IIC code updates UARTTXBuffInPos from an ISR when IIC data is received. If IIC data is received just after the empty buffer check, but before clearing UARTTXBuffInPos, that byte will get lost. You will need to provide some sort of mutual exclusion when updating UARTTXBuffInPos.</p>

<p>I am using the diagram recommended in the SIM800L datasheet to connect it to a <a href="https://ww1.microchip.com/downloads/aemDocuments/documents/OTH/ProductDocuments/DataSheets/PIC12LF1822-16LF1823-Data-Sheet-40001413F.pdf" rel="nofollow noreferrer">PIC12F1822</a> MCU operating at 3.3V and 16MHz using its internal RC oscillator.</p> <pre><code>(SIM800L TX) --- (1K Resistor) --- (MCU RX) (SIM800L RX) --- (1K Resistor) --- (MCU TX) | (5.6K Resistor) | (GND) </code></pre> <p>I used 2400bps baud rate to send commands from MCU to SIM800L but some characters were lost during communication. I also checked 9600bps but the problem still exists. I removed the SIM800L module and connected the PIC to the PC using a USB to Serial adapter and still have the problem. This is my PIC program code. I am using MPLAB X IDE with XC8 (v1.35) compiler.</p> <pre><code>TXSTA = 0b00100010; // enable TX, select asynchronous RCSTA = 0b10010000; // enable RX and EUSART SPBRG = 207; // 1200bps ... // super loop for (;;) { CLRWDT(); // clear watchdog timer if (UARTTXBuffInPos &gt; UARTTXBuffOutPos) { // if there is new data if ((TXIF) &amp;&amp; (SSP1STATbits.P)) { // if I2C is idle and last UART byte is sent TXREG = UARTTXBuff[UARTTXBuffOutPos]; // send data UARTTXBuffOutPos++; // next byte } } else { UARTTXBuffInPos = 0; // reset buffer pointer UARTTXBuffOutPos = 0; // reset buffer pointer } } </code></pre>

Some characters lost in UART Transmission (PIC12F1822 -> SIM800L)

2024-02-17T21:41:50.300

701896

|identification|

<p>I'm familiar with how Silergy marks their devices so by searching, &quot;Silergy SOT23-6 WB marking&quot;, I was able to find out that it is the <a href="https://datasheet.lcsc.com/lcsc/1811081220_Silergy-Corp-SY8120B1ABC_C88474.pdf" rel="nofollow noreferrer">SY8120</a>.</p> <p><a href="https://i.stack.imgur.com/0eK64.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/0eK64.png" alt="enter image description here" /></a></p>

<p>It is a SOT-23-6, probably a voltage regulator, used in a 3.3V controlled suction pump (Elephant Robotics <a href="https://rads.stackoverflow.com/amzn/click/com/B09PH8YCVM" rel="nofollow noreferrer" rel="nofollow noreferrer">https://www.amazon.com/gp/product/B09PH8YCVM</a>). They had the cable wired backward, so I think that is why it blew.</p> <p><a href="https://i.stack.imgur.com/v0VAH.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/v0VAH.png" alt="Blown IC looking to identify and replace" /></a></p> <p>Marking seems to be &quot;WBDCD&quot;. Google isn't being helpful. Any chance of identifying it?</p>

SMD marking code WBDCD

2024-02-17T23:06:41.880

701898

|batteries|lithium-ion|load|discharge|charge|

<p>To get 5V out of 3.8V battery requires an use of step-up switching converter. To get 9V, similar (or the same converter) will be required. Your measurements in 5-V mode indicate that the built-in converter has efficiency of about 87%, (which is pretty good), so the efficiency of the device with variable Li-Ion (internal) voltage is already factored in the 104Wh number. So your estimation looks correct, maybe should be a little lower since efficiency of switchers decreases with more difference between Vin and Vout.</p>

<p>A polymer lithium battery in a powerbank (marketed as 30,000 mAh / 3.8 V, 114 Wh), has an actual electric capacity of 19,944 mAh, and an energy capacity of 104 Wh as measured with a constant load connected non-stop to the powerbank's USB-A output that was drawing 5.21 V / 1.50 A for 13:18 hh:mm (until the powerbank &quot;died&quot;, the voltage remained constant to the end).</p> <p>For how many hours can this powerbank power a device that draws 9.2 V / 0.5 A from the powerbank's USB-C port? How does draining at different voltages alter the equation of battery run time? (USB-A and -C outputs are rated from 5 V / 2 A to 20 V / 3.25 A.)</p> <p>Is 104 Wh / 4.6 W = 22.6 h the best estimation?</p>

Estimating lithium-ion battery run time at different voltages

2024-02-17T23:46:45.570

701903

|voltage-regulator|high-voltage|gpio|current-limiting|voltage-detector|

<p>Thanks to the many helpful answers, I've learned a lot about the properties of this problem space. It seems like my main problem is that <em>even if</em> I found a &quot;neutral&quot; pole on the incoming AC, I couldn't trust its potential relative to my circuit's GND, which would absolutely fry my components. Because of this, <a href="https://en.wikipedia.org/wiki/Galvanic_isolation" rel="nofollow noreferrer">galvanic isolation</a> is needed so to acquire a voltage <em>relative to</em> the device ground. All of the answers suggested an optocoupler because of their size, cheapness, and ease of integration here by pulling the GPIO low.</p> <p>Here is my revised design. It uses a small capacitor on the output as @Simon Fitch suggested to prevent cut-off at the cycle midpoint, and an AC input optocoupler as @GodJihyo suggested to remove the need for a rectifying diode. This schematic assumes the MCU GPIO (<code>bell_in</code>) has an internal pull-up resistor.</p> <p><a href="https://i.stack.imgur.com/XsN0N.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/XsN0N.png" alt="The AC bell circuit connected to a SFH620A optocoupler through a 4.7k resistor in series; the collector of the optocoupler is connected to 3.3v via a 1uF capacitor and to the bell_in net, and the emitter tied to ground" /></a></p>

<p>My project involves detecting a ringing doorbell. The doorbell circuit is 16 V AC and I want a low-voltage binary signal from it. The obvious way to me is to transform that electrical signal until its properties are useful (read: not harmful) to a digital GPIO. Firstly, by getting a DC signal by feeding it through a rectifier, secondly bringing it to my microcontroller's operating voltage with a voltage regulator. These ought to solve the AC and high voltage problems, but they don't cover <em>current</em>. A breadboard test showed 0.38 A from the regulator output, which I'd expect to be too much for a data GPIO.</p> <p>Is this a real problem, or does the GPIO not actually <em>need</em> to sink all of that current?</p> <p>If it is a real problem, what kind of circuit is needed to cut down that ~400 mA by a couple orders of magnitude?</p> <p><a href="https://i.stack.imgur.com/Ktn9l.png" rel="nofollow noreferrer" title="Wiring diagram showing an incoming AC connected to a half-wave rectifier with a smoothing capacitor, connected then to a 3.3 V voltage regulator which sends its output to a GPIO pin on a Seeedstudio XIAO"><img src="https://i.stack.imgur.com/Ktn9l.png" alt="Wiring diagram showing an incoming AC connected to a half-wave rectifier with a smoothing capacitor, connected then to a 3.3 V voltage regulator which sends its output to a GPIO pin on a Seeedstudio XIAO" title="Wiring diagram showing an incoming AC connected to a half-wave rectifier with a smoothing capacitor, connected then to a 3.3 V voltage regulator which sends its output to a GPIO pin on a Seeedstudio XIAO" /></a></p>

Detecting 16 V AC with a GPIO

2024-02-18T01:42:31.550

701909

|dc|noise|

<p>Technically, the connections are wired correctly, but the arrangement is poor.</p> <p>So like what you did, by connecting probe ground clip and scope tip to power supply ground and supply pins are correct.</p> <p>However, the loose wiring makes a big loop and the loop of wires is right on top of the switch mode supply, so it will pick up interference.</p> <p>Usually ripple and noise are measured in a specific setup which you often see in many places.</p> <p>You have no load, but the load is optional, you can measure the ripple and noise at any load you want. The results may just vary while the load is varied too.</p> <p>The usual setup is to have some capacitance at the end of power supply cable where the scope probe connects. There is again no standard, but typically you might use a 10uF electrolytic for low frequencies and a 100nF ceramic capacitor for high frequencies.</p> <p>The measurements are also usually done with limited bandwidth, and that is why oscilloscopes usually have a setting to limit a channel to 20 MHz bandwidth.</p> <p>It must also match the correct probe settings, because 1x probes usually have very low bandwidth and you should use a 10x probe, or if the probe has a selectable setting, then use the 10x setting. As a rule of thumb, if you have a selectable probe, always use the 10x setting, unless you know you have a good reason to use the 1x setting.</p> <p>Still, there might be switching noise seen on the scope that is really not there, because the power supply has a two prong mains inlet, and there must be a capacitive noise suppression &quot;Y&quot; capacitor between mains input and DC output. It may help to use an isolation transformer on the supply (never defeat ground on your equipment). Also the scope and all other equipment used that have a three-prong earthed mains inlet must be properly earthed by connecting the plug to a properly earthed mains socket.</p>

<p>I am new and want to learn the right way to read noise and ripple from a linear power supply. In this case, I measured 5 V DC for a sample. I used 1 channel. I connected the center of the probe to +5 V and the shield of the probe to ground. Here is what I got:</p> <p><a href="https://i.stack.imgur.com/sJFe2.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/sJFe2.jpg" alt="enter image description here" /></a></p> <p><a href="https://i.stack.imgur.com/72oQL.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/72oQL.jpg" alt="enter image description here" /></a></p> <p><a href="https://i.stack.imgur.com/X0wxE.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/X0wxE.jpg" alt="enter image description here" /></a> <a href="https://i.stack.imgur.com/56Pco.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/56Pco.jpg" alt="enter image description here" /></a></p>

How to read ripple and noise on a linear power supply using RIGOL DS1202Z-e?

2024-02-18T02:51:29.667

701912

|circuit-analysis|rf|radio|frequency-modulation|tank|

<p>If you mean receiving all FM stations at once.</p> <p>No. The LC circuit is a must for slope detection of FM transmission signals.</p> <p>&quot;The slope detector circuit is also called frequency discrimination circuit. This circuit operates by detecting the variations in the input signal's slope to obtain the original modulating signal. It uses tuned LC circuit at the front, followed by diode rectification and low pass filtering. It is <strong>similar to AM envelope detector circuit except the tuned circuit.</strong>&quot;</p> <p>From:</p> <p><a href="https://www.ee-diary.com/2023/04/how-to-design-fm-slope-detector.html" rel="nofollow noreferrer">https://www.ee-diary.com/2023/04/how-to-design-fm-slope-detector.html</a></p>

<p>I was broadcasting FM signals at MHz frequencies in my room. I know that an AM radio will not work to receive FM transmissions.</p> <p>The special issue is that an AM radio can get any AM signal without a tank circuit by only setting an amplifier.</p> <p>I am struggling when I have to turn the trimmer capacitor to receive the right FM station signals inside a tank circuit. Is there a way to get and receive an FM station signal without a tank circuit like in AM radios?</p> <p>Below is a picture of the FM receiver. Can this circuit be made without a tank circuit?</p> <p><a href="https://i.stack.imgur.com/bpmVP.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/bpmVP.png" alt="circuit" /></a></p>

Is it possible to receive an FM signal without a tank circuit?

2024-02-18T03:31:41.080

701913

|socket|dip|

<p>DIP packages are supplied with the leads spread beyond the proper spacing for footprints or sockets. The lead spacing should be 0.3&quot; (7.62mm) for that package.</p> <p>They are intended to be slightly compressed or formed before insertion. Both sides equally. This would be done by a machine in production (the machine would grab the part on the outside of the leads and compress it while holding it). By hand you can just push each side carefully (eg. against a sturdy antistatic mat) to form the leads. It will take a bit of practice to go just far enough.</p> <p>There are tools, including <a href="https://swsystems.com/lead-forming-machine-for-dip-components-a075-ri/" rel="noreferrer">motor-driven automated ones</a>, that did the forming too, especially from back when DIP packages were more commonly used in production.</p> <p><a href="https://i.stack.imgur.com/AhSj8.jpg" rel="noreferrer"><img src="https://i.stack.imgur.com/AhSj8.jpg" alt="enter image description here" /></a></p> <p>While you can use a socket with (say) 24 or 28 pins and 0.3&quot; lead spacing for that microcontroller, it's not good practice unless there's a good reason (such as upward compatibility) since it increases the chances of error occurring. Some of such errors may cause permanent damage to the MCU or possibly something else on the board.</p>

<p>Consider a 20-pin DIP IC with 2 rows, 10 pins in each row. For example, the Texas Instrument MSP430G2452 microcontroller. The measured distance between these two rows is just over 9 mm. On page 62 of the datasheet for this microcontroller, it reads a maximum distance of &quot; 10.92 mm. &quot; It does not state any other distance between the two rows except this maximum number.</p> <p>At the same time, when searching through the Mouser website for a DIP socket, the only row spacing close to that number is &quot;10.16 mm,&quot; but this is for a &quot;22 position&quot; DIP / SIP socket. How do I interpret this ? Does this information mean or imply that I should bend the pins of one of the rows of the microcontroller in order to make it fit the DIP socket ? Is this common practice ? Is this safe ?</p> <p>Also, is it good practice to use a socket with the same amount of holes as the microcontroller, or does it not matter how many holes the DIP socket has as long as it has at least the same number of holes as there are pins on the microcontroller ? For that matter, will a difference between pin number of the microcontroller and hole number of the socket affect both the setup and functioning of the microcontroller ? Does the number of positions of a DIP socket need to match the pin count of an IC ??</p>

When selecting an IC DIP socket for a DIP 20-pin microcontroller, should the DIP socket have the same number of positions and row distance as the IC?

2024-02-18T03:35:50.867

701919

|pcb-design|relay|inductor|

<p>Distance affects the coupling coefficient between inductors.</p> <p>Most generally, one can consider all inductors coupled, that coupling given by a matrix of coupling factors, from each one to every other. Then, understand most of the matrix entries are very close to zero: close enough to approximate as actual zero for engineering purposes (e.g., interference is below noise floor for the audio signals, or below the emissions limits for EMC purposes), and thus we can work with it as a sparse matrix, or further subdivide it into groups of relatively-strongly coupled inductors, which may include groups of size 2 (mere adjacent pairs). We might also approximate small groups as pairs, or chains of pairs, to simplify analysis, when it is appropriate and convenient to do so.</p> <p>A full matrix approach is severe overkill for most purposes, but can find use at high frequencies, where indeed the whole PCB, or PCBA + wiring harnesses + enclosures, might need to be treated as a coupled system. Matrix extraction software is available (e.g. ANSYS tools).</p> <p>Mostly, we take the converse approach, designing the system from the bottom up, in such a way that the matrix will be near-sparse at frequencies of interest. In most commercial designs, this is done with a ground plane PCB strategy, or a metallic enclosure if needed; in RF designs, this is done by adding shield cans, or indeed solid metal covers (with pockets milled out to clear components and filter structures), to physically block fields between sections.</p> <p>Notice a sensitive RF transceiver will have a much tighter interference limit, and coupling factors are more significant at high frequencies, therefore more aggressive countermeasures are chosen. The interference threshold is a key part of the design process, and dictates what shielding strategy is chosen. The threshold is different for different parts, signals and applications.</p> <p>On a PCB, typically the interference thresholds and coupling factors are such that we only need to be concerned about those that are within a couple bounding spheres of each other, that is, taking the maximum outer dimensions or bounding sphere around each part, expand it by a factor of 2 or 3, and considering all within that space. And we can thin that down even further depending on part type, signal, etc.</p> <p>And, plenty of situations hardly care about coupling at all; most power applications won't care about coupling between inductors if they're heavily-loaded filter inductors (rod core type chokes are a common choice for DC output filtering), or doing similar things (the inductors in a phase-interleave converter might indeed benefit from coupling, there are a few papers on this topic). Or that the interference limit is high enough it can never be met through ordinary component placement (e.g. a wound-rod style ferrite bead on a 5V logic signal (~1.5V noise margin) beside an unshielded filter inductor on a power rail having &lt;1V of noise/ripple).</p> <p>Shielded type inductors are generally lower in external fields, though it's not a controlled commercial term and many parts are dubiously or loosely labeled as such. Conversely, due to geometry and relative orientation, there are unshielded types with lower external field, or less impact upon nearby parts of different orientation, compared to shielded types. It's a &quot;nice to have&quot; term, but not very meaningful for design purposes.</p> <p>Also, inductors are never rated in terms of fields or emissions, so you'll have to test samples to know absolutely for sure whether they will work in a design of given interference limit.</p> <p>Finally, regarding relays: the coil is generally well-shielded, on account of its magnetic path being constrained by the pole pieces and armature. What's more, the voltage is constrained by the flyback clamping circuit used, and the turns ratio is extremely low to anything nearby (the coil might have thousands of turns, and a couple tens of volts on the coil is reduced to 10s mV/turn). A far greater concern is switching current, as mechanical contacts act extremely quickly (sub-ns) and closing and opening under load can both generate intense electromagnetic pulse (see standards such as IEC 61000-4-4, electrical fast transients). You may want a snubber for the contacts, to avoid interference in the rest of your circuit.</p>

<p>How should inductors be placed on a PCB? I have a relay (MCHMR1-S DC24V) switching about 3 A of current. Do I need to separate the relay from nearby analog and digital components, or is it fine next to either?</p> <p>Additionally, can shielded inductors be placed next to each other (or near any other analog/digital components)? These inductors are not used for power switching, they are used in an audio application (not the relay). Both are 47 μH, 2.5 A, through-hole inductors.</p>

PCB layout for inductors

2024-02-18T04:08:41.547

701931

|fpga|spi|labview|

<p>The closest thing to a standard that defines SPI is <a href="https://www.nxp.com/docs/en/application-note/AN991.pdf" rel="nofollow noreferrer">this</a> (formerly Motorola) document.</p> <p>There's no inherent limit in SPI as to word length. Framing is via the /SS (usually called /CS) line-- the master drives it and the slave listens. If you pull /CS low and send the slave x clock edges, you'll get x bits of data at the input provided the slave has them to send (you'll actually get x bits of data clocked in even if the slave doesn't have them- they may be nonsense- whatever is on the MISO line is sampled) and provided you meet the phase and timing relationships defined in the slave chip datasheet. In general each chip can be different. Certainly in maximum clock frequency and timing, and there are four possible clock and data phase relationships.</p> <p>As to whether the particular NI device you have (myRIO) can support the particular chip you have in the hardware they supply, and under the layers of software (.vi) and how you use that hardware and software, that's more of an NI forums question, but <a href="https://forums.ni.com/t5/LabVIEW/MyRIO-SPI-on-FPGA/td-p/3206796" rel="nofollow noreferrer">this</a> forum thread has a link to some code (and some confused questions).</p>

<p>When receiving data via SPI communication, is there any constraints for word length (bit size)?</p> <p>I have a chip that sends 16 bits of data A and 16 bits of data B through a single pin, can I configure myRIO to receive those data without any loss?</p> <p>I'm wondering if myRIO has its own SPI word length limit, because in the LabVIEW example that I found (NI SPI IP) is set as 24 bits.</p>

SPI and word length

2024-02-18T07:40:59.297

701936

|mosfet|esp32|

<p>You should have a flyback diode across the load, otherwise the MOSFET will likely avalanche and die eventually due to pump motor and wiring inductance.</p> <p>You should be using a <strong>logic level</strong> MOSFET with <em>guaranteed</em> Rds(on) at 3.3V or less, not 10V as the one you have. Unless you can convince your supplier to only sell you 'typical' units and not ones that merely conform to the datasheet limits. You may have trouble finding one in a TO-220 package, most are SMT. If you find such a MOSFET you can add a large-ish series gate resistor and protect the ESP32 via that, however it will slow the MOSFET switching and that's hard on the MOSFET. Also don't divide it down by having a G-S resistor that reduces the Vgs(on) if you do this.</p> <p>If you want to use the particular MOSFET you have (with the flyback diode) you can make a simple gate driver with a couple transistors that will shift the 3.3V to 12V.</p> <p><img src="https://i.stack.imgur.com/jKGjK.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fjKGjK.png">simulate this circuit</a> &ndash; Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a>}</p>

<p>I made a simple circuit based on an ESP32 for my watering system.</p> <p>I built this circuit to switch a 12 V pump on and off:</p> <p><a href="https://i.stack.imgur.com/iLyyz.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/iLyyz.png" alt="enter image description here" /></a></p> <p>The circuit is powered by a USB power bank and a boost converter to convert 5 V to 12 V. The pump is switched using an <a href="https://datasheet.lcsc.com/lcsc/2004201506_Wuxi-NCE-Power-Semiconductor-NCE6050A_C502821.pdf" rel="nofollow noreferrer">NCE6050A</a> N-channel MOSFET. I've added an XKC-Y23A liquid sensor to detect when the water is running low.</p> <p>The circuit worked properly for several days but after that it stopped working.</p> <p>I noticed that the AMS1117 LDO converter and the ESP32 chip on my DEV kit board became very hot.</p> <p>I suppose that something burned it out, but I can't understand what is wrong with the circuit. Can anyone help me find the cause of the issue?</p>

Switching a 12 V pump with an N-channel MOSFET burned out my ESP32

2024-02-18T09:17:36.923

701941

|operational-amplifier|sensor|negative|

<p>This ridiculously simple resistor divider will produce an output between +0.24V and +3.0V for inputs going from -2.0V to +2.0V respectively:</p> <p><img src="https://i.stack.imgur.com/mtc3L.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fmtc3L.png">simulate this circuit</a> &ndash; Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a>}</p> <p><a href="https://i.stack.imgur.com/1Q9Jl.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/1Q9Jl.png" alt="enter image description here" /></a></p> <p>If you have a noisy +5V supply, it will inject some of that noise directly into the signal, though. This won't be a problem if your ADC uses the same supply (+5V in this case), or some fixed fraction of that supply, for its own internal reference voltage. If the ADC contains a precision reference, you'll get better results by using that instead of +5V, or by providing your own reference. Below I use the well loved TL431 to obtain a rock-steady +4.2V:</p> <p><img src="https://i.stack.imgur.com/zIjmM.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fzIjmM.png">simulate this circuit</a>}</p> <p>The output impedance of those last two designs is several kilohms. A typical microcontroller ADC would not have a problem with this, but yours might. You can buffer the signal with a voltage follower which will have an output impedance near zero. You could use any op-amp with inputs and output that can get near the negative supply, like the LM358, LM324, TLC2272 etc:</p> <p><img src="https://i.stack.imgur.com/KJYKM.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fKJYKM.png">simulate this circuit</a>}</p> <p>With careful choice of resistances and op-amp, it's possible to use a single op-amp to offset, scale <em>and</em> buffer the signal. This next circuit produces a +4.8V to +0.2V output (it inverts) in response to -2.0V to +2.0V in:</p> <p><img src="https://i.stack.imgur.com/p33WR.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fp33WR.png">simulate this circuit</a>}</p> <p>This requires an op-amp with an output capable of approaching both supply rails, of which the TLC2272 is an example. The +1.16V source V2 can be obtained using a voltage divider across the +5V and 0V supplies, or using a precision reference like the TL431. Here's the response:</p> <p><a href="https://i.stack.imgur.com/fQ1tI.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/fQ1tI.png" alt="enter image description here" /></a></p> <p>Not all input ranges can be accommodated with this particular op-amp configuration, but your symmetrical ±2V input is easy to work with; in particular you'll notice that no negative supplies are needed in any of the above solutions.</p>

<p>I'm trying to read a voltage that represents a signal from a sensor. This signal can range between -2 volts to +2 volts. I wanted to read this signal to log it, but most ADCs (including ones on an Arduino) can't handle the negative values.</p> <p>I wanted to make a circuit that could do this for me instead. I started with a circuit that would provide me with polarity detection and also a magnitude rectifier using two op-amps, and then read those two signals and post-process them on an Arduino. See the image below of the original circuit.</p> <p><a href="https://i.stack.imgur.com/0VVIM.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/0VVIM.png" alt="Detection circuit" /></a></p> <p>This didn't really work as well as I thought it would so I decided to make a circuit that could add a reference voltage of +2.5V to the input signal and then read that. See the image below.</p> <p><a href="https://i.stack.imgur.com/RSLxb.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/RSLxb.png" alt="enter image description here" /></a></p> <p>I'm not sure if either circuit is correct or what the correct way of doing this is.</p>

Measuring a voltage signal ranging from -2 to 2 volts into a 16 bit ADC circuit

2024-02-18T11:26:51.530

701942

|digital-logic|memory|computer-architecture|

<blockquote> <p>Yes, it's theoretically very elegant. But, how could this be achieved in reality?</p> </blockquote> <p>It is very simple. I think you're trying to view it as something complicated, but it's a very basic solution.</p> <blockquote> <p>Without going into too much detail of the circuitry, could you explain the main aspects of such a construction that would allow input/output of data in B sized cells?</p> </blockquote> <p>Imagine that addressing hardware is expensive. In the times of core memory, it certainly was. So you wanted to have N row drivers, N column drivers, B sense/write amplifiers. The NxN matrices were called core planes, one bit per plane. B planes gave you B bits, all addressed at the same time.</p> <p>You'd do the same with one-bit dynamic memory chips back in the 70s and 80s. The chips shared the address (muxed row/column), RAS and CAS signals (row address select and column address select respectively), but each chip had it own single bit data line. These were assembled to form 8, 16 or 32 bits as needed.</p> <p>Below is the schematic of a memory system with following specifications:</p> <ul> <li>4 bits/word,</li> <li>16 words,</li> <li>2x2 bit planes,</li> <li>demultiplexed addressing (row and column separate)</li> </ul> <p><img src="https://i.stack.imgur.com/PGTM8.png" alt="schematic" /></p> <p>Within each plane (matrix), Rn are row addresses, and Cn are column addresses.</p>

<p>Currently studying memory addressing in IC design, my professor mentioned matrix addressing and how it reduces the number of input lines to the memory block. But he didn't make himself clear on the part of word organized memory - where instead of a single bit being stored/accessed, an entire group of them is.</p> <p>I have tried to contact the professor and come up with my own interpretations, but sadly I haven't gotten anywhere useful.</p> <p>My point is that if stacking a 2D matrix is a solution to the problem, that would require us to include more input lines for accessing each matrix's bit, rendering the entire concept of reducing the number of input lines useless. Any ideas?</p> <p>TLDR: I want to know how to read/write data in a word organized matrix addressable memory block.</p>

How is the structure of a matrix addressable memory block realized?

2024-02-18T11:36:33.197

701951

|switches|battery-charging|dpdt|

<p>There are four pole double throw switches available, but they may not be avialble with the current rating you require.</p> <p>You could use a single switch to control a 4PDT relay, or two DPDT relays, depending on your current requirements.</p> <p>Since these things are only $10, perhaps you should use two of them, one for charge control, and one for discharge, then you won't need to do any switching.</p>

<p>I have a system with a 12 V lead acid battery, a charger (plugged into the wall outlet), and an invertor, which generates AC power from the 12 V battery.</p> <p>I am also using the following battery charge/discharge control unit to protect the lead acid battery:</p> <p><a href="https://rads.stackoverflow.com/amzn/click/com/B0C73DXJF7" rel="nofollow noreferrer" rel="nofollow noreferrer">https://www.amazon.com/EC-Buying-Discharge-Discharging-Protection/dp/B0C73DXJF7/ref=sr_1_2?crid=11M56WIWTLTHT&amp;dib=eyJ2IjoiMSJ9.BQM0ULvUaSbHeK2WwVhnKEMLw9TOUIPfxJbm-dlb8dcA73Qy5rh7eJFE3CRhsPF-.rvRzWw2UFdwGj98t1SegwTWyfryKbSa3gGiCxERMZm0&amp;dib_tag=se&amp;keywords=XY-CD60&amp;qid=1708249807&amp;sprefix=xy-cd60%2Caps%2C229&amp;sr=8-2</a></p> <p>This is a useful device in that, while charging the battery, it provides overcharge protection, and while discharging the battery, it limits discharge to 50% of battery capacity, which is critical for battery life for lead acid technology.</p> <p>The device operates in two modes: P1 charge and P2 discharge. Based on the mode, its Vin and Vout connections need to be configured as follows:</p> <p><a href="https://i.stack.imgur.com/R9RPJ.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/R9RPJ.png" alt="enter image description here" /></a></p> <p><a href="https://i.stack.imgur.com/T46MR.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/T46MR.png" alt="enter image description here" /></a></p> <p>With use of two DPDT rocker switches, I can configure the Vin and Vout connections to correspond to the two modes:</p> <p><a href="https://i.stack.imgur.com/OxrjH.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/OxrjH.png" alt="enter image description here" /></a></p> <p><a href="https://i.stack.imgur.com/WoOQX.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/WoOQX.png" alt="enter image description here" /></a></p> <p>However, in the solution above, I need to manually/simultaneously press the two DPDT rocker switches correctly, which is not ideal. If one of the switches was not thrown correctly, the configuration would not make sense. (For example, both DPDT 1 annd DPDT 2 could be connected to the battery.)</p> <p>I understand there could be a mechanical solution that moves the two DPDT switches lockstep (although I have not seen one during a rudimentary search).</p> <p>My question: Other than such a mechanical solution, is there some other, possibly more elegant solution that would swap Vin and Vout among three entities, namely the battery, the charger and the invertor?</p> <p>Thank you.</p>

Improvement for system with two DPDT switches

2024-02-18T12:49:27.290

701960

|soldering|

<blockquote> <p>removed the plaque by using a Dremel with a wire brush head</p> </blockquote> <p>Unless that wire brush head uses brass or copper wire, this is something you should <em>never</em> do. It's not as bad as sandpaper (which I've seen people use...) but mechanical abrasion with anything harder than brass wool (including the steel wire brushes that usually come with dremels) should never be used to clean a soldering tip. It'd probably be fine if you just brushed it a little manually, but using a dremel is probably too much for the tip.</p> <p>Soldering tips are a multi-layered structure, made mostly of copper that is then plated in iron, and the very tip plated in tin. Everything but the tip is usually plated with chromium (which is very difficult to get solder to stick to, so the solder stays on the tip). Note that all these plating layers are very thin, on the order of a few to a few dozen microns.</p> <p>Mechanically abrading the tip will remove any oxide buildup, sure, but it will also damage this layered structure. If you abrade away the tin, you will be left with exposed iron, which will not carry solder, and which can rust when exposed to air and high temperatures. Tip tinner may be able to re-plate the parts with scratched-off tin, but the real problem is if you abrade through the iron layer: in that case, you've exposed the copper, and <em>now</em> you've thoroughly destroyed your tip. You may not be aware of this, but copper actually dissolves in solder, and surprisingly quickly too. As you keep using the iron, you'll find that the tip grows more and more pitted as parts of it dissolve and get left behind in solder joints and on your tip cleaner.</p> <p>There is no practical way to re-apply the iron plating at home, so you'll just need to get a new tip if it was damaged this way. You need a new tip anyway--that one is way too oxidized to be used--but remember this in the future.</p>

<p>I recently installed a new tip on my soldering iron, but when heating it up for the first time (target temperature: +370 °C), it got a reddish plaque (some kinda oxide, I suppose), so that it it's very hard to melt (lead-free) soldering wire, and the tip doesn't pick up anything of the solder. Using a cleaning stone (ammonium chloride) and a wet sponge removed the oxide just for a couple of seconds. After that, the stone was covered in brownish plaque I have never seen when using the old tip:</p> <p><a href="https://i.stack.imgur.com/5TQcF.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/5TQcF.jpg" alt="enter image description here" /></a></p> <p>I followed the advice of the manufacturer and removed the plaque by using a Dremel with a wire brush head and after that polished the tip, but upon the next try, the tip was covered with the same reddish plaque again.</p> <p>What's wrong with my soldering tip? Is it broken? Or did I buy the wrong tip?</p>

How can I get rid of oxidisation of my soldering tip?

2024-02-18T15:33:56.093

701970

|grounding|safety|emc|earth|enclosure|

<blockquote> <p>Paintless (raw) enclosures seem rare, are they bad practice?</p> </blockquote> <p>Paintless <em>does not</em> imply raw, untreated aluminum. Yes, you can sure buy untreated aluminum enclosures, but they are not a finished product and must have some surface treatment applied before use. They look nasty and only turn nastier over time. Bad idea, very unprofessional impression.</p> <p>If painting is &quot;unecological&quot;*, then anodizing is the other low-resource-use option. All it does is add some oxide to the surface, and optionally some mineral pigment that poses no recyclability concerns.</p> <p>Anodizing is an &quot;interesting case&quot;. It has split personality:</p> <ul> <li><p>it is considered a conductive surface for the purpose of protection against electric shock, but</p> </li> <li><p>it is considered a non-conductive surface for the purpose of attaching PE conductors</p> </li> </ul> <p>In other words, for every EMC and PE ground connection, you'll need to either grind off the anodized layer, or, more properly, mask off the areas that need to contact other conductive parts prior to the anodizing bath. The former approach is OK for early prototyping. The latter approach is how you'd be doing production:</p> <ol> <li>Have raw aluminum enclosures made,</li> <li>Mask them,</li> <li>Anodize them.</li> </ol> <p>Steps 2 and 3 are done by metals finishing shops, per your drawing, or by the custom (or customized) enclosure vendor who provides step 1 too.</p> <p>*How many kilograms of paint do you think you will use over the lifetime of the project? Now look at how many resources, amortized, are needed to support your life, on average, for one hour. There's an awful lot of paint that is the resource-equivalent of a day's worth of engineering time. Don't throw the baby out with the bathwater. Literally a few hours of you considering this &quot;optimization&quot; at work will use up more resources than you're trying to save.</p> <p>To further illustrate the point of dubious savings, consider this excerpt from Joel Spolsky's essay <a href="https://www.joelonsoftware.com/2006/09/07/a-field-guide-to-developers-2/" rel="noreferrer">&quot;A Field Guide to Developers&quot;</a>.</p> <blockquote> <p>Let me, for a moment, talk about the famous Aeron chair, made by Herman Miller. They cost about $900. This is about $800 more than a cheap office chair from OfficeDepot or Staples.</p> </blockquote> <blockquote> <p>They are much more comfortable than cheap chairs. [...] The ergonomics, especially of the newer models with lumbar support, are excellent.</p> </blockquote> <blockquote> <p>They last longer than cheap chairs. We’ve been in business for six years and every Aeron is literally in mint condition: I challenge anyone to see the difference between the chairs we bought in 2000 and the chairs we bought three months ago. They easily last for ten years. The cheap chairs literally start falling apart after a matter of months. You’ll need at least four $100 chairs to last as long as an Aeron.</p> </blockquote> <blockquote> <p>So the bottom line is that an Aeron only really costs $500 more over ten years, or $50 a year. One dollar per week per programmer.</p> </blockquote> <blockquote> <p>A nice roll of toilet paper runs about a buck. Your programmers are probably using about one roll a week, each.</p> </blockquote> <blockquote> <p>So upgrading them to an Aeron chair literally costs the same amount as you’re spending on their toilet paper, and I assure you that if you tried to bring up toilet paper in the budget committee you would be sternly told not to mess around, there were important things to discuss.</p> </blockquote>

<p>I am producing a system with aluminium enclosures all connected to a central unit which is connected to Earth. All the enclosures of the system have their chassis ground connected together via cable shielding. The system will be used in academic and industrial environments. For ecological purposes and to increase recyclability, I would like to avoid using paint and instead laser mark the sheet metals with the company's logo and the connector names above the connector slots.</p> <p>Paintless (raw) enclosures seem rare, are they bad practice? If so, why? Electrical safety? EMC?</p>

Paintless (raw) aluminium enclosures connected to Earth: Bad practice?

2024-02-18T17:16:01.883

702000

|cooling|

<p>I think you are mixing two related, but distinct concepts here: the heat and the infrared emission.</p> <p>While we have certain amount of heat generated in an electronic device, it is not an infrared light at any point. It is heat - a chaotic movement of the particles and is usually transferred away by heat conduction and convection.</p> <p>On the other hand, these days we do have some very efficient LEDs. There, we force the electrons to jump the bandgap in conditions that don't favor dissipating the energy as heat so the electrons have no choice other than releasing their energy as light. Even there, some 50% (or more) of the energy becomes heat.</p> <p>In a transistor (be it bipolar or mos or a whole lot of mos transistors in a computer chip) few electrons find their way jumping the bandgap and the silicon itself is well known to favor heat instead of photons in this case. Silicon is also not very much transparent, so the few generated photons have little chance to get out of the crystal.</p> <p>In short, there is little to be gained from extracting the photons from the chip.</p>

<p>Could the same principle of LEDs be applied to chip (silicon or gallium) design to shift the infra-red heat towards the blue range then direct it away fromt the chip with fiber to allow the chip to remain cooler? This would change the wavelength of the radiation from infra-red (heat) to the blue or green light range to allow for the chip to run cooler by redirecting the light.</p>

Light emitting transistors on chip to reduce heat

2024-02-18T22:32:39.293

702006

|verilog|simulation|hdl|modelsim|testbench|

<p>A couple of problems.</p> <p>You are using nonblcoking assigments in your DUT, but blocking assignments in your testbench. When you do the comparison, the DUT has not updated its values yet.</p> <p>You wait too many clock cycles after reset.</p> <p>This works for me</p> <pre><code> initial begin $dumpfile(&quot;dump.vcd&quot;); $dumpvars; error = 1'b0; reset = 0; #80; reset = 1; #10; expected_c0 = 0; expected_c1 = 2; if (expected_c0 != c0 | expected_c1 != c1) begin $display(&quot;$0t, Error in reset test&quot;); total_errors = total_errors + 1; error = 1'bx; end else error = 1'b0; reset = 0; repeat (100) @(negedge clk) begin if (expected_c0 == 7) begin expected_c0 = 1; expected_c1 = expected_c1 + 1; end else expected_c0 = expected_c0 + 1; if (expected_c0 != c0 | expected_c1 != c1) begin $write(&quot;$0t, Error in test c0=%b, c1=%b &quot;, c0, c1); $display(&quot;$0t, expected c0=%b, c1=%b&quot;, expected_c0, expected_c1); total_errors = total_errors + 1; error = 1'bx; end else error = 1'b0; end $display(&quot;Finished with %0d errors&quot;, total_errors); $finish; end </code></pre>

<p>I've been practicing writing some more advanced testbenches for my Verilog circuits. I thought I'd work with something simple: a double counter setup, where c0 is 3-bits long and c1 is 16-bits long. On paper, my circuit should work as follows:</p> <p>c0: 0, 1, 2, 3, 4, 5, 6, 7, 1, 2, 3, 4, 5, 6, 7, 1, 2, 3, 4, 5, 6, 7, ...</p> <p>c1: 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 4, ...</p> <p>I quickly made the circuit and tested it by hand, and it works as expected.</p> <p>My module:</p> <pre><code>module double_counter (reset, clk, c0, c1); input reset, clk; output reg [2:0] c0; output reg [15:0] c1; always @(posedge reset or posedge clk) begin if (reset) begin c0 &lt;= 0; c1 &lt;= 2; end else if (c0 == 7) begin c0 &lt;= 1; c1 &lt;= c1 + 1; end else c0 &lt;= c0 + 1; end endmodule </code></pre> <p>The testbench I wanted to write would check at every positive edge of the clock if the counters were equal to some expected values. However, I'm getting a ton of errors (according to the testbench, not syntax errors) and I am not sure what I am doing wrong. Can anyone please help me understand what's going on?</p> <p>My (old) attempt at a testbench:</p> <pre><code>module double_counter_tb; reg reset, clk; wire [2:0] c0; wire [15:0] c1; reg [2:0] expected_c0; reg [15:0] expected_c1; reg error; integer i; integer total_errors = 0; double_counter DUT (reset, clk, c0, c1); initial begin clk = 0; forever begin #20 clk = ~clk; end end initial begin error = 1'b0; reset = 0; #80; reset = 1; #40; expected_c0 = 0; expected_c1 = 2; if (expected_c0 != c0 | expected_c1 != c1) begin $display(&quot;$0t, Error in reset test&quot;); total_errors = total_errors + 1; error = 1'bx; end else error = 1'b0; #40; reset = 0; #80; repeat (200) @(posedge clk) begin expected_c0 = expected_c0 + 1; if (expected_c0 == 7) begin expected_c0 = 1; expected_c1 = expected_c1 + 1; end if (expected_c0 != c0 | expected_c1 != c1) begin $display(&quot;$0t, Error in test c0=%b, c1=%b&quot;, c0, c1); total_errors = total_errors + 1; error = 1'bx; end else error = 1'b0; end $display(&quot;Finished with %0d errors&quot;, total_errors); end endmodule </code></pre> <p>I'm running a relatively old version of ModelSim (I think it was 5.7 since that's all I had handy) if that is of any help. Thanks in advance!</p> <p><strong>EDIT</strong>: Based on @dave_59's answer, I was able to make considerable improvements to my previous testbench. My final, working testbench, looks like the following:</p> <pre><code>module double_counter_tb; reg reset, clk; wire [2:0] c0; wire [15:0] c1; reg [2:0] expected_c0; reg [15:0] expected_c1; reg error; parameter fileout = &quot;double_counter_results.txt&quot;; integer i, f; integer total_errors = 0; double_counter DUT (reset, clk, c0, c1); initial begin clk = 0; forever begin #20 clk = ~clk; end end initial begin f = $fopen(fileout, &quot;w&quot;); $fwrite(f,&quot;Beginning test...\n\n&quot;); error = 1'b0; reset = 0; #80; reset = 1; #10; expected_c0 &lt;= 0; expected_c1 &lt;= 2; if (expected_c0 != c0 | expected_c1 != c1) begin $display(&quot;$0t, Error in reset test&quot;); $fwrite(f,&quot;$0t, Error in reset test\n&quot;); total_errors = total_errors + 1; error = 1'bx; end else error = 1'b0; reset = 0; repeat (100) @(posedge clk) begin if (expected_c0 == 7) begin expected_c0 &lt;= 1; expected_c1 &lt;= expected_c1 + 1; end else expected_c0 &lt;= expected_c0 + 1; if (expected_c0 != c0 | expected_c1 != c1) begin $fwrite(f,&quot;Error in test c0=%b c1=%b, expected c0=%b, c1=%b\n&quot;, c0, c1, expected_c0, expected_c1); $display(&quot;$0t, Error in test c0=%b, c1=%b &quot;, c0, c1); $display(&quot;$0t, expected c0=%b, c1=%b&quot;, expected_c0, expected_c1); total_errors &lt;= total_errors + 1; error &lt;= 1'bx; end else error &lt;= 1'b0; end $display(&quot;Finished with %0d errors&quot;, total_errors); $fwrite(f, &quot;Finished with %0d errors&quot;, total_errors); $fclose(f); $finish; end endmodule </code></pre>

Verilog Double Counter Testbench Issues

2024-02-19T01:18:00.780

702011

|usb-c|usb-host|

<p>Yes, but not the way you are approaching it</p> <p>You'll need QC-to-USB PD translation. You can do this by interfacing a QC downstream (powered device) chip with a PD upstream chip (power source) using a small microcontroller. Translator &quot;widgets&quot; may also exist on the market, I didn't check.</p> <p>Some USB power testers offer this translation. I know that the Fnirsi FNB58 I got does it: you can plug it into a QC charger, select the translation option, and it will appear to other devices like it was a USB-C PD charger with higher voltages available.</p>

<p>There's a wall outlet with a USB-A fast charging port</p> <p>It has a USB-A charging port that supports 9V 1.67A fast charging.</p> <p>It uses FP6601Q and supports QC2.0/QC3.0.</p> <p><a href="https://i.stack.imgur.com/hthD3.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/hthD3.png" alt="enter image description here" /></a> I'm trying to change the USB-A charging port to a USB-C charging port, but it doesn't work well.</p> <p>Can we simply switch A to C port to support 9V 1.67A charging speed without USB-PD negotiations?</p> <p>Below is a circuit that I made simple. I simply changed the port and connected only pull-up resistance to the cc pin of the usb-c port. <a href="https://i.stack.imgur.com/MX0xv.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/MX0xv.png" alt="enter image description here" /></a></p> <p>However, it initially charges 9V 1.67A, but after a few minutes, the charging speed drops to 5V 1.67A</p> <p>I tried all 56k/22k/10k resistance with cc pull up resistance, but the result was the same.</p> <p>What should I do?</p>

Is it possible to apply quick charge 3.0 to USB-C?

2024-02-19T02:14:56.763

702028

|microcontroller|circuit-analysis|digital-logic|gpio|microprocessor|

<p>Having a 22uF capacitor directly on a MCU output is not OK, the current will be too large when toggling the pin.</p> <p>If you intend to control the IC anyway with a MCU, you can enable it after power supplies are stable.</p> <p>So if you do control the pin with MCU, you can leave out the RC delay circuit that would automatically pull the pin high.</p>

<p>I am using <a href="https://www.ti.com/lit/ds/symlink/ds90ub926q-q1.pdf?ts=1708322836074&amp;ref_url=https%253A%252F%252Fwww.google.com%252F" rel="nofollow noreferrer">DS90UB926QSQNOPB</a> in my design.This is a 24-Bit Color FPD-Link III Deserializer</p> <p>With Bidirectional Control Channel.I have a question regarding Power-down Mode Input Pin.</p> <p>Below is the description of PDB pin.</p> <p><a href="https://i.stack.imgur.com/1Pqhx.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/1Pqhx.png" alt="enter image description here" /></a></p> <p>TI recommendations for PDB pin is given below.</p> <p><a href="https://i.stack.imgur.com/4CARl.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/4CARl.png" alt="enter image description here" /></a></p> <p>My circuit is given below.</p> <p><a href="https://i.stack.imgur.com/xIy6A.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/xIy6A.png" alt="enter image description here" /></a></p> <p>My question is can I connect the PDN circuit to Microcontroller GPIO as shown below.</p> <p><strong>I need to control power up/down using a microcontroller.</strong></p> <p>Below is my circuit. Will it make any issues</p> <p><a href="https://i.stack.imgur.com/a3iO1.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/a3iO1.png" alt="enter image description here" /></a></p> <p>In the above circuit <strong>PD</strong> is coming from <a href="https://www.nxp.com/part/FS32K142UAT0VLFT#/" rel="nofollow noreferrer">Microcontroller GPIO</a></p> <p>May I know is this circuit is fine or not. Can I control as shown above.</p>

DS90UB926QSQNOPB Power down control using Microcontroller GPIO

2024-02-19T06:20:31.130

702032

|power-supply|usb|breadboard|

<p>You have 2W x 2 actuators x 8 devices = 32W. The maximum you can reasonably get out of a single USB port at 5V is 15W, most chargers can even only deliver 10W or less. So that's not going to work. Additionally, voltage drop will be significant if you draw that much power out of an ordinary USB cable. Since you apparently only need the 5V power and no data lines, I would suggest to use a lab power supply instead. These can more easily deliver the required current (you need roughly 7A to be on the safe side) and also use adequate cables for that.</p>

<p>I have an audio device with 8 channels, every 2 of which need to be powered by a 5V power outlet. Up until now, my lab used USB chargers to solve the problem.<br /> But now I have to improve upon it, and I want to make sure I keep to best practices.<br /> Each device powers 2 vibrating actuators with 5V USB cables. Instead of connecting them to a splitter, I'd like to place all 3 power lines on a singular breadboard, and connect them all to a single USB, like so:</p> <pre><code> * * * * * * * * * * - * * * * * * * * * * * - * * * * D1pwr D2pwr D3pwr * * USBPWR * * * D1gnd D2gnd D3gnd * * USBGND * * * * * * * * * * - * </code></pre> <p>Is this the safe way to connect them all? Or would you have a better idea?</p>

How to connect multiple devices using one USB port and a breadboard?

2024-02-19T07:29:05.047

702046

|power|switch-mode-power-supply|dc-dc-converter|buck|boost|

<p>Question:</p> <p>&quot;When we say average model, should it not predict the any cycle variation or transient behavior?&quot;</p> <p>My simple answer:</p> <p>Transient behavior of a voltage regulator can be seen by applying a step load and observing the output voltage response.</p> <p>When we simulate an average model in the time domain, the <em>response</em> of the output voltage, when a load step is applied, should be matching that of the switching model. The average model does give results in the same time scale, <strong>but</strong> it is missing the higher order effects that are captured in the switching model (the effects of each switching cycle along with parasitics). The benefit of the average model is that it is faster to simulate.</p> <p>When we simulate the average model in the frequency domain, we get the bode plot, which can also predict the transient behavior (response to step load).</p>

<p><a href="https://i.stack.imgur.com/U6226.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/U6226.png" alt="enter image description here" /></a></p> <p>This image is from Christophe Basso presentation. It has been mentioned in the slide that average model can predict the transient response but I have one question when we say average model then it should not predict the any cycle variation or transient behavior. Is my understanding correct?</p> <p>I can understand that an average model is a non linear model but how it is predicting the transient behavior that is not clear to me.</p> <p>Document Link:<a href="http://powersimtof.com/Spice.htm" rel="nofollow noreferrer">http://powersimtof.com/Spice.htm</a></p> <p>File Name: The PWM switch in transitioning models (Page: 3)</p>

Power Converter Average Modelling

2024-02-19T10:24:14.697

702049

|ac|power-engineering|terminology|power-grid|

<p>According to 'IEC 60038' courtesy <a href="https://en.wikipedia.org/wiki/IEC_60038#:%7E:text=Three%2Dphase%2050%20Hz,-230%20V%20%2F%20400&amp;text=Suppliers%20using%20220%20V%20%2F%20380,least%20within%20the%20European%20Union." rel="nofollow noreferrer">Wikipedia</a>,</p> <p>'Where two voltages are given separated by &quot;/&quot;, the first is the root-mean-square voltage between a phase and the neutral connector, whereas the second is the corresponding root-mean-square voltage between two phases.'</p> <p>Thus '3-phase 50 Hz 230 V / 400 V' refers to phase-to-neutral voltage of 230 V and phase-to-phase voltage of 400 V.</p>

<p>The widely known 3-phase grid in Europe with 50 Hz and 400 V between two phases and 230 V between each phase and neutral is often referred to as &quot;3 x 400 V&quot; or &quot;3 x 230 V&quot;.</p> <p>Is one of these expressions &quot;more true&quot; or more precise than the other? Or does it depend on additional details, such as whether a neutral is used or not?</p> <p>Or is there another, better way to denote it?</p> <p><strong>[Edit, 19 Feb 2024] Context:</strong> Assume I was to write a technical data sheet for an electrical device that is plugged into the 3-phase grid and has a 3P + N + PE connector.</p>

Terminology: Proper way to denote typical European 3-phase AC grid

2024-02-19T11:05:05.077

702050

|ldo|nmos|error-amplifier|

<p>One problem is that you are trying to use a BJT (Q2) as a switch for signal path between the error amplifier and the output FET. I'm not really sure what you are trying to accomplish there, but I doubt that Q2 is ever going to do what you want.</p> <p>When Q2 is off, there's no DC current path to set M1's gate potential, so the state of M1 is then undefined. With Q2 in any other state, M1's gate cannot fall below Q2's base (remember there's a PN junction between collector and base), and so M1's gate potential is severely constrained by whatever Q1's collector is doing.</p> <p>The other mistake seems to be that you are modifying the output of the error amplifier, which will not change the overall output at all. All that does is alter how far the op-amp has to raise or lower its own output, to achieve the same 5V at M1's source.</p> <p>In the circuit below I've added 2V to the output of the error amplifier, using source V1, but all that will happen is the error amplifier lowers its own output by 2V to compensate. The output is still 5V:</p> <p><img src="https://i.stack.imgur.com/tbbDr.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2ftbbDr.png">simulate this circuit</a> &ndash; Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a>}</p> <p>That closed loop tries to maintain 5V at the output regardless of what stuff you place in the loop, or at the output. If you want the loop to output less, then <em>ask</em> it in a more appropriate way:</p> <p><img src="https://i.stack.imgur.com/2Zmbo.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2f2Zmbo.png">simulate this circuit</a>}</p> <p>Here I am using Q1's collector to become grounded when <span class="math-container">\$V_{CUT}\$</span> goes high. When that happens, R3 and R5 form a potential divider, cutting the reference input potential by 80%, resulting in the output also being cut by 80%.</p> <p>The point is, change what the closed loop produces at its output by changing its input, not by messing with the loop in the middle. That's not a hard-and-fast rule, of course you can change the feedback loop, and there might be a hundred reasons to do that, but I don't think this is one of them.</p> <p>An analogy might be that you don't slow down a drill by grabbing hold of the shaft/chuck. By interfering with its closed loop like that, all that happens is motor torque rises in compensation, to maintain the same speed. You slow it by asking it in the usual way, which is by releasing the trigger a little.</p> <p>In your case that would be to lower the voltage you apply at the non-inverting input of the error amplifier.</p> <hr /> <p>Since you insist on interrupting the loop to take control of M1's gate, you need to be very sure that U1's output can no longer have any influence:</p> <p><img src="https://i.stack.imgur.com/5D7q1.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2f5D7q1.png">simulate this circuit</a>}</p> <p>When DISABLE goes high, M2 (which could also be a BJT) shorts M1's gate to ground, disabling output. Be aware though, that in this state U1 will do its best to correct the error (it is after all an error amplifier), and its output will go as high as it can, saturating against the positive supply. When the disable signal returns low, it will take a few microseconds for U1 to recover, during which M1's gate is way too high, and you'll probably see the output spike to well over 5V until U1 can settle back into a reasonable, stable state.</p> <p>I repeat, I don't recommend this approach, where you throw a spanner in the loop. Control the desired output state (0V) by modifying the potential at the non-inverting input of U1. Set <em>that</em> (input) to 0V instead; so that U1 is always in control, never producing wild swings at its output.</p>

<p>I am trying to generate 5 V with this circuit for a load of 100 mA with a 2% tolerance in the output voltage. I don't want to use LDO ICs due to various reasons.</p> <p>My intention here is to enable/disable the output by making the base of Q1 high (output enable), or low (output disable).</p> <p>This circuit works when I change R16 to 100 kΩ, but I don't know why. I added a 20 kΩ resistor between M1's gate and ground to make it work (I know the reason).</p> <p>I also want to replace M1 with an NPN transistor. What changes should I make to this circuit?</p> <p><a href="https://i.stack.imgur.com/NcJ4w.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/NcJ4w.jpg" alt="enter image description here" /></a></p>

Why is this LDO circuit not working?

2024-02-19T11:16:13.173

702055

|circuit-analysis|current|analog|

<blockquote> <p><em>Any help will be appreciated!</em></p> </blockquote> <p>I would start by using the formulas to calculate impedance and convert them to simple polar values. For instance, the voltage across the two terminals written as <span class="math-container">\$2\sin(wt+π/4)\$</span> converts to a polar format of <span class="math-container">\$1.4142 \angle 45\$</span>. And the current converts to <span class="math-container">\$0.7071\angle 75\$</span>. The impedance is therefore: -</p> <p><span class="math-container">$$2\dfrac{\angle 45}{\angle 75}\hspace{1cm} = \hspace{1cm} 2\angle-30\hspace{1cm} = \hspace{1cm} 1.7321 - j1$$</span></p> <p>So, you have a 2 ohm impedance that is capacitive with a series resistance like this: -</p> <p><a href="https://i.stack.imgur.com/Ovde0.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/Ovde0.png" alt="enter image description here" /></a></p> <p>Image from <a href="https://ecstudiosystems.com/discover/textbooks/lessons/AC/chapter4-3-series-resistor-capacitor-circuits/" rel="nofollow noreferrer">Series Resistor-Capacitor Circuits</a></p> <p>However, given that you haven't stated the angular frequency it's impossible to drill down more.</p>

<p>Professor gave us a problem and I can't seem to figure it out. The task seems quite simple: we have a black box that has some kind of RLC circuit inside it, one input wire and one output wire connected to AC. He gave us two equations: <span class="math-container">$$ u(t)=2\cdot \sin(\omega t+\pi/4) $$</span> and: <span class="math-container">$$ i(t)=\sin(\omega t+75^\circ) $$</span> Using the information given I need to figure out what the circuit inside the black box is. Any help will be appreciated!</p>

How to figure out the schematic inside a "black box" if the only information I have is the signal equation: U(t) and I(t)

2024-02-19T12:26:44.930

702057

|mosfet|circuit-protection|

<p>You don’t need a PMOS for that: “In the event that the breaker switch trips” you can just use the resistor and LED as shown in the simulation below.</p> <p><a href="https://i.stack.imgur.com/hffpn.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/hffpn.png" alt="enter image description here" /></a></p> <p>However, if you still want to use the PMOS, it will be important how the Load and the Circuit Breaker are connected.</p> <p>If the circuit breaker sits between the load and the ground, it will work in reverse as the simulation below shows. The LED will stay ON and it will turn OFF when the circuit trips. In this case you will need to add the capacitor C1.</p> <p><a href="https://i.stack.imgur.com/f0Y1C.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/f0Y1C.png" alt="enter image description here" /></a></p> <p>I will assume that you want the Circuit Breaker to sit between the Power supply and the load as it is normally done. The simulation below shows the result and you still need the capacitor C1.</p> <p><a href="https://i.stack.imgur.com/cxQXH.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/cxQXH.png" alt="enter image description here" /></a></p> <p>Thanks.</p>

<p>I am using a 15 A circuit breaker. To detect the trip, I have designed a P-MOSFET based circuit.</p> <p><a href="https://i.stack.imgur.com/11Nlf.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/11Nlf.png" alt="enter image description here" /></a></p> <p>The idea is to connect the load signal of circuit breaker to the gate of MOSFET, which is pulled down to ground. When the ciruit function is normal the Vgs will be close to zero. In the event the breaker switch trips, the Vgs will be -12 V and will alert the user. This is the first time I am using a P-MOSFET. On paper I believe this circuit should work. Are there any downsides to this application?</p> <p>Thanks Deepak</p>

P-MOSFET Circuit Breaker trip detection

2024-02-19T12:30:38.917

702060

|rf|digital-communications|modulation|phase|digital-modulation|

<blockquote> <p><em>Is there perhaps some mitigating factor to this that I'm not seeing?</em></p> </blockquote> <p>It's the same with normal modulation like AM or FM; you don't need to take it to a level that is more complicated to see that a square wave modulating a sinewave carrier will produce massive disruptive harmonics. So, what we do is band limit the square wave so that the harmonics caused by the modulation are reasonable and under control. Then we band-pass filter the output and, if necessary we filter even harder.</p> <p>We may even consider extending a data bit by a small amount to ensure that it &quot;changes&quot; the carrier as it passes through a more benign region like 0 volts. We do what we have to in order to keep down the harmonics in the transmitted signal.</p>

<p>I've recently learned about <a href="https://en.wikipedia.org/wiki/Phase-shift_keying" rel="nofollow noreferrer">PSK</a> and <a href="https://en.wikipedia.org/wiki/Quadrature_amplitude_modulation" rel="nofollow noreferrer">QAM</a>. I first came across it in <a href="https://youtu.be/0faCad2kKeg?t=278" rel="nofollow noreferrer">this youtube video</a> (timestamped), and my understanding for how it works has remained the same as what is shown in that video. (I also understand that QAM essentially &quot;adds&quot; amplitude modulation to PSK).</p> <p>To me this all makes sense for BPSK (binary psk, only 2 states), you just do a &quot;vertical flip&quot; of the carrier frequency:<br /> <a href="https://i.stack.imgur.com/1jYWQ.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/1jYWQ.png" alt="enter image description here" /></a></p> <p>What I can't quite grasp however is &quot;higher-order&quot; PSK, because then from the various states, you can get &quot;jumps&quot; between them, like this:<br /> <a href="https://i.stack.imgur.com/UNGay.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/UNGay.png" alt="enter image description here" /></a></p> <p>Having explored a few areas of electronics now, the idea that a &quot;square wave is composed by many sine waves (harmonics)&quot; has been firmly impressed upon me:<br /> <a href="https://i.stack.imgur.com/egV91.gif" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/egV91.gif" alt="enter image description here" /></a></p> <p>So it would follow that those &quot;jumps&quot; in the modulated carrier frequency between phase changes would generate many harmonics.<br /> This seems like it would be very undesireable because it would &quot;polute&quot; above parts of the spectrum, which may even be illegal.</p> <p>So does PSK work differently in practice than it does in theory? Is there perhaps some mitigating factor to this that I'm not seeing? Or did I just get it wrong from the start? Thank you.</p>

Phase modulation for binary data - higher frequency harmonics?

2024-02-19T13:12:37.893

702075

|power|switch-mode-power-supply|dc-dc-converter|modelling|

<p>The control-to-output transfer function of the Cuk converter can be described by a 4th-order polynomial expression. It can be analyzed using state-space averaging (SSA) but I feel the PWM switch model derived by Vatché Vorpérian in 1986 is unbeatable in terms of simplicity and efficiency for analyzing switching cells. Dr. Vorpérian did apply his technique to the Cuk converter and studied the effects of the magnetizing inductance on the ac response in a <a href="https://ieeexplore.ieee.org/document/532257" rel="nofollow noreferrer">paper</a> he published in 1996.</p> <p>I looked at this transfer function in my last <a href="https://rads.stackoverflow.com/amzn/click/com/1949267512" rel="nofollow noreferrer" rel="nofollow noreferrer">book</a> on small-modeling of switching converter and the below drawing is an excerpt:</p> <p><a href="https://i.stack.imgur.com/QLaz3.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/QLaz3.png" alt="enter image description here" /></a></p> <p>By replacing the nonlinear PWM switch model by its linearized version, you can determine the transfer function. This is a long and tedious exercise and resorting to the fast analytical circuits techniques or FACTs is one way to go. Another approach is to use a SIMPLIS model such as the <a href="http://powersimtof.com/Downloads/Book/Christophe%20Basso%20SIMPLIS%20Collection.pdf" rel="nofollow noreferrer">ones</a> you can freely download from my webpage. The ac response is obtained in a fraction of seconds and you can compare it with your symbolic expression:</p> <p><a href="https://i.stack.imgur.com/Agbji.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/Agbji.png" alt="enter image description here" /></a></p> <p>This Cuk converter can be extended to a coupled-inductor or an isolated version but it seriously complicates the analysis. However, the FACTs are, in my opinion, the best possible tool to extract the transfer functions you need.</p>

<p>I would like to create average model of Cuk converter but not getting any reference. Can anyone give any reference or some idea to start with?</p> <p><em>&quot;Generally Cuk converter is 4th order but if we use current mode control with coupled inductor then it becomes second order.&quot;</em></p> <p>Is this correct?</p>

Cuk Converter Average Model

2024-02-19T15:41:04.957

702078

|solar-cell|

<blockquote> <p>Currently, I can only have 20 different resistors ...</p> </blockquote> <p>20 different resistors is way overkill, if you can select more than one at a time, give you plenty of resistance variation.</p> <p>Let's say you have the following resistors, all able to be connected in parallel by their individual FET. 10, 20, 40, 80, 160 ohms ... I think you can see where this 2ⁿ sequence is going.</p> <p>As they are in parallel, if you want to set the load to a resistance manually, it's probably easier to think in terms of conductance, each resistor has half the conductance of the previous one. However, as you are already using an Arduino, let it do the sums for you! Ask it for a load resistance, it flips that to conductance, and closes the relevant FET switches to get to that total. Given the binary sequence, there is a unique set of closed switches for any given conductance, and it's trivial to select them.</p> <p>Select the largest resistor for the lowest load you want to put on your cell, perhaps 100 kΩ? 20 resistors and switches will allow the smallest one to be 0.2 Ω (or is it 0.1 Ω? fence-post logic!) giving you half of that with all switches closed as the highest load.</p>

<p>The project I am working on is an experimental setup to automatically characterize a solar cell. To obtain the I-V curve, the load across the cell is to be varied automatically from open circuit to short circuit. The way I am doing this is by connecting different resistors to the cell by switching corresponding MOSFETs. The MOSFETs are turned on using Arduino. Currently, I can only have 20 different resistors, not much more than that. The problem is that the resistance at which peak power point occurs varies with irradiance. The more the irradiance, the lower the load resistance corresponding to the peak power point decreases. When the solar cell is under a table lamp, peak power occures at 3kohm resistance. But the same occurs at under 100 ohms under daylight. As I can have only 20 sample points sufficient to construct the I-V curve and the load needs to be varied between 10kohm to 0 ohm, how can I accomplish that so that I can get sufficient samples as well as capture the peak power point? Is there any way a continuous variable load can be implemented?</p>

How to implement an automatic and continuous variable load across a solar cell to obtain its I-V characteristics?

2024-02-19T15:58:53.713

702092

|pcb|pcb-design|integrated-circuit|identification|

<p>The top one is a <a href="https://datasheet.lcsc.com/lcsc/2304140030_Diodes-Incorporated-74LVC2G04W6-7_C460538.pdf" rel="nofollow noreferrer">Diodes Inc 74LVC2G04W6-7</a> dual inverter.</p> <p><a href="https://i.stack.imgur.com/XvUOu.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/XvUOu.png" alt="enter image description here" /></a></p> <p><a href="https://i.stack.imgur.com/MPP9R.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/MPP9R.png" alt="enter image description here" /></a></p> <p>(Source: <a href="https://www.lcsc.com/product-detail/Inverters_Diodes-Incorporated-74LVC2G04W6-7_C460538.html" rel="nofollow noreferrer">lcsc.com</a>)</p> <hr /> <p>The second one is a <a href="https://www.mouser.de/datasheet/2/115/DIOD_S_A0007370613_1-2512869.pdf" rel="nofollow noreferrer">Diodes Inc AH180-WG-7</a> Hall-Effect switch.</p> <p><a href="https://i.stack.imgur.com/QGgH7.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/QGgH7.png" alt="enter image description here" /></a></p> <p><a href="https://i.stack.imgur.com/0Vl7C.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/0Vl7C.png" alt="enter image description here" /></a></p> <p>(Source: AliExpress)</p> <hr /> <p>The third one is likely a <a href="https://datasheet.lcsc.com/lcsc/1811131510_MICRONE-Nanjing-Micro-One-Elec-ME6211C33M5G-N_C82942.pdf" rel="nofollow noreferrer">Microne ME6211C33M5G-N</a> LDO regulator.</p>

<p>What are the ICs with the markings in the photos?</p> <p><a href="https://i.stack.imgur.com/4XgF8.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/4XgF8.jpg" alt="enter image description here" /></a></p> <p><a href="https://i.stack.imgur.com/OCMJl.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/OCMJl.jpg" alt="enter image description here" /></a></p> <p><a href="https://i.stack.imgur.com/iCLss.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/iCLss.jpg" alt="enter image description here" /></a></p>

I can't find these ICs marked Z20hD, K00 JB, S2UI

2024-02-19T18:00:39.583