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703966 | |inductor| | <p>IRL, an inductor will have a <em>self resonant frequency</em> SRF.<br />
From DC to, say, one decade below the SRF its impedance will rise pretty much in proportion to frequency.<br />
From one decade above, impedance is bound to <em>fall</em> for a couple of decades.<br />
Behaviour <em>at</em> SRF depends on the "Quality Factor" QF of the resonance circuit it should be considered at this frequency.<br />
With a high QF, I'm inclined to see impedance <em>increases exaggeratedly</em> here.<br />
I wouldn't call it <em>isolation</em> / <em>insulator</em> even where used to <em>block</em> unwanted HF.</p>
| <p>My question may seem a little controversial, but as I've been studying electronics for a short time, this question arose and I imagine that many of those who read it were able to help me.</p>
<p>From what I have studied, one of the properties of the inductor is to store energy in the form of a magnetic field when a current is applied to it.</p>
<p>According to the formula that determines the inductive reactance of inductors, the higher the frequency, the greater the impedance it presents.</p>
<p>If an inductor were subjected to a very high frequency, would it be possible for it to behave close to an insulator, due to the fact that its resistivity increases exaggeratedly?</p>
| Inductor as insulator? | 2024-02-26T16:48:35.333 |
703974 | |digital-logic|level-shifting| | <p>There is nothing extravagant using two N-MOSFETS to replicate the signal at a higher voltage. Double MOSFET ic's are common, small, cheap and convenient for this use.</p>
<p>Please note that high level on input pins often depends on the supply voltage. If it's supplied with 12V it may not see 2V as high level. While it will do if supplied with 5V. Check the data sheet carefully.</p>
| <p>Suppose I want to enable an IC by pulling EN pin high with an Arduino. Suppose that the IC works on 12V and accepts a minimum 8V as high but the Arduino only outputs 3.3V.</p>
<p>What is the simplest way to shift that voltage level? I've seen some level shifter ICs but can't I do it with simpler components? I thought of using two N-MOSFETs as below but still it looks messy.</p>
<p><a href="https://i.stack.imgur.com/JzQSx.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/JzQSx.png" alt="enter image description here" /></a></p>
<p>I was about to get in trouble for that because the IC I'm working on indeed works on 12V but when I checked the datasheet I learned that it accepts a minimum 2V as high on the EN pin. I'm relieved as I don't need to shift Arduino voltage. Nevertheless, I wanted to ask the question for future use.</p>
<p>Over a request, I've added my incomplete circuit schematic below, the values are wrong. The question is a general level shifting question, it is not about programming an Arduino (the source of input logic could be something else) or gate drivers.</p>
<p><a href="https://i.stack.imgur.com/gt9BH.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/gt9BH.png" alt="enter image description here" /></a></p>
| How can I shift a low logic voltage to a higher one in the simplest way? | 2024-02-26T17:57:25.873 |
703991 | |dc-motor|stepper-motor|torque|synchronous-motor| | <p>Brushless motor torque is limited by the attractive force of the magnets used in the rotor. The "torque motors" to which you are referring are really just like standard brushless motors; they have a wound stator and magnets on the rotor. The also act just as any brushless motor; they can be stepped or driven synchronously as with any standard brushless motor.</p>
<p>A more common, small diameter brushless motor design may have two to eight magnets, or poles, meaning that to generate torque, each of these poles exerts a tangential force to the energized windings. Compared to a torque motor, the magnets are close to the center of rotationand thus do not enjoy the mechanical advantage of the torque motor, whose magnets are much farther away from the center. This provides a lever arm to produce many times the torque of a small diameter motor from each magnet for the same field strength. In addition, a torque motor can have tens of poles. The combination means that although each pole may provide the same tangential force as in a smaller motor, the distance from the center and number of magnets means that the torque motor can produce orders of magneitude more torque than a small motor.</p>
<p>The trade-off is speed. A 60-pole torque motor must have a drive frequency of thirty times the rate of revolution, whereas a 4-pole motor will require only two times the revolution. Put another way, a 60-hz drive would result in 1800 RPM for a four-pole motor, but only 120 RPM for a 60-pole motor.</p>
| <p>A <a href="https://www.mmsonline.com/articles/what-to-know-about-torque-motors" rel="nofollow noreferrer">torque motor</a> is <a href="https://www.heidenhain.us/resources-and-news/what-are-torque-motors-and-benefits/" rel="nofollow noreferrer">'either a rolled-up linear motor or a classic servo drive with a large number of poles'</a>. As I understand it they are ironless 3 phase supply motors, though perhaps neither of these attributes are necessary. Also as I understand it both torque and hybrid synchronous stepper motors have a permanent magnet rotor.</p>
<p>Am I correct in saying then the fundamental difference between a torque motor and a hybrid synchronous stepper motor is the torque motor is 3 phase whereas the stepper is only 2? Or am I missing something? And also is a torque motor necessarily 3 phase and ironless, and if not are they and stepper motors not then the same thing?</p>
<p>Please explain how I'm wrong! Thanks</p>
| What's the difference between a direct drive/torque motor and a stepper? | 2024-02-26T20:45:09.687 |
704010 | |control-system|transfer-function|stability|pole-zeroplot| | <p>It has to be excited at the resonant frequency for the amplitude to blow up.</p>
<p>I'm using the following transfer function with a DC gain of 1 and poles as you have specified.</p>
<p><span class="math-container">$$\frac{32}{(s-8 i) (s+8 i) \left(s+\frac{1}{2}\right)}$$</span></p>
<p>I can reproduce the resonant behavior you are observing.</p>
<p><a href="https://i.stack.imgur.com/nN6DT.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/nN6DT.png" alt="enter image description here" /></a></p>
<p>This does not happen with a sinusoid input having a non-resonant frequency.</p>
<p><a href="https://i.stack.imgur.com/vw2w0.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/vw2w0.png" alt="enter image description here" /></a></p>
<p>Or a step input.</p>
<p><a href="https://i.stack.imgur.com/7Chpk.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/7Chpk.png" alt="enter image description here" /></a></p>
| <p>I have a system with the three poles 0+8i, 0-8i, and -0.5. When I input a sinusoidal signal, this is the output:
<a href="https://i.stack.imgur.com/NZ56V.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/NZ56V.png" alt="enter image description here" /></a>
Based on the poles, -0.5 is in the left side of the plane so it should be stable. +8i and -8i are on the axis so the output will oscillate. I am confused on why the signal is gaining magnitude as time increases? Based on the poles I would not think this would be the behavior. I thought it would be a steady sinusoid. Where is the amplification coming from?</p>
| Poles of system seem counter intuitive | 2024-02-27T02:18:48.820 |
704031 | |transistors|pcb|identification|surface-mount| | <p>It's a <a href="https://datasheet.lcsc.com/lcsc/1811100910_Richtek-Tech-RT8059GJ5_C20542.pdf" rel="nofollow noreferrer">Richtek RT8059</a> step-down converter.</p>
<p><a href="https://i.stack.imgur.com/0HMVJ.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/0HMVJ.png" alt="enter image description here" /></a></p>
<p><a href="https://i.stack.imgur.com/VN0aH.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/VN0aH.png" alt="enter image description here" /></a></p>
<p>(Source: <a href="https://www.lcsc.com/product-detail/DC-DC-Converters_Richtek-Tech-RT8059GJ5_C20542.html" rel="nofollow noreferrer">lcsc.com</a>)</p>
| <p>I was installing a dash camera into a vehicle and didn't realize the input voltage for the camera was only 5 V instead of the 12 V I obtained from the car. Once plugged in the camera let out the magic blue smoke and it wouldn't turn on again. I proceeded to open the camera and inspect all areas of the circuit board for any signs of damage and this was the only area I could see had an issue.</p>
<p>I have tried looking for this code on these lookup sites using the code on the chip, but I wasn't able to identify in order to replace it:</p>
<p><a href="https://smd.yooneed.one/" rel="nofollow noreferrer">https://smd.yooneed.one/</a><br />
<a href="https://alltransistors.com/smd-search.php?search=" rel="nofollow noreferrer">https://alltransistors.com/smd-search.php?search=</a><br />
<a href="https://www.s-manuals.com/smd/" rel="nofollow noreferrer">https://www.s-manuals.com/smd/</a></p>
<p>If anyone is able to help I would appreciate it as I would still like to use this camera if possible, since it is still good as far as i can tell.</p>
<p>Undamaged nearby SMD component having the same identification code:
<a href="https://i.stack.imgur.com/UsOrR.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/UsOrR.jpg" alt="Undamaged nearby SMD component having the same identification code" /></a></p>
<p>Damaged component:
<a href="https://i.stack.imgur.com/frOnj.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/frOnj.jpg" alt="Damaged component" /></a></p>
| Identifying SMD component on a dash camera PCB | 2024-02-27T08:31:47.187 |
704034 | |power-electronics|ltspice|simulation|gate-driving|bootstrap| | <blockquote>
<p><em>My problem is that whatever I select Vin to be above 200 V output, it
can't pass 200 V</em></p>
</blockquote>
<p>The absolute maximum reverse voltage rating for the bootstrap diode (<a href="https://www.mouser.com/datasheet/2/348/rf081l2s-243023.pdf" rel="nofollow noreferrer">RF081L2S</a>) is 200 volts. That's your problem: -</p>
<p><a href="https://i.stack.imgur.com/qJkyZ.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/qJkyZ.png" alt="enter image description here" /></a></p>
| <p>I am working on a half-bridge simulation in LTspice. For the gate drive circuit I am working with an IR2110. My problem is that whatever I select Vin to be above 200 V output, it can't pass 200 V.</p>
<p>I am attaching output voltage waveform for the case where Vin is 300 V. I think the problem is that the high-side switch can't turn on fully. I am attaching the high-side switch DS voltage in the 2nd picture. Any suggestion?</p>
<p><a href="https://i.stack.imgur.com/blV1E.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/blV1E.png" alt="Output Voltage" /></a></p>
<p><a href="https://i.stack.imgur.com/w3E0x.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/w3E0x.png" alt="HIGH SIDE Vds" /></a></p>
<p><a href="https://i.stack.imgur.com/FjrG3.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/FjrG3.png" alt="LtSpice SCH" /></a></p>
| IR2110 LTspice high-side switching problem | 2024-02-27T08:42:55.520 |
704054 | |amplifier|digital-logic|zener|display|meter| | <blockquote>
<p>Working voltage was max 30v and I burned the transistor BL P11 NPN (1A) with more input.</p>
</blockquote>
<p>BL P11 is the marking of BCX56 which is a 80V/1A NPN transistor.</p>
<p>The 10k (if I read it correctly) resistor, burnt transistor and the Zener appear to be forming a series pass linear regulator to have an output of one diode drop less than the Zener voltage.</p>
<p><img src="https://i.stack.imgur.com/ztmCr.png" alt="schematic" /></p>
<p><sup><a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fztmCr.png">simulate this circuit</a> – Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a></sup></p>
<p>I can't see properly but I assume that the regulator is there to power the logic ICs which normally should be supplied with a voltage of maximum 6V. So first, I'd expect the Zener to be something like a 5V6 or 3V9 to have 3.3V or 5V logic supply.</p>
<p>The voltage across the transistor will be the input-output difference. To burn the transistor this difference should exceed 80V. So you must have applied ~100V. Note that, in this case, quite possibly the BJT's junctions would be shorted together so the ICs supplied from this regulator could have been exposed to your high input voltage. This may result in shorted supply rails inside the ICs. And that is probably why you see a short across the Zener because after the BJTs death and the ICs the Zener will effectively be in parallel with the supply rails of the ICs.</p>
<p>So the ICs and transistor might be showing a short, not the Zener (although the Zener could have died as well because of a high voltage and therefore high bias current). I'd worry more about the ICs rather than the Zener here.</p>
| <p>This is Digital Volt Amp meter display module. Working voltage was max 30v and I burned the transistor BL P11 NPN (1A) with more input. Replaced with CXT5551 (600mA), operating current for module is about 20mA so this should work.</p>
<p>But display didn't turned on and found Zener to be bad when tested after removing. Tested with multimeter on diode mode beep both side. Resistance is 2 ohms both direction. Nothing written on the Zener. I am not expert in electronics so need your help in finding this.</p>
<p><a href="https://assets.nexperia.com/documents/data-sheet/74HC_HCT138.pdf" rel="nofollow noreferrer">74HC138D Datasheet</a></p>
<p>Thanks a lot!</p>
<p><a href="https://i.stack.imgur.com/ePCw0.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/ePCw0.jpg" alt="Volt Amp Meter Back" /></a></p>
| Help Find Unknown Bad Zener: Digital Volt Amp Meter | 2024-02-27T11:55:12.540 |
704060 | |usb|connector|usb-device|usb-c|usb-pd| | <p>USB PD on Type-C does not use the DP/DN pins, only the CC pins. Or rather, only one pin at a time, and the pin depends on which orientation you plug in the cable to connector.</p>
<p>The first connector with only one CC pin will only work in one orientation, as there is only one CC wire in a cable.</p>
<p>The second connector with no DP/DN pins cannot negotiate BC and won't work with BC supplies with Type-A supplies. As it cannot enumerate with a host, it cannot draw even 500mA, because to draw more than 100mA, it must be requested from host if it is OK to draw more than 100mA.</p>
| <p>I'm working on a project to update a device to use a Li-Ion battery rather than non-rechargables. I would like it to be charged via USB-C.</p>
<p>I have previously used <a href="https://datasheet.lcsc.com/lcsc/2006111335_INJOINIC-IP2721_C603176.pdf" rel="noreferrer">IP2721</a> to handle the power delivery negotiation but have recently found this chip (<a href="https://www.analog.com/en/products/max77751.html" rel="noreferrer">MAX77751</a>) which looks like it can handle the PD negotiation and the battery charging in a single IC. It also doesn't need to be configured by a microprocessor which is very useful for my project.</p>
<p>My issue is with the USB-C connector. The IC requires CC1, CC2, D+ and D- in order to negotiate the current draw. I am struggling to find a USB-C connector with these signals available. The PCBs will be soldered by hand so the fewer pins on the connector the better (Not sure I have a steady enough hand to solder a 24-pin connector).</p>
<p>I have found a connector which fits my requirement (<a href="https://datasheet.lcsc.com/lcsc/2112021230_YIYUAN-YTC-TC8S-126_C2927290.pdf" rel="noreferrer">Datasheet)</a> but it only has CC1 and SBU1. Would this be able to correctly negotiate PD with only one CC signal?</p>
<p>Alternatively, I found another connector (<a href="https://datasheet.lcsc.com/lcsc/2305120909_Hanbo-Electronic-MC-306LS-H60_C6332264.pdf" rel="noreferrer">Datasheet</a>) which has both CC1/CC2 signals but no D+/D-. What would the limitations be if I used this connector? I assume I would lose BC1.2 detection. With a Type C power brick I'm guessing this would be fine but if I used a legacy USB-A power brick with a "Type A-Type C" cable would it work at all?</p>
<p>It's quite a large battery (10000 mAh) so I'd rather not be limited to 500 mA charging if the negotiation fails.</p>
| Does USB-C Power Delivery require both CC pins or D+/D- pins? | 2024-02-27T12:36:46.980 |
704066 | |motor|identification| | <p><a href="https://i.stack.imgur.com/21fEh.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/21fEh.jpg" alt="enter image description here" /></a></p>
<p>The photo quality is poor but it appears to have drive teeth close to the motor (which makes sense as there is most support from the bearing and least bending moment on the shaft).</p>
<p>The large disc has square teeth with gap = tooth. This looks to me that it is intended for servo positioning or speed monitoring. It looks like about 48 teeth around.</p>
<p>Potential applications are anything in the Sharp back-catalogue that required controlled motion. I have no idea if they sold parts to other OEMs.</p>
<blockquote>
<p>Is it AC or DC?</p>
</blockquote>
<p>Almost certainly DC. Look for a permanent magnet and brushes to confirm.</p>
| <p>I am trying to identify the use of this small motor. I have searched and searched but no luck. Would it be used in an electronic device such as a old VCR? Is it DC or AC.</p>
<p><a href="https://i.stack.imgur.com/Qws3s.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/Qws3s.jpg" alt="enter image description here" /></a></p>
<p><a href="https://i.stack.imgur.com/LXXpi.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/LXXpi.jpg" alt="enter image description here" /></a></p>
| What would this small motor be used in? | 2024-02-27T13:11:16.543 |
704075 | |current| | <p>The maximum operating current is the current at which a device can operate indefinitely.</p>
<p>Maximum instantaneous current is the current above which damage will occur if applied only for an instant. This is obviously higher than the operating current.</p>
<p>Take as an example light bulb. It will run for a long time at the max operating current but if you apply more than the max instantaneous current even for an instant the filament will burn out.</p>
| <p>What is the difference between maximum instantaneous current vs maximum operating current? Can you please provide a simple explanation or analogy? Which current is always higher?</p>
| Maximum instantaneous current vs maximum operating current | 2024-02-27T13:46:12.387 |
704076 | |circuit-analysis|boost|resonance|topology| | <p>This is a 3-level single-phase boost converter. I think it has been originally presented in a <a href="https://ieeexplore.ieee.org/document/468984" rel="noreferrer">paper</a> at APEC in 1995:</p>
<p><a href="https://i.stack.imgur.com/r4Fxy.png" rel="noreferrer"><img src="https://i.stack.imgur.com/r4Fxy.png" alt="enter image description here" /></a></p>
<p>You can simulate this structure with SIMPLIS for instance and the below circuit is part of the free 120+ <a href="http://powersimtof.com/Downloads/Book/Christophe%20Basso%20SIMPLIS%20Collection.pdf" rel="noreferrer">ready-made templates</a> you can download from my <a href="http://powersimtof.com/Spice.htm" rel="noreferrer">webpage</a>:</p>
<p><a href="https://i.stack.imgur.com/gk50E.png" rel="noreferrer"><img src="https://i.stack.imgur.com/gk50E.png" alt="enter image description here" /></a></p>
<p>You can obtain the control-to-output transfer function quickly, stabilize the converter and check the THD:</p>
<p><a href="https://i.stack.imgur.com/Tfv6g.png" rel="noreferrer"><img src="https://i.stack.imgur.com/Tfv6g.png" alt="enter image description here" /></a></p>
<p>Please note that both switches are interleaved which reduces the overall stress.</p>
<p>This type of 3-level converter is often used in high-power three-phase PFCs to stack-up power stages. This helps reducing the voltage stress on semiconductors like using 650-V transistors in 2 x 400 V rather than 1200-V types with a two-level 800-V dc link rail for instance:</p>
<p><a href="https://i.stack.imgur.com/BAYWy.png" rel="noreferrer"><img src="https://i.stack.imgur.com/BAYWy.png" alt="enter image description here" /></a></p>
<p>Please note that this particular structure has not been very popular due to the floating operation of the input source which is often a show stopper for the EMI signature. You can check this <a href="https://toshiba.semicon-storage.com/ap-en/semiconductor/design-development/referencedesign/detail.RD172.html" rel="noreferrer">AN</a> from Toshiba which also proposes a single-phase 3-level T-type PFC which approaches the Vienna rectifier.</p>
| <p>I'm working on a new topology.</p>
<p>I looked it up myself, and it says "3-level boost converter" has a low inductor.</p>
<p>Is this right? How do I search it?</p>
<p><a href="https://i.stack.imgur.com/igUST.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/igUST.png" alt="enter image description here" /></a></p>
| Do you know about topologies that look like this? | 2024-02-27T13:47:58.867 |
704089 | |voltage-regulator|texas-instruments|shunt-regulator| | <p>From the 1st page of the datasheet:</p>
<p><a href="https://i.stack.imgur.com/K1vH4.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/K1vH4.png" alt="enter image description here" /></a></p>
<p>And no worries - there have been <strong>plenty</strong> of times I've looked everywhere but the 1st paragraph on the first page of a datasheet, technical standard, etc. I can only sympathize.</p>
| <p>I'm trying to figure out how to set R1 + R2 on the LM431 shunt regulator. I have input V+ that I can't change at 9 V and I want Vout at 5 V. What value of resistors should I use for that? How does the Vref value change?</p>
<p><a href="https://i.stack.imgur.com/yF75A.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/yF75A.png" alt="Shunt regulator" /></a></p>
| LM431 shunt regulator | 2024-02-27T15:37:30.820 |
704097 | |serial|can|termination| | <p>The differential output voltage specification (in section 6.10 of the datasheet) says that the driver can generate a voltage drop of at most 3 V over the two termination resistors (2× 120 Ω in parallel). So the theoretical worst-case power dissipation in a single resistor during normal operation is (3 V)² / 120 Ω = 75 mW.</p>
<p>If you want to survive shorting the bus line(s) to some other voltage, you might need more.</p>
| <p>I am using ISO1042 CAN Transceiver to establish communication between my board micro-controller with other board controller separated by 0.5m distance. I am using standard 120 ohm termination resistance. I would like to size the resistor. For that I would like to estimate worst case power dissipation for the resistor. How can I do that?</p>
<p>Vcc1 of ISO1042 is 3.3V and Vcc2 is 5V.</p>
| CAN BUS Termination resistor sizing | 2024-02-27T16:21:25.007 |
704106 | |pcb-assembly|solder-paste|solder-mask| | <p>It really depends on the thermal mass of the devices and the soldering process - there are various variations on the manual soldering process, typically involving various modes of preheating the board, components, and use of fluxes, vs IR reflow, vs vapor phase reflow.</p>
<p>I have used large solid copper pours with dense power converter designs, and they posed no problems. I evaluated the behavior of the board during vapor phase reflow by instrumenting it with thermocouples and not much was different compared to the same board, same components, but a layout with thermal reliefs for all the pads connected to copper pours (polygons). But that's just an anecdote, it the <strong>your mileage may and WILL vary</strong> caveat emptor very much applies!</p>
<p>There's plenty of circumstances where it would be problematic. So you will have to talk to your PCB assembly house in detail to make sure it's acceptable. They are the ones that will ultimately know (or are expected to know, at least). It really is process-specific, and even though PCB assembly sounds like a "single" concept, there's a lot of detail in how it's implemented on assembly lines, how the process parameters are set, etc.</p>
| <p>Will placing a copper polygon/zone over multiple (same-net) surface-mount (SMT) pin-pads create any thermal issues with the solder (for example, paste not sufficiently heating up)?</p>
<p>The solder mask will still keep individual pins separate, where there is sufficient pin-to-pin clearance (pin pitch).</p>
<p>For example, pins 48 and 49:</p>
<p><a href="https://i.stack.imgur.com/Nh4jF.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/Nh4jF.png" alt="enter image description here" /></a></p>
| Acceptable: Polygon/zone over surface-mount (SMT) pads? | 2024-02-27T17:12:30.917 |
704126 | |analog|integrated-circuit|stability|pole-compensation| | <p>I cannot see how pole-splitting could ever extend the bandwidth. The whole idea of the technique is to alter the sum of the poles, but not its product (otherwise we'd be increasing the order of the system) such that both dominant pole and the 2nd pole become further away from each other to obtain more phase margin (2nd pole must be sufficiently below the 0dB line).</p>
<p>Since the dominant pole is shifted to a lower frequency, that means the UGF, must be, inevitably, reduced as well.</p>
<p>So I'd say that statement is wrong. It's also not clear to me that Razavi wrote or verified those solutions you have found. Beware.</p>
| <p>Razavi gives the answer of why the compensation capacitor should not be placed between the gate and drain of M3 transistor.</p>
<p>Below are the quotations of his question and answer:</p>
<p>Question:</p>
<blockquote>
<p>Explain why, in the circuit of Fig. 10.76, the compensation capacitor should not be placed between the gate and the drain of M2 or M3.</p>
</blockquote>
<p>Answer:</p>
<blockquote>
<p>Putting Cc "across" M3 only affects the dominant pole and we cannot
take advantage of pole-splitting to widen the bandwidth.</p>
</blockquote>
<p>If I remember correctly, shouldn't pole-splitting narrow the bandwidth instead of widening it, as the following answer suggests?</p>
<p><a href="https://electronics.stackexchange.com/q/548282">Regarding Miller compensation</a></p>
<p><a href="https://i.stack.imgur.com/nuohe.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/nuohe.png" alt="Answer" /></a></p>
<p>Here is the picture of Fig.10.76</p>
<p><a href="https://i.stack.imgur.com/MO4jp.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/MO4jp.png" alt="Fig.10.76" /></a></p>
<p>After breaking the loop, we will eventually arrive at the following equivalent circuit. Let's call it Figure A.</p>
<p><a href="https://i.stack.imgur.com/FZgCq.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/FZgCq.png" alt="Figure A" /></a></p>
<p>After certain calculation, we will get the pole at node A,B and Y.</p>
<p><span class="math-container">$$\omega_A=\frac{1}{C_Ar_{o1}}=1.24\times10^9 \frac{rad}{s}\tag{1}$$</span>
<span class="math-container">$$\omega_B=\frac{1}{C_Br_{o3}}=1.30\times10^7 \frac{rad}{s}\tag{2}$$</span>
<span class="math-container">$$\omega_Y=\frac{1}{C_Yr_{o2}}=1.89\times10^9 \frac{rad}{s}\tag{3}$$</span></p>
<p>Thus,without compensation, <span class="math-container">\$\omega_B\$</span> should be the dominant pole. <span class="math-container">\$\omega_A\$</span> should be the 2nd pole, and <span class="math-container">\$\omega_Y\$</span> should be the 3rd pole.</p>
<p>Here is his entire explanation:</p>
<blockquote>
<p>For Problem 10.14, Cc should not be placed "across" M2 or M3 because of the location of the poles, since the dominant pole was at node B, the second pole at node A, and the third pole at node Y, we need to split the first two poles by placing Cc across M1.</p>
<p>Putting Cc "across" M2 only splits the 2nd and 3rd pole keeping the dominant pole unchanged, It moves he 2nd pole toward the dominant pole and 3rd pole away, that cannot give a 60 degree P.M.</p>
<p>Putting Cc "across" M3 only affects the dominant pole and we cannot take advantage of pole-splitting to widen the bandwidth.</p>
</blockquote>
<p>Reference: Razavi, <em>Design of Analog CMOS Integrated Circuits</em></p>
| Does pole-splitting narrow or widen the bandgap width? | 2024-02-27T19:41:51.027 |
704135 | |circuit-analysis|mutual-inductance| | <p>Author of <a href="https://github.com/kpobrien/JosephsonCircuits.jl" rel="nofollow noreferrer">JosephsonCircuits.jl</a> here. You can include mutual inductance with the mutual coupling coefficient <code>K</code>. Here is an example where we see a mutual inductance results in the same scattering parameters as the T-circuit provided by @arnold8a:</p>
<pre><code># inductively coupled LC resonator example
using DSP
using Plots
using JosephsonCircuits
@variables R1 L1 K1 L2 C1
# netlist with a mutual inductor
circuit1 = [
("P1","1","0",1),
("R1","1","0",R1),
("L1","1","0",L1),
("K1","L1","L2",K1),
("L2","2","0",L2),
("C1","2","0",C1)]
# netlist with T circuit equivalent to mutual inductor
circuit2 = [
("P1","1","0",1),
("R1","1","0",R1),
("La","1","2",L1-K1*sqrt(L1*L2)),
("Lb","2","0",K1*sqrt(L1*L2)),
("Lc","2","3",L2-K1*sqrt(L1*L2)),
("C1","3","0",C1)]
circuitdefs = Dict(
L1 =>1000e-12,
L2 =>2000e-12,
C1 => 900e-15,
R1 => 50.0,
K1 => 0.1,
)
w=2*pi*(3.5:0.01:4.0)*1e9
sol1 = hblinsolve(w,circuit1,circuitdefs);
sol2 = hblinsolve(w,circuit2,circuitdefs);
plot(sol1.w/(2*pi*1e9),
unwrap(angle.(sol1.S(
outputmode=(0,),
outputport=1,
inputmode=(0,),
inputport=1,
freqindex=:),
)),
ylim=(-2pi,1.1*pi),
label="mutual inductor",
xlabel="Frequency (GHz)",
ylabel="Phase (radians)",
linewidth=2,
)
plot!(sol2.w/(2*pi*1e9),
unwrap(angle.(sol2.S(
outputmode=(0,),
outputport=1,
inputmode=(0,),
inputport=1,
freqindex=:),
)),
label="T-circuit equivalent",
linestyle=:dash,
linecolor=:black,
linewidth=2,
)
</code></pre>
<p><a href="https://i.stack.imgur.com/0ul1y.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/0ul1y.png" alt="enter image description here" /></a></p>
<p>If you have questions about the code or find bugs, you are welcome to open an issue or start a discussion at the Github repo.</p>
| <h2>Background</h2>
<p>I don't have any background in electrical engineering. My knowledge is very superficial. I am simulating a circuit which has mutual inductance between two components. However, the software package I want to use (<a href="https://github.com/kpobrien/JosephsonCircuits.jl" rel="nofollow noreferrer">JosephsonCircuits</a>) to simulate does not allow any method to set the mutual inductance. For example, another simulator that I have used for the same task (<a href="http://wrcad.com/wrspice.html" rel="nofollow noreferrer">WRSpice</a>) allows you to specify mutual inductance between two components.</p>
<hr />
<h2>Question</h2>
<p>So, my question is: Is there any way to emulate the effect of mutual inductance by only using capacitors, resistors and inductors? Is there a way to construct an equivalent circuit?</p>
<hr />
<h2>Details</h2>
<p>The following is the circuit I want to simulate:</p>
<p><a href="https://i.stack.imgur.com/kIVyV.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/kIVyV.png" alt="enter image description here" /></a></p>
<hr />
<h2>My attempt</h2>
<p>Looking at some online resources, it seems that I can emulate the behaviour of the above circuit using the following circuit:</p>
<p><a href="https://i.stack.imgur.com/00I8K.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/00I8K.png" alt="enter image description here" /></a></p>
<hr />
<p>Is that correct? If not, what would be an equivalent circuit that gives the same effects as the one with mutual inductance but only uses the circuit components and no mutual inductance?</p>
| How to emulate effect of mutual inductance? | 2024-02-27T20:44:01.460 |
704145 | |dc-dc-converter| | <p>As Andy stated in his answer, the primary (magnetising) inductance of a forward converter's transformer is usually much higher than that of a flyback converter for the same power levels and switching frequency. This brings lower magnetising currents and therefore lower losses.</p>
<p>A flyback converter transformer is a store-and-transfer thing i.e. the energy is stored in the primary magnetic field and then transferred to the secondary <em>(Energy storage and transfer are done by the secondary-side choke in a forward converter as it operates just like a buck)</em>. This requires an air gap, and the presence of an air gap basically means loss (Research terms here: Eddy current loss, proximity effect, proximity loss). An air gap is not necessarily needed in a forward converter.</p>
| <p>If you read comparisons of different topologies in the context of power, you may notice that forward converters are usually recommended for higher power levels compared to flyback converters.</p>
<p>Could you please check my reasoning: one of the reasons for this lies in the transformer design. In a flyback converter, ALL the output energy is "accumulated" in the transformer, resulting in high core losses due to magnetization.</p>
<p>In a forward converter, all the energy goes directly to the secondary winding where it then goes to the rectifier and LC filter.</p>
<p>But in this reasoning, I still don't understand this... because in a forward converter, all the losses associated with core magnetization have been transferred from the transformer to the inductance, and in total, we should get the same losses.</p>
<p>Can you help me understand this?</p>
| Comparison of forward and flyback converters in terms of losses | 2024-02-27T23:27:35.913 |
704152 | |operational-amplifier|adc|level-shifting|instrumentation-amplifier|dc-offset| | <p>I am not familiar with Multisim. If the scope has ac coupling capability, make sure it is set to dc coupling.</p>
| <p>I want to shift the measured EMG input signal to the positive side to use ADC. I used the REF input of AD8421 to add an offset of <strong>2.5V</strong>. I simulated the circuit below from the <a href="https://www.analog.com/media/en/technical-documentation/data-sheets/ad8421.pdf" rel="nofollow noreferrer">AD8421 datasheet</a> on Multisim.</p>
<p><a href="https://i.stack.imgur.com/2YMVn.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/2YMVn.png" alt="circuit diagram" /></a></p>
<p>The output is only amplified but not <strong>level-shifted</strong>. What am I doing wrong?</p>
<p><a href="https://i.stack.imgur.com/a3IYj.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/a3IYj.png" alt="Multisim circuit simulation" /></a></p>
| Level-Shifting not working in Instrumentation Amplifier | 2024-02-28T00:58:49.870 |
704161 | |ethernet|troubleshooting|over-current| | <p>The error is that there are no magnetics and your device passes 3.3V supply through the cable and other device.</p>
<p>Plugging it to another device will short 3.3V to GND through the cable, depending on how the other device terminates the wiring.</p>
<p>Some devices leave unused pins floating so nothing happens, but as those wires are used for gigabit ethernet, there is a risk of damage to the device, as the DC current will flow through the signal transformers.</p>
<p>So, an Ethernet design always needs the transformers, either as a separate discrete module, or integrated into the connector.</p>
| <p>I made a custom single board computer based on the Allwinner V3s. This system on chip has an integrated PHY.</p>
<p>All components seems to work except I noticed that when I plug the ethernet cable to a switch, the power is cut off at the PMIC level. The LEDs I have for 3.3V, 1.8V and other systems are off, and there's no signal on serial.</p>
<p>Out of the several boards I made, one could still keep the system running when plugged, but the current consumption was about 1.1 amperes while it is usually below 100mA. The PMIC was burning hot. For the other boards the PMIC seems to put itself in security mode and no heat.</p>
<p>This behavior does not happen at all when I plug to my router, no over-consumption, no failure, the OS starts and I get an IP with DHCP.</p>
<p>This is the schematic for the RJ45 connector and the integrated PHY input:</p>
<p><a href="https://i.stack.imgur.com/rAdP0.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/rAdP0.png" alt="schematic" /></a></p>
<p>I did not add the magnetics as all the reference designs I have seen with that SoC didn't have one.</p>
<p>Some info:</p>
<ul>
<li>I tried with 2 gigabit switch, same brand, I will try another if I can find one.</li>
<li>The router is also gigabit ethernet.</li>
<li>Board and switch are plugged on the same wall plug.</li>
<li>Connecting two boards together causes no issue.</li>
<li>I tried several cables, same result.</li>
<li>On the schematic, the original RJ45 port has integrated LEDs and a metal shield, I changed it for a plastic one without LEDs.</li>
</ul>
<p>I don't understand why a router connection would be perfectly fine and a switch not.</p>
<p>Edit: Most designs have the HR911105A connector which I found has integrated magnetics, maybe this is the issue here.</p>
<p>Edit 2 : I installed a RJ45 port with magnetics and all is working fine now ! thanks a lot</p>
| Why do my boards shut off when I connect an RJ45 cable to a switch but not a router? | 2024-02-28T04:52:36.127 |
704166 | |operational-amplifier|circuit-analysis|transfer-function|transimpedance-amplifier| | <blockquote>
<p><em>The two approaches seem contradictory. Which one is correct?</em></p>
</blockquote>
<p>Any impedance in series with a current source is of no consequence in the derivation of a transfer function and, that series impedance can be removed and replaced with a short circuit. This rule is basic 101 circuit analysis. Just as any impedance in parallel with a voltage source is irrelevant.</p>
<blockquote>
<p><em>Is the output voltage constant or not?</em></p>
</blockquote>
<p>It is constant for the reasons given above.</p>
| <p>Consider this circuit.
<a href="https://i.stack.imgur.com/QZUfa.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/QZUfa.jpg" alt="enter image description here" /></a></p>
<p>Since a constant current source is present, the output voltage will always be <span class="math-container">$$V_o=i_sR_f$$</span></p>
<p>However, you can also drive <span class="math-container">$$i_s=i_c+i_R=C\frac{dv_c}{dt}+v_c/R$$</span></p>
<p>Then you can say that the output voltage is a function of capacitor voltage and is an exponential function.</p>
<p>The two approaches seem contradictory. Which one is correct? Is the output voltage constant or not? Why?</p>
<p>Edit: Assume the current source is initially turned off, then turned on at t=0. So I am interested in the transient situation just after turning on.</p>
| Transimpedance amplifier with parallel RC | 2024-02-28T05:47:24.287 |
704174 | |voltage|audio|rms| | <p>0 dBm is 1mW, to convert into voltage you need to know the impedance, which in this case is "600 ohms phone line", so 0dBm in audio context is 0.775 V RMS. In a RF context you'd use 50 or 75 ohms so the voltage would not be the same.</p>
<p>dBu and dBv are the same. 0dBm = 0dBv = 0dBu = 0.775V RMS.</p>
<p>0dbV (with a capital V) = 1V RMS. </p>
<blockquote>
<p>what does -10dBV imply?</p>
</blockquote>
<p><span class="math-container">\$ 1V . 10 ^{-10/20} = 0.316V RMS \$</span></p>
<p>(if the V was capitalized, otherwise replace 1V with 0.775V)</p>
<blockquote>
<p>What is the actual RMS value of an RCA output</p>
</blockquote>
<p>Throw a dice and divide by 3 for RMS.</p>
<p>Signal to noise ratio is directly proportional to amplitude, likewise for noise immunity on the way between boxes, so high quality gear tends to have high output levels in order to score better on SNR benchmarks.</p>
<p>This means if you have an older amp which was designed for oldskool line levels (-10dBV) and you use it with a modern source, which will probably output 2V RMS or more, you will only get to use a tiny fraction of the volume pot, mostly at the left.</p>
| <p>Searching the RCA phono input spec online does not garner any official documentation, probably due to the large number of voltage levels and power levels being used in commercial products. Looking at the Wikipedia page on <a href="https://en.wikipedia.org/wiki/Line_level" rel="nofollow noreferrer">line level</a>, a graph is provided with peak voltages of consumer and pro equipment.<a href="https://i.stack.imgur.com/koWO8.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/koWO8.png" alt="Line level for consumer and pro equipment" /></a></p>
<p>However, searching RCA RMS voltage online reveals a lot of discrepancies, with some people saying its peak is around .5V while other sources state different voltages of 775mV(0dBV) RMS and many other differing voltages.</p>
<p>What is the actual RMS value of an RCA output, and what does -10dBV imply?</p>
| RCA RMS voltage | 2024-02-28T07:25:23.010 |
704181 | |temperature|thermistor|thermocouple| | <p>You may have error due to heat conducted down the thermocouple leads, which will reduce the measured temperature (bring it closer to ambient, to be more accurate). To minimize this use the smallest gauge of thermocouple that is practical and keep as much length of the leads in contact with the surface you are trying to measure as is practical.</p>
<p>You can find stick-on polyimide-insulated ribbon thermocouples that are way better than cheap bead thermocouples (and are available in popular alloy combinations such as ISA/ASTM E, J, K, T). A bit of insulation on the back and Robert's your uncle.</p>
<p>Cold junction stability is important when you are trying to measure close to room temperature, so make sure your measuring instrument is up to the job and that you have properly connected the sensor.</p>
<p>300A is also quite a bit of current in relation to the tens of uV/°C T/C output and you may have some effect due to that.</p>
| <p>I want to test the accuracy of the NTC soldered in a current sensing board with a shunt resistor. For that, I attached a thermocouple type K to the junction of the shunt using epoxy and applied a current of 300A to register the temperatures captured by both the NTC and the thermocouple using CAN. The results are attached below, red is Thermocouple and blue is NTC, the problem is that I'm expecting the thermocouple temperature to be higher or equal to the NTC's and not have much difference between them (2 or 3°C difference), which is not the case. I want to understand:</p>
<ul>
<li>the potential causes of this result.</li>
<li>If it's possible for the NTC's temperature to be higher, why is that?</li>
<li>Are there better ways to attach the thermocouple?</li>
</ul>
<p><a href="https://i.stack.imgur.com/USRWN.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/USRWN.png" alt="Temperature comparison" /></a></p>
| Thermocouple vs NTC | 2024-02-28T09:06:01.397 |
704183 | |adc| | <blockquote>
<p>Is the reference voltage <span class="math-container">\$V_{ref} = 0.625\$</span>V?</p>
</blockquote>
<p>We can't say that. And it's not indicated in the datasheet. The reference voltage determines the full scale voltage but this doesn't necessarily mean that the reference voltage equals to the full scale voltage <em>(e.g. The ADC might be doing some mathematical operations inside)</em>. All we know is that the full-scale voltage is 0.625V. The reference could be something else.</p>
<blockquote>
<p>Then could I say, as the AD9361 has 12-bit ADC, LSB = <span class="math-container">\$\frac{V_{ref}}{2^{11}}=0.305\$</span>mV?</p>
</blockquote>
<p>Your LSB calculation is wrong. LSB is ~153 μV:</p>
<p><span class="math-container">$$
\text{LSB}=\frac{V_{FS}}{2^N-1}=\frac{0.625}{2^{12}-1}=152.6 \ \mathrm{\mu V}
$$</span></p>
<p>where <span class="math-container">\$V_{FS}\$</span> is the full scale voltage, and <span class="math-container">\$N\$</span> is the number of bits that the ADC generates.</p>
<blockquote>
<p>Here I don't understand how we get the 63.5 dBFS because <span class="math-container">\$20 \log_{10}(2^{11}) = 66.22\$</span>dB.</p>
</blockquote>
<p>It doesn't seem like you can directly relate the numbers here.</p>
<p>"Low power threshold" is a programmable number given in -dBFS (<em>minus</em> decibels relative to full scale, which basically means less than 0.625V). In this case, anything down to -63.5 dBFS can be selected as a low power threshold (If you read the datasheet further, some functions like "auto incremental gain" can be used in case the incoming signal level is lower than this threshold).</p>
<p>So, -63.5 dBFS corresponds to ~418 μV:</p>
<p><span class="math-container">$$
-63.5 = 20 \ \log\frac{V_{LP}}{V_{FS}}=20 \ \log\frac{V_{LP}}{0.625} \\
\Rightarrow V_{LP}=417.7 \ \mathrm{\mu V}
$$</span></p>
<blockquote>
<p>The "resolution 0.5 dBFS per LSB" also makes me clueless.</p>
</blockquote>
<p>This is a multiplicator that you use when programming the low power threshold value. If the resolution was 1 dBFS / LSB then writing 0x15 to the settings register (assuming an 8-bit register) would set the threshold value to -21 dBFS. Since it's 0.5 dBFS / LSB, writing 0x15 will set the threshold to -10.5 dBFS. To program a low power threshold of -63.5 dBFS you'll need to write 127 or 0x7F.</p>
| <p>I got hard time understanding the definition of dBFS and resolution per LSB.</p>
<p>In the <a href="https://www.farnell.com/datasheets/2007082.pdf" rel="nofollow noreferrer">AD9361 manual (page 35 of 128),</a></p>
<blockquote>
<p>The ADC maximum input (0 dBFS) is 0.625 V peak. However, to avoid
compression the maximum recommend peak input level to the ADC is 0.5 V
peak, which is 1.9 dB lower than full scale.</p>
</blockquote>
<p>Is the reference voltage <span class="math-container">\$V_{ref} = 0.625\$</span>V? Then could I say, as the AD9361 has 12-bit ADC, LSB = <span class="math-container">\$\frac{V_{ref}}{2^{11}}=0.305\$</span>mV?</p>
<blockquote>
<p>The low power threshold is an absolute threshold measured in −dBFS with a resolution of 0.5 dBFS per LSB. The range is from 0 dBFS to −63.5 dBFS.</p>
</blockquote>
<p>Here I don't understand how we get the 63.5 dBFS because <span class="math-container">\$20 \log_{10}(2^{11}) = 66.22\$</span>dB. The "resolution 0.5dBFS per LSB" also makes me clueless.</p>
<p>How do we derive these numbers?</p>
| (AD9361) dBFS and resolution per LSB | 2024-02-28T09:19:14.333 |
704196 | |operational-amplifier| | <p>After a close look, your circuit appears to be operating correctly.</p>
<ul>
<li>Your current source is providing pulses at the rate of 10 per second. The output of the op-amp is pulsing at the rate of 10 pulses per second. That looks reasonable to me. The output follows the input, just as it should.</li>
<li>The pulses at the output reach about 13V at the peaks, about what I'd expect from a <a href="https://www.st.com/resource/en/datasheet/tl071.pdf" rel="nofollow noreferrer">TL071 operating on 15V.</a> On a 15V power supply, the TL071 output can reach about 13.5V. The output voltage swing of the TL071 is given in the datasheet.</li>
</ul>
<p>In all, the circuit and the simulation seem to be OK. The output follows the input pulses, and amplifies them. Its output clips to a level appropriate to the IC and the supply voltage.</p>
| <p>I have a charge amplifier built with the assistance of <a href="https://www.ti.com/lit/an/sloa033a/sloa033a.pdf" rel="nofollow noreferrer">this datasheet</a>.</p>
<p>According to this datasheet,</p>
<p><a href="https://i.stack.imgur.com/VJZAK.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/VJZAK.png" alt="enter image description here" /></a></p>
<p>In this charge amplifier I built, (see below) the input is 50mA and Cf is 100u. As</p>
<p><a href="https://i.stack.imgur.com/ggyxp.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/ggyxp.png" alt="enter image description here" /></a></p>
<p>This results in an output voltage of 50V, which exceeds the rated voltage.</p>
<p><a href="https://i.stack.imgur.com/O1798.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/O1798.png" alt="enter image description here" /></a></p>
<p>As a result, the system does not provide the mathematically expected input.</p>
<p><strong>What I want to know, however, is why the system failed the way it did.</strong> My output looks like this.</p>
<p><a href="https://i.stack.imgur.com/JUgtv.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/JUgtv.png" alt="enter image description here" /></a></p>
<p>If the voltage is exceeded, I would have expected it to reach a constant 14-15V (compensating for
usual op-amp tolerances), but not fluctuate wildly between 1 and 13V. Please let me know if more information is required.</p>
| What happened when I exceeded the range of the charge amplifier? | 2024-02-28T11:00:20.057 |
704198 | |power-supply|analog|signal-generator| | <p>It depends on how much noise the VDD line puts out, if it's on a switcher and the inductor won't be sufficient at filtering, a low noise LDO would be a better option. There is no PSRR rating in the AD9833 datasheet, but it does say that it needs a 0.1uF and 10uF cap and it has it's own power supply that operates at Vcc/2</p>
| <p>I'm in the process of building a signal generator using the <a href="https://www.analog.com/media/en/technical-documentation/data-sheets/ad9833.pdf" rel="nofollow noreferrer">AD9833</a>. It requires a dedicated analog power supply, but I'm not entirely clear on how to devise such a power supply.</p>
<p>From various resources like textbooks and open-source projects, I've observed that analog power supplies are often fashioned by integrating some inductors and capacitors (forming a low-pass filter) after a digital power supply, akin to the diagram below.</p>
<p><a href="https://i.stack.imgur.com/b6MPA.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/b6MPA.png" alt="An analog power supply from open-source project" /></a></p>
<p>I'm uncertain about how to determine the appropriate specifications of these components. Additionally, if this portion of the circuit indeed serves as a low-pass filter, how should I manage the power supply if the frequencies of my digital and analog components are similar?</p>
| How to create an analog power source? | 2024-02-28T11:14:48.737 |
704213 | |current|current-measurement|charge| | <p><strong>Observation</strong></p>
<p>You are using an op-amp as a TIA (transimpedance amplifier) to measure AC currents with the most negative supply pin for the op-amp tied to ground. The reference input (the non-inverting input) is also tied to ground. This means that the op-amp output is trying to keep the inverting input at 0 volts/GND.</p>
<p><strong>Problem #1</strong></p>
<p>If the piezo produces currents in excess of 10 mA and, the output is unable to drive below ground to keep the inverting input at 0 volts then, the input protection diode takes the full 10 mA. The absolute maximum as stated in the <a href="https://www.ti.com/lit/ds/symlink/tl071.pdf?ts=1709102601722&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252Fde-de%252FTL071" rel="nofollow noreferrer">data sheet</a> is 10 mA for the TL071A inputs: -</p>
<p><a href="https://i.stack.imgur.com/2uvN9.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/2uvN9.png" alt="enter image description here" /></a></p>
<p>So, there's a distinct possibility that you may have destroyed the op-amp.</p>
<p><strong>Problem #2</strong></p>
<p>But, there's another more likely problem and that is the input range that the TL071A can handle: -</p>
<p><a href="https://i.stack.imgur.com/D7i6H.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/D7i6H.png" alt="enter image description here" /></a></p>
<p>It clearly states that the lowest valid input has to be at least 4 volts higher than the negative supply rail so, if I were you I'd employ a negative rail of at least 5 volts and pray that the current you are measuring can always be dealt with properly by the op-amp output.</p>
| <p>I have a <a href="https://electronics.stackexchange.com/questions/48816/charge-model-vs-voltage-model-for-piezo-electric-sensor">piezoelectric disk</a>. I am trying to determine the sensitivity of this disk for the sake of making a charge model more accurate. The charge model in question:</p>
<p><a href="https://i.stack.imgur.com/RyzJh.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/RyzJh.png" alt="enter image description here" /></a></p>
<p>I have attached the piezoelectric disk to a multimeter. So far, I have measured the output voltage of the disk by fastening it to a shaker. However, I am using a charge model instead of a voltage model, and would like to be able to determine the current.</p>
<p>So far, the PZT does not respond to AC or DC current detection, with no changes to the AC or DC current regardless of pressure placed on the PZT. This is different from voltage detection where a response is immediate.</p>
<p><a href="https://i.stack.imgur.com/3FT4A.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/3FT4A.jpg" alt="enter image description here" /></a></p>
<p>I am aware that a PZT generates a charge instead of a current, but even when placed on the shaker when the pressure/acceleration is constantly changing (and the charge should be generating constantly), I am unable to detect any current from the PZT.</p>
<p>Please let me know if more information is required.</p>
| Piezoelectric Disk Charge Generation and Detection | 2024-02-28T13:11:08.697 |
704219 | |mosfet|mosfet-driver| | <p>Driving with single transformer isn’t possible? For 100kHz the core size can be very small like 15mm ferrite ring with about 3x50 turns.</p>
<p><a href="https://i.stack.imgur.com/vZS4z.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/vZS4z.jpg" alt="enter image description here" /></a></p>
| <p>I need to make a bidirectional load switch which can work with voltages 0-18V (or as low as possible if 0V isn't feasible) and currents from -3A to 3A and which needs to be able to switch quite fast (ideally 100-200kHz). I have an additional 24V rail (and optionally -10V one) which can be used to power the gate driver. I guess N-channel MOSFET should give better performance (lower Rdson) but that's not too critical.</p>
<p>What sort of driving circuit can I use to control the switch using logic level voltage and should I use common-drain or common-source connection? Are there some commercially available drivers which are powered from separate power rails - I tried searching haven't found anything yet which fits all requirements?</p>
| Driving high side back-to-back MOSFETs | 2024-02-28T14:34:18.427 |
704237 | |digital-logic|flipflop|state-machines|sequence-detector| | <p>There is a mistake in the FSM diagram for state <code>E</code>. Both transitions out of state <code>E</code> show the same input/output values, but they should be different.</p>
<p>Assuming the customary notation of <code>input/output</code>, both transitions show <code>0/0</code>. One of the transitions should show input=1, like <code>1/0</code>.</p>
<p>There is a similar mistake for state <code>B</code>. Both transitions out of the state show the same value: <code>1/0</code>.</p>
<blockquote>
<p>It has a total of 7 states (so I need 3 FFs right?)</p>
</blockquote>
<p>Yes, if you have 7 states, you can encode those states with 3 FFs.</p>
| <p>I was asked to design a Mealy FSM using SR Flip Flops to detect a pattern.
It should detect if the pattern is either '1001' or '0110'.</p>
<p>I was able to make the state diagram (I have attached the image), but I am confused about forming the state table and solving it with K- Map. It has a total of 7 states (so I need 3 FFs right?), and the inputs can either be 0 or 1, so that's a total of 5 variables then (please correct me if I am wrong).</p>
<p>So in that case, is this to be solved using a 5 variable K - Map?</p>
<p><a href="https://i.stack.imgur.com/cdzA3.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/cdzA3.jpg" alt="state diagram" /></a></p>
| Mealy FSM using SR Flip Flops: pattern detector | 2024-02-28T17:55:59.967 |
704250 | |ldo| | <p>Just want to update on what i've attempted. Might be one possible solution.</p>
<p>2.2uF aluminum capacitor: Same result. Significant output voltage drops down to the minimum 1.225 when under even very small loads.</p>
<p>2.2uF low ESR ceramic: voltage drops immediately with no load at all.</p>
<p>2.2uF low ESR ceramic + 5 Ohms series resistance: This seems to work best. Output remains constant with minimal drop throughout the full 0 - 500mA range. Noise is not great but less than 100mV p-p. Maybe the most important thing here is that the series resistance remains constant?</p>
<p>Correction: Noise is bad.. 500mV p-p. That could just be my circuit.</p>
<p>Another update today:
Turns out the input to my LDO was extremely noisy. Once I stabilized the input, the output became stable. It's also answered in a FAQ from the manufacturer that ceramic caps can be used with this LDO so it had nothing to do with that.</p>
| <p>I am troubleshooting a LDO that drops the output way down from 5V when put under very small loads. With a 100 Ohm load, it will typically drop below 4V, for example. Varies from board to board. In one extreme case, i've seen it drop all the way down to the minimum of 1.235V, almost as if R1 and R2 don't exist at all. This does not seem to remain consistent with the 0.4% load regulation in the datasheet.</p>
<p>VOUT = 1.235V x [1 + R1/R2] = 1.235V x [1 + 100/33] ~ 5V</p>
<p>From the datasheet of this LDO, it should be able to source 500mA. Dropout voltage also appears to be within the correct range. VIN is very stable. One hypothesis is that R1 and R2 are overheating but they don't seem to be getting very hot (100F).
</p>
<p>Based on the schematic alone, is this LDO being used correctly?</p>
<p>SPX3819S-L/TR
<a href="https://assets.maxlinear.com/web/documents/spx3819.pdf" rel="nofollow noreferrer">https://assets.maxlinear.com/web/documents/spx3819.pdf</a></p>
<p><img src="https://i.stack.imgur.com/PFCBJ.png" alt="schematic" /></p>
<p><sup><a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fPFCBJ.png">simulate this circuit</a> – Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a></sup></p>
| SPX3819 LDO output drops very low under small loads | 2024-02-28T20:14:29.073 |
704257 | |power-supply|pcb|integrated-circuit|identification| | <p>Single gate pin, large copper planes as heatsink connected to multiple pins...<br />
That looks like a mosfet or transistor.</p>
<p>Based on the similar wired part nearby they drive the transformer using a half-bridge.</p>
<p>One of them will be an N-channel and the other a P-channel. If you know more about the driving circuitry and the voltages and currents involved you could replace them. Assuming drive circuitry is still intact.</p>
| <p>I have a monitor that won't turn on. I opened it and found a burnt part on the board, but I can't identify that part. I want to know what this part is and what it does.</p>
<p><a href="https://i.stack.imgur.com/a1gNp.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/a1gNp.jpg" alt="enter image description here" /></a></p>
| Determining the type of defective part on the PCB | 2024-02-28T21:12:57.423 |
704262 | |led|light|phototransistor|photoresistor| | <p>You're right. That circuit does waste energy. The reason is you want your light sensor (CdS resistor?) to shunt current to your amplifying element (the transistor) NOT the load (the LED) as in your case. The idea is that the transistor amplifies the uA's of current as opposed to burning mA's of current - a savings of 1000x worth of battery juice! Try the following to get you going:</p>
<p><img src="https://i.stack.imgur.com/8SIfL.png" alt="schematic" /></p>
<p><sup><a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2f8SIfL.png">simulate this circuit</a> – Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a></sup></p>
<p>Q1 can be whatever single NPN transistor that you are already using, however, the Darlington should give you better performance due to high gain (less current needed, sharper transition). You might need lower value resistors in the single NPN case. Also, if the LED still stays "on" even dimly in bright conditions, and you don't like that, put a highish value resistor across the base and emitter of the transistor to control the gain and "force" the LED off in bright conditions.</p>
| <p>I am trying to design night light LED that brights up when it's dark. I know a solution using transistor that "drains" current so LED has not enough to light up.</p>
<p><a href="https://i.stack.imgur.com/dN7nZ.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/dN7nZ.png" alt="enter image description here" /></a></p>
<p>A current flow through transistor during day to "block" led. I can't get out of my head that waste of energy if the source is a small battery or super-capacitor.</p>
<hr />
<p>I wonder if there is a solution to make night light without unnecessary current drain. It would be disappointing if that needs complex stuff like IC, op-amp or comparator ...</p>
<p><strong>Is there a nice circuit using basic components that does not waste energy?</strong></p>
<p><em>Correct me if you see anything wrong, I am new to electronics.</em></p>
<p>Thank you.</p>
| How to bright up LED when it's dark without wasting battery energy? | 2024-02-28T21:45:00.753 |
704266 | |current|low-power|battery-operated|attiny|low-voltage| | <p>The internal pull-ups in an ATTiny/ATMega are usually in the range of 20-50 kΩ, which is quite low for a low-power application.</p>
<p>I would disable the internal pull-up resistor, and use an external pull-up resistor instead. You could easily go for something on the order of 1 MΩ or possibly larger. If you are concerned about noise, add a small capacitor in parallel with the reed switch for noise filtering. Only needs to be 100 pF or so. The capacitor will also provide some de-bouncing for the switch.</p>
<p>At 20 kΩ with a 3.3 V supply, by Ohm's law you will have a nominal 165 μA current through the resistor when the button is pressed (continuous for NC switch). For a 1 MΩ resistor that would drop to only 3.3 μA.</p>
<p>You could try as much as 10 MΩ, which would drop the current draw even further to 330 nA, though at some point leakage current into the ATtiny pin will start to dominate (actually datasheet lists this as 50 nA, so it could possibly go higher). You also trade off noise immunity with higher resistors.</p>
<hr />
<p>Alternatively, you could switch to a normally-open reed switch if that is possible. This way you are only drawing a current from the supply through the switch when pressed.</p>
| <p>I have an ATtiny412 that has 2 pins (PA1, PA2) set as internal input pullups.</p>
<p>These 2 pins (PA1, PA2) sense magnetic reed switches with the NC setting. GND is active when closed on these switches.</p>
<p>The other 4 pins are allocated as follows:</p>
<ul>
<li>PA6 goes to RF transmitter</li>
<li>PA7 controls EN on (WL102-341_TX_Module)</li>
<li>PA3 is set as output to avoid parasitic currents</li>
<li>PA0 UPDI is left alone</li>
</ul>
<p>The IC is working on a battery @ 1 MHz and 3.3 V.</p>
<p>On power-up the IC sets up interrupts and is set to <code>SLEEP_MODE_PWR_DOWN</code> and then goes into a sleep loop.</p>
<p><code>RTC_PIT_vect</code> is used for a long heartbeat loop.</p>
<p><code>PORTA_PORT_vect</code> is used to wake from a pin change pins (PA1, PA2) using <code>PORT_ISC_BOTHEDGES_gc</code>.</p>
<p>The sketch works well, however, I have been busy optimizing power consumption.</p>
<hr />
<p>From my measurements the IC by itself runs at 0.57 μA when in power-down mode (datasheet says 0.1 μA @ 25°C and 5.0 μA @ 85°C)</p>
<p>I'm OK with 0.57 μA since I used a multimeter and it's close enough.</p>
<p>My circuit draws around 264 μA when both pins (PA1, PA2) are grounded.</p>
<p>If I invert the pins I get 61 μA.</p>
<p>The regulator seems to have a quiescent current of around 54 - 60 μA but the datasheet does not specify.</p>
<p>I'm using the FS8860-33CH0003; it's what was available and the closest low-quiescent current and low-dropout I could get.</p>
<hr />
<p>So after noticing the huge decrease in current when I use inverted pins I integrated this into my project.</p>
<p>As far as I understand I can use an N-channel FET to have my NC reed switch trigger the MCU pin.</p>
<p>This works but adds an extra 33.2 μA per FET and a 100 kΩ pullup total changes to 127.4 μA in power down mode.</p>
<p>Still better than 264 μA, but I would like to get under at least something like 100 μA.</p>
<p>Are there any tricks or tips with a small component count to decrease the current even more? Maybe there is something I have not considered?</p>
<p>Maybe it's easier to just use a carefully selected resistor in series with the reed switch to limit current, or get a better FET or increase the FET pull-up resistor?</p>
<p>I will get a better regulator in the future but this question is regarding the low current consumption using the pins.</p>
<hr />
<p>In the picture:</p>
<ul>
<li>No. 1 inverted pins: is my simple FET switch witha 100 kΩ pull-up 127.4 μA in power down mode, saves 136.6 μA.</li>
<li>No. 2 non-inverted pins: is just a 10 kΩ resistor in series with the reed switch 182 μA in power down mode, saves 82 μA.</li>
</ul>
<p><a href="https://i.stack.imgur.com/CWA3z.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/CWA3z.png" alt="enter image description here" /></a></p>
| Low power consumption/leakage tips and tricks (input NC magnetic reed switches) | 2024-02-28T22:05:39.177 |
704270 | |pic|7segmentdisplay|pic16f|cd4017| | <p>This driving method is called "multiplexed driving". Only one display shows (displays) data at a time and switches to the next one. This repeats fast enough to give the impression that all of the displays are "on" at the same time.</p>
<hr />
<p>The segment data is common for all displays which appear to be common-cathode:</p>
<p><a href="https://i.stack.imgur.com/7eXKE.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/7eXKE.png" alt="enter image description here" /></a></p>
<p><a href="https://electrocredible.com/7-segment-display-with-raspberry-pi-pico/" rel="nofollow noreferrer"><em>Img Src</em></a></p>
<p>The segment data for each display is generated by the MCU and transferred to the displays using 74HCT4511 through 220R series (current limiting) resistors and then the respective display is selected whilst the rest are un-selected using ULN2003A.</p>
<p>ULN2003A can be thought of as a low-side switch: If you apply a positive voltage to, say, pin 1B then the pin 1C will connect to the ground. Likewise, if you apply to the pin 1B zero volts then 1C will become floating. For example, if you load the segment data and apply 3V to the 1B pin of the ULN2003A (also apply zero to the other inputs) then the data will be displayed on the 2nd digit of A2. Likewise, if you load another data to the segments and apply 3V to the 2B input then the data will be displayed on the 1st digit of A1.</p>
<p>The inputs (1B ... 4B) of the ULN2003A come from 4017 which is a counter, so every time a segment data is displayed on one display the next display is selected in the next <code>CLK</code> pulse. After the last display shows its data, the counter is reset to zero using the MR pin and the cycle starts afresh.</p>
| <p><a href="https://i.stack.imgur.com/nrx1u.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/nrx1u.png" alt="the electrical circuit" /></a></p>
<p>Can someone please help me understand the use of CD4017 AND ULN2003A with the 7-segment display?</p>
| A question about the use of 4017 and ULN2003A | 2024-02-28T22:51:27.140 |
704271 | |schematics|altium|footprint|library|bom| | <p>Try <code>CurrentFootprint</code>.</p>
<p>Yeah, it's silly how the names differ; there are, I think, three different naming schemes for the same object properties, in different contexts (what's actually labeled in the Properties dialog; the name in Query language; and the inline expression or "..." macro function; and some differ between SCH and PCB, like "Part" vs. "Component", etc.). Unfortunate, but historical baggage that can't be gotten rid of, just worked around, understood and accepted.</p>
<p><a href="https://i.stack.imgur.com/C6xTg.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/C6xTg.png" alt="enter image description here" /></a></p>
<p>In the spirit of "multiple ways to do something", besides copying it manually, you can also set it in List view (SCH or PCB), or Parameter Manager; or copy the data from these spreadsheet views into a spreadsheet program and perform more intricate manipulations on them, before pasting it all back in.</p>
<p>Do check that other modes/views show the data correctly, whatever it is you're ultimately outputting: PCB text labels (component parameters), BOM output columns, etc. (Footprint is an available BOM output column anyway, so this seems a bit redundant, but it should work fine either way.)</p>
| <p>I am creating a component in such a way that in the schematic file it would be possible to change the footprint, and the component parameter "Package" will be updated.
I tried to put "=Footprint" , but it didn't work.
Someone knows who to do it?
Thanks in advance</p>
<p><a href="https://i.stack.imgur.com/Mnm9q.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/Mnm9q.png" alt="enter image description here" /></a></p>
| How could I get the footprint name in Altium? | 2024-02-28T22:54:34.543 |
704272 | |transistors|switches|esp32| | <p>For pulling 3V3 to gnd you don’t need and extra transistor, just pull with mcu pin. If you want to use an external transistor anyway use this:</p>
<p><a href="https://i.stack.imgur.com/2X18a.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/2X18a.png" alt="enter image description here" /></a></p>
<p>For switching 12V use this circuit:</p>
<p><a href="https://i.stack.imgur.com/6x4Z2.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/6x4Z2.jpg" alt="enter image description here" /></a></p>
| <p>I do have a control panel in our camper van. It has four push buttons to turn on and off certain functions. I now want to add an ESP32 to make this panel smart and allow me to remotely control the switches (...well, more the functions attached to it).</p>
<p>Three of them are pretty easy:</p>
<p>It looks like the output of the switch is pulled-up to 3.3V. When you push the switch, it will pull to ground (they also use some kind of Microcontroller). The current when the switch is closed is somewhere in the uA range.</p>
<p>"All" I need to do is pulling the switch output to ground using my Microcontroller. I think it would be a bad idea to connect "my" Microcontroller directly.</p>
<p>So I guess I need a transistor in between. The output pin of "my" Microcontroller goes to the Base of the transistor and the emitter and collector are used to "close the circuit" for the switch to ground.</p>
<p>I know the some basics of transistors, but I'm struggling here. What transistor should I choose (NPN or PNP) and what resistors do I need?</p>
<p>The main switch - also a push button - is a bit more complicated. It's switching the "output" of the push button to 12V. So instead of pulling to ground like above, I would need to switch it the 12V+ using a transistor.</p>
<p>Thanks for your help....</p>
| Make mechanical switch panel smart (or how to electronically push buttons) | 2024-02-28T23:07:10.043 |
704290 | |digital-logic| | <ol>
<li><p><span class="math-container">\$\overline{A}+A+1=2^N\$</span>, where <span class="math-container">\$N\$</span> is the bits in the unsigned word. So:</p>
<p><span class="math-container">\$\overline{A}+1=2^N-A\$</span></p>
</li>
<li><p>Suppose <span class="math-container">\$A \gt B\$</span>. Then <span class="math-container">\$-A\lt-B\$</span>. Then:</p>
<p><span class="math-container">\$2^N-A\lt 2^N-B\$</span></p>
</li>
<li><p>Substituting #1 above into #2, then <span class="math-container">\$\overline{A}+1\lt 2^N-B\$</span>. Therefore:</p>
<p><span class="math-container">\$B+\overline{A}+1\lt 2^N\$</span></p>
</li>
<li><p>Since the sum in #3 is less than <span class="math-container">\$2^N\$</span> it follows there's no carry-out.</p>
</li>
<li><p>But <span class="math-container">\$B+\overline{A}+1=B-A\$</span>. In short, subtracting <span class="math-container">\$A\$</span> from <span class="math-container">\$B\$</span> to make the comparison.</p>
</li>
</ol>
<p>So I've proven that there is no carry-out when performing <span class="math-container">\$B-A\$</span> when <span class="math-container">\$A\gt B\$</span>.</p>
<p>Therefore, a carry-out of 0 means <span class="math-container">\$A\gt B\$</span> and a carry-out of 1 means <span class="math-container">\$A\le B\$</span>.</p>
| <p>My textbook (Harris and Harris <em>Digital Design and Computer Architecture</em>) give the following arrangements for facilitating the comparison of two <span class="math-container">\$N\$</span>-bit unsigned numbers:</p>
<p><a href="https://i.stack.imgur.com/eivi6.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/eivi6.png" alt="enter image description here" /></a></p>
<p>Given that I am self-studying I am a bit concerned with not fully understanding this. Each subtractor computes <span class="math-container">\$B-A\$</span>. Now <span class="math-container">\$A>B \iff B-A<0\$</span>. For two unsigned numbers it's not clear to me why the difference between them should give a 1 on the MSB (as per the picture) if and only if the difference is negative. This would seem to be the case for signed numbers, but why too in the unsigned case?</p>
| How does one do inequality comparison of unsigned numbers with a subtractor? | 2024-02-29T01:44:02.307 |
704296 | |switches| | <p>If you already have the DPDT switch in place, there is no value in changing it to SPST. Electrically, your circuits are equivalent. With no further context, that is your answer. To supplement:</p>
<ul>
<li>You can double the current capacity with the DPDT (or even DPST, in you case): the switch current rating is per pole. So if you have a DPDT/DPST switch rated 5A, wired the way you have it, your nominal capacity is now 10A.</li>
<li>Even if you have enough capacity with using one pole alone, put the other pole in parallel with the first pole anyway. This will extend switch life as the current (and arcing) gets split across both poles not just one. This is much more valuable if you are switching a sparky load like a motor or transformer.</li>
<li>The two pole switches a commonly used to break both phases of 230VAC systems. They are required for safety and compliance. Hopefully, this is not related to your application cause you aren't experienced to be working in that capacity and will likely cause harm.</li>
</ul>
| <p>In the circuit shecmatic, the switch is an DPST switch, the input pins are in parallel.</p>
<p>I look for the advantages of DPST, it is mainly used on independant circuits. If the input is not independant, should I replace it with a SPST switch or a simple metal dome?</p>
<p><a href="https://i.stack.imgur.com/0gBKj.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/0gBKj.png" alt="enter image description here" /></a></p>
| Do I need to use DPST for two loads? | 2024-02-29T04:49:10.003 |
704307 | |verilog|simulation|system-verilog|hdl|fixed-point| | <p>The post has this line</p>
<pre><code>logic [2*N-1:0] res = ({{N{a[N-1]}},a} * {{N{b[N-1]}},b}) >> P
</code></pre>
<p>That will initialize a signal but not behave as a continuously assigned multiply . This may not work in some synthesis tools even to initialize. I recommend not having the expectation to to declare and initialize or to declare-initialize-drive on the same line in Verilog/SV.</p>
<p>Cleaning up the multiply, and realizing the total is 128 bits internally then shifting to retain as many fractional bits as you want. Shifting zero retains all fractional bits.</p>
<pre><code>module fix_point_mul #(parameter N = 64, parameter P = 0)(
input logic signed [N - 1 : 0] a, b,
output logic signed [2*N - 1 : 0] c_out
);
// N bits * N bits is 2N bits
logic signed [(2 * N) - 1 : 0] c;
// Full precision multiply
assign c = a * b ;
// Shift and throw away some of the fractional bits because we don't
// care about full precision.
assign c_out = c >> P;
endmodule
</code></pre>
<p>For the testbench, if you want to shift the real number 14.26 twenty bits to the left multiply the real by <code>2**20</code>, then cast to an integer like this: <code>int_val = int'(14.26 * (2 ** 20))</code>. Its not possible to drive a bit-vector bus in verilog from a real variable. Using type'(value) to change value to the type is called static casting in SystemVerilog.</p>
<p>To retain only the integer bits to the left of the decimal, shift by 40 bits (20 fractional bits * 20 fractional bits), here I kept 39 (one decimal place).</p>
<pre><code>module fix_point_tb #(parameter N = 64);
logic signed [N - 1 : 0] a, b;
logic signed [(2 * N) - 1 : 0] c;
real c_scale_real;
fix_point_mul
// shift 39 bits to retain 1 fractional bit of fixed point number
#(.P(39))
mul_uut (.a(a), .b(b), .c_out(c));
// shifting by 2^1 to print the bit vector as a one decimal place real
// See note at the bottom
assign c_scale_real = real'(c)/2;
initial begin
a = 14.26 * 2**20;
b = 52.732 * 2**20;
#1;
$display("c = %0h,c_scale float one decimal place= %0f",c,c_scale_real);
$finish;
end
endmodule
</code></pre>
<p>Produces</p>
<pre><code>c = 5df,c_scale float one decimal place = 751.500000
</code></pre>
<p>A floating point calculator says 14.26*52.723 = 751.82998 so we are getting close. You can add more fractional bits to approach the float value. We are throwing away bits when casting the stimulus from real->int, so for many numbers the multiply will not perfectly agree with the real number even for full precision fixed point.</p>
<p>If you want to print anything in Verilog/SV with a decimal, you will need to change the bits to float. As an example if you have two bits 2'b11 Verilog will always print the bit vector as 3; to view it as one fractional bit (1.5) convert it to a float by dividing by the 2^number of fractional bits you want to represent, in this case: 2^1 = 2. If you have the two bit vector 2'b11 and want to consider it two fractional bits, divide the integer value by 2^2 to get the fixed point value. So we have 3/2^2 = 3/4 = .75</p>
| <p>I am implementing a fixed point multiplication circuit in SystemVerilog to multiply 2 64-bit numbers, each has 20 bits of decimal part (which remains 44 bits of integer part). The problem is the <code>res</code> signal is full of <code>X</code>, which causes the <code>out</code> also full of <code>X</code>.</p>
<pre><code>module fix_point_mul #(parameter N = 64, parameter P = 20)(
input logic signed [N-1:0] a, b,
output logic signed [N-1:0] out
);
logic [2*N-1:0] res = ({{N{a[N-1]}},a} * {{N{b[N-1]}},b}) >> P;
assign out = res[N-1:0];
endmodule
</code></pre>
<p>This is my testbench:</p>
<pre><code>module fix_point_tb #(parameter N = 64, parameter P = 20);
logic [N-1:0] a, b;
logic [N-1:0] out_mul;
logic carry;
fix_point_mul mul_uut (.a(a), .b(b), .out(out_mul));
initial begin
a = 14.26 << 20;
b = 52.732 << 20;
end
endmodule
</code></pre>
<p>What are the problems? And what is the proper way of doing it?</p>
| Fixed point multiplication circuit in HDL doesn't work as expected | 2024-02-29T06:53:50.607 |
704313 | |reverse-polarity|power-filtering| | <p>The most trivial reverse voltage protection implementations using a MOSFET requires just one MOSFET and nothing else, replacing the diode altogether:</p>
<p><img src="https://i.stack.imgur.com/utIm7.png" alt="schematic" /></p>
<p><sup><a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2futIm7.png">simulate this circuit</a> – Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a></sup></p>
<p>The body diode won't conduct the wrong way, so I disagree with Mr. R here. This is <span class="math-container">\$V_{OUT}\$</span> in response to a sweep of source voltage going from -20V to +20V:</p>
<p><a href="https://i.stack.imgur.com/TGXQA.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/TGXQA.png" alt="enter image description here" /></a></p>
<p>Considering that your only other concern is power dissipated in the block/pass element, this solution wins hands-down. The right MOSFET could dissipate less than 100mW with a 2A load current. Jelly-bean IRF9xxx models would dissipate well under 1W.</p>
<p>A slightly better solution would protect the gate from horrible spikes on the supply:</p>
<p><img src="https://i.stack.imgur.com/UsMtp.png" alt="schematic" /></p>
<p><sup><a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fUsMtp.png">simulate this circuit</a></sup></p>
<p>I agree with Mr. R regarding capacitor placement, but supply decoupling closer to the downstream electronics is of far greater importance, and will naturally have to come after the transistor.</p>
| <p>I am reviewing the power stage of a board which is to be connected to a wide range of cars and motorbikes, with internal combustion engines, old, new, 2 stroke, 4 stroke, etc.<br>
Current schematic looks like this:</p>
<p><img src="https://i.stack.imgur.com/SGDBb.png" alt="schematic" /></p>
<p><sup><a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fSGDBb.png">simulate this circuit</a> – Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a></sup></p>
<p>D1 serves as reverse polarity protection, D2 is a TVS, and F1 limits overcurrent if the board breaks and gets shorted.
Power consumption is low, peak current is around 1.1 A, and considering D1 voltage drop of about 0.5 V, power losses due to D1 are in the range of 0.6 W.
(Note: the input capacitors for the SMPS are not shown)<br></p>
<p>Power consumption of the next revision is set to increase, with peak current of about 2 A, bringing losses up to 1 W, and heat to match: my suggestion is to swap D1 with a P-MOS, to make use of a more efficient reverse polarity protection method.</p>
<p>Mr. R (as in Retired electronics designer) made the following observation: placement of D1 is wrong, it should be placed before the caps, because right now the caps are just parallel with the whole vehicle; we should move the caps after D1 so they will serve as current tanks for our board only.
We should forgo the P-MOS solution because it would conduct both ways and not solve this problem.
<br><br></p>
<p>Assuming we can draw infinite energy from the vehicle, what should I take into account when choosing a solution over the other?</p>
| How to choose reverse polarity protection - diode vs MOSFET | 2024-02-29T09:18:24.687 |
704320 | |resistors|parallel|series| | <blockquote>
<p><em>Why are the two resistors in parallel? They are next to each other, so
they should be in series, right?</em></p>
</blockquote>
<p>Strictly speaking they are neither in series nor in parallel because of the R3 connection.</p>
| <p>Why are the two resistors in parallel? They are next to each other, so they should be in series, right?</p>
<p><a href="https://i.stack.imgur.com/CKajh.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/CKajh.jpg" alt="enter image description here" /></a></p>
| Why are the two resistors in parallel? They are next to each other, so they should be in series, right? | 2024-02-29T10:50:49.417 |
704327 | |power|buck|atmega|boost|converter| | <p>The parts are unknown so we don't know if they will work.</p>
<p>However, you have drawn D2 as a Zener which makes no sense.</p>
<p>There are no input capacitors either.</p>
<p>PG is shorted to output so there will be damage to the IC.</p>
<p>Output has no caps and they are shorted instead.</p>
<p>FB capacitor is not present.</p>
| <p><a href="https://i.stack.imgur.com/yuFvz.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/yuFvz.png" alt="enter image description here" /></a></p>
<p>My Power System, can someone validate it? I'm not familiar with using the TPS63060.</p>
<p>Datasheet can be found at: <a href="https://www.ti.com/product/TPS63060" rel="nofollow noreferrer">https://www.ti.com/product/TPS63060</a></p>
<p>I'm trying to power a ATMega328p-AU + 4 digit 7-segment display. I'm not trying to do something overcomplicated, just run the circuit for a reasonable amount of time, at a good efficiency which is why I opted out of using a Linear Voltage Regulator.</p>
<p>It is to run a clock, a very simple gift I'm trying to design. My goal is to create a 3V3 output from the below circuit. The TPS63060 is a high input voltage buck-boost.</p>
<p>Input:
The power source is 4 x AAA cells in series at 1.5 V each, totaling at 6 V.</p>
<p>PS: I'm a absolute beginner at electronics so any recommendations/ knowledge would help a lot. Thank you to everyone who takes the time to help me and point me in the right direction.</p>
<p><strong>Edit and New</strong>: Thank you to everyone for the candid feedback, I needed it. I apologise for the rampant errors, I have no answer for it, here's the new schematic I'd love to know your thoughts on, please let me know if any mistakes persist.</p>
<p><a href="https://i.stack.imgur.com/dctpf.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/dctpf.png" alt="enter image description here" /></a>
New Schematic</p>
| Validate my 3V3 power system | 2024-02-29T13:05:19.650 |
704332 | |can|rs485|msp430| | <p>Some <a href="https://www.digikey.com/en/products/filter/microcontrollers/685?s=N4IgjCBcpgnAHLKoDGUBmBDANgZwKYA0IA9lANogAMIAugL73EBMFIAsgMoAKALAMw1iAGQCSAOQBGAV1x1iANmQgAlgBMoIALRgqEYgAcALppDEAjkYCem3WZDWD%2BTZlxpGQA" rel="nofollow noreferrer">MSP430s have LINbus</a>, which is a master-slave protocol targeted to vehicles. The LINbus, or <a href="https://en.wikipedia.org/wiki/Local_Interconnect_Network#Overview" rel="nofollow noreferrer">Local Interconnect Network</a>, is a less expensive network designed to work with CAN. It has a speed of about 19.2Kb/s and has 1 master and up to 16 slaves (requiring no bus arbitration), and is designed to work on top of a CAN backbone network, according to the Wikipedia article. I know that you need 20 slaves, and I don't know how one MSP430 can host two LINbus networks, but that's what I would try, though I have no experience with such.</p>
| <p>I am planning on building a system with one master and multiple slaves using MSP430 microcontrollers. The microcontrollers must talk with each other with serial interface using RS-485. I now need to decide how the messaging should be implemented.
The microcontrollers are several meters apart and there must be a possibility for atleast 20 slaves. The slaves need to be able to send messages back to the master.</p>
<p>The current implementation is made using a single UART. Slaves can only send messages after they have received a message from the master. The system has an additional non standard polling signal (on/off) which tells other devices that the line is busy. This is non-standard and an awful way, but without it the system can't know if it is safe to send messages.</p>
<p>I am new to this area and i dont really know about the options?
I have read about DMX512, but it can only send messages from the master.
There are things like MODBUS, LIN, SMBUS, I2C etc. which can message to multiple devices, but are they what I am looking for?</p>
<p>Is the best solution to use CAN bus using MC2515 microchip?
Or should I use two UARTS in one RJ45 cable where one is from master to slaves and another one is from slaves to master so I could pass a token between the slaves?</p>
<p>In general what kind of protocol should I be looking into?
I would like the system to be as flexible as possible.</p>
| What technology to use with multiple embedded systems talking to each other? | 2024-02-29T14:16:29.317 |
704344 | |safety|circuit-protection|inductance|spark|iec| | <blockquote>
<p>When assessing intrinsic safety, it is my understanding that CMC is to be included in the assessment. Is that correct?</p>
</blockquote>
<p>This depends on whether it's part of the intrinsic safety part. I don't see a connector in your diagram. I have the impression that the whole diagram is in the Ex zone? If so, yes, the common mode choke must be evaluated at least for auto-ignition energy. For example, for group IIC, the current in a 750µH choke must not exceed 280mA (see Figure A.4 for group II - EN 60079-11).</p>
<blockquote>
<p>Then what would be the voltage applied during the assessment? Is it V1max or Vz?</p>
</blockquote>
<p>From my point of view, since V1 is an infallible transformer, the only fault to be considered is an open circuit (because that's its failure mode), so only V1max is to be considered for evaluation.</p>
<p>The voltage Vz will be used to evaluate Cout's auto-ignition energy (see Figure A.3 for Group II - EN 60079-11).</p>
| <p>My IS circuit contains an inductance, capacitance, and resistance. Shown below is the simplified schematic, with uncountable and countable fault applied, resulting in the most onerous condition:</p>
<p><a href="https://i.stack.imgur.com/Wx2Bt.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/Wx2Bt.png" alt="enter image description here" /></a></p>
<p>The inductance is from a common mode choke, with the tolerance added. V1 is from an isolating, infallible transformer (non-mains), Rcharge is the ESR.</p>
<p>Since V1 could go to dangerous levels of voltage, a zener barrier + fuse is employed. This will limit the voltage to a safe level.</p>
<p>As you can see, the CMC is located between the isolation transformer and the IS region.</p>
<ol>
<li>When assessing intrinsic safety, it is my understanding that CMC is to be included in the assessment. Is that correct?</li>
<li>Then what would be the voltage applied during the assessment? Is it V1max or Vz? V1max - since at fault condition, the CMC would experience the V1max voltage. Or will it be Vz since Vz will be the voltage seen in the EX connection facility (across Cx).</li>
</ol>
<p>Thanks.</p>
| Intrinsic safety (IEC60079-11) - assessing spark ignition of RLC circuit, but the L is placed before the zener barrier | 2024-02-29T15:33:56.583 |
704354 | |gpio| | <p>Your link to the cable has a drawing that identifies the connector:</p>
<p><a href="https://i.stack.imgur.com/Rp6W9.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/Rp6W9.png" alt="enter image description here" /></a></p>
<p>It is a "1.25T-1-5Y" or "11251h00-5P"</p>
<p>The correct terminals are also listed.</p>
<p>You could easily re-create this cable yourself very cheaply.</p>
| <p>I have a <a href="https://www.elotouch.co.uk/accessories-backpack-4.html" rel="nofollow noreferrer">Elo Backpack 4</a> and I want to make use of the GPIO port to open a cash drawer via RJ11.</p>
<p>There is information regarding the GPIO in the <a href="https://docs.elotouch.com/UM600694.pdf" rel="nofollow noreferrer">Backpack user guide</a>. It mentions that <a href="https://myelo.elotouch.com/support/s/article/E211544-GPIO-Cable-Information" rel="nofollow noreferrer">this cable</a> can be used, but I'm finding it hard to source for a reasonable price.</p>
<p>My question is, is the port using a standard plug that I can source more easily? I was wondering if it was some sort of JST but I'm not convinced regarding the dimensions. If so, would it be feasible to create my own cable?</p>
| What port is this, and can I create a cable for it? | 2024-02-29T16:51:12.633 |
704356 | |mosfet|high-side|safe-operating-area| | <p>I think you're calling it too close on the MOSFET rating. For an actual current of 8A continuous I would be starting with a datasheet "big print" continuous current rating in excess of 60A (often they are misleading anyway, because they exclude package limitations).</p>
<p>Then sort by P-channel, voltage (keep it as low as safe), stock, price and package. That should yield a flood of possible parts. For example the ~5mm x 5mm <a href="https://goodarksemi.com/docs/datasheets/mosfets/SSFD3906.pdf" rel="nofollow noreferrer">GSFP03101</a> from "Good Ark" has a maximum Rds(on) of 3.3mΩ at 25°C so perhaps 5mΩ maximum even when hot, which would drop 40mV, well within the SOA of the transistor. It's also not too expensive. And dissipating about 0.33W worst-case you won't need much copper area to keep Tj reasonable under sensible Ta conditions.</p>
<p><a href="https://i.stack.imgur.com/H2LHs.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/H2LHs.png" alt="![enter image description here" /></a></p>
<p>Note that if your load is an incandescent bulb you might have to worry about the safe operating area during turn-on. Fortunately your driver circuit drives the MOSFET 'on' hard but turn-off is much softer (when the resistance of the load would be higher).</p>
| <p>I am designing a circuit where a logic level signal switches an NPN BJT (Q1A) which turns a P-channel MOSFET (Q2) on as a high-side configuration to power a load (<code>LOAD_100W</code>) of up to 100W at 12V.</p>
<p>My problem is finding a correct SMT MOSFET which will handle the situation without overheating (and preferably without a sink, just by a larger 2oz copper layer where it's sitting on).</p>
<p><a href="https://i.stack.imgur.com/BXMi6.png" rel="noreferrer"><img src="https://i.stack.imgur.com/BXMi6.png" alt="MOSFET High-Side Circuit" /></a></p>
<p>The load is e.g. a light bulb with 100W, operating at 12V.</p>
<p>With a current of <code>I = 8A</code> and a MOSFET <code>SQD50P04-13L</code> with an <code>Rds_on = 13mOhm</code>, we calculate a <code>Vds = 104mV</code> and the power dissipation of <code>Pdis = 104mV * 8A = 832mW</code>.</p>
<p>What I am confused about is the <code>safe operating area</code> plot in the <a href="https://www.vishay.com/docs/65157/sqd50p04-13l.pdf" rel="noreferrer">data sheet of the <code>SQ50P04-13L</code></a>. I marked a red dot where I think the MOSFET is operating (<code>I = 8A</code> and <code>Vds = 104mV</code>:</p>
<p><a href="https://i.stack.imgur.com/zEHic.png" rel="noreferrer"><img src="https://i.stack.imgur.com/zEHic.png" alt="Safe operating area of SQ50P04-13L, showing the value at I=8A and Vds=100mV" /></a></p>
<p>The red dot is <strong>not</strong> in the safe operating which is in that are "limited by Rds(on)".</p>
<p>My question now is: does this mean that the MOSFET will not operate at all, or will it overheat?</p>
<p>I have difficulties to find out if the package can dissipate almost 1W. According to the table on page 1, the <code>Junction-to Ambient</code> temperature is 50 °C/W, so if I understood correctly, this is actual temperature increase.</p>
<p>What's even more confusing is that if I search for MOSFETs with lower <code>Rds</code> to limit the temperature increase, I always hit the limit of the left edge of the "safe operating are" plot above the Rds limit.</p>
<p>Another question: the same circuit should also be able to switch low-power loads as well (1W or less). Is that even possible? Those are not even fitting in the "safe operating area" plot.</p>
<p>Say e.g. <code>I = 0.1A</code>, can I assume that <code>Rds = 13mOhm</code>? In the datasheet the lowest current I see in the plots is about 5A. which gives a <code>Vds = 1.3mV</code>. It's far left outside of the safe operating area but it makes intuitively little sense that such a "power MOSFET" cannot handle (whatever that means) <code>0.1A</code> at <code>12V</code>, isn't it?</p>
<p><a href="https://i.stack.imgur.com/WqU3F.png" rel="noreferrer"><img src="https://i.stack.imgur.com/WqU3F.png" alt="Drain current and Rds" /></a></p>
<p>Either I don't understand something or I need to search harder ;)</p>
| Understanding the safe operating area for low values of Vds | 2024-02-29T16:58:19.690 |
704369 | |batteries| | <p>Certainly capacity is affected by the load. At one extreme (almost zero load) there is no capacity since it's all eaten up by self-discharge.</p>
<p>At the other extreme (very heavy load) there is also no capacity since the battery cannot deliver 2.0V into the load due to the internal resistance.</p>
<p>The internal electrochemical processes inside the battery have losses that generally increase as the load current increases, on top of the internal resistance. Things like electrode polarization, for example.</p>
| <p><a href="https://i.stack.imgur.com/VfNWd.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/VfNWd.png" alt="enter image description here" /></a></p>
<p>The source is</p>
<p><a href="https://industrial.panasonic.com/cdbs/www-data/pdf2/AAA4000/AAA4000C321.pdf" rel="nofollow noreferrer">https://industrial.panasonic.com/cdbs/www-data/pdf2/AAA4000/AAA4000C321.pdf</a></p>
<p>I have seen a specification of the following</p>
<p><strong>CR2032</strong>: Lithium Batteries</p>
<p><strong>Product</strong>: Lithium Batteries</p>
<p><strong>Series/Type</strong>: Coin type lithium batteries (CR series)</p>
<p><strong>Parts no</strong>: CR2032</p>
<p><strong>Manufacturer</strong>: Panasonic</p>
<p>It shows that the capacity of the battery is a function of a load resistance. To me, a battery capacity can be affected by temperature, pressure, humidity and other factors, but I cannot see why the resistance can affect its capacity.</p>
<p>I am aware that the capacity will be decreased if it is discharged, but the data sheet does not state the time so I assume
<strong><span class="math-container">\$t = 0\$</span></strong> s</p>
<p>If <span class="math-container">\$Q = 225\$</span> mAh</p>
<p><span class="math-container">\$i = 1\$</span> mA</p>
<p>time will be <span class="math-container">\$t = 225\$</span> h.</p>
<p>If <span class="math-container">\$Q = 225\$</span> mAh</p>
<p><span class="math-container">\$i = 5\$</span> mA</p>
<p>time will be <span class="math-container">\$t = 45\$</span> h.</p>
<p>So time will change not the charge. This is how I see it</p>
<p>**</p>
<h2>The battery capacity is a design in characteristic.</h2>
<p>**</p>
| Does a battery capacity depend on the load? | 2024-02-29T18:56:39.393 |
704374 | |transformer| | <p>It certainly was for powering tube circuitry, given the filament and presumably B+ secondary windings.</p>
<p>Given the input frequency range, it probably was also for powering something with a high likelihood of being in an airplane.</p>
<p>The 50 Hz suggests it was designed for markets inside and outside the US and could have been used at normal line voltages on the ground, but the input frequency range of 1000 Hz would cover 400 Hz used in aviation electronics.</p>
<p>I worked on "reissuing" mag-amp based voltage regulators for nuclear plant diesel backups a few years ago and the form factor and mechanical design of this transformer are very similar to the '60s military and utility designs we were reproducing.</p>
| <p>I found the manufacturer, but their catalogue's don't have this item. Triad-Utrad, a subsidiary of Litton.
<a href="http://bitsavers.trailing-edge.com/components/triad-utrad/Triad-Utrad_Catalog_1979-80.pdf" rel="nofollow noreferrer">http://bitsavers.trailing-edge.com/components/triad-utrad/Triad-Utrad_Catalog_1979-80.pdf</a>
It's from 1964 and some sort of transformer? More details would be appreciated. I am fascinated by old electronics and am trying to understand the use. It weighs in at 12.7 lbs or 5.76 kg.</p>
<p><a href="https://i.stack.imgur.com/WfX7c.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/WfX7c.jpg" alt="enter image description here" /></a></p>
<p><a href="https://i.stack.imgur.com/HQvLl.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/HQvLl.jpg" alt=" " /></a></p>
| What is this transformer and what is it used for? | 2024-02-29T19:21:32.820 |
704381 | |pcb|voltage-regulator|switch-mode-power-supply|buck|debugging| | <p>Others have already addressed the cause of the smoke.</p>
<p>My concern is that even if you make this work, you will be disappointed with the noise performance. I would use a different part with lower peak current because it will be better for noise, but what follows assume you stick with this one.</p>
<p>You should <em>never</em> place the inductor on the other side of the board unless you have a lot of experience with this sort of thing and understand the tradeoffs involved. The single noisiest part of a DC/DC is the SW node (this is all the copper that connects, in your case, pin 2 to the inductor). A close second is the VIN node which is essentially part of this same circuit when the high side FET is turned on. <em>EDIT: I realise now that the inductor was not on the other side of the board - but the real issue is tunneling SW node through vias, so the comment stands.</em></p>
<p>You want low inductance on the VIN side; you already have a big cap and so adding a bit more capacitance by using lots of copper to connect the cap to VIN/GND pins is OK, so long as it reduces the inductance.</p>
<p>You want low capacitance on the SW side; otherwise you create a C-L-C like structure with the FET in the middle and whenever the FET switches on you'll get current washing back and forth through the parasitic inductance of the copper, leads, package, etc. So as a rule, use the minimum copper to connect SW to the inductor (minimum being something that will comfortably carry the peak current, in this case 3-4A I think).</p>
<p>The best way to minimise all the noise that these two bits of copper create is to move the inductor as close to the package as possible and then place the VIN cap as close as possible without compromising the inductor.</p>
<p>Don't forget that the copper carrying the positive half of the signal needs to be mirrored by copper on the GND side to carry the other half.</p>
<p>This package seems to have ignored this issue, but it's still possible to do something not too awful (it's never going to be "good").</p>
<p>This is a 2 layer with solid GND on L2 (not shown). The inductor is 12.7x12.7mm - that should be big enough to get a shielded 470uH inductor with adequate saturation current for your typical use case and beyond - you would need to test short circuit performance to make sure the DC:DC survives.</p>
<p>The GND return current for VIN is sub-optimal, but that's the compromise.</p>
<p><a href="https://i.stack.imgur.com/MExfZ.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/MExfZ.png" alt="Layout using 0805 VIN cap" /></a></p>
<p>The other option is to switch to something like a 1210 VIN cap. You may or may not get better results with this - very hard to say. If you do a new PCB, you could happily include both options and see which one works best.</p>
<p><a href="https://i.stack.imgur.com/4x6ut.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/4x6ut.png" alt="1210 VIN cap with SW routed through the gap" /></a></p>
<p>I am assuming a solid GND under all these designs. You could flood GND on L1 but I wouldn't, at least not to start with.</p>
<p>I deliberately keep the FB filter over on the far side of the chip away from noisy SW/VIN nodes.</p>
<p>Given the relative size of inductor to everything else, placement of VOUT cap(s) isn't going to do much - for a smaller inductor I would try to place them parallel to the inductor to minimise the size of the VIN-VOUT loop (the ripple current flows in this loop) - but we're beyond that here :-)</p>
<p>Also I am deliberately not using thermal relief on the SMD pads - this assumes you will always oven solder, where it doesn't matter so much for this size of component. I've only got copper pours where I think it will help matters.</p>
<p>Try to keep the inductor physically as far away from the noise sensitive circuit as possible - even a shielded inductor will produce an alternating magnetic field above the PCB (and below if you don't have solid copper underneath it - typically GND).</p>
<p>Finally, your LDO isn't going to do much, if anything, with the VOUT ripple current. As you only need 200mA approx I suspect you can design an RLC filter that will carry 200mA DC comfortably and provide plenty of attenuation at 500kHz. Probably be a couple of 0805/1206 parts (one L with non-zero DCR forming the RL and one C). Tiny compared to the enormous inductor :-)</p>
| <p>I'm in the process of debugging a PCB I made. On this board, a 24V input feeds through a DC/DC buck circuit (based around the TI TPS54202DDC) to output 11V, then an LDO to output 9V (to ensure a very stable 9V, I didn't want to convert directly to it).</p>
<p>When I plugged in the power supply, the TPS54202DDC popped immediately. I've provided my component selection logic below, have I made any mistakes there? I'll also include a picture of the layout on the PCB, though I'm relatively confident in it.</p>
<p>First, the datasheet for the converter - I'll include some screenshots below explaining my logic that contains excerpts: <a href="https://www.ti.com/lit/ds/symlink/tps54202.pdf" rel="noreferrer">https://www.ti.com/lit/ds/symlink/tps54202.pdf</a></p>
<p>Basic specs:</p>
<ul>
<li>Input Voltage: 24V (may not be rock solid, but I'll use a V_in(max) of 25V)</li>
<li>Output Voltage: ~11V (Just need adequate voltage that an LDO to 9V has plenty of headroom, but isn't burning too much voltage as heat)</li>
<li>Output Current: ~100mA, I'll spec for ~150mA to be safe.</li>
</ul>
<p>The datasheet suggests that all of these are well within the range for the selected converter. F_sw comes from the datasheet at ~500kHz.</p>
<p><a href="https://i.stack.imgur.com/9m0gX.png" rel="noreferrer"><img src="https://i.stack.imgur.com/9m0gX.png" alt="Buck Schematic" /></a></p>
<p><strong>8.2.3.1 Input Capacitor Selection</strong></p>
<p><span class="math-container">$$
\Delta V_{\rm in} = \frac
{0.25 \cdot I_{\rm out(max)}}
{C_{\rm bulk}\cdot f_{\rm sw}}
+ \left(
I_{\rm out(max)} \cdot {\rm ESR}_{\rm max}
\right)
\tag{4}
$$</span></p>
<p>I chose a <a href="https://www.lcsc.com/product-detail/Multilayer-Ceramic-Capacitors-MLCC-SMD-SMT_Murata-Electronics-GRM21BR61H106KE43L_C440198.html" rel="noreferrer">ceramic 10μF 50V capacitor</a>, and a parallel <a href="https://www.lcsc.com/product-detail/Multilayer-Ceramic-Capacitors-MLCC-SMD-SMT_Samsung-Electro-Mechanics-CL05B104KB54PNC_C307331.html" rel="noreferrer">0.1μF capacitor </a> as recommended by the datasheet. The ESR on ceramics should be basically negligible, so I calculate a <span class="math-container">\$\Delta V_{\rm in} = 7.5{\rm\,mV}\$</span>, which ought to be plenty small.</p>
<p><strong>8.2.3.2 Bootstrap Capacitor Selection</strong></p>
<p>The datasheet just says <a href="https://www.lcsc.com/product-detail/Multilayer-Ceramic-Capacitors-MLCC-SMD-SMT_Samsung-Electro-Mechanics-CL05B104KB54PNC_C307331.html" rel="noreferrer">0.1μF</a>, very straightforward. To be safe I kept it 50V tolerant.</p>
<p><strong>8.2.3.3 Output Voltage Set Point</strong></p>
<p><span class="math-container">$$
R_3 = \frac {R_2 \cdot V_{\rm ref}} {V_{\rm out}-V_{\rm ref}}
\tag{6}
$$</span></p>
<p><span class="math-container">$$
V_{\rm out} = V_{\rm ref} \left(\frac{R_2}{R_3} + 1 \right)
\tag{7}
$$</span></p>
<p>According to section 6.5, <span class="math-container">\$V_{\rm ref}\$</span> can vary from a minimum of 0.581v to a maximum of 0.611v with an expected value of 0.596v. Using the expected value of 0.596v and an R2 value as directed by the datasheet, which states "Select a value of R2 to be approximately 100 kΩ", we get a value of 5.73K for R3 - I selected a <a href="https://www.lcsc.com/product-detail/Chip-Resistor-Surface-Mount_Vishay-Intertech-CRCW04025K76FKED_C2091613.html" rel="noreferrer">5.76K</a> which should result in <span class="math-container">\$V_{\rm out} = 10.94V\$</span> - close enough.</p>
<p><strong>8.2.3.4 Undervoltage Lockout Set Point</strong></p>
<p>Ignored; left EN floating.</p>
<p><strong>8.2.3.5.1 Inductor Selection</strong></p>
<p><span class="math-container">$$
L_{\rm min} = \frac
{ V_{\rm out} \left(V_{\rm in(max)} - V_{\rm out} \right) }
{ V_{\rm in(max)} \cdot K_{\rm ind} \cdot I_{\rm out} \cdot f_{\rm sw} }
\tag{8}
$$</span></p>
<p>The datasheet tells us to use a <span class="math-container">\$K_{\rm ind}\$</span> value between 0.2 and 0.3 - I selected 0.3, as it was what they used in the example (and the text mentioned it was appropriate for low-ESR output capacitors, like I'll be using). Our minimum inductor value is 273μH. If we use slightly more rounded values - 11V for output, 24V for maximum input voltage, and 100mA current, then we get a minimum inductor value of 397μH. The datasheet also says "Smaller or larger inductor values can be used depending on the amount of ripple current the designer wants to allow so long as the other design requirements are met. Larger value inductors have lower AC current and result in lower output voltage ripple. Smaller inductor values increase AC current and output voltage ripple."</p>
<p>Because I want to minimize ripple (I want a very stable output voltage, hence the LDO stage that follows this DC/DC) and due to what I could find, I selected a <a href="https://www.lcsc.com/product-detail/Power-Inductors_YJYCOIN-YP0504-471M_C576609.html" rel="noreferrer">470μH inductor</a>.</p>
<p><strong>8.2.3.5.2 Output Capacitor Selection</strong></p>
<p><span class="math-container">$$
C_O > \frac
{ 2 \cdot \Delta I_{\rm out} }
{ f_{\rm sw} \cdot \Delta V_{\rm out} }
\tag{11}
$$</span></p>
<p>To have at most 100mV of output ripple for a 150mA step, equation 11 tells us we need at least 6μF of output capacitance. In general, more capacitance = less ripple, and I was already using a <a href="https://www.lcsc.com/product-detail/Multilayer-Ceramic-Capacitors-MLCC-SMD-SMT_Samsung-Electro-Mechanics-CL21A226MAQNNNE_C45783.html" rel="noreferrer">22μF capacitor</a> elsewhere on the board so I used it here, too.</p>
<p>This will give us a crossover frequency of 16.4kHz, according to equation 14, which is below the recommended 40kHz.</p>
<p><strong>8.2.3.5.3 Feed-Forward Capacitor</strong></p>
<p><span class="math-container">$$
C_6 = \frac{1}{2\pi\,f_0} \cdot \frac{1}{R_2}
\tag{16}
$$</span></p>
<p>We'll also use a 97pF capacitor as feed-forward "To improve the phase boost". I selected <a href="https://www.lcsc.com/product-detail/Multilayer-Ceramic-Capacitors-MLCC-SMD-SMT_FH-Guangdong-Fenghua-Advanced-Tech-0402CG101J500NT_C1546.html" rel="noreferrer">100pF</a>.</p>
<p>After the DC/DC Buck, I use an <a href="https://www.lcsc.com/product-detail/Linear-Voltage-Regulators-LDO_Advanced-Monolithic-Systems-AMS1117-ADJ_C6188.html" rel="noreferrer">AMS1117</a> to drop the voltage to 9V. It has a reference voltage of 1.25V, so for 9V output I used a <a href="https://www.lcsc.com/product-detail/Chip-Resistor-Surface-Mount_UNI-ROYAL-Uniroyal-Elec-0402WGF1200TCE_C25079.html" rel="noreferrer">120</a>/<a href="https://www.lcsc.com/product-detail/Chip-Resistor-Surface-Mount_YAGEO-RC0402FR-07750RL_C137936.html" rel="noreferrer">750</a> resistor divider, which should provide 9.0625V (close enough for my purpose, so long as it's stable).</p>
<p>I was careful with layout on the PCB to minimize loop area, and came up with this:</p>
<p><a href="https://i.stack.imgur.com/UPJyW.png" rel="noreferrer"><img src="https://i.stack.imgur.com/UPJyW.png" alt="PCB Layout" /></a></p>
<p>Immediately upon plugging in the power supply (confirmed 24V), the TPS54202DDC released the magic blue smoke. Is there anything I've done that's obviously wrong?</p>
| Why did my DC/DC Buck Circuit fail? | 2024-02-29T19:49:03.793 |
704395 | |pcb|pcb-design|routing| | <p>Absolutely nothing! It looks cool, that's all.</p>
<p>Maybe could be used to optimize routing density the tiniest bit, as the arcs can be stacked concentrically, whereas octagonal routes must stick out in the corners (and if snapped to grid, the diagonals will necessarily be spaced wider than the orthogonals, as a sqrt(2) slope can never be grid-aligned). Pretty rare use-case, I'd say, but it's an option.</p>
<p>Compare wavelength or edge rate (at the speed of light in the medium, i.e. including velocity factor in microstrip/stripline) to the radius of curvature; when wavelength is comparable or shorter, it can be perceptible in terms of a bump in impedance at that point along the transmission line, or with the trace as an antenna. We would therefore prefer larger radii -- gentler curves, smoother transitions -- for the highest frequencies, when the most stable impedance is demanded. That is, test equipment, precision RF/analog, may demand such geometry.</p>
<p>For no radius (sharp ortho/octo corners), compare to the trace width -- which is to say, it really only matters for frequencies so high, the transmission line itself is near cutoff (trace width ~ λ/4). These are high frequencies indeed, and the use of a PCB at all, becomes questionable: preferred methods may include (conventional air-filled metal) waveguides, dielectric waveguides or fiber optics, or even free-space optics.</p>
<p>It's unlikely that digital signals would even notice; the most likely interaction is the shift in impedance narrowing the eye, or increasing jitter (frequency-dependent amplitude effects, inter-symbol interference), which will be relevant for the most precise and demanding applications (~fs precise timing reference?). (Standards such as PCIe, HDMI, etc. are designed with quite crude interfaces in mind -- FR-4 PCBs, cheap connectors, consumer cables, etc. All the hard work is done by the interface chips, so that the supporting media can be as cheap as possible.)</p>
<p>The effect of curvature, is simply to stretch out (in time) and flatten out (in impedance), that bump in the characteristic impedance Zo of the trace. The width of the arc may also change depending on its curvature, to better maintain Zo.</p>
<p>You do see, from time to time, references where orthogonal routing has been done, with the corner clipped, chamfered -- there exists a calculation for this chamfer, to minimize Zo error along the trace. This could be seen as the limiting case of an arc segment of different trace width, as the chamfer effectively looks like a necked-down arc.</p>
<p>Again, even this is a small effect; in this case, the change in Zo might be modest (say, ±10%? I forget what the actual numbers are), and only in the vicinity of the corner, i.e. the trace length of differing Zo is very short. At lower frequencies, it looks like a lumped equivalent, a small L or C on the line.</p>
<p>See: <a href="https://www.microwaves101.com/encyclopedias/mitered-bends" rel="nofollow noreferrer">https://www.microwaves101.com/encyclopedias/mitered-bends</a> for better detail.</p>
<p>Regarding corners as antennas, really it matters more in terms of the change in boundary conditions: straight microstrip lines <em>are already antennas</em>, and we're not concerned about that <em>per se</em>, but the change in amount, particularly if it's ever higher. In other words, are there frequencies, signal levels, and emissions thresholds, such that the corner-turn can look like a sort-of-flattened 1/4-wave whip, or patch, or dipole or loop, type antenna? Again, these will only be pronounced effects at the highest frequencies, near cutoff, and can be safely ignored at low frequencies.</p>
<p>(A far stronger concern for emission, is whether the overall trace is sinuous, for example a trace that wiggles around will have a phase shift between segments which can therefore have all segments act in phase at some unlucky frequency, making a sort of phased-array multi-patch antenna; but for this purpose, the cornering of the trace is irrelevant, it's the topology that matters.)</p>
| <p>In PCB design, it's common to observe angled routings, yet curved routings are believed to offer better performance. Would using exclusively curved routings pose any issues in the PCB layout? Can someone clarify the differences in performance and potential considerations between angled and curved routing approaches?</p>
<p><a href="https://i.stack.imgur.com/7hNhq.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/7hNhq.jpg" alt="Curve routing For SPI" /></a></p>
<p><a href="https://i.stack.imgur.com/3mdQN.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/3mdQN.png" alt="Angled Routing " /></a></p>
| Angled vs. curved routing in PCB design specifically for SPI communication | 2024-02-29T21:31:27.567 |
704396 | |theory|qam| | <p>I see your question is explicitly about QAM, but implicitly is about what is called <strong>set partitioning</strong> and around it. Below i'll try to explain in detail.</p>
<h2>0. QAM itself as a digital-data transmission technique</h2>
<p>QAM operates on (modulates) a harmonic signal (the carrier). Given a timescale (or simply a time, <em>t</em>), we can represent a harmonic signal in the given timescale as a total of two orthogonal signals -- sine and cosine, of the same frequency (let's label it <em>w</em> = 2 * pi * <em>f</em>) -- of two amplitudes, let's call them A and B, respectively. I.e.,</p>
<p>harmonic(<em>t</em>) = A * sine(<em>w</em> * <em>t</em>) + B * cosine(<em>w</em> * <em>t</em>)</p>
<p>From this, we see that each orthogonal part can be modulated independently. I.e.,</p>
<p>modulated_harmonic(<em>t</em>) = A(t) * sine(<em>w</em> * <em>t</em>) + B(t) * cosine(<em>w</em> * <em>t</em>)</p>
<p>If we set A(t) = Q[t] and B(t) = I(t), where X[t] means a variable whose value changes discretely both in level and over time, this results in QAM(-modulated harmonic signaling):</p>
<p>QAM(t) = Q[t] * sin(<em>w</em> * <em>t</em>) + I[t] * cos(<em>w</em> * <em>t</em>)</p>
<p>Assuming that X[t] is generated by a DAC (digital-to-analog conversion) circuitry, we have that:</p>
<p>QAM(t) = DAC_Q[t] * sin(<em>w</em> * <em>t</em>) + DAQ_I[t] * cos(<em>w</em> * <em>t</em>)</p>
<p>From here is the answer for the first part of your title question:</p>
<blockquote>
<p>Why does QAM use a grid-like distribution ... ?</p>
</blockquote>
<p>As we can see, it is because a grid-like distribution is natural for QAM. Moreover, a regular, 2-D, square grid is the most natural for QAM, because it is an obvious way to use two similar DACs in the design.</p>
<p>In your initial figure two DACs of the same 2-bit construction each are assumed. Each drives it own orthogonal "sub-carrier" (Q or I) independently in content but synchronously in time, that gives a composite modulation of 4-bit a time, over the "total" carrier.</p>
<p>If we analyze only the discrete values (levels) of the Q and I DAC outputs, we deal with what is called the (initial) constellation (an image of the DAC-driven 2-D grid) of our QAM case.</p>
<p>Please note here that QAM itself gives us only a constellation, i.e., a set of abstract points in some abstract 2-D space. No codes (binary or other) are assigned (predefined) by the QAM itself.</p>
<p>Also, the QAM-specific part ends here, and the rest of my answer (and your implicit question) is applicable to any modulation that can be operated (abstractly modeled) as a constellation.</p>
<h2>0/1. Restricting the initial constellation</h2>
<p>Since we have an initial constellation, we can restrict on it, depending on our goals. It is an intermediate step in the coding design flow. I can give the following definition for this step: we eliminate the points which are never used in operation.</p>
<p>In literature, there is no consensus (in a form of attention) on this step is explicit or not, and often the initial constellation of a modulation scheme is already given restricted, i.e., with some number of its points excluded, before it will be partitioned. But in our case, it is better to explicitly demarcate it.</p>
<p>Please note here too, that still no codes are assigned after this step.</p>
<h2>1. Partitioned constellation</h2>
<p>Invented by <a href="https://en.wikipedia.org/wiki/Gottfried_Ungerboeck" rel="nofollow noreferrer">Gottfried Ungerboeck</a> as the basis of his <a href="https://en.wikipedia.org/wiki/Trellis_coded_modulation" rel="nofollow noreferrer">TCM</a>, set partitioning is a technique to partition a given initial (already restricted or not) constellation into a number of non-intersecting sets (also called cosets) of points. All such the points are used in operation.</p>
<p>At this level of abstraction, i.e., when we have a constellation, the most common metric used to qualify the points is the (square) distance, which is a geometric one, natural since a constellation is an geometric representation (reflection, model) of the signal.</p>
<p>During set partitioning, two (SQ)Ds are used: free minimal (SQ)D as (the square of) the Euclidean distance between two closest points in the initial constellation, and (simply) minimal (SQ)D as the same distance between to closest points in the partitioned cosets. Squares are preferred in comparison because give integer numbers.</p>
<p>The goal of partitioning is to provide, at least, M(SQ)D > free M(SQ)D. The purpose of set partitioning is to enable soft decoding-based FEC/FED (forward error correction/detection) on the receiving side, e.g., in a form of <a href="https://en.wikipedia.org/wiki/Viterbi_decoder" rel="nofollow noreferrer">Viterbi algorithm</a>.</p>
<p>In your initial figure, free MD is 1/sqrt(10), free MSQD=1/10. And as i can see, your need more :-)</p>
<p>And what do you propose?</p>
<h2>2. Your proposition</h2>
<p>Assuming QAM, you propose restrict on its initial constellation and next partition it (if i understand your coloring correctly, let's take it so), both to increase free M(SQ)D and next in-coset M(SQ)D, respectively. But your way seems unnatural because gives two different DACs, one is 6 levels (about one bit, even not a power of two) more in resolution than the other:</p>
<p><img src="https://i.stack.imgur.com/lb8sp.png" alt="Non-similar DACs" /></p>
<p>First, this leads for two irregular circuits of the same purpose to occur in the design. It's not optimal and good.</p>
<p>Second, let we'll be fair, your reinvent the wheel here, and the most close, practiced case here is the DSQ constellation design, e.g., <a href="https://www.ieee802.org/3/an/public/sep04/ungerboeck_2_0904.pdf" rel="nofollow noreferrer">DSQ-128 used in 10GBASE-T</a>:</p>
<p><img src="https://i.stack.imgur.com/6MjK5.png" alt="2D-PAM12 vs. DSQ-128" /></p>
<p>So, here the answer for the second part of your title question:</p>
<blockquote>
<p>... versus a more efficient spacing?</p>
</blockquote>
<p>There are many ways to increase the free M(SQ)D of an initial constellation, be it 2-D square grid (like in QAM) or other (e.g. <a href="https://grouper.ieee.org/groups/802/3/10G_study/public/june99/kardontchik_2_0699.pdf" rel="nofollow noreferrer">4-D hyper-cubic grid like it is modeled in 1000BASE-T</a>), (the most used) one of such is set partitioning giving a higher M(SQ)D between points in the resulted cosets.</p>
<p>An initial constellation is rarely used alone. The general way is:</p>
<p>Step 0/1. restrict the initial constellation</p>
<p>Step 1. partition the (restricted) constellation</p>
<p>Step 2. assign each operable point in each coset a code (binary or another)</p>
<p>Gray codes and/or other coding techniques are applied only on step 2 and contributes into the whole coding gain of the design. Today, an initial constellation (= plain modulation) alone is not considered in the context as the stand-alone subject of an effective solution, only as the ground for.</p>
<p>For example, PCI Express 6.0 uses the following coding scheme: RS-FEC over Gray over PAM-4.</p>
<p>1000BASE-T implements TCM over 8x2 cosets over 4D-PAM5 (at PCS, over 4D-PAM17, at PMA).</p>
<p>10GBASE-T implements LDPC-backed FEC over 2x (Gray + Pseud-Gray over DSQ-128 over 2D-[PAM16 + THP]), where THP = Tomlinson-Harashima Precoding.</p>
<p>(Of course, above i mention schemes that work over PAM, not QAM, but as i stated earlier (see sections 0 and 0/1), since we have a constellation (as an abstract, geometric representation of the underlying signaling and/or modulation), we can use the universal, modulation-independent principles of modeling.)</p>
<p>As Marcus Müller stated in his answer, (as an integral part of the whole coding design flow) <em>constellation shaping is a science of its own</em>. The above examples show this clean.</p>
<p>On other your sub-questions:</p>
<blockquote>
<p>Is it too complex to decode?</p>
</blockquote>
<blockquote>
<p>Maybe it doesn't offer any measurable benefit?</p>
</blockquote>
<p>Typically, a decoder is much more complex than the respective encoder. The complexity of encoding for 1000BASE-T and 10GBASE-T your can see in the above mentioned documents.</p>
<p>The measurable benefit is the coding gain of a coding scheme. As shown above, such a gain is a total of many but tightly-matched items. In the simplest modern case, it is resulted from well-matched binary FEC coding + bit coding + line coding (modulation).</p>
<p>At this point, i think the rest your sub-questions cannot have meaningful answers.</p>
<h2>Additional notes</h2>
<p>If you are interesting in this theme, i recommend you to begin with the following papers:</p>
<p>[1]. <a href="http://cs-www.cs.yale.edu/homes/yry/readings/wireless/wireless_readings/trellis1.pdf" rel="nofollow noreferrer">G. Ungerboeck, <em>Trellis-coded modulation with redundant signal sets, Part I: Introduction</em></a></p>
<p>[2]. <a href="http://cs-www.cs.yale.edu/homes/yry/readings/wireless/wireless_readings/trellis2.pdf" rel="nofollow noreferrer">G. Ungerboeck, <em>Trellis-coded modulation with redundant signal sets, Part II: State of the art</em></a></p>
<p>[3]. <a href="https://www.ieee802.org/3/an/public/sep04/ungerboeck_2_0904.pdf" rel="nofollow noreferrer">again G. Ungerboeck, <em>10GBASE-T Coding and Modulation: 128-DSQ + LDPC</em></a></p>
<p>[4]. <a href="https://grouper.ieee.org/groups/802/3/10G_study/public/june99/kardontchik_2_0699.pdf" rel="nofollow noreferrer">now not Ungerboeck, but Jaime E. Kardontchik, <em>4D ENCODING IN LEVEL-ONE'S PROPOSAL FOR 1000BASE-T</em></a></p>
<p>Moreover, you can meet how the real designers designed real constellation-based coding schemes, reading the materials documenting the respective IEEE 802.3 standardization processes:</p>
<p>[5]. <a href="https://www.ieee802.org/3/ab/public/index.html" rel="nofollow noreferrer">Public area of the 1000BASE-T task force</a></p>
<p>[6]. <a href="https://www.ieee802.org/3/an/public/index.html" rel="nofollow noreferrer">Public area of the 10GBASE-T task force</a> and <a href="https://www.ieee802.org/3/10GBT/public/index.html" rel="nofollow noreferrer">its preceding studying group</a></p>
<p>Also, because Marcus Müller mentioned some signal power-related issues in his answer, and because i see the tag "Theory" under your question, i recommend you to read something like this:</p>
<p>[7]. <a href="https://arxiv.org/ftp/arxiv/papers/2307/2307.12724.pdf" rel="nofollow noreferrer">"A collection of the data coding means and event coding means multiplexed over and inside the 1000BASE-T PMA sublayer"</a> (<a href="https://arxiv.org/abs/2307.12724" rel="nofollow noreferrer">abstract at arXiv</a>)</p>
<p>where power balancing of the physical signal is one of the tasks of the design flow, that results in schemes like a stellarial constellation over the 4D-PAM17 grid:</p>
<p><img src="https://i.stack.imgur.com/tbxRs.png" alt="stellarial constellation" /></p>
| <p>"Stand-Up Maths" recently did a <a href="https://www.youtube.com/watch?v=To7Ll5AGboI" rel="noreferrer">video</a> about QAM/data encoding. He presented a diagram of the encoding spacing for QAM:<br> <img src="https://download.huawei.com/mdl/image/download?uuid=d7f8fa0b937845e7952ccd54c0e19730" width="170" height="150" alt="Huawei provided QAM 16 diagram"></p>
<p>I'm from a software engineering background and I couldn't help but think: given that telecommunication companies are always aiming to get more out of the existing infrastructure, why not use a more efficient pattern for a QAM-like encoding scheme?</p>
<p>My original thought was a equilateral triangle spacing:</p>
<img src="https://upload.wikimedia.org/wikipedia/commons/thumb/6/64/Equilateral_Triangle_Lattice_3-color.svg/1024px-Equilateral_Triangle_Lattice_3-color.svg.png" width="100" height="100" alt="a grid of dots spaced as the vertex's of a plane of equilateral triangles">
<p>It satisfies some of the design parameters mentioned in the video (avoiding passing over the origin).</p>
<p>A triangular grid is about 2.3 times denser (the area of a equilateral triangle is about 0.43 with a grid spacing of 1).</p>
<p>My primary question is: what is the limiting factor for such a standard?</p>
<ul>
<li>Is it too complex to decode?</li>
<li>Maybe it doesn't offer any measurable benefit?</li>
<li>Could it be that a grid follows the same power of 2 expansion rate and that's just easier?</li>
<li>Perhaps larger encoding spaces can be achieved with increasing the maximum amplitude, rather than a more complex system?</li>
<li>Backwards compatibility?</li>
<li>Perhaps there isn't a single bit change "Gray code" system to traverse a triangular graph?</li>
</ul>
| Why does QAM use a grid-like distribution versus a more efficient spacing? | 2024-02-29T21:41:01.747 |
704404 | |rf|interference|tuning| | <p>Feeding an antenna raw into an amplifier input invites nonlinear behavior, leading to interference. I suggest replacing R1 with a parallel LC resonator, tuned to 40 kHz.</p>
<p>Speaking of tuning, I don't see any way to tune your filter. It's going to be too touchy to count on components off the shelf to resonate at exactly 40 kHz.</p>
| <p>The circuit in Figure 1 is designed to detect an RF signal at f0=40kHz. For information, this will be a portable proximity sensor, worn on a cat's collar, so it has be small and light.</p>
<p>The circuit detects 40kHz, but it also 'detects' almost any other piece of electrical equipment. My question is this: how can I ensure this circuit will pick up only 40kHz?</p>
<p>A subsidiary question is: if an LC tank circuit (at amp1) is better than an RC active filter (at amp2) at filtering signals, should I be using an LC tank circuit with amp2 (and vice versa)?</p>
<p><a href="https://i.stack.imgur.com/R6TaN.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/R6TaN.jpg" alt="enter image description here" /></a>
Figure 1.</p>
<p>The circuit is on a breadboard, so there are many connection wires on the breadboard which could pick up stray signals. However, removing the 18cm aerial eliminates the spurious activations at the output (F), which suggests the interference is not being picked up primarily by those breadboard connection wires (removing the aerial also prevents detection of my 40kHz signal).</p>
<p><strong>Overview of the circuit.</strong></p>
<p>The aerial has to be very short. The IC is a quad TLC274CN op amp. Amp1 uses the LC tank circuit to differentially amplify RF at 40kHz.</p>
<p>Amp2 is an active filter, using RC components centred on 40kHz, with a lower cut-off frequency of f1=30kHz and an upper cut-off frequency of f2=50kHz.</p>
<p>Amp3 just isolates all those RC components around amp2 from the rest of the circuit (and adds in some amplification with feedback resistor R5).
Amp3's output is rectified and smoothed before being fed to amp4.</p>
<p>Amp4 is a comparator, which compares amp3's output with a DC value set by the 50k variable resistor. The output from amp4 switches a transistor on/off which drives a buzzer (I have it connected to an LED instead now).</p>
<p>The RF at 40kHz is generated by an Arduino using a long stretch of speaker wire as a transmission antenna.</p>
| Tuned RF circuit: How to minimise interference? | 2024-02-29T23:12:49.033 |
704407 | |three-phase|power-measurement| | <blockquote>
<p>... phase to neutral or the phase to phase power?</p>
</blockquote>
<p>Assuming a balanced load:</p>
<p>It measures the power delivered or consumed on that phase. Even if the load is connected in Delta it still measures the power on that phase because the √3 times the voltage (between phases) is multiplied by 1/√3 due to the phase angle and the product is 1.</p>
<p>For an unbalanced load:</p>
<p>Take the cases where one of the <em><strong>Z</strong></em>s is open or short circuit then <em><strong>N<sub>L</sub></strong></em> will no longer be at the centre (star or wye point). The individual meter readings still tell you what power is being delivered by each phase but don't tell you <strong>where</strong> it is being consumed. The sum of the meters gives the total power consumed by the load.</p>
| <p>Does the zero point "where all the voltage coils are linked " in this watt meter connection indicates that the power measured by each one of the watt meter is the phase to neutral or the phase to phase power?</p>
<p><a href="https://i.stack.imgur.com/6f21W.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/6f21W.png" alt="enter image description here" /></a></p>
| Watt meter connection in three phase circuit | 2024-02-29T23:49:33.460 |
704409 | |mosfet|switches|logic-level| | <p>In the lower circuit, both transistors have their drains connected to the supplies. That's called <a href="https://en.wikipedia.org/wiki/Common_drain" rel="nofollow noreferrer">"common drain" or "source follower"</a>. The upper circuits have the sources connected to the supplies, a configuration called <a href="https://en.wikipedia.org/wiki/Common_source" rel="nofollow noreferrer">"common source"</a>.</p>
<p>Those two configurations behave very differently. For source followers, the source tends to follow the gate, but always different in potential by amount <span class="math-container">\$V_{GS(TH)}\$</span>. You can see that in action with a simulation:</p>
<p><img src="https://i.stack.imgur.com/1Q8xW.png" alt="schematic" /></p>
<p><sup><a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2f1Q8xW.png">simulate this circuit</a> – Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a></sup></p>
<p>With an input sweeping up and down between 0V and +5V (blue), here are the outputs of common drain (OUT1, orange) and common source (OUT2, brown) configurations:</p>
<p><a href="https://i.stack.imgur.com/z7jP7.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/z7jP7.png" alt="enter image description here" /></a></p>
<p>The main features to note are:</p>
<ul>
<li><p>The common source arrangement inverts</p>
</li>
<li><p>Common drain does not invert</p>
</li>
<li><p>Common source switches very "emphatically" when the input reaches <span class="math-container">\$V_{GS(TH)}\$</span>, having very high voltage gain</p>
</li>
<li><p>Common drain output "follows", with gain of about 1</p>
</li>
<li><p>Common source output extends all the way to both supply potentials.</p>
</li>
<li><p>Common drain output is lower than the input by amount <span class="math-container">\$V_{GS(TH)}\$</span>. For P-channel, the output would be higher, instead, but the offset would still be <span class="math-container">\$V_{GS(TH)}\$</span></p>
</li>
</ul>
<p>It is the <em><strong>potential difference</strong></em> between gate and <em><strong>source</strong></em> that determines the conduction state of the channel between drain and source. The difference in behaviour is due to the fact that in the common-drain setup, the source is permitted to rise and fall in potential by R1. By contrast, for common-source, source potential is held fixed at the supply potential (0V here, or +5V if this were P-channel).</p>
<p>Your circuits are simply combining those with P-channel equivalents, which replace the resistors in my N-channel examples. This produces a push-pull system able to both sink and source output current equally well (better than the resistor could), but the behaviour of each "half" individually remains exactly as I described above.</p>
<p>In the common drain configuration, you can never have an output that extends all the way to the supply rails (unless the input extends <em>well</em> beyond those supplies), and you will not have the clear, emphatic switching exhibited by the high-voltage-gain common source arrangements.</p>
| <p>I am trying to control the choice of 2 circuits using MOSFETs, at logic levels. Basically, I’d like to have one circuit feed bits to an IC in some conditions and another circuit do the same in another condition (both voltage related). The circuits in question don’t really matter, but rather I cannot figure out why the MOSFET route does not seem to work. It seems to hinge on the following, demonstrated in iCircuit:</p>
<p><a href="https://i.stack.imgur.com/zfQM5.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/zfQM5.jpg" alt="enter image description here" /></a>
<a href="https://i.stack.imgur.com/JeHnG.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/JeHnG.jpg" alt="enter image description here" /></a></p>
<p>When using the circuit on top in both examples, you get logic levels, but inverted (the circuit is indeed an inverter after all), and it works. But in the lower examples (which are not inverters, but rather simply a switch), you do not get logic levels any longer. Using the MOSFETs in this way seems to demonstrate a significant difference between the n and p versions.</p>
<p>Why do I not get logic levels from the lower circuit?</p>
| Making a circuit switch using MOSFETs | 2024-02-29T23:53:37.637 |
704413 | |mosfet|power|thermal|safe-operating-area| | <p>If the MOSFET is as "on" as it's possible to be, then <span class="math-container">\$R_{DS}=110m\Omega\$</span>. In this condition the graph of <span class="math-container">\$I_D\$</span> vs. <span class="math-container">\$V_{DS}\$</span> will be a straight line:</p>
<p><span class="math-container">$$ I_D = \frac{V_{DS}}{R_{DS}} = \frac{V_{DS}}{0.11\Omega} $$</span></p>
<p>This condition is represented by the diagonal portion of line at the upper left, shown in red here:</p>
<p><a href="https://i.stack.imgur.com/RYHLi.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/RYHLi.png" alt="enter image description here" /></a></p>
<p>Since it is technically impossible to obtain (DC) currents above this line, due to the minimum attainable <span class="math-container">\$R_{DS}\$</span> of 110mΩ, you need not concern yourself with that region.</p>
<p>In other words, it doesn't make much sense to plot values above that line in a graph of SOA, since you can't even get there in normal operation.</p>
<p>Your application requiring <span class="math-container">\$V_{DS}=77mV\$</span> and <span class="math-container">\$I_D=0.7A\$</span> will also necessarily lie on this line, and not above it, and is therefore "safe".</p>
| <p>I am using mosfet (IRHJ9A7234) as a load switch and Id current is about 0.7A and maximum Rds from datasheet is 110mohm. So I thought based on power calculation P= I^2*R = 77mW which is way below than rated power of 75W so I thought it was safe to use for my application. Now I am looking at the SOA curve as shown below. Vds in my case is Id * Rds = 77mV. However I don't see this range in Vds and not able to align with the conclusion I made with power calculation. So which one (SOA or power calculation) do I need to refer and make decision whether this Mosfet is good to use for my application? Same thing for Id vs Vds charateristic curve.. I do not see Vds below 0.1V
<a href="https://i.stack.imgur.com/390cQ.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/390cQ.jpg" alt="enter image description here" /></a></p>
| SOA Mosfet Confusion | 2024-03-01T00:37:43.873 |
704415 | |voltage-regulator|comparator| | <p>You're also going to have a problem that when the relay pulls in the voltage will drop a little due to the loading effect. Unless you add some hysteresis to the comparator the circuit will turn into a relay oscillator.</p>
<p>I would be inclined to make a separate rectifier for the comparator circuit - maybe a single diode, capacitor and discharge resistor - so that you can optimise the C value for the comparator and optimise a different C value for the load.</p>
<p>Having said all that, you might be better monitoring the frequency of the rectified, unsmoothed voltage, convert <em>that</em> to a voltage and then feed that to a comparator. The LM2907 might be suitable.</p>
<p><img src="https://i.stack.imgur.com/G8ZLG.png" alt="schematic" /></p>
<p><sup><a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fG8ZLG.png">simulate this circuit</a> – Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a></sup></p>
<p><em>Figure 1. A sketchy layout to get you started.</em></p>
<p>What does what:</p>
<ul>
<li>V1 and BR1 behave as before.</li>
<li>U2 provides a regulated 5 V supply for the F-to-V converter and the comparator setpoint (R2). I've shown a 7805 but they need about 7 V in to get 5 V out. This may result in incorrect switching at low voltage (at low RPM). You'll need to experiment.</li>
<li>D2 / R4 provide a half-wave pulse signal to the LM2907 for its frequency input.</li>
<li>I didn't read the datasheet but there will be a voltage limit on the input so D3 shunts any excess voltage off to the 5 V rail and R5 limits the current.</li>
<li>The LM2907 is just shown as a block. I haven't used one for about 30 years and didn't re-read the datasheet. C3 represents the timing capacitor. There are probably a few additional components required.</li>
<li>R2 determines the switching point on the comparator. It will be adjustable between 0 and 5 V.</li>
<li>Most comparators have open-collector outputs. That means they can only pull the output low.</li>
<li>Q1 is turned on by base current via R1. The comparator pulling low will turn Q1 off.</li>
<li>D4 is a snubbing relay to protect Q1 from high inductive kickback voltages when RLY1 is switched off.</li>
<li>I have not shown decoupling capacitors which are required on U1, U2 and CMP1. Follow the datasheet recommendations but usually 100 nF is right. Don't be tempted to omit them.</li>
</ul>
<p>Have fun.</p>
| <p>I have a variable AC voltage coming from the motor of a scooter, appropriately rectified with a bridge rectifier and large capacity capacitor.</p>
<p>The circuit I want to create will be powered by 12v DC, with which I created a threshold voltage of 7v with a divider.</p>
<p>With the LM393 I want to compare these two voltages: output high when the AC voltage exceeds the threshold voltage. I use the output of the LM393 to drive a relay. Being open collector, I can make the relay switch by placing it directly between output and +Vcc (with a protection diode).</p>
<p>The problem is that the comparator doesn't work with the rectified voltage coming from the motor. It would probably need a more careful adjustment...
Without It, the ripple being too high. How could I solve it?</p>
<p>I tried with an LM358 but it doesn't work anyway. How can I compare this very unstable voltage?
<a href="https://i.stack.imgur.com/rduHK.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/rduHK.jpg" alt="Schematics" /></a></p>
| LM393 - comparing variable AC voltage (rectified) | 2024-03-01T00:56:00.593 |
704430 | |lcd|display|lvds|deserialiser| | <p>Those pins are not sync pins.</p>
<p>The sync pins are already embedded in the LVDS data stream so it would make no sense for an LVDS display to require separate sync pins.</p>
<p>The pins just likely mirror the image horizontally and vertically.</p>
<p>Please double check from the pin description or ask the manufacturer.</p>
| <p>I need to use an LVDS display in my project.The pin configuration of LVDS display is given below(I can't share P/N here due to NDA).</p>
<p><a href="https://i.stack.imgur.com/UxjWH.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/UxjWH.png" alt="enter image description here" /></a></p>
<p><a href="https://i.stack.imgur.com/0s28y.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/0s28y.png" alt="enter image description here" /></a></p>
<p>As per my knowledge the PIN No 18 and 19 are Horizontal sync and Vertical Sync(Please correct me if I am wrong).</p>
<p>The deserializer used is <a href="https://www.ti.com/lit/ds/symlink/ds90ub928q-q1.pdf?HQS=dis-dk-null-digikeymode-dsf-pf-null-wwe&ts=1709264097467&ref_url=https%253A%252F%252Fwww.ti.com%252Fgeneral%252Fdocs%252Fsuppproductinfo.tsp%253FdistId%253D10%2526gotoUrl%253Dhttps%253A%252F%252Fwww.ti.com%252Flit%252Fgpn%252Fds90ub928q-q1" rel="nofollow noreferrer">DS90UB928QSQX/NOPB</a>.The deserailizer has no Horizontal Sync and vertical Sync PIN.</p>
<p><a href="https://i.stack.imgur.com/tD0Fi.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/tD0Fi.png" alt="enter image description here" /></a></p>
<p>May I know is it mandatory that Horizonatl and vertical sync pins are required for the working of this display ?.</p>
<p>Can I make pin no 18 and 19 of the display as not connected?</p>
| LVDS Display connected to Deserializer clarification needed | 2024-03-01T03:57:32.427 |
704433 | |pcb|connector|cables| | <p>Usually one uses male headers with an IDC cable such as this: <br />
<a href="https://www.adafruit.com/product/1675" rel="nofollow noreferrer">https://www.adafruit.com/product/1675</a> <br />
or say <a href="https://www.samtec.com/products/sfsd" rel="nofollow noreferrer">Samtec SFSD</a> or related parts.</p>
<p>If the header in question has alignment features, shrouding, etc., perhaps a better mate exists. Usually plain header is used for board-to-board purposes only (in production), and perhaps with a socket such as this for programming (during development and testing); as can be seen in the above link, they're a popular choice for JTAG/SWD connectors</p>
| <p>I am looking for a connector as shown in the image below. I am able to find the connector itself <a href="https://www.adafruit.com/product/5327?gad_source=1&gclid=Cj0KCQiA84CvBhCaARIsAMkAvkJhtro_grFFGYJgno9R_bye77RDB4u0DppRktMtPw2zFH9ti23X9JYaAntlEALw_wcB" rel="nofollow noreferrer" title="link">here</a>. But, I need cable connected to it as well. Can someone help me find this connector with cables connected to it?</p>
<p><a href="https://i.stack.imgur.com/t8RHX.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/t8RHX.png" alt="enter image description here" /></a></p>
| Can't find a mini connector (2x5, 0.05") | 2024-03-01T05:15:36.163 |
704437 | |mosfet| | <p>Below is the first stage, redrawn to have signals travel from left to right. I've drawn two identical instances of the same stage; on the left the input is 0V (digital low), and on the right the input is +3.3V (digital high):</p>
<p><img src="https://i.stack.imgur.com/8v1j0.png" alt="schematic" /></p>
<p><sup><a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2f8v1j0.png">simulate this circuit</a> – Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a></sup></p>
<p>The potential difference <span class="math-container">\$V_{GS} = V_G - V_S\$</span> is what determines the conduction state of Q8's channel.</p>
<ul>
<li><p>If <span class="math-container">\$V_{GS} >> V_{GS(TH)}\$</span> then the channel (between drain and source) is "on" and very conductive</p>
</li>
<li><p>If <span class="math-container">\$V_{GS} << V_{GS(TH)}\$</span> then that channel is "off", and conducts poorly.</p>
</li>
</ul>
<p>Notice that the transistor's source is tied to ground, and so has a fixed potential of <span class="math-container">\$V_S=0V\$</span>. This means that whatever potential <span class="math-container">\$V_G\$</span> applied to the gate will result in the following <span class="math-container">\$V_{GS}\$</span>:</p>
<p><span class="math-container">$$ V_{GS} = V_G - V_S = V_G - 0V = V_G $$</span></p>
<p>On the left, then, with <span class="math-container">\$V_{GS} = V_G = 0V\$</span>, we expect the transistor's channel to be like an open switch, not conducting, allowing R95 and R96 to "pull up" the potential at X to <span class="math-container">\$V_X = +12V\$</span>.</p>
<p>On the right, with <span class="math-container">\$V_{GS} = V_G = +3.3V\$</span>, the transistor is on, like a closed switch, highly conductive, and the potential at X is "pulled down" to <span class="math-container">\$V_X = 0V\$</span>.</p>
<p>If that's not clear enough, let me redraw those two scenarios with the transistors replaced by switches in those two states:</p>
<p><img src="https://i.stack.imgur.com/Uklr5.png" alt="schematic" /></p>
<p><sup><a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fUklr5.png">simulate this circuit</a></sup></p>
<p>Notice that this stage both translates logic levels from +3.3V up to +12V, <em>and</em> inverts so that high in -> low out and vice versa.</p>
<p>The second stage is very similar to that, except it employs a P-channel MOSFET insead of N-channel, so the source is connected to +12V instead of ground (0V). Also, there is presumably a heating element, which I represent with RH here:</p>
<p><img src="https://i.stack.imgur.com/IAcGP.png" alt="schematic" /></p>
<p><sup><a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fIAcGP.png">simulate this circuit</a></sup></p>
<p>This time, we require the gate to be significantly <em>lower</em> in potential than the source, for the transistor to be switched on, since the transistor is P-channel. This means <span class="math-container">\$V_{GS}\$</span> must be strongly negative. Notice that the source is tied to +12V, so now <span class="math-container">\$V_{GS}\$</span> is calculated like this:</p>
<p><span class="math-container">$$ V_{GS} = V_G - V_S = V_G - (+12V) $$</span></p>
<p>On the left, with <span class="math-container">\$V_G=+12V\$</span>, we have:</p>
<p><span class="math-container">$$ V_{GS} = (+12V) - (+12V) = 0V $$</span></p>
<p>Therefore we expect the transistor to be "off", highly resistive between drain and source. No current (well, nearly no current) flows due to this high resistance. With no current through it, heater RH has no potential difference across it, and it effectively "pulls down" the potential at OUT to 0V.</p>
<p>On the right, <span class="math-container">\$V_G = 0V\$</span>:</p>
<p><span class="math-container">$$ V_{GS} = (0V) - (+12V) = -12V $$</span></p>
<p>As stated above, this is the condition required for the transistor to be "on". The gate is significantly lower in potential than the source, so that <span class="math-container">\$V_{GS}\$</span> is strongly negative. That means the transistor conducts well. Node OUT is effectively connected directly to the +12V supply, and with the full 12V potential difference now across the heater RH, current flows restricted only by the heater's own resistance.</p>
<p>Again, these two scenarios can be represented with switches in the place of the transistors:</p>
<p><img src="https://i.stack.imgur.com/09YnX.png" alt="schematic" /></p>
<p><sup><a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2f09YnX.png">simulate this circuit</a></sup></p>
<p>This stage also inverts. That is, high potential at X produces low potential at OUT and vice versa. In this case, a <em>low</em> input will switch on the heater.</p>
<p>Your original, complete circuit is simply the first and second stages cascaded one after the other. The way it's drawn is very difficult to follow, but everything's easier to understand when care is taken with schematic layout:</p>
<p><img src="https://i.stack.imgur.com/9bmuE.png" alt="schematic" /></p>
<p><sup><a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2f9bmuE.png">simulate this circuit</a></sup></p>
<p>Hopefully it's clear now that:</p>
<ul>
<li><p>0V at IN causes +12V at X, which causes 0V at OUT, and no current flows in heater RH.</p>
</li>
<li><p>+3.3V at IN causes 0V at X, which causes +12V at OUT, and full current flows in heater RH.</p>
</li>
</ul>
<p>A couple more notes:</p>
<ul>
<li><p>R99 holds Q8's gate at 0V (avoiding a "floating" condition) in the absence of any explicit potential applied there. This ensures that the heater is off by default.</p>
</li>
<li><p>R96 is not necessary for this circuit to function. I suspect it is there to protect Q8 (and the microcontroller before it) from damage in the case that Q7 melts and becomes a source of unconstrained current direct from the power supply. R96 needs to be small compared to R95, since those two resistors form a potential divider, and we must avoid significantly altering (attenuating) the to 0V and +12V levels at X.</p>
</li>
</ul>
<hr />
<p>Additional note:</p>
<p>R95 is too large. Leakage current through Q8 can easily cause a significant voltage to develop across R95, which might partially switch on Q7. Just a few microamps of leakage current would cause this condition, and I recommend that R95 be 100kΩ instead. Leakage will depend on the model of Q8, which may well be specified to have sub-microamp leakage current (see "zero-gate-voltage drain current" in datasheets), but I think it's foolish to rely on such a parameter when it's so easy to mitigate.</p>
| <p>Forgive me as my electrical knowledge is sub par, but if someone can help clear up what I am trying to understand that would be greatly appreciated.</p>
<p>Q8 is an N channel enhancement MOSFET. From my understanding, when <code>Vgs == Vthresh</code> of a NMOS, then the gate turns on.</p>
<p>The <code>ON</code> input is an output from an MCU which should be 3v3. The <code>+12VHEAT</code> line is an output from another chip that is enabled via the MCU as well. These two signals are enabled one after another when a specific instruction is made.</p>
<p>What I am trying to understand is how the MOSFET works here. If <code>Vgs</code> (ON) is <code>== Vthresh</code> then the gate should become active right? What if there's an issue with the MCU and +12V becomes active? Does that mean the output to the IC (which is a P channel MOSFET) is still active? What if just the ON line is active, and there is no 12V - does 3v3 just run to the IC? I guess I'm really trying to understand how the ON line influences this gate and how it goes to ground/why it does.</p>
<p><a href="https://i.stack.imgur.com/iH5EG.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/iH5EG.png" alt="Here is the Circuit" /></a></p>
| What is happening in this circuit with N- and P-channel MOSFETs? | 2024-03-01T06:32:53.597 |
704441 | |power|switch-mode-power-supply|noise|linear-regulator|ferrite-bead| | <p>First some notes:</p>
<p>If your 24V load contains buck DC-DC converters to generate its internal power rails, or other noise makers like high current loads with PWM... it will generate a considerable amount of high frequency noise on the 24V input. Thus spending extra to feed it clean power is a waste of components. In fact, if a wall wart is used, the purpose of the input CLC filter in the device being powered is often to prevent noise from internal buck converters from radiating via the power cable...</p>
<p>High-current "low noise" power supplies are often a XY problem. If your load draws varying current (and if you use a 3.2A supply I'm pretty sure it will) then the output of your power supply will have ripple and noise due to load current variations and finite output impedance. This is unavoidable. The only way to have a perfectly clean power supply is to power something that draws constant current, like a clock oscillator.</p>
<p>Thus a targeted approach is often a lot more effective: find the thing in the circuit that is sensitive to noise (maybe some opamps, or a voltage reference) and add a good filter there. Since it will operate on a much lower current, you can get much better filtering more easily. Then find the thing that makes the most noise, and make it a quieter with a filter on the input, or other countermeasures.</p>
<p>For example if you have a class D audio amp, this will dump a ton of noise into the power supply. But the part that is sensitive to noise is just the input opamps, the error amp and modulator, in other words, maybe 10mA at 5-15V. So it's easy to design a very effective filter just for this.</p>
<p>Now on to the question: LM1084 PSRR according to datasheet:</p>
<p><a href="https://i.stack.imgur.com/LO1vi.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/LO1vi.png" alt="enter image description here" /></a></p>
<p>The first thing to do would be to characterize the ripple/noise on your power supply at the expected load current. You can use a spectrum analyzer, or a scope in FFT mode, or just eyeball the screen. Take note of noise in three frequency bands:</p>
<ul>
<li><p>Low (<10kHz)</p>
</li>
<li><p>Medium (10kHz-1MHz)</p>
</li>
<li><p>High (>1MHz)</p>
</li>
</ul>
<p>In the low band, if your switching power supply is competent there should be very little ripple and noise, unless the load is using low power and the supply enters a power-saving mode where it will go into cycles of burst then sleep or skip cycles, resulting in sawtooth ripple at much lower frequency than the usual switching frequency.</p>
<p>PSRR of LM1084 is very good in the low frequency band, so it will clean it up.</p>
<p>When looking at the PSRR plot in a datasheet, note that it very often includes the output cap, especially if the LDO requires one and can't be tested without it.</p>
<p>Medium band is the SMPS' switching frequency and harmonics. Linear regulators have falling PSRR with frequency so they're not usually very effective in this band. So you can use a LC filter. It should be well damped (usually by the capacitor's ESR). These filters usually employ electrolytic caps due to the large values required. The inductor will need to be quite high value and your current is also rather high, which means the inductor will be large, with many turns, thus high inter-winding capacitance and low self resonance frequency. In other words, the inductor will turn into a cap somewhere above 1MHz, and the capacitor, being large too, will turn into an inductor at a similar frequency. This means it will not be effective in the High band.</p>
<p>The high band contains switching spikes and their harmonics which extend very high. At this point, your LDO is a capacitor, so these go straight through. To clean this up you also need a LC filter, but with a low inductance cap (SMD MLCC) and an inductor that remains inductive at high frequency. Ferrite beads are ideal for this due to their dissipative nature. You should be careful to select one that will not saturate at your rated current.</p>
<p>Your SMPS may or may not already contain a LC filter at the output.</p>
<p>Filters should be placed before the LDO, otherwise they add up to the output impedance.</p>
| <p>Suppose I have an instrument which needs a very clean power supply line. I have an SMPS which outputs 24 V at 3.2 A, which is then cleaned via a LM1084 linear regulator.</p>
<p>Given that the output of a SMPS usually is considerably noisy (noise spikes and nonlinear ripple), would it be prudent to include a ferrite bead between the SMPS and the linear regulator to suppress HF noise? Or is the regulation provided by the LM1084 enough for a clean supply?</p>
| Ferrite bead on a SMPS output | 2024-03-01T07:24:23.317 |
704456 | |dc-blocking| | <p>As everyone said, place the (+) to the node with the highest DC potential.</p>
<p>And about C29, it has a direct DC path via the pot to the output of U6B, which can source or sink current, I'm sure.</p>
| <p>Where is the logic when using polarized DC blocking caps in a circuit?</p>
<p>I am not talking about -3dB point, but about the polarity orientation.</p>
<p>For example:<a href="https://i.stack.imgur.com/s7YsF.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/s7YsF.jpg" alt="enter image description here" /></a></p>
<p>this is taken from <a href="https://www.youtube.com/watch?v=-L-fKuAbQ9s" rel="nofollow noreferrer">USB Headphone Amplifier Design Walkthrough - Phil's Lab #101</a> on Youtube</p>
<p>How to determine the correct orientation?</p>
<p>AND: shouldn't we use a drain resistor after C29 to discharge it?</p>
| DC blocking caps | 2024-03-01T10:15:42.943 |
704471 | |circuit-protection|over-voltage-protection|reverse-polarity| | <p>The simplest reverse connect circuit is a reverse biased diode connected across the input in series with a fuse.</p>
<p>To protect against a sustained over voltage rather than transients you can use a crow bar circuit. This is a SCR
set up to be triggered in the event of the input voltage getting too high this again blows a fuse.</p>
<p>The fuse for these two schemes can be the same device. There are self healing or resetable fuses available.</p>
<p><img src="https://i.stack.imgur.com/25VRS.png" alt="schematic" /></p>
<p><sup><a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2f25VRS.png">simulate this circuit</a> – Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a></sup></p>
| <p>I am designing a device that will include a DC power jack. There is an external wall adapter that converts the 110-230 VAC from the mains to 20 VDC. Here is the schematic:</p>
<p><a href="https://i.stack.imgur.com/A4zcU.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/A4zcU.png" alt="enter image description here" /></a></p>
<p>I intend to use a standard DC power jack, such as the <strong>694106106102</strong> from Wurth Elektronik (<a href="https://fr.farnell.com/cliff-electronic-components/fc68148/embase-pcb-alim-dc-2-1mm-pqt-10/dp/224959" rel="nofollow noreferrer">URL</a>). The device will draw a maximum of 2 A from 20 VDC.</p>
<p>Here is my concern: I cannot prevent people from inserting an incompatible wall adapter. Thus, I need to make sure that this will not completely destroy the device. I suppose I need to prevent reverse polarity and over-voltage.</p>
<p>Do I need to add other protections? How are these protections generally integrated? Are there classical schematics/components that are usually used? Up to which voltage should I ensure over-voltage protection?</p>
<p>Thank you for your advice.</p>
| How to protect a device from reverse polarity and over-voltage? | 2024-03-01T12:38:14.747 |
704476 | |pic|pullup|reset| | <p>The nebuliser was needed fairly urgently, so in the interest of getting a marginally-useful fix (for what might be a common failure mode) into the record.</p>
<p>Provided that:</p>
<ul>
<li><p>With the head connected and the charger and battery disconnected, plugging in the charger activates the nebuliser.</p>
</li>
<li><p>With the head connected and the charger and battery disconnected, connecting the battery activates the nebuliser.</p>
</li>
<li><p>In both the above cases, pressing the button deactivates the nebuliser.</p>
</li>
<li><p>With the head and battery connected, shorting the PIC reset (pin 1) to the marked ground activates the nebuliser.</p>
</li>
</ul>
<p>An acceptable hack is to desolder the "on/off" button and to connect it instead between the PIC reset (pin 1) and the marked ground. With this done, the button turns the nebuliser on (green LED comes on) and it may be turned off by disconnecting the atomizer head (red LED comes on, shuts down after a few seconds).</p>
<p>The downside of this is that the PIC is permanently running, so the nebuliser benefits from being kept on the charger. Apart from that, since I believe there was no automatic cutoff once the medication had been dispensed the overall capabilities are very similar to the "as shipped" state.</p>
| <p>I'm trying to repair a "Flexineb E2" veterinary nebuliser for somebody, it holds a charge and works plausibly well if the battery connection is briefly interrupted but will not power-on if the power button is pressed.</p>
<p>PCB is 4-layer with multiple boost PSUs, and I'm very much trying to avoid tracing the circuit :-)</p>
<p>The power on/off button is momentary and looks like it has a FET across it to maintain power once the unit's on. There's a PIC33FJ12, which appears to do little else other than monitor the button for turn-off and presumably to detect that all medication has been dispensed.</p>
<p>If I short the PIC MCLR/ signal to ground the unit comes on, so an easy fix would be an external reset button.</p>
<p>MCLR/ has a 1k0 (SMD resistor marked 1001) pullup to 3v3 (labelled testpoint) with no nearby cap that I can see.</p>
<p>The datasheet etc. suggests a 10k pullup. Is it plausible that the problem as observed is due to the 1k0 pullup being vastly too strong?</p>
<p>Datasheet at <a href="https://ww1.microchip.com/downloads/en/devicedoc/70265b.pdf" rel="nofollow noreferrer">https://ww1.microchip.com/downloads/en/devicedoc/70265b.pdf</a></p>
| PIC reset pullup | 2024-03-01T13:25:33.683 |
704489 | |amplifier|transimpedance| | <p><strong>N-channel JFET</strong></p>
<p>An N-channel JFET is a "natural" at being a decent constant current sink.</p>
<p>Here's the J107 as an example: -</p>
<p><a href="https://i.stack.imgur.com/vWJQt.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/vWJQt.png" alt="enter image description here" /></a></p>
<p>The vertical axis is current and, the horizontal axis is time (in which the voltage source V1 is varied from zero to 20 volts). As you can see, once you get to about 0.4 seconds (5 volts across JFET and series resistor), it starts behaving like a constant current sink. Hey, it's not perfect but, what can you expect from two components.</p>
<p>Because you need to take the gate-source voltage negative in order to shut-down conduction, the source naturally "finds" a voltage where the device enters near-equilibrium.</p>
<p>If the JFET tries to conduct more, the gate becomes more negative with respect the gate and conduction decreases. If the JFET tries to conduct less, the gate is less-negative with respect to the source and conduction increases.</p>
<p>It's also a very good example of negative feedback in action.</p>
| <p>I am designing a mic amplifier with a transimpedance amplifier circuit. The mic is connected to a JFET. I know how a transimpedance amplifier works and that it works by converting current into a voltage but I do not understand in connection with the below circuit how exactly does this process take place?</p>
<p>So there is a voltage drop across the resistor R1 and this is a variable voltage. The capacitor C1 works as a short for AC so the variable voltage generated by the mic is directly seen at the negative input terminal of the op amp. Why doesn't the output then swing to the positive or negative voltage rail if the voltage at the negative input terminal fluctuates sinusoidally?</p>
<p>How exactly does the mic/JFET branch of the circuit function as a current source supplying a constant current to the op amp?</p>
<p>EDIT: THE JFET is integrated in the mic capsule in the below image</p>
<p><a href="https://i.stack.imgur.com/mSWvU.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/mSWvU.jpg" alt="enter image description here" /></a></p>
| How/why exactly does this JFET work as a current source? | 2024-03-01T14:54:00.590 |
704496 | |amplifier|differential|feedback| | <p>Apparently it exists...</p>
<p><a href="https://i.stack.imgur.com/HpOL1.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/HpOL1.png" alt="enter image description here" /></a></p>
<p>(<a href="https://www.semanticscholar.org/paper/Fully-Differential-Difference-Amplifier-for-Arbet-Nagy/23d526607dd0701ed831fcfcab0e67c16cf6c339" rel="nofollow noreferrer">source</a>)</p>
<p>It's a FDDA "Fully Differential Difference Amplifier", searching this term yields articles and schematics.</p>
<p>In other words, it's an opamp where both inputs and the output are differential signals.</p>
<p>Since a differential signal has two "halves", it has double the number of pins.</p>
<p>It has the same structure as a differential amplifier, but it has two gm input stages (<a href="https://www.researchgate.net/figure/Block-diagram-of-a-fully-differential-difference-amplifier_fig11_224185776" rel="nofollow noreferrer">source</a>).</p>
<p><a href="https://i.stack.imgur.com/beCeT.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/beCeT.png" alt="enter image description here" /></a></p>
<p>There is a small subtlety: in the usual differential amplifier, as long as feedback is operating and it's not clipped, both inputs sit at the same potential, which is between the common mode of input and output, and differential voltage between the two inputs is very small.</p>
<p>However, the FDDA has two differential inputs, which means each has its own common mode. And in the first pic of this post, voltage between Vin1 and Vin2 is the input signal, which means it's not small, which means these "+" and "-" don't belong to the same input LTP. Otherwise, it would clip. Or it would need to be something else than a LTP.</p>
<p>A quick fix is to swap one of the polarities from one LTP to the other... but this only works when input and output common mode are the same, otherwise the input LTPs get too much differential voltage...</p>
<p><a href="https://i.stack.imgur.com/km1Pj.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/km1Pj.png" alt="enter image description here" /></a></p>
| <p>There are several examples of the 4 feedback topologies in single-ended circuits.</p>
<p>In the case of series inputs (i.e. series-shunt and series-series topologies), the input is connected directly to an input terminal of the forward amplifier (e.g. non-inverting input of an op-amp or base of a transistor). Examples of single-ended series-shunt and series-series circuits are shown below (snipped from Design with Operational Amplifiers by Sergio Franco):
<a href="https://i.stack.imgur.com/ShMeP.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/ShMeP.png" alt="enter image description here" /></a>
<a href="https://i.stack.imgur.com/pP2FS.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/pP2FS.png" alt="enter image description here" /></a></p>
<p>Are there fully differential feedback circuits with series inputs?</p>
<p>An example of a fully differential feedback circuit is shown below (snipped from Gray and Meyer). This example, however, is a shunt-shunt topology after a Norton transformation is applied to the input.</p>
<p><a href="https://i.stack.imgur.com/56CyS.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/56CyS.png" alt="enter image description here" /></a></p>
<p>In the case of a fully differential amplifier, I think it would look something like connecting the input voltage between the feedback network and the amplifier input (potentially wrong example shown below).</p>
<p><img src="https://i.stack.imgur.com/jVAKJ.png" alt="schematic" /></p>
<p><sup><a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fjVAKJ.png">simulate this circuit</a> – Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a></sup></p>
| Are there fully differential feedback amplifiers with series inputs? | 2024-03-01T16:25:01.247 |
704497 | |theory|qam| | <p>Binary signals are <strong>0</strong> or <strong>1</strong> - a state will be assigned to each of these values. They come in the form of digital logic / voltage levels (e.g: On = 3.3v = Logic 1, and Off = 0v = Logic 0), but also in modulated signals, such as <a href="https://en.wikipedia.org/wiki/On%E2%80%93off_keying" rel="nofollow noreferrer">On-Off Keying</a> (where the presence or absence of a tone or carrier indicates the state, e.g: <a href="https://en.wikipedia.org/wiki/Morse_code" rel="nofollow noreferrer">Morse Code</a>). These are <em>very</em> simple to deal with, but still need to be assigned into one of the two buckets - noise and other factors can make this difficult, and assigning samples to the wrong bucket results in corruption, errors, retransmits, etc...</p>
<p>Extending binary signalling slightly, and you get <a href="https://en.wikipedia.org/wiki/Pulse-amplitude_modulation" rel="nofollow noreferrer">Pulse Amplitude Modulation</a> where the number of discrete levels is increased from 2, to <em>n</em>... For example, the ubiqutous <a href="https://en.wikipedia.org/wiki/Gigabit_Ethernet#Copper" rel="nofollow noreferrer">Gigabit Ethernet</a> employs PAM-5 (i.e: 5 discrete signal levels). An RF equivelant is <a href="https://en.wikipedia.org/wiki/Amplitude_modulation" rel="nofollow noreferrer">Amplitude Modulation</a> (and <a href="https://en.wikipedia.org/wiki/Amplitude-shift_keying" rel="nofollow noreferrer">ASK</a>), where the carrier tone is altered in amplitude only.</p>
<p>Another option is <a href="https://en.wikipedia.org/wiki/Frequency_modulation" rel="nofollow noreferrer">Frequency Modulation</a> (including things like <a href="https://en.wikipedia.org/wiki/Frequency-shift_keying" rel="nofollow noreferrer">FSK</a> and <a href="https://en.wikipedia.org/wiki/LoRa" rel="nofollow noreferrer">LoRa</a>), where the carrier tone is altered in frequency only... but that's not what we're focusing on here.</p>
<p>Pairing a shift in amplitude with a shift in phase, allows more data to be conveyed for any given symbol - all of a sudden we have two useful dimensions without leaning even harder on determining slight changes in amplitude. Note that the baudrate (i.e: rate at which the signal changes from one state to the next) will generally be many times the carrier's period (many wavelengths)... this is impractical to show in examples, so the signal is often truncated to a very small ratio between the two (1:1 in Matt's video).</p>
<p>Now, with those two useful dimensions, aside from a portion of the frontend, we can easily have an identical pair of signal paths - one that handles the I component (<strong>I</strong>n-Phase, 0°) , and one that handles the Q (<strong>Q</strong>uadrature, 90°), as discussed in <a href="https://electronics.stackexchange.com/a/704400/142242">my answer to your original question</a>. Both paths are able to place symbols into buckets, with the same number of buckets, the same spacing between buckets, etc...</p>
<p>When dealing with digital systems, it's also incredibly useful to have <em>n</em> equal to a <a href="https://en.wikipedia.org/wiki/Power_of_two" rel="nofollow noreferrer">power of two</a>... so for 16-QAM, we have 2x dimensions, each with 4x buckets, giving us a 4-bit value per symbol.</p>
<p>If we were to use something that packed points more tightly into a given 2D space, like your suggestion of an equilateral triangle, there are a few significant changes to the encoding:</p>
<ul>
<li>Each axis now has different number of levels (7 on the X, and only 4 on the Y), with different gaps between each point... that increase in levels converts directly into an increase in errors. If you can tolerate that, then why not increase the points on both axes?</li>
<li>Each one of the axes is able to detect and categorize more levels than before, but also, many of the resulting combinations are now invalid, which is inefficient.</li>
<li>If we consider the X axis to be -1.0 to +1.0, then the Y axis is only -0.86 to +0.86, which isn't optimal.</li>
<li>This constellation now gives us ~3.74 bits of information per symbol (a reduction when compared to 4), which would need to be rounded down to 3-bits (thus points discarded or trimmed), or combined with a more complex coding scheme on top.</li>
</ul>
<p><img src="https://i.stack.imgur.com/Sxctq.png" alt="X/Y plot showing the equilateral triangle points, with a bounding box at +/-1.0, and an invalid point marked" /></p>
| <p>This is a follow up from this previous <a href="https://electronics.stackexchange.com/questions/704396/why-does-qam-use-a-grid-like-distribution-versus-a-more-efficient-spacing">question</a> discussing why QAM encoding is spaced in a grid like pattern like this one:</p>
<img src="https://download.huawei.com/mdl/image/download?uuid=d7f8fa0b937845e7952ccd54c0e19730" width="170" height="150" alt="Huawei provided QAM 16 diagram">
<p>versus another with more efficient packing:</p>
<img src="https://upload.wikimedia.org/wikipedia/commons/thumb/6/64/Equilateral_Triangle_Lattice_3-color.svg/1024px-Equilateral_Triangle_Lattice_3-color.svg.png" width="100" height="100" alt="a grid of dots spaced as the vertex's of a plane of equilateral triangles">
<p>After looking at @Attie and @MarcusMüller's awesome answers and rewatching the video I have a leading idea that may explain a grid based QAM.</p>
<p><strong>Question</strong>:</p>
<p>If the broadcasted signal is the result of 2 waves' constructive and destructive interference and only each wave's amplitude is modulated... could it be a <a href="https://en.wikipedia.org/wiki/Quantization" rel="nofollow noreferrer">quantization</a> issue?</p>
<p>To clarify: I imagine we don't have a broadcasting device that has a perfectly continuous output and therefore can't output unlimited resolution for these signals. If that is the case, a combination of 2 discrete amplitudes would always result in a grid like pattern:</p>
<img src="https://i.stack.imgur.com/Nx6ma.png" width="200" height="200" alt="A stack of 4 bell curves all centered on x=0, y=1-4">
<p>So an equilateral or irregular symbol distribution would sacrifice a discrete step in order to conform to the non-grid standard. Example created in <a href="https://www.desmos.com/calculator/otto1ef7ei" rel="nofollow noreferrer">Desmos</a>:</p>
<p>Each purple line represents a discrete amplitude a broadcast device could reliably and accurately achieve. The example should show that the purple grid interests at points the equilateral distribution does not, yet the same resolution is required for both schemes.</p>
<img src="https://i.stack.imgur.com/AXxp1.png" width="500" height="500" alt="A regular grid intercepting a equilateral grid showing that the regular grid intersects at points that the equilateral triangle does not">
| Could QAM using a grid-like distribution be a quantization limitation? | 2024-03-01T16:29:19.747 |
704509 | |current|transformer|power-electronics|dc-dc-converter| | <p>Once the MOSFET deactivates, the flux in the core demagnetizes via the 3rd winding and diode. The dotted end of the 3rd winding tries to goes negative but, it's clamped at -0.7 volts by the diode and, the flux energy in the core returns as a current back to the power supply (from the undotted end of the 3rd winding).</p>
<p>This method saves an extra MOSFET but, these days probably more forward converters will use an extra MOSFET to drive the single primary winding in push-pull.</p>
<blockquote>
<p><em>Thus how can a current flow with no potential difference as the
voltage source and the coil are on same potential?</em></p>
</blockquote>
<p>An inductor's voltage does not prevent it from supplying current when the only route to demagnetize the core is via the 3rd winding. For instance, consider this <a href="https://electronics.stackexchange.com/questions/536975/what-happens-when-the-direction-of-initial-current-through-an-inductor-is-opposi/536986#536986">from here</a>: -</p>
<p><a href="https://i.stack.imgur.com/EdtzI.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/EdtzI.png" alt="enter image description here" /></a></p>
<p>At 10 seconds into the plot, the applied voltage on the inductor is positive but, the inductor current is negative. At 12 seconds is the point in a 3-winding forward converter when the magnetic field is discharged. Sorry, I haven't got a better example but hopefully you'll see why current can still flow back into the power supply (via your diode).</p>
<p>This is what inductors do in these types of circuit and in AC circuits.</p>
| <p>I am slightly confused about the flow of the current in the forward converter during the turn off time of the MOSFET (when diode on left is conducting) as shown below. Now I am considering that n1=n2=n3. During the turn of time there must be a current IM (im=i3) flowing in the extra winding with a diode. From the <a href="https://youtu.be/imvoBKdv09E?t=1403" rel="nofollow noreferrer">figure</a> below it is seen that there is a voltage of Vd across the winding also considering zero drop on diode.</p>
<p><a href="https://i.stack.imgur.com/IW3Tm.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/IW3Tm.png" alt="enter image description here" /></a></p>
<p>Thus how can a current flow with no potential difference as the voltage source and the coil are on same potential?? Shouldn't the potential on the coil be higher than the voltage source for the current to flow?</p>
| Forward converter current flow confusion | 2024-03-01T18:40:06.827 |
704527 | |microcontroller|gpio| | <p>Step 1 is to configure the pin using the <code>GPIOx_CTL0</code> and <code>GPIOx_GTL1</code> registers, as you know.</p>
<p>Step 2 in many MCUs, is to select <em>which</em> alternate function you wish to use, from within a GPIO or PINMUX type peripheral... I've tripped on this before with the STM32F103 family (very "<em>closely related</em>" to the GD32F103), and it seems neither of them support this - instead the output signals are enabled from the peripheral's side (I don't know what happens if you enable two, "<em>be careful</em>"?).</p>
<p>I haven't actually used the GD32F103, but I <em>believe</em> you can simply set <code>GPIOA_CTL0.CTL1</code> and <code>GPIOA_CTL0.MD1</code>, then:</p>
<ul>
<li>For <code>USART1_RTS</code>: set <code>USART_CTL.RTSEN</code></li>
<li>For <code>TIMER1_CH1</code>: set <code>TIMER1_CHCTL0.CH1MS[1:0]</code> to output, and then set <code>TIMER1_CHCTL2.CH1EN</code> to enable that output</li>
</ul>
| <p>I am trying to understand how alternate functions work at the register level for the GD32 microcontroller. For example, in the case of the <a href="https://www.gigadevice.com/product/mcu/arm-cortex-m3/gd32f103t4u6" rel="nofollow noreferrer">GD32F103</a>, there are several alternate functions available for pin PA1: USART1_RTS, ADC12_IN1, TIMER1_CH1, and TIMER4_CH1. From the <a href="https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20230227/GD32F103xxDatasheet_Rev2.14.pdf" rel="nofollow noreferrer">GD32F103xx datasheet</a>:</p>
<p><a href="https://i.stack.imgur.com/2nYbY.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/2nYbY.png" alt="enter image description here" /></a></p>
<p>The user manual states that to choose an alternate function, we should set 10 or 11 in the CTL register (GPIOx_CTL0). However, I don't understand which <strong>specific</strong> function will be assigned to PA1: USART, TIMER1, or TIMER4. From the <a href="https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20230209/GD32F10x_User_Manual_EN_Rev2.6.pdf" rel="nofollow noreferrer">GD32F10x User Manual</a>:</p>
<p><a href="https://i.stack.imgur.com/1OsA8.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/1OsA8.png" alt="enter image description here" /></a></p>
<p>Could someone with experience with the GD32 provide some guidance?</p>
| GPIO Alternate Function GD32 | 2024-03-01T22:38:37.523 |
704537 | |motor|dc-motor|design|electromagnetic|materials| | <p>This is more of a materials question. Materials are an important part of electronic equipment, but you may find more and better answers on the <a href="https://engineering.stackexchange.com/">Engineering Stack</a>.</p>
<p>Glass is a poor choice here, as it's hardly machinable, is sensitive to sudden changes in temperature (assumed: arcing), and isn't especially strong. Low-expansion types such as borosilicate or even fused quartz, are available, but are harder to work, and more expensive.</p>
<p>Tempered glass is almost certainly out, as tempering (freezing the surface faster than the core to lock in compression in the surface and tension in the core), can only be applied to whole pieces, largely flat and simple shapes. I don't know enough about tempering to say whether a part of this shape can be produced, but you almost certainly will not be able to machine (read: grind) it to an exact shape, not only because it deforms as that locked-in stress is partially relieved upon cutting the surface (compare: machining cold-rolled metal), but as is particularly notorious for tempered glass, any significant defect results in a cascade failure as the whole item shatters into a thousand bits.</p>
<p>Common choices for engineering materials include fiberglass reinforced epoxy or phenolic resin, available with quite reasonable operating temperatures (e.g., PCBs withstand soldering temperature, albeit not bearing much force at such temps). FR-4, G10 and other materials are cheap and abundant, and readily machined with carbide tools (or HSS in a pinch, if you don't mind dulling them quickly). There are also silicone and ceramic cements of varying strength and working temperature range.</p>
<p>You may not need any insulation at all. Ferrite magnets aren't particularly conductive, and the operating voltage is probably only ever going to be a few volts, if I make a ballpark guess at the speed and scale of this machine. Little current is shunted through such material.</p>
<p>Once you have exhaustively determined that heating is inevitable (i.e. the sliding contact or slip rings cannot be improved further), you may consider more advanced engineering materials. For example, the stator rings could be copper rings/collars/plates brazed onto, or pressed into, an alumina or other ceramic insulator substrate, into which the magnet is fitted. Water cooling passages can be embedded within either material, and rotating couplings can be used to cool the rotor. Copper-loaded tungsten might be used to increase abrasion resistance, or copper-loaded graphite for lubrication.</p>
<p>There are also softer, but better machinable, ceramic materials, such as Macor. Not terribly cheap IIRC, but effective for high temperature prototyping.</p>
<p>Also don't ignore sheet insulation materials. Airgap must be kept to a minimum for the magnets to do the most work. (I assume you also have steel pole pieces returning flux around the magnets.) Tough sheet materials like polyimide "foil", fiberglass, Nomex or Kevlar textile or composite, etc. are available. Fiberglass sheet and mica paper (dry, no resin) are available with very high operating temperatures, though not much abrasion resistance given their fibrous or soft nature.</p>
<hr />
<p>Most of all, though: don't commit premature optimization. <em>Don't care about materials.</em> Use glue, epoxy, paper, ABS; use aluminum or even iron conductors for all that matters. Solve everything else first. Minimize air gap -- use pole pieces, maximize cross-sectional area, maximize conductor width and optimize thickness, maximize brush contact area. To do all this, you need small prototypes that are easy to machine, iteration after iteration. You don't need brittle unworkable materials with high performance. Make a bad motor first. But make it the best damned "bad" motor you possibly can. Then make it "good" with proper choice of materials.</p>
<p>Only then: determine operating parameters, design torque, speed, voltage; mechanical outline / aspect ratio; and scale the mechanical design to that. Voltage determines insulation; you will likely find little is required for a motor of this type (like I said, single volts perhaps). Likely you can optimize performance enough to get efficiency usefully high (>80%?), so that high-temperature materials and water cooling aren't required, or not until higher power levels (kW+?).</p>
<p>Good luck!</p>
| <p>I am in the design phase of building a simple axial flux permanent motor, and I am wondering if I should use a piece of tempered glass as both an insulating material and as part of the motor's frame.</p>
<p>To illustrate the working principle of this conceptual DC electric motor, I have created three conceptual drawings. The first drawing shows two of the primary parts of this motor. The second drawing shows the other two primary parts of this motor. The third drawing shows the assembled primary parts of the motor.</p>
<p><a href="https://i.stack.imgur.com/OaRMD.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/OaRMD.png" alt="enter image description here" /></a>
<a href="https://i.stack.imgur.com/9e8WW.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/9e8WW.png" alt="enter image description here" /></a>
<a href="https://i.stack.imgur.com/PTmuD.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/PTmuD.png" alt="enter image description here" /></a></p>
<p>The purpose of using a pot magnet is to minimize the magnet's magnetic field within the interior area of the pot magnet so the rotor and the armature will not be slowed down by it and/or be heated up by it from resistive heating.</p>
<p>I am planning to fasten the circular rails (which will be made using bare 8-gauge solid core copper wires) to the piece of tempered glass using a strong metal-to-glass adhesive. The tempered glass will insulate the electrified circular rails from the pot magnet. Also, the two short pieces of bare wires attached to the armature will also be 8-gauge solid core copper wires.</p>
<p>The two bare copper wires on the armature will slide along on the bare copper circular rails, this direct contact will provide a path for the DC electrical current, and the magnetic interaction between the two rails and the two wires on the armature, along with the magnetic field of the pot magnet, will propel the two wires in a counter-clockwise direction and this will result in rotating the motor's rotor.</p>
<p>An unwanted side effect of this magnetic interaction is that the two rails will repel one another. I am concerned that this repulsion may become strong enough to break the adhesive bond holding the circular rails to the tempered glass if the electric current were to get too high. I think that this could also result in the tempered glass breaking/shattering and this is then a safety issue.</p>
<p>At this point, I do not know what other material that I could use in this motor other than using glass. The benefit of glass is it can take a lot of heat and it is also an electical insulator. This motor will get hot from the friction of wires rotating on wires and also depending on how many amps are run through the wires. I am thinking that this motor can only be run for short periods of time, perhaps for about two minutes or so, and it will then need to be shut off for a short time so the copper wires can cool down.</p>
<p>I am hoping that if someone here on Electrical Engineering.SE agrees that using tempered glass is not a good material to use for this type of motor, that he/she will suggest a different material to use instead of the tempered glass.</p>
<p>Would tempered glass be a good material to use within this simple axial flux permanent magnet motor?</p>
| Would tempered glass be a good material to use within this simple axial flux permanent magnet motor? | 2024-03-02T00:33:43.930 |
704540 | |digital-logic|integrated-circuit|debounce| | <p>As evidenced byboth your circuit and the reference circuit on page 6 of the datasheet, the IC already has internal pullups - the buttons just need to pull an input down, and no external pullup is provided.</p>
<p>According to the datasheet, the internal pullup current (with the switch closed) is between 25 and 200 uA, with a typical value of 120 uA.</p>
<p>As a result, it's fine to leave the inputs unconnected - the pullup will pull the input high without much power dissipation. If you're concerned about significant noise making it onto these pins, you may consider an external pullup for both used and unused pins (since used pins whose switches aren't pressed are also floating)</p>
| <p>I am using a LS19-s switch debouncing IC, and the datasheet does not specify what to do with unused inputs. I know for CMOS chips it standard to ground unused inputs and for TTL chips the unused inputs should be pulled high. However, the chips I am working with do not specify if it is CMOS or TTL based. Thanks in advance for any help.</p>
<p>The link to the datasheet: <a href="https://logiswitch.com/wp-content/uploads/LS10-Series-ICs-Technical-Details.pdf" rel="nofollow noreferrer">LS19-S datasheet</a></p>
<p>Below is the a portion of the circuit I am talking about:
<a href="https://i.stack.imgur.com/eo0ft.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/eo0ft.png" alt="circuit with the LS19-S with unused inputs" /></a></p>
| LS19-S, what to do with unused inputs> | 2024-03-02T01:28:56.927 |
704551 | |amplifier|digital-logic|low-voltage|datalogger| | <p>For one or two channels, what you described would be called a sound card. Your sample rate is anything but high! So, that seems like a solved problem. Laptop, microphone input, standard WAV recording program, done. Noise figures of audio equipment is quite nice, and I don't think you mean "minimal" where you write "minimal", or else we need to talk about impossible to avoid quantum noise in cryogenically cooled solid state electronics...</p>
<p>Your high channel count however makes this system pretty complicated, even theoretically, because now you have to keep a lot of sample clocks in lockstep. This is probably the point where you start building smaller modules that you can feed from the same clock source and plug them together, allowing them to multiplex their data onto a single data bus so that a sufficiently capable PC can record them onto an array of SSDs. Your SD card idea is cute, but betrayed you haven't even done back-of-envelope calculations: at 30 kS/s, 200 channels, you get 6 MS/s. At a sample depth of 16 bit (audio equipment usually nominally does 24, so this is already a concession), that's 96 Mb/s <em>sustained</em> write rate. SD cards don't do that for multiple seconds, let alone an hour. (By the way, that hour is about 40 GB worth of data.)</p>
<p>So, your question on "a modern component" is a bit off to a bad start: nothing you're doing here needs anything modern - this rate is just low, and millivolts aren't challenging. But it needs something well-designed, large-scale, so it's not a problem of finding the right component, but the right design.</p>
<p>If recommend opening a new question post that describes what you want to do in actual detail (no shortcuts, describe it, don't try to generate before you know what can and can't be abstracted!), and asks for a design approach. Selection of components comes way, way later in the design process then where you currently are!</p>
| <p>I'm trying to find modern components for a design that would be able to record millivolt range samples at a high sampling rate (~30 kHz) for ~1 hr interval. Key components I can think of thus far are digitizer, amplifier, some type of write circuit (SD card?). Importantly, are there any solutions that might be able to provide a high channel count ~1 - 200 channels? What considerations should I keep in mind recording from such low voltages with minimal noise?</p>
| Millivolt logger with high sampling rate | 2024-03-02T06:39:40.347 |
704556 | |led|generator| | <p>What you're looking at are called <em>nominal</em> ratings. "Nominal" means "in name only", or more accurately in an electronics context, it means the numbers that are on the data sheet or name plate; the numbers the part is designed for.</p>
<p>You don't <em>have</em> to use the part at those numbers.</p>
<p>A 6 volt motor is designed to be run at 6 volts. However, no law of physics stops you from plugging in 3 volts. It will run slower. No law of physics stops you from plugging in 9 volts. It will run a faster, and wear out sooner (still not for a long time), and it might overheat a little. No law of physics stops you from plugging in 48 volts. It will probably spin very fast, make some sparks inside it, then catch fire and you'll have to blow the fire out and buy a new motor.</p>
<hr />
<p>When you use it as a generator, the reverse applies. You can spin it faster than normal and get more volts. You can spin it slower than normal and get less volts. It even works in both directions. If you connect something that limits the voltage, once the voltage tries to go above that, it will increase the current instead, putting a drag on the generator and making it harder to turn.</p>
<p>If you have a plain LED without a resistor in it, the LED acts mostly like a voltage limiter. Once the voltage tries to go above the LED's forward voltage (about 3 volts for blue or white, 1.5-2 volts for other colours) the current will start flowing through the LED, holding the voltage down and putting a drag on the generator. If you try hard enough you can still make the voltage get up to 6 volts, but probably by that point, the LED's already burned out from too much current.</p>
<p>If the LED has a resistor, the same thing will happen but the resistor will 'absorb' some voltage making a 'softer' curve - less extra current flows when the voltage increases, making it easier to turn the generator faster, and the excess power will be spent in the resistor. Blue and white LEDs also have higher internal resistance than other colours and behave a bit like this.</p>
| <p>We are tasked to do a generator with LED for our project. We were given this <a href="https://www.youtube.com/watch?v=osZ49tzKmks&pp=ygUOZWFzeSBnZW5lcmF0b3I%3D" rel="nofollow noreferrer">video</a> as a guide.</p>
<p>I am planning to buy a 6 V DC motor to power a 3.3 V LED. Is that okay? Although I have read somewhere that as long as I spin the motor slowly it would be okay, I just want to make sure.</p>
| Using a 6 V DC motor for a 3.3 V LED | 2024-03-02T09:51:20.417 |
704564 | |mosfet|switches|rectifier|windturbine| | <p>You don't say how much is required to dump (is the inverter ever inoperative while the turbine is at nominal speed? is it ever overspeed?), so I will assume the total given. You can adjust values as needed if this is not the case.</p>
<p>6kW at 500V is 12A. 500V / 12A = 41.667Ω. You will need a sizable resistor (or array thereof) to dissipate this, rated 6kW in total, obviously.</p>
<p>The value can be lower, to provide a higher maximum dissipation capacity, and PWM used to achieve a higher average value as needed. Values from say 20 to 40Ω would seem reasonable here.</p>
<p>I'm also assuming nothing will mind ripple on the DC link, so that a PWM solution is acceptable.</p>
<p>The missing variables are the acceptable change in voltage (ripple peak-to-peak), frequency, and the value of that capacitor there. I will assume frequency near or above mains, and ripple ca. 10%.</p>
<p>I've previously built a worked example of such a circuit, for ballasting a 24V (nominal) supply to 29V at up to 2kW input. Schematic: <a href="https://www.seventransistorlabs.com/Images/ShuntBallast.pdf" rel="nofollow noreferrer">https://www.seventransistorlabs.com/Images/ShuntBallast.pdf</a> <br />
(disclosure: links to my website)</p>
<p><a href="https://i.stack.imgur.com/TQ0h2.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/TQ0h2.png" alt="enter image description here" /></a></p>
<p>In this case, I used an enable switch, and common TL431 voltage reference as comparator. In your case, this can most likely be wired always-on, and either a low-voltage or auxilary supply used to power it, or a lower current (TLVH431, etc.) model used to save current consumption while deriving supply directly from the 500V rail.</p>
<p>R1 supplies bias current to IC1 and Q2, regulated by a zener D1. These can be replaced with a high-voltage regulator, transistor follower or cascode to minimize excess current draw and increase compliance range, or an aux. supply can be used directly, as mentioned.</p>
<p>As shown, maximum current consumption is about 5mA, set by R5 and R9. A little extra is drawn due to gate charge, which is reduced by choice of low operating frequency, and gate drive peaks are supplied from C4. To reduce bias current, a complementary emitter follower (replace D2 with an NPN) might be used to amplify Q2's pull-up current, and a low-current TL431 can be chosen, allowing larger values for R2 and R5.</p>
<p>For a max. 500V supply, assuming a 1mA 2.5V TL431, you would need R1 < 490kΩ, R8 < 20k, R5 < (V<sub>CC</sub> - V<sub>BE</sub> - 2V) / (1mA), and R9 depends on required drive strength.</p>
<p>R4, R7 and R8 determine the rising and falling threshold voltages. Notice, when inactive, R7 is in series with R9, and this equivalent is in parallel with R8. This divides with R4, and the divider voltage must equal 2.5V when the input equals the 500V rising threshold. R4 and R8 will dominate, so that R4/R8 ≈ (500V - 2.5V) / (2.5V), but R8 will be slightly larger, or R4 slightly smaller, to account for the loading effect of R7 + R9. The falling threshold is determined by R7's effect upon the divider: we choose a value such that, for gate-on voltage applied to the resistor, the threshold drops by the hysteresis band, 10% or 50V, or 0.25V at the divider node. (Notice we can consider R4 and R8 in parallel, as a Thevenin equivalent, for these purposes.)</p>
<p>MOSFET choice and switching frequency determines gate drive requirements. Presumably, one would like to avoid a costly heatsink here, so choosing transistors for a modest power dissipation, say 20W (enough to require a small to medium heatsink, or chassis mounting, but no particularly special considerations beyond that), seems prudent. Based on conduction loss alone, at 12A, this is 0.14Ω max R<sub>DS(on)</sub>, and a rating over 600V should be used. 600-750V transistors are cheap and plentiful, though cutting the rating a little close (more on that in a bit). Examples include Infineon IPP60R099P7XKSA1, Vishay SIHG105N60EF-GE3, etc. Typical parts have gate charge in the ballpark of 40-100nC.</p>
<p>Switching frequency is controlled by link capacitance. In my example, an overcharged or disconnected battery can be assumed a fairly high impedance, and local capacitance can be assumed to dominate; the source can be assumed high impedance as well, worst-case a current source. Therefore, local capacitors were added, which also reduce ripple current throughout my battery system. We can assume the capacitors charge linearly while the dump is inactive, and discharge exponentially while active. In the small ripple approximation, the discharge can be assumed linear as well, and we have:</p>
<p><span class="math-container">$$ F_\text{sw} = \frac{I_\text{src}}{C \, \Delta V } \left( 1 - \frac{I_\text{src} R_\text{L}}{V_\text{max}} \right) $$</span></p>
<p>If we choose this as a couple kHz, and use a middling to low value load resistor, we have a minimum C around 60µF.</p>
<p>Likely, an inverter needs more for multiple reasons (generator or mains-frequency ripple handling, ripple current rating, to reduce dissipation, etc.), so this isn't a problem, and a lower F<sub>sw</sub> can be expected.</p>
<p>Suppose C = 1mF and R<sub>L</sub> = 20Ω; we can also choose a lower ΔV say 20V. We then expect F<sub>sw</sub> around 300Hz.</p>
<p>The gate switching speed should be fast enough to keep switching losses acceptably low, while not causing problems with nearby circuitry -- the resistors and wiring will be quite large, and hard-switching into them would be an EMI nightmare for nearby circuitry. For a first guess, we use the triangular approximation:</p>
<p><span class="math-container">$$ P_\text{sw} = 0.5 V_\text{off} I_\text{on} t_\text{sw} F_\text{sw} $$</span></p>
<p>where t<sub>sw</sub> is the total commutation time (rising plus falling).</p>
<p>Real MOSFETs have extremely nonlinear C<sub>oss</sub> (that is, dependent on V<sub>DS</sub>), in such a way that switching losses tend to be reduced significantly (but can also be many times more, in hard-switched half-bridge for example), relative to this calculation -- hence just a first guess. If we say 10W of switching loss, we have t<sub>sw</sub> < 11µs, very reasonable.</p>
<p>Gate current is <span class="math-container">\$I_G = \frac{Q_G}{t_\text{sw}}\$</span>, and for typ. 100nC and 10µs, we need 10mA. Probably boosting this to 100mA would be safe, without inviting EMI issues, and such currents are easily obtained from general-purpose transistors like MMBT3904/6, BC847/857, etc.</p>
<p>The gate resistor R3 and R6 values are noncritical; choose values comparable to gate drive speed, i.e. V<sub>GS(on)</sub> / I<sub>G(pk)</sub>, particularly when parallel transistors are used. (It sounds like this probably won't be required here; in my case, paralleling was convenient both to respect ratings of the transistors I had on hand, and to wire the resistors separately (which were also on hand) in case I wanted to do anything with the circuit at a later time.) So, 10-100Ω will be fine.</p>
<p>In contrast, I know from experience, transistors of this rating can switch quite quickly indeed, even with fairly large gate resistances; C<sub>oss</sub> and C<sub>rss</sub> drop so sharply above 20V or so, that Miller effect is nearly obviated. I would actually recommend considering / testing out, some added impedance, such as an R+C snubber between drain and gate. Typical values might be 22-100pF and 1kΩ. This ballasts the otherwise nonlinear capacitance, setting a maximum drain rate-of-change (dV/dt) while increasing Q<sub>G</sub> modestly.</p>
<p>Finally, some transient protection is likely desirable. The resistors will be wirewound type, having noticeable inductance (10s µH perhaps). MOSFETs of this type are not rated for repetitive avalanche, so it must be handled externally. Probably, turn-off time can't be made quite slow enough to dissipate this power reliably as channel power (which is a safe route for dissipation, at least in short (~µs) bursts as here; avalanche current is dissipated differently, in a way which gradually damages the device), so a TVS clamp diode as shown is effective mitigation.</p>
<p>If the resistors plus wiring amount to say 10µH total, the peak energy is (10µH)(12A)^2 / 2 or 720µJ, repeating every 300Hz, or about 0.2W. Even a small TVS will dissipate this handily; likely a somewhat larger type will be chosen for a sharper knee, or other reasons (transient voltages on this rail have not been mentioned; direct lightning strike of a windmill I suppose might be a motivating concern, to this end). Such voltages are not usually available, but series connections are perfectly suitable, and <a href="https://www.littelfuse.com/media?resourcetype=datasheets&itemid=37388813-0d6d-4329-969b-1aa8b7614ac1&filename=littelfuse_tvs_diode_smcj_datasheet.pdf" rel="nofollow noreferrer">SMCJ160A</a> × 3 might be a candidate. Downside: the clamping voltage would be over 777V, too far into the MOSFET rating to be comfortable. I would suggest choosing a higher rated device, then.</p>
<p>A larger TVS, just to further confine the peak voltage, or a MOV to reduce cost (at expense of higher peak voltage), or an RC or RCD snubber, are also options.</p>
<hr />
<p>Regarding MOSFET type and position, no requirements for low-side load were indicated, so there is no benefit to high-side gate drive, or a P-channel MOSFET. P-ch devices of suitable ratings are also few and far between, and perform quite poorly in comparison (not poorly enough it would be a problem here, but more to explain their general scarcity). (Specifically, the dynamic figure-of-merit is about 2.5 times poorer for P-ch than N, more or less a direct consequence of electron vs. hole mobility in Si.)</p>
<p>Probably, a practical design requires basic or reinforced type insulation from the chassis for safety or reliability purposes, and a captive element such as a load resistor can be freely wired either way; we prefer low side, then, to use a common-ground control/drive circuit.</p>
<p>A microcontroller is not required, either; nor would it be recommended, for reliability reasons.</p>
<p>Reliability diversion:</p>
<p>Proving the correctness of software, let alone of unknown or poorly documented (IC) hardware, is arbitrarily difficult; proving the correctness of analog circuitry -- though it may seem complicated or unfamiliar to some practitioners, is however far more tractable.</p>
<p>A simple function such as this, is easily realized from simple hardware -- transistors and simple ICs. They are cheap and readily available, well understood, and can be obtained in high-reliability and traceable versions as well, if one really needs it (e.g. MIL spec, aerospace, life support, etc.).</p>
<p>If needed, a digital input, or monitor output, could be added to the circuit; Q2 basically serves as a high-voltage logic inverter with <code>'1'</code> or <code>'Z'</code> output (and <code>'L'</code> state provided by R9), and logic functions (mask/enable, force-on, etc.) could be added with CD4000 series logic, or by using additional BJTs (MML ("Mickey Mouse Logic"), as Horowitz and Hill put it). A monitor output can easily be added by tapping R9 into a divider for logic-level (say 3.3 or 5V) output; a current sense shunt resistor could also be added under the transistor(s) for monitoring the load resistor.</p>
<p>More broadly speaking: I'm a strong proponent of the hands-off approach to digital control. Make a robust, responsive, but otherwise fairly dumb, analog circuit to control the nuts-and-bolts of the power switching system -- indeed, the dumber it is, the easier it is to design and verify, through inspection, simulation and testing. But only so dumb to a point: it must handle all foreseeable operating conditions and failure modes, and save enough time for the digital control to respond to them. Meanwhile, the digital control can be arbitrarily complex, while taking the time to prepare results -- which can be as straightforward as DAC outputs for voltage or current operating points at very modest sample rates (10kS/s, say?), plus some logic pins to direct machine state. It may be an old archetype (digital/hybrid systems dating back to the '70s and even earlier, simply didn't have CPUs at all, that could run more than a few MHz, let alone produce accurate timings or manipulate high sample-rate data streams by themselves!), but simplicity is a strength</p>
<p>It is, of course, possible to build a direct digital control circuit -- but it is exponentially more difficult to guarantee, or prove, operation. Most of the time, it's trivially impossible, simply because the devices aren't well enough documented by the manufacturer. Even when the logic diagram is under user control (e.g. FPGA), confirming and proving that design is a big challenge, let alone when CPU caches and concurrent threading get involved in the software case.</p>
<p>Not that this function requires complicated software, or anything -- but the problem isn't software complexity, it's the existence of software at all, and the unknown platform it's running on. You can only be as confident in the function and reliability of the overall system, as its weakest link -- and, at least personally speaking, I'm nowhere near a good enough coder to feel comfortable doing such a thing. (For reference -- not that it really means anything just to say so -- I would consider myself experienced at C. I probably have an average bug rate (to the extent one can imagine such a measuring that). The main thing is I'm rather slow at development. Hardware is more my specialty.) I have done a few power controls in software at this point, but I don't make a habit of it.</p>
<p>Anyway; perhaps these points are already well known and understood, and I'm preaching to the choir (excellent!). If not, perhaps there are other places in the project where such warnings might be profitably applied? Or, perhaps the project is too far along development to make such sweeping changes, in which case, this can still serve to guide the next project that comes along. Whatever the case, best of luck!</p>
| <p>I am currently designing an AC-DC rectifier for a 6 kW small-scale wind turbine. As part of this setup, I intend to integrate a dump load resistor to regulate overvoltage. When the DC voltage reaches 500 V, a switching mechanism will activate to safeguard the inverter and allow the dump load to dissipate excess energy.</p>
<p>My plan involves employing a MOSFET-based switching system. However, I'm uncertain about the optimal circuit design for this task. My initial approach is to utilize a microcontroller to control a low-power MOSFET, which in turn will drive a high-power MOSFET using pulse-width modulation (PWM). Despite this, I'm encountering confusion regarding the most suitable circuitry configuration, particularly regarding N-type versus P-type MOSFETs, loading on the high side or low side. (The peak current is expected to be 20 A.)</p>
<p>To illustrate, I have included a simple block diagram for reference.</p>
<p><a href="https://i.stack.imgur.com/nXEVi.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/nXEVi.png" alt="Line Diagam" /></a></p>
| MOSFET Driving for a Dump Load Resistor within a wind turbine | 2024-03-02T12:00:37.273 |
704590 | |motor|wiring| | <blockquote>
<p>... or could I just connect it to mains through a breaker and on/off switch?</p>
</blockquote>
<p>Nope. Sorry.</p>
<p>If it were an induction motor then there would be a slight chance you could get it to run with a separate start capacitor, although there's a much better chance that it'd overheat or it would never generate enough power.</p>
<p>Unless the label is lying to you, however, it's a permanent magnet motor. That means that even if you had 3-phase power to apply to it, it would just buzz and then overheat. The <em>reason</em> that synchronous motors are called that is because the applied voltage needs to be in phase with the physical position of the shaft, plus or minus a few tens of degrees.</p>
<blockquote>
<p>Given that the motor operated with variable speed and forward/reverse when in the washing machine, would I need to acquire a VFD ... ?</p>
</blockquote>
<p>You need to use a driver that's specifically designed for that, or a similar motor. Basically, that's a giant version of the brushless motors that are found in today's radio control planes and drones. It needs an electronic speed control that is designed for that type of motor.</p>
<p><em>Usually</em> if you buy a box that calls itself a "VFD" it'll be specifically designed for an induction motor -- while the electronics in a VFD would be perfectly suited for driving a motor like that, the software that determines how to drive the motor given how it's acting would be incorrect, and would probably just get confused and shut the whole thing down.</p>
| <p>I salvaged this motor from a washing machine with a view to using it to power a bench sander in my workshop.</p>
<p>There are three wires red,white and blue in addition to the green/yellow ground wire.</p>
<p>Given that the motor operated with variable speed and forward/reverse when in the washing machine, would I need to acquire a VFD or could I just connect it to mains through a breaker and on/off switch?</p>
<p><a href="https://i.stack.imgur.com/x9PYl.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/x9PYl.jpg" alt="enter image description here" /></a></p>
| How do I wire a permanent magnet synchronous motor? | 2024-03-02T16:39:50.027 |
704591 | |electromagnetism| | <p>Funny: I actually designed the B12 unit above. The wire diameter/ turns/resistance is a function of geometry/heat dissipation/ voltage. With a given geometry, you only have so much coil space and so much heat dissipation ability, that determines the power, and then it is basically ohms law to get the resistance in the coil that will fit and only generate that amount of heat in watts. As the voltage goes up, the resistance and turns go up but the watts (and amp turns stay about the same. So you get the same force out/ watt</p>
| <p>In videos like <a href="https://www.youtube.com/watch?v=mdZo_keUoEs" rel="noreferrer">this one</a> by electroboom, people make electromagnets with itty bitty wires. It seems the intuition is more turns, greater magnetic field. But I'm not so sure about that.</p>
<p>Suppose we have some annealed copper wire at 20°C. (I used <a href="https://www.omnicalculator.com/physics/wire-resistance" rel="noreferrer">this</a> site to calculate the resistances). With wire at 1/8th of an inch and 1 foot long, the resistance is 0.6583 mΩ. If we halve the diameter, then the cross sectional area is divided by 4, the length increases by 4 times (quadrupling the number of turns), and the resistance increases 4 times per foot and 16 times over all, and is now 10.533 mΩ.</p>
<p>The magnetic field near a wire is given by <span class="math-container">\$B=\mu_0I/2\pi R\$</span> (where R is the distance from the wire, not the resistance.) In the case with 1/8th inch wire, the current will be 16 times larger, but will have 4 times fewer turns. The end result is that the magnetic field is 4 times greater with the thicker wire.</p>
<p>So why do people use thin wire? Is it always best to maximize number of turns and minimize wire diameter (within other engineering constraints)? Is it always best to maximize wire diameter and minimize turns? Or is this a case where we're trying to match the resistance in the inductor to something else (such as the internal resistance of the power supply, or the resistance in the rest of the circuit), and if so, what? What design considerations dictate the wire diameter?</p>
| Why do electromagnets have itty bitty wires? | 2024-03-02T16:48:08.110 |
704597 | |power-supply|inverter|high-voltage|vacuum-tube|ccfl| | <p>The chances are low.</p>
<p>CCFL inverters provide around 800 V AC sine wave, so you would need a HV rectifier with fast, low capacitance diodes and end up with an even higher DC voltage.</p>
<p>Most inverter circuits include some current measurement to verify the correct function of the backlight or they act as regulated AC current source. The inverter just stops if the current is inconsistent. It is very difficult to stay in the accepted current range with such a tube as load.</p>
<p>It is not possible to feed such a CCFL module with PWM, except some very simple unregulated modules containing just two transistors as active components.</p>
<p>I don't think you need 100 mA to drive an EM 84, the anode would become really hot at 29 W, but I will test this.</p>
| <p>I would like to build a circuit that has a magic eye in it. That needs ~290V. I was wondering if I can/should use a CCFL inverter (salvaged from an old laptop) to generate that voltage, maybe driving it with an LM2576 so that it doesn't produce the usual ~600V. Are there any advantages or disadvantages of this method, if it is at all possible?</p>
| Can I use a laptop backlight inverter as a tube power supply? | 2024-03-02T17:21:30.223 |
704600 | |digital-logic|floating-point|computer-arithmetic| | <p>If the shift amount is greater than the width of the mantissa (24 bits), then the mantissa of the smaller number becomes completely irrelevant and can be simply zero'd out. That what the AND-OR logic is determining.</p>
<p>This allows the barrel shifter to be smaller, since it only needs to handle 24 cases rather than the full 256 cases.</p>
<p>This would have been a lot more obvious if the Verilog had been written as</p>
<pre class="lang-vhdl prettyprint-override"><code> always_comb
if (shamt >= 24)
shmant = 24'b0;
else
shmant = shiftedval;
</code></pre>
<p>which synthesizes to exactly the same logic as the original code.</p>
| <p>My textbook (Harris and Harris, <em>Digital Design and Computer Architecture</em>) asks us to design a simplified (in that only positive numbers be considered, with NaN and infinities ignored) FP adder block. They provide the following schematic as a solution which I generally follow, except for the Shift Mantissa block:</p>
<p><a href="https://i.stack.imgur.com/Ktl31.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/Ktl31.png" alt="enter image description here" /></a>
It is the final MUX in the Shift Mantissa block (select signal generated by the AND-OR sequence) which I don't understand.</p>
<p>This is certainly not an error as they give the following Verilog for that block:</p>
<pre><code>module shiftmant(input logic alessb,
input logic [23:0] manta, mantb,
input logic [7:0] shamt,
output logic [23:0] shmant);
logic [23:0] shiftedval;
assign shiftedval = alessb ?
(manta >> shamt) : (mantb >> shamt);
always_comb
if (shamt[7] | shamt[6] | shamt[5] |
(shamt[4] & shamt[3]))
shmant = 24'b0;
else
shmant = shiftedval;
endmodule
</code></pre>
<p>What is the purpose of this final <code>always_comb</code> block (which corresponds to that final MUX I mentioned above)? Why doesn't our initial shift take care of everything, why do we need the extra logic? I've gone back over the algorithm for FP addition and don't see what this bit of hardware corresponds to.</p>
| Why is this extra MUX here when shifting mantissa as part of a FP add? | 2024-03-02T17:36:44.247 |
704603 | |inverter|solar-energy| | <p>I'm answering both your question and Dave Tweed's comment, so I'll start with some useful details because not all countries manage PV in the same way...</p>
<ul>
<li><p>You have a low power grid tied solar installation (say 2 kWp)</p>
</li>
<li><p>You have a heater using 4kW with low duty cycle.</p>
</li>
</ul>
<p>Presumably your utility meter does not count backwards, or counts energy imported from and exported to the grid in two different bins with different prices, one of them being potentially zero. For example in France you can give a few kW to the grid, the meter will count your score in the "export" tab, but it's not substracted from your bill unless you have a special contract. If you do not, it's useless. If you do, the price you sell that power back to the grid is "meh not worth it".</p>
<p>In your case, which is usual:</p>
<ul>
<li><p>When the heater is on, the meter sees (4kW load - 2kW solar) = 2kW import, which it bills</p>
</li>
<li><p>When the heater is off, the meter sees 2kW solar = 2kW export, which it does not refund</p>
</li>
</ul>
<p>So you still pay for 50% of the energy to heat that resistor even though you produce enough to not pay anything, because of duty cycle and accounting subtleties.</p>
<p>Anyway. Like everyone else who has PV now you want a solar router/diverter!</p>
<p><strong>TODO: google "DIY solar diverter" for a ton of projects.</strong></p>
<p>If you use a triac, say with a duty cycle of 50%, the following will happen:</p>
<ul>
<li>Your inverter will be absolutely fine and won't notice anything special.</li>
</ul>
<p>If you use a grid tied inverter, your load current does not go through the inverter. Instead, the inverter monitors grid voltage, synchronizes to it, and injects sinewave <strong>current</strong> into the grid. The triac dimmer may make the voltage waveform a bit uglier, but that won't bother the inverter.</p>
<p>If your inverter is linked to a smartmeter, it will see the house is drawing more power due to the heater, and will attempt to produce more power (if available from solar panels).</p>
<ul>
<li>The utility meter will notice power flows in "export" direction when the triac dimmer is off, and in the "import" direction when the triac dimmer is on.</li>
</ul>
<p>Residential utility meters usually bill active power only. This means they have to count the total energy used per period and bill that. During a period, power may flow in both directions, but only the total amount of energy transferred during a period counts.</p>
<p>Current meter chipsets (I read the datasheets) do not distinguish solar plus a triac dimmed load, or a big reactive load with a terrible power factor, like a motor. The energy metering chip just computes <span class="math-container">\$ \int v(t) i(t) \$</span> and does not care about the rest.</p>
<p>So it will work fine.</p>
<p>The only consequences are:</p>
<ol>
<li><p>Every time it switches, the triac will inject a high frequency noise spike into the grid, which may manifest as buzzing in your hifi. Please look up "Triac noise suppression", you will need an inductor for this, easy to DIY, you will need a very large iron powder core.</p>
</li>
<li><p>The distorted current waveform will create harmonics. This is a bit rude towards the grid, but you most likely won't be billed for it. If your grid connection has high resistance, this will manifest as harmonics on your voltage, which means your motors may act as loudspeakers and emit weird buzz/growl sounds.</p>
</li>
</ol>
<p>The triac solution is nice because you can control it easily: measure power exported by the house, and adjust the phase angle so all the power that would be exported to the grid is used by the heating element instead.</p>
<p>The "civilized" solution is to use a pure sine wave dimmer ; these are usually more expensive than the amount they will save on your electricity bill. Fronius sells one for 1k€ for example.</p>
<p>There are other solutions, for example if your 4kW heating element is actually a three phase resistor, you can rewire the three resistors in series so it will use much less power. The thermostat will do its job so it will simply heat for a longer time, for the same end result, but it will use more power from solar.</p>
<p><strong>Under no circumstances should you ever use diodes to reduce power used by a load</strong> as that will draw DC current, which may saturate the utility transformer.</p>
<p>However the real answer is: install more solar panels.</p>
| <p>I'm trying to optimise the usage of a residential solar system. It's a fairly low capacity system connected to the grid with an inverter (no batteries). There is also resistive heater which uses, on average, 1-2kW, which is less than the capacity of the solar panels/inverter. However, it simply uses a thermostat to switch on and off, and the heating element is 3-4kW, significantly above the solar system's capacity (duty cycle is approximately 50%).</p>
<p>My question is, is it ok to use a triac style dimmer to limit the power going to the heater? I know it shouldn't be a problem for the heater, since it's just resistive, but what about the inverter? Will it be ok since it's a grid-tie inverter? Will it basically result in high frequency spikes of mains usage, or will the capacitors in the inverter even this out and make it work as intended? Is the EMI likely to be a problem due to switching a high power device?</p>
<p>If it's relevant, the max/min power factor of the inverter is ±0.8. If you could include in your answer why the power factor is/isn't relevant that would be great, because I always struggle a bit with power factors. Also note I am not proposing building a dimmer myself, just buying one.</p>
| Disadvantages of using triac to control inverter load | 2024-03-02T17:49:56.373 |
704612 | |circuit-analysis|linearity| | <blockquote>
<p>I believe this is typically done by recognizing that a circuit is composed entirely of linear components.</p>
</blockquote>
<p>This is the definition of linearity. Not the electronic component definition of linearity, but the mathematical definition of linearity from which the electronic component version of linearity is derived. Recall Fourier transforms which are linear and that for a linear system, the component frequencies in the output can only contain frequencies that were present in the input. No new frequencies can be introduced in a linear system. The concept of superposition is directly derived from this in that if your circuit only has linear components, you can analyze each source, whether it be DC, or AC of varying frequencies separately and then add them all up in the end. That's literally how the Fourier transform works.</p>
<p>One somewhat more rigourous but still intuitive way to look at it is to take two lines of different slopes that run over the same span of X coordinates. Then add them up and find what the slope of the new line is. It's the slope of the new line is just the sum of the slopes of the first two lines. Now instead of thinking of superimposing small segments of line, extend to derivatives which are is the slope at any point on a curve (or rather the slope of the tangent to any point on a curve).</p>
<p>That's why ideal capacitors and inductors are linear components:</p>
<p><span class="math-container">\$V_L = L\frac{di}{dt}\$</span></p>
<p><span class="math-container">\$I_c = C\frac{dv}{dt}\$</span></p>
<p>Even though they have that little derivative term.</p>
| <p>We can use the concept of linear circuits to simplify circuit analysis (e.g. superposition & Thevinin’s theorem.) In order to do this, we need a simple way to identify linear circuits.</p>
<p>I believe this is typically done by recognizing that a circuit is composed entirely of linear components. It makes intuitive sense that linear components would create linear circuits, but is there a more rigorous explanation as to why?</p>
<p>Even if all components are linear (obey additivity and homogeneity,) it’s not clear to me why every input/output relationship in that circuit has to share this property.</p>
| Why do linear components make linear circuits? | 2024-03-02T19:34:48.230 |
704617 | |1-wire|uuids| | <p>The datasheet for <a href="https://www.analog.com/media/en/technical-documentation/data-sheets/DS2502-E48.pdf" rel="nofollow noreferrer">DS2502-E48 48-Bit Node Address Chip</a> contains the following in the features:</p>
<blockquote>
<p>Provides valid MAC-48/EUI-48 Ethernet address</p>
</blockquote>
<p>And the following the description:</p>
<blockquote>
<p>The first 32 bytes of the DS2502-E48’s EPROM memory contain a globally unique 48-bit node address and are <strong>write-protected</strong>.</p>
</blockquote>
<p>And shows the following breakdown of the data structure:
<a href="https://i.stack.imgur.com/NR2HX.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/NR2HX.png" alt="enter image description here" /></a></p>
<p>I.e. if you connect a DS2502-E48 it should come with a unique ID.</p>
| <p>(I previously posted this question on the Arduino SE, but it was downvoted as "not Arduino enough", so I post it here in the hope it will be better received.)</p>
<p>If I wanted to make my own 1wire device, I would need to give it a "globally unique" 48-bit identifier.</p>
<p>How are these identifiers generated? How can we guarantee no identifier conflicts with another brand's devices?</p>
| How are "unique IDs" generated for 1wire devices? | 2024-03-02T20:06:27.457 |
704627 | |power-supply|voltage|pcb| | <blockquote>
<p>Is this necessity to increase the voltage normal</p>
</blockquote>
<p>It depends what we consider normal :)</p>
<p>It has nothing to do with aging, but everything to do with the age in which these systems were designed, and with market pressures involved.</p>
<p>Back then, getting a PCB prototype manufactured was an expensive proposition and it usually took weeks to get the boards back, unless you wanted to pay rush fees. The PCB design software was rudimentary, and some layout was done by hand and thus was very time consuming. And multi-layer PCBs cost significantly more than two-layer, so for most people 2-layer was "the PCB" and they couldn't afford more layers than that.</p>
<p>Laying out a board, getting the prototype, realizing that "oops, the voltages are low, we have to beef up some traces" is not a big deal today most of the time, but back then it was just not done unless you sat on an excessively large pile of money. Getting heavier copper load on the board was an option that would save on the cost of redoing the films and the NC drill tape, but that increased unit costs, so was avoided. If there was a way to get something to work cheaply, even if not very elegantly, it was the way chosen.</p>
<p>A designer without a good mentor would do a 2-layer design and not draw out and subsequently calculate the power distribution tree. The power and ground traces compete for space with signal traces, and usually leave something to be desired. And unless you calculate voltage drops, you are blissfully unaware of what's going on.</p>
<p>Thus, the voltages at various points in the circuit had values lower than they otherwise would, if the designer had time and wherewithal to design the board to work with 5.0V±10% at the power input terminals.</p>
<p>Today, you can set up a finite element voltage drop model of a PCB layout in an hour or less, and just see exactly what the voltages will be. It is not particularly complicated if you've done it once, and in expensive EDA software this functionality is just a few clicks away. Open source tools also support it but it's a pain to initially set up.</p>
<p>Back then, you could do these sorts of simulations in big engineering departments, or if you were an engineer who "graduated" such a department and had good contacts for computing resources for rent by the hour to run the simulations. I had personally seen a Gerber to SPICE DC model extraction workflow in the 80s, done on a low budget, but that took a rather capable engineer, who had to know that such workflows even existed. There was no Internet to look things up - a trivial task today, but back then such experience was not googleable, you had to have either had done it, or been active in continuing engineering education and met people who did it, or had good mentors.</p>
<p>A lot of the arcade and similar "prosumer" systems made by media companies were marginal engineering done under extreme time constraints, with budgets that people in larger engineering firms would laugh at.</p>
<blockquote>
<p>If you got a perfectly working PCB from the factory years ago, would it have needed the same increased voltage requirement?</p>
</blockquote>
<p>Sure. It was designed-in, whether intentionally or not. But most of the time, it was just a "shrug, crank up the power supply and ship it".</p>
<blockquote>
<p>Sometimes I still have to remind myself that increasing the voltage at the power supply is not the only way to get enough voltage at all the chips</p>
</blockquote>
<p>It was common for the boards were under-designed in terms of power distribution (too much resistance), but there was no time and/or money to fix that. In arcade business, if it was good enough to ship, it got shipped, and sometimes each unit had to be tweaked individually. Design engineers were asked to make it work, and as soon as they said "I got it to work but..." they were cut off and the production got their grubby hands on it :) If you read the stories, some of the products were released with no money left. They shipped or project was canceled, and if it was The Project that was to keep the company alive, then the company went bankrupt.</p>
| <p>I have a few projects restoring old arcade video game PCBs. Some of the boards need a slightly higher voltage (~5V DC) to power all the components (esp. the ROMs furthest away from the power connector (e.g. JAMMA input). This requirement is often mentioned by other restorers.</p>
<p>Is this necessity to increase the voltage normal or is it related to components and/or age related resistance? I.e. if you got a perfectly working PCB from the factory years ago, would it have needed the same increased voltage requirement?</p>
| Is it normal for a PCB to create a voltage drop at the power supply | 2024-03-02T23:15:15.413 |
704632 | |mosfet|p-channel|depletion-mode| | <p>I don't know of any, current or past.</p>
<p>For low currents you might be able to use a P-channel JFET, for example, the MMBFJ175LT1G has an Idss between 7 and 60mA with Vds = 15V.</p>
| <p>I cannot find any P-Channel Depletion mode mosfets at any supplier.</p>
<p>I see this question from 10+ years ago: <a href="https://electronics.stackexchange.com/questions/32528/where-are-the-depletion-pmos-transistors">Where are the depletion PMOS transistors?</a></p>
<p>But has ANYONE been able to source a P-Channel Depletion mode mosfet for a power application (>2A current), or for that matter, any power or small signal depletion mode p-channel mosfets?</p>
<p>I am not looking for advice on WHERE to buy them, just advice on whether or not I should include them in a design. No point including them if they are not made by ANYONE.</p>
| Has anyone ever obtained a P-Channel Depletion mode power mosfet? | 2024-03-03T00:28:39.507 |
704636 | |circuit-analysis|control-system|transfer-function|passive-networks| | <p>Well, your transfer function is given by:</p>
<p><span class="math-container">$$\mathscr{H}\left(\text{s}\right):=\frac{\displaystyle\text{V}_\text{o}\left(\text{s}\right)}{\displaystyle\text{V}_\text{i}\left(\text{s}\right)}=\frac{\displaystyle\frac{\displaystyle1}{\displaystyle\text{sC}}}{\displaystyle\frac{\displaystyle1}{\displaystyle\text{sC}}+\left(\text{R}\space\text{||}\space\text{sL}\right)}=\frac{\displaystyle\frac{\displaystyle1}{\displaystyle\text{sC}}}{\displaystyle\frac{\displaystyle1}{\displaystyle\text{sC}}+\frac{\displaystyle\text{R}\cdot\text{sL}}{\displaystyle\text{R}+\text{sL}}}=\frac{\displaystyle\text{R}+\text{sL}}{\displaystyle\text{R}+\text{sL}+\text{s}^2\text{CLR}}\tag1$$</span></p>
<p>Where <span class="math-container">\$\displaystyle\alpha\space\text{||}\space\beta:=\frac{\displaystyle\alpha\beta}{\displaystyle\alpha+\beta}\$</span>.</p>
| <p>i'm trying to figure this out, but i'm still confused. Can anyone help me? Thank you</p>
<p><a href="https://i.stack.imgur.com/h8ZEx.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/h8ZEx.png" alt="enter image description here" /></a></p>
<p>This is what i've done. Am i in the correct path?
<a href="https://i.stack.imgur.com/qY0Ee.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/qY0Ee.jpg" alt="enter image description here" /></a></p>
| Consider the following circuit system (RLC Circuit, R and L parallel then series with C), please determine the transfer function | 2024-03-03T02:33:16.690 |
704644 | |antenna|ham-radio|propagation| | <p>Local background noise is hardly ever the same. Even <em>not-so-local</em> background noise is often different, since each station in a long-distance contact "sees" a different part of the ionosphere. I know you asked to discount that, but it's worth keeping in mind as a real-world source of "one way propagation". Sometimes, if you're lucky, you can use it to your advantage by getting on at a time when the band is open in the direction you want to work, but closed in the direction that provides the most QRM.</p>
<p>And advanced stations frequently have dedicated receiving antennas, which are designed for high directivity even at the cost of very low efficiency (negative absolute gain).</p>
<p>Aside from that, reciprocity works pretty well. There is a widely-reported phenomenon where the ionosphere is actually non-reciprocal, treating eastbound paths differently from westbound paths. The explanation, which is a bit over my head, involves the Earth's magnetic field, and it happens mainly at MF frequencies (160m and the AM broadcast band) because those are similar to the electron gyrofrequency in the ionosphere.</p>
| <p>The Antenna Theory book by Balanis goes through a theoretical explanation. In my real antennas (I'm an Amateur Radio operator) there are other things like transmission lines and matching circuits. I'd think that as long as this extra stuff stays linear between high transmission power and low reception power, reciprocity still holds.</p>
<p>My main antenna is a 1/4 wavelength vertical (monopole), but the ground plane is far from perfect - it is a combination of the earth and radial wires, and there are a lot of inefficiencies in the ground plane half. Still, it seems reciprocity could hold.</p>
<p>In Amateur radio, there are often contacts between stations with massive tower mounted high-gain antennas and stations with little omni-directional antennas (as mine). But assuming the rest of the stations are the same (including transmit power and local background noise) it seems that, due to reciprocity, both operators should hear (more or less) the same receive signal quality. How accurate is this?</p>
| How accurate is the antenna reciprocity principle in practice? | 2024-03-03T05:50:55.643 |
704649 | |motor-controller|triac|dimming| | <p>The purpose of D1, D2 and R3 is to reset the capacitor if it never triggers. This reduces the "snap-on" effect in cheap dimmers where there is a hysteresis in the behavior at low settings. D2 is forward biased by C1.</p>
<p>The reset only occurs on alternate half cycles, but that's enough.</p>
| <p>Here is a typical TRIAC SBS trigger circuit to control a resistive load. This example is from the <a href="https://www.alldatasheet.com/datasheet-pdf/pdf/1756487/POWEREX/BS08A.html" rel="nofollow noreferrer">BS08A datasheet</a> but there are plenty of others.</p>
<p>What is the purpose of the D1,D2 and R3? It appears to me that there should be never current from the SBS gate through D2. (That is, D2 is never forward biased.)</p>
<p><a href="https://i.stack.imgur.com/HVTiC.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/HVTiC.png" alt="enter image description here" /></a></p>
| What is the purpose of diodes on the gate of a silicon bilateral switch (SBS) TRIAC trigger circuit | 2024-03-03T08:56:31.733 |
704652 | |electrolytic-capacitor| | <p>Possibility? Yes.</p>
<p>Aluminium electrolytic capacitors do not necessarily just blow up if you get the polarity wrong. They might and what happens depends on the circuit they are in.</p>
<p>There are a lot of examples of products where capacitors are mounted with incorrect polarity and the circuit still works. For example some models of Commodore Amiga CD32.</p>
<p>I am sure I have read an application note from a capacitor manufacturer what happens if a capacitor is mounted incorrectly. There was some estimate on the effect of various degraded parameters such as loss of capacitance and higher ESR, so at least those capacitors could handle usage at wrong polarity at least once. Unfortunately, I could not find which application note it was and from which manufacturer.</p>
<p>The point just is that the capacitor starts to conduct a lot of current in reverse after it is being subjected to reverse voltage around 1..2V, so depending on the conditions, such as available current limiting, the process might happen too fast and too much pressure builds up and the capacitor vents or explodes, but if it happens slowly enough, the oxide layer starts to form and the capacitor will be somewhat degraded but will work with the new polarity.</p>
| <h2>Introduction</h2>
<p>First of all, this question more like theorical rather than practical as I want to test my understanding about Aluminum Electrolytic Capacitor, which I will later called Al-Cap for short.</p>
<h2>Preliminary knowledge</h2>
<h3>Manufacturing process.</h3>
<p>First of all, le begin with manufacturing process of Al-Cap. the processes consist of following procedure.</p>
<ol>
<li>Roughten and preformed anode (positive) foil to increse surface area and pre made oxide layer.</li>
<li>Cutting anode and cathode foil into desire size.</li>
<li>winding, rolling anode, paper separator and cathode in to the cylindral form.</li>
<li>Impregnation, apply electrolyte using vaccuum.</li>
<li>Sealing, prevent electrolyte from leakage.</li>
<li>Post forming or aging, apply voltage (CC/CV manner) with high temperature to heal imperfect dielectric layer or non forming area like curring edge. Improving self discharge rate.</li>
</ol>
<p>Note: This website from capacitor manufacturer provide grate detail about these process <a href="https://www.chemi-con.co.jp/en/faq/detail.php?id=29AMNMV" rel="nofollow noreferrer">website</a>,</p>
<h3>Theory or operation.</h3>
<p>The anode foil and electrolyte act as electrode or plate like ordinary capacitor and oxide layer on anode foil act like dielectric. Combinding fact that the oxide layer is relatively thin and surface area of anode in increse by about factor of 200 due to rought surface, the Al-cap provide high capacitance campare to ordinary one. we need to use liquid electrode for cathode to match up the surface of anode. the cathode foil act like electrical contact point to electrolyte.</p>
<h3>Reversing polarity</h3>
<p>One of trade-off of electrolytic cap is that it polarize cap. inverse polarity can cause damage to the capacitor by dissolve anode's oxide layer lead to decreasing of break down voltage. As the resistance of electrolyte is very low, the capacitor become short circuit which product a lot of heat and pressure due to gas production from electrolysis reaction.</p>
<h2>My assumption</h2>
<p>As we can reforming capacitor which means there are oxide in the electrolyte. so if replicate those reforming condition by apply high temp and control voltage and current of inverse polarity supply. we can remove oxide layer from anode and form them on cathod instead then the capacitor is successfully reverese polarity.</p>
<h2>Question</h2>
<p>Q1. Is that possible to do so with my assumption procedure.
Q2. If there are better or possible method please recommend and explain.</p>
<h2>Expectation benefit</h2>
<p>Whether this is possible or not, I hope this discussion raise awareness and understanding of operating principle of aluminum electrolytic capacitor. Personally I used to remembering that don't connect them in reverse polarity or majic smoke will appear but I never wonder why that such thing happen.</p>
| Possibillity of reverse polarity of Aluminum Electrolytic Capacitor | 2024-03-03T09:27:03.987 |
704657 | |transformer|high-voltage|isolation|specifications| | <blockquote>
<p><em>I would like to make sure that I am referencing the proper
specification for voltage isolation capability between primary and
secondary side of transformer.</em></p>
</blockquote>
<p>and</p>
<blockquote>
<p><em>Where is the continuous isolation voltage limit in this spec?</em></p>
</blockquote>
<p>The working isolation voltage is there on the front page of the <a href="https://www.bourns.com/docs/product-datasheets/hctsm8.pdf" rel="nofollow noreferrer">data sheet</a>: -</p>
<p><a href="https://i.stack.imgur.com/qjpzk.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/qjpzk.png" alt="enter image description here" /></a></p>
<blockquote>
<p><em>what's the highest peak or rms voltage I can apply across each
inductor</em></p>
</blockquote>
<p>The transformer is designed to interface with the <a href="https://www.ti.com/lit/ds/symlink/sn6505b.pdf?ts=1709398625726&ref_url=https%253A%252F%252Fwww.ti.com%252Fsitesearch%252Fen-us%252Fdocs%252Funiversalsearch.tsp%253FlangPref%253Den-US%2526searchTerm%253Dsn6505%2526nr%253D379" rel="nofollow noreferrer">SN6505B</a>. It runs at 420 kHz and an upper limit of supply voltage of 5 volts DC. Thus, the SN6505B limits the maximum voltage across the full primary to 10 volts p-p. Note that the E*T limit for the transformer is 11 <span class="math-container">\$\text{volt}\cdot\mu s\$</span> and that ties in nicely with the SN6505B's limits (when you do the math).</p>
| <p>Could you please help me understanding this transformer spec?</p>
<p>I am planning to use <a href="https://www.bourns.com/docs/product-datasheets/hctsm8.pdf" rel="nofollow noreferrer">HCTSM80101AAL</a> transformer and I would like to make sure that I am referencing the proper specification for voltage isolation capability between primary and secondary side of transformer. Hi-Pot test is just to use as a guideline for short transient as I understand.</p>
<p>Where is the continuous isolation voltage limit in this spec?</p>
<p>I believe level of insulation spec is about working voltage level on each leg (i.e., primary 1-2 or 2-3 or secondary 6-5 or 6-4). Please correct me if I my understanding is not correct.</p>
| Isolation voltage spec in transformer | 2024-03-03T10:09:10.260 |
704661 | |mosfet|diodes|buck| | <blockquote>
<p>However, the power dissipation on the MOSFET is R(dson)×I^2, while on the diode it is VF×I. So, when the current is high enough, will the efficiency of synchronous buck converters be lower?</p>
</blockquote>
<p>Yes, of course, and that also applies to all resistive losses (inductor DCR, cap ESR, MOSFETs, etc).</p>
<p>Due to that squared I², above a certain level of current you need multiple phases. For example, consider a PC motherboard VRM which converts 12V into Vcore, which is in the vicinity of 1V with huge current (sometimes more than 100A). Here's a <a href="https://overclocking.com/vous-voulez-en-savoir-plus-sur-les-vrm/" rel="nofollow noreferrer">picture</a>.</p>
<p><a href="https://i.stack.imgur.com/fpjcA.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/fpjcA.jpg" alt="enter image description here" /></a></p>
<p>You can see 16 dual MOSFETs and 16 inductors, for a 16 phase buck converter. A bit overkill.</p>
<p>If you use N phases, current in each phase is divided by N, thus conduction losses in each phase (RI²) are divided by N². There are N phases, so total loss is only divided by N compared to a one phase design using the same parts. This is not usually true, because the lower current in each phase allows faster MOSFETs with higher RdsON which increases conduction losses but reduces switching losses. It also spreads the heat over a much larger area which makes cooling easier.</p>
<p>On the other end of voltage, high voltage MOSFETs have pretty high ESR usually, so in this case a diode may have lower losses, or perhaps some other switch type (IGBT...)</p>
| <p>For I know, the reason why the efficiency of synchronous buck converters is higher than that regular ones is because they use a MOSFET instead of a freewheeling diode, and MOSFETs generally have higher efficiency than diodes. However, the power dissipation on the MOSFET is R(dson)×I^2, while on the diode it is VF×I. So, when the current is high enough, will the efficiency of synchronous buck converters be lower?</p>
<p>The above content is my own thinking. Does such a situation exist in reality?</p>
| Is the synchronous buck converter suitable for high current applications? | 2024-03-03T10:52:42.850 |
704681 | |diodes|protection|circuit-protection|esd|tvs| | <p>The maximum clamping voltage is the voltage across the TVS when it is carrying the specified current. Consider <a href="https://www.littelfuse.com/media?resourcetype=datasheets&itemid=2b2f4a8c-2e81-4894-8d41-3d748bb79e68&filename=littelfuse-tvs-diode-5-0smdj-datasheet" rel="nofollow noreferrer">this</a> Littelfuse TVS datasheet as an example:</p>
<p><a href="https://i.stack.imgur.com/rtNrn.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/rtNrn.png" alt="![enter image description here" /></a></p>
<p>The breakdown voltage of the bottom model number is somewhere between 36.7 and 40.6V when it is conducting a small amount of current (1mA). The Reverse standoff voltage is specified as 33V so it is suitable for a 32V maximum input.</p>
<p>The clamping voltage is specified as 53.3V (maximum) at 93.9A (test current) so if you need your circuit to withstand that particular current <strong>you must design your circuit to withstand a momentary voltage of at least 53.3V</strong>.</p>
<p>For currents between 1mA and 93.9A the voltage can be more than 40.6V but less than 53.3V. So a 40V device would be inadequately protected and a 60V rating would be prudent. Things like resistors that can withstand brief overloads may be okay or may need to be beefed up. Capacitors and ICs, less so. You may be able to find typical voltage vs. current curves for the particular TVS device and you would need to adjust those to estimate the worst-case voltage if it's not at the specific guaranteed test values of current.</p>
<p>You don't have a free choice of voltages, once you know your the maximum operating voltage (which determines your standoff voltage requirement), the clamping voltage will be considerably higher for a given series of TVS devices.</p>
| <p>This is the following specification of my circuit
Vin 8V to 32V
The breakdown voltage should be 33V of TVS
I don't know what clamping voltage means please simplify it for me</p>
<p>What should be Vc?</p>
| How to select ESD TVS diode? | 2024-03-03T13:02:38.510 |
704691 | |launchpad| | <p><a href="https://www.ti.com/tool/download/SLAC437" rel="noreferrer">https://www.ti.com/tool/download/SLAC437</a> on the TI website contains a link to download the MSP-EXP430G2 Hardware Design Files.</p>
<p>Inside the download there is a MSP-EXP430G2_LaunchPad_BOM.xls spreadsheet containing the Bill Of Materials (BOM) for the launchpad. This has the row with:</p>
<div class="s-table-container"><table class="s-table">
<thead>
<tr>
<th>Pos.</th>
<th>Ref Des</th>
<th>Number per board</th>
<th>Description</th>
<th>DigiKey part #</th>
</tr>
</thead>
<tbody>
<tr>
<td>43</td>
<td>S1, S2</td>
<td>2</td>
<td>Push Button</td>
<td>P12225STB-ND </td>
</tr>
</tbody>
</table></div>
<p><a href="https://www.digikey.be/en/products/detail/panasonic-electronic-components/EVQ-21505R/160362" rel="noreferrer">P12225STB-ND</a> is the DigiKey page the switch part number.</p>
<p>The switch is <code>EVQ-21505R</code> manufactured by <em>Panasonic Electronic Components</em>. The description is:</p>
<blockquote>
<p>SWITCH TACTILE SPST-NO 0.02A 15V</p>
</blockquote>
<p>The EVQ-21505R is reported as obsolete, and can't seem to find the datasheet on the Panasonic website.</p>
<p><a href="https://www.mouser.co.uk/datasheet/2/315/PANAS38662_1-2560512.pdf" rel="noreferrer">Light Touch Switches/EVQ2</a> is the datasheet found on the Mouser website and lists following electrical parameters:
<a href="https://i.stack.imgur.com/NAv2S.png" rel="noreferrer"><img src="https://i.stack.imgur.com/NAv2S.png" alt="enter image description here" /></a></p>
| <p>What are the current and voltage maximum and minimum limits for the push buttons / tactile switches on the TI Launchpad MSP-EXP430G2 ?
Also, what is the manufacturer number for this component ? I have not found any datasheet that details this information.</p>
| Texas Instrument Launchpad MSP-EXP430G2 tactile switch / push button power specifications and manufacturer number | 2024-03-03T14:57:07.613 |
704693 | |mosfet|circuit-design| | <blockquote>
<p><em>Edit: Attempt 2:</em></p>
</blockquote>
<p>The 2nd attempt will also not do anything useful.</p>
<p>It's really not as easy as you think. You have to detect that the right side voltage is greater than the left side voltage (and deactivate the MOSFET) and, you have to use a P-channel MOSFET.</p>
<p>If the left side voltage is greater, current will flow how you want it to. If the right side voltage is greater, you must deactivate the p-channel MOSFET.</p>
| <p>I am designing a circuit board that has two possible ways to receive 20V DC power, either from USB power delivery, or from a screw terminal.</p>
<p>When the board is powered via USB power delivery (<code>USB_PD_20V</code>), I would like the screw terminal to act as an output for the 20V.</p>
<p>However, when the power input is from the screw terminal, I would like to prevent any reverse current/polarity on <code>USB_PD_20V</code> (Note: <code>USB_PD_20V</code> will be at 0V when inactive).</p>
<ol>
<li>Is the schematic below suitable?</li>
<li>Is the resistor pointless?</li>
</ol>
<p>(I am using the Zener diode to prevent V<sub>GS(max)</sub> from being exceeded)
<a href="https://i.stack.imgur.com/c4GKV.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/c4GKV.png" alt="Schematic" /></a></p>
<p>Thank you!</p>
<p>Edit:
Attempt 2:
<a href="https://i.stack.imgur.com/yBG9t.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/yBG9t.png" alt="Attempt 2" /></a></p>
| N Channel MOSFET for reverse polarity protection for circuit with two possible voltage sources | 2024-03-03T15:11:55.173 |
704699 | |capacitor|current|resistors|phase| | <p>In you question you suggest the water flow metaphor - a question that has not been addressed by others. The water metaphor fails as explanation in this and some other aspects, I feel.</p>
<p>First, a bit off the topic, the current flow in a conductor is indeed in phase first with magnetism (always) and with the resistance - which involves Jule-an current "wasting" or "burning" and production of heat - the consumption of power.</p>
<p>Again, a bit of the topic (but quite analogously to some relations quoted by others0 you probably know that if the circuit has self induction e = L di/dt there is an induced back emf which lags behind current by 90 degrees - and according to Charles Steinmetz being an action/reaction phenomenon causes a wattless drop of potential (reactance component - which added in quadrature with resistance - by pythagorean theorem equals impedence).</p>
<p>Watless - in other words - means energy is used to build magnetic field and restored by collapse of the magnetic field that again induces current - all in the proper phase relation. Here inductance (L) a coefficient of energy storage by lines of magnetic force. It is actually quite analogous to "C" which is a coefficient of energy storage by static lines of force - at least it was described so by old 19th century electricians.</p>
<p>With the issue of the capacitor,inside it, as some other posts rightly indicate (there is a displacement "flux" established in the dielectric and as 19th century electricians knew it could be made "denser" with different dielectric permittivities). Nowadays we talk about charge on plates but Steinmetz complains about this thinking, in 19th century they thought that it was dielectric which was polarized (confirming the fact experimentally). SO.... If there were no inductance and/ or resistance in the entirety of the circuit at the moment of closing the switch the capacitor would have charge instantly. Remember the old experiments in electrostatics? - the condition of tension (difference of potential) influenced by bringing a charged ball to the insulated conductor and disappearing as it was withdrawn- if you were clever you could actually have a two part joint conductor and separate the minus and plus charges if you avoided discharging to ground). The "charge" induced by this (as they called) "influence" would be permanently left on both sides unless discharged to ground.</p>
<p>Quoting Steinmetz in the case of alternate current "current flows into the condenser during rising EMF and out of the condenser during decreasing EMF" that is current "consumed by the condenser leads the impressed EMF 90 degrees" - reference "Theoretical Elements of Electrical Engineering" by Charles Proteus Steinmetz page 56.</p>
<p>The following are copies of pages 17 and 18 from Theory and Calculation of Transient Electric Phenomenta by Steinmetz.</p>
<p><a href="https://i.stack.imgur.com/8SqL5.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/8SqL5.png" alt="Steinmetz on capacitors" /></a></p>
<p><a href="https://i.stack.imgur.com/4srYU.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/4srYU.png" alt="Steinmetz on capacitors2 " /></a></p>
<p>PS. For consistency, above Steinmetz does talk about charges on plates but in earlier publications he quietly complains, a lot of terms and ideas have changed since first publications within a decade or so .... (that's also confirmed by one Eric Dollard)</p>
| <p>Imagine an AC source in series with an RC circuit.</p>
<p>In <a href="https://youtu.be/JBi4nI1WeqY?si=APTpXFjoWx-eXN4M" rel="noreferrer">this video</a>, the instructor claims current will be 90 degrees behind voltage inside the capacitor but not inside the resistor or the whole circuit. If that's true, I don't understand.</p>
<p>I am imagining current as a flow of water inside a tube and I cannot see how the water can be delayed on a point in the tube and not delayed 1 inch later.</p>
<p>Can someone please explain?</p>
| How can current phase shift be 90 degrees behind voltage just "inside the capacitor" on an RC series circuit but be in phase in the resistor? | 2024-03-03T16:10:22.793 |
704709 | |mosfet|motor-controller|stepper-motor| | <p>It is for reverse voltage protection (hooking up the battery or power supply backwards across the input supply terminals). The zener diode and resistor are to stop the MOSFET gate-source junction from blowing due to overvoltage. This is because the MOSFET gate-source voltage limit is lower than the source-drain voltage limit. It would not be required if the expected voltage supply was lower than the MOSFET gate-source voltage rating.</p>
<p>It does <em>almost</em> the same thing as a diode except for two points:</p>
<ul>
<li>The diode has a higher forward voltage drop and thus more losses</li>
<li>The diode will protect against a reverse-current protection whereas the PMOS, as shown. This is also known as a "load-dump" and is when the load pushes current back towards the input power supply. This can happen if the motor starts generating, or if the input power supply is something like a bench supply but is unplugged from the AC wall outlet with all the bench supply's internal component still connected to the motor driver.</li>
</ul>
<p>The simply reason why the simple PMOS circuit as shown does not protect a reverse-current scenario but a diode will is that the PMOS circuit relies on the voltage across the input terminals to operate whereas a diode does not. A diode only relies on the voltage across the terminals of the diode itself to operate.</p>
<p>Overcoming this flaw requires additional circuitry for the PMOS circuit.</p>
<p>See this for more information for more details on the operation, behaviour, and solutions:
<a href="https://electronics.stackexchange.com/questions/480237/nmos-reverse-current-protection/480238#480238">nmos reverse current protection</a></p>
| <p><a href="https://i.stack.imgur.com/vDdfb.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/vDdfb.png" alt="enter image description here" /></a></p>
<p>I was looking at the schematic for the <a href="https://www.pololu.com/product/3730/" rel="nofollow noreferrer">Pololu High-Power Stepper Motor Driver 36v4
</a> and can make sense of most of it, except for this portion of the circuit. What is the purpose of the MOSFET and diode? Why can't I just connect my power supply at VM instead of VIN?</p>
<p>The circuit worked fine at a microstep of 1/2, but once I set it to 1/32, Q1 blew immediately. I think the first step of debugging this is understanding the function of the MOSFET in the circuit.</p>
| What is the purpose of the this part of a motor controller circuit? | 2024-03-03T18:29:06.003 |
704726 | |current|amplifier|circuit-design|common-collector| | <p>There are two effects in play here, both are related to the quiescent current in Q1.</p>
<p>With the bias resistor values being used there is only about 1mA quiescent current flowing through R3. That will mean that the effective output resistance is going to be about 25 ohms (25/Ie - the simulation shows it as being 29 ohms) Since your load is only 10 ohms the gain will be about 10/(10 + 25) = 0.28.</p>
<p>A second problem is that it will be easily overloaded with a maximum output of only a few millivolts. The maximum current that can be sent to the load is the change between the transistor being cutoff (ie zero current) and twice the quiescent current when the signal goes positive.</p>
<p>In this case it would be 2mA peak to peak.</p>
<p>2mA into the 10 ohm load only results in 20mV peak to peak or about 6mV RMS.</p>
<p>The quiescent current through the transistor needs to be greatly increased by reducing the value of R1. For example changing R1 to 10k would result in about 6V across R3 giving about 30mA quiescent current. This would reduce the output resistance to a couple of ohms, improving the gain, and increase the maximum output level.</p>
<p>With 30mA through R3 the load current could increase to 60mA pk-pk giving 600mV pk-pk or about 200mV RMS output.</p>
| <p>Common collector amplifier gives a good current gain and there is a link on internet, that makes the calculation for current amplification automatically.</p>
<p><a href="http://www.vk2zay.net/calculators/transistors/commonCollector.php" rel="nofollow noreferrer">http://www.vk2zay.net/calculators/transistors/commonCollector.php</a></p>
<p>I tested it in LTSpice. I placed the components into circuit with given inputs. Unfortunately, it seems to be working
wrong somehow, because the expected output voltage should be at the value nearly the input voltage, but it is much less than the input. I did something wrong. Could you help me to build and place the needed components into the common collector amplifier?</p>
<p>Why is not the circuit below working from LTSpice? Why does it give much less voltage than expected? How can I correct this?</p>
<p><a href="https://i.stack.imgur.com/wLRSj.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/wLRSj.png" alt="circuit" /></a></p>
<p>Edit:</p>
<p>Below a working example. It works as expected.</p>
<pre><code>frequency 3.3 MHz
Input voltage: 1V
Output voltage : ~1V
</code></pre>
<p>It has a current gain about 20.</p>
<p><a href="https://i.stack.imgur.com/oc1im.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/oc1im.png" alt="working" /></a></p>
| Common collector amplifier gives much less voltage than expected? | 2024-03-03T20:40:25.553 |
704736 | |led|led-driver|led-strip|constant-current|led-matrix| | <blockquote>
<p>I will put 100 LEDs in tha panel and want to control brightness of each led separately via ESP32 PWM.</p>
</blockquote>
<p>100x LEDs, with 3x colors each comes to 300 PWM channels. You're not going to find many low-end parts that can drive that many PWM channels concurrently, and certainly no ESP32s!</p>
<hr />
<p>Your preferred route will likely depend on how frequently you need (want) to update the display, and how concerned you are about color balance, power budgets, run-time complexity, and CPU time on the ESP32.</p>
<p>The most simple option is one or more strings of "<em>addressable RGB LEDs</em>" - each string requires only one or two signals from the controller, and each LED has a controller built in to deal with the communication, chaining, and maintain the set brightness.</p>
<p>Another option is to employ a number of separate parts, each dedicated to a small group of LEDs... "<em>LED drivers</em>" exist with up to 32 channels from a single package (possibly more), meaning that you'd require around 10x of these (or more, depending on channel count per IC). They'll likely also maintain the set brightness, will probably have lower quiescent current, and may have some nicer features (e.g: higher / configurable PWM frequency).</p>
<p>You're heading into "<em>LED matrix</em>" territory here, the schematics for which are widely available. They typically split up the R/G/B channels into serial streams (using shift registers), addressing the LEDs in a column / row scheme... they shift out the bits (on/off) for each column of the display's full width, and then strobe a single line, repeating this very quickly to "<em>scan</em>" the whole display, forever - keeping the display "<em>refreshed</em>" relies on doing it fast enough (i.e: persistence of vision) and requires constantly flashing each row one at a time, no stopping. Achieving 8 colors (Black, Red, Green, Blue, Yellow, Cyan, Magneta, White) is fairly straightforward, but as the bit-depth increases, so does the work involved, along with the signalling speeds.</p>
| <p>i want to make RGB LEDs panel using <a href="https://www.lcsc.com/product-detail/Light-Emitting-Diodes-LED_TCWIN-TC5050RGBF08-3CJH-P35C_C784539.html" rel="nofollow noreferrer">https://www.lcsc.com/product-detail/Light-Emitting-Diodes-LED_TCWIN-TC5050RGBF08-3CJH-P35C_C784539.html</a> RGB LEDs. I will put 100 LEDs in tha panel and want to control brightness of each led separately via ESP32 PWM. I am unable to figure out what sort of led driver should i use or how to connect leds in such a way that i can control brightness of each led separately.</p>
| RGB LEDs indvidual brightness control | 2024-03-03T21:43:21.000 |
704756 | |operational-amplifier|piezo-buzzer|cutoff-frequency| | <p>Your value for C3 is way too large. It is the main reason that signals at <em>most</em> frequencies are being attenuated. It is only when the impedances of C2 and C3 become comparable, that fluctuations can begin to appear at their junction. That condition only occurs at high frequency.</p>
<p>C3 is supposed to represent the combined parasitic capacitance of elements such as op-amp inputs and cabling. For instance:</p>
<ul>
<li><p>The TL081's inputs will have a couple of picofarads between them.</p>
</li>
<li><p>1m of twisted wire pair used to connect the transducer will have something like 50pF capacitance between the conductors.</p>
</li>
<li><p>PCB traces will add a few more picofarads</p>
</li>
</ul>
<p>At a guess, I would expect C3 to be anywhere between 20pF and 200pF, not 100nF.</p>
| <p>I have a piezoelectric element, which acts as an accelerometer. Attached to it is a charge amplifier, built based on <a href="https://www.ti.com/lit/an/sloa033a/sloa033a.pdf" rel="nofollow noreferrer">this documentation</a>. The op-amp is the <a href="https://www.ti.com/product/TL081#tech-docs" rel="nofollow noreferrer">TL081</a>.</p>
<p><a href="https://i.stack.imgur.com/7Oegl.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/7Oegl.png" alt="enter image description here" /></a></p>
<p>The PZT element is simulated based on a model, where C2 is the transducer capacitance, R3 is the leakage resistance, and C3 is the stray capacitance.</p>
<p>Per my understanding, the charge amplifier should provide a "gain" of -C2/C1, as Vo = -Qp/Cf, and Qp is correlated to the transducer capacitance C2. I am producing an AC signal with offset of 0V, so I will simplify this gain to C2/C1.</p>
<p><a href="https://i.stack.imgur.com/sIjUs.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/sIjUs.png" alt="enter image description here" /></a></p>
<p>My issue is that the charge amplifier does not amplify on most lower frequencies. According to my understanding, the cutoff frequency should be (220<em>10^-12</em>1.2<em>10^6</em>2pi)^-1 = 602Hz. However, I am experiencing no amplification until at least 3.5kHz. The peak is still 6kHz.</p>
<p>This is currently being built on an op-amp.</p>
<p>Things I've tried:</p>
<ul>
<li>Swapping the Op-amp. No effect.</li>
<li>Changing the PZT element into a sine wave generator to simulate the sine wave. No effect.</li>
<li>Swapping the parts to confirm the value of the resistor/capacitor 220pF and 1.2MOhm. No change.</li>
</ul>
<p>Please let me know if more information is required.</p>
| Charge Amplifier not amplifying at most frequencies | 2024-03-04T01:58:47.003 |
704776 | |power|resistors|datasheet| | <p>The operation modes relate to the life expectancy and resistance drifts. Each mode refers to a set of operation modes and a resultant life expectancy along with a resistance change (drift). So these are "options" provided by the manufacturer for different "expectations".</p>
<p><strong>GENERAL</strong> mode, for example, refers to operation conditions such as up to 125 °C film temperature and a power dissipation of up to 270 mW for 1206-case resistors. Under these conditions, the expected life time would be 225 khrs (20+ yrs) with a resistance change (drift) of up to 0.3%.</p>
<p>If you are happy with lower life expectancy, such as up to 1000 hrs (40 days) then <strong>ADVANCED</strong> mode which corresponds to half a watt along with a permissible film temperature of up to 175°C is an option. If you check the table again, you'll see that ADVANCED mode is not available for 1210-case resistors. That's probably because the life expectancy becomes less than 1000 hrs.</p>
<p>So, basically, with different conditions, expect different "life expectancies" and "resistance drifts".</p>
| <p>The <a href="https://download.siliconexpert.com/pdfs2/2024/1/19/22/13/39/392980/vsh_/manual/tnpw_e3.pdf" rel="nofollow noreferrer">datasheet</a> refers to different operating modes for the resistor with the below note- What does it really mean?</p>
<p><strong>Note:</strong> The presented operation modes do not refer to different types of resistors, but actually show examples of different loads, that lead to different film temperatures and different achievable load-life stability (drift) of the resistance value.</p>
<p><a href="https://i.stack.imgur.com/sMcm2.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/sMcm2.png" alt="enter image description here" /></a></p>
| What is meant by operation mode of a resistor? | 2024-03-04T07:23:42.027 |
704784 | |verilog|quartus| | <p>First the obligatory statement: forget everything you know about programming. Verilog is not a programming language, but rather circuit design.</p>
<hr />
<p>With Verilog, at the very least Quartus in particular, pretty much if any part is unsigned, be that input or output, the whole thing is unsigned. It's an annoying quirk you have to live with.</p>
<p>In your case because the output is to an unsigned ternary operator, it's treating the whole calculation as unsigned - essentially <strong>casting any signed operands to unsigned</strong> before performing the operation.</p>
<p>All of you 'fixes' split the shift operation out from the ternary operator and allow the sub operation output (from the shift) to be treated as signed, thus the cast to unsigned in the ternary operator no longer affects the shift.</p>
<p>Equally you could use the much clearer and descriptive:</p>
<pre><code>signed wire [31:0] signedShift;
wire [31:0] unsignedShift;
assign signedShift = $signed(in) >>> shift_amount;
assign unsignedShift = in >> shift_amount;
assign out = signext ? signedShift : unsignedShift;
</code></pre>
<p>Remember that in Verilog, fewer lines is not more efficient, its just less descriptive.</p>
| <p>Here is the module, I want to use <code>signext</code> to determine whether it is ASR or LSR.</p>
<pre><code>module test(
input wire [31:0] in,
input wire [4:0] shift_amount,
input wire signext,
output wire [31:0] out
);
assign out = signext ? ($signed(in) >>> shift_amount) : (in >> shift_amount);
endmodule
</code></pre>
<p>However, Quartus shows <code>Warning (15610): No output dependent on input pin "signext"</code>, and RTL viewer shows it is just an LSR.</p>
<p><a href="https://i.stack.imgur.com/KCyZI.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/KCyZI.png" alt="RTL viewer: LSR" /></a></p>
<p>Add something may fix this problem, but I cannot tell why.</p>
<p><strong>fix 1</strong>: add <code>$signed()</code> to the ASR result:</p>
<pre><code>assign out = signext ? $signed($signed(in) >>> shift_amount) : (in >> shift_amount);
</code></pre>
<p><strong>fix 2</strong>: add <code>$unsigned()</code> to the ASR result:</p>
<pre><code>assign out = signext ? $unsigned($signed(in) >>> shift_amount) : (in >> shift_amount);
</code></pre>
<p><strong>fix 3</strong>: add <code>$signed()</code> to the LSR operand:</p>
<pre><code>assign out = signext ? ($signed(in) >>> shift_amount) : ($signed(in) >> shift_amount);
</code></pre>
<p><strong>fix 4</strong>: add <code>$signed()</code> to the LSR result:</p>
<pre><code>assign out = signext ? ($signed(in) >>> shift_amount) : $signed(in >> shift_amount);
</code></pre>
<p>In conclusion, I guess that the <strong>naked</strong> result of <code>($signed(in) >>> shift_amount)</code> is forced to be <code>unsigned</code> because of the other <code>unsigned</code> value, so <code>>>></code> means <code>unsigned arithmetic right shift</code> and is the same as LSR then.</p>
<p>(It's hard for a C++ programmer like me to believe that operator can be overloaded by the type of result.)</p>
<p>So, wrap the left side or change the type of the right side to <code>signed</code> may fix the problem.</p>
<p>Then I find the 5th fix.</p>
<p><strong>fix 5</strong>: add <code>{}</code> to the ASR result:</p>
<pre><code>assign out = signext ? {($signed(in) >>> shift_amount)} : (in >> shift_amount);
</code></pre>
<p>The problem is: <strong>I'm not sure why this does not work and why fixes would work, I'm just guessing and trying.</strong></p>
<p>Hope someone could tell me what is really happening, thanks.</p>
<blockquote>
<p>Quartus version:</p>
<p>Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version</p>
<p>Also happens at:</p>
<p>Quartus Prime Version 22.1std.1 Build 917 02/14/2023 SC Lite Edition</p>
</blockquote>
| (Verilog) Why $signed() and >>> operation cannot generate ASR when inside ?: operator in such case? | 2024-03-04T08:41:53.763 |
704786 | |insulation-voltage|voltage-rating| | <p>Rated Voltage Uo/U (Um)</p>
<p>Uo, phase to earth<br />
U, phase to phase<br />
Um, maximum voltage</p>
<p>The cable is intended for Uo/U but there is headroom up to Um because most systems, such as mains grid, have 10% indefinite and 20% temporary voltage swell headroom.</p>
| <p>I'm confused about voltage ratings of some special cable. Most cables for low voltage applications (<= 1kV) either have a single rating (e.g. 300V) or manufacturers give a different rating for AC and for DC.</p>
<p>However for marine cables one will find ratings like this: 0.6/1 (1.2) kV.
e.g. for this cable:
<a href="https://www.nexans.no/en/products/Ship-Marine-and-Offshore-Topside-Cables/Ship-Marine-Cables/Power---Control-cables/MPRXCX%C2%AE---27321.html" rel="nofollow noreferrer">Nexans MPRXCX</a></p>
<p>I'm rather sure this is not the rating for AC and DC, because I found other marine cables which again have separate ratings for AC and DC, however again two values for each, which makes 4 ratings in total.</p>
<p>The manufacturers don't expose any explanation on their websites, at least I couldn't find any during almost one hour of search.</p>
<p>My guess is that the two (or even three) voltages describe ratings between two conductors and between one conductor and the outer. But if so, which one is the lower and which one is the higher?</p>
<p>The one in round brackets might be a peak voltage, but I can only guess.</p>
<p>I'm pretty sure there is some sort of rule with these ratings, because most manufacturers rate marine cables like that.</p>
| Voltage rating of cables in marine applications | 2024-03-04T08:46:02.190 |
704790 | |uart|serial|emc| | <p>When something is connected, the receiver will be a high-impedance CMOS input, which behaves pretty much the same as an open end. So there is no practical difference between connected and unconnected.</p>
<p>How much you need to care about EMI depends on the board layout, the environment, and how fast the signal edges are. Anyway, to reduce EMI, you can add source termination. Assuming that the trace has a characteristic impedance of about 50 Ω, and that your driver's output impedance is lower, add a series resistor of about 22 Ω or 33 Ω directly at the TX pin.</p>
| <p>I have a PCB with a serial TX UART used for programming & logs.</p>
<p>Most of the time nothing is connected & the ~50mm TX trace is unconnected - basically an antenna.</p>
<p>Are there any best practices for reducing the EMI caused by an unconnected TX port? Is it even necessary? It's 115200bps.</p>
<p>I already have a solid ground plane underneath it.</p>
| Reducing EMI caused by unterminated serial TX line | 2024-03-04T09:46:42.333 |
704802 | |altium| | <p>In your schematic, <strong>E</strong>dit > <strong>J</strong>ump > Jump <strong>C</strong>omponent (Alt+E..J..C)</p>
<p>Type in the designator into the pop up box
<a href="https://i.stack.imgur.com/tcRuW.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/tcRuW.png" alt="enter image description here" /></a></p>
<p>If it is a multi-part component, a second box will open, where you can cycle between parts, and the schematic will jump to that part.</p>
<p><a href="https://i.stack.imgur.com/IKxzH.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/IKxzH.png" alt="enter image description here" /></a></p>
| <p>I have a large multi-sheet schematic in Altium, which uses the multi-part schematic symbol for an LS1046 CPU. This part has 15+ components, which across the multiple sheets of the schematic are hard to keep track of? How do I find a specific part of the mutli-part symbol?</p>
<p>Normally I would use the search bar in the top right, but this only contains the First of the parts (in this case U2A), and clicking on the search result brings me to a random part of the symbol (in my case, U2G).</p>
<p>Additionally, having clicked on the search result, I get green lines connecting to all the other symbol parts on the same schematic sheet - how do I get rid of these??</p>
| How to find an already placed schematic symbol in Altium schematic | 2024-03-04T12:00:09.373 |