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bshada

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electronics.stackexchange.com

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700315

|voltage|inductor|current-measurement|voltage-measurement|history|

<p>That appears to be an <a href="https://en.m.wikipedia.org/wiki/Galvanometer#Astatic_galvanometer" rel="nofollow noreferrer">astatic galvanometer</a> in the drawing of Faraday's demonstration of the law of induction.</p> <p>In an astatic galvanometer, there's a support (the two &quot;posts&quot;) from which a fine thread suspends two needles. There's a coil under the scale to drive the needles.</p>

<p>Does anyone understand the galvanometer in Faraday's experiment to the left in the picture below? How does it operate? It looks like it uses a magnet and some xy axis the needle swings over or maybe the disc spins. There is what looks like a coil of wire under the disc and unsure if that’s an inductor. Also unsure about the two posts inside the apparatus if they carry current as well.</p> <p><a href="https://i.stack.imgur.com/Nchgf.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/Nchgf.png" alt="enter image description here" /></a></p> <p>Ref <a href="https://en.wikipedia.org/wiki/Faraday%27s_law_of_induction" rel="nofollow noreferrer">link</a></p>

What type of galvanometer is in this picture?

2024-02-06T06:09:27.357

700322

|display|signal-integrity|texas-instruments|interface|hdmi|

<p>So , I figured out what was going wrong.</p> <p>In my second iteration of the PCB layout, the driver board is now operating flawlessly. I made some minor adjustments, such as adding a 90 ohm CMR filter next to the HDMI input differential pair and tuned all the differential traces to a length of 60mm with proper impedance matching.(issue was the improper routing of Diff. pair)</p>

<p>I have designed my own display driver board using a TI <a href="https://www.ti.com/lit/ds/symlink/tfp401.pdf" rel="nofollow noreferrer">TFP401PZP</a> TMDS DVI receiver/deserializer which is connected to a 24-bit, parallel RGB, 7 inch capacitive touch display with a resolution of 800x480.</p> <p>The power distribution is perfectly done to all segments. The driver board is designed on a two-layer PCB (the back layer is dedicated to only ground plane).</p> <p>Pin configurations:</p> <ul> <li>DFO = pulled down for continuous clock</li> <li>nPDO = connected to SCDT for normal operation/drivers on</li> <li>ST = pulled up for high drive strength</li> <li>PIXS = pulled down for 1 px/clk</li> <li>nSTAG = pulled high for normal simultaneous even/odd pixel output</li> <li>OCK_INV = pulled high for: latches output data on rising ODCK edge</li> </ul> <p>My findings through oscilloscope after changing another probe:</p> <ul> <li>ODCK = 34 MHz</li> <li>VSYNC = 60 Hz</li> <li>HSYNC = 31.04 kHz</li> <li>DE = 28.81 kHz (Vpp = 2.24 v)</li> </ul> <p>I also set the EDID to external EEPROM with 800x480 resolution.</p> <p>At the output I'm getting distorted video (ghost screen/pixel mismatch) with greenish horizontal lines. I've also shared the video output screen and circuit board with schematic.</p> <p>My schematic: <a href="https://i.stack.imgur.com/yflBy.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/yflBy.jpg" alt="enter image description here" /></a></p> <p><strong>The distorted video output/black screen:</strong></p> <p><a href="https://i.stack.imgur.com/D9i5J.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/D9i5J.jpg" alt="enter image description here" /></a></p> <p><strong>video output after 5 mins of display on time when ODCK, HSYNC, VSYNC disappears:</strong></p> <p><a href="https://i.stack.imgur.com/ZqxmV.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/ZqxmV.jpg" alt="enter image description here" /></a></p> <p>Any help would be greatly appreciated.</p>

TFP401PZP: Unable to get proper video output, ghost screen/distorted pixels

2024-02-06T06:44:58.500

700330

|capacitor|circuit-design|audio|

<p>The speaker can be damaged by a constant DC voltage, so the DC should be removed. The capacitor will quickly charge to the DC average of the source.</p> <p>The simulation confirms that the cap never sees a negative voltage.</p> <p><img src="https://i.stack.imgur.com/2Y1lB.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2f2Y1lB.png">simulate this circuit</a> &ndash; Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a>}</p> <p><a href="https://i.stack.imgur.com/98DDh.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/98DDh.png" alt="enter image description here" /></a></p>

<p>Looking through the <a href="https://www.ti.com/lit/gpn/tpa3123d2" rel="nofollow noreferrer">datasheet</a> for the TPA3123D2, I have noticed some confusing symbol usage and positioning. From my understanding, aluminium electrolytic capacitors can only be 'charged' on the positive terminal, while 'charging' it from the negative terminal will dissolve the oxide layer, resulting in a short circuit and subsequent failure of the capacitor. With the other capacitors in the schematic, generic film capacitors can be used (avoiding ceramic due to electromechanical vibration,) but the two 470uF capacitors (excluding PSU decoupling) are too big to be replaced with a film/polyester type capacitor.</p> <p>The notion of only 'charging' a polarized capacitor from its positive terminal holds true for the two 470uF capacitors just before the outputs, but isn't an audio signal inherently AC? Why isn't the capacitor damaged when the output reverses polarity?</p> <p>Additionally, regarding capacitor voltage ratings, should an AC VRMS(max) value be used instead of its maximum voltage rating marked on the body of the capacitor?</p> <p><a href="https://i.stack.imgur.com/5xjHK.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/5xjHK.png" alt="Application circuit of the TPA3123D2" /></a></p>

Aluminium electrolytic capacitors in an AC circuit

2024-02-06T08:18:34.373

700335

|pcb|instrumentation-amplifier|interference|fft|bnc|

<p>You are connecting &quot;an antenna&quot; to your input and, it is picking up extraneous electric fields from within your environment.</p> <p>At the very least (for this test to have valid results), you should connect a low impedance to the ends of your coaxial cable.</p> <p>Also note that the module you have purchased does not have bias-current-bleed resistors fitted on both inputs to ground and this will certainly exacerbate your experience.</p> <p>In short, you are abusing the module in ways that are not technically acceptable.</p>

<p>I bought an AD620 instrumentation amplifier module and below is the module schematic.</p> <p><a href="https://i.stack.imgur.com/XFyEF.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/XFyEF.png" alt="module schematic" /></a> Souurce - <a href="https://protosupplies.com/product/ad620-instrumentation-amplifier-module/" rel="nofollow noreferrer">https://protosupplies.com/product/ad620-instrumentation-amplifier-module/</a></p> <p>A problem shows up when I'm testing the circuit and couldnt't find what cause it.</p> <p>When only appling the <strong>Vsupply</strong> voltage and let <strong>Signal Input</strong> pin floating.</p> <p><a href="https://i.stack.imgur.com/nt1Ef.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/nt1Ef.png" alt="Configuration A" /></a></p> <p>The frequency FFT result from <strong>Signal Output</strong> pin is shown below (Configuration A).</p> <p><a href="https://i.stack.imgur.com/Ak6b5.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/Ak6b5.png" alt="Configuration A FFT" /></a></p> <p>The result is expected, a flat frequency band except DC signal (Maybe caused by Voffset of the amplifier).</p> <p>However, when I connect the &quot;BNC to minigrabber cable&quot; to <strong>Signal Input</strong> pin, and let the BNC terminal floating (Configuration B).</p> <p><a href="https://i.stack.imgur.com/67LDh.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/67LDh.png" alt="Configuration B" /></a></p> <p>The FFT from <strong>Signal Output</strong> pin is changed as shown.</p> <p><a href="https://i.stack.imgur.com/fVQ4U.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/fVQ4U.png" alt="Configuration B FFT" /></a></p> <p>There seems to be an unwanted signal into the BNC termanial and get amplified from AD620 module and the FFT band is not flat anymore.</p> <p>My questions are</p> <p>a) What cause the unwanted signal input to the AD620 module by just connecting a cable?</p> <p>b) Is there any solutions or ways to avoid this situation?</p> <p>Any suggestions would be very helpful to me!</p> <p>Thanks</p>

Unexpected signal at AD620 module output when Vsupply is on

2024-02-06T08:36:02.363

700343

|led-driver|dac|led-strip|rgb|

<p>To complement on @bobflux, if you're interested in running on 24V you should look at the WS2814. You will need to put some LEDs in series to get close to your power supply voltage (ideally 6 for 24V) to limit the voltage drop that the chip will see and then reduce it's power dissipation. I've been working on custom LED bars using those with 4 LEDs in series and a 17V power supply to reduce power dissipation in the WS2814, it's been working pretty well and efficiently.</p>

<p>I am seeking help to design a small PCB that can translate digital RGB like Neopixel to analog signals for driving high current LED RGB. I know it's a bit weird. I would like to connect to a board that I know is sending Neopixel code (WS2812.) I don't want an LED strip with WS2812, but instead a high current LED strip. I have been looking at the UCS8904 which is 16-bit LED driver.</p> <p>I would very much appriciate some help to get started. I hope the question is clear enough.</p> <p><a href="https://i.stack.imgur.com/3ETkm.png" rel="noreferrer"><img src="https://i.stack.imgur.com/3ETkm.png" alt="enter image description here" /></a></p>

RGB digital to analog converter

2024-02-06T09:26:51.870

700347

|kirchhoffs-laws|

<p>Your generalization works fine as long as you account for displacement current (current through capacitances). Of course those may flow perpendicular to a planar circuit, so you should really consider volumes rather than areas. The sum of the physical currents and displacement currents into a volume is zero.</p> <p>If you are using KCL, you are implicitly promising to account for displacement current.</p>

<p>I'm very new at learning electronics, and I came across KCL. I think I understand it, I've used it to solve problems, and it makes sense to me (it feels very much like conservation laws in mechanics, no current gets created so what comes in at a junction comes out)</p> <p>Thinking about this analogy (KCL and other conservation laws), I was wondering if there's a generalized version that goes beyond junctions to whole sections of a circuit. It would look something like this: &quot;draw any enclosed area on a circuit, which may contain other components. Look at every connection going across the boundary of this area. Add the currents on those (with different sign based on their direction) and you should get zero.</p> <p>It intuitively makes sense to me and I feel it could help me analyse bigger circuits. But I'm not sure if this generalization is actually valid, or if there are any counterexamples?</p>

Is it correct to generalize Kirchoff's current law to areas?

2024-02-06T10:06:45.300

700348

|pcb|pcb-design|emc|

<p>The best practice (IMO) is to use a copper pour for GND, with thermal spokes, and plenty of GND Vias to stitch the planes together. GND vias should be reasonably close to the pins. <a href="https://i.stack.imgur.com/rIUHF.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/rIUHF.png" alt="enter image description here" /></a></p> <p>The use of a solid copper pour is only necessary when the current is extremely high, or it's impractical to use spokes. Sometimes there's not enough room to fit spokes in, so a solid pour must be used.<br> I'd note that you can use a free calculator like saturn's to get an idea of the amount of resistance in a thermal spoke, and it really is quite small. It's only things like ESCs or high power FETs that truly call for solid pours.<p> Solid pours obviously come at the disagvantage of being very hard to solder manually. This isn't a concern when having the boards reflowed but still they make rework also very difficult. Large ammounts of copper connected directly to pins could also pose problems bu acting as a heatsink and affecting the reflow - though I dont know if there's actually much risk of this in an industrial process.<p> The manual many wires process is also just a bit of a pain. It would probably work, but I can't see a single reason to prefer it over a pour with spokes.</p>

<p>There is a mezzanine connector with many GND pins to be routed.</p> <p>I am wondering, which arrangement would be more beneficial?</p> <p>This is 6-layer PCB, red is top layer, next one is GND plane (hidden in picture)</p> <p><a href="https://i.stack.imgur.com/DQaOc.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/DQaOc.png" alt="Tracking" /></a></p> <p>Two scenarios here.</p> <p>Bottom part: individual tracks from each pin to meet in the middle and via to ground plane beneath. Top part: Copper zone with vias to connect to GND.</p> <p>Is any of these two better, or even, shall I connect each pin individually to GND? Or, expand GND area as much as possible to form massive one, embracing all GND pins if possible?</p> <p>Please consider soldering issues (thermal reliefs not existing in copper area scenario). It is going to be soldered externally, probably using machines.</p> <p>P.S. Ground plane available below, as in this picture:<br /> <a href="https://i.stack.imgur.com/JPNl3.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/JPNl3.png" alt="GndAvailable" /></a></p>

Ground tracks or area for mezzanine connector

2024-02-06T10:17:58.153

700358

|fpga|verilog|xilinx|

<p>The question refers to a look-up table, which is a ROM. These solutions apply to both RAM and ROM models.</p> <p>There are 2-3 good ways to perform ROM/RAM initialization in Vivado &amp; ISE for Verilog.</p> <p><strong>For Vivado</strong>, refer to Xilinx doc UG-901 <a href="https://docs.xilinx.com/r/en-US/ug901-vivado-synthesis/Specifying-RAM-Initial-Contents-in-the-HDL-Source-Code" rel="nofollow noreferrer">Specifying-RAM-Initial-Contents-in-the-HDL-Source-Code</a></p> <p>Two styles are shown in the guide:</p> <ol> <li>for loop</li> </ol> <pre><code>reg [DATA_WIDTH-1:0] ram [DEPTH-1:0]; integer i; initial for (i=0; i&lt;DEPTH; i=i+1) ram[i] = 0; end </code></pre> <p>2 Using an external data file</p> <p>Use the file read function in the HDL source code to load the RAM initial contents from an external data file.<br /> The external data file is an ASCII text file with any name.<br /> Each line in the external data file describes the initial content at an address position in the RAM.<br /> There must be as many lines in the external data file as there are rows in the RAM array. An insufficient number of lines is flagged.<br /> The addressable position related to a given line is defined by the direction of the primary range of the signal modeling the RAM.<br /> You can represent RAM content in either binary or hexadecimal. You cannot mix both.<br /> The external data file cannot contain any other content, such as comments.</p> <pre><code>reg [31:0] ram [0:3]; initial begin $readmemb(&quot;rams_20c.data&quot;, ram, 0, 3); end </code></pre> <p>The following external data file initializes an 4 x 32-bit RAM with binary values:</p> <pre><code>00001110110000011001111011000110 00101011001011010101001000100011 01110100010100011000011100001111 01000001010000100101001110010100 </code></pre> <p><strong>Another way to create ROMS with initialization using Vivado</strong><br /> The Vivado IP Catalog tool allows the user to launch a block memory generator to create custom ROMS <a href="https://docs.xilinx.com/v/u/en-US/blk_mem_gen_ds512" rel="nofollow noreferrer">blk_mem_gen_ds512</a> See the section with the heading 'Specifying Initial Memory Contents' where it is stated<br /> &quot;The Block Memory Generator core supports memory initialization using a memory coefficient (COE) file or the default data option in the CORE Generator GUI, or a combination of both.&quot;</p> <p><strong>Xilinx ISE</strong> has known bugs with $readmem&lt;h/b&gt;()<br /> You could use approach 1. or use the ISE Coregen tool to create the RAM or ROM and choose to create an initialization file when creating the core.</p> <p>ISE support stopped years ago; its difficult to find documentation (today, when searching for ISE docs you find are broken links pointing to the Xilinx/AMD site, it looks like they don't what users reading the old docs). I did find this guide which walks the user thru the process of creating memories (with init files) using the ISE Coregen tool. <a href="https://www.rose-hulman.edu/class/cs/archive/other-old/most_of_OLD_from_CSSE232-Fall-2011/0405b/www/Resources/In-Class%20Exercises/03%20-%20Xilinx/0405b_XilinxIntroductionPart_%204.pdf" rel="nofollow noreferrer">rose-hulman</a></p> <p><strong>Another way for ISE</strong> I found a guide for the ISE synthesis tool XST here <a href="https://acg.cis.upenn.edu/milom/cse372-Spring06/xilinx/xst.pdf" rel="nofollow noreferrer">cse372-Spring06</a> from 2006 which shows this style</p> <pre><code>reg [19:0] ram [63:0]; initial begin ram[63] = 20'h0200A; ram[62] = 20'h00300; ram[61] = 20'h08101; ram[60] = 20'h04000; ram[59] = 20'h08601; ram[58] = 20'h0233A; ... ram[2] = 20'h02341; ram[1] = 20'h08201; ram[0] = 20'h0400D; end </code></pre>

<p>I need to initialize multiple lookup tables, for which I need a 12-bit array of possibly many indexes. An example:</p> <pre><code>reg [11:0] address[1:0]; </code></pre> <p>For this, how do I initialize it with 0? For all index values? Also, I am unable to use the initial block, since it cannot be used in RTL synthesis. The purpose of this is to interface multiple lookup tables and access the values via an index through the address variable.</p>

How do I initialise an Unpacked array in Verilog?

2024-02-06T11:25:29.923

700369

|operational-amplifier|input-offset-voltage|

<p>Personally I would:</p> <ul> <li><p>Flip the whole schematic upside down so the input stage becomes NPN</p> </li> <li><p>Now the input transistors operate at low Vce, so they can be replaced with cheap low offset matched BCM847 or similar, which have matched Vbe and hFe ; for the current mirror you can use matched BCM857 too.</p> </li> <li><p>Equalize base resistance, as mentioned in the other answers.</p> </li> </ul> <p>Another option: use a low voltage low offset opamp, combined with the usual <a href="https://electronics.stackexchange.com/questions/404405/op-amp-voltage-boost-circuit-how-does-it-work">opamp booster circuit</a>, or something like this:</p> <p><a href="https://i.stack.imgur.com/w0EQO.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/w0EQO.png" alt="enter image description here" /></a></p> <p>The opamp, combined with R8, operates as a low input offset transconductance error amp. It does essentially the same thing as the input stage in the discrete amp. Then common base transistor Q1 steers this current to drive the output stage.</p> <p>The big difference is that the opamp has a single pole response, whereas the LTP it replaces does not. This gives better accuracy at low frequency, but headaches at high frequency.</p> <p>Compensation is likely to be fiddly and annoying. What compensation circuit to use depend on who's faster, the opamp or the output stage.</p> <p><strong>Episode 2</strong></p> <p>Since you said you wanted &quot;a solution that could be used by hobbyists&quot; I picked LM2904 as an opamp: it has +/-1mV offset, and it's easy to find. It's also pretty slow (1MHz gain bandwidth product). I changed the circuit to one much easier to compensate, it should be pretty robust.</p> <p><a href="https://i.stack.imgur.com/2jjO9.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/2jjO9.png" alt="enter image description here" /></a></p> <p>Since the opamp provides extra gain, the VAS transistor in the discrete opamp was no longer needed. Due to your &quot;negative only&quot; output voltage this makes a very simple circuit where the LTP collector drives the output directly. It has feedback, the negative input of this opamp is Q3's base. At &quot;high&quot; frequency (&quot;high&quot; for LM2904 is above 100kHz) feedback is through C2 so the discrete opamp acts as a unity gain voltage follower. At low frequency, C2 is out of the picture, and... there is no DC feedback from the output, instead Q3's base receives a fixed DC bias, which means low frequency gain will be very high.</p> <p>This is the gain of this discrete opamp:</p> <p><a href="https://i.stack.imgur.com/EyjII.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/EyjII.png" alt="enter image description here" /></a></p> <p>The important thing here is that the phase lag returns to near zero near the unity gain frequency of LM2904, which preserves its phase margin.</p> <p>Then the outer loop is closed through the opamp, which works at the desired gain of x16 at low frequency, and unity gain at high frequency.</p> <p>Due to this, an important feature is that the opamp is not slew rate limited during settling, so the input stage doesn't get differential heating. So it should settle slowly (a couple hundred µs) but cleanly.</p> <p>I have used Vbe multiplier Q4 for bias ; these are convenient but they need a trimmer which also acts as a self destruct device if you turn it towards too much bias. So maybe you'll want to keep the diodes, or use larger value emitter resistors.</p> <p>With the values shown this should work with other opamps with gain bandwidth in the 1-2MHz region, for example a zero drift opamp. I used SMD SOT223 versions of 2N5401/5551, TO92 will work just as well.</p> <p><strong>Faster version</strong></p> <p>Replace the opamp with a faster one, for example LM833 (10MHz GBW) and adjust C2,C3 in proportion (4.7-10pF, adjust with square wave input to get nice settling without overshoot). This makes the whole circuit 10x faster both in terms of slew rate and settling time.</p> <p>LM833 has low &quot;typical&quot; offset but the min/max and input offset current are a bit high, so in DIP you could use MCP6021, TLC070, etc, or a SO8 opamp. I don't think a SO-8 opamp (without powerpad) would be a problem for DIYers...</p>

<p>I have a design for a valve tester that previously used OPA445 op-amps to create the grid voltage - the grid circuit is just a 4.096 V I2C DAC running into the amp with a gain of -16.5, which means I can create grid voltages up to -66 V.</p> <p>The OPA445 is a rare beast because it has a maximum supply voltage of 90 V (my supplies are +8 V and -70 V) and is available in DIP rather than SMT so it is more viable for the hobbyist - but it is pretty much the only device I can use with these characteristics and it isn't cheap.</p> <p>In my latest design I have replaced the OPA445 with a simple discrete op-amp (making the build far more accessible), thus:</p> <p><img src="https://i.stack.imgur.com/XkMS9.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fXkMS9.png">simulate this circuit</a> &ndash; Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a>}</p> <p>Having assembled the PCB, it mostly seems to work OK, but an input of 0 V from the DAC (which measures as 0 V) results in an output of +0.7 V. This seems to be a systematic offset as I can increase the DAC output slightly to get the output to 0 V and its maximum output is pretty close to -66 V.</p> <p>Given that putting +0.7 V on the grid of, say, an ECC83, is a bit unkind I really need to fix this small offset but I am stumped as to what is causing it. I haven't measured the devices I've soldered in, but the batch of 2N5551s seem pretty good with an h_FE of ~190 and a V_BE of 0.74 V - the 2N5401s are a little less consistent with an h_FE of 55 - 70 and a V_BE of ~0.725 V.</p> <p>Things I have tried so far:</p> <ul> <li>removing the emitter degeneration on the LTP (no effect)</li> <li>lowering the resistance on the non-inverting input to 10 kΩ (no effect)</li> <li>lowering the VAS current source resistance to 470 Ω thus putting a little over 1 mA through the VAS (no effect)</li> <li>putting a 5 kΩ pot on the current source for the LTP (the full 5 kΩ takes the offset down, but only to about 0.35 V)</li> </ul> <p>Things I am now speculating over include:</p> <ul> <li>using 2 x 1N4148 for output stage bias may not result in sufficient quiescent current through the output stage (possibly made worse by the emitter degeneration in the output)?</li> <li>the emitter degeneration of the current mirror may not be helping?</li> <li>the offset may be caused by the CMRR given that the circuit's ground is significantly biased towards the amp's Vcc (in which case, how would I fix that)?</li> </ul>

Discrete op-amp small voltage offset

2024-02-06T12:48:55.457

700373

|operational-amplifier|dac|calibration|precision|voltage-amplification|

<p>Some of the things I've designed such multi-channel wide-range analog outputs into had a provision for a serial port header on the board.</p> <p>In some designs, I'd calibrate using an HP 34970A with a mux card wired to a D-SUB connector that was the analog output of the device. An off-the-shelf MAX232 dongle was used to connect the serial port header to HP 34970A. The built-in firmware supported this calibration. On start-up of an uncalibrated board it'd wait for the 34970A to be present, and then it calibrated itself.</p> <p>In some other designs, I had added cheap analog muxes so that there would be a single diagnostic pin that had all sorts of internal signals switchable to it. Most muxes have tiny analog offsets when outputting to a high impedance load, so that was no problem. The firmware controlled the muxes and used an external HP 34401A to perform production tests as well as calibration. Since this was a low volume device, engineering time drove the cost, a few extra parts on the PCB were noise cost-wise.</p> <p>Since there was no need to have separate test software and a separate bed-of-nails test harness, this was cheap to implement - throw muxes onto the board, add some cal/test routines to existing firmware, done.</p>

<p>I'm using a 16-bit 8-channel DAC (DAC8568), driven by STM32 MCU.</p> <p>I need to obtain the 0-5V and 0-10V switchable output range, so to achieve that the voltage must be amplified with op-amp. This raises several questions:</p> <ul> <li><p>There are different grades in DAC8568, higher grade could produce 0-5V, lower grade produces 0-2.5V. By using a higher-grade DAC, I'll need to amplify it for 0-10V, and probably use 0-5V as is. However, the higher-grade DAC is more expensive. Can I amplify the 0-2.5V range by 2x and 4x times without losing too much precision? Or maybe it is better to just use a higher-grade DAC and amplify by 2x to obtain 0-10V? Also, I want to avoid expensive precision op-amps and use generic parts.</p> </li> <li><p>In the case of amplification, op-amps most likely will produce errors in result voltages (and also the DAC itself will be not ideal) so it will require calibration. Does it make sense to offset the output of a DAC with op-amp a little like (-0.25V, 5.25V) or (-0.25V, 10.25V) (offsets are arbitrary here), so then I can calibrate it with software, know which value produces 0V, and which 10V, and scale everything in between accordingly? Or maybe there is a better way to do it?</p> </li> <li><p>As I understand, DAC should be calibrated to address the offset/gain error of the DAC itself. By addressing this, and the op-amp amplification deviation, it looks like the calibration process will become pretty complicated. Should it be really like this?</p> </li> </ul> <p>I'm not looking for ultra-precision, but I need to reliably obtain the required voltages without too much deviation.</p>

External DAC (DAC8568) software calibration

2024-02-06T13:10:33.217

700383

|batteries|battery-charging|phase|thyristor|scr|

<p>These kind of circuits create a lot of harmonics in the grid current and are no longer allowed in many countries.</p> <p>However, if you want to go this way, you don't need to use optocouplers because the current sense circuit already has a connection to MCU GND.</p> <p>It is difficult to define a proper resistor value in the SCR gate path, that guarantees ignition under all usable angles and does not waste too much power. I recommend to use a constant current source and only short trigger pulses of around 100 µs.</p> <p>A single current source Q1 is sufficient here because only one of the SCRs has a cathode voltage below GND during a usable ignition angle. The diodes will sort this out.</p> <p>The MJE350 has enough thermal and voltage margin for your application.</p> <p><img src="https://i.stack.imgur.com/uT20x.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fuT20x.png">simulate this circuit</a> &ndash; Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a>}</p> <p>Addendum in response to comment:</p> <p>R2 and R3 are added to lower the impedance of the SCR gates. This avoids to some degree false ignitions introduced by EMI or fast transients coupled in via the transformer. Typical values are between 100 Ω and 1 kΩ.</p> <p>If you don't use a current source you need a relative low gate resistor if you want to trigger at an early angle where the cathode voltage is near GND. If you want to trigger at the peak of the sine wave you would prefer a larger resistor to stay below the maximum allowed trigger current. This problem disappears using the current source: Same trigger current at all angles.</p> <p>Your original circuit takes the trigger current from a much higher voltage and it is not pulsed because the couplers latch after the ignition signal from the controller. This needs power resistors in the 2 W range.</p> <p>A proper power factor is important if you take so much power from the grid. So I think a PFC stage is mandatory because you want to take around 1.4 kW maximum here.</p>

<p>I'm making a battery charger with phase control. While making the circuit I had some doubts.</p> <p>The transformer has a center tap, in this way I can make a full wave rectifier without diodes. Then rectifying the negative side, so I can use a more common shunt measurement.</p> <p>I´m using as optocoupler MOC3021 and SCR is 40TPS. I attached 2 images, these are my main doubts.</p> <p><a href="https://i.stack.imgur.com/wshcu.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/wshcu.png" alt="Without R3 and R4" /></a></p> <p><a href="https://i.stack.imgur.com/ExHWM.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/ExHWM.png" alt="With R3 and R4" /></a></p> <p>Are R3 and R4 needed? Is the circuit ok? The value of R1 and R2 can be calculated like this? <a href="https://i.stack.imgur.com/6rIvH.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/6rIvH.png" alt="enter image description here" /></a></p> <p>VTM = Peak On–State Voltage of optocoupler</p> <p>VGT = Maximum required DC gate voltage to trigger</p> <p>I let you the datasheets. <a href="https://www.vishay.com/docs/94388/vs-40tps-m3series.pdf" rel="nofollow noreferrer">https://www.vishay.com/docs/94388/vs-40tps-m3series.pdf</a> <a href="https://www.farnell.com/datasheets/97984.pdf" rel="nofollow noreferrer">https://www.farnell.com/datasheets/97984.pdf</a></p> <p>Is there anything else to improve this circuit?</p> <p>Thank you!</p>

SCR phase control

2024-02-06T15:05:38.167

700393

|ltspice|frequency|loop-gain|

<p>In the small-signal circuit, <span class="math-container">\$r_{o_1}\$</span> and <span class="math-container">\$r_{o_2}\$</span> appear in parallel between the output node and ground, so your hand calculation isn't correct (note that it also predicts the wrong DC gain). Specifically, the <span class="math-container">\$V_{in}/r_{o1}\$</span> term should be <span class="math-container">\$V_o/r_{o1}\$</span>. The correct pole frequency is <span class="math-container">$$f_p = \frac{1}{2\pi(r_{o1} \parallel r_{o2})C}.$$</span></p> <p>I'm not going to attempt to calculate the exact values <span class="math-container">\$r_{o1}\$</span> and <span class="math-container">\$r_{o2}\$</span>, but using <span class="math-container">\$r_o\propto \lambda^{-1}\$</span> and assuming you've calculated <span class="math-container">\$(2\pi r_{o2}C)^{-1}\$</span> correctly,</p> <p><span class="math-container">$$f_p = \frac{r_{o1} + r_{o2}}{r_{o1}}\frac{1}{2\pi r_{o2}C}.$$</span> <span class="math-container">$$= \frac{0.1^{-1} + 0.14^{-1}}{0.1^{-1}}\times 20.37\text{ MHz}$$</span> <span class="math-container">$$= 34.9\text{ MHz}$$</span></p> <p>which is much closer to what your simulation is giving.</p>

<p>This is the circuit:</p> <p><a href="https://i.stack.imgur.com/3LANS.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/3LANS.png" alt="enter image description here" /></a></p> <p><span class="math-container">$$V_{in} g_{m1} + \frac{V_{in}} {r_{o1}} = (V_{in} - V_o) s C - \frac{V_o} {r_{o2}}$$</span></p> <p><span class="math-container">$$\Rightarrow \frac{V_o} {V_{in}} = \frac{s C - g_{m1} - 1/ r_{o1}} {s C + 1/r_{o2}}$$</span></p> <p>The pole frequency is when C = 1e-13 = <span class="math-container">\$ 10^{-13}\ \mathrm{F}\$</span> (3 dB loss)</p> <p><span class="math-container">$$ f_p = \frac{\omega_p} {2 \pi} = \frac{1} {2 \pi r_{o2} C} \approx 20.37\ \mathrm{MHz} $$</span></p> <p><a href="https://i.stack.imgur.com/plmiI.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/plmiI.png" alt="enter image description here" /></a></p> <p>The graph (green line) shown is around <strong>33.29 MHz.</strong></p> <p>Formula correction according to @Puk. (Shout out to Puk!)</p> <p><span class="math-container">$$V_{in} g_{m1} + \frac{V_{o}} {r_{o1}} = (V_{in} - V_o) s C - \frac{V_o} {r_{o2}}$$</span></p> <p><span class="math-container">$$\Rightarrow \frac{V_o} {V_{in}} = \frac{g_{m1} - s C} {s C + 1/r_{o2} + 1/r_{o2}}$$</span></p> <p>For analysis in feedback loop.</p> <p>Open loop DC gain:</p> <p><span class="math-container">$$V_{in} g_{m1} + \frac{V_{o}} {r_{o1}} = \frac{V_o} {r_{o2}}$$</span></p> <p><span class="math-container">$$\Rightarrow \frac{V_o} {V_{in}} = - g_{m1} (r_{o1} \parallel r_{o2})$$</span></p> <p>But I don't know how to calculate the <span class="math-container">\$\beta\$</span> for this feedback network.</p>

Why is my LTspice simulation so different from my calculation by hand?

2024-02-06T15:59:27.717

700401

|digital-logic|verilog|system-verilog|rtl|

<p>The correct answer to the question in title is <em>yes</em>, there are some operators you cannot use in continuous assignment (or any non-procedural context); specifically the inc_or_dec_expressions (++/--) or operators_assigment (+=/&gt;&gt;=,etc)</p> <p>For example</p> <pre><code>bit a,b,c; assign a = b + c--; </code></pre> <p>The SystemVerilog BNF syntax prevents some of these expressions, but there should be some text somewhere disallowing side-effects in non-procedural contexts.</p>

<p>My question is, essentially, as stated in the title. For what it's worth, it's prompted by a comment made by Stuart Sutherland on page 256 of his <em>RTL Modelling with SystemVerilog</em>:</p> <blockquote> <p>The primary RTL modeling construct for combinational logic is the always proce­dure, using either the general purpose always keyword or the RTL-specific always_comb keyword. <strong>These always procedures can take advantage of the robust set of operators programming statements that are discussed in Chapters 5 and 6, whereas continuous assignments are limited to using only SystemVerilog operators.</strong></p> </blockquote> <p>I have bolded the relevant sentence. The suggestion seems to be that there are more operators which can be used while in an <code>always</code> statement but, even after flipping back through the book, I can't seem to find any suggestion of this.</p> <p>Chapter 5 is titled &quot;RTL Expression Operators&quot; and Chapter 6 &quot;RTL Programming Statements&quot;. I suspect Sutherland was using &quot;operator&quot; very inclusively to also mean things like <code>if-else</code> statements, <code>case</code> statements, etc., in which case the claim makes sense.</p>

In SystemVerilog, is the set of operators usable in a continuous assignment smaller than that usable in an always statement?

2024-02-06T16:50:28.487

700402

|operational-amplifier|mosfet|high-voltage|protection|tvs|

<p>Disclaimer: I've never done this before, but that never stopped anyone from giving an opinion on the internet, right?</p> <p>OK, suppose 1kV appears on the left of this schematic:</p> <p><a href="https://i.stack.imgur.com/A3UEU.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/A3UEU.png" alt="enter image description here" /></a></p> <p>If the TVS diode does its job, it will limit the differential voltage at the input of your instrumentation amps to 15V. Indeed, you will have about 50A flowing (1000V/20 ohms and neglecting 15V across the TVS) which means each 10 ohm resistor will have about 500V across it, so it will dissipate 25kW during say 20ms, or about 500 Joules. Let's check the energy meter:</p> <blockquote> <p>.45 ACP bullet muzzle energy: 432 J</p> </blockquote> <p>So you need a rather serious pulse power rated resistor, most likely many resistors in series/parallel combination so they withstand the high voltage and power.</p> <p>The TVS limits voltage so it will get much lower energy, although it's still a substantial amount. In this scenario it gets 50A * 15V * 20ms = 15J which is probably too much. Since your amps have a gain of 2000, I guess your input voltage must be tiny, so a pair of antiparallel diodes would probably be a better choice. With lower voltage, they'll get lower energy.</p> <p>This is only an estimation, it depends on the exponential decay of your voltage pulse, but I guess it's better to play it safe...</p> <p>Instead of fixed resistors, you could use some kind of current limiting device. The idea is to keep the resistance as low as possible during normal use (for low noise) while limiting current. One example would be PTC resistors, polyswitch, PTC heating wire... or simply a fast fuse.</p> <p>Note this is only about differential mode. There is no guarantee the common mode will not blow your opamps. If you remove the current from that superconducting coil in milliseconds there's going to be a huge variable magnetic field which is probably going to make everything in the vicinity act like a transformer and cause a common mode spike on your sensor wires. If you use TVS or diodes to dump it into ground or the supply rails, this current still has to go somewhere and may cause problems for the next equipment in the chain. I guess you'd have to measure it.</p> <p>Here's a simple current limiting circuit. It only works in one direction so you'd need two circuits in anti-series configuration to limit current in both directions, and it needs an isolated power supply (for example from a photovoltaic optocoupler). So it's a bit cumbersome.</p> <p><a href="https://i.stack.imgur.com/z34IV.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/z34IV.png" alt="enter image description here" /></a></p> <p>V2 is normally around 0V, so almost no current flows, voltage on the 1R resistor is negligible, the BJT is off, and the MOSFET is fully ON, which means it acts as a low value resistor.</p> <p>When V2 turns on, applying high voltage, a large current spike flows through the MOSFET, which turns on the BJT, and after a very short time (couple tens of nanoseconds) it becomes a 600mA constant current source.</p>

<p>I have a setup consisting of 8x AD8428 ultra-low noise opamps on a PCB to measure very small voltages with a noise floor of around some 100uV and a low-pass filter up to 10kHz. The input is connected to a superconductive solenoid with an inductance of up to 10mH. Normally, the solenoid is in a superconductive state, resulting in no voltage drop across it. However, in certain circumstances, when loss of superconductivity appear a pneumatic switch will kick off feeding current of around 2kA therefor a voltage peak of up to 1kV with exponential decay (20-30ms duration) can appear on the coil and the opamp input.</p> <p>I am seeking a solution to protect the preamplifier against this high voltage peak without increasing the noise level. The current configuration with input low-pass filter and some existing protection is the following:</p> <p><a href="https://i.stack.imgur.com/xnF0r.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/xnF0r.png" alt="enter image description here" /></a></p> <p>My plan is to put directly before the choke (next after the LEMO connector):</p> <ul> <li>10 - 10 Ω resistor</li> <li>8.0SMDJ15CA TVS diode (300A peak pulse current)</li> </ul> <p>My calculation indicates that, in the worst case of a 1000V peak, the current through the diode would be limited to 50A for that short duration.</p> <p>I would like to know if this solution provides the necessary and reliable protection or if there is a better way to achieve this?</p> <p><a href="https://i.stack.imgur.com/s9UCl.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/s9UCl.png" alt="enter image description here" /></a></p> <p><strong>UPDATE:</strong></p> <p>Out of curiosity, the circuit will also function as a detection circuit to detect the resistive state (voltage) of a solenoid. Detecting this early as possible, allows for promptly cutting the feeding current, preventing potential damage to the coil. Therefore, it is crucial to be able to measure the smallest voltage just above the noise floor.</p> <p>Some asked about the shape of the peak, its a simple circuit consisting of magnetically charged solenoid, diode and discharge resistor with value of about 0.3ohm and with thick cables. So its a fast rump up of voltage as pneumatic switch cut the current then an exponential decay with tau=L/Rdisch. For safety reasons the voltage should be limited to 1kV.</p> <p>Thanks for the answers, from the ideas they provided, I put together the following circuit. Looks like it would be able to handle +-1kV for several 100 ms which is more than enough: <a href="https://i.stack.imgur.com/vQAel.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/vQAel.png" alt="protection circuit with mosfet" /></a> This is the dissipation on one of the MOSFET and the output voltage: <a href="https://i.stack.imgur.com/Jz9Zw.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/Jz9Zw.png" alt="Dissipation on mosfet and output voltage" /></a></p> <p>However I still see a space for a slight improvement, if its possible:</p> <ol> <li><p>The dissipation is still around 40-60W, because the MOSFET is not fully closed - it will never be, because then there will be no voltage drop on R1 or R4. Now its value is 10ohms. Is there any trick to decrease further this dissipation without increasing this resistance?</p> </li> <li><p>The voltage to be blocked is quite high, reaching up to 1kV. It might be beneficial to use multiple MOSFETs in series to reduce the voltage drop across each. However, when I added another MOSFET in series, I observed a voltage drop and power dissipation only on one. This was due to a Vgs difference between the first and second MOSFETs, with the first having 4.69V and the second having 4.76V, resulting in a 70mV difference caused by voltage drop on second MOSFET. Is there a simple method to equalize these voltages? The problem is much clearer from the picture: <a href="https://i.stack.imgur.com/Q9x3U.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/Q9x3U.png" alt="" /></a></p> </li> </ol> <p><strong>UPDATE 2:</strong> Are my assumption correct, that until the MOSFET is fully open there is no significant noise?</p> <p>Thanks</p>

Operation amplifier input HV protection

2024-02-06T17:00:07.847

700411

|fpga|xilinx|vivado|

<p>No! you cannot expand it. Expanding primitives is not supported in Vivado.</p> <p>But if you are interested in which pin is connected to which flip flop (in the register) here is how you can see it: Three dots will appear on the input bus near the register/flip flop,</p> <p><a href="https://i.stack.imgur.com/D6e6m.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/D6e6m.png" alt="Three Dots appear the concatenation" /></a></p> <p>and if you take the cursor to the three dots, or zoom in, You will be able to see the detail of how the input are concatenated to make a single bus that goes to the register.</p> <p><a href="https://i.stack.imgur.com/gCaDi.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/gCaDi.png" alt="Close up view" /></a></p> <p>Here it shows that the bus bits 6:0 goes to the 7:1 location of the register. Quick approach, simply the signal that is at the top is LSB.</p>

<p>I am trying to make the design shown below which is basically a shift register: <a href="https://i.stack.imgur.com/3vSvS.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/3vSvS.png" alt="LFSR" /></a></p> <p>When I elaborate this design in Vivado, it shows me the following:</p> <p><a href="https://i.stack.imgur.com/rAVsN.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/rAVsN.png" alt="Vivado design" /></a></p> <p>How can I see which flip-flops the inputs and outputs of the XOR gates are connected to? i.e. is there a way to &quot;expand&quot; out the RTL_REG component to look like the first image?</p> <p>Update: The three dots on the bus do not appear to be there for me when I zoom in: <a href="https://i.stack.imgur.com/MqFlx.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/MqFlx.png" alt="enter image description here" /></a></p>

How to see the connections of each flip-flop in Vivado RTL schematic view?

2024-02-06T18:13:00.183

700423

|power|antenna|radio|transmitter|

<p>There is a video on internet. It demonstrates a long distance radio transmitter with schematics. The antenna is on the label &quot;ANT&quot;. It is similar to your RF circuit.</p> <p><a href="https://www.youtube.com/watch?v=OtfEhW0PRj0" rel="nofollow noreferrer">https://www.youtube.com/watch?v=OtfEhW0PRj0</a></p>

<p>I want to measure the transmit power of my AM modulated RF circuit. Below is the RF circuit from LTSpice. Should the power be calculated at nodes R5 or C3? Which node can serve as an antenna? The reason for my question is about the power calculation at nodes C3 and R5. C3 is very high but R5 is low. How can I get rid of this difference when an antenna should transmit?</p> <p><a href="https://i.stack.imgur.com/JnRqL.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/JnRqL.png" alt="circuit" /></a></p>

Where is the transmit power of antenna in RF circuit schematic calculated?

2024-02-06T19:57:06.023

700432

|rf|fsk|

<p>Your consideration regarding the <strong>frequency error</strong> is correct; the uncertainty of the reference oscillator's frequency gets scaled by the same factor as its frequency to the carrier.</p> <p>So, you have an uncertainty of ca ± 17 kHz at 868 MHz.</p> <p><strong>However</strong>, you're probably incorrect on the bandwidth; frequency synchronization will probably correct the frequency offset, leaving you with the bandwidth error of the (equivalent, not necessarily physically manifest) baseband signal, and that would depend on the sampling frequency error.</p> <p>I don't know the chip you mention well enough to tell you whether the sampling rate is identical to the crystal frequency, or derived as a multiple or fraction of that.</p>

<p>The datasheet for Semtech LLCC68 states, that when choosing appropriate bandwidth for 2FSK, one must obey the following constraint:</p> <p><span class="math-container">$$ Bandwidth[DSB] \geqslant bitrate + 2\cdot frequency\ deviation + frequency\ error $$</span></p> <p>It further states, that</p> <blockquote> <p>frequency error is two times the <strong>crystal frequency error</strong> used</p> </blockquote> <p>The first two terms are from Carson's bandwidth rule, but what about &quot;frequency error&quot;?</p> <p>If we follow the datasheet to the letter, we must use the maximum absolute error of the crystal frequency (in relation to its frequency, as stated in the spec). So, for example, for <span class="math-container">\$f_{xtal} = 32\ \mathrm{MHz}\$</span> and an error of 20 ppm, frequency error will be calculated as follows:</p> <p><span class="math-container">$$ f_{err} = \dfrac{32 * 10^6 * 20}{10^6} = 640\ \mathrm{Hz} $$</span></p> <p>This seems illogical, since in reality the &quot;native&quot; frequency of the crystal is not used directly (it is too low), but it is &quot;upscaled&quot; (don't know the correct word for it, but the crystal is used to drive the PLL at the desired higher frequency) to the operating frequency of the transceiver. For example, if we are operating in the 868 Mhz ISM band, then 868 MHz should be used in the numerator (obviously, &quot;upscaling&quot; the crystal's frequency to 868 MHz results in &quot;upscaling&quot; the error proportionally as well), so we get this:</p> <p><span class="math-container">$$ f_{err} = \dfrac{868 * 10^6 * 20}{10^6} = 17360\ \mathrm{Hz} $$</span></p> <p>Which one is correct? Intuitively, the second calculation seems to be correct, but I might be missing something.</p>

What to use as "frequency error" when determining appropriate bandwidth for 2FSK?

2024-02-06T21:55:34.293

700446

|connector|

<p>The big one is almost certainly a <a href="https://www.molex.com/en-us/products/part-detail/428160212?display=pdf" rel="nofollow noreferrer">Molex Mini-Fit SR</a>, probably 0428160212.</p> <p>The small one looks like a <a href="https://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&amp;DocNm=411-5899&amp;DocType=SS&amp;DocLang=Japanese" rel="nofollow noreferrer">TE Economy Power</a>, probably 1-1123722-3.</p> <p>If you have dimensions or other views of the plug, the answer would be more definitive. Prepare for sticker shock on the tooling; the Molex crimper is $4400.</p>

<p>Can you identify these connectors from a Lippert RV leveling system?</p> <p><a href="https://i.stack.imgur.com/P9Q5h.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/P9Q5h.png" alt="enter image description here" /></a></p> <p>Photo isd from etrailers.com</p>

What are these connectors from a Lippert RV leveling system?

2024-02-07T00:05:49.467

700447

|microcontroller|clock|symbol|clock-speed|system-on-chip|

<p>Figure 67. <em>Bus clock enable logic</em> shows a little more detail. The <code>sys_ck</code> input to the <code>SCGU</code> is shown as a 2-input AND gate. One input is the clock signal, and the other is a control signal. This serves as a logical clock gate, where the control signal is the gate enable. Here is the description for this specific clock signal:</p> <pre><code>As shown in the Figure 67, the enabling of the core and bus clock of each domain depends on several input signals: • cpu_sleep and cpu_deepsleep signals from the CPU • srd_sleepdeep signal • RCC_xxxxENR.PERxEN bits of peripherals located on the CPU domain </code></pre> <p>The clock gate likely is implemented with special timing to prevent clock glitches when the enable changes. It may even be implemented as a latch, but it is useful to simply think of it as an AND function from a chip user perspective.</p>

<p>I'm looking at this clock diagram, and it has five of these little boxes with symbols that look like AND gates inside them. But, they only have one input. What do they mean here?</p> <p>Source <a href="https://www.st.com/resource/en/reference_manual/rm0455-stm32h7a37b3-and-stm32h7b0-value-line-advanced-armbased-32bit-mcus-stmicroelectronics.pdf" rel="nofollow noreferrer">here</a></p> <p><a href="https://i.stack.imgur.com/cY4pl.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/cY4pl.png" alt="clock diagram" /></a></p>

What does an AND gate inside a box mean?

2024-02-07T00:06:46.947

700453

|soldering|

<p>ALWAYS wipe it on the slightly wet sponge before turning off. After wiping, coat it in solder and turn it off. Even with that, the newer Weller tips will eventually oxidize.</p>

<p>I’ve been soldering (amateur level) for about 2 years now and a common issue I keep facing is the tip always gets oxidised.</p> <p>I recently bought a new tip and I’ve used it 4 times. The first three times I got it to work fantastically, but the last time I used it, the tip got oxidised really bad.</p> <p>I didn’t really do anything differently, I set the temperature to around 300 C, tin the tip with solder, use flux, and regularly clean my tip with a damp sponge, with the occasional steel wool.</p> <p>Here’s what my tip looks like right now. <a href="https://i.stack.imgur.com/k6tWk.jpg" rel="noreferrer"><img src="https://i.stack.imgur.com/k6tWk.jpg" alt="enter image description here" /></a></p> <p>Is there any way to save this tip?</p> <p>Also, I would love some good advice on how to use my soldering iron properly so that I can prevent the tip from getting oxidised again.</p>

Soldering iron tip gets oxidised

2024-02-07T01:07:31.403

700467

|avr|avr-gcc|

<p>You access serial number using <code>SERNUMx</code> register, so searching for <code>SERNUM0</code> should give you the results you want:</p> <p><a href="https://github.com/search?q=repo%3Aavrdudes%2Favr-libc%20SERNUM0&amp;type=code" rel="nofollow noreferrer">https://github.com/search?q=repo%3Aavrdudes%2Favr-libc%20SERNUM0&amp;type=code</a></p> <p>or if you want to see the list locally:</p> <pre><code>git clone https://github.com/avrdudes/avr-libc cd avr-libc/ git grep -l SERNUM '*.h' </code></pre> <p>this returns 80 entries currently, such as avr128da28, &quot;iom1608&quot; (meaning &quot;atmega1608&quot;), &quot;iotn212&quot; (meaning atttiny212) etc...</p> <p>(also, if you want newer avr-gcc you can use 3rd-party embedded managers like &quot;platformio&quot;.)</p>

<p>On Microchip's site, the &quot;parametric search&quot; table for microcontrollers does not have a filter column to select the models that feature a unique ID. Is there a way to list (enumerate) all models that have this feature?</p> <p>For example, I saw that the ATtiny416 does have it. However, this model is not supported on the avr-gcc toolchain on Linux (at least not the version I have, with Ubuntu 22.04); hence my motivation for this question.</p> <p>Is there some particular keyword(s) that I could search inside the .h files, say, <code>/usr/lib/avr/include/avr/io*.h</code> that would reveal which ones among those supported models feature the unique ID?</p>

How to identify all AVR MCUs (ATtiny and ATmega) that feature a factory-programmed unique ID

2024-02-07T02:50:23.717

700470

|circuit-analysis|control-system|laplace-transform|

<p>If you take the inverse Laplace Transform of the transfer function, you get the impulse response in time (<span class="math-container">\$h(t)\$</span>). This is not yout intention here. In order to get the corresponding linear differential equation, you can work as below:</p> <p><span class="math-container">$$ H(s)= \frac{75(s+1)}{s(s+5)(s+25)+75(s+1)} $$</span></p> <p>Considering <span class="math-container">\$V_i(s)\$</span> and <span class="math-container">\$V_o(s)\$</span> as the input and output of the system, respectively:</p> <p><span class="math-container">$$ H(s)= \frac{V_o(s)}{V_i(s)} = \frac{75s+75}{s^3+30s^2+200s+75} $$</span></p> <p><span class="math-container">$$ (s^3+30s^2+200s+75)V_o(s) = (75s+75)V_i(s) $$</span></p> <p>We know that transfer function assumes zero initial conditions. So, when converting from the <span class="math-container">\$s\$</span> domain to time domain, is enough to ensure that each <span class="math-container">\$s^n\$</span> factor is translated to an operation <span class="math-container">\$\frac{d^n.(t)}{dt^n}\$</span> (or n-derivative):</p> <p><span class="math-container">$$ \frac{d^3v_o(t)}{dt^3}+30\frac{d^2v_o(t)}{dt^2}+200\frac{dv_o(t)}{dt}+75v_o(t)=75\frac{dv_i(t)}{dt}+75v_i(t) $$</span></p>

<p>I have the transfer function of this circuit, which is <a href="https://i.stack.imgur.com/ggBpD.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/ggBpD.png" alt="enter image description here" /></a></p> <p>I am being asked to find the differential equation that represents the relationship between input and output voltage. Since the transfer function H(s)=Vo(s)/Vi(s), I thought that I would be able to get this equation by taking the inverse laplace transform of H(s). But I can't figure out the answer, and when I put it into MATLAB I get this ridiculously long answer <a href="https://i.stack.imgur.com/E3xhV.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/E3xhV.png" alt="enter image description here" /></a> full output: <code>5*symsum((exp(root(z^3 + 30*z^2 + 200*z + 75, z, k)*t)*root(z^3 + 30*z^2 + 200*z + 75, z, k))/(60*root(z^3 + 30*z^2 + 200*z + 75, z, k) + 3*root(z^3 + 30*z^2 + 200*z + 75, z, k)^2 + 200), k, 1, 3) + 75*symsum(exp(t*root(z^3 + 30*z^2 + 200*z + 75, z, k))/(3*root(z^3 + 30*z^2 + 200*z + 75, z, k)^2 + 60*root(z^3 + 30*z^2 + 200*z + 75, z, k) + 200), k, 1, 3)</code></p> <p>Am I going about this incorrectly? Is the differential equation I'm looking for not the inverse laplace transform? Any help is appreciated, I am quite confused.</p>

What is the differential equation that relates input and output voltage of a circuit?

2024-02-07T03:19:38.183

700473

|dc-dc-converter|boost|

<p>There is nothing obviously wrong with the schematic or the layout.</p> <p>Failure without overheating points towards excessive voltage or current on some semiconductor or capacitor. Because replacing the chip didn't help, I would measure input and output capacitors, the inductor and the diode when the chip is removed.</p> <p>It's also possible that your power supply is delivering voltage spikes when being plugged in. Some cheap DC supplies have bad regulation that spikes up the voltage when hot-plugged into ceramic capacitors.</p>

<p>I am trying to assemble a boost converter using the <a href="https://www.ti.com/product/LM27313" rel="nofollow noreferrer">LM27313</a> (<a href="https://www.ti.com/lit/gpn/lm27313" rel="nofollow noreferrer">datasheet link</a>), following the reference design and calculations given in the data sheet. The load is 6 white LEDs (Vf=2.95V) in series.</p> <p>Each assembly will drive the load once or twice, but after that, it will not work again. After replacing the chip, I noticed a faint 'click' from the inductor when I applied power, but Vout would never rise above Vin. Upon replacing the chip for a third attempt, the assembly delivers a 10-20 ms pulse of light immediately after power is applied, after which Vout decays back to Vin minus the diode's forward voltage drop. At no point was the chip ever too hot to touch.</p> <p>What am I doing that's killing these ICs this fast?</p> <p>I have checked the power supply: it is capable of supplying the required current, it does not overshoot when turned on, and delivers (to my inexperienced eye) ripple-free 12V DC. The load draws ~150mA when connected to a bench power supply.</p> <p><a href="https://i.stack.imgur.com/W8hHg.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/W8hHg.png" alt="schematic" /></a></p> <p>_{(Schematic download also on <a href="https://mega.nz/file/Q3pGhCpL#V7eud8AWw-szYsrPeOAknNhqJdB62LVK7dj97i-s-JM" rel="nofollow noreferrer">mega.nz</a>)}</p> <p>Rb and D2-D7 are not on the same board as the other components, but are connected with a few inches of hookup wire. Ground is connected from J2 to J3 on the bottom layer.</p> <p>PCB layout:</p> <p><a href="https://i.stack.imgur.com/C5riy.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/C5riy.png" alt="PCB layout" /></a></p> <p>_{(PCB layout download also on <a href="https://mega.nz/file/InwzBZaC#5h5F2saY4GDjztocRtXxVcwisK0dKh4FJtH4Akhv9xA" rel="nofollow noreferrer">mega.nz</a>)}</p>

LM27313 boost converter failure

2024-02-07T03:30:58.553

700494

|microcontroller|power-electronics|buck|switching-regulator|

<p>Buck converter IC's almost invariably have a &quot;FB&quot; pin or equivalent that is driven high when Vout exceeds Vrequired and low when Vout is below Vrequired.<br /> This can (usually very easily) be used to provide a uC controlled output by providing a comparator that is driven by Vout divided to some useful value and a reference voltage from the uC - either analog or filtered PWM.<br /> When Vout divided is below Vref_microcontroller the FB pin is driven high.<br /> When Vout_divided rises above Vref_microcontroller FB is driven low.</p> <p>This is a very common method of control.<br /> The divider ratio can be anything wanted (within reason).<br /> If this arrangement does not meet your needs please advise why in adequate detail.</p> <p>Diagrammatic only:</p> <p><a href="https://i.stack.imgur.com/AsHxj.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/AsHxj.png" alt="enter image description here" /></a></p> <p>Original of hacked about image from <a href="https://resources.pcb.cadence.com/blog/how-to-spot-voltage-mode-control-in-dc-dc-converters" rel="nofollow noreferrer">here</a></p> <hr /> <p>Applying the above method with <a href="https://www.diodes.com/assets/Datasheets/AP3211.pdf" rel="nofollow noreferrer">this</a> regulator, to your application appears to meet your need.<br /> I've copied the first page of the datasheet below to show the specs that it meets and simplicity of operation. It does not have synchronous rectification so is not quite as efficient as the best in class. It achieves over 90% efficiency across some portions of its Vin/Vout/Iload map). (If desired, synchronous rectification which could be added with a FET across D1 and minimal control logic.)<br /> The AP3211 costs $US1.02 in 1 quantity from Digikey and under $0.40/1000. (OR 15c and 11c <a href="https://www.lcsc.com/search?q=ap3211" rel="nofollow noreferrer">from LCSC!</a>.</p> <p><a href="https://i.stack.imgur.com/lhmmp.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/lhmmp.png" alt="enter image description here" /></a></p> <p>Many maybes <a href="https://www.digikey.co.nz/short/zrp53v5r" rel="nofollow noreferrer">here</a></p>

<p>I am designing for an application where I need a buck converter that takes the voltage from a 2S Li-ion battery (6-8.4 V) and the load I need to drive is 0-6 V and will take 1.2 A max. I need to control the buck converter's output voltage (0-6 V) from my microcontroller.</p> <p>In my particular application, I can not use bigger inductor or capacitor values so I need a higher switching frequency (greater than 1 MHz. 2 MHz is preferred).</p> <p>I need a buck converter IC that is able to set the output voltage based on the signal from my microcontroller. The signal can be analog or digital. Maybe an IC that does not use its internal reference voltage but the reference voltage from my microcontroller's DAC.</p> <p>I can not use a digital potentiometer like X9C104 because I will not be able to output a voltage less than the buck converter chip's internal reference voltage. I also tried a &quot;hack&quot; where I put a voltage on the soft start pin of the buck converter IC to control the output voltage but I am not able to make it work reliably.</p>

MCU Controlled Buck Converter IC

2024-02-07T08:03:35.833

700496

|integrated-circuit|dac|texas-instruments|comparison|

<p>According to TIs <a href="https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/941678/dac8562t-difference-between-8562-and-8562t" rel="nofollow noreferrer">E2E forum</a>, the only difference is the digital input threshold levels.</p> <p>The T version is designed to be compatible with 5V TTL logic levels whils the non-T version uses CMOS voltage levels.</p> <hr /> <p>If you scroll down towards the bottom of the TI product pages, they show some of the E2E posts relating to each product which can be a rather useful source of info about their products.</p>

<p>These two callouts have distinct product pages (<a href="https://www.ti.com/product/DAC8562?dcmp=dsproject&amp;hqs=pf" rel="nofollow noreferrer">https://www.ti.com/product/DAC8562?dcmp=dsproject&amp;hqs=pf</a> and <a href="https://www.ti.com/product/DAC8562T?dcmp=dsproject&amp;hqs=pf" rel="nofollow noreferrer">https://www.ti.com/product/DAC8562T?dcmp=dsproject&amp;hqs=pf</a>) and distinct data sheets. I've spot-checked several pages of the PDF data sheets for these two chips with my eyeballs and, aside from typesetting differences and the different callouts for the chip part numbers, found the specs and text to be identical. I don't know of a diff tool that will work on PDFs! Rather than trying to discern a significant difference by manually comparing every page using my unreliable wetware, I'm hoping someone (from TI, perhaps?) might know what's up with this. These chips are obviously related, but the datasheets and product pages on the TI website for each part make no mention of the other. Is one just a die-shrink of the other? Are they intended to be identical? Or is there an actual difference between the two parts documented somewhere in the 63-page data sheets?</p>

What is the difference between the DAC8562 and DAC8562T chips from Texas Instruments?

2024-02-07T08:36:24.563

700502

|pwm|negative|

<p>Presumably, the device converts a High-side switched PWM into a Low-side switched PWM signal.</p> <p>So it pretty much converts from the right hand to the left hand in the following image: <a href="https://i.stack.imgur.com/QtlpV.png" rel="noreferrer"><img src="https://i.stack.imgur.com/QtlpV.png" alt="Low side vis High side switch" /></a><br /> <a href="https://www.quora.com/What-is-a-high-side-low-side-driver-in-electronics" rel="noreferrer">Image Source</a></p> <p>I would assume that this device simply consists of one N-channel MOSFET, and one or two resistors. And possibly some over-voltage protection if applicable.</p>

<p>I was reading documentation about flaps control unit for experimental aircraft, and I found, that indicator LEDs on device are dimming by something they called &quot;<code>negative PWM (with switched ground)</code>&quot;.</p> <p>After some research I found out, that this company sells some device (called DIM BOX), that converts positive PWM type to negative PWM type.</p> <p>That part of product list:</p> <p>[<img src="https://i.stack.imgur.com/j9iVt.png" alt="Description from product list1" /></p> <p>Firstly, I was thinking that they mean that this negative PWM is simply PWM with negative voltage (so -12V instead of 12V). But in electrical parameters table, there is clearly written that OUT voltage is also positive, only current is negative: <a href="https://i.stack.imgur.com/powHw.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/powHw.png" alt="Electrical parameters" /></a></p> <p>It is also consistent with arrows on installation schema: <a href="https://i.stack.imgur.com/Jtz8K.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/Jtz8K.png" alt="Installation schema" /></a></p> <p>So, my question are:</p> <ol> <li>I never heard anything about &quot;<code>negative PWM type (switched minus)</code>&quot;. What is it? I can imagine, that it is somehow &quot;reversed&quot; usual PWM, so in <em>off state</em>, there is 12V on output, and in <em>on state</em>, there is 0V (ground), but in this case, it is only usual PWM with reversed duty cycle, isn't it?</li> <li>How this negative PWM can be generated (or converted from positive PWM)?</li> </ol> <p><a href="https://lambert-aerodevices.cz/wp-content/uploads/2023/05/dimbox_productlist_en.pdf" rel="nofollow noreferrer">Here is full product list pdf for this &quot;DIM BOX&quot; device</a></p>

What is negative PWM (with switched ground)?

2024-02-07T09:16:12.253

700505

|mosfet|switches|

<p>The <a href="https://www.vishay.com/docs/91027/irf620.pdf" rel="nofollow noreferrer">IRF620 MOSFET</a> has an output capacitance of 100 pF. That capacitance is from drain to source internally and, it is that capacitance (along with resistor R1, 100 Ω) that defines the maximum risetime of the output.</p> <p>At best it's going to be C*R = 10 ns and probably more like 20 ns (if you take the 10% to 90% definition of what risetime is). Then, you need to consider how hard you are driving the gate. Not very hard is the problem; R2 and R5 set the gate drive impedance (267 Ω) and, that has to charge the gate capacitance up (260 pF). That's very nearly 70 ns in its own right.</p> <p>So, you are feeding a slow risetime into more filtering and that will just add to the woes of the circuit.</p> <p>May I recommend that you use a source follower GaN MOSFET driven by a fast driver. I've used <a href="https://epc-co.com/epc/" rel="nofollow noreferrer">EPC GaN parts</a> driven by a TI driver chip to achieve around 1 ns rise time at 80 volts. Obviously this is slightly overkill for what you want but, you need to <strong>aim high</strong> with this sort of design.</p> <ul> <li><a href="https://epc-co.com/epc/Portals/0/epc/documents/datasheets/EPC2037_datasheet.pdf" rel="nofollow noreferrer">EPC2037 GaN MOSFET</a></li> <li><a href="https://www.ti.com/lit/ds/symlink/lmg1020.pdf?ts=1707231476622&amp;ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FLMG1020%253Fqgpn%253Dlmg1020" rel="nofollow noreferrer">LMG1020 gate driver</a></li> </ul> <p>I floated both the GaN MOSFET and TI driver chip to form a source follower. I used a Recom isolated dc-dc converter to do this. Sorry, can't give much more on details as it has IP.</p>

<p>I want to calibrate the P6015A Tektronix probe and need a source of about 40-60V pulses (so the probe, which is 1/1000 won't drown it in noise) with the leading edge about 5ns. I have a square generator with insufficient leading edge, so I decided to add something fast after it.</p> <p>I made switch below, but all I get is a leading edge of 76ns.</p> <p>Would you please suggest any changes or a different approach?</p> <p><a href="https://i.stack.imgur.com/epkoA.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/epkoA.jpg" alt="schematics" /></a></p>

Fast MOSFET switch for leading edge about 5ns

2024-02-07T10:21:22.900

700510

|operational-amplifier|switching|dac|charge-pump|analog-switch|

<p>There's no one correct way, the best way may depend on other unstated things, but here are a couple methods:</p> <ol> <li><p>Add another op-amp and add an analog multiplexer between the two op-amp outputs and the resistor to the VCO.</p> </li> <li><p>Set the op-amp gain to 3 and divide down the 0-5V output of the AF4158 to 0~3.3V. Put an analog multiplexer between the two 0~3.3V sources.</p> </li> <li><p>Change the gain of the op-amp by switching the feedback resistors, and don't divide the AF4158 output, but retain the analog multiplexer.</p> </li> </ol> <p>For 2. and 3. you could use a <a href="https://www.sparkfun.com/datasheets/Components/General/74HC4052.pdf" rel="nofollow noreferrer">74HC4052</a> for the multiplexer(s), which is inexpensive and will operate well from a 5V supply. It's a dual so you would need only one component to both change the gain and change the source for the op-amp. For 1. you would need a different kind of multiplexer because of the 10V requirement. Note that the control voltage would be 0/5V not 0/3.3V with this part.</p> <p>I think I would pick 2. or 3.</p>

<p>I have two sources to generate a ramp signal to drive a voltage controlled oscillator.</p> <p>Source one is DAC of the STM32H743 and the second one is RF Synthesizer ADF4158's charge pump output.</p> <p>RF Synthesizer is better solution for ramp generation. Because of that i simply added 0 ohm resistors to select the desired source physically. However now I want to add more software selectable solution for using DAC as well without soldering components.</p> <p>VCO's range is 0 to 10V. ADF4158 generates 0 to 5V ramp so op-amp gain is set to 2. However STM32H743 DAC is 0 to 3.3V and the gain also must be set to 3 when DAC is selected.</p> <ol> <li><p>I need to change the gain of op-amp. (I will use a digital pot for gain selection if no other way is suggested here.)</p> </li> <li><p>I want to be able to change ramp source between RF Synthesizer and DAC by using MCU software.</p> </li> </ol> <p>What is the correct and simple way of doing this without affecting the circuit behaviour?</p> <p><a href="https://i.stack.imgur.com/6Ksoh.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/6Ksoh.png" alt="Schematic" /></a></p>

How to correctly switch between two analog signals before op-amp

2024-02-07T11:51:35.430

700513

|operational-amplifier|rail-to-rail|

<p>Remove C19 or replace it with 100pF. It's adding a lot of phase shift to the feedback.</p>

<p>I have been developing a 0-10v / 4-20ma analog output board</p> <p>I have come across an issue when connecting to some certain loads I am experience signifcant oscillating where the output is swinging from 0v to the rail voltage (24v in this case).</p> <p>Below is the schematic. The op-amp is an LM358</p> <p><a href="https://i.stack.imgur.com/OmYvC.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/OmYvC.png" alt="Analog schematic" /></a></p> <p>J4 allows us to swap between 0-10 (1-2) and 4-20ma (2-3). AO_SIG1 is fed from an MCP4728.</p> <p>Below are 3 captures from a scope, yellow channel is the output and blue channel is the output of MCP4728.</p> <p>NO LOAD target 10v <a href="https://i.stack.imgur.com/TOCl6.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/TOCl6.png" alt="No Load" /></a></p> <p>target 10v output with 1K resistor across output (A_OUT2+ - A_OUT2-) <a href="https://i.stack.imgur.com/xcPF4.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/xcPF4.png" alt="enter image description here" /></a></p> <p>Target 10v output w. 10mA load set by a programmable load (DL24) <a href="https://i.stack.imgur.com/VlkXF.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/VlkXF.png" alt="enter image description here" /></a></p> <p>I would appreciate any guidance to what could be the issue and how I might go about eliminating this oscillation.</p>

Unstable output with op-amp under some loads (LM358)

2024-02-07T12:12:00.660

700519

|antenna|impedance-matching|low-pass|high-pass-filter|

<p>It's a low-pass pi-filter that is used to match the impedance of the antenna to the port impedance of the RF switch (taking into account that it is in series with 33 pF). For the values shown, I would say that its region of operation is pretty close to 900 MHz but, without details of the antenna and port it's impossible to say exactly what impedances it attempts to match.</p> <blockquote> <p><em>Upon calculation, I found that the cut off frequency of this low-pass pi filter is approximately 1800 MHz</em></p> </blockquote> <p>That is incorrect; it is 939.3 MHz and pretty-much about right for impedance matching (slightly above the nominal operating frequency) for a low-pass pi filter.</p>

<p>In the schematics <a href="https://www.st.com/content/ccc/resource/technical/layouts_and_diagrams/schematic_pack/group1/2e/e5/94/2a/d7/46/48/57/MB1389-WL55JC-highband-E02_Schematic/files/MB1389-WL55JC-highband-E02_Schematic.pdf/jcr:content/translations/en.MB1389-WL55JC-highband-E02_Schematic.pdf" rel="nofollow noreferrer">en.MB1389-WL55JC-highband-E02_Schematic</a>, there's a Pi filter following the RF switch before it links to the SMA connector for the antenna. <a href="https://i.stack.imgur.com/zHjFM.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/zHjFM.png" alt="enter image description here" /></a></p> <p>Upon calculation, I found that the cutoff frequency of this low-pass pi filter is approximately 1800 MHz, which is significantly higher than the 870 MHz of LoraWAN frequencies this schematics is built for.<br> Could someone clarify what could be the intention behind including this section in the schematics?<br> Ultimately, I intend to integrate a chip antenna onto the PCB and eliminate the SMA connector.<br> Should I retain these filters, or do I need to adjust the values of the pi filter components?</p> <p>Thank you!</p>

How can I calculate filter parameters between RF switch and antenna?

2024-02-07T13:11:12.810

700522

|raspberry-pi|can|bus|

<p>I found a poor soldering at the tranceiver power supply. It is work now.</p>

<p>I have two CAN transceivers on the same PCB; they are connected to a Raspberry and a PIC32 MCU.</p> <p>The PIC32 can receive and send any message, but the RPI can rarely receive messages from the microcontroller. Messages from external USB CAN devices can be received perfectly by both devices. Termination is OK between L and H.</p> <p>Is it a problem that the 2 transceivers are too close together? Should I look for the problem in the software settings?</p> <p><img src="https://i.stack.imgur.com/pz3Z6.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fpz3Z6.png">simulate this circuit</a> &ndash; Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a>}</p> <p>Update: Thank you for your answers. Sorry if my question did not contain enough information.</p> <p>I have been using and planning CAN bus communication for years. When I designed the circuit I thought it shouldn't be a problem if I put two transceivers that close together. I tried so many things in the troubleshooting process that I started to doubt everything. I actually wondered if the particular arrangement could cause a problem.</p> <p>Baud rate, wiring, other basic things to look at are fine. Now I suspect the timing, but I would be very surprised if there was a problem with that, since all the devices run an external oscillator to get the clock as accurate as possible.</p> <p>I also thought about intermittent bad soldering, but then there would be more problems with the external usbcan device also. I will doublecheck that.</p> <p>I think there is a software problem, but I have tried the same configuration several times and so far no problem.</p> <p><a href="https://i.stack.imgur.com/CWnAP.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/CWnAP.png" alt="mcu tranceiver" /></a></p> <p><a href="https://i.stack.imgur.com/1e4PG.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/1e4PG.png" alt="RPI CANBUS" /></a></p>

Two CAN transceivers on the same PCB

2024-02-07T13:32:47.837

700524

|ltspice|plot|

<p>LTspice is correctly plotting what you asked for. If you look at the subtracted result, the amplitude will always be constant but, the phase will change from 0° to -180° as expected: -</p> <p><a href="https://i.stack.imgur.com/NfeKg.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/NfeKg.png" alt="enter image description here" /></a></p>

<p>I have a circuit with an AC source. It is a low pass and high pass filter that have the same component values so the critical frequencies are the same. The filters are driven from the same source. I'd like to subtract the output voltage at the low pass filter from the output of the high pass filter. It seems like LTspice is plotting the absolute value of the difference. I thought that is might have something to do with the x-axis being a log scale but this does not change if I change it to linear.</p> <p>The red trace is the difference between the output of the low pass filter (blue) and the high pass filter (green) <a href="https://i.stack.imgur.com/0g2yU.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/0g2yU.png" alt="enter image description here" /></a></p>

Subtracting two plots as an algebraic expression - Sign convention of the result

2024-02-07T13:54:24.577

700525

|rf|resonance|

<blockquote> <p>... why not maximize Q by setting L huge and C tiny?</p> </blockquote> <p>Guess ... No OP &quot;current&quot; defined ...</p> <p>Should be &quot;difficult&quot; to set a huge L.</p> <p>Calculated with coil64, air inductor, multilayer, with 0.1 mm wire ...<br /> Examples:<br /> 100 mH -&gt; Rdc= 726 Ohm -&gt; wo<em>L/R = 8.65 @10 kHz<br /> 1000 mH -&gt; Rdc= 2374 Ohm -&gt; wo</em>L/R = 26.5 @10 kHz</p> <p><a href="https://i.stack.imgur.com/5F8GZ.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/5F8GZ.png" alt="enter image description here" /></a></p> <p><a href="https://i.stack.imgur.com/KmHyU.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/KmHyU.png" alt="enter image description here" /></a></p> <p>No parasitic capacitor into account ...<br /> No &quot;skin&quot; effect calculated.</p>

<p>For the tank circuit below, the resonant frequency is f0=10kHz, where:</p> <p><span class="math-container">$$ f0=1/(2 \pi \sqrt{L_1 C_1}). $$</span></p> <p>Assuming R=1 ohm, and given that [correction thanks to @Franc] <span class="math-container">$$ Q_1 = \frac{R} {\sqrt{L_1/C_1}}, $$</span> the value of Q for the circuit below comes to 6,287.</p> <p>If I want to maximise Q, I could just increase the inductance by a factor of 10 and decrease the capacitance by a factor of 10, which defines L2=1000mH and C2=0.253nF. The resonant frequency remains the same at f0=10kHz but the quality Q has increased to Q2 = 62,870.</p> <p>Why is it a bad idea to just keep increasing the ratio L/C? What are the costs of doing so?</p> <p>So the numbers above are wrong, but the general question about changing the ratio L/C while keeping the product LC constant remains.</p> <p><img src="https://i.stack.imgur.com/rcyf4.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2frcyf4.png">simulate this circuit</a> &ndash; Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a>}</p>

Given that \$Q = {R} {\sqrt{L/C}}\$, why not maximise Q by setting L huge and C tiny?

2024-02-07T13:57:21.777

700540

|negative-feedback|

<ul> <li><p>Negative feedback will increase the upper frequency limit of an amplifier (lowpass principle) by the factor <strong>(1-loopgain)</strong> with loop gain <strong>LG=-Ao*B</strong> (Ao=Gain without feedback and B=feedback factor)</p> </li> <li><p>The input resistance will be modified by the <strong>same factor (1-loop gain)</strong>.</p> <p>Feedback as a <strong>voltage</strong>: Input resistance will <strong>increase</strong>;</p> <p>Feedback as a <strong>current</strong>: Input resistance will be <strong>reduced</strong>.</p> </li> </ul>

<p>I'm interested in how negative feedback affects bandwidth and the cutoff frequency. Is the cutoff frequency always increased by (1-Ab) times? fg_r = fgo*(1-Ab)? Does the same apply to input resistance?</p>

The influence of negative feedback on input resistance and bandwidth

2024-02-07T15:22:44.033

700544

|led-strip|impedance-matching|constant-current|load|balancing|

<blockquote> <p>even tiny differences in resistance will lead to relatively larger differences in current flow through each path</p> </blockquote> <p>Not quite. It is differences in the forward voltage (Vf) of each individual LED that add up to a significant difference in overall voltage drop from one panel to another. The panel with the lowest total Vf hogs current from the ones with higher Vf, even if the difference is only a few tenths of a volt.</p> <p>The solution is actually <em>more</em> resistance. If you add a resistor in series with each panel, so that now there are three resistor-LED-panel circuits connected to the voltage source in parallel, you can size the resistor such that the voltage drop across it is larger than the voltage differences among the panels. This decreases efficiency and brightness, but you can compensate for the brightness by increasing the driving voltage. The ballast resistors will work to even out the current through the panels, and it is the current that determines an LEDs brightness.</p>

<p>I have three (or 'n', where n=3 at the moment) large LED panels that I want to run in parallel.</p> <p>As we know (or should have known before the 'royal we' actually tried it!), just wiring them together in parallel leads to them being at very different brightnesses because even tiny differences in resistance will lead to relatively larger differences in current flow through each path (duh).</p> <p>I have in the back of my head that there is a very simple discrete (like just resistors and caps, basically) self-balancing circuit that solves this problem. But I keep getting a Wheatstone bridge when I try to draw it out.</p> <p>I can't find what I'm thinking of through simple internet search. The search terms &quot;load&quot; combined in any way with &quot;balancing&quot; ends up with computer load balancers of an infinite variety.</p>

Connecting multiple loads in self-balancing parallel

2024-02-07T15:39:16.457

700558

|pcb|raspberry-pi|ground|ground-plane|

<p>As always in engineering, the answer is a tradeoff. The tighter the clearance you use in a design, the more you can cram in, but the more it will cost. When it comes to clearance for suitable isolation, then something like the Saturn PCB toolkit is a good place to start. For 0-15V signals on a component pin/pad, it says you need at least 0.13mm (5.1 mil) conductor spacing. I think its numbers correspond to IPC-2221B so it's a reasonable starting point as a minimum clearance.</p> <p> Personally, I usually start at 0.15 mm/6 mil and go down if I need tighter gaps. This is my starting point as it's above the clearance needed on component pads up to 100V, and generally, I think it's the bottom of prices. I don't think you get much cheaper from PCB fabs for wanting 8 or 10 mil clearance, but that's anecdotal from me. <br> Alternatively, you could look at your finest pitch part, find the clearance between the pads, and use that. Any more clearance and you wouldn't be able to place your parts but any less and you'll be spending money for specs you don't need. You should round down to the nearest mil's worth of clearance.<br> Or if you were getting your boards made from a fab like OSHPark with a fixed minimum spec, you'd find that spec and use it for all your projects. FAB input is important for this sort of thing. <P> I've only ever used one or two clearance values in my work personally when I've had some high (>100V) voltages involved. It is worth noting that the clearance you need for pins/pads is much greater than you need for traces side by side so if you were *really* cramming the routing in you might use as low as 0.05mm for your clearance on the internal layer traces, but 0.13mm around component pads.

<p>I am designing a PCB to handle some modifications as a stepping stone from a well designed pcb from professionals to what my modifications need to be.</p> <p>I have poured ground on top and bottom and joined them with vias throughout the board. <a href="https://i.stack.imgur.com/b4Lpf.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/b4Lpf.png" alt="enter image description here" /></a></p> <p>Question: Should I be including these ground planes, and if so, is the clearance between our through holes on the 2x20 pin connector okay? What width and clearance values are needed and is there a rule of thumb for clearance distance with the ground planes and traces/ through holes? I know the software handles this, but the clearance values can be set. How does one determine the correct clearance values? <a href="https://i.stack.imgur.com/ZXXKj.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/ZXXKj.png" alt="enter image description here" /></a> Notes: Every signal will be 5v pull ups on the pins other than the 5V pin 02 and SGND pin 39.</p> <p>The floating pins are unused. The signal net traces to the right are 5V encoder pins.</p> <p>The Nets 25- 28 is our POE pair signals going from a 4 pin connector (wire to board) and a 4 pin connector to our main board. This is for test and the other board has 0 ohm resistors that will be removed if it doesnt work.</p>

Ground Plane Method

2024-02-07T16:48:38.447

700576

|usb-c|usb-pd|

<p>Both resistors to ground &quot;Rd&quot; are mandatory. See <a href="https://www.usb.org/sites/default/files/USB%20Type-C%20Spec%20R2.0%20-%20August%202019.pdf" rel="nofollow noreferrer">Spec</a> at page 151 and around. Figure 4-5 is normative.</p> <p>One famous example of failed attempt to do this optimization is RaspberryPi 4 which received quite <a href="https://hackaday.com/2019/07/16/exploring-the-raspberry-pi-4-usb-c-issue-in-depth/" rel="nofollow noreferrer">a lot</a> <a href="https://techcrunch.com/2019/07/09/the-raspberry-pi-4-doesnt-work-with-all-usb-c-cables/" rel="nofollow noreferrer">of</a> <a href="https://arstechnica.com/gadgets/2019/07/raspberry-pi-4-uses-incorrect-usb-c-design-wont-work-with-some-chargers/" rel="nofollow noreferrer">press</a> coverage about its non-compliant USB Type-C.</p> <p>In short, don't do this. It will break.</p> <p>Benson Leung has a <a href="https://medium.com/@leung.benson/how-to-design-a-proper-usb-c-power-sink-hint-not-the-way-raspberry-pi-4-did-it-f470d7a5910" rel="nofollow noreferrer">nice writeup</a> about ins and outs of this.</p>

<p>I want to charge a small, battery-powered device via a USB-C socket. It has a single LiPo battery, so 5V is fine. Since I want to make the connection as simple as possible, I do not want to engage in enumeration. My understanding is that a 5.1 kΩ pulldown on the CC lines will signal the source to behave like a conventional USB charger and supply 5V at 500 mA max. Furthermore, since the connection is reversible, only one CC line should be queried. Now my thinking is that it should be enough to connect both CC lines and to have one single resistor pull down this connection. Or do I need one resistor per line?</p>

USB-C pulldown on the CC lines: Is one resistor enough?

2024-02-07T19:26:46.780

700606

|voltage-divider|passive-filter|

<p>The voltage divider is correct to where left off, just need to slug through the algebra.</p> <p>Starting where the OP left off:</p> <p><span class="math-container">$$\frac{V_{out}}{V_{in}}=\frac{Z_2}{Z_1+Z_2}$$</span> <span class="math-container">$$\frac{V_{out}}{V_{in}}=\frac{\frac{1}{\frac{1}{R2}+jωC}}{R_1+\frac{1}{\frac{1}{R2}+jωC}}$$</span></p> <p>Multiply top and bottom by <span class="math-container">\$\left( \frac{1}{R2}+jωC\right) \$</span></p> <p><span class="math-container">$$\frac{V_{out}}{V_{in}}=\frac{1}{R_1\left( \frac{1}{R_2}+jωC\right)+1}=\frac{R_2}{R_1+R_2}\frac{1}{1+jω(R_1||R_2)C}$$</span></p> <p>So the the gain can be seen to be <span class="math-container">$$A_V=\frac{R_2}{R_1+R_2}$$</span>.</p> <p>The cutoff frequency <span class="math-container">$$2\pi f_C=\frac{1}{(R_1||R_2)C}$$</span></p>

<p>I am a mechanical engineer by training and I'm self-studying circuits. I'm trying to understand how to derive the gain and cut-off frequency for the following circuit:<a href="https://i.stack.imgur.com/DDYr2.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/DDYr2.png" alt="enter image description here" /></a></p> <p>I think that I should use the generalized voltage divider approach, where <span class="math-container">$$Z_1 = R_1$$</span> <span class="math-container">$$Z_2 = \left(\frac{1}{R_2}+\frac{1}{j\omega C}\right)^{-1}$$</span> and <span class="math-container">$$\frac{V_{out}}{V_{in}}=\frac{Z_2}{Z_1+Z_2}$$</span></p> <p>but the complex algebra is really tripping me up. I also tried brute forcing the calculation using numpy complex numbers, but I don't think I did it right. Any help would be appreciated.</p>

Voltage divider with filter cap gain derivation

2024-02-08T02:24:12.440

700628

|capacitor|electromagnetism|

<p>Following this <a href="https://www.vcalc.com/wiki/TylerJones/Capacitance+of+a+Cylindrical+Capacitor" rel="nofollow noreferrer">calculator</a>, the formula used is right (75 pF).</p> <p>But if the external rod is not &quot;full&quot; metallic, it says that capacitor value is 3 to 6 pF ...<br /> This confirms your measure (outer radius quasi &quot;infinite&quot; or not wired).</p>

<p>We have two concentric cylindrical rods in the configuration shown below. They are held isolated by two 3D-printed PLA endcaps. The capacitance can be modelled as concentric cylinders using the well-known formula.</p> <p><span class="math-container">$$C=\frac{2\pi\epsilon_0L}{\ln(\frac{b}{a})}$$</span></p> <p>For our dimensions, 2a = 0.375&quot;, 2b = 0.625&quot;, and L = 27&quot;. The dielectric is air.</p> <p>This yields a theoretical result of approximately 75pF.</p> <p>However, we measured the capacitance of these rods using a professor's measurement tool in his lab, and it read 3pF... He then verified the accuracy of his tool by measuring a known 6pF reference capacitor.</p> <p>We're struggling to believe this result is accurate since it differs significantly from well-known theory. Is there some non-ideal effect that we've failed to consider?</p> <p><a href="https://i.stack.imgur.com/8LU0s.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/8LU0s.jpg" alt="enter image description here" /></a></p> <p>Edit for more information:</p> <ul> <li>The imperial units in the calculation were correctly converted to metric using a factor of 1&quot; = 0.0254m.</li> <li>The rods were measured vertically, and care was taken to ensure concentricity.</li> <li>The rod material is steel (not stainless)</li> <li>The professor's tool measures the phase shift of a 0.1V 150kHz signal and relates that back to capacitance. I can ask for more details if that's helpful.</li> <li>The steel was sanded at the connection points and then wound with wires that were taped down to maintain tight contact.</li> </ul>

Concentric Cylinders: Measured Capacitance Contradicting Theory

2024-02-08T07:04:39.853

700634

|dc|passive-networks|transient|switching-transients|

<p>Transient analysis. I looked at the various situations. <a href="https://i.stack.imgur.com/f6ZjJ.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/f6ZjJ.png" alt="enter image description here" /></a> <a href="https://i.stack.imgur.com/1HGqz.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/1HGqz.png" alt="enter image description here" /></a> <a href="https://i.stack.imgur.com/9nOG0.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/9nOG0.png" alt="enter image description here" /></a> <a href="https://i.stack.imgur.com/OweWs.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/OweWs.png" alt="enter image description here" /></a> <a href="https://i.stack.imgur.com/EELQw.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/EELQw.png" alt="enter image description here" /></a> <a href="https://i.stack.imgur.com/sWhsY.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/sWhsY.png" alt="enter image description here" /></a> <a href="https://i.stack.imgur.com/MITkD.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/MITkD.png" alt="enter image description here" /></a> <a href="https://i.stack.imgur.com/Nfw1T.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/Nfw1T.png" alt="enter image description here" /></a> <a href="https://i.stack.imgur.com/loUAA.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/loUAA.jpg" alt="enter image description here" /></a> <a href="https://i.stack.imgur.com/lAjz4.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/lAjz4.png" alt="enter image description here" /></a> <a href="https://i.stack.imgur.com/qkckn.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/qkckn.png" alt="enter image description here" /></a> <a href="https://i.stack.imgur.com/3wfTD.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/3wfTD.png" alt="enter image description here" /></a> <a href="https://i.stack.imgur.com/1eExS.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/1eExS.png" alt="enter image description here" /></a></p>

<p>While reading Shenkman's <em>Transient Analysis of Electric Power Circuits</em> I came across the following problem:</p> <blockquote> <p>... This circuit represents the equivalent of a d.c. supply network. At the instant of time <span class="math-container">\$t=0\$</span>, the short-circuit fault occurs at node ‘‘<span class="math-container">\$a\$</span>’’ and when the short-circuit current <span class="math-container">\$i_{\text{sc}}\$</span> through the breaker reaches the value <span class="math-container">\$I=500 \text A\$</span>, the circuit breaker opens practically instantaneously. Find the transient response of current <span class="math-container">\$i_2\$</span> after the fault. The circuit parameters are <span class="math-container">\$R_1 =1 \text{ Ohm}, R=R_2 =9 \text{ Ohm}, L_1 =0.01 \text{H}, L_2 = 0.45 \text{H}\$</span> and <span class="math-container">\$V_s =1100 \text{V}.\$</span> <a href="https://i.stack.imgur.com/uIph5.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/uIph5.png" alt="fig2,18" /></a> First stage (the period between a short circuit <span class="math-container">\$t=0\$</span> and opening the circuit breaker, BR, <span class="math-container">\$t=t\$</span> Since the circuit is divided into two sub circuits: the left one with current <span class="math-container">\$i_1\$</span> and the right one with current <span class="math-container">\$i_2\$</span> , we shall obtain two time constants and two natural responses: ... <span class="math-container">\$i_{1,n}=A_1e^{−100t}\$</span>, <span class="math-container">\$i_{2,n}=A_2e^{−20t}\$</span>. The forced responses in these circuits are: <span class="math-container">\$ (1) i_{1,f}= V_s/ R_1 =1100/ 1 =1100 \text{A}, (2) i_{2,f} =0.\$</span> The initial conditions of the above two currents may be obtained by inspection of the given circuit prior to short-circuiting: <span class="math-container">\$ (1) i_1(0−)= V_s/\big(R_1+ (R2||R3)\big) =200 \text{A}, (2) i_2(0−) = i_1 (0 −)/2=100 \text{A}. \$</span></p> </blockquote> <p>Now reading the above analysis for currents at <span class="math-container">\$t=0-\$</span> and <span class="math-container">\$t=0+\$</span> I could think of the following circuits, as <span class="math-container">\$t \to \infty\$</span>, the circuit breaker opens at some point disconnecting the middle branch and the inductances are now in series, but the author suggests somehow the entire right branch is opened. I can't understand that.:<a href="https://i.stack.imgur.com/awDhr.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/awDhr.png" alt="enter image description here" /></a></p>

Transient analysis in presence of faults

2024-02-08T07:48:12.903

700643

|fpga|dac|hdl|

<p>The number of LUT values corresponds simply to the temporal resolution of your output waveform. So if you have an 8-bit LUT, your output waveform cannot be more accurate than 256 steps if reading directly from the LUT, and will have less resolution when outputting at higher frequencies.</p> <p>The frequency of the DDS output waveform is controlled by how fast you increment your phase accumulator. If you set the phase accumulator to increment at one LUT value per cycle, then the frequency of the output waveform will be simply the sample rate divided by the number of LUT entries. If you increased to incrementing by two LUT addresses per cycle, you double the output waveform frequency.</p> <p>The beauty of DDS is that it allows you to also increment by fractional values to control the waveform frequency - however doing so also introduces jitter and spurious frequencies into the output waveform. This is because the fraction position within the LUT gets rounded to the nearest sample. This is where having more entries in the LUT helps somewhat - the maximum frequency drops, but the temporal resolution increases - you get less rounding of the phase accumulator value.</p> <p>To output at lower frequencies, you need to add additional resolution to the phase accumulator value. This could mean increasing the length of the LUT, but that becomes impractical at lower frequencies as you have found out. Instead, you keep the LUT size the same, but still increase the phase accumulator bit size. To select the output value, you simply truncate the lower bits of the phase value when feeding into the LUT. This has the effect of reading the same sample repeatedly, giving you a stepped waveform.</p> <p>Of course for very accurate waveforms, or much lower frequencies, a stepped waveform is undesirable. As such you can start doing some linear approximations to increase the output resolution. A simple linear interpolator can be made by taking your phase accumulator value, and reading two samples from the LUT, one either side of the value, then interpolate between the two.</p> <p>Lets say your LUT is 10bit, and your accumulator is 16bit:</p> <ol> <li><p>Set <code>x1 = accum[15:6]</code> and <code>x2 = x1 + 1</code>.</p> </li> <li><p>Read from addresses <code>x1</code> and <code>x2</code> from your LUT. This gives you the bounding points for the sample value <code>y1 = LUT[x1]</code> and <code>y2 = LUT[x2]</code>.</p> </li> <li><p>Your output value is then linearly interpolated between the two values:</p> <p><code>y = (y1 * (64 - accum[5:0])) + y2 * accum[5:0])</code></p> </li> </ol>

<p>VLSI/FPGA beginner here.</p> <p>I interfaced my Digilent Arty A7-35 with a DAC, using basic DDS (implementing timing diagram of the DAC on FPGA) and interfacing LUT(s) to form sine waves of multiple frequencies.</p> <p>Trouble is, as LUT values increase, the output frequency of the sine wave decreases, exponentially.</p> <p>Below is the graph plotted in Excel:</p> <p>[![enter image description here][1]][1]</p> <p>I have observed that the output sine waveform becomes smoother with an increase in LUT values, which is obvious due to an increase in precision, and a decrease in the number of jumps between values. However, a professor informed me that there is no certainty that frequency will <em>definitely</em> decrease with an increase in the number of LUT values, but rather that there will be a change.</p> <p>There are two problems that I am facing:</p> <ol> <li>My observations after increasing LUT values to 2^16, contradict the professor (not completely, but as of now, it is definitely decreasing).</li> <li>I need to produce a sine wave of less frequency with a lower number of LUT values, because of memory constraints.</li> </ol> <p>My questions:</p> <ol> <li>What is the relation between LUT values and output frequency?</li> <li>Is it possible to produce a sine wave of lower frequency with lesser LUT values?</li> </ol> <p>I could think of one solution: Induce a delay between sending data to the DAC, by which I can space out the data, thereby causing frequency to decrease, but implementing this would be a hassle.</p> <p>Additionally, reducing the number of LUT values could help reduce timing issues.</p>

What is the relation between number of LUT values and output frequency?

2024-02-08T09:52:19.573

700647

|circuit-analysis|ac|fourier|

<p>While the main applications of the Fourier Transform (FT) in Electrical Engineering are mainly related to the frequency response of systems and filtering, it can also be used in circuit analysis, as long as certain conditions apply to the input signals. Instead of saying that FT has <strong>disadvantages</strong>, we can say that it has <strong>limitations</strong>. The three Dirichlet conditions are sufficient for FT to exist. The main one is that the signal is absolutely integrable over an infinite interval:</p> <p><span class="math-container">$$\int_{-\infty }^{\infty }\left| x(t) \right|dt&lt;\infty $$</span></p> <p>But it's worth repeating, these are sufficient conditions, but <strong>not necessary</strong>. Some signals that do not satisfy the conditions can still be considered to have a FT, if <strong>impulse functions</strong> are allowed in the transform (e.g. step input, sine,...).</p> <p>As well stated by Prof. B.P. Lathi:</p> <blockquote> <p>Any signal that can be generated in practice satisfies the Dirichlet conditions and therefore has a Fourier Transform. Therefore, the physical existence of a signal is a sufficient condition for the existence of its transform.</p> </blockquote> <p>Put another way: Has anyone ever seen an ramp voltage extending to infinite in time?</p> <p>Another limitation of FT is its difficulty in dealing with initial conditions. As the Laplace transform does not have these limitations, it may be preferable in circuit analysis. But the solution via FT can be useful to the student who is learning.</p> <p><strong>THE MODEL</strong></p> <p><a href="https://i.stack.imgur.com/7uqUj.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/7uqUj.png" alt="enter image description here" /></a></p> <p>Here, instead of obtaining the expression for the output using the impedance of the components, as is traditionally done, I preferred the approach from the associated differential equation. You can ignore this if you wish.</p> <p><span class="math-container">$$v_i(t)-Ri_L(t)-\frac{1}{C}\int_{-\infty}^{t}i_L(\varsigma)d\varsigma-v_o(t)= 0$$</span></p> <p>Deriving with repect to <span class="math-container">\$t\$</span>:</p> <p><span class="math-container">$$\frac{dv_i(t)}{dt}-R\frac{di_L(t)}{dt}-\frac{i_L(t)}{C}-\frac{dv_o(t)}{dt}= 0$$</span></p> <p>Trying to use the relation <span class="math-container">\$i_L(t)=C\frac{dv_c(t)}{dt}\$</span> won't help here. So, deriving one more time:</p> <p><span class="math-container">$$\frac{dv_i^2(t)}{dt^2}-R\frac{di^2_L(t)}{dt^2}-\frac{1}{C}\frac{di_L(t)}{dt}-\frac{d^2v_o(t)}{dt^2}= 0$$</span></p> <p>Now, we can use <span class="math-container">\$\frac{di_L(t)}{dt}=\frac{v_o(t)}{L}\$</span>:</p> <p><span class="math-container">$$\frac{dv^2_o(t)}{dt^2}+\frac{R}{L}\frac{dv_o(t)}{dt}+\frac{1}{LC}v_o(t)= \frac{dv^2_i(t)}{dt^2}$$</span></p> <p>Taking the FT from both sides:</p> <p><span class="math-container">$$(j\omega)^2V_o(\omega)+\frac{R}{L}j\omega V_o(\omega)+\frac{1}{LC}V_o(\omega)=(j\omega)^2V_i(\omega)$$</span></p> <p>The output, along with the Transfer Function, is:</p> <p><span class="math-container">$$V_o(\omega)=\frac{(j\omega)^2}{(j\omega)^2 + \frac{R}{L}j\omega+\frac{1}{LC}}V_i(\omega) \qquad[1]$$</span></p> <p><strong>THE INPUT</strong></p> <p>Consider the Fourier Transform properties, named linearity and time shifting, as shown below:</p> <p><a href="https://i.stack.imgur.com/H8php.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/H8php.png" alt="enter image description here" /></a></p> <p>In our case, <span class="math-container">\$A=10 V\$</span>, <span class="math-container">\$a=2.5 s\$</span> and <span class="math-container">\$\tau=1.5 s\$</span>.</p> <p><span class="math-container">$$V_i(\omega)=20e^{-j1.5\omega}\frac{\sin(2.5\omega)}{\omega}$$</span></p> <p><strong>THE OUTPUT</strong></p> <p>Replacing <span class="math-container">\$V_i(\omega)\$</span> in <span class="math-container">\$[1]\$</span>:</p> <p><span class="math-container">$$V_o(\omega)=\frac{20(j\omega)^2e^{-j1.5\omega}}{(j\omega)^2+1.25j\omega+2.5}\frac{\sin(2.5\omega)}{\omega} $$</span></p> <p>Taking in account that:</p> <p><span class="math-container">$$\sin(2.5\omega)=\frac{e^{j2.5\omega}-e^{-j2.5\omega}}{2j}$$</span></p> <p><span class="math-container">$$V_o(\omega)=\frac{10j\omega( e^{j\omega}-e^{-4j\omega})}{(j\omega)^2+1.25j\omega+2.5}$$</span></p> <p>In order to get the response <span class="math-container">\$v_o(t)\$</span> (ie the inverse Fourier Transform) it's simpler to use the form below. Start rewriting it as:</p> <p><span class="math-container">$$V_o(\omega)=F(\omega)\left( e^{j\omega}-e^{-4j\omega}\right) \qquad[2]$$</span></p> <p>where:</p> <p><span class="math-container">$$F(\omega)=\frac{10j\omega}{(j\omega)^2+1.25j\omega+2.5}$$</span></p> <p>That's convenient, since the exponentials in <span class="math-container">\$[2]\$</span> are highlighted to apply the time shifting property later.</p> <p>Replacing <span class="math-container">\$j\omega\$</span>, for another variable, like <span class="math-container">\$j\omega=v\$</span>:</p> <p><span class="math-container">$$F(v)=\frac{10v}{v^2+1.25v+2.5}$$</span></p> <p>Since the roots of denominator are complex conjugates, I'm going to prepare the expression to get inversion based on <span class="math-container">\$sine(.)\$</span> and <span class="math-container">\$cosine(.)\$</span> functions, along with the method <strong>completing the square</strong>:</p> <p><span class="math-container">$$F(v)=10\left[\frac{v+0.625-0.625}{(v+0.625)^2+1.452^2}\right]$$</span></p> <p><span class="math-container">$$F(v)=10\left[ \frac{v+0.625}{(v+0.625)^2+1.452^2}- 0.4304\frac{1.452}{(v+0.625)^2+1.452^2}\right]$$</span></p> <p>Substituting this result into <span class="math-container">\$[2]\$</span> and replacing <span class="math-container">\$v=j\omega\$</span>:</p> <p><span class="math-container">$$ \begin{align} V_o(\omega)=&amp;\left[ 10\frac{j\omega+0.625}{(j\omega+0.625)^2+1.452^2}- 4.304\frac{1.452}{(j\omega+0.625)^2+1.452^2}\right]e^{j\omega}+\\ &amp;\left[-10\frac{j\omega+0.625}{(j\omega+0.625)^2+1.452^2} + 4.304\frac{1.452}{(j\omega+0.625)^2+1.452^2}\right]e^{-j4\omega} \end{align} $$</span></p> <p>Considering the the table below</p> <p><a href="https://i.stack.imgur.com/Ua7NN.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/Ua7NN.png" alt="enter image description here" /></a></p> <p>and applying the time shifting property, we can complete the inversion to time domain:</p> <p><span class="math-container">$$ \begin{align} v_o(t)=&amp;e^{-0.625(t+1)} \left\{10\cos\left[1.452(t+1)\right]-4.304\sin\left[1.452(t+1) \right] \right\}u(t+1)+\\ &amp;e^{-0.625(t-4)} \left\{-10\cos\left[1.452(t-4)\right]+4.304\sin\left[1.452(t-4) \right] \right\}u(t-4) \end{align} $$</span></p> <p>We can get a smaller form by replacing each pair of <span class="math-container">\$sine(.) \pm cosine(.)\$</span> of same frequency) for just one <span class="math-container">\$cosine\$</span> with a phase shift:</p> <p><span class="math-container">$$ \begin{align} v_o(t)=&amp;\left[10.89e^{-0,625(t+1)}\cos(1.452t+0.592\pi)\right]u(t+1)+\\ &amp;\left[10.89e^{-0,625(t-4)}\cos(1.452t-0.719\pi)\right]u(t-4) \end{align} $$</span></p> <p>A plot showing the pulse <span class="math-container">\$v_i(t)\$</span> and the corresponding response <span class="math-container">\$v_o(t)\$</span>:</p> <p><a href="https://i.stack.imgur.com/LgEo9.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/LgEo9.png" alt="enter image description here" /></a></p>

<p>I was trying to calculate output voltage across the inductor in the RLC circuit below. I had used the Fourier transform to convert input signal <span class="math-container">\$V_{i}(t)\$</span> which is a single rectangular wave pulse in time domain and I also calculated the transfer function of the circuit as <span class="math-container">$$h(jω) = \frac{V_{o}(jω)}{V_{i}(jω)}$$</span> and the output voltage in frequency domain as <span class="math-container">$${V_{o}(jω)} = {V_{i}(jω)} h(jω) $$</span> The transfer function is in terms of impedance in the circuit and the angular frequency ω. When I calculated the inverse fourier transform of <span class="math-container">\$V_{o}(jω)\$</span> using the equation below, I am getting complex terms in the integration result. I had used Wolfram alpha integral evaluator for this.The integral evaluation seems complex and it is not really a plausible result. Is the method of Fourier analysis really correct and how does one evaluate the complex integral from -∞ to +∞ in inverse Fourier transform? I had briefly shown the steps I obtained in calculating the fourier transform of output voltage as below.</p> <p>Equation to calculate inverse fourier transform is</p> <p><span class="math-container">$$V_{o}(t) = \int_{-∞}^{+∞} v_{o}(jw) e^{jwt}dω$$</span></p> <p>R = 1Ω, C = 500 mF and L = 800 mH in the circuit.</p> <p><a href="https://i.stack.imgur.com/zJ88J.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/zJ88J.jpg" alt="enter image description here" /></a></p>

Fourier circuit analysis of a RLC circuit

2024-02-08T10:24:59.103

700658

|microcontroller|stm32|embedded|uart|transmitter|

<p>Most likely the code is fine, and the problems are receiving the data in hardware or software.</p> <p>You are using a 5V Arduino with Atmega16U2 as the USB to serial adapter for a (likely) 3.3V signal. It should work but not all STM32 pins are 5V tolerant and it might cause the Atmega16U2 to output excessive current trying to push 5V into STM32 which tries to clamp the overvoltage with internal protection diodes to supply.</p> <p>You would be far better off with a USB to serial adapter with IO voltage that matches the STM32 supply, and trying another terminal program.</p> <p>But it is still possible the problem is in the code. You have a completely custom framework nobody knows anything about, auto-generating some register access code, and you are posting only pseudocode.</p> <p>There is just too many variables and you need to eliminate things one by one, for example by verifying with an oscilloscope or logic analyzer if there really is only one byte coming out, or debug the code by stepping it through.</p>

<p>For some context I'm using a STM32H7A3 chip: <a href="https://www.st.com/resource/en/reference_manual/rm0455-stm32h7a37b3-and-stm32h7b0-value-line-advanced-armbased-32bit-mcus-stmicroelectronics.pdf" rel="nofollow noreferrer">reference manual</a></p> <p>With this UART and pin configuration:</p> <pre><code>GPIOB.OSPEEDR.OSPEED9 = 0b10 // usart_ker_ck_pres(8MHz) = usart_ker_ck(64MHz) / PRESCALER(8) UART4.PRESC.PRESCALER = 0b0100 // 1 start bit, 8 data bits UART4.CR1.M0 = 0 UART4.CR1.M1 = 0 // baud(9600) = usart_ker_ck_pres(8MHz) / USARTDIV(833) UART4.BRR.BRR = 0x0341 // 1 stop bit UART4.CR2.STOP = 0 // Enable UART UART4.CR1.UE = 1 // Enable transmit UART4.CR1.TE = 1 </code></pre> <p>in addition to the relevant clocks enabled and pin alternative function.</p> <p>Now sending a string of characters by waiting for <code>UART4.ISR.TXE</code> and writing to <code>UART4.TDR</code> for each character results in only the first character being actually sent. In pseudocode:</p> <pre><code>function transmit(message) { for byte in message { while UART4.ISR.TXE == 0 { // wait } UART4.TDR.TDR = byte } } </code></pre> <p>What might be a hint is that if I wait for some time after sending each character, it works, but obviously it's slower. Essentially sending a &quot;first character&quot; repeatedly:</p> <pre><code>function transmit(message) { for byte in message { while UART4.ISR.TXE == 0 { // wait } UART4.TDR.TDR = byte delay(100000) } } </code></pre> <p>A possibly relevant piece of additional information is that I'm using an arduino UNO with RST connected to GND as a serial to USB converter, and I'm using arduino-cli to monitor the serial connection on my pc.</p>

Why would a UART only transmit the first character and then stop?

2024-02-08T11:33:13.973

700659

|solenoid|contactor|

<p>Here is some <a href="http://www.imajteknik.com.tr/ravioli-t106-t156-T206-single-pole-dc-contactor" rel="nofollow noreferrer">technical data</a> for a product that looks very similar in markings, save for the manufacturer or supplier logo which is a very Italian &quot;Ravioli&quot; rather than &quot;Quick&quot;.</p> <p>They claim it has a feature for quick drop-out and slow pull in for reversing applications. Also the coil appears to be intermittent duty only (80% duty cycle maximum) as marked on your unit- coil dissipation is a hefty 20W. Maximum on-time 15 minutes.</p> <p>Your &quot;Bobina&quot; (coil) is 12V.</p> <p>150A is the maximum continuous current (limited by heating) and it can break 720A.</p> <p>&quot;Class 300 - 50%&quot; appears to mean maximum 300 operations per hour at 50% of rated current (not sure whether it's 50% of the 150A or the higher 180A intermittent rating).</p> <p>As with all ratings, it's best to stay well away from the maximums if you want long and reliable life span. No indication is given (that I can see) of the expected life in the webpage or pdf document that are linked. The 'mechanical life' of 2,000,000 operations is with zero load and is basically how long it takes to shake itself to death. Electrical life will likely be much, much fewer operations (could be as low as thousands or as high as 50,000 or 100,000) and very much dependent on load current and nature of the load.</p>

<p>This is a solenoid from an Italian made marine windlass.</p> <p>Could you please help me understand the specifications written on it?</p> <p><a href="https://i.stack.imgur.com/qzKAJ.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/qzKAJ.jpg" alt="enter image description here" /></a></p> <p>From what I know, the coil and connector is 12V because that is the voltage on the connections.</p> <p>It was hooked up to an Optima Red Top battery for operations.</p>

How do I read the specifications on this DC contactor?

2024-02-08T11:34:27.643

700700

|digital-logic|verilog|system-verilog|synthesis|rtl|

<p>Your example, and the standard <code>negedge rstN</code> do <strong>not</strong> have the same behaviour. Let's see why.</p> <hr /> <p>I assume we are trying to make a positive edge clocked D-FF with an asynchronous active-low reset. So lets start building up the desired behaviour. The first thing we need is to have an output, <code>q</code>, change whenever there is a positive clock edge:</p> <pre><code>always @(posedge clk) q &lt;= d; </code></pre> <p>As I'm sure you know, this simply states, at the positive edge of a <code>clk</code>, <code>q</code> is updated to equal <code>d</code>. Great, that's the expected behaviour of a D-FF.</p> <p>Now we want to add in a reset:</p> <pre><code>always @(posedge clk) if (!rstN) q &lt;= 0; else q &lt;= d; </code></pre> <p>When the block is executed, which at the moment is posedge of <code>clk</code>, then if <code>rstN</code> is low, the output <code>q</code> will be set to 0, otherwise it will still set <code>d</code>. Great, we have a reset behaviour. However this only happens at the positive edge of the clock, it's a synchronous reset.</p> <p>To make it asynchronous, we need to trigger the block when the reset signal needs to be handled. We have two ways of triggering an always block, level sensitivity and edge sensitivity.</p> <p>Let's look at what level sensitivity implies, your example:</p> <pre><code>always @(posedge clk or rstN) if (!rstN) q &lt;= 0; else q &lt;= d; </code></pre> <p>When <code>rstN</code> goes low, the block executes, regardless of whether there is a clock edge (hurray, async reset). <code>q</code> is set to <code>0</code>, because <code>rstN</code> is low.</p> <p>Now what happens if <code>rstN</code> goes high? The block executes again! <code>q</code> is now set to <code>d</code> because <code>rstN</code> is high. Argh! This is not the behaviour we want, the D-FF has just changed its output in response to the reset being released!</p> <p>Instead we will try edge sensitivity:</p> <pre><code>always @(posedge clk or negedge rstN) if (!rstN) q &lt;= 0; else q &lt;= d; </code></pre> <p>When <code>rstN</code> goes low, the block executes, regardless of whether there is a clock edge (hurray, async reset). <code>q</code> is set to <code>0</code>, because <code>rstN</code> is low.</p> <p>Now what happens if <code>rstN</code> goes high? Absolutely nothing. <code>q</code> retains its reset value. Problem solved, de-assertion of the reset no longer causes the D-FF to change its output state.</p> <p>So to get an async reset, we must use edge sensitivity for both clock and reset.</p> <hr /> <p>Perhaps though, you want the behaviour of clock on release of the reset. This is not the usual behaviour for our standard circuit elements. To implement this in hardware would require a more complicated circuit than a simple DFF. Something like:</p> <pre><code>reg qsel; reg qclk; reg qrst; // Detect first posedge-clock after reset always @ (posedge clk or negedge rstN) if (!rstN) qsel &lt;= 0; else qsel &lt;= 1; // Normal D-FF always @ (posedge clk or negedge rstN) if (!rstN) qclk &lt;= 0; else qclk &lt;= d; // Shadow D-FF used to load d when exiting reset always @ (posedge rstN) qrst &lt;= d; // When reset is released, but before first clock // occurs, output the value clocked by reset release, // otherwise use normal D-FF output. assign q = (rstN &amp;&amp; !qsel) ? qrst : qclk; </code></pre> <p>I haven't simulated it, and would make for a terrible circuit implementation, but that is in essence what would have to be inferred from your design.</p> <p>The question is, is that a construct which would be of much general use? Probably not. In which case there is little point in the synthesis tools being able to directly infer it.</p>

<p>In a number of sources I've come across, it's mentioned that for sensitivity lists which include an &quot;edge&quot;, you cannot include other signals in the sensitivity list if you want synthesis to work.</p> <p>Thus, for example, consider the code below for an active-low asynchronous-reset DFF:</p> <pre><code>always @(posedge clk or rstN) if (!rstN) q &lt;= 0; else q &lt;= d; </code></pre> <p>This is legal syntactically and will simulate, but synthesis compilers will not accept it. Instead, one needs to use <code>negedge rstN</code>. The simulation will be the same, but now it will synthesize as expected.</p> <p>Why the prohibition by synthesis compilers against things like the snippet I gave above? Is there some fundamental aspect or ambiguity which makes parsing such a snippet hard for compilers?</p> <p>I follow that this is outside of what is a synthesizable construct but I am hoping to understand <em>why</em> that is. That is, I'm hoping to understand why the compiler would struggle with synthesizing this?</p> <hr /> <p><strong>Edit:</strong> After reading further, I should note that Sutherland does discuss exactly this case on page 289. Thus, we should emphasize two things: (1) As Tom says in the accepted answer, my snippet above does not even <em>simulate</em> correctly. (2) Even if it did simulate correctly (or, rather, even if we considered an analogous snippet which mixed signal levels with signal edges in the sensitivity list) we would not get the snippet to <em>synthesize</em> because it is a synthesis requirement that if <code>posedge</code> or <code>negedge</code> is used for one signal in a sensitivity list, then an edge must be specified for all signals in said sensitivity list.</p>

Why can't you mix edge signals with level signals in SystemVerilog for synthesis?

2024-02-08T17:15:18.190

700701

|digital-logic|verilog|system-verilog|rtl|

<p>In general synthesis tools don't care if you use blocking or nonblocking assignments to variables unless you try to read the same variable after writing to it in the same block. That determines if you need to use the old or new value of the variable. There are no problems doing multiple assignments to the same variable is the same always block as long as you use the same kind of assigment--last write wins.</p> <p>However there are problems mixing blocking and nonblocking assignments to the same variable that will create functional problems.</p> <p>The original example mixes synchronous and asynchronous in a single <code>always</code> block. If the <code>posedge clk</code> occurs first, a non-blocking assignment to <code>q</code> gets scheduled. But then a <code>negedge rstN</code> occurs the same time (a race in the same event region), <code>q</code> is set to 0. However the nonblocking assignment to q is still pending. The asynchronous reset gets ignored.</p> <p>This is an unfortunate consequence of current synthesis tool modeling styles requiring a variables be assigned from only a single <code>always</code> block. Verilog was originally designed to handle this with two seperate `always blocks.</p> <pre><code>always @(posedge clk) begin // synchronous behavior q &lt;= d; end always @(rstN) begin asynchronous behavior if (!rstN) assign q = 0; // procedural continuous assignment else deassign q; end </code></pre> <p>A number of synthesis tools used to support this modeling style, but they are now obsolete.</p> <p>Another problem is much simpler to describe</p> <pre><code>always @(posedge clk) begin flag &lt;=0; // default value if (condition) flag = 1; // will be overwritten by NBA end </code></pre> <p>This is syntactically legal, but will never behave correctly. Synthesis tools flag this as an error because it cannot set the flag to 1. Both assignments should be nonblocking.</p>

<p>In most intros to Verilog, it's basically stated as a law that &quot;blocking is for combinational and nonblocking is for sequential&quot;. That turns out to be a good rule of thumb because of how blocking and nonblocking statements work, but that's not a priori what blocking and nonblocking mean.</p> <p>In Stuart Sutherland's <em>RTL Modeling with SystemVerilog</em>, he writes that one of the prohibitions enforced by synthesis compilers on <code>always</code> procedural blocks aimed at achieving FF synthesis is that</p> <blockquote> <p>(6) A variable assigned a value in a sequential logic procedure cannot have a mix of blocking and nonblocking assignments. For example, the reset branch cannot be modeled with a blocking assignment and the clocked branch modeled with a non- blocking assignment.</p> </blockquote> <p>Thus, for instance, the code below for an active-low asynchronous-reset DFF would apparently not synthesize (correctly?):</p> <pre><code>always @(posedge clk or negedge rstN) if (!rstN) q = 0; // NB the blocking statement made here else q &lt;= d; </code></pre> <p>There is no problem from a simulation perspective given that the two branches of the <code>if-else</code> do not interact. Thus, my question is why doesn't synthesis accept/interpret this correctly? As far as I know, the point (6) above is also enforced by the <code>always_ff</code> block. Now that makes sense as a matter of good practice (since, as far as I know, <code>always_ff</code> etc. is meant to be for synthesis), but it still doesn't explain to me why in a general <code>always</code> block the above wouldn't work?</p> <p>I follow that this is outside of what is a synthesizable construct but I am hoping to understand <em>why</em> that is. That is, I'm hoping to understand why the compiler would struggle with synthesizing this?</p>

Why the prohibition against blocking statements in FF synthesis?

2024-02-08T17:28:02.863

700725

|sensor|capacitance|detection|water|

<p>You already have a ground reference. It's the circuit, and its power supply, and you.</p> <p>The problem is getting a sufficiently repeatable ground for the measurement such that the changes in capacitance are meaningful, ie dependent on the test electrode &lt;-&gt; water distance much more than the water &lt;-&gt; grounded things distance.</p> <p>It may be good enough that hold the tank with your hand, and earth yourself to the circuit's power supply.</p> <p>If you can put the plastic tank into a metal container and connect that to the circuit ground, that would be even better.</p>

<p>I need to detect the presence of water, but there is a catch. I can only have one single electrode contacting/submerged in water. It is in a mini-tank made of plastic (for a handheld device) so I cannot even have a ground probe with the tank.</p> <p>Could I somehow measure the change in capacitance of the electrode in water vs air? Is this possible without a ground reference point?</p> <p>I imagine some similar setup as this - <a href="https://docs.arduino.cc/tutorials/generic/capacitance-meter/" rel="noreferrer">https://docs.arduino.cc/tutorials/generic/capacitance-meter/</a></p> <p>Would this work without a ground reference to the water? Is there some other method that I can use with a single-electrode?</p> <p><a href="https://i.stack.imgur.com/O7CWP.png" rel="noreferrer"><img src="https://i.stack.imgur.com/O7CWP.png" alt="enter image description here" /></a></p>

Is it possible to do water detection with a single electrode?

2024-02-08T20:36:39.783

700726

|current|diodes|datasheet|reverse|

<p>Yes, you likely would violate the reverse voltage spec in that situation.</p> <p>Although &quot;maximum reverse voltage between all terminals&quot; (from the datasheet) isn't the most technical description one could imagine, it basically just means the maximum voltage that is allowed in opposition to the normal operating current flow, i.e. the maximum voltage from GND to OUT, or from OUT to REXT, etc.</p> <p>Putting a diode on the output should solve your issue as long as the leakage current isnt too high.</p>

<p>I don't quite understand the meaning of the reverse voltage (Vr) parameter of constant current sources.</p> <p>For example the <a href="https://www.diodes.com/assets/Datasheets/BCR401UW6.pdf" rel="nofollow noreferrer">Diodes Incorporated BCR401UW6.</a></p> <p>Suppose that at the OUT output of the IC there is a capacitor that is charging and reaches its maximum charge to the same input voltage. If I disconnect the input power supply suddenly, does it mean that I will have an inverse voltage Vr between the output and the input?</p> <p>If this is so, would it be sufficient to place a diode on the output?</p>

Reverse voltage parameter Vr in constant current regulators

2024-02-08T20:43:14.207

700728

|ltspice|leakage-current|sample-and-hold|

<blockquote> <p><em>Is there an obvious way to reduce this? Is this a function of the FET / op-amp used?</em></p> </blockquote> <p>The input bias current for the <a href="https://www.analog.com/media/en/technical-documentation/data-sheets/1800fa.pdf" rel="nofollow noreferrer">op-amp</a> is <strong>typically</strong> 25 nA and, that would cause the voltage across the sample capacitor (220 nF) to drift at a little over 100 mV / second. You can prove this by removing the op-amp and monitoring the voltage directly.</p> <p>There may also be a few nA leakage from the JFET.</p>

<p>I've built a sample and hold circuit on LTSpice, and the output will drift up at a rate of ~100mV/s. Is there an obvious way to reduce this? Is this a function of the FET / opamp used?</p> <p>The obvious choice would be to use a specific sample and hold IC, however part of this exercise is to build it from discreets + opamps.</p> <p>I have messed around with the simulation adding in resistances here and there, adjusting components to see a change, but got nowhere with it.</p> <p><a href="https://i.stack.imgur.com/6MWHq.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/6MWHq.png" alt="LTSpice Circuit Diagram of Filter" /></a> V3 is <code>PULSE(0 5 0.1 0.001 0.001 0.02 0.41 20)</code></p> <p><a href="https://i.stack.imgur.com/0gVjh.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/0gVjh.png" alt="Output Stream" /></a></p>

How to reduce sample and hold circuit drift

2024-02-08T20:48:59.700

700748

|pcb-design|transformer|power-electronics|symbol|footprint|

<p>They are specified. All your pads are identical. The dimensions of each pad are 1.27mm x 1.55mm. The reason every pad's dimensions aren't specified is would make drawing super messy. BTW, pins 3 and 8 are purely mechanical and don't have electrical connections. But they should still have pads for mechanical integrity.</p>

<p><a href="https://www.coilcraft.com/getmedia/fe569a42-533f-4322-ab3b-764883f54979/fct1xxm22sl.pdf" rel="nofollow noreferrer">FCT1-50M22SLD</a> Pads 3 and 8 are not specified, or am I incorrect?</p> <p>How would you link the footprint to the symbol, since no models are available for this?</p> <p><a href="https://i.stack.imgur.com/irSA0.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/irSA0.png" alt="enter image description here" /></a></p>

Transformer Pads not specified

2024-02-08T23:24:02.173

700752

|transistors|audio|switching|npn|

<p>I'm not sure I understood your requirements. I think you want a single switch to both control power to a bluetooth module, and change from radio to bluetooth audio.</p> <p>I know you asked for a transistor design, but that's non trivial. Instead here's a simple DPDT relay solution, which is more robust, and won't require complicated power supply conditioning to survive the evils of a typical automotive 12V supply:</p> <p><img src="https://i.stack.imgur.com/gOS39.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fgOS39.png">simulate this circuit</a> &ndash; Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a>}</p> <p>The relay coil is rated for 12V DC, your car's battery voltage.</p> <p>This requires an SPST (SW1) to operate the relay coil, the relay does the rest. One pair of relay contacts controls power to the bluetooth module, the other controls which audio source is selected.</p>

<p>I have what I hope to be a really simple question I have to ask now as it stopping me sleeping lol.</p> <p>I’ve added Bluetooth to a 1950s car radio, using 2 SPDT switches (one could be replaced with SPST for power to be fair.) Anyhow, 1 switch basically gives power to the Bluetooth module when pressed in.</p> <p>The other switch at the same time switches it from the Long/Medium wave audio signal to Bluetooth which is the two throws and the pole the audio output to the volume control.</p> <p>The volume control knob I’ve had to replace because of space issues however would rather use the original switch as it has better range of control on it, which could be done if I only had 1 SPDT switch that I currently have. I’ve never used transistors before but I believe they can used a switches, and that I could potentially use the 5v supply being switched on as the signal to also switch the audio signal electronically? Replacing the need for an SPDT switch?</p> <p>Can anyone give a diagram on how I would do this? As with the diagram I can learn alot for future projects and will hopefully understand.</p> <p>Thanks in advance.</p>

Switching between audio sources with transistors. Mimicking a SPDT switch

2024-02-09T00:37:00.303

700756

|datasheet|solid-state-relay|bias|

<p>First, the datasheet has a typo: note 1 refers to figure 4, not figure 5.</p> <p>Also, in note 1, it actually reads &quot;... Use the <strong>standard resistor value</strong> equal to or less than the value found in Figure [sic] 4&quot;. This is important to mention because you can't just pick an arbitrarily low resistor for your convenience or everyone would pick the degenerate case of &quot;zero ohm&quot; resistor.</p> <p>Now onto your questions. It is true that there is internal current limiting that takes place inside the device as you correctly observed from the plateau of the current graph in fig 3. The reason for this external resistor isn't for current limiting. The real reason is when you increase the voltage across a current-limited element (we call this the compliance voltage), that excess voltage turns into heat - the device isn't designed to handle the excess heat from high (&gt;6V) compliance voltages. Remember, the power dissipated is V x I. If I is fixed at the 25mA, then the power dissipated is proportional to the voltage dropped. So the idea is to use an external resistor to burn off the excess voltage and therefore the excess heat outside the SSR instead of inside the SSR.</p> <p>Why wouldn't they design it to handle the excessive voltage? Simply because of cost and/or market. Most users will use this with low (&lt;6V) bias voltages for most logic level controls. For those that don't, they're stuck with adding their own resistor to burn off heat. Sure the manufacture could include complete turnkey circuitry to handle the full voltage range (Crydom does this with their line), but it's a compromise.</p> <p>With the resistor, the 4.2 - 32VDC spec is the input BEFORE the resistor. Think, if that was the spec. after the resistor, you wouldn't need the resistor! However, the control input is still limited to 18V in the 3-terminal setup.</p> <p>Here's a more detailed block diagram on what's going on inside:</p> <p><img src="https://i.stack.imgur.com/MaqU5.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fMaqU5.png">simulate this circuit</a> &ndash; Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a>}</p>

<p>I am a bit confused by some of the specification on this solid state relay <a href="https://www.teledynedefenseelectronics.com/relays/Datasheets%20MSSR/LD00KM_Datasheet.pdf" rel="nofollow noreferrer">LD00KM</a>. I am looking at the case in which this relay is used in the 2 Terminal Input (Direct Drive) Configuration as shown in Figure 1 - B.</p> <p>Looking at the INPUT (CONTROL) SPECIFICATIONS Section (when used in the 2 terminal configuration) it lists the input supply range is 4.2 - 32 VDC, and it is accompanied by Note 1. Note 1 says that for any input voltages above 6 V a series resistor should be added in series with the bias. They tell you to pick a resistor equal to or less than that shown in Figure 5. My questions are as follows:</p> <ol> <li><p>What is the purpose of adding this resistor? Based on Figure 3, it looks like there is some sort of current limiting operation above ~5-6 V, but why have the resistor if there is already some limiting circuit?</p> </li> <li><p>With the addition of the resistor, does the Input Voltage Range they specify (4.2 - 32 VDC) apply to the voltage before the series resistor or to the voltage seen at the bias pin (after the resistor)?</p> </li> </ol>

Solid-state relay input characteristics

2024-02-09T02:25:22.017

700770

|batteries|power-electronics|battery-charging|lithium-ion|charger|

<p>No.</p> <p>If you try, <strong>KABOOM!</strong></p> <p>That's because they are not isolated. Upon connection, they make a short circuit across one Li-ion cell.</p> <blockquote> <p>Is there any way to make two of these modules do the job?</p> </blockquote> <p>Yes, but it's more expensive than buying the correct charger. It involves adding an isolated DC-DC converter between the USB port and one of the charger modules.</p>

<p>I need a solution to charge two 3.7 V lithium-ion cells that are in series. However I have a very limited access to modules and I need to have current limitation as my source won't stand beyond 0.5 A.</p> <p>I have this module available (TP4056 based), but it's for a single cell. Is there any way to make two of these modules do the job?</p> <p><a href="https://i.stack.imgur.com/RCLdE.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/RCLdE.png" alt="enter image description here" /></a></p> <p>Datasheet: <a href="https://dlnmh9ip6v2uc.cloudfront.net/datasheets/Prototyping/TP4056.pdf" rel="nofollow noreferrer">TP4056</a></p>

Can I use two of these modules to charge two lithium-ion cells that are in series?

2024-02-09T07:10:09.397

700775

|esd|swd|

<p>Note: The direction of D2 in your schematic is incorrect.</p> <p>You can calculate the resistors for R5 and R6 using the following information:</p> <ol> <li>Max injection/clamping current of the IO pin</li> <li>Max clamping voltage of the ESD protection diode at its peak clamping current</li> </ol> <p>The clamping voltage of the ESDALC6V1-1U2 at its peak pulse of 4A is around 12.5V. So <span class="math-container">$$ R &gt; \frac{12.5 - V_{CCIO}}{i_{INJ}} $$</span> where <span class="math-container">\$V_{CCIO}\$</span> is the voltage supply of the IO and <span class="math-container">\$i_{INJ}\$</span> is the maximum injection current of the IO pin.</p> <p>A side note: The ESD protection diodes should be placed very close to the entry point of the signals (close to the H4 connector).</p>

<p>I have connected two TVS diodes close to header, and Resistor for limiting the current.<br> Is it enough to protect the ports from ESD or i need to add anything else or correct this schematics?</p> <p><a href="https://i.stack.imgur.com/wyWsX.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/wyWsX.png" alt="enter image description here" /></a></p>

How can I protect MCU SWD portf from ESD?

2024-02-09T08:17:36.280

700784

|i2c|timing|

<p>I estimate that the rise time between 0.3×Vdd and 0.7xVdd is about 200ns. That also approximates the capacitance to be about 60pF.</p> <p>So it will violate timings of a 1 MHz FMPlus bus.</p> <p>But you are not running in FM+ mode because the clock is below 400 kHz so this is in Fast Mode range. It allows for 300ns rise time, so this should be within i2C specification.</p> <p>So I would say the rise time is OK. FMPlus chips are required to be downward compatible with slower bus modes.</p> <p>The clock pulse spends more than the required 600ns above 0.7×Vdd which is also OK for Fast Mode bus.</p> <ol> <li><p>I2C specs have different modes. The rise time specs are different e.g. within 0 to 100 kHz, 100 kHz to 400 kHz, and 400 kHz to 1MHz ranges.</p> </li> <li><p>You can but do not need to reduce the resistance to make the rise time faster if you work in Fast Mode. If you intend to make the clock faster and go into the Fast Mode Plus range and near 1 MHz, then you must reduce the resistance to meet the rise time requirement.</p> </li> </ol> <p>While the requirement is a requirement, generally, you also need to be reasonable. You don't need to go from 300ns to 120ns rise time just because you switched from 399 kHz to 401 kHz clock, in practice it is enough that you meet the pulse to be at least 500ns while meeting Vih of all chips. But, it is good to be strictly within specfications if you need to prove someone that the bus meets and is well within official specifications.</p>

<p>I am using a <a href="https://invensense.tdk.com/wp-content/uploads/2022/09/DS-000292-ICM-42605-v1.7.pdf" rel="nofollow noreferrer">ICM-42605</a> IMU in conjunction with a GNSS module, which has a blackbox firmware that realizes the communication with the IMU via I²C. I can see signs that the communication works fine, and can measure the lines directly.</p> <p>I noticed that the rising edge of the I²C pulses looks a bit 'overdamped' and despite things working fine, decided to investigate a bit. Here is an image of a measured clock pulse:</p> <p><a href="https://i.stack.imgur.com/9nMw3.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/9nMw3.png" alt="enter image description here" /></a></p> <p>The SDA and SCL pins are open drain and I have 3k3 resistors as pull-ups. The frequency can be up to 1MHz and seems to be 334kHz judging by the measurement. Also, the risetime of each pulse is about ~380ns, but the datasheet of the IMU specifies a maximum risetime of 120ns:</p> <p><a href="https://i.stack.imgur.com/8vNtD.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/8vNtD.png" alt="enter image description here" /></a></p> <p>Here are my questions:</p> <ol> <li><p>Is this maximum value fixed throughout frequencies? It seems to me that it would depend on the pulse width and, hence, why the circuit currently works as is.</p> </li> <li><p>Should I be looking to reduce the resistance values so as to reduce the risetime?</p> </li> </ol>

How to interpret maximum risetime on I²C communication timing specification

2024-02-09T09:48:05.950

700790

|ltspice|

<p>First, just to clarify your question, you're not talking about normal <code>.op</code> output of voltages and currents. You're talking about the calculated small-signal parameters for non-linear semiconductor devices that are spit out in the SPICE Error Log <kbd>CTRL+L</kbd> after a <code>.op</code> analysis.</p> <p>Anyway, I asked this same exact question to the then-author of LTspice (Mike Engelhardt) back in August 2018. Below is a copy/paste of my question and his answer.</p> <br> <p><strong>QUESTION</strong></p> <blockquote> <p>Hello. I was wondering if there's a way to get more significant digits when looking at the linearized small-signal parameters in the error log after a DC operating point analysis. Example output is below:</p> <pre><code>Direct Newton iteration for .op point succeeded. Semiconductor Device Operating Points: --- Diodes --- Name: d1 Model: 1n4148 Id: 8.25e-03 Vd: 6.84e-01 Req: 5.49e+00 CAP: 3.65e-09 </code></pre> <p>I tried changing a few of the significant digit items in the .options but that didn't affect this output. Is this controlled via a separate command?</p> <p>Thanks!</p> </blockquote> <br> <p><strong>ANSWER</strong></p> <blockquote> <p>There's no adjustment available. BTW, I've never seen a semiconductor model with three digit accuracy, either.</p> </blockquote> <p>TRANSLATION: No, there is no way to do this, but it shouldn't matter since the model parameters which are inputs to these calculations never have an accuracy higher than three digits to begin with.</p>

<p>The following is the circuit in LTspice.</p> <p><a href="https://i.stack.imgur.com/LhroQ.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/LhroQ.png" alt="enter image description here" /></a></p> <p>The following results only show 3 digits.</p> <pre><code> --- MOSFET Transistors --- Name: m1 Model: nmos-sh Id: 1.91e-04 Vgs: 7.96e-01 Vds: 9.03e-01 Vbs: 0.00e+00 Vth: 4.00e-01 Vdsat: 3.96e-01 Gm: 9.61e-04 Gds: 1.75e-05 Gmb: 0.00e+00 Cbd: 0.00e+00 Cbs: 0.00e+00 Cgsov: 0.00e+00 Cgdov: 0.00e+00 Cgbov: 0.00e+00 Cgs: 0.00e+00 Cgd: 0.00e+00 Cgb: 0.00e+00 </code></pre> <p>How can I make them display more than 3 digits?</p>

How can I have LTspice display more digits with .op command?

2024-02-09T11:05:44.000

700795

|microcontroller|power-supply|switch-mode-power-supply|ldo|review|

<p>IF uC operates on 5V then use a pulldown on EN and drive EN from the uC pin.</p> <p>If Vhi_uC is say 3V3:<br /> Use an NPN transistor.</p> <ul> <li>Connect collector to EN.</li> <li>Connect pullup to EN to Vdd_MCU5V as you have done now.</li> <li>Connect base to 3V3 via say 10k.</li> <li>Drive emitter from uC pin.</li> </ul> <p>This gives you a voltage upconverter with same polarity in and out.</p>

<p>I am using two regulators in my design. They need to be enabled by a microcontroller.</p> <p>The microcontroller is working at 5 V. The regualtor P/N is a <a href="https://www.ti.com/lit/ds/symlink/tps62160-q1.pdf" rel="nofollow noreferrer">TPS62160QDSGRQ1</a> and the microcontroller is an <a href="https://www.nxp.com/docs/en/data-sheet/S32K1xx.pdf" rel="nofollow noreferrer">FS32K148UJT0VLQT_LQFP_144L</a>.</p> <p>My schematic is given below. May I know your comments about it?</p> <p><a href="https://i.stack.imgur.com/9uhnY.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/9uhnY.png" alt="enter image description here" /></a></p>

Enabling power supply using microcontroller: schematic review

2024-02-09T11:16:46.170

700813

|connector|hardware|glue|

<p>No. No glue necessary. If done correctly, the 400 solder joints provide plenty retention.</p>

<p>I designed a debug card for the <a href="https://www.xilinx.com/products/boards-and-kits/ek-v7-vc707-g.html" rel="nofollow noreferrer">Virtex 7 FPGA VC707 Evaluation Kit</a></p> <p>My card has <a href="https://www.samtec.com/standards/vita/fmc/" rel="nofollow noreferrer">two large connectors Vita 57.1 (FMC-HPC)</a>. Each with 400 BGA pads.</p> <p>I was wondering, if I shoulod use any glue to keep the connector in place.</p> <p>Do you think the 400 pads are enough to hold the connectors in place? I'm connecting my debug board to the VC707, so I'm worried the connectors are going to come off of my board, when I pull my board off. I'm assembling my board by myself, so the connction might not have the best connection.</p> <p><a href="https://i.stack.imgur.com/XjIAk.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/XjIAk.png" alt="enter image description here" /></a></p> <p>The connetor has two asymmetric pins, only not to place the connetor 180° flipped. But these provide no stability</p>

Do I need to glue connectors to my debug board, so they don't come off?

2024-02-09T14:43:52.497

700821

|ddr4|

<blockquote> <p>Performance is very much dependent on the SW application and what type of transaction are used more often. in general the DDR bandwidth can be reduced going from x8 to x16, simply because x8 has 16 available open pages vs. x16 has 8 available open pages. the specific SW needs to be tested on the system to give you specific concrete results to determine the performance differences.</p> </blockquote> <p>Source: <a href="https://community.nxp.com/t5/Layerscape/LS1043-DDR4-memory-organization-x8-vs-x16/td-p/1686200" rel="nofollow noreferrer">https://community.nxp.com/t5/Layerscape/LS1043-DDR4-memory-organization-x8-vs-x16/td-p/1686200</a></p> <p>So it comes down to benchmarks and application and here is an example of that with benchmarks.</p> <p><a href="https://i.stack.imgur.com/9tKQy.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/9tKQy.png" alt="enter image description here" /></a> <a href="https://rkblog.dev/posts/pc-hardware/laptop-ddr4-caveats-x8-layout-versus-x16-versus-single-and-dual-channel/" rel="nofollow noreferrer">https://rkblog.dev/posts/pc-hardware/laptop-ddr4-caveats-x8-layout-versus-x16-versus-single-and-dual-channel/</a></p> <p>If you know your application and it can do better with more pages then use x8</p>

<p>I'm working on a design that has a 16 bit DDR4 memory controller and also has a reference schematic. The reference design has two separate x8 DDR4 memory devices connected to the controller DQ[0:7] and DQ[8:15], respectively, and both memory devices share the same address lines. What would be the practical difference between using two x8 DDR4 memory devices as in the reference schematic instead of one x16 DDR4 device that would be cheaper, considering that the final amount of memory is the same?</p>

Difference between using a single x16 DDR4 memory device or two x8 DDR4 memory devices

2024-02-09T16:14:20.680

700827

|capacitor|identification|

<p>CE 105<span class="math-container">\$^\circ\$</span>C is the temperature rating, electrolytic capacitors generally come in either 85<span class="math-container">\$^\circ\$</span>C or 105<span class="math-container">\$^\circ\$</span>C ratings.</p> <p>220 <span class="math-container">\$\mu\$</span>F is the capacitance in micro-Farads.</p> <p>WV is Working Voltage. This is the maximum continuous voltage that should be applied to the capacitor.</p> <p>I believe GM(M) is the capacitor series which is manufacturer specific.</p>

<p>Understanding markings as a beginner. I am getting educated on what electronic items do. I have no experience and want to learn. I was not able to find the info I am looking for on the general web.</p> <p><a href="https://i.stack.imgur.com/VrV6s.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/VrV6s.jpg" alt="enter image description here" /></a></p> <pre><code>Nichicon (manufacturer) CE 105C (temp range) 220 uf (micro farad) 160 wv (watt voltage) ? GM(M) (?) </code></pre>

Identification of marking on capacitor

2024-02-09T16:41:58.223

700838

|differential|transmission-line|high-speed|lvds|

<p>Does there have to be an air gap? You could put a thin thermal pad in there and vacuum bond the assemblies together. This should at least give you a more controlled height (H1) and dielectric constant so that you could adjust your line widths (W) and spacings (S) to give you the differential impedance you desire.</p>

<p>I have a 1.8 V, 350 MHz, 100 Ω LVDS signal on an FFC on the bottom plane. Below the FFC is an aluminum metal layer; the aluminum is pretty much unconnected from the FFC. The air gap/solder mask gap is currently a few thousands of an inch, maybe 1-3, but I could put some kapton tape underneath to ensure it's not a problem and widen that gap to whatever the thinkness of the tape is 10-20 mil.</p> <p>Will I have an issue with this changing the parameters of my transmission line more than say 5% or 10%?</p> <p>This is what the 'stakup' looks like. The aluminum has enough impedance from the diff pair that it could be considered as mostly disconnected at 350 MHz as it's not very capacitively coupled.</p> <p><a href="https://i.stack.imgur.com/humQL.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/humQL.png" alt="enter image description here" /></a></p> <p>I think the answer is no, because I assume this is like a edge coupled internal asymmetric differential pair.</p> <p>In the diagram below I have this upside down from the previous diagram where H1 is the coupled distance in the cable and H2 is the aluminum. The material says FR-4 but I have the Er plugged in for Kapton FFC, but I'm not sure because H2 is disconnected.</p> <p><a href="https://i.stack.imgur.com/e3uod.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/e3uod.png" alt="enter image description here" /></a></p>

Is a gap needed with LVDS with metal layer below it?

2024-02-09T18:10:03.290

700839

|power-electronics|battery-charging|lithium-ion|

<p>Proper battery management must handle many parameters, cases, and eventualities, most of which you didn't even know needed to be addresses. A design error can result in a fire, which is particularly scary in an EV. Therefore, I always recommend to buy an off-the-shelf BMS: well designed, cheaper, meets regulations, guaranteed to work, gets you up and running in hours, not months. For example, lately I have been impressed by the <a href="https://wattius.com/web/" rel="nofollow noreferrer">Wattius BMS</a>.</p> <p>Also, consider an off-the shelf Li-ion battery with an integral BMS. There are <a href="https://www.google.com/search?q=12V+50AH+Li-ion+battery" rel="nofollow noreferrer">many off-the-shelf 12 V 50 Ah Li-ion batteries</a>, including <a href="http://en.topakpower.com/product-center/2302.html" rel="nofollow noreferrer">some with I2C communications</a>.</p>

<p>We have been asked to design a Battery management system that gets the state of charge while plugged in or not for a prototype EV with 5 batteries in series each 12 V 50 Ah. I've tried looking for such a project online and on youtube but couldn't find anything to help me or I just didn't get it</p> <p>I did extensive research on how to charge lithium-ion batteries, to charge the 5 batteries in the shortest amount of time safely, I decided to charge them at 60 V and 10 A.</p> <p>I'm focusing mostly on the main challenge of getting the state of charge, I have been actively searching for an IC on the market(for 2 weeks now) mostly from JLCPCB and I'm also looking at Texas Instruments ,that can handle 60 V at 10 A . It must also have SDA for I2C communication so that I can hook it up to a microcontroller which would give me charge state of charge, using this data to open the circuit with a relay when the battery is full(also to display the battery percentage).</p> <p>Here's what I found what I found:</p> <p>1. <a href="https://www.analog.com/media/en/technical-documentation/data-sheets/29411f.pdf" rel="nofollow noreferrer">https://www.analog.com/media/en/technical-documentation/data-sheets/29411f.pdf</a></p> <p>This IC can handle 60 V but I think it can't handle currents above 800 mA-1 A unless I didn't read it right</p> <p>2. <a href="https://datasheet.lcsc.com/lcsc/1805311218_Analog-Devices-LTC4013EUFD-PBF_C107935.pdf" rel="nofollow noreferrer">https://datasheet.lcsc.com/lcsc/1805311218_Analog-Devices-LTC4013EUFD-PBF_C107935.pdf</a></p> <p>I was excited to find this one because it met my needs but it doesn't seem to support SDA I2C communication , And from the data sheet I can't seem to find any other way to get the SOC</p> <p>I'm still searching but:</p> <ul> <li>what charge voltage or current would you propose?</li> <li>Is using such an IC for this single task the best method or is their a tradition method that works?</li> <li>Do you know of any IC's that can do the job?</li> </ul>

Designing a Battery Management System

2024-02-09T18:31:29.067

700842

|mosfet|analog|design|cmos|calculus|

<p>I'm going to ignore the <span class="math-container">\$V_{_\text{THN}}\$</span> term and focus on the remaining term, which is a product of two functions.</p> <p>If you have the product of two functions, call them <span class="math-container">\$P\$</span> and <span class="math-container">\$Q\$</span>, so that <span class="math-container">\$F=Q\cdot P\$</span>, then the product rule would have:</p> <p><span class="math-container">$$\begin{align*} \text{d} F&amp;= P\cdot\text{d} Q+Q\cdot\text{d} P \\\\ &amp;= \frac{Q}{Q}\cdot P\cdot\text{d} Q+\frac{P}{P}\cdot Q\cdot\text{d} P \\\\ &amp;= Q\cdot P\cdot\frac{\text{d} Q}{Q}+P\cdot Q\cdot\frac{\text{d} P}{P} \\\\ &amp;= Q\cdot P\cdot\left[\frac{\text{d} Q}{Q}+\frac{\text{d} P}{P}\right]\tag{1}\label{eq:1} \end{align*}$$</span></p> <p>The way to read the above Eq. \ref{eq:1} is to think: <em>&quot;The differential change in the product of <span class="math-container">\$Q\$</span> and <span class="math-container">\$P\$</span> is that same product times the sum of the %-change in <span class="math-container">\$Q\$</span> plus the %-change in <span class="math-container">\$P\$</span>.&quot;</em></p> <p><em>(Note that I've not yet actually taken the derivative with respect to any other infinitesimal. In fact, I don't yet even know what <span class="math-container">\$P\$</span> and <span class="math-container">\$Q\$</span> are functions of. And I don't care. This is how I prefer to perform calculus. I don't know anything about <span class="math-container">\$P\$</span> or <span class="math-container">\$Q\$</span> except that they may yet become functions of something. Yet I have already been able to say something useful about the differential of their product!)</em></p> <p>In your specific case:</p> <p><span class="math-container">\$P\$</span> is a function of <span class="math-container">\$K\$</span>, so write: <span class="math-container">\$P_{_\text{K}}=1-\frac1{\sqrt{K}}\$</span>.</p> <p><span class="math-container">\$Q\$</span> is a function of <span class="math-container">\$R\$</span>, so write: <span class="math-container">\$Q_{_\text{R}}=\frac2{\beta_1\,R}\$</span>.</p> <p><span class="math-container">$$\begin{align*}\require{cancel} \text{d} F&amp;= Q\cdot P\cdot\left[\frac{\text{d} Q}{Q}+\frac{\text{d} P}{P}\right] \\\\ \frac{\text{d} F}{\text{d}\,T}&amp;= Q_{_\text{R}}\cdot P_{_\text{K}}\cdot\left[\frac{\frac{\text{d}\, Q_{_\text{R}}}{\text{d}R}}{Q_{_\text{R}}}\cdot\frac{\text{d}\,R}{\text{d}T}+\frac{\frac{\text{d}\, P_{_\text{K}}}{\cancel{\text{d}K}}}{P_{_\text{K}}}\cdot\frac{\cancel{\text{d}\,K}}{\text{d}T}\right] \\\\ &amp;\quad\quad\text{substituting, } \frac{\frac{\text{d}\, Q_{_\text{R}}}{\text{d}R}}{Q_{_\text{R}}}=-\frac1{R} \\\\ &amp;= Q_{_\text{R}}\cdot P_{_\text{K}}\cdot\left[\frac{-\text{d}\,R}{R}\cdot\frac{1}{\text{d}T}+\frac{\text{d}\, P_{_\text{K}}}{P_{_\text{K}}}\cdot\frac{1}{\text{d}T}\right]\tag{2}\label{eq:2} \\\\ &amp;= Q_{_\text{R}}\cdot P_{_\text{K}}\cdot\left[\frac{-\text{d}\,R}{R}+\frac{\text{d}\, P_{_\text{K}}}{P_{_\text{K}}}\right]\cdot\frac{1}{\text{d}T}\tag{3}\label{eq:3} \\\\ &amp;\quad\quad\text{or also,}\\\\ \frac{\text{d} F}{F}&amp;=\frac{\text{d}\, P_{_\text{K}}}{P_{_\text{K}}}-\frac{\text{d}\,R}{R}\tag{4}\label{eq:4} \end{align*}$$</span></p> <p>That's what I come up with just applying math and not attempting to read the paper with understanding.</p> <p>Take note that Eq. <span class="math-container">\$\ref{eq:2}\$</span> casts, yet again, things in terms of %-change in <span class="math-container">\$R\$</span> and %-change in <span class="math-container">\$P_{_\text{K}}\$</span>. Looking at things as %-change helps focus on a <em>sensitivity</em> viewpoint, which is a very powerful way to consider issues at hand. To ask, &quot;<em>How sensitive is the output to a %-change in input <span class="math-container">\$x\$</span> or a %-change in input <span class="math-container">\$y\$</span>?&quot;</em>, is quite powerful!</p> <p>Compare Eq. <span class="math-container">\$\ref{eq:2}\$</span> with equation 7 in your document, perhaps. I suspect their <strong>KP(T)</strong> is <span class="math-container">\$P_{_\text{K}}\$</span>, above, knowing that <strong>K</strong> is a function of <strong>T</strong>. <em>(Eq. <span class="math-container">\$\ref{eq:3}\$</span> is just another way of writing it.)</em></p> <p>I think Eq. <span class="math-container">\$\ref{eq:4}\$</span> may also be important to understand. It says how a %-change in <span class="math-container">\$V_{_\text{REF}}\$</span> depends on %-changes elsewhere. And it suggests a way to consider how one may attempt to zero-out, or at least minimize the worst case of, any variation in <span class="math-container">\$V_{_\text{REF}}\$</span> by balancing two terms. But it isn't covered in your document. So I'll leave it, for now.</p>

<p>I am currently working on designing a beta multiplier voltage reference, and came across <a href="https://citeseerx.ist.psu.edu/document?repid=rep1&amp;type=pdf&amp;doi=8fa2d8e22d52bd31c948aa19220eaac8b2427289#:%7E:text=Beta%2DMultiplier%20Voltage%20Reference&amp;text=Experimental%20results%20from%20a%202,a%20supply%20sensitivity%20under%2050mVN" rel="nofollow noreferrer">this paper</a>.</p> <p>I am slightly confused as to how they ended up with equation (6) after taking the derivative of (5) with respect to temperature.</p> <p>It would be appreciated if someone could show how to do it and provide an intuitive understanding of how to approach these sorts of derivatives, specifically for application purposes as in the case below.</p> <hr /> <p>Solving for <span class="math-container">\$I\$</span> and <span class="math-container">\$V_{REF}\$</span> using the three equations yields <span class="math-container">$$ I=\frac{2}{R^2\,\beta_1} {\left(1 - \frac{1}{\sqrt{K}} \right)}^2 \tag{4} $$</span> and <span class="math-container">$$ V_{REF} = V_{GS1} = \frac{2}{R\,\beta_1} \left(1 - \frac{1}{\sqrt{K}} \right) + V_{THN}. \tag{5} $$</span> The temperature coefficient of the voltage reference is given by <span class="math-container">$$ \frac{{\rm d}V_{REF}}{{\rm d}T} = \frac{{\rm d}V_{THN}}{{\rm d}T} - \frac{2}{R\,\beta_1} \left( 1 - \frac{1}{\sqrt{K}} \right) \left( \frac{1}{R} \frac{{\rm d}R}{{\rm d}T} + \frac{1}{KP(T)} \frac{{\rm d}KP(T)}{{\rm d}T} \right) \tag{6} $$</span></p> <hr />

Getting temperature dependence for a beta multiplier circuit

2024-02-09T18:52:35.387

700854

|transfer-function|bode-plot|pole-zeroplot|

<p>Assuming that the output voltage is defined across RL the transfer funktion Vout/Iin is nothing else than the input impedance of the RC-network.</p> <p><strong>Vout/In=RL||(ESR + 1/sCo)</strong></p> <p><strong>Vout/In=[RL + s * RL * ESR * Co]/[1 + sCo * (RL+ESR)]</strong></p>

<p>I am reading through some lecture and wondering how to derive transfer function when input source is a current source. Can you anyone give me an advice? Thank you</p> <p><a href="https://i.stack.imgur.com/mh5pM.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/mh5pM.jpg" alt="enter image description here" /></a></p>

How do I derive a transfer function of RC circuit including ESR?

2024-02-09T20:44:17.660

700858

|pcb|pcb-design|transformer|footprint|pad|

<p>I see two concerns:</p> <ol> <li>The given footprint is mirrored from convention. This is sneaky, because they give this drawing:</li> </ol> <p><a href="https://i.stack.imgur.com/6JghI.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/6JghI.png" alt="enter image description here" /></a></p> <p>A cursory look might assume the pins are in the normal order, but the bottom drawing is the bottom view (hence the windings are visible inside the core). The land pattern is top-down, mirrored from this view.</p> <p>You have a conventionally arranged footprint, which will swap primary and aux, causing poor and unexpected performance, or destruction.</p> <p>In cases like this, I tend to ignore the numbering as given by the manufacturer, <em>which is objectively wrong,</em> and using a conventional pinout instead.</p> <p>(It may be worth adding a note to this effect, to the schematic, or other design review materials, if other engineers will be looking at this and double-checking your work.)</p> <p>In that case, you should change the schematic to have bias on pins 1-2, primary 4-5, and the secondary is in the same place, give or take phasing.</p> <ol start="2"> <li>You can swap all windings end for end, to get the same response; at least at low frequencies.</li> </ol> <p>At high frequencies, it may be preferred to keep one or another end of a winding near GND, or referenced to certain ends of other windings (typically VCC and GND, both being AC-ground nodes), and then the choice of which end to ground matters, or which end of the winding the rectifier diode goes on. (With a sync rect, I think this probably isn't applicable here, but to say there are cases when it is.)</p> <p>For such a small transformer, and at low to moderate voltages, this probably doesn't make a difference. It may also be that the transformer isn't made with the particular winding techniques, or shielding, where this would affect the result (in other words: don't worry about it).</p> <p>It's also a &quot;don't worry&quot; situation if you won't be re-doing the design, to optimize transformer windup, component placement, EMI filtering, etc. Since, you'll do the design, the EMI filtering is whatever it needs to be, and that's that; maybe it could be simpler if a more suitable transformer wiring or windup were chosen, but if these aren't variables you're going to test, then the EMI is just whatever you get with the configuration you will test.</p> <p>Assuming of course, that EMI is a concern and will be tested.</p>

<p>I am replicating one of our recommended designs for a POE application.</p> <p>Here I have an EP13 forward transformer <a href="https://www.coilcraft.com/getmedia/fe569a42-533f-4322-ab3b-764883f54979/fct1xxm22sl.pdf" rel="nofollow noreferrer">FCT1-50M22SL</a> as recommended in the BOM. The pins do not match the provided image of the PCB layout provided. I understand pins 3 and 8 do not matter, but the component is not rotated.</p> <p>They are treating coil pin 1 as pad 2 &amp; 3, pin 5 as pad 4, etc.</p> <p>Am I wrong in thinking the model pins for the symbol are not pin 1 = pad 1? Are there other ways to configure the transformer and can I just use the image to map my pins?</p> <p><a href="https://i.stack.imgur.com/d8vVZ.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/d8vVZ.png" alt="enter image description here" /></a></p> <p><a href="https://i.stack.imgur.com/wMc8F.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/wMc8F.png" alt="enter image description here" /></a></p> <p><a href="https://i.stack.imgur.com/nwTKb.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/nwTKb.png" alt="Component I created from the reference" /></a></p> <p><a href="https://i.stack.imgur.com/9lawR.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/9lawR.png" alt="enter image description here" /></a></p>

Transformer pins not matching PCB layout

2024-02-09T21:17:24.863

700861

|rf|interference|damage|

<blockquote> <p>Is having so many RF modems close to each others, all trying to transmit and send on top of each others, at risk of damaging each other?</p> </blockquote> <p>Nah. They have separate up- and downlink bands anyways, and their transmit filters should be pretty steep, so that there's little emission on the downlink.</p>

<p>I use Iridium SBD 9603 N modems in some hardware (oceanographic buoys). I use high gain antenna, typically the setup is based on <a href="https://www.sparkfun.com/products/18712" rel="nofollow noreferrer">https://www.sparkfun.com/products/18712</a> and <a href="https://www.sparkfun.com/products/16838" rel="nofollow noreferrer">https://www.sparkfun.com/products/16838</a> .</p> <p>I typically build a series of instruments (20-ish) at a time, and put them outside for testing, very close to each others.</p> <p>Is having so many RF modems close to each others, all trying to transmit and send on top of each others, at risk of damaging each other? I don't care if a message don't get through now and then because the modems try to 'speak over each others', but I don't want to damage hardware if a modem tries to send a message while it's neighbour is listening... I.e. is 'shouting in the ears of your neighbour who is listening' something that can typically damage Iridium 9603 modems, or is this not a risk at all because there are built in over voltage / RF hardware / RF amplifier protection?</p> <p>Is there some form of RF protection to avoid any risks of damage, or should I be worried / stop testing my instruments and modems like this?</p>

Is there a risk of damaging built in RF components having several Iridium SBD 9603N modems active close to each others?

2024-02-09T21:28:21.943

700867

|stm32|uart|baudrate|stm32cubeide|lin|

<p>The stop bits must be set to 1 in LIN mode.</p> <p>That and other prerequisites for proper operation in LIN mode is specified in the reference manual for the MCU.</p> <p>Basically, if you are not using other weird settings, just set stop bits to 1 and it should work.</p>

<p>I am using the UART of an STM32F103C8T6. When selecting the <strong>Asynchronous</strong> mode via the CubeMX everything works fine using either of the functions <code>HAL_UART_Transmit_IT()</code> and <code>HAL_UART_Transmit()</code>. I am using a Baud Rate of 250kBits/s (for DMX).</p> <p>When I set the mode to <strong>LIN</strong> and don't change anything else, the baud rate which the STM is sending at isn't correct anymore (measured with an oscilloscope), even though I didn't change it in my configuration.</p> <p>Interestingly when I set the baud rate to (the wrong value of) ~230kBits/s it sends at approximately the correct data rate again. This is when using <code>HAL_UART_Transmit_IT()</code>. When using <code>HAL_UART_Transmit()</code>, I need to set it to ~210kBits/s to achieve a decently correct baud rate.</p> <p>What could be the cause of this problem? Just changing it to a wrong value such that it <em>somehow</em> kinda works without knowing what's going on is a bit unsettling and isn't what I'd consider a great solution. Also, the receiver doesn't really decode the data correctly.</p> <p>Thanks for your help.</p> <p>The code:</p> <p><code>main.c</code> (in Asynchronous mode):</p> <pre><code>/* USER CODE BEGIN Header */ /** ****************************************************************************** * @file : main.c * @brief : Main program body ****************************************************************************** * @attention * * Copyright (c) 2024 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* USER CODE END Header */ /* Includes ------------------------------------------------------------------*/ #include &quot;main.h&quot; #include &quot;usb_device.h&quot; /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ /* USER CODE END Includes */ /* Private typedef -----------------------------------------------------------*/ /* USER CODE BEGIN PTD */ /* USER CODE END PTD */ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN PD */ /* USER CODE END PD */ /* Private macro -------------------------------------------------------------*/ /* USER CODE BEGIN PM */ /* USER CODE END PM */ /* Private variables ---------------------------------------------------------*/ TIM_HandleTypeDef htim2; UART_HandleTypeDef huart2; /* USER CODE BEGIN PV */ /* USER CODE END PV */ /* Private function prototypes -----------------------------------------------*/ void SystemClock_Config(void); static void MX_GPIO_Init(void); static void MX_TIM2_Init(void); static void MX_USART2_UART_Init(void); /* USER CODE BEGIN PFP */ /* USER CODE END PFP */ /* Private user code ---------------------------------------------------------*/ /* USER CODE BEGIN 0 */ uint8_t DMX_state = 0; // 0: idle (ready to send), 1: data is available, 2: break on DMX line, 3: mark after break on DMX line, 4: sending data uint8_t DMX_loop_counter = 0; uint8_t DMX_data[513]; // first byte is the zero-byte/ start byte /* USER CODE END 0 */ /** * @brief The application entry point. * @retval int */ int main(void) { /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); MX_TIM2_Init(); MX_USART2_UART_Init(); MX_USB_DEVICE_Init(); /* USER CODE BEGIN 2 */ /* USER CODE END 2 */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) { /* USER CODE END WHILE */ /* USER CODE BEGIN 3 */ } /* USER CODE END 3 */ } /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1; RCC_OscInitStruct.HSIState = RCC_HSI_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; if (HAL_RCC_OscConfig(&amp;RCC_OscInitStruct) != HAL_OK) { Error_Handler(); } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; if (HAL_RCC_ClockConfig(&amp;RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) { Error_Handler(); } PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLL_DIV1_5; if (HAL_RCCEx_PeriphCLKConfig(&amp;PeriphClkInit) != HAL_OK) { Error_Handler(); } } /** * @brief TIM2 Initialization Function * @param None * @retval None */ static void MX_TIM2_Init(void) { /* USER CODE BEGIN TIM2_Init 0 */ /* USER CODE END TIM2_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; TIM_MasterConfigTypeDef sMasterConfig = {0}; /* USER CODE BEGIN TIM2_Init 1 */ /* USER CODE END TIM2_Init 1 */ htim2.Instance = TIM2; htim2.Init.Prescaler = 71; htim2.Init.CounterMode = TIM_COUNTERMODE_UP; htim2.Init.Period = 11; htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; if (HAL_TIM_Base_Init(&amp;htim2) != HAL_OK) { Error_Handler(); } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; if (HAL_TIM_ConfigClockSource(&amp;htim2, &amp;sClockSourceConfig) != HAL_OK) { Error_Handler(); } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; if (HAL_TIMEx_MasterConfigSynchronization(&amp;htim2, &amp;sMasterConfig) != HAL_OK) { Error_Handler(); } /* USER CODE BEGIN TIM2_Init 2 */ /* USER CODE END TIM2_Init 2 */ } /** * @brief USART2 Initialization Function * @param None * @retval None */ static void MX_USART2_UART_Init(void) { /* USER CODE BEGIN USART2_Init 0 */ /* USER CODE END USART2_Init 0 */ /* USER CODE BEGIN USART2_Init 1 */ /* USER CODE END USART2_Init 1 */ huart2.Instance = USART2; huart2.Init.BaudRate = 250000; huart2.Init.WordLength = UART_WORDLENGTH_8B; huart2.Init.StopBits = UART_STOPBITS_2; huart2.Init.Parity = UART_PARITY_NONE; huart2.Init.Mode = UART_MODE_TX_RX; huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; huart2.Init.OverSampling = UART_OVERSAMPLING_16; if (HAL_UART_Init(&amp;huart2) != HAL_OK) { Error_Handler(); } /* USER CODE BEGIN USART2_Init 2 */ /* USER CODE END USART2_Init 2 */ } /** * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { GPIO_InitTypeDef GPIO_InitStruct = {0}; /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOD_CLK_ENABLE(); __HAL_RCC_GPIOA_CLK_ENABLE(); /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(TRANSISTOR_GPIO_Port, TRANSISTOR_Pin, GPIO_PIN_RESET); /*Configure GPIO pin : TRANSISTOR_Pin */ GPIO_InitStruct.Pin = TRANSISTOR_Pin; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; HAL_GPIO_Init(TRANSISTOR_GPIO_Port, &amp;GPIO_InitStruct); } /* USER CODE BEGIN 4 */ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef* htim) { // htim2.Init.Prescaler = 71; // prescale 72 MHz to 1 MHz -&gt; every 1 microsecond // htim2.Init.Period = 11; // count from 0 to 11 -&gt; 12 microseconds // break for 8 periods (8*12=96) (count to 8), and mark after break for one period (just wait for next loop execution) if (DMX_state == 1){ // 0: idle (ready to send), 1: data is available, 2: break on DMX line, 3: mark after break on DMX line, 4: sending data HAL_GPIO_WritePin(TRANSISTOR_GPIO_Port, TRANSISTOR_Pin, 1); // pulls low -&gt; break DMX_loop_counter = 0; DMX_state = 2; } else if (DMX_state == 2){ if (DMX_loop_counter &lt; 8) { // wait 8 loop executions DMX_loop_counter++; } else { HAL_GPIO_WritePin(TRANSISTOR_GPIO_Port, TRANSISTOR_Pin, 0); // stops pulling low -&gt; mark after break DMX_state = 3; } } else if (DMX_state == 3){ HAL_UART_Transmit_IT(&amp;huart2, DMX_data, sizeof(DMX_data)); HAL_TIM_Base_Stop_IT(&amp;htim2); DMX_state = 4; } } void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { DMX_state = 0; } /* USER CODE END 4 */ /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) { } /* USER CODE END Error_Handler_Debug */ } #ifdef USE_FULL_ASSERT /** * @brief Reports the name of the source file and the source line number * where the assert_param error has occurred. * @param file: pointer to the source file name * @param line: assert_param error line source number * @retval None */ void assert_failed(uint8_t *file, uint32_t line) { /* USER CODE BEGIN 6 */ /* User can add his own implementation to report the file name and line number, ex: printf(&quot;Wrong parameters value: file %s on line %d\r\n&quot;, file, line) */ /* USER CODE END 6 */ } #endif /* USE_FULL_ASSERT */ </code></pre> <p>In the <code>usbd_cdc_if.c</code>, I added something in <code>CDC_Receive_FS()</code>:</p> <pre><code>static int8_t CDC_Receive_FS(uint8_t* Buf, uint32_t *Len) { /* USER CODE BEGIN 6 */ USBD_CDC_SetRxBuffer(&amp;hUsbDeviceFS, &amp;Buf[0]); USBD_CDC_ReceivePacket(&amp;hUsbDeviceFS); uint32_t length = (uint32_t) *Len; uint8_t buffer[length]; memcpy(buffer, Buf, length); extern uint8_t DMX_data[513]; extern uint8_t DMX_state; extern htim2; if (length &gt;= 1) { if ((buffer[0] == 0x80) &amp;&amp; (DMX_state == 0) &amp;&amp; (length &gt;= 2)) { memset(DMX_data, 0x00, sizeof(DMX_data)); memcpy(&amp;DMX_data[1], &amp;buffer[1], (length-1)); HAL_TIM_Base_Start_IT(&amp;htim2); DMX_state = 1; } } return (USBD_OK); /* USER CODE END 6 */ } </code></pre> <p>I also enabled the Interrupts for <code>TIM2</code> and <code>USART2</code>.</p>

STM32 UART in LIN mode sends with incorrect baudrate but not in asynchronous mode

2024-02-09T22:50:45.180

700875

|noise|oscilloscope|emc|

<p>These results are not unexpected at all. Nothing to do with the TV. Try it with charging bricks or other switching &quot;brick&quot; power supplies.</p> <blockquote> <p>it is unlike any switching noise I have seen before</p> </blockquote> <p>What you're seeing is most likely the impulse response of the scope probe assembly (probe, cable, scope's front-end).</p> <p>That the problem with such &quot;measurements&quot;: they can be qualitative in nature at best. You shouldn't be using a floating scope probe to measure such things. Use proper EMC near field probes.</p> <blockquote> <p>I have had a go at probing the RCA outputs of my TV</p> </blockquote> <blockquote> <p>The probe is about 30cm from the rear of the TV</p> </blockquote> <p>These two statements are contradictory. Either the probe is properly connected (tip and ground ring) to the RCA outputs, or it isn't. Probes floating in the air are antennas. Every modern consumer &quot;IT&quot; device radiates quite a bit, just try tuning to anything on a short wave radio.</p>

<p>Using my oscilloscope near my TV(a Panasonic TH-L42U20A) seems to introduce an unidentifiable source of noise. The scope probe is floating, neither probe or ground clip is connected to anything, however my scope shows a strange prominent 'ringing' waveform even though the input is floating.</p> <p>The probe is about 30cm from the rear of the TV, and the waveform disappears when I bring the probe close to the floor, appearing again when I raise its height to about 15-20cm above the floor. Attaching the ground clip to ground attenuates the waveform slightly, but still has considerable ripple.</p> <p>I suspect this might be some kind of EMI from an internal switching regulator, but it is unlike any switching noise I have seen before, and is considerably strong as well.</p> <p><a href="https://i.stack.imgur.com/xR5eN.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/xR5eN.jpg" alt="Oscilloscope waveform capture" /></a></p> <p>(10mV p/div, 10us timescale)</p>

Unknown signal source

2024-02-10T01:50:03.197

700885

|diodes|analog-computer|analog-multiplier|

<h1>When the circuit does not work</h1> <p>There is a paradox in circuitry that perhaps applies to everything in life - <em>for the purposes of understanding, it is better that the circuit does not start working after you make it and turn on the power</em>. Because if it starts working right away, you will not think about it, but if it does not work, you are forced to do it. That is why I have always told my students in the lab, &quot;Be glad your circuit did not work and be sorry when it did&quot; :-)</p> <h1>Looking for the idea</h1> <p>There have been quite a few circuit solutions of a log converter (with diodes, transistors and op-amps) and this makes us think of somehow arranging them. The most logical way is to start from the simplest and reach the most complex schematic solution; thus, by following the evolution of the circuit idea, we will understand it best.</p> <p>There are a bunch of interesting questions here that we need to answer: &quot;Why is only a diode not enough to make a log converter? Why do we add a resistor first and then an op-amp? Why we replace the diode with a transistor? And how is it that with just a simple connection between the base and the collector, the transistor is transformed so that it starts converting current to voltage instead of voltage to current as usual? Does the op-amp from the last circuit (with the so-called &quot;transdiode&quot;) have anything to do with this? Why are the op-amp implementations inverting?&quot;</p> <h1>Diode log converters</h1> <p>To make a functional (log) converter, we need a device with a corresponding functional relationship between its input and output magnitude. Fortunately, the IV curve of a PN junction is close to logarithmic...</p> <h2>I-to-V log converter</h2> <p>... so the first thought that comes to mind is to use a diode as a <em>log current-to-voltage converter</em>. This means that we have to pass a current through the diode as an input quantity and take the voltage drop across the diode as an output quantity.</p> <p><strong>Unloaded:</strong> Let's first connect a (perfect) voltmeter as a &quot;load&quot; (open circuit or simply put, &quot;nothing&quot;) and begin to change the current within wide limits. We notice that the voltage across the diode changes very little, which corresponds to our intuitive idea about this element. The reason is that the diode behaves like a &quot;dynamic resistor&quot; that decreases its resistance when the current increases and vice versa, increases its resistance when the current decreases.</p> <p><img src="https://i.stack.imgur.com/RK8En.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fRK8En.png">simulate this circuit</a> &ndash; Schematic created using <a href="https://www.circuitlab.com/" rel="noreferrer">CircuitLab</a>}</p> <p>If we sweep (change) the input current from zero to 1 mA by the help of the CircuitLab <em>DC Sweep Simulation</em>, we will see that the output voltage changes logarithmically.</p> <p><a href="https://i.stack.imgur.com/u89zM.png" rel="noreferrer"><img src="https://i.stack.imgur.com/u89zM.png" alt="STEP 1.1.1" /></a></p> <p><strong>Loaded:</strong> Now let's load this passive circuit with say 1 kΩ load (for this purpose, we can just set such resistance on the voltmeter in its <em>parameters</em> field). The load diverts a current through itself, the equivalent resistance decreases, and we see that the voltage drops by about 40 mV...</p> <p><img src="https://i.stack.imgur.com/ogCnO.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fogCnO.png">simulate this circuit</a>}</p> <p>... and the curve changes its shape. Therefore, the load degrades the shape of the curve.</p> <p><a href="https://i.stack.imgur.com/FIWL1.png" rel="noreferrer"><img src="https://i.stack.imgur.com/FIWL1.png" alt="STEP 1.1.2" /></a></p> <p><strong>Buffered:</strong> The straightforward solution is to buffer the output with a voltage follower. It now copies the diode voltage across the load by supplying it with current from its own supply rather than the input source. The result is obvious - the voltage returns to its initial value (without load, Schematic 1.1.1)...</p> <p><img src="https://i.stack.imgur.com/sCFMx.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fsCFMx.png">simulate this circuit</a>}</p> <p>... and the curve takes its initial shape as in the graph to Schematic 1.1.1.</p> <p><a href="https://i.stack.imgur.com/EYPxV.png" rel="noreferrer"><img src="https://i.stack.imgur.com/EYPxV.png" alt="STEP 1.1.3" /></a></p> <h2>V-to-V log converter</h2> <p><strong>Unloaded:</strong> However, we want the drive circuit not by current but by voltage. For this purpose, we connect in series with the input voltage source a resistor acting as a <em>voltage-to-current converter</em>. We know that the resistor is supposed to be a linear converter...</p> <p><img src="https://i.stack.imgur.com/v1Nl2.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fv1Nl2.png">simulate this circuit</a>}</p> <p>... but we see that the circuit performs poorly at 1 V input voltage.</p> <p><a href="https://i.stack.imgur.com/kaeAH.png" rel="noreferrer"><img src="https://i.stack.imgur.com/kaeAH.png" alt="STEP 1.2.1.1" /></a></p> <p><strong>Vin = 10 V:</strong> Aha... see, the voltage across the resistor (the difference between the input and output voltages) is small. If we increase the input voltage to say 10 V...</p> <p><img src="https://i.stack.imgur.com/C6q4n.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fC6q4n.png">simulate this circuit</a>}</p> <p>... things get better.</p> <p><a href="https://i.stack.imgur.com/s9Fsj.png" rel="noreferrer"><img src="https://i.stack.imgur.com/s9Fsj.png" alt="STEP 1.2.1.2" /></a></p> <p><strong>Loaded:</strong> As above, the load distorts the shape of the curve...</p> <p><img src="https://i.stack.imgur.com/HcmmN.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fHcmmN.png">simulate this circuit</a>}</p> <p>... especially if the input voltage is low (1 V).</p> <p><a href="https://i.stack.imgur.com/GyoiE.png" rel="noreferrer"><img src="https://i.stack.imgur.com/GyoiE.png" alt="STEP 1.2.2" /></a></p> <p>Therefore, the simple passive circuit has two major problems - <em>input</em> (low input voltage) and <em>output</em> (low-resistance load). And here we wonder if there is no remedy to solve both problems?</p> <p><strong>Voltage-source compensated:</strong> It turns out that there is, and it is very well known to us from life - <em>we compensate for the voltage loss VF across the diode by adding a voltage of the same value</em>. For this purpose, we connect a following (&quot;behavioral&quot;) voltage source Vout = VF in series and use its voltage as output.</p> <p><img src="https://i.stack.imgur.com/Xlniz.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fXlniz.png">simulate this circuit</a>}</p> <p>The results of this simple action are amazing - the input voltage and the load resistance can be as low as we want because there is no VF and the load is supplied by another voltage source. Note that the output voltage is negative in respect to ground (the curve is below zero) but is added to Vin when travelling the loop.</p> <p><a href="https://i.stack.imgur.com/gxawk.png" rel="noreferrer"><img src="https://i.stack.imgur.com/gxawk.png" alt="STEP 1.2.3" /></a></p> <p><strong>Op-amp compensated:</strong> In practical circuits, an op-amp can serve as the compensating voltage source Vout. By the help of the negative feedback principle, it compares its output voltage Vout with the diode voltage VF and makes the difference between them (almost) equal to zero (the so-called <em>virtual ground</em>). As a result, Vout = VF.</p> <p><img src="https://i.stack.imgur.com/QneOJ.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fQneOJ.png">simulate this circuit</a>}</p> <p>The curve is the same as above and below zero.</p> <p><a href="https://i.stack.imgur.com/7i46Y.png" rel="noreferrer"><img src="https://i.stack.imgur.com/7i46Y.png" alt="STEP 1.2.4" /></a></p> <h1>Transistor-diode log converters</h1> <p>A tempting idea is to make a log converter with a transistor instead of a diode. Transistors are active devices and also have such but an inverse (exponential) functional relationship between the input (Vbe) and output (Ic) quantity... and for some reason it is better. So it would be great if we could &quot;reverse&quot; them so that they convert current to voltage instead of voltage to current. For example, if some people are born bad but we force them to do good deeds, they become good; if we are too considerate of our subordinates, they are effectively ruling us, etc. The name of this trick is <em>negative feedback</em>.</p> <p><strong>Unloaded:</strong> So, if we connect the transistor base to its collector, it will adjust its Vbe so that to pass the input current Vin/R through its base-emitter part.</p> <p><img src="https://i.stack.imgur.com/TkEce.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fTkEce.png">simulate this circuit</a>}</p> <p>Thus the transistor is &quot;reversed&quot; and its transfer curve is the same as of the diode IV curve.</p> <p><a href="https://i.stack.imgur.com/5TMeE.png" rel="noreferrer"><img src="https://i.stack.imgur.com/5TMeE.png" alt="STEP 2.1" /></a></p> <p><strong>Loaded:</strong> The collector-emitter section connected in parallel to the base-emitter junction acts as a &quot;shunt booster&quot;.</p> <p><img src="https://i.stack.imgur.com/LXIrp.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fLXIrp.png">simulate this circuit</a>}</p> <p>So the curve is good even if a load is connected.</p> <p><a href="https://i.stack.imgur.com/0UEbe.png" rel="noreferrer"><img src="https://i.stack.imgur.com/0UEbe.png" alt="STEP 2.2" /></a></p> <h2>Op-amp transistor diode</h2> <p>The &quot;harmful&quot; collector-emitter voltage can be neutralized by an op-amp like in the Schematic 1.2.4 above.</p> <p><img src="https://i.stack.imgur.com/GALuq.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fGALuq.png">simulate this circuit</a>}</p> <p><a href="https://i.stack.imgur.com/1YOoc.png" rel="noreferrer"><img src="https://i.stack.imgur.com/1YOoc.png" alt="STEP 2.3" /></a></p> <h1>Transdiode log converters</h1> <p>And finally, the transistor can be controlled by the op-amp from the side of the emitter (like in the common-base configuration). The op-amp adjusts its Vout so that to pass the input current Vin/R through the transistor base-emitter part. An additional advantage is that the base current does not flow through the input voltage source.</p> <p><img src="https://i.stack.imgur.com/GHFmv.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fGHFmv.png">simulate this circuit</a>}</p> <p><a href="https://i.stack.imgur.com/H1kqr.png" rel="noreferrer"><img src="https://i.stack.imgur.com/H1kqr.png" alt="STEP 3.1" /></a></p> <p>&quot;Trans-&quot; comes from the fact that unlike a regular diode where the voltage and current appear between two same points (cathode and anode), here they appear in different places (base-emitter and collector-emitter).</p>

<p><img src="https://i.stack.imgur.com/UUfxv.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fUUfxv.png">simulate this circuit</a> &ndash; Schematic created using <a href="https://www.circuitlab.com/" rel="noreferrer">CircuitLab</a>}</p> <p>I am trying to build a circuit on a breadboard which takes in a voltage and calculates its logarithm. I found on YouTube that Vout = -(ideality factor · thermal voltage)·log(Vin/Is·R) where Is is the reverse saturation current and R is the resistance. I am using a 1N4148 diode and an LM741 op-amp.</p> <p>In the given equation, I do not know the ideality factor and Is. I tried different voltages on the input trying to find Is, but each time it gives a different Is.</p> <p>I was thinking of using log and antilog circuits to make a voltage multiplier that takes two input voltages V1 and V2 and gives output k·V1·V2 where k is some constant, but since the log circuit is not working as expected.</p> <p>The LTspice simulation is showing the output properly but, it is not working on the breadboard.</p> <p>Here is the log circuit I am using (from <a href="https://youtu.be/Nrfb-s0wl6g?si=POPSO2nVojF6cIMG&amp;t=403" rel="noreferrer">YouTube</a>):</p> <p><a href="https://i.stack.imgur.com/MWrnt.png" rel="noreferrer"><img src="https://i.stack.imgur.com/MWrnt.png" alt="enter image description here" /></a></p>

Logarithm circuit using op-amp not working

2024-02-10T05:03:04.833

700889

|microcontroller|digital-logic|avr|logic-level|

<p>I did a real-world measurement using AVR32DD28.</p> <p>Using this setup:</p> <p><img src="https://i.stack.imgur.com/hQu5w.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fhQu5w.png">simulate this circuit</a> &ndash; Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a>}</p> <p>And I used this simple code:</p> <pre class="lang-c prettyprint-override"><code>#include &lt;avr/io.h&gt; int main(void) { PORTD_DIRSET = (1 &lt;&lt; PIN7_bp); while (1) { PORTD_OUT = PORTA_IN; } } </code></pre> <p>And the voltmeter shows that the <span class="math-container">\$V_{IH}\$</span> is aroud <span class="math-container">\$2.78V\$</span></p> <p>And <span class="math-container">\$V_{IL}\$</span> around <span class="math-container">\$2V\$</span></p> <p>So it seems to match the typical value shown in the datasheet. But again we have to remember that this is a typical value. And it will very form device to devise and with the temperature (VIH will increase for lower temperature). And maybe this is why they say that <span class="math-container">\$V_{IH} = 0.8 \:VDD\$</span> to stay on the safe side.</p>

<p>I am looking into using an AVR32DA48 MCU for a design. The MCU will be powered at 5V and needs to interface with an IC at 3.3V. The IC is 5V tolerant and I am trying to figure out if a level translator is required for the IC to MCU communication.</p> <p>According to the <a href="https://ww1.microchip.com/downloads/aemDocuments/documents/MCU08/ProductDocuments/DataSheets/AVR32DA28-32-48-Data-Sheet-40002228B.pdf" rel="nofollow noreferrer">AVR32DA datasheet</a>, on page 565, the <em>Table 37-7. I/O Pin Specifications</em> states that the I/O ports require 0.8xVDD minimum for VIH, which in this case means 4V. On page 605, though, the graph in <em>Figure 38-74 Input Pin with Schmitt Trigger - Minimum VIH vs. VDD</em>, reveals that the minimum VIH for 5V is nominally around 2.8V.</p> <p>How is this discrepancy explained?</p>

AVR32DA VIH threshold

2024-02-10T05:25:23.890

700902

|relay|low-voltage|fluid-pump|undervoltage|

<blockquote> <p>at around 280 feet</p> </blockquote> <p>Is that depth or horizontal distance?</p> <hr /> <ol> <li><p>An electromechanical relay designed for 230-240V nominal won't pull in reliably at 170V as you've noticed. Use a solid-state relay (SSR). Make sure you put it on a heatsink as per the datasheet.</p> </li> <li><p>At too low of a voltage, the motor may stall or not develop enough head pressure to keep the water moving in the pipe. In either case, the motor will be dissipating the entire electrical power it consumes as heat into the stagnant water inside the pump. The pump head will overheat. Depending on construction, the water inside may boil, plastic parts may get damaged, as can bearing seals, o-rings, etc.</p> </li> </ol> <p>I wouldn't worry much about persistent overvoltage. That doesn't really happen all that much. Undervoltage is a real concern for you, and for that you'd want an undervoltage protection relay.</p> <p>Something <a href="https://rads.stackoverflow.com/amzn/click/com/B08R8TPB25" rel="nofollow noreferrer" rel="nofollow noreferrer">similar to this device</a>, but preferably from a major brand and a major distributor of industrial controls, rather than non-name unsupported products from Amazon where your only remedy is maybe a return.</p> <p>If you decide to go with the Amazon deal, it may be worth buying a couple of them, preferably looking differently so that hopefully if one has some design or production mistake, the other one won't.</p> <p>But you'll do well to peruse legit industrial automation brands and distributors, and consider buyer beware on anything from Amazon, eBay, AliExpress, etc.</p>

<p>I have an irrigation setup in a rural area with voltage fluctuations.</p> <p>The irrigation setup consists of a Hunter X2 Controller powering a pump start relay which in turn runs a 1.5 HP submersible motor at around 280 feet.</p> <p>The pump operates well when the pump controller displays a voltage over 200 V (AC single-phase) after starting the motor. However, when the pump runs at a displayed voltage of 170 V the relay heats up and chatters.</p> <p>Due to the nature of supply in rural areas I would like to mitigate this condition. My search yielded two options:</p> <ol> <li>Voltage stabilizer</li> <li><a href="https://www.amazon.in/dp/B0BWRGTLJ7" rel="nofollow noreferrer">Voltage protection device with under and over voltage cutoff</a></li> </ol> <p>I am looking for advice on my analysis as well as the solution option to finalise.</p>

Voltage stabilizer or voltage protection device for irrigation setup

2024-02-10T09:32:09.440

700903

|pcb|antenna|altium|routing|drc|

<p>I believe you are getting the net antenna error markers on the vias because there is a small fragment of trace under the pad that is not visible, similar to the fragment that is visible below the U3 designator. They don't necessarily hurt anything as is, but you should fix them.</p> <p>If you delete those fragments the errors will go away. Filter on <strong>just tracks</strong> then select sweeping over the pad then delete the bit that gets highlighted. Don't forget to clear the filter.</p>

<p><a href="https://i.stack.imgur.com/CFsOj.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/CFsOj.png" alt="PCB design in Altium Designer 24. Translator, resistors and capacitors" /></a></p> <p>I was wondering if anyone could help me understanding the DRC Net Antennae: via errors that look like lollipops. I've read that the double lines are related to un-routed net constraints.</p>

Altium Designer 24 DRC error symbols meaning

2024-02-10T09:49:09.360

700913

|resistors|identification|

<p>As said already, it is a resistor with a special marking.</p> <p>Colour bands are orange-orange-silver-gold-black, which means it is a 0.33 ohm 5% resistor.</p> <p>The black band could mean multiple things. Like you guessed, it might mean non-inductive or tempco.</p> <p>It might mean other things too, like failure rate or fusible resistor for safety.</p> <p>Since it is anyway a 5% resistor, tempco would not make a lot of sense. Maybe failure rate either.</p> <p>It does not look like a wirewound so it might mean non-inductive.</p> <p>But it has also broken in a way that the colour bands are readable and it is not charred beyond recognition.</p> <p>So it could mean a fusible resistor.</p> <p>At least if it is a fusible resistor, do not replace it with a non-fusible resistor, for obvious safety reasons.</p> <p>On the other hand, the whole thing is potted in some compound, so working on the board will be difficult.</p> <p>Resistors do not generally blow up without a reason, so if the board or some actuator is faulty, replacing the resistor is useless, as the new resistor would just fry up again until the actual problem is fixed.</p>

<p>Can someone tell me how to read this resistor value?</p> <p><img src="https://i.ibb.co/rsz7Mbh/Whats-App-Image-2024-02-10-at-09-56-13-dbf46a0e.jpg" alt="" /></p> <p>After reading <em><a href="https://forum.digikey.com/t/when-your-5-band-resistor-is-not-a-5-band-resistor/1501" rel="nofollow noreferrer">When your 5 Band Resistor is not a 5 Band Resistor</a></em> on the DigiKey forum I realized this is a 4-band resistor, and the 5th band is probably the temperature coefficient. However, it could be an indication that this is a non-inductive resistor.</p> <p>From the link above: &quot;If your 5th band is black you are best to try to identify the resistor manufacturer and look at their data sheet.&quot;</p> <p>I don't know who manufactured it.</p> <p>This PCB is the main board of a consumer washing machine. The stage in which the resistor is located seems to be a SMPS. Mains are connected across the yellow relay, bottom right, and black relay, bottom center. I'd say this is a 0.33 Ω shunt resistor, but I'd like to know if that last black band means just the tempco or if it is a non-inductive resistor. I can't measure it, since it is destroyed. Any thoughts?</p> <p><img src="https://i.ibb.co/PzVrHQ2/Resistor-full.jpg" alt="Full board" /></p> <p>I still can't measure anything, so what I am posting next is still hypothetical.</p> <p>The SMPS controller is a <a href="https://www.semicon.sanken-ele.co.jp/ctrl/en/product/category/AcDcConverter/detail/?product=STR-W6052S" rel="nofollow noreferrer">STRW6052S</a>. These were the best light incidences on the markings I got:</p> <p><img src="https://i.ibb.co/QXY6nZw/IMG-0125.jpg" alt="" /></p> <p><img src="https://i.ibb.co/ZBsMLcz/IMG-0127.jpg" alt="" /></p> <p>This trace in red comes from the bridge and caps, and goes straight to the aforementioned resistor:</p> <p><img src="https://i.ibb.co/1qsk16k/IMG-0122-bedit.jpg" alt="" /></p> <p>Looking at the STRW6052S datasheet, pg 21, the main traces should be as wide as possible, and they come straight from the bridge + caps:</p> <p><img src="https://i.ibb.co/Tg47hHs/ds1.jpg" alt="" /></p> <p>Also, on pg 23, Reference Design, we see that this is the only resistor rated for 1 W, or more than 1/8 W:</p> <p><img src="https://i.ibb.co/jg30gWL/refdes.jpg" alt="" /></p> <p>In the reference design it is R2, 0.27 Ω, a current detection resistor, very close to the 0.33 Ω on the physical board.</p> <p>It also makes sense that the 1 kV ceramic disk cap and the resistors next are fried, since they are on the same path of the rectified mains voltage, which is about 537 V (380 VAC):</p> <p><img src="https://i.ibb.co/j8SJqcx/IMG-0128.jpg" alt="" /></p> <p>These resistors are 2x 470 Ω, connecting PIN1 to the snubber and the primary. They are not shown on the reference design, and I am not sure what they are doing there.</p> <p>Now, here is the interesing part: the datasheet recommends that this current detection resistor should be a non-inductive part, pg 18:</p> <p><img src="https://i.ibb.co/Y0DnSzq/DS2.jpg" alt="" /></p> <p>So far I am inclined to think that this is actually a non-inductive resistor, and obviously should be replaced by another of the same kind.</p>

Is this a non inductive resistor? (bands won't match usual tables)

2024-02-10T13:32:56.917

700917

|capacitor|identification|

<p>You literally have the TDK part number (TDK ITEM NO) to look up via google. It will bring up a datasheet. Yes, those are surface-mount capacitors. <em>Are they something still used?</em> Such capacitors are fungible parts. There's nothing too special about them, so as long as the specs are what's needed in a design, they are as good as any other capacitor with similar specs. So yes, they'd be very much still used.</p> <p>If you think of selling them, a reasonable price would be like $10 per 5,000, free shipping in a small first class envelope. They are extremely cheap, and even cheaper when in bulk packaging and not on a tape. Normally they are sold in a tape that can be loaded into part placement machines as nobody is assembling these things by hand in volume production. When not on a tape, they need to be re-spooled before use, and that takes time and hassle. So, in the form you have, they are only of use to hobbyists, who have thousands of other sources to buy the same parts from.</p> <p>Even if this particular model of a capacitor is not made any more, they are fungible, so nobody really cares about the model. They care about capacitance, voltage, dielectric material, and maybe ESR, and that's about that for most users. So you have to be selling seriously under the price of new parts for anyone to bother buying them from you and not from a legit vendor.</p>

<p>I have literally 1 million of these. How are they attached and used? Are they capacitors? Are they something still used?</p> <p><img src="https://i.stack.imgur.com/Z543b.jpg" alt="enter image description here" /></p> <p><a href="https://i.stack.imgur.com/hqd2f.jpg" rel="noreferrer"><img src="https://i.stack.imgur.com/hqd2f.jpg" alt="enter image description here" /></a></p>

Is this a miniature capacitor?

2024-02-10T13:40:54.527

700918

|transistors|finfet|

<p>The channel region is adjacent to the <strong>source terminal</strong>. When the FET turns on, electrons from the source get swept into the channel (and then, after going through there, to the drain).</p>

<p>Until very recently I believed free electrons from the P-type substrate/body(minority charge carriers) form the inversion layer. This explanation works fine for planar MOSFET and FinFET type transistors</p> <p><a href="https://i.stack.imgur.com/rVy0Z.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/rVy0Z.png" alt="planar MOSFET" /></a> <a href="https://i.stack.imgur.com/rD7rR.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/rD7rR.png" alt="FinFET" /></a></p> <p>But in GAA transistors(RibbonFETs and MBCFETs), the substrate isn't connected to the channel at all. What's the source of free electrons in such a device?</p> <p><a href="https://i.stack.imgur.com/Qg1zM.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/Qg1zM.png" alt="MBCFET" /></a></p> <p><a href="https://youtu.be/3otqUu-7WUQ?si=tnNiR1c2XfirQ36v" rel="nofollow noreferrer">image taken from SamsungSemiUS</a></p>

What's the source of electrons formation of inversion layer?

2024-02-10T13:46:04.920

700938

|power-supply|operational-amplifier|adc|inverting-amplifier|

<blockquote> <p>I can't use an op-amp inverter, because load resistance will be variable, which makes fixed unity gain impossible.</p> </blockquote> <p>But you can, and you don't need to worry about &quot;fixed unity gain&quot;. You can use one (1) inverting op-amp per signal:-<br /> a) one to sense the voltage, and<br /> b) one to sense the current.</p> <p>In fact, the situation you have here is perfect for op-amps - and you won't need a negative power supply, you can use the same supply as for the ADC &amp; MCU (+5V); provided you keep the output of the op-amps below 5V.</p> <p>The schematic below shows the idea. Consider V2, which is the voltage of the shunt resistor, R1. When your &quot;old power supply&quot; Vx is supplying 30V to the load, this voltage will be negative wrt GND, and will be scaled at 0.5V per amp of load current (Since R1 is a 0.5ohm resistor). This is easily converted to a positive voltage by an inverting op-amp, U1, and then scaled by the ratio R7 / R8 - in this case, the scale is 1, so 1A of load gives V2=-0.5V which is converted to +0.5V by U1. You could make R7=200k ie: twice R8, so that the scale factor is 1A per volt, ie: 1V at U1 output represents 1A of load current. Adjust R7 and R8 to suit your particular requirements, just be sure to keep the value of R8 much higher than the value of shunt resistor R1 (so that the current in R8 is negligible and does not adversely affect the accuracy).</p> <p><a href="https://i.stack.imgur.com/8SAYA.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/8SAYA.jpg" alt="enter image description here" /></a></p> <p>Now consider V3, which is the voltage of the output of the power supply. We can remove R2 (200k) from the circuit, and connect R3 directly to U2's negative input. R6 converts the current flowing in R3 to a positive voltage that is proportional to the current in R6. Since the negative input of U2 is a &quot;virtual earth&quot; (so is the negative input of U1 for that matter), then the current in R3 is directly proportional to the voltage at V1. At 30V, R3 current is 30uA. This current flows in R6, which then sets the voltage at the output of U2. At 30uA, the voltage across R6 will be 3.0V, meaning that U2 output is one-tenth of V1.</p> <p>The simulation result (below) shows what happens when load current (current source I1) is swept from 0A to 1A. The horizontal axis is load current (current through R1).</p> <p><a href="https://i.stack.imgur.com/U3eCR.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/U3eCR.jpg" alt="enter image description here" /></a></p>

<p>I am implementing digital voltage and current measurement on an old power supply.</p> <p>Due to the design of the supply, I am forced to use the positive output probe as a common ground for my ADC and MCU.</p> <p>However, this means that both the voltages on R1 (0 to 0.5 V) and R2 (0 to 5 V) will be negative (as measured by V2 and V3) in reference to ADC and MCU, which I need to convert to positive for ADC measurement.</p> <p><a href="https://i.stack.imgur.com/57hCI.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/57hCI.png" alt="power supply voltage and curent measurement" /></a></p> <p>I can't use an op-amp inverter, because load resistance will be variable, which makes fixed unity gain impossible.</p> <p>I don't really have any other ideas.</p> <p>What would you do in my place?</p>

Need help inverting DC voltage without op-amp

2024-02-10T16:20:08.210

700940

|pcb|connector|soldering|manufacturing|tolerance|

<p>Even if you overcome your alignment issues (and they are issues), you are going to rip your SMD headers off the board the first time you try to unmate so many pins at the same time with them being separated by such vast distances across the board. Without a separation jig that can separate the boards directly in line with each other, the first time you try to unmate them it's going to tilt, jam, and then tear off some SMD headers.</p> <p>My experience was with boards that had a single 2x20 0.100&quot;, standard force, through-hole header. The force on all those pins adds up and the jamming gets worse the farther apart the pins are. If they were SMD square post headers, they would have torn off, and you have more pins and they are spaced farther apart. Going back, I would have used different connectors and I suggest you do the same.</p>

<p>I am designing two boards. The bottom one is the power board that contains power switches on IMS (metal-clad board), while the top board is the logic board (4-layer FR4). Board to board height is about 0.5&quot;.</p> <p>The connection of signals from top to bottom is through a 2.0 mm dual row pin header.</p> <ul> <li>the number of headers is about 20 pcs of 2x2 arranged in a 16 mm x 20 mm grid.</li> <li>On the bottom board the only option is an SMD male pin header.</li> <li>On the logic board I have multiple options: TH on the bottom layer, or SMD on bottom layer or SMD on the top layer with holes (the female header is made for variable board heights).</li> </ul> <p>Since there is a high number of connections I am worried about soldering tolerance which might cause the two boards to mate incorrectly.</p> <p>Question 1: which of the three options for female headers would be more suitable (I am thinking SMD is better since it has less play during soldering).</p> <p>Question 2: If no solution would give the required tolerance for all the headers to mate, should I consider reducing the number of headers (knowing that the layout and performance will be worse)?</p> <p>Any reference or guidance to where such information can be learned is highly appreciated.</p>

Tolerance of board-to-board headers

2024-02-10T16:27:03.427

700941

|capacitor|identification|

<p>Those are 10nF ceramic disk capacitors.</p> <p>The 3 is the multiplier. The 10 is the value in picofarads.</p> <p>That's 10 picofarads multiplied by 1000 (three zeroes.) That's 10000 picofarads, which is also called 10 nanofarads.</p> <p>That's a pretty standard way of marking ceramic disk capacitors. If it were just two digits then the value would be picofarads only. <a href="https://circuitdigest.com/calculators/capacitor-value-code-calculator" rel="nofollow noreferrer">Have a look here for a longer description.</a></p>

<p>I am trying to learn how to identify old capacitors I have. I haven't been able to crack the search &quot;code&quot;. I tried testing with my MESR100 ESR meter with no luck. Just says OL. Help finding a site where I can research better would help.</p> <p>Pictured is my latest conundrum:</p> <p><a href="https://i.stack.imgur.com/oRsBs.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/oRsBs.jpg" alt="enter image description here" /></a></p> <p><a href="https://i.stack.imgur.com/gvtZ5.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/gvtZ5.jpg" alt="capacitor" /></a></p>

What is this capacitor marked F 103?

2024-02-10T16:29:13.753

700959

|microcontroller|voltage|circuit-design|reset|

<p>The EN input is using a pull-up resistor and a pull-down switch, SW3.</p> <ul> <li>When SW3 is open the EN pin is pulled to 3.3 V by R11, a 10 kΩ resistor.</li> <li>When SW3 is closed the EN pin is connected to 0 V through the switch. R11 is still trying to pull EN high but the resistance of the switch is so much lower that it will always win!</li> </ul> <hr /> <p>From the comments:</p> <blockquote> <p>So essentially, if 3.3v has more current, then the EN pin reads high, if gnd has more current, then the EN pin reads low? Is there a formula that calculates the final voltage at the EN pin?</p> </blockquote> <p>Your understanding is quite garbled. Try this:</p> <ul> <li>The EN pin is very high impedance - tens or hundreds of MΩs. It draws so little current that we can ignore it.</li> <li>The EN pin is sensitive to <strong>voltage</strong>, not current. The datasheet will specify the logic threshold levels for the EN pin but we can simplify and say that we'd expect something in the range of<br /> <strong>0 V ≤ V_EN ≤ 1.2 V</strong> gives a logic <strong>0</strong> and<br /> <strong>1.7 V ≤ V_EN ≤ 3.3 V</strong> gives a logic <strong>1</strong>.</li> </ul> <p>There's no need for a formula.</p> <ul> <li>If the switch is closed V_EN = 0 V and is read as a 0.</li> <li>If the switch is open V_EN = 3.3 V because it is pulled high by R11 and is read as a 3.3 V. (Note 'V' for 'volt' is always capitalised.)</li> </ul> <p>It so happens that when the switch is closed that about 0.33 mA will flow through R11 and the switch to ground and is &quot;wasted&quot;. In long-life battery powered applications this might be a problem so further design work would be required to reduce the power loss.</p>

<p>I am a beginner and I am trying to make my own ESP32 development board, with a switch so that I can manually reset everything. I followed a tutorial online and it did this:</p> <p><a href="https://i.stack.imgur.com/10rHg.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/10rHg.png" alt="Schematics" /></a></p> <p>My question is, why does the EN pin (or the place circled in red) read low voltage when the switch is connected? The place circled in red should have 3.3 V running through it regardless, no?</p>

Connecting both 3.3V and GND switch to ESP32 EN pin?

2024-02-10T19:15:45.750

700971

|ltspice|frequency-response|

<p>I do not see <span class="math-container">\$C_{gdov}\$</span> in your model. This cap could be miller multiplied. This seems like a potential source of error in your modeling.</p> <p>Btw, your open loop gain is 1 (!). The intrinsic gain of your mosfet is 50 but the <span class="math-container">\$g_{ds}\$</span> (<span class="math-container">\$=1/r_o)\$</span> is in parallel with <span class="math-container">\$R_{D1}\$</span>,the open-loop gain at DC is then <span class="math-container">\$\frac{g_m}{g_{ds}+1/R_{D1}}\$</span>, which, given your small signal parameters, come out as 1. In other words, your mosfet doesn't have any open-loop gain to sustain a proper negative feedback operation.</p> <p>I suggest you increase the impedance of your feedback network such that the loading is negligible compared to your <span class="math-container">\$R_{D1}\$</span> resistor. Or better yet, use a proper current source.</p> <p>Just as an FYI, the output of this amplifier is given by (assuming your loop gain is large): <span class="math-container">$$ V_{out} = V_{gs}\left(1+\frac{R_{f1}}{R_{s1}}\right) + V_{in}\left(-\frac{R_{f1}}{R_{s1}}\right) $$</span></p>

<p>The first is the schematics from NMOS4 with parasitic capacitance:</p> <p><a href="https://i.stack.imgur.com/DVqMT.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/DVqMT.png" alt="enter image description here" /></a></p> <p>From DC analysis:</p> <pre> --- MOSFET Transistors --- Name: m3 Model: nmos-sh Id: 2.21e-04 Vgs: 8.28e-01 Vds: 8.42e-01 Vbs: 0.00e+00 Vth: 4.00e-01 Vdsat: 4.28e-01 Gm: 1.03e-03 Gds: 2.03e-05 Gmb: 3.08e-04 Cbd: 2.32e-14 Cbs: 3.32e-14 Cgsov: 3.58e-15 Cgdov: 3.58e-15 Cgbov: 0.00e+00 Cgs: 7.11e-14 Cgd: 0.00e+00 Cgb: 0.00e+00 </pre> <p>AC analysis:</p> <p><a href="https://i.stack.imgur.com/uQDYf.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/uQDYf.png" alt="enter image description here" /></a></p> <p>I tried to build an equivalent schematic with my .op analysis for the first schematic:</p> <p><a href="https://i.stack.imgur.com/U2AIc.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/U2AIc.png" alt="enter image description here" /></a></p> <p>The following is the AC analysis:</p> <p><a href="https://i.stack.imgur.com/w9i26.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/w9i26.png" alt="enter image description here" /></a></p> <p>You can see these two have significant differences in terms of AC frequency analysis.</p> <p>What's wrong with my capacitor model?</p> <p>The following is the asc file for whom is interested:</p> <pre><code>Version 4 SHEET 1 880 808 WIRE -224 16 -368 16 WIRE 32 16 -224 16 WIRE -368 32 -368 16 WIRE -368 160 -368 112 WIRE -304 160 -368 160 WIRE -368 176 -368 160 WIRE -368 176 -384 176 WIRE -368 208 -368 176 WIRE -304 256 -368 256 WIRE 192 256 192 208 WIRE 352 256 352 208 WIRE -608 288 -656 288 WIRE -576 288 -608 288 WIRE -464 288 -464 176 WIRE -464 288 -496 288 WIRE -416 288 -464 288 WIRE 32 288 32 16 WIRE -368 368 -368 304 WIRE -368 368 -656 368 WIRE -304 368 -304 256 WIRE -304 368 -368 368 WIRE 32 368 -304 368 WIRE 192 368 192 336 WIRE 192 368 32 368 WIRE 352 368 352 336 WIRE 352 368 192 368 WIRE -656 384 -656 368 FLAG -656 384 0 FLAG -224 16 VDD FLAG -464 288 VG FLAG -304 160 VO IOPIN -304 160 Out FLAG 192 208 Vicm FLAG 352 208 Vid FLAG -608 288 VIN SYMBOL nmos4 -416 208 R0 WINDOW 3 56 60 Left 2 SYMATTR Value NMOS-SH SYMATTR InstName M1 SYMATTR Value2 l=1u w=12.35u ad=6.2p as=6.2p pd=13.4u ps=13.4u SYMBOL voltage 32 272 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName VDD2 SYMATTR Value 1.2 SYMBOL voltage 192 240 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName Vicm2 SYMATTR Value 0.69 SYMBOL voltage 352 240 R0 WINDOW 3 24 152 Left 2 WINDOW 123 24 124 Left 2 WINDOW 39 0 0 Left 0 SYMATTR Value 0 SYMATTR Value2 AC 1 SYMATTR InstName Vid2 SYMBOL bv -656 272 R0 WINDOW 0 -60 23 Left 2 SYMATTR InstName VIN2 SYMATTR Value V=V(Vicm)+V(Vid) SYMBOL res -368 160 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName Rf1 SYMATTR Value {Rf} SYMBOL res -384 16 R0 SYMATTR InstName RD1 SYMATTR Value 1k SYMBOL res -480 272 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName RS1 SYMATTR Value 1k TEXT -528 -152 Left 2 !.MODEL PMOS-SH pmos(kp=45u,vto=-0.42, lambda = {0.1/1}, gamma = 0.5, phi = 0.7\n+TOX=4.0n CGSO=0.28n CGBO=0 CGDO=0.28n CJ=1.38m CJSW=1.44n) TEXT -528 -96 Left 2 !.MODEL NMOS-SH nmos(kp=180u,vto=0.4, lambda = {0.1/1}, gamma = 0.5, phi = 0.7\n+TOX=4.0n CGSO=0.29n CGBO=0 CGDO=0.29n CJ=3.65m CJSW=0.79n) TEXT -496 -184 Left 2 ;M1: l=1u w=12.35u ad=6.2p as=6.2p pd=13.4u ps=13.4u TEXT -688 48 Left 2 !.op\n.ac oct 10 100MEG 100G TEXT -688 24 Left 2 !;tf V(VO) Vid TEXT 104 32 Left 2 !.step param Rf list 1e2 1e3 1e4 TEXT -688 0 Left 2 !;dc VDD 0 1.8 0.01 </code></pre>

Why do these two NMOS frequency responses give significant differences in LTspice simulation?

2024-02-10T21:07:29.587

700978

|operational-amplifier|circuit-design|comparator|

<p>No, adding a high-value resistor there is an absolutely terrible idea.</p> <p>Adding the resistor doesn't change the load that the LM393 presents to the line, it merely prevents the line from driving it properly. The load current from the LM393's input will still flow just like before, but with the series resistor, it will also cause a voltage drop that makes the measurement very inaccurate. Additionally, it'll introduce a delay as it forms a RC low-pass together with the comparator's parasitic input capacitance.</p> <p>A 50 ohm terminated line has quite some drive strength, so you can (and should) attach the comparator's input to it directly, or at most via a protection resistor no greater than 1k ohms.</p> <p>You might also want to add a bypass capacitor (i.e. 10nF) from the comparator's non-inverting input to ground to buffer the voltage from the resistive divider.</p>

<p>I have a comparator(LM393B) on a preterminated transmission line(50 ohm) which is intended to detect low and high voltages, i.e. off and active levels.</p> <p>Would it be a good idea to attach a high-value series resistor R1 (i.e. 100k-1M) on the inverting input to reduce signal loading? The LM393B has BJT inputs and an open-collector output, the 1uF capacitor is per the TPA3123D2 datasheet.</p> <p><a href="https://i.stack.imgur.com/IhZ27.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/IhZ27.png" alt="Comparator circuit" /></a></p>

High value resistor on comparator input

2024-02-10T23:01:38.553

700986

|rf|impedance-matching|receiver|frequency-modulation|low-noise-amplifier|

<blockquote> <p><em>I would like the gain to be 24dB from the range of 88-108MHz</em></p> </blockquote> <p>This won't happen with the 2SC3837 because it has a transition frequency of only 1.5 GHz. That's the point when the current gain falls to unity and, you need current gain to achieve voltage gain. So, the transition frequency is a little less than 15 times greater the upper frequency of operation and, because current gain falls linearly with frequency, we can predict that the current gain at 100 MHz is a bit less than 23.8 dB.</p> <p>OK there are a few tricks that can be done such as resonating the input with an LC but, I don't think you will quite reach what you desire with that transistor. Try going for a BJT with an <span class="math-container">\$f_T\$</span> of 5 GHz.</p>

<p>I'm designing a RF receiver for FM Radio. I simulated the circuit in LTspice and got an output as shown below:</p> <p><a href="https://i.stack.imgur.com/BFJ44.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/BFJ44.png" alt="enter image description here" /></a></p> <p>This is OK, but I would like the gain to be 24 dB across the range of 88-108 MHz.</p> <p>The component values I chose for the amplifier are through trial and error, and I'm not sure if the input impedance I calculated is right. How can I calculate these values, and make a more stable amplifier with low noise?</p> <p>Schematic:</p> <p><a href="https://i.stack.imgur.com/XUY1p.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/XUY1p.png" alt="enter image description here" /></a></p>

How to design an RF frontend for an FM receiver

2024-02-11T02:59:50.770

701003

|feedback|

<blockquote> <p><em>What is the feedback β for this resistor feedback?</em></p> </blockquote> <p>This boils down to how much the output signal is attenuated at the gate (with the input VIN set to zero. So, it's a simple potential divider involving Rf1 and RS1.</p> <p>You should also take into account the AC small signal loading effect of Rf1 and RS1 on the drain voltage. This is usually not negligible. They are, in effect, a series connection in parallel with Rd1.</p> <blockquote> <p><em>Should we include the capacitor Cgd for this feedback?</em></p> </blockquote> <p>That's completely up to you. If you want accuracy then yes.</p>

<p>The first is the schematics from NMOS4 with parasitic capacitance:</p> <p><a href="https://i.stack.imgur.com/DVqMT.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/DVqMT.png" alt="enter image description here" /></a></p> <p>What is the feedback <span class="math-container">\$\beta\$</span> for this resistor feedback? And Should we include the capacitor <span class="math-container">\$C_{gd}\$</span> for this feedback?</p> <p>The following is the asc file for whom is interested:</p> <pre><code>Version 4 SHEET 1 880 808 WIRE -224 16 -368 16 WIRE 32 16 -224 16 WIRE -368 32 -368 16 WIRE -368 160 -368 112 WIRE -304 160 -368 160 WIRE -368 176 -368 160 WIRE -368 176 -384 176 WIRE -368 208 -368 176 WIRE -304 256 -368 256 WIRE 192 256 192 208 WIRE 352 256 352 208 WIRE -608 288 -656 288 WIRE -576 288 -608 288 WIRE -464 288 -464 176 WIRE -464 288 -496 288 WIRE -416 288 -464 288 WIRE 32 288 32 16 WIRE -368 368 -368 304 WIRE -368 368 -656 368 WIRE -304 368 -304 256 WIRE -304 368 -368 368 WIRE 32 368 -304 368 WIRE 192 368 192 336 WIRE 192 368 32 368 WIRE 352 368 352 336 WIRE 352 368 192 368 WIRE -656 384 -656 368 FLAG -656 384 0 FLAG -224 16 VDD FLAG -464 288 VG FLAG -304 160 VO IOPIN -304 160 Out FLAG 192 208 Vicm FLAG 352 208 Vid FLAG -608 288 VIN SYMBOL nmos4 -416 208 R0 WINDOW 3 56 60 Left 2 SYMATTR Value NMOS-SH SYMATTR InstName M1 SYMATTR Value2 l=1u w=12.35u ad=6.2p as=6.2p pd=13.4u ps=13.4u SYMBOL voltage 32 272 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName VDD2 SYMATTR Value 1.2 SYMBOL voltage 192 240 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName Vicm2 SYMATTR Value 0.69 SYMBOL voltage 352 240 R0 WINDOW 3 24 152 Left 2 WINDOW 123 24 124 Left 2 WINDOW 39 0 0 Left 0 SYMATTR Value 0 SYMATTR Value2 AC 1 SYMATTR InstName Vid2 SYMBOL bv -656 272 R0 WINDOW 0 -60 23 Left 2 SYMATTR InstName VIN2 SYMATTR Value V=V(Vicm)+V(Vid) SYMBOL res -368 160 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName Rf1 SYMATTR Value {Rf} SYMBOL res -384 16 R0 SYMATTR InstName RD1 SYMATTR Value 1k SYMBOL res -480 272 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName RS1 SYMATTR Value 1k TEXT -528 -152 Left 2 !.MODEL PMOS-SH pmos(kp=45u,vto=-0.42, lambda = {0.1/1}, gamma = 0.5, phi = 0.7\n+TOX=4.0n CGSO=0.28n CGBO=0 CGDO=0.28n CJ=1.38m CJSW=1.44n) TEXT -528 -96 Left 2 !.MODEL NMOS-SH nmos(kp=180u,vto=0.4, lambda = {0.1/1}, gamma = 0.5, phi = 0.7\n+TOX=4.0n CGSO=0.29n CGBO=0 CGDO=0.29n CJ=3.65m CJSW=0.79n) TEXT -496 -184 Left 2 ;M1: l=1u w=12.35u ad=6.2p as=6.2p pd=13.4u ps=13.4u TEXT -688 48 Left 2 !.op\n.ac oct 10 100MEG 100G TEXT -688 24 Left 2 !;tf V(VO) Vid TEXT 104 32 Left 2 !.step param Rf list 1e2 1e3 1e4 TEXT -688 0 Left 2 !;dc VDD 0 1.8 0.01 </code></pre>

What is the feedback \$\beta\$ for this resistor feedback?

2024-02-11T09:24:48.253

701012

|power-supply|voltage|amplifier|

<p>From <a href="https://shop.griederbauteile.ch/info/l/LF13741.pdf" rel="nofollow noreferrer">this</a></p> <p><a href="https://i.stack.imgur.com/IChJG.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/IChJG.png" alt="enter image description here" /></a></p> <p>noise can be induced. Note that the PSSR is measured with both sides of power supplies changing.</p> <p>From <a href="https://archive.org/details/mc12cd_202110" rel="nofollow noreferrer">microcap v12</a>, here is an example ...</p> <p><a href="https://i.stack.imgur.com/3YkCk.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/3YkCk.png" alt="enter image description here" /></a></p> <p>If this is &quot;noise&quot;, it can be make &quot;noise&quot; at the output of an amplifier.</p> <p>Here is the effect of a square voltage around Vcc= 15 V. Resulting noise is 116 uV peak to peak.</p> <p><a href="https://i.stack.imgur.com/lylpz.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/lylpz.png" alt="enter image description here" /></a></p> <p>Here is another simulation (change of value of R6, added R-C decoupling).</p> <p><a href="https://i.stack.imgur.com/zvjQp.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/zvjQp.png" alt="enter image description here" /></a></p>

<p>Is it possible that a slight voltage difference between voltage rails of a symmetrical supply can make noise if connected to an amplifier?</p> <p>If yes, how do I get rid of it?</p>

Amplifier supply voltage difference

2024-02-11T10:59:29.280

701026

|operational-amplifier|simulation|ngspice|eda|netlists|

<p>Triangles are a symptom of slew rate limiting. LM324 has a typical slew rate of 0.5 V/us. That's not fast enough to swing 30V in 16 us.</p> <p>Flat sections are a symptom of limited output drive. LM324 has a typical positive drive of 30 mA, so it can only drive 9V into your 300 ohm load. Note that even with no load, it won't be able to drive 30V p-p with a 30V supply: see the &quot;Output voltage swing&quot; spec for the (somewhat complicated) details.</p> <p>Typical limits are not guaranteed: different models and different batches of chips may have different behaviors.</p>

<p>I'm newbie in ngspice and having a hard time to understand the LM324 models downloaded from various sources.</p> <p>Made an example with 4 different instances to demonstrate my doubt. The idealOpAmp works as supposed, but any instance of modeled LM324 (SN, ONSEMI, TI, etc) doesn't even get close. The circuit is just an non-inverting amplifier with G=3, for 32Khz (so way below LM324 bandwith limits). For convenience, cutted the relevant parts of the .libs (kept source refence inside), and annexed on the zip file with all parts.</p> <p>In my understanding, the instances of circuits should give similar results . On the following image, gwave vREFx3 shows the expected output (on ideal OpAMP), the others show different and strange results (different LM324 SUBCKT models). Don't know what i am doing wrong.</p> <ul> <li>environment:</li> <li>Debian BookWorm-6.1.0-16-amd64 #1 SMP PREEMPT_DYNAMIC Debian 6.1.67-1 (2023-12-12) x86_64 GNU/Linux</li> <li>lepton-eda - 1.9.18</li> <li>ngspice - 42+ds-2~bpo12+1</li> <li>gwave 20190116-2+b2</li> <li>bash</li> </ul> <p>Steps to reproduce:</p> <pre><code> export SCHEMABASE=teste324_02 lepton-netlist -g spice-sdb -O sort_mode -o ${SCHEMABASE}.net ${SCHEMABASE}.sch ngspice -b -r ${SCHEMABASE}.dat ${SCHEMABASE}.net gwave ${SCHEMABASE}.dat </code></pre> <p>Source schema: <a href="https://drive.google.com/file/d/1S_p6NQvpbgfAAwNOViOlZFVIHN_2OdsF/view?usp=sharing" rel="nofollow noreferrer">ZIP file with complete schematic and support files</a></p> <p>Demonstration: <a href="https://i.stack.imgur.com/hAlhG.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/hAlhG.png" alt="gwaveView " /></a></p> <p>Circuit: <a href="https://i.stack.imgur.com/bW3aR.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/bW3aR.png" alt="Schematic Image" /></a></p>

Help on LM324 SUBCKT model

2024-02-11T13:33:28.157

701030

|circuit-analysis|multivibrator|monostable|one-shot|

<p>Most monostable circuits are based on a property of capacitors - the voltage across a capacitor cannot change instantaneously. Thus, if you yank one end of a cap from one voltage to another rapidly, the other end of the cap will change by the same amount. If it was at a different potential before the yank, as coupling capacitors often are, the potential difference across the cap will be maintained briefly before the circuit currents work to stabilize the cap an new, post-yank voltages.</p> <p>U1 is a logic gate, so its output has only two (idealized) valid states: Vcc and GND. When the circuit is at rest and S1 is open, P1 holds the inputs to U1B low, so its output is high, so both inputs to U1A are high, so the U1A output is low. Thus, C3 has 0 V across it; both sides are at GND.</p> <p>When S1 closes, the logic low at U1A propagates around the positive feedback loop and appears at the other U1A input as a low: U1A out goes high, both sides of the cap go high (see above), the inputs to U1B go high, U1B out goes low, and that low is fed back to a U1A input. This is the start of the timing period.</p> <p>Because of how a NAND gate functions, this low holds the loop in this &quot;triggered&quot; state even if S1 is opened, or bounces, or is pressed multiple times. The 100% positive feedback loop that is a characteristic of a &quot;true&quot; monostable causes a kind of input lockout during the timing period.</p> <p>All of that happens in less than 1 microsecond after S1 closes. Now the timing starts to happen. When the right side of C3 snaps high, it immediately begins to charge down through P1, causing the voltage at the U1B inputs to decrease slowly. How slowly? That is the what makes this circuit useful.</p> <p>Terminology: Charging down and discharging are not the same thing. In discharging, the total charge in the cap is decreasing, as is the voltage across it. In charging down, the charge in the cap is increasing, but the voltage at the end we are interested in is decreasing with respect to GND because that end of the cap was at Vcc with zero charge in it. The voltage across the cap is increasing, but since the positive end is clamped at Vcc, the U1B inputs see a downward voltage slope.</p> <p>All logic gates have an input characteristic called the threshold voltage, the input voltage at which the gate &quot;sees&quot; a change from one logic level to another. In your circuit you have Schmitt trigger gates that have two threshold voltages, but that does not affect the basic operation of the circuit. The U1B input voltage decreases exponentially, at a rate determined by the values of P1 and C3. Eventually, the decreasing cap voltage moves through the gate threshold voltage. While its input voltage continues downward toward GND, the U2B output goes high. This is the end of the timing period.</p> <p>The timing period ends no matter the state of S1. At this point there is 5 V across C3, and this needs to be discharged to 0 V for the next timing cycle to be accurate. How the circuit resets itself does depend on S1. If S1 is open, both inputs to U1A now are high, and its output goes low. yanking the left side of C3 low means yanking the right side from GND to -Vcc, again because the voltage across a cap cannot change infinitely fast. -Vcc is a bad thing to apply to the input of any logic gate. While many logic types have internal protection against ESD transients of both polarities, often these structures cannot handle the energy dump of a large timing capacitor. D3 protects against this damage. D3 begins to conduct at around -0.6 V, clamping the U1B inputs at a safe level and basically short-circuiting C3 down to 0.6 V across it. After that, P1 discharges C3 the rest of the way down to 0 V. If S1 is closed immediately after a timing period ends, the residual charge in C3 will mean a shorter timing cycle.</p> <p>If S1 is closed at the end of a timing cycle, the U1A output remains high and the circuit is parked with 5 V across C3. When S1 is opened, the circuit will reset as above. This can be important, because at first glance it appears that the U1A output is identical to the U1B output, but inverted. It is, but only if S1 is open at the end of the timing period.</p> <p>With appropriate logic level shifts, this circuit can be adapted to work with any type of logic gate. The only criteria is that the the loop be non-inverting. Thus, two AND, OR, or NOR gates will work. Two simple inverters also will work with the addition of 1 resistor and 1 diode. .</p>

<p>I've seen a monostable multivibrator circuit shown below. The purpose of the circuit is to provide a power to a circuit for an amount of time controlled by potentiometer after pressing the momentary pushbutton. The power supply connected with a 1k resistor is a load circuit. The second power supply is designed for powering the monostable circuit. I created an simulation from the circuit photo and it consumes very low current (few nA), it is much less than CMOS NE555 or CD4541. Could someone explain the principles of operation of this system and its possible disadvantages/drawbacks? <a href="https://i.stack.imgur.com/gHRkW.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/gHRkW.png" alt="enter image description here" /></a></p> <p>Link to the simulation: <a href="http://tinyurl.com/25jcl3kw" rel="nofollow noreferrer">http://tinyurl.com/25jcl3kw</a></p>

Analysis of NAND-based low-power monostable circuit

2024-02-11T14:03:32.043

701035

|analog|switching|current-mirror|chip-design|

<p>How about putting a PMOS between Isens and your load, and another PMOS between Isens and ground? Invert the gate drive between them. This doesn't shut down the mirror, but steers its current to ground when you don't want it going to the load.</p>

<p>I have started learning microelectronics design and I am currently working on my bachelor thesis. There's one thing I wanted to ask you about current mirrors and its switching.</p> <p>My thesis is mainly focused on converting sensor's changing resistance to current, then to frequency. Firstly, I charge the capacitor with constant current and then discharge it with constant current as well. During the discharging, I want to turn off the current mirror responsible for charging the capacitor.</p> <p>Problem is, I have tried placing PMOS transistor in parallel with my PMOS current mirror, but it turned off my reference part of the mirror as well (which has to be active all the time).</p> <p>Some of you may say: ,,Why don't you just put PMOS transistor in series with your load part of the circuit and control it that way?&quot; Yes, it may be possible, but when the switch opens, the current mirror tries to push the current through infinite load and it creates voltage spike until it settles. So I discarded that idea.</p> <p>I will show you the diagram so you can better understand my problem (blue part has to be disconnected).</p> <p><a href="https://i.stack.imgur.com/Pr6Xe.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/Pr6Xe.png" alt="enter image description here" /></a></p> <p>If I explained something incorrectly, I would be glad if you showed me the right way to do it. I am willing to learn all the time :). Any opinion will be gladly received.</p> <p>Thank you!</p>

Disconnecting load circuit from reference [current mirrors]

2024-02-11T15:14:30.567

701042

|power|ac|emc|interference|5v|

<blockquote> <p>Should I worry?</p> </blockquote> <p>Regarding data transmission, no worries, Ethernet is extremely robust.</p> <p>CAT5 has a loop resistance of about 0.2 ohm/m (this is for both wires of one pair over 1m). So for 30m you get 6 ohms resistance on your power supply. With your quoted 200mA current draw, this will drop 1.2V, so you'll get 3.8V on the LDO input (assuming there is no reverse polarity protection diode).</p> <p>AMS1117 won't work with such a low dropout. Besides, this LDO is really bad, it's slow, needs an expensive cap, tends to burn on overcurrent, etc. A good pinout-compatible replacement is LDL1117 from ST. It will deliver 3.3V from 3.8V input. When replacing AMS1117 with LDL1117, the 10µF tantalum output cap must be replaced with a 10µF MLCC. A side effect of the much improved transient response is much rarer crashes and reboots.</p> <p>Note if you just want a temperature sensor, there are simpler solutions. DS18B20 works fine with 30m wires, and there are plenty of cheap Zigbee sensors on the market too.</p>

<p>I'm planning to put several Ethernet ESP32s with AMS1117 5 V to 3.3 V power converters and SHT31 temperature sensors around my house to report temperatures. They will be connected over Ethernet; power to the ESP32s will be delivered by free pairs in UTP cable.</p> <p>Originally I planned to use PoE, but I found a big problem: the PoE converter emits too much heat and makes the SHT31 self-heating.</p> <p>Could I just get rid of thePoE converters and power the ESP boards with 5 V from a central power supply, with some capacitor on the end of the wires?</p> <p>Maximum distance from the Ethernet switch is 30 m and current drawn by the board is quite low (max. 200 mA), so voltage drop shouldn't be an issue.</p> <p>What I'm worrying about is that Ethernet cables will placed along 230 V lines. My house is a pure residential environment, no electric motors or any induction style devices, but I'm still worried about interference from the 230 V lines.</p> <p>Should I worry?</p> <p>Thank you very much for your answers! It looks like i've calculated voltage drop incorrectly and you're right :/ I'll go with other solution for powering device, probably adding some 12V-&gt;5V converter on end.</p>

ESP32 powered over long lines with 230V

2024-02-11T16:14:13.693

701048

|feedback|negative-feedback|

<p>This is the correct abstraction of your NMOS common-source amplifier into a nullor. Note, this is an AC representation, which is the reason why I'm connecting <span class="math-container">\$R_D\$</span> to ground. You can of course connect it to supply for simulation purposes.</p> <p><a href="https://i.stack.imgur.com/WgvXy.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/WgvXy.png" alt="Nullor abstraction of common-source amplifier" /></a></p> <p><strong>EDIT:</strong></p> <p>You can write 2 equations out of this nullor. First, the one that will get you transfer function already. Apply KCL at the virtual ground, which is held at 0 due to the nullator at the input which equates both (+) and (-) inputs. I assume <span class="math-container">\$V_{out}\$</span> is the output node (top of <span class="math-container">\$R_{d}\$</span>).</p> <p><span class="math-container">$$ \frac{0-V_{out}}{R_f}+\frac{0-V_{in}}{R_s}=0 $$</span> After some algebra, we arrive at the well-known inverting amplifier gain equation: <span class="math-container">$$ \frac{V_{out}}{V_{in}}=-\frac{R_f}{R_s} $$</span></p> <p>You can write another KCL equation at the output. If assume there's a current <span class="math-container">\$I_L\$</span> coming <em>out</em> of the (-) terminal of the nullor output, then this will divide over <span class="math-container">\$R_f\$</span> and <span class="math-container">\$R_d\$</span>. <span class="math-container">$$ I_L = \frac{V_{out}}{R_D}+\frac{V_{out}}{R_f} = V_{out}\left(\frac{1}{R_D}+\frac{1}{R_f}\right) $$</span></p> <p>However, all this is saying is that the current at the output of the nullor is given by <span class="math-container">\$V_{out}\$</span> divided by the parallel combination of <span class="math-container">\$R_D\$</span> and <span class="math-container">\$R_f\$</span>. Well, that's expected as the load current will depend on the loading conditions of the amplifier, BUT NOT the output voltage... that's the whole point of a voltage amplifier.</p>

<p>The first is the schematics from NMOS4 with parasitic capacitance:</p> <p><a href="https://i.stack.imgur.com/DVqMT.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/DVqMT.png" alt="enter image description here" /></a></p> <p>I recently read an article on how to analyse the circuit with <a href="https://www.designalog.com/uncategorized-en/the-nullor-and-some-applications-part-i/" rel="nofollow noreferrer">The Nullor and Some Applications</a>.</p> <p>The equivalent nullor circuit. I am not sure this is correct. Can anyone point my error if there is any?</p> <p><a href="https://i.stack.imgur.com/0tzMa.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/0tzMa.png" alt="enter image description here" /></a></p>

How to analyse this with nullor block?

2024-02-11T16:39:32.817

701052

|safety|maximum-ratings|

<p>First of all, you have to ask your client why he had 127VAC LED modules before and what's the voltage of the wires leading to the indicator LED's in his installation. If your client answers that it's a machine working with a special power source giving 127VAC, then you should advise him to look for the same 127VAC LED modules. Because the 110VAC LEDs may shine too brightly and consume too much. They may fail earlier but this is still long/mid term issue. They won't fail after 3 weeks or something. But they will have to be replaced earlier.</p> <p>Depending on the quality, and on the internal circuitry of the LED module, it could be that they perfectly support 127V without overconsuming and without yielding too much light and respecting their advertised lifespan. But since there is no datasheet and the product is classified as <em>cheap</em>, I wouldn't bet on it.</p> <p>There is high chance that the voltage used is the regular 110VAC and that the old LED modules were rated with a margin <em>up to</em> 127VAC. But your client should confirm that this is the case. In this case, of course, there is no reason not to use them.</p> <p>This more a commercial advise than a technical one: Always talk with the client and spend time explaining the pro and cons.</p>

<p>The available LEDs have no famous brand so they don't have a specific datasheet where you can search and look-up online. So I need a general answer to my question based on the &quot;most common&quot; behavior of the LEDs, or based on a previous experience that you may have had before.</p> <p>I'm a sales electrical engineer and I want to sell the 110V LEDs to a factory and they will replace the existing 127V LEDs. I haven't tried it before but I would assume that the new 110V LEDs won't fail because the is no big difference in the rated voltage that they bear. I also think that the 110 V will be brighter, and their lifespan will be reduced a little.</p> <p>Are my assumptions right and should I sell the LEDs based on these assumptions? Or Will they fail immediately (as if I connect a 12V LED to a 220V source)? Are there any factors to put into consideration?</p> <p>Thank you so much,</p> <p><a href="https://i.stack.imgur.com/XbcZ0.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/XbcZ0.png" alt="enter image description here" /></a></p>

Is it okay to replace a 127 V indicator LED with a 110 V one? (Both are AC)

2024-02-11T17:06:02.570

701060

|resonance|inductive|wireless-charging|

<blockquote> <p><em>From what I gather higher frequencies allow for more efficient power transfer</em></p> </blockquote> <p>No, that is not correct. At the higher frequencies (such as high VHF or UHF) it's more likely that you'll be transmitting a propagating EM wave and, only a fraction of that power will reach the receiver; the rest is lost.</p> <p>With lower frequency near-field coupling, the energy wasted on generating an EM wave is much smaller (governed by physical dimensions) hence, because you will be receiving the near-field electric or magnetic fields (note that I didn't say EM fields), there is little energy lost.</p> <blockquote> <p><em>would I be better off with an resonant frequency in the MHz range or GHz range?</em></p> </blockquote> <p>It totally depends on your application and requirements and, I'm not going to guess at those. But, I will say this; I'm quite happy with my designs that run sub-MHz but, like I said, my designs are aimed at a specific target application.</p> <blockquote> <p><em>And if so what would you say is an ideal range for me to aim for?</em></p> </blockquote> <p>This cannot be answered.</p> <blockquote> <p><em>Ideally I want make a low cost extension cord that is power efficient for a 13 ampere circuit</em></p> </blockquote> <p>This doesn't make sense.</p>

<p>I am having a go at designing an extension cord that uses resonant inductive coupling. My knowledge lacks in this area, so I'm going back and forth via online research &amp; chatgpt 3.5.</p> <p>From what I gather, higher frequencies allow for more efficient power transfer but it can also raise additional challenges and costs.</p> <p>Ideally I want make a low cost extension cord that is power efficient for a 13 ampere circuit but also if I decided to put in a large volume order it is not going to break the bank to do so / charge a fortune to an end user.</p> <p>With that being said, would I be better off with a resonant frequency in the MHz range or GHz range?</p> <p>If so what would you say is an ideal range for me to aim for?</p> <p>Edit:</p> <p>Sorry, let me make better sense of the idea, I'm trying to design a modular power strip. Everything is modular including the socket (will house a receiving coil &amp; inductor) &amp; socket base (which will house a transmitting LC circuit), additionally I wanted to make it so that actual sockets had unlimited rotation.</p> <p>I had originally looked at slip rings, realised they're too expensive for this application, so started looking into Resonant Inductive coupling, whereby you could insert any form of socket into the socket base, rotate it to how you want it (cable management) without fear of losing power.</p> <p>The entire power strip socket base is also modular, so you could attach more bases think nano leaf but as a power strip.</p> <p>I've already figured out I'll be having to use 14 AWG wire to achieve the current need.</p> <p>Distance between the actual socket base and socket is planned to be only couple cm's at most.</p> <p>So back to my original question, I'm looking for what frequency would be best for the short distance and achieve everything above I've stated.</p>

Ironing out a design for resonant inductive coupling on 13A. Would I be better off with MHz or GHz for efficient power transfer?

2024-02-11T18:20:41.550

701071

|circuit-analysis|transfer-function|frequency-response|

<p>Lets assume that the source voltage <span class="math-container">\$e(t)\$</span> is given by <span class="math-container">$$ e(t) = u(t) V \leftrightarrow E(s) = \frac{1}{s} V$$</span> where <span class="math-container">\$E(s)\$</span> is the laplace transform of <span class="math-container">\$e(t)\$</span> and <span class="math-container">\$u(t)\$</span> is a unit step function. The voltage <span class="math-container">\$u_2(t)\$</span> with laplace transform <span class="math-container">\$U_2(s)\$</span> then follows to <span class="math-container">$$ U_2(s) = \frac{Z(s)}{Z(s) + R} \cdot E(s)$$</span> by making use of kirchhoffs current and voltage laws. In the following i will assume that <span class="math-container">\$Z(s)\$</span> takes the form <span class="math-container">$$ Z(s) = K\frac{s + a}{s + b}$$</span> based on your description of the response of the first circuit. It is left as an exercise for you to determine the correct parameters <span class="math-container">\$K, \,a,\,b\$</span>. This leaves us with the following expression for the desired voltage in the laplace domain <span class="math-container">$$ U_2(s) = \frac{Ks + Ka}{Ks + Ka + R(s + b)} \frac{1}{s} V.$$</span> Finally we need to perform the inverse laplace transform of <span class="math-container">\$U_2(s)\$</span> to get <span class="math-container">\$u_2(t)\$</span> in time domain. First we identify the poles by setting the characteristic polynomial in the denominator equal to zero and calculating the roots as done below <span class="math-container">$$ s((K+R)s + (Ka + Rb)) = 0 $$</span> <span class="math-container">$$\rightarrow s = 0 =:s_1 \,\, or \,\, s = - \frac{(Ka + Rb)}{(K+R)} =: s_2.$$</span> In a second step we perform a partial fraction decomposition <span class="math-container">$$ U_2(s)/V = \frac{[U_2(s)\cdot (s - s_1)](s \rightarrow s_1)}{s - s_1} + \frac{[U_2(s)\cdot (s-s_2)](s \rightarrow s_2)}{s - s_2}$$</span> where <span class="math-container">$$[U_2(s)\cdot (s - s_1)](s \rightarrow s_1) = \lim_{s\rightarrow s_1} U_2(s)\cdot (s - s_1).$$</span> (Warning: This direct method of calculating the coefficients in the denominator work only for poles with multiplicity of 1. The method has to be adjusted for poles with greater multiplicity and for cases where the numerator polynomial is of higher or equal order than the denominator polynomial.)</p> <p>The third step of attaining <span class="math-container">\$u_2(t)\$</span> in time domain is done by applying the inverse laplace transform to each term of the partial fraction sum (i.e. looking up the inverse transform in corresponding tables). In our case we will get <span class="math-container">$$u_2(t)/V = ([U_2(s)\cdot (s - s_1)](s \rightarrow s_1) + [U_2(s)\cdot (s - s_2)](s \rightarrow s_2)\cdot e^{s_2 \cdot t } ) \cdot u(t) .$$</span> To summarize, first determine all the poles (and relative degree). In a second step perform a partial fraction decomposition. And third, apply the inverse laplace transform to each term. The final result will be the response signal in the time domain.</p>

<p><a href="https://i.stack.imgur.com/b7tKz.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/b7tKz.png" alt="enter image description here" /></a></p> <p>Goal is to solve for the voltage u₂(t)</p> <p>I'm somewhat confused by this. I solved the transfer function Z(s) earlier in the top circuit, which is simply just Z. The voltage across Z in the top circuit is <span class="math-container">$$u_1(t)=5e^{(-100t)}u(t)$$</span> and the current source is j(t) = u(t), where u(t) is the step function. Z is a circuit system itself with no independent sources and all initial values are zero.</p> <p>Using basic principles for u₂(t) you obtain e(t)·Z/(R+Z), where again e(t) = u(t), so it's u(t)·Z/(R+Z).</p> <p>Obviously, just from that equation you can't solve for voltage. I'm thinking this has something to do with the frequency response, but I don't know how I'm supposed to use it for this problem.</p> <p>Z(s) is the same in both circuits.</p>

Transfer functions to determine voltage of a similar circuit

2024-02-11T19:58:30.827

701073

|led-strip|bluetooth-low-energy|reverse-engineering|

<p><strong>UPDATE AND SOLUTION</strong></p> <p>After getting the Nordic nRF52840 Dongle working to sniff BLE packets, I was able to capture and decipher enough ATT packets from the manufacturer's app to the LED controller to learn what I needed to. I was also able to write a Windows console app to send commands. Here are some takeaways in case someone sees this in the future:</p> <ul> <li>The nRF dongle can be fiddly. The instructions from Nordic for getting it running and capturing to Wireshark are good, but there would be times where it just quit (didn't appear in the list of Wireshark options). Restarting usually fixed this - I think maybe there were problems with assigned COM ports.</li> <li>Make sure the target (GATT server) is not connected to anything else, even the nRF Connect app before you try to capture packets.</li> <li>It turns out that, yes, the controller does just write out &quot;012345678&quot; on the writable characteristic whether you send a successful command or not.</li> <li>FWIW, here are some example commands for this particular brand of LED strips (GUPUP): <ul> <li>The final two bytes of all commands are CRC, specifically CRC-16 (MODBUS, big endian, normal). I found this out by using <a href="https://www.scadacore.com/tools/programming-calculators/online-checksum-calculator/" rel="nofollow noreferrer">this site</a>. If you are revere engineering a different set of commands that have CRC bytes, you can input the command and check this site's outputs against captured packets.</li> <li>Turn on: A0110401b121</li> <li>Turn off: A011040070e1</li> <li>Change color: A01506RRGGBBnnnn where RR, GG, and BB are hex values for the color and nnnn are the two CRC bytes</li> <li>Change brightness: A01304xxnnnn where xx is 0 to 100 in hex</li> <li>etc.</li> </ul> </li> <li><a href="https://www.youtube.com/watch?v=CozmqN_iwNs" rel="nofollow noreferrer">This video</a> walks through how to create a C# console app for Win 10 that talks to the a BLE device. Be warned, .NET and Visual Studio change so often that it doesn't take long for certain parts of code tutorials to go stale. In my case (in March 2024), I was unable to add Windows.Devices as done in the video. There are a few fixes for this out there that are already also stale, but what worked for me was to change the target .NET version (the TargetFramework field in the .csproj XML file) from 'net8.0' to 'net6.0-windows10.0.19041.0'. I have no idea how proper or sustainable this is - it was just the first thing I tried that worked.</li> </ul> <p>Good luck, fellow reverse engineers!</p>

<p>I am trying to create a custom application to control some Bluetooth-controlled LED strips. That is, I would like to reverse engineer how they are controlled without having any datasheet -- I'll figure out the control software itself later. There are a number of tutorials out there, but I have come up against a problem when trying to command them myself.</p> <p>The LED strips are made by GUPUP (?) and the documentation I've been able to find just describes how to use them with their own app.</p> <p>I have learned a bit about BLE and GATT and have gotten to the point where I can see a powered-up strip on nRF Connect (on an iPhone) and the services it advertises. There is just the one with an unnamed Notify characteristic and an unnamed Read/Write characteristic:</p> <p><a href="https://i.stack.imgur.com/x2Ryx.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/x2Ryx.png" alt="[nRF image]" /></a></p> <p>These are consistent with what I see in LightBlue (another iPhone Bluetooth scanner):</p> <p><a href="https://i.stack.imgur.com/HHBoj.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/HHBoj.png" alt="[LightBlue image]" /></a></p> <p>There are plenty of tutorials out there where at this point, I would just write to the writable characteristic and change the color, but I get stuck here. When I try to write to it, not only does the strip not react, the value of the characteristic doesn't even seem to change. The log files from the apps show the write requests, but I can't get the value to be anything other than what you see there: 3031 3233 3435 3637 3800</p> <p>Meanwhile, I can change the color using either the provided remote (which looks like the same one all Bluetooth LED products come with, but cannot control another Bluetooth LED I have) or the manufacturer's app (&quot;Allbest Home&quot; for iPhone). Those changes do not alter the writable characteristic's value, either, but they do trigger a message sent back on the Notify characteristic when I change something.</p> <p>So unless I am scanning and/or writing to the characteristic wrong, it seems like these LED strips are controlled in some way that is more complex than just asynchronously writing RGB-encoded bytes. Not sure if it's a coincidence, but the characteristic value that won't change seems to just be the null-terminated string &quot;012345678&quot; in ASCII.</p> <p>Any clues or leads for me to follow? Is there a time-based protocol (send this, then that, then the next thing, etc.)? Is it actually accepting my writes, processing them, but then overwriting the characteristic with &quot;012345678&quot; immediately after? In that case, I'd need to guess at the proper structure of the characteristic value since I can't get any feedback on successful requests other that a change in the lights themselves.</p> <p>I have seen third-party apps for controlling similar LED strips, so there must be people out there who have cracked them, but I am out of guesses for what to search for.</p> <p>I have ordered a Nordic BLE sniffer, but thought I'd post this while I wait in case someone has some insight.</p>

Reverse engineer BLE LED strip protocol

2024-02-11T20:01:15.003

701078

|transistors|mosfet|led|signal|

<p>Given the answer @nedd provided that the transistors is, more to the point a Programmable Unijunction Transistor, was the key to why the circuit was not working. (Had nothing to do with the load).</p> <p>So I was able to find an alternative/equivalent circuit to use, since my simulation software does not have a Programmable Unijunction Transistor in its library.</p> <p>Here is what works. I am however giving the answer to @Nedd for understanding the question and giving the reason for it not working, and linking to the video.</p> <p><img src="https://i.stack.imgur.com/QwsvD.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fQwsvD.png">simulate this circuit</a> &ndash; Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a>}</p>

<p>I am trying to recreate the circuit for a <strong>TWO PIN</strong> 12 Volt Electronic Flasher unit for LED turn signals. It is the inline flasher &quot;relay&quot; that I need. Where power comes in the B (Battery) pin and out the L (Load) pin.</p> <p>I have searched the net to find a 2 pin circuit but all I can find is the 3 pin.</p> <p>I found this guy's Youtube video, where he diagrams one but he does not give all the values and does not show some details. Like what MOSFET and Transistor.</p> <p><a href="https://youtu.be/mWQCSdkiYXg?t=83" rel="nofollow noreferrer">https://youtu.be/mWQCSdkiYXg?t=83</a></p> <p><a href="https://rads.stackoverflow.com/amzn/click/com/B07D33JGLC" rel="nofollow noreferrer" rel="nofollow noreferrer">Product he is referencing.</a></p> <p>Here is his diagram. I am just guessing at the MOSFET and transistor values. I need help getting this to work.</p> <p><img src="https://i.stack.imgur.com/amTzc.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2famTzc.png">simulate this circuit</a> &ndash; Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a>}</p> <p>Thank you.</p> <p>Need to add this. The load is not the issue here. Please stop bringing this up. The device obviously works and is demonstrated in the video. The need to add resistance is merely because he does not have it wired in a vehicle, where the wiring will add the resistance needed. That's how they are designed.</p> <p>The issue, is the DIAGRAM correct or is it not? Will it work? Is it a viable circuit? The guy in the video drew up the diagram but he could have drawn it incorrect. That is what I am here to find out. That is what I am asking.</p> <p>Pretend that the load is perfect. Assume that there is something wrong in the circuit. Where is it wrong. I have the circuit in my simulator and no matter how much resistance is added the flasher circuit itself does not work. I have used a LED tail light configuration with plenty of load, relays, solenoids, motors and it does not work. So Again, The load is not the issue here. Please stop bringing this up.</p> <p>To the people who keep trying to edit my question. Stop. Do not remove this since it is to save time and effort. It needs to be here, even tho it shouldn't need to be.</p>

Recreate an inline 12 Volt Electronic Flasher unit for LED turn signals

2024-02-11T21:20:15.593

701080

|operational-amplifier|amplifier|ac|audio|summing|

<h1>Introduction</h1> <p>Your question is specific and you got good specific answers that will help you solve the problem. But I suggest you take another step further to realize the &quot;philosophy&quot; of these famous circuits. Then you will not only know how to use them, but also really understand them.</p> <p>To do this, I suggest revealing the ideas behind these circuits by doing a number of experiments. Only two of them (framed in black) are your practiсal circuits; the others (framed in pale gray) are more abstract and only help to understand the ideas.</p> <h1>Are passive and active circuits related?</h1> <blockquote> <p>I can either use two resistors to combine the audio signals, or I can use a summing amplifier.</p> </blockquote> <p>Both circuits solve the same problem - <em>summing voltages</em>, but while the first is <em>passive</em>, the second is <em>active</em>. At first glance, they are different. But if you look carefully at the second circuit diagram, you will see that it contains the first one (the R1-R2 network); just another op-amp and resistor are added. This leads us to think that somehow the passive circuit has become active, or that <em>the active circuit is an improved passive circuit</em>. If we find out what this &quot;magic&quot; way is, we will be able to convert any passive circuit into an active one!</p> <h1>Passive summer</h1> <p>The simplest way to sum voltages is according to Kirchhoff's voltage law by connecting the sources in series (without any resistors). The problem is that the output voltage is &quot;floating&quot; (not relative to ground). That is why the alternative way by summing currents according to Kirchhoff's current law has been imposed.</p> <h2>Full circuit</h2> <p>To implement it, we can convert the input voltages (Vin1 and Vin2) by resistors (R1 and R2) into input currents (Iin1 and Iin2), and sum the latter. The output voltage Vout appears at the midpoint between the two resistors. As you can see, it is a 0.5 weighted sum of the two input voltages (you can calculate it by applying the superposition principle).</p> <p>Note that the same current Iin1 = Iin2 flows through both sources in the direction from Vin1 (the higher voltage) to Vin2 (the lower voltage). It looks like one current is input and the other is output, which is a bit confusing. So, the input sources must be <em>bilateral</em> (pass current in both directions).</p> <p><img src="https://i.stack.imgur.com/JuPkd.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fJuPkd.png">simulate this circuit</a> &ndash; Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a>}</p> <h2>Vin2 disconnected</h2> <p>As mentioned in other answers, if we remove one of the sources (e.g. V2), the weight factor of its other input changes (from 0.5 to 1), and this is a problem. There is no current flowing.</p> <p><img src="https://i.stack.imgur.com/npAYF.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fnpAYF.png">simulate this circuit</a>}</p> <h2>Loaded</h2> <p>Another problem appears if we connect a load to the output (I have simulated it in the schematic below by decreasing the voltmeter's resistance RL to 1 kΩ). It decreases the equivalent resistance (R1||R2||RL), the input weight factors (&quot;gains&quot;) and the output voltage. Now there is a true output current IL through the load but there is no Iin2 input current in this specific case (since VL = Vin2).</p> <p><img src="https://i.stack.imgur.com/gU3Bk.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fgU3Bk.png">simulate this circuit</a>}</p> <h2>The main problem</h2> <p>The networks Vin1- R1, Vin2-R2 and why not RL can be thought as <em>imperfect current sources</em> that &quot;like&quot; to be short connected (zero output voltage). Only then can they individually set their currents (Iin1 = Vin1/R1 and Iin2 = Vin2/R2).</p> <p>So <em><strong>the main problem of the passive resistor summer is that its output voltage is non-zero</strong></em>.</p> <h2>Short connected</h2> <p>Can't we just shorten its output? In the schematic below, the middle point is connected to the real ground (RG) through an &quot;ideal&quot; ammeter; the &quot;unwanted&quot; voltage is gone and the input currents are exactly Vin/R.</p> <p><img src="https://i.stack.imgur.com/nRaHB.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fnRaHB.png">simulate this circuit</a>}</p> <h2>How to destroy the &quot;undesired&quot; voltage</h2> <p>The problem, however, is that we need this voltage since it is the circuit output voltage. So we have to destroy it but have a &quot;copy&quot; of it.</p> <p>For this purpose, we can add another input of the summer to which we can apply (through another resistor) a voltage equal to the output but with the opposite polarity. As a result, the output voltage will be zero, and we can use the new input voltage as output.</p> <h1>Negative-feedback summer</h1> <p>This is usually done using the so-called &quot;negative feedback&quot;. Since the name does not tell us much, let's first do it the way they would have done it back in the 19th century.</p> <h2>&quot;Man-controlled summer&quot;</h2> <p>Following the recipe above, we connect a variable &quot;input&quot; voltage source Vout through a resistor R3 to the common point and also a grounded null indicator NI (sensitive voltmeter).</p> <p><img src="https://i.stack.imgur.com/rKqv6.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2frKqv6.png">simulate this circuit</a>}</p> <p>Next, we adjust Vout so that NI shows zero voltage (the so-called <em>virtual ground</em>). When we are done, Vout shows the exact sum of Vin1 and Vin2.</p> <p>Note that Vout is negative when the input voltages are positive. This is because Vout must be added to them when travelling the input loops (- +, - +).</p> <h2>With behavioral voltage source</h2> <p><strong>Unloaded:</strong> The summer above is perfect but we have to do this routine work. However, human beings are lazy by nature and look for someone to do this work :-) We are no exception and so we decide to outsource it to a <em>behavioral voltage source</em> VA from the CircuitLab library. Simply put, this is an abstract voltage amplifier (a prototype of the future real op-amp) with a gain of 100,000.</p> <p><img src="https://i.stack.imgur.com/q8R0B.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fq8R0B.png">simulate this circuit</a>}</p> <p>Now the &quot;conceptual op-amp&quot; adjusts Vout so that NI shows zero voltage.</p> <p><strong>Loaded:</strong> If we connect a load RL to the VA output, nothing changes since VA provides a current for the load.</p> <p><img src="https://i.stack.imgur.com/d1OEB.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fd1OEB.png">simulate this circuit</a>}</p> <h2>Op-amp inverting summer</h2> <p>Practical circuits are implemented using an op-amp. It does exactly the same as the conceptual circuits above do, only faster.</p> <p><strong>Full circuit:</strong> I have left the zero indicator just for us; the op-amp does not need it.</p> <p><img src="https://i.stack.imgur.com/BtWNQ.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fBtWNQ.png">simulate this circuit</a>}</p> <p><strong>Vin2 disconnected:</strong> the result is the same as in the Schematic 1.2 above.</p> <p><img src="https://i.stack.imgur.com/Bo1tJ.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fBo1tJ.png">simulate this circuit</a>}</p> <h1>No feedback summer</h1> <p>Although the principle of negative feedback is dominant, it is possible to achieve the same goal (Vout = 0 V) without it. Here are some more extravagant circuit solutions to get our imaginations going.</p> <h2>Negative-resistor summer</h2> <p>If we look more closely at the R3-Vout network, we will notice that the two elements are as if &quot;mirrored&quot; - R3 subtracts a voltage drop VR3 while Vout adds voltage VR3. This means that Vout acts as a <em>negative R3 resistor</em>.</p> <p>I was pleasantly surprised to see that CircuitLab supports negative resistances. So we can simulate this arrangement by connecting a -1 kΩ negative resistor -R3 in series to the positive resistor R3; the result is zero resistance (&quot;piece of wire&quot;) between the midpoint and ground.</p> <p><img src="https://i.stack.imgur.com/G3KmI.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fG3KmI.png">simulate this circuit</a>}</p> <p>But how do we implement a negative resistor?</p> <h2>With behavioral voltage follower</h2> <p>We can do it by a behavioral voltage source that copies the voltage drop VR3 and inserts it in series to VR3.</p> <p><img src="https://i.stack.imgur.com/u8FyW.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fu8FyW.png">simulate this circuit</a>}</p> <h2>With op-amp voltage follower</h2> <p>The practical circuit can be implemented by an amplifier with a fixed gain of 1 (voltage follower). Because there are not such a device in the CircuitLab library, I have reduced the gain of a conventional op-amp to 1. As you can see, the differential op-amp input is connected in parallel to R3, and the op-amp output is connected in series to R3. Also, I have set the op-amp output resistance to zero to eliminate the impact of the voltage drop across this resistance.</p> <p><img src="https://i.stack.imgur.com/qsU07.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fqsU07.png">simulate this circuit</a>}</p>

<p>I'm working on a project that requires me to mix two audio signals from two sources (both on the same PCB).</p> <p>Source one is an audio output coming from the the <a href="https://www.sparkfun.com/datasheets/Components/SMD/vs1053.pdf" rel="noreferrer">VS1053B MP3 Audio CODEC IC</a>, and source two is the output of a DAC (<a href="https://ww1.microchip.com/downloads/en/DeviceDoc/22248a.pdf" rel="noreferrer">MCP4921</a>). Both these audio signals will be going into a class-D amplifier <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&amp;gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftpa3110d2" rel="noreferrer">(TPA3110 from TI)</a>.</p> <p>I've been doing some research, and it seems to me that in order to do this, I can either user two resistors to combine the audio signals, or I can use a summing amplifier.</p> <p>What I don't understand are the pros/cons of one over the other. I would like to use two resistors since it's easier, but if this method is strongly inferior, then I may use a summing amplifier. What are the pros/cons of each method?</p> <p>Using resistors: <a href="https://i.stack.imgur.com/Cnhas.png" rel="noreferrer"><img src="https://i.stack.imgur.com/Cnhas.png" alt="enter image description here" /></a></p> <p>Using a summing amplifier: <a href="https://i.stack.imgur.com/fFCOD.png" rel="noreferrer"><img src="https://i.stack.imgur.com/fFCOD.png" alt="enter image description here" /></a></p>

Mixing audio signals: pros and cons of using resistors instead of an op-amp

2024-02-11T21:21:33.627

701113

|signal-theory|circuit-theory|

<p>You can't.</p> <p>Any matrix of resistors has a certain transfer charcteristics between input and output, and can only attenuate the input signal.</p> <p>You can only observe the transfer parameters how test signals on input affects the output, and how varying output load affects the input current.</p> <p>The problem is, these transfer characteristics can be represented in two different forms, both having three resistors. So you can either construct a T-network or a pi-network of resistors that has the exact same transfer function as the original arbitarily complex circuit of resistors.</p> <p>So as any network can be reduced into two different basic topologies of three resistors, you cannot in theory determine anything about the original topology.</p>

<p>Let's have a circuit only composed of resistors connected in a given topology. This topology (network) has a well defined boundary (input/output connectors) but otherwise we don't know how it is connected internally. We can perform all sort of experiments on the input/output (for example: connect them to other circuits). This is a thought experiment, in principle we do not have time/resources/practical limitations (for instance, the resistors doesn't burn).</p> <p>Is it possible to infer the internal topology in this conditions? What kind of measurements are the more informative?</p>

How can I infer a circuit topology only from measuring/controlling its input and output?

2024-02-12T05:11:39.467

701114

|microcontroller|pcb|stm32|usb|

<p>The datasheet says FT232R chip has an internal 1k5 pull-up resistor on D+.</p> <p>You don't need an external 1k5 resistor on D+.</p> <p>Depending on what you want to achieve, you may not need the FT232R either. The MCU has a built-in USB, which in most cases could be used communicate USB directly without FT232R.</p>

<p>I am designing a TYPE C plug with STM32L432KC MCU and was wondering how to physically position the 1.5 kΩ pull-up resistor on D+ connection.<br /> (male plug --- ft323 --- mcu)<br /> Should it be next to the MCU or close to the receptacle or what?<br /> Does it even make a difference?</p> <p><a href="https://i.stack.imgur.com/tTGBW.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/tTGBW.jpg" alt="enter image description here" /></a></p>

How to position the 1.5 kΩ pull-up resistor on USB Type-C D+ connection?

2024-02-12T05:28:54.993

701129

|inverter|feedback|buffer|sine|capacitive|

<h1><strong>Assumptions:</strong></h1> <p>I'm assuming you need to preserve the amplitude and frequency information of your signal. Therefore, you need a linear amplifier, which means, you need negative feedback. I also assume you don't mind inverting the signal as long as the gain=1.</p> <h1><strong>The Simplified Amplifier Circuit Architecture</strong></h1> <p>CMOS inverters lend themselves easily for inverting amplifier implementations, as we can readily use the 1st stage inverter gate as the virtual ground. See the circuit below:</p> <p><img src="https://i.stack.imgur.com/uZ47d.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fuZ47d.png">simulate this circuit</a> &ndash; Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a>}</p> <p>You can only do this with an odd number of stages, otherwise you don't have negative feedback. However, 1 stage only might provide too low of a loop gain (thus, poor distortion) and 5 stages will probably be a nightmare to frequency compensate. 3 stages should be the sweet spot.</p> <h1><strong>Problem: Inverter's sensitivity with respect to supply voltage</strong></h1> <p>Unfortunately, an inverter's transconductance can vary significantly over temperature and process corners and supply voltage. The process variation you can't avoid, the temperature and voltage variations you can with the solution below.</p> <h1><strong>Solution: Dedicated Voltage Regulators for the stages</strong></h1> <p>One way to overcome this is to bias your inverters such that they have a dedicated current through them, and have them track over temperature. To this end, you can design a regulator that provides a replica voltage to your inverters supply, like this:</p> <p><img src="https://i.stack.imgur.com/lEByk.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2flEByk.png">simulate this circuit</a>}</p> <p>(BTW, I'm just drawing schematics to illustrate my ideas, I didn't simulate any of these.)</p> <p>The nice thing about this regulator is that, say, if your &quot;model/replica&quot; inverters (M2 and M3) are of size <span class="math-container">\$W/L\$</span>, and have a current <span class="math-container">\$I_b\$</span>, then, in your actual stage, you can scale up your size as <span class="math-container">\$k\times W/L\$</span> and your current will be scaled up accordingly as well (it's a replica/model-based kind of biasing, so it'll never be super accurate, but you get the idea).</p> <h1>Extra Suggestion</h1> <p>As an extra, there might be a possibility of distorted currents from the 2nd stage coupling via the supply to the 3rd stage, which dominates distortion. That means it can have more distortion than usual. A way around this could be isolate the supply by putting dedicated regulators for 2nd and 3rd stage. Perhaps 1st stage can share the regulator with the 2nd. You have to experiment.</p>

<p>Is it possible to buffer a sine wave using inverters alone or with some kind of feedback?</p> <p>I've been browsing google for minimalistic (I'm in 3.3-12 V domain) sine wave buffers and this thought stuck in my mind.</p> <p>The idea was there, because I came upon <a href="https://chrome-extension://efaidnbmnnnibpcajpcglclefindmkaj/https://cmosedu.com/jbaker/students/theses/High%20Speed%20Digital%20CMOS%20Input%20Buffer%20Design.pdf" rel="nofollow noreferrer"><em>High Speed Digital CMOS Input Buffer Design</em> by Krishna Duvvada</a>, and I already asked a <a href="https://electronics.stackexchange.com/q/699297/83621">question</a> with this in reference but of a different kind, so I don't think I'm breaking any rules with this one.</p> <p>I realized, a bit later, that in that master thesis, that's actually not how you would wire the output of the first stage, the rail to rail input stage. Do you agree? So it's some kind of inverters structure basically.</p> <p>I don't have enough knowledge to contribute my thoughts, and my thoughts are currently very tangled, hence the question.</p>

Sine wave CMOS buffer from inverters with or without feedback

2024-02-12T08:40:14.687

701159

|inductor|radio|medium-wave|

<p>That coil serves two purposes: <strong>antenna</strong> and <strong>resonator</strong> (the resonator may require an associated capacitor). A choke is a terrible antenna, but may have lighter weight than a loopstick's ferrite.<br></p> <p>Andy's answer shows how a ferrite rod collects AC magnetic fields, aiding its purpose as antenna. If you wish to limit weight, use a long rod with small diameter. Such a rod is fragile, because ferrite is brittle.<br> Stacking rods end-to-end is theoretically possible, but very difficult to do practically, because magnetic coupling from rod-to-rod involves an inevitable air-gap.<br></p> <p>The alternative to ferrite rod antenna uses a large-diameter solenoid. The large diameter makes the resulting inductor a fairly efficient antenna with directional characteristics similar to a loopstick. However, with no ferrite, a great length of wire is required, which is also weighty. For example, a 1m diameter coil of 50 turns has about 5mh inductance.</p> <p>A choke inductor might have 5mh inductance, but is likely designed to confine magnetic field to itself, so that it doesn't radiate - opposite of what you want for an antenna.<br> Some inductors inside a radio are used with a capacitor as <strong>resonators</strong> and not as antennas. In this case, they tend to be choke-like, with carefully-confined magnetic fields. Small size is a design objective.</p>

<p>For reception in the medium wave range (500-1600kHz) a ferrite rod (loopstick) has a measured inductance of Lc=2mH and a resistance Rf=5 ohms, whereas an RF choke with Lf=2mH has a resistance Rc=8 ohms.</p> <p>Given that a choke is much smaller than a ferrite rod, why do medium wave (AM) radios use a ferrite rod rather than a choke to tune into radio stations?</p> <p><strong>Context</strong>: I am using a choke (4mH) and a capacitor (2.2nF) in parallel in a tank circuit with a resonant frequency of 50kHz, and I am wondering if I should be using a loopstick instead of a choke. I am using a choke because I need to minimise weight.</p> <p><strong>EDIT1</strong>: The following text and image were added for information after answers were received. From the comments below, it seems to matter that the choke has ferrite caps. Not sure if this is relevant, but I am trying to receive (not transmit) RF signals.</p> <p><a href="https://i.stack.imgur.com/OWTa8.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/OWTa8.jpg" alt="enter image description here" /></a> Figure 1. Picture of a (very) spare choke, with the plastic coating removed (I managed to break the wires inside in the process of removing the plastic). The material at both ends (caps) of the coiled wire is magnetic (ferrite?).</p> <p><strong>EDIT2</strong>: This edit has also been included as a <a href="https://electronics.stackexchange.com/questions/701556/why-do-loopsticks-and-chokes-receive-rfs-equally-well">new question</a>, so please put any responses there.</p> <p>The circuit in Figure 2 was used to test predictions made in answers to this question.</p> <p>The inductor was either a) a choke with Lc=0.54mH (R=3.2ohms) (as in the figure 1), or b) a loopstick with Ll=0.6mH (R=8.3 ohms)) (Figure 3, from a radio clock).</p> <p>A sinusoidal 1V (p2p) signal from a signal generator was injected across the whole circuit. The frequency was adusted to maximise the voltage across the tank circuit, which corresponds to the resonant frequency, measured as f0=40kHz (for both the choke and the loopstick).</p> <p>As an aside: The measured p2p amplitude across the tank circuit at f0 was 57mV, so that</p> <p>57mV/1000mV = Z/(Z+20k),</p> <p>so, solving for Z yields Z = 1200 ohms at f0.</p> <p>Finally, I disconnected the scope from the circuit, and used the scope to generate an RF signal at f0 through a long wire antenna. I then measured the amplitude V induced across the tank circuit at a short distance from the antenna.</p> <p>Result: With the loopstick, Vl = 4mV, whereas with the choke, Vc = 3mV.</p> <p>This seems to suggest that both the choke and the loospstick are almost equaly good at converting the RF signal into voltage. What am I missing?</p> <p><a href="https://i.stack.imgur.com/uFhv0.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/uFhv0.jpg" alt="enter image description here" /></a> Figure 2. Circuit used to estimate resonant frequency f0 and impedance Z of tank circuit at resonant frequency f0.</p> <p><a href="https://i.stack.imgur.com/GgfOy.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/GgfOy.jpg" alt="enter image description here" /></a> Figure 3. Loopstick used to replace choke in tank circuit.</p>

Why use a loopstick rather than a choke for MW radio frequency reception?

2024-02-12T12:56:05.863

701170

|batteries|lithium-ion|tp4056|

<p>Get a meter. Measure the voltage directly at the cell (not at the battery terminals).</p> <p>If the voltage of the cell is at least 2.8 V, the battery may be salvageable.</p> <p>If lower, do not attempt to circumvent the BMS and recharge the cell. Doing so may damage the cell such that it may blow up.</p>

<p>I made this Bluetooth speaker and I was happy it's working.</p> <p>I left it running and somehow the battery is dead. Battery voltage is now ZERO</p> <p>Any attempt to charge it using TP4056 board is not bringing it back to life.</p> <p>So the battery is totally useless? <a href="https://i.stack.imgur.com/StXEH.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/StXEH.jpg" alt="enter image description here" /></a></p>

How to revive this dead 3.7 V Li-ion pouch battery?

2024-02-12T14:48:40.103