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698452

|embedded|arm|breadboard|cortex-m4|

<p>There does not exist physical CPUs that only contain an ARM Cortex-M4 core with no peripherals. You always get them integrated with peripherals so you have an MCU.</p>

<p>I want to know if can I use an <a href="https://www.arm.com/products/silicon-ip-cpu/cortex-m/cortex-m4" rel="nofollow noreferrer">ARM-Cortex-M4</a> processor directly on a breadboard and then create a microcontroller on a breadboard. I already tried searching google but didn't find anything.</p> <p>Please note that I am taking about &quot;creating&quot; a microcontroller on a breadboard and NOT &quot;using&quot; a microcontroller on a breadboard.</p>

Using ARM Cortex on breadboard

2024-01-22T08:38:58.917

698455

|digital-logic|tri-state|high-impedance|

<p>If there's nothing else connected to the line, a circuit like this will do:</p> <p><img src="https://i.stack.imgur.com/D1eTX.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fD1eTX.png">simulate this circuit</a> &ndash; Schematic created using <a href="https://www.circuitlab.com/" rel="noreferrer">CircuitLab</a>}</p> <p>Run simulation to see how it behaves.</p> <p>Note that comparators are required, because the logic levels are non-standard. A simpler transistor-based version could be used, but probably takes as many or more components, even if resistor packs are considered.</p> <p>If <code>IN</code> is not allowed to float (something else is pulling on it), or must meet valid logic threshold voltage otherwise (because other CMOS/TTL inputs are connected), another solution is required, or no solution may be possible.</p> <p>I am assuming the tristate pin is available in isolation by itself.</p>

<p>I'm looking for an IC or small circuit that implements the following truth table:</p> <div class="s-table-container"> <table class="s-table"> <thead> <tr> <th>Input</th> <th>Output 1</th> <th>Output 2</th> </tr> </thead> <tbody> <tr> <td>H</td> <td>H</td> <td>L</td> </tr> <tr> <td>L</td> <td>L</td> <td>H</td> </tr> <tr> <td>Z</td> <td>H</td> <td>H</td> </tr> </tbody> </table> </div> <p>Is this possible?</p> <p>The purpose is to keep an SPI SS signal pulled high for two devices when the input is high-Z, and to otherwise select one of two devices. It would be possible to simply use an inverter but then one of the SS signals would always be active.</p>

Tri-state input to three logic states

2024-01-22T09:00:07.427

698460

|capacitor|measurement|

<p>As stated in the material you quote, DC source is used for measuring 'large' capacitors. AC impedance is therefore used for measuring 'small' capacitors.</p> <p>Check the ICT machine specifications to see whether the ranges overlap in 'medium sized' capacitors, where you could use either method.</p>

<p>My ICT machine has two capacitor measurement modes on the PCB:</p> <p>Mode 1: Use DC source test method (Figure 1)</p> <p><a href="https://i.stack.imgur.com/tDNol.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/tDNol.png" alt="enter image description here" /></a></p> <p>Mode 2: Use AC source test method (Figure 2)</p> <p><a href="https://i.stack.imgur.com/1rswj.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/1rswj.png" alt="enter image description here" /></a></p> <p>Could anyone please help me with the questions: What is the importance of each mode? When do we use mode 1? When do we use mode 2? It is best if we could compare these two modes.</p>

Capacitor test mode in ICT

2024-01-22T09:34:25.957

698476

|microcontroller|stm32|embedded|

<ol> <li>Data sheets and reference designs are just suggestions. Everywhere (AN5690, Discovery schematics) there are two caps shown on VREF+ pin, but sometimes there is 1uF and 100nF, sometimes 1uF and 10nF.</li> </ol> <p>The actual bypassing also depends on if you plan to use the VREF+ pin as output or input, and if you are going to use it as input, then it is about if you connect it directly to VDD on PCB, or to some other supply for the reference voltage.</p> <p>So if you don't know beforehand, just draw two caps on the PCB. Then validate your design how many caps you really need later. Or just leave in both caps as it likely does not matter if it is not required for operation.</p> <p>The point is, you can apply as much or as little bypassing as you need for your design to work with good margin.</p> <ol start="2"> <li><p>Apparently not, because you can either connect it to VDD/VDDA yourself, or turn on an internal reference so the pin is an output and pin must be connected to caps only.</p> </li> <li><p>Eval boards may be universal and the VREF+ may be connected to a jumper or solder bridge, which allows you to decide how to connect the reference pin, by moving jumper blocks around or soldering or unsolderint some blobs on the PCB. That can't be seen in the schematics as presented where the VREF+ is really going or is it left unconnected.</p> </li> </ol>

<p>I am currently working on a STM32G071C8U7 microcontroller schematic and have some questions regarding the decoupling and general connectivity of the power supply pins.</p> <ol> <li>First I am presented with this diagram that clearly indicates how VDD/VDDA should be decoupled. However, I am not sure about VREF+/VREF decoupling capacitors. Is 1 uF recommended regardless of the intended use of VREF+ pin and 100 nF is only recommended if an external VREF is used? <a href="https://i.stack.imgur.com/bifDe.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/bifDe.jpg" alt="enter image description here" /></a></li> <li>If I understand this correctly, the analog power supply (VDDA) for ADC/DAC does not provide any reference and thus will not work if VREF+ is left floating with a 1 uF tied to ground. Based on that, if VREF+ is not connected to any other external voltage source it should be tied to VDD/VDDA, but decoupled with 1 uF (+ 100nF potentially). Is my thought process correct?</li> <li>Lastly, I am wondering what is the best known practice for this type of power supply configuration to improve power supply to analog peripherals or is it only gonna get as good as my VDD/VDDA decoupling capacitors and their placement relative to its pin/s.</li> </ol> <p>NOTE: on this particular MCU part, VREF+ is not bonded with VDD/VDDA internally and has its own dedicated external pin.</p> <p>Please find some additional documentation that I was able to extract from few documents: <a href="https://i.stack.imgur.com/mQJGH.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/mQJGH.jpg" alt="enter image description here" /></a> <a href="https://i.stack.imgur.com/7NPMJ.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/7NPMJ.jpg" alt="enter image description here" /></a> <a href="https://i.stack.imgur.com/5lwD1.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/5lwD1.jpg" alt="enter image description here" /></a></p> <p>In this diagram it appears that VREF+ is not even connected to VDD/VDDA?</p>

Power Supply for STM32G071CxU microcontroller (VDD/VDDA vs VREF+ for analog peripherals)

2024-01-22T11:58:58.667

698477

|components|lcd|

<p>Yes, the rubber contains conductive paths between PCB and LCD glass.</p> <p>There is a series of narrow channels so that a larger pad on PCB and glass connect via multiple conductive paths in the rubber.</p> <p>The component is casually also called a zebra strip because usually the non-conductive parts are white and the conductive parts are black and the bands alternate.</p>

<p>Hoping to scavenge the LCD from an old bathroom scale for another project, I took it apart. There were four sensors -- one in each 'foot' of the scale -- all wired to a small circuit board whose back half is shown below, with the neat line of traces near the top. Sitting atop these was the small, rubbery rectangle that you see here, with its long thin edge touching the traces, and its other edge touching the LCD glass. <a href="https://i.stack.imgur.com/XGdQA.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/XGdQA.jpg" alt="enter image description here" /></a> If you look closely above the jaws of the crescent wrench, you can see some milky-grayish rectangles on the LCD; those are where the other long thin edge of the rubber piece was sitting, and I assume they are the 'connections' for the LCD.</p> <p>I'm therefore guessing that this rubber thing is somehow connecting the board-traces to the gray &quot;traces&quot; on the LCD. Can this be true? Is this a standard electronic part? I can't see any wires embedded in the rubber (but my eyes aren't great), and the alignment of the parts was maintained by what seemed like a somewhat sloppy and loose plastic assembly, which seems to belie the idea of tiny wires making the connection.</p> <p>Can anyone explain?</p> <p>(I've abandoned the idea of using this LCD, obviously, but I wish I could find something comparable, one with <strong>pins</strong> I can attach to...even AliExpress hasn't helped; It's the large size of the display that I need!)</p>

Puzzling 'conductor' in a bathroom scale

2024-01-22T12:04:20.693

698479

|circuit-analysis|kirchhoffs-laws|

<p>We have two transistors connected in series between the positive terminal of a supply voltage and the GND. The upper one <strong>Q2</strong> is &quot;working&quot; as a diode.</p> <p>Thus, for <strong>Q2</strong> we have <strong>Vce2 = Vbe2 = 0.7V</strong></p> <p>Because the <strong>Q2</strong> base terminal is directly connected to the collector.</p> <p>And from KVL we have this:</p> <p><span class="math-container">$$ V_{DD} = V_{BE2} + V_{CE1} $$</span></p> <p>So we can easily find the <strong>Vce1</strong> value</p> <p><span class="math-container">$$V_{CE1} = V_{DD} - V_{BE2} = 1.5V - 0.7V = 0.8V$$</span></p> <p>And we done.</p> <p><img src="https://i.stack.imgur.com/080qh.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2f080qh.png">simulate this circuit</a> &ndash; Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a>}</p>

<p>I have a question regarding applying KVL in a circuit with a npn-transistor. Unfortunately this is badly documented in the textbook, and I couldn't find the answer so far.</p> <p>For the circuit below, it was given that V_BE = 0.7, and from this V_CE = 0.8V is derived. This was derived from V_DD = V_CE + V_BE. This is where my confusion stems from, wouldn't using KVL give the equation V_DD = V_CE? I don't see how to use KVL correctly in this circuit.</p> <p><a href="https://i.stack.imgur.com/Gwexk.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/Gwexk.png" alt="enter image description here" /></a></p>

KVL on circuit with transistor

2024-01-22T12:21:08.740

698484

|s-parameters|matching|reflection-coefficient|

<blockquote> <p>As far as I know, matching mean &quot;zero reflection&quot;.</p> </blockquote> <p>As you noted: It also means 100% power transfer from input to output.</p> <p>So either and both of b) and c) would be correct. If only one answer is allowed then there is a 50/50 chance of getting the mark for the question.</p>

<p>This question was asked in a competitive exam in India. Two-port S matrix is assumed here.</p> <p>For matched junction S parameters, which of the following is correct ?</p> <p>(a) S₁₁ not equal to 0</p> <p>(b) S₁₁ equal to 0</p> <p>(c) S₂₁ equal to 1</p> <p>(d) |S₂₁| equal to 0</p> <p>As far as I know, matching mean &quot;zero reflection&quot;.</p> <p>I am confused between options (b) and (c). S₂₁ equal to 1 means forward transmission is 100% thereby implying that reflection at port 1 is zero (S₁₁=0)</p> <p>However, option (b) gives S₁₁ = 0 directly and so looks more appropriate. The paper setter has given option (c) as correct. I am thinking about challenging it. References to any standard textbook will be highly appreciated. Thanks a lot !</p>

Matched junction S parameters

2024-01-22T12:41:32.353

698488

|mosfet|bjt|speed|

<p>I would answer (c) because I would think that's what they're looking for but it's a stupid question.</p> <p>You can make <a href="https://www.nxp.com/docs/en/white-paper/SIGE_FACT_SHEET.pdf" rel="nofollow noreferrer">SiGe bipolar transistors</a> (on a chip) with ft's approaching 100GHz, and 4000 series CMOS (enhancement mode MOSFETS) that struggle to switch at 5MHz with low supply voltage. Eg. <a href="https://www.ti.com/lit/ds/symlink/cd4013b.pdf" rel="nofollow noreferrer">4013B</a></p>

<p>This question was asked in a competitive exam in India.</p> <p>Which of the following offers highest speed of operation?</p> <p>(a) BJT</p> <p>(b) FET</p> <p>(c) Enhancement Mode MOSFET</p> <p>(d) Depletion Mode MOSFET</p> <p>As far as I know, the speed of operation depends on application. In some applications, MOSFET is faster that BJT, whereas in some other applications BJT beats MOSFET. So this questions appears little incomplete to me. The paper setter has given (c) as the correct option.</p> <p>I wish to challenge this question. Please let me know your views regarding this question. References to any standard textbook will be highly appreciated. Thanks a lot!</p>

Highest speed of operation [BJT vs MOSFET]

2024-01-22T12:51:52.677

698498

|batteries|bms|contactor|electric-vehicle|

<blockquote> <p>which value should we use to calculate the rated current for the contactor?</p> </blockquote> <blockquote> <p>Does this imply that our contactor should have a rated current of 200 A?</p> </blockquote> <p>You need to ensure that your contactor will survive whatever current might cross it (including worst case scenario).</p> <p>If you have a fuse or another overcurrent between the batteries and the contactor, then you need to choose a contactor that supports whatever current can pass through your overcurrent protection, including :</p> <ul> <li>high currents for short duration (a thermal fuse for example won't blow on a short high current pulse)</li> <li>somewhat lower currents for somewhat longer durations (most fuses allow several time the nominal current for a few seconds)</li> <li>a bit more than the blowing current of the fuse for unlimited duration (nb : most fuses don't blow at there nominal current, but need some higher current before really flowing)</li> </ul> <blockquote> <p>I've noticed a few Tesla models using the Gigavac 200, which is rated for 500+ Amps at 12-800 Vdc. Why is it specified as 500+ and not an exact number?</p> </blockquote> <p>If you look at the datasheet of the <a href="https://www.sensata.com/sites/default/files/a/sensata-gigavac-gv200-series-open-contactors-datasheet.pdf" rel="nofollow noreferrer">Gigavac 200</a>, you have this very interesting figure : <a href="https://i.stack.imgur.com/B8s82.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/B8s82.png" alt="enter image description here" /></a> You can sustain 500A for about 600 seconds (ie 10 minutes).</p> <p>The current you can sustain for infinite time seems more like 300A.</p> <p>On the other hand, an inrush current of 2000A is OK for 20 seconds.</p> <p>So there is no hard limit for the maximum peak current (or at least I didn't found it by quickly reading through the datasheet). The maximum current depends mainly on how long you want to sustain it (and how well you can cool down the contactor).</p> <p>So the 500+ A is just a marketing value for a typical use case (for a car, if you can be full power for 10 minutes, it's more than sufficient, usually you only accelerate strongly for a few tens of seconds).</p> <p>So to answer your main question about choosing your contactor : what matters is not the current rating of your battery itself, but of the current protection that is (hopefully) either included in the battery or put at its output. Your switch must be rated to support all (current, duration) pairs your current limiting circuit can let through.</p> <p>So find the curve current-vs-duration of your battery protection, and compare it with the one of your contactor. Take the worst case scenario for both (ie highest (current,time) for the protection, and lowest resistance for the contactor. If the curve for the contactor is above the one for the protection with decent margin, you are fine. If not, choose another contactor.</p> <p>NB : a single figure for maximum current will not suffice to know if you are fine or not</p>

<p>I’m designing a battery pack and am uncertain about which contactor to select. Many electric vehicles (EVs) use three contactors: one each in the positive terminal, negative terminal, and precharge circuits. I believe we can use one type of contactor for all three positions.</p> <p><a href="https://i.stack.imgur.com/s40Ot.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/s40Ot.png" alt="simple diagram" /></a></p> <p>The current rating of the contactor should match the rated current of the pack. Let's assume we have 3 modules, each with a 6s20p configuration and our pack voltage is 400V. The &quot;Max. Discharge Current&quot; for each cell is 10,000 mA for continuous discharge and 15,000 mA for non-continuous discharge. My question is: which value should we use to calculate the rated current for the contactor?</p> <p>If we use &quot;Max. Discharge Current for continuous discharge&quot; of 10,000 mA for our calculation, then we would have 10 A * 20 = 200 A. Does this imply that our contactor should have a rated current of 200 A?</p> <p>I've noticed a few Tesla models using the Gigavac 200, which is rated for 500+ Amps at 12-800 Vdc. Why is it specified as 500+ and not an exact number?</p>

Choosing Contactors for an EV Battery Pack

2024-01-22T13:53:38.640

698515

|ltspice|transmission-line|schematic|

<p>Use the lossy transmission line element:</p> <p><a href="https://i.stack.imgur.com/fUwaH.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/fUwaH.png" alt="enter image description here" /></a></p> <p>You'll need more parameters then the ones you mention, such as resistance and capactance and length. Use saturn PCB tool for PCB calcs.</p> <pre><code>.model O1 LRTA(len=10 R=10m L=700n C=3p) </code></pre> <p>More info here: <a href="https://ltwiki.org/files/LTspiceHelp.chm/html/O-device.htm" rel="nofollow noreferrer">https://ltwiki.org/files/LTspiceHelp.chm/html/O-device.htm</a></p>

<p>For designing a high speed serdes system, I need to model a lossy channel of FR-4 substrate of length as 30 inch and 20dB attenuation. How can I implement it in LtSpice tool?</p>

How to simulate a 30 inch FR-4 lossy channel (20dB loss) using ltline symbol in LtSpice?

2024-01-22T16:21:45.483

698516

|circuit-analysis|stm32|gpio|digital-input|boot-configure|

<p>As I said at the comments, there are 3 resistors mounted on the PCB, but I was checking the third resistor at the wrong place. Resistor R316 is actually not mounted.</p> <p><strong>So pull up configuration doesn't exists on this board version</strong>. Although there is annotation carence on these schematics sheets, I think this scheme has CAD layout updating proposals.</p> <p>Let me explain it and let me name the Rpull Up connections: option A, and Rpull Down connections: option B.</p> <p>This way designer lets the chance for two mounting options (A/B) and he also lets the possibility of fixing BOOT1 to HIGH (option A) or fixing BOOT1 to LOW (option B), but not both at the same time. <strong>Only one of them will be finally mounted.</strong> If R316 is mounted, R317 should be removed and Rpull Down configuration is goten for BOOT1 pin. When R316 is mounted, the other one should be removed and Rpull Up will be goten for BOOT1 connection.</p>

<p>I was viewing a circuit in a schematics that is given to me. I found this voltage divider with a resistor connected to the BOOT1 pin from a microcontroller:</p> <p><a href="https://i.stack.imgur.com/FpZK7.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/FpZK7.png" alt="voltage divider with 3 resistors at BOOT1 input pin" /></a></p> <p>NOTE: BOOT1 is connected to the BOOT1 microcontroller pin. There are no more elements connected this net.</p> <p>In STM32Fxx families BOOT1 and BOOT0 are a 2-bit port used for boot system. But BOOT1 is only considered when BOOT0 is getting a certain value that means &quot;go and read the BOOT1 pin logic level&quot;. Depending on B1 value the system will start instruction reading from a memory zone or another one. BOOT1 is an input pin, this means this pin is high-impedance in order to read voltage. This needs no current driving through the pin.</p> <p>Looking at the circuit I can see:</p> <ul> <li><p>how the pin is floating, so R29 resistor won't get voltage falling, because there is no current through resistor.</p> </li> <li><p>how the voltage divider is fixing this pin to a half of VCC that is 3.3 V/2 = 1.65 V, because resistor R29 has no influence on the voltage divider.</p> </li> <li><p>Acording to this expression: <a href="https://i.stack.imgur.com/6O0LT.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/6O0LT.png" alt="stm32f10 VIH expression" /></a> allowed VIHmin = 1.833V</p> </li> <li><p>Acording to this another one: <a href="https://i.stack.imgur.com/3pFKA.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/3pFKA.png" alt="VIL expression" /></a> allowed VILmax = 1.16 V</p> </li> <li><p>It seems to be an indetermined value.</p> </li> </ul> <p>If I'm not wrong, I don't understand why to fix BOOT1 to a half of 3.3 V.</p> <p>Could anyone tell me what I'm missing?</p>

Voltage divider with serial resistor connected to BOOT1 pin from STM32F10X microcontroller

2024-01-22T16:32:42.367

698518

|mosfet|component-selection|

<p>I've ended up ordering some <a href="https://www.infineon.com/dgdl/irf3708pbf.pdf" rel="nofollow noreferrer">IRF3708</a>s, largely because they're easier to solder than SI2302, being TO-220 packages. Another SI2302 would have done the trick, I'm not sure why I was so against using one!</p>

<p>I'm overwhelmed by all the MOSFETs available. I'm trying to duplicate the effect of an <a href="https://datasheet.lcsc.com/lcsc/1810202111_Guangdong-Hottech-SI2302_C181087.pdf" rel="nofollow noreferrer">SI2302</a>, so an N-channel MOSFET, and specifically one that can be operated by an ESP32 logic level input (I think therefore Vgs(th) &lt; 3.3 V) and can handle a reasonable current (the existing has Id of 2.1 A).</p> <p>A package of either TO-92 or TO-220 would make it easy to solder into place - there is no space for a SMT device to be added.</p> <p>I'd love to just hook into the existing component's gate but that's connected to a whole load of other things which I don't want to power from the GPIO.</p> <p>Can anyone point me in the direction of a component that would suit?</p>

How to select a MOSFET?

2024-01-22T16:37:09.453

698520

|latch|

<p>For normal operation, the conversion is as you describe. A NOR ff has positive-true logic action (a high level asserts the output) and a NAND ff has negative-true inputs. In terms of input action, one inverter at each input effects the conversion.</p> <p>And you are correct about the outputs. Swapping them restores which output will go high when an input (before the added input inverter) goes high.</p> <p>What changes is what happens when both inputs are true. With a NOR ff, both outputs are low; with a NAND ff, both outputs are high. If you want the NAND circuit to behave like the NOT circuit in this state, then do not swap the outputs, and add an inverter to each one. Now you have completed the DeMorgan transformation of the circuit.</p> <p><a href="https://en.wikipedia.org/wiki/De_Morgan%27s_laws#Engineering" rel="nofollow noreferrer">https://en.wikipedia.org/wiki/De_Morgan%27s_laws#Engineering</a></p> <p><a href="https://en.wikipedia.org/wiki/De_Morgan%27s_laws#Generalising_De_Morgan_duality" rel="nofollow noreferrer">https://en.wikipedia.org/wiki/De_Morgan%27s_laws#Generalising_De_Morgan_duality</a></p>

<p>What is the general rule of thumb to convert SR (NOR) latch into S'R' (NAND) latch? I only know the two inputs (S,R) need to be inverted. What about outputs (Q)?</p>

How to convert SR (NOR) latch into S'R' (NAND) latch

2024-01-22T17:16:59.717

698522

|current|resistors|current-divider|

<p>If both loads are designed to operate from 5 volts, they will each draw whatever current they require from your 5 volt supply. There is no need for you to try to control the individual currents.</p>

<p>Edit: The original version of this question is malformed. There is an edit further down below with an updated explanation of the issue I'm trying to solve.</p> <p>In a simple current divider, I know the ratio of the parallel resistors determines the current flowing through each parallel section of the circuit, however, I don't know which resistance fits best on a given circuit.</p> <p>Given a 5V/5A dc power supply, a ratio of 2/3 would mean that one circuit would get 2A and the other would get 3, but that would be true both with a 2Ω and 3Ω resistor and a 2kΩ and 3kΩ resistor.</p> <p><a href="https://i.stack.imgur.com/JUHjV.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/JUHjV.png" alt="circuit order of 1 ohm resistance" /></a></p> <p><a href="https://i.stack.imgur.com/AXWaH.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/AXWaH.png" alt="circuit order of 1000 ohm resistance" /></a></p> <p>How is the proper resistance determined?</p> <h2>Edit</h2> <p>I see my misunderstanding. I made this question because I am working on a project where I have two loads that I have to connect in parallel, and each of them require different currents to go through them. I do not know their resistance, and it can probably vary, given that they are a microcontroller and an LCD.</p> <p>The load of the screen requires a power supply of 5V and at most 2A. The load of the microcontroller requires a 5V power supply capable of reaching, but not limited to, 3A.</p> <p>The problem is that I need to power both of these loads from the same source, and since one of them requires a higher load than what the other can take, I am worried I am going to damage the smaller load (the screen). I thought of using a current divider for this, but now it doesn't seem like the best idea. After searching some more I think a current limiter will do a better job at protecting the screen, but I am still unsure on how to go about this. This seems like should be on a different question though, so I'll write a new one. Thanks to everyone!</p>

How to choose the proper value of resistors for current dividers

2024-01-22T17:22:35.943

698525

|led|switches|led-strip|touch|

<p>If the gnds of 3V and 12V are or can be connected together (not isolated), you can use a NPN transistor like 3904 with 47k in base. Otherwise you have to use an optocoupler.</p> <p><a href="https://i.stack.imgur.com/HKD44.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/HKD44.jpg" alt="enter image description here" /></a></p>

<p>I would like to trigger a 3 V line (a push dimmer circuit) with a touch button (which is powered by 12 V).</p> <p>Closing the 3 V will turn off (short press)/turn on (short press)/dim (long press) the LED strip.</p> <p>Here is my complete circuit:</p> <p><a href="https://i.stack.imgur.com/rCjlR.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/rCjlR.png" alt="enter image description here" /></a></p> <p>How can I connect the outgoing 12 V line from the touch button to close the 3 V line (the red question mark)?</p> <p>Can this be realized by a transistor, optocoupler, etc.?</p> <p>Hardware used:<br /> LED controller: GLEDOPTO GL-C-013P (zigbee (3 wire/2 wire 2in1)) <a href="https://www.aliexpress.com/item/1005004400974419.html" rel="nofollow noreferrer">LED Conttroller</a><br /> Touch button: <a href="https://de.aliexpress.com/item/1005003191400339.html" rel="nofollow noreferrer">Touch Button</a></p>

Trigger a 3 V line with 12 V

2024-01-22T17:27:34.623

698532

|operational-amplifier|voltage-divider|wheatstone-bridge|

<p>As in Spehro's answer you need to assume that the circuit diagram examples are actually simplified versions of a bridge amplifier, some details are not being shown, (for e.g.: feedback, bias, gain resistors, etc.).</p> <p>In both examples it is shown that the resistive sensor located at the bottom right increases, as shown by the (R+dR) , so typically the voltage at Point A will be greater than point B. In bridge jargon with this arrangement you could label point A as the +Signal connection and point B as the -Signal connection.</p> <p>So starting with the example diagram 2 you have the +Signal output to +input of the amplifier and the -Signal to the -input of the amplifier, (++, --). Therefore the amplifier output would be G(VA-VB).</p> <p>In example diagram 1 you have the bridge outputs connected in reverse, the +Signal connects to the -input and the -Signal to the +input, (+-, -+). So in this case the amplifier output is also reversed giving the negated output of -G(VA-VB).</p>

<p>I am not sure when the correct formula for Vout is Vout = G(VA - VB) or Vout = -G(VA - VB).</p> <p><a href="https://i.stack.imgur.com/wX3hJ.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/wX3hJ.png" alt="enter image description here" /></a></p> <p>Can you explain the difference between these two examples? The circuits and the formulas provided are from my textbook, yet I struggle to understand how the formula for Vout ​is derived in each case.</p>

Wheatstone bridge connected to op-amp: confusion about Vout formula

2024-01-22T18:20:02.840

698536

|circuit-analysis|diodes|

<p><a href="https://i.stack.imgur.com/iBQsR.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/iBQsR.png" alt="Redraw of OP's passive circuit consisting of resistors and diodes" /></a></p> <p>I also offer a redraw. :-) As we are in the -24V case, I placed GND on top. I hope that helps.</p> <blockquote> <p>Why is the bottom half (everything below the source, apparentely) shortcircuited?</p> </blockquote> <p>The &quot;components in the bottom half&quot; (R4, D2, R5, D3) are shown in the upper right on my image. As D2 is in reverse, this whole branch has a much higher resistance then R3. (diodes in reverse exhibit some Megaohm in resistance). Therefore, R4,D2,R5,D3 can be ignored as they are dominated (&quot;shorted&quot;) by the much lower resistor R3, which is in parallel.</p> <blockquote> <p>Why is D1 in reverse?</p> </blockquote> <p>All diodes in this situation are in reverse. All the &quot;cathode bar&quot; markings (the short line in the diode symbol orthogonal to the current path) are oriented towards the positive voltage rail (in this case Ground).</p> <blockquote> <blockquote> <p>Teachers solution: The entire bottom of the source is shorted, while the mesh on the right has D1 in reverse ⟹ only the left mesh remains ⟹ I=24 V /6kΩ=4mA and Vo=−6 kΩ⋅4 mA=24 V.</p> </blockquote> </blockquote> <blockquote> <p>The current <em>I</em>, goes through the 6 kΩ resistor. How exactly is that current used in computing Vo? That is, where does the equation Vo=−6 kΩ⋅4 mA come from?</p> </blockquote> <p>I too, cannot follow the reasoning behind that. R1 (or the current flowing through it) is not needed to calculate Vout. R1 could have any value (aside from 0 Ohm) without influencing Vout (see also simulation below) How I would calculate Vout:</p> <p>The voltage of V1 is divided across R3,D1 and R2. D1 (being in reverse) and R3 together have a much higher resistance then R2. So nearly all -24V appear across R3+D1, which is equal to Vout</p> <p>One word to the teacher's calculation: Seemingly, at first, the current through R1 is calculated based on the voltage across it. Afterwards, the voltage is again calculated from R1's current, which is not wrong but futile. There is no calculation needed at all: Vout equals V1.</p> <p>Here's a simulation, sweeping R1's value from 1 Ohm to 10k: <a href="https://i.stack.imgur.com/j35jA.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/j35jA.png" alt="enter image description here" /></a></p>

<blockquote> <p>Given the circuit diagram below, indicate the on/off state of each diode and calculate the output voltage <span class="math-container">\$V_o\$</span> in each of the two half-cycles of source <span class="math-container">\$V_1\$</span>, which applies a square wave with an amplitude of <span class="math-container">\$24\ \mathrm{V}\$</span>. The threshold voltage of each diode is <span class="math-container">\$0.6\ \mathrm{V}\$</span>. Resistor units are in <span class="math-container">\$\Omega\$</span>.</p> </blockquote> <p><a href="https://i.stack.imgur.com/OmPVT.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/OmPVT.png" alt="enter image description here" /></a></p> <hr /> <p>I wish to understand the teacher's solution for the negative period of the voltage source; it consists of a couple of lines:</p> <blockquote> <p>The entire bottom of the source is shorted, while the mesh on the right has <span class="math-container">\$D_1\$</span> in reverse <span class="math-container">\$\implies\$</span> only the left mesh remains <span class="math-container">\$\implies\$</span> <span class="math-container">\$I= 24\ \mathrm{V} / 6\ \mathrm{kΩ} = 4\ \mathrm{mA}\$</span> and <span class="math-container">\$V_o = - 6\ \mathrm{kΩ} · 4\ \mathrm{mA} = 24\ \mathrm{V}\$</span>.</p> </blockquote> <ul> <li><p>Why is the bottom half (everything below the source, apparantely) shortcircuited?</p> </li> <li><p>Why is <span class="math-container">\$D_1\$</span> in reverse?</p> </li> <li><p>The current <span class="math-container">\$I\$</span> computed is that which goes through the <span class="math-container">\$6\ \mathrm{k\Omega}\$</span> resistor. How exactly is that current used in computing <span class="math-container">\$V_o\$</span>? That is, where does the equation <span class="math-container">\$V_o = -6\ \mathrm{k\Omega}\cdot 4\ \mathrm{mA}\$</span> come from?</p> </li> </ul> <hr /> <p><strong>My attempt</strong> (not needed to answer the post): I label the currents as follows:</p> <p><a href="https://i.stack.imgur.com/HHMhC.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/HHMhC.png" alt="enter image description here" /></a></p> <p>Applying Kirchoff's voltage law to each quadrant gives us four equations:</p> <p><span class="math-container">$$\varepsilon_0: V_1 = -I_0\cdot 6k\Omega$$</span> <span class="math-container">$$\varepsilon_1: V_1-0.6V = -2I_1\cdot k\Omega - I_2k\Omega$$</span> <span class="math-container">$$\varepsilon_2: 0.6V = I_1\cdot k\Omega -3I_2\cdot k\Omega +I_3\cdot k\Omega$$</span> <span class="math-container">$$\varepsilon_3: 0.6V = I_2\cdot k\Omega - I_3\cdot k\Omega$$</span></p> <p>Equation <span class="math-container">\$\varepsilon_0\$</span> always applies as is, while the other equations are subject to the fact that if diode <span class="math-container">\$D_k\$</span> is off, current <span class="math-container">\$I_k=0\$</span>.</p> <p>The problem is divided into two depending on whether <span class="math-container">\$V_1\$</span> is positive or negative. Assume the latter for now. My strategy was then to subdivide the problem as follows: for each of the eight possible configuration of the diodes (e.g. <span class="math-container">\$D_1\$</span> on, <span class="math-container">\$D_2\$</span> off, <span class="math-container">\$D_3\$</span> on) I solve the equations <span class="math-container">\$\varepsilon_1\$</span>, <span class="math-container">\$\varepsilon_2\$</span>, and <span class="math-container">\$\varepsilon_3\$</span>. For example, our equations now are:</p> <p><span class="math-container">$$\varepsilon_1: -24.6V = -2I_1\cdot k\Omega$$</span> <span class="math-container">$$\varepsilon_2: 0.6V = I_1\cdot k\Omega +I_3\cdot k\Omega$$</span> <span class="math-container">$$\varepsilon_3: 0.6V = - I_3\cdot k\Omega$$</span></p> <p>giving <span class="math-container">\$I_1=12.3\ \mathrm{mA}\$</span> and <span class="math-container">\$I_3 = -0.2\ \mathrm{mA}\$</span>. As the latter current <em>should</em> be positive, we have reached a contradiction, and I discard the current configuration.</p> <p>As another example, assume all diodes are on. Our equations are <span class="math-container">$$\varepsilon_1: -24.6V = -2I_1\cdot k\Omega - I_2k\Omega$$</span> <span class="math-container">$$\varepsilon_2: 0.6V = I_1\cdot k\Omega -3I_2\cdot k\Omega +I_3\cdot k\Omega$$</span> <span class="math-container">$$\varepsilon_3: 0.6V = I_2\cdot k\Omega - I_3\cdot k\Omega$$</span></p> <p>which may be written in matrix form as</p> <p><span class="math-container">$$ \begin{pmatrix} -2 &amp; -1 &amp; 0\\ 1 &amp; -3 &amp; 1\\ 0 &amp; 1 &amp; -1 \end{pmatrix} \begin{pmatrix} I_1\\ I_2\\ I_3 \end{pmatrix} = \begin{pmatrix} -24.6\\ 0.6\\ 0.6 \end{pmatrix} \implies \begin{pmatrix} I_1\\ I_2\\ I_3 \end{pmatrix} = \frac{1}{5} \begin{pmatrix} -2 &amp; 1 &amp; 1\\ -1 &amp; -2 &amp; -2\\ -1 &amp; -2 &amp; -7 \end{pmatrix} \begin{pmatrix} -24.6\\ 0.6\\ 0.6 \end{pmatrix} = \frac{1}{5} \begin{pmatrix} 50.4\\ 22.2\\ 19.2 \end{pmatrix} $$</span></p> <p>As no contradiction is found, I posit the configuration to be one of the many 'possible' ones and continue to compute <span class="math-container">\$V_o\$</span>:</p> <p><span class="math-container">$$V_o = -24\ \mathrm{V} - I_2\cdot\ \mathrm{k\Omega} = -24\ \mathrm{V} - 4.44\ \mathrm{mA}\cdot\ \mathrm{k\Omega} = -28.44\ \mathrm{V}.$$</span></p> <p>I continue this procedure for the remaining configurations.</p>

Understanding a short solution to a diode exercise

2024-01-22T18:44:50.240

698547

|analog|capacitive-coupling|

<p>Here's a circuit with voltage gain of 100, implemented as two stages of gain 10:</p> <p><img src="https://i.stack.imgur.com/R1WXP.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fR1WXP.png">simulate this circuit</a> &ndash; Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a>}</p> <p>I've artificially introduced minor input offsets using V2 and V3. Even the slightest offset at the input is also multiplied by 100, which is why, with an explicit input of 0V, the output of this amplifier is 1V.</p> <p>I assume you understood this already; that a sequence of cascaded DC coupled single-ended amplifiers will compound any input offset, until at some point one of the amplifier outputs is so far from its intended quiescent level that it is bound to clip against one or the other of its own supply potentials, as the real input signal fluctuates.</p> <p>I assume that you also understand that coupling capacitors solve this issue by developing a &quot;permanent&quot; DC potential that bridges the potential difference between the quiescent output level on one side, and the quiescent input level on the other.</p> <p>Perhaps it's not obvious that those tiny offsets can drift with time and temperature, and even if you did manage to compensate for them by some means, (perhaps you subtract 10mV at the input), that might work at 25°C, but the required offset will be very different at 40°C, or 2 years later.</p> <p>Again, capacitors adjust automatically to compensate for the difference between mean DC voltages on either side. For many applications, such as audio (where frequency components below 20Hz or above 20kHz are not of interest) AC coupling with capacitors is such a simple fix that there's no real advantage to direct, DC coupled stages.</p> <p>Sometimes, though, you <em>do</em> want DC coupled stages, because 0Hz (DC potential) is just as important to you as any fluctuations about that level.</p> <p>In the discrete transistor amplifier you showed us, where capacitors lie between each stage, those capacitors charge over time to some average, DC voltage to bridge the average potential difference between the two sides. Consequently, average DC current through the coupling capacitor eventually drops to zero. If you wish to directly couple those stages, you somehow need to obtain this same condition, zero average current flowing from stage to stage. Take this single stage for instance:</p> <p><img src="https://i.stack.imgur.com/vrDmw.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fvrDmw.png">simulate this circuit</a>}</p> <p>It has been carefully biased to produce exactly +6.000V at the collector, but injecting even only 1μA of DC current at the input will permanently offset the output by 80mV.</p> <p>Let's say we somehow manage to bias two stages so that the first produces exactly the correct quiescent potential at its output to perfectly match the quiescent potential established at the input of the second stage. In the above circuit, quiescent input potential is +1.250V. You can't just cascade two such stages directly, since connecting the 6V quiescent output of the first stage to the 1.250V quiescent input of the second would result in significant DC current being injected into stage 2's input, which would &quot;mess up&quot; its biasing. You have to produce a stage 1 whose quiescent output is equal to stage 2's quiescent input:</p> <p><img src="https://i.stack.imgur.com/kZNQZ.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fkZNQZ.png">simulate this circuit</a>}</p> <p>The important thing to note here is that these are direct coupled stages, and there is no direct current flowing in the path between stage 1 output and stage 2 input.</p> <p>Watch what happens if I change the <span class="math-container">\$\beta\$</span> (current gain) of Q1 from 140 to 100, representing just one of many variations that occur between transistors of the same type, and even the same batch:</p> <p><img src="https://i.stack.imgur.com/9GbXh.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2f9GbXh.png">simulate this circuit</a>}</p> <p>The quiescent output potential of stage 1 is necessarily different, and suddenly we have a tiny 62nA direct current flowing into stage 2's input. The consequence is a permanent 5mV offset at the output. It doesn't sound like much, but stages further along the chain will have to deal with this somehow.</p> <p>That's just one change. We have temperature changing <span class="math-container">\$V_{BE}\$</span> and all resistance values, aging of components, dependence of quiescent levels on power supply voltage, and goodness knows how many other uncertainties. Biasing a circuit like this to maintain the same quiescent output level, under those changing conditions, is very challenging.</p> <p>There are a few techniques available to mitigate these offsets in single ended amplifiers, such as negative feedback, and chopper-stabilised op-amps.</p> <p>Another solution you alluded to is to employ differential amplifiers:</p> <p><img src="https://i.stack.imgur.com/yJ2eP.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fyJ2eP.png">simulate this circuit</a>}</p> <p>The two stages here are typical implementations, the first producing a differential output, the second producing a single-ended output (with respect to ground). You could cascade as many of the first type as you desire.</p> <p>V2 introduces an undesired +100mV offset to <em>both</em> input potentials, but the nature of a differential amplifier is to remove that offset, by performing the subtraction <span class="math-container">\$V_{IN1} - V_{IN2}\$</span>.</p> <p>You still have op-amp imperfections to worry about, which will cause OA1 and OA2 to introduce introduce slight offsets of their own, but if those two devices are well matched, and have the same temperature and age similarly, those offsets will be similar, and the following differential stage can all but cancel them. This assumption is little a naive, there will be other things to cause an offset at OUT, but the worries are far fewer than for direct coupled single-ended amplifiers.</p>

<p>As in the title, my question is basically about understanding what is the &quot;problem&quot; with directly-coupled (below, I will use dc for &quot;directly-coupled&quot; and DC for &quot;direct current&quot;) amplifiers which necessitates the use of coupling amplifiers? Note that this question is being asked in the context of old-school discrete-circuit amplifiers, but I think that understanding that case will be helpful for me (and hopefully others) in deeply understanding the problem which differential pairs solve.</p> <p>Consider for example the figure below (from Gray, Hurst, Lewis, and Meyer, 5th edition):</p> <p><a href="https://i.stack.imgur.com/aL5XM.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/aL5XM.png" alt="enter image description here" /></a></p> <p>We see that the &quot;classical&quot; biasing arrangement for each stage (using the degeneration resistors at the emitters and voltage division at the bases) is used, and that the signal input flows through a few coupling capacitors. I should emphasize that this circuit is by no means optimal even under the discrete-circuit paradigm of the day. The point being made by the authors is around the discrete-circuit implementation using large resistors and caps whereas an integrated circuit implementation cannot (cannot use coupling caps, and so must face the direct-coupling problem head on rather than averting it by using coupling caps). I am in particular wondering about the need for the <em>coupling</em> caps in this question:</p> <p>My question is why these coupling capacitors are <em>necessary</em>, and I give the two suspicions I have below. If someone is able to explain if one or the other (or something else entirely) is correct, I would greatly appreciate it. Again, I am trying to understand <em>why we can't get away</em> without coupling capacitors (or differential pairs).</p> <p>(1) Not using coupling capacitors makes doing DC biasing hard, since then the biasing of a given stage is &quot;connected&quot; to an earlier stage. I am suspicious that this is the reason for the capacitors since it seems to me that, if we worked hard enough, we could overcome this by simply considering the path to the preceding transistor as being in parallel with the lower resistor in the voltage division circuit at each base and adjusting our biasing resistor values accordingly.</p> <p>(2) If there is some DC component to <span class="math-container">\$v_i\$</span> (or some DC noise injected at any subsequent stage's input, or referenced thereto) then without the coupling capacitors we would get a dc signal which messes with the circuit. This is very hazy in my head and I can't quite figure out what &quot;messes with&quot; ought to mean. I guess I can argue by superposition and say that this &quot;propagating DC signal/offset&quot; would ride on top of whatever the intended bias voltages are, thereby changing the bias point (and also therefore the relevant small-signal quantities) and therefore the amplification at the intended frequencies?</p> <p>In the end, I believe this question is related to my earlier one <a href="https://electronics.stackexchange.com/questions/690853/what-is-the-direct-coupling-problem-which-differential-amplifiers-help-avert">here</a> which has a very nice answer from Andy, but I am still struggling to understand if the issue is about a biasing issue or a dc small signal, as per (1) and (2) above, respectively. As I write above, I suspect (2) is the issue, but I am not sure because Andy's very nice answer seems in retrospect to me to be concerned with the biasing at each stage, but perhaps I am misunderstanding.</p>

What is the "problem" with directly coupled amplifiers?

2024-01-22T19:31:12.730

698554

|voltage|voltage-divider|

<p>You can certainly have more than one resistor in a divider, in old vacuum tube circuits it was common to derive a number of different voltages needed by the circuitry by just putting a big multi-resistor divider across the the high voltage supply to tap off the lower voltages needed.</p> <p>A good way to look at voltage dividers is to think of them as taking a part of a whole.</p> <p>In your circuit you have a 2k, a 1k, and another 2k for a total of 5k. There is 4 V across the whole thing. Now say you want the voltage from ground to V1, so you're taking 2 parts out of 5 (you can forget the k as long as they're all specified in k) so you just think 'two-fifths of 4 V', a fifth of 4 is 0.8, multiply by 2 and you've got 1.6 V. If you want ground to V2 that's three-fifths of 4 V, or 2.4 V. You could find the voltage across just the 1k, one-fifth of 4 V is 0.8 V. With a bit of practice a lot of times you can do the math in your head, otherwise a simple calculator will suffice.</p> <p>You can work this backwards to design a divider, say you have a 12 V source and you want 5 V, so you think 'I want 5 parts of 12', then you can just make the total resistance some multiple of 12, say 12<span class="math-container">\$\times\$</span>100 for 1200<span class="math-container">\$\Omega\$</span>, and you know the bottom resistor must be 5 parts of that so 5<span class="math-container">\$\times\$</span>100 = 500<span class="math-container">\$\Omega\$</span>, then just subtract that from the total to get 700<span class="math-container">\$\Omega\$</span> for the top resistor.</p>

<p>As a step in an exercise, I'm trying to find voltages <span class="math-container">\$V_1\$</span> and <span class="math-container">\$V_2\$</span> below</p> <p><a href="https://i.stack.imgur.com/9Z7BS.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/9Z7BS.png" alt="enter image description here" /></a></p> <p>Could a voltage divider (with more than two resistors) be used here? So that, for example:</p> <p><span class="math-container">$$V_2 = \frac{2\ \mathrm{k\Omega}}{2\ \mathrm{k\Omega}+1\ \mathrm{k\Omega}+2\ \mathrm{k\Omega}}\cdot 4\ \mathrm{V} = 1.6\ \mathrm{V}$$</span></p>

Could a voltage divider with more than two resistors be used?

2024-01-22T20:07:53.140

698555

|mosfet|mosfet-driver|half-bridge|

<p>Turns out my scope probes were placed incorrectly. I was measuring from HO to Gnd and should have been measuring from HO to VS.</p>

<p>Using an <a href="https://www.infineon.com/dgdl/Infineon-IRS2153D-DataSheet-v01_00-EN.pdf?fileId=5546d46269e1c019016a4ea5480f0d88" rel="nofollow noreferrer">IRS2513</a> half bridge driver tuned at 30 kHz with <a href="https://pdf1.alldatasheet.com/datasheet-pdf/view/60635/FUJI/1MBH60-100.html" rel="nofollow noreferrer">1MBH60-100</a> 1000 V, 60 A IGBTs, the driver is giving the high-side gate the full 24 V input voltage.</p> <p>I have included a picture of how I configured the driver and how the oscilloscope looked when measuring (measured from HO to GND and LO to GND).</p> <p>Why is this happening? The driver has an internal 15.4 V zener clamp.</p> <p><a href="https://i.stack.imgur.com/GjpfH.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/GjpfH.png" alt="IRS2513" /></a></p> <p><a href="https://i.stack.imgur.com/aMQ3B.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/aMQ3B.png" alt="scope" /></a></p>

Half-bridge driver giving high-side gate full input voltage

2024-01-22T20:18:03.307

698564

|voltage|amplifier|audio|speakers|

<p>There are other, better topologies for an audio amp, but what you have can be improved without starting over.</p> <ol> <li><p>As mentioned by JS, R10 and R11 are too large. Starting with your 4 V peak output voltage and the subsequent peak output current, take the transistor gain at that current (from the datasheet), divide that in half for operating margin, and use that to calculate the required base current. 100% of the base current comes from R10 and R11.</p> </li> <li><p>You have two opamps plus a 1-transistor gain stage all for a total gain of 6. You can keep C1, eliminate U1 and Q1 (and its parts), and configure U3 for a gain of 6.</p> </li> <li><p>There is no DC reference at the input to U1. Now that U1 is gone, add a 100K resistor from the U3 non-inverting input to GND.</p> </li> <li><p>Delete R9, C2, and C4. I don't know why they are there, but they make things worse, The output stage needs a low driving point impedance, such as the direct output of an opamp.</p> </li> </ol> <p>The way the circuit actually works, U3 does not provide any base current to the output transistors. It shunts current from R10 and R11 away from the output transistors. For example, in a positive half-cycle, R10 pulls up the Q2 base and sources its base current. for any particular instantaneous voltage, R10 pulls up the base until D1 starts to conduct, which is when the base is 0.7 V greater than the U3 output voltage. To pull the base down, the U3 output goes down, pulling down D1, which pulls down R10 and the Q2 base.</p> <p>Note that a 741 might not be able to provide enough output current to drive the output stage to the level you want. Still, you should be able to get things closer your desired output.</p>

<p>I am making an audio amplifier circuit in LTspice. This is the circuit that I've made:</p> <p><a href="https://i.stack.imgur.com/ekaif.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/ekaif.png" alt="enter image description here" /></a></p> <p>Notice that the input is 20 mV. The output plot is as follows:</p> <p><a href="https://i.stack.imgur.com/8vpXW.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/8vpXW.png" alt="enter image description here" /></a></p> <p>That is around the gain I want to obtain. The speaker that I will be using is an 8 Ω, 0.5 W speaker that can sustain a maximum 10 V peak-to-peak input.</p> <p>The problem is that as soon as I model this in LTspice, the voltage just drops too much and the shape distorts.</p> <p><a href="https://i.stack.imgur.com/YT6yU.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/YT6yU.png" alt="enter image description here" /></a></p> <p>Why is this happening and how do I fix it? Does it have anything to do with impedances?</p>

Why is the output voltage across the load dropping a lot in this audio amplifier circuit?

2024-01-22T21:12:23.513

698572

|analog|comparator|

<p>Use lower value resistors (order of 10s of kΩs). With the values you selected, everything is acting like an antenna, especially if this is on a breadboard. Also, your &quot;<em>very high voltmeter impedance</em>&quot; isn't very high compared to the resistances of your circuit.</p>

<p>I am testing the following comparator schematic:</p> <p><img src="https://i.stack.imgur.com/gGYOQ.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fgGYOQ.png">simulate this circuit</a> &ndash; Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a>}</p> <p>I've replaced the original 280 kΩ resistor with R1 and trimpot R3. The hysteresis resistors are calculated to switch on at 30.78 V battery (2.54 V on + input) and switch off at 29.78 V (2.46 V on + input). Battery voltage at testing time was 28.89 V.</p> <p>So, I am pressing the button SW1 and turning the pot until comparator triggers ON. First I noticed some flicker on the output before switching to a solid ON. This is already strange, since hysteresis should have taken care of it. When I release the button the comparator stays ON for a random period of 5 to 15 seconds, then switches OFF.</p> <p>I thought the calculations were wrong, so I connected a voltmeter to TP1. The comparator switched ON at 2.63 V, not at the expected 2.54 V. With the button released the voltage dropped to 2.35 V and the comparator switched OFF immediately.</p> <p>I re-tested everything several times and the result is the same: with the voltmeter connected the circuit switches ON and OFF immediately when the button is pressed and released. There is no jitter when I rotate the potentiometer either. Without the voltmeter there is a jitter and then it stays ON for some time. Furthermore, connecting the voltmeter <em>sometimes</em> activates the output, sometimes not. Considering the very high voltmeter impedance this is very strange.</p> <p>Any ideas why this is happening and what I can do to fix it?</p> <p>UPDATE:</p> <p>The original circuit had two problems that combined to produce the observed strange behavior.</p> <p>First, I failed to account for 5V feedback voltage injected into the voltage divider via R4, R5. Accidentally, with selected R1-R3 it was enough to keep TP1 voltage at 2.457V, i.e. within millivolts of the OFF threshold. Connecting the voltmeter pushed this down enough to trip the comparator. This was fixed by changing R1 to 200k.</p> <p>Second, high resistor values made circuit susceptible to noise. This was fixed by adding 1nF capacitors to TP1 and 2.5V reference. I've used smaller values because they will remain in the circuit after the test button removed, so will affect the dynamic response.</p> <p>My thanks to @unawriter and @mosfet for helping me pinpoint these problems.</p> <p>UPDATE 2:</p> <p>After more testing it become apparent that while changing R1 did make the circuit working, the experimental resistance values and thresholds do not correspond to theoretical calculations. It seems the hysteresis formulas in comparator datasheet assume very low source impedance. In this case it is very high, so feedback chain significantly affects the thresholds. Maybe I have to make another question specifically for the calculations.</p>

Strange comparator behavior

2024-01-22T22:28:26.203

698576

|power-supply|circuit-protection|current-limiting|

<p>You simply need to have a power supply that can supply enough current for both devices operating at their max current consumption state. L1 requires at least 3A. L2 draws, at most, 2A. Take the sum of these loads: 3A + 2A = 5A. You will need a power supply that can provide 5A @ 5V. A good engineer will go with something higher than 5A in a professional setting where reliability matters.</p> <p>In other words, The loads are only going to draw as much current as the need - not how much current the power supply can force down there proverbial throats. The max and min current specs are device specs. Not power supply specs.</p>

<p>I have a project that has two separate sections that must be powered from the same power source. I do not know the resistance of said loads, but I know the power supply that each of them on their own would need. I apologize in advance for any ignorant mistakes you find in this question, I'm a software guy and I haven't done much beyond following Arduino schematics.</p> <p>The first one (L1) requires a 5 V power supply capable of reaching at least 3 A.</p> <p>The second one (L2) requires a 5 V power supply that is limited to 2 A.</p> <p>The pretty obvious conflict is that no power supply meets both requirements at once, so I need to use a power supply that can supply both loads at max. load and protect L2 so that it isn't accidentally overloaded.</p> <p>How can I do this? My first (rather uninformed) thought was to use a voltage divider, but after asking another question <a href="https://electronics.stackexchange.com/questions/698522/how-to-choose-the-proper-value-of-resistors-for-current-dividers">here</a> I noticed that that is probably not going to work.</p> <p>I've searched some more around and I haven't been able to find anything that could work. I've thought of using a current limiter, but all I have found is about limiting the current to the whole circuit, and I am unsure of how it would behave in a parallel circuit</p> <p>Here's a diagram of how the project more or less looks:</p> <p><a href="https://i.stack.imgur.com/zGFYO.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/zGFYO.png" alt="diagram" /></a></p> <p>I've used resistors to represent the loads, but I do not know the resistance of each load (they might as well vary since they are a microcontroller and a screen). I need to somehow ensure that I can provide at least 3 A to L1, while ensuring that L2 never receives over 2 A.</p> <p>How can I go about this?</p> <p>I have thought about powering the screen from the microcontroller itself (so technically in series?) but I'm not sure that the microcontroller can provide enough current or at a close enough voltage to 5 V through its IO pins to power the screen, so I don't know. I don't want to risk anything breaking because the components are expensive so I'd rather figure things out in theory before attempting anything with the lab power supply.</p> <p>In detail, L1 is a <a href="https://wiki.geekworm.com/X635" rel="nofollow noreferrer">Geekworm X635</a> board with a Raspberry Pi CM4 and an NVMe SSD, and L2 is just a generic LCD screen</p>

Protecting parallel loads

2024-01-22T23:21:29.493

698577

|amplifier|stm32|dac|i2s|

<p>Figured it out. My GPIO Slew rate was too high. It was introducing too much EMI. Lowering it fixed the problem.</p>

<p>I have both an SD card and a <a href="https://www.analog.com/media/en/technical-documentation/data-sheets/max98357a-max98357b.pdf" rel="nofollow noreferrer">MAX98357A</a> (I2S Amplifier) breakout board connected to my STM32 Nucleo. As soon as I open a file for reading in FatFs using the <code>f_open</code> command, the speaker attached to the MAX98357A starts making a horribly loud pitch static noise and visibly vibrates.</p> <p>I'm pretty confident that this is due to the 16 MHz clock line that I have running to the SDIO. If I remove any of the SDIO/FatFs functions, then I no longer get that noise, just some occasional clicks. This is all without even initializing any of the I2S peripherals. The breakout board is just connected to power and ground.</p> <p>Unfortunately, I'm still stuck with breadboarding this for now. Are they any strategies that I could use to remove that noise?</p> <p>Things I've tried:</p> <ul> <li>680 μF and 470 nF capacitor on power and ground rails</li> <li>Connecting the MAX98357A to a separate ground PIN</li> <li>Using a 5 V regulator for the MAX98357A</li> </ul> <p>Putting my hand on my laptop near the USB port seems to also alleviate the buzzing noise.</p> <p>Photo for reference:</p> <p><a href="https://i.stack.imgur.com/R8lhO.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/R8lhO.jpg" alt="enter image description here" /></a></p>

Horrible noise coming from speaker when using SDIO

2024-01-22T23:26:11.297

698581

|power-supply|power|capacitor|thermistor|inrush-current|

<p>No, or probably not.</p> <p>Plain resistors are a poor choice, as the current decreases exponentially over time; charging eventually to say 99% is very slow compared to a current limiter of nominal value. Compare:</p> <p><img src="https://i.stack.imgur.com/dhUFT.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fdhUFT.png">simulate this circuit</a> &ndash; Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a>}</p> <p><a href="https://i.stack.imgur.com/8oQkC.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/8oQkC.png" alt="enter image description here" /></a></p> <p>You'd want a higher hFE part for practical use, or a PMOS and more control circuitry, and probably an enable so it's not idling with so much bias current once it's charged.</p> <p><strong>NTC thermistors:</strong></p> <p>Mains rated parts are designed for specific ratings. For example, a 20mm 10Ω part might be suitable for 120/240V use up to 1mF or so. They're not rated for, or at least I'm not aware of any for, low voltage use. Mind, I haven't exactly shopped in detail for them.</p> <p>They will be usable at lower voltage, and proportionally higher capacitance, to give the same heating and thus charging curve, but I don't know that you'll have a combination for this particular combination of capacitor, inrush current, and charging time.</p> <p>The tricky thing is, matching the resistance value and heat capacity to the power supply and capacitor. There may not be a part commercially available with the right combination of values.</p> <p>And you may not want that solution anyway, because its operation depends on the temperature rising during a full-enough charge cycle to do the job. Otherwise it's just a slow resistor with little temp rise.</p> <p><strong>Best?</strong></p> <p>Of course, an SMPS. You can't use just any regulator here; what's required, is one with continuous current limiting (foldback may be acceptable, but hiccup/faulting isn't workable), and low dropout (ability to reach 100% duty). It can even be a synchronous buck-boost or &quot;flying inductor&quot; regulator that's bidirectional, supplying the 5V during discharge. You'll have to find a chip for that (or design the function yourself..!).</p>

<p>I'm designing a very simple circuit to enable a Raspberry Pi to power down safely in the event of a power outage.</p> <p>It is comprised of a supercapacitor, a diode to prevent reverse current flow, and a PNP transistor to bridge two pins and send a shutdown signal to the Pi in the event of power supply loss. There is a boost converter on the output so I can provide 5 V to the Pi for as long as possible.</p> <p>Currently, I have a 15 W, 2 Ω resistor in series with the diode to limit inrush current to the capacitor, but I understand that NTC thermistors are more commonly used for this purpose.</p> <p>However, the specs provided for most NTC thermistors seem to be geared towards AC power supply usage. Everything here is operating at 5 V. My questions:</p> <ol> <li><p>Is a resistor an appropriate choice for inrush current limiting in this case, given that the power is relatively low (max supply power is 15 W), or is there some reason I'm missing that resistors as inrush limiters are a terrible idea?</p> </li> <li><p>I'm finding the dissipation constant/heat calculation confusing for NTC thermistors. For example, if I want to limit the current to 2 A, it seems obvious to me that my minimum resistance value should be Vpeak/Imax, or 2.5 Ω. What I'm less certain of is how to figure out, based on dissipation constant, if my chosen NTC thermistor will heat up <em>too much</em> (overheat), or <em>not enough</em> (resistance remains too high during normal operation after inrush) at the power levels I'm working with.</p> </li> </ol> <p>Am I overthinking it, and should I just choose an NTC with a higher continuous current rating (say 5 A) than I need and an appropriate resistance at 25°C?</p>

Choosing an NTC thermistor for inrush current limiting at 5 V

2024-01-23T00:48:40.233

698597

|capacitor|cmos|energy|nmos|pmos|

<p>The formula for energy stored in a capacitor is:</p> <p><span class="math-container">$$ E = \frac{1}{2}CV^2 $$</span></p> <p>In either state, one of those capacitors is fully charged, with energy <span class="math-container">\$\frac{1}{2}C{V_{DD}}^2\$</span> joules, and the other fully discharged, with 0J of energy.</p> <p>The total stored energy energy in <em>both</em> cases is therefore:</p> <p><span class="math-container">$$ E_{TOTAL} = \frac{1}{2}C{V_{DD}}^2 $$</span></p> <p>In other words, the net change in stored energy when state changes from top capacitor charged and bottom discharged, to top discharged and bottom charged is <em>zero</em>.</p> <p>You might think that the power supply doesn't need to provide any energy at all, since net stored energy hasn't changed, but you'd be wrong. There's a cost to charging a capacitor, and a cost to discharging it, because the charging path has resistance.</p> <p>The supply has non-zero internal resistance, and the MOSFETs have non-zero on-resistance, and all current that results from the charging and discharging of those capacitors will have to pass via these resistances. Consequently those resistances will dissipate power, and that energy is lost as heat. That energy is what the supply is delivering to the system during each transition between states. I'm going to ignore the supply's internal resistance, and assume that the only resistance in play is the MOSFET's own <span class="math-container">\$R_{DS(ON)}\$</span>.</p> <p>Assuming we start with the upper capacitor (<span class="math-container">\$C_{VDD}\$</span>) discharged (0V across it), and the lower one (<span class="math-container">\$C_{GND}\$</span>) charged (the full <span class="math-container">\$V_{DD}\$</span> across it). When we switch on the lower MOSFET, to discharge <span class="math-container">\$C_{GND}\$</span> and charge <span class="math-container">\$C_{VDD}\$</span>, the system looks like this:</p> <p><img src="https://i.stack.imgur.com/v4IXs.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fv4IXs.png">simulate this circuit</a> &ndash; Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a>}</p> <p>I've renamed stuff to make the algebra easier to write. The voltage across C1 is <span class="math-container">\$V_{C1} = V_S - V_X\$</span>. The voltage across <span class="math-container">\$V_{C2} = V_X - 0V = V_X\$</span>. The voltage across R is <span class="math-container">\$V_R = V_X - 0V = V_X\$</span>. Supply voltage is fixed at <span class="math-container">\$V_S\$</span>.</p> <p>I'm not sure that the following is the easiest or quickest proof. There's probably a more intuitive approach that I haven't spotted.</p> <p>We wish to find the energy delivered to the rest of the circuit by source VS. Energy is the time-integral of power, where power <span class="math-container">\$P=IV\$</span>, the product of voltage across the recipient and current through it:</p> <p><span class="math-container">$$ \begin{aligned} E &amp;= \int^\infty_{t=0}{P \cdot dt} \\ \\ &amp;= \int^\infty_{t=0}{IV_S \cdot dt} \\ \\ &amp;= V_S\int^\infty_{t=0}{I \cdot dt} \\ \\ \end{aligned} $$</span></p> <p>By Ohm's law, current <span class="math-container">\$I_1\$</span> through R is:</p> <p><span class="math-container">$$ I_1 = \frac{V_X}{R} $$</span></p> <p>Capacitor C1 current is:</p> <p><span class="math-container">$$ \begin{aligned} I &amp;= C_1 \frac{d(V_S-V_X)}{dt} \\ \\ &amp;= C_1 \frac{V_S}{dt} - C_1 \frac{V_X}{dt} \\ \\ \end{aligned} $$</span></p> <p>Remembering that <span class="math-container">\$V_S\$</span> is constant, so <span class="math-container">\$\frac{dV_S}{dt}=0\$</span>, that simplifies to:</p> <p><span class="math-container">$$ I = - C_1 \frac{dV_X}{dt} $$</span></p> <p>Capacitor C2 current is:</p> <p><span class="math-container">$$ I_2 = C_2\frac{dV_X}{dt} $$</span></p> <p>With expressions for all three currents, we can combine them using KCL, which says:</p> <p><span class="math-container">$$ \begin{aligned} I &amp;= I_1 + I_2 \\ \\ - C_1 \frac{V_X}{dt} &amp;= \frac{V_X}{R} + C_2\frac{dV_X}{dt} \\ \\ - \frac{dV_X}{dt}(C_1 + C_2) &amp;= \frac{V_X}{R} \\ \\ \frac{dV_X}{dt} &amp;= -\frac{V_X}{R(C_1+C_2)} \end{aligned} $$</span></p> <p>Solving this differential equation for <span class="math-container">\$V_X\$</span> is fairly trivial, I won't show any working, just the solution:</p> <p><span class="math-container">$$ V_X(t) = V_X(0)e^{-\frac{t}{R(C_1+C_2)}} $$</span></p> <p><span class="math-container">\$V_X(0)\$</span> is the initial potential of node X, at time <span class="math-container">\$t=0\$</span>, which we know to be <span class="math-container">\$V_S\$</span>, so this becomes:</p> <p><span class="math-container">$$ V_X(t) = V_Se^{-\frac{t}{R(C_1+C_2)}} $$</span></p> <p>You might recognise that last equation as the classic capacitor discharge formula. Interestingly, it has time constant <span class="math-container">\$R(C_1+C_2)\$</span>, as if C1 and C2 were in parallel. What this tells us is that potential <span class="math-container">\$V_X\$</span> starts equal to <span class="math-container">\$V_S\$</span>, and decays exponentially to zero, with a time constant of <span class="math-container">\$R(C_1+C_2)\$</span> seconds.</p> <p>Plug our expressions for <span class="math-container">\$V_X\$</span> and its derivative back into our equation for <span class="math-container">\$I\$</span>:</p> <p><span class="math-container">$$ \begin{aligned} I &amp;= -C_1 \frac{dV_X}{dt} \\ \\ &amp;= (-C_1)(-\frac{V_X}{R(C_1+C_2)}) \\ \\ &amp;= \frac{C_1}{R(C_1+C_2)}V_X \\ \\ &amp;= \frac{C_1}{R(C_1+C_2)}V_Se^{-\frac{t}{R(C_1+C_2)}} \\ \\ \end{aligned} $$</span></p> <p>I'll substitute <span class="math-container">\$\tau=R(C_1+C_2)\$</span>, just to tidy things up:</p> <p><span class="math-container">$$ I = \frac{C_1}{\tau}V_Se^{-\frac{t}{\tau}} $$</span></p> <p>We're ready to calculate energy <span class="math-container">\$E\$</span>:</p> <p><span class="math-container">$$ \begin{aligned} E &amp;= V_S\int^\infty_{t=0}{I \cdot dt} \\ \\ &amp;= V_S\int^\infty_{t=0}{\frac{C_1}{\tau}V_Se^{-\frac{t}{\tau}} \cdot dt} \\ \\ &amp;= {V_S}^2\frac{C_1}{\tau}\int^\infty_{t=0}{e^{-\frac{t}{\tau}} \cdot dt} \\ \\ &amp;= {V_S}^2\frac{C_1}{\tau}\left[ -\tau e^{-\frac{t}{\tau}} \right]^\infty_{t=0} \\ \\ &amp;= {V_S}^2C_1\left[ -e^{-\frac{t}{\tau}} \right]^\infty_{t=0} \\ \\ &amp;= {V_S}^2C_1\left[\vphantom{\frac{}{}} (0) - (-1) \right] \\ \\ &amp;= {V_S}^2C_1 \end{aligned} $$</span></p> <p>That's the energy supplied by voltage source VS (<span class="math-container">\$V_{DD}\$</span>) to the entire system, during a transition from output high to output low, (or input low to high, since this is an inverter). You can repeat the procedure for a transition from low to high, and I'm sure you'll obtain a similar result, but with C2 (<span class="math-container">\$C_{GND}\$</span>) in the expression instead.</p>

<p>Can someone please explain why, when <span class="math-container">\$ln\$</span> is transitioning from low to high, the energy supplied is <span class="math-container">\$C_{vdd}\cdot V_{dd}^2\$</span>?</p> <p><a href="https://i.stack.imgur.com/DR7wU.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/DR7wU.png" alt="" /></a></p>

CMOS (Energy Supply of voltage)

2024-01-23T06:20:14.380

698616

|photodiode|phototransistor|

<p>The manufacturer is an LED assembler. They don't make LED chips, let alone photodiode chips, but rather buy them from a semiconductor fab (probably in the form of a wafer scribed and on a stretchy backing) and stick them into packages in job lots.</p> <p>The 5mm variant is shown on their website, with a similar sketchy datasheet.</p> <p>I have grave doubts as to how well they are tested or if they are properly characterized, but I don't doubt that they are selling some form of generic photodiode or phototransistor chip packaged into one of their standard LED moldings. The relatively high sensitivity and relatively low speed suggests a phototransistor. Compare the <a href="https://www.kingbrightusa.com/images/catalog/SPEC/WP7113P3BT.pdf" rel="nofollow noreferrer">Kingbright</a> phototransistor datasheet (and note that the speed of 15usec is with a 10x higher load resistance than the Huiyuan part, so essentially the same).</p> <p>As others have said, it's not really worth bothering with this kind of supplier in low quantities. If you have an application that uses something like this in large quantity they'll prepare a multi-page specification document that covers exactly how they will test and characterize the parts, and provide samples. But they're not going to bother with that for a small order.</p> <p>Here's a similar 3mm⌀ product from <a href="https://datasheet.lcsc.com/lcsc/2006021732_Chau-Light-ZPT034C_C575318.pdf" rel="nofollow noreferrer">Chau Light</a> that's less than 3 cents in quantity and has a better datasheet. There are other similar suppliers.</p>

<p>The <a href="https://www.reichelt.com/de/en/3mm-photo-diode-clear-10-10us-3004m1c-p363976.html" rel="nofollow noreferrer">datasheet</a> describes the 3004M1C as a &quot;high speed and high sensitive PIN photodiode&quot;. Distributors also label it as a photodiode. However, the datasheet mentions &quot;Collector-Emitter Breakdown Voltage&quot;, &quot;Emitter-Collector Breakdown Voltage&quot;, &quot;Collector-Emitter Saturation Voltage&quot;, which seems to make sense only for phototransistors. I also tried some checks suggested in &quot;<a href="https://electronics.stackexchange.com/questions/175894/is-it-a-photodiode-or-a-phototransistor">is it a photodiode or a phototransistor?</a>&quot;: The open circuit voltage of the 3004M1C is 0 when I point a bright light to it. Also, the diode tester doesn't read anything.</p> <p>So, is the 3004M1C a phototransistor mislabeled as a photodiode?</p>

Is 3004M1C a photodiode or a phototransistor?

2024-01-23T11:30:44.983

698627

|microcontroller|dc-motor|pid-controller|

<p>Discrete-time PID will do it. Sampling rate doesn't matter all that much, as long as there is no aliasing. In your case, the sensing point is always at the same mechanical angle, so it's probably fine. The upper end of the regulator bandwidth will be pretty low - a couple of Hz, say 2..4Hz.</p> <p>Most likely you won't need the D term unless there's a structural resonance, and even then you'd only want to enable that term within the RPM range of structural resonance.</p> <p>Do mind, though, that for stability you may end up interpolating between 2-3 sets of P,I,D coefficients, based on RPM.</p> <p>Say that there's a structural resonance at 750RPM. You'd do one tuning at 500RPM, call it PID₅₀₀, another at 1000RPM, PID₁₀₀₀ and then at 750RPM where the resonance is - PID₇₅₀. These parameter sets would be blended, using a set of blending functions, for example (Mathematica output):</p> <p><a href="https://i.stack.imgur.com/1rHkT.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/1rHkT.png" alt="enter image description here" /></a></p>

<p>I have a system driven by a geared DC motor spinning at between 500 and 1000 RPM. Once in operation, the load on the motor will not change and the speed should be held constant.</p> <p>I have a single digital Hall-effect sensor sampling the output of the system once per rotation. Most PID controllers I’ve seen have much higher sampling rates. Will a traditional PID or PI controller work here? Are there alternative control algorithms I could use?</p> <p>Additional context: The motor is driving a linearly reciprocating mechanism. The load will vary within a cycle, but the average load per cycle should be constant during operation (i.e. no external forces acting on the system aside from friction and air resistance). Speed variation should be less than 1%. I can’t place more than one sensor due to space restrictions and a limited number of available IO pins on my microcontroller.</p>

DC motor control algorithm with low sample rate

2024-01-23T12:59:13.527

698628

|power-supply|isolation|poe|

<blockquote> <p>I'm unsure if I need isolation for the PoE injectors or not.</p> </blockquote> <p>POE isolation is needed for two reasons:</p> <ol> <li>If you have a large potential between devices</li> <li>If you need to meet regulatory and compliance, more specifically, if your POE PD (Powered Device) needs to be 803.2af or at compliant (you need isolation to certify AFAIK)</li> </ol> <p>I don't think either applies to you.</p> <p>Since you have both devices in a metal box, and if you have chassis grounds connected to the box the potential would be the same. Unless you have some fault current on the box there should be no issue (if you think you could have a large fault current then that could create an issue in the event of a fault with large voltages being presented on the chassis.</p> <p>All that being said, If I were doing this design for myself I would choose isolation (and 802.3xx devices) for three reasons:</p> <ol> <li>Because if there is a fault or some other event with high voltages, the current will not travel down the ethernet cable and create issues.</li> <li>Because it isn't that much more cost to get isolation and an 802.3af or at PSE (Power Sourcing Equipment ) POE, these can be had for less than 20$. POE DC 'splitters' that simply run DC over Ethernet direct are much lower cost (maybe 2-5$) but the cost vs risk would be worth not using direct injectors and lowering any risk by using isolation</li> </ol> <blockquote> <p>The question is: can I use a 55 V supply voltage referenced to 0V_SIGNAL to power my PoE injectors, or do I need isolation? In this case, do I need isolation between each PoE port or not?</p> </blockquote> <p>Again you don't <em>need isolation</em> if the ground potential is the same and will always be the same. The hard thing is determining what the fault pathway will be if there is some issue with a short. Because of this the system will most likely be more robust if you isolate the POE.</p> <p>Again, if you are confident in your ground then POE would not be needed, but if you think there could be a current fault where any large current could follow the ground, it would be worth isolating.</p> <blockquote> <p>More precisely, which of the following solutions can I use:</p> </blockquote> <blockquote> <ul> <li>A dedicated isolated DC/DC converter generating the 0 V, 55 V for a single PoE injector</li> </ul> </blockquote> <p>If your PD (Powered Devices are 802.3af or at (or more) then you'll want a PSE (Powered Sourcing Equipment). That being said, many devices will work if you put 48-55V on the spare pairs. The direction isn't important because most devices have a rectifier that will work with either polarity. When I do Powered Device testing, I usually just hookup a bench supply for an 802.3af device and measure the power with the bench supply. 802.3xx devices also need to negotiate power and can detect bad power conditions. So if you had multiple POE devices, you will need 1 injector per cable or a hub with many POE ports. If I were doing this myself I'd probably use a POE switch some even have remote monitoring capabilities which could be useful for your application</p> <blockquote> <ul> <li>A shared DC/DC converter generating the 0 V, 55 V for all PoE injectors (but isolated from the rest of my electronics box)</li> </ul> </blockquote> <p>You could do this if you wish, and use isolated POE injectors or even passive injectors, <a href="https://rads.stackoverflow.com/amzn/click/com/B00NRHNPUA" rel="nofollow noreferrer" rel="nofollow noreferrer">passive injectors</a> just take the spare pairs and split them out so you can connect a bench supply or DC/DC converter to them.</p> <blockquote> <ul> <li>No isolation at all, all signal grounds are connected together</li> </ul> </blockquote> <p>Since you have a chassis and it's probably always going to be zero volts you don't have to have isolation, but isolation is nice to have. This scheme with using <a href="https://rads.stackoverflow.com/amzn/click/com/B00NRHNPUA" rel="nofollow noreferrer" rel="nofollow noreferrer">passive POE injectors</a> would work for your application</p> <p>EDIT:</p> <p>Solution #2 would be best since you are developing your own PCB:</p> <p><a href="https://i.stack.imgur.com/l5q7T.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/l5q7T.png" alt="enter image description here" /></a><br /> Figure 1.1 <a href="https://ww1.microchip.com/downloads/aemDocuments/documents/POE/ApplicationNotes/ApplicationNotes/AN3361-Designing-an-IEEE802.3af-at-bt-PoE-System-based-on-PD692x0-and-PD69208-Chipset.pdf" rel="nofollow noreferrer">Microchip AN3361</a></p>

<p>On the robot I'm currently designing, there will be several connectors with PoE ethernet and supply voltage (0 V, 24 V) and some other signals (referenced to 0 V).</p> <p>I'm unsure if I need isolation for the PoE injectors or not.</p> <p>More precisely, which of the following solutions can I use:</p> <ol> <li>A dedicated isolated DC/DC converter generating the 0 V, 55 V for a single PoE injector</li> <li>A shared DC/DC converter generating the 0 V, 55 V for all PoE injectors (but isolated from the rest of my electronics box)</li> <li>No isolation at all, all signal grounds are connected together</li> </ol> <p>Please not that I don't require to be officially PoE compliant (if it's easy, why not, but it's just a small nice to have), only that it works in practice.</p> <p>Some elements about the electrical architecture of the robot that might be relevant (or not?): <a href="https://i.stack.imgur.com/ihHxp.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/ihHxp.jpg" alt="electrical architecture" /></a></p> <p>The surface unit is powered from mains, and generates and isolated DC voltage of 350 V (and forwards protective earth). The isolation from the DC rail (OV_PWR and 350V_PWR) to protective earth is monitored continuously, and power is cut in case the isolation resistance is &lt;200 kΩ.</p> <p>Then there is a long cable (400 m max) containing 0 V, 350 V, earth and optical fiber for Ethernet communication. Nothing else.</p> <p>On the robot, 0V_PWR, 350V_PWR and protective earth and fiber enter the main electronics box (metal enclosure, currently not connected to PE, not decided yet if it will be connected on the new revision).</p> <p>OV_PWR, 350V_PWR and protective earth leave again the main box to power the motors (control interface is isolated). They also go to the isolated DC/DC converter(s). Those converters generate all the low voltage rails (0V_SIGNAL, 1.8 V, 3.3 V, 5 V, 12 V, 24 V, 55 V), with all the low voltage grounds connected together (but isolated from the 0V_PWR).</p> <p>Those lower power voltage rails will power the ethernet switch, the internal electronics, and the external connectors for low power devices (connectors shared with PoE ethernet).</p> <p>The question is: can I use a 55 V supply voltage referenced to 0V_SIGNAL to power my PoE injectors, or do I need isolation? In this case, do I need isolation between each PoE port or not?</p> <p>In case it's relevant, the cables outside the electronics box are usually &lt;1.5 m, and will never exceed 4 m.</p> <p>EDIT: All external connectors are subsea connectors (i.e. not RJ45), so there is no risk of the user trying to connect to a computer or a switch without thinking about it (he would need to first manufacture a specific cable to do so).</p> <p>EDIT2 :</p> <ul> <li>most devices powered by PoE will be outside the metalic box</li> <li>there will be some PoE+ and PoE++ devices</li> <li>for PoE/PoE+ on 100Mbps Ethernet, the power will be on the data lines (the whole point of using 100Mbps only on some connectors instead of 1Gbps is to need only 4 wires, freeing the other ones for other signals)</li> <li>all ethernet switching and PoE(+/++) will happen on my PCB (for the 1Gbps switching in a PCB mounted module, the 100Mbps switching and injection directly with ICs). No off the shelf Ethernet switches or PoE injectors will be used (space is quite limited, so I need tighter integration than what of the shelf products would allow)</li> </ul>

PoE: PSE isolation requirements

2024-01-23T13:21:07.683

698631

|resistors|audio|identification|

<p>Resistor identified. It a 10ohm 3 watt fusable resistor. I identified the wattage based on the dimensions. It took a bit of trial and error getting the right resistance but did some guesswork based on input voltage and found a safe starting number and worked my way down till something worked. Crude but effective. I was able to get a resistance reading off the burnt resistor by touching the exposed core to a wire end. That also read 10ohms but I wasn't sure I could trust that reading initially.</p>

<p><a href="https://i.stack.imgur.com/GYDlF.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/GYDlF.png" alt="failed resistor" /></a></p> <p>I have a Daewoo AVS1339 200 W barrel speaker. It failed the other day and no power is getting to the display.</p> <p>After some testing with a multimeter and visual inspection I found a resistor with scorch marks and a cracked ceramic coating.</p> <p>I am trying to replace the resistor but can't identify what I need. It's a basic grey resistor with one visible black band at the top. Length is about 14 mm, width is 4 mm. The input voltage for the speaker is 15 V. Attached is a picture of the failed resistor. Any ideas what type this might be?</p>

Identify resistor on Daewoo AVS1339 speaker

2024-01-23T13:34:08.757

698637

|operational-amplifier|identification|surface-mount|

<p>Could be Analog Devices <a href="https://www.analog.com/media/en/technical-documentation/data-sheets/ada4896-2_4897-1_4897-2.pdf" rel="nofollow noreferrer">ADA4896 series</a>. Single channel rail-to-rail OP. Marking H2P. Ground on pin 4, supply on pin 7 (pin 8 is a /Disable pin and could be tied to Vdd probably). And this might be what they call a &quot;LFCSP-8&quot; package aka MO-229, with a pad underneath the chip indeed (I'd probably call it &quot;QFN&quot; too).</p>

<p>I'm looking for help identifying this chip, which I believe is a dual op-amp (pin 4 is grounded, pin 8 is power). Package appears to be QFN, possibly with a pad (there are no vias under the chip). I suspect an op-amp because of the application (analogue sensor signal conditioning board) with several other op-amps.</p> <p>If it is an op-amp, it will be a low-noise, low-offset, low-bias variety given the instrumentation application.</p> <p>I've tried looking up the marking &quot;H2P IFA&quot; using a variety of reverse lookup tables without success (H2P returns some 5-pin devices).</p> <p>I've said that the second line of marking is &quot;IFA&quot;, but the &quot;I&quot; is curiously-wide. Under the scope it looks vaguely like a cartoon pine tree or a gummy bear (see images). <a href="https://i.stack.imgur.com/z8LX8.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/z8LX8.jpg" alt="Entire chip" /></a><a href="https://i.stack.imgur.com/UQYbL.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/UQYbL.jpg" alt="Closeup of the &quot;I&quot;" /></a></p> <p>Any assistance would be appreciated!</p>

Assistance identifying an op-amp marked "H2P IFA"- includes photos

2024-01-23T15:53:16.087

698644

|current|current-measurement|multimeter|

<blockquote> <p>I was trying to calculate [the Thevenin equivalent resistance] using an open circuit voltage and short circuit current</p> </blockquote> <p>A low-cost multimeter's low-range current shunt is far from a short circuit. You have to post-process the measurement, based on the burden voltage, i.e. the voltage across the non-ideal &quot;short circuit&quot; that the multimeter's shunt represents.</p> <p>The two measurements you're performing look as follows:</p> <p><img src="https://i.stack.imgur.com/sKdZK.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fsKdZK.png">simulate this circuit</a> &ndash; Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a>}</p> <p>As you can see, the non-zero burden voltage of a real multimeter's current shunt has to be measured in-circuit and subtracted from Voc measured using VM1. The burden voltage is current-dependent, so it must be measured in-circuit. Out-of-circuit burden voltage will be zero.</p> <p>Also note that the Rmeter is the shunt resistance of a voltmeter circuit in a multimeter. Typical nominal values are either 1MΩ or 10MΩ, but that's not always the case. Some multimeters have a high-impedance mode where Rmeter is on the order of giga-ohms. Analog multimeters have resistance that scales with voltage, say 20kΩ/V may be typical.</p> <p>The reason for the burden voltage is that the &quot;short circuit&quot; of a multimeter is very much a non-zero resistance:</p> <p><img src="https://i.stack.imgur.com/P4ZBU.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fP4ZBU.png">simulate this circuit</a>}</p> <p>The exact value of Rshunt depends on the multimeter and on the chosen measurement range. You can measure it using an ohmmeter attached across the current input, as long as auto-ranging is disabled (i.e. you've manually chosen the measurement range).</p>

<p>I was trying to calculate R_TH using an open-circuit voltage and a short-circuit current, and I am having trouble with the current measurement. I noticed that my calculated R_TH didn’t match my measured value.</p> <p>I’ve tried 3 different multimeters and on all of them, my voltage and resistance values are consistent, but my current values are all completely different. I checked the fuses and there doesn’t seem to be anything wrong with the multimeters. Any idea on what I’m doing wrong?</p> <p>The cheapest multimeter is the only one that appears to give a valid current reading (based on the voltage and resistance values). I got 0.96 mA with a DT830B multimeter (unsure of the brand), 1.3 mA with a Mastfuyi FY8233E multimeter, and 2.47 mA with a Klein MM400 multimeter.</p> <p>The reason I don't have the blue one on the 60 mA setting is because it was giving 14.88 mA, which was wayyyy off. I don’t know why it was doing that either .</p> <p>I’ve attached images below of the multimeters I used:</p> <p><a href="https://i.stack.imgur.com/uNweR.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/uNweR.png" alt="DT830B Multimeter" /></a></p> <p><a href="https://i.stack.imgur.com/0lz0h.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/0lz0h.jpg" alt="Mastfuyi FY8233E Multimeter" /></a></p> <p><a href="https://i.stack.imgur.com/mM478.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/mM478.jpg" alt="Klein MM400 Multimeter" /></a></p>

Why do different multimeters give me very different current measurements?

2024-01-23T16:26:47.083

698661

|batteries|capacitor|dc|

<p>Your reasoning of a change in charge density is about right.</p> <p>If you push an electron onto one plate of the capacitor, the charge density there will necessarily rise, but in doing so, the increased negative potential of that plate will repel an electron out of the other plate, thereby reducing the charge density on the other side of the dielectric.</p> <p>Said another way, if an electron enters one side of a capacitor, an electron must <em>leave</em> the other side. Repeatedly forcing an electron onto one plate leaves you with an accumulation of electrons on one plate (the plate became negatively charged), and a deficit of the same number of electrons on the other plate (positively charged). To an external observer, Kirchhoff's current law (KCL) is not violated; current in both capacitor terminals is equal.</p> <p>That's how a current can flow &quot;through&quot; a capacitor. There appears to be a current flow, equal on both sides in accordance with KCL, but in reality no electron ever crosses the dielectric barrier.</p> <p>Also to an external observer, the net electric charge of the capacitor is still zero. There are still equal numbers of protons and electrons throughout the material of the <em>entire</em> capacitor but locally to the plates there <em>is</em> a charge imbalance, immediately either side of the dielectric, an imbalance which gives rise to the potential difference (voltage) across the capacitor.</p> <p>Current stops flowing altogether when the potential difference of the voltage source (battery) equals the difference in potential of charges on the capacitor plates. That's logical, considering that to push an extra electron onto a plate, that electron must have greater potential energy than those already there. This means that current flow will only be momentary, until the source and capacitor potential differences equalise.</p> <p>As far as the wires are concerned, it's true that for there to be a current flow along a wire, there must be a potential difference between the two ends, suggesting that there is a place of lower potential energy that a charge can/will move towards, and this would imply a charge density gradient along the wire. Initially, immediately after the capacitor is connected to the source, this will be the case.</p> <p>If current were unconstrained by resistance in the loop, it would be infinite, but that's never the case. Everything in the system has resistance, including the battery and wiring, so current will be capped. Initially the voltage source has some potential difference, and the capacitor has zero potential difference, and by connecting them together you produce a situation in which charges must move from one to the other to make them equal. The imbalance must be resolved. Charges will move through whatever resistances are present in the loop, and it is those resistances which initially have the greatest potential difference across them, bridging the gap between source and capacitor voltages, but limiting the current that will flow according to Ohm's law. If those resistances are small, with a large potential difference across them current will be huge.</p> <p>So, yes, there will initially be a potential gradient along the wires, and along resistances inside the voltage source itself, which is what is meant by an &quot;electric field&quot;, and that gradient is what defines the forces on charges that find themselves there, and the potential energy they possess. That's what propels the charges, always to a place of lower potential energy.</p> <p>Explicitly placing a resistor in the loop is a measure to control initial current, and the greater that resistance, the greater its initial share of the potential difference, meaning that the source and wiring resistances share a much smaller fraction of the overall potential discrepancy.</p> <p>Eventually though, capacitor voltage will have risen enough to equal the voltage source, and there will be a state of equilibrium, in which there's no current because no conductive element in the system has any potential difference across it; all charges at all points along any conductive part of the loop have the same potential. The two wires each have the same electrical potential along their length, so there's uniform electron distribution (thermal and quantum fluctuations notwithstanding) along them. The charge imbalance is constrained to the vicinity of the capacitor plates.</p> <p>All this is a macroscopic understanding of the system, in classical terms. Depending on how deep you want to go down this rabbit-hole, what really happens is less prosaic. <a href="https://electronics.stackexchange.com/a/695688/292884">Here's another answer I wrote</a> addressing these mechanisms in terms of potential waves and, to some extent, quantum principles.</p>

<p>To specify what I am asking: How do we even get a current for a moment when the circuit technically never is completed? And what is it that does this? Here I am thinking of a very simple circuit where there is a DC power source and a capacitor (if we want to be accurate, I'm sure we'd need a resistor as well).</p> <p>So, when we connect the DC power supply to this circuit, what happens inside? I understand that plates connected to a power supply will be charged according to the charge coming into it, so if the negative terminal of the battery were connected to a plate, it would cause that plate to be negatively charged as well. However, why does this happen and how?</p> <p>(Just realizing this is only indirectly correlated to a capacitor, but whatever.)</p> <p>First, I thought maybe the charge density in the two plates of the capacitor were changed according to the voltage applied, so that there would be a voltage across, but that also confused me and didn't make sense, because (unless I'm wrong) for there to be higher charge density in one part of the wire, wouldn't the charge density have to decrease at other places in the wire? And wouldn't this have created a local electric field through this wire?</p> <p>I tried to draw a picture to visualize what I'm thinking (the stronger the color, the greater the charge density):</p> <p><a href="https://i.stack.imgur.com/DCjKK.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/DCjKK.jpg" alt="enter image description here" /></a></p> <p>This just didn't feel right, so what is it that actually happens? Also, how does this give us a current for a second before it flattens out?</p>

What does really happen when you connect a capacitor in DC series?

2024-01-23T18:36:55.863

698662

|555|high-frequency|astable|

<p>Use a different 555 timer... The TI <a href="https://www.ti.com/lit/ds/symlink/lmc555.pdf" rel="nofollow noreferrer">LMC555</a> can run at up to 3MHz and should suit your application. Make sure you are soldering and not using a breadboard which has enough parasitic capacitance and inductance to be a problem for your target frequency. Solder or use a PCB if possible.</p>

<p>I need to produce a 1.7 MHz signal. Up to around 200 kHz the 555 IC and my simple astable circuit are working just fine as expected, but when I decrease R1 and R2 to less than 100 Ω the frequency doesn't increase more than about 200 kHz.</p> <p>I tried reducing C, but got the same result and it seems somehow I can't get frequencies beyond 300 kHz. Is there any limitation for higher frequencies with the 555? Any suggestions?</p>

How to get megahertz frequency with a 555?

2024-01-23T18:38:28.437

698675

|circuit-analysis|analog|integrated-circuit|comparator|

<p>Here's a more complete example from Professor Ikeda's openIP design library, unfortunately no longer on line.</p> <p><a href="https://i.stack.imgur.com/yXW8k.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/yXW8k.png" alt="enter image description here" /></a></p> <p>Two differential stages, the second with high gain, and then a high gain common source stage. Plenty of gain, which is what you want from a comaparator.</p>

<p>I'm trying to implement a comparator for ADC. The schematic is shown as follows.</p> <p><a href="https://i.stack.imgur.com/KRNKNm.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/KRNKNm.png" alt="schematic" /></a></p> <p>_{Image source: S. Lan, C. Yuan, Y. Y. H. Lam and L. Siek, &quot;An ultra low-power rail-to-rail comparator for ADC designs,&quot; <em>2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS)</em>, Seoul, Korea (South), 2011, pp. 1-4, doi: 10.1109/MWSCAS.2011.6026511 (<a href="https://ieeexplore.ieee.org/document/6026511" rel="nofollow noreferrer">link</a>)}</p> <p>My question is: if the gain of this opamp (it also looks like an OTA to me) is large enough, because I simulated this circuit and the gain was only 20. I'll explain my understanding of the circuit below:</p> <p>Suppose gm1=gm2=gm, and the input is a differential signal Vd. Then the gain from node Vo2 is gm times the impedance at node Vo2 (call it Ro2). Ro2 = 1/gm6 || Rout4 || Rout2 (the impedance at the node Vo2 is the parallel of the output resistance of M4, M6, and M2). The gain is even less than a single stage amplifier, because of the impedance in parallel.</p> <p>Is my analysis correct, and how to use this topology as a comparator?</p>

How to boost the gain of this comparator?

2024-01-23T19:45:06.900

698682

|rf|microwave|test-equipment|radiation|

<p>I never carried out this type of measurement in my previous work, but I do have a text on the subject. Unfortunately in French: <a href="https://www.j3ea.org/articles/j3ea/pdf/2016/01/j3ea160002.pdf" rel="nofollow noreferrer">https://www.j3ea.org/articles/j3ea/pdf/2016/01/j3ea160002.pdf</a></p> <p><a href="https://i.stack.imgur.com/vA2et.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/vA2et.png" alt="https://theses.hal.science/tel-03034434v1/document" /></a> <em>source:<a href="https://theses.hal.science/tel-03034434v1/document" rel="nofollow noreferrer">https://theses.hal.science/tel-03034434v1/document</a></em></p> <h2><strong>1-</strong> The first method</h2> <p>Was explained by Tim Williams</p> <p><a href="https://i.stack.imgur.com/yxtbi.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/yxtbi.png" alt="enter image description here" /></a> source:<a href="https://www.j3ea.org/articles/j3ea/pdf/2016/01/j3ea160002.pdf" rel="nofollow noreferrer">https://www.j3ea.org/articles/j3ea/pdf/2016/01/j3ea160002.pdf</a></p> <h2><strong>2-</strong> The second method</h2> <p>Consists of using a mode-stirred reverberation chamber. It's a very complex system, and I didn't have access to this type of equipment. It uses the reverberations to make measurements, unlike the anechoic chamber where they are attenuated to make the measurements.</p> <p><a href="https://i.stack.imgur.com/XJuwA.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/XJuwA.png" alt="enter image description here" /></a> source:<a href="https://www.j3ea.org/articles/j3ea/pdf/2016/01/j3ea160002.pdf" rel="nofollow noreferrer">https://www.j3ea.org/articles/j3ea/pdf/2016/01/j3ea160002.pdf</a></p> <h2><strong>3-</strong> The conclusion is interesting.</h2> <p>The anechoic chamber makes it possible to measure the high attenuation efficiency of shielding. Only two measurements are needed (without shielding for calibration and with shielding for measurement), but the actual efficiency is overestimated, since the main assumption is a plane wave perpendicular to the shielding. The mode-stirred reverberation chamber provides a better measure of efficiency; multiple polarization is more penalizing in terms of shielding efficiency, and the results, particularly at low frequencies, will be closer to the actual shielding efficiency.</p> <p><a href="https://i.stack.imgur.com/n4GeE.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/n4GeE.png" alt="enter image description here" /></a> source: <a href="https://www.j3ea.org/articles/j3ea/pdf/2016/01/j3ea160002.pdf" rel="nofollow noreferrer">https://www.j3ea.org/articles/j3ea/pdf/2016/01/j3ea160002.pdf</a></p>

<p>I am a hobbyist and I am intersted in testing some materials for their ability of reflectance/absorbance/transmittance for microwave radiation and I want to know if a spectrum analyzer is suitable for this task and how to do this (setup)?</p> <p>I posted this question in engineering site and I was recomanded to post here.</p>

Can I test the EM shielding of a material with a spectrum analyzer?

2024-01-23T20:16:46.190

698695

|voltage-regulator|troubleshooting|

<p>I would like to express my gratitude to all those who responded to my inquiry. Ultimately, I opted for a voltage divider given the stable 12V DC power source. Initially, the central component of the divider circuit was malfunctioning, but after fabricating a new PCB, everything functioned seamlessly. Regarding the regulators, I am uncertain about the issue. While the dividers were procured from a reputable source, there is a possibility that they were defective from the outset.</p>

<p>I am working on a PCB board that incorporates three <a href="https://www.ti.com/lit/ds/symlink/lm1085.pdf" rel="nofollow noreferrer">LM1085IT</a> voltage regulators, all connected to a common 12 V input source. The intended configuration is to obtain a regulated 5 V output from each LM1085IT. However, I am encountering an issue where one LM1085IT is providing the expected 5 V output, while the other two are outputting 12 V, despite having identical configurations.</p> <p>Here are the details of the setup:</p> <ul> <li>Input voltage: 12 V</li> <li>Three LM1085IT voltage regulators in parallel</li> <li>All LM1085IT components are configured for a 5 V output</li> <li>No load or minimal load conditions on the regulators</li> </ul> <p>Is this discrepancy in output voltage likely to be a result of faulty components, or could there be other factors contributing to this issue? I have double-checked the connections and configurations, and they seem consistent across all three LM1085IT components. Any insights or troubleshooting tips would be greatly appreciated.</p> <p><a href="https://i.stack.imgur.com/NR5xE.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/NR5xE.png" alt="Schematic" /></a></p> <p>EDIT: I rearranged the placement of the operational regulator, exchanging it with one of the faulty regulators. Currently, it appears that the previously functional regulator is no longer regulating properly, delivering 12V, while the other one is providing 5V. This suggests that the issue likely resides within the circuit. Any suggestions on what could be causing this problem?</p> <p>EDIT-2: I reprinted the PCB, and initially, every regulator exhibited a 5V output. However, after several instances of use, the second regulator resumed outputting 12V.</p> <p>EDIT-3: After successfully reassembling the circuit board, all regulators were initially functioning correctly. However, following several applications, the middle regulator inexplicably began generating a 12V output. Unfortunately, this issue went unnoticed until the connected device experienced damage from overvoltage. Subsequently, the load on the device increased beyond the minimum threshold. Even after the device was destroyed, the middle regulator consistently produces a 12V output under varying loads.</p> <p><a href="https://i.stack.imgur.com/jCSOk.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/jCSOk.png" alt="Layout" /></a></p> <p><a href="https://i.stack.imgur.com/ldo6C.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/ldo6C.jpg" alt="Soldered board" /></a></p> <p><a href="https://i.stack.imgur.com/VBDnw.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/VBDnw.jpg" alt="Top View" /></a></p> <p>EDIT-4: Given that my input voltage remains stable at 12V, and aiming for an output voltage around 5V (with a tolerance range of 4.8V to 6.3V), I considered implementing three voltage dividers using resistor values of R1 = 220k and R2 = 180k. However, upon measuring the output voltage, I observed that the middle divider exhibited the same problem as the middle regulator, both outputting 12V (equivalent to the input voltage), while the other dividers yielded the correct 5V. While this alignment may be coincidental, it could provide valuable insights into the underlying issue with the regulators.</p> <p><a href="https://i.stack.imgur.com/ZrtOg.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/ZrtOg.png" alt="Voltage Divider" /></a></p>

LM1085IT-5.0 voltage regulator outputting 12 V instead of 5 V with 12 V input

2024-01-24T01:35:36.667

698700

|amplifier|circuit-design|audio|signal-integrity|coax|

<p><em>&quot;RCA output&quot;</em> is a bit vague but this answer assumes you're trying to handle <em>video</em> signals. The answers are mostly valid for audio signals as well, it would just be unusual or audiophile-grade weird. If your TV has audio outputs through RCA connectors they are likely <em>not</em> designed for a terminated receiver!</p> <ol> <li>Since you only have control of the <em>sink</em> (as opposed to the <em>source</em>; you're at the receiving end) you can and must do parallel termination. Video transmission depends on it, and the source assumes it.</li> <li>The values must equal the impedance. (but don't obsess about sub-percentage tolerances)</li> <li>To my knowledge there are no consumer or professional video applications with 50 Ω impedance. It's all 75 Ω, so don't bother trying to do both. If you don't know, assume it's 75 Ω.</li> </ol> <p>If you have an oscilloscope you should be able to measure the impedance (and length!) of an unknown cable.</p>

<p>I am building an amplifier that takes in an RCA output from a TV. From my general understanding, RCA coaxial cables typically have an impedance of either 50 Ω or 75 Ω and a small amount of capacitance in the pF range, and require end termination to prevent signal 'bounce' (or reflection).</p> <p>A couple of questions:</p> <ol> <li>Is series or parallel termination with resistors (no isolation transformers used) better in terms of signal quality and latency/propagation?</li> <li>What value resistor do I use for terminating 50 Ω or 75 Ω cables (single end termination only)?</li> <li>Is it possible to design a termination circuit for both 50 Ω and 75 Ω cables? This is especially since my local store does not list impedances for generic RCA coax cables, nor have I found a reliable way to measure said cable.</li> </ol>

RCA coax end termination

2024-01-24T02:33:49.857

698707

|circuit-design|truth-table|

<h3>to start</h3> <p>I believe you have correctly drawn out a viable table with everything you need. I can't argue with it. But it appears you need help with k-maps. So let's get going on that.</p> <p><em>(In the following, I'm using a tool called <a href="https://github.com/hneemann/Digital" rel="nofollow noreferrer"><strong>Neemann's Digital</strong></a>.)</em></p> <h3>RED k-map</h3> <p>The k-map for the RED LIGHT is probably easier to see and make from your table:</p> <p><span class="math-container">\$\quad\quad\quad\quad\quad\$</span> <a href="https://i.stack.imgur.com/rZATZ.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/rZATZ.png" alt="enter image description here" /></a></p> <p>Here's what the above might look like as a start for your circuit:</p> <p><a href="https://i.stack.imgur.com/qVA7A.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/qVA7A.png" alt="enter image description here" /></a></p> <h3>GREEN k-map</h3> <p>The k-map for the GREEN LIGHT is only slightly harder to see by eye:</p> <p><span class="math-container">\$\quad\quad\quad\quad\$</span> <a href="https://i.stack.imgur.com/JeKgt.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/JeKgt.png" alt="enter image description here" /></a></p> <p>But you know that it must only the case for <span class="math-container">\$\overline{S_2}\: \overline{S_1}\: \overline{S_0}\$</span>, too, because of how you designed things. So it's not difficult to work out the above k-map from that knowledge.</p> <p>Here's the newly modified circuit to include that light:</p> <p><a href="https://i.stack.imgur.com/p7HWg.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/p7HWg.png" alt="enter image description here" /></a></p> <h3>RED k-map you produced</h3> <p>But let's stop for a moment and look at what you <em><strong>actually</strong></em> produced for your <strong>RED</strong> table (newly updated in your question -- thanks):</p> <p><a href="https://i.stack.imgur.com/8WkxO.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/8WkxO.png" alt="enter image description here" /></a></p> <p>It's not correct. I'm not sure how you created your table on the left side there. But you missed a lot. Do you see how it is really just <span class="math-container">\$S_2+S_1 S_0\$</span>?</p> <p><em>(This is just doing it <strong>by eye</strong>. But it's also not hard to see.)</em></p> <h3>automated tool</h3> <p>Perhaps you would like to use an automated tool for this work, instead?</p> <p>Let's take a moment's break and grab up a copy of <a href="https://github.com/hneemann/Digital" rel="nofollow noreferrer"><strong>Neemann's Digital</strong></a>.</p> <p>Then you may access the following service it offers:</p> <p><a href="https://i.stack.imgur.com/jo4j2.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/jo4j2.png" alt="enter image description here" /></a></p> <p>This will pop up a starter dialog for you that looks like this:</p> <p><a href="https://i.stack.imgur.com/p3V2L.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/p3V2L.png" alt="enter image description here" /></a></p> <p>Right-click on the titles to change them <em>(note that using an underscore in the name causes the following text to appear as a subscript)</em>:</p> <p><a href="https://i.stack.imgur.com/edRY3.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/edRY3.png" alt="enter image description here" /></a></p> <p>Then add another input variable:</p> <p><a href="https://i.stack.imgur.com/Q90mF.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/Q90mF.png" alt="enter image description here" /></a></p> <p>Unfortunately, this adds it to the end of the current list <em>(and gives it a default name, which you need to rename as well.)</em> So move it to the front:</p> <p><a href="https://i.stack.imgur.com/zln0P.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/zln0P.png" alt="enter image description here" /></a></p> <p>Now rename the output column <strong>Y</strong> to <strong>RED</strong> and add more output columns:</p> <p><a href="https://i.stack.imgur.com/G8E3v.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/G8E3v.png" alt="enter image description here" /></a></p> <p>Your table might now look like this:</p> <p><a href="https://i.stack.imgur.com/euH15.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/euH15.png" alt="enter image description here" /></a></p> <p>At this point, start marking the values in the output columns. For example, this is what it looks like when modifying the <strong>GREEN</strong> column to make it a <strong>1</strong>:</p> <p><a href="https://i.stack.imgur.com/HXnCu.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/HXnCu.png" alt="enter image description here" /></a></p> <p>When done, you should have the following table completed:</p> <p><a href="https://i.stack.imgur.com/4dOyW.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/4dOyW.png" alt="enter image description here" /></a></p> <p>Then select the k-map option:</p> <p><a href="https://i.stack.imgur.com/Llg9R.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/Llg9R.png" alt="enter image description here" /></a></p> <p>Then you can work through that to find:</p> <p><a href="https://i.stack.imgur.com/uZxmt.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/uZxmt.png" alt="enter image description here" /></a></p> <p>This is a little more nuanced than what I produced above, as it includes the <code>don't care</code> states for <strong>state 7</strong>.</p> <p>If you now use the following table service:</p> <p><a href="https://i.stack.imgur.com/QlLDE.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/QlLDE.png" alt="enter image description here" /></a></p> <p>It will generate the logic for the above in a separate instance of <strong>Digital</strong>:</p> <p><a href="https://i.stack.imgur.com/k1jZD.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/k1jZD.png" alt="enter image description here" /></a></p> <p>On the left side above is what <strong>Digital</strong> generated, directly, using <strong>AND</strong>/<strong>OR</strong> logic.</p> <p>Clearly, also, the inputs will instead be coming from the D FFs you already know you need to set up. So on the right side I've added those, by hand.</p> <h2>summary</h2> <p>At this point, I think I've carried you far enough along. You should be able to generate your own table for creating the inputs needed for the D FFs. If you followed the above process, all you need to do is now add three more output columns to represent the next state in your table. Then correctly fill them out. (<em>If you want, you can reorder the output columns, too.</em>)</p> <p>I also would suggest that you play with some of the other options you have available in <strong>Digital</strong>, too. I've only touched upon a few of your choices. For example, <strong>Digital</strong> will generate CUPL or JEDEC code that can be used to program a <a href="https://ece-classes.usc.edu/ee459/library/datasheets/16v8.pdf" rel="nofollow noreferrer">GAL16V8</a>! Explore.</p>

<p>I am currently working on a traffic light system, the state transition table developed for the project reads as follows:<br /> <a href="https://i.stack.imgur.com/huwaH.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/huwaH.png" alt="enter image description here" /></a><br /> I have additionally used Neeman's Digital software to create a table (and K-Maps) for the output F2, F1, and F0.</p> <p>As I was trying to repeat the process for D2, D1 and D0, with a table that has the following appearance. I would like to clarify that the Input I is being represented by E in the table.<br /> <a href="https://i.stack.imgur.com/MVReY.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/MVReY.png" alt="D truth table" /></a></p> <p>Which returns the following expressions for the output expressions:<br /> <a href="https://i.stack.imgur.com/P7Nnn.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/P7Nnn.png" alt="x expressions" /></a></p> <p>I have also tried replacing the x with 0 and get the following output expressions:<br /> <a href="https://i.stack.imgur.com/XGS2v.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/XGS2v.png" alt="0 expressions" /></a></p> <p>Both these aproaches revealed insufficient, because only F0 (the GREEN light) gets lit up, even when Input is true. I would therefore like help resolving this issue.<br /> Thank you very much.</p>

Help with truth table and K-Maps

2024-01-24T04:08:35.793

698708

|connector|

<p>It looks like a <a href="https://www.te.com/usa-en/product-292133-8.datasheet.pdf" rel="nofollow noreferrer">TE AMP CT</a> header. Part numbers probably 292133-10 and -6.</p>

<p>I am trying to identify these board-to-wire connectors found on a PCB for a garage opener. The pitch is 2mm. At first I thought they were JST PH, but the two slots are spaced a little too far apart, and a JST PH cable will not fit. The unit is sold in the US and the PCB has the year 2017 printed on it.</p> <p>They are not latched, and fully shrouded, with openings only on the sides.</p> <p>I have tried web searches and the <a href="https://connectorbook.com/identification.html" rel="nofollow noreferrer">Identiconn utility</a> but failed to find any matches.</p> <p>Ideally I would like to find a ready-made cable for the 10-pin connector.</p> <p><a href="https://i.stack.imgur.com/TmPN8.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/TmPN8.jpg" alt="10-pin connector" /></a> <a href="https://i.stack.imgur.com/OOxWU.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/OOxWU.jpg" alt="enter image description here" /></a></p>

Can you identify these connectors (JST or Molex type)?

2024-01-24T04:33:11.470

698714

|led|fluorescent-lamp|ballast|

<p>A magnetic ballast is no different than a choke, so it has an inductance and a series resistance (DC resistance - DCR).</p> <p>If you leave it in the circuit it'll be in series with the entire circuit. Depending on the current drawn, its DC resistance will dissipate some power.</p> <blockquote> <p>...with a further ~9 Watts lost in the magnetic ballast...</p> </blockquote> <p>This looks like an exaggeration to me. Normally, a 36W tube along with a magnetic ballast (the entire circuit), draws an RMS current of ~0.5 A when supplied from 230V grid and with no power correction at all. A dedicated magnetic ballast is usually an iron-core choke with an inductance of usually 1~1.5 Henries and a DCR of 30~40 Ohms. Now if you work out the current and DCR the real dissipation of the choke should be about 6-7 Watts. But maybe, in some circumstances, the dissipation may increase so the author of the reference might have taken those into account.</p> <hr /> <p><strong>EDIT:</strong> My &quot;~0.5 Amps&quot; above was a crude guess from memory. The RMS current drawn by a magnetic ballast and tube network should be around <strong>0.3 ~ 0.4 Amps</strong> from 230 V if there's no power correction which is usually done with a parallel capacitor across the L-N.</p> <p>Now, for an <strong>uncorrected</strong> setup, the total apparent power will be around 80-85 VA but let's be pessimistic and take 90 VA. For an uncorrected PF of 0.5, the real power will be 45 W, therefore leaving 9 W of real power dissipation to the ballast/choke if we assume the tube will dissipate 36 W <em>(usually they are overdriven slightly but let's be optimistic here)</em>. So a pessimistic approximation verifies that the ballast choke may dissipate 9 Watts, but the real numbers usually hover around 6-8 W. I also took the cold resistance of a typical 36 W magnetic ballast, so it may increase a little when hot and increase the dissipation further to approach 9 Watts.</p>

<p>The diagrams for the GE T8 tubes have these alternative retrofit circuit diagrams:</p> <p><a href="https://i.stack.imgur.com/4GxDf.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/4GxDf.png" alt="Electronic to Fuse only" /></a></p> <p><a href="https://i.stack.imgur.com/DVn0s.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/DVn0s.png" alt="Magnetic and Starter to Magnetic and Fuse" /></a></p> <p>On this website, <a href="https://reductionrevolution.com.au/products/philips-led-tube-t8" rel="nofollow noreferrer">9W in Starter</a>, it states:</p> <blockquote> <p>....with a further ~9 Watts lost in the magnetic ballast...</p> </blockquote> <p>I have magnetic ballasts and a starter, so the retrofit does not require a rewire, but I will leave the magnetic ballast in the circuit. However, I could rewire and remove the ballast.</p> <p>My question is: will it actually save 9 W, or is that loss only when a fluorescent tube is in the circuit?</p> <p>I have found that the Philips installation instructions match the GE ones, but I could only found the GE circuits.</p> <p>I have read this <a href="https://electronics.stackexchange.com/questions/95491/is-it-more-energy-efficient-to-remove-the-ballast-by-using-led-tube/194725#194725">SE.EE question</a>, but it really does not have an answer.</p>

How much more energy-efficient is it to remove the magnetic ballast for an LED tube?

2024-01-24T07:26:37.200

698725

|microcontroller|digital-logic|circuit-design|schematics|

<blockquote> <p><em>What is the purpose of R32 resistor?</em></p> </blockquote> <p>R32 does two different things: -</p> <ol> <li>It discharges the capacitor should the main power (VCC3) be removed</li> <li>It elongates the time the device remains in reset when VCC3 is applied</li> </ol> <p>Personally I wouldn't recommend designing it for (2) because there is a danger that it never comes out of reset should the Schmitt trigger threshold not be reached. Instead just make C7 a larger value.</p> <blockquote> <p><em>if I want to make a manual reset, is it ok to place a button in parallel with capacitor?</em></p> </blockquote> <p>Yes it's OK but you need a small value resistor in series with the switch to avoid a high impulse discharge current. Maybe 10 Ω to 100 Ω.</p>

<p>I'm designing a device based on Prolific PL2773 and in reference PCB schematic there is an unusual reset circuit.</p> <p><a href="https://i.stack.imgur.com/p6qLf.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/p6qLf.png" alt="PL2773 reset circuit" /></a></p> <p>VCC3 is 3.3V and reset input (RESETB) is active low 3.3V TTL input with Schmitt-trigger (Vt- 1.1V, Vt+ 1.6V). What is the purpose of R32 resistor? And, if I want to make a manual reset, is it ok to place a button in parallel with capacitor?</p>

The purpose of resistor and capacitor in parallel in MCU reset circuit

2024-01-24T10:54:07.050

698728

|operational-amplifier|ltspice|simulation|differential-amplifier|

<p>Notice the sensed voltage (at least <code>Vdiff+</code>) is clamped by D2/D3 between 0 and 9.6V (or rather a Vf beyond that range). Suppose it's at +9.6V, and follow the resistor divider path R6/R8 to the output. Even if the amp is saturated hard negative (-3.3V) (which is plausible, being that we're applying positive voltage to -IN), the 1M/1M divider puts -IN at ((9.6V) - (-3.3V)) * (1MΩ) / (1MΩ + 1MΩ) + (-3.3V) = 3.15V, dangerously close to the positive supply rail. But the input differential is not sufficient to do that, it's only about 1.2V and the gain is 1, so the output will be about 1.2V (or, try to be), and <code>Vdiff+</code> will hit the ESD clamp diode. Note in the <a href="https://www.analog.com/media/en/technical-documentation/data-sheets/max4162-max4164.pdf" rel="nofollow noreferrer">datasheet</a>, the inputs are limited to 0.3V outside Vdd/Vss, usually implying clamp diodes to the respective supplies for ESD protection.</p> <p>The common-mode shunt resistors R7, R9 act to increase the noise gain of the amplifier. They literally reduce the input (error voltage) to the amp, increasing noise as the name suggests, reducing loop gain and bandwidth; normally this is undesirable, but here, it reduces the common-mode voltage, allowing the amp to continue to function at all.</p> <p>The values are given by the common-mode (average of both inputs) or normal-mode (each divider by itself) gain from the sensed nodes to the amp, and the design maximum value of V3.</p>

<p>I'm trying to measure a differential voltage in LTSpice using the following structure: <a href="https://i.stack.imgur.com/nfM92.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/nfM92.png" alt="enter image description here" /></a></p> <p>The simulation results are correct, the voltage at the output is very similar to the differential input voltage. My question is: Why are the 40k resistors R7 and R9 needed? When I remove them, the results are not correct (see second picture), and with some OpAmps the simulation will even fail.</p> <p><a href="https://i.stack.imgur.com/xRzLE.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/xRzLE.png" alt="correct results" /></a></p> <p>These are the waveforms when I remove R7 and R9. But that is the typical differential amplifier structure. Can anyone tell me why this happens?</p> <p><a href="https://i.stack.imgur.com/HY6mW.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/HY6mW.png" alt="enter image description here" /></a> <a href="https://i.stack.imgur.com/7QaG1.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/7QaG1.png" alt="enter image description here" /></a></p> <p><strong>Edit:</strong> this is the full schematic including Vcc and Vss: <a href="https://i.stack.imgur.com/XOIzU.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/XOIzU.png" alt="enter image description here" /></a></p>

Why won't this differential amplifier work without these two additional resistors?

2024-01-24T11:07:36.437

698731

|ac|delay|

<p>Yes, there are AC time-delay relays, usually based on heating a bimetallic strip at a controlled rate.</p> <p>Other methods for more complex sequencing include motor-driven cam switches, etc.</p> <p>I can't think of any purely electronic methods that don't involve converting the AC to DC at some point.</p>

<p>Sorry if it's a stupid question but.. is there any AC delay circuit? All I know is RC and RL circuits but are based on DC current For example, to delay for a second the triggering of an AC relay thanks</p>

AC delay circuit question

2024-01-24T11:59:30.360

698732

|motor|electromagnetism|brushless-dc-motor|electromagnetic|power-engineering|

<p>At some point the gap will no longer dominate the total reluctance of the magnetic circuit you you'll get diminishing returns. Otherwise you'd be approaching infinite torque with zero gap, which is not going to happen any more than magnets which come into contact are inseparable.</p> <p>Things like manufacturing tolerances and bearing runout (new and at end of life) will limit how narrow the gap can be made, in any case.</p>

<p>I'm asking this because the smaller the distances between electromagnets, the stronger the electromagnetic field.</p> <p>I don't know if this would mean a proportional increase in power, be it either torque or RPM.</p> <p>The closest I could find to this was <a href="https://digital.wpi.edu/pdfviewer/9p2909417" rel="nofollow noreferrer">this article which explores the use of ferrofluids to reduce the gap</a>. It was able to double the torque, but nothing in a proportional sense.</p>

Would reducing the air gap between the rotor and stator to micrometer/nanometer scale distance proportionately increase a motor's power?

2024-01-24T12:03:30.467

698734

|i2c|esp32|

<p>Yes, it was a mistake to pull 3.3V IO pins to 5V with resistors.</p> <p>It does not blow up because you can assume that MCU IO pins have built-in protection diodes to supply voltage to clamp excessive input voltages from doing damage.</p> <p>And since you have resistors, they limit current which allow the protection diodes to work instead of damage due to excessive current.</p> <p>Assuming the MCU supply is 3.3V, and the protection diodes start to conduct at about 0.5V above that, there will be 3.8V on IO pin and clamping current is only about 0.25mA. So this is why it did not burn.</p> <p>There is no one true and correct value. There is a suitable range which depends on many things you are not mentioning. It depends on which speed you want to communicate, and how much total capacitance there is on bus, which depends on your wiring/cabling, bus length, number of devices on bus, how fast they are capable of communicating and in which mode, and in which limits they need to operate. So there are I2C specification limits, and limits imposed by the chips which may be within or outside I2C specs, and there is the limits imposed by the environment the chips are in, and that may also be within or outside of I2C specs.</p> <p>So 4k7 to 3.3V could either work or not. It will be somewhat slower bus than 4k7 to 5V. It depends if any other module already has pull-ups or not. The total pull-up resistance must not be too strong or too weak, so that all chips are capable of reliably communicating at the speed you want to use, and you may need to do some tradeoffs.</p> <p>And yes if you have devices with 5V I2C bus which are not compatible with 3.3V I2C bus then you need a level shifter.</p> <p>Even if you have slave modules that take in 5V supply, it means nothing how they work internally, as they might still have internal 3.3V regulation and must not be connected to a 5V I2C bus.</p>

<p>I have a question about I2C and esp32. when I started long time ago making circuit based on esp32 I think i have made a mistake on the pullup resistor by putting 4.7K on 5 volt on i2c lines.</p> <p>the I2C lines work well I want to know why i did not burn esp32 SDA and SCL pin witch are 3.3 volt logic ?</p> <p>if I am wrong what is the value for the resistor on 3.3volt.</p> <p>Last question about slaves modules with are 5v do I need a level shifter on the i2c line in case of 3.3 volt resistor line.</p>

I2C circuit resistance value

2024-01-24T12:17:15.160

698745

|dc|inductance|back-emf|

<blockquote> <p><em>So my question is which of these two scenarios is correct?</em></p> </blockquote> <p>Neither.</p> <ul> <li><p>At the instant that S3 shorts, there is <strong>still</strong> 1 amp flowing through L1, R1 and R2.</p> </li> <li><p>Given that R1 (2.5 Ω) is grounded to 0 volts by S3, the top node of R1 has to be at -2.5 volts.</p> </li> <li><p>I think you can work out the other voltage now.</p> </li> </ul>

<p>I have been learning the basics of inductors in simple LR circuits with DC currents. I think I get most of it but I am a bit unclear about the secondary EMF produced by the inductor after the primary supply is disconnected. In particular I am unsure about the actual electric potentials at the ends of the inductor just after the primary battery supply has been disconnected.</p> <p>In the QUCS (v. 0.0.19) transient simulation image below, the maximum voltage drop across the inductor (L1), at time &gt; 0.150 s is about -5 V (see the graph for voltage probe PR2). (I would like to plot the value of potential around the circuit at different times - but I have not found a way to do this with QUCS).</p> <p><a href="https://i.stack.imgur.com/hEbup.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/hEbup.png" alt="Figure 1" /></a></p> <p>I assume that this means the potential at the front is 0 V and at the back it is about +5 V. This would make sense to me in that the inductor subsequently acts like a dying battery - pushing a dwindling current around the secondary loop in a clockwise direction.</p> <p>But I am also aware that the -5 V voltage drop across the inductor could also be caused by potentials of -5 V at the front and 0 V at the end. It seems to me that scenario would also drive a current around the secondary loop in the clockwise direction.</p> <p>So my question is: which of these two scenarios is correct?</p> <p><strong>Update after Question Answered</strong></p> <p>Following the receommendation by u/RussellH I probed the potentials at points A,B,C,D with the following (QUCS) graphical results (below). I also plotted (in Excel)(further below) the profile of Potential vs. X (relative position along the section of the circuit containing R1,L1,R2).</p> <p><a href="https://i.stack.imgur.com/qsxDn.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/qsxDn.png" alt="QUCS plot of Potentials and Voltage Drops" /></a></p> <p><a href="https://i.stack.imgur.com/ZFsmV.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/ZFsmV.png" alt="Excel plot of Potential P profiles along X at different times" /></a></p>

What are the potentials at front and back of inductor when primary DC supply is disconnected in LR circuit?

2024-01-24T13:53:05.750

698757

|i2s|

<p>I2S bus does have an addressing mechanism. Otherwise it could not know the difference which sample is left or right, or even which bits belong to which sample.</p> <p>That sync signal can have multiple names but it is called WS in ESP32 MCUs.</p> <p>And there are multiple methods how to transfer 8 PCM channels on I2S. The ESP32 supports 8 channels as four data wires sending 2 I2S channels each, or in TDM mode with up to 16 channels on single data wire.</p> <p>But the mic sends PDM bits, not multi-bit PCM samples. There can be only two mics per data wire, and the correct clock to use for the mics is WS because also the ESP32 has to be in PDM input mode. So the bit clock is not needed.</p>

<p>I'm currently working on a graduation project where I am tasked with building an embedded system using an ESP32-S3 and four MEMS microphones capable of detecting ultrasonic waves. The goal is to understand the sound specifications of an industrial machine. The specific microphone model I am using is the SPH0641LU4H-1. You can find the datasheet here (<a href="https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/930/SPH0641LU4H-1.PDF" rel="nofollow noreferrer">https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/930/SPH0641LU4H-1.PDF</a>).</p> <p>In the ESP32 documentation, particularly in the ESP-IDF programming guide, I've learned that the ESP32 has two built-in I2S (Inter-IC Sound) interfaces, namely I2S0 and I2S1. However, I noticed that while I2S0 can support up to 8 multiple sound sources in mono mode, I couldn't find clear information on how the microcontroller distinguishes between these data sources. Unlike I2C, the I2S bus frame doesn't have a specific addressing mechanism.</p>

integration of multiple microphones in same ESP32-S3 I2S interface

2024-01-24T15:07:52.497

698763

|transient|

<p>Well, notice that we know that:</p> <p><span class="math-container">$$\text{V}_\text{L}\left(t\right)=\text{L}\text{I}_\text{L}'\left(t\right)\tag1$$</span></p> <p>So, when:</p> <p><span class="math-container">$$\text{I}_\text{L}\left(t\right)=2\left(1-\exp\left(-\frac{t}{\text{T}}\right)\right)\tag2$$</span></p> <p>We get:</p> <p><span class="math-container">$$ \begin{alignat*}{1} \text{I}_\text{L}'\left(t\right)&amp;=\frac{\partial}{\partial t}\left(2\left(1-\exp\left(-\frac{t}{\text{T}}\right)\right)\right)\\ \\ &amp;=2\left(\frac{\partial}{\partial t}\left(1\right)-\frac{\partial}{\partial t}\left(\exp\left(-\frac{t}{\text{T}}\right)\right)\right)\\ \\ &amp;=2\left(\frac{\partial}{\partial t}\left(1\right)-\exp\left(-\frac{t}{\text{T}}\right)\cdot\frac{\partial}{\partial t}\left(-\frac{t}{\text{T}}\right)\right)\\ \\ &amp;=2\left(\frac{\partial}{\partial t}\left(1\right)+\frac{1}{\text{T}}\cdot\exp\left(-\frac{t}{\text{T}}\right)\cdot\frac{\text{d}}{\text{d}t}\left(t\right)\right)\\ \\ &amp;=2\left(0+\frac{1}{\text{T}}\cdot\exp\left(-\frac{t}{\text{T}}\right)\cdot1\right)\\ \\ &amp;=\frac{2}{\text{T}}\cdot\exp\left(-\frac{t}{\text{T}}\right) \end{alignat*} \tag3 $$</span></p> <p>So, we get:</p> <p><span class="math-container">$$\text{V}_\text{L}\left(3\cdot10^{-3}\right)=10\cdot10^{-3}\cdot\frac{2}{2\cdot10^{-3}}\cdot\exp\left(-\frac{3\cdot10^{-3}}{2\cdot10^{-3}}\right)=\frac{10}{\exp\left(\frac{3}{2}\right)}\approx2.2313\space\text{V}\tag4$$</span></p> <blockquote> <p>So, you're right!</p> </blockquote>

<p>I have a solution for the following exercise, but I'm not sure if it's a good one.</p> <p>This is the current time function of the inductance:</p> <p><span class="math-container">$$i(t) = 2-2e^{-t/T}\text{ (A)}$$</span> <span class="math-container">$$L = 10\text{ mH}$$</span> <span class="math-container">$$T = 2\text{ ms}$$</span></p> <p>Calculate the inductance voltage at <span class="math-container">\$t = 3\text{ ms}\$</span>.</p> <p>This is my solution:</p> <p><span class="math-container">$$UL = L \times \frac{di(t)}{dt}$$</span> <span class="math-container">$$UL(t) = 10\text{ mH}$$</span> <span class="math-container">$$UL(t) = 10 \times e^{-t/t}$$</span> <span class="math-container">$$UL(t=3\text{ ms}) = 10 \times e^{-3/2} = 2.23\text{ V}$$</span></p> <p>Is it right?</p>

Calculate the inductance voltage from its current time function

2024-01-24T15:42:08.953

698787

|sensor|

<p>If you exceed the sensor's current specification limit for an extended time, it will heat up and eventually fail.</p> <p>You can boost the siren current by using a transistor buffer. For example, a <a href="https://www.onsemi.com/pdf/datasheet/p2n2222a-d.pdf" rel="nofollow noreferrer">2N2222</a> is good for about 600mA.</p> <p>Such a setup would look like this (<a href="https://www.falstad.com/circuit/circuitjs.html?ctz=CQAgjCAMB0l3BWcMBMcUHYMGZIA4UA2ATmIxAUgpABZsKBTAWjDACgAXEXG8YlbggFh%20UcFGiEaGMHlyzIdYmAEwMNYpFzYEYbFkhlhcEABMGAMwCGAVwA2HNgHNBAtHlcgUKXlUhsAd08wDEJgml82WQgdYRVw3248PGg6PGJ0tFkaFHowExU-VIkaNgAlYPjYkDw-MRoqeLqYBDYAJ25FPjcEMJFVZDhOcFDwCK8fMcSWECYW7H4UBGwaBF6EPAwCWZhCDZowHPyRGkIUPUGzS1sHQIneMEIqbwfRfyDq1jdJr6g7l-A8QBKg8-g6hweowh9zElHgzimMOhPmad2h6PGITC-gAzoj0VDxnVrHYcQw2AAjQECWpebAeIiRAAeyA8hAZKxAMlo4AEAHkAA4cACWAGMrHYADo4skAOxxAHs2tKABQAWwV5jsAEo2Cz9MIMrRuVkeUCAHLebzSpXSnHCtXCuxWNr-XrdJFvNhAA" rel="nofollow noreferrer">simulate it here</a>):</p> <p><a href="https://i.stack.imgur.com/yhflg.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/yhflg.png" alt="enter image description here" /></a></p> <p>You could also use the sensor to activate a relay, assuming the relay coil current is low enough.</p>

<p>I'm just learning and looked at this circuit to implement. I have read the infrared sensor could be damaged by the larger current requirement of the light/siren without a relay. Is that true?</p> <p>If so, why doesn't the light/siren just not operate right due to the sensor only outputting 100 mA vs the need to have 300 mA to operate?</p> <p><a href="https://i.stack.imgur.com/jIBKD.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/jIBKD.png" alt="enter image description here" /></a></p>

Would this sensor get damaged without a relay?

2024-01-24T19:51:03.643

698791

|poe|certification|nrtl|

<p>It looks like a PD falls under 55022/ CISPR 22. I would be doing class A since its commercial.</p> <blockquote> <p>The PD must comply with EMC standards, such as that defined by EN 55022 / CISPR 22, in order to be sold in many markets. The EN 55022 / CISPR 22 standard establishes limits for both conducted emissions and radiated emissions. The limits are defined for Class A (commercial) and Class B (residential) equipment, with Class B being the more stringent. The conducted emissions generated by a PD, which is considered to be a telecommunication port, are measured as common-mode disturbances on the CAT-5 cable. The radiated emissions associated with a PD can be in the form of emissions radiating from the CAT-5 cable as a result of the PD’s conducted common-mode noise (i.e. antenna mode disturbances), or emissions that radiate directly from the PD itself.</p> </blockquote> <p>Source: <a href="https://www.ti.com/lit/an/slua454/slua454.pdf?ts=1706213102228&amp;ref_url=https%253A%252F%252Fwww.google.com%252F" rel="nofollow noreferrer">https://www.ti.com/lit/an/slua454/slua454.pdf?ts=1706213102228&amp;ref_url=https%253A%252F%252Fwww.google.com%252F</a></p>

<p>For IoT devices with a Powered Device (PD) for Power Over Ethernet (POE) and not plugged into AC mains; What, if any, standards would a device potentially be subject to at an Nationally Recognized Testing Lab (NRTL)?</p> <p>Are there also any conducted emissions standards for 802.3af or 802.3at certification?</p>

Conducted emissions testing for POE 802.3 device?

2024-01-24T20:00:57.317

698792

|circuit-analysis|resistors|

<p>For a current to flow you would need two <em>independant</em> nodes between the left and right. The right side only connects to the left at node B. They may have drawn it to look like there are two nodes, but the connections from the right are in fact both to node B, so only one node is connected.</p> <p>Note that I use the word <em><a href="https://en.wikipedia.org/wiki/Node_(circuits)" rel="nofollow noreferrer">node</a></em>. In a schematic a node is a part of the circuit where two or more circuit elements connect, and it is assumed that this connection has zero resistance. It is considered to act as a single point even though it is drawn as lines between the components. So node B includes all of the lines connected to where it says B, up to where they attach to a component.</p> <p>Here I have highlighted node B, all of the red is considered to be at the same voltage potential, and all of the currents entering and leaving it will sum to zero. <a href="https://i.stack.imgur.com/aoqoa.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/aoqoa.png" alt="enter image description here" /></a></p> <p>So as you can see, current coming from node B can't flow around to A and through the 500<span class="math-container">\$\Omega\$</span> resistor back to B. For any current to flow, some part of the right side that's not connected to node B would need to connect to some part of the left side other than node B.</p> <p>That is why I said in the previous question that the right side of the circuit is irrelevant to the voltage from A to B.</p>

<p>A follow-up this post regarding the following circtuit:</p> <p><a href="https://i.stack.imgur.com/hQ8a8.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/hQ8a8.png" alt="enter image description here" /></a></p> <hr /> <p>I continue to struggle to understand why the right half of the circuit is irrelevant when computing the voltage between <span class="math-container">\$A\$</span> and <span class="math-container">\$B\$</span>. One answer to the previous post reads</p> <blockquote> <p>The <span class="math-container">\$500Ω\$</span> resistor is not short-circuited, but there's effectively only one connection from the left half of the circuit to the right, so the current source and the <span class="math-container">\$28V\$</span> voltage source can have no effect on the voltage from <span class="math-container">\$A\$</span> to <span class="math-container">\$B\$</span>.</p> </blockquote> <ul> <li>Aren't there <em>two</em> connections from the left half to the right?</li> </ul> <p><a href="https://i.stack.imgur.com/tSjuL.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/tSjuL.png" alt="enter image description here" /></a></p> <ul> <li>Even if there is only one connection, why does that imply the sources in the right half of the circuit cannot have an effect on the voltage from <span class="math-container">\$A\$</span> to <span class="math-container">\$B\$</span>?</li> </ul> <p>Another answer reads</p> <blockquote> <p>The right half of the circuit only connects to node <span class="math-container">\$B\$</span>, there is no path for any current from the <span class="math-container">\$28 V\$</span> or <span class="math-container">\$10 mA\$</span> sources to flow to node <span class="math-container">\$A\$</span>, so that whole part of the circuit is irrelevant to the voltage from <span class="math-container">\$A\$</span> to <span class="math-container">\$B\$</span>.</p> </blockquote> <ul> <li>It seems to me the right half connects to <span class="math-container">\$A\$</span>:</li> </ul> <p><a href="https://i.stack.imgur.com/0Mr87.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/0Mr87.png" alt="enter image description here" /></a></p>

Why is the right half of the circuit irrelevant?

2024-01-24T20:23:38.213

698796

|circuit-analysis|diodes|

<p>For charge to flow there must be a closed path around the voltage source V1. If V1 is negative D1 is reversed biased so can be removed for the sake of analysis. So the circuit can be redrawn as in Figure 1.</p> <p>For charge to flow in the lower circuit, there must be a closd path from node A through V1, through the lower circuit to node B, then return to node A through an additional path, which does not exist.</p> <p>Rx in Figure 2 is an example of an additional path from node B back to node A, <strong>closing the circuit</strong>.</p> <p>In figure 1 Rx is infinite, thus <strong>opening the circuit</strong>, so there is no current in any of the elements in the lower circuit, making them irrelevent to circuit operation when V1 is negative.</p> <blockquote> <p>...according to the teacher, the bottom half of the circuit is short-circuited...</p> </blockquote> <p>The circuit is not shorted, but open.</p> <p><img src="https://i.stack.imgur.com/FJmxT.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fFJmxT.png">simulate this circuit</a> &ndash; Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a>}</p>

<p>A follow up to <a href="https://electronics.stackexchange.com/questions/698536/understanding-a-short-solution-to-a-diode-exercise">this post</a>, regarding this circuit:</p> <p><a href="https://i.stack.imgur.com/Z68j4.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/Z68j4.png" alt="enter image description here" /></a></p> <p>Below <span class="math-container">\$V_1\$</span> applies a rectangular wave of amplitude <span class="math-container">\$24V\$</span>. For this post I'm only concerned in the case <span class="math-container">\$V_1 = -24V\$</span>. In that case, according to the teacher, the bottom half of the circuit is short-circuited i.e. need not be taken into account. <strong>Why is this the case?</strong></p>

Why is the bottom half of the circuit shortcircuited?

2024-01-24T21:15:38.463

698799

|power|inverter|watts|time|

<p>Generally, a 12 volt 100Ah battery has an equivalent watt-hour rating of 12 x 100 i.e. 1200 watt-hours (Wh). So, if your load needs 750 watts then the battery will typically be able to supply that power for 1 hour and 36 minutes.</p> <p>However, there is not much info about the battery and, it may droop its terminal voltage both under load and, over time so, I wouldn't bet on getting anything more than 1 hour from the battery.</p>

<p>I want to buy a 12v 100ah lithium battery to power a 750 watts power converter that provides 120V.</p> <p>I would like to know how many hours of energy will I have with this information. I tried some online calculators, but it's not clear if I'm doing it right.</p> <p>Why?</p> <p>Well, the 750 watts is related to the 120V part of the power converter, so I don't know how to calculate on the 12V part of the battery.</p>

How to properly calculate the run time of a battery using a power converter?

2024-01-24T21:19:15.113

698814

|emc|cables|emissions|emc-filtering|

<p>Ended up making a 40 pin cable based off of the molex drawing at pcbway and it worked really well! It cut 5-10dB off each spike, so it was for sure the cable.</p> <p>Also added 10 ohm resistors in series, have to wait to see if that worked as it's a cheaper option.</p>

<p>I have a 40 pin FFC cable that looks like this between 2 PCB's:</p> <p><a href="https://i.stack.imgur.com/NdUvFs.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/NdUvFs.jpg" alt="enter image description here" /></a><br /> <a href="https://www.digikey.com/en/products/detail/molex/0151660427/3281308" rel="nofollow noreferrer">https://www.digikey.com/en/products/detail/molex/0151660427/3281308</a></p> <p><a href="https://i.stack.imgur.com/PPTyb.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/PPTyb.png" alt="enter image description here" /></a></p> <p>The problem is I'm getting radiated emissions from mostly the cable.</p> <p><a href="https://i.stack.imgur.com/9NWrE.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/9NWrE.png" alt="enter image description here" /></a></p> <p>I'm thinking that shorting - at minimum - the power rails on the cable (there are three) to ground would stop most of the high frequency emissions on the cable. The cable does have interleaved grounds every 4 conductors.</p> <p><a href="https://i.stack.imgur.com/iu4X4.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/iu4X4.png" alt="enter image description here" /></a></p> <p>There are no comm lines operating above 50MHz So I need to short out all frequencies above - say - 70MHz.</p> <p>I am wondering if anyone has had a similar experience. What is a good way to short out the high frequency rails to ground? Would a simple 0.1uF cap work? Do I need low ESL caps?</p> <p>More on the digital. There are 2 I2C lines 2 PWM lines, and I2S and UART and SPI bus, none operate more than 30MHz. All go to a processor that operates at 1GHz. I also don't see these frequencies with PCB1 detached and the cable hanging or any radiation in those frequencies when I look at PCB2.</p>

Conducted/Radiated emissions through 40-pin FFC cable

2024-01-24T23:52:24.680

698818

|impedance|transmission-line|characteristic-impedance|

<h2>Not a transmission line</h2> <p>This is actually an antenna, or an air coupled coil. The aim of this structure is to maximize the transfer of energy through the air. Changing the shape of the coil will also change its characteristics.</p> <h2>Why 50ohms</h2> <p>If you design your antenna such it shows a 50ohm impedance to the circuit when coupled to the air, then you would have the most efficient emission and reception possible through that chain. This is called impedance matching and is required when dealing with RF signals. Of course, the impedance of the antenna will depend on the signal frequency, the PCB substrate used, the thickness of the traces etc...</p> <h2>Transmission line</h2> <p>The purpose of a Transmission Line is the exact opposite. It must contain the impact it has on the field within itself. It minimizes transmission of energy from the signal to the air and from the air to the signal by minimizing the distance between the signal and the return path. In the case of a flexible transmission line, as long as the coiling is not absurdly small in diameter, the impedance won't change that much because the current path stays more or less the same.</p> <h2>Some resources:</h2> <p>I can recommend this video from Zack Star. He explain most of this is a very nice way for an introduction. <a href="https://www.youtube.com/watch?v=pXWbdxOAuDs" rel="nofollow noreferrer">https://www.youtube.com/watch?v=pXWbdxOAuDs</a></p>

<p>If I take an advertised 50 ohm impedance cable and turn it into a coil will this change its characteristic impedance from 50 ohm to something else? My intuition tells me it should as if we look at one section of the coil the inductance per unit length should be higher as we still have the wires self inductance but the magnetic field produced now interacts with the neighbouring wires and induces a current in them which resists the initial current which sounds like the inductance per unit length would be higher which would increase the characteristic impedance. Is this correct?</p> <p>EDIT: For context I'm working on an RFID project which has an coil design similar to this <a href="https://i.stack.imgur.com/b81c9.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/b81c9.png" alt="enter image description here" /></a></p> <p>Essentially I'm wondering if I set my trace impedance to 50 ohm and make this coil will the characteristic impedance of the trace be altered?</p>

Does coiling a transmission line affect its characteristic impedance?

2024-01-25T02:07:10.910

698820

|noise|troubleshooting|transducer|floating|

<p>This will be fine.</p> <p>The inductive pickup of noise from the pickup that is connected with only one wire will be entirely prevented. Its extremely large series resistance (of the open switch) prevents any signal contribution.</p> <p>It will pickup a slight bit of electric field noise as will any dangling conductor that is connected to your circuit, such as the bridge, the strings, even yourself. But this noise is <em>common-mode</em> noise. As opposed to a differential signal between the two poles of your guitar cable, the common-mode noise is usually not amplified, so it doesn't matter either.</p> <p>Another intuitive way, you can see why this will be fine is the following: With a standard pickup selector, the unselected pickup is still connected with one side to the &quot;ground&quot; node of the guitar circuit, but doesn't contribute noise. Since the guitar output is a differentiel voltage between its two output poles, anything dangling on the &quot;ground&quot; pole is no better or worse than dangling on the &quot;signal&quot; pole.</p>

<p>I want to wire my guitar using two SPDT switches for my pickup selector. This is so I can have four sounds: lower, upper, both in parallel, both in series. I'm concerned that when it's set to use just the lower pickup (as shown in the schematic) that it will cause some noise/hum to be added to the output signal since the upper pickup still has one wire connected to the output jack with the other wire left floating. If this does add noise, will it help much if I keep the wires from the upper pickup very short (an inch or so)?</p> <p><a href="https://i.stack.imgur.com/HHDNg.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/HHDNg.jpg" alt="guitar wiring set to use only the lower pickup" /></a></p>

Will this electric guitar wiring scheme be noisy?

2024-01-25T02:45:42.877

698824

|y-to-delta|

<h3>direct answers</h3> <blockquote> <p>Can someone check my work and let me know of any errors?</p> </blockquote> <p>I think your equations are fine. I don't see any errors.</p> <blockquote> <p>let me know if there's any better way to format this.</p> </blockquote> <p>I think whatever works for you is better. I don't see any obvious choice, one way or another. Some will prefer one, others another.</p> <blockquote> <p>I'm trying to find a more intuitive equation for wye to delta formations</p> </blockquote> <p>I can't say what's more intuitive for you. And if this is just a question about which algebraic form &quot;looks better&quot; then I'm stuck there. But there is <a href="https://spinningnumbers.org/a/delta-wye-derivations.html" rel="nofollow noreferrer">this page</a> that you might skim.</p> <p>I can add these thoughts:</p> <h3><span class="math-container">\$\Delta\$</span> and <strong>Y</strong> KCL</h3> <p>Here's your diagram with <span class="math-container">\$N_{_\text{Y}}\$</span> and a few currents added to it:</p> <p><a href="https://i.stack.imgur.com/Pxjod.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/Pxjod.png" alt="enter image description here" /></a></p> <p>In the following, I'll be using conductances for everything. So <span class="math-container">\$G_1=\frac1{R_1}\$</span>, etc.)</p> <p>From KCL we can make the following initial observation about the <strong>Y</strong>:</p> <p><span class="math-container">$$\begin{align*} V_{_\text{Y}}\cdot G_1+V_{_\text{Y}}\cdot G_2+V_{_\text{Y}}\cdot G_3 &amp;=V_1\cdot G_1+V_2\cdot G_2+V_3\cdot G_3 \\\\ \therefore\quad V_{_\text{Y}}&amp;=\frac{V_1\cdot G_1+V_2\cdot G_2+V_3\cdot G_3}{G_1+ G_2+G_3} \end{align*}$$</span></p> <p>The net node currents given in the above diagram for each configuration is:</p> <p><span class="math-container">$$\begin{array}{lcccc} &amp;\textbf{Y}&amp;&amp;&amp;\Delta\\\\ I_1:&amp;\left(V_1-V_{_\text{Y}}\right)\cdot G_1 &amp;&amp;&amp; \left(V_1-V_3\right)\cdot G_{_\text{B}}+\left(V_1-V_2\right)\cdot G_{_\text{C}} \\\\ I_2:&amp;\left(V_2-V_{_\text{Y}}\right)\cdot G_2 &amp;&amp;&amp; \left(V_2-V_1\right)\cdot G_{_\text{C}}+\left(V_2-V_3\right)\cdot G_{_\text{A}} \\\\ I_3:&amp;\left(V_3-V_{_\text{Y}}\right)\cdot G_3 &amp;&amp;&amp; \left(V_3-V_2\right)\cdot G_{_\text{A}}+\left(V_3-V_1\right)\cdot G_{_\text{B}} \end{array}$$</span></p> <p>But <span class="math-container">\$V_{_\text{Y}}\$</span> can be expanded and then the above can be re-arranged as follows:</p> <p><span class="math-container">$$\begin{array}{lcccc} &amp;\textbf{Y}&amp;&amp;&amp;\Delta\\\\ I_1:&amp;\frac{\left(V_1\,\left[G_2+G_3\right]-V_2\:G_2-V_3\:G_3\right)\, G_1}{G_1+G_2+G_3} &amp;&amp;&amp; V_1\cdot\left(G_{_\text{B}}+G_{_\text{C}}\right)-V_2\cdot G_{_\text{C}}-V_3\cdot G_{_\text{B}} \\\\ I_2:&amp;\frac{\left(V_2\,\left[G_3+G_1\right]-V_3\:G_3-V_1\:G_1\right)\, G_2}{G_1+G_2+G_3} &amp;&amp;&amp; V_2\cdot\left(G_{_\text{C}}+G_{_\text{A}}\right)-V_3\cdot G_{_\text{A}}-V_1\cdot G_{_\text{C}} \\\\ I_3:&amp;\frac{\left(V_3\,\left[G_1+G_2\right]-V_1\:G_1-V_2\:G_2\right)\, G_3}{G_1+G_2+G_3} &amp;&amp;&amp; V_3\cdot\left(G_{_\text{A}}+G_{_\text{B}}\right)-V_1\cdot G_{_\text{B}}-V_2\cdot G_{_\text{A}} \end{array}$$</span></p> <p>You can now directly compare the left and right columns. By inspection, the following <em><strong>must</strong></em> be true:</p> <p><span class="math-container">$$\begin{align*} G_{_\text{A}}&amp;=\frac{G_2\,G_3}{G_1+G_2+G_3} \\\\ G_{_\text{B}}&amp;=\frac{G_3\,G_1}{G_1+G_2+G_3} \\\\ G_{_\text{C}}&amp;=\frac{G_1\,G_2}{G_1+G_2+G_3} \end{align*}$$</span></p> <h3>expanding the topic further</h3> <p>There's a really nice selection of historical papers on the topic, from a modern 2022 perspective, that can be found in the first few paragraphs of <a href="https://arxiv.org/pdf/2110.07764.pdf" rel="nofollow noreferrer"><em>A degree preserving delta wye transformation with applications to 6-regular graphs and Feynman periods</em>, by Shannon Jeffries and Karen Yeats, July 29, 2022</a>. I recommend at least skimming the first page there just to get a good list of relevant literature on the topic. (And Karen is the contacting author, if you've a mind for that.)</p> <p>They cite perhaps the earliest paper on the topic as <a href="http://www.infinitefactors.org/docs/1899,%20Kennelly,%20The%20Equivalence%20of%20Triangles%20and%20Three-Pointed%20Stars%20in%20Conducting%20Networks.pdf" rel="nofollow noreferrer"><em>&quot;Equivalence of triangles and three-pointed stars in conducting networks,&quot;</em> <strong>Electrical World and Engineer</strong>, 34:413–414, 1899 by A. E. Kennelly</a>. (I just obtained a public domain copy.)</p> <p>Another important paper is <em>&quot;Polyeder und Raumeinteilungen&quot;</em>, <strong>Enzyklopadie der mathematischen Wissenschaften mit Einschluss ihrer Anwendungen</strong>, 1916 by E. Steinitz.</p> <p>The above authors are, of course, no longer with us.</p> <p>Perhaps one of the better living experts on this topic would be Isidoro Gitler. I think he is currently at the <em>&quot;Center for Research and Advanced Studies of the National Polytechnic Institute&quot;.</em> His doctoral thesis, at the University of Waterloo in 1991, was <em>&quot;Delta-Wye-Delta Transformations: Algorithms and Applications.&quot;</em> He then published <a href="https://core.ac.uk/download/pdf/81174967.pdf" rel="nofollow noreferrer"><em>&quot;On topological spin models and generalized ∆–Y transformations&quot;</em></a> in 2002, followed by <a href="https://www.math.cinvestav.mx/sites/default/files/3termArizona2008-5.pdf" rel="nofollow noreferrer"><em>&quot;On terminal delta-wye reducibility of planar graphs&quot;</em></a>, 2011.</p> <p>If you are looking for important insights, I'd strongly recommend making contact. Your questions would be squarely and directly related to his work and publications. I expect you'd get a favorable response to queries.</p>

<p>I'm trying to find a more intuitive equation for wye to delta formations (going from delta to wye, the traditional equations make sense to me). I came up with the following solution, but I'm not 100% this is useable. Can someone check my work and let me know of any errors?</p> <p>Side quest: let me know if there's any better way to format this.</p> <p>Starting from the wye to delta equations:</p> <p><span class="math-container">$$R_1 R_a= R_1 R_2 + R_2 R_3 + R_1 R_3$$</span></p> <p><span class="math-container">$$R_2 R_b= R_1 R_2 + R_2 R_3 + R_1 R_3$$</span></p> <p><span class="math-container">$$R_3 R_c= R_1 R_2 + R_2 R_3 + R_1 R_3$$</span></p> <p>Using the first equation for this example:</p> <p>gives <span class="math-container">$$R_a = (R_1 R_2 + R_2 R_3 + R_1 R_3)/R_1$$</span> <span class="math-container">$$ = (R_1 R_2/R_1 + R_2 R_3/R_1 + R_1 R_3/R_1)$$</span></p> <p><span class="math-container">$$ = (R_1 R_2R_3/R_1R_3 + R_2 R_3R_1/R_1R_1 + R_1 R_3R_2/R_1R_2)$$</span></p> <p><span class="math-container">$$ = R_1R_2R_3/R_1 * (1/R_3 +1/R_1+1/R_2)$$</span> <span class="math-container">$$R_a= R_2R_3 * (1/R_3 +1/R_1+1/R_2)$$</span></p> <p>Using the following labeling (diagram from <a href="https://www.youtube.com/watch?v=biomymZbK-U" rel="nofollow noreferrer">https://www.youtube.com/watch?v=biomymZbK-U</a>): <a href="https://i.stack.imgur.com/IOFDe.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/IOFDe.png" alt="enter image description here" /></a></p>

Wye to delta transformation

2024-01-25T04:16:05.860

698833

|three-phase|single-phase|power-meter|

<blockquote> <p><em>How does a three-phase power meter (for example the one used by my power company) know the difference between a single three-phase load and multiple single-phase loads?</em></p> </blockquote> <p>A properly designed power meter doesn't care whether the incoming supply is 3-phase or, whether there is a balanced 3-phase load on the output or, only a single phase load on the output. It won't even care (within reason) if the voltage supply is significantly non-sinusoidal either.</p> <blockquote> <p><em>What am I missing here?</em></p> </blockquote> <p>It calculates power delivered to the load from the supply irrespective of what I have mentioned above mentioned above.</p>

<p>How does a three-phase power meter (for example the one used by my power company) know the difference between a single three-phase load and multiple single-phase loads?</p> <p>For example: a three-phase heater at 4 kW (400 V * 10 A) vs three single phase heaters also totaling 10 A (230 V * 3.333333… A * 3 = 2.3 kW).</p> <p>What am I missing here?</p>

How does a power meter differentiate between three-phase and single-phase loads?

2024-01-25T06:38:49.967

698843

|transformer|audio|

<p>&quot;To my knowledge, transformers only have an impedance ratio which is the square of the turns ratio.&quot; Only in textbooks. Real transformers are complicated beasts. Magnetizing and leakage inductance, capacitance, resistance, eddy currents, hysteresis, ...</p> <p>Real transformers are usually engineered to behave approximately like textbook transformers in their intended application. Part of this is designing for a specific impedance. Operation at a different impedance will impact other characteristics like frequency response and power handling capability.</p>

<p>For context I've looked at DI boxes for audio applications. Passively operated ones use a transformer to step a source voltage down as well as provide an <a href="https://en.wikipedia.org/wiki/Impedance_bridging" rel="nofollow noreferrer">impedance bridge</a> for a potentially high-impedance source to a low-impedance input for maximum voltage transfer efficiency - desirable in audio applications. A bridging impedance is Z_load &gt;&gt; Z_source, usually a ratio of 10 or so.</p> <p>The DI circuits are basically equivalent to only a transformer (see the &quot;block diagram&quot; section <a href="https://www.radialeng.com/product/jdi/specifications" rel="nofollow noreferrer">here</a> and below). However, products in this space often report input and output impedances. One reports 140 kOhm in and 150 Ohm out for a 1 kHz signal, with a turns ratio of 11.5 (see the transformer specs <a href="https://www.jensen-transformers.com/wp-content/uploads/2014/08/jt-db-e.pdf" rel="nofollow noreferrer">here</a> and below).</p> <p><a href="https://i.stack.imgur.com/91Gd8.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/91Gd8.png" alt="DI block diagram" /></a> <a href="https://i.stack.imgur.com/F28Or.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/F28Or.png" alt="transformer specs" /></a> <a href="https://i.stack.imgur.com/fa4ll.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/fa4ll.png" alt="test circuit" /></a></p> <p>To my knowledge, transformers only have an impedance <em>ratio</em> which is the square of the turns ratio. So in a <a href="https://en.wikipedia.org/wiki/Impedance_bridging" rel="nofollow noreferrer">voltage divider</a>, a transformer would only shift the apparent impedance of the load, unlike say when using an active <a href="https://en.wikipedia.org/wiki/Buffer_amplifier" rel="nofollow noreferrer">buffer amplifier</a> that has set input and output impedances. But then the ratio of the reported impedances of the transformer (140k / 150 = 930), does not match the square of the turns ratio either (130).</p> <p>Here is a simple schematic of the system:</p> <p><img src="https://i.stack.imgur.com/Qfm3G.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fQfm3G.png">simulate this circuit</a> &ndash; Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a>}</p> <p>So above, the load impedance of 1 kOhm would ideally present as 100 kOhm to the source, providing a bridging impedance.</p> <p>Is there something else at play or have I misunderstood the issue? Is it only a matter of marketing and the transformer not being ideal? Thank you.</p>

Why are a transformer's high and low impedance reported directly?

2024-01-25T08:10:28.143

698854

|power-supply|pcb-design|power-electronics|switch-mode-power-supply|buck|

<p>It looks good to me.</p> <p>My observations are:</p> <ol> <li>LX1 and L140 ought to be connected in series.</li> <li>Keep in mind that ceramic output caps are required.</li> </ol>

<p>I am using a <a href="https://www.analog.com/media/en/technical-documentation/data-sheets/MAX20029-MAX20029D.pdf" rel="nofollow noreferrer">MAX20029ATIAV</a> in my design for powering a <a href="https://www.analog.com/media/en/technical-documentation/data-sheets/max96724.pdf" rel="nofollow noreferrer">Quad Tunneling GMSL2/1 to CSI-2 Deserializer</a>.</p> <p>MAX20029ATIAV is Quad Low-Voltage Step-Down DC-DC Converters.</p> <p>My schematic is given below. May I know your valuable suggestions/comments?</p> <p><a href="https://i.stack.imgur.com/X3Zzm.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/X3Zzm.png" alt="enter image description here" /></a></p> <p><a href="https://i.stack.imgur.com/lf8mw.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/lf8mw.png" alt="enter image description here" /></a></p> <p><a href="https://i.stack.imgur.com/c4Lmq.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/c4Lmq.png" alt="enter image description here" /></a></p>

Schematic review MAX20029ATIAV

2024-01-25T09:28:57.873

698856

|circuit-design|pcb-design|analog|low-power|power-consumption|

<p>It sounds like the main current draw is the op-amp. <a href="https://www.analog.com/media/en/technical-documentation/data-sheets/ad8605_8606_8608.pdf" rel="nofollow noreferrer">AD8608</a> advertises ~1mA/amp or 4mA total here. With a 10MHz GBW product, this will give rapid settling for the 300kS/s advertised in the original circuit, but with a sample rate at most a few per second, this is entirely wasted power for you. It's a poor choice.</p> <p>There are precision micropower op-amps available; <a href="http://ww1.microchip.com/downloads/en/DeviceDoc/MCP6V16-Family-Data-Sheet-DS20006204A.pdf" rel="nofollow noreferrer">MCP6V19-E/ST</a> seems quite viable here.</p> <p>A faster amp can also be switched on for a reading; you would need an additional digital input to convey this (or at least a pulse detector on SPI, and you discard the first sample then quickly resample, and then it turns itself off after a time delay). Suitable types need to not load the input, else parasite power is drawn through the REF pin if nothing else; or VREF could be switched with an analog switch (e.g. 74HC1G66). Supply could then be switched with a PMOS (BSS84?) or other load switch.</p> <p>Incidentally, I'm not seeing many op-amps rated for non-loading inputs like this; ironically MCP6V19 is one of the exceptions, but its consumption is low enough to perhaps not need it, already. (Pay attention to the input ESD, protection and limiting section in the datasheet. My interpretation is, it can be overvolted gently, powered up or not, so will tolerate a supply switching scheme; but it may be there are other limitations they don't document which show up in such an operating mode. Or if it might be more vulnerable in such a state.)</p> <p>In any case, that seems a possibility to reap more savings in your application, should you need it. Next, the ADC would be pulled into question, and I would suggest a sigma-delta type which is available in low sample rates, potentially higher bit depth if that should be desirable, and lower clock rates and current consumption, while being relatively immune to input noise between sample and clock rates (due to its integrating design) so that input filtering requirements can be relaxed a bit.</p> <p>Pay attention to filtering the inputs; with an analog bandwidth of some 10s kHz for this op-amp type, expect errors to show up for any signals outside that bandwidth: asymmetrical slewing and input rectification can turn higher frequencies into DC offsets, and madness ensues. An RC filter of some Hz cutoff frequency would seem more than sufficient here. (You probably want to avoid type 2 dielectric ceramics, as they are nonlinear, hysteretic and microphonic. Electrolytic aren't very stable (esp. varies with temperature), and may prove leaky. Film would be ideal, but you may also find this is a suitable application for tantalum.)</p> <p>Without adding more op-amps (and of adequate GBW to handle the less-filtered or unfiltered inputs), I suppose active filters are out of the question, so a 1st or 2nd order RC filter with a cutoff somewhat above what you need, will have to do. This forces settling time to be rather slow, as you can't speed up the transfer function with the presence of complex poles.</p> <p>Speaking of input rectification, note that the diode shown, while it does ensure specified current flow direction, it is also susceptible to RF interference. As long as the developed DC offset is absorbed by the current loop, this can be fine (within compliance range; which is most likely more than enough until ludicrous RF input, but, maybe it's not, you'd have to check), but there will be transient error as the interference keys on/off; this would be more of a problem for the original (higher bandwidth) circuit than here, but more to the point, we can avoid this concern entirely by merely filtering the input at the connector. A ferrite bead and couple nF capacitor will most likely suffice.</p>

<p>I've been facing some issues with my analog readings. The problem has been somewhat resolved using the following circuit design:</p> <p><a href="https://i.stack.imgur.com/t02vp.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/t02vp.png" alt="enter image description here" /></a></p> <p>You can find more information about the circuit's 'function and its benefits' <a href="https://www.analog.com/en/design-center/reference-designs/circuits-from-the-lab/cn0336.html#rd-functionbenefits" rel="nofollow noreferrer">here</a>.</p> <p>However, a new challenge has emerged – the circuit is consuming too much current. I aim to power it with a battery charged by a small solar panel.</p> <p>I noticed this information a little late:</p> <blockquote> <p><em>Power dissipation is only 9.2 mW on a 3.3 V supply.</em></p> </blockquote> <p>This aligns with my measurements, which indicate around 5.5 mA since there are two analog channels. This consumption is approximately ten times higher than the rest of the board.</p> <p>What measures can I take to reduce power consumption?<br></p> <p>Here are the circuits I have:</p> <p><a href="https://i.stack.imgur.com/obltn.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/obltn.png" alt="enter image description here" /></a></p> <p><a href="https://i.stack.imgur.com/Ypt0f.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/Ypt0f.png" alt="enter image description here" /></a></p> <p><strong>Edit</strong><br> Is there alternative circuit designs that can be used that could bring down power consumption or any other ideas/suggestions?</p> <p>I'll be on vacation so I won't check in for a while.</p>

Optimizing power efficiency: Troubleshooting high power consumption in analog reading circuit

2024-01-25T09:57:05.630

698877

|batteries|buck|boost|

<p>This is not a simple thing to be answered in a few sentences. Different things should be considered together such as failure modes, environmental conditions, cost, etc. I'll try to cover only a limited section of these.</p> <p>Whether you go for a buck or a boost, the complexity, overall efficiency, and material cost will be pretty much the same for both.</p> <p>Lower battery voltage and boost converter require thicker input wires, but higher battery voltage and buck converter require good interconnection of the batteries/cells. This will make you consider the overall build of the system. And, for now, we can assume the power loss at input section to be equal for both buck and boost.</p> <p>Practically speaking, 10 Amps is not a low number for an output current. It's high enough to give you headache due to the losses and heat.</p> <p>If you go for a boost converter with, say, 12V battery voltage, the rectifier diode will be in conduction for almost 80% of a switching cycle (assuming CCM). This means that the diode dissipation will be substantial. You can go for a synchronous boost converter and replace the rectifier with a MOSFET but it's not a common thing these days. So you can select a higher battery voltage and go for a synchronous buck instead.</p> <p>You should also consider the potential failures:</p> <ul> <li>In a boost converter if the switch fails first it'll short the battery. But if the rectifier diode fails first your load will see the input voltage, 12V.</li> <li>In a sync buck converter, if the top switch fails first the load will see the full input voltage, presumably 24V. But if the bottom switch fails first the battery will be shorted.</li> </ul> <p>There are also other possible failure modes. If you want to deep dive into the details google &quot;FMEA&quot;.</p> <ul> <li>Consider the potential danger of the load being exposed to higher or lower voltage.</li> <li>Do a rough calculation/estimation of the losses and cooling of the critical components, and take the complexity and implementation difficulties along with cost and availability, and decide which is acceptable for you. Since there's no such thing as &quot;best&quot; in engineering, it is not to make the best but it's to make the &quot;good enough&quot;.</li> </ul> <p>PS: Personally, I'd start with a synchronous buck.</p>

<p>I have a system with a battery. I do not know what will be the battery at the moment. And so I can select the voltage battery in function of my system. I need to regulate a voltage (15 V) thanks to a converter. The output current will be around 10 A, i.e 150 W.</p> <p>The question is it better to use a boost converter or a buck converter for doing the job as I can choose the voltage level of the battery? Also I think that If the voltage level of the battery increase, it will also increase the output impedance of the battery as more cell will be put in series and so when some current will be drawn by the load, the voltage of the battery will be lower. Also I think that the battery will have a lower energy density if I increase the voltage than if I took a battery with a lower voltage. So I think that it will be better to use a boost converter. But as I do not know really much battery, I would appreciate to have your opinions.</p> <p>I put away the non inverting buck boost topologies as it would be less efficient.</p>

Battery consideration and topology choice

2024-01-25T12:56:27.350

698930

|identification|intel|

<p>It will probably at at least appear to function perfectly without the capacitor. Bypass capacitors are not an exact science and having more is like insurance.</p> <p>If you feel like gambling a bit though, you can find the largest value 6.3V X5R capacitor that will fit that footprint (and is stocked in volume) and plunk it down.</p>

<p>How can I find out what the value of the capacitor shown in the photo is on an Intel Core i5-4690 processor?</p> <p><a href="https://i.stack.imgur.com/GOBpj.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/GOBpj.jpg" alt="enter image description here" /></a></p>

How can I find out what the value of the capacitor on an Intel Core i5-4690 processor?

2024-01-25T19:44:44.560

698939

|transistors|switches|esp32|gpio|npn|

<p>There's a few options for the pushbutton. You could simply parallel the C-E of the transistor with your pushbutton. <strong>Especially in this case, the TVS (ESD protection device) shown is highly recommended</strong> since ESD could work its way from the finger to the switch to the input.</p> <p>If you make the pushbutton drive the transistor you could also do this:</p> <p><img src="https://i.stack.imgur.com/aXydP.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2faXydP.png">simulate this circuit</a> &ndash; Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a>}</p> <p><a href="https://i.stack.imgur.com/DN4bE.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/DN4bE.png" alt="enter image description here" /></a></p> <p>The 47kΩ resistor deals with any leakage in case the input is left open (for example if the ESP is unplugged or in a state where the GPIO is high-Z). It will probably work okay with it removed.</p>

<p>I need some help regarding a small circuit that I'm currently working on. I have a microcontroller (ESP32) that I want to use to control a chip with a GPIO pin of my ESP32 as output, and at the same time, I want to be able to also use a physical push button to do the same job.</p> <p>The chip is a RF module with a power on/off pin. When this pin is held low (sub 1.5 V) for 1 sec the module boots (or reboots). Otherwise it's internally pulled high to 1.8 V during normal operation.</p> <p><a href="https://www.texim-europe.com/Cmsfile/SMM-SIM7080G-Hardware-Design-V1.04-DS-200525-TE.pdf" rel="nofollow noreferrer">datasheet</a></p> <p>The datasheet suggests to use a NPN transistor for this purpose following this figure:</p> <p><a href="https://i.stack.imgur.com/j64JV.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/j64JV.png" alt="enter image description here" /></a></p> <p>I used Falstad circuit simulator (first time using it) to try to design a good circuit but I have to admit that I'm struggling. I came up with this circuit. It seems to work fine without the push button, the RF pin goes high when ESP pin is low and goes low when ESP pin is high.</p> <p><a href="https://i.stack.imgur.com/17caT.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/17caT.png" alt="enter image description here" /></a></p> <p>However, I would like this push button to also reboot the RF module. And I don't know how and where to place it. I tried to connect the base with the emitter and the collector like this and now the RF pin follows ESP pin (RF high when ESP high and low when low) but now of course it's as if I didn't have a transistor. Moreover, the voltage is now 3.3 V at the RF pin and I think it might damage the RF module given that its internal voltage is 1.8 V. What's the best and simple way to deal with this? Just for info, I will be using this transistor:</p> <p><a href="https://www.mouser.fr/datasheet/2/258/MMBT2222A_SOT_23_-2510672.pdf" rel="nofollow noreferrer">Datasheet</a></p> <p><a href="https://i.stack.imgur.com/bD5gD.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/bD5gD.png" alt="enter image description here" /></a></p> <p>Another question: What's the purpose of the 47 k resistor? It doesn't change anything when I remove it and the simulator says that it's a bad connection. I don't understand.</p>

Control chip with a GPIO pin using a transistor and a push button switch

2024-01-25T20:40:01.793

698946

|system-verilog|uvm|

<p>Limit the use of parameters to places that require constant expressions. In this case, there is no need to make IF_PATH a <code>parameter</code>; it can be a <code>string</code> variable.</p> <pre><code>module dut_verif_bind ( inout A, input B ); string IF_PATH; import uvm_pkg::*; AB_intf vif(); assign vif.A = A; assign vif.B = B; initial begin wait(IF_PATH !=&quot;&quot;) uvm_config_db#(virtual AB_intf)::set(null, IF_PATH, &quot;vif&quot;, vif); end endmodule module tb#(string IF_PATH = &quot;uvm_test_top*&quot;) (); dut my_dut(); bind my_dut dut_verif_bind dut_if_binds (.*); initial my_dut.dut_verif_bind.IF_PATH = $sformatf(&quot;%s.dut*&quot;, IF_PATH); endmodule </code></pre>

<p>I would like to bind a module, and pass a parameter from the module I declared the bind in, rather than them all coming from the module I am binding <em>to</em>.</p> <pre><code>module dut(input logic A, output logic B); assign B = A; endmodule module dut_verif_bind#( string IF_PATH = &quot;a_string&quot; ) ( inout A, input B ); import uvm_pkg::*; AB_intf vif(); assign vif.A = A; assign vif.B = B; initial begin uvm_config_db#(virtual AB_intf)::set(null, IF_PATH, &quot;vif&quot;, vif); end endmodule </code></pre> <p>The bind module would be bound from some higher level (a testbench, or another bind module) to <code>dut</code>. The fact that this can be another bind module is why I want to be able to bind the parameters like this.</p> <pre><code>module tb#(string IF_PATH = &quot;uvm_test_top*&quot;) (); dut my_dut(); bind my_dut dut_verif_bind#(.IF_PATH($sformatf(&quot;%s.dut*&quot;, IF_PATH))) dut_if_binds (.*); endmodule </code></pre> <p>The above however, gives errors, because in the parameter binding of the bind module (<code>#(.IF_PATH($sformatf(&quot;%s.dut*&quot;, IF_PATH)))</code>) it is searching for the IF_PATH parameter in the module being bound <em>to</em>, not in the scope of the bind declaration. This is somewhat intuitive, though I hadn't considered that issue, but it also seems like there should be a way around it.</p> <p>For those wondering, this structure is something I am exploring because it should wind up making mid-level testbenches and tests nearly trivial to run if you have a unit and system test anyways. Just need a couple extra sequences and a couple more agent instantiations, but you don't have to start over with declaring interfaces and tossing them in the database, and shouldn't have to move them around the database at all.</p> <p>How to bind a module in system verilog, with parameters not from the target location?</p>

How to bind a module in system verilog, with parameters not from the target location

2024-01-25T21:45:18.330

698952

|circuit-analysis|ltspice|modeling|

<h3>note 1 about the .TRAN card</h3> <p>I guess, first off, your <strong>.TRAN</strong> card is providing <span class="math-container">\$10\:\text{s}\$</span> as an initial step-size guess (as well as a plotting increment.) This is unusual. But it's fine, too. I'm just being pedantic to note it here.</p> <h3>note 2 about the .TRAN card</h3> <p>You are specifying an end-time of <span class="math-container">\$100\:\text{s}\$</span> for the run. Again, just being pedantic for now.</p> <h3>initial transient solution</h3> <p>Spice simulators will usually first try to find the DC operating point of the circuit. This is called the &quot;initial transient solution&quot; step (sometimes shortened to <strong>ITS</strong>), which takes place immediately prior to <span class="math-container">\$t=0\$</span>.</p> <p>There is an option called UIC on the .TRAN card that will tell Spice to avoid this initial <strong>ITS</strong> step.</p> <p>The use of UIC on the <strong>.TRAN</strong> card means that Spice will not go through the <strong>ITS</strong> step.</p> <p>Instead, when using this option, the initial value of every single energy storage (voltage/capacitor and current/inductor) device to be treated as zero -- except for those which are explicitly provided using the <strong>.IC</strong> card. (You can add as many <strong>.IC</strong> cards as you feel you need.)</p> <h3>your situation, as given</h3> <p>So, without the <strong>UIC</strong> option on the <strong>.TRAN</strong> card, Spice will go through the <strong>ITS</strong> step.</p> <p>(<em>In doing so, it will still look for specific <strong>.IC</strong> cards and set things as indicated. But aside from any modifications by <strong>.IC</strong> cards, the other energy storage devices (inductors and capacitors) will be initialized with zero stored energy.</em>)</p> <p>This means it will attempt to find a <span class="math-container">\$t\to\infty\$</span> solution before starting the run. And in your case, this means finding a <em><strong>very large</strong></em> result as the starting point of the run.</p> <p>This isn't what you want.</p> <p>So check off the <strong>UIC</strong> option of the <strong>.TRAN</strong> card. This will avoid the <strong>ITS</strong> step.</p> <h3>results</h3> <p>If you do as I suggested, then you will expect to see <span class="math-container">\$\frac{\text{d}\,V}{\text{d}t}=\frac{I}{C}=\frac{2\:\text{A}}{20\:\mu\text{F}}=100\:\text{k}\frac{\text{V}}{\text{s}}\$</span>. So, in <span class="math-container">\$t=100\:\text{s}\$</span> you would expect to see <span class="math-container">\$10\:\text{MV}\$</span> at the output.</p> <p>Let's see:</p> <p><a href="https://i.stack.imgur.com/1YJzP.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/1YJzP.png" alt="enter image description here" /></a></p> <p>Yup! Looks right to me!</p>

<p>I try to model a simple RC circuit with input of 2 A DC and I get an out voltage (Vc) of 2 TV. I am not sure what I am doing wrong.</p> <p><a href="https://i.stack.imgur.com/S7m2s.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/S7m2s.png" alt="enter image description here" /></a></p> <p><strong>EDIT:</strong> This is for MacOS</p>

LTspice: weird behavior of simple RC circuit

2024-01-25T23:39:20.887

698957

|transmitter|receiver|sdr|

<blockquote> <p>What are the possible sample rates for both transmit and receive on the Ettus USRP B200 mini ?</p> </blockquote> <p>Too many to explicitly list. Whatever clock rate the synthesizer on the ad936x can generate, divided by an integer between 1 and 512.</p> <blockquote> <p>Does the radio use integer divisors of the master clock rate?</p> </blockquote> <p>Yes</p> <blockquote> <p>Or does it support arbirtrary sample rates as suggested here?</p> </blockquote> <p>That page does not suggest that.</p>

<p>What are the possible sample rates for both transmit and receive on the <a href="https://www.ettus.com/all-products/usrp-b200mini-i-2/" rel="nofollow noreferrer">Ettus USRP B200 mini</a> ? This SDR uses the <a href="https://www.analog.com/en/products/ad9364.html" rel="nofollow noreferrer">AD9364</a> chip.</p> <p>Does the radio use integer divisors of the master clock rate? Or does it support arbirtrary sample rates as suggested <a href="https://files.ettus.com/manual/page_usrp_b200.html" rel="nofollow noreferrer">here</a>?</p>

USRP B200 sample rates

2024-01-26T00:25:16.583

698970

|integrated-circuit|pins|

<p>I measured resistance between pins 1 and 4 (assuming top left is pin #1) and got a resistance of 1 or 2 MOhms (I can't remember now). Pins 3 to 6 were not connected. So this supports top left being pin #1.</p> <p>Thanks for the input.</p>

<p>Where is pin #1 on this IC?</p> <p>It seems to have a line and a dot. The dot doesn't seem to line up with a corner pin though.</p> <p>Chip is a INA210AIDCKR.</p> <p><a href="https://i.stack.imgur.com/mzfED.jpg" rel="noreferrer"><img src="https://i.stack.imgur.com/mzfED.jpg" alt="enter image description here" /></a></p>

Which pin is pin #1?

2024-01-26T04:55:44.847

698973

|pcb-design|current-measurement|

<p>You can put multiple shunt resistors in parallel or you can use a copper trace as a shunt resistor.</p>

<p>What is the best way to large current flow through SMD resistor?</p> <p>As you know, latest FPGA like ULTRA series or Versal series need large Core current almost over the hundred ampere.</p> <p>It is not problem, if i not use shunt resistor or use expensive DC/DC regulator that has power management function(can get measuring output voltage or current), because they connected through just copper plane from voltage source to FPGA.</p> <p>If i use shunt resistor and that has not enough big smd pads, i think it will be make problem.</p> <p>Because i can make big enough copper island but current must flow through shunt resistor smaller and narrower than island.</p> <p>is there any good way?</p>

Large current flow through SMD shunt resistor

2024-01-26T05:33:53.007

698978

|mosfet-driver|isolation|ground-loop|half-bridge|

<p>Your circuitry isn't going to work. Even with isolated supplies. The fundamental issue is that the logic input reference is common to the MOSFET gate return. What you need is a high-side gate driver with bootstrap to drive an N-channel MOSFET. What you really need is a half-bridge driver that includes the bootstrap diode. There are so many to choose from including high-voltage versions (up to ~600VDC). Some even include adjustable deadtime. TBH, the whole left side of you circuit (everything except you power stage) could be replaced with a single 8-pin gate drive and boot capacitor.</p> <p>You probably want something like this if you have no idea what I'm talking about: <a href="https://www.ti.com/lit/ds/symlink/ucc27712-q1.pdf?ts=1706252591500&amp;ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FUCC27712-Q1" rel="nofollow noreferrer">https://www.ti.com/lit/ds/symlink/ucc27712-q1.pdf?ts=1706252591500&amp;ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FUCC27712-Q1</a></p> <p>I don't know your requirements, but there are plenty of options available: High-voltage, built in shoot-through protection, single input, independent gate control, fixed dead-time, adjustable dead time, programable slew rate if you want to get fancy, ect. All the big names make these: TI, ADI, Infinium, Microchip Tech, OnSemi, ect.</p>

<p>I built this half-bridge driver using a generic Schmitt trigger/hex inverter IC and a 555 timer as the square wave generator. By varying the value of the resistors, the dead time can be adjusted and it works perfectly!</p> <p>The outputs are connected to the input of a <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/21419D.pdf" rel="nofollow noreferrer">TC4420</a> MOSFET driver IC. One for each output. I thought this would work by using two (galvanically-isolated) power supplies for each of the TC4420s but then realized that a ground loop still exists between the input signals.</p> <p>Is there a way I can eliminate this ground loop without optocouplers? Optocouplers are slow and even the fast ones might draw more current than the hex inverter can output.</p> <p><a href="https://i.stack.imgur.com/QocwG.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/QocwG.jpg" alt="half-bridge driver" /></a></p>

Half-bridge driver ground loop elimination

2024-01-26T06:25:26.970

698992

|power-supply|batteries|datalogger|

<p>There are some specialty lithium batteries (LiSOCl2) that can take up to 125°C.<br /> For an example see <a href="https://tadiranbat.com/applications/high-temperature/" rel="noreferrer">Tadirn TLH batteries</a>.<br /> Yet <a href="https://www.huajubattery.com/high-temperature-battery/" rel="noreferrer">another manufacturer</a> using a similar Li chemistry claims a 165°C limit.</p>

<p>I have constructed a data logger which will be used in a tumble dryer. During the drying process the temperatures inside are 60-80 °C. The data logger is designed to move freely inside the tumbler. The data logger is very compact. How would you supply it with electricity (3 V, 50 mA)?</p>

How to supply a data logger with electricity inside a tumble dryer at 80 °C?

2024-01-26T07:38:59.893

699005

|mosfet|

<p>If you calculate the gain of this amplifier, it would come out to be: <span class="math-container">$$ A_v = \frac{(1-g_mR_G)R_D}{R_G+R_D} $$</span> Assuming that <span class="math-container">\$R_G &gt;&gt; R_D\$</span>, <span class="math-container">\$A_v = -g_mR_D\$</span>. Thus, keeping <span class="math-container">\$R_G\$</span> much larger (for example, <span class="math-container">\$R_G = 10\times R_D\$</span>) than <span class="math-container">\$R_D\$</span> ensures that the amplifier gain is not affected by it.</p>

<p>I have a doubt and can't find relevant information in books/internet about setting a suitable value of Rg resistance during MOSFET biasing using a large drain-to-gate feedback resistance. Here is a visualization of the problem:</p> <p><a href="https://i.stack.imgur.com/ezeh1.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/ezeh1.png" alt="MOSFET biasing" /></a></p> <p>The current of Rg is 0 amperes, meaning that we cannot use Ohm's law here. But as far as I understand, the voltage at the gate is the same as drain Vd (the upper half of the MOSFET). It seems a bit not very intuitive to me, but I will get it.</p> <p>Now, the common knowledge says that the value of Rg must be &quot;sufficiently large&quot; around some Mega Ohms, but still, I had not seen any formula or a way to find its minimum value or something. Is there a formal way to determine it resistance, or just say that it should be &quot;large&quot; around some Mega Ohms?</p>

MOSFET biasing and Rg value

2024-01-26T10:36:06.350

699012

|circuit-analysis|capacitor|

<p>Let X be the total capacitance, then</p> <p>Q = U * X = 200V * X = 10 uC</p> <p>X = 1/20 uC / V = 50 nF</p> <p>This is the total capacitance of the two series caps. Now figure C2 in the task:</p> <p>50nF = C2 * 4<em>C2 / (C2 + 4</em>C2) = 4<em>C2^2 / 5</em>C2 = 4/5 * C2</p> <p>C2 = 5/4 * 50nF = 62.5nF</p> <p>C1 = 4*C2 = 250nF</p>

<p><img src="https://i.stack.imgur.com/H3KeH.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fH3KeH.png">simulate this circuit</a> &ndash; Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a>}</p> <p>The exercise:</p> <blockquote> <p>We switch 200 V as a resulting voltage on two capacitors in series. <br> The charge of the two capacitor is 10 µAs (Q1=Q2).</p> <p>What is the capacitance of the two, if C1 = 4C2 ?</p> </blockquote> <p>The capacitative voltage divider would be an option, but we do not know either capacitance.</p>

A bit tricky exercise that I'm currently looking for help to solve it

2024-01-26T11:32:37.353

699014

|operational-amplifier|low-pass|integrator|

<p>5MΩ is not a very high value if your accuracy requirements are modest and the environment is benign. You normally don't start to run into problems with long time constants until the times get into the minutes. I have made analog products with time constants as high as 30 or 60 minutes. But that was then, now we would generally do that digitally once it gets beyond seconds.</p> <p>You should pick an op-amp with a guaranteed low input bias current and a capacitor with guaranteed low leakage (neither of which are much of an issue for the numbers involved). And get a reasonably stable resistor.</p> <p>I suggest also that you at least consider a digital solution, which can largely avoid the relatively large (relative to the accuracy of a crystal) temperature dependency of R and C values and several other sources of error.</p>

<p>I have to design an integrator for very low frequencies (corner frequency around 0.5 Hz).</p> <p>Are there any reasons why I cannot choose a really high resistor value (say 5M Ohm) to keep the capacitor value reasonably low? Consider that the signals at play are also quite small.</p>

High R for low frequency op amp integrator

2024-01-26T11:44:27.720

699021

|ultrasound|flux|

<blockquote> <p>Is there any chance I could completely clean the PCB in ultrasound?</p> </blockquote> <p>I would switch to a better solvent, if that is something that is tolerable and still PCB compatible. I usually recommend some of techsprays stuff but it wouldn't work well in a bath. IPA is a weak solvent:</p> <blockquote> <p>IPA isn’t a great cleaner. It has a Kb (Kauri-butanol) value of about 50, meaning it’s not strong enough to tackle the tougher-to-remove lead-free and no-clean flux residue commonly used today. It also isn’t very good at removing greasy or oily fingerprints. Source: <a href="https://www.microcare.com/en-US/Resources/Insights/June-2021/Stop-Using-IPA-to-Clean-Your-PCBs" rel="nofollow noreferrer">https://www.microcare.com/en-US/Resources/Insights/June-2021/Stop-Using-IPA-to-Clean-Your-PCBs</a></p> </blockquote> <p>Also make sure you are using 99% IPA and not something from the local store that has a lot of water in it.</p> <p>So try and find something higher on the Kb scale that will work for your application.</p> <blockquote> <p>Would increasing (how much?) the isopropyl alcohol temperature help?</p> </blockquote> <p>Yeah, but it will also cause your IPA to evaporate much faster as the boiling point is at ~80C, lower than water. Increasing it beyond 40C gets it into the air in a hurry.</p> <p>Another thing would be to switch the flux, I really like chipquick 291 (no clean), and maybe they have something that would be easy to clean in a <a href="https://www.chipquik.com/store/index.php?cPath=300" rel="nofollow noreferrer">water-soluable or rosin based</a> that would work better with IPA</p>

<p>I have tried to clean the flux remnants on a high-voltage PCB using isopropyl alcohol in ultrasound. The flux remnants were visible around the big SMD components such as transistors or in the creepage-distance cutouts. The main idea of the cleaning was to prepare the PCBs for potting.</p> <p>The result was that after applying ultrasound for one hour the flux remnants are still there but seem broken up. The broken up flux remnants still stick to the PCB even though they can be manually removed relatively easily.</p> <p>Is there any chance I could completely clean the PCB in ultrasound? Would increasing (how much?) the isopropyl alcohol temperature help?</p>

Ultrasound cIeaning of PCBs with isopropyl alcohol

2024-01-26T12:33:34.633

699023

|mosfet|schematics|powermosfet|reverse-polarity|

<p>The two sources (1,2,3) are connected together. The grey thick line has obscured the internal connection from body to source.</p> <p>This is a standard back-to-back MOSFET connection to make a bilateral switch.</p> <p><a href="https://i.stack.imgur.com/2Lk8Q.png" rel="noreferrer"><img src="https://i.stack.imgur.com/2Lk8Q.png" alt="enter image description here" /></a></p>

<p>I'm trying to implement a USB PD controller, STUSB4500, but the typical application example shows 2x P-Channel MOSFETs STL6P3LLH6 with different arrow indications. I'm now confused about the pins, T4 has the same MOSFET drawing as in the STL6P3LLH6 datasheet, so the left pin is the drain (5,6,7,8) and the right source (1,2,3). But for T1, which is reversed, is the right side pins 5,6,7,8 or 1,2,3? Any further clarifications on this will be appreciated.</p> <p>Image Sources/Datasheet links:</p> <p>STUSB4500: <a href="https://www.st.com/en/interfaces-and-transceivers/stusb4500.html" rel="nofollow noreferrer">https://www.st.com/en/interfaces-and-transceivers/stusb4500.html</a></p> <p>STL6P3LLH6: <a href="https://www.st.com/en/power-transistors/stl6p3llh6.html" rel="nofollow noreferrer">https://www.st.com/en/power-transistors/stl6p3llh6.html</a></p> <p><a href="https://i.stack.imgur.com/8lzOa.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/8lzOa.png" alt="STL6P3LLH6" /></a></p> <p><a href="https://i.stack.imgur.com/lHk6z.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/lHk6z.png" alt="STUSB4500" /></a></p>

Same MOSFET component but reversed arrow

2024-01-26T12:49:01.613

699032

|instrumentation-amplifier|

<p>With instrumentation amplifiers, in addition to input voltage range and output voltage range you would look it for an op-amp, you also have to pay attention to the &quot;Diamond&quot; diagrams to ensure you have high enough supply voltages that internal nodes don't saturate.</p> <p>From your datasheet link:</p> <p><a href="https://i.stack.imgur.com/kYkrI.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/kYkrI.png" alt="enter image description here" /></a></p> <p>Analog Devices has an excellent &quot;<a href="https://www.analog.com/en/analog-dialogue/studentzone/studentzone-september-2017.html" rel="nofollow noreferrer">Diamond Plot Tool</a>&quot; which can simplify this analysis with their products, however the part design you have is owned by TI (née Burr-Brown).</p>

<p>I am using a Wheatstone bridge to measure a resistance and an instrumentation amplifier to amplify the signal. Specifically, I am using the <a href="https://docs.rs-online.com/57f8/A700000006811975.pdf" rel="nofollow noreferrer">INA121</a>. According to the amplifier datasheet, the input voltage can be in the range of ±2.5V and ±15V. In addition, it says that</p> <blockquote> <p>Typical performance curves, “Input Common-Mode Range vs Output Voltage” show the range of linear operation for ±15V, ±5V, and ±2.5V supplies.</p> </blockquote> <p>Therefore, my choice would be one of those voltages. However, which one should I choose? Does a high voltage offer advantages over a low voltage (or vice-versa) in instrumentation amplifiers?</p>

Choosing a supply voltage for an instrumentation amplifier

2024-01-26T14:56:10.627

699033

|pcb|diodes|diagram|

<p>I've ordered the OSHWLab project PCB and did the same thing as on the video. It works.</p>

<p>I've to construct 8x8x8 LED cube. I'm not interested in electronics but I have to make this project.</p> <p>I've found <a href="https://www.youtube.com/watch?v=mN5JWQUfrxY&amp;t=683s" rel="nofollow noreferrer">this video.</a></p> <p>I don't want to solder paths myself so I'd like to go for the PCB but the project does not include the Gerber file.</p> <p>I searched for a similar one and <a href="https://oshwlab.com/alex.kost/led_qub_8x8x8-20a70d70e61f4f599c07546a7e8ece52" rel="nofollow noreferrer">found this.</a></p> <p>The circuit diagram looks almost identical in both projects except for the Arduino part.</p> <p>Video diagram:</p> <p><a href="https://i.stack.imgur.com/rFE0X.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/rFE0X.png" alt="video diagram" /></a></p> <p>OSHWLab diagram:</p> <p><a href="https://i.stack.imgur.com/Ocm5V.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/Ocm5V.png" alt="oshwlab diagram" /></a></p> <p>If I order this:</p> <p><a href="https://i.stack.imgur.com/THA1f.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/THA1f.png" alt="pcb" /></a></p> <p>Will it look and work like this:</p> <p><a href="https://i.stack.imgur.com/y0A2B.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/y0A2B.png" alt="cube" /></a></p>

Will the PCB from the project found online work the same as the one from the video?

2024-01-26T14:58:26.820

699037

|kicad|footprint|routing|

<p>@Hearth It worked, thanks! To make it clear: Footprint needs to be opened in Footprint Editor, next click on Edit Footprint properties (yes, there are more than one 'Properties')</p> <p><a href="https://i.stack.imgur.com/P9PEd.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/P9PEd.png" alt="FtptProperties" /></a></p> <p>Next, go to the 'Clearance Overrides and Settings', click small '+' and place desired pads (in my case: 1, 2)</p> <p><a href="https://i.stack.imgur.com/4uUua.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/4uUua.png" alt="enter image description here" /></a></p>

<p>I have created a footprint for NetTie of custom size (I wanted 0.2mm pad/connection), as the library-provided one has the size of 0.5mm and is too big.</p> <p>I have tried two ways of routing:</p> <ul> <li>from other pad to NetTie: trying to route it from outside (of NetTie) the track stops before reaching NetTie's pad</li> </ul> <p><a href="https://i.stack.imgur.com/yTBpe.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/yTBpe.png" alt="Routing from right-to-left" /></a></p> <ul> <li>when trying to start the track from NetTie, when clicking pad of NetTie, this green block shows up, the screen blinks and no track appears.</li> </ul> <p><a href="https://i.stack.imgur.com/zxtAG.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/zxtAG.png" alt="routing from NetTie" /></a></p> <p>Most probably there is a DRC rule on the way. To prevent it, I ensured that during footprint creation all layers, polygons etc. were the same as the working NetTie from library. Unless there are some additional settings invisible in KiCAD of which I don't know.</p> <p>What to check to make this custom made NetTie to be possible to route?</p>

Custom made NetTie in KiCAD7 can't be routed

2024-01-26T15:19:11.300

699040

|microcontroller|capacitor|pcb|integrated-circuit|low-pass|

<p>The capacitors for the LED driver are necessary for stabilizing the chip - they decouple the power supply and provide local noise immunity. If you want a robust design, keep the capacitors. Also, they prevent disturbing the VCC plane that other IC's are using especially if this LED driver modulates via PWM.</p> <p>Will the circuit work with out them? Probably. But it's bad design practice - it's a lot of risk for practically no cost or effort.</p>

<p><a href="https://i.stack.imgur.com/VxFT5.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/VxFT5.png" alt="Circuit Design for PCB" /></a>I have two circuits, one is a POE to 5V, another is an IC for leds. They both include capacitors between 5v and gnd. Should I include the first 5V circuit POE capacitors since it should already be doing the filtering? Transformer for POE: <a href="https://www.coilcraft.com/de-de/products/transformers/power-transformers/power-converter-transformers/fct1-xxm22sl/fct1-50m22sl/" rel="nofollow noreferrer">https://www.coilcraft.com/de-de/products/transformers/power-transformers/power-converter-transformers/fct1-xxm22sl/fct1-50m22sl/</a> POE datasheet: <a href="https://www.monolithicpower.com/en/documentview/productdocument/index/version/2/document_type/Datasheet/lang/en/sku/MP8009GV-Z/document_id/4873/" rel="nofollow noreferrer">https://www.monolithicpower.com/en/documentview/productdocument/index/version/2/document_type/Datasheet/lang/en/sku/MP8009GV-Z/document_id/4873/</a> LED Current Regulator: <a href="https://www.digikey.com/en/products/detail/lumissil-microsystems/IS31FL3236A-QFLS4-TR/14308348" rel="nofollow noreferrer">https://www.digikey.com/en/products/detail/lumissil-microsystems/IS31FL3236A-QFLS4-TR/14308348</a> Or is there something I am missing. Here are the schematics: [![enter image description here][2]][2]</p>

Should you include multiple low-pass capacitor circuits in integrated IC PCB design?

2024-01-26T15:36:02.870

699052

|microcontroller|transistors|led|

<p>Rb4 should be connected between Vss and the base of Q4. The collector of Q3 should be connected to the base of Q4 and your “fwd” node.</p>

<p>I built the following circuit but am getting a result I wasn't expecting.</p> <p><a href="https://i.stack.imgur.com/iVahN.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/iVahN.png" alt="LED module circuit (image)" /></a></p> <p>Here is a link to the CircuitLab model (I don't know how to upload a saved circuit to StackExchange):</p> <p><a href="https://www.circuitlab.com/circuit/23xpuqf4k49e/led_module_1/" rel="nofollow noreferrer">LED_module_circuit_diagram</a></p> <p>The circuit design was supposed to work as follows:</p> <p>The bank of LEDs labelled FWD are three white LEDS, the bank of LEDs labelled REV are two red LEDs. These represent the lights at one one end of a model locomotive which may move forward or reverse and the lights respond accordingly. The lights on the rear of the locomotive would behave the opposite way.</p> <p>The four inputs on the left are logic high (+5V) or low (0V) (from a MCU), except Vss which is tied to the positive supply (+5V). For the purposes of this question the input nINTEN may be ignored.</p> <p>A logic low on input nEXTEN is supposed to enable use of the FWD and REV banks of LEDs. A logic high should switch off both banks. While nEXTEN is logic low the input FWDnREV should dictate which bank of LEDs is lit. With logic high the white LEDs should light (red LEDs off), with logic LOW the red LEDs should light (white LEDs off).</p> <p>The circuit works as desired except in one case. With nEXTEN low, and FWDnREV low, the red LEDs light as desired, but the white LEDs are dimly lit as oposed to fully extinguished.</p> <p>What is the cause of this and what should solve it?</p>

Why do I see unwanted current through this BJT switching circuit?

2024-01-26T17:48:05.550

699068

|integrated-circuit|cmos|

<p>I believe that your problem is your assumption:</p> <p><span class="math-container">$$ I_D = K \frac{W} {L} (|V_{GS}| - |V_{th}|)^2 (1 + \lambda |V_{DS}|) $$</span></p> <p>This is only valid if:</p> <p><span class="math-container">$$ (|V_{GS}| &gt; |V_{th}|) $$</span></p>

<p>This is my LTspice schematic.</p> <p><a href="https://i.stack.imgur.com/DcdIp.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/DcdIp.png" alt="enter image description here" /></a></p> <p>I want to calculate <span class="math-container">\$V_{D5}\$</span>, <span class="math-container">\$V_{D1}\$</span>, <span class="math-container">\$V_{o}\$</span> with <strong>vpasolve</strong> of matlab. (body effect is omitted)</p> <p><span class="math-container">$$I_D = K \frac{W} {L} (|V_{GS}| - |V_{th}|)^2 (1 + \lambda |V_{DS}|)$$</span></p> <p>The following is my matlab code for this. I have tried to assume it works in saturation region.</p> <pre><code>syms Vd5 Vd1 Vo Vg1 = 0.5; eq1 = 45*0.28^2*(1+0.14*(1.8-Vd5)); eq2 = 45*(Vd5 - Vg1 - 0.42)^2*(1+0.14*(Vd5 - Vd1)); eq3 = 180*(Vd1 - 0.4)^2*(1+0.1*Vd1); eq4 = 45*(Vd5 - Vg1 - 0.42)^2*(1+0.14*(Vd5 - Vo)); eq5 = 180*(Vd1 - 0.4)^2*(1+0.1*Vo); assume(Vd5,'real') assume(Vd5 &gt; 0) assume(Vd1,'real') assume(Vd1 &gt; 0) assume(Vo,'real') assume(Vo &gt; 0) sols=vpasolve([eq1 == eq2 + eq4, eq1 == eq3 + eq5, eq2 == eq3, eq4 == eq5], [Vd5 Vd1 Vo]) sols.Vd5 sols.Vd1 sols.Vo </code></pre> <p>However, I get four solutions for each of them.</p> <p><span class="math-container">$$ V_{D5}\\ 0.71344432404311890453319743751794\\ 1.1187983792156107381232495588654\\ 0.71045661574218931843791077163816\\ 1.1163074481576831005801671170109 $$</span></p> <p><span class="math-container">$$ V_{D1}\\ 0.29527690618454959297640091709984\\ 0.50110568892034423447002647073843\\ 0.50369771677840608850545439819988\\ 0.29788531456890030501286382283015 $$</span></p> <p><span class="math-container">$$ V_{o}\\ 0.29527690618454959297640091709984\\ 0.50110568892034423447002647073843\\ 0.50369771677840608850545439819988\\ 0.29788531456890030501286382283015 $$</span></p> <p>We know that <span class="math-container">\$|V_{DS}| &gt; |V_{GT}|\$</span>. However, it is still impossible to eliminate any of this four solution results.</p> <p>The following is the asc file from LTSpice.</p> <pre><code>Version 4 SHEET 1 880 680 WIRE 16 -160 -48 -160 WIRE 336 -160 16 -160 WIRE 640 -160 336 -160 WIRE 320 -144 64 -144 WIRE 448 -144 320 -144 WIRE -48 -112 -48 -160 WIRE 16 -112 -48 -112 WIRE 16 -48 16 -64 WIRE -32 -32 -80 -32 WIRE 16 -32 16 -48 WIRE 16 -32 -32 -32 WIRE 48 -32 16 -32 WIRE 96 -32 48 -32 WIRE -192 -16 -272 -16 WIRE -128 -16 -192 -16 WIRE 288 -16 144 -16 WIRE -32 16 -32 -32 WIRE -32 16 -80 16 WIRE 48 16 48 -32 WIRE 96 16 48 16 WIRE -576 64 -576 0 WIRE -416 64 -416 0 WIRE -272 64 -272 -16 WIRE 288 64 288 -16 WIRE 448 64 448 -144 WIRE 640 64 640 -160 WIRE -80 96 -80 64 WIRE 16 96 -80 96 WIRE 96 112 96 64 WIRE 144 112 96 112 WIRE -80 128 -80 96 WIRE 96 128 96 112 WIRE -80 176 -160 176 WIRE 176 176 96 176 WIRE 16 208 16 96 WIRE 16 208 -32 208 WIRE 48 208 16 208 WIRE -576 240 -576 144 WIRE -416 240 -416 144 WIRE -416 240 -576 240 WIRE -272 240 -272 144 WIRE -272 240 -416 240 WIRE -160 240 -160 176 WIRE -160 240 -272 240 WIRE -80 240 -80 224 WIRE -80 240 -160 240 WIRE 96 240 96 224 WIRE 96 240 -80 240 WIRE 176 240 176 176 WIRE 176 240 96 240 WIRE 288 240 288 144 WIRE 288 240 176 240 WIRE 448 240 448 144 WIRE 448 240 288 240 WIRE 640 240 640 144 WIRE 640 240 448 240 WIRE -576 256 -576 240 FLAG -576 256 0 FLAG 336 -160 VDD FLAG 320 -144 VB FLAG -192 -16 VG1 FLAG 288 -16 VG2 FLAG 16 96 VD1 FLAG -576 0 Vicm FLAG -416 0 Vid FLAG 144 112 Vo IOPIN 144 112 Out FLAG 16 -48 VD5 SYMBOL nmos4 48 128 R0 WINDOW 123 56 100 Left 2 SYMATTR Value2 l=1u w=20u SYMATTR InstName M4 SYMATTR Value NMOS-SH SYMBOL nmos4 -32 128 M0 WINDOW 123 56 100 Left 2 SYMATTR Value2 l=1u w=20u SYMATTR InstName M3 SYMATTR Value NMOS-SH SYMBOL pmos4 144 64 R180 WINDOW 3 -107 24 Left 2 WINDOW 123 -106 -4 Left 2 SYMATTR Value PMOS-SH SYMATTR Value2 l=1u w=20u SYMATTR InstName M2 SYMBOL pmos4 -128 64 M180 WINDOW 3 -106 15 Left 2 WINDOW 123 -106 43 Left 2 SYMATTR Value PMOS-SH SYMATTR Value2 l=1u w=20u SYMATTR InstName M1 SYMBOL pmos4 64 -64 R180 WINDOW 123 96 35 Left 2 SYMATTR Value2 l=1u w=20u SYMATTR InstName M5 SYMATTR Value PMOS-SH SYMBOL voltage -576 48 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName Vicm SYMATTR Value 0.5 SYMBOL voltage -416 48 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName Vid SYMATTR Value 0 SYMBOL voltage 448 48 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName VB SYMATTR Value 1.1 SYMBOL voltage 640 48 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName VDD SYMATTR Value 1.8 SYMBOL bv -272 48 R0 WINDOW 3 -98 210 Left 2 SYMATTR Value V=V(Vicm)+V(Vid)/2 SYMATTR InstName B1 SYMBOL bv 288 48 R0 WINDOW 3 -103 209 Left 2 SYMATTR Value V=V(Vicm)-V(Vid)/2 SYMATTR InstName B2 TEXT -264 -240 Left 2 !.MODEL NMOS-SH nmos(kp=180u,vto=0.4, lambda = {0.1/1}, gamma = 0.5, phi = 0.7) TEXT -264 -216 Left 2 !.MODEL PMOS-SH pmos(kp=45u,vto=-0.42, lambda = {0.14/1}, gamma = 0.5, phi = 0.7) TEXT -264 -264 Left 2 !;dc Vicm 0 1.8 0.01 TEXT -264 -288 Left 2 !;tf V(Vo) Vid TEXT -256 -320 Left 2 !.op </code></pre>

How to eliminate other possible solutions when doing DC analysis of Analog CMOS

2024-01-26T20:10:07.037

699069

|operational-amplifier|single-supply-op-amp|sallen-key|

<p>There are two things that can be taken from <a href="https://www.analog.com/media/en/technical-documentation/data-sheets/ad712.pdf" rel="nofollow noreferrer">this graph in the datasheet</a>: -</p> <p><a href="https://i.stack.imgur.com/XD0gX.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/XD0gX.png" alt="enter image description here" /></a></p> <ul> <li>The minimum supply voltage is +/- 5 volts (a 10 volt span)</li> <li>The valid input voltage range is about 3.5 volts for a +/- 5 volt supply</li> </ul> <p>Additionally, the data sheets informs that the input voltage range is from +3.5 volts above the negative rail to 0.5 volts below the positive rail.</p> <p>No-way will it work on a single 3.3 volt power rail.</p>

<p>I was designing an active low pass filter for simple sigma-delta modulation signals. I found that the op-amp will output 3V when the input is 0V given that the power supply is 0~3.3V.</p> <p>I simulate the circuit and find the same result. The circuit and the result are shown below. The blue line is the output of the op-amp.</p> <p><a href="https://i.stack.imgur.com/wzBTx.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/wzBTx.png" alt="simulation" /></a></p> <p>According to my analysis, it is essentially a unity gain buffer with 10k2 input resistance in this scenario and the output should be 0V.</p> <p>I noticed that the voltage will follow when V2 is slightly greater than 0V.</p> <p>Why does that happen?</p>

2nd-order Sallen-key low pass filter with unity gain outputs rail voltage when input is 0V

2024-01-26T20:42:51.920

699077

|circuit-analysis|transfer-function|laplace-transform|

<p>Well, using the voltage divider formula:</p> <p><span class="math-container">$$\mathscr{H}\left(\text{s}\right):=\frac{\displaystyle\text{V}_\text{o}\left(\text{s}\right)}{\displaystyle\text{V}_\text{i}\left(\text{s}\right)}=\frac{\displaystyle\frac{\displaystyle1}{\displaystyle\text{sC}}\space\text{||}\space\text{sL}}{\displaystyle\text{R}+\left(\frac{\displaystyle1}{\displaystyle\text{sC}}\space\text{||}\space\text{sL}\right)}=\frac{\displaystyle\text{sL}}{\displaystyle\text{CLRs}^2+\text{Ls}+\text{R}}\tag1$$</span></p> <p>Where <span class="math-container">\$\displaystyle\alpha\space\text{||}\space\beta:=\frac{\displaystyle\alpha\beta}{\displaystyle\alpha+\beta}\$</span>.</p>

<p><a href="https://i.stack.imgur.com/aqTS6.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/aqTS6.png" alt="enter image description here" /></a> I am trying to get the transfer function G(s)=Vo(s)/VI(s) of this circuit and I am lost. I know that in the s domain, L=sL and C=1/sC. I tried to calculate it already and got R+(Ls)/((Ls^2)*C+1). But I don't know if that is correct because I didn't really do anything with current?</p> <p>I think I am confused on the overall method of getting a transfer function for a circuit. I thought the steps were get Vi, manipulate it until the right is in terms of Vo, and then do Laplace, and then put into Vo/Vi form. But I am seeing around this forum another method where you use impedance somehow? That is what I attempted to use to get my top answer, impedance of R + Xc || XL. I tried looking at other RLC circuit transfer functions on here where that method was used and I did not understand what the process is.</p> <p>So how am I supposed to calculate this?</p>

Using impedance to get RLC Transfer Function

2024-01-26T21:29:33.713

699084

|wiring|

<p>Here is a <a href="https://www.nbdibo.com/wp-content/uploads/2020/06/DB2EK-3.5-XXP-C-S.pdf" rel="noreferrer">Dorabo terminal block PDF</a> close to the P/N that you have. It is the top half of the terminal block assembly. As you can see there are also key guides that help locate and seat the halves.</p> <p>Not sure if there is a locking tab that first needs to be disengaged.<br /> You might try prying very carefully at the first plastic to plastic interface above the PCB surface to separate the two sections. Once separated you would loosen the terminal screw, insert the wire, re-tighten the screw, repeat for all other wires on that terminal block, then reinsert the upper block into the lower section.</p>

<p>I have this power supply (actually part of a control box for a robot arm) which has terminal blocks, but most of the screws seem complete inaccessible due to how closely the blocks are placed together. Here is a picture of the one semi-reachable screw in the whole device.</p> <p><a href="https://i.stack.imgur.com/BGn2b.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/BGn2b.png" alt="a reachable screw among unreachable screws" /></a></p> <p>Here is a top view of where I want my wires to go in.<br /> <a href="https://i.stack.imgur.com/4H3ix.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/4H3ix.png" alt="top view" /></a></p> <p>I thought maybe the connection pads were spring loaded but I could not pry them open with a tweezer.</p> <p>Taking a picture from one side, I noticed there is a label! &quot;DORABO DB2EK-3.5&quot; <a href="https://i.stack.imgur.com/VR85i.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/VR85i.jpg" alt="label on the block" /></a></p>

How to connect to these terminal blocks?

2024-01-27T00:11:21.833

699129

|transceiver|mil-std-1553|

<blockquote> <p>Is GND connection required for two independent modules to communicate in MIL STD 1553 protocol?</p> </blockquote> <p>Because the physical layer of MIL STD 1553 requires transceivers to be connected to the bus via isolation transformers, no common ground connection is required between transceivers.</p> <p>The Holt IC application note AN-550 referenced in the question shows a center tap on bus-side of the isolation transformer, which it says is &quot;often&quot; not connected.</p> <p>Data Defense Corporations <a href="https://www.milstd1553.com/wp-content/uploads/2012/12/MIL-STD-1553B.pdf" rel="nofollow noreferrer">Review and Rationale of MIL STD 1553 A and B</a> has a similar schematic which shows no bus-side center tap on the isolation transformer.</p> <p><a href="https://i.stack.imgur.com/Jyne6.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/Jyne6.png" alt="enter image description here" /></a></p> <p>If however, the bus-side center tap of the isolation transformer is grounded on one module, the differential pair will not &quot;float&quot;, but will be referenced to that ground. If more than one module has the bus-side center tap connected to ground, and the modules are direct-connected to the bus, then there is a ground path through the differential pair. If the ground potentials are different at the different modules, this ground current could be significant, and might possibly interfere with communication. Therefore, the bus-side center tap of the isolation transformer should not be connected to ground if the modules are directly connected to the bus.</p> <p>Rather than connect the bus-side isolation transformer center-tap to ground, it <em>might</em> make sense to connect it to the shield of the twisted pair cable. Whether or not shields should be connected on both ends has been debated. I will only say that &quot;both ends connected&quot; might work in some circumstances, and &quot;one end only&quot; might work in other circumstances. I will leave it to others to comment further on this topic if they choose to.</p> <p>If the modules you are using require a common ground connection in order to communicate, they are failing to meet the standard. Something is wrong. The schematic for the Holt IC module provided in the question shows such an isolation transformer. Can you check the modules to see if they do indeed have isolation transformers? Can you verify that the bus-side center taps of the isolation transformers are not connected to ground?</p>

<p>I use a Holt IC 2130 MIL-STD-1553 transceiver. When I connect only the A and B differential lines in two independent modules, I can't communicate between the two modules, but when I connect the GND pins, the communication is completed successfully.</p> <p>Is GND connection required for two independent modules to communicate using the MIL-STD-1553 protocol? Or is there another point I missed? As far as I know, GND connection is not required for differential lines.</p> <p><a href="https://i.stack.imgur.com/ghCEk.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/ghCEk.png" alt="enter image description here" /></a></p> <p><a href="https://i.stack.imgur.com/Qn6lJ.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/Qn6lJ.png" alt="enter image description here" /></a> Source: <a href="https://smallpdf.com/result#r=aa4b30d6011942438c3436c435231433&amp;t=share-document" rel="nofollow noreferrer">Holt IC AN-550</a></p>

Is GND connection required for two independent modules to communicate in MIL STD 1553 protocol?

2024-01-27T12:42:52.130

699132

|power-supply|sensor|battery-operated|gas-sensor|

<p>The MQ6 has a heater inside it that draws about 200 mA @ 5 V. This is far more than a standard rectangular 9V battery can supply for any length of time.</p>

<p>I've connected an MQ6 gas sensor to the output of a 78L05 5 V regulator, with its input connected to the + terminal of a Duracell 9 V battery. The DOUT pin of the MQ6 is connected to the - terminal of a buzzer.</p> <p>After a while, the green light on the MQ6 indicating that it is operational goes out, the red light indicating that there is a gas leak lights up very dimly and the buzzer starts to sound even though there is no leak.</p> <p>When I disconnect the whole thing and let the battery rest for a while, the sensor starts working again until it stops working properly.</p> <p>can anyone tell me what's wrong with my project ? I was inspired by this project <a href="https://www.youtube.com/watch?v=wq1bM2EpRdI" rel="nofollow noreferrer">https://www.youtube.com/watch?v=wq1bM2EpRdI</a> but I had to add a voltage regulator because the MQ6 requires a voltage of 5 volts.</p> <p><a href="https://i.stack.imgur.com/5PTEp.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/5PTEp.png" alt="enter image description here" /></a></p> <p>Datasheet : <a href="https://joy-it.net/files/files/Produkte/SEN-MQ6/SEN-MQ6_Datasheet_2023-09-26.pdf" rel="nofollow noreferrer">https://joy-it.net/files/files/Produkte/SEN-MQ6/SEN-MQ6_Datasheet_2023-09-26.pdf</a></p>

My MQ6 gas detector stops working properly after some time when using a battery

2024-01-27T13:18:56.410

699137

|instrumentation-amplifier|

<p>R250 is needed to allow natural bias currents from the op-amp inputs to flow to local 0 volts. If it were not there, the inputs would float and likely cause common-mode input range problems.</p> <p>The differential input impedance (S2A and S2B in current positions) is R163 + R164 = 1022 Ω. This increases by 28 kΩ when S2A and S2B are changed over.</p>

<p>I have a problem understanding which resistors set input impedance of an instrumentation amplifier. What is the input impedance of the circuit given and what is the purpose of R250 (10k to GND)?</p> <p><a href="https://i.stack.imgur.com/IreF2.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/IreF2.png" alt="enter image description here" /></a></p>

Input impedance of instrumentation amplifier

2024-01-27T15:41:05.890

699177

|analog|biasing|

<p>I'm not sure what you mean by <em>&quot;biasing by fixing the DC currents of amplifying stages as opposed to the DC voltages&quot;</em>. Assuming we're talking about a common-emitter/source amplifier within a feedback loop (down to DC), you always fix the current and let the loop find the right base/gate voltages and currents (yes, even if they're nA or pA) to properly bias your amplifier stage at your desired collector/drain current.</p> <p><em>(As an aside, one could &quot;fix&quot; the current with a collect/drain resistor, but then that would incur in bias errors as long your design specs permits it)</em></p> <p>If, on the other hand, you're referring to the observation that current mirrors might be more ubiquitous in IC designs while resistive voltage dividers are seen more in discrete designs, then the reason for this choice is matching.</p> <p>In the picture below, we have implemented a voltage source with a diode-connected transistor Q2 and current source (enclosed in the dashed box). If the surroundings and external conditions change (process variations, temperature, etc), this circuit will keep adapting its base voltage such that the current is 1mA (or close to it). Since Q1 is equal to Q2 in an integrated circuit (provided there's a proper IC layout), we can closely approximate the behavior of Q1 with Q2, so we expect that Q1 will have the same current flowing through it as Q2, because they have the same size and physical characteristics (there's the collector voltage difference which might induce a collector current error, of course, but that's beside the point).</p> <p><img src="https://i.stack.imgur.com/q6qRC.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fq6qRC.png">simulate this circuit</a> &ndash; Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a>}</p> <p>If Q2 and I1 were replaced by a resistive divider, then we will not have this tracking behavior and we'd probably have more errors in the set current.</p> <p>Finally, it is not true that <em>resistors are not accessible</em> in IC technologies. We use them, all the way from a few ohms to a few Mohms, if not more. The only reason they're not used that often is due to area. Of course, no one will accept that you build a textbook degenerated common-emitter amplifier in an IC because you could design something a lot smaller with much more quality, i.e. a feedback amplifier with larger loop gain and smaller area.</p>

<p>I have this vague sense that in the design of analog <em>integrated</em> circuits we tend to think of or do biasing by fixing the DC <em>currents</em> of amplifying stages as opposed to the DC <em>voltages</em> (as seemed to be the case when studying the biasing of discrete transistors). For instance, we do biasing using current mirrors rather than doing voltage division using resistors. Now I know and understand why resistors aren't really accessible to us in the integrated circuit context, but that doesn't seem to me to be an a priori (perhaps <em>necessary and sufficient</em> is more appropriate here) reason that we focus on biasing in terms of currents rather than voltages in the integrated circuit context.</p> <ol> <li>Is this sense accurate?</li> <li>If so, is there some (deep?) reason for this or is this just sort of an accident of how the analog integrated circuits trade developed?</li> </ol>

Transistor biasing in integrated versus discrete circuits

2024-01-27T23:25:59.753

699181

|analog|feedback|common-emitter|

<p>In what follows, the calculations to obtain the elements of the quadrupole admittance matrix or relative y parameters are reported:</p> <p><a href="https://i.stack.imgur.com/gb2Ze.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/gb2Ze.png" alt="enter image description here" /></a> <a href="https://i.stack.imgur.com/zeOeq.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/zeOeq.png" alt="enter image description here" /></a> <a href="https://i.stack.imgur.com/lICCG.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/lICCG.png" alt="enter image description here" /></a> <a href="https://i.stack.imgur.com/HyAio.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/HyAio.png" alt="enter image description here" /></a> <a href="https://i.stack.imgur.com/CJgsX.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/CJgsX.png" alt="enter image description here" /></a> <a href="https://i.stack.imgur.com/Yde8J.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/Yde8J.png" alt="enter image description here" /></a> <a href="https://i.stack.imgur.com/zx4T5.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/zx4T5.png" alt="enter image description here" /></a> <a href="https://i.stack.imgur.com/KAixO.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/KAixO.png" alt="enter image description here" /></a> <a href="https://i.stack.imgur.com/uuxdI.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/uuxdI.png" alt="enter image description here" /></a> <a href="https://i.stack.imgur.com/wPaRF.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/wPaRF.png" alt="enter image description here" /></a> <a href="https://i.stack.imgur.com/qNJ8J.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/qNJ8J.png" alt="enter image description here" /></a></p> <p>Based on these results, the quadripole is reciprocal only if ro is considered tending to zero.</p>

<p>Consider the attached small-signal diagram for an emitter-degenerated CE stage: <a href="https://i.stack.imgur.com/19KQK.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/19KQK.png" alt="enter image description here" /></a> It's been a long day so I must be making an error, but I continue to conclude that this two-port is unilateral (defined as <span class="math-container">\$y_{12} = 0\$</span>) which seems absurd.</p> <p>To see this analysis, let's set <span class="math-container">\$v_i = 0\$</span> from which it follows that <span class="math-container">\$i_b = -v_e/r_\pi\$</span>. Now from KCL at the emitter and KCL at the collector and eliminating <span class="math-container">\$i_o\$</span> as marked on the graph I arrive at <span class="math-container">$$v_e = i_b \left(\frac{1 + (\beta_0 +1)r_0/R_C}{1/R_C +1/R_E +r_0/(R_ER_C)} \right).$$</span> Inserting my earlier expression for <span class="math-container">\$i_b\$</span> to this monstrosity above I conclude that <span class="math-container">\$v_e = 0\$</span> (because the LHS is positive and the RHS is negative) and thus that <span class="math-container">\$i_b = 0\$</span>. Ergo, <span class="math-container">\$y_{12} = 0\$</span>.</p> <p>But I have surely gone wrong here because</p> <p>(1) I &quot;know&quot; this circuit is bilateral since it's a standard example of negative feedback and</p> <p>(2) My analysis above contradicts that current <span class="math-container">\$v_o/r_o \neq 0\$</span> flows in the <span class="math-container">\$R_E || r_\pi\$</span> path so that <span class="math-container">\$v_e \neq 0\$</span>.</p> <p>Can anyone set me straight as to where I'm going wrong here?</p>

Why am I concluding that the emitter-degenerated CE stage is unilateral?

2024-01-28T00:04:45.800

699191

|audio|speakers|dpdt|guitar-amplifier|

<p>As mentioned above you have to provide load at amplifier output (it's just resistor but it should be rated for higher power) if amp you &quot;unplug&quot; is turned on but I don't think it's good idea to switch cabinet with amp turned on especially if it's tube amp. Whether you press switch or use relay there is short period of time when cabinet is disconnected and load isn't connected yet. I don't have much experience in that matter but it may happen that even this short period is enough to fry your output transformer. With solid state amps it's probably safer but there's still a risk.</p>

<p>Problem statement:</p> <ul> <li>I have 2 guitar amplifiers and I have 2 speaker cabinets that normally connect via speaker cables (1/4&quot; connectors). I would like to create a passive device that lets me switch which guitar amplifier to connect with which speaker cabinet.</li> </ul> <p>What I think want/need:</p> <ul> <li>I think I could do this by wiring together 2 identical switches; one for the amplifier selection and one for the cabinet selection (the cabinet selection wired in reverse of the amplifier selection since the signal would be coming IN from the select amplifier yet going OUT to the selected cabinet)</li> <li>I think each switch would need 6 connections (4x2)</li> <li>2 sets of 2 connections connected via switch to a single pair of connections</li> </ul> <p>For context:</p> <ul> <li>I've done some soldering for car audio applications and an old synthesizer chip replacement, and done some LED projects with breadboards and microprocessors but do not have an incredible amount of experience in this space.</li> </ul> <p>After some research:</p> <ul> <li>Within each of the 2 sections, the components must be completely isolated (the amplifiers speaker outputs do not share terminals) - therefore, I think I'm looking for DPDT (Dual Pole Dual Throw) switches</li> <li>In an effort to super-simplify the project, I looked up DPDT &quot;light switches&quot; and found <a href="https://www.homedepot.com/p/Leviton-20-Amp-Industrial-Grade-Heavy-Duty-Double-Pole-Double-Throw-Center-Off-Maintained-Contact-Toggle-Switch-White-1286-W/301447135" rel="nofollow noreferrer">these</a>.</li> </ul> <p>Would that work for what I'd like to do? I have a few concerns:</p> <ul> <li>that switch is very expensive for a light switch, and I'd need 2!</li> <li>what if I wanted to grow this to handle 3 or 4 amplifiers, and maybe another cabinet or 2? I'd need to handle more than 2 sets of inputs/outputs.</li> </ul> <p>So after some additional digging, I came across <a href="https://www.youtube.com/watch?v=6e4fLc-44ho" rel="nofollow noreferrer">this video</a>. My main question is around how he selected the right switch at <a href="https://youtu.be/6e4fLc-44ho?t=126" rel="nofollow noreferrer">this point</a> in the video. The switch he selects is rated at 500 mA and I think that is too small. According to <a href="https://electronics.stackexchange.com/questions/155779/home-audio-how-much-current-flows-through-my-speaker-amplifiers-output">this question</a>, even an 8 Ω speaker rated at 25 W could peak at just below 2 A. My concern is slightly reinforced <a href="https://www.soundstagesolo.com/index.php/features/342-understanding-current" rel="nofollow noreferrer">here</a> where it is mentioned:</p> <blockquote> <p>Let’s say you’re listening at loud levels and hitting 100W peaks, and you have 8-ohm and 4-ohm speakers. Using the equations above, you can calculate that the 8-ohm speaker will demand 3.5A of peak current, while the 4-ohm speaker will demand 5A of current.</p> </blockquote> <p>And yeah, guitars can get loud so I think I'd like this device to suffice for a max. 100 W speaker.</p> <p>All that to say, if I go the Mouser route, I <em>think</em> I'd be safest with a slightly beefier switch, so I tried to tweak the <a href="https://www.mouser.com/c/electromechanical/switches/rotary-switches/?contact%20style=Non-Shorting&amp;current%20rating=5%20A&amp;number%20of%20decks=2%20Deck&amp;number%20of%20positions=4%20Position" rel="nofollow noreferrer">Mouser search</a> and much to my surprise, the results of that search are listing up to almost $100.</p> <p>So - thought I'd ask for input from anyone that might be able to temper my logic and help make sure that indeed that is the type of switch I'd need to consider - or, if you'd offer a different suggestion. At this rate, I'm starting to cost more than buying something <a href="https://rads.stackoverflow.com/amzn/click/com/B0BGHMGY7J" rel="nofollow noreferrer" rel="nofollow noreferrer">off the shelf</a>.</p>

DIY guitar amp cabinet selector switch

2024-01-28T03:54:36.620

699199

|verilog|system-verilog|modelsim|questasim|tcl|

<p>You should set up your simulations so that output can be controlled by command line switch and <code>$value$plusargs</code> then there is no need to recompile your design if you want to change what gets printed. The UVM has greater print control than this.</p> <p>For example (leaving it to you to add better error checking)</p> <pre><code>realtime starttime, stoptime; bit printed; initial fork if ($value$plusargs(&quot;starttime=%g&quot;,starttime) begin $display(&quot;print starting at %t&quot;, starttime) #(starttime) printed = 1; end if ($value$plusargs(&quot;stoptime=%g&quot;,stoptime) begin $display(&quot;print stoping at %t&quot;, stoptime) #(starttime) printed = 0; end join </code></pre> <p>Then wrap all your printing with</p> <pre><code>if (printed) call_my_print_functions; </code></pre> <p>There are a few approaches people take to this verification problem</p> <ol> <li><p>Set up your simulation to run as fast as possible. Maximize optimization by turning off all access and dumping. Print out as little information as possible just enough to know that your test has passed or failed and what time in the simulation things started going wrong. Then go back and restart your simulation with the <code>printed</code> flag that turns the printing on at the needed time (use a command line $value$plusargs).</p> </li> <li><p>A variation of 1. is using checkpoint to save the entire state of the simulation at regular intervals. Then go back to the last checkpoint before you want to start printing data. Turn the flag on at the appropriate time when restoring the checkpoint. Since the $value$plusargs function got called at time 0, you'll have use a simulator command line option to set the <code>printed</code> flag.</p> </li> <li><p>Save the data you want printed to Questa's waveform database and use the Tcl <code>searchlog</code> command to print the data you want. You would have to write a Tcl script to format the data the way you want it.</p> </li> <li><p>Output the data you want printed in a compact binary form using whatever language you want (SystemVerilog/C/Python) to read the data back in and then print it the way you want.</p> </li> </ol>

<p>My simulation takes hours until it's stopped from my SystemVerilog code using <code>$stop;</code>.</p> <p>When it stops, to have proper information, I need to run a Verilog task/function at a certain time before it stopped. The function reads the memory and prints various information.</p> <p>Is there a way to do that?</p> <p>Otherwise, what would be the appropriate alternative?</p> <p>How do verification engineers debug such a situation?</p> <p>There is the <code>call</code> Tcl command, but it doesn't have the time parameter, and once the error has happened, it's too late. Maybe the <code>examine</code> Tcl command can be used?</p>

How can I run Verilog code with data at a specific time in the past?

2024-01-28T08:34:12.737

699200

|mosfet|sensor|i2c|low-power|

<p>One simple option would be to use an N-channel MOSFET as a switch to connect/disconnect the IC to/from Ground instead of VCC. Just make sure any pins that connect to ground only do so through the same switch</p>

<p>I have an I2C sensor connected to a microcontroller. The whole system is battery powered, so I need to find ways to switch off power from devices when they are not in use.</p> <p>For the sensor, I am thinking of using an IO Expander or something similar to disconnect the sensor from Vcc. But what to do with the I2C pins? They are pulled up with 10 kΩ resistors.</p> <p>Even though I am disconnecting the sensor from the power, there will be still current flowing through the pull-up resistors. Is there a way to also disconnect SDA and SCL pins, so that the sensor is not drawing any current at all when not in use?</p> <p>I am considering using MOSFETs as switches, but wondering if there are any standard solutions or best practices.</p>

Looking for circuitry to save power on an I2C sensor

2024-01-28T08:38:26.257

699214

|audio|adc|input|sine|teensy|

<blockquote> <p><em>Looking for suggestions on a balanced to unbalanced circuit that is capable of handling frequencies of 10 Hz to 20 kHz</em></p> </blockquote> <p>I could easily suggest a differential amplifier but, given that the power output <em>might</em> have considerable common-mode signals associated with it, I would favour an audio transformer from people like Hammond.</p> <blockquote> <p><em>Also, can I connect the input ground of the dc-dc converter to the com output?</em></p> </blockquote> <p>You won't need an isolating DC-DC converter with this method.</p> <p>If you insist on using op-amps, <a href="https://cdn.inmusicbrands.com/rane/pdf/old/mp2016_sch.pdf" rel="nofollow noreferrer">this is a decent mixer input for a balanced signal from Rane</a>. The following is an image of the specific section (microphone amplifier with an added 30 dB attenuator):</p> <p><a href="https://i.stack.imgur.com/g9EnJ.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/g9EnJ.png" alt="enter image description here" /></a></p>

<p>I'm building a prototype, checking the potential for a project.</p> <p>I want to be able to sample a sine wave from a power amplifier using a Teensy4 ADC.</p> <p>I have a Teensy 4.0 powering an Evisun isolated DC-DC module to generate +/-15v I have a full wave precision rectifier to eliminate any negative voltage on the output and increase digital range on the ADC (I don't need to recreate the sound, just need to capture the half cycles)</p> <p>My missing part is a differential input stage, where I can connect either a single ended output or a differential output amplifier, then feed the unbalanced output into the precision rectifier &gt;&gt; ADC and sample the half cycles.</p> <p>I need to have a voltage divider connected on each input to reduce up to 200v peak-peak down to 6v peak-peak.</p> <p>I'm looking for suggestions on a balanced to unbalanced circuit that is capable of handling frequencies of 10Hz to 20kHz.</p> <p>Also, can I connect the input ground of the dc-dc converter to the com output? I don't really need an isolated supply and used it just for low component count, and I need a ground reference for the ADC anyways.</p>

Input stage for sampling audio sine wave with ADC

2024-01-28T13:45:02.493

699221

|power-electronics|switch-mode-power-supply|feedback|error-amplifier|

<p>The TL494 PWM controller hosts two op-amps for controlling current and voltage. However, if the vast majority of CC-CV controllers (constant-current and constant-voltage) use ORed op-amps wired in an <em>inverting</em> configuration, the TL494, for an unknown reason, has its two op-amps configured in a <em>non-inverting</em> configuration which makes compensation an extremely unpleasant exercise. It is part of the response I gave on <a href="https://electronics.stackexchange.com/questions/655264/tl494-compensation/655483#655483">SE</a> and I released a <a href="http://powersimtof.com/Downloads/PPTs/NINV%20type%203.pdf" rel="nofollow noreferrer">PDF</a> you can download from my page. The <span class="math-container">\$RC\$</span> network you see on the schematic is linked to compensation of this converter but I suspect trial-and-error is behind this process.</p> <p>Regarding the UC384x and an optocoupler, I recommend to stay away from the application circuit you reproduced. The most reliable way is to <em>disable</em> the internal op-amp by grounding its FB pin. You then connect the COMP pin to the 5-V VREF pin via a given pull-up resistance - say 10 kOhms - and you connect the optocoupler from COMP and the GND pin of the IC:</p> <p><a href="https://i.stack.imgur.com/TbnTq.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/TbnTq.png" alt="enter image description here" /></a></p> <p>It important here to care about the PCB layout - sorry for the <em>crapCAD</em> schematic : ) the two copper traces from the optocoupler (FB and GND) go side-by-side and the emitter connects to the IC ground which is quiet: do not connect to a noisy point or the converter won't be stable. Same for the collector, go to the COMP pin and have the filter capacitor which introduces a wanted pole, wired very close to the IC. This is an industry-standard configuration that I have seen many times in ac-dc converters.</p>

<p>I am having a slight confusion regarding the selection compensation pin of the UC3842 IC and the current mode control system given in the datasheet.</p> <ol> <li>Why is there an RC combination at the feedback of the error amplifer? Can I simply use a resistor at that pin?</li> <li>Secondly as far as I have seen, the optocoupler will allow a current to flow in the right side only if the voltage gets below the threshold. But this will only give either a high or a low voltage at that pin. It wount give the amount by which the voltage got decreased or the real reference as is done in the <a href="https://www.ti.com/lit/ds/symlink/tl494.pdf?ts=1706424362432&amp;ref_url=https%253A%252F%252Fduckduckgo.com%252F" rel="nofollow noreferrer">TL494</a> IC where the IC gets a propper reference from the voltage divider as shown below. But here from getting either a high or a low how can we figure the measure of change of pwm duty cycle??</li> </ol> <p><a href="https://i.stack.imgur.com/LlmDq.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/LlmDq.png" alt="enter image description here" /></a> <a href="https://www.ti.com/lit/ds/symlink/uc3842.pdf?ts=1706433835393&amp;ref_url=https%253A%252F%252Fwww.ti.com.cn%252Fproduct%252Fcn%252FUC3842" rel="nofollow noreferrer">UC3842:</a> <a href="https://i.stack.imgur.com/QvV8m.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/QvV8m.png" alt="enter image description here" /></a> Kindly help me out in understanding these two concepts and the working of this IC with optocoupler. Considering I am using the voltage mode of the UC3842 IC. Here is a scehmatic of the changes made in the current and voltage mode control: <a href="https://i.stack.imgur.com/5eHhF.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/5eHhF.png" alt="enter image description here" /></a></p>

UC3842 optocoupler feedback confusion

2024-01-28T14:18:18.330

699225

|transfer-function|math|

<p>For realizable systems, complex poles always occur in pairs. For example, a second order transfer function can be written: <span class="math-container">$$ G(s)=\frac{N(s)}{s^2+a_1s+a_0} $$</span> Or factored into poles as: <span class="math-container">$$ G(s)=\frac{N(s)}{(s-p_1)(s-p_2)} $$</span></p> <p>If <span class="math-container">\$p_1\$</span> is complex then so must <span class="math-container">\$p_2\$</span> be the complex conjugate of <span class="math-container">\$p_1\$</span>.</p> <p>If a pole is complex, then its conjugate must exist, so the denominitor of the transfer function can be found as is shown in the OP. That's all this means.</p> <p>For higher order systems, each pair of complex poles will reveal a quadratic factor in the denominator.</p>

<p>This comes from Sedra's <em>Microelectronic Circuits</em>, example 17.1.</p> <p>If I have a transfer function with a pole <span class="math-container">\$p_1 = \omega_0(-0.1736 + j0.9848)\$</span>.</p> <p>The example talks about &quot;combining <span class="math-container">\$p_1\$</span> with its complex conjugate&quot;, becoming <span class="math-container">\$s^2+0.3472s + \omega_0^2\$</span>.</p> <p>By trial and error I found that this &quot;combining with its complex-conjugate&quot; assumes an expression <span class="math-container">\$s^2 + (p_1 + \overline{p_1})s + p_1 \overline{p_1}\$</span>. But I don't get what this combination means exactly and why it needs to happen here.</p>

Complex-conjugate poles from transfer function

2024-01-28T15:13:50.420

699228

|mosfet|power|batteries|usb|

<blockquote> <p>When the USB cable is attached the circuit should automatically switch off the battery input and start using 5 V from the USB.</p> </blockquote> <p>Your circuit will not work like that.</p> <p>When <code>VIN</code> is available, regardless of whether <code>VUSB</code> is available or not, the 5V regulator will see <code>VIN</code> through the PMOS DMG341 (either its body diode or its &quot;on&quot; resistance, R_DS-on) as per the connection shown:</p> <ul> <li>When <code>VUSB</code> is unavailable whilst <code>VIN</code> is available, the PMOS will be on so the regulator will see <code>VIN</code>.</li> <li>When <code>VUSB</code> is available whilst <code>VIN</code> is available, the PMOS will be off but the regulator will see <code>VIN</code> <strong>through the PMOS's body diode</strong>.</li> </ul> <blockquote> <p>The Zener diode that goes between the USB voltage input and the voltage regulator output</p> </blockquote> <p>It's not a Zener diode, it's a Schottky barrier diode.</p> <blockquote> <p>My understanding is that it is typically not recommended to have another voltage input attached to the output of a voltage regulator without a protection diode</p> </blockquote> <p>I don't know the 1117's design but I personally wouldn't apply an external voltage across a regulator's output, regardless of whether through a diode or directly. If 1117's series pass element is a PNP transistor (I really don't know, I just assumed so), for example, which means the output is taken from the collector, then the external voltage applied across the output will simply forward bias the CB junction when the regulator is off (i.e. no input). This may or may not result in an IC failure, I don't know. If you want to have the regulator output and the <code>VUSB</code> OR'ed then the simplest way is to connect them with OR'ing diodes:</p> <p><img src="https://i.stack.imgur.com/biZgw.png" alt="schematic" /></p> <p>^{<a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fbiZgw.png">simulate this circuit</a> &ndash; Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a>}</p> <blockquote> <p>... but I assume if the Arduino has gotten away with it then maybe it will work in this case and save me a component as well as the voltage drop over that diode.</p> </blockquote> <p>I've just checked the <a href="https://www.arduino.cc/en/uploads/Main/Arduino_Uno_Rev3-schematic.pdf" rel="nofollow noreferrer">R3's schematic</a>. When there's no power applied from the power input connector shown as X1^{<em>why would a designer name a connector with X anyway?</em>}, the <code>USBVCC</code> (USB 5V) will pass through T1 PMOS (FDN340P) body diode ^{<strong>1</strong>} and power LP2985 to generate 3.3V, also will be used as <code>+5V</code> for the rest of the circuit. Now the potential problem here is that the <code>USBVCC</code> might be supplying current into the regulator's output when the regulator is off. If this usage is allowed by the design/designer then that's fine, but I wouldn't do that.</p> <hr /> <p>^{<strong>1</strong>} The T1 is simply there just as a reverse-polarity protection. If the main intention is the disconnect the <code>USBVCC</code> when a DC input is available then simply it won't work like that.</p>

<p>I want to have a project be powered by six AA batteries or USB. When the USB cable is attached the circuit should automatically switch off the battery input and start using 5 V from the USB.</p> <p>This is the circuit I've come up with by copying component setups from the Arduino Uno R3 and an Adafruit Feather, the idea here being that when the USB power is connected it applies voltage to the MOSFET that then disconnects the battery from the voltage regulator.</p> <p>The Zener diode that goes between the USB voltage input and the voltage regulator output protects the USB from backfeed. In total my entire circuit that this supplies power to will use less than 500 mA.</p> <p>My understanding is that it is typically not recommended to have another voltage input attached to the output of a voltage regulator without a protection diode, but I assume if the Arduino has gotten away with it then maybe it will work in this case and save me a component as well as the voltage drop over that diode.</p> <p>If, however, I do need a diode there, what would be a good one to use?</p> <p><a href="https://i.stack.imgur.com/hAjZj.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/hAjZj.jpg" alt="enter image description here" /></a></p>

Will this battery to USB auto switching circuit work?

2024-01-28T16:03:56.793

699231

|pcb|kicad|trace|through-hole|

<p>Yes, it's fine.</p> <p>First, copper traces are etched.</p> <p>Then, green soldermask is applied everywhere except pads. It's a varnish that protects copper traces and prevents solder bridges and shorts.</p> <p>Then, white silkscreen (basically paint) is applied on top so you can see your component labels. It has no electrical function.</p> <p>So, traces that pass below the white component outlines (silkscreen) are not a problem at all, they just receive a bit of silkscreen ink on top. Unless:</p> <ul> <li>The trace carries high voltage (like mains), and you need a specific distance between the trace and components/other pads for isolation/creepage protection.</li> </ul> <p>For example if you use an optocoupler to isolate a part of the circuit from mains, your isolation/creepage distance is the width of the optocoupler. So usually you wouldn't route traces under it, because that would reduce the creepage distance.</p> <p>For low voltage stuff, no issue at all.</p> <ul> <li>Or the trace carries high frequency/high amplitude signals and could couple into a the sensitive input of an amplifier.</li> </ul> <p>Some notes:</p> <ul> <li><p>You need mounting holes in the 4 corners (pick your favorite screw, measure the head, make a pad with the same diameter as the head, and the hole 0.5mm wider than the screw)</p> </li> <li><p>Label the power supply connector: you can stick some text next to it like &quot;+5V&quot; &quot;GND&quot; next to the appropriate pins.</p> </li> <li><p>In prototype quantity, double sided boards usually cost the same as single sided boards, so go ahead and use both sides! You'll save a lot of time.</p> </li> </ul> <p>Also all your PCB is in red, which means it's on the top layer. If you order a single sided board without plated through holes, you won't be able to solder your components, because you won't have any pads on the bottom. But if you order a double sided board with plated through holes, it's fine.</p> <ul> <li>Placement:</li> </ul> <p>On the right you have 2 caps and a resistor that only connect to the chip in the middle. If they only connect to the chip, they should be close to the chip. This shortens traces, reduces the number of long traces, and thus the amount of work.</p>

<p>Will this work, knowing that I'm running traces across THT footprints?</p> <p>Kicad lets me do it, but will PCB manufacturers be able to print the board?</p> <p>On the other hand I had no other choice as I might also want to etch boards myself, so I had to keep it single layer.</p> <p><a href="https://i.stack.imgur.com/burLv.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/burLv.jpg" alt="enter image description here" /></a></p>

Running traces across THT footprints

2024-01-28T16:23:29.293

699237

|led|analog|photoresistor|

<p>Circuit below:</p> <p>Discharging path ensure two 10k resistors.</p> <p>The right PNP creates a monostable circuit to not stop fade if hand is out of LDR.</p> <p>470k trimpot sets the LDR trigger point according what LDR is used and light conditions around. Better use lower resistance LDR like 10k.</p> <p><a href="https://i.stack.imgur.com/Uv3Pj.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/Uv3Pj.jpg" alt="enter image description here" /></a></p>

<p>I'm making an interactive art project and I'd like to have an LED that turns on when someone puts their hand in front of a light sensor (photoresistor). I got that working. Next step is that I'd like to have the LED fade back to off after a second after it turns on.</p> <p>What I'm after is:</p> <ul> <li>When photoresistor goes from uncovered (low resistance) to covered (high resistance), turn LED on immediately, then fade to off over ~1 second.</li> <li>When photoresistor is not covered, the LED should be off.</li> <li>I don't care too much what happens if the photoresistor becomes uncovered while the LED is fading, but the best would be if it keeps fading to off.</li> </ul> <p>Here's my circuit attempt. It works the first time but there's no path to discharge the capacitor so it won't turn on a second time.</p> <p><a href="https://i.stack.imgur.com/luBTb.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/luBTb.png" alt="circuit attempt" /></a></p> <p>Can someone point me in the right direction?</p>

Shadow-triggered LED fade circuit

2024-01-28T17:01:45.443