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696740	\|microcontroller\|sensor\|low-power\|attiny\|photoresistor\|	<p>Sleep on the watchdog timer (or other low power timer) instead and then only power the photodetector at the end of each sleep.</p> <p>Connect the top of the photoresistor circuit to a GPIO so that you can power the circuit off.</p> <p><img src="https://i.stack.imgur.com/Zllkq.png" alt="schematic" /></p> <p><sup><a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fZllkq.png">simulate this circuit</a> – Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a></sup></p>	<p>I'm looking for a simple hack to minimise current when detecting change in light intensity using photoresistor. I'm using ATTiny85 in deep sleep (power down, ADC disabled, using below 1 microamp) waking by pin change (interrupt pin). After pin change ATTiny executes some operations and goes to sleep again. Device is powered with small battery and the battery should last for a year.</p> <p>The event that wakes microcontroller is change on pin PB3. PB3 is connected to ground by photoresistor. Everything works as expected. Change in light conditions wakes the microcontroller, and after some actions it goes to sleep again.</p> <p>The photoresistor, when it is dark, has 1 megohm resistance, so the current is minimal. But when it is sunny, the resistance falls below 10 kilohm, and the PB3 pin leaks above 50 microamps all day, even though the microcontroller is in deep sleep, not doing anything. I'm interested only in pin change, so after it gets sunny, and the low photoresistor resistance triggers PB3 I'd like somehow to block the current flow till the next change.</p> <p>Is there any simple circuit (possible using capacitor?) to achieve that?</p>	How to prevent photoresistor sensor from draining battery	2024-01-07T20:52:21.930
696745	\|operational-amplifier\|ldo\|differential-amplifier\|single-ended\|	<p>The one thing that I have encountered in the past, is oscillataion do to positive feedback through the common mid-point bias connections. I have shown one such positive feedback path in the diagram as a red line. If the gain around this loop is greater than 1, then it will oscillate.</p> <p>Look at pin 3 of U32A. A signal <3MHz on this pin will be multiplied by 11. So the rest of the path must attenuate by at least the same amount.</p> <p>You can find other such positive feedback paths on both schematic diagrams.</p> <p>If I am not mistaken, there is one long path from DCBIAS on U15A pin 3 through IFF+,through U32A Pin 3, and returning to DCBIAS through U32D Pin 12.</p> <p>There are 3 non-inverting gain sections for signals on this positive feedpack path totaling about 1700.</p> <p>This is likely the source of your oscillation.</p> <p>There is another source for oscillation. As the bias network grows, the capacitive load on an op-amp driver will increase. If the capacitive load is too great for the opamp, it will oscillate. Using a regulator instead may be better. Choose a regulator that can work with 10s of microfarad capacitance on its output.</p> <p><a href="https://i.stack.imgur.com/p5oOk.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/p5oOk.png" alt="enter image description here" /></a></p> <p>An op-amp used for mid-point bias must be able to handle all the ac current that must pass through the bias network.</p> <p>An LDO regulator can sink current only through its output capacitor so may not be appropriate either.</p> <p>Even if a perfect source is available, the inductance and resistance of the bias distribution network (BDN) will cause the voltage to bounce depending which way the current passes.</p> <p>To correct this problem, the positive feedback loops must be broken or decoupling applied at each tap from the BDN. Both these methods are shown below.</p> <p>In Figure 1. R1,C1 and R2,C2 decouple the OA1 and OA2 respectively from the BDN and from each other, But there is still a hardwired connection between each stage.</p> <p>In Figure 2, The voltage dividers provide a local bias voltage while the capacitors provide an ac ground. The stages are completely separate from each other so cannot interfere with each other. The voltage dividers each can be buffered with an op-amp if necessary, but usually just the bypassed voltage divider is enough. You may not need the capacitor depending on configuration.</p> <p>I have used both methods successfully and prefer the method in figure 2.</p> <p><img src="https://i.stack.imgur.com/0mTNS.png" alt="schematic" /></p> <p><sup><a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2f0mTNS.png">simulate this circuit</a> – Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a></sup></p>	<p>First schematic below is the initial gain stage of the intermediate signal generated by mixer of radar. It is passed through sallen key high pass filter.</p> <p><a href="https://i.stack.imgur.com/yYTOm.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/yYTOm.png" alt="Initial gain and sallen key high pass filter" /></a></p> <p>Second schematic for differential to single ended conversion with some gain. And then another stage with digital potentiometer for adjusting the gain with a microcontroller.</p> <p><a href="https://i.stack.imgur.com/isd9o.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/isd9o.png" alt="Second part of the circuit" /></a></p> <p>At last stage i need to convert signal back to differential for driving the SAR ADC. I have found 2 reference designs from links below and converted accordingly.</p> <p><a href="https://www.mouser.com.tr/datasheet/2/609/ADA4807_1_4807_2_4807_4-3119636.pdf" rel="nofollow noreferrer">Page 28 of the datasheet for single to differential convertion</a></p> <p><a href="https://www.analog.com/en/technical-articles/adc-driving-single-ended-to-differential-conversion.html" rel="nofollow noreferrer">Single to differential convertion reference 2</a></p> <p>ADC range is 0-3.3V and DC Bias should be around 1.65V.</p> <p>My questions are:</p> <ol> <li><p>Is this design correct, especially the second schematic. When you check the stages, is there any problem that i could not see such as wrong conversion, wrong dc bias apply or connection etc. For example can i directly connect pin 14 of the ADA4807 to pin 5.</p> </li> <li><p>For DC Bias generation, can i simply use a LDO regulator with high PSRR. I had oscillation problems when i generated DC Bias with op-amp voltage follower.</p> </li> </ol> <p><a href="https://www.mouser.com.tr/datasheet/2/609/ADA4807_1_4807_2_4807_4-3119636.pdf" rel="nofollow noreferrer">ADA4807 Datasheet</a></p> <p><a href="https://www.analog.com/media/en/technical-documentation/data-sheets/623012fc.pdf" rel="nofollow noreferrer">LT6232 Datasheet</a></p> <p><strong>Later Update for further details of the system:</strong> For radar, a closest target at 1 meter distance will reflect 1 to 3 kHz 0.05-0.1V IF signal but the signals coming from further targets are a lot weaker down to microvolts. The reason of the high pass sallen key is that distant target will reflect microvolt level signal therefore it is like a noise on closer target. When 40 dB/dec high pass filter is used, the closer signals will become weaker meaning lower amplitudes (fc = 400 kHz, Q = 0.5, damp = 1 for this setup because radar cannot see beyond 200-250 meters but it can be changed for higher cutoff later). This is the end of first schematic. Overall we amplified signal and prepare it for filtering. After the high pass filter section the signal is compensated but still needs a lot more amplification because after first gain stage filtering decreased amplitudes.</p> <p>Higher sampling rate improves SNR performance along with differential input thats why i kept it differential, but converting single ended would be easier in case of number of components as well. Sampling will be around 3.3 to 5.6 MHz (higher sampling and down sampling is better. It will be certain according to the USB throughput). For now it will be 3.3 MHz sampling rate.</p>	Single Ended to Differential Conversion with Opamp and Correct DC Biasing Method	2024-01-07T22:34:25.880
696751	\|single-supply-op-amp\|input-bias-current\|	<blockquote> <p>What happens is when I connect a battery (or power supply) to VBAT, somehow that voltage is makes its way to the V+ pin</p> </blockquote> <p>It sounds like you are expecting no voltage on V+ (because the 5v rail is off in shutdown mode), but there is. This is likely because you are operating the op amp outside of the absolute maximum ratings. From the datasheet, the voltage on an input pin should never exceed 0.2v + V+. In this case you are exceeding it by 3v.</p> <p>To fix this, you could disconnect the inputs to the op amp when in shutdown, or, if possible for your application, power it directly from the battery.</p>	<p>I've built this exact circuit here, except for one variation: SHDN is connected via a 10K resistor to ground. The opamp should be off!!!</p> <p>What happens is when I connect a battery (or power supply) to VBAT, somehow that voltage is makes it way to the V+ pin, which is connected to 5V (turned off ATM, I'm only focusing on Vin rn). If I connect a 100k resistor between 5V and GND, the circuit draws about 200uA when 3V is on VBAT. SHDN is at GND, the output is also at GND.</p> <p>What on earth is happening here? This opamp is supposed to have an input bias current in the pA range. How is the input "getting through" the chip?</p> <p>This is very important because this is a battery powered device, and I need uA of consumption when the circuit is off, not in the 100s.</p> <p>The only ideas I've found from google so far are more decoupling (I tried adding 2x 10uFs, same problem) or that the input impedance was too high...</p> <p><a href="https://i.stack.imgur.com/TQyIg.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/TQyIg.png" alt="enter image description here" /></a></p>	Noninverting input voltage seen on V+ pin of OpAmp	2024-01-08T00:34:53.393
696767	\|transformer\|inductance\|	<p>For a two- or three-element resonant tank having at least one L (e.g. LCC or LLC), it doesn't matter how you obtain the L.</p> <p>For an LLC series resonant converter, for example, the resonant inductor (namely Lr) is the combination of the transformer's primary leakage and the external inductance (if there's any). If you calculated the required Lr as, say, 20 uH and the xfmr's primary leakage is 5 uH then you can place an external 15 uH in series.</p> <p><img src="https://i.stack.imgur.com/al8Ly.png" alt="schematic" /></p> <p><sup><a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fal8Ly.png">simulate this circuit</a> – Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a></sup></p> <p>Or, you can design your transformer so that it has a leakage of 20 uH.</p> <p><img src="https://i.stack.imgur.com/JV7Yi.png" alt="schematic" /></p> <p><sup><a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fJV7Yi.png">simulate this circuit</a></sup></p>	<p>I know that the leakage inductance is present due to the imperfect linking of flux between the two transformer windings. I have selected a core for the transformer to be used within a series resonant converter.</p> <p>Using FEMM, I have simulated the transformer core along with the windings to get some idea about the leakage inductance for the transformer. I have calculated the leakage inductance value from the simulation results to be about 7 μH.</p> <p>In this case, if I require a leakage inductance value of about 100 μH for the SRC to work for my application, can I keep an external inductor in series with the transformer primary to get the required value? If this is not possible, are there any other ways to achieve the required inductance value?</p> <p>I am trying to implement a PCB transformer in this case, as inter-winding isolation is important.</p>	Leakage inductance in a series resonant converter	2024-01-08T04:53:37.867
696774	\|circuit-analysis\|passive-networks\|stability\|nodal-analysis\|	<p>My statement is incorrect. Consider the following <span class="math-container">\$LC\$</span> circuit under sinusoidal input: <a href="https://i.stack.imgur.com/UpU1O.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/UpU1O.png" alt="enter image description here" /></a></p> <p>KVL states:</p> <p><span class="math-container">$$V(t) = V_c(t) + V_l(t)$$</span> <span class="math-container">$$V(t) = \frac{q}{C} + L \frac{di}{dt} \implies V'(t) = A\sin(\omega t) = Li''+\frac{i}{c}$$</span></p> <p>The general solution to ODE is:</p> <p><span class="math-container">$$i(t) = i_h(t)+i_p(t)$$</span></p> <p><span class="math-container">\$i_p(t)\$</span> is of the form <span class="math-container">\$C_1 \sin(\omega t) + C_2 \cos(\omega t)\$</span></p> <p>and <span class="math-container">\$i_h(t)\$</span> is of the form <span class="math-container">\$C_3 \sin(\omega_x t) + C_4 \cos(\omega_x t)\$</span>,</p> <p>where <span class="math-container">\$\omega_x ^2 = \frac{1}{LC}\$</span>.</p> <p>Thus,</p> <p><span class="math-container">$$i(t) = C_1 \sin(\omega t) + C_2 \cos(\omega t) + C_3 \sin(\omega_x t) + C_4 \cos(\omega_x t)$$</span></p> <p>which is not the sinusoid of the same frequency as input.</p> <p>The requirement about having a resistor is still not sufficient since we can have a resistor in parallel like that:</p> <p><a href="https://i.stack.imgur.com/XO1ge.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/XO1ge.png" alt="enter image description here" /></a></p> <p>which wouldn't change anything.</p> <p><strong>In fact, this circuit is not even BIBO stable!</strong> That is because we can choose the circuit paramenters to cause resonance.</p>	<p>I conjecture that any <span class="math-container">\$RLC\$</span> circuit with <span class="math-container">\$n \ge 0\$</span> independent sinusoidal voltage sources of the same frequency is exponentially stable.</p> <p><strong>How to prove this or if this is not true, how to modify the condition and prove the corresponding result?</strong></p> <p>I find the general characteristic polynomial's roots not so easy to analyze to show that all of them have negative real parts.<br /> Having an answer to <a href="https://electronics.stackexchange.com/questions/696718/how-to-derive-an-ode-for-a-general-n-th-order-lti-circuit">this question</a> would surely help, but I'd like to see any other approach, desirably as many other rigorous approaches as possible.</p> <p>I tried to form a general system of ODEs using voltage node method as follows:</p> <p>Say we have a reference node <span class="math-container">\$0\$</span> and nodes <span class="math-container">\$v_1, ... v_n\$</span>. Consider an arbitrary node <span class="math-container">\$v_k\$</span>. The equation for it will go into <span class="math-container">\$k\$</span>-th row of the system matrix.</p> <p>Define the following functions used to represent the currents:</p> <p><span class="math-container">$$f_R(R, v) = \frac{v}{R}$$</span> <span class="math-container">$$f_c(C, v) = C\frac{dv}{dt}$$</span> <span class="math-container">$$f_L(L, v) = \frac{1}{L}\int v dt$$</span> <span class="math-container">$$f_0(0, v) = 0$$</span></p> <p>Then, using KCL, the <span class="math-container">\$k\$</span>-th row will be:</p> <p><span class="math-container">$$-f_{\text{component_type}_1}(\text{component_type}_1, v1), \ ... \sum_{\text{component_type_i}} f(\text{component_type_i}, v_k), \ ...-f_{\text{component_type}_n}(\text{component_type}_n, vn), \ \sum_{i = 0}^m x_i$$</span>,</p> <p>where component types <span class="math-container">\$\in \{R, L, C, 0\}\$</span> depending on which component is directly connected between nodes <span class="math-container">\$v_i\$</span> and <span class="math-container">\$v_k\$</span> and <span class="math-container">\$x_i\$</span> are the sinusoidal sources connected directly to <span class="math-container">\$v_k\$</span>.</p> <p>The main difficulty in analyzing such a system is its generality. In order to eliminate the integral in <span class="math-container">\$f_L\$</span> functions I would have to differentiate the equation, but since I don't know whether the inductor is present or not, I have to differentiate all the equations, which further complicates the analysis.</p>	Exponential stability of a general \$RLC\$ circuit with sinusoidal input	2024-01-08T06:45:30.243
696785	\|identification\|winding\|	<p>It's a deflection yoke, here is a picture of a similar tube yoke in this question:<br /> <a href="https://i.stack.imgur.com/ED076.png" rel="noreferrer"><img src="https://i.stack.imgur.com/ED076.png" alt="enter image description here" /></a><br /> From: <a href="https://electronics.stackexchange.com/questions/628701/why-are-the-vertical-deflection-coils-in-a-crt-deflection-yoke-so-different-from">Why are the vertical deflection coils in a CRT deflection yoke so different from the horizontal coils?</a></p>	<p>I found this thing in a heap of stuff to be dismantled for recycling. There is a flanged chassis with winding wire rising up the wall, going along the rim, and diving back down, all this duplicated on the other half of the circumference. There is also a second layer of winding below that seems to wrap under itself at the rim without following the circumference.</p> <p>Was it some kind of motor, or perhaps a piston loudspeaker?</p> <p><a href="https://i.stack.imgur.com/N9M6c.jpg" rel="noreferrer"><img src="https://i.stack.imgur.com/N9M6c.jpg" alt="enter image description here" /></a></p>	What is this flange with wire windings in a conical / horn shape?	2024-01-08T09:00:19.860
696791	\|stm32\|usb\|uart\|	<p>With a USB UART bridge, you can see the virtual COM port in your PC and communicate with it, even if there is no firmware on MCU.</p> <p>Also the MCU then does not need firmware that supports USB in any way and can simply communicate with UART.</p> <p>Which means that since the F103 does not support DFU with factory bootloader, you are forced to write your own firmware and/or custom bootloader that supports USB enough to be able to update the firmware portion.</p> <p>The factory bootloader does support UART so with a USB to UART chip, you don't need any special custom firmware or bootloader, as you can simply boot (somehow, maybe with a button) into factory bootloader and program the MCU, and you are never locked out of the system.</p> <p>However, using the MCU USB interface allows you to present itself as any device you want, such as keyboard, mouse or mass storage, etc, which isn't possible through the USB UART chip.</p> <p>So it really depends what you want to do. If you don't use the USB for anything else than uploading new firmware, then you need to develop software yourself that you trust has no bugs when you upload the firmware. And then you need to implement the PC side too if you use your own custom protocol. This is something you don't need at all if you put a hardware USB UART chip there.</p> <p>The other option is also not to use the F103. If you use an STM32 which supports USB in the factory bootloader, then you don't need the USB UART chip and can upload with existing GUI tools.</p>	<p>I've been doing some research over the last few days into implementing usb communication protocol on the stm32. I know that the stm32 has dedicated pins for USB communication, however I still see a lot of designs using a UART-USB bridge despite the existence of these pins. I haven't been able to find much in the way of what the advantages/disadvantages of using a UART-USB bridge is vs just using the USB pins directly. If it makes a difference, for my application I am planning just to use the USB port for programming after the initial bootloader is uploaded, however I am considering making an GUI that goes with this circuit at some point. For the design I am using a STM32F103RCT6</p>	Using UART/USB Bridge vs straight USB stm32	2024-01-08T09:31:31.170
696811	\|operational-amplifier\|protection\|pspice\|current-sink\|	<p>There's a clue in the 72.73 μA flowing into R2 (330 kΩ): -</p> <p><a href="https://i.stack.imgur.com/O8j4i.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/O8j4i.png" alt="enter image description here" /></a></p> <p>That current and that resistance implies a voltage source of 24 volts somewhere in your circuit and, hey-presto, there it is on the 2nd and 3rd diagram: -</p> <p><a href="https://i.stack.imgur.com/AK3Ka.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/AK3Ka.png" alt="enter image description here" /></a></p> <p>So, it seems to me that the current you see running into your supply is negative and this should be no surprise given the 24 volts at the input. It's likely that PSPICE calculates the currents at the initial point (rather than waiting for everything to settle down.</p> <blockquote> <p><em>How can I prevent this in Pspice?</em></p> </blockquote> <p>If it's a problem then you have to redesign your circuit. It isn't a PSpice problem that requires some kind of PSpice fix.</p>	<p>In an ideal world, most power supplies have a current sourcing feature but not a sinking feature. In this circuit, you can see that the 15V supply is sinking current. How can I prevent this in Pspice?</p> <p><a href="https://i.stack.imgur.com/tGpZ4.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/tGpZ4.png" alt="enter image description here" /></a></p> <p><a href="https://i.stack.imgur.com/Ragq9.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/Ragq9.png" alt="enter image description here" /></a> <a href="https://i.stack.imgur.com/EX2h2.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/EX2h2.png" alt="enter image description here" /></a></p>	PSPICE non sinking voltage source	2024-01-08T13:42:26.833
696812	\|arduino\|mosfet\|pcb-design\|routing\|	<p>Looks like your etching is incomplete and it has left some 'whiskers' between traces. There may be more (I think I see the 9V too, but maybe the input power has burned that out):</p> <p><a href="https://i.stack.imgur.com/YtIQo.jpg" rel="noreferrer"><img src="https://i.stack.imgur.com/YtIQo.jpg" alt="enter image description here" /></a></p>	<p><strong>Background</strong></p> <p>I'm making a heat sealing machine. The mechanical side is all OK but the electronics is challenging me. Here's the gist of the setup. I've put it all in the image below. Apologies for the rather unconventional circuit diagram... <a href="https://i.stack.imgur.com/TKd0s.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/TKd0s.png" alt="enter image description here" /></a></p> <p><strong>The Target</strong></p> <p>I need to make a PCB that has all the components together with the Arduino Nano - everything soldered on one board -- so that I can install it in my machine.</p> <p><strong>What works so far</strong></p> <p>I have built the circuit on a breadboard. It works great, so the circuit itself and the Arduino code is functional (as is the PID algorithm).</p> <p><strong>The problem</strong></p> <p>After testing on a breadboard, naturally the next step is to translate it to a PCB.</p> <p>Using Altium CircuitMaker, I have made the circuit and routed it as in the image below. Here is the schematic <a href="https://i.stack.imgur.com/Z4rD2.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/Z4rD2.png" alt="Circuit schematic design" /></a></p> <p>and here is the routed PCB. <a href="https://i.stack.imgur.com/JWT2f.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/JWT2f.png" alt="PCB Routing" /></a></p> <p>After transferring, etching and soldering, I have found that the circuit does not work. It actually burnt the regulator on my Nano and fried it but I am unable to tell why this is happening. This is even before I attach the external 15V supply for the higher power part of the circuit. It literally burns out even when I put the 9V into Vin.</p> <p>I'm using a single-sided copper clad board for my PCB so I am limited to a single conductive surface. My transfer mechanism is also rather coarse, so I'm sticking with 70mil pads and 40mil traces.</p> <p>Here are some images of the final board <a href="https://i.stack.imgur.com/U9Smx.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/U9Smx.jpg" alt="Final soldered board" /></a></p> <p>And here's the solder side of the PCB <a href="https://i.stack.imgur.com/LqX3X.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/LqX3X.jpg" alt="enter image description here" /></a></p> <p><strong>Where I'd like some help</strong></p> <p>I'd like to learn what's wrong with my board routing, and anything else that I'm doing wrong from a circuit-making perspective, that's preventing my circuit from operating correctly.</p> <p>I'm a little stumped because I have routed everything as in the breadboard version of the circuit, but it doesn't work. I suspect there is something seriously wrong with how I've routed the board, but I have no idea what it could be. I just don't have the knowledge.</p> <p>Happy to share the CircuitMaker files and Arduino code if necessary.</p>	Arduino Nano in PCB for a controlled heating rig - Can't get it to work	2024-01-08T13:46:32.090
696813	\|clock\|555\|timer\|switching\|breadboard\|	<p>Feed your control signal to the reset pin (assuming the control signal is 0 V to +5 V).</p> <p>You don't need that 10 uF cap connected to the output.</p> <p>Obviously you need to disconnect the reset pin from Vcc first.</p>	<p>I'm making a clock signal for my circuits, and I'm utilizing the 555 timer for this. I made this circuit below which outputs a clock signal. And now I'm trying to figure out how can I add on and off state on it.</p> <p>I want the clock turn on when a constant high input is in and turns off when it is low (kind of like a switch).</p> <p>Below is the schematic I made.</p> <p><a href="https://i.stack.imgur.com/6XeNJ.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/6XeNJ.jpg" alt="enter image description here" /></a></p>	Adding on and off state in a 555 timer clock circuit	2024-01-08T13:47:56.830
696840	\|bjt\|power-dissipation\|base\|	<blockquote> <p>maximum <strong>emitter-base</strong> voltage is specified as 4.0V</p> </blockquote> <p>This is not the same as <strong>base-emitter</strong>. <em>The order of the words matters</em>. The first word is the terminal with the higher potential.</p> <p>You never have a situation where emitter-base voltage goes positive (where the emitter is higher than the base), much less where it would go positive enough to be 4V positive. If you expect large negative transients on the return line then a reverse diode connected from emitter to base will do the job of protecting the B-E junction from reverse breakdown.</p> <p>The base-emitter voltage is limited by the base junction forward diode drop. It will be well below 1V in your application, but again - that's not specified anywhere, since the B-E junction acts like a nice silicon junction diode.</p> <p>There's another <a href="https://electronics.stackexchange.com/q/696413/10810">question that is based on the same misunderstanding</a>. See the answers to it as well.</p>	<p>I have a functional circuit designed for return line reverse protection, and a relevant portion of the circuit is shown below:</p> <p><img src="https://i.stack.imgur.com/QNq9Z.png" alt="schematic" /></p> <p><sup><a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fQNq9Z.png">simulate this circuit</a> – Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a></sup></p> <p>In this circuit, I anticipate that when +28V is connected to the return line, it will turn on Q1, causing point B to be at 0.7V. However, if point A is at 28V, point B would theoretically be 2 * 28V = 56V. Although the transistor (Q1) stabilizes point B to 0.7V, there is still dissipation heat generated that could potentially damage the transistor. According to the <a href="https://www.diodes.com/assets/Datasheets/MMBTA05_MMBTA06.pdf" rel="nofollow noreferrer">MMBTA06</a> datasheet, the maximum emitter-base voltage is specified as 4.0V, which suggests that Q1 might be at risk of failure. Surprisingly, despite this, Q1 does not blow up. Upon consulting my teacher, he indicated that the use of 0805-sized resistors R3 and R2 may be preventing any issues. But it does not make sense to me. Please advise.</p>	Maximum voltage applied to the BJT base	2024-01-08T17:22:49.243
696848	\|ground\|transmission-line\|isolated\|medical\|	<p>Medical Device Standards like IEC-60601 require special considerations regarding the Means of Patient Protection (MOPP) and Means of Operator Protection (MOOP). In general a "first fault" tolerance is required. E.g., if one Isolator breaks down the second one is required to withstand the full load AND the second measurement failure has to be very unlikely in that case (Mean Time Between Failures -MTBF) or the first fault needs to be reliably detectable and lead to a safe state. Another concern is the Leakage Current. Depending on the application this current can be very low (<100 µA). The idea is that such devices can be coupled directly to your cardiovascular system (type BF devices) and even small currents can be deadly. If all devices connected to a patient (and the so called patient environment) is floating, a fault of one devices is no issue as the other devices provide enough isolation to limit the current. However, if a grounded device is present device failure can be deadly. Those are (some) reasons why many medical devices are required to be floating.</p> <p>Besides the advantage that grounding the device housing is an easy way to prevent a "silent" fault, where a live wire connects to a touchable part, posing a potential life thread, there is another less obvious benefit: superior EMI/EMC behaviour. EM radiation typically occurs if parts are not properly grounded and potential differences across gaps form antennas. Guess that happens if one builds an isolation circuit - you will design a very nice antenna. In this case the usual approach is to increase the GND coupling/virtually close the gap using e.g. decoupling caps across the isolation. However, those caps will increase your (AC-coupled) leakage current, making it hard to meet the max allowed leakage current. It can take several iterations to balance EMI/EMC behaviour against the isolation requirements and even plugging in a slightly different cable or device can change everything - I heard stories of tests passing/failing tests depending on wether the notebook's charger is plugged in.</p> <p>TL;DR: To the best of my knowledge, grounded housing is a very lean way to get fault detection and less EMC/EMI trouble, while floating devices allow for more fault tolerance but require much more effort and restrictions.</p>	<h2>Introduction</h2> <p>I try to make more sense of safety and reliability of grounded and isolated electricity. I divided the problem into 3 stages:</p> <ol> <li>Power-transmission line</li> <li>Household electricity</li> <li>Electrical appliances</li> </ol> <p>From my understanding high-voltage transmission lines are isolated with over-head earth ground that acts like a lightning rod. The three phases are floating relative to earth ground (3 hot phases).</p> <p>Before going to household, the electricity passes a 3-phase step-down transformer which introduces a common neutral wire (cold) which is connected to a ground rod at the transformer.</p> <p>Then at the household, we have line and neutral which is selected from one of the phases, then we have a ground therminal that connects to the ground rod at the house. In some country, neutral also connected to ground at the consumer unit.</p> <p>As compliance should be safe to touch or shock-proof, the metal case of appliance must be connected to earth ground to ensure that electric potential always equals to ground and human body.</p> <p>Neutral should be connected to ground at the transformer's location because if not, the lightning might pass through the AC wire to appliances' ground potential. With neutral connected to earth, this lightning can bypass to ground at the transformer without much damage to appliances.</p> <p>In my country's standard, neutral must connect to the earth therminal to make a high-current return path in case that the line voltage leaks to appliances' metal casing so the breaker can trip.</p> <h2>Question</h2> <p>If an isolated system is power or more reliable, why can't we just make a household's system isolated by disconnecting neutral from earth ground? Will it work the same way as isolated power?</p> <p>*note: I've edited the question to be more focused, the question is only on but it required some explanation in each cases.</p> <h2>Reference</h2> <ol> <li>Application of isolation transformer in biomedical devices.</li> </ol> <p><a href="https://i.stack.imgur.com/WXxzk.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/WXxzk.png" alt="Application of isolation transformer in biomedical devices" /></a></p>	Safety of grounded and isolated AC in medical systems	2024-01-08T18:31:30.757
696854	\|inductor\|	<p>The inductor acts against a change in current. For an ideal step change, i.e. a forcible change of current in no time, the resulting voltage is infinite.</p> <p><span class="math-container">\$V = L \cdot \frac{\Delta I}{\Delta t} \qquad[Volt;Henry;\frac{Amper}{second}]\$</span></p> <p>For a finite slope of current over time, you get a finite voltage.</p>	<p>When there is an initial change in current, I understand that the inductor resists the change. but how does it eventually give in with the flow of current? can someone give me the nuances of the working of the inductor?</p>	Inductors - understanding the depth of its working	2024-01-08T20:00:30.563
696858	\|transmitter\|	<p>You have made several errors, not all of which contribute to your wrong answer</p> <blockquote> <p>The output IP3 is the third-order intercept point, which is the input power level at which the third-order intermodulation distortion (IM3) products are 30 dB below the main tones.</p> </blockquote> <p>The output IP3 is the power level at which an IM3 component is equal to one of the main signals, not 30 dB below.</p> <p>It's worth correcting this, even though it doesn't contribute to your error, as you then give the correct formula for IP3</p> <p><span class="math-container">$$OIP3[dBm] = P1 [dBm] + \frac{\Delta P [dBc]} {2} = 62.5 dBm$$</span></p> <p>Having given the correct formula, when you evaluate it, 30 dBm creeps in again instead of the actual P1, which for two equal tones with a total power of 20 dBm is 17 dBm.</p> <p>Using the correct P1 gives the book answer</p> <p><span class="math-container">$$OIP3 = 17dBm + \frac{65 dB} {2} = 49.5 dBm$$</span></p>	<p>The following is a tutorial question from my teacher.</p> <blockquote> <p>A transmitter requires the IM3 products to be -65dB below the main tones when the total output power is 20 dBm. Calculate the output IP3 of this transmitter.</p> </blockquote> <p>This is what I think.</p> <p>The output IP3 is the third-order intercept point, which is the input power level at which the third-order intermodulation distortion (IM3) products are 30 dB below the main tones. In this case, the IM3 products are -65 dB below the main tones,</p> <p><span class="math-container">$$OIP3[dBm] = P1 [dBm] + \frac{\Delta P [dBc]} {2} = 62.5 dBm$$</span></p> <p><span class="math-container">$$OIP3 = 30dBm + \frac{65 dB} {2} = 62.5 dBm$$</span></p> <p>But the book give me 49.5 <span class="math-container">\$dBm\$</span>.</p>	Calculate the output IP3 of this transmitter	2024-01-08T21:06:25.780
696863	\|telephone\|	<p>Telephones are two wire appliances that are grounded only at the exchange end.</p> <p>A hold-music circuit could go something like this:</p> <p><img src="https://i.stack.imgur.com/Hqrul.png" alt="schematic" /></p> <p><sup><a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fHqrul.png">simulate this circuit</a> – Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a></sup></p> <p>The resistor will probably get hot so use a 2W part (or 4 half watt 150 ohm resistors in series etc.)</p> <p>600 ohms is a guess, measure the current and voltage during a call to get a more precise value.</p> <p>"Music source" should be at approximately headphone power level.</p> <p>This is not the best solution it is just the simplest.</p> <p>There are laws about connecting equipment to the telephone network. Sometimes these are protectionism to stifle competition and innovation, but usually they are there to stop people from connecting dangerous equipment to the network that could harm phone company equipment and employees. If you connect something that behaves very much like a telephone and is safe no-one will care.</p>	<p>We have retro rotary telephones, and I'd like to make a hold button for the one in my office in the UK. This is literally a "ye olde rotary phone" (1940s) made from bakelite</p> <p>I have fairly basic electronics skills but I don't actually know how the phone works, in that sense anyway.</p> <p>Is this just a case of switching out the circuit to one playing "The girl from Ipenema" or is it more complicated than that?</p> <p>For example, what is it that keeps the line open if I make an outgoing call? Could I accidentally cut the call or does the line need to go open circuit to do that? What are the voltage limits?</p> <p>(I would just buy one, but can't find any!)</p> <blockquote> <p>[UPDATE]</p> <p>Some good points have been made in the comments that bear highlighting.</p> <p>When I used to work in a shop repairing computers (about 40 years ago) we also sold telephone handsets to the public; the ones with green stickers were allowed to be connected to the phone network, the ones without - or with red stickers - were not. I'm pretty sure the same or similar system exists today, especially with digital exchanges, "digital voice" etc.</p> <p>So, to be clear, nobody should be connecting unauthorised equipment of any kind to the telephone network.</p> </blockquote>	Hold button for UK Landline telephone	2024-01-08T22:27:18.857
696864	\|transistors\|circuit-design\|diodes\|boolean-algebra\|	<p>This circuit will light the respective LED when current is flowing through the respective 14.5Ω resistor, typically turning on about 1/2 of the expected current. In other words, if the resistors are less than about 28 ohms you can expect the LEDs to light when the switches are 'on'.</p> <p><img src="https://i.stack.imgur.com/FVEOO.png" alt="schematic" /></p> <p><sup><a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fFVEOO.png">simulate this circuit</a> – Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a></sup></p> <p>It uses a single 8-pin DIP integrated circuit dual op-amp. I don't think the circuit can be much simpler. You should connect a bypass capacitor of 100nF across and near the op-amp supply pins.</p> <p>Vr is about 40mV and the resistors R1/R3 drop about 80mV when the switches are 'on'. R1 and R3 are low resistance so they waste very little heat and can be small parts.</p>	<p>I'm a newbie in electronics and just recently decided to get some deeper knowledge and try to start some projects. But it didn't take that long before I became stuck. Here's my problem.</p> <p>I want to design a circuit with 12DC output that will be connected to two loads in parallel and each load would have its own signal LED diode. This diode will light up if everything works correctly and be off in case of a open circuit. I was thinking about using transistors or making some sort of a logic gate but I'm not sure how to continue: <a href="https://i.stack.imgur.com/RgKyy.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/RgKyy.png" alt="enter image description here" /></a> I came up with this diagram, R1 and R2 being the loads that use 10W (so there needs to be 14.5ohm resistance in the circuit, right?). But curcuitlab doesn't even think that's a valid circuit (neither do I, haha)</p> <p>So could you please help me understand how to make that circuit work? Also that would be an option only for an open circuit, for a short circuit fault would something like a fuse be an appropriate solution? Thanks</p>	How to limit current for this LED in circuit with a load?	2024-01-08T22:33:50.570
696897	\|voltage-regulator\|	<p>Vref is a voltage reference inside the IC. It fixes the voltage between OUT and the ADJ pin to 1.25 V, regardless of Vin. You can use Vref to manipulate the voltage on the ADJ pin through the feedback network provided by R1 and R2.</p> <p>For regulation, you should use the formula:</p> <p><code>Vout = Vref (1 + R2/R1)</code></p> <p>where Vref is 1.25 V and R1 is 120 Ω (or something between 100 Ω and 200 Ω)</p> <p>For example, if you set R1=120 Ω and R2=240 Ω you will get the following output voltage:</p> <pre><code>Vout = 1.25(1+240/120) = 3.75 V </code></pre> <p>The second part of the long formula in the datasheet can be ignored, as it explains, because Iadj is in the order of microamps, so very small.</p> <p>So, with ADJ tied to GND you would get 1.25 V in Vout. But with the voltage divider you force a higher value in Vout that, once divided, matches with the 1.25 V difference between both pins. It's a feedback system to increase Vout and it doesn't depend on Vin, because of the internal absolute voltage reference.</p>	<p>I am using two 5V 1W voltage sources in parallel and I want to regulate the output to 3.3V using an LD1117. I need help calculating the R2 value for the LD1117.</p> <p>I have read the datasheet linked below but I find it confusing. How do I calculate the value for R2, given that R1 is 120 Ohm?</p> <p>I know it is described in the datasheet but I do not understand Vref.</p> <p><a href="https://i.stack.imgur.com/CtF3q.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/CtF3q.png" alt="enter image description here" /></a></p> <p><sup>Source: <a href="https://www.st.com/resource/en/datasheet/ld1117.pdf" rel="nofollow noreferrer">LD1117 Datasheet</a></sup></p>	5V to 3.3V LD1117 voltage regulator design	2024-01-09T06:55:33.183
696910	\|rf\|	<blockquote> <p>But how can we know reason 9.6[dB] from this graph?</p> </blockquote> <p>That comes from heavy math and approximations using <a href="https://en.wikipedia.org/wiki/Taylor_series" rel="nofollow noreferrer">Taylor expansion</a>.</p> <p>I will not do the entire math here but here's a summary:</p> <p>The presence of harmonics allows us to approximate a system's output (for a sinusoidal input e.g. <span class="math-container">\$v_i=v \cos(\omega t)\$</span>) using Taylor expansion and half-angle formulas (trigonometry):</p> <p><span class="math-container">$$ \begin{align} v_o&=a \ v_i \\ &=a (v \cos (\omega t))\\ &=a_0+a_1 (v \cos (\omega t))+a_2(v \cos (\omega t))^2+a_3 (v \cos (\omega t))^3+... \\ &=(a_0+\frac{1}{2}a_2v_2+\frac{3}{8}a_4v_4+...)+(a_1+\frac{3}{4}a_3v_2+...) \ v\cos(\omega t) +... \end{align} $$</span></p> <p><span class="math-container">\$P_{1\mathrm{dB}}\$</span> (1 dB compression point) can be calculated from ideal vs real fundamental components of the approximation above i.e. ideal fundamental: <span class="math-container">\$a_1v \cos(\omega t)\$</span> and real (approx) fundamental: <span class="math-container">\$(a_1+\frac{3}{4}a_3v_2+...) \ v\cos(\omega t)\$</span></p> <p>Using the expansion you can also find IP3 (<span class="math-container">\$P_{\mathrm{IP3}}\$</span>) i.e. the point (input power) where the output third harmonic and the output fundamental powers are equal. But this first requires the Taylor expansion above to be re-written from a multi-frequency input e.g. <span class="math-container">\$v_i=v_1\cos (\omega_1 t)+v_2\cos (\omega_2 t)\$</span>.</p> <hr /> <p>Now the main assumption is that the system's output has components up to the 4th order. This allows you to write the IP3 point in terms of <span class="math-container">\$P_{1\mathrm{dB}}\$</span>. Therefore</p> <p><span class="math-container">$$ R=\frac{P_{\mathrm{IP3}}}{P_{1\mathrm{dB}}}=\frac{1}{1-10^{-1/20}}\approx 9.2 \ \mathrm{W/W} $$</span></p> <p>Or in dB:</p> <p><span class="math-container">$$ R_{dB}=10\log (R)\approx 9.6 \ \mathrm{dB} $$</span></p>	<p><a href="https://i.stack.imgur.com/krFv0.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/krFv0.png" alt="enter image description here" /></a></p> <p>The diagram can be found at <a href="https://blog.minicircuits.com/every-block-covered-cascaded-p1db-and-ip3-in-a-26-ghz-5g-front-end/" rel="nofollow noreferrer">graph link</a></p> <p>A lot of textbook give this formula.</p> <p><span class="math-container">$$IP3 = P_{1dB} [dBm] + 9.6[dB]$$</span></p> <p><em>This equation is valid for both input and output referred quantities.</em></p> <p>But how can we know reason <span class="math-container">\$9.6[dB]\$</span> from this graph?</p> <p><a href="https://i.stack.imgur.com/rcOpK.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/rcOpK.png" alt="enter image description here" /></a></p>	How can we know reason \$9.6[dB]\$ from this graph?	2024-01-09T09:20:24.827
696924	\|transistors\|batteries\|	<p>I would use a Double Pole Single Throw (DPST) switch - "Double Pole" means that the switch will switch two separate circuits simultaneously.</p>	<p>I have a circuit that uses an EMG module that requires a V+, GND and V- input. When only one of these lines are turned off, the module remains on.</p> <p><img src="https://i.stack.imgur.com/cGcLV.png" alt="schematic" /></p> <p><sup><a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fcGcLV.png">simulate this circuit</a> – Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a></sup></p> <p>I need to be able to open and close any two lines with a single switch. I have tried to use a PNP and NPN transistor for the V+ and V- lines with little success.</p> <p>Any help would be greatly appreciated.</p>	Dual channel control using a single switch	2024-01-09T12:15:56.867
696932	\|ground\|grounding\|fault\|virtual-ground\|	<p>It appears that some commercial ROVs have a mechanism to measure resistance between circuit common and the frame of the ROV by the reports I get about leakage current problems. Perhaps you could rig up some sort of ohmmeter to perform this function.</p> <p>There are commercial Ground Fault Protectors (GFP) for DC which see common usage in solar panel arrays. These are for equipment protection and the trip currents I have seen are not suitable for human safety.</p> <p>Otherwise, you would need to build your own using a flux gate sensor or perhaps a hall-effect sensor (hall-effect may be prone to falsing due to drift and noise) and a pair of side-by-side parallel wires. If the current on the positive lead matches the return current on the negative lead the combined magnetic field of the parallel wires is zero. If there's a mismatch in the return current, the magnetic fields from the parallel wires would be mismatched and cause a net combined magnetic field that you may be able to measure. The circuit would do something like warn and/or disconnect. A flux gate magnetometer is susceptible to the Earth's magnetic field, potentially causing false alarms as the vehicle moves about.</p> <p>Your comment</p> <blockquote> <p>and will always have less current on the return due to energy converted to heat the outgoing current versus return current</p> </blockquote> <p>does not make sense.</p> <p>Consider a light bulb connected to a battery. <br>On the positive lead there is 1 A of current flowing. <br>What is the current on the negative (return) lead if the bulb is 50% efficient? <br>The answer should be 1 A unless there is another path for the return current.<br>This is the whole premise of current flow analysis in a circuit - what goes in must come out.</p>	<p>I'm helping my friend's kid with a school project where their team has to produce a small ROV. Most of their design I was able to review and help make corrections with them but I'm stumped at one junction, because it's not something I've had to work with much... Ground Faulting. They need to detect a ground fault to the metal hull/frame of the ROV.</p> <p>They currently have no design to accommodate this, and I had suggested they start by looking at current on the supply compared to return, but that's where I got stuck because that only accounts for the power use and will always have less current on the return due to energy converted to heat.</p> <p>I've heard of people using a negative voltage on the hull/frame and monitoring that for ground fault detection. Does anyone have any experience with this and can suggest a design or point to a resource for this application?</p> <p>Edit: There is no battery connection to the frame, but some control boards are mounted to it. The system is supposed to be fully isolated. The thruster motors are also mounted to the frame. They are home made thrusters, so the core laminations may not be isolated from the frame, despite being encapsulated.</p> <p>Update - I probably should have said this the first time. There's an isolated power system, and a non isolated battery bus. I cannot supply schematics - they're not mine to supply. Does one use only one ground fault detection circuit or does it not matter if the impedance is large enough?</p>	Ground fault detection on an ROV	2024-01-09T13:44:26.950
696938	\|identification\|ground\|	<p>The picture is from <a href="https://en.m.wikipedia.org/wiki/Ground_and_neutral" rel="nofollow noreferrer">this Wikipedia article</a> (among others). The caption under the picture is correct. It is a shorting bar that connects the neutral and earth. The nearby label “PEN” stands for Protective Earthed Neutral.</p>	<p>This is the photo of the power distribution panel inside industrial building. On the left most, next to the two thick wires colored yellow/green so as it is likely to be the "ground" we see a strange looking device connected between the two copper rods. There are two more blue wires more on the right. Deciding from color and letter N, the blue wires are connected to the horizontal rod that is "neutral".</p> <p>Hence deciding from labeling and cables, the device seems connecting neutral and ground in the distribution box that I would expect to be directly connected here. However the device appears more complex than just a simple rod. Why does it appear more mechanically complex? I assume the complexity is somehow related to its less than trivial electric functionality.</p> <p><a href="https://i.stack.imgur.com/Sd5oe.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/Sd5oem.jpg" alt="enter image description here" /></a></p>	What is the exact function of this device connected between ground and neutral?	2024-01-09T15:27:30.833
696940	\|rf\|impedance\|ultrasound\|	<p>The diagram you showed is for measuring a 2-port device, not a 1-port. Each port is shown as a single point on the DUT block rather than as two distinct terminals, and each transmission line is shown as a single line rather than as distinct signal and return conductors.</p> <p>The set-up you want, (from the <a href="https://testworld.com/wp-content/uploads/using-a-network-analyzer-to-characterize-high-power-components.pdf" rel="nofollow noreferrer">same Agilent app note</a>) is this one:</p> <p><a href="https://i.stack.imgur.com/Q0z8y.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/Q0z8y.png" alt="enter image description here" /></a></p> <p>I've erased a line from the original drawing because you are measuring a 1-port device rather than a 2-port.</p> <p>This uses a directional coupler to pick off the reflected wave from the DUT's input port and return it to the 'R' port of the network analyzer. The 'R' port is available on a certain style of VNA that requires an external <em>test set</em>. If your VNA doesn't have an 'R' port, you could connect the reflection signal to the '2' port instead, and treat your DUT plus the directional coupler as a single 2-port DUT. You would then need to do some calibrations to determine how to scale the measurement to accurately determine the reflection coefficient of your DUT.</p> <p>The difference between this arrangement and your proposal is that the directional coupler preferentially directs the reflected wave to its coupled output, while your "sampler" circuit doesn't distinguish between the forward-travelling wave and the reflected wave.</p> <p>I should add one other comment:</p> <blockquote> <p>Now I want to see if the impedance changes when the stimulus voltages are higher than what the network analyzer can supply (I need ~15Vpp).</p> </blockquote> <p>If your device's behavior changes when the stimulus amplitude increases, then it is a nonlinear device. When you provide a stimulus at frequency <em>f</em>, the reflection will have components at <em>2f</em>, <em>3f</em>, etc. The basic VNA is, by design, only meant to measure linear devices, and won't correctly deal with the harmonics of the reflected wave.</p> <p>You may have a "special" VNA designed for this purpose, but if you don't, you need to be very careful about how you interpret your measurement results...or consider doing the measurement with a different instrument.</p>	<p>When I characterise ultrasound transducers, I normally do it with a network analyzer in a shunt configuration - ie, I connect the transducer across port 1 of the network analyzer. This gives me plots of phase and resistance across a range of frequencies.</p> <p>Now I want to see if the impedance changes when the stimulus voltages are higher than what the network analyzer can supply (I need ~15Vpp). To do this I will boost the output of the NA using a 40 dB power amplifier. I came across <a href="https://testworld.com/wp-content/uploads/using-a-network-analyzer-to-characterize-high-power-components.pdf" rel="nofollow noreferrer">this document</a> which describes different ways you might protect the NA. The second configuration in this document is the easiest to implement and uses an attenuator to dissipate the excess power. But I don't think this is what I want as it will also reduce the current going through the DUT:</p> <p><a href="https://i.stack.imgur.com/awBJI.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/awBJI.png" alt="Original configuration in document" /></a></p> <p>I am wondering if instead of an attenuator I can use an RF sampler between port 1 and the DUT, whilst connecting the sample port to port 2 on the NA. The sample connection will have a 40dB attenuator, and the RF connection will have a very low impedance path to the DUT. Like this:</p> <p><a href="https://i.stack.imgur.com/PZOb8.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/PZOb8.png" alt="Proposed configuration for protecting NA" /></a></p> <p>My questions are:</p> <ol> <li>Is this a good way to protect the NA?</li> <li>Will I get accurate measurements?</li> <li>What information will I <em>not</em> get doing it this way? The document mentions that I cannot get reflection measurements, but I don't see why the NA can't deduce that from the forward measurements going into port 2. (presuming my amplifier is fairly linear in phase and gain).</li> </ol> <p>By the way, the nominal resistance is 70 Ohms in the region of interest. I care most about 100 kHz - 1 MHz range.</p>	Is an RF sampler a good way to protect my network analyzer during high voltage impedance measurements?	2024-01-09T15:57:42.963
696942	\|digital-logic\|flipflop\|vlsi\|	<p>The goal of what's being discussed is to determine practical values of setup and hold time while being able to treat the flip-flop circuit as a black box. This method is reasonable, and produces a model that will work over a lot more conditions while not being overly conservative. What is described here is an algorithm/method.</p> <p>Consider Fig. 10:36, annotated for just the D falling case. First, consider that this is not a single simulation occurring - in the "D falls, Q rises case", the value stored in the flop is '0', while the "D falls, Q falls" case starts with a '1'.</p> <p>Understanding what's going on in the red and yellow parts of this curve, part of the 'D' signal change has made it into the latches and the internal value has begun to change. In the red region, you have low confidence that you will be able to predict the value stored in the flop, or eventually you will know you have the <em>wrong</em> value. This is the metastability mentioned in the second page. Further away from that point, you may have confidence that you know the value, but the CLK->Q timing will be negatively impacted. In a timing library where you give only one value for CLK->Q regardless of the D->CLK timing, that introduces an extra uncounted delay that may result in timing failures in fabricated parts. Finally, you can increase your setup and hold margins so much that you have no measurable benefits - you are sandbagging more than needed.</p> <p><a href="https://i.stack.imgur.com/BMMil.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/BMMil.png" alt="enter image description here" /></a></p> <p>Going back to your questions:</p> <ol> <li>Yes, I believe you have correctly stated what "hold" means. I agree that you understand the WH method for selecting an optimal hold time.</li> <li>Your understanding is correct. Relaxing the setup or hold time (reducing the aperture using the WH terminology) will result in increased CLK->Q delay that is not properly considered.</li> <li>If you take a rule-like interpretation to setup and hold, then you would expect that if you satisfy both setup and hold, you will store the expected state with the expected CLK->Q delay. This is a reasonable interpretation, but you might run into the case where barely meeting both setup and hold will result in the incorrect value being latched. In this case, our model/abstraction of the flip-flop may not be accurate enough for all the use cases. Usually, you have either long logic paths that push against your setup constraint but easily meet hold time, OR extremely short paths (or clock skew) that push against your hold constraint but easily meet setup. Having a timing arc where both occur is uncommon, which leads to the implicit assumption here, which is that setup and hold is valid if D is only changing <em>once</em>. Reality can be a bit more complicated. If you need your setup and hold to guarantee short pulses on D, then you should either find a way of ensuring that a minimum width is enforced, or de-rate setup/hold to ensure that a signal barely meeting setup <em>and</em> hold is properly captured.</li> </ol>	<p>Consider the attached from Weste and Harris's (WH) <em>CMOS VLSI Design</em>. I follow all of the discussion and definitions except for the hold time definition.</p> <p><a href="https://i.stack.imgur.com/wJEsN.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/wJEsN.png" alt="enter image description here" /></a></p> <p>Now I am familiar with the common/heuristic hold time definition which says something like "the time relative to the clock edge (measured positive past the clock edge) during which the data input must be stable for correct operation". There are of course analogous heuristic definitions for <span class="math-container">\$t_{setup}\$</span> and I do understand how these connect to the underlying definition given by WH. However, I can't follow for <span class="math-container">\$t_{hold}\$</span>. Indeed, I don't even understand what they mean by "clock to D" here.</p> <p><strong>Edit:</strong></p> <p>In this edit I include the next page which may shed some light on my question.</p> <p><a href="https://i.stack.imgur.com/0awmW.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/0awmW.png" alt="enter image description here" /></a></p> <p>My understanding/guess about the hold time is now the following. Let's focus on the given flip-flop intending to capture a <span class="math-container">\$D = 0\$</span> input. We examine first the "D falls Q falls" curve. We define <span class="math-container">\$t_{setup}\$</span> as the <span class="math-container">\$t_{DC}\$</span> at which the slope of the <span class="math-container">\$t_{CQ}(t_{DC})\$</span> curve equals -1. The corresponding <span class="math-container">\$t_{CQ}\$</span> value is called <span class="math-container">\$t_{pcq}\$</span> (the reason this definition makes sense is that, in our design, we will always arrange things such that tokens arrive before <span class="math-container">\$t_{setup}\$</span> so that, per the Figure, <span class="math-container">\$t_{pcq}\$</span> will indeed be an upper bound on <span class="math-container">\$t_{CQ}\$</span>). We can also define <span class="math-container">\$t_{ccq}\$</span> as <span class="math-container">\$t_{CQ}\$</span> in the <span class="math-container">\$t_{DC} \to \infty \$</span> limit.</p> <p><strong>Now for hold time:</strong> We begin by examining the "D rises Q falls" curve. First of all, we notice that it has a vertical asymptote. We take this as implying that if D rises any earlier than this vertical asymptote then the flip-flop captures a 1 (rather than a 0) incorrectly. (An analogous comment applies to the vertical asymptote for "D falls Q falls".) Now among all of these times at which D can change to 1 and yet the flip-flop still correctly captures a 0, we see that the earlier this change happens the longer it takes for the flip-flop to capture that 0 (this presumably has to do with the inverters in the feedback loops of the flip-flop fighting each other, but we'll leave that aside). Among these <span class="math-container">\$t_{DC}\$</span>, the hold time is defined as the negative of the maximum <span class="math-container">\$t_{DC}\$</span> such that <span class="math-container">\$t_{CQ} \leq t_{pcq}\$</span>. This matches the definition given on the previous page by WH: "The hold time is the minimum delay from clock to D changing [i.e. <span class="math-container">\$-t_{DC}\$</span>] such that the <span class="math-container">\$t_{CQ} \leq t_{pcq}\$</span> [and such that we get correct capture of the token].</p> <p>My questions are as follows:</p> <p>(1) Do you agree with my understanding of the hold time definition?</p> <p>(2) Why is the added requirement of "such that the <span class="math-container">\$t_{CQ} \leq t_{pcq}\$</span>" in the hold time definition necessary? Why not define the hold time as the vertical asymptote alluded to above? I think the answer is that our timing parameter definitions are such that, if we meet them, then we are guaranteed a maximum <span class="math-container">\$t_{CQ}\$</span> of <span class="math-container">\$t_{pcq}\$</span> whereas if we relaxed the hold time definition to be at that vertical asymptote then we might have huge <span class="math-container">\$t_{CQ}\$</span> delays. I would appreciate confirmation on this point.</p> <p>(3) WH write "If D is a very short pulse. the flip-flop may fail to capture it even if D is stable during the setup and hold times around the rising clock edge." How can this be? Wasn't setup and hold time defined (among other things) to give a window during which we would get correct token capture if the D input is stable?</p> <p><strong>Edit 2:</strong> As noted in a comment below, this version of the text has an error (a crucial one!) which is explained in an erratum by the authors below: <a href="https://i.stack.imgur.com/HwP3Z.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/HwP3Z.png" alt="enter image description here" /></a></p>	Understanding the rigorous definition of hold time	2024-01-09T16:01:30.897
696945	\|pcb\|stm32\|	<p>Your crystal connections are wrong. The capacitors do to connect that way. The picture below is from the <a href="https://www.st.com/en/evaluation-tools/nucleo-f411re.html#overview" rel="nofollow noreferrer">NUCLEO-F411RE</a> <a href="https://www.st.com/content/ccc/resource/technical/layouts_and_diagrams/schematic_pack/group2/5a/85/d6/9a/34/e2/47/1d/MB1136-DEFAULT-C05_Schematic/files/MB1136-DEFAULT-C05_Schematic.pdf/jcr:content/translations/en.MB1136-DEFAULT-C05_Schematic.pdf" rel="nofollow noreferrer">schematic</a>:</p> <p><a href="https://i.stack.imgur.com/0cHBN.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/0cHBN.jpg" alt="enter image description here" /></a></p>	<p>I ordered a PCB with the following schematic based on an STM32F411. As you can see, the NSRT pin is connected to a LP filter. I think I should have connected it to a switch to easily enter boot mode, but I still have 6 external pins: GND, +3V3, SWDIO, SWO, SWCLK, and NRST.</p> <p>I tried to connect NRST to GND but I still could not enter boot mode.</p> <ul> <li>First I connected the USB power supply to my laptop.</li> <li>I shorted NRST to GND, still could not boot.</li> <li>Then I tried pushing BOOT0 to high before plugging the USB connector in.</li> </ul> <p>How can I boot an STM32F411CEU6 with NRST based on the following schematic? Can I still do it with the SWDIO ?</p> <p>The following picture is from a personal project:</p> <p><a href="https://i.stack.imgur.com/Cf9PR.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/Cf9PR.png" alt="enter image description here" /></a></p>	How can I enter boot mode with an STM32F411CEU6?	2024-01-09T16:51:02.783
696960	\|pwm\|i2c\|components\|	<p>It's not a peripheral, but... 8x RP2040's is $5.6, each can do 14 PWM's using 7 timers. (one of them is for i2c)</p> <p>Or even cheaper, do the PWM in software, because why not?<br /> Then you can do 28 PWM channels per chip, say 5 chips, $3.5.</p>	<p>I'm currently looking for some sort of interface which can generate many (up to 100 potentially) individual PWM outputs. I figure I2C is the best way to go about this, but I'm open to other possibilities.</p> <p>The only thing I've found so far is the Adafruit PCA9685, but at $15 a pop ($105 for the 7 I'd need,) I'm open to other options.</p> <p>I don't have particularly high needs in terms of frequency or resolution - a step resolution of 1% (7 bit, I guess), at 10 ms time resolution at 1 Hz update rate would be my lower bounds on performance.</p>	I2C to 100+ PWM	2024-01-09T18:32:45.133
696967	\|operational-amplifier\|voltage-divider\|thevenin\|single-supply-op-amp\|hysteresis\|	<p>Here are the two scenarios you describe, one with negative feedback (left), the other with positive (right):</p> <p><img src="https://i.stack.imgur.com/7f9wH.png" alt="schematic" /></p> <p><sup><a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2f7f9wH.png">simulate this circuit</a> – Schematic created using <a href="https://www.circuitlab.com/" rel="noreferrer">CircuitLab</a></sup></p> <p>The only difference between the two circuits is the polartiy of op-amp inputs; OA2's inputs are swapped with respect to OA1. In both circuits, some fraction of a <em>change</em> in the output is fed back to one of the inputs, but the effect of that change will be grossly different in each case.</p> <p>On the right, where feedback is positive, a rise in output causes the non-inverting input potential to also rise. Being the non-inverting input, that rise further increases the output potential, which increases non-inverting input potential, which further increases the output, and so on. The result is that the output hurtles upwards until it can't go any further. The same thing happens in the opposite direction; when the non-inverting input is slightly negative, the output falls, making the input more negative still, making the output even more negative and so on, until he output gets stuck at the negative extreme.</p> <p>Positive feedback ensures that <span class="math-container">\$V_P\$</span> and <span class="math-container">\$V_Q\$</span> are as <em>different</em> as it's possible for them to be.</p> <p>On the left, a rise in output potential causes a rise in potential at the input as before, but this time the rise occurs at the <em>inverting</em> input instead. A rise at the <em>inverting</em> input will incur a <em>fall</em> in output potential (and vice versa), in <em>opposition</em> to any change in output. That is, any fluctuation in output tends to correct itself, and it doesn't go off on some wild swing to extremes. In fact, what happens is that it settles at whatever potential is required to satisfy this condition:</p> <p><span class="math-container">$$ V_P = V_Q $$</span></p> <p>In each case the algebra that describes behavior may look similar, but there's a crucial sign difference that causes one circuit to behave very differently from the other. For instance, the formula for the left hand circuit, relating output to input is:</p> <p><span class="math-container">$$ V_{OUT} = -\frac{R_2}{R_1} $$</span></p> <p>That would be a straight line on a graph of <span class="math-container">\$V_{OUT}\$</span> vs. <span class="math-container">\$V_{IN}\$</span>, behaviour we called "linear".</p> <p>For the circuit on the right, a graph of <span class="math-container">\$V_{OUT}\$</span> vs. <span class="math-container">\$V_{IN}\$</span> would have vertical discontinuities at the thresholds, and horizontal portions elsewhere, very non-linear behaviour.</p> <p>That's why the article you referred to says "a comparator cannot be operated as a hysteresis comparator when a negative feedback is applied"; either you get linear behaviour with negative feedback, or hysteresis from positive feedback, and never the twain shall meet. If you do try to mix them, you still end up with one or the other, depending on which of the two feedback quantities is dominant.</p> <hr /> <p>With regard to calculating the thresholds when input comes from a resistor potential divider, having formulae is OK, but knowing why is priceless. One way (possibly the simplest) is to take the Thevenin equivalent of that divider:</p> <p><img src="https://i.stack.imgur.com/7u8UX.png" alt="schematic" /></p> <p><sup><a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2f7u8UX.png">simulate this circuit</a></sup></p> <p>Replace the components in the blue box with their Thevenin equivalent:</p> <p><img src="https://i.stack.imgur.com/1s1Fn.png" alt="schematic" /></p> <p><sup><a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2f1s1Fn.png">simulate this circuit</a></sup></p> <p>Thevenin resistance <span class="math-container">\$R_{TH}\$</span> is</p> <p><span class="math-container">$$ R_{TH} = R_3 \parallel R_4 = \frac{R_3R_4}{R_3+R_4} $$</span></p> <p>Thevenin voltage <span class="math-container">\$V_{TH}\$</span> is</p> <p><span class="math-container">$$ V_{TH} = V_{IN} \frac{R_4}{R_3 + R_4} $$</span></p> <p>Now you have resistors <span class="math-container">\$R_{TH}\$</span> and <span class="math-container">\$R_1\$</span> in series, with a combined resistance of <span class="math-container">\$R_{TH} + R_1\$</span>, which permits you to calculate thresholds using the usual method, yielding thresholds in terms of <span class="math-container">\$V_{TH}\$</span>.</p> <p>Then you can use the above relationship between <span class="math-container">\$V_{TH}\$</span> and <span class="math-container">\$V_{IN}\$</span> to express those thresholds to be in terms of <span class="math-container">\$V_{IN}\$</span>.</p> <p>An example:</p> <p><img src="https://i.stack.imgur.com/5DWMr.png" alt="schematic" /></p> <p><sup><a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2f5DWMr.png">simulate this circuit</a></sup></p> <p><span class="math-container">$$ R_{TH} = R_3 \parallel R_4 = \frac{12k\Omega \times 6k\Omega}{12k\Omega + 6k\Omega} = 4k\Omega $$</span></p> <p><span class="math-container">$$ V_{TH} = V_{IN} \frac{6k\Omega}{12k\Omega + 6k\Omega} = \frac{1}{3}V_{IN} $$</span></p> <p><img src="https://i.stack.imgur.com/OGbkL.png" alt="schematic" /></p> <p><sup><a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fOGbkL.png">simulate this circuit</a></sup></p> <p><img src="https://i.stack.imgur.com/WxCmj.png" alt="schematic" /></p> <p><sup><a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fWxCmj.png">simulate this circuit</a></sup></p> <p>Assuming that CMP1 is rail-to-rail output, reaching extremes of ±12V, the switching thresholds of <span class="math-container">\$V_{TH}\$</span> can be calculated like this:</p> <p><span class="math-container">$$ \begin{aligned} V_{TH(L)} + \left(V_{OUT(H)} - V_{TH(L)}\right) \frac{R_5}{R_2 + R_5} &= 0 \\ \\ V_{TH(L)} + \left(12 - V_{TH(L)}\right) \frac{50k}{150k} &= 0 \\ \\ V_{TH(L)} + 4 - \frac{1}{3}V_{TH(L)} &= 0 \\ \\ \frac{2}{3}V_{TH(L)} = -4 \\ \\ V_{TH(L)} = -6 \\ \\ \end{aligned} $$</span></p> <p><span class="math-container">$$ \begin{aligned} V_{TH(H)} + \left(V_{OUT(L)} - V_{TH(H)}\right) \frac{R_5}{R_2 + R_5} &= 0 \\ \\ V_{TH(H)} = +6 \\ \\ \end{aligned} $$</span></p> <p>From before, we established the relationship between <span class="math-container">\$V_{TH}\$</span> and <span class="math-container">\$V_{IN}\$</span>, and we can use that relationship to obtain thresholds in terms of <span class="math-container">\$V_{IN}\$</span>:</p> <p><span class="math-container">$$ \begin{aligned} V_{TH} &= \frac{1}{3}V_{IN} \\ \\ V_{IN} &= 3V_{TH} \\ \\ V_{IN(L)} &= 3 V_{TH(L)} \\ \\ &= -18V \\ \\ V_{IN(H)} &= 3 V_{TH(H)} \\ \\ &= +18V \\ \\ \end{aligned} $$</span></p> <p>Let's run a simulation to verify:</p> <p><img src="https://i.stack.imgur.com/3kITL.png" alt="schematic" /></p> <p><sup><a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2f3kITL.png">simulate this circuit</a></sup></p> <p>Sweeping the input <span class="math-container">\$V_{IN}\$</span> from −24V to +24V, and back, input <span class="math-container">\$V_{IN}\$</span> is blue, output <span class="math-container">\$V_{OUT}\$</span> is orange:</p> <p><a href="https://i.stack.imgur.com/pKnIf.png" rel="noreferrer"><img src="https://i.stack.imgur.com/pKnIf.png" alt="enter image description here" /></a></p>	<p>If you examine 98% of circuits online that include hysteresis for a comparator, they always implement the hysteresis on the non-inverting input, like so:</p> <p><a href="https://i.stack.imgur.com/82ffVm.png" rel="noreferrer"><img src="https://i.stack.imgur.com/82ffVm.png" alt="enter image description here" /></a></p> <p>This is easy enough to calculate. However, let's say your input is from a voltage divider. The calculation of the hysteresis gets a bit more complicated. A page of equations and a handy excel calc later, I got it figured out. I used a combination of the <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/MCP6541%20Output%20SubMicroamp%20Comparators%2020001696K.pdf" rel="noreferrer">MCP6541's datasheet</a> and this <a href="https://www.ti.com/lit/ug/tidu020a/tidu020a.pdf?ts=1704733269562" rel="noreferrer">handy document from TI</a>. The circuit looks like:</p> <p><a href="https://i.stack.imgur.com/FYhB7m.png" rel="noreferrer"><img src="https://i.stack.imgur.com/FYhB7m.png" alt="enter image description here" /></a></p> <p>It's worth noting that in almost every explanation of hysteresis for op amps, the reference pin is on the non-inverting terminal, with input signal on the inverting terminal. While going through all this math, I wondered to myself, why can't I just add the hysteresis circuit on the inverting terminal? The math is simpler, and it seems like it would work much the same way. I could not find a single circuit online that did this, which made me wonder if I'm missing something terribly obvious. Additionally, I found this note in a <a href="https://fscdn.rohm.com/en/products/databook/applinote/ic/amp_linear/comparator/gpl_cmp_hysteresis-e.pdf" rel="noreferrer">ROHM application note</a>, "<em>Note: A comparator cannot be operated as a hysteresis comparator when a negative feedback is applied.</em>" My favorite question....but why not? I may be misunderstanding that statement. That circuit would look like this:</p> <p><a href="https://i.stack.imgur.com/UFbD3m.png" rel="noreferrer"><img src="https://i.stack.imgur.com/UFbD3m.png" alt="enter image description here" /></a></p> <p>I'm not sure what's wrong with this. If you do the math, it seems like the VREF changes slightly with the expected hysteresis depending on whether Vout is slammed to GND or Vcc. I built the circuit in every circuit, and it seems to function just fine.</p> <p>Is there a issue with this method of implementing hysteresis on the negative feedback loop?</p>	Hysteresis on inverting terminal for comparator circuits?	2024-01-09T19:34:31.887
696979	\|transistors\|shift-register\|	<p>With a 6mA spec at 5V, this implies that the output Rds(on) for high-drive is 125 ohms or less for Voh = 4V / Vdd=4.5V. Considering you also have a series resistor per LED, you will not likely burn the chip even if you are driving a bit above that level. We'll get into that below.</p> <p>Where you will get into trouble is if you exceed the <a href="https://www.ti.com/lit/ds/symlink/sn74hc595.pdf?ts=1704805914624&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FSN74HC595%253Futm_source%253Dgoogle%2526utm_medium%253Dcpc%2526utm_campaign%253Dti-null-null-xref-cpc-pf-google-wwe%2526utm_content%253Dxref%2526ds_k%253D%257B_dssearchterm%257D%2526DCM%253Dyes%2526gad_source%253D1%2526gclid%253DCjwKCAiA-vOsBhAAEiwAIWR0TcHSqIQvFCy1P9ZdbnqqKh5B_f3fItmi-F-wQ0-W380FyEclj2RPJxoCFJAQAvD_BwE%2526gclsrc%253Daw.ds" rel="nofollow noreferrer">'HC595</a> total package limit of 70mA (8.75mA/pin x 8), either to Vdd or to GND. This will certainly be the case if you don't have resistors. As it is, 220 ohms is marginal - you're likely to exceed the package limit if you use red (Vf 1.8V) LEDs.</p> <p>How to estimate the resistor then? We compute the target current based on Vf:</p> <ul> <li>R(led) = (Vdd-Vf)/I(led) - Rds(on)</li> </ul> <p>For a red LED at 6mA then:</p> <ul> <li>R(led) = (5V - 1.8V) / 6mA - 125 ohms = 408 ohms.</li> </ul> <p>At max allowed (8.75mA):</p> <ul> <li>R(led) = (5V - 1.8V) / 8.75mA - 125 ohms = 240 ohms.</li> </ul> <p>As you can see, 220 ohms is still too low of a value.</p> <p>The color of the LED changes things, since Vf changes.</p> <p>Example: white LED at 6mA:</p> <ul> <li>R(led) = (5V - 3.1V) / 6mA - 125 ohms = 316 ohms.</li> </ul> <p>Which is a lower value than for red.</p> <p>That said, 4mA per LED is usually enough for indicators, especially if you use high-efficiency LEDs. If you need more current than that it's perfectly valid to use an external transistor like you've shown, or a FET (e.g., 2N7001, BSS138), or a high-drive IC buffer.</p> <p>You may also choose an LED driver IC that has built-in current source drive, like the <a href="https://www.ti.com/lit/ds/symlink/tlc59284.pdf?ts=1704834273260&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FTLC59284" rel="nofollow noreferrer">TI TLC59284</a> which can handle 35 or 45mA. This device uses a single resistor to set the LED current, so you don't need series resistors on each LED.</p>	<p>I want to light some LEDs (from 1 to 5 at the same time) using a shift register. <a href="https://www.ti.com/lit/ds/symlink/sn54hc595.pdf?ts=1704791065554&ref_url=https%253A%252F%252Fwww.mouser.de%252F" rel="nofollow noreferrer">I read</a> that the shift register is supposed to output 6mA per pin: <code>±6-mA output drive at 5 V</code>, which seems a bit low so I figured I could use transistors like described below. I'm a bit confused though:</p> <ul> <li>Are the transistors actually required or could I send the shift register output directly to the LED ?</li> <li>What if I connect the shift register output directly to the LED (with or without a resistor) ? Will the current be safely limited to 6mA, or is it going to raise and damage the chip ?</li> <li>I'll use the shift-register to multiplex with other outputs, which means the leds won't be turned on continuously. Does that change anything to the maximum current I can send in the LEDs/shift register ?</li> </ul> <p>[edit]: the LED should be moved to the collector-side, as mentioned by @vir.</p> <h2>Option A: with transistors</h2> <p><a href="https://i.stack.imgur.com/WcSgT.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/WcSgT.png" alt="with bjts" /></a></p> <h2>Option B: The more basic approach:</h2> <p><a href="https://i.stack.imgur.com/Rf7pg.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/Rf7pg.png" alt="enter image description here" /></a></p>	Is it worth adding a transistor on shift register output to drive a LED?	2024-01-09T22:31:31.320
697000	\|pcb-design\|flash\|rp2040\|	<p>From the datasheet: "... it cannot be left floating and must be driven..."</p> <p>If you use DQ2 for the QSPI_SD2 pin then it's driven by the SPI hardware interface and you don't need to add any external pull-up resistor.</p> <hr /> <p>You must add an external pull-up resistor only if you, for some reason, leave that pin floating.</p>	<p>I am making my first micro controller board with the rp2040. It requires external flash and so I picked the MT25QL128ABA1EW7 since it seems to match all the requirements based on this document: <a href="https://datasheets.raspberrypi.com/rp2040/hardware-design-with-rp2040.pdf#_supported_flash_chips" rel="nofollow noreferrer">https://datasheets.raspberrypi.com/rp2040/hardware-design-with-rp2040.pdf#_supported_flash_chips</a>.</p> <p>However, in the datasheet of the flash IC, there is a two inputs(W#/DQ2) that share a pin: <a href="https://media-www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/mt25q/die-rev-a/mt25q_qlhs_l_128_aba_0.pdf#unique_10" rel="nofollow noreferrer">https://media-www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/mt25q/die-rev-a/mt25q_qlhs_l_128_aba_0.pdf#unique_10</a>. It says the following for "This signal does not have internal pull-ups, it cannot be left floating and must be driven, even if none of W#/DQ2 function is used".</p> <p>I plan to use this pin as DQ2 for the QSPI_SD2 pin from the rp2040, but I don't know if I can just connect them directly or if I need a resistor close to the DQ2 pin of the flash chip in order to prevent unwanted behavior. And if the resistor is need, how can I figure out the resistance value because it is not mentioned in the datasheet.</p>	Is resistor needed for Flash IC?	2024-01-10T03:30:59.040
697007	\|resistors\|control\|temperature\|heat\|current-sensing\|	<p>Measuring the temperature of the heater is not really measuring the temperature of whatever it is you are trying to control. I'm also not sure the Kanthal elements will last all that long if you're operating that close to the maximum but it really depends on the atmosphere they will be exposed to. You also need to find a way to calibrate it (a thermocouple or an optical pyrometer) and 50ppm/°C means you will have trouble with tight control. I think it can be made to work at least for a short time (without my doing a lot of evaluation of your proposed method) but I don't think it will be comparable to a thermocouple controller unless you have a very special need to control the temperature of the heating elements themselves.</p> <p>A not insignificant problem is that the resistance and the elements themselves will change significantly during use so that your actual controlled temperature will drop continuously as the elements erode away and the resistance increases.</p> <p>A standard platinum-rhodium thermocouple can easily handle those temperatures (type R or S are most common, and work up to 1450°C). They don't have to be fat like AWG 8 thermocouples, even a fine wire will last a long time, because Pt is very non-reactive ('noble'). The output is quite a bit less than common base-metal thermocouples such as K or N type, but still not a problem for modern electronics.</p>	<h3>Context</h3> <p>I'm making an electric furnace for melting metal, and aiming to make my own controller.</p> <p>Everyone seems to just use thermocouples and a control loop, I thought perhaps I could just measure the resistivity from the heating element. I'm planning on using Kanthal A-1 (rated for 1400°C/2552°F) at temperatures that can reach 1200°C/2192°F. Highest temperature thermocouples I've been able to find were 1250°C/2282°F which is a bit too close for comfort.. a control loop overshoot may kill it and then.. kanthal isn't cheap.</p> <hr /> <h3>Current Thinking</h3> <p>Now while kanthal has a quite low tempco of ~50ppm/°K, we're talking about a big delta here and precision in the single digits isn't required, so I think it could work. Calibration could be done with the thermocouple.</p> <p>Since I'm aiming for somewhere around 3-4kw, I was thinking of just rectifying some mains AC, and using 3 ADCs to take the resistivity reading.</p> <p>Here's the rough idea:<br /> <a href="https://i.stack.imgur.com/Mn3ik.png" rel="noreferrer"><img src="https://i.stack.imgur.com/Mn3ik.png" alt="enter image description here" /></a><br /> (The switching mechanism for controlling the temperature just isn't drawn, I'm not forgetting it needs to exist).</p> <p>ADC for this doesn't need to be fast, 100Ksps will give me 1000 readings per every cycle (though I'm thinking 1Msps for switching headroom). And for a 16-bit adc, the 4% change in resistivity over the full temperature swing still gives me a range with <code>2^16 x 0.04 ≈ 2621</code> values - about half a degree celsius per increment.<br /> To take the kelvin reading, I'm thinking of using kanthal leads. That way they won't melt. Just tig weld them near the ends of the heating element on the inside of the furnace. The point at which they reach the controller should be ambient temperature, so thermal EMF issues are avoided too.</p> <p>There are a couple vishay 20ppm/°K 1mΩ shunts for very cheap on mouser, so even though we're talking high currents I think very good precision can be achieved. Could also use multiple, use a heatsink, or even do both.<br /> At 20ppm/°K, in the eggagerated scenario of a 40°C temperature rise we get <code>20/1,000,000*40 = 0.0008 ≈ 0.1%</code>. That would be 1/40 of that 4% resistivity change.</p> <hr /> <h3>Wind-Up</h3> <p>I realize this has more possible points of failure than the typical implementation - reading a thermocouple and running a PID loop is tried, tested and rhobust. I'm not asking whether this is the simplest solution to my problem as I know it isn't.<br /> But it does seem the most reasonable for the resources I have at my disposal.</p> <p>So, provided what I wrote above is right (and please, tell me if it's not), is this sensible? Or is there something I'm missing?</p>	Is it wise to determine heating element temperature from resistivity?	2024-01-10T05:45:55.777
697008	\|voltage\|current\|transformer\|induction-motor\|soft-starter\|	<p>When the motor is at zero RPM it can be seen as a transformer with the stator as primary winding and the rotor as secondary winding.</p> <p>The secondary winding is shorted hence the startup current is a short circuit current of that transformer. The short circuit current is proportional to the voltage applied, as it is solely determined by the inductance and resistance of the components.</p> <p>This is different from a motor running close to its synchronous RPM. Running at exactly synchronous RPM is, to stay with that analogy an open secondary winding of that transformer.</p> <p>That's where the analogy reaches its limit. Close to synchronous RPM lies the nominal RPM and when loaded the motor runs just below the nominal RPM.</p> <p>When a load is applied the behaviour of the motor is defined by its resistances and inductances and additionally by the behavior of the load. The load of most machinery has a rather flat curve at nominal RPM in comparison to the curve of the motor. Lets say the induction motor moves a conveyor belt. If the conveyor belt moves some material horizontally the torque will increase slowly with the RPM. But near the nominal RPM the M-n curve of the motor is extremely steep. The amplitude of the whole M-n curve however is proportional to the voltage.</p> <p>Consider a flat curve crossing the steep section of the curve. If the voltage is reduced, the operating point moves faintly to a lower RPM and even more faintly the torque will drop. In total the mechanical power delivered by the motor will be almost the same. However, the power must be delivered by the motor. So if the voltage drops significantly the current has to increase reciprocally.</p> <p>Those effects at 0 RPM and with typical load near nominal RPM shouldn't be confused.</p>	<p>This is the question I am trying to solve:</p> <blockquote> <p>A delta connected fully loaded induction motor draws 90A from a 400V supply when started direct online. Show by calculation the current at start up that the motor would draw when connected to a star delta starter in the star position.</p> </blockquote> <p>I was under the impression with delta star, that when voltage goes up, current goes down, however here the answer to the question shows that the ratio between delta star is 1.732.</p> <p>With Delta-Star I understand this to be a ratio of 1.732:1 (Delta:Star) So when the phase voltage gets divided by 1.732 the phase current should be increasing by 1.732 times.</p> <p>This is the solution given.</p> <blockquote> <p><a href="https://i.stack.imgur.com/hrFf1.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/hrFf1.png" alt="solution given" /></a></p> </blockquote> <p>Why at the final step of the solution do the say 52/sqrt(3) instead of 52*sqrt(3) as I was under the impression that if the phase voltage goes down (is lower in star than in delta) then the current in star should be higher than in delta?</p>	Electrician Theory: Delta Star Induction motor question	2024-01-10T05:59:21.497
697013	\|relay\|gpio\|output\|isolated\|	<p>Technically, it will work.</p> <p>But it does not isolate, because you used the same ground and same 5V supply on both sides of the optoisolator.</p> <p>So if you wanted to have isolation over the optocoupler between two different supplies and grounds to keep them separate, then the opto is useless and based on that the design is not correct.</p> <p>Also any off leakage current through optoisolator to Q1 base may turn it on.</p>	<p>I am making a circuit for an optically isolated relay output controlled by a Raspberry Pi GPIO pin.</p> <p>I am not sure if this is the correct way of doing it. Can someone please help me out on this?</p> <p><a href="https://i.stack.imgur.com/1QDu4.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/1QDu4.png" alt="enter image description here" /></a></p> <hr /> <p>Edit: Modified circuit based on answer from JustMe.</p> <p><a href="https://i.stack.imgur.com/k44SW.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/k44SW.png" alt="enter image description here" /></a></p>	Is this the correct isolated circuit to control a relay output from a Raspberry Pi GPIO?	2024-01-10T06:36:27.117
697016	\|ethernet\|optoelectronics\|	<p>'Dual ethernet' may well be referring to bonded ethernet.</p> <p>This is where two physical ethernet cable connections are logically linked to appear so they appear a single logical connection to their host systems. This gives two benefits:</p> <ul> <li><p>Redundancy. If a cable breaks or becomes disconnected, the other cable can provide the logical connection.</p> </li> <li><p>Speed. While both are working, the logical connection has a theoretical speed of twice that of a single physical connection.</p> </li> </ul> <p>You'll find plenty of detail about this on the internet, with <a href="https://en.wikipedia.org/wiki/Link_aggregation" rel="nofollow noreferrer">this Wikipedia article</a> a good start on the subject.</p>	<p>I came across a word called dual ethernet while working on a project and it got me curious like is the word misspelled or is there any real concept on this?</p>	Is there concept called dual ethernet?	2024-01-10T07:10:31.397
697018	\|simulation\|esd\|pspice\|	<blockquote> <p><em>Switch opens at 0.1 uS</em></p> </blockquote> <p>Prior to the switch opening, all the capacitors in your circuit will be fully charged to 25 kV. This is an inevitability of your circuit and, your graph indicates that. After the switch opens, the state of charge of all the capacitors will be exactly the same. This is also as shown in the graph.</p> <blockquote> <p><em>Could anyone give a guidance or feedback?</em></p> </blockquote> <p>If you are simulating an ESD gun then you should charge C1 (330 pF) with the switch open then, close the switch but, you should also disengage V1 at that very moment to prevent V1 from having any effect. Some point later you should open the switch labelled U1 and restart the process as desired.</p>	<p>Issue: I do not know how to build a ESD simulation model in PSpice Orcad capture.</p> <p>Question: What is wrong with the simulation circuit? The simulation result seems like the ESD is not discharging properly. Why I cannot see the same response as the simulation result in the reference?</p> <ul> <li>For the second simulation result, I set to close the switch at 5 μs. How come the voltage at C2 behaves as if it is connected to 25 kV before the first 5 μs?</li> </ul> <p>Simulation conditions:</p> <ul> <li>Conform ISO 10605 (voltage range -25 kV to +25 kV, discharge capacitor: 330 pF, discharge resistor: 2000 Ohm)</li> <li>Simulation time: 20 μs</li> <li>Switch opens at 0.1 μs</li> <li>Switch closes at 5 μs</li> </ul> <p><em>ESD circuit with open switch at T:</em><br /> <a href="https://i.stack.imgur.com/kb1CN.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/kb1CN.png" alt="ESD circuit with Open switch at T" /></a></p> <p><em>Simulation result 1:</em><br /> <a href="https://i.stack.imgur.com/Fa5wT.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/Fa5wT.png" alt="Simulation result 1" /></a></p> <p><em>ESD circuit with close switch at T:</em><br /> <a href="https://i.stack.imgur.com/QUDx0.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/QUDx0.png" alt="ESD circuit with Close switch at T" /></a></p> <p><em>Simulation result 2:</em><br /> <a href="https://i.stack.imgur.com/0qTvl.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/0qTvl.png" alt="Simulation result 2" /></a></p> <p>Reference: <a href="https://electronics.stackexchange.com/questions/597679/how-to-choose-capacitor-voltage-rating-for-esd-protection">How to choose capacitor voltage rating for ESD protection?</a></p> <p>Could anyone give a guidance or feedback?</p>	How can I utilize PSpice for ESD simulation?	2024-01-10T07:14:50.100
697020	\|rf\|ground\|impedance-matching\|via\|	<p>As the previous author suggested it is highly advisable to connect the connector GND to the substrate RF GND. In the configuration you have suggested the electromagnetic wave carried by the coplanar waveguide exists partly in the dielectric substrate (in the RO4003C), and partly in the air above it. So even though the CPW is on layer 1 with the energy carried mostly in between the signal track and the two side grounds, there is some also being carried through the air and immediately underneath deep in the Rogers dielectric. Your ground stitching proposed are neither correct nor incorrect. It really depends on how they appear to your HF signals. Generally, as you may or may not know, vias can be modeled as tiny inductors in series with your signal and in this case both length and via diameter will influence the total parasitic inductance. If you sprinkle more of the vias as advised by the manufacturer’s app notes you essentially place the many small parasitic inductances in parallel, thus reducing the overall parasitic inductance. The via length also tends to increase the parasitic inductance so you would be inclined to want to keep them as short as possible. Now summarizing the above leads to the following :</p> <ol> <li>Most of the HF signal’s EM energy is mostly found in the rogers dielectric between <strong>layers 1 and 2</strong>.</li> <li>Short vias add less lumped parasitic inductance, and more vias in parallel reduces overall total lumped parasitic inductance seen by your signal. So <strong>short</strong> and <strong>more</strong> vias seems to be generally better (not worse)…</li> </ol> <p>Combining 1. and 2. above would suggest you’d achieve what you want with less parasitic inductance affecting your signal by the use of blind vias between layers 1 and 2 as this is where your signal’s energy is <strong>mainly propagating through</strong> from/to the connector. However if cost is your main concern you might consider the through vias as an alternative, keeping in mind that having your RF GND stitching going from layer 1 to layer 2 and then to layer 7 serves no benefit whatsoever for your RF signal, for the reasons already mentioned (or it might possibly degrade it to some extent). All your GNDs will eventually have to all meet-up at some point on your PCB but it may be not the best to do it right there at the RF connector end near the RF signal track of your GCPW etc.</p>	<p>I am currently developing an RF board that receives up to 8GHz. The board consists of a multi-layer structure combining Ro4003C (8mil) and FR-4. The connector I will be using for the RF board is a solderless connector, and I will be using the model 'NE06FS001' from waveguides. (See photo below)</p> <p><a href="https://i.stack.imgur.com/IZbMg.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/IZbMg.png" alt="NE06FS001" /></a></p> <p>The board I am developing will mirror the GCPW structure presented by waveguides. waveguides presents the GCPW design shown in the photo below for the RO4003C (8 mil) using the NE06FS001.</p> <p><a href="https://i.stack.imgur.com/ksWFA.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/ksWFA.png" alt="RO4003C 8mil GCPW" /></a></p> <p>The red boxed area in the photo above is where I'm having trouble. My board adds an FR-4 substrate underneath the RO4003C, should I do a through-hole via or just bilnd via to the RO4003C?</p> <p>I'm also adding the datasheet of the connector for further advice. I expect the number of layers for RO4003C+FR-4 to be around 6.</p> <p><strong>+Added specific layer information.</strong> <a href="https://i.stack.imgur.com/gzgiw.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/gzgiw.png" alt="enter image description here" /></a></p> <p><strong>++What do you think of these processes? The idea is to add a single RO4003C board near the connector so that the connector GND is connected to the RF GND, and configure both sides of the RF path as blind via (layer1&layer2).</strong> <a href="https://i.stack.imgur.com/cwhHI.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/cwhHI.jpg" alt="enter image description here" /></a></p>	Via process when implementing GCPW in RO4003 + FR-4 multilayer structure	2024-01-10T08:11:58.673
697024	\|wire\|	<p>Over 30 years ago I remember using a verowire pen. This dispensed polyurethane enamelled wire which was wrapped around pins for through hole components on verboards with square pads, and then soldered to make a connection between the component lead and wire.</p> <p>This is still available from distributors. E.g. the following picture is from the RS components <a href="https://uk.rs-online.com/web/p/wire-wrapping-tools/1054626?searchId=b09c5d4e-be50-4c8a-9848-97d9f2c5b945&gb=s" rel="noreferrer">Vero Technologies Manual Wire Wrapping Tool 34AWG</a> page:</p> <p><a href="https://i.stack.imgur.com/53Fr8.png" rel="noreferrer"><img src="https://i.stack.imgur.com/53Fr8.png" alt="enter image description here" /></a></p> <p>At the time I used verowire and leaded solder to make hobby circuits and didn't have any fume extraction setup.</p> <p>There is the following warning for verowire:</p> <blockquote> <p><strong>Warning</strong> : Polyurethane coatings may produce small quantities of toluene di-isocynanate (T.D.I.) when subjected to normal soldering temperatures. Therefore, fume extraction may be neccessary to ensure the maximum permitted concentration is not exceeded.</p> </blockquote> <p>After reading <a href="https://wwwn.cdc.gov/TSP/MMG/MMGDetails.aspx?mmgid=1139&toxid=245" rel="noreferrer">Medical Management Guidelines for Toluene Diisocyanate</a> about the toxic affects of TDI, at the time should have payed attention to fume extraction.</p>	<p>Last time I visited my PCB manufacturer to do some modifications on a prototype PCB, they used some very thin wire (probably something like AWG 30-35) where they just burned away the insulation with the soldering iron.</p> <p>Is there a name for such (thin) wires where you can burn away insulation, or is there a specific thing to look for in the datasheet to know if I can do this for a given wire?</p>	Name of very thin wires with insulation removed with soldering iron	2024-01-10T09:00:44.977
697027	\|filter\|oscilloscope\|	<p>There's another way to do this which is using the rise time. You can use the rise time approximation for a single pole RC low-pass filter to calculate the bandwidth of a circuit. <span class="math-container">$$ BW = {0.35 \over t_r} $$</span> The bandwidth of a simple RC low-pass is: <span class="math-container">$$ BW = {1 \over 2 \pi RC} $$</span> Where <span class="math-container">\$BW\$</span> is the bandwidth and <span class="math-container">\$t_r\$</span> is the rise time between the 10% and 90% points.</p> <p>Playing some games with algebra: <span class="math-container">$$ BW = {0.35 \over t_r} = {1 \over 2 \pi RC}$$</span> <span class="math-container">$$ C = {t_r \over 2\pi R \;0.35} = {t_r \over 0.7 \; \pi R} $$</span></p> <p><a href="https://i.stack.imgur.com/vlHpx.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/vlHpx.png" alt="enter image description here" /></a></p> <p>If we use 219.24 us for the rise time as measured by the cursors, we end up with C = 9.97 nF which is about a -0.3% error.</p> <p>As others have stated, know the output impedance of the scope calibration output and make sure the rise time of the calibration output is at least 10 times faster than the rise time of the RC circuit. For smaller capacitors, the probe capacitance (around 13 pF) and resistance may become significant.</p>	<p>I have some ceramic capacitors and would like to know for sure what capacitance they have. I don't have a multimeter (or any other instrument) that allows me to measure capacitance directly, so I build a simple RC filter that filters a square wave input, I know that the voltage at the output at the time constant R*C is 63% of Vinput ... I reverse the formula and find C.</p> <p>The question (which is probably stupid) is whether I can use as input the square wave produced by the oscilloscope (is usually used to check before each measurement if the probe is correctly calibrated) .. otherwise I would need a square wave generator :/ <a href="https://i.stack.imgur.com/I6K8E.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/I6K8E.jpg" alt="enter image description here" /></a></p> <p><a href="https://i.stack.imgur.com/Id8oh.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/Id8oh.jpg" alt="enter image description here" /></a></p> <p>After the responses I received, I will upload the photo of the calculations made and ask if they are correct: (565mV is the V measured with the CH1 probe at the ends of 220 ohms) <strong>EDIT: missing a multiplication by 2 in the equation! With that multiplication, the result is about 560 ohms which is correct because I used a 500ohm + 100ohm series finding about 1Vpp at the output .. which is half of 2Vpp</strong> <a href="https://i.stack.imgur.com/rCgdR.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/rCgdR.png" alt="enter image description here" /></a></p> <p>I tried measuring a 100nF capacitor but obtained 36nF: <a href="https://i.stack.imgur.com/S5fGI.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/S5fGI.jpg" alt="enter image description here" /></a></p>	Square wave of oscilloscope for RC circuit	2024-01-10T09:25:23.550
697036	\|lithium-ion\|solar-cell\|mppt\|electric-vehicle\|	<p>Yes, that should work fine.</p> <p>Just one caveat: Li-ion ion cells degrade while connected to a charger that keeps them at the full voltage. Either shut off the charger when the battery is full. Otherwise, you may want to reduce the max voltage from the charger to the equivalent of 3.4 V / cell for LFP cells or 4.0 V for LCO/NMC cells.</p>	<p>I have an EV 72V li-ion battery with given charger (peaks at 11 A).</p> <p>My MPPT solar charger is designed among other types for li-ion up to 96V ie 12/24/36/48/60/72/84/96V settable at 72 V. 50 A max.</p> <p>Given the amps will vary depending on sunshine it will provide the correct volts but limit the amps based on available sun. (Between 0.0 A to 11 A). And has all the features to vary the amps based on charge state, (float etc). and user defined max of, in my case 11 A.</p> <p>Given that from time to time the input amps may fall short of the amps a wall unit may provide, my question is this.</p> <p>Can I use this controller to charge my EV battery pack safely? It has all the protections etc. Essentially the amps may, from time to time, fall short of the 11 A (I'm sure the wall unit too varies amps likewise, based on charge state, averaging around 6 A, lets say.)</p>	Charging li-ion 72V with solar MPPT controller	2024-01-10T10:22:28.447
697040	\|ethernet\|wire\|twisted-pair\|	<p>It is worth considering the <a href="https://amphenolltw.com/product-info/X-Lok/X-Lok.StandardSize" rel="nofollow noreferrer">Amphenol X-Lok connectors</a>.</p> <p><a href="https://i.stack.imgur.com/VSwiL.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/VSwiL.png" alt="enter image description here" /></a></p> <p>(Picture from Amphenol datasheet.)</p> <p>They comes in a variety of sizes, and the <a href="https://amphenolltw.com/product-info/X-Lok/X-Lok.MiniSize" rel="nofollow noreferrer">"mini"</a> size is rated for 5A/contact if just 2 of the contacts are in use.</p> <p>There are also <a href="https://docs.rs-online.com/46a0/A700000007556681.pdf" rel="nofollow noreferrer">adapters</a> which convert to standard RJ45, and the whole assemble is rated for CAT5e/Gigabit operation.</p> <p>22AWG UTP CAT5e cables are fairly widely available for just this kind of power over data applications, and depending on environment two cores should be good at 5A. <a href="https://hubbellcdn.com/specsheet/PREMISE_C5ELPRW_spec.pdf" rel="nofollow noreferrer">Here's</a> a link to an example from Hubbell. There are also a more limited range of 20AWG UTP cables.</p>	<p>I'm planning to use 2 types of connectors:</p> <ul> <li>A : GND + 24V + 100Mbps ethernet (4 wires) + 2 wires with various functions</li> <li>B : 1 Gbps ethernet with PoE (8 wires)</li> </ul> <p>For type B, I found of the shelf connectors meeting my needs (small size + subssea,) but I haven't found any for type A that can handle at least 3A (ideally 5A) while also being rated for use with Ethernet (so I might need to have it custom made.)</p> <p>Using 2 different connectors, one of which custom made, is quite sub-optimal. Is it possible to reliably do one of the 2 things below:</p> <ol> <li>Use a single custom connector with 4 twisted pairs, with some pairs thick enough to carry 3 or 5A? (Either a single thin pair, or the 2 pairs not used for 100Mbps, or all pairs.) This way, I could use the same custom connector for everything.</li> <li>Use non-twisted (and thicker) wires for the 100Mb connection, knowing that there will be up to 3 or 5A flowing next to them? Maximum length is 3m. This way, I could use only standard connectors (2 different models.)</li> </ol> <p>NB: Reliability is very important to me. If it can't be done in a reliable way, I'd rather use 1 standard + 1 custom connector rather that take any risk (no security risk, but downtime costs >1k$/day, vs connectors about 200$.)</p>	Can I use thicker wires or twisted pair for Ethernet?	2024-01-10T10:50:57.520
697043	\|pcb-design\|esp32\|jtag\|	<p>Fielded this exact question at work this week (although it was a programming interface for a PIC, not an ESP).</p> <p>Yes, you need to attach an EEPROM to the FT2232H. While it's considered optional, in this scenario it's quite important to have. The reason is that the EEPROM defines the idle states for the signal and GPIO lines of your programming port. If you omit the EEPROM, you'll risk a situation where you can program and debug your board just fine when the debug USB connection is active, but as soon as you turn off the USB debugger, your chip goes into reset and doesn't work.</p> <p>The EEPROM provides some nice additional capabilities as well, such as the ability to set string descriptors so you can distinguish this FTDI virtual serial port from others attached to the same USB host.</p>	<p>I am currently involved in designing a custom ESP32 board (ESP32-WROOM-32E) and adding the FT2232H chip for JTAG debugging to avoid having to get a FT2232H breakout board or ESP-PROG.</p> <p>I have a question. What are EECS, EECLK, EEDATA pins for in the FT2232H chip and do I need it for JTAG or is it for another protocol? Ive read online that is for EEPROM which has something to do with temporary memory and programming.</p> <p>edit: Not sure if I can just copy the schematics of an ESP-PROG or other FT2232H breakout boards since they use the FT2232H for other purposes like USB to UART (we are already using cp210x) and probably more.</p>	Custom ESP32 board with FT2232H chip for JTAG debugging	2024-01-10T11:15:38.540
697047	\|operational-amplifier\|differential-amplifier\|single-supply-op-amp\|single-ended\|	<p>I am answering your question based upon what I believe you are apparently trying to accomplish, rather than what you ask directly.</p> <p>I believe what you are trying to accomplish is to amplify a differential signal, with a variable gain based upon a single variable resistance. The following circuit will do that job:</p> <p><img src="https://i.stack.imgur.com/gJaXE.png" alt="schematic" /></p> <p><sup><a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fgJaXE.png">simulate this circuit</a> – Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a></sup></p> <p>R1 and R2 should be precision resistors and have the same value. The differential mode gain will be:</p> <p><span class="math-container">$$A_{V(diff)} = 1 + 2\frac{R1}{R{gain}}$$</span></p> <p>You may want to put a fixed resistor in series with the variable resistor to prevent the total resistance going to near 0, and the gain being unreasonably high.</p> <p>The common mode input voltage is "passed through" this circuit. Thus, if the input signals are centered around 1V, instead of 0V, the output signals will also be centered around 1V.</p>	<p>In the first stage the signal is converted to single-ended, and it is amplified using a digital potentiometer in the second stage to be able to change the gain with a microcontroller.</p> <p>In the last stage I have converted the signal back to differential again.</p> <p>Thd ADC range is 0-3.3 V and the max. sampling frequency is 5.6 MHz, or 3.3 MHz will be used.</p> <p>The reason for the differential input is because it has 6 to 8 dB better SNR performance. The signal frequency range of interest is 1 kHz to 1.5 MHz or so.</p> <p>If you can answer each question specifically it would be great.</p> <p><a href="https://www.mouser.com.tr/datasheet/2/609/ADA4807_1_4807_2_4807_4-3119636.pdf" rel="nofollow noreferrer">ADA4807 Datasheet</a></p> <p><a href="https://i.stack.imgur.com/xKAA4.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/xKAA4.png" alt="Schematic" /></a></p> <p>My questions are:</p> <ol> <li><p>Is this schematic correct in the case of cascade connections and especially the part where the signal converted back to differential again (the last stage)? The gain is adjusted in the second stage, so the first and last stages are just for proper conversion. Please correct any wrong resistance value I selected, if any.</p> </li> <li><p>What should be the values of R12 and R14? One reference design uses 1 kΩ, another one uses 10 kΩ. Is it important?</p> </li> <li><p>Does R10 (10 kΩ) have to be the same as R13 (1 kΩ)? Another way of asking is, is the value of R10 important in this conversion?</p> </li> <li><p>Do I need R9 and R19 before the DC bias voltage connection?</p> </li> <li><p>SAR ADC recommends an RC filter at the input for filtering and capacitance recharging, so I have placed 20 Ω and 2.7 nF. Is this correct?</p> </li> </ol>	Op-amp schematic connection questions and DC biasing	2024-01-10T12:25:07.417
697052	\|diodes\|analog\|basic\|lcr\|resonant\|	<p>It's technically possible.</p> <p>For the circuit below, for example, the main idea is to change the damping whilst maintaining the tank resonance frequency:</p> <p><img src="https://i.stack.imgur.com/fWAEt.png" alt="schematic" /></p> <p><sup><a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2ffWAEt.png">simulate this circuit</a> – Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a></sup></p> <p>You can simulate the circuit above with different R1 and R2 values for different amplitudes. Below is the simulation result for the given values:</p> <p><a href="https://i.stack.imgur.com/GX5VK.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/GX5VK.png" alt="enter image description here" /></a></p> <p>So the positive peak hits ~18V and the negative one hits ~23V.</p> <hr /> <p>From your comment under Stefan Wyss's answer:</p> <blockquote> <p>But is there a similar way that dissipates less energy? Without the loss on the resistor being the main source of asymmetry of the waveform</p> </blockquote> <p>In case you ask the same question, I'm going to answer here:</p> <p>Yes, it's possible. In the circuit above, if you replace R1 and R2 with inductors, and L1 with a resistor, you can still have a similar behaviour. However, to create a substantial amplitude difference, the inductance ratios should be high accordingly. Here's an example:</p> <p><img src="https://i.stack.imgur.com/Xq2kE.png" alt="schematic" /></p> <p><sup><a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fXq2kE.png">simulate this circuit</a></sup></p> <p>Just like the other one, you can simulate this circuit. Here is a simulation result for the values above:</p> <p><a href="https://i.stack.imgur.com/NTM4Q.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/NTM4Q.png" alt="enter image description here" /></a></p> <p>The positive peak passes 6V and the negative one passes -8V.</p>	<p>Is there a circuit that can produce an asymmetric wave, where some parameters of positive and negative half waves are different, such as voltage amplitude or time?</p> <p>Intuition says that we need a component that acts differently to the positive and negative voltage. A diode does that, but when I test it in a simulator it shows a symmetrical sine wave, so my intuition is wrong ,which means that I don't understand some important aspect of it. The naive view says something like 'in one half wave a x2 inductor is active, and in other half wave a x1 inductor is active.'</p> <p>Circuit: battery, switch and LCR parallel circuit, where L is doubled and each has a diode facing antiparallel, and one of the L has twice the inductance:</p> <p><a href="https://i.stack.imgur.com/pjdGG.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/pjdGG.jpg" alt="LCR with diodes" /></a></p> <p>The perfect answer would explain the difference between the naive view and the simulation result and if there are any similar circuits that consist of resistors, inductors (can be coupled), capacitors, diodes that can produce a wave with half waves of positive and negative voltage on a capacitor which are not the same in time or amplitude.</p>	Asymmetric LC tank with diodes	2024-01-10T13:24:58.510
697075	\|pcb\|connector\|	<p>The fasteners in the answer by Davide are made by PEM. They also make solderable studs. You press them into a plated-thru hole, maybe thread on a spacer to lift the ring terminal above the board, and fasten the terminal with either a standard nut, a KEPS nut, or a wing nut.</p> <p><a href="https://catalog.pemnet.com/category/studs-broaching-type-kfh" rel="nofollow noreferrer">https://catalog.pemnet.com/category/studs-broaching-type-kfh</a></p> <p><a href="https://catalog.pemnet.com/viewitems/studs-broaching-type-kfh/broaching-studs-type-kfh-unified#" rel="nofollow noreferrer">https://catalog.pemnet.com/viewitems/studs-broaching-type-kfh/broaching-studs-type-kfh-unified#</a></p>	<p>I need to attach these four wires to a PCB I am designing.</p> <p>The three ferruled wires will be connected through a terminal block. I have space next to the terminal block for the lug but I need a method for connecting the lug to the PCB.</p> <p>A simple solution is just a plated through hole, connected to ground. I could then bolt the lug directly to the PCB.</p> <p>I would prefer a binding post of some kind I could solder directly to the PCB and then attach the lug to the binding post.</p> <p>Does anyone know where I can find a connector like this? I'm coming up empty searching the usual places. I don't know what the correct name for this part would be.</p> <p><a href="https://i.stack.imgur.com/to1Dn.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/to1Dn.png" alt="ferrules with lug" /></a></p>	Screw post or binding post on PCB for lugged gnd wire?	2024-01-10T16:12:22.050
697084	\|operational-amplifier\|differential-amplifier\|high-pass-filter\|biasing\|sallen-key\|	<p><strong>Question 1</strong></p> <p>I don't think you need biasing but, if you plan to use the Digi-pot at anything above audio, the terminal capacitances of the wiper and A/B will become very significant. Have you looked at the capacitances in the <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/21945e.pdf" rel="nofollow noreferrer">data sheet</a>? Why not try simulating stage 3 and see what I mean: -</p> <p><a href="https://i.stack.imgur.com/w8uwh.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/w8uwh.png" alt="enter image description here" /></a></p> <p>I believe that the gain is likely to start to increase above audio (around 20 kHz) and become just too high at 1.5 MHz. Digi-pots are very difficult to use at these sorts of frequencies due to internal parasitic capacitances. Also, they have a natural imbalanced capacitance between A/B and wiper that might disturb the balanced signal you are trying to amplify.</p> <p>Looking at your circuit a bit more reveals that you are using 10 kΩ feedback resistors in the stage 3 op-amps. The effect of this and 120 pF to ground on the wiper means a 3 dB increase in gain at 137 kHz. If this resistor was reduced to 1 kΩ that 3 dB change would occur at 1.37 MHz. You might be able to live with this but, if you can't then you'll just have to keep on lowering it.</p> <p>But then you might run into op-amp loading problems and, the current into the Digi-pot input might exceed limits. Maybe you can also find a better low-capacitance Digi-pot. It's been a while since I looked so I can't recall what I chose but, my circuit was limited to 100 kHz.</p> <p><strong>Question 2</strong></p> <p>A low differential input resistance isn't as bad as what it seems; given that op-amps are used in linear applications, due to the virtual ground effect, both inputs of the op-amp will be at very close to the same voltage hence, the differential current into the op-amp inputs will be quite low.</p>	<p>I have a differential IF (intermediate frequency) signal generated by an ADL5801 RF mixer.</p> <p>Stage 1: the signal is amplified before active filtering and it has LC LPF in the beginning for filtering unwanted frequencies above 2 MHz.</p> <p>Stage 2: the signal is passed through a Sallen-Key HPF with -40 dB/dec, Fc= 400 KHz.</p> <p>Stage 3: the signal needs more amplification because of filtering in stage 2. The gain is not fixed. It will be controlled by an MCU with a digital potentiometer. Stage 3 is suggested <a href="https://electronics.stackexchange.com/questions/697047/opamp-schematic-connection-questions-and-dc-biasing">in this section</a> as an answer to my other question which simplified the circuit.</p> <p>ADC range is 0 - 3.3 V and max sampling frequency is 5.6 MHz or 3.3 MHz will be used. Signal frequency range of interest is 1 kHz to 1.5 MHz or so. 1.65 V is generated by an LDO which is stable with 10 μF output capacitance.</p> <p>My questions are:</p> <ol> <li><p>Do I need biasing at stage 3 (ADA4807 part of the first schematic)? Is stage 3's design correct in general?</p> </li> <li><p>Both the LT6232 and the ADA4807 have a low differential input resistance (7.5 kΩ and 35 kΩ). What resistor values should I select for gain, or do I need another op-amp?</p> </li> </ol> <p><a href="https://www.mouser.com.tr/datasheet/2/609/ADA4807_1_4807_2_4807_4-3119636.pdf" rel="nofollow noreferrer">ADA4807 Datasheet</a></p> <p><a href="https://www.analog.com/media/en/technical-documentation/data-sheets/623012fc.pdf" rel="nofollow noreferrer">LT6232 Datasheet</a></p> <p><a href="https://www.analog.com/media/en/technical-documentation/data-sheets/adl5801.pdf" rel="nofollow noreferrer">ADL5801 Datasheet</a></p> <p><a href="https://i.stack.imgur.com/RSfJI.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/RSfJI.png" alt="Schematic" /></a></p> <p><a href="https://i.stack.imgur.com/ur4h9.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/ur4h9.png" alt="Schematic 2" /></a></p>	Differential amplifier op-amp schematic connection and DC biasing	2024-01-10T16:59:17.217
697092	\|fan\|acoustic-noise\|	<p>Note V.I.7 on page 11 of the datasheet says not to use PWM on either the ground or power terminal to control the fan speed - likely because of the internal drive/monitoring electronics. Your plan to supply a constant 3.3V to drive the fan should work, as it is inside the operating voltage range of 2.5-6V. This of course does not preclude using the spare MOSFET to turn it on and off.</p> <p>I would also measure the current draw at 3.3V and make sure that it is acceptable for the entire power path since the values on the datasheet may have been measured at 5V.</p>	<p>I'm using a 25x10mm fan (<a href="https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/2315/MF25100V1-1000U-A99.pdf" rel="nofollow noreferrer">Sunon MF25100V1-1000U-A99</a>) - I was using a different fan from the same manufacturer (<a href="https://www.digikey.com/en/products/detail/sunon-fans/MC25060V2-000U-A99/2757803?s=N4IgTCBcDaILIGEwFYAMA2VA1MBaVBAqrgIICcZIAugL5A" rel="nofollow noreferrer">Sunon MC25060V2-000U-A99</a>) and just plugging it right 5V/GND and it worked fine. Unfortunately that fan went obsolete / out-of-production, and I selected the other fan to replace it. I find that the new fan is much louder in the same electrical setup, to the point where I don't think it's tolerable for the end-users of my product.</p> <p>So I'm doing some experimenting to try and solve this problem, and I decided to try PWM'ing the fan through a spare open/GND n-channel MOSFET which I happen to have on my board under software control. The circuit looks like this (using <a href="https://www.diodes.com/assets/Datasheets/ds30937.pdf" rel="nofollow noreferrer">DMN2004DMK-7</a>):</p> <p><a href="https://i.stack.imgur.com/4bxfr.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/4bxfr.png" alt="enter image description here" /></a></p> <p>I'm connecting the fan's red wire to 5V and the black wire to /DIN1 (aka pin D1), and PWM'ing the DIN1 signal (aka pin G1) in software with a 3.3V MCU output. For various settings of duty cycle and frequency, I can give up some airflow and drastically reduce the fan noise. It seems like the lower I set the frequency, the higher I can go in duty cycle to a similar effect, and in all cases of frequency, there's a single step in duty cycle (dependent on frequency) where the fan suddenly goes from being reasonably quiet to being loud.</p> <p>I've settled (somewhat arbitrarily) on a PWM frequency of 18kHz and a duty cycle of 200 / 255 = ~78.5%. I'm not trying to implement variable fan speed control or anything like that, I just want a reasonably constant airflow through my enclosure and make the fan noise not be obnoxious. It seems like it's doing what I want.</p> <p>Am I making a terrible mistake here? Any advice on whether my choice of frequency and duty cycle is a good one? Just looking for experience-based feedback on the mitigation strategy I'm attempting here.</p>	25x10mm 5V fan is too loud	2024-01-10T17:34:03.967
697093	\|atmega\|feedback\|proteus\|	<blockquote> <p><em>I tried using the DS1631 thermostat for this purpose, but the current temperature in Proteus can only be set manually, whereas I need programmatic control.</em></p> </blockquote> <p>Use an ADC fed by a voltage source to emulate a variable temperature digital input into your MCU. The voltage source can be from a DAC if you wish to maintain full control of the process from one MCU to the other.</p> <p>Or, if your MCUs have analogue inputs and digital outputs, use those. 1 volt can represent whatever temperature you want!!</p>	<p>I am writing a term paper on the topic "Modeling of an Artificial Blood Circulation Apparatus". The task is to design a control unit based on the ATmega128 microcontroller in Proteus software. It was decided to implement two feedback loops: one regulates the mean blood pressure, and the other regulates blood temperature. Since there is no concept of the "environment" in the software, I had to use a second microcontroller to emulate the organism. <a href="https://i.stack.imgur.com/45kvU.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/45kvU.png" alt="Current state of model" /></a> Pressure regulation is implemented as follows: the artificial blood circulation apparatus (AICA) controls the pump rotor, thereby regulating the blood flow rate. The blood flow rate is "felt" by the "organism" (the second microcontroller) by reading pulses from the motor encoder. Then, the motor rotation frequency is formulaically converted into a blood pressure value, and this value is transmitted to the first microcontroller (AICA control unit) using a smoothed PWM signal, simulating the operation of a pressure sensor.</p> <p>The question is as follows: how to now implement a temperature regulation system? I tried using the DS1631 thermostat for this purpose, but the current temperature in Proteus can only be set manually, whereas I need programmatic control. <a href="https://i.stack.imgur.com/lILzk.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/lILzk.png" alt="DS1631 model in Proteus" /></a></p>	Designing a temperature feedback loop in Proteus	2024-01-10T17:46:27.943
697099	\|safety\|frequency-measurement\|signal-generator\|	<p>This contraption is supposed to power a <a href="https://www.youtube.com/watch?v=4V__6X4CyXg&t=275s" rel="nofollow noreferrer">plasma tube</a> which looks suspiciously like a neon tube, so the high voltage transformer will have <strong>at least several kV output</strong>.</p> <p>Internal wiring is complete garbage, I can't even see on the photos where the high voltage wires go or if they use insulation rated for this voltage. Given the mess, there could be all sorts of arcing opportunities between high voltage wires and... everything else.</p> <p>Then the high voltage is output on banana jacks, which is insane. Held together with hot melt glue.</p> <p>I find the switch above the banana jacks particularly tasteful:</p> <ul> <li><p>It is probably within arcing distance of the high voltage.</p> </li> <li><p>Its placement means fingers will be in close proximity to high voltage on banana plugs held together with hot melt.</p> </li> <li><p>It says "Footbath".</p> </li> </ul> <p>Honorable mention for the note that says that if it is arcing, you have to put your finger on the thing to turn it off.</p> <blockquote> <p>How safe is this apparatus?</p> </blockquote> <p>It probably won't cure cancer. But at least the user won't die of cancer when they get electrocuted, so there's always that.</p> <p>The most reliable item in this device is probably the wago XD</p> <p>Related <a href="https://www.youtube.com/watch?v=BGD-oSwJv3E" rel="nofollow noreferrer">safety video</a>.</p>	<p>A close friend bought a <a href="https://www.truerife.com/product-page/f-122-with-v-software-software-version-6" rel="nofollow noreferrer">TrueRife frequency generator</a> in hope of improving health. I'm skeptical of the claimed healing powers, however let's put this aside for a moment; if it helps - great! The question is not about that.</p> <p>The above linked page states:</p> <blockquote> <p>Please note there are no Ground Ports on Generators produced after June 2023. All of our grounding products plug directly into a wall outlet and new grounding units will need to be purchased if you have old products that used to plug into the machine.</p> </blockquote> <p>There's a warning label on the top cover of F-122: <a href="https://i.stack.imgur.com/fXye3.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/fXye3.jpg" alt="" /></a></p> <p>Concerned from the stories about <em>high voltages, high currents, static zaps, and necessity for grounding</em>, I opened the <strong>entirely plastic</strong> case to check what's inside, and I'm flabbergasted: <a href="https://i.stack.imgur.com/9XBX7.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/9XBX7.jpg" alt="3" /></a></p> <p>A circuit board "SG03-" with Lattice iCE40HX1K Field Programmable Gate Array, USB 3.0 (Type B) port, and 12V power input, <em>seems to be the only properly engineered component</em>. <a href="https://i.stack.imgur.com/XVVQT.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/XVVQT.jpg" alt="4" /></a></p> <p><a href="https://i.stack.imgur.com/h3RmS.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/h3RmS.jpg" alt="5" /></a></p> <p><a href="https://i.stack.imgur.com/NVFZd.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/NVFZd.jpg" alt="6" /></a></p> <p>The tightly packed mess in the middle with lots of electrolytic caps must be a PSU.<br /> Outputs (12V DC). Notice bad soldering: <a href="https://i.stack.imgur.com/kwQsl.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/kwQsl.jpg" alt="7" /></a></p> <p>Inputs (120V AC). Notice the melted T2.5A 250V CQ MST microfuse corner: <a href="https://i.stack.imgur.com/EaqaU.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/EaqaU.jpg" alt="8" /></a></p> <p>On the other side of PSU is a transformer with open(? or non-looped?) core. <a href="https://i.stack.imgur.com/YUnDN.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/YUnDN.jpg" alt="can't see where is 0.25mm red going to" /></a></p> <p><a href="https://i.stack.imgur.com/clOWH.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/clOWH.jpg" alt="10" /></a></p> <p><a href="https://i.stack.imgur.com/PskJG.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/PskJG.jpg" alt="11" /></a></p> <p>The back wall houses two (plus one spare, not connected) 2N6284G power transistors <em>with heatsinks</em>, soldered together in some really funky way. There's also a fuse, which is wired between ground from the power cable and Darlingtons' emitters (blacks, also see 1st photo). <a href="https://i.stack.imgur.com/zy1Qb.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/zy1Qb.jpg" alt="12" /></a></p> <p><a href="https://i.stack.imgur.com/Qp4j1.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/Qp4j1.jpg" alt="13" /></a></p> <p>Some wires are hard to trace. Here's my best effort (may have diodes in reverse): <a href="https://i.stack.imgur.com/tleAM.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/tleAM.png" alt="" /></a> I marked wire colors (in parenthesis) and nominations, where identifiable.</p> <p>I am a 30y computer engineer with some experience specifically in electrical work. This cobweb of wires makes me shudder, even though they are soldered in most places (as opposed to pin connectors - better solid contact). Here're some of my issues:</p> <ul> <li>Wires soldered together in the middle (e.g. 2nd red +12V from the top of PSU)</li> <li>Tightly packed electrolytic caps inside a heatsink (top of PSU)</li> <li>WAGO 221 clamp to connect a ~2mm thick black output cable with 0.25mm red (not sure where is it from, if that's the core can it be 120V AC?), 0.5mm black from the winding, and two more 0.5mm black wires going to front LEDs</li> <li>PSU board mounted on a foam pad</li> <li>No ventilation of any kind in the case</li> <li>Power transistors (rated 100V 20A 160W) mounted on the outside with heatsinks on the plastic wall</li> <li>Excessive hot glue to "clamp" cables and other components</li> <li>Even the hole for USB port could have better fit</li> </ul> <p>To me this looks like a poorly executed one-time garage project.</p> <p>My questions:</p> <ol> <li><strong>How safe is this apparatus?</strong></li> </ol> <ul> <li>for plugging into a home outlet</li> <li>for touching /making contact to body</li> </ul> <ol start="2"> <li><strong>Is there any way to scientifically verify generated frequencies?</strong></li> </ol> <ul> <li>With an oscilloscope? Any advice, how exactly?</li> </ul> <p><strong>UPDATE 2024-Jan-11</strong>:</p> <ul> <li><p>Added 1st (so question reads more consistently) photo of a warning label on top cover.</p> </li> <li><p>A device of similar purpose (<a href="https://www.spooky2.com/generatorx/" rel="nofollow noreferrer">Spooky2 Generator X</a>) has full metal case, ventilation holes on 2 sides, proper USB port cutout, and is powered by 12VDC 2A wall wart PSU.<br /> At least that makes more sense to me.</p> </li> <li><p>Upon digging deeper through TrueRife's website I found the <a href="https://www.truerife.com/_files/ugd/159cea_9af316e2c238481e87ce8a27df8984f6.doc?dn=F-122%20Manual%202023.doc" rel="nofollow noreferrer">F-122 manual</a>!</p> </li> </ul> <p>I may be wrong about the need for skin /body contact, but they mention <em>footbaths with salted water</em> in manual and <a href="https://youtu.be/xSpd3GNprHY" rel="nofollow noreferrer">video</a>, which makes me really nervous. Due to high voltage /current warnings combined with shoddy manufacturing this looks like an electrical and/or fire hazard.</p> <p><strong>UPDATE 2024-Jan-15</strong>:</p> <ul> <li>Added an electrical schema.</li> </ul>	How safe is this TrueRife F-122 frequency generator?	2024-01-10T19:02:39.120
697107	\|switches\|toggle-switch\|undervoltage\|	<p>Looking at the datasheet, it appears as though the solenoid is only used to hold the internal plunger in the activated position once it has been placed there manually with the switch baton, not to electrically remotely activate the switch, hence the absence of separate "pull-in" and "holding" current ratings. However, the switch is qualified for flight deck use on military aircraft, where the plunger <em>must not</em> move under extreme shock or vibration conditions so the holding force is probably far in excess of what you'd need to hold it in under "normal" use.</p> <p>For casual, non-critical use, I'd do a few tests (let the coil warm up) to see where it drops out and then give yourself a healthy margin (25-50%) between the highest measured voltage and 28V.</p> <p>Or you could try emailing Honeywell. I've had long, involved conversations with TDK-Lambda engineers about products that cost less than one of those switches.</p>	<p>I have acquired a <a href="https://prod-edam.honeywell.com/content/dam/honeywell-edam/sps/siot/ja/products/switches/toggle-switches/et-series/documents/sps-siot-micro-switch-et-toggle-product-sheet-005433-1-en-ciid-159442.pdf" rel="nofollow noreferrer">Honeywell ET series switch (best datasheet I could find)</a> whose holding coil is rated to run on 28 VDC. I know it is often deployed in aeronautical environments where voltage can drop to near 24 V when operating on battery.</p> <p>From my testing, the switch seems to hold reliably with voltages as low as 7 V. With such low voltages, the force required to bring the switch to the OFF position without cutting power is much lower.</p> <p>Up until now, I've considered its coil analogous to the one of a relay. I know most of these really shouldn't be undervolted, but is that only coming from the fact their construction is usually of lower quality and thus wouldn't operate reliably on lower voltages?</p> <p>Would I need to beware of undervolting this switch to something like 9 V to reduce the force required to turn it off mechanically? What precautions should I take if I go forward with such a design?</p> <p>This is only for a personal project of mine and wouldn't be deployed at scale so any variance in the manufacturing of different switches is not a factor to me. I can adapt my system to the tolerances of mine if need be.</p> <p>I find it very hard to find such information on the limits of MIL spec components since they are almost never used by most hobbyists.</p>	Undervolting magnetically held switches	2024-01-10T19:31:02.747
697112	\|dc-dc-converter\|switching-regulator\|	<p>When making high-frequency switchers, one should always follow "reference designs" and <a href="https://prom-electric.ru/media/MT3608.pdf" rel="nofollow noreferrer">recommended board layouts</a>, due to presence of "<a href="https://www.ti.com/document-viewer/lit/html/SSZTBF4" rel="nofollow noreferrer">high-current loop</a>s" in switching converters. Can you see the differences between your layout and the reference? I would also try to follow the reference BOM, because some overlooked parasitics of components may affect declared performance of the device.</p> <p><a href="https://i.stack.imgur.com/yyrhR.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/yyrhR.png" alt="enter image description here" /></a></p>	<p>I have PCB printed a board that feeds a 12V led strip from either a Li-ion battery or a 5V USB. With no load, the output is 12V, as it should. As soon as I connect the led strip (80mA at 12V), the output voltage drops to ~8V, and the current drops to a few mA. The circuit also produces a distinct high-freq sound when a load is connected. However, the circuit works fine with other input voltages. Below is the list of working and non-working input voltages, and the current:</p> <ul> <li>Vin < 3.0: does not work (expected)</li> <li>3.0 < Vin < 3.7: works, I ~ 450 mA</li> <li>3.7 < Vin < 5.5: does not work, I ~ 20 mA</li> <li>Vin > 5.5: works, I ~ 240 mA</li> </ul> <p>The current flows from the top to the bottom in the pic below. It's a one-sided board.</p> <p>C4: 25V 22uF X5R ±20% 0805</p> <p>L1: 2.3A 10uH ±20% SMD,5x5mm</p> <p>D5: 40V 0.45V 5A DO-214AA Schottky</p> <h2>Version 1</h2> <p><a href="https://i.stack.imgur.com/YRmMS.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/YRmMS.png" alt="enter image description here" /></a> <a href="https://i.stack.imgur.com/xangA.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/xangA.png" alt="enter image description here" /></a></p> <p>Questions:</p> <ol> <li>why does it behave like this?</li> <li>how can I fix it?</li> <li>can I fix it without re-printing the PCB?</li> </ol> <p>There are related questions:</p> <ul> <li><a href="https://electronics.stackexchange.com/questions/477651/mt3608-improper-output-voltage">MT3608 Improper Output Voltage</a></li> <li><a href="https://electronics.stackexchange.com/questions/630287/mt3608-wrong-output-voltage">MT3608 wrong output voltage</a></li> </ul> <p>but the former hasn't shown how far the capacitor had been placed in the beginning (is my cap C4 placed too far or acceptable?) and after he found the solution, and the latter seems to be not resolved, only hints.</p> <hr /> <h2>Version 2</h2> <p>After reading the replies, I updated the layout as follows:</p> <p><a href="https://i.stack.imgur.com/xai1m.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/xai1m.png" alt="enter image description here" /></a></p> <hr /> <h2>Version 3</h2> <p>Where possible, replaced tracks with copper pour.</p> <p><a href="https://i.stack.imgur.com/dvcnl.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/dvcnl.png" alt="enter image description here" /></a></p> <hr /> <h2>Version 4</h2> <p>Tight SOT23-6 footprint, removed R_EN.</p> <p><a href="https://i.stack.imgur.com/pGgXZ.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/pGgXZ.png" alt="enter image description here" /></a></p> <hr /> <p>Full project link: <a href="https://github.com/dizcza/flashlight_kicad" rel="nofollow noreferrer">https://github.com/dizcza/flashlight_kicad</a></p>	MT3608 is not switching for particular input voltage	2024-01-10T19:51:43.500
697118	\|capacitor\|adc\|filter\|	<p>There's two components of noise at play, both of which are worth trying to mitigate:</p> <ul> <li>one is the noise in the differential measurement across the bridge</li> <li>the other is the noise seen symmetrically on both sides of the bridge</li> </ul> <p>The chip is intended to perform a differential measurement, and represent the difference between the two inputs as its output, so at first glance it seems that the common-mode noise should be ignored. However, this common-mode rejection is not perfect, and is characterized a specification known as "common-mode rejection ratio" (CMRR). At quick glance, I wasn't able to find a CMRR-vs-frequency plot in the datasheet(^), but often, CMRR gets worse with increasing frequency.</p> <p>The names of the capacitors provide a key clue as well: C_DIF (for differential) vs C_CM (for Common Mode). The two CM capacitors are placed symmetrically on the two lines to ground, thus symmetrically attenuating common-mode components of any high-frequency noise.</p> <p>Meanwhile, C_dif will not attenuate the common-mode component to any appreciable extent; since the common-mode noise is seen equally on both terminals, no high-frequency current flows through C_dif in response.</p> <p>As the datasheet points out, the two capacitors (and likewise the two upstream series resistors) ought to be well-matched, as their mismatch will convert common-mode noise into differential noise (which then gets measured directly by the chip if not well-attenuated by C_dif).</p> <blockquote> <p>I understand the point of CDIF1, which is to mirror noise from one signal to the other</p> </blockquote> <p>Not quite. It doesn't "mirror" noise from one to the other (in the sense of turning DM noise into CM noise), but rather it shunts that noise away by allowing current to pass at high frequencies in response to differential voltages, which creates a low-pass filter structure</p> <p>^ CMRR is given in plots on page 14 and the table on page 8. The provided spec seems to only discuss CMRR at DC and for 50/60 Hz (likely expected powerline noise).<br /> ^^ A mechanical analogy for CMRR, for readers that prefer an intuitive visualization: Imagine measuring an object with a ruler while on a bumpy train ride; while all of the motion is common-mode (both ends of the object move together), you'll still have a difficult time with yourself, your workpiece, and the floor thrashing about.</p>	<p>The circuit below can be found on page 59 of the ADS122C04 chip <a href="https://www.ti.com/lit/ds/symlink/ads122c04.pdf?ts=1638364197104&ref_url=https%253A%252F%252Fwww.google.com%252F#:%7E:text=The%20ADS122C04%20is%20a%20precision,applications%20measuring%20small%20sensor%20signals.&text=At%2020%20SPS%2C%20the%20digital,rejection%20for%20noisy%20industrial%20applications." rel="nofollow noreferrer">datasheet</a>. The purpose is to take the differential input of two voltages from a resistive bridge. For example, I am using it to collect data from a load cell. I understand the point of C<sub>DIF1</sub>, which is to mirror noise from one signal to the other so that the differential input is not affected by said noise. I also understand the point of R<sub>F1</sub> and R<sub>F2</sub>, which would be to allow the capacitor to do its job just as any RC circuit functions. <p>What I don't understand is what the point of C<sub>CM1</sub> and C<sub>CM2</sub> are. I would have thought they were there to filter out noise, but isn't that what C<sub>DIF1</sub> is for? Are they redundancy layers for each other, any noise that isn't filtered to ground gets mirrored to the other signal, and vice versa?</p> <p><a href="https://i.stack.imgur.com/6RopI.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/6RopI.png" alt="Reference circuit from the ADS122C04 datasheet" /></a></p>	What is the function of CCM1 and CCM2 in this resistive bridge measurement circuit?	2024-01-10T20:00:22.260
697121	\|digital-logic\|circuit-design\|logic-gates\|ttl\|7400\|	<p>It should be sufficient to watch just one of the outputs of the 6820 to detect the high impedance state of the output driver.</p> <p><img src="https://i.stack.imgur.com/Lfl92.png" alt="schematic" /></p> <p><sup><a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fLfl92.png">simulate this circuit</a> – Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a></sup></p> <p>The series resistor ladder R1-R4 sets half of the supply voltage at V_BUS for the high impedance state. In this state none of the MOSFETs is conducting, Vgs is below the threshold. NOE_B is high and so the output driver of the 74LS240 is disabled.</p> <p>The resistor values are relative low to ensure fast switching of the MOSFETs. Higher values may be acceptable if the circuit deals only with slow I/O signal changes. This was not specified.</p> <p>The switches SW1 and SW2 represent the tri-state buffers of the ICs.</p> <p>If NOE_A is low, V_BUS is either high, which turns M2 on, or it is low, which turns M1 on. If M1 is conducting this also turns M2 on via R8, so M2 is always conducting if V_BUS is not in the high impedance state. This reconstructs the original NOE_A signal with around 200 ns delay at NOE_B.</p> <p>R9 just emulates the estimated output driver strength of the 6820.</p> <p>R6 and R7 are added to show the high impedance state of the 74240 in the simulator, so V_BUS and OUT_B can be compared in the diagram.</p> <p>There is a very short glitch in V_G during a high/low level change of V_BUS, but this does not reach NOE_B.</p>	<p>I have two TTL style logic chips, call them <strong>A</strong> and <strong>B</strong> (), where the outputs of A are the inputs to B (think: 8 data lines). <strong>A</strong> has tri-state outputs, so when they are turned off they float. <strong>B</strong> is an inverting buffer which also offers tri-state outputs (if you toggle off its chip enable)</p> <p>What I'd ideally like to do is "detect" the high-z state seen at the <strong>A</strong> outputs and use that state to disable the chip enable for <strong>B</strong> (thus causing <em>it</em> to go to hi-z on <em>its</em> outputs). This is because, otherwise, when the output of <strong>A</strong> is floating and "meaningless", the output of <strong>B</strong> is also meaningless, but will be driven and not predictable.</p> <p><strong>A</strong> is an interface chip that goes into high-z outputs based on internal state, so there's no trivial enable line to <strong>A</strong> that I can simply also use for <strong>B</strong>.</p> <p>I'm a still-learning hobbyist here. <a href="https://electronics.stackexchange.com/questions/164493/detecting-hi-z-state-of-charge-controller">This question suggests</a> that using a voltage divider on an output from <strong>A</strong> can result in three well-known states, which could be used to do other stuff. I'm not sure exactly how, or what would be involved in that? Could someone offer a thought on how they might think about achieving this?</p> <p>(The backup plan, which seems less elegant, is simply to use pull-ups or downs on all of the inputs to <strong>B</strong> so that <strong>B</strong>'s outputs may be always-on but are always predictable.)</p> <p>() A is a 6820 PIA and B is a 74LS240, but I don't think that's critical to the question.</p>	Simple TTL: Is there a way to "detect" a high-z state and easily use that to drive other logic?	2024-01-10T20:19:22.680
697134	\|led\|resistors\|circuits\|motherboard\|sata\|	<p>Take a black Sharpie and apply some physical dimming to the led. it may take several applications.</p> <p>Other brands of permanent marker will also work. the ink is non-conductive and will not alter the electrical perfomance of the circuit.</p> <p>Removing the LED will probably work and not compromise the performance of the circuit, but there is an increased risk especially if you're a klutz like me.</p>	<p>So, I've bought this SATA case from internet but it has a really bright light on it and annoys me. I don't haver any kind of tool to manage any electronic component, and neither have electrical tape to hide this light, so I would like to know if it is safe and it will continue working if I remove it with a knife or something like that (touching only the light, ofc)</p> <p><a href="https://i.stack.imgur.com/HF65m.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/HF65m.jpg" alt="photo of the circuits" /></a></p> <p><a href="https://i.stack.imgur.com/X5mJ5.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/X5mJ5.jpg" alt="complete photo" /></a></p> <p>I want to remove the LED2.</p>	Is it safe to remove this LED from that motherboard?	2024-01-10T22:11:25.690
697138	\|altium\|	<p>Constraint manager is a new feature in Altium and it is intended to replace the Rules in the future. When old projects are opened in Altium, the intended behavior is that Rules are used. When new projects are created in Altium, the intended behavior is that Constraint Manager is used.</p> <p>Doesn't quite work correctly.</p> <p>This is from memory, so might be a bit off...</p> <p>Go into your Altium settings. At the bottom right, there's an "Advanced" button. Click it. Search for "constraint" and disable the two constraint manager options there and restart Altium. This will force Altium to use the legacy rules.</p>	<p>I'm encountering an issue in Altium Designer that is proving to be quite challenging. After importing some libraries into my PCB projects and updating the PCB, I noticed that the "Rules" section under the Design tab has disappeared. I've tried opening new projects and even deleting the recently added libraries, but to no avail.</p> <p>Currently, all I see is the Constraint Manager, and the absence of the Rules section is causing complications in my workflow. I'm seeking assistance on how to revert this or bring back the Rules section.</p> <p>Any guidance or suggestions on how to resolve this issue would be greatly appreciated. Thank you in advance for your help!</p> <p>Altium Version: 23.11.1</p> <p><a href="https://i.stack.imgur.com/aauKi.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/aauKi.png" alt=" " /></a></p>	Altium Designer Constraint Manager instead of Rules Tab	2024-01-10T22:35:12.337
697139	\|motor\|servo\|encoding\|position-sensor\|	<p>Most available stepper motors rotate 360deg. If you need position then you'll need one with an encoder or other rotary position system (resistive). You can however drive steppers open loop so you can 'home' them with a switch and then step them X steps away from that position and they'll go there if within their torque range (ie nothing blocking it)</p> <p>You can also take many hobby servo motors that are 90deg or 180deg and make it into a 360deg, but I don't know if that will give you 'position-ally' aware.</p> <p>Instructions here: <a href="https://www.circuitbread.com/tutorials/how-to-make-a-360-degree-continuous-rotation-servo-motor" rel="nofollow noreferrer">https://www.circuitbread.com/tutorials/how-to-make-a-360-degree-continuous-rotation-servo-motor</a></p>	<p>Most servo motors out there are driven within 180° (at least hobby ones). There are more bulky and expensive servos out there as well. Since, I have tight space constraints, I am looking for a solution to have full positional awareness (0-360°), an can even cross 360° boundary for shortest path rotation.</p> <p>e.g. from 350° to 10° in 20° step and not with a 340° backwards rotation.</p> <p>The servo modifications, which I have found remove positional awareness for continuous drive. I have been wondering, what solutions are common out there? I remember taking apart an inkjet printer to find a transparent disk attached to the motor with black stripes for opto-interrupt encoding. I guess, this would be solution. I might as well use a geared DC motor or a stepper motor for this purpose. I was wondering, what solutions are commonly used for this purpose. I will have an IC to do the controlling but more plug and play solutions are welcome.</p>	Positionally aware 360° (or beyond) motor (DC or stepper)?	2024-01-10T22:37:50.913
697166	\|power-supply\|voltage-regulator\|linear-regulator\|	<p>Reconsider a derived power supply for the opamp. If the Power Q is a darlington, the opamp needs only 5 to 10 mA of operating and output current. This can be done with 1 zener diode, 1 resistor, and 1 noise filter capacitor. 50 cents? You don't show a power supply decoupling capacitor for the opamp, but it already should be a part of the control schematic.</p>	<p>I'm building a linear power supply. The first stages are all working great. Coming out of the rectifier and filter caps, I have 28V DC. I also have a voltage reference circuit (LM317) that gives me a stable 14V.</p> <p>Here's a schematic of what I have so far:</p> <p><img src="https://i.stack.imgur.com/yrdlR.png" alt="schematic" /></p> <p><sup><a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fyrdlR.png">simulate this circuit</a> – Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a></sup></p> <p>I now want to add the regulation circuit for the output transistors. Similar to a power supply I built before, I was just going to use an op amp to drive the output transistors (probably through a high current buffer) so the output voltage matches the reference voltage. I also had a transistor for current limiting, like this:</p> <p><img src="https://i.stack.imgur.com/Vy6M7.png" alt="schematic" /></p> <p><sup><a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fVy6M7.png">simulate this circuit</a></sup></p> <p>However, that would require me powering the op amp off of 28V (under no load), and the most any of the op amps I have can handle is 22V supply. I'm figuring I can't run the op amp off of the 14V line since its output will likely need to be higher than 14V to drive the output transistor.</p> <p>I could buy other op amps, but I'm curious if I can get by with what I have.</p> <p>I know I could just make a step down circuit to power the op amp, but I'm thinking there has to be a more elegant solution. Is there a more elegant/better solution?</p>	Alternate voltage regulation for a linear power supply	2024-01-11T05:40:22.183
697173	\|control-system\|charger\|gate-driving\|component-selection\|llc-converter\|	<blockquote> <p>I don't understand how can I control the MOSFET's switching cycle with control input of gate drivers. In the market there is a resonant driver but I don't understand how to control it digitally with, for example, an FAN7621.</p> </blockquote> <p>FAN7621 is not what you are looking for. You can't control it digitally as it's an analog controller which has everything internally.</p> <p>What you need is a combined high- and low-side driver, not a controller. There are many gate drive ICs in the market. IR2112 is one of them, though I don't recommend it.</p> <ul> <li>These ICs generally use <a href="https://toshiba.semicon-storage.com/eu/semiconductor/knowledge/faq/linear_high-voltage-ipds/high-voltage06.html" rel="nofollow noreferrer">bootstrapping</a> to drive the high-side switch, so make sure the IC's bridge node (generally named as VS node) voltage rating is higher than your maximum DC input voltage. For example, IR2112's VS node rating is 600V, and if your max DC input voltage is 450V then it's suitable.</li> <li>For LLC HB converter the dead time is important, especially for ZVS (zero voltage switching), overall efficiency and general operation. So make sure the IC you select does <strong>NOT</strong> generate a fixed dead time or if it does it should match your needs. Ideally, it should be under your control for maximum performance.</li> <li>You may also want a high peak drive current capability (generally around 1 A) for simplicity. Although the turn on time is not important in an LLC so a relatively high gate stopper resistor (which means lower peak gate drive current) generally works, the turn off time is important. So if you don't want external transistors (i.e. totem pole or push-pull) it's better to choose an IC with high peak current capability.</li> </ul> <hr /> <p>Another options are:</p> <ol> <li>Drive the low-side switch directly and the high-side with a dedicated high-side driver.</li> <li>Use gate drive transformers.</li> </ol>	<p>I am designing a LLC half bridge charger. I am going to use a microcontroller to control the switching frequency, with feedback from the output to smoothly control the switching requency.</p> <p>I don't understand how can I control the MOSFET's switching cycle with control input of gate drivers. In the market there is a resonant driver but I don't understand how to control it digitally with, for example, an FAN7621.</p>	Gate driver selection for digitally controlled via PFM, LLC resonant half bridge charger	2024-01-11T07:18:55.583
697183	\|antenna\|ground\|transmission-line\|electric-field\|faraday-cage\|	<p>Taking example of the ground plane antenna, consider the case with a monopole, perpendicular to multiple ground spokes in a plane:</p> <p><a href="https://i.stack.imgur.com/qNjA2.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/qNjA2.png" alt="enter image description here" /></a></p> <p>Suppose we have a feedpoint voltage Vs (and more generally a port, with feedline and incident and reflected waves, not shown).</p> <p>Within a certain degree of symmetry, we can consider each ground spoke as its own monopole with respect to the rest.</p> <p>Notice the geometric symmetry is not perfect, because the remaining spokes and the monopole element (considering Vs = 0 by superposition) do not form a plane perpendicular to the spoke in question, whereas they do for the monopole. This moderately affects the characteristic impedance of the element in question, but does not change the overall argument.</p> <p>Considering a spoke as a driven element, like any other element, it exhibits a characteristic impedance, looking into its feedpoint. In normal use, that feedpoint is connected to an approximate short circuit -- Rg being a small value. But "approximate" is not "perfect". The element has some resistance along its length, which for reasons not important to go into here, can be represented as an equivalent total resistance at the base, and the rest of the element assumed ideal.</p> <p>Given the symmetry (and limitations as noted), the characteristic impedance of the spoke as an element, will be comparable to the monopole element itself, typically 30-40Ω. We can understand the effect of Rg, when it is small in relation to this impedance, as the reflection coefficient at that port.</p> <p>The <a href="https://en.wikipedia.org/wiki/Reflection_coefficient" rel="nofollow noreferrer">reflection coefficient</a> is given by,</p> <p><span class="math-container">$$ \Gamma = \frac{Z_L - Z_0}{Z_L + Z_0} $$</span></p> <p>For <span class="math-container">\$Z_0 = 40\,\Omega\$</span> and say <span class="math-container">\$Z_L = R_g = 0.1\,\Omega\$</span>, we have <span class="math-container">\$\Gamma = 0.995\ldots\$</span>, quite high <em>but not exactly one</em>.</p> <p>So, we have some energy absorbed in the element, but most of the incident energy is reflected in phase.</p> <p>Important take-away: real situations are always both absorption and reflection simultaneously. (Or transmission, if applicable.) How much of each, is the question. Real in-practice ground planes, wires, shields, waveguides, etc. act as guides or mirrors to incident waves, usually to quite a good degree (a mirror below 90% reflectivity might be considered poor even at optical frequencies, and over 99% is typical at radio frequencies). But we must keep in mind there is always absorption in that small remainder below 100%.</p> <hr /> <p>We also have high reflectance for <span class="math-container">\$\Gamma \rightarrow -1\$</span>. What would that do?</p> <p>We could connect the element(s) open-circuit, which gives this condition. The meaning of negative Γ is that waves reflect in opposing phase. What does this do to the monopole-with-ground-plane antenna? Well, the reflected waves would oppose the driven element's waves, and... nothing happens. Which is as we expect: Vs would be essentially open-circuit on one side (all Rg's infinite), so feedline current cannot flow.</p>	<p>From my current knowledge, any metal whether grounded (and or earthed) or not will reflect radio waves as seen on dishes, Faraday cages, etc. On the other side the ground in transmission lines or the ground planes in PCB, I see more as a place where the fields are absorbed, as the energy travels between the two. It’s always constantly stated to have proper grounding for high speed signals.</p> <p>All in all it seems in different scenarios, metal absorbs the fields, and other times reflects/guides the fields.</p> <p>What is the main reason for this?</p> <p>I am assuming it is to do with the impedance seen to the metal, for instance a Faraday cage or ground plane for antennas is certainly not seen as the impedance of the propagating waves, but that's only my limited knowledge understanding.</p> <p>Which brings on to the actual question: Why would the wires acting as the ground plane on those monopole ground plane antennas be reflecting the signal, when they are directly connected to the coax shield?</p>	Why do the metal sticks (for the ground) on the ground plane antenna reflect and not absorb?	2024-01-11T09:36:15.890
697190	\|mosfet\|ltspice\|small-signal\|	<p>As proposed by @Ste Kulov, waveform arithmetic is exactly what I was looking for. I took the derivative function <strong>d(V(out)/Id(M1))</strong>.</p> <p><a href="https://i.stack.imgur.com/g99PL.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/g99PL.png" alt="enter image description here" /></a></p> <p>Concerning the small signal gain, this can be done by right-click on V1, specify a (small) AC amplitude like 0.01V and change the simulation command to .ac and desired frequency range.</p>	<p>I have a simple NMOS FET where I would like to plot the differential output resistance at the operating point of Vgs = 1.7V (which is the Vgs voltage for Id=9.4mA)</p> <p>I managed to plot the output resistance with the help of the behavioural source B1 as follows:</p> <p><a href="https://i.stack.imgur.com/8w0np.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/8w0np.png" alt="enter image description here" /></a></p> <p>I can read from the difference of cursors 1 and 2 in the plot that the differential resistance should be about 2386 Ohms at Vgs ~= 1.7V.</p> <p>Main question: How can I get a plot of this differential resistance? Is there for example a way to plot the derivative of a trace in LTSpice?</p> <p>Bonus question: How could I plot the small signal gain of this amplifier?</p>	Differential output resistance with LTSpice	2024-01-11T10:28:03.313
697212	\|digital-logic\|logic-gates\|	<p>You can detect any single value in a binary number using a wide-enough AND gate, plus inverters as necessary.</p> <p>The AND gate will detect bits that are '1' while the inverters are needed for bits that are logic '0'.</p> <p>So, for example, in digital logic the below circuit will detect 3-bit value 'n' being 110 binary.</p> <p>Specific value ranges for a binary number can be detected by omitting inputs from the AND gate. So if the below circuit was a 2-input AND connected to n2 and n1, its output would be HIGH when n was 110 or 111 binary i.e. 6..7 decimal.</p> <p>So to your question, an AND gate could detect when an 8-bit counter reached 129 decimal by ANDing just bits n7 and n1. The AND would in fact detect every odd number from 129 to 255 but, if counting up from under 128 for example, 129 is the first one reached and the 2-input AND is sufficient.</p> <p>Using smaller-width gates like ANDs/ORs in this way has been done for a long time to save on gates.</p> <p><img src="https://i.stack.imgur.com/sIEjam.png" alt="schematic" /></p> <p><sup><a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fsIEjam.png">simulate this circuit</a> – Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a></sup></p>	<p>With a incrementing counter, starting from zero, I can tell when 128 is reached by looking for a positive edge on bit:7.</p> <p>I can detect when 129 is reached by looking for a positive edge on (bit:7 & bit:0)</p> <p>I think that I can detect when 130 is reached by looking for a positive edge on (bit:7 & bit:1)</p> <p>Can I AND all the expected set bits together to detect when an incrementing counter reaches a expected value? This will be used to reset the counter.</p>	Can you detect when an incrementing counter has reached N by AND'ing the expected set bits?	2024-01-11T13:26:44.103
697224	\|transistors\|pullup\|	<p>Rather than point out the issues in the original (like inconsistent / missing resistors and misconnected carry-out logic), here's a working example with those problems fixed (<a href="https://www.falstad.com/circuit/circuitjs.html?ctz=CQAgjCAMB0l3BWcMBMcUHYMGZIA4UA2ATmIxARQosgoFMBaMMAKACUQHsqvIAWTt0HZCUMX1pJa06AhYBzQTzAZRXZYWlQWAF055aDFBKWdjWiDAQI8YPmUJE7kYpEvRC2PKrx9s9hBJXbGRaABM6ADMAQwBXABsdFgAnUyNAtNwBWjB4XX1DMGIeISZisXdAvjw8bCxsbGI8JpRiKA8JLD8RN0w%20BAFc8Ki4xJYAdzSUYyn8bVSGAzMTJk1li3hIFM4wNbKeJf2KzYmpjNWzDK3Ji-S1XbMZ6521acHXp9Pbh4eL59vqi8gf9SoCAXh5i8cmolg8cicFodSrtDEJ4Xkbsi1GjtHpFtDTHDwJw%20NAwNYSL1cAZICFSSgKa4wCghsRmGBGBChiAIjEEkkFqCIepOMRROitnikSUZRVODAGnAvAhVGQmb52sxFSg6hhyZ5rJAkNzeaMkooRaUhIDpOw0mK0syIVoTFIxFZTiidigueUmD7tJMvatoYUA887AIQ%20A9l6tqlfg6HQwHRL4yBk5GYzs%20NlQnBPbnvVyi0xmbiM2oHVmU%20LiVY9Xw7OT-E69c7ZM1-OZCLliBIbKEeSN%20dsa16a2hnfn8pmi%20OizkSdB%20v1CJpe14MNUpGTlbZIAzCBhitwQiaR2NFDXYaXCHmthxJ3NJyYXZJ3e05DcihpCn6nUDMw5mjI5oy2AAZYQq2xQhhVTMQYniABnOgQGwDxtCgrgRBzKMRGFLMlyQ1D0Mw9McJgy4qLTbY7jw6CGNom4p2LYDCPLSVqNFV4QIQiAuBXYpCAQX9jAMNl-DIhBhNE4pIBwIh%20k5IdTVHBZWNAzTWIlfJ6KYUtNKI4kGBgddmmKBBuB1Wo8BEzUFP8AxqnvDAWVEwY4GHPkr3Ygo-IYe93TtIwQO0sK33ED8tA9IN7nnD5sk9KjfjhL5gyxMNnXS2MA1A38gPyvKCv9bKfz2cxGKMN8vgaeL8Nw6rbUxRrkzq7MQVw1K1jSyZMCoVjcwhHTTn6ysQDGka%20rckBATGhgbVOIaSWGmaFrK2bASCptRCC55lu2m0gOWr0DqSyZHAEB1LvAVQgJuraZhFR9Zq8i4JEMI7aFdT8PUUD7wHLAHANtPRsEoWaIQBo7KmPMBbMaPwXMPdpPDIFRtzIPhjGYY0vLUsZUgB603qJIYuPBqgHQB-ivxsShwcPSh73R1GJE8PgT28BA3F2Ll8cvJJJgB7avKWdNKchiaZphhFpap0RJf4k5ha860HjRJaNaoHaQD2u0MAhi5DZ4L7XuoGLZAUEATcBqhbZBisMH4KXbZhr9jx1IhmeIbhRN3NHVGYWxXBk-oIAvHyBRtiGhFtv4Zz0Z2rtEW3aasY8kbFSkJGacgzKbAZVCwZoRMoCOBaj05baC23xe2ZOpYe6dyfTG6HUb5WMRjqg47g9CqGeHwB5t-v9cmYegppPWko4FVRAdeeZ8-H7LbkRQl7eCg7sq0GKADL0l7jEzSVzSSVDwKyvaePc4aCPUiHXXJ%20eGKvUiPosl67rjKGGuZN7mEuDO7MBiOF8HUVyX4Q6%20z1PPfAKgqCRzNKcI%20d0j7lHTL-GM31ATH1btsZarEsE6XzM8D%20AgZKIMXCg8oWZKG3XFDQxBd0boqEYZMehIobrPSYZwIKnDNYcLuoFChfp9ZEyOlgjYeR355UBMtdaxxu5LxFCotKegpHbzrEuBa0BWhwVzPeJsU5%20yalAf0YwIk-D9k5qIJB6ktF8IocI5gg9E772FICFR7sYDwDctwSAnhMYBN7OKMkMl6a5mxobLInlX7II3ndB4S8cQvTUeWNRi4ooW3dFbaaOtfQFKAgVXBAFwyjRmm1XCqYWDYXam1futMSJoQwowued0AmOJ9NOb60Vcnr0cctJefA9oViwV4ZxisNQ6NJL4KyRddjYHJDYQet89TO16HqXUfhVKC22Ck-uKS0BKJ-gGPwVBhk4lhvJE8Ng2FWUXJ2LZjg%20zMBcNWSuyChGiABsMtKsiIQTM2oC6ZpCCHyKEFg85JyyEdMOeUAiQF6GIvoQDMh5QRYzDRVrXaAhdZAv2hrDUy0CVLQhcoDFgidhlMIpSwepwHpeQwMSryWwACyIBp5TyEKMlAVsOXMrxWLEmWg%20VyAAB6cs8DbWgbJ7Z0gmgIAAyrEAAtiwSVdlekQjZFDZgs1FUgAAMIMAAPaxCSJKha8MdheBJLSW1SABAzAAIIapJCoUUpsUaLDaM6gQAAhd1C0upvUaOeB1-rjUMAAJYADsWBAA" rel="nofollow noreferrer">simulate it here</a>):</p> <p><a href="https://i.stack.imgur.com/cDMIT.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/cDMIT.png" alt="enter image description here" /></a></p> <p>All-NAND Logic design follows this example: <a href="https://www.eeweb.com/full-adder-nand-equivalent/" rel="nofollow noreferrer">https://www.eeweb.com/full-adder-nand-equivalent/</a></p> <p>Key point to note in your design: <strong>mind the bias of each NAND's transistor input</strong>. In the NAND gate, the 'upper' base the pair will need a higher voltage than the 'lower' one because the upper one has the lower one’s Vce voltage added to it. Using separate base resistors for each input papers over this issue.</p> <p>This isn't as much of a problem if you use transistor-based NOR. Unlike the NAND, the NOR gate has both emitters grounded, and so each transistor turns on at the same bias voltage.</p> <p>Speaking of which, here's what an all-NOR version of a full adder looks like (<a href="https://www.falstad.com/circuit/circuitjs.html?ctz=CQAgjCAMB0l3BWcMBMcUHYMGZIA4UA2ATmIxARQosgoFMBaMMAKACUQHsqmwfvOYACxCoYobSS1p0BCwDmnAWEJKqA6SwAunPLQZC8azobEQGMSGCx6RQlHgSHCCBOUuEUT4vcIZiBIYoomBwIAAmdABmAIYArgA2WiwATsYMhKJcPMxUtKFw2rrSxiUQMK54eBiQQghgCJBoeNhS0ITYxGiQ3F6OeGAtyLSRsYnJaQx6JkZMhPqm%20fCQqYLzYlMlS-AsAO7pmWuchyv7c8dZKqV7RxkhqndQLAAyStgPxA-vs59mILEJADOdBA2HaT1eXHeghESkIs2Eony-xiQJBYNUpxAGDwWUOAweJxumCovyhql%20K0h2GhZO%20IEp4BRaNB4KxnlEwVoOM5EieAFkQASLkLTI9aChZCxBTyQFyhQJ5RKpQAPIX%20TgIIxdWauEC8kAAZTiAFsWGq8OtgtrBnL6vq5aIAMIMAD2cWSaoMtqY2FmEmwglaDuCIAAguaTNZOF0TE1dMQQ6IAEKRgzQgpKYiB0KBg0ugCWADsbtlbldzljztWKxpS8pMeBMfX%20Hlrvt9Bom08O5wlYJY1WBAx%20yO%20UOcrGa4ObvowFOK-O8qWKyhQ9WlS2%20%20vV6Gq6uMG2R4ee7cSWfx1vjzkHueVpMVPpmsU%20-gzMtVps%20wgHo-v42CkKHQvxHN8y1AoxkQsWBrBxWoRAcJwqjwRMPC8IQfCIfxAgGYYImieIkk-Ydz3A7gyh2YDphHH90i8ACoFkLVqlqepGmaZhGI6Lo4F6LUtUGKhM1GQjkkUcCl3SaxGxWDgyLQdJWjbWg%20SkMQKnYV9ZmfCC%203HcRJHUxi5HEnTqJ0k4nmA%20iYSyHTET%20CpCGETxiHqDBQkwTwuK5PhsCwTDQlxPCRPGT97PWXTdO2FZrNohgyR0xlylkZyhFc9zPIwNwfIkPyAvsIKQoIsLJhsphYXJWz3x2SYaQ%20W94uSj8zgiucF3WfcOvanIHFPJhusEDBf060t7L4AccgmrqpsnXrILGsDqOkl8q3svqmGGwQ%20v3LamA2lav1k8BKufByxy2fVDK2KVFHO6Zzss2KGV-WFzocqChGgecfsQoRuAaeNLD0bhSDAfyBjcIQMBCMJQqItJ3vWc7nxiooyV%20c7kpMb7iF%20xx-pQQGkVgEGUDBiGGkPRNhJKhGXuqxdYRi%209uwSikGpqwp9iR-JIr-LE-zmPm5x2m4hb-UiBfFyrcibOdpvF-mJolsWecqh69umQXZb6w6%20AWnm9oN8Atc0M56uqqqaObC3oRttYn1ood7bpaFzbeRthfU2c%20xPA9lx529-depElZFCtKRXSK2sd-r9f5xOPe9lOhcWG4RFmQ5M-1Q39WHbOxSJfYc94KhS%20LkAOVBKhq496vNtUBv0-2eYES2huVqxc9fhzqP9jvOUT37oebxUsVpYHk8DCMKXRv2WUy1lK4sWy1tsWCstV8obtl9t7F4SOYbZjrBed-OY%20jlXw-HkXyvL9vm-T%20xc-Dgfok0jr7FaiMwDWZqLIphm6QWGEBb%20SIX7KSZAYaAeNPg1EgEhLU8IXCMXwD0cmXRQgdFxP9GmcM6YTEgSKNeghpqgKKAAmYxCZ5-BgV0SgEg-DvHBnoFKkAYbZWzE0XA1RcAZgIWMIiihSFXFIV2Y6pCy40I%20gZagN05Al2HAIQm3YsQSE7OXZRgcrp83zkJfeQhFyqCMV8HRGijimKvhnCs2cC5hxLrY0QVit4ZzCI8FxH9R5iCUr-D8aRfG0NIosUBz1fEqTCGUYyzkPIkCaAERwDhAwwE8IMfyP5ML%20DXDmQRolVgWI8e4uWaMdCBNMAUkJKUfwkBEIMLU9gqgNB8jUTIiSHBrmyqoWmQixK6O7BYiRmkCly2GczORakZByA4G4W8oYZn-iMqpIyGlFDzPZhQM2PsdCUAROsNZAsmROUaChbglpXA0lwikzouJ%20j4BQuDEgxUemrH2VtNZa4IGASKDsshVB9nkPMJYFyfp%20LYGEIgyAnxIKwHmHwSAhAEVwM4VgWGIxCEvIOusUuBy-75InhNH50iWY3FeaoBAC4tpYnJTkN5C5mYkopU3MCXcSXGz6tS7aecOX7SMNyj6Nw24xjJVOEeazfjctFcbWEgqKoOKrsy6VYER6CsOIK4prKm6iBVXK%20Zcs1WK32By6YHLK7zONbGbWDL1C11DM-DlAgTU6q2g62MdY0h9zJX1ZqtUKB9XKeUkBuLtlerJVtbGFRmIALYlYec2ASbcW6HxFCnhDjdLyWkeZDrjYAUor6owph5mVM4JYNAaAeIaPJuShAySYVWDQAimoBMcDpVRfhZ5qytpy11TtJ40zs0bIeCEiJ8j1JSj7V02MurOrjOWbdAdNdJDOvdlZPNdpQ2qBsp9WB1ysnOR6P4ZyaDYVoFiTgUg8I9a5NKvO%20UurBwUODUYXAohM0-y3dmGGjRGgGxjZiGF6EfDDQwjicG84nnptXTZHOm7Ql4qfT-H5z6uZUq2re2Mm5DXodUuhk8VKsO0Grhhm9VQKDoZI3hqgDheU4Z0ZmhSgryKnnmeeQVd4BVvhY2%20Rj6iA36lMJujOpgkPeyQ-udYwm04LSAA" rel="nofollow noreferrer">simulate it here</a>):</p> <p><a href="https://i.stack.imgur.com/C5tc9.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/C5tc9.png" alt="enter image description here" /></a></p> <p>Looks the same, doesn't it? Indeed, in this case just substituting NOR for NAND everywhere yields the same result. All the transistors have grounded emitters; making it easy to merge and delete some of the base resistors if that is a design goal. (In fact you only need three: one each for A, B and C-in inputs.)</p> <hr /> <p>Implementing full adders out of NAND is aesthetically pleasing. It has those nice symmetric XOR (half-adder) structures that are things of beauty. Now, is it the most efficient way to make an XOR, let alone a full adder? Nope.</p> <p>Anyway, extending on this all-NAND idea, some argue that NAND is <em>the</em> 'universal gate' since you can make any logic out of it. Well, no; you can do that with NOR as well.</p> <p>Related: <a href="https://electronics.stackexchange.com/questions/575289/what-is-the-lowest-level-of-cpu-programming-above-transistors/575299#575299">What is the lowest level of CPU programming above transistors?</a></p> <p>In fact, the best known example a computer made from just one 'universal' gate type is the one that flew to the Moon: the <a href="https://www.righto.com/2019/09/a-computer-built-from-nor-gates-inside.html" rel="nofollow noreferrer">Apollo Guidance Computer</a>. That beast used just one kind of logic IC, a <a href="https://djjondent.blogspot.com/2019/07/the-apollo-guidance-computer-nor-gate.html" rel="nofollow noreferrer">dual 3-input RTL <strong>NOR</strong>.</a></p> <p>On the other hand, I've not heard of anything nearly as significant as the AGC being built entirely of NAND gates. Have you?</p>	<p>I am trying to build a full adder with NAND gates. I have a transistor implementation:</p> <p><a href="https://i.stack.imgur.com/H8DdQ.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/H8DdQ.png" alt="Full adder circuit" /></a></p> <p>I am getting the wrong output voltages for Cout and S; is there a way to fix this? Is it my resistors that have incorrect values? I am pretty sure the circuit is well connected; it is more a problem of resistors. What can I do to fix it?</p>	Multiple NAND gates built with transistors linked together	2024-01-11T14:30:36.650
697229	\|switch-mode-power-supply\|dc-dc-converter\|	<blockquote> <p>I'm currently looking into isolated step-down DC/DC converters, to convert from high voltages (a few hundreds volts) to 24 V.</p> </blockquote> <p>Apart from some exotic exceptions, all these DC-DC converters use transformers that provide both isolation and a good efficiency at high step-down ratio. There are many different topologies: flyback, push-pull, resonant... In the case of flyback, the transformer is used as coupled inductor.</p> <p>But there's always a primary winding, a secondary winding, and therefore there is a turns ratio between primary and secondary. This turns ratio will usually be optimized for best efficiency at the nominal input and output voltage ratios.</p> <p>Therefore, the further away you get from this nominal ratio, the worse it gets. In fact, it's already pretty good to get a 1:2 input voltage range with a transformer that has a fixed turns ratio.</p> <p>There are other factors too: at constant output power, input power is inverse proportional to input voltage. As input voltage gets lower, more current is needed to provide the same power. Extending the input voltage range down will require switching devices capable of higher current, larger dies, with more capacitance, and more switching losses. Also it needs thicker wire in the primary, which costs more and makes the transformer bulkier. If the application does not require it, there's no reason to incur the extra costs and loss of efficiency.</p> <p>The usual "universal wall wart" supplies with 85-240V AC input generally use flyback topologies, which offer a wider voltage range at a low cost, but at the expense of higher losses. It's okay for a low power converter, but at 500W there are much better options.</p> <p>For high power AC-DC converters with "universal input" you'll usually get a boost power factor correction stage or a capacitive voltage doubler, which compresses the allowed input voltage range into a much narrower DC bus voltage range, followed by a resonant converter which allows very high efficiency. So the actual isolated DC-DC converter in these supplies does not have to handle the full input range.</p> <blockquote> <p>When the input voltage is close to the output voltage, I understand that keeping a few volts of difference makes things far easier.</p> </blockquote> <p>This would apply to a buck converter, which is a non-isolated topology using an inductor. It's a completely different topology from a transformer-isolated converter.</p>	<p>I'm currently looking into isolated step-down DC/DC converters, to convert from high voltages (a few hundreds volts) to 24 V.</p> <p>I'm surprised that the minimum input voltage is often quite high (like 200 V for a 300 V nominal input voltage (<a href="https://product.tdk.com/system/files/dam/doc/product/power/switching-power/dc-dc-converter/catalog/ph1200a280_e.pdf" rel="nofollow noreferrer">example</a>)).</p> <p>When the input voltage is close to the output voltage, I understand that keeping a few volts of difference makes things far easier.</p> <p>But I'm wondering : what tradeoffs can explain why most DC/DC converters with 300 V nominal input have a lower input limit >150 V?</p> <p>I'm referring to switching power supplies, in the 500-2000 W range. For the topology, I haven't looked at those in detail yet for this kind of power (and manufacturers often don't specify it), so whatever classical topology in this power range is interesting.</p>	DC/DC step-down converters: what trade-offs prevent lower minimal input voltages?	2024-01-11T14:52:53.997
697235	\|voltage\|divider\|	<p>The general formula for a voltage divider is</p> <p><span class="math-container">$$ E_n = E_{total}\times \frac{R_n}{R_{total}} $$</span></p> <p>Where:</p> <p><span class="math-container">\$R_n\$</span> is the resistor or series of resistors you want to find the voltage across.</p> <p><span class="math-container">\$E_n\$</span> is the voltage across <span class="math-container">\$R_n\$</span>.</p> <p><span class="math-container">\$R_{total}\$</span> is the total resistance in the divider.</p> <p><span class="math-container">\$E_{total}\$</span> is the voltage across the entire divider.</p> <p>This can be applied to a divider with any number of resistors, but two resistors is what you typically see.</p> <p>Example: In the following circuit we want to find the voltage across R2, this will be our <span class="math-container">\$R_n\$</span>. <span class="math-container">\$R_{total}\$</span> will be 3.3k + 1.2k = 4.5k and <span class="math-container">\$E_{total}\$</span> will be the total supply voltage, 15 V.</p> <p><img src="https://i.stack.imgur.com/tqbty.png" alt="schematic" /></p> <p><sup><a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2ftqbty.png">simulate this circuit</a> – Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a></sup></p> <p>We get: <span class="math-container">$$ E_n = 15~V\times \frac{1.2k}{4.5k} = 4~V $$</span></p> <p>This finds the voltage dropped across the resistor, if you want to reference that to another node in the circuit, such as the common connection of two voltage sources, you would then have to add any voltages between <span class="math-container">\$R_n\$</span> and that point, in this case we would add the voltage across R2 to -5 V and the voltage at <span class="math-container">\$R_{n1}\$</span> with respect to <em>Reference</em> would be -1 V. It would be a good idea to label the voltages with + and -, then following the circuit starting at <span class="math-container">\$R_{n1}\$</span> and ending at <em>Reference</em> you get (+4 V) + (-5 V) = -1 V.</p>	<p><a href="https://i.stack.imgur.com/8rWuc.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/8rWuc.png" alt="enter image description here" /></a></p> <p>Let's imagine there is a symmetrical DC power supply +10V and -10V and two resistors, R1=10k and R2=100k. What is the voltage in point A? What is the correct formula for this kind of calculation?</p>	Voltage divider for symmetrical DC power	2024-01-11T16:09:00.200
697239	\|usb\|voltage-regulator\|usb-device\|	<p>"Or" the supplies together, or shut down the 5V supply if the USB is plugged in. Here is and example of how to share power supplies <a href="https://electronics.stackexchange.com/questions/96398/or-ing-power-supplies-diode-or-mosfet">OR-ing power supplies (diode or mosfet)</a></p> <p>If you aren't going to use the power from VBUS on usb then don't connect it at all (you may need to connect it to the a processor or IC for VBUS detection)</p> <blockquote> <p>If I connect my µUSB bus to the other 5V bus what are the consequences?</p> </blockquote> <p>If there are any differences in voltage between the supplies then one will feed the other, take for example if VBUS on usb is 4.9V and the +5V rail is 5.01V. You will get an indeterminate amount of current transfering from one to the other dependent on the series resistance of the line and the supplies. Sometimes they even out, sometimes they don't, its anybody's guess. So the best thing to do is use a power sharing scheme or just not use VBUS.</p>	<p><a href="https://i.stack.imgur.com/HieyQ.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/HieyQ.png" alt="µUSB and 5 to 3.3V regulator" /></a></p> <p>If I connect my µUSB bus to the other 5V bus what are the consequences? What can I put in place to make it safe?</p> <p>The µUSB would be plugged in while the circuit is active to reach a µC by default. The other two states are that 5V will be off and 5V will not physically be present because it will be disconnected from the other PCB.</p>	Is it safe to connect a µUSB bus to another voltage bus?	2024-01-11T16:25:46.067
697252	\|operational-amplifier\|analog\|voltage-regulator\|	<p>I would recommend just using a voltage regulator. For 3mA an SOT23 version will do. Smaller and up to the job.</p>	<p>I'm working on a CubeSat project and I need to produce a 3.3 V voltage rail for an ADC (<a href="https://www.ti.com/product/ADC128S102" rel="nofollow noreferrer">ADC128S102</a>). The ADC only needs 3 mA total when in active mode. I'm selectively upgrading the most critical parts on the bus to versions that are radiation tolerant/hardened.</p> <p>I have a +5 V rail and I want to avoid buying another voltage regulator just to produce this 3.3 V line if I can. I have an unused op-amp (<a href="https://www.ti.com/product/OPA4H199-SEP#design-development" rel="nofollow noreferrer">OPA4H199-SEP</a>) that I think I could use to produce a 3.3 V line for the ADC. This 3.3 V is only used for the digital signals reference, not the analog reference voltage itself.</p> <p>The ADC needs 0.1 μF + 1 μF of decoupling on the digital line and I simulated the op-amp feeding these capacitors and it looks like an isolation resistor of 100 Ω makes the op-amp stable.</p> <p>If the ADC drew its maximum rated current from this supply constantly, the voltage would drop to 3.0 V on the digital input of the ADC. This is still within the operating conditions of the part and seems like it would still produce valid logic levels for an MCU to read.</p> <p>Is there any reason that this wouldn't work in practice or wouldn't behave like I've simulated? I know op-amps could be used to drive the base/gate of a transistor to produce a linear regulator, but based on everything here, it looks like I can get away with just using the op-amp to drive it directly.</p> <p>The circuit would probably look something like this (with the +5 V line replaced with a +10 V line):</p> <p><img src="https://i.stack.imgur.com/vggIC.png" alt="schematic" /></p> <p><sup><a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fvggIC.png">simulate this circuit</a> – Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a></sup></p>	Using an op-amp to produce a low-current voltage rail	2024-01-11T18:06:40.093
697255	\|stm32\|crystal\|	<p>The MCO output does not depend on your crystal, so there is no real reason to want a 25 MHz crystal even if you want a 25 MHz output.</p> <p>However, if the MCO output comes from a PLL, it might be a problem. This configuration was specifically not recommended on STM32F2 due to jitter.</p> <p>If you really want a single 25 MHz clock source for both, why bother with a crystal, if you can buy a 25 MHz crystal oscillator module and feed the 25 MHz square wave to both devices. The problem anyway is routing 25 MHz clocks properly between the chips.</p> <p>Or, it may be cheaper to get a 25 MHz crystal for the Ethernet PHY and separate crystal for STM32.</p> <p>I forgot the answers:</p> <ol> <li><p>Somewhat worried. Depends a bit who you ask. 3 to 5 might be acceptable or not safe. 5 to 10 is just safe or very safe. Sometimes above 10 is very safe. ST themselves say 5 is minimum to ensure proper operation and if margin is less than 5 you should change the crystal. They know their own MCUs and their internal oscillator circuitry best.</p> </li> <li><p>I don't know if crystal parameters matter much. Crystal circuits are very sensitive so any EMI is bad. I think what affects more is proper PCB layout than any of the crystal parameters. Refer to STM32 hardware design guides for crystal layout guidelines.</p> </li> <li><p>Based on what I wrote above, likely yes.</p> </li> </ol>	<p>I want to connect a 25MHz crystal to STM32H750. However, I've trouble finding a part which is suitable for use with this particular MCU.</p> <p>From <a href="https://www.st.com/resource/en/application_note/cd00221665-oscillator-design-guide-for-stm8af-al-s-stm32-mcus-and-mpus-stmicroelectronics.pdf" rel="nofollow noreferrer">AN2867</a>: <a href="https://i.stack.imgur.com/RwHUc.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/RwHUc.png" alt="AN2867" /></a></p> <p>In addition:</p> <p><a href="https://i.stack.imgur.com/3NhwN.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/3NhwN.png" alt="AN2867" /></a></p> <p>The <em>gm</em> for STM32H750 is 1.5 mA/V (<a href="https://www.st.com/resource/en/datasheet/stm32h750ib.pdf" rel="nofollow noreferrer">datasheet</a>). This means that in order to meet the recommendation, the crystal has to have <em>gmcrit</em> equal to or lower than 0.3 mA/V.</p> <p>The only crystals which <em>come close</em> to this recommendation are the ones in bigger packages and with low load capacitance (The best one I've been able to find has <em>gmcrit</em> of 0.478 mA/v). So, I have few questions:</p> <ol> <li><p>How much should I be worried about the <em>gain margin > 5</em> recommendation?</p> </li> <li><p>My circuit will be exposed to EMI from relays and contactors. Which parameters of a crystal are the most important for stability in this case?</p> </li> <li><p>The 25MHz crystal is not a strict requirement - I wanted to use HSE as source for the Master Clock Output for a Ethernet PHY. Should I just opt in for a lower frequency crystal and use a different source for the MCO instead?</p> </li> </ol>	Connecting 25MHz crystal to STM32H7	2024-01-11T18:16:20.377
697265	\|led\|automotive\|light\|cob\|	<p><strong>Etendue</strong></p> <p>see <a href="https://en.wikipedia.org/wiki/Etendue" rel="nofollow noreferrer">https://en.wikipedia.org/wiki/Etendue</a></p> <p>COB LED filament household lightbulbs produce a lot of light by having a large surface area - which is similar how a lot of light is produced by a fluorescent lamp in a tube format.</p> <p>A headlamp wants to be able to focus the available light into a narrow forward beam - which by etendue requires a small emitting area (for the same optical power output).</p> <p>Small sources of intense light are commonly produced by small tungsten filaments or by small arc lamps. This is difficult in an LED format as the white light is produced by exciting a phosphor with blue LED light - and limited by the optical power density and temperature the phosphor can tolerate and by the heat dissipation of the lamp. A tungsten lamp (by definition an incandescent source) wants to run hot.</p>	<p>COB LED filament household lightbulbs are a thing now. Can someone explain to me what limitations there are to using these COB filaments in car headlights? They emit a very similar light pattern if you preserve the geometry and glass shape. I believe there must be a reason why manufacturers kept clear of this approach for the past 10 years.</p> <p><a href="https://i.stack.imgur.com/zvkoT.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/zvkoT.png" alt="LED COB filament in a H7 bulb" /></a></p>	Usability of COB LED filaments as replacement for traditional filaments	2024-01-11T18:50:21.180
697277	\|transistors\|pullup\|dimensions\|	<p>One of the things you have to take into consideration is if the input will both source and sink current. Is logic low defined as 0 V or the absence of 5 V? That is to say, will whatever drives the gate be able to not only put 5 V on the gate inputs, but also pull them to ground rather than just letting them float.</p> <p>The voltage sources in LTspice will go to 0 V, which is what you would normally want with diode logic like this. The problem is you have diodes DA, DB,DC and DD connected so that the source will not be able to pull S1 and S2 low.</p> <p>You can remove those diodes and connect the pulse sources directly to S1 and S2. This will make it so the output can go low. You'll still have the diode drops of D11 and D21 though. You can minimize this by using Schottky diodes. This should reduce the low output voltage to less than 100 mV. You also have to take into account the loading on the output, if R2 is large and loading can reduce your high output voltage significantly. Schottky diodes also have higher reverse leakage than silicon, so you have to adjust the resistances a bit, making the input resistors higher, and the biasing resistor lower.</p> <p>Here is a simulation showing all of this: <a href="https://i.stack.imgur.com/ED2vG.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/ED2vG.jpg" alt="diode and gate" /></a></p> <p>You can see the output is around 4.6 V for high and 180 mV for low.</p> <p><strong>Update:</strong> Thinking about it, you can leave out the 10k resistors. The ones on the input will make little difference except to draw a little more current from the sources, the one on the output will load it down a little, leaving it out gets the logic high voltage close to 5 V.</p>	<p>I am building this AND gate, and I managed to get it to work properly. However, I had to increase the value of the pull-up resistor to 3 megohms which is too big for what I need. However if I don't make this value big enough, when my input is (0, 0) for example, I won't get an output signal < 0.5 V.</p> <p><a href="https://i.stack.imgur.com/bWd8Z.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/bWd8Z.png" alt="AND Gate design" /></a></p> <p>How can I ensure that (0,0) (0,1) (1,0) < 0.5V and that (1,1) > 4V. Thank you in advance.</p>	Alternative to pull-up resistor	2024-01-11T20:12:16.883
697279	\|footprint\|through-hole\|ipc\|	<p>Annular ring is the width of the ring. So for a 0.35mm minimum annular ring the hole is no more than 0.7mm smaller diameter than the pad diameter.</p> <p>There seem to be some differences whether "minimum annular ring" should account for misalignment of the holes, and whether the drilled hole size or the finished hole size should be used.</p> <p>PCB manufacturers generally accept a minimum annular ring which assumes perfect hole alignment and using finished hole size, in my experience.</p> <p>IPC has a definition of minimum annular ring that includes all the factors, so it does not necessarily correspond to what you would set as a DRC limit in an EDA program. In other words they are referring to the minimum ring you would actually measure under a microscope with misalignment and other manufacturing tolerances and not the nominal difference between hole and pad radius.</p> <p>According to IPC, for Level B there is a 0.25mm fabrication allowance for 1oz or less copper thickness and 8 or fewer layers.</p> <p>So according to IPC, the minimum pad diameter for external layers is the maximum diameter of the finished hole plus double the minimum annular ring (including etch back allowance) plus the fabrication allowance. For internal layers, the same numbers are used but the maximum drill diameter is used.</p> <p>The fabrication allowance increases for more than 8 layers, and for heavier copper. See IPC-2221A.</p> <p>Refer to the actual standards if the slight differences are important.</p>	<p>When looking at IPC-7251 Table 3-3 (see the table in Sergei Gorbikov's answer at <a href="https://electronics.stackexchange.com/questions/115996/how-to-determine-annular-ring-width-for-thru-hole-pads">How to determine annular ring width for thru-hole pads?</a>), for a through-hole pad in Level B the annular ring is given as 0.35mm. Is that the actual annular ring width or the total width to add to the hole size? What I mean is suppose you have a 0.4mm diameter hole, would you have a 0.75mm diameter pad or a 1.1mm diameter one?</p>	IPC 7251 annular ring meaning	2024-01-11T20:15:32.597
697289	\|circuit-analysis\|kirchhoffs-laws\|thevenin\|nodal-analysis\|	<p>I guess the rightmost 1V source doesn't belong to the original circuit, it's a later scribble and should be wiped off. I guess also that B is the lowest horizontal wire in the circuit.</p> <p>Assume there's voltage =Vth between A and B. When writing proper circuit analysis equations and eliminating node voltage V1 you get 2 seemingly contradicting equations. One says that Vth = P * Vx where P is a constant. The other says that Vth = Q * Vx.</p> <p>Both P and Q are expressions which contain the resistances and the dependent source factor.</p> <p>Of course, both equations can be fulfilled at the same time only in 2 cases:</p> <p>Case1: Vx = Vth = 0</p> <p>Case2: P = Q and in that case any Vth is as good. The circuit happens to be an active circuit which can settle to any Vth and stay there. P=Q is a condition between the resistances and the dependent source factor. Of course that's generally not possible in any practical circuit, because exact resistor values are impossible to make in practice.</p> <p>One simple dependent source circuit does not have that problem:</p> <p><a href="https://i.stack.imgur.com/P6MW8.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/P6MW8.jpg" alt="enter image description here" /></a></p> <p>But it's still nothing more than a trick, because such dependent source is not available.</p>	<p>I don't understand why the Thévenin equivalent is equal to zero in this case because, if the load is a resistance, then yes, the circuit would be dead as there would be no voltage drop across Vx. But if there is a voltage or current source in the load section then the circuit would have power (not dead) and therefore there'd be a voltage drop across Vx, so the dependent source would have a voltage produced over it, therefore negating the fact that Vth is equal to 0 in this case.</p> <p><em>My question is: Why is there no Thévenin source if there are cases when the dependent source would have voltage over it.</em></p> <p>Update: point B is the lower wire point.<br /> The circuit is equivalent to only a resistor, no Thevenin voltage equivalent.</p> <p>Edit: I don't know what more detail to add, I just want to know why if there is a voltage source in the load circuit between points A and B, then wouldn't that case a current through the resistor Vx? Therefore, that would active the dependent source and Vth would no longer be 0.</p> <p><a href="https://i.stack.imgur.com/XbG5J.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/XbG5J.png" alt="The circuit" /></a></p>	How can there be no Thévenin voltage with only a dependent voltage source?	2024-01-11T21:05:19.053
697308	\|transistors\|semiconductors\|computer-architecture\|	<p>MOSFETs are controlled by their gate-to-source voltage, called Vgs. No current flows through the 'input' (gate). Rather, current flows through the other two terminals, called <em>source</em> and <em>drain</em>.</p> <p>In typical CMOS logic, the n-FET sources is tied to GND, while the p-FET sources are tied to the supply (often called Vdd or Vcc).</p> <p>Where does the logic-high voltage come from? Vdd is the logic voltage, which could be 5V, 3.3V, or some lower voltage such as 1.2V as mentioned in your example. Again, in your example, this logic-high power supply is connected to the top p-FET, as shown by your red arrow.</p> <p>How do you get a logic high? When <strong>both</strong> p-FETs are on, the output is connected to power supply through both FETs in series.</p> <p>On the low side, GND, or logic low, is supplied through the n-FETs. When <strong>either</strong> FET is on, the output is connected to GND.</p> <p>Now, back to that gate-to-source voltage and what it does to the FETs:</p> <ul> <li>n-FET is 'on' when gate-source (Vgs) is <em>positive</em>, or logic '1'</li> <li>p-FET is 'on' when gate-source (Vgs) is <em>negative</em>, or logic '0'</li> </ul> <p>If you work out the diagram and how the FETs behave, you can see 4 cases:</p> <ul> <li>A, B = 0, 0 => both p-FETs are 'on', n-FETs are off => output is HIGH</li> <li>A, B = 0, 1 => one p-FET is 'on', one n-FET is on => output is LOW</li> <li>A, B = 1, 0 => other p-FET is 'on', other n-FET is on => output is LOW</li> <li>A, B = 1, 1 => both p-FETs are 'off', both n-FETs are on => output is LOW</li> </ul> <p>So what you have is a NOR gate. Try one out (<a href="https://www.falstad.com/circuit/circuitjs.html?ctz=CQAgDOB0YzCsICMZICYaoOyYMxgByoBsAnCZiHBAlZQKYC0iiAUAGYhapIAsPIOHEV78EiSAhRhULAO4ChSIhEHDEJbmBYAlBWtT49IfBFMge1cFZRx2nTN3SHVnApSQSo0uUdSp%20Lv6mPoEWvnDCWhxc9tyBDuYektAyALK%20YRYQQVaoEnaImMIxOTH84sne8qVhpRHgPjUqijlaAOactfiGOTjo1iwdgd1GfWZa1QlOsTMTSEUi88UJc4VqfDOIG1oAMkuLiAaLEIggbACGADYAznTuuzPThz1uJ2dXt-csQA" rel="nofollow noreferrer">simulate it here</a>):</p> <p><a href="https://i.stack.imgur.com/i7Jitm.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/i7Jitm.png" alt="enter image description here" /></a></p>	<p>Going through a <em>Introduction to Computing Systems</em> by Yale N. Patt and Sanjay J. Patel and currently reading a chapter on MOS transistors. From what I understand, N-type transistors "close" a circuit when supplied with current and break it if absent. P-type transistors act in the opposite way. When supplied with current then it closes the circuit and breaks if present.</p> <p>Now according to the textbook regarding the image below, "...if both A and B are supplied with 0 volts, the two P-type transistors conduct, and the output C is connected to 1.2 volts."</p> <p>What I don't understand is where the 1.2 volts is coming from if input A and B are supplied with 0 volts? Based on the quote, I would assume that the power supply is coming from A and B but the only alternative I could think is that it is coming from the area indicated in red and that A and B are sort of like a light switch dictating the behaviour of the transistors</p> <p><a href="https://i.stack.imgur.com/XWKZk.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/XWKZk.png" alt="enter image description here" /></a></p>	How do P-type transistors conduct current?	2024-01-12T02:11:32.857
697316	\|circuit-design\|relay\|	<p>The circuit looks fine. A 2N3904 or other general purpose NPN would work since the coil current is 40mA at 5V which is pretty undemanding. Aim for a base current of 4mA with a Vbe of 0.95V for a 2N3904 or whatever your transistor's Vbe(sat) is, which gives you a base resistor of ~500 ohms. 510 or 470 would both work. For the diode, you want something that can handle at least the same current as the relay coil with at least the same reverse voltage rating, and fast. It shouldn't be hard to find a Schottky diode with these specs.</p>	<p>This is my current circuit draft</p> <p><a href="https://i.stack.imgur.com/kBxkjl.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/kBxkjl.png" alt="Circuit schematic" /></a></p> <p>Which had the SPST-NO symbol adapted from the supplier's symbol</p> <p><a href="https://i.stack.imgur.com/VNfSgm.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/VNfSgm.png" alt="Relay symbol" /></a></p> <ul> <li>I have not chosen any specific parts for diode, resistor or transistor.</li> <li>ALDP105W Relay datasheet: <a href="https://datasheet.datasheetarchive.com/originals/distributors/Datasheets-DGA17/901128.pdf" rel="nofollow noreferrer">here</a></li> </ul> <hr /> <p>I am new to circuitry and PCB design, I was wondering if anyone could help me:</p> <ul> <li>Spot any issues or areas for concern</li> <li>Suggest some simple specs that I should look out for when buying a diode and transistor.</li> </ul> <p>Thank you</p> <p><strong>EDIT</strong>:</p> <p>The <code>GND</code> error flag seems to be invalid. I just have it connected to a screw terminal with a <code>PWR_FLAG</code> and the default KiCad NPN symbol as the emitter as <code>Open Emitter</code></p>	Is this relay circuit valid?	2024-01-12T03:44:37.350
697317	\|mosfet\|switches\|inverter\|flipflop\|	<p>You shouldn't need Pull-up resistors for those invertors - pull-up resistors are only necessary when you have open-collector outputs. These do not.</p> <p>If the LED is still on when you short the gate to ground, that means your transistor is destroyed or highly leaky. Try swapping the transistor with either the one that you know works in the circuit or a new one. Also try swapping the position of the Red and Blue LEDs to see if the behavior is the same. If the red LED exhibits the same behavior, it is definitely the transistor. Of course, try swapping the LEDs BEFORE you introduce new transistors into the circuit.</p> <p>If the blue LED is still behaving the same after being installed in the "known good red LED" side, then it is almost entirely due to leakage - it only takes a few uA to get an LED to glow brightly. The red LED could have the same issue as the blue one, but you just can't perceive it because it has worse luminous efficiency. As a kludge, you can try putting a relatively high (~47k?) resistor across the blue LED to ensure that it stays off even with some leakage. I don't personally like this solution - it's bad design and you shouldn't have to do this. But given the nature of this circuit, it's obviously not that critical. So if it works for your application, it works!</p> <p>Putting the diode from gate to ground isn't causing any negative voltage; it's not real - you are either measuring wrong or this could be related to the already mentioned leakage issue.</p> <p>One unlikely reason that you could be having, that I will include for completeness, is that the transistor is acting as an antennae and picking up and rectifying a nearby EMI source. This phenomenon would also explain why you are reading negative voltage on you DMM - it too may be affected by local interference.</p>	<p>I want to create a circuit that has two outputs, and two states, where the outputs are either "on, off" or "off, on". The state should be switchable using a <em>momentary</em> SPST switch.</p> <p>I am using two inverters from a CD40106.</p> <p>Here is the current circuit:</p> <p><a href="https://i.stack.imgur.com/HUeDx.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/HUeDx.png" alt="cd40106 bistable" /></a></p> <p>Here, VCC is 9V (the cd40106 is powered by VCC). The unused inverters have their inputs tied to ground, and the unused outputs are floating. I used two LEDs to test the "on" and "off" states.</p> <p>I built this on a breadboard, using red LEDs. The circuit worked as expected: on power-up, one of the LEDs was lit, the other dark. Pressing the switch caused the dark LED to light up, and the light LED to go dark.</p> <p><strong>Question 1:</strong> I swapped one of the red LEDs for a <em>blue</em> LED. Now, the blue LED never goes fully dark: it's fully on when the red LED is off, but when the red LED is on, the blue is just a little bit on.</p> <ul> <li>Using this schematic, assume D2 is the blue LED: even if I jumper Q2's gate to ground, the blue LED is still slightly dim.</li> <li>If I completely remove Q2, D2 goes dark.</li> <li>I also tried using a diode to connect Q2's gate to ground, with the anode to the gate and cathode to ground: this actually creates a <em>negative</em> voltage at Q2's gate (per my DMM). D2 still never goes completely dark.</li> <li>I tried changing the pull-up resistors (R10, R10) to pull-down resistors (i.e. having them go to ground rather than VCC). D2 still not completely dark.</li> </ul> <p><strong>Question 2:</strong> Are the pull-up resistors (R10, R11) actually necessary? I basically copied this circuit from <a href="https://www.eevblog.com/forum/beginners/single-momentary-push-button-for-on-off-(toggling)-a-signal-connection/msg3374316/#msg3374316" rel="nofollow noreferrer">this discussion post</a>, where it is suggested to use the pull-up resistors, but doesn't say why. I've seen countless other variations of this circuit posted in various places on the internet, and don't see them using pull-up (or pull-down) resistors.</p>	NAND-based bistable with momentary switch	2024-01-12T03:55:48.363
697321	\|diodes\|	<p>Only one winner here:</p> <ol> <li><p>The diode lowers the voltage source voltage, because the source's own internal resistance is more significant than the diode's, or</p> </li> <li><p>The voltage source's internal resistance is low enough that the diode passes many hundreds of amps.</p> </li> </ol> <p>Maybe you get something between the two, but this is just another irresistible force vs. immovable object thing. Neither the voltage source nor the diode has zero impedance, so pitting one against the other is just going to explode the least perfect one.</p>	<p>What will be the voltage across the terminals of the diode if its directly connected (forward biased) to a variable voltage source that varies from 0.7 to 5 volts?</p> <p>Will it remain 0.7 volt at the output of the diode terminal or the output of the diode will vary with the voltage to which the diode is directly connected. I know it's a basic question but I am confused.</p> <p>On thing that comes in my mind is that the resistance of the diode will decrease as the voltage/current increases across the diode and thus the voltage across the diode will remain a constant 0.7 across the diode but I am confused. Can anyone please clear this confusion?</p>	Voltage across the diode	2024-01-12T04:54:47.233
697328	\|operational-amplifier\|feedback\|stability\|	<p>A robust design implies that the circuit is highly tolerant to component-to-component variation. The Q=0.5 condition is the theoretical limit that can be achieved without overshoot while minimizing the settling time (fastest response). The issue is that slight variation (tolerances) could cause Q>0.5 which results overshoot in the response. Some applications can't tolerate any overshoot for any duration. This is why you don't want to place the pole at the limit when you are trying to achieve a robust design. In practice, you would want to shift the pole a bit to the left (Q<0.5) to assure you have adequate damping (at the expense of speed) to mitigate any overshoot over all operating conditions.</p> <p>In other words, it's a sensitive balance between performance (fast response) and robustness (insensitive to component values).</p>	<p>In Systematic Design of Analog CMOS Circuits (Jespsers, Murmann) page 343, the following is stated in the context of where to place the non-dominant pole in a second-order loop transfer function of a switched-capacitor amplifier:</p> <blockquote> <p>The case of ωp2/ωu1 = 4 (Q = 0.5) results in a critically damped step response. This corresponds to the fastest possible settling without overshoot [7] and is the preferred choice for SC [switched capacitor] circuits that are designed for maximum speed. <em>Designing for ωp2/ωu1 < 4 is not recommended to avoid overshoot, which is difficult to manage if the goal is to create a robust design.</em></p> </blockquote> <p>The emphasis is mine, and also see the figure below if helpful. Note that the reference [7] in the quote is <a href="https://ieeexplore.ieee.org/document/52726" rel="nofollow noreferrer">this paper</a>. (I don't think this paper addresses my question, below).</p> <p>My questions are:</p> <ol> <li>Why is overshoot "difficult to manage" in a "robust" design?</li> <li>What are the main problems that overshoot could cause? The above quote comes from the context of switched-capacitor circuits, so that may be relevant. The main thing I can think of is maybe the overshoot could result in dropping the output stage devices / input devices of the next stage out of saturation if the overshoot makes the signal swing too big, I'm unsure if this is one such problem / if there are others.</li> </ol> <p><a href="https://i.stack.imgur.com/ORn6e.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/ORn6e.png" alt="loop gain unity crossover" /></a></p>	Avoiding overshoot in step response for robustness	2024-01-12T07:11:14.177
697340	\|short-circuit\|circuit-protection\|reverse-polarity\|	<p>Short circuit protection for outputs is conveniently handled by using "smart" MOSFET drivers with built-in current limits, short circuit protection, temperature protection etc etc. <a href="https://www.infineon.com/cms/en/product/power/smart-power-switches/high-side-switches/profet-plus-24v-automotive-smart-high-side-switch/" rel="nofollow noreferrer">Examples</a>. Additionally you'll need to have a flyback diode per solenoid.</p> <p>Reverse polarity protection is commonly handled as shown in this answer: <a href="https://electronics.stackexchange.com/a/623011/6102">https://electronics.stackexchange.com/a/623011/6102</a>.<br /> A P-MOSFET is placed "in reverse" with drain towards +. The gate is pulled low with pull-down. This means very low voltage drop given that the R<sub>DS(on)</sub> will be very low. MOSFETs come in all manner of current and voltage ranges. In case of reverse polarity, the gate is no longer pulled down, the MOSFET won't conduct and + is disconnected from the circuit so that no current flows.<br /> Optionally you can add a zener from source to gate as shown in the answer, to protect against overvoltages.</p>	<p>I have read many posts and articles about short circuit and reverse polarity protection design for a PCB, but still I am quite confused about the industry standard/common principles here. The specifications for my PCB is:</p> <p>PSU for input is 24V, 1.66A The PCB have relay outputs controlling 24V solenoids, and also CAN bus 24V ports.</p> <p>My question is how do I properly design short circuit protection for the outputs, and how do I design reverse polarity protection for the input?</p>	How to design short circuit and reverse polarity protection for PCB?	2024-01-12T10:01:37.280
697348	\|ltspice\|temperature\|	<p>I think you just want a linear sweep of the temperature. If so, just use a card like this one:</p> <pre><code>.step temp 0 100 1 </code></pre> <p>That sweeps from <span class="math-container">\$0^\circ\text{C}\$</span> to <span class="math-container">\$100^\circ\text{C}\$</span> in <span class="math-container">\$1^\circ\text{C}\$</span> increments.</p> <p>I'd then set up a behavioral voltage supply and set it equal to <code>temp</code>. Then set the x-axis to its output.</p> <p>Here's an example to illustrate:</p> <p><a href="https://i.stack.imgur.com/BKkpo.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/BKkpo.png" alt="enter image description here" /></a></p> <p>Let me know if there's something I missed.</p>	<p>I want to simulate the effect of temperature on a semiconductor.</p> <p>I can use <code>.temp ...</code> or <code>.option temp ...</code> or <code>.step temp ...</code>, but all of these show multiple lines and I am not able to do anything with it in the simulation, for instance, having an op-amp/comparator react on the change in the forward voltage of the semiconductor.</p> <p>LTspice has some tricks to convert a voltage to a resistance, like this:</p> <p><a href="https://i.stack.imgur.com/ZYF66.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/ZYF66.png" alt="enter image description here" /></a></p> <p>Is there something similar to create a gradient in temperature from 0°C at the beginning of the simulation to 100°C at the end?</p>	LTspice: simulating temperature	2024-01-12T10:57:28.570
697361	\|power-supply\|mosfet\|mosfet-driver\|actuator\|	<p>I wouldn't use that solenoid on the basis of the information in the data sheet (unless you can find a better data sheet of get it corrected): -</p> <p><a href="https://i.stack.imgur.com/Ujk4y.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/Ujk4y.png" alt="enter image description here" /></a></p> <p>After all, why at 100% duty would it take 10 watts whilst at 10% duty it takes 100 watts. I expect that the figures need reversing but, that's quite a big assumption given how poor the data sheet generally is.</p> <blockquote> <p><em>I have the 6V version of the actuator, and it says in the datasheet that at 100% duty cycle, it uses 100 W of power.</em></p> </blockquote> <p>No it doesn't and, that's therein lies the problem.</p>	<p>I have a linear actuator that I need to design a circuit for, where an Arduino is going to control it.</p> <p>Here's the datasheet (pdf) for the actuator: <a href="https://www.red-magnetics.com/en/product-groups/linear-solenoids/cylinder-solenoids/its-lz-2560-z/?pdf=1" rel="nofollow noreferrer">https://www.red-magnetics.com/en/product-groups/linear-solenoids/cylinder-solenoids/its-lz-2560-z/?pdf=1</a></p> <p>It's the first time I'm using an actuator so I'm not sure how to read this datasheet which doesn't seem to have much information. So I have to choose a power supply and an appropriate MOSFET for this, but what would be the power rating?</p> <p>I have the 6V version of the actuator, and it says in the datasheet that at 100% duty cycle, it uses 100 W of power. Would the power supply need to be able to deliver 100/6 = 16,7 A?</p> <p>Related question: <a href="https://electronics.stackexchange.com/questions/665176/linear-solenoid-specifications">Linear solenoid specifications</a></p>	How much power to drive this actuator?	2024-01-12T13:26:07.477
697362	\|analog\|cmos\|	<p>I think in the linked document the terminology (A_open) and the used symbols (beta=h21) are somewhat confusing. More than that, to use an ideal current source to drive a MOSFET complicates the whole analysis. Nevertheless, I think that everything is correct.</p> <p>At first, we should realize that we have <strong>current-controlled feedback</strong> and we need - at the same time - a <strong>voltage</strong> to drive the FET M1 in Fig. 8.66.</p> <p><strong>1)</strong> How works the feedback? The current source I_in drives the current through the Rf-path and creates a gate voltage at node Y (across Rs\|\|1/g) which will be reduced by the voltage drop across Rs caused by the current I_out (no feeedback current through RF). <strong>This describes the feedback effect</strong> in words (180deg phase inversion due to common-source/common drain): Two currents with opposite sign meet in node Y and create the gate voltage for M1.</p> <p><strong>2.)</strong> My explanation starts with the well-known <strong>classical feedback model</strong> applied (as an example) to an inverting opamp (voltage-controlled current feedback). We will se that the used quantity "<strong>Aopen</strong>" in the linked doc needs an interpretation (because it is <strong>NOT identical</strong> to the opamps <strong>open-loop gain Ao</strong>).</p> <p><strong>3.)</strong> The closed-loop gain of the inverting opamp is <strong>Acl=-(Hf * Ao)/[1+(Hr * Ao)]</strong></p> <p>with forward damping <strong>Hf=R2/(R1+R2)</strong> and feedback factor <strong>Hr=R1/(R1+R2)</strong>.</p> <p>For Ao approaching infinity we arrive at the well-known expression <strong>Acl=-Hf/Hr=R2/R1</strong>.</p> <p><strong>4.)</strong> Now let us compare the expression for the closed-loop expression in 3. with the closed-loop gain in the linked document (ignoring the negative sign):</p> <p><strong>Acl=(Hf * Ao)/[1+(Hr * Ao)]=Aopen/(1+ h21 * Aopen)</strong></p> <p>As we can see, both open-loop gain expressions are <strong>not identical</strong> because Aopen does not equal Ao. Therefore, the feedback factor <strong>Hr</strong> is <strong>not identical</strong> to the used feedback quantity <strong>h21</strong>.</p> <p>The comparison gives: <strong>Hr=h21 * Hf</strong> or <strong>h21=Hr/Hf</strong>.</p> <p><strong>5.)</strong> Applying the (classical) definitions for Hf and Hr (see 3.) on the shown circuit in Fig. 8.66 we can write:</p> <p><strong>Hr=Rs</strong> (feedback voltage across Rs and no current through Rf) and <strong>Hf=Rs+Rf</strong> (input voltage caused by the signal source I_in).</p> <p>Therefore: <strong>h21=beta=Hr/Hf=Rs/(Rs+Rf)</strong>.</p> <p>(Because of current feedback the quantities Hf and Hr are not dimensionless; the are given in V/A).</p> <p><strong>Comment</strong>: From the circuit it was by simple visual inspection not evident to me that the feedback factor is Rs/(Rs+Rf). I think the reason is that (1) we have current-controlled feedback and (2) an input current source and - at the same time - a FET which does not consume any input current. And another reason was a definition for the gain without feedback (A_open) which - in contrast to the opamp example - contains also the input damping of the feedback network. Consequently, also the feedback factor beta=h21 has another definition if compared with the opamp example which I am more familiar with.</p> <p>Finally, it must be mentioned that Razavis "A_open" is NOT identical to the commonly used term "loop gain".</p> <p><strong>EDIT</strong> : Upon request I have added the example circuit (inverter) and the corresponding block diagram (feedback model, Hf and Hr as defined in the text above).</p> <p><a href="https://i.stack.imgur.com/6afyt.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/6afyt.jpg" alt="enter image description here" /></a></p>	<p>The following is from the book <a href="https://electrovolt.ir/wp-content/uploads/2014/08/Design-of-Analog-CMOS-Integrated-Circuit-2nd-Edition-ElectroVolt.ir_.pdf" rel="nofollow noreferrer">Design of Analog CMOS Integrated Circuit</a>, Page 314.</p> <p>Calculate the open-loop and closed-loop gains of the circuit shown in Fig. 8.66(a). Assume that λ = γ = 0.</p> <p><a href="https://i.stack.imgur.com/a2LT0.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/a2LT0.png" alt="enter image description here" /></a></p> <p>For feedback network consisting of <span class="math-container">\$R_S\$</span> and <span class="math-container">\$R_F\$</span>,</p> <p><span class="math-container">$$h_{21} = -\frac{R_S} {R_S + R_F}$$</span></p> <p>How did the author get this <span class="math-container">\$h_{21}\$</span>?</p> <p>The author has a similar example for this.</p> <p><a href="https://i.stack.imgur.com/r4qpt.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/r4qpt.png" alt="enter image description here" /></a></p> <p>In this case, the feedback network is</p> <p><span class="math-container">$$g_{21} = \frac{R_S} {(R_F + R_S)}$$</span></p> <p><strong>Similarly, we can also use this method for example 8.66.</strong></p> <p><span class="math-container">$$h_{21} = \frac{R_F} {R_S + R_F}$$</span></p>	Where am I wrong in understanding feedback network?	2024-01-12T13:26:15.323
697364	\|transistors\|ltspice\|	<p>What the plot shows is pretty much what you'd expect, even if you didn't have the ridiculously large capacitors. You have a 1 kHz sine wave and your plot shows 70 µs of it. That's about 1/14th of a cycle or around 25<span class="math-container">\$^\circ\$</span>.</p>	<p>I have this circuit I'm supposed to analyze. I am asked to set v1 to a sine wave V1= A sin (2pi f t) with a frequency f = 1 kHz and A = 5mV. I think I did everything right, but when I run the simulation I have 2 issues:</p> <p>Edit: I just realized that it should be SIN(0 0.005 1k), but it doesn't change my problem.</p> <p><a href="https://i.stack.imgur.com/NaDhZ.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/NaDhZ.png" alt="enter image description here" /></a></p> <p>One: It takes REALLY long to simulate, like much longer than all my other circuits and most importantly,</p> <p>Two: Instead of showing a sine wave, I get this instead:</p> <p><a href="https://i.stack.imgur.com/eKIZm.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/eKIZm.png" alt="enter image description here" /></a></p> <p>It should, however, show a normal sine wave. Can anyone explain why this is happening?</p>	Bizarre behavior with SIN LTSpice	2024-01-12T13:47:33.150
697367	\|capacitor\|voltage-doubler\|	<blockquote> <p>In the circuit, we know that when D1 is connected then the C1 capacitor is also in the circuit until it's fully charged.</p> </blockquote> <p>Terminology: D1 is permanently (always) connected. You mean "when D1 is forward biased (conducting)".</p> <blockquote> <p>Why when D1 is disconnected and D2 and C2 are in the circuit, C1 can't discharge?</p> </blockquote> <p>The characteristic of a diode is to allow current to flow in one direction only - the direction of the arrow in its symbol.</p> <p>The result is that C1 and C2 can't discharge back to the voltage source but they can discharge to the load, R<sub>L</sub>. The result of this will be to cause some ripple on the otherwise steady DC supply.</p> <blockquote> <p>What is the reason behind it?</p> </blockquote> <p><a href="https://i.stack.imgur.com/15n8Wm.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/15n8Wm.png" alt="enter image description here" /></a></p> <p>You might find the non-return valve analogy useful on my page, <a href="http://lednique.com/what-is-an-led/" rel="nofollow noreferrer">What is an LED</a>.</p> <blockquote> <p>And so doesn't C2?</p> </blockquote> <p>D2 and C2 form in inverse of the D1 and C1 circuit. They generate a negative voltage relative to the C1 - C2 common node.</p>	<p><a href="https://i.stack.imgur.com/akQsF.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/akQsF.jpg" alt="enter image description here" /></a></p> <p>In the circuit, we know that when D1 is connected then the C1 capacitor is also in the circuit until it's fully charged. Why when D1 is disconnected and D2 and C2 are in the circuit, C1 can't discharge? What is the reason behind it? And so doesn't C2?</p>	Why don't the C1 and C2 capacitors discharge?	2024-01-12T14:38:46.160
697368	\|capacitor\|resistors\|ltspice\|pulse\|	<blockquote> <p><em>My aim is to lower it's Voltage by 7.3V, so it will have a pulse graph going from 2.7 to -17.3V. But I don't know how to configure the circuit for that</em></p> </blockquote> <p>You need D2 to be equivalent to an ideal diode in series with a voltage source of 2.7 volts: -</p> <p><a href="https://i.stack.imgur.com/yVK80.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/yVK80.png" alt="enter image description here" /></a></p> <p>This prevents the voltage on the anode of D2 rising any higher than +2.7 volts. If the only model of diode you have has a forward volt drop that isn't zero (ideal) you will have to play around the the 2.7 volt source by lowering it maybe 0.5 volts. Experiment!!!</p>	<p>I am trying to make a negative clamper in LTspice. The pulse source goes from 10V to -10V harmonically. My aim is to lower it's voltage by 7.3V, so it will have a pulse graph going from 2.7 to -17.3V, but I don't know how to configure the circuit for that.</p> <p><a href="https://i.stack.imgur.com/uKPZP.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/uKPZP.png" alt="" /></a></p>	How do I configure a negative clamper in LTspice?	2024-01-12T14:45:37.033
697377	\|flipflop\|counter\|synchronous\|sequential-logic\|	<h3>initial state, general comments</h3> <p>One of the first issues encountered in a problem like this is the initial state, itself. In simulators, FF's usually start up with <span class="math-container">\$Q=0\$</span> and <span class="math-container">\$\overline{Q}=1\$</span>.</p> <p>In some physical reality cases, there's no way to know the power-up state. In such cases, am asynchronous <strong>CLR</strong> and/or <strong>SET</strong> pin is needed. (Or some other mechanism to delay use until the initial states can be established.) Here, I'd attach a power-on reset circuit so that the FFs are held in either <strong>CLR</strong> or <strong>SET</strong> state while the power supply becomes stable, releasing that line only after the supply is known-stable.</p> <p>But in these purposes I'll assume that at the beginning <span class="math-container">\$Q=0\$</span> and <span class="math-container">\$\overline{Q}=1\$</span>.</p> <h3>initial state assumptions</h3> <p>In this case, I'll take it that each T FF powers up with <span class="math-container">\$Q=0\$</span> and <span class="math-container">\$\overline{Q}=1\$</span>.</p> <p><strong>Antonio51</strong> brings up an important point: state <strong>2</strong> comes up twice and it doesn't transition to the same <em><strong>next</strong></em> state. So this means you need an additional T FF to distinguish one from the other, or four T FFs not three.</p> <p>It doesn't matter what it's initial state is, you can work with it either way. But for simplicity's sake, let's assume that the first state <span class="math-container">\$2\$</span> uses the added T FF as <span class="math-container">\$Q=0\$</span> and <span class="math-container">\$\overline{Q}=1\$</span> and the second state <span class="math-container">\$2\$</span> uses it, oppositely.</p> <p>This distinguishing bit can be placed anywhere you want. Doesn't matter. But I'll make it the higher-order bit of the sequence, again for simplicity's sake.</p> <p>Since you want the initial state to be <span class="math-container">\$6\$</span> this just means that you set things up so that your <em><strong>actual</strong></em> output is taken as <span class="math-container">\$\overline{Q_2}\:\overline{Q_1}\:Q_0\$</span>.</p> <p>To get the desired result, <code>6 → 4 → 2 → 0 → 2 → 5 → 3 → 1</code>, the states will be <span class="math-container">\$0\$</span>, <span class="math-container">\$2\$</span>, <span class="math-container">\$4\$</span>, <span class="math-container">\$6\$</span>, <span class="math-container">\$12\$</span>, <span class="math-container">\$3\$</span>, <span class="math-container">\$5\$</span>, and <span class="math-container">\$7\$</span>.</p> <p>Take <span class="math-container">\$\overline{Q_2}\$</span>, <span class="math-container">\$\overline{Q_1}\$</span>, and <span class="math-container">\$Q_0\$</span> as the counter outputs.</p> <h3>FF options</h3> <p>The following is just a note. You've already said that you want T FF. Granted.</p> <p>But to be pedantic it doesn't hurt to keep in mind there are at least these options for FFs:</p> <p><span class="math-container">$$\begin{array}{c\|c\|c} \text{Transition} & \text{JK FF} & \text{T FF} & \text{D FF}\\\hline {\begin{smallmatrix}\begin{array}{c} \text{start }\to\text{ end}\\\\ 0 \quad \to \quad 0\\ 1 \quad \to \quad 1\\ 0 \quad \to \quad 1\\ 1 \quad \to \quad 0 \end{array}\end{smallmatrix}} & {\begin{smallmatrix}\begin{array}{cc} J & K \\\\ 0&x\\ x&0\\ 1&x\\ x&1 \end{array}\end{smallmatrix}} & {\begin{smallmatrix}\begin{array}{c} T\\\\ 0\\ 0\\ 1\\ 1 \end{array}\end{smallmatrix}} & {\begin{smallmatrix}\begin{array}{c} D\\\\ 0\\ 1\\ 1\\ 0 \end{array}\end{smallmatrix}} \end{array}$$</span></p> <h3>counter table</h3> <p>The table I see for this problem is:</p> <p><span class="math-container">$$\begin{array}{c\|c} \text{States} & \text{FF Inputs}\\\hline\\ {\begin{smallmatrix}\begin{array}{cccc} Q_D & Q_C & Q_B & Q_A\\ \vphantom{\left.\overbrace{\begin{array}{ccc}J & K & T & D\end{array} } \right.}\\ 0&0&0&0\\ 0&0&1&0\\ 0&1&0&0\\ 0&1&1&0\\ 1&1&0&0\\ 0&0&1&1\\ 0&1&0&1\\ 0&1&1&1\\\\ 0&0&0&1\\ 1&0&0&0\\ 1&0&0&1\\ 1&0&1&0\\ 1&0&1&1\\ 1&1&0&1\\ 1&1&1&0\\ 1&1&1&1 \end{array}\end{smallmatrix}} & {\begin{smallmatrix}\begin{array}{cccc} Q_D & Q_C & Q_B & Q_A\\ \left.\overbrace{\begin{array}{cccc}T\\ 0\\ 0\\ 0\\ 1\\ 1\\ 0\\ 0\\ 0\\\\ x\\ x\\ x\\ x\\ x\\ x\\ x\\ x \end{array} } \right. & \left.\overbrace{\begin{array}{cccc}T\\ 0\\ 1\\ 0\\ 0\\ 1\\ 1\\ 0\\ 1\\\\ x\\ x\\ x\\ x\\ x\\ x\\ x\\ x \end{array} } \right. & \left.\overbrace{\begin{array}{cccc}T\\ 1\\ 1\\ 1\\ 1\\ 1\\ 1\\ 1\\ 1\\\\ x\\ x\\ x\\ x\\ x\\ x\\ x\\ x \end{array} } \right. & \left.\overbrace{\begin{array}{cccc}T\\ 0\\ 0\\ 0\\ 0\\ 1\\ 0\\ 0\\ 1\\\\ x\\ x\\ x\\ x\\ x\\ x\\ x\\ x \end{array} } \right. \end{array}\end{smallmatrix}} \end{array}$$</span></p> <h3>k-maps</h3> <p>I'm not going to draw out the k-maps. You can take the above table and generate those, if you like. And it's good practice.</p> <p>However, you can also readily plug any part of the above information into Steve Rickman's <em>Logic Friday</em> program (the latest version I have is 1.1.4.) It will minimize the logical algebra. If you do your own k-maps, verifying your findings using Logic Friday makes sense.</p> <p>When using <em>Logic Friday</em>, also make sure that you select its <code>minimize</code> option as shown below:</p> <p><a href="https://i.stack.imgur.com/YDtks.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/YDtks.png" alt="enter image description here" /></a></p> <p>From there, you should be able to set up the logic for your T FFs.</p> <p>Don't forget that your output is <em><strong>not</strong></em> taken from the <span class="math-container">\$Q\$</span> outputs the lower-order three T FFs. Take <span class="math-container">\$\overline{Q_2}\$</span>, <span class="math-container">\$\overline{Q_1}\$</span>, and <span class="math-container">\$Q_0\$</span> as the counter outputs!</p>	<p>I'm trying to design a counter circuit that counts 6 → 4 → 2 → 0 → 2 → 5 → 3 → 1 using T flip flops and I haven't been able to achieve it. I tried the steps below and designed the circuit below in CircuitVerse, but it doesn't work properly. Where am I making a mistake? Some people have pointed out I needed to use a Mealy machine, but I haven't been able to understand why.</p> <p><a href="https://i.stack.imgur.com/Zye9H.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/Zye9H.png" alt="First three steps" /></a></p> <p><a href="https://i.stack.imgur.com/Fjdxy.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/Fjdxy.jpg" alt="Circuit Diagram" /></a></p>	Trying to design a synchronous sequential counter circuit with a given sequence	2024-01-12T17:09:20.257
697382	\|timer\|	<p>The Curtis Instruments <a href="https://cdn.curtisinstruments.com/products/datasheets/200_datasheet_en.pdf" rel="nofollow noreferrer">Solid State Elapsed Time Monitor 200 SERIES</a> description contains:</p> <blockquote> <p>Safe, reliable EEPROM memory storage of data <strong>without battery back up</strong></p> </blockquote> <p>The datasheet linked above shows the data format used to read the elapsed time: <a href="https://i.stack.imgur.com/GRcio.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/GRcio.png" alt="enter image description here" /></a></p> <p>Some models have a pin which can reset the elapsed time. It looks like there is some protection against inadvertent reset of the elapsed time since:</p> <ol> <li>The supply voltage range is 4.75 – 10 VDC</li> <li>The reset voltage is 20 VDC +/– 5%, supplied on a dedicated pin.</li> </ol> <p>This was just the first example of a Solid State Elapsed Time Monitor I found where the datasheet described how the elapsed time was recorded in non-volatile memory (in this example EEPROM).</p>	<p>I don't know if such a thing exists already. I'm looking for a component that can record how long a circuit has been powered on. Kind of like the "change filter" light on a fancy vacuum cleaner. It must be able to resume recording after being powered off and on again and cannot use a battery backup.</p> <p>I've already implemented this before using a microcontroller and FRAM, but i'm curious if such a thing already exists on the market in one package.</p> <p>edit: the component must also be resettable.</p>	Is there a component that can record circuit on-time without a battery?	2024-01-12T18:22:36.110
697391	\|power-supply\|dc-motor\|	<p>If the motors are rated at 250W, then you need a 500W supply, 20.83A unless you test at your desired max torque (but how will you power the test?). However the starting current surge can be 3x the rated current, regardless of how much current you intend to use to drive the motors steady-state. You can reduce this somewhat with soft-start circuits, ramped PWM, or inrush current limiters, but expect to have to deal with this. Some power supplies can support brief 50% or 100% overloads but some will trip off on overcurrent protection. Consult the datasheet.</p>	<p><a href="https://i.stack.imgur.com/yccPj.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/yccPj.jpg" alt="enter image description here" /></a></p> <p>I recently purchased 2 Jazzy Wheelchair Gearbox Motors (12-24 VDC) to use in a robotics project. I've done tons of LED, Arduino, and smaller motor projects but this is my first time doing a project with heavier duty electronics so I want to make sure I don't burn out any expensive parts before I start tinkering.</p> <p>Naturally the finished robot will eventually run on two 12 V batteries in series. Wheelchair batteries are easy to come by so I'm not too worried about finding a proper unit, though I don't really want to deal with batteries until the build is done. I'm not 100% sure as the motor listing omitted this, but I believe it to be rated at 250 W.</p> <p>How many amps must a power supply be rated for in order to run both motors?</p> <p>(24 V x 10 A = 240 W) Does that mean I need 20 A? More? The motors won't be working too hard during testing; they'll be mounted on my workbench for this part.</p>	Testing wheelchair motors on an AC to DC power supply	2024-01-12T19:15:06.983
697406	\|circuit-design\|solar-cell\|diy\|electromagnet\|small-gauge-wire\|	<blockquote> <p>magnetic resistance</p> </blockquote> <p>I know what you mean, but that's not really a term in widespread use. Electromagnetic force would be quite descriptive instead.</p> <blockquote> <p>a better solar cell?</p> </blockquote> <p>Yes, definitely. A larger solar cell would help. The square ones you'd find on top of solar lights should be sufficient for this.</p> <blockquote> <p>a smaller capacitor?</p> </blockquote> <p>Not at all. The bigger the better. But of course it will take longer to charge up. I'd leave the capacitor unchanged for now. There is a possibility that the capacitor itself is bad (electrically leaky). But I wouldn't replace for a larger capacity value. Leave be for now.</p> <hr /> <p>It's likely that the toy doesn't have an "undervoltage lockout" and wastes energy that way.</p> <p>Solar toys that have insufficient solar input to work just off solar power - and this one is of that kind, due to a very small cell - need to first charge up a capacitor from the solar cell. Once the voltage on that capacitor is high enough, the "motor" is turned on and the toy will "run" for some time.</p> <p>There are modern, single-chip, ultra-low-power (they don't use much electricity) voltage monitors that can be used to detect when a capacitor is charged up high enough and turn on the electromagnet and its driving logic. Such a chip uses so little power that it won't be discharging the capacitor while the latter is charging up ("soaking up the Sun").</p> <hr /> <p>I'm sure the toy is salvageable, but how much reengineering it will need is anyone's guess unless they opened a similar toy before.</p> <p>Perhaps getting it to work from a regular small battery - say one or two AAA cells, so 1.5V or 3V - would be a good starting point. Just to make sure the thing functions at all. Only then will it make sense to mess with the solar cell, capacitor, etc.</p>	<p>My son has a minecraft solar bobble head (in this case a bobble Steve). Under light it swings a diamond sword this exact one (Puckator Officially Licensed Minecraft Steve Solar Pal <a href="https://amzn.eu/d/gH1XvAn" rel="nofollow noreferrer">https://amzn.eu/d/gH1XvAn</a>).</p> <p>It is made up of a small solar cell, connected to a circuit board that holds a single capacitor and the board is connected to the copper coil. A magnet sits in a plastic housing that is connected to Steve by automaton connections and dynamics (photos can be added if needed).</p> <p>It is dismal it barely moves under any light regardless of source (sun, room, phone, torch, plant grow UV). How can I increase its magnetic resistance? A better solar cell? A smaller capacitor? A smaller/larger voice cell copper coil? I've already tried swapping out the magnet for neodymium button magnets but it seems the issue isn't in the strength of the magnet</p> <p>Ps. I know it's silly and probably never worked in the first place but me and my son are going to fix it or make it better, so any suggestions aren't wasted they are all in the name of my son learning electronics and physics. (He's 8 and rather ahead for his age.)</p>	How to improve my son's solar bobble head	2024-01-12T22:01:03.873
697414	\|verilog\|hdl\|	<p>We no longer implement our own hardware like Jack Kilby did in 1958 creating the first <a href="https://americanhistory.si.edu/collections/nmah_689592" rel="nofollow noreferrer">Integrated Circuit</a>. Even if you write the Boolean equations for a full adder, some tool needs to synthesize and map those equations to a set of transistors or logic gates.</p> <p>Synthesis tools have captured millions of hours of human intelligence to implement circuits with the best performance and area in the least amount of time. So unless you think you have come up with some new implementation a synthesis tool has never seen before, you should write your code at the highest level of abstraction your tool can understand.</p>	<p>When using Verilog, when should you use default operators like <code>a + b</code>, and when should you implement your own version of the hardware, like writing a full adder? Is it only when you need a specific need, or is it better practice to know exactly what hardware is being generated?</p>	When should you use default operators vs. implementing your own hardware?	2024-01-12T23:30:51.797
697425	\|mosfet\|	<p>The circuit works as intended. The source terminal of the MOSFET is the ground connection, not 12V.</p> <p>Swap the output terminals around - you have them backwards.</p> <p>If you want to switch the +12V line (instead of ground), you need a reverse polarity protection circuit based on a P-Channel MOSFET instead. The N-Channel version always switches ground.</p>	<p>I have a bare PCB with N-Channel MOSFET in the input (12V), however when connecting the power source, no voltage comes out from the MOSFET, and when connecting with reverse polarity, the output from the MOSFET is -12V.</p> <p>Tried three different MOSFETs, all give the same results. The MOSFET is - <a href="https://www.lcsc.com/product-detail/MOSFETs_HUAYI-HYG025N06LS1C2_C2827231.html" rel="nofollow noreferrer">https://www.lcsc.com/product-detail/MOSFETs_HUAYI-HYG025N06LS1C2_C2827231.html</a></p> <p>I initially tried with the original circuit attached, and after also tried to remove everything (The Diode and Capacitor)except the MOSFET - same results. Nothing comes out from the (S)ource when connecting (+12V) (maybe 500mV...), but if connecting (-12V) (reveres polarity) the (S)ource outputs (-12V).</p> <p>Is this a faulty schematic or faulty MOSFET?</p> <p><a href="https://i.stack.imgur.com/4wBTL.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/4wBTL.jpg" alt="Here is the original circuit" /></a></p>	Help with N-Channel MOSFET circuit and behaviour	2024-01-13T01:17:22.913
697430	\|impedance\|impedance-matching\|half-bridge\|	<p><img src="https://i.stack.imgur.com/PDNdv.png" alt="schematic" /></p> <p><sup><a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fPDNdv.png">simulate this circuit</a> – Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a></sup></p> <p>Note we omit the coupling capacitor for convenience. Choose a value such that reactance is much less than (say <10%) the minimum inverter load impedance, at minimum operating frequency. (At such low ripple fraction, it can even be polyester type, though higher current handling can be found in polypropylene.)</p> <p>This is an implicit L-match network, the equations of which can be referenced from RF tools, or solved directly:</p> <p><span class="math-container">$$ {L_M}^2 = \frac{1}{\frac{\omega_r}{Q R_I L_W} - \frac{1}{Q^2 {L_W}^2}} $$</span></p> <p>Where <span class="math-container">\$L_M\$</span> is the matching inductance, <span class="math-container">\$L_W\$</span> is the work coil inductance, <span class="math-container">\$\omega_r\$</span> is the resonant frequency, <span class="math-container">\$Q\$</span> is the work coil Q factor (other components assumed ideal, or their losses rolled into an equivalent value here), and <span class="math-container">\$R_I\$</span> is the desired inverter load resistance.</p> <p>We can rearrange this to an alternative form,</p> <p><span class="math-container">$$ L_M = L_W Q \sqrt{\frac{R_I}{R - R_I}} $$</span></p> <p>where <span class="math-container">\$R\$</span> is the resistance of the tank circuit, <span class="math-container">\$R = Q \omega_r L_W\$</span>. Of course either sign is an acceptable solution to the equation, but we choose positive for convenience.</p> <p>Note that we can split the circuit into the cascade of two resonant circuits, series matching to parallel:</p> <p><img src="https://i.stack.imgur.com/5Ihhc.png" alt="schematic" /></p> <p><sup><a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2f5Ihhc.png">simulate this circuit</a></sup></p> <p>At resonance, the parallel tank reactances disappear, and we have an R-loaded series resonant L-match circuit, LM-CM-R. We can virtually split <span class="math-container">\$C_T\$</span> into corresponding series and parallel resonant fractions <span class="math-container">\$C_T = C_M + C_W\$</span>, and this condition occurs when <span class="math-container">\$C_W = C_T \frac{L_M}{L_W + L_M}\$</span> and <span class="math-container">\$C_M = C_T \frac{L_W}{L_W + L_M}\$</span>.</p> <p>We can express the resonant frequency in this way, or by noting that the circuit has an inductor divider, the Thevenin equivalent of which has them acting in parallel. Or even more directly, since the inverter is assumed zero impedance (a good approximation for a high-efficiency switching circuit), by superposition, they are simply in parallel. So we have:</p> <p><span class="math-container">$$ \omega_r = \sqrt{\frac{L_M + L_W}{C L_M L_W}} $$</span></p> <p>Note that L<sub>M</sub> is a term in ω<sub>r</sub>, so we have a circular reference if we try to solve based on given values; this goes away if we assume a fixed operating frequency and allow C<sub>T</sub> for example to shift, and adjust our calculations until close to the intended value.</p> <p>We can simulate some values to prove it out:</p> <p><img src="https://i.stack.imgur.com/KZmpT.png" alt="schematic" /></p> <p><sup><a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fKZmpT.png">simulate this circuit</a></sup></p> <p>Without loss of generality, <span class="math-container">\$C_T\$</span> and <span class="math-container">\$L_W\$</span> have been fixed (<span class="math-container">\$Z_0 = 1\,\Omega\$</span>), and four values of <span class="math-container">\$R\$</span>, <span class="math-container">\$L_M\$</span> have been chosen. The peak input current in each was measured. They give R<sub>I</sub> of:</p> <ol> <li>L<sub>M</sub> = 47µH, R = 10Ω (Q = 10): R<sub>I</sub> = 20.33Ω; <strong>expected L<sub>M</sub>: 8.52Ω</strong></li> <li>L<sub>M</sub> = 47µH, R = 50Ω (Q = 50): R<sub>I</sub> = 9.747Ω; expected L<sub>M</sub>: 9.36Ω</li> <li>L<sub>M</sub> = 10µH, R = 50Ω (Q = 50): R<sub>I</sub> = 0.5963Ω; expected L<sub>M</sub>: 0.593Ω</li> <li>L<sub>M</sub> = 10µH, R = 10Ω (Q = 10): R<sub>I</sub> = 2.489Ω; expected L<sub>M</sub>: 2.308Ω</li> </ol> <p>The low-Q solutions don't work well, more or less because no real solution exists (notice the second relation blows up when R<sub>I</sub> ≈ R); this is a byproduct of the assumption used to derive these relations (inverter current is real at resonance). In general there are three conditions: inverter current always inductive, inverter current just reaches zero reactance (double root), and inverter current reaches zero at two points (going capacitive inbetween). This at least requires a quadratic to express, but an exact solution of L<sub>M</sub> requires solving a quartic or quintic polynomial, which obviously isn't very convenient to write out and is best solved numerically. Alternately, you can repeat the calculation and adjust values in a simulator until impedance and frequency are as expected; the system should be stable with quickly converging results.</p> <p>Note that typical work coil Q factors range from 3-10 (close fit between coil and work, ferrous material below Curie temperature), to 10-30 (tight fit, highly conductive materials; modest fit, most materials), to 50+ (loose fit). I find it easy enough to estimate Q based on work coil and material, and an exact figure can be established later.</p> <p>Note also, the Q generally varies during operation, as work temperature rises, and magnetism disappears (if applicable). The load on the inverter therefore varies as well.</p> <p>Typically, the inverter is designed for excess capacity: for an inverter factor of 2, it can deliver nominal power at up to twice the nominal load current (i.e. Pmax / Vout), or down to half the nominal supply (if it's a variable-input type control).</p> <p>There is some gain, in terms of inverter factor, from making use of frequency-shift control, but notice this has a significant downside: the control loop has a double pole, which goes as the difference between driven and resonant frequencies, with the same time constant as the tank. This makes compensation quite challenging, especially if you have to operate into high-Q loads.</p> <hr /> <p>The original source to that schematic, by the way, appears to be Richie Burnett's work. The page is a classic in the internet induction heating community: <br /> <a href="http://www.richieburnett.co.uk/indheat.html" rel="nofollow noreferrer">High Frequency Induction Heating \| richieburnett.co.uk</a></p> <p>Sadly it appears to have been widely plaigarized now. I see a number of sites the schematic alone appears in:</p> <ul> <li><a href="https://www.researchgate.net/publication/326838893_State-of-the-Art_of_an_Induction_Furnace_Design_Construction_and_Control" rel="nofollow noreferrer">Shaila, Patil & Soni, P & Vaidya, Harshal. (2018). State-of-the-Art of an Induction Furnace: Design, Construction and Control. 07. 31-35.</a></li> <li><a href="https://www.slideshare.net/UdayAdha/induction-heating-by-high-frequency?smtNoRedir=1" rel="nofollow noreferrer">INDUCTION HEATING BY HIGH FREQUENCY RESONANT INVERTER, Uday Kumar Adha Vasavi College \| Slideshare.net</a></li> <li><a href="https://www.uihm.com/en/Induction-Heating-Technology/Base-details-of-High-Frequency-Induction-Heating.html" rel="nofollow noreferrer">Base details of High Frequency Induction Heating \| UIHM.com</a></li> </ul> <p>A more responsible search would repeat steps for each figure, and passages of text. Just from this result, I imagine quite many other instances can be found.</p>	<p>I’m currently building a half bridge induction heater and can’t understand impedance matching for the life of me.</p> <p>Here’s an example of a basic half bridge induction heater. How and why was 45uH calculated for the matching inductor? Note that I do know how to calculate and simplify impedances, I’m just confused on how the matching inductor value was calculated.</p> <p><a href="https://i.stack.imgur.com/kDG3h.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/kDG3h.png" alt="Barebones Half Bridge Induction Heater" /></a></p>	Half Bridge Impedance Matching	2024-01-13T05:11:02.677
697450	\|operational-amplifier\|sensor\|pir\|	<blockquote> <p><em>how would it be able to detect a person walking in front of it?</em></p> </blockquote> <p>I'd be looking at the other test circuit they show and recognize that to measure small changes in signal you need an AC amplifier as shown in the test circuit for white noise output: -</p> <p><a href="https://i.stack.imgur.com/aazAp.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/aazAp.png" alt="enter image description here" /></a></p> <p>Everything to the right of the red arrow needn't be built. But, you really need an oscilloscope. What you may find is that the 2.1 MΩ resistor (feedback on the left op-amp) might be adequate or, it might need adjusting for your actual needs. You might also find that the 22 μF capacitor might need to be bigger to adequately detect slow moving changes in IR picked-up.</p>	<p>I am using a Murata IRA-S500ST01A01 PIR motion sensor. This is the <a href="https://www.farnell.com/datasheets/3968253.pdf" rel="nofollow noreferrer">datasheet</a>. Based on a description of the pyro-electric effect from part 2 of <a href="https://docs.rs-online.com/440e/0900766b815bf4ed.pdf" rel="nofollow noreferrer">these application notes</a> for the IRA S210 (same family of sensors), the output voltage of the sensor should change in reaction to a change in temperature of the pyro-electric element.</p> <p>I have built this circuit from <a href="https://www.murata.com/%7E/media/webrenewal/products/sensor/infrared/datasheet_pir.ashx?la=en" rel="nofollow noreferrer">this data sheet</a> for the IRA S210:</p> <p><a href="https://i.stack.imgur.com/8mWt4.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/8mWt4.png" alt="enter image description here" /></a></p> <p>The op-amp I am using is actually the LM324N. I have connected the OUT line to a 10K resistor and then to GND, and placed the nodes of a multi-meter on either side of the resistor to measure voltage. What I have observed is that the voltage is stable at about 850mV. When I wave my hand across the sensor I get no response, but when I cup my hands around it or wave a stove-heated spatula across it I do see an increase in voltage of about 10mV. Is this to be expected?</p> <p>If so, how would it be able to detect a person walking in front of it?</p>	Is this behavior for a Murata PIR motion sensor test circuit expected?	2024-01-13T11:31:46.637
697459	\|rcd\|	<blockquote> <p><em>Maybe this is a very stupid question but to be sure. Does the neutral-ground bonding needs to be done before the RCD/GFCI breaker?</em></p> </blockquote> <p>It absolutely does (as indicated in your diagram).</p> <blockquote> <p><em>If there is an energized metal frame due to a fault, the RCD/GFCI breaker will see a difference between live and neutral only if the bonding is done before the breaker?</em></p> </blockquote> <p>Correct.</p>	<p>Does the neutral-ground bonding need to be done <strong>before</strong> the RCD/GFCI breaker? If there is an energized metal frame due to a fault, will the RCD/GFCI breaker see a difference between live and neutral only if the bonding is done before the breaker?</p> <p><a href="https://i.stack.imgur.com/KHFbz.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/KHFbz.png" alt="enter image description here" /></a></p>	Neutral to ground bonding place question	2024-01-13T13:02:17.530
697472	\|homework\|system\|	<p>Let <span class="math-container">\$x(t)=\delta(t)\$</span>. The output (the impulse response) is <span class="math-container">\$h(t) = \sin(t)\$</span>, which is not strictly zero for <span class="math-container">\$t<0\$</span>. Therefore, the system is not causal. A non-causal system is also not memoryless.</p> <p>The output signal for <span class="math-container">\$x(t)=\delta(t-2\pi)\$</span> is also <span class="math-container">\$\sin(t)\$</span>. Since the inputs <span class="math-container">\$\delta(t)\$</span> and <span class="math-container">\$\delta(t-2\pi)\$</span> produce the same output, the system is not invertible.</p>	<p><span class="math-container">\$T{(x(t))} = \int _{-\infty }^{+\infty }sin\left(t+\tau \right)x\left(\tau \right)d\tau\$</span></p> <p>Is this system causal or not? Is it memoryless or not?</p> <p>At first I thought it was not causal and with memory since the boundaries are from <span class="math-container">\$-\infty\$</span> to <span class="math-container">\$+\infty\$</span>.</p> <p>I later realized that since the boundary does not depend on <span class="math-container">\$t\$</span> then it is not correct to do it that way.</p> <p>I guess it means that the system is causal and memoryless, since it does not have dependence on <span class="math-container">\$t\$</span> at integral.</p> <p>How do I show it?</p> <p>If this helps:</p> <p>The system is linear, not time invariant, not stable (according to what I managed to find,) regarding invertible I guess it is not, but could not prove it. My intuition says it is not.</p>	Linear system - causal and memoryless system (integral)	2024-01-13T15:48:30.090
697473	\|circuit-analysis\|passive-filter\|frequency-response\|	<p>In the last formula with s ( in denominator),</p> <p><a href="https://i.stack.imgur.com/pJKAz.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/pJKAz.png" alt="enter image description here" /></a></p> <p>the term <span class="math-container">\$s^ 2 L\$</span> should be <span class="math-container">\$ s^2 L C \$</span> -> <span class="math-container">\$-w^2LC\$</span>.</p> <p>NB: you don't need passing to <span class="math-container">\$w\$</span>.<br /> Just search the "limit" when s-> infinity = <span class="math-container">\$(s^2 C R1 L)/(s^2 L C) = R1\$</span>.</p> <p>And it is R2 when s-> zero.</p>	<p>Consider the following circuit:</p> <p><a href="https://i.stack.imgur.com/vdhe6.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/vdhe6.png" alt="enter image description here" /></a></p> <p>By inspection, it can be said that the complex impedance of the circuit will be <span class="math-container">\$R_2\$</span> for very low frequencies and <span class="math-container">\$R_1\$</span> for very high ones, as the inductor will behave as an open circuit for very high frequencies and the capacitor will do the same for very low ones.</p> <p>I have tried to demonstrate the second statement (the impedance will be <span class="math-container">\$R_1\$</span> for very high frequencies) mathematically but I can't. Below are my calculations (let <span class="math-container">\$s\$</span> be <span class="math-container">\$j\omega\$</span>):</p> <p><span class="math-container">$$Z_t = \frac{1}{\frac{1}{R_1 + \frac{1}{sC}} + \frac{1}{R_2 + sL}} = $$</span></p> <p><span class="math-container">$$\frac{1}{\frac{sC}{sCR_1 + 1} + \frac{1}{R_2 + sL}} = $$</span></p> <p><span class="math-container">$$\frac{(sCR_1 + 1)(R_2 + sL)}{sC(R_2+sL) + sCR_1 + 1} = $$</span></p> <p><span class="math-container">$$\frac{sCR_1 R_2 + s^2CR_1 L + R_2 + sL }{s^2L + 1 + s(CR_1 + CR_2)} = $$</span></p> <p><span class="math-container">$$\frac{-w^2CR_1 L + R_2 + j\omega(L + CR_1 R_2)}{-w^2L + 1 + j\omega(CR_1 + CR_2)}$$</span></p> <p>Then, I calculate the module of <span class="math-container">\$Z_t\$</span> as:</p> <p><span class="math-container">$$\|{Z_t}\| = \frac{\sqrt{(R_2 - \omega^2CR_1L)^2 + (\omega(L+CR_1R_2))^2}}{\sqrt{(1-\omega^2L)^2 + (\omega(CR_1+CR_2))^2}}$$</span>.</p> <p>For very high frequencies, I do:</p> <p><span class="math-container">$$\lim_{\omega \to \infty}\frac{\sqrt{(R_2 - \omega^2CR_1L)^2 + (\omega(L+CR_1R_2))^2}}{\sqrt{(1-\omega^2L)^2 + (\omega(CR_1+CR_2))^2}}$$</span></p> <p>As <span class="math-container">\$(\omega^2)^2 = \omega^4\$</span>, I cancel out the squared terms to the right, leaving the following:</p> <p><span class="math-container">$$\lim_{\omega \to \infty}\frac{\sqrt{(R_2 - \omega^2CR_1L)^2}}{\sqrt{(1-\omega^2L)^2}}$$</span></p> <p>which yields</p> <p><span class="math-container">$$\frac{\sqrt{C^2R_1^2L^2}}{\sqrt{L^2}} = CR_1$$</span></p> <p>But it should be <span class="math-container">\$R_1\$</span>. What am I missing?</p>	Help demonstrating mathematically the behaviour of a passive filter	2024-01-13T16:04:11.780
697475	\|soldering\|hot-air\|	<p>There are a lot of videos of repair processes by really skilled electronics technicians. <a href="https://www.youtube.com/@ststele" rel="nofollow noreferrer">Here</a> is one, and he frequently mentions the temperatures and flow rates he is using to repair iPhones and such like, but keep in mind the flow rate settings are going to be different for different hot air rigs. There are others, of course, and watching a variety of techs work won't hurt at all. Rework is a physical skill with some technical aspects and I think a video or in-person instruction is most helpful in learn it.</p> <p>It's not just temperature, but how you play the airflow around and how much airflow there is.</p> <p>Also practicing on something that doesn't matter before you tackle something that is valuable to you. You need to be able to see what is going on, so lots of light and a microscope or magnifier is invaluable when dealing with smaller parts.</p> <p>The best method depends what is around it, and what kind of solder was originally used and what all is around the part you are trying to remove. One method uses special very low melting point solder (eg. Chip Quik- some of which melt at less than 65°C) to dilute the original high melting point lead-free solder, which is then thoroughly removed using fresh desoldering braid and replaced with medium melting point solder such as leaded eutectic 63/37 to place the replacement connector. And with relatively copious quantities of liquid flux applied very locally at each step, then cleaned off with pure isopropanol and inspected before proceeding to the next step.</p> <p>If the connector is broken, overheating it is not so much of an issue but you might want to shield adjacent parts from the air flow to prevent them from being blow off or overheated.</p>	<p>I am learning how to use a hot air gun on PCBs.</p> <p>I saw some videos of FPC connectors being desoldered by heating the back side of the PCB with a hot air gun. I am assuming it is being done to prevent melting of the plastic of the connectors.</p> <p>Is that an acceptable or even the preferred way of doing it? If so, at what temperature and airflow rate would one do that?</p>	What temperature should I use to desolder a FPC connector by heating the back side of the PCB with a hot air gun?	2024-01-13T16:20:56.613
697487	\|amplifier\|audio\|jfet\|	<p>If you see a 120Hz sawtooth on the output of your boost converter, and the device is battery powered, the question is whether it is a measurement issue or not, and in the latter case, how did it get in there...</p> <p>So first set the scope to trigger on mains. It's probably in the "trigger source" menu. When that's done, the scope will trigger on mains voltage zero crossing. If your "120Hz" remains steady on screen, it means it's synchronized to mains. If it sweeps then it's not synchronized and it does not come from mains.</p> <p>Assuming it is synchronized, next step is to check if it's a measurement artifact or not. You can do that by probing the circuit ground with your scope. You should get a flat trace, with a little bit of switching noise from your DC-DC. Then without moving the scope ground clip, probe VCC. If you see the same sawtooth when probing GND or VCC, then... the noise is not on VCC, it's probably being picked up by your probe.</p> <p>Note most scopes are Earthed. The guitar isn't Earthed but the guitar pedal you're working on is probably connected to a guitar amp that is Earthed. So you have a ground loop with the scope. You can check if the noise you're measuring with the scope goes away when you disconnect the output jack, which breaks the ground loop.</p> <p>If you conclude the 120Hz sawtooth really is present on VCC, then it can either come from the boost converter:</p> <ul> <li>feedback resistors picking up some noise</li> <li>or it operates in light load power saving mode</li> </ul> <p>...or it can come from variable output current wiggling the DC-DC's output voltage. I mean if there is a 120Hz signal on the input jack, your JFET amp is going to pull variable current from the supply, which will introduce some ripple on the supply. But in this case the supply ripple is not the cause of the problem, only a symptom of hum being picked up at the input.</p>	<p>In my first realization of a common source JFET preamplifier, I encountered a rather predictable problem but for which I was unable to find any documentation: the power supply ripple and noise are reflected in the output signal, which comes out amplified and audible in the audio output!</p> <p>The ripple has a frequency of about 120Hz and a Vpp of 7mV, this is the picture of the power supply output: <img src="https://i.stack.imgur.com/egClh.png" alt="enter image description here" /></p> <p>This is the ripple at the output of a 4.7μH π LC filter and ~4mF placed after the 600kHz step-up, which falls within the audibility threshold. This ripple also contains noise at 265kHz and 2MHz, which, being well beyond the audibility threshold, should not be a problem.</p> <p>So I wonder: what are the best ways to obtain a clean output of the signal to be amplified? Would an RC filter of 200Ω and 47μF only attenuate the issue, but not be a real solution? I would like to use a solution that requires discrete components and does not overly complicate the circuit. Can the noise at 265kHz and 2MHz have a negative impact for an audio application?</p> <p><strong>Additional information required:</strong></p> <ul> <li>Power Source:<a href="https://www.ti.com/lit/ds/symlink/tlv61048.pdf?ts=1705168279208&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FTLV61048" rel="nofollow noreferrer">TLV61048</a>, 3.7V input and 14V output,600kHz,4.7μH;</li> <li>JFETs tested: 2SK208, BF862;</li> <li>Inductor:<a href="https://datasheet.lcsc.com/lcsc/2310251551_Sunlord-SWPA5040S4R7NT_C305174.pdf" rel="nofollow noreferrer">SWPA5040S4R7NT</a></li> <li>Amplifier design source:<a href="https://www.runoffgroove.com/fetzervalve.html" rel="nofollow noreferrer">Fetzer Valve</a> R17=~2.3k</li> <li>Audio input: <a href="https://www.guitarscience.net/tsc/fender.htm#RIN=0&R1=100k&RT=200k&RB=200k&RM=10k&RL=1M&C1=230p&C2=100n&C3=47n&RB_pot=LogA&RM_pot=Linear&RT_pot=LogA" rel="nofollow noreferrer">Tone Stack</a> from pre-amplified guitar <a href="https://i.stack.imgur.com/8uHuu.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/8uHuu.png" alt="Circuit" /></a></li> </ul>	How to filter noise/ripple for a JFET audio amplifier?	2024-01-13T17:18:39.327
697492	\|microcontroller\|usb\|input\|mouse\|	<p>You need to look up how USB works.</p> <p>When plugged in, there is an enumeration process where PC asks what kind of device was connected, and in this case, your device likely wants to tell the PC that it a mouse or some other standard HID device. Then you need to send movement and button changes in USB packects according to HID standard.</p>	<p>I am making a device, similar to a cross between a controller and a mouse, and I wondered how I would send input to the computer.<br /> For example: Transmitting movement, buttons pressed etc.<br /> Also, how would I make it so the computer automatically detects it as a mouse.</p> <p>Thanks in advance.</p>	Transmitting input through USB from microcontroller	2024-01-13T18:38:20.660
697500	\|batteries\|capacitor\|motor\|dc-dc-converter\|generator\|	<p>Super capacitor or large capacitors (reservoir capacitor) are much cheaper, and sometimes exist only for low voltage. It's better to place the reservoir capacitor after the LDO because the linear voltage regulators just waste the energy that is between the input voltage and output voltage (so to speak).</p> <p>A step down regulator will also waste 15 to 20% of energy. Thought a large capacitor on the 24V side could increase the efficiency a little bit because it will power the LDO until it reaches 4V. So it has 20V to go before it says bye bye.</p> <p><img src="https://i.stack.imgur.com/HLEwK.png" alt="schematic" /></p> <p><sup><a href="/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fHLEwK.png">simulate this circuit</a> – Schematic created using <a href="https://www.circuitlab.com/" rel="nofollow">CircuitLab</a></sup></p>	<p>I just started to work on a small home project. I have an indoor bike that I use quite a lot. The resistance of the bike can be adjusted manually in a purely mechanical way (by tightening a screw). And I have some 24V DC motors laying around, so I thought, why not combine the two and create a smarter bike.</p> <p>My plan is to connect the motor to the bike and use a MOSFET and PWM to set the resistance level. When I exercise, the <em>generator</em> is going to generate some DC voltage, depending on the speed. I feed it through a bridge rectifier, just in case, then I place an N-channel MOSFET for setting the resistance level using a PWM signal.</p> <p>This is very simple so far, but now comes the fun part. I also want to run the circuit that handles the automatic difficulty setting using the power generated from the motor. But since the resistance is set using a PWM signal, the output voltage is also a square wave. Therefore, I add some capacitance after a diode to smooth out the voltage. I also added a zener diode to prevent too high voltages, just in case. I convert the output DC voltage of the motor to 5V (needed for the encoder of the motor and maybe some other circuitry) using a buck converter, and then I convert the 5V to 3.3V using an LDO. There, I will place my ESP or STM-based microcontroller circuit, which should not draw much current.</p> <p>I also want to measure both the input voltage and the 5V voltage line, and when it drops to an insufficient level, I want to have enough time to persist some data by writing it to a flash memory or an SD card. I will work on the low voltage detection later with some transistor-based interrupt line.</p> <p>You can find my current design later. Is this a viable idea? To use capacitors to extend the uptime with a couple of milliseconds for persisting data? Where should I place the capacitances, on which voltage line? I thought about putting them on the 3.3V line, because that is the most crucial circuit that would need to be up the longest. But when the supply voltage is gone and the circuit draws current from the capacitor, then the voltage of the capacitor will start to drop as well. Therefore, maybe I should pack capacitors on the 5V line or even the 24V line, so that even if that voltage drops, I will still have a stable 3.3V for the circuit. But then if I put the capacitances on the 24V or 5V line, then the additional circuitry will drain it faster. Or maybe put extra capacitances everywhere, so that every line has its own storage, and then the 3.3V line is up for the most time. But I don't necessarily want to overload the circuit with capacitances either. What capacitance size would you recommend using?</p> <p><a href="https://i.stack.imgur.com/8awNb.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/8awNb.png" alt="enter image description here" /></a></p>	How to extend up-time after power supply is gone	2024-01-13T19:21:44.167
697501	\|mosfet\|semiconductors\|solid-state-devices\|fabrication\|semiconductor-process-technology\|	<p>Generally, transistors used in logic circuits do have symmetrical source and drain characteristics. This includes the basic design and layout of the device, halo doping effects, VT adjusts and strain effects.</p> <p>Devices used for analog circuits may, and all high voltage devices have asymmetrical source and drain structures. This is because the source will not be biased more than a small voltage (say < 5 V) above the bulk, and VGS will not exceed a similar small value. However the drain may need to withstand very high voltages (to 1000 V) -- therefore it needs a lighter doping than the source (and portions of it need to be spaced further aways from the gate structure).</p> <p>For HV devices, this has the effect of adding a significant resistance in series with the drain (which is not present in the source side). This alone gives a different DC characteristic to the device. The additional capacitance associated with the drain gives a different AC characteristic.</p>	<p>In textbook treatments, one has that the source and drain of a MOSFET are completely symmetrical and therefore interchangeable -- the distinction is only made by which is at a higher voltage in the circuit in which the MOSFET is used. Gray and Meyer (<em>Analysis and Design of Analog Integrated Circuits</em>, 5e) however note that "In practice, the symmetry is good but not perfect."</p> <p>Why is the symmetry not perfect? Is it the case that fab processes actually design drain and source diffusions slightly differently (for, say, the unit transistor in a given process) or is the "in practice" caveat simply to note that drains will be connected to, for example, an output node with lots of other connections thereto whereas a source might not be. That is, is the "in practice" distinction between source and drain <em>intrinsic</em> to the process or simply about how we electrically connect them in most circuit designs?</p>	Why are drain and source not actually perfectly symmetric?	2024-01-13T19:24:53.347
697508	\|audio\|components\|component-selection\|	<p>If you only do care about understandability of the voice and not some other voice characteristics and your environment is not particularly noisy, 85-90dB are way above the pleasant sound level and will probably scare the hell of an unexpecting user. The normal human talking is 50-60dB and this is ~1000 times less power than 90dB.</p> <p>In practice, if you throw 10-100mW at whatever speaker you dig from the junk bin, you will get enough sound level to recognize speech. This is the power level most people listen to radio at in small and more or less quiet rooms.</p> <p>You may want to limit the bandwidth of the signal to e.g. 300-3000Hz just like older phone systems do in order to get good recognition vs distortion and used power.</p>	<p>I need a compact speaker suitable for a 16mm diameter tubular enclosure. The speaker must be capable of playing voice audio clips with sufficient clarity and volume to be easily hearable and understandable for 1-2m away in a small room. I'm thinking about 30% of a modern iPhones volume level would be fine.</p> <p>I'm looking at CUI Devices speakers page, they have <a href="https://www.cuidevices.com/catalog/audio/speakers?q=3Uv9-0cP0dM0fR0hZa3Wv9-0cP0dj0dM0fq0fR0g_0hZ0uL0JE0JK0Mx" rel="nofollow noreferrer">good filters</a> for width/height and tons of options that physically fit.</p> <p>I think I might have found a possibility: CMS-151125-076L100B</p> <ul> <li>15 x 11mm</li> <li>S.P. Level (dB): 92.5 (0.7 W / 1 m)</li> <li><a href="https://www.cuidevices.com/product/audio/speakers/miniature-(10-mm%7E40-mm)/cms-151125-076l100a" rel="nofollow noreferrer">Product page (links to data sheet)</a></li> </ul> <p>I'm worried though, is this as loud as I think it might be / how loud will it be? Maybe I'm missing something? It's pretty tiny.</p> <p>According to some <a href="https://www.quora.com/How-loud-can-an-iPhone-play-music-in-decibels" rel="nofollow noreferrer">random Quora answer</a> from 5y ago about iPhone volume: <em>"I have read that one can get up to 85–90 db at 0.5 meters"</em>. (an iPhone) So if this answer is accurate, then it should be relatively loud and meet my requirements as it?</p> <p>Is a speaker like this even capable of playing voice clips?</p>	Small Speaker with High dB. Loud enough?	2024-01-13T20:34:00.023
697509	\|led\|resistors\|basic\|low-voltage\|protoboard\|	<p>My students often made this mistake. So I forced myself to make this image of a similar board with drawn connecting lines.</p> <p><a href="https://i.stack.imgur.com/M3XUt.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/M3XUt.jpg" alt="Board (in front)" /></a></p> <p>Also, I removed (with great difficulty) the adhesive pad from the underside of the circuit board to reveal the connecting spring elements.</p> <p><a href="https://i.stack.imgur.com/pE51p.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/pE51p.jpg" alt="Board behind" /></a></p> <p>Finally, I even removed the spring elements so they could see their device. This "demo board" was constantly sitting on the workbenches.</p> <p><a href="https://i.stack.imgur.com/cO5Wh.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/cO5Wh.jpg" alt="A workbench" /></a></p> <p>And yet they were still making this wrong connection. As a result, LEDs, multimeters configured as ammeters...</p> <p><a href="https://i.stack.imgur.com/G5wBj.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/G5wBj.jpg" alt="Blown multimeter fuses" /></a></p> <p>... and pots suffered the most.</p> <p><a href="https://i.stack.imgur.com/s2eB5.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/s2eB5.jpg" alt="Blown pot" /></a></p> <p>I recommend you sacrifice a board and "reverse engineering" it:-)</p>	<p>I'm working on a super simple circuit, I want to light the LED.</p> <p>Power Source 1: 5.5v from 9v battery through breadboard power supply module<br /> Power Source 2: 5.5v from lab bench PSU<br /> LED Info: Vf - 3v to 3.2v; If = 20mA;<br /> Resistor: 150 +/- 2% - brown/green/black/black/brown (the close-up picture makes the browns look purple, but they <strong>are</strong> brown)</p> <p>Things to note:</p> <ol> <li>I have used a multimeter to test the connectivity, it beeps</li> <li>I have used a multimeter to verify voltage is getting through, it does</li> <li>I have used several different breadboards AND multiple tie points for each breadboard.</li> <li>I have used multiple different colors (adjusting the resistor for each based on Vf & If for the color)</li> <li>Whenever I check the LED connectivity with the 3.3v with an LED that can hold up to it, it lights up, again in multiple tie points</li> <li>weirdly, if I use a jumper cable to connect row abcde to fghij, the LED does not light up (again checking multiple tie points, and multiple boards), but when I directly connect the anode to abcde and the cathode to fghij it does light up.</li> <li>Yes I make sure that the anode and cathode or appropriately placed</li> <li>Yes I use the multimeter to check everything every new setup</li> <li>Yes I have used multiple values of Resistors pushing the resistance as low as is safely possible for the LED</li> <li>Yes I have checked the Ohms of for each resistor that I have used</li> <li>Yes, I have used both sides of the power tie strips</li> </ol> <p><strong>Working Configurations:</strong><br /> 3.3v from lab bench PSU <a href="https://i.stack.imgur.com/JOeda.jpg" rel="noreferrer"><img src="https://i.stack.imgur.com/JOeda.jpg" alt="3.3v from lab bench PSU" /></a></p> <p>3.3v from 9v via power supply module <a href="https://i.stack.imgur.com/ovFPP.jpg" rel="noreferrer"><img src="https://i.stack.imgur.com/ovFPP.jpg" alt="3.3v from 9v via power supply module" /></a></p> <p><strong>Non-Working Configurations:</strong><br /> 5.5v from lab bench PSU <a href="https://i.stack.imgur.com/ctpTG.jpg" rel="noreferrer"><img src="https://i.stack.imgur.com/ctpTG.jpg" alt="5.5v from lab bench PSU" /></a></p> <p>5.5v from 9v battery via power supply module<br /> <a href="https://i.stack.imgur.com/tnuqi.jpg" rel="noreferrer"><img src="https://i.stack.imgur.com/tnuqi.jpg" alt="5.5v from 9v battery via power supply module" /></a></p> <p>close up of parts<br /> <a href="https://i.stack.imgur.com/3WWGK.jpg" rel="noreferrer"><img src="https://i.stack.imgur.com/3WWGK.jpg" alt="close up of parts" /></a></p>	LED Fails to illuminate, what am I not seeing in my configuration(s)?	2024-01-13T20:43:41.997
697512	\|capacitor\|ac\|sensor\|capacitance\|	<p>You need a buffer amplifier (e.g. opamp connected as a unity gain buffer) to drive the guard from the sensing electrode signal. That way the voltage difference between the guard and the sensing electrode will be (ideally) zero; thus that capacitance won't draw any current and so the guard won't affect the sensed signal.</p> <p>Note that the opamp will (slightly) load the sensing signal -- you will have to calibrate this out of your system.</p> <p>Note that there are many sources of error in this type of setup that require care and high performance circuits to get accurate and reproducible results.</p>	<p>I am attempting to build my own capacitance probe for high precision displacement measurements. The working principle is simple - a constant current AC signal (~100kHz) is passed through the probe sensing electrode, and the surface being probed is grounded. As the capacitance between the probe and probed surface changes with distance, the voltage amplitude of the resulting AC signal is directly proportional to the distance.</p> <p>The circuit for providing the constant current AC signal can be found in <a href="https://www.researchgate.net/publication/332363868_Designing_a_High-Precision_AC_Current_Source_to_Measure_the_nm-Scale_Displacements_in_Mechanical_Systems" rel="nofollow noreferrer">literature</a>, so for the sake of this post assume that I already have an AC current source. The probe architecture I have decided on is one with a guard ring as shown below. <a href="https://i.stack.imgur.com/zqrhf.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/zqrhf.png" alt="enter image description here" /></a></p> <p>From my understanding, the guard ring is held at the same potential as the sensing electrode so it helps ensure the electric field between the sensing electrode and the probed surface is as uniform as possible. My question is how to accomplish this in practice?</p> <p>Simply connecting the sensing electrode to the guard ring would accomplish this, but it wouldn't work as the edge effects at the guard ring would be included in the measurement, defeating the entire purpose of the guard ring. I am wondering if using an op-amp buffer would work?</p>	Capacitance displacement probe guard ring circuitry	2024-01-13T20:56:16.550
697515	\|feedback\|	<p>Simple analysis: Have a look at the closed loop (the <strong>loop gain</strong> with Vin=0) and find the <strong>number of signal inversions</strong> within the loop. For negative feedback, there must be an <strong>uneven</strong> number of inversions.</p> <p>In your example: M1 does not cause a signal inversion between source and droain (common gate principle). However, and M2 in common source operation will cause a 180deg phase shift. T</p> <p>Therefore, we have <strong>negative feedback</strong> (one single sign inversion).</p> <p><strong>Comment to your last figure</strong>: For loop gain analysis, you should try to find a node within the loop where a relatively low output resistance is connected to a much larger input resistance.</p> <p>Then you can open the loop at this point and you can inject a test signal without changing too much the loading conditions at this point. Therefore, open the path at the gate of M2 and inject the test signal BETWEEN the drain node of M1 and the gate of M2. This is important, in particular, for loop gain simulation because otherwise you would destroy the DC operational point of the circuit.</p> <p>However, for a rough loop gain analysis (visual inspection only) you can use the scheme as shown in the figure: Test voltage Vf at the gate of M2 and output at the drain of M1 (with Vin=0).</p>	<p>The following is from the book <a href="https://electrovolt.ir/wp-content/uploads/2014/08/Design-of-Analog-CMOS-Integrated-Circuit-2nd-Edition-ElectroVolt.ir_.pdf" rel="nofollow noreferrer">Design of Analog CMOS Integrated Circuit</a>, Page 307.</p> <p><a href="https://i.stack.imgur.com/6y5O5.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/6y5O5.png" alt="enter image description here" /></a></p> <p>I think feedback is <strong>negative</strong> in my opinion.</p> <p>Here is what I think, see picture below.</p> <p><a href="https://i.stack.imgur.com/1FW7o.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/1FW7o.png" alt="enter image description here" /></a></p>	Is feedback positive or negative for this closed-loop circuit?	2024-01-13T21:53:13.500