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num_examples: 3
- name: m_Ti64_p_80_v_1.1
num_bytes: 73026665
num_examples: 2
- name: m_Ti64_p_80_v_1.2
num_bytes: 73026665
num_examples: 2
- name: m_Ti64_p_80_v_1.3
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- name: m_Ti64_p_80_v_1.4
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- name: m_Ti64_p_80_v_1.5
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num_examples: 2
- name: m_Ti64_p_80_v_1.6
num_bytes: 73026665
num_examples: 2
- name: m_Ti64_p_80_v_1.7
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num_examples: 1
- name: m_Ti64_p_80_v_1.8
num_bytes: 36513333
num_examples: 1
- name: m_Ti64_p_80_v_1.9
num_bytes: 36513333
num_examples: 1
- name: m_Ti64_p_80_v_2.0
num_bytes: 36513333
num_examples: 1
- name: m_Ti64_p_80_v_2.1
num_bytes: 36513333
num_examples: 1
- name: m_Ti64_p_80_v_2.2
num_bytes: 36513333
num_examples: 1
- name: m_Ti64_p_80_v_2.3
num_bytes: 36513333
num_examples: 1
download_size: 4445609703
dataset_size: 14386252952
configs:
- config_name: baseline
data_files:
- split: m_Ti6Al4V_v_0.0_0.1_0.1
path: baseline/m_Ti6Al4V_v_0.0_0.1_0.1-*
- split: m_Ti6Al4V_v_0.0_2.9_0.1
path: baseline/m_Ti6Al4V_v_0.0_2.9_0.1-*
- config_name: default
data_files:
- split: train
path: data/train-*
- config_name: process_maps
data_files:
- split: m_Ti64_p_0_20_20_v_0.0_0.0_0.1
path: process_maps/m_Ti64_p_0_20_20_v_0.0_0.0_0.1-*
- split: m_Ti64_p_0_480_20_v_0.0_2.9_0.1
path: process_maps/m_Ti64_p_0_480_20_v_0.0_2.9_0.1-*
- split: m_Ti64_p_0_480_20_v_0.0_2.9_0.1_a_0.27
path: process_maps/m_Ti64_p_0_480_20_v_0.0_2.9_0.1_a_0.27-*
- config_name: process_maps_baseline
data_files:
- split: m_Ti6Al4V_p_0_480_20_v_0.0_2.9_0.1
path: process_maps_baseline/m_Ti6Al4V_p_0_480_20_v_0.0_2.9_0.1-*
- split: m_Ti6Al4V_p_0_480_20_v_0.0_0.1_0.1
path: process_maps_baseline/m_Ti6Al4V_p_0_480_20_v_0.0_0.1_0.1-*
- config_name: process_maps_baseline_test
data_files:
- split: m_Ti6Al4V_p_0_480_20_v_0.0_0.1_0.1
path: process_maps_baseline_test/m_Ti6Al4V_p_0_480_20_v_0.0_0.1_0.1-*
- split: m_Ti6Al4V_p_0_480_20_v_0.0_2.9_0.1
path: process_maps_baseline_test/m_Ti6Al4V_p_0_480_20_v_0.0_2.9_0.1-*
- config_name: process_maps_baseline_test_2
data_files:
- split: m_IN625_p_0_480_20_v_0.0_2.9_0.1
path: process_maps_baseline_test_2/m_IN625_p_0_480_20_v_0.0_2.9_0.1-*
- config_name: process_maps_baseline_test_3
data_files:
- split: m_IN625_p_0_480_20_v_0.0_2.9_0.1
path: process_maps_baseline_test_3/m_IN625_p_0_480_20_v_0.0_2.9_0.1-*
- config_name: process_maps_test
data_files:
- split: m_Ti6Al4V_p_0_480_20_v_0.0_0.1_0.1
path: process_maps_test/m_Ti6Al4V_p_0_480_20_v_0.0_0.1_0.1-*
- split: m_Ti6Al4V_p_0_480_20_v_0.0_2.9_0.1
path: process_maps_test/m_Ti6Al4V_p_0_480_20_v_0.0_2.9_0.1-*
- config_name: simulations
data_files:
- split: m_Ti64_p_0_v_0.0
path: simulations/m_Ti64_p_0_v_0.0-*
- split: m_Ti64_p_20_v_0.0
path: simulations/m_Ti64_p_20_v_0.0-*
- split: m_Ti64_p_0_v_0.1
path: simulations/m_Ti64_p_0_v_0.1-*
- split: m_Ti64_p_0_v_0.2
path: simulations/m_Ti64_p_0_v_0.2-*
- split: m_Ti64_p_0_v_0.3
path: simulations/m_Ti64_p_0_v_0.3-*
- split: m_Ti64_p_0_v_0.4
path: simulations/m_Ti64_p_0_v_0.4-*
- split: m_Ti64_p_0_v_0.5
path: simulations/m_Ti64_p_0_v_0.5-*
- split: m_Ti64_p_0_v_0.6
path: simulations/m_Ti64_p_0_v_0.6-*
- split: m_Ti64_p_0_v_0.7
path: simulations/m_Ti64_p_0_v_0.7-*
- split: m_Ti64_p_0_v_0.8
path: simulations/m_Ti64_p_0_v_0.8-*
- split: m_Ti64_p_0_v_0.9
path: simulations/m_Ti64_p_0_v_0.9-*
- split: m_Ti64_p_0_v_1.0
path: simulations/m_Ti64_p_0_v_1.0-*
- split: m_Ti64_p_0_v_1.1
path: simulations/m_Ti64_p_0_v_1.1-*
- split: m_Ti64_p_0_v_1.2
path: simulations/m_Ti64_p_0_v_1.2-*
- split: m_Ti64_p_0_v_1.3
path: simulations/m_Ti64_p_0_v_1.3-*
- split: m_Ti64_p_0_v_1.4
path: simulations/m_Ti64_p_0_v_1.4-*
- split: m_Ti64_p_0_v_1.5
path: simulations/m_Ti64_p_0_v_1.5-*
- split: m_Ti64_p_0_v_1.6
path: simulations/m_Ti64_p_0_v_1.6-*
- split: m_Ti64_p_0_v_1.7
path: simulations/m_Ti64_p_0_v_1.7-*
- split: m_Ti64_p_0_v_1.8
path: simulations/m_Ti64_p_0_v_1.8-*
- split: m_Ti64_p_0_v_1.9
path: simulations/m_Ti64_p_0_v_1.9-*
- split: m_Ti64_p_0_v_2.0
path: simulations/m_Ti64_p_0_v_2.0-*
- split: m_Ti64_p_0_v_2.1
path: simulations/m_Ti64_p_0_v_2.1-*
- split: m_Ti64_p_0_v_2.2
path: simulations/m_Ti64_p_0_v_2.2-*
- split: m_Ti64_p_0_v_2.3
path: simulations/m_Ti64_p_0_v_2.3-*
- split: m_Ti64_p_0_v_2.4
path: simulations/m_Ti64_p_0_v_2.4-*
- split: m_Ti64_p_0_v_2.5
path: simulations/m_Ti64_p_0_v_2.5-*
- split: m_Ti64_p_0_v_2.6
path: simulations/m_Ti64_p_0_v_2.6-*
- split: m_Ti64_p_0_v_2.7
path: simulations/m_Ti64_p_0_v_2.7-*
- split: m_Ti64_p_0_v_2.8
path: simulations/m_Ti64_p_0_v_2.8-*
- split: m_Ti64_p_0_v_2.9
path: simulations/m_Ti64_p_0_v_2.9-*
- split: m_Ti64_p_20_v_0.1
path: simulations/m_Ti64_p_20_v_0.1-*
- split: m_Ti64_p_20_v_0.2
path: simulations/m_Ti64_p_20_v_0.2-*
- split: m_Ti64_p_20_v_0.3
path: simulations/m_Ti64_p_20_v_0.3-*
- split: m_Ti64_p_20_v_0.4
path: simulations/m_Ti64_p_20_v_0.4-*
- split: m_Ti64_p_20_v_0.5
path: simulations/m_Ti64_p_20_v_0.5-*
- split: m_Ti64_p_20_v_0.6
path: simulations/m_Ti64_p_20_v_0.6-*
- split: m_Ti64_p_20_v_0.7
path: simulations/m_Ti64_p_20_v_0.7-*
- split: m_Ti64_p_20_v_0.8
path: simulations/m_Ti64_p_20_v_0.8-*
- split: m_Ti64_p_20_v_0.9
path: simulations/m_Ti64_p_20_v_0.9-*
- split: m_Ti64_p_20_v_1.0
path: simulations/m_Ti64_p_20_v_1.0-*
- split: m_Ti64_p_20_v_1.1
path: simulations/m_Ti64_p_20_v_1.1-*
- split: m_Ti64_p_20_v_1.2
path: simulations/m_Ti64_p_20_v_1.2-*
- split: m_Ti64_p_20_v_1.3
path: simulations/m_Ti64_p_20_v_1.3-*
- split: m_Ti64_p_20_v_1.4
path: simulations/m_Ti64_p_20_v_1.4-*
- split: m_Ti64_p_20_v_1.5
path: simulations/m_Ti64_p_20_v_1.5-*
- split: m_Ti64_p_20_v_1.6
path: simulations/m_Ti64_p_20_v_1.6-*
- split: m_Ti64_p_20_v_1.7
path: simulations/m_Ti64_p_20_v_1.7-*
- split: m_Ti64_p_20_v_1.8
path: simulations/m_Ti64_p_20_v_1.8-*
- split: m_Ti64_p_20_v_1.9
path: simulations/m_Ti64_p_20_v_1.9-*
- split: m_Ti64_p_20_v_2.0
path: simulations/m_Ti64_p_20_v_2.0-*
- split: m_Ti64_p_20_v_2.1
path: simulations/m_Ti64_p_20_v_2.1-*
- split: m_Ti64_p_20_v_2.2
path: simulations/m_Ti64_p_20_v_2.2-*
- split: m_Ti64_p_20_v_2.3
path: simulations/m_Ti64_p_20_v_2.3-*
- split: m_Ti64_p_20_v_2.4
path: simulations/m_Ti64_p_20_v_2.4-*
- split: m_Ti64_p_20_v_2.5
path: simulations/m_Ti64_p_20_v_2.5-*
- split: m_Ti64_p_20_v_2.6
path: simulations/m_Ti64_p_20_v_2.6-*
- split: m_Ti64_p_20_v_2.7
path: simulations/m_Ti64_p_20_v_2.7-*
- split: m_Ti64_p_20_v_2.8
path: simulations/m_Ti64_p_20_v_2.8-*
- split: m_Ti64_p_20_v_2.9
path: simulations/m_Ti64_p_20_v_2.9-*
- split: m_Ti64_p_40_v_0.0
path: simulations/m_Ti64_p_40_v_0.0-*
- split: m_Ti64_p_40_v_0.1
path: simulations/m_Ti64_p_40_v_0.1-*
- split: m_Ti64_p_40_v_0.2
path: simulations/m_Ti64_p_40_v_0.2-*
- split: m_Ti64_p_40_v_0.3
path: simulations/m_Ti64_p_40_v_0.3-*
- split: m_Ti64_p_40_v_0.4
path: simulations/m_Ti64_p_40_v_0.4-*
- split: m_Ti64_p_40_v_0.5
path: simulations/m_Ti64_p_40_v_0.5-*
- split: m_Ti64_p_40_v_0.6
path: simulations/m_Ti64_p_40_v_0.6-*
- split: m_Ti64_p_40_v_0.7
path: simulations/m_Ti64_p_40_v_0.7-*
- split: m_Ti64_p_40_v_0.8
path: simulations/m_Ti64_p_40_v_0.8-*
- split: m_Ti64_p_40_v_0.9
path: simulations/m_Ti64_p_40_v_0.9-*
- split: m_Ti64_p_40_v_1.0
path: simulations/m_Ti64_p_40_v_1.0-*
- split: m_Ti64_p_40_v_1.1
path: simulations/m_Ti64_p_40_v_1.1-*
- split: m_Ti64_p_40_v_1.2
path: simulations/m_Ti64_p_40_v_1.2-*
- split: m_Ti64_p_40_v_1.3
path: simulations/m_Ti64_p_40_v_1.3-*
- split: m_Ti64_p_40_v_1.4
path: simulations/m_Ti64_p_40_v_1.4-*
- split: m_Ti64_p_40_v_1.5
path: simulations/m_Ti64_p_40_v_1.5-*
- split: m_Ti64_p_40_v_1.6
path: simulations/m_Ti64_p_40_v_1.6-*
- split: m_Ti64_p_40_v_1.7
path: simulations/m_Ti64_p_40_v_1.7-*
- split: m_Ti64_p_40_v_1.8
path: simulations/m_Ti64_p_40_v_1.8-*
- split: m_Ti64_p_40_v_1.9
path: simulations/m_Ti64_p_40_v_1.9-*
- split: m_Ti64_p_40_v_2.0
path: simulations/m_Ti64_p_40_v_2.0-*
- split: m_Ti64_p_40_v_2.1
path: simulations/m_Ti64_p_40_v_2.1-*
- split: m_Ti64_p_40_v_2.2
path: simulations/m_Ti64_p_40_v_2.2-*
- split: m_Ti64_p_40_v_2.3
path: simulations/m_Ti64_p_40_v_2.3-*
- split: m_Ti64_p_40_v_2.4
path: simulations/m_Ti64_p_40_v_2.4-*
- split: m_Ti64_p_40_v_2.5
path: simulations/m_Ti64_p_40_v_2.5-*
- split: m_Ti64_p_40_v_2.6
path: simulations/m_Ti64_p_40_v_2.6-*
- split: m_Ti64_p_40_v_2.7
path: simulations/m_Ti64_p_40_v_2.7-*
- split: m_Ti64_p_40_v_2.8
path: simulations/m_Ti64_p_40_v_2.8-*
- split: m_Ti64_p_40_v_2.9
path: simulations/m_Ti64_p_40_v_2.9-*
- split: m_Ti64_p_60_v_0.0
path: simulations/m_Ti64_p_60_v_0.0-*
- split: m_Ti64_p_60_v_0.1
path: simulations/m_Ti64_p_60_v_0.1-*
- split: m_Ti64_p_60_v_0.2
path: simulations/m_Ti64_p_60_v_0.2-*
- split: m_Ti64_p_60_v_0.3
path: simulations/m_Ti64_p_60_v_0.3-*
- split: m_Ti64_p_60_v_0.4
path: simulations/m_Ti64_p_60_v_0.4-*
- split: m_Ti64_p_60_v_0.5
path: simulations/m_Ti64_p_60_v_0.5-*
- split: m_Ti64_p_60_v_0.6
path: simulations/m_Ti64_p_60_v_0.6-*
- split: m_Ti64_p_60_v_0.7
path: simulations/m_Ti64_p_60_v_0.7-*
- split: m_Ti64_p_60_v_0.8
path: simulations/m_Ti64_p_60_v_0.8-*
- split: m_Ti64_p_60_v_0.9
path: simulations/m_Ti64_p_60_v_0.9-*
- split: m_Ti64_p_60_v_1.0
path: simulations/m_Ti64_p_60_v_1.0-*
- split: m_Ti64_p_60_v_1.1
path: simulations/m_Ti64_p_60_v_1.1-*
- split: m_Ti64_p_60_v_1.2
path: simulations/m_Ti64_p_60_v_1.2-*
- split: m_Ti64_p_60_v_1.3
path: simulations/m_Ti64_p_60_v_1.3-*
- split: m_Ti64_p_60_v_1.4
path: simulations/m_Ti64_p_60_v_1.4-*
- split: m_Ti64_p_60_v_1.5
path: simulations/m_Ti64_p_60_v_1.5-*
- split: m_Ti64_p_60_v_1.6
path: simulations/m_Ti64_p_60_v_1.6-*
- split: m_Ti64_p_60_v_1.7
path: simulations/m_Ti64_p_60_v_1.7-*
- split: m_Ti64_p_60_v_1.8
path: simulations/m_Ti64_p_60_v_1.8-*
- split: m_Ti64_p_60_v_1.9
path: simulations/m_Ti64_p_60_v_1.9-*
- split: m_Ti64_p_60_v_2.0
path: simulations/m_Ti64_p_60_v_2.0-*
- split: m_Ti64_p_60_v_2.1
path: simulations/m_Ti64_p_60_v_2.1-*
- split: m_Ti64_p_60_v_2.2
path: simulations/m_Ti64_p_60_v_2.2-*
- split: m_Ti64_p_60_v_2.3
path: simulations/m_Ti64_p_60_v_2.3-*
- split: m_Ti64_p_60_v_2.4
path: simulations/m_Ti64_p_60_v_2.4-*
- split: m_Ti64_p_60_v_2.5
path: simulations/m_Ti64_p_60_v_2.5-*
- split: m_Ti64_p_60_v_2.6
path: simulations/m_Ti64_p_60_v_2.6-*
- split: m_Ti64_p_60_v_2.7
path: simulations/m_Ti64_p_60_v_2.7-*
- split: m_Ti64_p_60_v_2.8
path: simulations/m_Ti64_p_60_v_2.8-*
- split: m_Ti64_p_60_v_2.9
path: simulations/m_Ti64_p_60_v_2.9-*
- split: m_Ti64_p_80_v_0.0
path: simulations/m_Ti64_p_80_v_0.0-*
- split: m_Ti64_p_80_v_0.1
path: simulations/m_Ti64_p_80_v_0.1-*
- split: m_Ti64_p_80_v_0.2
path: simulations/m_Ti64_p_80_v_0.2-*
- split: m_Ti64_p_80_v_0.3
path: simulations/m_Ti64_p_80_v_0.3-*
- split: m_Ti64_p_80_v_0.4
path: simulations/m_Ti64_p_80_v_0.4-*
- split: m_Ti64_p_80_v_0.5
path: simulations/m_Ti64_p_80_v_0.5-*
- split: m_Ti64_p_80_v_0.6
path: simulations/m_Ti64_p_80_v_0.6-*
- split: m_Ti64_p_80_v_0.7
path: simulations/m_Ti64_p_80_v_0.7-*
- split: m_Ti64_p_80_v_0.8
path: simulations/m_Ti64_p_80_v_0.8-*
- split: m_Ti64_p_80_v_0.9
path: simulations/m_Ti64_p_80_v_0.9-*
- split: m_Ti64_p_80_v_1.0
path: simulations/m_Ti64_p_80_v_1.0-*
- split: m_Ti64_p_80_v_1.1
path: simulations/m_Ti64_p_80_v_1.1-*
- split: m_Ti64_p_80_v_1.2
path: simulations/m_Ti64_p_80_v_1.2-*
- split: m_Ti64_p_80_v_1.3
path: simulations/m_Ti64_p_80_v_1.3-*
- split: m_Ti64_p_80_v_1.4
path: simulations/m_Ti64_p_80_v_1.4-*
- split: m_Ti64_p_80_v_1.5
path: simulations/m_Ti64_p_80_v_1.5-*
- split: m_Ti64_p_80_v_1.6
path: simulations/m_Ti64_p_80_v_1.6-*
- split: m_Ti64_p_80_v_1.7
path: simulations/m_Ti64_p_80_v_1.7-*
- split: m_Ti64_p_80_v_1.8
path: simulations/m_Ti64_p_80_v_1.8-*
- split: m_Ti64_p_80_v_1.9
path: simulations/m_Ti64_p_80_v_1.9-*
- split: m_Ti64_p_80_v_2.0
path: simulations/m_Ti64_p_80_v_2.0-*
- split: m_Ti64_p_80_v_2.1
path: simulations/m_Ti64_p_80_v_2.1-*
- split: m_Ti64_p_80_v_2.2
path: simulations/m_Ti64_p_80_v_2.2-*
- split: m_Ti64_p_80_v_2.3
path: simulations/m_Ti64_p_80_v_2.3-*