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download_size: 4445609703
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configs:
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data_files:
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path: baseline/m_Ti6Al4V_v_0.0_0.1_0.1-*
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path: baseline/m_Ti6Al4V_v_0.0_2.9_0.1-*
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data_files:
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path: process_maps/m_Ti64_p_0_20_20_v_0.0_0.0_0.1-*
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path: process_maps/m_Ti64_p_0_480_20_v_0.0_2.9_0.1-*
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path: process_maps_baseline_test/m_Ti6Al4V_p_0_480_20_v_0.0_2.9_0.1-*
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path: process_maps_baseline_test_2/m_IN625_p_0_480_20_v_0.0_2.9_0.1-*
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path: process_maps_baseline_test_3/m_IN625_p_0_480_20_v_0.0_2.9_0.1-*
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data_files:
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path: process_maps_test/m_Ti6Al4V_p_0_480_20_v_0.0_0.1_0.1-*
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path: process_maps_test/m_Ti6Al4V_p_0_480_20_v_0.0_2.9_0.1-*
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path: simulations/m_Ti64_p_20_v_0.0-*
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path: simulations/m_Ti64_p_0_v_0.1-*
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path: simulations/m_Ti64_p_0_v_0.2-*
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path: simulations/m_Ti64_p_0_v_0.3-*
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path: simulations/m_Ti64_p_0_v_0.4-*
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path: simulations/m_Ti64_p_0_v_0.5-*
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path: simulations/m_Ti64_p_0_v_0.6-*
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path: simulations/m_Ti64_p_0_v_0.7-*
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path: simulations/m_Ti64_p_0_v_0.8-*
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path: simulations/m_Ti64_p_0_v_0.9-*
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path: simulations/m_Ti64_p_0_v_1.0-*
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path: simulations/m_Ti64_p_0_v_1.1-*
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path: simulations/m_Ti64_p_0_v_1.2-*
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path: simulations/m_Ti64_p_0_v_1.3-*
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path: simulations/m_Ti64_p_0_v_1.4-*
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path: simulations/m_Ti64_p_0_v_1.5-*
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path: simulations/m_Ti64_p_0_v_1.6-*
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path: simulations/m_Ti64_p_0_v_1.7-*
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path: simulations/m_Ti64_p_0_v_1.9-*
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path: simulations/m_Ti64_p_0_v_2.0-*
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path: simulations/m_Ti64_p_0_v_2.1-*
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path: simulations/m_Ti64_p_0_v_2.2-*
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path: simulations/m_Ti64_p_0_v_2.3-*
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path: simulations/m_Ti64_p_0_v_2.4-*
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path: simulations/m_Ti64_p_0_v_2.5-*
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path: simulations/m_Ti64_p_0_v_2.6-*
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path: simulations/m_Ti64_p_20_v_0.1-*
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path: simulations/m_Ti64_p_20_v_0.2-*
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path: simulations/m_Ti64_p_20_v_0.3-*
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path: simulations/m_Ti64_p_20_v_0.4-*
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path: simulations/m_Ti64_p_20_v_0.5-*
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path: simulations/m_Ti64_p_20_v_0.6-*
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path: simulations/m_Ti64_p_20_v_0.7-*
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path: simulations/m_Ti64_p_20_v_0.8-*
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path: simulations/m_Ti64_p_20_v_0.9-*
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path: simulations/m_Ti64_p_20_v_1.0-*
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path: simulations/m_Ti64_p_20_v_1.1-*
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path: simulations/m_Ti64_p_20_v_1.2-*
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path: simulations/m_Ti64_p_20_v_1.3-*
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path: simulations/m_Ti64_p_20_v_1.4-*
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path: simulations/m_Ti64_p_20_v_1.5-*
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path: simulations/m_Ti64_p_20_v_1.6-*
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path: simulations/m_Ti64_p_20_v_1.7-*
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path: simulations/m_Ti64_p_20_v_1.8-*
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path: simulations/m_Ti64_p_20_v_1.9-*
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path: simulations/m_Ti64_p_20_v_2.0-*
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path: simulations/m_Ti64_p_20_v_2.1-*
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path: simulations/m_Ti64_p_20_v_2.2-*
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path: simulations/m_Ti64_p_20_v_2.3-*
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path: simulations/m_Ti64_p_20_v_2.4-*
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path: simulations/m_Ti64_p_20_v_2.5-*
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path: simulations/m_Ti64_p_20_v_2.6-*
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path: simulations/m_Ti64_p_20_v_2.7-*
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path: simulations/m_Ti64_p_20_v_2.8-*
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path: simulations/m_Ti64_p_40_v_0.1-*
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path: simulations/m_Ti64_p_40_v_0.2-*
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path: simulations/m_Ti64_p_40_v_0.3-*
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path: simulations/m_Ti64_p_40_v_0.4-*
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path: simulations/m_Ti64_p_40_v_0.5-*
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path: simulations/m_Ti64_p_40_v_0.6-*
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path: simulations/m_Ti64_p_40_v_0.7-*
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path: simulations/m_Ti64_p_40_v_1.6-*
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path: simulations/m_Ti64_p_40_v_2.1-*
- split: m_Ti64_p_40_v_2.2
path: simulations/m_Ti64_p_40_v_2.2-*
- split: m_Ti64_p_40_v_2.3
path: simulations/m_Ti64_p_40_v_2.3-*
- split: m_Ti64_p_40_v_2.4
path: simulations/m_Ti64_p_40_v_2.4-*
- split: m_Ti64_p_40_v_2.5
path: simulations/m_Ti64_p_40_v_2.5-*
- split: m_Ti64_p_40_v_2.6
path: simulations/m_Ti64_p_40_v_2.6-*
- split: m_Ti64_p_40_v_2.7
path: simulations/m_Ti64_p_40_v_2.7-*
- split: m_Ti64_p_40_v_2.8
path: simulations/m_Ti64_p_40_v_2.8-*
- split: m_Ti64_p_40_v_2.9
path: simulations/m_Ti64_p_40_v_2.9-*
- split: m_Ti64_p_60_v_0.0
path: simulations/m_Ti64_p_60_v_0.0-*
- split: m_Ti64_p_60_v_0.1
path: simulations/m_Ti64_p_60_v_0.1-*
- split: m_Ti64_p_60_v_0.2
path: simulations/m_Ti64_p_60_v_0.2-*
- split: m_Ti64_p_60_v_0.3
path: simulations/m_Ti64_p_60_v_0.3-*
- split: m_Ti64_p_60_v_0.4
path: simulations/m_Ti64_p_60_v_0.4-*
- split: m_Ti64_p_60_v_0.5
path: simulations/m_Ti64_p_60_v_0.5-*
- split: m_Ti64_p_60_v_0.6
path: simulations/m_Ti64_p_60_v_0.6-*
- split: m_Ti64_p_60_v_0.7
path: simulations/m_Ti64_p_60_v_0.7-*
- split: m_Ti64_p_60_v_0.8
path: simulations/m_Ti64_p_60_v_0.8-*
- split: m_Ti64_p_60_v_0.9
path: simulations/m_Ti64_p_60_v_0.9-*
- split: m_Ti64_p_60_v_1.0
path: simulations/m_Ti64_p_60_v_1.0-*
- split: m_Ti64_p_60_v_1.1
path: simulations/m_Ti64_p_60_v_1.1-*
- split: m_Ti64_p_60_v_1.2
path: simulations/m_Ti64_p_60_v_1.2-*
- split: m_Ti64_p_60_v_1.3
path: simulations/m_Ti64_p_60_v_1.3-*
- split: m_Ti64_p_60_v_1.4
path: simulations/m_Ti64_p_60_v_1.4-*
- split: m_Ti64_p_60_v_1.5
path: simulations/m_Ti64_p_60_v_1.5-*
- split: m_Ti64_p_60_v_1.6
path: simulations/m_Ti64_p_60_v_1.6-*
- split: m_Ti64_p_60_v_1.7
path: simulations/m_Ti64_p_60_v_1.7-*
- split: m_Ti64_p_60_v_1.8
path: simulations/m_Ti64_p_60_v_1.8-*
- split: m_Ti64_p_60_v_1.9
path: simulations/m_Ti64_p_60_v_1.9-*
- split: m_Ti64_p_60_v_2.0
path: simulations/m_Ti64_p_60_v_2.0-*
- split: m_Ti64_p_60_v_2.1
path: simulations/m_Ti64_p_60_v_2.1-*
- split: m_Ti64_p_60_v_2.2
path: simulations/m_Ti64_p_60_v_2.2-*
- split: m_Ti64_p_60_v_2.3
path: simulations/m_Ti64_p_60_v_2.3-*
- split: m_Ti64_p_60_v_2.4
path: simulations/m_Ti64_p_60_v_2.4-*
- split: m_Ti64_p_60_v_2.5
path: simulations/m_Ti64_p_60_v_2.5-*
- split: m_Ti64_p_60_v_2.6
path: simulations/m_Ti64_p_60_v_2.6-*
- split: m_Ti64_p_60_v_2.7
path: simulations/m_Ti64_p_60_v_2.7-*
- split: m_Ti64_p_60_v_2.8
path: simulations/m_Ti64_p_60_v_2.8-*
- split: m_Ti64_p_60_v_2.9
path: simulations/m_Ti64_p_60_v_2.9-*
- split: m_Ti64_p_80_v_0.0
path: simulations/m_Ti64_p_80_v_0.0-*
- split: m_Ti64_p_80_v_0.1
path: simulations/m_Ti64_p_80_v_0.1-*
- split: m_Ti64_p_80_v_0.2
path: simulations/m_Ti64_p_80_v_0.2-*
- split: m_Ti64_p_80_v_0.3
path: simulations/m_Ti64_p_80_v_0.3-*
- split: m_Ti64_p_80_v_0.4
path: simulations/m_Ti64_p_80_v_0.4-*
- split: m_Ti64_p_80_v_0.5
path: simulations/m_Ti64_p_80_v_0.5-*
- split: m_Ti64_p_80_v_0.6
path: simulations/m_Ti64_p_80_v_0.6-*
- split: m_Ti64_p_80_v_0.7
path: simulations/m_Ti64_p_80_v_0.7-*
- split: m_Ti64_p_80_v_0.8
path: simulations/m_Ti64_p_80_v_0.8-*
- split: m_Ti64_p_80_v_0.9
path: simulations/m_Ti64_p_80_v_0.9-*
- split: m_Ti64_p_80_v_1.0
path: simulations/m_Ti64_p_80_v_1.0-*
- split: m_Ti64_p_80_v_1.1
path: simulations/m_Ti64_p_80_v_1.1-*
- split: m_Ti64_p_80_v_1.2
path: simulations/m_Ti64_p_80_v_1.2-*
- split: m_Ti64_p_80_v_1.3
path: simulations/m_Ti64_p_80_v_1.3-*
- split: m_Ti64_p_80_v_1.4
path: simulations/m_Ti64_p_80_v_1.4-*
- split: m_Ti64_p_80_v_1.5
path: simulations/m_Ti64_p_80_v_1.5-*
- split: m_Ti64_p_80_v_1.6
path: simulations/m_Ti64_p_80_v_1.6-*
- split: m_Ti64_p_80_v_1.7
path: simulations/m_Ti64_p_80_v_1.7-*
- split: m_Ti64_p_80_v_1.8
path: simulations/m_Ti64_p_80_v_1.8-*
- split: m_Ti64_p_80_v_1.9
path: simulations/m_Ti64_p_80_v_1.9-*
- split: m_Ti64_p_80_v_2.0
path: simulations/m_Ti64_p_80_v_2.0-*
- split: m_Ti64_p_80_v_2.1
path: simulations/m_Ti64_p_80_v_2.1-*
- split: m_Ti64_p_80_v_2.2
path: simulations/m_Ti64_p_80_v_2.2-*
- split: m_Ti64_p_80_v_2.3
path: simulations/m_Ti64_p_80_v_2.3-*
---
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