code
stringlengths 35
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| score
float64 6.5
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|
|---|---|
module one_bit_comparator (
bit_a,
bit_b,
less_in,
equal_in,
greater_in,
less_out,
equal_out,
greater_out
);
//Input Bits
input bit_a;
input bit_b;
//Input less, equal or greater bits till now
input less_in;
input equal_in;
input greater_in;
//Output less, equal or greater bits after this comparison
output wire less_out;
output wire equal_out;
output wire greater_out;
// Combinational logic for less_out, equal_out, greater_out
assign less_out = ((~bit_a) & bit_b) & (equal_in) | (less_in & (~equal_in));
assign equal_out = (~(bit_a ^ bit_b)) & equal_in;
assign greater_out = ((bit_a & (~bit_b)) & (equal_in)) | (greater_in & (~equal_in));
endmodule
| 8.270443
|
module three_bit_comparator (
A,
B,
less
);
input [2:0] A;
input [2:0] B;
output wire less, equal, greater;
wire lin, ein, gin;
wire [7:0] less_3;
wire [7:0] equal_3;
wire [7:0] greater_3;
assign lin = 0;
assign ein = 1;
assign gin = 0;
// One bit comparator for MSB (3rd) position
one_bit_comparator c2 (
A[2],
B[2],
lin,
ein,
gin,
less_3[2],
equal_3[2],
greater_3[2]
);
one_bit_comparator c1 (
A[1],
B[1],
less_3[2],
equal_3[2],
greater_3[2],
less_3[1],
equal_3[1],
greater_3[1]
);
one_bit_comparator c0 (
A[0],
B[0],
less_3[1],
equal_3[1],
greater_3[1],
less_3[0],
equal_3[0],
greater_3[0]
);
assign less = less_3[0];
endmodule
| 8.281171
|
module top;
reg [2:0] Input1;
reg [2:0] Input2;
reg [2:0] Input3;
reg [2:0] Input4;
wire [1:0] Output;
compute_index COMPUTE_INDEX (
Input1,
Input2,
Input3,
Input4,
Output
);
always @(Input1 or Input2 or Input3 or Input4 or Output) begin
$display("time=%g: Input1 = %b, Input2 = %b, Input3 = %b, Input4 = %b, Output = %d", $time,
Input1, Input2, Input3, Input4, Output);
end
initial begin
#10 $finish;
end
initial begin
Input1 = 3'b110;
Input2 = 3'b001;
Input3 = 3'b001;
Input4 = 3'b001;
#1 $display("\n");
Input1 = 3'b110;
Input2 = 3'b001;
Input3 = 3'b111;
Input4 = 3'b010;
#1 $display("\n");
Input1 = 3'b111;
Input2 = 3'b011;
Input3 = 3'b010;
Input4 = 3'b110;
#1 $display("\n");
Input1 = 3'b110;
Input2 = 3'b001;
Input3 = 3'b111;
Input4 = 3'b010;
#1 $display("\n");
Input1 = 3'b001;
Input2 = 3'b111;
Input3 = 3'b010;
Input4 = 3'b110;
#1 $display("\n");
Input1 = 3'b110;
Input2 = 3'b001;
Input3 = 3'b111;
Input4 = 3'b010;
#1 $display("\n");
Input1 = 3'b110;
Input2 = 3'b111;
Input3 = 3'b010;
Input4 = 3'b000;
#1 $display("\n");
Input1 = 3'b000;
Input2 = 3'b001;
Input3 = 3'b111;
Input4 = 3'b010;
#1 $display("\n");
Input1 = 3'b001;
Input2 = 3'b111;
Input3 = 3'b000;
Input4 = 3'b110;
#1 $display("\n");
Input1 = 3'b101;
Input2 = 3'b001;
Input3 = 3'b111;
Input4 = 3'b010;
end
endmodule
| 7.327079
|
module test();
reg clk;
// 设置时钟
initial begin
clk = 1'b1;
forever begin
#5 clk=~clk;
end
end
reg [7:0] mem[0:65535];
reg [7:0] ans[0:65535];
reg [255:0] msg=0;
reg [63:0] pubk="hardware";
reg [21:0] prik=22'b1101001110000110010001;
wire [0:0] out_key;
wire [0:0] init_flag;
reg [0:0] flag=1'b0;
integer f,file,cnt=0,plane=0;
cipher uut(
.clk(clk),
.pubk(pubk),
.prik(prik),
.out_key(out_key),
.flag(flag),
.init_flag(init_flag));
initial begin
$readmemh("output.txt",mem);
file=$fopen("decrypt.txt","w");
end
always @(posedge clk)
begin
if(init_flag==0) begin
flag=1;
end
if(flag==1&&cnt<65536) begin
ans[cnt][plane]=mem[cnt][plane]^out_key;
<<<<<<< HEAD:exp2/a5_1_decrypt_tb.v
// if(cnt==0) begin
// $display("%b,%b",mem[cnt][plane],out_key);
// end
=======
>>>>>>> blackhole:exp2/verilog/a5_1_decrypt_tb.v
plane=plane+1;
if(plane==8) begin
cnt=cnt+1;
plane=0;
end
end
if(cnt==65536) begin
for(f=0;f<65536;f=f+1) begin
$fwrite(file,"%02x\n",ans[f]);
end
$fclose(file);
$display("finished.");
$display("Total time=%0t",$time);
<<<<<<< HEAD:exp2/a5_1_decrypt_tb.v
// $display("%b",ans[0]);
// $display("%b",ans[1]);
=======
>>>>>>> blackhole:exp2/verilog/a5_1_decrypt_tb.v
$stop;
end
end
endmodule
| 6.635409
|
module test();
reg clk;
// 设置时钟
initial begin
clk = 1'b1;
forever begin
#5 clk=~clk;
end
end
reg [7:0] mem[0:65535];
reg [7:0] ans[0:65535];
reg [63:0] pubk="hardware";
reg [21:0] prik=22'b1101001110000110010001;
wire [0:0] out_key;
wire [0:0] init_flag;
reg [0:0] flag=1'b0;
integer f,file,cnt=0,plane=0;
cipher uut(
.clk(clk),
.pubk(pubk),
.prik(prik),
.out_key(out_key),
.flag(flag),
.init_flag(init_flag));
initial begin
$readmemh("testfile.txt",mem);
file=$fopen("output.txt","w");
end
always @(posedge clk)
begin
if(init_flag==0) begin
flag=1;
end
if(flag==1&&cnt<65536) begin
ans[cnt][plane]=mem[cnt][plane]^out_key;
<<<<<<< HEAD:exp2/a5_1_tb.v
// if(cnt==0) begin
// $display("%b,%b",mem[cnt][plane],out_key);
// end
=======
>>>>>>> blackhole:exp2/verilog/a5_1_tb.v
plane=plane+1;
if(plane==8) begin
cnt=cnt+1;
plane=0;
end
end
if(cnt==65536) begin
for(f=0;f<65536;f=f+1) begin
$fwrite(file,"%02x\n",ans[f]);
end
$fclose(file);
$display("finished.");
$display("Total time=%0t",$time);
<<<<<<< HEAD:exp2/a5_1_tb.v
// $display("%b",ans[0]);
// $display("%b",ans[1]);
=======
>>>>>>> blackhole:exp2/verilog/a5_1_tb.v
$stop;
end
end
endmodule
| 6.635409
|
module decoder (
instruct,
clk,
read_address1,
read_address2,
write_address,
opcode
);
input [33:0] instruct;
input clk;
output wire [4:0] read_address1, read_address2, write_address;
output wire [2:0] opcode;
assign opcode = instruct[33:31]; // opcode needed to decode the operation
assign read_address1 = instruct[30:26]; // needed to decode register to read from
assign read_address2 = instruct[25:21]; // needed to decode register to read from
assign write_address = instruct[20:16]; // needed to decode register to write to
endmodule
| 7.018254
|
module one_bit_addr (
a,
b,
cin,
opcode,
sum,
carry
);
input a, b, cin, opcode;
output sum, carry;
wire sum;
wire carry;
assign sum = a ^ (b ^ opcode) ^ cin;
assign carry = ((a & (b ^ opcode)) | ((b ^ opcode) & cin) | (a & cin));
endmodule
| 6.810869
|
module for one bit adder/subtracter
module one_bit_adder_subtracter(a, b, cin, opcode, sum, carry);
input a,b,cin,opcode; // a,b -> operands, cin -> carry in, opcode -> operation code
output wire sum, carry; // sum -> a \operation b, carry out
wire b_dummy; // additional dummy variable stores b^opcode
assign b_dummy = b^opcode;
assign sum = a^b_dummy^cin;
assign carry = (a&b_dummy) | (b_dummy&cin) | (cin&a);
endmodule
| 7.558657
|
module register_file (
clk,
valid,
read_addr_1,
read_addr_2,
write_addr,
write_data,
read_1,
read_2
);
input clk; // Clock
input [2:0] valid; // Indicator for which read/write operation to perform
input [4:0] read_addr_1; // 5 bit 1st source register address
input [4:0] read_addr_2; // 5 bit 2nd source register address
input [4:0] write_addr; // 5 bit destination register address
input [15:0] write_data; // 16 bit data to write in a register
output reg [15:0] read_1; // 16 bit data read from the 1st register
output reg [15:0] read_2; // 16 bit data read from the 2nd register
reg [15:0] REGISTER[0:31]; //32 16-bit register file
reg read_cycles_counter; //Register to simulate read delay independent of clock
reg write_cycles_counter; //Register to simulate write delay independent of clock
initial // Initialisation of register file
begin
read_cycles_counter = 2'b0;
write_cycles_counter = 2'b0;
REGISTER[0] = 16'b0;
REGISTER[1] = 16'b0;
REGISTER[2] = 16'b0;
REGISTER[3] = 16'b0;
REGISTER[4] = 16'b0;
REGISTER[5] = 16'b0;
REGISTER[6] = 16'b0;
REGISTER[7] = 16'b0;
REGISTER[8] = 16'b0;
REGISTER[9] = 16'b0;
REGISTER[10] = 16'b0;
REGISTER[11] = 16'b0;
REGISTER[12] = 16'b0;
REGISTER[13] = 16'b0;
REGISTER[14] = 16'b0;
REGISTER[15] = 16'b0;
REGISTER[16] = 16'b0;
REGISTER[17] = 16'b0;
REGISTER[18] = 16'b0;
REGISTER[19] = 16'b0;
REGISTER[20] = 16'b0;
REGISTER[21] = 16'b0;
REGISTER[22] = 16'b0;
REGISTER[23] = 16'b0;
REGISTER[24] = 16'b0;
REGISTER[25] = 16'b0;
REGISTER[26] = 16'b0;
REGISTER[27] = 16'b0;
REGISTER[28] = 16'b0;
REGISTER[29] = 16'b0;
REGISTER[30] = 16'b0;
REGISTER[31] = 16'b0;
end
always @(posedge clk) begin
if (read_cycles_counter == 1'b1) // complete by 2 clock cycles -- give read output
begin
read_1 <= REGISTER[read_addr_1];
read_2 <= REGISTER[read_addr_2];
read_cycles_counter <= 1'b0;
end
if (write_cycles_counter == 1'b1) // complete by 2 clock cycles -- give read output
begin
REGISTER[write_addr] <= write_data;
write_cycles_counter <= 1'b0;
end
if ( valid[0] || valid[1]) // If any read valid bit is active, set read_cycles bit
begin
read_cycles_counter <= 1'b1;
end
if (valid[2]) // If write valid bit is active, set write_cycles bit
begin
write_cycles_counter <= 1'b1;
end
end
endmodule
| 6.605344
|
module compute (
clk,
current_state,
command,
operand1,
operand2,
shift_amount,
result
);
input clk;
input [1:0] current_state;
input [2:0] command;
input [15:0] operand1;
input [15:0] operand2;
input [3:0] shift_amount;
output [15:0] result;
reg [15:0] result;
always @(posedge clk) begin
if (current_state == `STATE_COMPUTE) begin
if (command == 3'b101) begin
result <= operand1 + operand2;
end else if (command == 3'b110) begin
result <= operand1 - operand2;
end else if (command == 3'b111) begin
result <= operand1 << shift_amount;
end
end
end
endmodule
| 6.596023
|
module register_file (
clk,
current_state,
read1Addr,
read2Addr,
writeAddr,
writeValue,
read1Valid,
read2Valid,
writeValid,
read1Value,
read2Value
);
input clk;
input [1:0] current_state;
input [4:0] read1Addr;
input [4:0] read2Addr;
input [4:0] writeAddr;
input [15:0] writeValue;
input read1Valid;
input read2Valid;
input writeValid;
output [15:0] read1Value;
output [15:0] read2Value;
reg [15:0] read1Value;
reg [15:0] read2Value;
reg [15:0] regfile[0:31];
initial begin
regfile[0] = 0;
regfile[1] = 0;
regfile[2] = 0;
regfile[3] = 0;
regfile[4] = 0;
regfile[5] = 0;
regfile[6] = 0;
regfile[7] = 0;
regfile[8] = 0;
regfile[9] = 0;
regfile[10] = 0;
regfile[11] = 0;
regfile[12] = 0;
regfile[13] = 0;
regfile[14] = 0;
regfile[15] = 0;
regfile[16] = 0;
regfile[17] = 0;
regfile[18] = 0;
regfile[19] = 0;
regfile[20] = 0;
regfile[21] = 0;
regfile[22] = 0;
regfile[23] = 0;
regfile[24] = 0;
regfile[25] = 0;
regfile[26] = 0;
regfile[27] = 0;
regfile[28] = 0;
regfile[29] = 0;
regfile[30] = 0;
regfile[31] = 0;
end
always @(posedge clk) begin
if (current_state == `STATE_RF_RW) begin
if (read1Valid == 1) begin
read1Value <= regfile[read1Addr];
end
if (read2Valid == 1) begin
read2Value <= regfile[read2Addr];
end
if (writeValid == 1) begin
regfile[writeAddr] <= writeValue;
end
end else if (current_state == `STATE_RF_W) begin
regfile[writeAddr] <= writeValue;
end
end
endmodule
| 6.605344
|
module state_control(clk, command, done, current_state);
input clk;
input [2:0] command;
output done;
reg done = 0;
output [1:0] current_state;
reg [1:0] current_state;
reg [4:0] delay_count;
initial begin
current_state = `STATE_INPUT;
end
always @ (posedge clk) begin
if (current_state == `STATE_INPUT) begin
current_state <= `PROP_DELAY `STATE_RF_RW;
delay_count <= `PROP_DELAY 1;
done <= `PROP_DELAY 0;
end
else if ((current_state == `STATE_RF_RW) && (delay_count != `LATENCY_RF_READ)) begin
delay_count <= `PROP_DELAY delay_count + 1;
end
else if ((current_state == `STATE_RF_RW) && (delay_count == `LATENCY_RF_READ) &&
((command == 3'b000) || (command == 3'b001) || (command == 3'b010) ||
(command == 3'b011) || (command == 3'b100))) begin
// Assumes read/write latency to be same as a simplification
// Otherwise the condition above will be a bit more complex
current_state <= `PROP_DELAY `STATE_INPUT;
done <= `PROP_DELAY 1;
end
else if ((current_state == `STATE_RF_RW) && (delay_count == `LATENCY_RF_READ) &&
((command == 3'b101) || (command == 3'b110) || (command == 3'b111))) begin
current_state <= `PROP_DELAY `STATE_COMPUTE;
delay_count <= `PROP_DELAY 1;
end
else if ((current_state == `STATE_COMPUTE) && (delay_count != `LATENCY_COMPUTE)) begin
delay_count <= `PROP_DELAY delay_count + 1;
end
else if ((current_state == `STATE_COMPUTE) && (delay_count == `LATENCY_COMPUTE)) begin
current_state <= `PROP_DELAY `STATE_RF_W;
delay_count <= `PROP_DELAY 1;
end
else if ((current_state == `STATE_RF_W) && (delay_count != `LATENCY_RF_WRITE)) begin
delay_count <= `PROP_DELAY delay_count + 1;
end
else if ((current_state == `STATE_RF_W) && (delay_count == `LATENCY_RF_WRITE)) begin
current_state <= `STATE_INPUT;
done <= `PROP_DELAY 1;
end
end
endmodule
| 6.516943
|
module count (
instr[31:0],
clk,
countR[5:0],
countI[5:0],
countJ[5:0],
count3[5:0],
count4[5:0],
count5[5:0],
count6[5:0]
);
input [31:0] instr;
input clk;
output reg [5:0] countR = 0;
output reg [5:0] countI = 0;
output reg [5:0] countJ = 0;
output reg [5:0] count3 = 0;
output reg [5:0] count4 = 0;
output reg [5:0] count5 = 0;
output reg [5:0] count6 = 0;
/*
R Instructions (ALU)
sll (0x0), srl (0x2), sra (0x3), sllv (0x4), srlv (0x6),
srav (0x7), jr (0x8), jalr (0x9), mfhi (0x10), mthi (0x11),
mflo (0x12), mtlo (0x13), mult (0x18), multu (0x19), div (0x1a),
divu(0x1b), add (0x20), addu (0x21), sub (0x22), subu (0x23),
and (0x24), xor (0x26), nor (0x27), or (0x25), slt (0x2a), sltu (0x2b)
*/
/*
I instructions
Arithmetic instructions: signed immediate operand (addi, addiu, slti) or unsigned immediate operand (sltiu)
– Logical instructions: unsigned immediate operand (andi, ori, xori, lui)
– Branch instructions: PC-relative signed jump offset (beq, bne, blez, bltz, bgtz, bgez)
– Load and store instructions: signed displacement from the base register
*/
/*
J Instructions
j or jal
*/
always @(posedge clk) begin
#2
if (instr[31:26] == 0) begin
countR <= countR + 1;
// rd -> 15 to 11
if (instr[15:11] == 3) count3 <= count3 + 1;
if (instr[15:11] == 4) count4 <= count4 + 1;
if (instr[15:11] == 5) count5 <= count5 + 1;
if (instr[15:11] == 6) count6 <= count6 + 1;
end else if (instr[31:26] != 2 && instr[31:26] != 3) begin
countI <= countI + 1;
if (instr[20:16] == 3) count3 <= count3 + 1;
if (instr[20:16] == 4) count4 <= count4 + 1;
if (instr[20:16] == 5) count5 <= count5 + 1;
if (instr[20:16] == 6) count6 <= count6 + 1;
end else countJ <= countJ + 1;
end
endmodule
| 6.680742
|
module hardware (
clk,
terminate
);
memory MEMORY (
prog_counter,
instruction
); // Module instantiation for Instruction Memory
wire [31:0] instruction; // 32 bit instruction from the MEMORY
reg [2:0] prog_counter; // 3 bit program counter
reg [2:0] r_counter; // 3 bit R-Format Counter
reg [2:0] i_counter; // 3 bit I-Format Counter
reg [2:0] j_counter; // 3 bit J-Format Counter
reg [2:0] reg_counter[0:3]; // 4 3-bit counter for $3, $4, $5, $6
input clk; // Clock input for the module
output reg terminate; // A terminate signal
//sent to the top processor to give $finish signal
initial // Initialising everything to zero
begin
prog_counter = 3'b000;
r_counter = 3'b000;
i_counter = 3'b000;
j_counter = 3'b000;
terminate = 1'b0;
reg_counter[0] = 3'b000;
reg_counter[1] = 3'b000;
reg_counter[2] = 3'b000;
reg_counter[3] = 3'b000;
end
always @(posedge clk) begin
if(terminate == 1'b0) // Only run when terminate condition is not set
begin
// R - Format (0 as opcode)
if (instruction[31:26] == 6'b000000) begin
r_counter <= r_counter + 1;
case (instruction[15:11])
3'b011: reg_counter[0] <= reg_counter[0] + 1;
3'b100: reg_counter[1] <= reg_counter[1] + 1;
3'b101: reg_counter[2] <= reg_counter[2] + 1;
3'b110: reg_counter[3] <= reg_counter[3] + 1;
endcase
end // J - Format (2, 3, 26(trap) as opcode)
else if ((instruction[31:26] == 6'b000010) || (instruction[31:26] == 6'b000011) || (instruction[31:26] == 6'b011010))
begin
j_counter <= j_counter + 1;
end // I - Format
else begin
i_counter <= i_counter + 1;
case (instruction[20:16])
3'b011: reg_counter[0] <= reg_counter[0] + 1;
3'b100: reg_counter[1] <= reg_counter[1] + 1;
3'b101: reg_counter[2] <= reg_counter[2] + 1;
3'b110: reg_counter[3] <= reg_counter[3] + 1;
endcase
end
// To terminate the program an display output if the prog_count reaches the last count or increment value
if (prog_counter == 3'b111) begin
terminate <= 1'b1;
$monitor(
"Format Counts::\t\t R: %d\t I:%d\t J: %d\t\nRegister Write Counts:: $3: %d\t$4: %d\t$5: %d\t$6: %d",
r_counter, i_counter, j_counter, reg_counter[0], reg_counter[1], reg_counter[2],
reg_counter[3]);
end else begin
prog_counter <= prog_counter + 1;
end
end
end
endmodule
| 7.166936
|
module decoder (
clk,
memory,
R_counter,
I_counter,
J_counter,
reg_3_counter,
reg_4_counter,
reg_5_counter,
reg_6_counter
);
input [31:0] memory;
input clk;
output reg [2:0] R_counter;
output reg [2:0] I_counter;
output reg [2:0] J_counter;
output reg [2:0] reg_3_counter;
output reg [2:0] reg_4_counter;
output reg [2:0] reg_5_counter;
output reg [2:0] reg_6_counter;
initial begin
R_counter = 0;
I_counter = 0;
J_counter = 0;
reg_3_counter = 0;
reg_4_counter = 0;
reg_5_counter = 0;
reg_6_counter = 0;
end
always @(posedge clk) begin
if (memory[31:26] == 6'b0) begin
R_counter <= R_counter + 1;
case (memory[15:11])
3: reg_3_counter <= reg_3_counter + 1;
4: reg_4_counter <= reg_4_counter + 1;
5: reg_5_counter <= reg_5_counter + 1;
6: reg_6_counter <= reg_6_counter + 1;
endcase
end else if (memory[31:26] == 6'h2 || memory[31:26] == 6'h3) begin
J_counter <= J_counter + 1;
end else begin
I_counter <= I_counter + 1;
case (memory[20:16])
3: reg_3_counter <= reg_3_counter + 1;
4: reg_4_counter <= reg_4_counter + 1;
5: reg_5_counter <= reg_5_counter + 1;
6: reg_6_counter <= reg_6_counter + 1;
endcase
end
end
endmodule
| 7.018254
|
module main (
clk,
pc,
r,
i,
j,
three,
four,
five,
six
);
input clk;
output reg [2:0] pc = 3'b0;
output reg [2:0] r = 3'b0;
output reg [2:0] i = 3'b0;
output reg [2:0] j = 3'b0;
output reg [2:0] three = 3'b0;
output reg [2:0] four = 3'b0;
output reg [2:0] five = 3'b0;
output reg [2:0] six = 3'b0;
reg [31:0] registers[0:7];
wire [31:0] curr_inst;
wire [5:0] curr_opcode;
wire [4:0] curr_rd;
wire [4:0] curr_rt;
assign curr_inst = registers[pc];
assign curr_opcode = curr_inst[31:26];
assign curr_rd = curr_inst[15:11];
assign curr_rt = curr_inst[20:16];
initial begin
registers[0] = 32'b00100000000001000011010001010110;
registers[1] = 32'b00100000000001011111111111111111;
registers[2] = 32'b00000000101001000011000000010100;
registers[3] = 32'b00100000000000110000000000000111;
registers[4] = 32'b00000000110000110011000000000100;
registers[5] = 32'b00000000000000110001100001000010;
registers[6] = 32'b01011100100001011001101010111100;
registers[7] = 32'b00001000000100100011010001010110;
end
always @(posedge clk) begin
if (curr_opcode == 0) begin
// R
r <= #1 r + 1;
if (curr_rd == 3) begin
three <= #1 three + 1;
end else if (curr_rd == 4) begin
four <= four + 1;
end else if (curr_rd == 5) begin
five <= five + 1;
end else if (curr_rd == 6) begin
six <= six + 1;
end
end else if (curr_opcode == 2 | curr_opcode == 3) begin
// J
j <= #1 j + 1;
end else begin
// I
i <= #1 i + 1;
if (curr_rt == 3) begin
three <= #1 three + 1;
end else if (curr_rt == 4) begin
four <= four + 1;
end else if (curr_rt == 5) begin
five <= five + 1;
end else if (curr_rt == 6) begin
six <= six + 1;
end
end
// $display("%b %b\n", curr_inst, curr_opcode);
pc <= #1 pc + 1;
end
endmodule
| 7.779865
|
module processor;
reg clk;
reg [31:0] mem[7:0];
// Counters
reg [3:0] pc = 0;
reg [2:0] count_R = 0;
reg [2:0] count_I = 0;
reg [2:0] count_J = 0;
reg [2:0] count_3 = 0;
reg [2:0] count_4 = 0;
reg [2:0] count_5 = 0;
reg [2:0] count_6 = 0;
reg [32:0] cur_inst;
// Setting up clk signal
initial begin
forever begin
clk = 0;
#5 clk = 1;
#5 clk = 0;
end
end
initial begin
mem[0] = 32'b00100000000001000011010001010110;
mem[1] = 32'b00100000000001011111111111111111;
mem[2] = 32'b00000000101001000011000000010100;
mem[3] = 32'b00100000000000110000000000000111;
mem[4] = 32'b00000000011001100011000000000100;
mem[5] = 32'b00000000000000110001100001000010;
mem[6] = 32'b00010100100001011001101010111100;
mem[7] = 32'b00001000000100100011010001010110;
end
always @(posedge clk) begin
cur_inst = mem[pc];
if (cur_inst[31:26] == 6'b000000) begin
count_R = count_R + 1;
case (cur_inst[15:11])
5'b00011: count_3 = count_3 + 1;
5'b00100: count_4 = count_4 + 1;
5'b00101: count_5 = count_5 + 1;
5'b00110: count_6 = count_6 + 1;
endcase
end else if (cur_inst[31:26] == 6'b000010 || cur_inst[31:26] == 6'b000011) begin
count_J = count_J + 1;
end else begin
count_I = count_I + 1;
case (cur_inst[20:16])
5'b00011: count_3 = count_3 + 1;
5'b00100: count_4 = count_4 + 1;
5'b00101: count_5 = count_5 + 1;
5'b00110: count_6 = count_6 + 1;
endcase
end
pc = pc + 1;
if (pc == 8) begin
$display(
" R-format : %d\n I-format : %d\n J-format : %d\n Writes to $3: %d\n Writes to $4: %d\n Writes to $5: %d\n Writes to $6: %d",
count_R, count_I, count_J, count_3, count_4, count_5, count_6);
$finish;
end
end
endmodule
| 6.998875
|
module decoder (
clk,
decode_enable,
instruct,
opcode,
rs,
rt,
rd,
shift_amt,
func,
immediate
);
input [31:0] instruct; //32-bits instruction
input clk;
input decode_enable; //Needed to enable the decoder
output reg [5:0] opcode, func;
output reg [4:0] rs, rt, rd, shift_amt;
output reg [15:0] immediate;
always @(negedge clk) begin
if (decode_enable == 1'b1) begin
if (instruct[31:26] == 6'd0) begin // R-format
opcode <= instruct[31:26];
rs <= instruct[25:21];
rt <= instruct[20:16];
rd <= instruct[15:11];
shift_amt <= instruct[10:6];
func <= instruct[5:0];
end else if (instruct[31:26] == 6'd9) begin // I-format
opcode <= instruct[31:26];
rs <= instruct[25:21];
rt <= instruct[20:16];
immediate <= instruct[15:0];
end
end
end
endmodule
| 7.018254
|
module onebit (
a,
b,
cin,
opcode,
sum,
cout
);
input a, b, cin, opcode;
output sum, cout;
wire sum, cout;
assign sum = a ^ (b ^ opcode) ^ cin;
assign cout = (a & (b ^ opcode)) | ((b ^ opcode) & cin) | (cin & a);
endmodule
| 6.774993
|
module for one bit adder/subtracter
module one_bit_adder_subtracter(a, b, cin, opcode, sum, carry);
input a,b,cin,opcode; // a,b -> operands, cin -> carry in, opcode -> operation code
output wire sum, carry; // sum -> a \operation b, carry out
wire b_dummy; // additional dummy variable stores b^opcode
assign b_dummy = b^opcode;
assign sum = a^b_dummy^cin;
assign carry = (a&b_dummy) | (b_dummy&cin) | (cin&a);
endmodule
| 7.558657
|
module register_file (
clk,
read1Addr,
read2Addr,
writeAddr,
writeValue,
read1Valid,
read2Valid,
writeValid,
read1Value,
read2Value
);
input clk;
input [1:0] current_state;
input [4:0] read1Addr;
input [4:0] read2Addr;
input [4:0] writeAddr;
input [7:0] writeValue;
input read1Valid;
input read2Valid;
input writeValid;
output [7:0] read1Value;
output [7:0] read2Value;
reg [7:0] read1Value;
reg [7:0] read2Value;
reg [7:0] regfile[0:31];
initial begin
regfile[0] = 0;
regfile[1] = 0;
regfile[2] = 0;
regfile[3] = 0;
regfile[4] = 0;
regfile[5] = 0;
regfile[6] = 0;
regfile[7] = 0;
regfile[8] = 0;
regfile[9] = 0;
regfile[10] = 0;
regfile[11] = 0;
regfile[12] = 0;
regfile[13] = 0;
regfile[14] = 0;
regfile[15] = 0;
regfile[16] = 0;
regfile[17] = 0;
regfile[18] = 0;
regfile[19] = 0;
regfile[20] = 0;
regfile[21] = 0;
regfile[22] = 0;
regfile[23] = 0;
regfile[24] = 0;
regfile[25] = 0;
regfile[26] = 0;
regfile[27] = 0;
regfile[28] = 0;
regfile[29] = 0;
regfile[30] = 0;
regfile[31] = 0;
end
always @(posedge clk) begin
// if (current_state == `STATE_RF_RW) begin
if (read1Valid == 1) begin
read1Value <= regfile[read1Addr];
end
if (read2Valid == 1) begin
read2Value <= regfile[read2Addr];
end
if (writeValid == 1) begin
regfile[writeAddr] <= writeValue;
end
// end
// else if (current_state == `STATE_RF_W) begin
// regfile[writeAddr] <= writeValue;
// end
end
endmodule
| 6.605344
|
module reg_file (
clk,
read1,
read2,
write,
write_data,
input_valid,
out1,
out2
);
// Inputs
input clk;
input [4:0] read1;
input [4:0] read2;
input [4:0] write;
input [7:0] write_data;
input [2:0] input_valid;
// Outputs
output reg [7:0] out1;
output reg [7:0] out2;
// Declaration of memory
reg [7:0] mem[31:0];
// Initialising of memory
initial begin
mem[0] = 0;
mem[1] = 0;
mem[2] = 0;
mem[3] = 0;
mem[4] = 0;
mem[5] = 0;
mem[6] = 0;
mem[7] = 0;
mem[8] = 0;
mem[9] = 0;
mem[10] = 0;
mem[11] = 0;
mem[12] = 0;
mem[13] = 0;
mem[14] = 0;
mem[15] = 0;
mem[16] = 0;
mem[17] = 0;
mem[18] = 0;
mem[19] = 0;
mem[20] = 0;
mem[21] = 0;
mem[22] = 0;
mem[23] = 0;
mem[24] = 0;
mem[25] = 0;
mem[26] = 0;
mem[27] = 0;
mem[28] = 0;
mem[29] = 0;
mem[30] = 0;
mem[31] = 0;
end
always @(negedge clk) begin
if (input_valid[2] == 1) begin
out1 = mem[read1];
end
end
always @(negedge clk) begin
if (input_valid[1] == 1) begin
out2 = mem[read2];
end
end
always @(negedge clk) begin
if (input_valid[0] == 1) begin
mem[write] = write_data;
end
end
endmodule
| 7.294051
|
module a7top (
input CLK_100MHZ_FPGA,
input [3:0] BUTTONS,
input [1:0] SWITCHES,
output [3:0] LEDS,
input FPGA_SERIAL_RX,
output FPGA_SERIAL_TX
);
wire cpu_clk;
localparam CPU_CLOCK_PERIOD = 13;
localparam CPU_CLOCK_FREQ = 1_000_000_000 / CPU_CLOCK_PERIOD;
// Clocking wizard IP from Vivado (wrapper of the PLLE module)
// Generate CPU_CLOCK_FREQ clock from 125 MHz clock
// PLL FREQ = (CLKFBOUT_MULT_F * 1000 / (CLKINx_PERIOD * DIVCLK_DIVIDE) must be within (800.000 MHz - 1600.000 MHz)
// CLKOUTx_PERIOD = CLKINx_PERIOD x DIVCLK_DIVIDE x CLKOUT0_DIVIDE / CLKFBOUT_MULT_F
clk_wiz #(
.CLKIN1_PERIOD (10),
.CLKFBOUT_MULT_F(10),
.DIVCLK_DIVIDE (1),
.CLKOUT0_DIVIDE (CPU_CLOCK_PERIOD)
) clk_wiz (
.clk_out1(cpu_clk), // output
.reset (1'b0), // input
.locked (), // output, unused
.clk_in1 (CLK_100MHZ_FPGA) // input
);
// Button parser
// Sample the button signal every 500us
localparam integer B_SAMPLE_CNT_MAX = 0.0005 * CPU_CLOCK_FREQ;
// The button is considered 'pressed' after 100ms of continuous pressing
localparam integer B_PULSE_CNT_MAX = 0.100 / 0.0005;
wire [3:0] buttons_pressed;
button_parser #(
.WIDTH(4),
.SAMPLE_CNT_MAX(B_SAMPLE_CNT_MAX),
.PULSE_CNT_MAX(B_PULSE_CNT_MAX)
) bp (
.clk(cpu_clk),
.in (BUTTONS),
.out(buttons_pressed)
);
wire reset = (buttons_pressed[0] & SWITCHES[1]);
wire [31:0] csr;
wire cpu_tx, cpu_rx;
Riscv151 #(
.CPU_CLOCK_FREQ(CPU_CLOCK_FREQ)
) cpu (
.clk(cpu_clk),
.rst(reset),
.FPGA_SERIAL_TX(FPGA_SERIAL_TX),
.FPGA_SERIAL_RX(FPGA_SERIAL_RX),
.csr(csr)
);
assign LEDS[3:0] = csr[3:0];
endmodule
| 6.525358
|
module a7_ddr3_rd_ctrl (
input wire sclk,
input wire rst,
//user read ports
input wire rd_cmd_start,
input wire [2:0] rd_cmd_instr,
input wire [6:0] rd_cmd_bl,
input wire [27:0] rd_cmd_addr,
output wire [127:0] rd_data_128bit,
output wire rd_data_valid,
output wire rd_end,
//ddr3 ipcore ports
input wire [127:0] app_rd_data,
input wire app_rd_data_valid,
output wire app_en,
input wire app_rdy,
output wire [27:0] app_addr,
output wire [2:0] app_cmd
);
reg [2:0] cmd_instr;
reg [6:0] cmd_bl;
reg app_en_r;
reg [6:0] cmd_cnt;
reg [27:0] app_addr_r;
reg [6:0] data_cnt;
reg rd_end_r;
assign rd_data_128bit = app_rd_data;
assign rd_data_valid = app_rd_data_valid;
assign app_en = app_en_r;
assign app_addr = app_addr_r;
assign rd_end = rd_end_r;
always @(posedge sclk) begin
if (rst == 1'b1) begin
cmd_instr <= 'd0;
cmd_bl <= 'd0;
end else if (rd_cmd_start == 1'b1) begin
cmd_instr <= rd_cmd_instr;
cmd_bl <= rd_cmd_bl;
end
end
assign app_cmd = cmd_instr;
always @(posedge sclk) begin
if (rst == 1'b1) begin
cmd_cnt <= 'd0;
end else if (app_en_r == 1'b1 && app_rdy == 1'b1 && cmd_cnt == (cmd_bl - 1)) begin
cmd_cnt <= 'd0;
end else if (app_en_r == 1'b1 && app_rdy == 1'b1) begin
cmd_cnt <= cmd_cnt + 1'b1;
end
end
always @(posedge sclk) begin
if (rst == 1'b1) begin
app_en_r <= 1'b0;
end else if (app_en_r == 1'b1 && app_rdy == 1'b1 && cmd_cnt == (cmd_bl - 1)) begin
app_en_r <= 1'b0;
end else if (rd_cmd_start == 1'b1) begin
app_en_r <= 1'b1;
end
end
always @(posedge sclk) begin
if (rst == 1'b1) begin
app_addr_r <= 'd0;
end else if (rd_end_r == 1'b1) begin
app_addr_r <= 'd0;
end else if (rd_cmd_start == 1'b1) begin
app_addr_r <= rd_cmd_addr;
end else if (app_en_r == 1'b1 && app_rdy == 1'b1) begin
app_addr_r <= app_addr_r + 'd8;
end
end
always @(posedge sclk) begin
if (rst == 1'b1) begin
data_cnt <= 'd0;
end else if (data_cnt == (cmd_bl - 1) && app_rd_data_valid == 1'b1) begin
data_cnt <= 'd0;
end else if (app_rd_data_valid == 1'b1) begin
data_cnt <= data_cnt + 1'b1;
end
end
always @(posedge sclk) begin
if (rst == 1'b1) begin
rd_end_r <= 'd0;
end else if (data_cnt == (cmd_bl - 1) && app_rd_data_valid == 1'b1) begin
rd_end_r <= 1'b1;
end else begin
rd_end_r <= 1'b0;
end
end
endmodule
| 6.547039
|
module a7_ddr3_wr_ctrl (
input wire sclk,
input wire rst,
//user write ports
input wire wr_cmd_start,
input wire [2:0] wr_cmd_instr,
input wire [6:0] wr_cmd_bl,
input wire [27:0] wr_cmd_addr,
input wire [127:0] data_128bit,
input wire [15:0] wr_cmd_mask,
output wire data_req,
output wire wr_end,
//ddr3 ipcore ports
output wire app_wdf_wren,
output wire [127:0] app_wdf_data,
input wire app_wdf_rdy,
output wire app_en,
input wire app_rdy,
output wire [27:0] app_addr,
output wire [2:0] app_cmd
);
reg [2:0] cmd_instr;
reg [6:0] cmd_bl;
reg [27:0] cmd_addr;
reg [15:0] cmd_mask;
reg wdf_wren;
reg [7:0] data_cnt;
reg app_en_r;
reg [7:0] cmd_cnt;
reg wr_end_r;
assign wr_end = wr_end_r;
assign app_wdf_wren = wdf_wren;
assign app_en = app_en_r;
assign app_addr = cmd_addr;
assign app_cmd = cmd_instr;
always @(posedge sclk) begin
if (rst == 1'b1) begin
cmd_instr <= 'd0;
cmd_bl <= 'd0;
cmd_mask <= 'd0;
end else if (wr_cmd_start == 1'b1) begin
cmd_instr <= wr_cmd_instr;
cmd_bl <= wr_cmd_bl;
cmd_mask <= wr_cmd_mask;
end
end
always @(posedge sclk) begin
if (rst == 1'b1) begin
wdf_wren <= 1'b0;
end else if (wdf_wren == 1'b1 && data_cnt == (cmd_bl - 1) && app_wdf_rdy == 1'b1) begin
wdf_wren <= 1'b0;
end else if (wr_cmd_start == 1'b1) begin
wdf_wren <= 1'b1;
end
end
always @(posedge sclk) begin
if (rst == 1'b1) begin
data_cnt <= 'd0;
end else if (data_cnt == (cmd_bl - 1) && data_req == 1'b1) begin
data_cnt <= 'd0;
end else if (data_req == 1'b1) begin
data_cnt <= data_cnt + 1'b1;
end
end
assign data_req = wdf_wren & app_wdf_rdy;
assign app_wdf_data = data_128bit;
always @(posedge sclk) begin
if (rst == 1'b1) begin
app_en_r <= 1'b0;
end else if (app_en_r == 1'b1 && app_rdy == 1'b1 && cmd_cnt == (cmd_bl - 1)) begin
app_en_r <= 1'b0;
end else if (data_req == 1'b1) begin
app_en_r <= 1'b1;
end
end
always @(posedge sclk) begin
if (rst == 1'b1) begin
cmd_cnt <= 'd0;
end else if (cmd_cnt == (cmd_bl - 1) && app_rdy == 1'b1 && app_en_r == 1'b1) begin
cmd_cnt <= 'd0;
end else if (app_en_r == 1'b1 && app_rdy == 1'b1) begin
cmd_cnt <= cmd_cnt + 1'b1;
end
end
always @(posedge sclk) begin
if (rst == 1'b1) begin
cmd_addr <= 'd0;
end else if (wr_end_r) begin
cmd_addr <= 'd0;
end else if (app_rdy == 1'b1 && app_en_r == 1'b1) begin
cmd_addr <= cmd_addr + 'd8;
end else if (wr_cmd_start == 1'b1) begin
cmd_addr <= wr_cmd_addr;
end
end
always @(posedge sclk) begin
if (rst == 1'b1) begin
wr_end_r <= 'd0;
end else if (cmd_cnt == (cmd_bl - 1) && app_rdy == 1'b1 && app_en_r == 1'b1) begin
wr_end_r <= 1'b1;
end else begin
wr_end_r <= 1'b0;
end
end
endmodule
| 7.170692
|
module A7_gen1x1_pcie_gtp_cpllpd_ovrd (
input i_ibufds_gte2,
output o_cpllpd_ovrd,
output o_cpllreset_ovrd
);
(* equivalent_register_removal="no" *)reg [ 95:0] cpllpd_wait = 96'hFFFFFFFFFFFFFFFFFFFFFFFF;
(* equivalent_register_removal="no" *)reg [127:0] cpllreset_wait = 128'h000000000000000000000000000000FF;
always @(posedge i_ibufds_gte2) begin
cpllpd_wait <= {cpllpd_wait[94:0], 1'b0};
cpllreset_wait <= {cpllreset_wait[126:0], 1'b0};
end
assign o_cpllpd_ovrd = cpllpd_wait[95];
assign o_cpllreset_ovrd = cpllreset_wait[127];
endmodule
| 7.051487
|
module A7_gen1x1_pcie_gtx_cpllpd_ovrd (
input i_ibufds_gte2,
output o_cpllpd_ovrd,
output o_cpllreset_ovrd
);
(* equivalent_register_removal="no" *)reg [ 95:0] cpllpd_wait = 96'hFFFFFFFFFFFFFFFFFFFFFFFF;
(* equivalent_register_removal="no" *)reg [127:0] cpllreset_wait = 128'h000000000000000000000000000000FF;
always @(posedge i_ibufds_gte2) begin
cpllpd_wait <= {cpllpd_wait[94:0], 1'b0};
cpllreset_wait <= {cpllreset_wait[126:0], 1'b0};
end
assign o_cpllpd_ovrd = cpllpd_wait[95];
assign o_cpllreset_ovrd = cpllreset_wait[127];
endmodule
| 7.051487
|
module data (
data_index,
data_out
);
reg [7:0] data[0:10];
input [3:0] data_index;
output wire [7:0] data_out;
initial begin
// To be initialised by the TA
data[0] = 8'b10000000;
data[1] = 8'b01111111;
data[2] = 8'b10000000;
data[3] = 8'b01111111;
data[4] = 8'b00000001;
data[5] = 8'b00000001;
data[6] = 8'b00000001;
data[7] = 8'b00000001;
data[8] = 8'b00000001;
data[9] = 8'b00000001;
data[10] = 8'b00001100;
end
assign data_out = data[data_index];
endmodule
| 6.592692
|
module decode(clk, state, instruction, opcode, rs, rt, rd, imm, func, jump_target);
input clk;
input [2:0] state;
input [31:0] instruction;
output reg [5:0] opcode;
output reg [4:0] rs;
output reg [4:0] rt;
output reg [4:0] rd;
output reg [15:0] imm;
output reg [5:0] func;
output reg [25:0] jump_target;
always @ (posedge clk) begin
if (state == `STATE_ID) begin
opcode <= `PROP_DELAY instruction[31:26];
rs <= `PROP_DELAY instruction[25:21];
imm <= `PROP_DELAY instruction[15:0];
func <= `PROP_DELAY instruction[5:0];
jump_target <= `PROP_DELAY instruction[25:0];
rd <= `PROP_DELAY instruction[15:11];
if (instruction[31:26] == `OP_JAL) begin
rt <= `PROP_DELAY 31;
end
else begin
rt <= `PROP_DELAY instruction[20:16];
end
end
end
endmodule
| 6.557982
|
module decoder (
clk,
state,
instruct,
format,
opcode,
rs,
rt,
rd,
shift_amt,
immediate,
target
);
input [31:0] instruct; //32-bits instruction
input [2:0] state;
input clk;
output reg [1:0] format;
output reg [4:0] rs, rt, rd, shift_amt;
output reg [5:0] opcode;
output reg [15:0] immediate;
output reg [25:0] target;
always @(posedge clk) begin
if (state == `ID) begin // Decode state
if (instruct[31:26] == 6'd0) begin // R-format
format <= `R;
rs <= instruct[25:21];
rt <= instruct[20:16];
rd <= instruct[15:11];
shift_amt <= instruct[10:6];
opcode <= instruct[5:0];
end else if (instruct[31:26] == `JAL) begin // J-format: only jal needs to be supported
format <= `J;
opcode <= instruct[31:26];
target <= instruct[25:0];
end else begin // I-format
format <= `I;
opcode <= instruct[31:26];
rs <= instruct[25:21];
if(instruct[31:26] == `BEQ || instruct[31:26] == `BNE) begin // 2 source operands for beq and bne - store second in rt to maintain uniformity
rt <= instruct[20:16];
end else begin
rd <= instruct[20:16];
end
immediate <= instruct[15:0];
end
end
end
endmodule
| 7.018254
|
module for 8 bit adder/subtracter
module eight_bit_add_sub (a, b, opcode, sum);
input [7:0] a, b; // operands
input opcode; // operation code
output wire [7:0] sum; // output of operation
wire carry, overflow; // Ignored carry over and overflow
wire [6:0] intermediate_carry; // required dummy variable.
one_bit_adder_subtracter AB0 (a[0], b[0], opcode, opcode, sum[0], intermediate_carry[0]);
one_bit_adder_subtracter AB1 (a[1], b[1], intermediate_carry[0], opcode, sum[1], intermediate_carry[1]);
one_bit_adder_subtracter AB2 (a[2], b[2], intermediate_carry[1], opcode, sum[2], intermediate_carry[2]);
one_bit_adder_subtracter AB3 (a[3], b[3], intermediate_carry[2], opcode, sum[3], intermediate_carry[3]);
one_bit_adder_subtracter AB4 (a[4], b[4], intermediate_carry[3], opcode, sum[4], intermediate_carry[4]);
one_bit_adder_subtracter AB5 (a[5], b[5], intermediate_carry[4], opcode, sum[5], intermediate_carry[5]);
one_bit_adder_subtracter AB6 (a[6], b[6], intermediate_carry[5], opcode, sum[6], intermediate_carry[6]);
one_bit_adder_subtracter AB15 (a[7], b[7], intermediate_carry[6], opcode, sum[7], carry);
assign overflow = intermediate_carry[6]^carry;
endmodule
| 6.704869
|
module for one bit adder/subtracter
module one_bit_adder_subtracter(a, b, cin, opcode, sum, carry);
input a,b,cin,opcode; // a,b -> operands, cin -> carry in, opcode -> operation code
output wire sum, carry; // sum -> a \operation b, carry out
wire b_dummy; // additional dummy variable stores b^opcode
assign b_dummy = b^opcode;
assign sum = a^b_dummy^cin;
assign carry = (a&b_dummy) | (b_dummy&cin) | (cin&a);
endmodule
| 7.558657
|
module register_file (
clk,
state,
read_address1,
read_address2,
write_address1,
write_address2,
write,
format,
valid,
read_out1,
read_out2,
write_in,
done
);
input [7:0] write_in;
input [4:0] read_address1, read_address2;
input [4:0] write_address1, write_address2;
input [2:0] state;
input [1:0] format;
input clk, write, valid;
output reg [7:0] read_out1, read_out2;
output reg done;
reg [7:0] registers[31:0];
initial begin
// Initialising 32 registers each of width 8 bits
registers[0] = 8'd0;
registers[1] = 8'd0;
registers[2] = 8'd0;
registers[3] = 8'd0;
registers[4] = 8'd0;
registers[5] = 8'd0;
registers[6] = 8'd0;
registers[7] = 8'd0;
registers[8] = 8'd0;
registers[9] = 8'd0;
registers[10] = 8'd0;
registers[11] = 8'd0;
registers[12] = 8'd0;
registers[13] = 8'd0;
registers[14] = 8'd0;
registers[15] = 8'd0;
registers[16] = 8'd0;
registers[17] = 8'd0;
registers[18] = 8'd0;
registers[19] = 8'd0;
registers[20] = 8'd0;
registers[21] = 8'd0;
registers[22] = 8'd0;
registers[23] = 8'd0;
registers[24] = 8'd0;
registers[25] = 8'd0;
registers[26] = 8'd0;
registers[27] = 8'd0;
registers[28] = 8'd0;
registers[29] = 8'd0;
registers[30] = 8'd0;
registers[31] = 8'd0;
done <= 1'b0;
end
always @(posedge clk) begin
if (state == `RF) begin // Fetch source operands from registers
read_out1 <= registers[read_address1];
read_out2 <= registers[read_address2];
end else if (state == `WB) begin // Write results to registers
if (write == 1'b1 && valid == 1'b1) begin // Write is required, instruction is valid
if (format == `J && write_address2 != 5'd0) begin
registers[write_address2] <= write_in; // Write to register address computed by ALU - for jump targets
end else if (write_address1 != 5'd0) begin
registers[write_address1] <= write_in; // Write to instruction destination register
end
end
end else if (state == `OUT) begin // Fetch output and mark done
read_out1 <= registers[`OUTPUT_REG];
done <= 1'b1;
end
end
// gtkwave debugging for register storage
// initial begin
// $dumpfile("proc.vcd");
// $dumpvars(0, registers[0]);
// $dumpvars(0, registers[1]);
// $dumpvars(0, registers[2]);
// $dumpvars(0, registers[3]);
// $dumpvars(0, registers[4]);
// $dumpvars(0, registers[5]);
// $dumpvars(0, registers[6]);
// $dumpvars(0, registers[31]);
// end
endmodule
| 6.605344
|
module register_file(clk, state, rs, rt, rd, result, instruction_invalid, rsv, rtv, done);
input clk;
input [2:0] state;
input [4:0] rs;
input [4:0] rt;
input [4:0] rd;
input [7:0] result;
input instruction_invalid;
output reg [7:0] rsv;
output reg [7:0] rtv;
output reg done;
reg [7:0] regfile [0:31];
reg [5:0] i;
initial begin
for (i = 0; i < 32; i = i + 1) begin
regfile[i] = 0;
end
done = 0;
end
always @ (posedge clk) begin
if (state == `STATE_RF) begin
rsv <= `PROP_DELAY regfile[rs];
rtv <= `PROP_DELAY regfile[rt];
end
else if ((state == `STATE_WB) && (rd != 0) && (instruction_invalid == 0)) begin
regfile[rd] <= `PROP_DELAY result;
end
else if (state == `STATE_OUTPUT) begin
rsv <= `PROP_DELAY regfile[`OUTPUT_REG];
done <= `PROP_DELAY 1;
end
end
endmodule
| 6.605344
|
module reg_file (
clk,
read1,
read2,
write,
write_data,
input_valid,
out1,
out2
);
// Inputs
input clk;
input [4:0] read1;
input [4:0] read2;
input [4:0] write;
input [7:0] write_data;
input [2:0] input_valid;
// Outputs
output reg [7:0] out1;
output reg [7:0] out2;
// Declaration of memory
reg [7:0] mem[31:0];
// Initialising of memory
initial begin
mem[0] = 0;
mem[1] = 0;
mem[2] = 0;
mem[3] = 0;
mem[4] = 0;
mem[5] = 0;
mem[6] = 0;
mem[7] = 0;
mem[8] = 0;
mem[9] = 0;
mem[10] = 0;
mem[11] = 0;
mem[12] = 0;
mem[13] = 0;
mem[14] = 0;
mem[15] = 0;
mem[16] = 0;
mem[17] = 0;
mem[18] = 0;
mem[19] = 0;
mem[20] = 0;
mem[21] = 0;
mem[22] = 0;
mem[23] = 0;
mem[24] = 0;
mem[25] = 0;
mem[26] = 0;
mem[27] = 0;
mem[28] = 0;
mem[29] = 0;
mem[30] = 0;
mem[31] = 0;
end
always @(negedge clk) begin
if (input_valid[2] == 1) begin
out1 = mem[read1];
end
end
always @(negedge clk) begin
if (input_valid[1] == 1) begin
out2 = mem[read2];
end
end
always @(negedge clk) begin
if (input_valid[0] == 1) begin
mem[write] = write_data;
end
end
endmodule
| 7.294051
|
module state_control(clk, program_counter, state);
input clk;
input [7:0] program_counter;
output reg [2:0] state;
initial begin
state = `STATE_IF;
end
always @ (posedge clk) begin
if ((state == `STATE_WB) && (program_counter < `MAX_PC)) begin
state <= `PROP_DELAY `STATE_IF;
end
else if (state != `STATE_OUTPUT) begin
state <= `PROP_DELAY state + 1;
end
end
endmodule
| 6.516943
|
module data (
data_index,
data_out
);
reg [7:0] data[0:2];
input [1:0] data_index;
output wire [7:0] data_out;
initial begin
// To be initialised by the TA
data[0] = 8'b11110110;
data[1] = 8'b00010100;
data[2] = 8'b00000010;
end
assign data_out = data[data_index];
endmodule
| 6.592692
|
module decode(clk, state, instruction, opcode, rs, rt, rd, imm, func, jump_target);
input clk;
input [2:0] state;
input [31:0] instruction;
output reg [5:0] opcode;
output reg [4:0] rs;
output reg [4:0] rt;
output reg [4:0] rd;
output reg [15:0] imm;
output reg [5:0] func;
output reg [25:0] jump_target;
always @ (posedge clk) begin
if (state == `STATE_ID) begin
opcode <= `PROP_DELAY instruction[31:26];
rs <= `PROP_DELAY instruction[25:21];
imm <= `PROP_DELAY instruction[15:0];
func <= `PROP_DELAY instruction[5:0];
jump_target <= `PROP_DELAY instruction[25:0];
rd <= `PROP_DELAY instruction[15:11];
if (instruction[31:26] == `OP_JAL) begin
rt <= `PROP_DELAY 31;
end
else begin
rt <= `PROP_DELAY instruction[20:16];
end
end
end
endmodule
| 6.557982
|
module decoder (
clk,
state,
instruct,
format,
opcode,
rs,
rt,
rd,
shift_amt,
immediate,
target
);
input [31:0] instruct; //32-bits instruction
input [2:0] state;
input clk;
output reg [1:0] format;
output reg [4:0] rs, rt, rd, shift_amt;
output reg [5:0] opcode;
output reg [15:0] immediate;
output reg [25:0] target;
always @(posedge clk) begin
if (state == `ID) begin // Decode state
if (instruct[31:26] == 6'd0) begin // R-format
format <= `R;
rs <= instruct[25:21];
rt <= instruct[20:16];
rd <= instruct[15:11];
shift_amt <= instruct[10:6];
opcode <= instruct[5:0];
end else if (instruct[31:26] == `JAL) begin // J-format: only jal needs to be supported
format <= `J;
opcode <= instruct[31:26];
target <= instruct[25:0];
end else begin // I-format
format <= `I;
opcode <= instruct[31:26];
rs <= instruct[25:21];
if(instruct[31:26] == `BEQ || instruct[31:26] == `BNE) begin // 2 source operands for beq and bne - store second in rt to maintain uniformity
rt <= instruct[20:16];
end else begin
rd <= instruct[20:16];
end
immediate <= instruct[15:0];
end
end
end
endmodule
| 7.018254
|
module for 8 bit adder/subtracter
module eight_bit_add_sub (a, b, opcode, sum);
input [7:0] a, b; // operands
input opcode; // operation code
output wire [7:0] sum; // output of operation
wire carry, overflow; // Ignored carry over and overflow
wire [6:0] intermediate_carry; // required dummy variable.
one_bit_adder_subtracter AB0 (a[0], b[0], opcode, opcode, sum[0], intermediate_carry[0]);
one_bit_adder_subtracter AB1 (a[1], b[1], intermediate_carry[0], opcode, sum[1], intermediate_carry[1]);
one_bit_adder_subtracter AB2 (a[2], b[2], intermediate_carry[1], opcode, sum[2], intermediate_carry[2]);
one_bit_adder_subtracter AB3 (a[3], b[3], intermediate_carry[2], opcode, sum[3], intermediate_carry[3]);
one_bit_adder_subtracter AB4 (a[4], b[4], intermediate_carry[3], opcode, sum[4], intermediate_carry[4]);
one_bit_adder_subtracter AB5 (a[5], b[5], intermediate_carry[4], opcode, sum[5], intermediate_carry[5]);
one_bit_adder_subtracter AB6 (a[6], b[6], intermediate_carry[5], opcode, sum[6], intermediate_carry[6]);
one_bit_adder_subtracter AB15 (a[7], b[7], intermediate_carry[6], opcode, sum[7], carry);
assign overflow = intermediate_carry[6]^carry;
endmodule
| 6.704869
|
module for one bit adder/subtracter
module one_bit_adder_subtracter(a, b, cin, opcode, sum, carry);
input a,b,cin,opcode; // a,b -> operands, cin -> carry in, opcode -> operation code
output wire sum, carry; // sum -> a \operation b, carry out
wire b_dummy; // additional dummy variable stores b^opcode
assign b_dummy = b^opcode;
assign sum = a^b_dummy^cin;
assign carry = (a&b_dummy) | (b_dummy&cin) | (cin&a);
endmodule
| 7.558657
|
module register_file (
clk,
state,
read_address1,
read_address2,
write_address1,
write_address2,
write,
format,
valid,
read_out1,
read_out2,
write_in,
done
);
input [7:0] write_in;
input [4:0] read_address1, read_address2;
input [4:0] write_address1, write_address2;
input [2:0] state;
input [1:0] format;
input clk, write, valid;
output reg [7:0] read_out1, read_out2;
output reg done;
reg [7:0] registers[31:0];
initial begin
// Initialising 32 registers each of width 8 bits
registers[0] = 8'd0;
registers[1] = 8'd0;
registers[2] = 8'd0;
registers[3] = 8'd0;
registers[4] = 8'd0;
registers[5] = 8'd0;
registers[6] = 8'd0;
registers[7] = 8'd0;
registers[8] = 8'd0;
registers[9] = 8'd0;
registers[10] = 8'd0;
registers[11] = 8'd0;
registers[12] = 8'd0;
registers[13] = 8'd0;
registers[14] = 8'd0;
registers[15] = 8'd0;
registers[16] = 8'd0;
registers[17] = 8'd0;
registers[18] = 8'd0;
registers[19] = 8'd0;
registers[20] = 8'd0;
registers[21] = 8'd0;
registers[22] = 8'd0;
registers[23] = 8'd0;
registers[24] = 8'd0;
registers[25] = 8'd0;
registers[26] = 8'd0;
registers[27] = 8'd0;
registers[28] = 8'd0;
registers[29] = 8'd0;
registers[30] = 8'd0;
registers[31] = 8'd0;
done <= 1'b0;
end
always @(posedge clk) begin
if (state == `RF) begin // Fetch source operands from registers
read_out1 <= registers[read_address1];
read_out2 <= registers[read_address2];
end else if (state == `WB) begin // Write results to registers
if (write == 1'b1 && valid == 1'b1) begin // Write is required, instruction is valid
if (format == `J && write_address2 != 5'd0) begin
registers[write_address2] <= write_in; // Write to register address computed by ALU - for jump targets
end else if (write_address1 != 5'd0) begin
registers[write_address1] <= write_in; // Write to instruction destination register
end
end
end else if (state == `OUT) begin // Fetch output and mark done
read_out1 <= registers[`OUTPUT_REG];
done <= 1'b1;
end
end
// gtkwave debugging for register storage
// initial begin
// $dumpfile("proc.vcd");
// $dumpvars(0, registers[0]);
// $dumpvars(0, registers[1]);
// $dumpvars(0, registers[2]);
// $dumpvars(0, registers[3]);
// $dumpvars(0, registers[4]);
// $dumpvars(0, registers[5]);
// $dumpvars(0, registers[6]);
// $dumpvars(0, registers[31]);
// end
endmodule
| 6.605344
|
module register_file(clk, state, rs, rt, rd, result, instruction_invalid, rsv, rtv, done);
input clk;
input [2:0] state;
input [4:0] rs;
input [4:0] rt;
input [4:0] rd;
input [7:0] result;
input instruction_invalid;
output reg [7:0] rsv;
output reg [7:0] rtv;
output reg done;
reg [7:0] regfile [0:31];
reg [5:0] i;
initial begin
for (i = 0; i < 32; i = i + 1) begin
regfile[i] = 0;
end
done = 0;
end
always @ (posedge clk) begin
if (state == `STATE_RF) begin
rsv <= `PROP_DELAY regfile[rs];
rtv <= `PROP_DELAY regfile[rt];
end
else if ((state == `STATE_WB) && (rd != 0) && (instruction_invalid == 0)) begin
regfile[rd] <= `PROP_DELAY result;
end
else if (state == `STATE_OUTPUT) begin
rsv <= `PROP_DELAY regfile[`OUTPUT_REG];
done <= `PROP_DELAY 1;
end
end
endmodule
| 6.605344
|
module reg_file (
clk,
read1,
read2,
write,
write_data,
input_valid,
out1,
out2
);
// Inputs
input clk;
input [4:0] read1;
input [4:0] read2;
input [4:0] write;
input [7:0] write_data;
input [2:0] input_valid;
// Outputs
output reg [7:0] out1;
output reg [7:0] out2;
// Declaration of memory
reg [7:0] mem[31:0];
// Initialising of memory
initial begin
mem[0] = 0;
mem[1] = 0;
mem[2] = 0;
mem[3] = 0;
mem[4] = 0;
mem[5] = 0;
mem[6] = 0;
mem[7] = 0;
mem[8] = 0;
mem[9] = 0;
mem[10] = 0;
mem[11] = 0;
mem[12] = 0;
mem[13] = 0;
mem[14] = 0;
mem[15] = 0;
mem[16] = 0;
mem[17] = 0;
mem[18] = 0;
mem[19] = 0;
mem[20] = 0;
mem[21] = 0;
mem[22] = 0;
mem[23] = 0;
mem[24] = 0;
mem[25] = 0;
mem[26] = 0;
mem[27] = 0;
mem[28] = 0;
mem[29] = 0;
mem[30] = 0;
mem[31] = 0;
end
always @(negedge clk) begin
if (input_valid[2] == 1) begin
out1 = mem[read1];
end
end
always @(negedge clk) begin
if (input_valid[1] == 1) begin
out2 = mem[read2];
end
end
always @(negedge clk) begin
if (input_valid[0] == 1) begin
mem[write] = write_data;
end
end
endmodule
| 7.294051
|
module state_control(clk, program_counter, state);
input clk;
input [7:0] program_counter;
output reg [2:0] state;
initial begin
state = `STATE_IF;
end
always @ (posedge clk) begin
if ((state == `STATE_WB) && (program_counter < `MAX_PC)) begin
state <= `PROP_DELAY `STATE_IF;
end
else if (state != `STATE_OUTPUT) begin
state <= `PROP_DELAY state + 1;
end
end
endmodule
| 6.516943
|
module FullAdd4 (
A,
B,
Cin,
Sum,
Cout
);
input [3:0] A, B;
input Cin;
output [3:0] Sum;
output Cout;
assign {Cout, Sum} = A + B + Cin;
endmodule
| 6.742264
|
module Comparator2 (
A,
B,
Equals
);
input [1:0] A, B;
output reg Equals;
assign Equals = ~(A[0] ^ B[0]) & ~(A[1] ^ B[1]);
// student code here
endmodule
| 6.679309
|
module Majority (
A,
B,
C,
Y
);
input A, B, C;
output Y;
reg Y;
// student code here
assign Y = (A & B) | (A & C) | (B & C);
endmodule
| 6.913887
|
module ALU (
input [2:0] Op_code,
input [31:0] A,
B,
output reg [31:0] Y
);
reg [31:0] Yaux;
/*Change*/
always @(A, B, Op_code) begin
case (Op_code)
/*A*/
3'b000: Y <= A;
/*Add*/
3'b001: Y <= A + B;
/*Substract*/
3'b010: Y <= A - B;
/*AND*/
3'b011: Y <= A & B;
/*OR*/
3'b100: Y <= A | B;
/*Increment A*/
3'b101: Y <= A + 1;
/*Decrement A*/
3'b110: Y <= A - 1;
/*B*/
3'b111: Y <= B;
/**/
default: Y <= 0;
endcase
end
/*Assign output*/
//assign Y = Yaux;
endmodule
| 7.960621
|
module LS161a (
input [3:0] D, // Parallel Input
input CLK, // Clock
input CLR_n, // Active Low Asynchronous Reset
input LOAD_n, // Enable Parallel Input
input ENP, // Count Enable Parallel
input ENT, // Count Enable Trickle
output [3:0] Q, // Parallel Output
output RCO // Ripple Carry Output (Terminal Count)
);
reg [3:0] counter;
reg cout;
always @(posedge CLK) begin
if (CLR_n == 1'b0) begin
counter = 4'b0000;
cout = 1'b0;
end else begin
if (LOAD_n == 1'b0) begin
counter = D;
end else if ((ENP == 1'b1) & (ENT == 1'b1)) begin
if (counter == 4'b1111) begin
cout <= 1'b1;
counter <= 4'b0000;
end else begin
counter <= counter + 1;
cout <= 1'b0;
end
end
end
end
assign Q = counter;
assign RCO = cout;
endmodule
| 6.565615
|
module RAM128x32 #(
parameter Data_width = 32, //# of bits in word
Addr_width = 7 // # of address bits
) ( //ports
input wire clk,
input wire we,
input wire [(Addr_width-1):0] address,
input wire [(Data_width-1):0] d,
output wire [(Data_width-1):0] q
);
reg [31:0] MEMORY[2**7-1:0];
always @(posedge clk) begin
if (we) MEMORY[address] <= d;
else MEMORY[address] <= 32'hxxxxxxxx;
end
assign q = MEMORY[address];
endmodule
| 8.380911
|
module AALU(x, y, lose, bonus);
// x: first input
// y: second input
// lose: if 1, the player loses the game.
// bonus: the achieved points.
input [4:0] x;
input [4:0] y;
output reg [4:0] bonus;
output lose;
wire reg [4:0] greater
wire reg [4:0] lower;
comparator comp(
.x(x[4:0]),
.y(y[4:0]),
.greater(greater[4:0]),
.lower(lower[4:0]),
.same(lose)
);
subtractor(
.operandone(greater[4:0]),
.operandtwo(lower[4:0]),
.result(bonus[4:0])
);
endmodule
| 7.174979
|
module subtractor(operandone, operandtwo, result);
// For better readability, verilog operation used.
input [4:0] operandone;
input [4:0] operandtwo;
output [4:0] result;
result <= operandone - operandtwo;
endmodule
| 6.611259
|
module register (
data_in,
resetn,
clk,
data_result
);
input [4:0] data_in;
input resetn;
input clk;
output reg [4:0] data_result;
always @(posedge clk) begin
if (!resetn) begin
data_result <= 5'b00000;
end else data_result <= data_in;
end
endmodule
| 6.542519
|
module AASD (
AASD_output,
clk,
rst
);
reg R1;
output reg AASD_output;
input clk, rst;
always @(posedge clk or negedge rst)
if (!rst) begin
R1 <= 1'b0;
AASD_output <= 0;
end else begin
R1 <= 1'b1;
AASD_output <= R1;
end
endmodule
| 7.083945
|
module ab2cd (
rst,
clk,
ab,
cd
);
input rst; //复位信号，高电平有效
input clk; //FPGA系统时钟
input [1:0] ab; //输入的绝对码数据
output [1:0] cd; //转换后的相对码数据
reg [1:0] ef;
always @(posedge clk or posedge rst)
if (rst) begin
ef <= 2'd0;
end else begin
if ((ab == 2'b10) && (ef == 2'b00)) ef <= 2'b10;
else if ((ab == 2'b10) && (ef == 2'b10)) ef <= 2'b11;
else if ((ab == 2'b10) && (ef == 2'b11)) ef <= 2'b01;
else if ((ab == 2'b10) && (ef == 2'b01)) ef <= 2'b00;
else if ((ab == 2'b11) && (ef == 2'b00)) ef <= 2'b11;
else if ((ab == 2'b11) && (ef == 2'b10)) ef <= 2'b01;
else if ((ab == 2'b11) && (ef == 2'b11)) ef <= 2'b00;
else if ((ab == 2'b11) && (ef == 2'b01)) ef <= 2'b10;
else if ((ab == 2'b01) && (ef == 2'b00)) ef <= 2'b01;
else if ((ab == 2'b01) && (ef == 2'b10)) ef <= 2'b00;
else if ((ab == 2'b01) && (ef == 2'b11)) ef <= 2'b10;
else if ((ab == 2'b01) && (ef == 2'b01)) ef <= 2'b11;
else if ((ab == 2'b11) && (ef == 2'b00)) ef <= 2'b11;
else if ((ab == 2'b11) && (ef == 2'b10)) ef <= 2'b01;
else if ((ab == 2'b11) && (ef == 2'b11)) ef <= 2'b00;
else if ((ab == 2'b11) && (ef == 2'b01)) ef <= 2'b10;
else if ((ab == 2'b00) && (ef == 2'b00)) ef <= 2'b00;
else if ((ab == 2'b00) && (ef == 2'b10)) ef <= 2'b10;
else if ((ab == 2'b00) && (ef == 2'b11)) ef <= 2'b11;
else if ((ab == 2'b00) && (ef == 2'b01)) ef <= 2'b01;
end
assign cd = ef;
endmodule
| 6.852546
|
module ab8016a
(
output [0:15] z_out,
output [0:15] z_oe,
input [0:15] z_in,
input cen,
input rw,
input [0:7] a,
input sys_clk
);
wire [7:0] a_r;
wire [15:0] z_out_r;
wire [15:0] z_in_r;
assign a_r[7:0] = {a[7], a[6], a[5], a[4], a[3], a[2], a[1], a[0]};
assign z_out[0:15] = {z_out_r[0], z_out_r[1], z_out_r[2], z_out_r[3], z_out_r[4], z_out_r[5], z_out_r[6], z_out_r[7],
z_out_r[8], z_out_r[9], z_out_r[10], z_out_r[11], z_out_r[12], z_out_r[13], z_out_r[14], z_out_r[15]};
assign z_in_r[15:0] = {z_in[15], z_in[14], z_in[13], z_in[12], z_in[11], z_in[10], z_in[9], z_in[8],
z_in[7], z_in[6], z_in[5], z_in[4], z_in[3], z_in[2], z_in[1], z_in[0]};
`ifdef SIMULATION
reg [15:0] r_z_out_r;
// reg [15:0] r_z_out_r_dly;
reg [0:15] r_z_oe = 16'h0000;
// reg [0:15] r_z_oe_dly = 16'h0000;
reg [15:0] ram_blk [0:(1<<8)-1];
// assign z_oe = r_z_oe_dly;
assign z_out_r = r_z_out_r;
assign z_oe = r_z_oe;
always @(posedge sys_clk)
begin
// r_z_out_r_dly <= r_z_out_r;
// r_z_oe_dly <= r_z_oe;
if (~cen) begin
if (~rw) begin
ram_blk[a_r][15:0] <= z_in_r;
end
r_z_out_r <= ram_blk[a_r][15:0];
end
r_z_oe <= (~cen & rw) ? 16'hffff : 16'h0000;
end
`else
wire wren;
reg [0:15] r_z_oe = 16'h0000;
// reg [0:15] r_z_oe_dly = 16'h0000;
assign z_oe = r_z_oe;
always @(posedge sys_clk)
begin
r_z_oe <= (~cen & rw) ? 16'hffff : 16'h0000;
end
assign wren = (~cen & ~rw);
altsyncram altsyncram_component (
.wren_a (wren),
.clock0 (sys_clk),
.address_a (a_r),
.data_a (z_in_r),
.q_a (z_out_r),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 256,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 8,
altsyncram_component.width_a = 16,
altsyncram_component.width_byteena_a = 1;
`endif
endmodule
| 6.786311
|
module ab8616a
(
output [0:15] z_out,
output [0:15] z_oe,
input [0:15] z_in,
input cen,
input rw,
input [0:8] a,
input sys_clk
);
wire [8:0] a_r;
wire [15:0] z_out_r;
wire [15:0] z_in_r;
assign a_r[8:0] = {a[8], a[7], a[6], a[5], a[4], a[3], a[2], a[1], a[0]};
assign z_out[0:15] = {z_out_r[0], z_out_r[1], z_out_r[2], z_out_r[3], z_out_r[4], z_out_r[5], z_out_r[6], z_out_r[7],
z_out_r[8], z_out_r[9], z_out_r[10], z_out_r[11], z_out_r[12], z_out_r[13], z_out_r[14], z_out_r[15]};
assign z_in_r[15:0] = {z_in[15], z_in[14], z_in[13], z_in[12], z_in[11], z_in[10], z_in[9], z_in[8],
z_in[7], z_in[6], z_in[5], z_in[4], z_in[3], z_in[2], z_in[1], z_in[0]};
`ifdef SIMULATION
reg [15:0] r_z_out_r;
reg [0:15] r_z_oe = 16'h0000;
// reg [0:15] r_z_oe_dly = 16'h0000; //GE
reg [15:0] ram_blk [0:(1<<9)-1];
assign z_oe = r_z_oe;
// assign z_oe = r_z_oe_dly; //GE
assign z_out_r = r_z_out_r;
always @(posedge sys_clk)
begin
// r_z_oe_dly <= r_z_oe; //GE
r_z_oe <= (~cen & rw) ? 16'hffff : 16'h0000;
if (~cen) begin
if (~rw) begin
ram_blk[a_r][15:0] <= z_in_r;
end
r_z_out_r <= ram_blk[a_r][15:0];
end
end
`else
wire wren;
reg [0:15] r_z_oe = 16'h0000;
// reg [0:15] r_z_oe_dly = 16'h0000; //GE
assign z_oe = r_z_oe;
// assign z_oe = r_z_oe_dly; //GE
always @(posedge sys_clk)
begin
// r_z_oe_dly <= r_z_oe; //GE
r_z_oe <= (~cen & rw) ? 16'hffff : 16'h0000;
end
assign wren = (~cen & ~rw);
altsyncram altsyncram_component (
.wren_a (wren),
.clock0 (sys_clk),
.address_a (a_r),
.data_a (z_in_r),
.q_a (z_out_r),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 512,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 9,
altsyncram_component.width_a = 16,
altsyncram_component.width_byteena_a = 1;
`endif
endmodule
| 7.283799
|
module top (
input clk1,
clk2,
output led1,
led2
);
reg [15:0] counter1 = 0;
reg [15:0] counter2 = 0;
assign led1 = counter1[15];
assign led2 = counter2[15];
always @(posedge clk1) counter1 <= counter1 + 1;
always @(posedge clk2) counter2 <= counter2 + 1;
endmodule
| 7.233807
|
module $__PP3_DFFEPC_SYNCONLY (
output Q,
input D,
input CLK,
input EN,
);
dffepc ff (.Q(Q), .D(D), .CLK(CLK), .EN(EN), .PRE(1'b0), .CLR(1'b0));
endmodule
| 6.970665
|
module $__PP3_DFFEPC_SYNCONLY (
output Q,
input D,
input CLK,
input EN,
);
// For some reason ABC9 adds init attributes to wires even though they were removed before mapping.
// As a workaround, remove any init attributes that get reintroduced.
wire _TECHMAP_REMOVEINIT_Q_ = 1;
dffepc _TECHMAP_REPLACE_ (.Q(Q), .D(D), .CLK(CLK), .EN(EN), .PRE(1'b0), .CLR(1'b0));
endmodule
| 6.970665
|
module BUF(A, Y);
input A;
output Y = A;
endmodule
| 6.918193
|
module NOT(A, Y);
input A;
output Y = ~A;
endmodule
| 7.323172
|
module NAND(A, B, Y);
input A, B;
output Y = ~(A & B);
endmodule
| 7.167084
|
module NOR(A, B, Y);
input A, B;
output Y = ~(A | B);
endmodule
| 7.436332
|
module DFF (
C,
D,
Q
);
input C, D;
output reg Q;
always @(posedge C) Q <= D;
endmodule
| 7.813248
|
module DFFSR (
C,
D,
Q,
S,
R
);
input C, D, S, R;
output reg Q;
always @(posedge C, posedge S, posedge R)
if (S) Q <= 1'b1;
else if (R) Q <= 1'b0;
else Q <= D;
endmodule
| 6.733438
|
module VNOR (
out,
in0,
in1
);
input in0;
input in1;
output out;
//timing information, rise/fall and min:typ:max
specify
(in0 => out) = (0.260604: 0.513000: 0.955206, 0.255524: 0.503000: 0.936586);
(in1 => out) = (0.260604: 0.513000: 0.955206, 0.255524: 0.503000: 0.936586);
endspecify
nor (out, in0, in1);
endmodule
| 6.547684
|
module PDFF (
q,
qbar,
prebar,
clrbar,
d,
clk
);
input prebar, clrbar, d, clk;
output q, qbar;
wire o1, o2, o3, o4;
buf b1 (q, qq);
buf b2 (qbar, qqbar);
buf B3 (clr, clrbar);
buf B4 (pre, prebar);
buf B5 (ck, clk);
nand n1 (o1, pre, o2, o4), n2 (o2, clr, o1, ck), n3 (o3, ck, o4, o2), n4 (o4, clr, d, o3);
nand n5 (qq, pre, qqbar, o2), n6 (qqbar, clr, qq, o3);
endmodule
| 6.675725
|
module abl (
input clk,
input rdy,
input CI, // carry input
input cond, // condition code input
output CO, // carry output
input [7:0] DB, // Data Bus
input [7:0] REG, // output from register file
input [3:0] op, // operation
input ld_ahl, // indicates whether AHL should be loaded
input ld_pc, // indicates whether PCL should be loaded
input inc_pc, // indicates whether PCL should be incremented
output pcl_co, // Carry out from PCL
output [7:0] PCL, // Program Counter low
output [7:0] ADL // unregistered version of output
);
wire [7:0] AHL;
wire [7:0] ABL;
wire [7:0] base;
/*
* AHL register. The AHL (Address Hold Low register) is a temporary
* storage for DB input, most notably for use in 16 bit address
* fetches, such as in the absolute addressing modes.
*
* Sometimes the DB has to be held over multiple cycles, such as
* for JSR which fetches first operand byte before pushing old
* PC to the stack, and then fetches 2nd operand byte.
*/
reg8 ahl (
.clk(clk),
.EN (ld_ahl),
.RST(1'b0),
.D (DB),
.Q (AHL)
);
/*
* ABL logic has 2 stages. First stage selects a base register,
* 2nd stage adds an offset.
*
* There are a total of 6 useful combinations.
*
* operation | op[1:0] | application
* ===========|=========|================================
* PCL + 00 | 00 | PC restore
* REG + 00 | 01 | stack access or vector pull
* ABL + DB | 10 | take branch
* ABL + 00 | 01 | stay at current or move to next
* REG + DB | 10 | zeropage + index
* REG + AHL | 11 | abs + index
* ======================================================
*
*/
/*
* First stage. Select base value.
*
* casez( {cond, op[3:2]} )
* 3'b?00: base = 8'h00;
* 3'b?01: base = PCL;
* 3'b?10: base = AHL;
* 3'b011: base = 8'h00;
* 3'b111: base = DB;
* endcase
*/
mux8_3 #(
.INIT(64'haaccf000_00ccf000)
) adl_base_mux (
.O (base),
.I0(DB),
.I1(AHL),
.I2(PCL),
.op({cond, op[3:2]})
);
/*
* Second stage. Add offset.
*
* case( op[1:0] )
* 2'b00: {CO, ADL} = REG + CI;
* 2'b01: {CO, ADL} = base + REG + CI;
* 2'b10: {CO, ADL} = base + CI;
* 2'b11: {CO, ADL} = base + ABL + CI;
* endcase
*/
add8_3 #(
.INIT(64'h5aaa66cc_a0008800)
) abl_add (
.CI(CI),
.CO(CO),
.I0(base),
.I1(REG),
.I2(ABL),
.op(op[1:0]),
.O (ADL)
);
/*
* ABL register
*
* if( RDY )
* ABL <= ADL
*/
reg8 abl (
.clk(clk),
.EN (rdy),
.RST(1'b0),
.D (ADL),
.Q (ABL)
);
/*
* update PCL (program counter low)
*
* if( ld_pc )
* PCL <= ABL + inc_pc
*
*/
wire [7:0] PCL1;
inc8 pcl_inc (
.I (ABL),
.CI(inc_pc),
.O (PCL1),
.CO(pcl_co)
);
/*
* PCL register
*/
reg8 pcl (
.clk(clk),
.EN (ld_pc),
.RST(1'b0),
.D (PCL1),
.Q (PCL)
);
endmodule
| 8.30705
|
module ablk (
//**************************************
//Power Domain
//Input - Own Power Domain
//Output - N/A
//**************************************
//Signals
//Input
ABLK_PG, //Active High
ABLK_RESETn, //Active Low
ABLK_EN, //Active High
ABLK_CONFIG_0, //Config Bits
ABLK_CONFIG_1 //Config Bits
//Output
);
input ABLK_PG;
input ABLK_RESETn;
input ABLK_EN;
input [3:0] ABLK_CONFIG_0;
input [3:0] ABLK_CONFIG_1;
always @(ABLK_PG) begin
$write("%c[1;34m", 27);
$display("ablk Input ABLK_PG Has been changed to:%x", ABLK_PG);
$write("%c[0m", 27);
end
always @(ABLK_RESETn) begin
$write("%c[1;34m", 27);
$display("ablk Input ABLK_RESETn Has been changed to:%x", ABLK_RESETn);
$write("%c[0m", 27);
end
always @(ABLK_EN) begin
$write("%c[1;34m", 27);
$display("ablk Input ABLK_EN Has been changed to:%x", ABLK_EN);
$write("%c[0m", 27);
end
always @(ABLK_CONFIG_0) begin
$write("%c[1;34m", 27);
$display("ablk Input ABLK_CONFIG_0 Has been changed to:%x", ABLK_CONFIG_0);
$write("%c[0m", 27);
end
always @(ABLK_CONFIG_1) begin
$write("%c[1;34m", 27);
$display("ablk Input ABLK_CONFIG_1 Has been changed to:%x", ABLK_CONFIG_1);
$write("%c[0m", 27);
end
endmodule
| 6.797033
|
module ablProcessor (
clk,
rst,
out,
in
);
input clk;
input rst;
//ALU flags
wire ZERO;
wire NEG;
//board terminals
input [7:0] in;
output [7:0] out;
wire [7:0] OUTTERMINAL;
//GPRs
wire [7:0] A;
wire [7:0] B;
wire [7:0] C;
wire [7:0] D;
wire [7:0] effectiveAddress;
wire [7:0] nextAddress;
wire [15:0] instruction;
wire [2:0] branchOP;
wire [2:0] registerOP;
wire writeEnable;
wire [2:0] aluOP;
wire dataOP;
wire bypassData;
wire [7:0] multiplexOut;
wire [7:0] RA;
wire [7:0] RB;
wire [7:0] aluOut;
wire [7:0] dataOut;
branchUnit newAddress (
.clk(clk),
.rst(rst),
.BROP(branchOP),
.ZERO(ZERO),
.NEG(NEG),
.brAddr(instruction[7:0]),
.currAddr(nextAddress),
.effAddr(effectiveAddress)
);
programCounter PC (
.clk(clk),
.rst(rst),
.effAddr(effectiveAddress),
.currAddr(nextAddress)
);
instructionMem getInstruction (
.clk(clk),
.currAddr(nextAddress),
.inst(instruction)
);
instControl signalComp (
.opcode(instruction[15:12]),
.brx(instruction[11]),
.BROP(branchOP),
.REGOP(registerOP),
.WRITEREG(writeEnable),
.ALUOP(aluOP),
.DATAOP(dataOP),
.BYPASSMEM(bypassData)
);
registerMem getReg (
.rst(rst),
.clk(clk),
.regAddr1(instruction[11:10]),
.regAddr2(instruction[9:8]),
.immVal(instruction[7:0]),
.WRITEREG(writeEnable),
.REGOP(registerOP),
.readReg1(RA),
.readReg2(RB),
.inTerminal(in),
.outTerminal(OUTTERMINAL),
.outReg0(A),
.outReg1(B),
.outReg2(C),
.outReg3(D),
.wrData(multiplexOut)
);
assign out = OUTTERMINAL;
ALU numberCrunch (
.ALUOP(aluOP),
.readReg1(RA),
.readReg2(RB),
.resultALU(aluOut),
.ZERO(ZERO),
.NEG(NEG)
);
dataMem RAM (
.clk(clk),
.rst(rst),
.DATAOP(dataOP),
.useAddr(instruction[7:0]),
.readReg1(RA),
.dataOut(dataOut)
);
multiplexer2In dataORalu (
.resultData(dataOut),
.resultALU(aluOut),
.select(bypassData),
.dataOut(multiplexOut)
);
endmodule
| 7.002008
|
module abort_transaction (
input clock,
input reset,
input enb_abort_trans
);
endmodule
| 6.580103
|
module apb_interface (
Pwrite,
Penable,
Pselx,
Paddr,
Pwdata,
Pwrite_out,
Penable_out,
Pselx_out,
Paddr_out,
Pwdata_out,
Prdata
);
input Pwrite, Penable;
input [2:0] Pselx;
input [31:0] Paddr, Pwdata;
output Pwrite_out, Penable_out;
output [2:0] Pselx_out;
output [31:0] Paddr_out, Pwdata_out;
output reg [31:0] Prdata;
assign Pwrite_out = Pwrite;
assign Penable_out = Penable;
assign Pselx_out = Pselx;
assign Paddr_out = Paddr;
assign Pwdata_out = Pwdata;
always @(*) begin
if (!Pwrite && Penable) Prdata = {$random} % 256;
else Prdata = 32'h0;
end
endmodule
| 6.87051
|
module ABRCKT (
input ABAUD,
UxRX,
clk,
rst,
output UxRXIF,
output [7:0] out,
count
);
wire cnt_en, cnt_rst, ld_en;
ABRCKT_Controller cu (
ABAUD,
UxRX,
clk,
rst,
cnt_en,
cnt_rst,
UxRXIF,
ld_en
);
ABRCKT_Datapath dp (
cnt_en,
cnt_rst,
ld_en,
clk,
rst,
count,
out
);
endmodule
| 7.12077
|
module ABRCKT_TB ();
wire divide;
wire UxRXIF, up;
reg i8, i7, i6, i5, i4, i3, i2, i1;
reg down, load, preset, ABAUD, UxRX;
inverter #(5, 3) inv (
1'b1,
up
);
ABRCKT abrkct (
up,
ABAUD,
UxRX,
UxRXIF
);
divide_counter divv (
divide,
i8,
i7,
i6,
i5,
i4,
i3,
i2,
i1,
up,
down,
load,
preset
);
initial begin
i8 = 0;
i7 = 1;
i6 = 1;
i5 = 1;
i4 = 0;
i3 = 0;
i2 = 0;
i1 = 1;
down = 0;
load = 0;
preset = 0;
UxRX = 0;
ABAUD = 1;
////////
UxRX = 1;
UxRX = 0;
UxRX = 1;
UxRX = 0;
UxRX = 1;
UxRX = 0;
UxRX = 1;
UxRX = 0;
/////////
ABAUD = 0;
end
endmodule
| 6.716885
|
module absoluteCalculator (
in,
out
);
input [7:0] in;
output [7:0] out;
wire [7:0] complemented;
wire [7:0] fin;
complementor cmp0 (
in[0],
1'b0,
complemented[0],
fin[0]
); //complement all the bits
complementor cmp1 (
in[1],
fin[0],
complemented[1],
fin[1]
);
complementor cmp2 (
in[2],
fin[1],
complemented[2],
fin[2]
);
complementor cmp3 (
in[3],
fin[2],
complemented[3],
fin[3]
);
complementor cmp4 (
in[4],
fin[3],
complemented[4],
fin[4]
);
complementor cmp5 (
in[5],
fin[4],
complemented[5],
fin[5]
);
complementor cmp6 (
in[6],
fin[5],
complemented[6],
fin[6]
);
complementor cmp7 (
in[7],
fin[6],
complemented[7],
fin[7]
);
mux2x1_8bit m (
in,
complemented,
in[7],
out
); //select the complemented number if the most significant digit is 1
endmodule
| 6.705034
|
module AbsoluteDifference (
input wire [num_bits*window_size-1:0] in1,
input wire [num_bits*window_size-1:0] in2,
input wire clock,
input wire reset_n,
output wire [num_bits*window_size-1:0] out
);
parameter window_size = 5;
parameter num_bits = 8;
genvar i;
generate
for (i = 0; i < window_size; i = i + 1) begin : abs_dif
Subtractor #(num_bits) s1 (
.in1(in1[num_bits*i+:num_bits]),
.in2(in2[num_bits*i+:num_bits]),
.clock(clock),
.reset_n(reset_n),
.out(out[num_bits*i+:num_bits])
);
end
endgenerate
endmodule
| 8.677079
|
module absoluter (
input signed [15:0] in,
output wire signed [15:0] out
);
assign out = ~in + 16'b1;
endmodule
| 6.96513
|
module absolute_value #(
parameter DATA_WIDTH = 32
) (
//========== INPUT ==========
input wire signed [DATA_WIDTH - 1 : 0] data_in,
//========== OUTPUT ==========
output wire signed [DATA_WIDTH - 1 : 0] data_out
//========== IN/OUT ==========
);
wire signed [DATA_WIDTH - 1 : 0] data_sign_ext, data_tmp;
wire signed [DATA_WIDTH - 1 : 0] abs_value;
assign data_sign_ext = {(DATA_WIDTH) {data_in[DATA_WIDTH-1]}};
assign data_tmp = data_in ^ data_sign_ext;
assign abs_value = data_tmp - data_sign_ext;
assign data_out = abs_value;
endmodule
| 8.093701
|
module illustrates how an o_carry value can be calculated
// in an abstract fashion. This abstract version *includes* the
// functionality of the non-abstract clock, but also allows the
// counter to step forward much faster than simulation time.
//
// To Prove:
//
// 1. That o_carry still takes place anytime the counter rolls over.
//
// 2. That o_carry is never true on any other clock cycles.
//
// 3. That any time o_carry is true, the counter must be equal to zero.
//
// 4. That prior to any clock where o_carry is true, the counter must be
// equal to -1.
//
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2018, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory. Run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
`default_nettype none
//
module absoneup(i_clk, o_carry);
parameter [0:0] OPT_ABSTRACT = 1'b1;
input wire i_clk;
//
output reg o_carry;
reg [31:0] r_count;
wire [31:0] increment;
generate if (OPT_ABSTRACT)
begin : ABSTRACT_COUNTER
//
// Your logic goes here
//
end else begin : NO_ABSTRACTION
assign increment = 1'b1;
end endgenerate
initial r_count = 0;
initial o_carry = 0;
always @(posedge i_clk)
{ o_carry, r_count } <= r_count + increment;
`ifdef FORMAL
reg f_past_valid;
initial f_past_valid = 1'b0;
always @(posedge i_clk)
f_past_valid <= 1'b1;
//
// Your proof goes here
//
`endif
endmodule
| 7.388872
|
module abstract_fx_add #(
parameter BIT_W = 8,
parameter N = 64
) (
input clk,
input reset,
input start_fx,
input [BIT_W-1:0] x_in,
output fx_finish,
output [BIT_W-1:0] fx_out
);
reg [7:0] control_cnt;
always @(posedge clk or negedge reset)
if (!reset) control_cnt <= 0;
else if (start_fx) control_cnt <= 0;
else if (control_cnt < N) control_cnt <= control_cnt + 1'b1;
assign fx_finish = (control_cnt == N) ? 1'b1 : 1'b0;
function [BIT_W-1:0] subfx;
input [BIT_W-1:0] x;
begin
subfx = fx_i(x);
end
endfunction
reg [2*BIT_W-1:0] sum_acc;
always @(posedge clk or negedge reset)
if (!reset) sum_acc <= 0;
else if (control_cnt < N) sum_acc <= sum_acc + subfx(x_in);
assign fx_out = sum_acc[2*BIT_W-1:BIT_W];
endmodule
| 6.971395
|
module Abs_Diff_ALU (
Frame,
Window,
AD
);
input [31:0] Frame, Window;
output reg [31:0] AD;
always @(*) begin
if (Frame < Window) begin
AD <= Window - Frame;
end else begin
AD <= Frame - Window;
end
end
endmodule
| 7.878589
|
module abs_saturation (
input [7:0] signed_value,
output reg [6:0] result
);
//Definition for Variables in the module
//Load other module(s)
//Logical
always @(signed_value) begin
if ( signed_value[7])
//Negative number input
begin
if ( signed_value[6:0] == 7'b000_0000)
//-128
begin
result <= 7'h7f;
end else begin
result <= (~signed_value[6:0]) + 7'h01;
end
end else
//Positive number or zero input
begin
result <= signed_value[6:0];
end
end
endmodule
| 7.104895
|
module counter input
CLR: module counter input
out_num: output port for the counter module
OV: overflow flag
------------------------------------------------------
History:
01-06-2016: First Version by Garfield
***********************************************/
`timescale 10 ns/100 ps
//Simulation time assignment
//Insert the modules
module Abs_Saturation_test;
//defination for Variables
reg clk;
reg reset;
reg[7:0] cntr;
wire EN;
wire CLR;
wire[7:0] out_num;
wire OV;
wire[6:0] result;
//Connection to the modules
counter C1(.clk(clk), .Reset(reset), .EN(EN),
.CLR(CLR), .counter(out_num), .OV(OV));
abs_saturation A1(.signed_value(out_num), .result(result));
begin
assign EN = 1'b1;
assign CLR = 1'b0;
//Clock generation
initial
begin
clk = 0;
//Reset
forever
begin
#10 clk = !clk;
//Reverse the clock in each 10ns
end
end
//Reset operation
initial
begin
reset = 0;
//Reset enable
#14 reset = 1;
//Counter starts
end
//Couner as input
always @(posedge clk or reset)
begin
if ( !reset)
//reset statement: counter keeps at 0
begin
cntr <= 8'h00;
end
else
//Wroking, counter increasing
begin
cntr <= cntr + 8'h01;
end
end
end
endmodule
| 7.206611
|
module counter input
CLR: module counter input
out_num: output port for the counter module
OV: overflow flag
------------------------------------------------------
History:
12-18-2015: First Version by Garfield
***********************************************/
`timescale 10 ns/100 ps
//Simulation time assignment
//Insert the modules
module Abs_test;
//defination for Variables
reg clk;
reg reset;
reg[7:0] cntr;
wire EN;
wire CLR;
wire[7:0] out_num;
wire OV;
wire[6:0] result;
//Connection to the modules
counter C1(.clk(clk), .Reset(reset), .EN(EN),
.CLR(CLR), .counter(out_num), .OV(OV));
abs A1(.signed_value(out_num), .result(result));
begin
assign EN = 1'b1;
assign CLR = 1'b0;
//Clock generation
initial
begin
clk = 0;
//Reset
forever
begin
#10 clk = !clk;
//Reverse the clock in each 10ns
end
end
//Reset operation
initial
begin
reset = 0;
//Reset enable
#14 reset = 1;
//Counter starts
end
//Couner as input
always @(posedge clk or reset)
begin
if ( !reset)
//reset statement: counter keeps at 0
begin
cntr <= 8'h00;
end
else
//Wroking, counter increasing
begin
cntr <= cntr + 8'h01;
end
end
end
endmodule
| 7.206611
|
modules generate an output that is the absolute value of input.
//
//////////////////////////////////////////////////////////////////////////////////
module abs_val #(parameter R=14)
(
input signed [ R-1:0] in,
output [ R-2:0] out,
output [ R-1:0] outR,
);
wire signed [ R-1:0] tmp ;
assign tmp = &(in^{ 1'b0 , {R-2{1'b1}} } ) ? { 1'b0 , {R-1{1'b1}} } :
in[R-1] ? (~in[R-2:0]) + 1'b1 :
{ 1'b0 , in[R-2:0] } ;
assign out = tmp[R-2:0] ;
assign outR = tmp[R-1:0] ;
endmodule
| 8.349329
|
module DSEL4D (
output [7:0] out,
input en,
input en0,
input [7:0] dt0,
input en1,
input [7:0] dt1,
input en2,
input [7:0] dt2,
input en3,
input [7:0] dt3
);
wire [7:0] o = en0 ? dt0 : en1 ? dt1 : en2 ? dt2 : en3 ? dt3 : 8'h0;
assign out = en ? o : 8'h0;
endmodule
| 6.762864
|
module DSEL3D (
output [7:0] out,
input en,
input en0,
input [7:0] dt0,
input en1,
input [7:0] dt1,
input en2,
input [7:0] dt2
);
wire [7:0] o = en0 ? dt0 : en1 ? dt1 : en2 ? dt2 : 8'h0;
assign out = en ? o : 8'h0;
endmodule
| 7.040204
|
module AB_Reg (
Read_Data1,
CLK,
Reset,
Reg_AB_Out
);
input [31:0] Read_Data1;
input CLK, Reset;
output reg [31:0] Reg_AB_Out;
always @(posedge CLK) begin
if (Reset) Reg_AB_Out <= 0;
else Reg_AB_Out <= Read_Data1;
end
endmodule
| 7.325942
|
module ac (
input valid_i,
input [PHY_REG_ADDR_WIDTH - 1 : 0] rd_addr_i,
input opcode_i,
input [1:0] size_i,
input [VIRTUAL_ADDR_LEN - 1 : 0] addr_i,
output [EXCEPTION_CODE_WIDTH - 1 : 0] ecause_o,
output exception_valid_o
);
wire misalign_fault;
wire access_fault;
assign misalign_fault = (size_i == 2'b01 && addr_i[0] != 0) || // hw
(size_i == 2'b10 && addr_i[1:0] != 0) || // w
(size_i == 2'b11 && addr_i[2:0] != 0); // dw
assign access_fault = (rd_addr_i == '0);
assign ecause_o =
access_fault ? (opcode_i ? EXCEPTION_STORE_ACCESS_FAULT : EXCEPTION_LOAD_ACCESS_FAULT) :
misalign_fault ? (opcode_i ? EXCEPTION_STORE_ADDR_MISALIGNED : EXCEPTION_LOAD_ADDR_MISALIGNED) :
0;
assign exception_valid_o = valid_i & (misalign_fault);
endmodule
| 7.122194
|
module AC97Conf ( /*AUTOARG*/
// Outputs
ac97_out_slot1,
ac97_out_slot1_valid,
ac97_out_slot2,
ac97_out_slot2_valid,
// Inputs
ac97_bitclk,
rst_b,
ac97_strobe,
actrl_master_volume,
actrl_mic_volume,
actrl_line_in_volume,
actrl_cd_volume,
actrl_pcm_volume,
actrl_record_select,
actrl_record_gain
);
/* AC97 */
input ac97_bitclk;
input rst_b;
input ac97_strobe;
output wire [19:0] ac97_out_slot1;
output wire ac97_out_slot1_valid;
output wire [19:0] ac97_out_slot2;
output wire ac97_out_slot2_valid;
/* Configuration Input */
input [15:0] actrl_master_volume;
input [15:0] actrl_mic_volume;
input [15:0] actrl_line_in_volume;
input [15:0] actrl_cd_volume;
input [15:0] actrl_pcm_volume;
input [15:0] actrl_record_select;
input [15:0] actrl_record_gain;
reg ac97_out_slot1_valid_r;
reg [19:0] ac97_out_slot1_r;
reg ac97_out_slot2_valid_r;
reg [19:0] ac97_out_slot2_r;
assign ac97_out_slot1 = ac97_out_slot1_r;
assign ac97_out_slot1_valid = ac97_out_slot1_valid_r;
assign ac97_out_slot2 = ac97_out_slot2_r;
assign ac97_out_slot2_valid = ac97_out_slot2_valid_r;
reg [3:0] state = 4'h0;
reg [3:0] nextstate = 4'h0;
always @(*) begin
ac97_out_slot1_valid_r = 0;
ac97_out_slot1_r = 20'hxxxxx;
ac97_out_slot2_valid_r = 0;
ac97_out_slot2_r = 20'hxxxxx;
nextstate = state;
case (state)
4'h0: begin
ac97_out_slot1_valid_r = 1;
ac97_out_slot1_r = {1'b0 /* write */, 7'h00 /* reset */, 12'b0 /* reserved */};
ac97_out_slot2_valid_r = 1;
ac97_out_slot2_r = {16'h0, 4'h0};
nextstate = 4'h1;
end
4'h1: begin
ac97_out_slot1_valid_r = 1;
ac97_out_slot1_r = {1'b0 /* write */, 7'h02 /* master volume */, 12'b0 /* reserved */};
ac97_out_slot2_valid_r = 1;
ac97_out_slot2_r = {actrl_master_volume, 4'b0};
nextstate = 4'h2;
end
4'h2: begin
ac97_out_slot1_valid_r = 1;
ac97_out_slot1_r = {1'b0 /* write */, 7'h0E /* mic volume */, 12'b0 /* reserved */};
ac97_out_slot2_valid_r = 1;
ac97_out_slot2_r = {actrl_mic_volume, 4'b0};
nextstate = 4'h3;
end
4'h3: begin
ac97_out_slot1_valid_r = 1;
ac97_out_slot1_r = {1'b0 /* write */, 7'h10 /* line in volume */, 12'b0 /* reserved */};
ac97_out_slot2_valid_r = 1;
ac97_out_slot2_r = {actrl_line_in_volume, 4'b0};
nextstate = 4'h4;
end
4'h4: begin
ac97_out_slot1_valid_r = 1;
ac97_out_slot1_r = {1'b0 /* write */, 7'h12 /* cd volume */, 12'b0 /* reserved */};
ac97_out_slot2_valid_r = 1;
ac97_out_slot2_r = {actrl_cd_volume, 4'b0};
nextstate = 4'h5;
end
4'h5: begin
ac97_out_slot1_valid_r = 1;
ac97_out_slot1_r = {1'b0 /* write */, 7'h18 /* pcm volume */, 12'b0 /* reserved */};
ac97_out_slot2_valid_r = 1;
ac97_out_slot2_r = {actrl_pcm_volume, 4'b0};
nextstate = 4'h6;
end
4'h6: begin
ac97_out_slot1_valid_r = 1;
ac97_out_slot1_r = {1'b0 /* write */, 7'h1A /* record select */, 12'b0 /* reserved */};
ac97_out_slot2_valid_r = 1;
ac97_out_slot2_r = {actrl_record_select, 4'b0};
nextstate = 4'h7;
end
4'h7: begin
ac97_out_slot1_valid_r = 1;
ac97_out_slot1_r = {1'b0 /* write */, 7'h1C /* record gain */, 12'b0 /* reserved */};
ac97_out_slot2_valid_r = 1;
ac97_out_slot2_r = {actrl_record_gain, 4'b0};
nextstate = 4'h8;
end
4'h8: begin
ac97_out_slot1_valid_r = 1;
ac97_out_slot1_r = {1'b1 /* read */, 7'h7C /* vendor id 1 */, 12'b0 /* reserved */};
ac97_out_slot2_valid_r = 1;
ac97_out_slot2_r = 20'h00000;
nextstate = 4'h9;
end
4'h9: begin
ac97_out_slot1_valid_r = 1;
ac97_out_slot1_r = {1'b1 /* read */, 7'h7C /* vendor id 2 */, 12'b0 /* reserved */};
ac97_out_slot2_valid_r = 1;
ac97_out_slot2_r = 20'h00000;
nextstate = 4'h1;
end
endcase
end
always @(posedge ac97_bitclk or negedge rst_b) begin
if (!rst_b) begin
state <= 0;
end else if (ac97_strobe) begin
state <= nextstate;
end
end
endmodule
| 6.78364
|
module ac97test (
input CCLK,
input RST,
input BITCLK,
output AUDSDO,
output AUDSYNC,
output AUDRST,
input ap,
output reg ut
);
wire ready, frame_done, AUD_SDO, AUD_SYNC, AUD_RST, reset, CLKFX_OUT;
wire [ 7:0] cmd_addr;
wire [15:0] cmd_data;
wire [19:0] leftadc, rightadc, reg_status, status_data;
wire [19:0] leftdac, rightdac;
assign AUDSDO = AUD_SDO;
assign AUDSYNC = AUD_SYNC;
assign AUDRST = AUD_RST;
always begin
if (ap == 1) ut <= 1;
end
s6ac97 M0 (
CCLK,
RST,
cmd_vd,
left_vd,
right_vd,
BITCLK,
AUD_SDO,
AUD_SYNC,
AUD_RST,
leftdac,
rightdac,
cmd_addr,
cmd_data,
ready,
frame_done,
leftadc,
rightadc,
reg_status,
status_data
);
genac97 M1 (
CCLK,
RST,
ready,
frame_done,
leftadc,
rightadc,
reg_status,
status_data,
cmd_vd,
left_vd,
right_vd,
leftdac,
rightdac,
cmd_addr,
cmd_data
);
endmodule
| 6.763806
|
module genac97 (
input CCLK,
input rst,
input ready,
input frame_done,
input [19:0] leftadc,
input [19:0] rightadc,
input [19:0] reg_status,
input [19:0] status_data,
output reg cmd_vd,
output reg left_vd,
output reg right_vd,
output reg [19:0] leftdac,
output reg [19:0] rightdac,
output reg [7:0] cmd_addr,
output reg [15:0] cmd_data
);
reg set;
reg [4:0] state;
//reg rst = 0;
always @(posedge CCLK) begin
if (rst) begin
//reset registers
state = 0;
cmd_vd = 0;
left_vd = 0;
right_vd = 0;
leftdac = 0;
rightdac = 0;
cmd_addr = 0;
cmd_data = 0;
set = 0;
//rst = 1;
end else begin
case (state)
0: begin //Init State
//Check codec status after reset or power-on
if (ready) begin
cmd_addr = 8'h80 + 8'h26; //read + addr
cmd_vd = 1;
if (status_data[7:4] == 4'hF) //status = ready
state = 1;
end else state = 0;
end
1: begin //master volume
if (ready) begin
cmd_addr = 8'h02;
cmd_data = 16'h0000;
set = 1;
end else state = 1;
if (frame_done && set) begin
state = 2;
set = 0;
end
end
2: begin //Line-in gain
if (ready) begin
cmd_addr = 8'h10;
cmd_data = 16'h0000;
set = 1;
end else state = 2;
if (frame_done && set) begin
state = 3;
set = 0;
end
end
3: begin //Record Select
if (ready) begin
cmd_addr = 8'h1A;
cmd_data = 16'h0404;
set = 1;
end else state = 3;
if (frame_done && set) begin
state = 4;
set = 0;
end
end
4: begin //Record gain
if (ready) begin
cmd_addr = 8'h1C;
cmd_data = 16'h0000;
set = 1;
end else state = 4;
if (frame_done && set) begin
state = 5;
set = 0;
end
end
5: begin //Send ADC input data directly to DAC
if (ready) begin
cmd_addr = 8'h80;
cmd_vd = 0;
leftdac = leftadc;
rightdac = rightadc;
left_vd = 1;
right_vd = 1;
set = 1;
end
if (frame_done && set) begin
set = 0;
end
end
endcase
end
end
endmodule
| 7.197212
|
module ac97_asfifo #(
parameter DATA_WIDTH = 8,
ADDRESS_WIDTH = 4,
FIFO_DEPTH = (1 << ADDRESS_WIDTH)
)
//Reading port
(
output wire [DATA_WIDTH-1:0] Data_out,
output reg Empty_out,
input wire ReadEn_in,
input wire RClk,
//Writing port.
input wire [DATA_WIDTH-1:0] Data_in,
output reg Full_out,
input wire WriteEn_in,
input wire WClk,
input wire Clear_in
);
/////Internal connections & variables//////
reg [DATA_WIDTH-1:0] Mem[FIFO_DEPTH-1:0];
wire [ADDRESS_WIDTH-1:0] pNextWordToWrite, pNextWordToRead;
wire EqualAddresses;
wire NextWriteAddressEn, NextReadAddressEn;
wire Set_Status, Rst_Status;
reg Status;
wire PresetFull, PresetEmpty;
//////////////Code///////////////
//Data ports logic:
//(Uses a dual-port RAM).
//'Data_out' logic:
assign Data_out = Mem[pNextWordToRead];
// always @ (posedge RClk)
// if (!PresetEmpty)
// Data_out <= Mem[pNextWordToRead];
// if (ReadEn_in & !Empty_out)
//'Data_in' logic:
always @(posedge WClk) if (WriteEn_in & !Full_out) Mem[pNextWordToWrite] <= Data_in;
//Fifo addresses support logic:
//'Next Addresses' enable logic:
assign NextWriteAddressEn = WriteEn_in & ~Full_out;
assign NextReadAddressEn = ReadEn_in & ~Empty_out;
//Addreses (Gray counters) logic:
ac97_graycounter #(
.COUNTER_WIDTH(ADDRESS_WIDTH)
) GrayCounter_pWr (
.GrayCount_out(pNextWordToWrite),
.Enable_in(NextWriteAddressEn),
.Clear_in(Clear_in),
.Clk(WClk)
);
ac97_graycounter #(
.COUNTER_WIDTH(ADDRESS_WIDTH)
) GrayCounter_pRd (
.GrayCount_out(pNextWordToRead),
.Enable_in(NextReadAddressEn),
.Clear_in(Clear_in),
.Clk(RClk)
);
//'EqualAddresses' logic:
assign EqualAddresses = (pNextWordToWrite == pNextWordToRead);
//'Quadrant selectors' logic:
assign Set_Status = (pNextWordToWrite[ADDRESS_WIDTH-2] ~^ pNextWordToRead[ADDRESS_WIDTH-1]) &
(pNextWordToWrite[ADDRESS_WIDTH-1] ^ pNextWordToRead[ADDRESS_WIDTH-2]);
assign Rst_Status = (pNextWordToWrite[ADDRESS_WIDTH-2] ^ pNextWordToRead[ADDRESS_WIDTH-1]) &
(pNextWordToWrite[ADDRESS_WIDTH-1] ~^ pNextWordToRead[ADDRESS_WIDTH-2]);
//'Status' latch logic:
always @(Set_Status, Rst_Status, Clear_in) //D Latch w/ Asynchronous Clear & Preset.
if (Rst_Status | Clear_in) Status = 0; //Going 'Empty'.
else if (Set_Status) Status = 1; //Going 'Full'.
//'Full_out' logic for the writing port:
assign PresetFull = Status & EqualAddresses; //'Full' Fifo.
always @(posedge WClk, posedge PresetFull) //D Flip-Flop w/ Asynchronous Preset.
if (PresetFull) Full_out <= 1;
else Full_out <= 0;
//'Empty_out' logic for the reading port:
assign PresetEmpty = ~Status & EqualAddresses; //'Empty' Fifo.
always @(posedge RClk, posedge PresetEmpty) //D Flip-Flop w/ Asynchronous Preset.
if (PresetEmpty) Empty_out <= 1;
else Empty_out <= 0;
endmodule
| 7.962302
|
module ac97_cra (
clk,
rst,
crac_we,
crac_din,
crac_out,
crac_wr_done,
crac_rd_done,
valid,
out_slt1,
out_slt2,
in_slt2,
crac_valid,
crac_wr
);
input clk, rst;
input crac_we;
output [15:0] crac_din;
input [31:0] crac_out;
output crac_wr_done, crac_rd_done;
input valid;
output [19:0] out_slt1;
output [19:0] out_slt2;
input [19:0] in_slt2;
output crac_valid;
output crac_wr;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg crac_wr;
reg crac_rd;
reg crac_rd_done;
reg [15:0] crac_din;
reg crac_we_r;
reg valid_r;
wire valid_ne;
wire valid_pe;
reg rdd1, rdd2, rdd3;
////////////////////////////////////////////////////////////////////
//
// Codec Register Data Path
//
// Control
assign out_slt1[19] = crac_out[31];
assign out_slt1[18:12] = crac_out[22:16];
assign out_slt1[11:0] = 12'h0;
// Write Data
assign out_slt2[19:4] = crac_out[15:0];
assign out_slt2[3:0] = 4'h0;
// Read Data
always @(posedge clk or negedge rst) begin
if (!rst) crac_din <= #1 16'h0;
else if (crac_rd_done) crac_din <= #1 in_slt2[19:4];
end
////////////////////////////////////////////////////////////////////
//
// Codec Register Access Tracking
//
assign crac_valid = crac_wr | crac_rd;
always @(posedge clk) crac_we_r <= #1 crac_we;
always @(posedge clk or negedge rst)
if (!rst) crac_wr <= #1 1'b0;
else if (crac_we_r & !crac_out[31]) crac_wr <= #1 1'b1;
else if (valid_ne) crac_wr <= #1 1'b0;
assign crac_wr_done = crac_wr & valid_ne;
always @(posedge clk or negedge rst)
if (!rst) crac_rd <= #1 1'b0;
else if (crac_we_r & crac_out[31]) crac_rd <= #1 1'b1;
else if (rdd1 & valid_pe) crac_rd <= #1 1'b0;
always @(posedge clk or negedge rst)
if (!rst) rdd1 <= #1 1'b0;
else if (crac_rd & valid_ne) rdd1 <= #1 1'b1;
else if (!crac_rd) rdd1 <= #1 1'b0;
always @(posedge clk or negedge rst)
if (!rst) rdd2 <= #1 1'b0;
else if ((crac_rd & valid_ne) | (!rdd3 & rdd2)) rdd2 <= #1 1'b1;
else if (crac_rd_done) rdd2 <= #1 1'b0;
always @(posedge clk or negedge rst)
if (!rst) rdd3 <= #1 1'b0;
else if (rdd2 & valid_pe) rdd3 <= #1 1'b1;
else if (crac_rd_done) rdd3 <= #1 1'b0;
always @(posedge clk) crac_rd_done <= #1 rdd3 & valid_pe;
always @(posedge clk) valid_r <= #1 valid;
assign valid_ne = !valid & valid_r;
assign valid_pe = valid & !valid_r;
endmodule
| 7.357009
|
module ac97_dma (
input sys_rst,
input sys_clk,
output reg [31:0] wbm_adr_o,
output [2:0] wbm_cti_o,
output reg wbm_we_o,
output wbm_cyc_o,
output wbm_stb_o,
input wbm_ack_i,
input [31:0] wbm_dat_i,
output [31:0] wbm_dat_o,
output reg down_en,
input down_next_frame,
output reg down_pcmleft_valid,
output reg [19:0] down_pcmleft,
output reg down_pcmright_valid,
output reg [19:0] down_pcmright,
output reg up_en,
input up_next_frame,
input up_frame_valid,
input up_pcmleft_valid,
input [19:0] up_pcmleft,
input up_pcmright_valid,
input [19:0] up_pcmright,
/* in 32-bit words */
input dmar_en,
input [29:0] dmar_addr,
input [15:0] dmar_remaining,
output reg dmar_next,
input dmaw_en,
input [29:0] dmaw_addr,
input [15:0] dmaw_remaining,
output reg dmaw_next
);
assign wbm_cti_o = 3'd0;
reg wbm_strobe;
assign wbm_cyc_o = wbm_strobe;
assign wbm_stb_o = wbm_strobe;
reg load_read_addr;
reg load_write_addr;
always @(posedge sys_clk) begin
if (load_read_addr) wbm_adr_o <= {dmar_addr, 2'b00};
else if (load_write_addr) wbm_adr_o <= {dmaw_addr, 2'b00};
end
reg load_downpcm;
always @(posedge sys_clk) begin
if (load_downpcm) begin
down_pcmleft_valid <= dmar_en;
down_pcmright_valid <= dmar_en;
down_pcmleft <= {20{dmar_en}} & {{wbm_dat_i[31:16], wbm_dat_i[30:27]}};
down_pcmright <= {20{dmar_en}} & {{wbm_dat_i[15:0], wbm_dat_i[14:11]}};
end
end
assign wbm_dat_o = {up_pcmleft[19:4], up_pcmright[19:4]};
reg [2:0] state;
reg [2:0] next_state;
parameter IDLE = 3'd0;
parameter DMAR = 3'd1;
parameter DMAW = 3'd2;
parameter NEXTDFRAME = 3'd3;
parameter NEXTUFRAME = 3'd4;
wire dmar_finished = dmar_remaining == 16'd0;
wire dmaw_finished = dmaw_remaining == 16'd0;
always @(posedge sys_clk) begin
if (sys_rst) state <= IDLE;
else state <= next_state;
//$display("state:%d->%d %b %b %b", state, next_state, down_next_frame, dmar_en, ~dmar_finished);
end
always @(*) begin
next_state = state;
wbm_strobe = 1'b0;
load_read_addr = 1'b0;
load_write_addr = 1'b0;
wbm_we_o = 1'b0;
down_en = 1'b0;
up_en = 1'b0;
dmar_next = 1'b0;
dmaw_next = 1'b0;
load_downpcm = 1'b0;
case (state)
IDLE: begin
down_en = 1'b1;
up_en = 1'b1;
if (down_next_frame) begin
if (dmar_en) down_en = 1'b0;
else load_downpcm = 1'b1;
end
if (up_next_frame) begin
if (dmaw_en) up_en = 1'b0;
end
if (down_next_frame & dmar_en & ~dmar_finished) begin
load_read_addr = 1'b1;
next_state = DMAR;
end else if (up_next_frame & dmaw_en & ~dmaw_finished) begin
load_write_addr = 1'b1;
next_state = DMAW;
end
end
DMAR: begin
wbm_strobe = 1'b1;
load_downpcm = 1'b1;
if (wbm_ack_i) begin
dmar_next = 1'b1;
next_state = NEXTDFRAME;
end
end
DMAW: begin
wbm_strobe = 1'b1;
wbm_we_o = 1'b1;
if (wbm_ack_i) begin
dmaw_next = 1'b1;
next_state = NEXTUFRAME;
end
end
NEXTDFRAME: begin
down_en = 1'b1;
next_state = IDLE;
end
NEXTUFRAME: begin
up_en = 1'b1;
next_state = IDLE;
end
endcase
end
endmodule
| 6.624284
|
module ac97_graycounter #(
parameter COUNTER_WIDTH = 2
) (
output reg [COUNTER_WIDTH-1:0] GrayCount_out, //'Gray' code count output.
input wire Enable_in, //Count enable.
input wire Clear_in, //Count reset.
input wire Clk
);
/////////Internal connections & variables///////
reg [COUNTER_WIDTH-1:0] BinaryCount;
/////////Code///////////////////////
always @(posedge Clk)
if (Clear_in) begin
BinaryCount <= {COUNTER_WIDTH{1'b0}} + 1; //Gray count begins @ '1' with
GrayCount_out <= {COUNTER_WIDTH{1'b0}}; // first 'Enable_in'.
end else if (Enable_in) begin
BinaryCount <= BinaryCount + 1;
GrayCount_out <= {
BinaryCount[COUNTER_WIDTH-1],
BinaryCount[COUNTER_WIDTH-2:0] ^ BinaryCount[COUNTER_WIDTH-1:1]
};
end
endmodule
| 7.154606
|
module ac97_if (
input ClkIn,
input Reset,
input [15:0] PCM_Playback_Left,
input [15:0] PCM_Playback_Right,
output wire [15:0] PCM_Record_Left,
output wire [15:0] PCM_Record_Right,
output wire PCM_Record_Valid,
output wire PCM_Playback_Accept,
output wire AC97Reset_n,
input AC97Clk,
output wire Sync,
output wire SData_Out,
input SData_In
);
// synthesis translate_off
reg resetState;
assign AC97Reset_n = 1'b1;
assign Sync = 1'b0;
assign SData_Out = 1'b0;
initial begin
resetState = 1'b1;
// Delay two clock posedges
@(posedge ClkIn);
@(posedge ClkIn);
resetState = 1'b0;
end
wire [7:0] cycles_current;
dffr #(8) cycles_ff (
.clk(ClkIn),
.r (resetState),
.d (cycles_current + 8'b1),
.q (cycles_current)
);
assign PCM_Playback_Accept = cycles_current[4];
// The following is merely keeping state so that we can display an error
// message if we change the input to the codec at the wrong time!
wire New_Frame_previous;
wire new_frame_one_pulse;
dffr #(1) new_frame_latch (
.clk(ClkIn),
.r (resetState),
.d (PCM_Playback_Accept),
.q (New_Frame_previous)
);
assign new_frame_one_pulse = ~New_Frame_previous && PCM_Playback_Accept;
wire [31:0] previous_latched_sample;
dffre #(32) latched_sample (
.clk(ClkIn),
.r (resetState),
.en (new_frame_one_pulse),
.d ({PCM_Playback_Left, PCM_Playback_Right}),
.q (previous_latched_sample)
);
always @(posedge ClkIn)
if (~new_frame_one_pulse && {PCM_Playback_Left, PCM_Playback_Right} != previous_latched_sample)
$display("ERROR: you are changing the inputs to the codec at the wrong time!");
// Generate a SND file with the audio data
integer file, samplecount;
initial begin
// Open the output file. GENERATES_SND (a player is auto-launched)
file = $fopen("audio.snd", "wb");
$display("Audio out: sound file audio.snd opened for output.");
// Write the SND header. It consists of 6 32-bit, big-endian words, and
// is followed by four 8-bit zero bytes to signify no annotations.
// 0: Magic number: ASCII ".snd"
// 1: Offset of the audio data in bytes: 28
// 2: Data size: unknown -> all F's
// 3: Encoding format: 3 = 16-bit linear PCM
// 4: Sample rate: 48KHz = 0xBB80
// 5: Number of channels: 2
// (6): No annotations: 0
$fwrite(file, ".snd%u%u%u%u%u%u", 32'h1C_00_00_00, 32'hFF_FF_FF_FF, 32'h03_00_00_00,
32'h80_BB_00_00, 32'h02_00_00_00, 32'h00_00_00_00);
// After this is all the PCM data, stored in big-endian format.
samplecount = 0;
forever begin
// Wait for a new sample
@(posedge new_frame_one_pulse);
// Output the sample data (16-bit big-endian, left then right)
$fwrite(file, "%u", {PCM_Playback_Right[7:0], PCM_Playback_Right[15:8],
PCM_Playback_Left[7:0], PCM_Playback_Left[15:8]});
samplecount = samplecount + 1;
if (samplecount && samplecount % 48000 == 0)
$display("[%0t] Audio out: generated %0d seconds.", $time, samplecount / 48000);
end
end
// synthesis translate_on
endmodule
| 7.762818
|
module ac97_sin (
clk,
rst,
out_le,
slt0,
slt1,
slt2,
slt3,
slt4,
slt6,
sdata_in
);
input clk, rst;
// --------------------------------------
// Misc Signals
input [5:0] out_le;
output [15:0] slt0;
output [19:0] slt1;
output [19:0] slt2;
output [19:0] slt3;
output [19:0] slt4;
output [19:0] slt6;
// --------------------------------------
// AC97 Codec Interface
input sdata_in;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg sdata_in_r;
reg [19:0] sr;
reg [15:0] slt0;
reg [19:0] slt1;
reg [19:0] slt2;
reg [19:0] slt3;
reg [19:0] slt4;
reg [19:0] slt6;
////////////////////////////////////////////////////////////////////
//
// Output Registers
//
always @(posedge clk) if (out_le[0]) slt0 <= #1 sr[15:0];
always @(posedge clk) if (out_le[1]) slt1 <= #1 sr;
always @(posedge clk) if (out_le[2]) slt2 <= #1 sr;
always @(posedge clk) if (out_le[3]) slt3 <= #1 sr;
always @(posedge clk) if (out_le[4]) slt4 <= #1 sr;
always @(posedge clk) if (out_le[5]) slt6 <= #1 sr;
////////////////////////////////////////////////////////////////////
//
// Serial Shift Register
//
always @(negedge clk) sdata_in_r <= #1 sdata_in;
always @(posedge clk) sr <= #1{sr[18:0], sdata_in_r};
endmodule
| 6.754416
|
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