code
stringlengths 35
6.69k
| score
float64 6.5
11.5
|
|---|---|
module eight_bit_adder (
x,
y,
carry_in,
sum,
carry_out
);
input [7:0] x;
input [7:0] y;
input carry_in;
output [7:0] sum;
wire [7:0] sum;
output carry_out;
wire carry_out;
wire [6:0] intermediate_carry;
one_bit_full_adder FA0 (
x[0],
y[0],
carry_in,
sum[0],
intermediate_carry[0]
);
one_bit_full_adder FA1 (
x[1],
y[1],
intermediate_carry[0],
sum[1],
intermediate_carry[1]
);
one_bit_full_adder FA2 (
x[2],
y[2],
intermediate_carry[1],
sum[2],
intermediate_carry[2]
);
one_bit_full_adder FA3 (
x[3],
y[3],
intermediate_carry[2],
sum[3],
intermediate_carry[3]
);
one_bit_full_adder FA4 (
x[4],
y[4],
intermediate_carry[3],
sum[4],
intermediate_carry[4]
);
one_bit_full_adder FA5 (
x[5],
y[5],
intermediate_carry[4],
sum[5],
intermediate_carry[5]
);
one_bit_full_adder FA6 (
x[6],
y[6],
intermediate_carry[5],
sum[6],
intermediate_carry[6]
);
one_bit_full_adder FA7 (
x[7],
y[7],
intermediate_carry[6],
sum[7],
carry_out
);
endmodule
| 7.124161
|
module eight_bit_adder_top;
reg [7:0] A;
reg [7:0] B;
reg Cin;
wire [7:0] Sum;
wire Carry;
eight_bit_adder ADDER (
A,
B,
Cin,
Sum,
Carry
);
always @(A or B or Cin or Sum or Carry) begin
$display("time=%d: A = %d, B = %d, Cin = %d, Sum = %d, Carry = %d", $time, A, B, Cin, Sum,
Carry);
end
initial begin
#100 $finish;
end
initial begin
A = 100;
B = 100;
Cin = 1;
#1 $display("\n");
A = 50;
B = 60;
Cin = 0;
#1 $display("\n");
A = 200;
B = 200;
Cin = 0;
#1 $display("\n");
A = 10;
B = 10;
Cin = 1;
#1 $display("\n");
A = 1;
B = 2;
Cin = 0;
#1 $display("\n");
A = 20;
B = 0;
Cin = 0;
#1 $display("\n");
A = 0;
B = 0;
Cin = 1;
#1 $display("\n");
A = 255;
B = 255;
Cin = 0;
#1 $display("\n");
A = 20;
B = 200;
Cin = 0;
#1 $display("\n");
A = 5;
B = 6;
Cin = 1;
end
endmodule
| 7.124161
|
module one_bit_adder (
a,
b,
c_in,
sum,
c_out
);
input a, b, c_in;
output wire sum, c_out;
// full adder logic for a single bit
assign sum = a ^ b ^ c_in;
assign c_out = (a & b) || (b & c_in) || (a & c_in);
endmodule
| 6.839629
|
module one_bit_full_adder (
a,
b,
cin,
sum,
cout
);
input a;
input b;
input cin;
output sum;
wire sum;
output cout;
wire cout;
assign sum = cin ^ (a ^ b);
assign cout = ((a & b) | (b & cin) | (a & cin));
endmodule
| 6.938543
|
module eight_bit_comparator (
x,
y,
greater,
less,
equal
);
input [7:0] x;
input [7:0] y;
output wire greater;
output wire less;
output wire equal;
wire [7:0] inter_equal;
wire [7:0] inter_greater;
wire [7:0] inter_less;
assign inter_equal[7] = 1;
assign inter_greater[7] = 0;
assign inter_less[7] = 0;
one_bit_full_comparator FA7 (
x[7],
y[7],
inter_greater[6],
inter_less[6],
inter_equal[6],
inter_greater[7],
inter_less[7],
inter_equal[7]
);
one_bit_full_comparator FA6 (
x[6],
y[6],
inter_greater[5],
inter_less[5],
inter_equal[5],
inter_greater[6],
inter_less[6],
inter_equal[6]
);
one_bit_full_comparator FA5 (
x[5],
y[5],
inter_greater[4],
inter_less[4],
inter_equal[4],
inter_greater[5],
inter_less[5],
inter_equal[5]
);
one_bit_full_comparator FA4 (
x[4],
y[4],
inter_greater[3],
inter_less[3],
inter_equal[3],
inter_greater[4],
inter_less[4],
inter_equal[4]
);
one_bit_full_comparator FA3 (
x[3],
y[3],
inter_greater[2],
inter_less[2],
inter_equal[2],
inter_greater[3],
inter_less[3],
inter_equal[3]
);
one_bit_full_comparator FA2 (
x[2],
y[2],
inter_greater[1],
inter_less[1],
inter_equal[1],
inter_greater[2],
inter_less[2],
inter_equal[2]
);
one_bit_full_comparator FA1 (
x[1],
y[1],
inter_greater[0],
inter_less[0],
inter_equal[0],
inter_greater[1],
inter_less[1],
inter_equal[1]
);
one_bit_full_comparator FA0 (
x[0],
y[0],
greater,
less,
equal,
inter_greater[0],
inter_less[0],
inter_equal[0]
);
endmodule
| 7.255245
|
module eight_bit_comparator_top;
reg [7:0] A;
reg [7:0] B;
wire Greater;
wire Less;
wire Equal;
eight_bit_comparator COMPARE (
A,
B,
Greater,
Less,
Equal
);
always @(A or B or Greater or Equal or Less) begin
$display("time=%d: A = %d, B = %d, Greater = %d, Less = %d, Equal = %d", $time, A, B, Greater,
Less, Equal);
end
initial begin
#100 $finish;
end
initial begin
A = 100;
B = 100;
#1 $display("\n");
A = 50;
B = 60;
#1 $display("\n");
A = 32;
B = 31;
#1 $display("\n");
A = 255;
B = 255;
#1 $display("\n");
A = 0;
B = 255;
#1 $display("\n");
A = 31;
B = 128;
#1 $display("\n");
A = 26;
B = 75;
#1 $display("\n");
A = 99;
B = 100;
#1 $display("\n");
A = 235;
B = 200;
#1 $display("\n");
A = 6;
B = 6;
end
endmodule
| 7.255245
|
module one_bit_full_comparator (
a,
b,
greater,
less,
equal,
prev_greater,
prev_less,
prev_equal
);
input a;
input b;
input prev_greater;
input prev_less;
input prev_equal;
output wire greater;
output wire less;
output wire equal;
assign greater = prev_greater | (prev_equal & a & (~b));
assign less = prev_less | (prev_equal & b & (~a));
assign equal = prev_equal & (((~a) & (~b)) | (a & b));
endmodule
| 6.938543
|
module MUX (
input wire [15:0] i0,
i1,
input wire s,
output wire [15:0] MUX_o
);
mux2 m0 (
i0[0],
i1[0],
s,
MUX_o[0]
);
mux2 m1 (
i0[1],
i1[1],
s,
MUX_o[1]
);
mux2 m2 (
i0[2],
i1[2],
s,
MUX_o[2]
);
mux2 m3 (
i0[3],
i1[3],
s,
MUX_o[3]
);
mux2 m4 (
i0[4],
i1[4],
s,
MUX_o[4]
);
mux2 m5 (
i0[5],
i1[5],
s,
MUX_o[5]
);
mux2 m6 (
i0[6],
i1[6],
s,
MUX_o[6]
);
mux2 m7 (
i0[7],
i1[7],
s,
MUX_o[7]
);
mux2 m8 (
i0[8],
i1[8],
s,
MUX_o[8]
);
mux2 m9 (
i0[9],
i1[9],
s,
MUX_o[9]
);
mux2 m10 (
i0[10],
i1[10],
s,
MUX_o[10]
);
mux2 m11 (
i0[11],
i1[11],
s,
MUX_o[11]
);
mux2 m12 (
i0[12],
i1[12],
s,
MUX_o[12]
);
mux2 m13 (
i0[13],
i1[13],
s,
MUX_o[13]
);
mux2 m14 (
i0[14],
i1[14],
s,
MUX_o[14]
);
mux2 m15 (
i0[15],
i1[15],
s,
MUX_o[15]
);
endmodule
| 7.716553
|
module FA (
input wire a,
b,
c,
output s,
carr
);
xor3 x3 (
a,
b,
c,
s
);
wire t1, t2, t3;
and2 ab (
a,
b,
t1
);
and2 bc (
b,
c,
t2
);
and2 ac (
a,
c,
t3
);
or3 carry (
t1,
t2,
t3,
carr
);
endmodule
| 8.362615
|
module OneBitAddSub (
input a,
b,
c,
addsub,
output sum,
carr
);
wire t;
xor2 b_x (
b,
addsub,
t
);
FA s_c (
a,
t,
c,
sum,
carr
);
endmodule
| 7.455969
|
module invert (
input wire i,
output wire o
);
assign o = !i;
endmodule
| 7.953624
|
module and2 (
input wire i0,
i1,
output wire o
);
assign o = i0 & i1;
endmodule
| 8.35921
|
module or2 (
input wire i0,
i1,
output wire o
);
assign o = i0 | i1;
endmodule
| 8.541431
|
module xor2 (
input wire i0,
i1,
output wire o
);
assign o = i0 ^ i1;
endmodule
| 8.782532
|
module nand2 (
input wire i0,
i1,
output wire o
);
wire t;
and2 and2_0 (
i0,
i1,
t
);
invert invert_0 (
t,
o
);
endmodule
| 7.360689
|
module nor2 (
input wire i0,
i1,
output wire o
);
wire t;
or2 or2_0 (
i0,
i1,
t
);
invert invert_0 (
t,
o
);
endmodule
| 7.781479
|
module xnor2 (
input wire i0,
i1,
output wire o
);
wire t;
xor2 xor2_0 (
i0,
i1,
t
);
invert invert_0 (
t,
o
);
endmodule
| 7.523861
|
module and3 (
input wire i0,
i1,
i2,
output wire o
);
wire t;
and2 and2_0 (
i0,
i1,
t
);
and2 and2_1 (
i2,
t,
o
);
endmodule
| 7.185291
|
module or3 (
input wire i0,
i1,
i2,
output wire o
);
wire t;
or2 or2_0 (
i0,
i1,
t
);
or2 or2_1 (
i2,
t,
o
);
endmodule
| 7.924047
|
module nor3 (
input wire i0,
i1,
i2,
output wire o
);
wire t;
or2 or2_0 (
i0,
i1,
t
);
nor2 nor2_0 (
i2,
t,
o
);
endmodule
| 7.838557
|
module nand3 (
input wire i0,
i1,
i2,
output wire o
);
wire t;
and2 and2_0 (
i0,
i1,
t
);
nand2 nand2_1 (
i2,
t,
o
);
endmodule
| 7.036906
|
module xor3 (
input wire i0,
i1,
i2,
output wire o
);
wire t;
xor2 xor2_0 (
i0,
i1,
t
);
xor2 xor2_1 (
i2,
t,
o
);
endmodule
| 8.362259
|
module xnor3 (
input wire i0,
i1,
i2,
output wire o
);
wire t;
xor2 xor2_0 (
i0,
i1,
t
);
xnor2 xnor2_0 (
i2,
t,
o
);
endmodule
| 7.872322
|
module mux2 (
input wire i0,
i1,
j,
output wire o
);
assign o = (j == 0) ? i0 : i1;
endmodule
| 7.816424
|
module mux8 (
input wire [0:7] i,
input wire j2,
j1,
j0,
output wire o
);
wire t0, t1;
mux4 mux4_0 (
i[0:3],
j2,
j1,
t0
);
mux4 mux4_1 (
i[4:7],
j2,
j1,
t1
);
mux2 mux2_0 (
t0,
t1,
j0,
o
);
endmodule
| 7.606032
|
module a23_gc_main #(
// mem size in words (32bit)
parameter CODE_MEM_SIZE = 64, //Code: 0x00000000
parameter G_MEM_SIZE = 64, //AdrGarbler: 0x01000000
parameter E_MEM_SIZE = 64, //AdrEvaluator: 0x02000000
parameter OUT_MEM_SIZE = 64, //AdrOut: 0x03000000
parameter STACK_MEM_SIZE = 64 //AdrStack: 0x04000000
) (
input clk,
input rst,
input [CODE_MEM_SIZE*32-1:0] p_init,
input [G_MEM_SIZE *32-1:0] g_init,
input [E_MEM_SIZE *32-1:0] e_init,
output [OUT_MEM_SIZE *32-1:0] o,
output terminate
);
wire [31:0] m_address;
wire [31:0] m_write;
wire m_write_en;
wire [ 3:0] m_byte_enable;
wire [31:0] m_read;
a23_core u_a23_core (
.i_clk (clk),
.i_rst (rst),
.o_m_address (m_address),
.o_m_write (m_write),
.o_m_write_en (m_write_en),
.o_m_byte_enable(m_byte_enable),
.i_m_read (m_read),
.terminate (terminate)
);
a23_mem #(
.CODE_MEM_SIZE (CODE_MEM_SIZE),
.G_MEM_SIZE (G_MEM_SIZE),
.E_MEM_SIZE (E_MEM_SIZE),
.OUT_MEM_SIZE (OUT_MEM_SIZE),
.STACK_MEM_SIZE(STACK_MEM_SIZE)
) u_a23_mem (
.i_clk(clk),
.i_rst(rst),
.p_init(p_init),
.g_init(g_init),
.e_init(e_init),
.o (o),
.i_m_address (m_address),
.i_m_write (m_write),
.i_m_write_en (m_write_en),
.i_m_byte_enable(m_byte_enable),
.o_m_read (m_read)
);
endmodule
| 6.935551
|
module a23_testbench();
localparam CODE_MEM_SIZE = 64; //_start: 0x00000000
localparam G_MEM_SIZE = 64; //AdrAliceX: 0x01000000
localparam E_MEM_SIZE = 64; //AdrBobY: 0x02000000
localparam OUT_MEM_SIZE = 64; //AdrOutZ: 0x03000000
localparam STACK_MEM_SIZE = 64; //AdrStack: 0x04000100
localparam TEST_NAME = "sum";
reg clk;
reg rst;
wire [CODE_MEM_SIZE*32-1:0] p_init;
wire [G_MEM_SIZE *32-1:0] g_init;
wire [E_MEM_SIZE *32-1:0] e_init;
wire [OUT_MEM_SIZE *32-1:0] o;
wire terminate;
genvar i;
integer cc;
a23_gc_main_CODE_MEM_SIZE64_G_MEM_SIZE64_E_MEM_SIZE64_OUT_MEM_SIZE64_STACK_MEM_SIZE64
// a23_gc_main
// #
// (
// .CODE_MEM_SIZE ( CODE_MEM_SIZE ),
// .G_MEM_SIZE ( G_MEM_SIZE ),
// .E_MEM_SIZE ( E_MEM_SIZE ),
// .OUT_MEM_SIZE ( OUT_MEM_SIZE ),
// .STACK_MEM_SIZE ( STACK_MEM_SIZE )
// )
u_a23_gc_main
(
.clk ( clk ),
.rst ( rst ),
.p_init ( p_init ),
.g_init ( g_init ),
.e_init ( e_init ),
.o ( o ),
.terminate ( terminate )
);
reg [31:0] p_init_reg [CODE_MEM_SIZE -1:0];
reg [31:0] g_init_reg [G_MEM_SIZE -1:0];
reg [31:0] e_init_reg [E_MEM_SIZE -1:0];
reg [31:0] o_word_wire [OUT_MEM_SIZE -1:0];
generate
for (i = 0; i < CODE_MEM_SIZE; i = i + 1)begin: code_gen
assign p_init[32*(i+1)-1:32*i] = p_init_reg[i];
end
for (i = 0; i < G_MEM_SIZE; i = i + 1)begin: g_gen
assign g_init[32*(i+1)-1:32*i] = g_init_reg[i];
end
for (i = 0; i < E_MEM_SIZE; i = i + 1)begin: e_gen
assign e_init[32*(i+1)-1:32*i] = e_init_reg[i];
end
for (i = 0; i < OUT_MEM_SIZE; i = i + 1)begin: o_gen
always@* o_word_wire[i] = o[32*(i+1)-1:32*i];
end
endgenerate
initial
begin
clk = 0;
rst = 1;
cc = 0;
$readmemh($sformatf("../../TinyGarble/a23/%s/p.txt", TEST_NAME), p_init_reg);
$readmemh($sformatf("../../TinyGarble/a23/%s/test/g.txt", TEST_NAME), g_init_reg);
$readmemh($sformatf("../../TinyGarble/a23/%s/test/e.txt", TEST_NAME), e_init_reg);
#28
rst = 0;
while (~terminate) begin
@(posedge clk);
cc = cc +1;
end
$writememh("./o.txt.out", o_word_wire);
$display("Terminate at %dcc\n", cc);
$stop;
end
always #5 clk=~clk;
endmodule
| 7.02009
|
module a25_barrel_shift (
i_clk,
i_in,
i_carry_in,
i_shift_amount,
i_shift_imm_zero,
i_function,
o_out,
o_carry_out,
o_stall
);
/************************* IO Declarations *********************/
input i_clk;
input [31:0] i_in;
input i_carry_in;
input [7:0] i_shift_amount; // uses 8 LSBs of Rs, or a 5 bit immediate constant
input i_shift_imm_zero; // high when immediate shift value of zero selected
input [1:0] i_function;
output [31:0] o_out;
output o_carry_out;
output o_stall;
/************************* IO Declarations *********************/
wire [31:0] quick_out;
wire quick_carry_out;
wire [31:0] full_out;
wire full_carry_out;
reg [31:0] full_out_r = 32'd0;
reg full_carry_out_r = 1'd0;
reg use_quick_r = 1'd1;
assign o_stall = (|i_shift_amount[7:2]) & use_quick_r;
assign o_out = use_quick_r ? quick_out : full_out_r;
assign o_carry_out = use_quick_r ? quick_carry_out : full_carry_out_r;
// Capture the result from the full barrel shifter in case the
// quick shifter gives the wrong value
always @(posedge i_clk) begin
full_out_r <= full_out;
full_carry_out_r <= full_carry_out;
use_quick_r <= !o_stall;
end
// Full barrel shifter
a25_shifter_full u_shifter_full (
.i_in (i_in),
.i_carry_in (i_carry_in),
.i_shift_amount (i_shift_amount),
.i_shift_imm_zero(i_shift_imm_zero),
.i_function (i_function),
.o_out (full_out),
.o_carry_out (full_carry_out)
);
// Quick barrel shifter
a25_shifter_quick u_shifter_quick (
.i_in (i_in),
.i_carry_in (i_carry_in),
.i_shift_amount (i_shift_amount),
.i_shift_imm_zero(i_shift_imm_zero),
.i_function (i_function),
.o_out (quick_out),
.o_carry_out (quick_carry_out)
);
endmodule
| 7.686943
|
module single_port_ram_128_8 (
clk,
data,
we,
addr,
out
);
`define ADDR_WIDTH_128_8 8
`define DATA_WIDTH_128_8 128
input clk;
input [`DATA_WIDTH_128_8-1:0] data;
input we;
input [`ADDR_WIDTH_128_8-1:0] addr;
output [`DATA_WIDTH_128_8-1:0] out;
reg [`DATA_WIDTH_128_8-1:0] out;
reg [`DATA_WIDTH_128_8-1:0] RAM [255:0];
always @(posedge clk) begin
if (we) begin
RAM[addr] <= data;
out <= RAM[addr];
end
end
endmodule
| 8.023817
|
module single_port_ram_21_8 (
clk,
data,
we,
addr,
out
);
`define ADDR_WIDTH_21_8 8
`define DATA_WIDTH_21_8 21
input clk;
input [`DATA_WIDTH_21_8-1:0] data;
input we;
input [`ADDR_WIDTH_21_8-1:0] addr;
output [`DATA_WIDTH_21_8-1:0] out;
reg [`DATA_WIDTH_21_8-1:0] out;
reg [`DATA_WIDTH_21_8-1:0] RAM [255:0];
always @(posedge clk) begin
if (we) begin
RAM[addr] <= data;
out <= RAM[addr];
end
end
endmodule
| 8.023817
|
module a25_multiply (
i_clk,
i_core_stall,
i_a_in,
i_b_in,
i_function,
i_execute,
o_out,
o_flags,
o_done
);
input i_clk;
input i_core_stall;
input [31:0] i_a_in; // Rds
input [31:0] i_b_in; // Rm
input [1:0] i_function;
input i_execute;
output [31:0] o_out;
output [1:0] o_flags; // [1] = N, [0] = Z
output o_done; // goes high 2 cycles before completion
reg o_done = 1'd0;
wire enable;
wire accumulate;
wire [33:0] multiplier;
wire [33:0] multiplier_bar;
wire [33:0] sum;
wire [33:0] sum34_b;
reg [ 5:0] count = 6'd0;
reg [ 5:0] count_nxt;
reg [67:0] product = 68'd0;
reg [67:0] product_nxt;
reg [ 1:0] flags_nxt;
wire [32:0] sum_acc1; // the MSB is the carry out for the upper 32 bit addition
assign enable = i_function[0];
assign accumulate = i_function[1];
assign multiplier = {2'd0, i_a_in};
assign multiplier_bar = ~{2'd0, i_a_in} + 34'd1;
assign sum34_b = product[1:0] == 2'b01 ? multiplier :
product[1:0] == 2'b10 ? multiplier_bar :
34'd0 ;
// -----------------------------------
// 34-bit adder - booth multiplication
// -----------------------------------
assign sum = product[67:34] + sum34_b;
// ------------------------------------
// 33-bit adder - accumulate operations
// ------------------------------------
assign sum_acc1 = {1'd0, product[32:1]} + {1'd0, i_a_in};
// assign count_nxt = count;
always @* begin
// update Negative and Zero flags
// Use registered value of product so this adds an extra cycle
// but this avoids having the 64-bit zero comparator on the
// main adder path
flags_nxt = {product[32], product[32:1] == 32'd0};
if (count == 6'd0) product_nxt = {33'd0, 1'd0, i_b_in, 1'd0};
else if (count <= 6'd33) product_nxt = {sum[33], sum, product[33:1]};
else if (count == 6'd34 && accumulate) begin
// Note that bit 0 is not part of the product. It is used during the booth
// multiplication algorithm
product_nxt = {product[64:33], sum_acc1[31:0], 1'd0}; // Accumulate
end else product_nxt = product;
// Multiplication state counter
if (count == 6'd0) // start
count_nxt = enable ? 6'd1 : 6'd0;
else if ((count == 6'd34 && !accumulate) || // MUL
(count == 6'd35 && accumulate)) // MLA
count_nxt = 6'd0;
else count_nxt = count + 1'd1;
end
always @(posedge i_clk)
if (!i_core_stall) begin
count <= i_execute ? count_nxt : count;
product <= i_execute ? product_nxt : product;
o_done <= i_execute ? count == 6'd31 : o_done;
end
// Outputs
assign o_out = product[32:1];
assign o_flags = flags_nxt;
endmodule
| 7.219736
|
module a25_barrel_shift (
i_clk,
i_in,
i_carry_in,
i_shift_amount,
i_shift_imm_zero,
i_function,
o_out,
o_carry_out,
o_stall
);
/************************* IO Declarations *********************/
input i_clk;
input [31:0] i_in;
input i_carry_in;
input [7:0] i_shift_amount; // uses 8 LSBs of Rs, or a 5 bit immediate constant
input i_shift_imm_zero; // high when immediate shift value of zero selected
input [1:0] i_function;
output [31:0] o_out;
output o_carry_out;
output o_stall;
/************************* IO Declarations *********************/
wire [31:0] quick_out;
wire quick_carry_out;
wire [31:0] full_out;
wire full_carry_out;
reg [31:0] full_out_r = 32'd0;
reg full_carry_out_r = 1'd0;
reg use_quick_r = 1'd1;
assign o_stall = (|i_shift_amount[7:2]) & use_quick_r;
assign o_out = use_quick_r ? quick_out : full_out_r;
assign o_carry_out = use_quick_r ? quick_carry_out : full_carry_out_r;
// Capture the result from the full barrel shifter in case the
// quick shifter gives the wrong value
always @(posedge i_clk) begin
full_out_r <= full_out;
full_carry_out_r <= full_carry_out;
use_quick_r <= !o_stall;
end
// Full barrel shifter
a25_shifter_full u_shifter_full (
.i_in (i_in),
.i_carry_in (i_carry_in),
.i_shift_amount (i_shift_amount),
.i_shift_imm_zero(i_shift_imm_zero),
.i_function (i_function),
.o_out (full_out),
.o_carry_out (full_carry_out)
);
// Quick barrel shifter
a25_shifter_quick u_shifter_quick (
.i_in (i_in),
.i_carry_in (i_carry_in),
.i_shift_amount (i_shift_amount),
.i_shift_imm_zero(i_shift_imm_zero),
.i_function (i_function),
.o_out (quick_out),
.o_carry_out (quick_carry_out)
);
endmodule
| 7.686943
|
module single_port_ram_128_8 (
clk,
data,
we,
addr,
out
);
input clk;
input [`DATA_WIDTH_128_8-1:0] data;
input we;
input [`ADDR_WIDTH_128_8-1:0] addr;
output [`DATA_WIDTH_128_8-1:0] out;
reg [`DATA_WIDTH_128_8-1:0] out;
reg [`DATA_WIDTH_128_8-1:0] RAM [255:0];
always @(posedge clk) begin
if (we) begin
RAM[addr] <= data;
out <= RAM[addr];
end
end
endmodule
| 8.023817
|
module single_port_ram_21_8 (
clk,
data,
we,
addr,
out
);
input clk;
input [`DATA_WIDTH_21_8-1:0] data;
input we;
input [`ADDR_WIDTH_21_8-1:0] addr;
output [`DATA_WIDTH_21_8-1:0] out;
reg [`DATA_WIDTH_21_8-1:0] out;
reg [`DATA_WIDTH_21_8-1:0] RAM [255:0];
always @(posedge clk) begin
if (we) begin
RAM[addr] <= data;
out <= RAM[addr];
end
end
endmodule
| 8.023817
|
module single_port_ram_128_8 (
clk,
data,
we,
addr,
out
);
input clk;
input [`DATA_WIDTH_128_8-1:0] data;
input we;
input [`ADDR_WIDTH_128_8-1:0] addr;
output [`DATA_WIDTH_128_8-1:0] out;
reg [`DATA_WIDTH_128_8-1:0] out;
reg [`DATA_WIDTH_128_8-1:0] RAM [255:0];
always @(posedge clk) begin
if (we) begin
RAM[addr] <= data;
out <= RAM[addr];
end
end
endmodule
| 8.023817
|
module single_port_ram_21_8 (
clk,
data,
we,
addr,
out
);
input clk;
input [`DATA_WIDTH_21_8-1:0] data;
input we;
input [`ADDR_WIDTH_21_8-1:0] addr;
output [`DATA_WIDTH_21_8-1:0] out;
reg [`DATA_WIDTH_21_8-1:0] out;
reg [`DATA_WIDTH_21_8-1:0] RAM [255:0];
always @(posedge clk) begin
if (we) begin
RAM[addr] <= data;
out <= RAM[addr];
end
end
endmodule
| 8.023817
|
module single_port_ram_128_8 (
clk,
data,
we,
addr,
out
);
`define ADDR_WIDTH_128_8 8
`define DATA_WIDTH_128_8 128
input clk;
input [`DATA_WIDTH_128_8-1:0] data;
input we;
input [`ADDR_WIDTH_128_8-1:0] addr;
output [`DATA_WIDTH_128_8-1:0] out;
reg [`DATA_WIDTH_128_8-1:0] out;
reg [`DATA_WIDTH_128_8-1:0] RAM [255:0];
always @(posedge clk) begin
if (we) begin
RAM[addr] <= data;
out <= RAM[addr];
end
end
endmodule
| 8.023817
|
module single_port_ram_21_8 (
clk,
data,
we,
addr,
out
);
`define ADDR_WIDTH_21_8 8
`define DATA_WIDTH_21_8 21
input clk;
input [`DATA_WIDTH_21_8-1:0] data;
input we;
input [`ADDR_WIDTH_21_8-1:0] addr;
output [`DATA_WIDTH_21_8-1:0] out;
reg [`DATA_WIDTH_21_8-1:0] out;
reg [`DATA_WIDTH_21_8-1:0] RAM [255:0];
always @(posedge clk) begin
if (we) begin
RAM[addr] <= data;
out <= RAM[addr];
end
end
endmodule
| 8.023817
|
module a25_multiply (
i_clk,
i_core_stall,
i_a_in,
i_b_in,
i_function,
i_execute,
o_out,
o_flags,
o_done
);
input i_clk;
input i_core_stall;
input [31:0] i_a_in; // Rds
input [31:0] i_b_in; // Rm
input [1:0] i_function;
input i_execute;
output [31:0] o_out;
output [1:0] o_flags; // [1] = N, [0] = Z
output o_done; // goes high 2 cycles before completion
reg o_done = 1'd0;
wire enable;
wire accumulate;
wire [33:0] multiplier;
wire [33:0] multiplier_bar;
wire [33:0] sum;
wire [33:0] sum34_b;
reg [ 5:0] count = 6'd0;
reg [ 5:0] count_nxt;
reg [67:0] product = 68'd0;
reg [67:0] product_nxt;
reg [ 1:0] flags_nxt;
wire [32:0] sum_acc1; // the MSB is the carry out for the upper 32 bit addition
assign enable = i_function[0];
assign accumulate = i_function[1];
assign multiplier = {2'd0, i_a_in};
assign multiplier_bar = ~{2'd0, i_a_in} + 34'd1;
assign sum34_b = product[1:0] == 2'b01 ? multiplier :
product[1:0] == 2'b10 ? multiplier_bar :
34'd0 ;
// -----------------------------------
// 34-bit adder - booth multiplication
// -----------------------------------
assign sum = product[67:34] + sum34_b;
// ------------------------------------
// 33-bit adder - accumulate operations
// ------------------------------------
assign sum_acc1 = {1'd0, product[32:1]} + {1'd0, i_a_in};
// assign count_nxt = count;
always @* begin
// update Negative and Zero flags
// Use registered value of product so this adds an extra cycle
// but this avoids having the 64-bit zero comparator on the
// main adder path
flags_nxt = {product[32], product[32:1] == 32'd0};
if (count == 6'd0) product_nxt = {33'd0, 1'd0, i_b_in, 1'd0};
else if (count <= 6'd33) product_nxt = {sum[33], sum, product[33:1]};
else if (count == 6'd34 && accumulate) begin
// Note that bit 0 is not part of the product. It is used during the booth
// multiplication algorithm
product_nxt = {product[64:33], sum_acc1[31:0], 1'd0}; // Accumulate
end else product_nxt = product;
// Multiplication state counter
if (count == 6'd0) // start
count_nxt = enable ? 6'd1 : 6'd0;
else if ((count == 6'd34 && !accumulate) || // MUL
(count == 6'd35 && accumulate)) // MLA
count_nxt = 6'd0;
else count_nxt = count + 1'd1;
end
always @(posedge i_clk)
if (!i_core_stall) begin
count <= i_execute ? count_nxt : count;
product <= i_execute ? product_nxt : product;
o_done <= i_execute ? count == 6'd31 : o_done;
end
// Outputs
assign o_out = product[32:1];
assign o_flags = flags_nxt;
endmodule
| 7.219736
|
module a25_top #(
parameter AXIL_AW = 32,
parameter AXIL_DW = 128,
parameter AXIL_SW = AXIL_DW >> 3
) (
input clk,
input rst_n,
input irq,
input firq,
input system_rdy,
output [AXIL_AW-1:0] m_axil_awaddr,
output [ 2:0] m_axil_awprot,
output m_axil_awvalid,
input m_axil_awready,
output [AXIL_DW-1:0] m_axil_wdata,
output [AXIL_SW-1:0] m_axil_wstrb,
output m_axil_wvalid,
input m_axil_wready,
input [1:0] m_axil_bresp,
input m_axil_bvalid,
output m_axil_bready,
output [AXIL_AW-1:0] m_axil_araddr,
output [ 2:0] m_axil_arprot,
output m_axil_arvalid,
input m_axil_arready,
input [AXIL_DW-1:0] m_axil_rdata,
input [ 1:0] m_axil_rresp,
input m_axil_rvalid,
output m_axil_rready
);
localparam WB_DW = AXIL_DW;
localparam WB_SW = AXIL_SW;
localparam WB_AW = AXIL_AW;
// Wishbone Master Buses
wire [WB_AW-1:0] m_wb_adr;
wire [WB_SW-1:0] m_wb_sel;
wire m_wb_we;
wire [WB_DW-1:0] m_wb_dat_w;
wire [WB_DW-1:0] m_wb_dat_r;
wire m_wb_cyc;
wire m_wb_stb;
wire m_wb_ack;
wire m_wb_err;
a25_wbs2axilm #(
.C_AXI_ADDR_WIDTH(AXIL_AW),
.C_AXI_DATA_WIDTH(AXIL_DW)
) wbs2axilm (
.i_clk (clk),
.i_rst_n(rst_n),
.o_axi_awvalid(m_axil_awvalid),
.i_axi_awready(m_axil_awready),
.o_axi_awaddr (m_axil_awaddr),
.o_axi_awprot (m_axil_awprot),
.o_axi_wvalid(m_axil_wvalid),
.i_axi_wready(m_axil_wready),
.o_axi_wdata (m_axil_wdata),
.o_axi_wstrb (m_axil_wstrb),
.i_axi_bvalid(m_axil_bvalid),
.o_axi_bready(m_axil_bready),
.i_axi_bresp (m_axil_bresp),
.o_axi_arvalid(m_axil_arvalid),
.i_axi_arready(m_axil_arready),
.o_axi_araddr (m_axil_araddr),
.o_axi_arprot (m_axil_arprot),
.i_axi_rvalid(m_axil_rvalid),
.o_axi_rready(m_axil_rready),
.i_axi_rdata (m_axil_rdata),
.i_axi_rresp (m_axil_rresp),
.i_wb_cyc (m_wb_cyc),
.i_wb_stb (m_wb_stb),
.i_wb_we (m_wb_we),
.i_wb_addr (m_wb_adr),
.i_wb_data (m_wb_dat_w),
.i_wb_sel (m_wb_sel),
.o_wb_stall(),
.o_wb_ack (m_wb_ack),
.o_wb_data (m_wb_dat_r),
.o_wb_err (m_wb_err)
);
a25_core u_amber_wb (
.i_clk (clk),
.i_rst_n(rst_n),
.i_irq (irq),
.i_firq(firq),
.i_system_rdy(system_rdy),
.o_wb_adr(m_wb_adr),
.o_wb_sel(m_wb_sel),
.o_wb_we (m_wb_we),
.i_wb_dat(m_wb_dat_r),
.o_wb_dat(m_wb_dat_w),
.o_wb_cyc(m_wb_cyc),
.o_wb_stb(m_wb_stb),
.i_wb_ack(m_wb_ack),
.i_wb_err(m_wb_err)
);
endmodule
| 6.915859
|
module a25_write_back(
i_clk,
i_mem_stall,
i_mem_read_data,
i_mem_read_data_valid,
i_mem_load_rd,
o_wb_read_data,
o_wb_read_data_valid,
o_wb_load_rd,
i_daddress,
// i_daddress_valid
);
input i_clk;
input i_mem_stall; // Mem stage asserting stall
input [31:0] i_mem_read_data; // data reads
input i_mem_read_data_valid; // read data is valid
input [10:0] i_mem_load_rd; // Rd for data reads
output [31:0] o_wb_read_data; // data reads
output o_wb_read_data_valid; // read data is valid
output [10:0] o_wb_load_rd; // Rd for data reads
input [31:0] i_daddress;
//input i_daddress_valid;
reg [31:0] mem_read_data_r = 32'd0; // Register read data from Data Cache
reg mem_read_data_valid_r = 1'd0; // Register read data from Data Cache
reg [10:0] mem_load_rd_r = 11'd0; // Register the Rd value for loads
assign o_wb_read_data = mem_read_data_r;
assign o_wb_read_data_valid = mem_read_data_valid_r;
assign o_wb_load_rd = mem_load_rd_r;
always @( posedge i_clk )
if ( !i_mem_stall )
begin
mem_read_data_r <= i_mem_read_data;
mem_read_data_valid_r <= i_mem_read_data_valid;
mem_load_rd_r <= i_mem_load_rd;
end
// Used by a25_decompile.v, so simulation only
//synopsys translate_off
reg [31:0] daddress_r = 32'd0; // Register read data from Data Cache
always @( posedge i_clk )
if ( !i_mem_stall )
daddress_r <= i_daddress;
//synopsys translate_on
endmodule
| 6.942168
|
module is implemented for converting ASCII values into binary data received
// via UART Receiver.
/////////////////////////////////////////////////////////////////////////////
module ascii2binaryconverter (in,out,clk,rst,w_RX_dv);
input [7:0] in; //ASCII input
input clk; //Clock Signal
input rst;
input w_RX_dv; //This bit goes to 1 if the data byte is received properly
output reg [7:0] out; //Binary Output
parameter s0 = 2'b00, s1 = 2'b01, s2 = 2'b10, s3 = 2'b11; //defining different states for Finite State Machine
reg fsm; //FSM output
reg [7:0] a;
reg [1:0] state; //Variable for tracking the state
task ascii2binary;
input [7:0] w_RX_byte;
output [7:0]out;
begin
case (w_RX_byte)
48: out = 0; //ASCII value 48 = 0 in Binary
49: out = 1; //ASCII value 49 = 1 in Binary
50: out = 2; //ASCII value 50 = 2 in Binary
51: out = 3; //ASCII value 51 = 3 in Binary
52: out = 4; //ASCII value 52 = 4 in Binary
53: out = 5; //ASCII value 53 = 5 in Binary
54: out = 6; //ASCII value 54 = 6 in Binary
55: out = 7; //ASCII value 55 = 7 in Binary
56: out = 8; //ASCII value 56 = 8 in Binary
57: out = 9; //ASCII value 57 = 9 in Binary
endcase
end
endtask
always @ (posedge clk)begin
if (rst)begin
state = s0; out = 0; a =0 ;
end
else begin //Finite State Machine: Mealy Machine
case (state)
s0: begin
fsm =0;
if (w_RX_dv) begin
state = s1;
ascii2binary(in,a);
out = out + a * 100;
$display ($realtime, "ns %d", out);
end
else begin
state = s0;
end
end
s1: begin
fsm =0;
if (w_RX_dv) begin
state = s2;
ascii2binary(in,a);
out = out + a * 10;
$display ($realtime, "ns %d", out);
end
else begin
state = s1;
end
end
s2: begin
fsm =0;
if (w_RX_dv) begin
state = s3;
ascii2binary(in,a);
out = out + a * 1;
$display ($realtime, "ns %d", out);
end
else begin
state = s2;
end
end
s3: begin
fsm =1;
if (w_RX_dv == 0) begin
$display ($realtime, "ns %d", out);
state = s0;
end
else begin
state = s3;
end
end
endcase
end
end
endmodule
| 6.726025
|
module PushButton_Debouncer (
input clk,
input PB, // "PB" is the glitchy, asynchronous to clk, active low push-button signal
output reg PB_state // 1 as long as the push-button is active (down)
);
// First use two flip-flops to synchronize the PB signal the "clk" clock domain
reg PB_sync_0;
always @(posedge clk) PB_sync_0 <= PB; // invert PB to make PB_sync_0 active high
reg PB_sync_1;
always @(posedge clk) PB_sync_1 <= PB_sync_0;
// Next declare a 16-bits counter
reg [1:0] PB_cnt;
// When the push-button is pushed or released, we increment the counter
// The counter has to be maxed out before we decide that the push-button state has changed
wire PB_idle = (PB_state == PB_sync_1);
wire PB_cnt_max = &PB_cnt; // true when all bits of PB_cnt are 1's
always @(posedge clk)
if (PB_idle) PB_cnt <= 0; // nothing's going on
else begin
PB_cnt <= PB_cnt + 1; // something's going on, increment the counter
if (PB_cnt_max) PB_state <= ~PB_state; // if the counter is maxed out, PB changed!
end
endmodule
| 7.366064
|
module Angle_to_on_time (
input [ 3:0] angle, //ON/OFF FPGA switch to select angle
output reg [27:0] out //Ontime_bus
);
parameter x = 100000; // factor for 1 ms
always @(angle) begin
case (angle)
/*Assigning set of on-time/Angle using different ON/OFF
Switches for a particular action to be performed*/
4'b0001: out = 1.0 * x; // 45 degree
4'b0010: out = 1.5 * x; // 90 degree
4'b0100: out = 2.0 * x; // 135 degree
4'b1000: out = 2.5 * x; // 180 degree
default: out = 0; // default on-time is zero
endcase
end
endmodule
| 6.545659
|
module SEL_PRI_32x4 (
input [31:0] src0,
input [31:0] src1,
input [31:0] src2,
input [31:0] src3,
input [ 3:0] sel,
output reg [31:0] result
);
always @(*) begin
if (sel[0]) begin
result = src0;
end else begin
if (sel[1]) begin
result = src1;
end else begin
if (sel[2]) begin
result = src2;
end else begin
if (sel[3]) begin
result = src3;
end else begin
result = 32'h0;
end
end
end
end
end
endmodule
| 7.245393
|
module SEL_PRI_32x3 (
input [31:0] src0,
input [31:0] src1,
input [31:0] src2,
input [ 2:0] sel,
output reg [31:0] result
);
always @(*) begin
if (sel[0]) begin
result = src0;
end else begin
if (sel[1]) begin
result = src1;
end else begin
if (sel[2]) begin
result = src2;
end else begin
result = 32'h0;
end
end
end
end
endmodule
| 6.998545
|
module GPR (
input [ 4:0] rd_adr_0,
output [31:0] rd_dat_0,
input [ 4:0] rd_adr_1,
output [31:0] rd_dat_1,
input [ 4:0] rd_adr_2,
output [31:0] rd_dat_2,
input wr_en_0,
input [ 4:0] wr_adr_0,
input [31:0] wr_dat_0,
input clk,
input reset
);
reg [31:0] _zz_1_;
reg [31:0] _zz_2_;
reg [31:0] _zz_3_;
wire _zz_4_;
wire _zz_5_;
wire _zz_6_;
reg [31:0] regFile[0:31] /* verilator public */;
//wtf:icarus $dumpvars cannot dump a vpiMemory
generate
genvar i;
for (i = 0; i < 32; i = i + 1) begin : loc
wire [0:31] dat;
assign dat = regFile[i];
end
endgenerate
assign _zz_4_ = 1'b1;
assign _zz_5_ = 1'b1;
assign _zz_6_ = 1'b1;
always @(posedge clk) begin
if (_zz_4_) begin
_zz_1_ <= regFile[rd_adr_0];
end
end
always @(posedge clk) begin
if (_zz_5_) begin
_zz_2_ <= regFile[rd_adr_1];
end
end
always @(posedge clk) begin
if (_zz_6_) begin
_zz_3_ <= regFile[rd_adr_2];
end
end
always @(posedge clk) begin
if (wr_en_0) begin
regFile[wr_adr_0] <= wr_dat_0;
end
end
assign rd_dat_0 = _zz_1_;
assign rd_dat_1 = _zz_2_;
assign rd_dat_2 = _zz_3_;
endmodule
| 6.538374
|
module SEL_32x4 (
input [31:0] src0,
input [31:0] src1,
input [31:0] src2,
input [31:0] src3,
input [ 3:0] sel,
output [31:0] result
);
assign result = ((((src0 & (sel[0] ? 32'hffffffff : 32'h0)) | (src1 & (sel[1] ? 32'hffffffff : 32'h0))) | (src2 & (sel[2] ? 32'hffffffff : 32'h0))) | (src3 & (sel[3] ? 32'hffffffff : 32'h0)));
endmodule
| 7.719684
|
module SEL_32x3 (
input [31:0] src0,
input [31:0] src1,
input [31:0] src2,
input [ 2:0] sel,
output [31:0] result
);
assign result = (((src0 & (sel[0] ? 32'hffffffff : 32'h0)) | (src1 & (sel[1] ? 32'hffffffff : 32'h0))) | (src2 & (sel[2] ? 32'hffffffff : 32'h0)));
endmodule
| 7.924547
|
module ALU (
input [31:0] src1,
input [31:0] src2,
input [ 0:0] cin,
output [31:0] result,
output [ 1:0] add_cr,
output [ 1:0] cmp_cr,
output [ 1:0] cmpl_cr,
output ca,
output ov
);
wire [32:0] _zz_1_;
wire [32:0] _zz_2_;
wire [31:0] _zz_3_;
wire [31:0] _zz_4_;
wire [32:0] adder;
wire [31:0] ra;
wire [31:0] rb;
wire [ 0:0] cin_1_;
assign _zz_1_ = ({(1'b0), ra} + {(1'b0), rb});
assign _zz_2_ = {32'd0, cin_1_};
assign _zz_3_ = ra;
assign _zz_4_ = rb;
assign ra = src1;
assign rb = src2;
assign cin_1_ = cin;
assign adder = (_zz_1_ + _zz_2_);
assign result = adder[31 : 0];
assign add_cr = {adder[31], (adder[31 : 0] == 32'h0)};
assign cmpl_cr = {(ra < rb), (ra == rb)};
assign cmp_cr = {($signed(_zz_3_) < $signed(_zz_4_)), (ra == rb)};
assign ca = adder[32];
assign ov = ((adder[32] ^ adder[31]) && (!(ra[31] ^ rb[31])));
endmodule
| 7.960621
|
module MUL16_U (
input [15:0] src1,
input [15:0] src2,
output [31:0] result
);
wire [31:0] _zz_1_;
assign _zz_1_ = (src1 * src2);
assign result = _zz_1_;
endmodule
| 6.844947
|
module WBExecute (
input [31:0] src0,
input [31:0] src1,
input [31:0] src2,
input [31:0] src3,
input [31:0] src4,
input [31:0] src5,
input [ 5:0] sel,
input [ 2:0] zom,
output reg [31:0] result
);
wire [31:0] _zz_1_;
wire [31:0] _zz_2_;
wire _zz_3_;
wire [31:0] _zz_4_;
wire [31:0] _zz_5_;
wire [31:0] presel;
reg [31:0] constant_1_;
assign _zz_1_ = (sel[0] ? 32'hffffffff : 32'h0);
assign _zz_2_ = (sel[1] ? 32'hffffffff : 32'h0);
assign _zz_3_ = sel[2];
assign _zz_4_ = 32'hffffffff;
assign _zz_5_ = 32'h0;
assign presel = ((((((src0 & _zz_1_) | (src1 & _zz_2_)) | (src2 & (_zz_3_ ? _zz_4_ : _zz_5_))) | (src3 & (sel[3] ? 32'hffffffff : 32'h0))) | (src4 & (sel[4] ? 32'hffffffff : 32'h0))) | (src5 & (sel[5] ? 32'hffffffff : 32'h0)));
always @(*) begin
constant_1_ = 32'h0;
if (zom[2]) begin
constant_1_ = 32'hffffffff;
end else begin
if (zom[1]) begin
constant_1_ = 32'h00000001;
end
end
end
always @(*) begin
result = constant_1_;
if ((zom == (3'b000))) begin
result = presel;
end
end
endmodule
| 7.266876
|
module decoder3to8 (
in,
out
);
input [2:0] in;
output reg [7:0] out;
always @(in) begin
out = 8'd0;
case (in)
3'b000: out[0] = 1'b1;
3'b001: out[1] = 1'b1;
3'b010: out[2] = 1'b1;
3'b011: out[3] = 1'b1;
3'b100: out[4] = 1'b1;
3'b101: out[5] = 1'b1;
3'b110: out[6] = 1'b1;
3'b111: out[7] = 1'b1;
endcase
end
// Method II:
// output wire [7:0] out;
// assign out[0] = ~in[2] & ~in[1] & ~in[0];
// assign out[1] = ~in[2] & ~in[1] & in[0];
// assign out[2] = ~in[2] & in[1] & ~in[0];
// assign out[3] = ~in[2] & in[1] & in[0];
// assign out[4] = in[2] & ~in[1] & ~in[0];
// assign out[5] = in[2] & ~in[1] & in[0];
// assign out[6] = in[2] & in[1] & ~in[0];
// assign out[7] = in[2] & in[1] & in[0];
endmodule
| 8.532605
|
module encoder8to3 (
in,
out
);
input [7:0] in;
output reg [2:0] out;
always @(in) begin
case (in)
8'b10000000: out = 3'b111;
8'b01000000: out = 3'b110;
8'b00100000: out = 3'b101;
8'b00010000: out = 3'b100;
8'b00001000: out = 3'b011;
8'b00000100: out = 3'b010;
8'b00000010: out = 3'b001;
8'b00000001: out = 3'b000;
endcase
end
// Method II:
// output wire [2:0] out;
// assign out[0] = in[7] | in[5] | in[3] | in[1] ;
// assign out[1] = in[7] | in[6] | in[3] | in[2] ;
// assign out[2] = in[7] | in[6] | in[5] | in[4] ;
endmodule
| 7.108121
|
module priority_encoder8to3 (
inp,
out
);
input [7:0] inp; // receives input
output wire [2:0] out; // gives output
assign out[0] = (~inp[0]) & (inp[1] | (~inp[1] & ~inp[2] & (inp[3] | (~inp[3] & ~inp[4] & (inp[5] | (~inp[5] & ~inp[6] & inp[7]))))));
assign out[1] = ~inp[0] & ~inp[1] & (inp[2] | inp[3] | (~inp[2] & ~inp[3] & ~inp[4] & ~inp[5] & (inp[6] | inp[7])));
assign out[2] = ~inp[0] & ~inp[1] & ~inp[2] & ~inp[3] & (inp[4] | inp[5] | inp[6] | inp[7]);
endmodule
| 7.114361
|
module priority_encoder8to3 (
in,
out
);
input [7:0] in;
output reg [2:0] out;
always @(in) begin
casex (in)
8'b10000000: out = 3'b111;
8'bx1000000: out = 3'b110;
8'bxx100000: out = 3'b101;
8'bxxx10000: out = 3'b100;
8'bxxxx1000: out = 3'b011;
8'bxxxxx100: out = 3'b010;
8'bxxxxxx10: out = 3'b001;
8'bxxxxxxx1: out = 3'b000;
endcase
end
// Method II:
// output reg [2:0] out;
// always @(*)
// begin
// if (in[0]) out <= 3'b000;
// else if (in[1]) out <= 3'b001;
// else if (in[2]) out <= 3'b010;
// else if (in[3]) out <= 3'b011;
// else if (in[4]) out <= 3'b100;
// else if (in[5]) out <= 3'b101;
// else if (in[6]) out <= 3'b110;
// else if (in[7]) out <= 3'b111;
// else out <= 3'bxxx;
// end
// Method III:
// output wire [2:0] out;
// assign out = (in[0] == 1'b1) ? 3'b000:
// (in[1] == 1'b1) ? 3'b001:
// (in[2] == 1'b1) ? 3'b010:
// (in[3] == 1'b1) ? 3'b011:
// (in[4] == 1'b1) ? 3'b100:
// (in[5] == 1'b1) ? 3'b101:
// (in[6] == 1'b1) ? 3'b110:
// (in[7] == 1'b1) ? 3'b111: 3'bxxx;
endmodule
| 7.114361
|
module top;
reg [7:0] Input;
wire [2:0] Output;
priority_encoder8to3 PRIORITY_ENCODER (
Input,
Output
);
always @(Input or Output) begin
$display("time=%d: Input = %b, Output = %b", $time, Input, Output);
end
initial begin
#100 $finish;
end
initial begin
Input = 0;
#1 $display("\n");
Input = 1;
#1 $display("\n");
Input = 2;
#1 $display("\n");
Input = 32;
#1 $display("\n");
Input = 40;
#1 $display("\n");
Input = 64;
#1 $display("\n");
Input = 60;
#1 $display("\n");
Input = 200;
#1 $display("\n");
Input = 12;
#1 $display("\n");
Input = 36;
#1 $display("\n");
Input = 128;
end
endmodule
| 7.327079
|
module a429_rx_iface
(
input clk2M,
input reset,
input enable,
input [1:0] speed,
input a429_in_a,
input a429_in_b,
input parcheck,
output reg [32:1] data,
output reg wr_en
);
////////////////////////////////////////
// Constants for the sampling counter //
////////////////////////////////////////
// Counter values for first/other sampling intervals
// 2.5us/10us for 100Kbps mode,
// 20us/80us for 12,5Kbps mode.
wire [8:0] first_sc_value = (speed[0]) ? 9'd4 : 9'd39;
wire [8:0] other_sc_value = (speed[0]) ? 9'd19 : 9'd159;
// Counter values for gap search
// 40us for 100Kbps mode, setting it to 30us
// 320us for 12,5Kbps mode, setting it to 240us.
wire [8:0] gap_sc_value = (speed[0]) ? 9'd59 : 9'd479;
///////////////////////////////////////////////////////
// Register 'aorb' previous value for edge detection //
///////////////////////////////////////////////////////
wire aandb = a429_in_a & a429_in_b;
wire aorb = a429_in_a | a429_in_b;
reg aorb_prev;
always @(posedge clk2M or posedge reset)
if (reset)
aorb_prev <= 1'b0;
else
aorb_prev <= aorb;
///////////////////////////////////////////////
// RX state machine parameters and registers //
///////////////////////////////////////////////
localparam IDLE = 2'b00;
localparam RECEIVING = 2'b01;
localparam WAITFORGAP = 2'b10;
reg [1:0] state;
reg parity;
reg [32:1] shift_reg;
reg [4:0] shift_counter;
reg [8:0] sampling_counter;
/////////////////////////////////////
// RX state machine implementation //
/////////////////////////////////////
always @(posedge clk2M or posedge reset)
if (reset) begin
state <= WAITFORGAP;
sampling_counter <= gap_sc_value;
shift_counter <= 5'b0;
data <= 32'b0;
shift_reg <= 32'b0;
wr_en <= 1'b0;
end else begin
case (state)
IDLE:
//
// Wait for 'aorb' rising edge
//
begin
parity <= 1'b0;
sampling_counter <= first_sc_value;
shift_counter <= 5'd31;
if (aorb & !aorb_prev)
state <= RECEIVING;
end
RECEIVING:
//
// Logical shift right until shift_counter = 0
//
if (~|sampling_counter)
if ((aandb == 1'b1) || (aorb == 1'b0)) begin // Bus error
sampling_counter <= gap_sc_value;
state <= WAITFORGAP;
end else if (~|shift_counter) begin // Complete word received
data <= {a429_in_a, shift_reg[32:10],
shift_reg[2], shift_reg[3], shift_reg[4], shift_reg[5],
shift_reg[6], shift_reg[7], shift_reg[8], shift_reg[9]};
if ((parity == a429_in_b) || !parcheck) // Odd parity ok, or no parity check
wr_en <= 1'b1;
sampling_counter <= gap_sc_value;
state <= WAITFORGAP;
end else begin // bit received
shift_reg <= {a429_in_a, shift_reg[32:2]};
parity <= parity ^ a429_in_a;
shift_counter <= shift_counter - 5'b1;
sampling_counter <= other_sc_value;
end
else
sampling_counter <= sampling_counter - 9'b1;
WAITFORGAP:
//
// Wait until a new gap is found
//
begin
wr_en <= 1'b0;
if (~|sampling_counter)
state <= IDLE;
else if (aorb == 1'b1)
sampling_counter <= gap_sc_value;
else
sampling_counter <= sampling_counter - 9'b1;
end
default: // This should never happen
begin
wr_en <= 1'b0;
sampling_counter <= gap_sc_value;
state <= WAITFORGAP;
end
endcase
end
endmodule
| 7.799288
|
module eight_bit_adder_top;
reg signed [7:0] A;
reg signed [7:0] B;
reg opcode;
wire signed [7:0] Sum;
wire Carry;
wire Overflow;
eight_bit_addr ADDER (
A,
B,
opcode,
Sum,
Carry,
Overflow
);
always @(A or B or opcode) begin
$monitor(
"time=%d: A = %d, B = %d, Opcode = %d, Output = %d\ntime=%d: A = %b, B = %b, Opcode = %d, Output = %b, Carry = %d, Overflow = %d\n",
$time, A, B, opcode, Sum, $time, A, B, opcode, Sum, Carry, Overflow);
// $monitor("time=%d: A = %b, B = %b, Opcode = %d, Output = %b, Carry = %d, Overflow = %d\n", $time, A, B, opcode, Sum, Carry, Overflow);
end
initial begin
#15;
$finish;
end
// Test Cases.
initial begin
A = 8'b01100100;
B = 8'b01100100;
opcode = 1;
#1;
$display("\n");
A = 8'b01111000;
B = 8'b01111000;
opcode = 0;
#1;
$display("\n");
A = 8'b00010100;
B = 8'b01100100;
opcode = 1;
#1;
$display("\n");
A = 8'b11100111;
B = 8'b01111111;
opcode = 0;
#1;
$display("\n");
A = 8'b01010000;
B = 8'b00101000;
opcode = 0;
#1;
$display("\n");
A = 8'b00001010;
B = 8'b01100100;
opcode = 1;
#1;
$display("\n");
A = 8'b00100001;
B = 8'b00010100;
opcode = 0;
#1;
$display("\n");
A = 8'b00101011;
B = 8'b00011110;
opcode = 0;
#1;
$display("\n");
A = 8'b00101000;
B = 8'b00010100;
opcode = 1;
#1;
$display("\n");
A = 8'b00110110;
B = 8'b00001010;
opcode = 1;
#1;
end
endmodule
| 7.124161
|
module eight_bit_adder_subtractor (
x,
y,
opcode,
sum,
carry_out,
overflow
);
// Inputs
input [7:0] x;
input [7:0] y;
input opcode;
// Outputs
output wire [7:0] sum;
output wire carry_out;
output wire overflow;
// Intermediate wire
wire [6:0] intermediate_carry;
// Instantiating the 8 one-adder modules
one_bit_full_adder_subtractor FAS0 (
x[0],
y[0],
opcode,
opcode,
sum[0],
intermediate_carry[0]
);
one_bit_full_adder_subtractor FAS1 (
x[1],
y[1],
intermediate_carry[0],
opcode,
sum[1],
intermediate_carry[1]
);
one_bit_full_adder_subtractor FAS2 (
x[2],
y[2],
intermediate_carry[1],
opcode,
sum[2],
intermediate_carry[2]
);
one_bit_full_adder_subtractor FAS3 (
x[3],
y[3],
intermediate_carry[2],
opcode,
sum[3],
intermediate_carry[3]
);
one_bit_full_adder_subtractor FAS4 (
x[4],
y[4],
intermediate_carry[3],
opcode,
sum[4],
intermediate_carry[4]
);
one_bit_full_adder_subtractor FAS5 (
x[5],
y[5],
intermediate_carry[4],
opcode,
sum[5],
intermediate_carry[5]
);
one_bit_full_adder_subtractor FAS6 (
x[6],
y[6],
intermediate_carry[5],
opcode,
sum[6],
intermediate_carry[6]
);
one_bit_full_adder_subtractor FAS7 (
x[7],
y[7],
intermediate_carry[6],
opcode,
sum[7],
carry_out
);
assign overflow = intermediate_carry[6] ^ carry_out;
endmodule
| 7.124161
|
module eight_bit_adder_subtractor_top;
// Inputs
reg [7:0] A;
reg [7:0] B;
reg opcode;
// Outputs
wire [7:0] sum;
wire carry;
wire overflow;
// Instantiation of the 8-bit adder module
eight_bit_adder_subtractor FULL_ADD_SUBT (
A,
B,
opcode,
sum,
carry,
overflow
);
// Displaying the output
always @(A or B or opcode or sum or carry or overflow) begin
$display(
"<%d>: Input_A = %b, Input_B = %b, Input_opcode = %b, Sum = %b, Carry = %b, Overflow = %b",
$time, A, B, opcode, sum, carry, overflow);
end
// Initialising the inputs
initial begin
// + + +
A = 115;
B = 30;
opcode = 0;
#1 $display("\n");
// + + -
A = 115;
B = 30;
opcode = 1;
#1 $display("\n");
// + - +
A = 68;
B = -93;
opcode = 0;
#1 $display("\n");
// + - -
A = 68;
B = -93;
opcode = 1;
#1 $display("\n");
// - + +
A = -57;
B = 79;
opcode = 0;
#1 $display("\n");
// - + + = 0
A = -127;
B = 127;
opcode = 0;
#1 $display("\n");
// - + -
A = -57;
B = 79;
opcode = 1;
#1 $display("\n");
// - - +
A = -88;
B = -98;
opcode = 0;
#1 $display("\n");
// - - -
A = -88;
B = -98;
opcode = 1;
#1 $display("\n");
// - - - = 0
A = -128;
B = -128;
opcode = 1;
#1 $display("\n");
end
endmodule
| 7.124161
|
module eight_bit_addr (
a,
b,
opcode,
sum,
carry,
overflow
);
input [7:0] a;
input [7:0] b;
input opcode;
output [7:0] sum;
output carry;
output overflow;
wire [7:0] sum;
wire carry;
wire overflow;
wire [6:0] intermediate_carry;
one_bit_addr F0 (
a[0],
b[0],
opcode,
opcode,
sum[0],
intermediate_carry[0]
);
one_bit_addr F1 (
a[1],
b[1],
intermediate_carry[0],
opcode,
sum[1],
intermediate_carry[1]
);
one_bit_addr F2 (
a[2],
b[2],
intermediate_carry[1],
opcode,
sum[2],
intermediate_carry[2]
);
one_bit_addr F3 (
a[3],
b[3],
intermediate_carry[2],
opcode,
sum[3],
intermediate_carry[3]
);
one_bit_addr F4 (
a[4],
b[4],
intermediate_carry[3],
opcode,
sum[4],
intermediate_carry[4]
);
one_bit_addr F5 (
a[5],
b[5],
intermediate_carry[4],
opcode,
sum[5],
intermediate_carry[5]
);
one_bit_addr F6 (
a[6],
b[6],
intermediate_carry[5],
opcode,
sum[6],
intermediate_carry[6]
);
one_bit_addr F7 (
a[7],
b[7],
intermediate_carry[6],
opcode,
sum[7],
carry
);
assign overflow = intermediate_carry[6] ^ carry;
// always @(overflow) begin
// $display("time : %d, 7th bit carry : %d, carry : %d\n\n", $time, intermediate_carry[6], carry);
// end
endmodule
| 7.124161
|
module for eight bit adder/subtracter
module eight_bit_adder_subtracter (a, b, opcode, sum, carry, overflow);
input [7:0] a, b; // operands
input opcode; // operation code
output wire [7:0] sum; // output of operation
output wire carry, overflow; // carry over and overflow
wire [6:0] intermediate_carry; // required dummy variable.
one_bit_adder_subtracter AB0 (a[0], b[0], opcode, opcode, sum[0], intermediate_carry[0]);
one_bit_adder_subtracter AB1 (a[1], b[1], intermediate_carry[0], opcode, sum[1], intermediate_carry[1]);
one_bit_adder_subtracter AB2 (a[2], b[2], intermediate_carry[1], opcode, sum[2], intermediate_carry[2]);
one_bit_adder_subtracter AB3 (a[3], b[3], intermediate_carry[2], opcode, sum[3], intermediate_carry[3]);
one_bit_adder_subtracter AB4 (a[4], b[4], intermediate_carry[3], opcode, sum[4], intermediate_carry[4]);
one_bit_adder_subtracter AB5 (a[5], b[5], intermediate_carry[4], opcode, sum[5], intermediate_carry[5]);
one_bit_adder_subtracter AB6 (a[6], b[6], intermediate_carry[5], opcode, sum[6], intermediate_carry[6]);
one_bit_adder_subtracter AB7 (a[7], b[7], intermediate_carry[6], opcode, sum[7], carry);
assign overflow = intermediate_carry[6]^carry;
endmodule
| 7.415363
|
module onebit (
a,
b,
cin,
opcode,
sum,
cout
);
input a, b, cin, opcode;
output sum, cout;
wire sum, cout;
assign sum = a ^ (b ^ opcode) ^ cin;
assign cout = (a & (b ^ opcode)) | ((b ^ opcode) & cin) | (cin & a);
endmodule
| 6.774993
|
module one_bit_full_adder (
a,
b,
cin,
opcode,
sum,
carry
);
input a;
input b;
input cin;
input opcode;
output wire sum;
output wire carry;
assign sum = cin ^ (a ^ (b ^ opcode));
assign carry = ((a & (b ^ opcode)) | ((b ^ opcode) & cin) | (cin & a));
endmodule
| 6.938543
|
module one_bit_addr (
a,
b,
cin,
opcode,
sum,
carry
);
input a, b, cin, opcode;
output sum, carry;
wire sum;
wire carry;
assign sum = a ^ (b ^ opcode) ^ cin;
assign carry = ((a & (b ^ opcode)) | ((b ^ opcode) & cin) | (a & cin));
endmodule
| 6.810869
|
module for one bit adder/subtracter
module one_bit_adder_subtracter(a, b, cin, opcode, sum, carry);
input a,b,cin,opcode; // a,b -> operands, cin -> carry in, opcode -> operation code
output wire sum, carry; // sum -> a \operation b, carry out
wire b_dummy; // additional dummy variable stores b^opcode
assign b_dummy = b^opcode;
assign sum = a^b_dummy^cin;
assign carry = (a&b_dummy) | (b_dummy&cin) | (cin&a);
endmodule
| 7.558657
|
module one_bit_full_adder_subtractor (
a,
b,
cin,
opcode,
sum,
cout
);
// Inputs
input a;
input b;
input cin;
input opcode;
// Intermediate wires
wire b_in;
// Outputs
output wire sum;
output wire cout;
// Combinational logic for the module
assign b_in = b ^ opcode;
assign sum = a ^ b_in ^ cin;
assign cout = (a & b_in) | (b_in & cin) | (a & cin);
endmodule
| 6.938543
|
module eight_bit_adder_top;
reg signed [7:0] A;
reg signed [7:0] B;
reg Opcode;
wire signed [7:0] Sum;
wire Carry;
wire Overflow;
eight_bit_adder ADDER (
A,
B,
Opcode,
Sum,
Carry,
Overflow
);
always @(A or B or Opcode or Sum or Carry or Overflow) begin
$display("time=%g: A = %d, B = %d, Opcode = %b, Sum = %d, Carry = %d, Overflow = %b", $time, A,
B, Opcode, Sum, Carry, Overflow);
end
initial begin
#100 $finish;
end
initial begin
A = 100;
B = 100;
Opcode = 1;
#1 $display("\n");
A = 50;
B = 60;
Opcode = 0;
#1 $display("\n");
A = 110;
B = 30;
Opcode = 1;
#1 $display("\n");
A = -10;
B = -12;
Opcode = 1;
#1 $display("\n");
A = 1;
B = 25;
Opcode = 1;
#1 $display("\n");
A = 20;
B = 100;
Opcode = 0;
#1 $display("\n");
A = 0;
B = 0;
Opcode = 1;
#1 $display("\n");
A = -123;
B = 6;
Opcode = 0;
#1 $display("\n");
A = 127;
B = 120;
Opcode = 1;
#1 $display("\n");
A = 5;
B = 6;
Opcode = 1;
end
endmodule
| 7.124161
|
module find_coordinates (
clk,
dir,
steps,
x,
y
);
// Inputs
input clk;
input [1:0] dir;
input [1:0] steps;
// Outputs
output reg [4:0] x;
output reg [4:0] y;
// Intermediate registers to store the changes in state
reg [4:0] cur_state_x = 0;
reg [4:0] cur_state_y = 0;
reg [4:0] provided_cord;
reg provided_op;
wire [4:0] new_cord;
wire carry_out;
// Instantiating the full-adder-subtractor module
five_bit_fulladder ADD (
provided_cord,
{{3{1'b0}}, steps[1:0]},
provided_op,
new_cord,
carry_out
);
// Calculating new position in posedge
always @(posedge clk) begin
if (dir == 2'b00) begin
provided_cord = cur_state_x;
provided_op = 0;
end else if (dir == 2'b01) begin
provided_cord = cur_state_x;
provided_op = 1;
end else if (dir == 2'b10) begin
provided_cord = cur_state_y;
provided_op = 0;
end else if (dir == 2'b11) begin
provided_cord = cur_state_y;
provided_op = 1;
end
end
// Checking for out of bound values and updating the new position in negedge
always @(negedge clk) begin
if (dir == 2'b00) begin
x = new_cord;
y = cur_state_y;
cur_state_x = new_cord;
if (new_cord[4] == 1) begin
x = 15;
cur_state_x = 15;
end
end else if (dir == 2'b01) begin
x = new_cord;
y = cur_state_y;
cur_state_x = new_cord;
if (new_cord[4] == 1) begin
x = 0;
cur_state_x = 0;
end
end else if (dir == 2'b10) begin
x = cur_state_x;
y = new_cord;
cur_state_y = new_cord;
if (new_cord[4] == 1) begin
y = 15;
cur_state_y = 15;
end
end else if (dir == 2'b11) begin
x = cur_state_x;
y = new_cord;
cur_state_y = new_cord;
if (new_cord[4] == 1) begin
y = 0;
cur_state_y = 0;
end
end
end
endmodule
| 6.938746
|
module five_bit_adder (
x,
y,
opcode,
sum
);
input [4:0] x;
input [4:0] y;
input opcode;
output wire [4:0] sum;
wire carry_out;
wire [3:0] intermediate_carry;
one_bit_full_adder FA0 (
x[0],
y[0],
opcode,
opcode,
sum[0],
intermediate_carry[0]
);
one_bit_full_adder FA1 (
x[1],
y[1],
intermediate_carry[0],
opcode,
sum[1],
intermediate_carry[1]
);
one_bit_full_adder FA2 (
x[2],
y[2],
intermediate_carry[1],
opcode,
sum[2],
intermediate_carry[2]
);
one_bit_full_adder FA3 (
x[3],
y[3],
intermediate_carry[2],
opcode,
sum[3],
intermediate_carry[3]
);
one_bit_full_adder FA4 (
x[4],
y[4],
intermediate_carry[3],
opcode,
sum[4],
carry_out
);
endmodule
| 7.094859
|
module five_bit_fulladder (
x,
y,
carry_in,
sum,
carry_out
);
// Inputs
input [4:0] x;
input [4:0] y;
input carry_in;
// Outputs
output [4:0] sum;
wire [4:0] sum;
output carry_out;
wire carry_out;
// Intermediate wire
wire [4:0] intermediate_carry;
// Instantiating the 5 one-adder modules
one_bit_full_adder FA0 (
x[0],
carry_in ^ y[0],
carry_in,
sum[0],
intermediate_carry[0]
);
one_bit_full_adder FA1 (
x[1],
carry_in ^ y[1],
intermediate_carry[0],
sum[1],
intermediate_carry[1]
);
one_bit_full_adder FA2 (
x[2],
carry_in ^ y[2],
intermediate_carry[1],
sum[2],
intermediate_carry[2]
);
one_bit_full_adder FA3 (
x[3],
carry_in ^ y[3],
intermediate_carry[2],
sum[3],
intermediate_carry[3]
);
one_bit_full_adder FA4 (
x[4],
carry_in ^ y[4],
intermediate_carry[3],
sum[4],
carry_out
);
endmodule
| 7.212021
|
module one_bit_full_adder (
a,
b,
cin,
sum,
cout
);
// Inputs
input a;
input b;
input cin;
// Outputs
output sum;
wire sum;
output cout;
wire cout;
// Combinational logic for the module
assign sum = a ^ b ^ cin;
assign cout = (a & b) | (b & cin) | (a & cin);
endmodule
| 6.938543
|
module one_bit_full_adder (
a,
b,
cin,
opcode,
sum,
carry
);
input a;
input b;
input cin;
input opcode;
output wire sum;
output wire carry;
assign sum = cin ^ (a ^ (b ^ opcode));
assign carry = ((a & (b ^ opcode)) | ((b ^ opcode) & cin) | (cin & a));
endmodule
| 6.938543
|
module onebit (
a,
b,
cin,
opcode,
sum,
cout
);
input a, b, cin, opcode;
output sum, cout;
wire sum, cout;
assign sum = a ^ (b ^ opcode) ^ cin;
assign cout = (a & (b ^ opcode)) | ((b ^ opcode) & cin) | (cin & a);
endmodule
| 6.774993
|
module worm (
in,
clk,
out1,
out2
);
input [3:0] in; // 4-bit encoded input - direction and steps
input clk;
output wire [4:0] out1, out2;
reg [4:0] state [1:0]; // Store location of worm
wire [4:0] buff; // Store next state computation results
// Storage for adder operations
reg [4:0] A, B;
reg opcode;
wire overflow, c_out;
five_bit_adder ADDER (
A,
B,
opcode,
buff,
c_out,
overflow
); // Instantiate adder module
initial begin // Inititalize at (0,0)
state[0] <= 5'd0;
state[1] <= 5'd0;
A <= 5'd0;
B <= 5'd0;
opcode <= 1'd0;
end
// Direction encoding: 00 - N, 01 - E, 10 - S, 11 - W
always @(posedge clk) begin // Compute next state using current input
A <= state[in[2]]; // Current state: state[0] for N/S, state[1] for E/W
B <= {in[1], in[0]}; // Number of steps
opcode <= in[3]; // Add steps for N/E, subtract for S/W
end
always @(negedge clk) begin // Correct overflow before updating next state
if (buff[4] == 1'b1) begin // 5th bit is 1 - result is negative or exceeds 15
state[in[2]] <= {1'b0, {4{~in[3]}}}; // Set to 15 for N/E, 0 for S/W overflow
end else begin
state[in[2]] <= buff; // no overflow
end
end
// Set outputs
assign out1 = state[0];
assign out2 = state[1];
// initial begin
// $dumpfile("worm.vcd");
// $dumpvars(0, worm);
// $dumpvars(0, state[0][4:0]);
// $dumpvars(0, state[1][4:0]);
// end
endmodule
| 7.053898
|
module one_bit_adder (
a,
b,
cin,
opcode,
sum,
carry
);
input a, b, cin, opcode;
output sum, carry;
wire sum;
wire carry;
assign sum = a ^ (b ^ opcode) ^ cin;
assign carry = ((a & (b ^ opcode)) | ((b ^ opcode) & cin) | (a & cin));
endmodule
| 6.839629
|
module five_bit_adder(in_x, in_y, dir, dist, out_x, out_y, out_carry);
input [3:0] in_x;
input [3:0] in_y;
input [1:0] dir;
input [1:0] dist;
output [4:0] out_x;
output [4:0] out_y;
output out_carry;
wire [4:0] out_x;
wire [4:0] out_y;
wire out_carry;
// 00 - east, 01 - west, 10 - north, 11 - south
wire [3:0] intermediate_carry_x;
wire [3:0] intermediate_carry_y;
wire x1;
wire x2;
wire y1;
wire y2;
// we have to change x when dir=east or west, which both have dir[1] = 0, vice versa for y
assign x1 = dist[0] & ~dir[1];
assign x2 = dist[1] & ~dir[1];
assign y1 = dist[0] & dir[1];
assign y2 = dist[1] & dir[1];
wire opcode; // operation code - sub(1) and add(0)
assign opcode = dir[0]; // since we have to sub when dir=west(01) or south(11) and vice versa
one_bit_adder X0 (in_x[0], x1, opcode, opcode, out_x[0], intermediate_carry_x[0]);
one_bit_adder X1 (in_x[1], x2, intermediate_carry_x[0], opcode, out_x[1], intermediate_carry_x[1]);
one_bit_adder X2 (in_x[2], 1'b0, intermediate_carry_x[1], opcode, out_x[2], intermediate_carry_x[2]);
one_bit_adder X3 (in_x[3], 1'b0, intermediate_carry_x[2], opcode, out_x[3], intermediate_carry_x[3]);
one_bit_adder X4 (1'b0, 1'b0, intermediate_carry_x[3], opcode, out_x[4], out_carry);
one_bit_adder Y0 (in_y[0], y1, opcode, opcode, out_y[0], intermediate_carry_y[0]);
one_bit_adder Y1 (in_y[1], y2, intermediate_carry_y[0], opcode, out_y[1], intermediate_carry_y[1]);
one_bit_adder Y2 (in_y[2], 1'b0, intermediate_carry_y[1], opcode, out_y[2], intermediate_carry_y[2]);
one_bit_adder Y3 (in_y[3], 1'b0, intermediate_carry_y[2], opcode, out_y[3], intermediate_carry_y[3]);
one_bit_adder Y4 (1'b0, 1'b0, intermediate_carry_y[3], opcode, out_y[4], out_carry);
endmodule
| 7.094859
|
module for eight bit adder/subtracter
module five_bit_adder_subtracter (a, b, opcode, sum, carry, overflow);
input [4:0] a, b; // operands
input opcode; // operation code
output wire [4:0] sum; // output of operation
output wire carry, overflow; // carry over and overflow
wire [3:0] intermediate_carry; // required dummy variable.
one_bit_adder_subtracter AB0 (a[0], b[0], opcode, opcode, sum[0], intermediate_carry[0]);
one_bit_adder_subtracter AB1 (a[1], b[1], intermediate_carry[0], opcode, sum[1], intermediate_carry[1]);
one_bit_adder_subtracter AB2 (a[2], b[2], intermediate_carry[1], opcode, sum[2], intermediate_carry[2]);
one_bit_adder_subtracter AB3 (a[3], b[3], intermediate_carry[2], opcode, sum[3], intermediate_carry[3]);
one_bit_adder_subtracter AB7 (a[4], b[4], intermediate_carry[3], opcode, sum[4], carry);
assign overflow = intermediate_carry[3]^carry;
endmodule
| 7.415363
|
module for one bit adder
module one_bit_adder (a, b, cin, sum, cout);
// inputs
input a; // first operand bit
input b; // second operand bit
input cin; // carry in bit
// outputs
output sum; // final sum bit
wire sum;
output cout; // carry out bit
wire cout;
assign sum = a^b^cin;
assign cout = (a|b)&(b|cin)&(cin|a);
endmodule
| 7.558657
|
module for one bit adder/subtracter
module one_bit_adder_subtracter(a, b, cin, opcode, sum, carry);
input a,b,cin,opcode; // a,b -> operands, cin -> carry in, opcode -> operation code
output wire sum, carry; // sum -> a \operation b, carry out
wire b_dummy; // additional dummy variable stores b^opcode
assign b_dummy = b^opcode;
assign sum = a^b_dummy^cin;
assign carry = (a&b_dummy) | (b_dummy&cin) | (cin&a);
endmodule
| 7.558657
|
module worm (
clk,
dirn,
step,
x,
y
);
input clk;
input [1:0] dirn;
input [1:0] step;
output reg [3:0] x;
output reg [3:0] y;
// Variables for ADD SUB Combinational Logic
wire [4:0] in_x;
wire [4:0] in_y;
wire [4:0] out_x;
wire [4:0] out_y;
wire [4:0] in_step;
wire over_x, over_y, carry_x, carry_y, op;
assign in_x = {1'b0, x};
assign in_y = {1'b0, y};
assign in_step = {3'b000, step};
assign op = dirn[0];
five_bit_adder_subtracter X_OP (
in_x,
in_step,
op,
out_x,
carry_x,
over_x
);
five_bit_adder_subtracter Y_OP (
in_y,
in_step,
op,
out_y,
carry_y,
over_y
);
initial begin
x = 4'b0000;
y = 4'b0000;
end
always @(posedge clk) begin
if (dirn[1] == 1'b0) begin
if (over_x == 1'b1) x <= 4'b1111;
else begin
if (out_x[4] == 1'b1) x <= 4'b0000;
else x <= out_x[3:0];
end
end else begin
if (over_y == 1'b1) y <= 4'b1111;
else begin
if (out_y[4] == 1'b1) y <= 4'b0000;
else y <= out_y[3:0];
end
end
end
endmodule
| 6.775455
|
module top_module ();
reg clk;
reg [1:0] dir_in;
reg [1:0] step_in;
wire [3:0] x;
wire [3:0] y;
worm WORM_GAME (
clk,
dir_in,
step_in,
x,
y
);
always @(posedge clk) begin
$display("Time: %3d, Input: Direction: %d Steps: %d, Output: x: %d, y : %d, ", $time, dir_in,
step_in, x, y);
end
always @(x | y) begin
$display("Time: %3d, Input: Direction: %d Steps: %d, Output: x: %d, y : %d, ", $time, dir_in,
step_in, x, y);
end
initial begin
#150 $finish;
end
initial begin
clk = 0; // Implementing clock with time period 10 units and 50% duty cycle for 10 cycles.
repeat (30) begin
#5 clk = ~clk;
end
end
initial begin
$display("Direction: 0: EAST, 1: WEST, 2: NORTH, 3: SOUTH");
#3 dir_in = 2'b01;
step_in = 2'b01;
$display("\n");
#10 dir_in = 2'b10;
step_in = 2'b11;
$display("\n");
#10 dir_in = 2'b11;
step_in = 2'b01;
$display("\n");
#10 dir_in = 2'b11;
step_in = 2'b01;
$display("\n");
#10 dir_in = 2'b01;
step_in = 2'b11;
$display("\n");
#10 dir_in = 2'b10;
step_in = 2'b10;
$display("\n");
#10 dir_in = 2'b10;
step_in = 2'b11;
$display("\n");
#10 dir_in = 2'b10;
step_in = 2'b11;
$display("\n");
#10 dir_in = 2'b10;
step_in = 2'b11;
$display("\n");
#10 dir_in = 2'b10;
step_in = 2'b11;
$display("\n");
#10 dir_in = 2'b01;
step_in = 2'b01;
$display("\n");
#10 dir_in = 2'b00;
step_in = 2'b10;
$display("\n");
#10 dir_in = 2'b00;
step_in = 2'b10;
$display("\n");
#10 step_in = 2'b00;
end
endmodule
| 6.627149
|
module A5001_3 (
//inputs
input wire SLBD7, //2 I1
input wire SLD7, //3 I2
input wire SLD0, //4 I3
input wire SLD1, //5 I4
input wire SLD2, //6 I5
input wire i7, //7 VCC I6
input wire i8, //8 VCC I7
input wire i9, //9 VCC I8
input wire i11, //11 VCC I9
input wire H1_SD30_r, //13 B1
//outputs
output wire COLBANK5, //12 B0
output wire LAYER_SELA, //15 B3
output wire LAYER_SELB, //16 B4
output wire COLBANK3, //17 B5
output wire COLBANK4 //18 B6
);
// !COLBANK5 =>
// !H1_SD30_r & !SLD7 & !SLD0 & SLD1 & SLD2
// # !H1_SD30_r & !SLD0 & SLD1 & SLD2 & VCC & VCC & VCC
// # !H1_SD30_r & SLD1 & SLD2 & !VCC & VCC & VCC & VCC
// !LAYER_SELA =>
// !H1_SD30_r & SLD1 & SLD2
// # !H1_SD30_r & SLD7 & !VCC
// # !H1_SD30_r & SLD7 & !VCC
// # !H1_SD30_r & SLD7 & !VCC
// !LAYER_SELB =>
// !H1_SD30_r & SLD1 & SLD2 & VCC & VCC & VCC
// !COLBANK3 =>
// !H1_SD30_r & !SLBD7
// # !H1_SD30_r & !SLD1
// # !H1_SD30_r & !SLD2
// # !H1_SD30_r & !VCC
// # !H1_SD30_r & !VCC
// # !H1_SD30_r & !VCC
// !COLBANK4 =>
// !H1_SD30_r & SLBD7
// # !H1_SD30_r & !SLD1
// # !H1_SD30_r & !SLD2
// # !H1_SD30_r & !VCC
// # !H1_SD30_r & !VCC
// # !H1_SD30_r & !VCC
wire H1_SD30_r_neg;
wire SLBD7_neg;
wire SLD7_neg;
wire SLD0_neg;
wire SLD1_neg;
wire SLD2_neg;
assign H1_SD30_r_neg = ~H1_SD30_r;
assign SLBD7_neg = ~SLBD7;
assign SLD7_neg = ~SLD7;
assign SLD0_neg = ~SLD0;
assign SLD1_neg = ~SLD1;
assign SLD2_neg = ~SLD2;
//------------------------------------------------------
// assign COLBANK5 = ~((H1_SD30_r_neg & SLD7_neg & SLD0_neg & SLD1 & SLD2) |
// (H1_SD30_r_neg & SLD0_neg & SLD1 & SLD2) |
// (H1_SD30_r_neg & SLD1 & SLD2));
assign COLBANK5 = ~((H1_SD30_r_neg & SLD7_neg & SLD0_neg & SLD1 & SLD2) |
(H1_SD30_r_neg & SLD0_neg & SLD1 & SLD2));
//------------------------------------------------------
assign LAYER_SELA = ~((H1_SD30_r_neg & SLD1 & SLD2));
//------------------------------------------------------
assign LAYER_SELB = ~((H1_SD30_r_neg & SLD1 & SLD2));
//------------------------------------------------------
assign COLBANK3 = ~((H1_SD30_r_neg & SLBD7_neg ) |
(H1_SD30_r_neg & SLD1_neg ) |
(H1_SD30_r_neg & SLD2_neg ));
//------------------------------------------------------
assign COLBANK4 = ~((H1_SD30_r_neg & SLBD7 ) |
(H1_SD30_r_neg & SLD1_neg ) |
(H1_SD30_r_neg & SLD2_neg ));
endmodule
| 7.288772
|
module A5004_3 (
//inputs
input wire SD31, //1
input wire SD0, //2
input wire SLD7, //3
input wire SLD0, //4
input wire SLD1, //5
input wire SLD2, //6
input wire L2D0, //7
input wire L2D1, //8
input wire L2D2, //9
input wire i11, //11 VCC
input wire SD31_r, //13
input wire SD30_ANDr, //14
//outputs
output wire COLBANK5, //12
output wire LAYER_SELA, //15
output wire LAYER_SELB, //16
output wire COLBANK3, //17
output wire COLBANK4, //18
output wire SD30_AND //19
);
wire SD31_r_neg;
wire SD31_neg;
wire SD30_ANDr_neg;
wire SD0_neg;
wire SLBD7_neg;
wire SLD7_neg;
wire SLD0_neg;
wire SLD1_neg;
wire SLD2_neg;
wire L2D2_neg;
wire L2D1_neg;
wire L2D0_neg;
wire i11_neg;
assign SD31_r_neg = ~SD31_r;
assign SD30_ANDr_neg = ~SD30_ANDr;
assign SLD7_neg = ~SLD7;
assign SLD0_neg = ~SLD0;
assign SLD1_neg = ~SLD1;
assign SLD2_neg = ~SLD2;
assign L2D2_neg = ~L2D2;
assign L2D1_neg = ~L2D1;
assign L2D0_neg = ~L2D0;
assign i11_neg = ~i11;
assign SD31_neg = ~SD31;
assign SD0_neg = ~SD0;
assign COLBANK5 = ~((SD30_ANDr_neg )|
( SLD7_neg & SLD0_neg & SLD1 & SLD2 & SD31_r_neg)|
( SLD0_neg & SLD1 & SLD2 & L2D1 & L2D2 & i11 & SD31_r_neg)|
( SLD1 & SLD2 & L2D0_neg & L2D1 & L2D2 & i11 & SD31_r_neg));
//------------------------------------------------------
assign LAYER_SELA = ~((SLD7 & L2D1_neg & SD31_r_neg)|
(SLD7 & L2D2_neg & SD31_r_neg)|
(SLD7 & i11_neg & SD31_r_neg)|
(SLD1 & SLD2 & SD31_r_neg));
//------------------------------------------------------
assign LAYER_SELB = ~((SLD1 & SLD2 & L2D1 & L2D2 & i11 & SD31_r_neg));
//------------------------------------------------------
assign COLBANK3 = ~((SLD1 & SLD2 & L2D1 & L2D2 & i11 & SD31_r_neg) | (LAYER_SELA & SD31_r_neg));
//------------------------------------------------------
assign COLBANK4 = ~((SLD1_neg & SD31_r_neg)|
(SLD2_neg & SD31_r_neg)|
(L2D1_neg & SD31_r_neg)|
(L2D2_neg & SD31_r_neg)|
(i11_neg & SD31_r_neg));
assign SD30_AND = ~(SD31_neg & SD0_neg);
endmodule
| 6.662153
|
module A500_ACCEL (
// Control Inputs and Outputs
input RESET,
input MB_CLK,
input CPU_CLK,
input CPU_AS,
output MB_AS,
input MB_DTACK,
output CPU_DTACK,
output MB_E_CLK,
input MB_VPA,
output MB_VMA,
input [2:0] FC,
input INTERNAL_CYCLE
);
reg delayedMB_AS = 1'b1;
reg delayedMB_DTACK = 1'b1;
reg fastCPU_DTACK = 1'b1;
wire emulated_DTACK;
assign MB_AS = delayedMB_AS;
assign CPU_DTACK = emulated_DTACK & delayedMB_DTACK & fastCPU_DTACK;
MC6800 MC6800EMULATION (
.RESET(RESET),
.CLK (MB_CLK),
.E_CLK(MB_E_CLK),
.VPA (MB_VPA),
.VMA (MB_VMA),
.DTACK(emulated_DTACK),
.AS (CPU_AS),
.FC (FC)
);
// Shift /CPU_AS into the 7MHz clock domain gated by /INTERNAL_CYCLE.
// Delay /MB_DTACK by 1 7MHz clock cycle to sync up to asynchronous CPU_CLK.
always @(posedge MB_CLK or posedge CPU_AS) begin
if (CPU_AS == 1'b1) begin
delayedMB_DTACK <= 1'b1;
delayedMB_AS <= 1'b1;
end else begin
delayedMB_AS <= CPU_AS | ~INTERNAL_CYCLE;
/*
delayedMB_DTACK <= MB_DTACK | delayedMB_AS;
*/
delayedMB_DTACK <= MB_DTACK;
end
end
// Generate a fast DTACK for accesses in Interal Space (FastRAM, IO Portetc)
always @(posedge CPU_CLK or posedge CPU_AS) begin
if (CPU_AS == 1'b1) begin
fastCPU_DTACK <= 1'b1;
end else begin
fastCPU_DTACK <= INTERNAL_CYCLE;
end
end
endmodule
| 6.662404
|
module A5Buffer (
input wire clk,
input wire reset_n,
input wire load,
output wire [31:0] data_out,
output wire empty,
output wire full,
output wire busy,
input wire rd_en,
input wire [63:0] key,
input wire [21:0] frame
);
reg fifo_wr_en;
reg [31:0] shift_reg;
wire a5_out;
wire lfsr_stall = full | fifo_wr_en;
wire lfsr_valid;
A5Generator A5Generator (
.clk(clk),
.reset_n(reset_n),
.load(load),
.stall(lfsr_stall),
.q(a5_out),
.valid(lfsr_valid),
.busy(busy),
.key(key),
.frame(frame)
);
Fifo #(
.data_width(32),
.depth(4)
) Fifo (
.clk(clk),
.reset_n(reset_n),
.flush(load),
.wr_en(fifo_wr_en),
.wr_data(shift_reg),
.rd_en(rd_en),
.rd_data(data_out),
.empty(empty),
.full(full)
);
always @(posedge clk or negedge reset_n)
if (!reset_n) {shift_reg, fifo_wr_en} <= {1'b1, 32'b0};
else
{shift_reg, fifo_wr_en} <=
!lfsr_valid || load || fifo_wr_en ? {1'b1, 32'b0} :
lfsr_stall ? {shift_reg, fifo_wr_en} :
{a5_out, shift_reg};
endmodule
| 8.191081
|
module A5Generator (
input wire clk,
input wire reset_n,
input wire load,
input wire stall,
output wire q,
output reg valid,
output wire busy,
input wire [63:0] key,
input wire [21:0] frame
);
wire l0_q;
wire l1_q;
wire l2_q;
reg [85:0] init_sr;
wire lfsr_in = init_sr[0];
wire [2:0] lfsr_clk_en = ({3{~stall}} & {lfsr_clk_bits[2] == clk_bit_majority,
lfsr_clk_bits[1] == clk_bit_majority,
lfsr_clk_bits[0] == clk_bit_majority}) | {3{clock_unconditional}};
wire [2:0] lfsr_clk_bits;
wire clock_unconditional = init_cycle_count > 99;
reg clk_bit_majority;
// 64 key bits + 22 frame number bits + 100 mix 0's
localparam init_cycles = 64 + 22 + 100;
localparam init_bits = $clog2(init_cycles);
reg [init_bits-1:0] init_cycle_count;
reg init_done;
assign q = l0_q ^ l1_q ^ l2_q;
assign busy = |init_cycle_count | valid | init_done;
always @(posedge clk)
if (load) init_sr <= {frame, key};
else init_sr <= {1'b0, init_sr[85:1]};
always @(posedge clk or negedge reset_n)
if (!reset_n) init_done <= 1'b0;
else init_done <= load ? 1'b0 : ~|init_cycle_count;
always @(posedge clk or negedge reset_n)
if (!reset_n) valid <= 1'b0;
else valid <= load ? 1'b0 : init_done;
always @(posedge clk or negedge reset_n)
if (!reset_n) init_cycle_count <= init_cycles - 1'b1;
else begin
if (load) init_cycle_count <= init_cycles - 1'b1;
else if (|init_cycle_count) init_cycle_count <= init_cycle_count - 1'b1;
end
always @(*) begin
case (lfsr_clk_bits)
3'b000: clk_bit_majority = 1'b0;
3'b001: clk_bit_majority = 1'b0;
3'b010: clk_bit_majority = 1'b0;
3'b011: clk_bit_majority = 1'b1;
3'b100: clk_bit_majority = 1'b0;
3'b101: clk_bit_majority = 1'b1;
3'b110: clk_bit_majority = 1'b1;
3'b111: clk_bit_majority = 1'b1;
endcase
end
A5LFSR #(
.num_bits (19),
.num_taps (4),
.tap_bits (19'b111_0010_0000_0000_0000),
.clock_bit(8)
) l0 (
.clk(clk),
.reset_n(reset_n),
.load(load),
.clk_en(lfsr_clk_en[0]),
.d(lfsr_in),
.q(l0_q),
.clk_bit_o(lfsr_clk_bits[0])
);
A5LFSR #(
.num_bits (22),
.num_taps (4),
.tap_bits (22'b11_0000_0000_0000_0000_0000),
.clock_bit(10)
) l1 (
.clk(clk),
.reset_n(reset_n),
.load(load),
.clk_en(lfsr_clk_en[1]),
.d(lfsr_in),
.q(l1_q),
.clk_bit_o(lfsr_clk_bits[1])
);
A5LFSR #(
.num_bits (23),
.num_taps (4),
.tap_bits (23'b111_0000_0000_0000_1000_0000),
.clock_bit(10)
) l2 (
.clk(clk),
.reset_n(reset_n),
.load(load),
.clk_en(lfsr_clk_en[2]),
.d(lfsr_in),
.q(l2_q),
.clk_bit_o(lfsr_clk_bits[2])
);
endmodule
| 6.6567
|
module A5If (
input wire clk,
input wire reset_n,
input wire wbs_stb_i,
input wire wbs_cyc_i,
input wire wbs_we_i,
input wire [3:0] wbs_sel_i,
input wire [31:0] wbs_dat_i,
input wire [31:0] wbs_adr_i,
output reg wbs_ack_o,
output reg [31:0] wbs_dat_o
);
localparam REG_ID_OFFS = 'h00;
localparam REG_STATUS_OFFS = 'h04;
localparam REG_CONTROL_OFFS = 'h08;
localparam REG_DATA_OFFS = 'h0c;
localparam REG_KEY_LO_OFFS = 'h10;
localparam REG_KEY_HI_OFFS = 'h14;
localparam REG_FRAME_OFFS = 'h18;
wire access = wbs_stb_i & wbs_cyc_i & ~wbs_ack_o;
wire reg_access_id = access && wbs_adr_i[4:0] == REG_ID_OFFS;
wire reg_access_status = access && wbs_adr_i[4:0] == REG_STATUS_OFFS;
wire reg_access_control = access && wbs_adr_i[4:0] == REG_CONTROL_OFFS;
wire reg_access_data = access && wbs_adr_i[4:0] == REG_DATA_OFFS;
wire reg_access_key_lo = access && wbs_adr_i[4:0] == REG_KEY_LO_OFFS;
wire reg_access_key_hi = access && wbs_adr_i[4:0] == REG_KEY_HI_OFFS;
wire reg_access_frame = access && wbs_adr_i[4:0] == REG_FRAME_OFFS;
wire [31:0] id_o = 32'h41354135;
wire [31:0] status_o = {29'b0, keystream_busy, keystream_full, ~keystream_empty};
wire [31:0] control_o = 32'b0;
wire [31:0] data_o = keystream_data;
wire [31:0] key_lo_o = key[31:0];
wire [31:0] key_hi_o = key[63:32];
wire [31:0] frame_o = {10'b0, frame};
reg [31:0] wb_data_o;
wire [31:0] keystream_data;
wire keystream_empty;
wire keystream_full;
wire keystream_busy;
reg keystream_read;
reg keystream_load;
reg [63:0] key;
reg [21:0] frame;
A5Buffer A5Buffer (
.clk(clk),
.reset_n(reset_n),
.load(keystream_load),
.data_out(keystream_data),
.empty(keystream_empty),
.full(keystream_full),
.busy(keystream_busy),
.rd_en(keystream_read),
.key(key),
.frame(frame)
);
always @(*) begin
case (wbs_adr_i[5:0])
REG_ID_OFFS: wb_data_o = id_o;
REG_STATUS_OFFS: wb_data_o = status_o;
REG_CONTROL_OFFS: wb_data_o = control_o;
REG_DATA_OFFS: wb_data_o = data_o;
REG_KEY_LO_OFFS: wb_data_o = key_lo_o;
REG_KEY_HI_OFFS: wb_data_o = key_hi_o;
REG_FRAME_OFFS: wb_data_o = frame_o;
default: wb_data_o = 32'b0;
endcase
end
always @(posedge clk or negedge reset_n)
if (!reset_n) key <= 64'b0;
else begin
if (reg_access_key_lo && wbs_we_i && &wbs_sel_i) key[31:0] <= wbs_dat_i;
if (reg_access_key_hi && wbs_we_i && &wbs_sel_i) key[63:32] <= wbs_dat_i;
end
always @(posedge clk or negedge reset_n)
if (!reset_n) frame <= 22'b0;
else if (reg_access_frame && wbs_we_i && &wbs_sel_i) frame <= wbs_dat_i[21:0];
always @(posedge clk or negedge reset_n)
if (!reset_n) keystream_load <= 1'b0;
else begin
keystream_load <= 1'b0;
if (reg_access_control && wbs_we_i && &wbs_sel_i) keystream_load <= wbs_dat_i[0];
end
always @(posedge clk or negedge reset_n)
if (!reset_n) keystream_read <= 1'b0;
else keystream_read <= reg_access_data & ~wbs_we_i & ~keystream_empty;
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
wbs_ack_o <= 1'b0;
wbs_dat_o <= 32'b0;
end else begin
wbs_ack_o <= access;
wbs_dat_o <= access ? wb_data_o : 32'b0;
end
end
endmodule
| 9.099055
|
module A5LFSR #(
parameter num_bits = 8,
parameter num_taps = 3,
parameter tap_bits = 8'h80,
parameter clock_bit = 0
) (
input wire clk,
input wire reset_n,
input wire load,
input wire clk_en,
input wire d,
output wire q,
output wire clk_bit_o
);
reg [num_bits-1:0] sr;
reg feedback;
wire [num_bits-1:0] next_sr = load ? {num_bits{1'b0}} :
clk_en ? {sr[num_bits-2:0], d ^ feedback} :
sr;
integer i;
assign q = sr[num_bits-1];
assign clk_bit_o = sr[clock_bit];
always @(*) begin
feedback = 1'b0;
for (i = 0; i < num_bits; i = i + 1) begin
if (tap_bits[i]) feedback = feedback ^ sr[i];
end
end
always @(posedge clk or negedge reset_n)
if (!reset_n) sr <= {num_bits{1'b0}};
else sr <= next_sr;
endmodule
| 6.84437
|
module for four bit incrementer
module four_bit_incrementer (x, sum);
// inputs
input [3:0] x; // one four-bit operand
// outputs
output [3:0] sum; // 4-bit sum
wire [3:0] sum;
// output carry_out; // carry-out bit ( not used in the implementation )
wire carry_out;
wire [2:0] intermediate_carry;
// connecting 4 one-bit half adders to make four bit incrementer
one_bit_half_adder HA0 (x[0], 1'b1, sum[0], intermediate_carry[0]);
one_bit_half_adder HA1 (x[1], intermediate_carry[0], sum[1], intermediate_carry[1]);
one_bit_half_adder HA2 (x[2], intermediate_carry[1], sum[2], intermediate_carry[2]);
one_bit_half_adder HA3 (x[3], intermediate_carry[2], sum[3], carry_out);
endmodule
| 8.016617
|
module fsm (y, clk, state);
input [1:0] y;
input clk;
output reg [3:0] state;
reg [2:0] dispatchROM1 [2:0];
reg [3:0] dispatchROM2 [1:0];
reg [2:0] microcodeROM [12:0];
initial begin
state = 0;
dispatchROM1[0] = 4;
dispatchROM1[1] = 5;
dispatchROM1[2] = 6;
dispatchROM2[0] = 11;
dispatchROM2[1] = 12;
microcodeROM[0] = 0;
microcodeROM[1] = 0;
microcodeROM[2] = 0;
microcodeROM[3] = 1;
microcodeROM[4] = 2;
microcodeROM[5] = 2;
microcodeROM[6] = 0;
microcodeROM[7] = 0;
microcodeROM[8] = 0;
microcodeROM[9] = 0;
microcodeROM[10] = 3;
microcodeROM[11] = 4;
microcodeROM[12] = 4;
end
always @(posedge clk) begin
case (microcodeROM[state])
0: state <= `TICK state + 1;
1: begin
case (y)
2'b00: state <= `TICK dispatchROM1[0];
2'b01: state <= `TICK dispatchROM1[1];
default: state <= `TICK dispatchROM1[2];
endcase
end
2: state <= `TICK 7;
3: begin
case (y)
2'b00: state <= `TICK dispatchROM2[0];
default: state <= `TICK dispatchROM2[1];
endcase
end
4: state <= `TICK 0;
endcase
end
endmodule
| 6.847314
|
module top_module ();
reg clk;
reg [1:0] inp;
wire [3:0] out;
FSM fsm (
clk,
inp,
out
);
initial begin
#150 $finish; // Simulating for 15 clock cycles
end
initial begin
clk = 0;
clk = 1; // Implementing clock with time period 10 units and 50% duty cycle for 10 cycles.
repeat (30) begin
#5 clk = ~clk;
end
end
always @(posedge clk) begin
$display("Time: %3d Input: %b Output: (Current State to be Changed) %b = %4d", $time, inp, out,
out);
end
initial begin
#8 inp = 2'b00;
//$display("\n");
#10 inp = 2'b01;
//$display("\n");
#10 inp = 2'b11;
//$display("\n");
#10 inp = 2'b10;
//$display("\n");
#10 inp = 2'b00;
//$display("\n");
#10 inp = 2'b11;
//$display("\n");
#10 inp = 2'b00;
//$display("\n");
#10 inp = 2'b01;
//$display("\n");
#10 inp = 2'b10;
//$display("\n");
#10 inp = 2'b11;
//$display("\n");
#10 inp = 2'b00;
//$display("\n");
#10 inp = 2'b10;
//$display("\n");
#10 inp = 2'b00;
//$display("\n");
#10 inp = 2'b11;
//$display("\n");
#10 inp = 2'b01;
end
endmodule
| 6.627149
|
module next_state (
current_state,
clk,
branch_control,
new_state,
in
);
input clk;
input [3:0] current_state;
input [2:0] branch_control;
input [1:0] in;
output reg [3:0] new_state;
reg [3:0] dispatches[1:0][3:0]; // Dispatch ROMs
initial begin
// Dispatch ROM for branch 1: Transitions for S3
dispatches[0][0] <= 4'd4;
dispatches[0][1] <= 4'd5;
dispatches[0][2] <= 4'd6;
dispatches[0][3] <= 4'd6;
// Dispatch ROM for branch 2: Transitions for S10
dispatches[1][0] <= 4'd11;
dispatches[1][1] <= 4'd12;
dispatches[1][2] <= 4'd12;
dispatches[1][3] <= 4'd12;
new_state <= 4'd0; // Initialize next_state with
end
always @(posedge clk) begin
#2 // Propagation delay modelling - we wait for branch control and input fetch
if (branch_control == 3'd0) begin
new_state <= current_state + 4'd1; // Increment current_state by 1
end else if (branch_control == 3'd1) begin
new_state <= dispatches[0][in]; // Fetch from dispatch ROMs
end else if (branch_control == 3'd2) begin
new_state <= dispatches[1][in]; // Fetch from dispatch ROMs
end else if (branch_control == 3'd3) begin
new_state <= 4'd7; // Branch 3: All transitions to S7
end else begin
new_state <= 4'd0; // Branch 4: All transitions to S0
end
end
endmodule
| 7.081991
|
module for one bit half adder
module one_bit_half_adder (a, b, sum, cout);
// inputs
input a; // first operand bit
input b; // second operand bit
// outputs
output sum; // final sum bit
wire sum;
output cout; // carry out bit
wire cout;
assign sum = a^b;
assign cout = a&b;
endmodule
| 7.287761
|
module microcode (
input_address,
output_data
);
input [3:0] input_address;
output reg [2:0] output_data; //Micro Instruction
reg [2:0] micro_code_rom[0:12];
initial begin
micro_code_rom[0] = 3'b000;
micro_code_rom[1] = 3'b000;
micro_code_rom[2] = 3'b000;
micro_code_rom[3] = 3'b001;
micro_code_rom[4] = 3'b010;
micro_code_rom[5] = 3'b010;
micro_code_rom[6] = 3'b000;
micro_code_rom[7] = 3'b000;
micro_code_rom[8] = 3'b000;
micro_code_rom[9] = 3'b000;
micro_code_rom[10] = 3'b011;
micro_code_rom[11] = 3'b100;
micro_code_rom[12] = 3'b100;
output_data = 3'b000;
end
always @(input_address) begin
output_data <= micro_code_rom[input_address];
end
endmodule
| 6.907893
|
module get_index (
a,
b,
c,
d,
index
);
// Inputs
input [2:0] a, b, c, d;
// Outputs
output wire [1:0] index;
// Intermediate wires
wire Less1, Less2, Less3;
wire Equal1, Equal2, Equal3;
wire Greater1, Greater2, Greater3;
wire [2:0] out1, out2;
// Combinational Logic for finding max_index
three_bit_comparator COMPARATOR1 (
a,
b,
1'b0,
1'b1,
1'b0,
Less1,
Equal1,
Greater1
);
mux_2to1 MUX1 (
a,
b,
Greater1,
out1
);
three_bit_comparator COMPARATOR2 (
c,
d,
1'b0,
1'b1,
1'b0,
Less2,
Equal2,
Greater2
);
mux_2to1 MUX2 (
c,
d,
Greater2,
out2
);
three_bit_comparator COMPARATOR3 (
out1,
out2,
1'b0,
1'b1,
1'b0,
Less3,
Equal3,
Greater3
);
assign index = Greater3 ? {{1'b1}, Greater2} : {{1'b0}, Greater1};
endmodule
| 7.781566
|
module least_index (
A,
B,
C,
D,
index
);
input [2:0] A, B, C, D;
output reg [1:0] index;
wire [5:0] l;
wire e, g;
// For instant output we have to manually compare all possible combinations
three_bit_comparator COMP1 (
A,
B,
l[0],
e,
g
);
three_bit_comparator COMP2 (
C,
D,
l[1],
e,
g
);
three_bit_comparator COMP3 (
A,
C,
l[2],
e,
g
);
three_bit_comparator COMP4 (
B,
D,
l[3],
e,
g
);
three_bit_comparator COMP5 (
A,
D,
l[4],
e,
g
);
three_bit_comparator COMP6 (
B,
C,
l[5],
e,
g
);
always @(A or B or C or D or l) begin
if (l[0]) begin
if (l[2]) begin
if (l[4]) begin
index <= 2'b00; // case: A < B && A < C && A < D
end else begin
index <= 2'b11; // case: A < B && A < C && A > D
end
end else begin
if (l[1]) begin
index <= 2'b10; // case: A < B && A > C && C < D
end else begin
index <= 2'b11; // case: A < B && A > C && C > D
end
end
end else begin
if (l[3]) begin
if (l[5]) begin
index <= 2'b01; // case: A > B && B < D && B < C
end else begin
index <= 2'b10; // case: A > B && B < D && B > C
end
end else begin
if (l[1]) begin
index <= 2'b10; // case: A > B && B > D && C < D
end else begin
index <= 2'b11; // case: A > B && B > D && C > D
end
end
end
end
// initial begin
// $dumpfile("least.vcd");
// $dumpvars(0, least_index);
// end
endmodule
| 7.433294
|
module minm (
A0,
A1,
A2,
A3,
out
);
// 4 3-bit inputs
input [2:0] A0;
input [2:0] A1;
input [2:0] A2;
input [2:0] A3;
// stores least index
output wire [1:0] out;
wire l0, l1, l2;
wire [2:0] B0; // stores min of A0 and A1.
wire [2:0] B1; // stores min of A2 and A3.
three_bit_comparator c1 (
A1,
A0,
l0
);
three_bit_comparator c2 (
A3,
A2,
l1
);
assign B0[0] = ((l0 & A1[0]) | ((~l0) & A0[0]));
assign B0[1] = ((l0 & A1[1]) | ((~l0) & A0[1]));
assign B0[2] = ((l0 & A1[2]) | ((~l0) & A0[2]));
assign B1[0] = ((l1 & A3[0]) | ((~l1) & A2[0]));
assign B1[1] = ((l1 & A3[1]) | ((~l1) & A2[1]));
assign B1[2] = ((l1 & A3[2]) | ((~l1) & A2[2]));
three_bit_comparator c3 (
B1,
B0,
l2
);
assign out[1] = l2;
assign out[0] = ((l2 & l1) | ((~l2) & l0));
endmodule
| 7.522956
|
module mux_2to1 (
input [2:0] a,
input [2:0] b,
input s,
output [2:0] out
);
assign out = s ? b : a;
endmodule
| 7.207195
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.