code
stringlengths 35
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| score
float64 6.5
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module ac97_soc (
clk,
wclk,
rst,
ps_ce,
resume,
suspended,
sync,
out_le,
in_valid,
ld,
valid
);
input clk, wclk, rst;
input ps_ce;
input resume;
output suspended;
output sync;
output [5:0] out_le;
output [2:0] in_valid;
output ld;
output valid;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg [7:0] cnt;
reg sync_beat;
reg sync_resume;
reg [5:0] out_le;
reg ld;
reg valid;
reg [2:0] in_valid;
reg bit_clk_r;
reg bit_clk_r1;
reg bit_clk_e;
reg suspended;
wire to;
reg [5:0] to_cnt;
reg [3:0] res_cnt;
wire resume_done;
assign sync = sync_beat | sync_resume;
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
always @(posedge clk or negedge rst)
if (!rst) cnt <= #1 8'hff;
else if (suspended) cnt <= #1 8'hff;
else cnt <= #1 cnt + 8'h1;
always @(posedge clk) ld <= #1 (cnt == 8'h00);
always @(posedge clk) sync_beat <= #1 (cnt == 8'h00) | ((cnt > 8'h00) & (cnt < 8'h10));
always @(posedge clk) valid <= #1 (cnt > 8'h39);
always @(posedge clk) out_le[0] <= #1 (cnt == 8'h11); // Slot 0 Latch Enable
always @(posedge clk) out_le[1] <= #1 (cnt == 8'h25); // Slot 1 Latch Enable
always @(posedge clk) out_le[2] <= #1 (cnt == 8'h39); // Slot 2 Latch Enable
always @(posedge clk) out_le[3] <= #1 (cnt == 8'h4d); // Slot 3 Latch Enable
always @(posedge clk) out_le[4] <= #1 (cnt == 8'h61); // Slot 4 Latch Enable
always @(posedge clk) out_le[5] <= #1 (cnt == 8'h89); // Slot 6 Latch Enable
always @(posedge clk) in_valid[0] <= #1 (cnt > 8'h4d); // Input Slot 3 Valid
always @(posedge clk) in_valid[1] <= #1 (cnt > 8'h61); // Input Slot 3 Valid
always @(posedge clk) in_valid[2] <= #1 (cnt > 8'h89); // Input Slot 3 Valid
////////////////////////////////////////////////////////////////////
//
// Suspend Detect
//
always @(posedge wclk) bit_clk_r <= #1 clk;
always @(posedge wclk) bit_clk_r1 <= #1 bit_clk_r;
always @(posedge wclk) bit_clk_e <= #1 (bit_clk_r & !bit_clk_r1) | (!bit_clk_r & bit_clk_r1);
always @(posedge wclk) suspended <= #1 to;
assign to = (to_cnt == `AC97_SUSP_DET);
always @(posedge wclk or negedge rst)
if (!rst) to_cnt <= #1 6'h0;
else if (bit_clk_e) to_cnt <= #1 6'h0;
else if (!to) to_cnt <= #1 to_cnt + 6'h1;
////////////////////////////////////////////////////////////////////
//
// Resume Signaling
//
always @(posedge wclk or negedge rst)
if (!rst) sync_resume <= #1 1'b0;
else if (resume_done) sync_resume <= #1 1'b0;
else if (suspended & resume) sync_resume <= #1 1'b1;
assign resume_done = (res_cnt == `AC97_RES_SIG);
always @(posedge wclk)
if (!sync_resume) res_cnt <= #1 4'h0;
else if (ps_ce) res_cnt <= #1 res_cnt + 4'h1;
endmodule
| 6.874042
|
module ac97_transceiver (
input sys_clk,
input sys_rst,
input ac97_clk,
input ac97_rst_n,
/* to codec */
input ac97_sin,
output reg ac97_sout,
output reg ac97_sync,
/* to system, upstream */
output up_stb,
input up_ack,
output up_sync,
output up_data,
/* to system, downstream */
output down_ready,
input down_stb,
input down_sync,
input down_data
);
/* Upstream */
reg ac97_sin_r;
always @(negedge ac97_clk) ac97_sin_r <= ac97_sin;
reg ac97_syncfb_r;
always @(negedge ac97_clk) ac97_syncfb_r <= ac97_sync;
wire up_empty;
asfifo #(
.data_width(2),
.address_width(6)
) up_fifo (
.data_out({up_sync, up_data}),
.empty(up_empty),
.read_en(up_ack),
.clk_read(sys_clk),
.data_in({ac97_syncfb_r, ac97_sin_r}),
.full(),
.write_en(1'b1),
.clk_write(~ac97_clk),
.rst(sys_rst)
);
assign up_stb = ~up_empty;
/* Downstream */
/* Set SOUT and SYNC to 0 during RESET to avoid ATE/Test Mode */
wire ac97_sync_r;
always @(negedge ac97_rst_n, posedge ac97_clk) begin
if (~ac97_rst_n) ac97_sync <= 1'b0;
else ac97_sync <= ac97_sync_r;
end
wire ac97_sout_r;
always @(negedge ac97_rst_n, posedge ac97_clk) begin
if (~ac97_rst_n) ac97_sout <= 1'b0;
else ac97_sout <= ac97_sout_r;
end
wire down_full;
asfifo #(
.data_width(2),
.address_width(6)
) down_fifo (
.data_out({ac97_sync_r, ac97_sout_r}),
.empty(),
.read_en(1'b1),
.clk_read(ac97_clk),
.data_in({down_sync, down_data}),
.full(down_full),
.write_en(down_stb),
.clk_write(sys_clk),
.rst(sys_rst)
);
assign down_ready = ~down_full;
endmodule
| 7.297785
|
module ac97_wb_if (
clk,
rst,
wb_data_i,
wb_data_o,
wb_addr_i,
wb_sel_i,
wb_we_i,
wb_cyc_i,
wb_stb_i,
wb_ack_o,
wb_err_o,
adr,
dout,
rf_din,
i3_din,
i4_din,
i6_din,
rf_we,
rf_re,
o3_we,
o4_we,
o6_we,
o7_we,
o8_we,
o9_we,
i3_re,
i4_re,
i6_re
);
input clk, rst;
// WISHBONE Interface
input [31:0] wb_data_i;
output [31:0] wb_data_o;
input [31:0] wb_addr_i;
input [3:0] wb_sel_i;
input wb_we_i;
input wb_cyc_i;
input wb_stb_i;
output wb_ack_o;
output wb_err_o;
// Internal Interface
output [3:0] adr;
output [31:0] dout;
input [31:0] rf_din, i3_din, i4_din, i6_din;
output rf_we;
output rf_re;
output o3_we, o4_we, o6_we, o7_we, o8_we, o9_we;
output i3_re, i4_re, i6_re;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg [31:0] wb_data_o;
reg [31:0] dout;
reg wb_ack_o;
reg rf_we;
reg o3_we, o4_we, o6_we, o7_we, o8_we, o9_we;
reg i3_re, i4_re, i6_re;
reg we1, we2;
wire we;
reg re2, re1;
wire re;
////////////////////////////////////////////////////////////////////
//
// Modules
//
assign adr = wb_addr_i[5:2];
assign wb_err_o = 1'b0;
always @(posedge clk) dout <= #1 wb_data_i;
always @(posedge clk)
case (wb_addr_i[6:2]) // synopsys parallel_case full_case
5'he: wb_data_o <= #1 i3_din;
5'hf: wb_data_o <= #1 i4_din;
5'h10: wb_data_o <= #1 i6_din;
default: wb_data_o <= #1 rf_din;
endcase
always @(posedge clk) re1 <= #1 !re2 & wb_cyc_i & wb_stb_i & !wb_we_i & `AC97_REG_SEL;
always @(posedge clk) re2 <= #1 re & wb_cyc_i & wb_stb_i & !wb_we_i;
assign re = re1 & !re2 & wb_cyc_i & wb_stb_i & !wb_we_i;
assign rf_re = re & (wb_addr_i[6:2] < 5'h8);
always @(posedge clk) we1 <= #1 !we & wb_cyc_i & wb_stb_i & wb_we_i & `AC97_REG_SEL;
always @(posedge clk) we2 <= #1 we1 & wb_cyc_i & wb_stb_i & wb_we_i;
assign we = we1 & !we2 & wb_cyc_i & wb_stb_i & wb_we_i;
always @(posedge clk) wb_ack_o <= #1 (re | we) & wb_cyc_i & wb_stb_i & ~wb_ack_o;
always @(posedge clk) rf_we <= #1 we & (wb_addr_i[6:2] < 5'h8);
always @(posedge clk) o3_we <= #1 we & (wb_addr_i[6:2] == 5'h8);
always @(posedge clk) o4_we <= #1 we & (wb_addr_i[6:2] == 5'h9);
always @(posedge clk) o6_we <= #1 we & (wb_addr_i[6:2] == 5'ha);
always @(posedge clk) o7_we <= #1 we & (wb_addr_i[6:2] == 5'hb);
always @(posedge clk) o8_we <= #1 we & (wb_addr_i[6:2] == 5'hc);
always @(posedge clk) o9_we <= #1 we & (wb_addr_i[6:2] == 5'hd);
always @(posedge clk) i3_re <= #1 re & (wb_addr_i[6:2] == 5'he);
always @(posedge clk) i4_re <= #1 re & (wb_addr_i[6:2] == 5'hf);
always @(posedge clk) i6_re <= #1 re & (wb_addr_i[6:2] == 5'h10);
endmodule
| 7.949675
|
module aca_csu16_2 (
a,
b,
sum
);
input [15:0] a, b;
output [16:0] sum;
wire [15:0] p, g;
wire [6:0] appc, cout, c;
wire bp1, bp2, bp3, bp4, bp5, bp6;
assign p = a ^ b;
assign g = a & b;
assign appc[0] = g[1] | p[1] & g[0];
assign appc[1] = g[3] | p[3] & g[2];
assign bp1 = p[3] & p[2];
assign appc[2] = g[5] | p[5] & g[4];
assign bp2 = p[5] & p[4];
assign appc[3] = g[7] | p[7] & g[6];
assign bp3 = p[7] & p[6];
assign appc[4] = g[9] | p[9] & g[8];
assign bp4 = p[9] & p[8];
assign appc[5] = g[11] | p[11] & g[10];
assign bp5 = p[11] & p[10];
assign appc[6] = g[13] | p[13] & g[12];
assign bp6 = p[13] & p[12];
assign c[0] = appc[0];
csu cin2 (
bp1,
appc[1],
g[1],
1'b0,
1'b0,
c[1]
);
csu cin3 (
bp2,
appc[2],
g[3],
1'b0,
1'b0,
c[2]
);
csu cin4 (
bp3,
appc[3],
g[5],
1'b0,
1'b0,
c[3]
);
csu cin5 (
bp4,
appc[4],
g[7],
1'b0,
1'b0,
c[4]
);
csu cin6 (
bp5,
appc[5],
g[9],
1'b0,
1'b0,
c[5]
);
csu cin7 (
bp6,
appc[6],
g[11],
1'b0,
1'b0,
c[6]
);
carry_look_ahead_2bit cla1 (
p[1:0],
g[1:0],
1'b0,
sum[1:0],
cout[0]
);
carry_look_ahead_2bit cla2 (
p[3:2],
g[3:2],
c[0],
sum[3:2],
cout[1]
);
carry_look_ahead_2bit cla3 (
p[5:4],
g[5:4],
c[1],
sum[5:4],
cout[2]
);
carry_look_ahead_2bit cla4 (
p[7:6],
g[7:6],
c[2],
sum[7:6],
cout[3]
);
carry_look_ahead_2bit cla5 (
p[9:8],
g[9:8],
c[3],
sum[9:8],
cout[4]
);
carry_look_ahead_2bit cla6 (
p[11:10],
g[11:10],
c[4],
sum[11:10],
cout[5]
);
carry_look_ahead_2bit cla7 (
p[13:12],
g[13:12],
c[5],
sum[13:12],
cout[6]
);
carry_look_ahead_2bit cla8 (
p[15:14],
g[15:14],
c[6],
sum[15:14],
sum[16]
);
endmodule
| 7.590513
|
module carry_look_ahead_2bit (
p,
g,
cin,
sum,
cout
);
input [1:0] p, g;
input cin;
output [1:0] sum;
output cout;
wire [1:0] c;
assign c[0] = cin;
assign c[1] = g[0] | (p[0] & c[0]);
assign cout = g[1] | (p[1] & g[0]) | p[1] & p[0] & c[0];
assign sum = p ^ c;
endmodule
| 6.511278
|
module csu (
bp,
cprdt,
gin,
ci,
control,
cout
);
output cout;
input bp, cprdt, gin, ci, control;
assign cout = cprdt & (~bp) | (~control) & bp & gin | control & bp & ci;
endmodule
| 6.637748
|
module aca_csu16_4 (
a,
b,
sum
);
input [15:0] a, b;
output [16:0] sum;
wire [15:0] p, g;
wire [2:0] appc, cout, c;
wire bp1, bp2;
assign p = a ^ b;
assign g = a & b;
appc app0 (
p[3:0],
g[3:0],
appc[0]
);
appc app1 (
p[7:4],
g[7:4],
appc[1]
);
appc app2 (
p[11:8],
g[11:8],
appc[2]
);
assign bp1 = p[7] & p[6] & p[5] & p[4];
assign bp2 = p[11] & p[10] & p[9] & p[8];
assign c[0] = appc[0];
csu cin2 (
bp1,
appc[1],
g[3],
1'b0,
1'b0,
c[1]
);
csu cin3 (
bp2,
appc[2],
g[7],
1'b0,
1'b0,
c[2]
);
carry_look_ahead_4bit cla1 (
p[3:0],
g[3:0],
1'b0,
sum[3:0],
cout[0]
);
carry_look_ahead_4bit cla2 (
p[7:4],
g[7:4],
c[0],
sum[7:4],
cout[1]
);
carry_look_ahead_4bit cla3 (
p[11:8],
g[11:8],
c[1],
sum[11:8],
cout[2]
);
carry_look_ahead_4bit cla4 (
p[15:12],
g[15:12],
c[2],
sum[15:12],
sum[16]
);
endmodule
| 7.124332
|
module carry_look_ahead_4bit (
p,
g,
cin,
sum,
cout
);
input [3:0] g, p;
input cin;
output [3:0] sum;
output cout;
wire gext;
wire [2:0] c, g1, p1;
assign gext = g[0] | p[0] & cin;
assign c[0] = gext;
assign g1[0] = g[1] | p[1] & gext;
assign c[1] = g1[0];
PGgen pggen01 (
g1[1],
p1[1],
g[2],
p[2],
g[1],
p[1]
);
PGgen pggen02 (
g1[2],
p1[2],
g[3],
p[3],
g[2],
p[2]
);
assign c[2] = g1[1] | p1[1] & gext;
assign cout = g1[2] | p1[2] & g1[0];
assign sum[0] = p[0] ^ cin;
xor x[3:1] (sum[3:1], p[3:1], c[2:0]);
endmodule
| 6.511278
|
module appc (
p,
g,
cout
);
input [3:0] g, p;
output cout;
wire [2:0] c, g1, p1;
assign g1[0] = g[1] | p[1] & g[0];
PGgen pggen02 (
g1[2],
p1[2],
g[3],
p[3],
g[2],
p[2]
);
assign cout = g1[2] | p1[2] & g1[0];
endmodule
| 6.585026
|
module csu (
bp,
cprdt,
gin,
ci,
control,
cout
);
output cout;
input bp, cprdt, gin, ci, control;
assign cout = cprdt & (~bp) | (~control) & bp & gin | control & bp & ci;
endmodule
| 6.637748
|
module aca_csu16_8 (
a,
b,
sum
);
input [15:0] a, b;
output [16:0] sum;
wire [15:0] p, g;
wire appc, cout, c;
assign p = a ^ b;
assign g = a & b;
appc app (
p[7:0],
g[7:0],
appc
);
assign c = appc;
carry_look_ahead_8bit cla1 (
p[7:0],
g[7:0],
1'b0,
sum[7:0],
cout
);
carry_look_ahead_8bit cla2 (
p[15:8],
g[15:8],
c,
sum[15:8],
sum[16]
);
endmodule
| 6.997855
|
module carry_look_ahead_8bit (
p,
g,
cin,
sum,
cout
);
input [7:0] g, p;
input cin;
output [7:0] sum;
output cout;
wire gext, pext;
wire [6:0] c, g1, p1;
wire [5:0] g2, p2;
assign gext = g[0] | p[0] & cin;
assign c[0] = gext;
PGgen pggen00 (
g1[0],
p1[0],
g[1],
p[1],
gext,
pext
);
assign c[1] = g1[0];
PGgen pggen01 (
g1[1],
p1[1],
g[2],
p[2],
g[1],
p[1]
);
PGgen pggen02 (
g1[2],
p1[2],
g[3],
p[3],
g[2],
p[2]
);
PGgen pggen03 (
g1[3],
p1[3],
g[4],
p[4],
g[3],
p[3]
);
PGgen pggen04 (
g1[4],
p1[4],
g[5],
p[5],
g[4],
p[4]
);
PGgen pggen05 (
g1[5],
p1[5],
g[6],
p[6],
g[5],
p[5]
);
PGgen pggen06 (
g1[6],
p1[6],
g[7],
p[7],
g[6],
p[6]
);
assign g2[0] = g1[1] | p1[1] & gext;
assign c[2] = g2[0];
assign g2[1] = g1[2] | p1[2] & g1[0];
assign c[3] = g2[1];
PGgen pggen12 (
g2[2],
p2[2],
g1[3],
p1[3],
g1[1],
p1[1]
);
PGgen pggen13 (
g2[3],
p2[3],
g1[4],
p1[4],
g1[2],
p1[2]
);
PGgen pggen14 (
g2[4],
p2[4],
g1[5],
p1[5],
g1[3],
p1[3]
);
PGgen pggen15 (
g2[5],
p2[5],
g1[6],
p1[6],
g1[4],
p1[4]
);
assign c[4] = g2[2] | p2[2] & gext;
assign c[5] = g2[3] | p2[3] & g1[0];
assign c[6] = g2[4] | p2[4] & g2[0];
assign cout = g2[5] | p2[5] & g2[1];
assign sum[0] = p[0] ^ cin;
xor x[7:1] (sum[7:1], p[7:1], c[6:0]);
endmodule
| 6.511278
|
module carry_look_ahead_8bit(p,g,cin,sum,cout);
// input [7:0] g,p;
// input cin;
// output [7:0] sum;
// output cout;
// wire [7:0] c;
// wire [3:0] g1, p1;
// wire [1:0] g2, p2;
// wire [1:0] g3, p3;
// wire gext;
// assign gext = g[0] | p[0]&cin;
// assign c[0] = gext;
// assign g1[0] = g[1] | p[1]&gext; assign c[1] = g1[0];
// PGgen gen11(g1[1],p1[1],g[3],p[3],g[2],p[2]);
// PGgen gen12(g1[2],p1[2],g[5],p[5],g[4],p[4]);
// PGgen gen13(g1[3],p1[3],g[7],p[7],g[6],p[6]);
// PGgen gen20(g2[0],p2[0],g1[1],p1[1],g1[0],p1[0]);assign c[3] = g2[0];
// PGgen gen21(g2[1],p2[1],g1[3],p1[3],g1[2],p1[2]);
// assign g3[0] = g1[2] | p1[2]&g2[0]; assign c[5] = g3[0];
// assign g3[1] = g2[1] | p2[1]&g2[0]; assign c[7] = g3[1];
// assign c[2] = g[2] | p[2]&g1[0];
// assign c[4] = g[4] | p[4]&g2[0];
// assign c[6] = g[6] | p[6]&g3[0];
// assign sum[0] = p[0]^cin;
// xor x[7:1](sum[7:1],p[7:1],c[6:0]);
// assign cout = c[7];
// endmodule
| 6.511278
|
module appc (
p,
g,
cout
);
input [7:0] g, p;
output cout;
wire [3:0] g1, p1;
wire [1:0] g2;
wire p2;
assign g1[0] = g[1] | p[1] & g[0];
PGgen gen11 (
g1[1],
p1[1],
g[3],
p[3],
g[2],
p[2]
);
PGgen gen12 (
g1[2],
p1[2],
g[5],
p[5],
g[4],
p[4]
);
PGgen gen13 (
g1[3],
p1[3],
g[7],
p[7],
g[6],
p[6]
);
assign g2[0] = g1[1] | p1[1] & g1[0];
PGgen gen21 (
g2[1],
p2,
g1[3],
p1[3],
g1[2],
p1[2]
);
assign cout = g2[1] | p2 & g2[0];
endmodule
| 6.585026
|
module aca_csu32_2 (
a,
b,
sum
);
input [31:0] a, b;
output [32:0] sum;
wire [31:0] p, g;
wire [14:0] appc, cout, c;
wire bp1, bp2, bp3, bp4, bp5, bp6, bp7, bp8, bp9, bp10, bp11, bp12, bp13, bp14;
assign p = a ^ b;
assign g = a & b;
assign appc[0] = g[1] | p[1] & g[0];
assign appc[1] = g[3] | p[3] & g[2];
assign bp1 = p[3] & p[2];
assign appc[2] = g[5] | p[5] & g[4];
assign bp2 = p[5] & p[4];
assign appc[3] = g[7] | p[7] & g[6];
assign bp3 = p[7] & p[6];
assign appc[4] = g[9] | p[9] & g[8];
assign bp4 = p[9] & p[8];
assign appc[5] = g[11] | p[11] & g[10];
assign bp5 = p[11] & p[10];
assign appc[6] = g[13] | p[13] & g[12];
assign bp6 = p[13] & p[12];
assign appc[7] = g[15] | p[15] & g[14];
assign bp7 = p[15] & p[14];
assign appc[8] = g[17] | p[17] & g[16];
assign bp8 = p[17] & p[16];
assign appc[9] = g[19] | p[19] & g[18];
assign bp9 = p[19] & p[18];
assign appc[10] = g[21] | p[21] & g[20];
assign bp10 = p[21] & p[20];
assign appc[11] = g[23] | p[23] & g[22];
assign bp11 = p[23] & p[22];
assign appc[12] = g[25] | p[25] & g[24];
assign bp12 = p[25] & p[24];
assign appc[13] = g[27] | p[27] & g[26];
assign bp13 = p[27] & p[26];
assign appc[14] = g[29] | p[29] & g[28];
assign bp14 = p[29] & p[28];
assign c[0] = appc[0];
csu cin2 (
bp1,
appc[1],
g[1],
1'b0,
1'b0,
c[1]
);
csu cin3 (
bp2,
appc[2],
g[3],
1'b0,
1'b0,
c[2]
);
csu cin4 (
bp3,
appc[3],
g[5],
1'b0,
1'b0,
c[3]
);
csu cin5 (
bp4,
appc[4],
g[7],
1'b0,
1'b0,
c[4]
);
csu cin6 (
bp5,
appc[5],
g[9],
1'b0,
1'b0,
c[5]
);
csu cin7 (
bp6,
appc[6],
g[11],
1'b0,
1'b0,
c[6]
);
csu cin8 (
bp7,
appc[7],
g[13],
1'b0,
1'b0,
c[7]
);
csu cin9 (
bp8,
appc[8],
g[15],
1'b0,
1'b0,
c[8]
);
csu cin10 (
bp9,
appc[9],
g[17],
1'b0,
1'b0,
c[9]
);
csu cin11 (
bp10,
appc[10],
g[19],
1'b0,
1'b0,
c[10]
);
csu cin12 (
bp11,
appc[11],
g[21],
1'b0,
1'b0,
c[11]
);
csu cin13 (
bp12,
appc[12],
g[23],
1'b0,
1'b0,
c[12]
);
csu cin14 (
bp13,
appc[13],
g[25],
1'b0,
1'b0,
c[13]
);
csu cin15 (
bp14,
appc[14],
g[27],
1'b0,
1'b0,
c[14]
);
carry_look_ahead_2bit cla1 (
p[1:0],
g[1:0],
1'b0,
sum[1:0],
cout[0]
);
carry_look_ahead_2bit cla2 (
p[3:2],
g[3:2],
c[0],
sum[3:2],
cout[1]
);
carry_look_ahead_2bit cla3 (
p[5:4],
g[5:4],
c[1],
sum[5:4],
cout[2]
);
carry_look_ahead_2bit cla4 (
p[7:6],
g[7:6],
c[2],
sum[7:6],
cout[3]
);
carry_look_ahead_2bit cla5 (
p[9:8],
g[9:8],
c[3],
sum[9:8],
cout[4]
);
carry_look_ahead_2bit cla6 (
p[11:10],
g[11:10],
c[4],
sum[11:10],
cout[5]
);
carry_look_ahead_2bit cla7 (
p[13:12],
g[13:12],
c[5],
sum[13:12],
cout[6]
);
carry_look_ahead_2bit cla8 (
p[15:14],
g[15:14],
c[6],
sum[15:14],
cout[6]
);
carry_look_ahead_2bit cla9 (
p[17:16],
g[17:16],
c[7],
sum[17:16],
cout[7]
);
carry_look_ahead_2bit cla10 (
p[19:18],
g[19:18],
c[8],
sum[19:18],
cout[8]
);
carry_look_ahead_2bit cla11 (
p[21:20],
g[21:20],
c[9],
sum[21:20],
cout[9]
);
carry_look_ahead_2bit cla12 (
p[23:22],
g[23:22],
c[10],
sum[23:22],
cout[10]
);
carry_look_ahead_2bit cla13 (
p[25:24],
g[25:24],
c[11],
sum[25:24],
cout[11]
);
carry_look_ahead_2bit cla14 (
p[27:26],
g[27:26],
c[12],
sum[27:26],
cout[12]
);
carry_look_ahead_2bit cla15 (
p[29:28],
g[29:28],
c[13],
sum[29:28],
cout[13]
);
carry_look_ahead_2bit cla16 (
p[31:30],
g[31:30],
c[14],
sum[31:30],
sum[32]
);
endmodule
| 7.331945
|
module carry_look_ahead_2bit (
p,
g,
cin,
sum,
cout
);
input [1:0] p, g;
input cin;
output [1:0] sum;
output cout;
wire [1:0] c;
assign c[0] = cin;
assign c[1] = g[0] | (p[0] & c[0]);
assign cout = g[1] | (p[1] & g[0]) | p[1] & p[0] & c[0];
assign sum = p ^ c;
endmodule
| 6.511278
|
module csu (
bp,
cprdt,
gin,
ci,
control,
cout
);
output cout;
input bp, cprdt, gin, ci, control;
assign cout = cprdt & (~bp) | (~control) & bp & gin | control & bp & ci;
endmodule
| 6.637748
|
module aca_csu32_4 (
a,
b,
sum
);
input [31:0] a, b;
output [32:0] sum;
wire [31:0] p, g;
wire [6:0] appc, cout, c;
wire bp1, bp2, bp3, bp4, bp5, bp6;
assign p = a ^ b;
assign g = a & b;
appc app0 (
p[3:0],
g[3:0],
appc[0]
);
appc app1 (
p[7:4],
g[7:4],
appc[1]
);
appc app2 (
p[11:8],
g[11:8],
appc[2]
);
appc app3 (
p[15:12],
g[15:12],
appc[3]
);
appc app4 (
p[19:16],
g[19:16],
appc[4]
);
appc app5 (
p[23:20],
g[23:20],
appc[5]
);
appc app6 (
p[27:24],
g[27:24],
appc[6]
);
assign bp1 = p[7] & p[6] & p[5] & p[4];
assign bp2 = p[11] & p[10] & p[9] & p[8];
assign bp3 = p[15] & p[14] & p[13] & p[12];
assign bp4 = p[19] & p[18] & p[17] & p[16];
assign bp5 = p[23] & p[22] & p[21] & p[20];
assign bp6 = p[27] & p[26] & p[25] & p[24];
assign c[0] = appc[0];
csu cin2 (
bp1,
appc[1],
g[3],
1'b0,
1'b0,
c[1]
);
csu cin3 (
bp2,
appc[2],
g[7],
1'b0,
1'b0,
c[2]
);
csu cin4 (
bp3,
appc[3],
g[11],
1'b0,
1'b0,
c[3]
);
csu cin5 (
bp4,
appc[4],
g[15],
1'b0,
1'b0,
c[4]
);
csu cin6 (
bp5,
appc[5],
g[19],
1'b0,
1'b0,
c[5]
);
csu cin7 (
bp6,
appc[6],
g[23],
1'b0,
1'b0,
c[6]
);
carry_look_ahead_4bit cla1 (
p[3:0],
g[3:0],
1'b0,
sum[3:0],
cout[0]
);
carry_look_ahead_4bit cla2 (
p[7:4],
g[7:4],
c[0],
sum[7:4],
cout[1]
);
carry_look_ahead_4bit cla3 (
p[11:8],
g[11:8],
c[1],
sum[11:8],
cout[2]
);
carry_look_ahead_4bit cla4 (
p[15:12],
g[15:12],
c[2],
sum[15:12],
cout[3]
);
carry_look_ahead_4bit cla5 (
p[19:16],
g[19:16],
c[3],
sum[19:16],
cout[4]
);
carry_look_ahead_4bit cla6 (
p[23:20],
g[23:20],
c[4],
sum[23:20],
cout[5]
);
carry_look_ahead_4bit cla7 (
p[27:24],
g[27:24],
c[5],
sum[27:24],
cout[6]
);
carry_look_ahead_4bit cla8 (
p[31:28],
g[31:28],
c[6],
sum[31:28],
sum[32]
);
endmodule
| 7.476312
|
module carry_look_ahead_4bit (
p,
g,
cin,
sum,
cout
);
input [3:0] g, p;
input cin;
output [3:0] sum;
output cout;
wire gext;
wire [2:0] c, g1, p1;
assign gext = g[0] | p[0] & cin;
assign c[0] = gext;
assign g1[0] = g[1] | p[1] & gext;
assign c[1] = g1[0];
PGgen pggen01 (
g1[1],
p1[1],
g[2],
p[2],
g[1],
p[1]
);
PGgen pggen02 (
g1[2],
p1[2],
g[3],
p[3],
g[2],
p[2]
);
assign c[2] = g1[1] | p1[1] & gext;
assign cout = g1[2] | p1[2] & g1[0];
assign sum[0] = p[0] ^ cin;
xor x[3:1] (sum[3:1], p[3:1], c[2:0]);
endmodule
| 6.511278
|
module appc (
p,
g,
cout
);
input [3:0] g, p;
output cout;
wire [2:0] c, g1, p1;
assign g1[0] = g[1] | p[1] & g[0];
PGgen pggen02 (
g1[2],
p1[2],
g[3],
p[3],
g[2],
p[2]
);
assign cout = g1[2] | p1[2] & g1[0];
endmodule
| 6.585026
|
module csu (
bp,
cprdt,
gin,
ci,
control,
cout
);
output cout;
input bp, cprdt, gin, ci, control;
assign cout = cprdt & (~bp) | (~control) & bp & gin | control & bp & ci;
endmodule
| 6.637748
|
module aca_csu32_8 (
a,
b,
sum
);
input [31:0] a, b;
output [32:0] sum;
wire [31:0] p, g;
wire [2:0] appc, cout, c;
wire bp1, bp2;
assign p = a ^ b;
assign g = a & b;
appc app0 (
p[7:0],
g[7:0],
appc[0]
);
appc app1 (
p[15:8],
g[15:8],
appc[1]
);
appc app2 (
p[23:16],
g[23:16],
appc[2]
);
assign bp1 = p[15] & p[14] & p[13] & p[12] & p[11] & p[10] & p[9] & p[8];
assign bp2 = p[23] & p[22] & p[21] & p[20] & p[19] & p[18] & p[17] & p[16];
assign c[0] = appc[0];
csu cin2 (
bp1,
appc[1],
g[7],
1'b0,
1'b0,
c[1]
);
csu cin3 (
bp2,
appc[2],
g[15],
1'b0,
1'b0,
c[2]
);
carry_look_ahead_8bit cla1 (
p[7:0],
g[7:0],
1'b0,
sum[7:0],
cout[0]
);
carry_look_ahead_8bit cla2 (
p[15:8],
g[15:8],
c[0],
sum[15:8],
cout[1]
);
carry_look_ahead_8bit cla3 (
p[23:16],
g[23:16],
c[1],
sum[23:16],
cout[2]
);
carry_look_ahead_8bit cla4 (
p[31:24],
g[31:24],
c[2],
sum[31:24],
sum[32]
);
endmodule
| 7.125723
|
module carry_look_ahead_8bit (
p,
g,
cin,
sum,
cout
);
input [7:0] g, p;
input cin;
output [7:0] sum;
output cout;
wire gext, pext;
wire [6:0] c, g1, p1;
wire [5:0] g2, p2;
assign gext = g[0] | p[0] & cin;
assign c[0] = gext;
PGgen pggen00 (
g1[0],
p1[0],
g[1],
p[1],
gext,
pext
);
assign c[1] = g1[0];
PGgen pggen01 (
g1[1],
p1[1],
g[2],
p[2],
g[1],
p[1]
);
PGgen pggen02 (
g1[2],
p1[2],
g[3],
p[3],
g[2],
p[2]
);
PGgen pggen03 (
g1[3],
p1[3],
g[4],
p[4],
g[3],
p[3]
);
PGgen pggen04 (
g1[4],
p1[4],
g[5],
p[5],
g[4],
p[4]
);
PGgen pggen05 (
g1[5],
p1[5],
g[6],
p[6],
g[5],
p[5]
);
PGgen pggen06 (
g1[6],
p1[6],
g[7],
p[7],
g[6],
p[6]
);
assign g2[0] = g1[1] | p1[1] & gext;
assign c[2] = g2[0];
assign g2[1] = g1[2] | p1[2] & g1[0];
assign c[3] = g2[1];
PGgen pggen12 (
g2[2],
p2[2],
g1[3],
p1[3],
g1[1],
p1[1]
);
PGgen pggen13 (
g2[3],
p2[3],
g1[4],
p1[4],
g1[2],
p1[2]
);
PGgen pggen14 (
g2[4],
p2[4],
g1[5],
p1[5],
g1[3],
p1[3]
);
PGgen pggen15 (
g2[5],
p2[5],
g1[6],
p1[6],
g1[4],
p1[4]
);
assign c[4] = g2[2] | p2[2] & gext;
assign c[5] = g2[3] | p2[3] & g1[0];
assign c[6] = g2[4] | p2[4] & g2[0];
assign cout = g2[5] | p2[5] & g2[1];
assign sum[0] = p[0] ^ cin;
xor x[7:1] (sum[7:1], p[7:1], c[6:0]);
endmodule
| 6.511278
|
module appc (
p,
g,
cout
);
input [7:0] g, p;
output cout;
wire [3:0] g1, p1;
wire [1:0] g2;
wire p2;
assign g1[0] = g[1] | p[1] & g[0];
PGgen gen11 (
g1[1],
p1[1],
g[3],
p[3],
g[2],
p[2]
);
PGgen gen12 (
g1[2],
p1[2],
g[5],
p[5],
g[4],
p[4]
);
PGgen gen13 (
g1[3],
p1[3],
g[7],
p[7],
g[6],
p[6]
);
assign g2[0] = g1[1] | p1[1] & g1[0];
PGgen gen21 (
g2[1],
p2,
g1[3],
p1[3],
g1[2],
p1[2]
);
assign cout = g2[1] | p2 & g2[0];
endmodule
| 6.585026
|
module csu (
bp,
cprdt,
gin,
ci,
control,
cout
);
output cout;
input bp, cprdt, gin, ci, control;
assign cout = cprdt & (~bp) | (~control) & bp & gin | control & bp & ci;
endmodule
| 6.637748
|
module aca_csu8_2 (
a,
b,
sum
);
input [7:0] a, b;
output [8:0] sum;
wire [7:0] p, g;
wire [2:0] appc, cout, c;
wire bp1, bp2;
assign p = a ^ b;
assign g = a & b;
assign appc[0] = g[1] | p[1] & g[0];
assign appc[1] = g[3] | p[3] & g[2];
assign bp1 = p[3] & p[2];
assign appc[2] = g[5] | p[5] & g[4];
assign bp2 = p[5] & p[4];
assign c[0] = appc[0];
csu cin2 (
bp1,
appc[1],
g[1],
1'b0,
1'b0,
c[1]
);
csu cin3 (
bp2,
appc[2],
g[3],
1'b0,
1'b0,
c[2]
);
carry_look_ahead_2bit cla1 (
p[1:0],
g[1:0],
1'b0,
sum[1:0],
cout[0]
);
carry_look_ahead_2bit cla2 (
p[3:2],
g[3:2],
c[0],
sum[3:2],
cout[1]
);
carry_look_ahead_2bit cla3 (
p[5:4],
g[5:4],
c[1],
sum[5:4],
cout[2]
);
carry_look_ahead_2bit cla4 (
p[7:6],
g[7:6],
c[2],
sum[7:6],
sum[8]
);
endmodule
| 7.539202
|
module carry_look_ahead_2bit (
p,
g,
cin,
sum,
cout
);
input [1:0] p, g;
input cin;
output [1:0] sum;
output cout;
wire [1:0] c;
assign c[0] = cin;
assign c[1] = g[0] | (p[0] & c[0]);
assign cout = g[1] | (p[1] & g[0]) | p[1] & p[0] & c[0];
assign sum = p ^ c;
endmodule
| 6.511278
|
module csu (
bp,
cprdt,
gin,
ci,
control,
cout
);
output cout;
input bp, cprdt, gin, ci, control;
assign cout = cprdt & (~bp) | (~control) & bp & gin | control & bp & ci;
endmodule
| 6.637748
|
module aca_csu8_4 (
a,
b,
sum
);
input [7:0] a, b;
output [8:0] sum;
wire [7:0] p, g;
wire appc, cout, c;
assign p = a ^ b;
assign g = a & b;
appc app0 (
p[3:0],
g[3:0],
appc
);
assign c = appc;
carry_look_ahead_4bit cla1 (
p[3:0],
g[3:0],
1'b0,
sum[3:0],
cout
);
carry_look_ahead_4bit cla2 (
p[7:4],
g[7:4],
c,
sum[7:4],
sum[8]
);
endmodule
| 7.34305
|
module carry_look_ahead_4bit (
p,
g,
cin,
sum,
cout
);
input [3:0] g, p;
input cin;
output [3:0] sum;
output cout;
wire gext;
wire [2:0] c, g1, p1;
assign gext = g[0] | p[0] & cin;
assign c[0] = gext;
assign g1[0] = g[1] | p[1] & gext;
assign c[1] = g1[0];
PGgen pggen01 (
g1[1],
p1[1],
g[2],
p[2],
g[1],
p[1]
);
PGgen pggen02 (
g1[2],
p1[2],
g[3],
p[3],
g[2],
p[2]
);
assign c[2] = g1[1] | p1[1] & gext;
assign cout = g1[2] | p1[2] & g1[0];
assign sum[0] = p[0] ^ cin;
xor x[3:1] (sum[3:1], p[3:1], c[2:0]);
endmodule
| 6.511278
|
module appc (
p,
g,
cout
);
input [3:0] g, p;
output cout;
wire [2:0] c, g1, p1;
assign g1[0] = g[1] | p[1] & g[0];
PGgen pggen02 (
g1[2],
p1[2],
g[3],
p[3],
g[2],
p[2]
);
assign cout = g1[2] | p1[2] & g1[0];
endmodule
| 6.585026
|
module ACC0 (
input wire clk,
input wire next,
input wire prev,
output wire d0,
output wire d1,
output wire d2,
output wire d3,
output wire d4,
output wire d5,
output wire d6,
output wire d7
);
//-- Rom file
parameter ROMFILE = "rom.list";
//-- Parameters for the memory
localparam AW = 12; //-- Address bus
localparam DW = 16; //-- Data bus
//-- Initial address
localparam BOOT_ADDR = 12'h800;
wire [DW-1:0] rom_dout;
//-- Instantiate the ROM memory (2K)
genrom #(
.ROMFILE(ROMFILE),
.AW(AW - 1),
.DW(DW)
) ROM (
.clk (clk),
.cs (S[AW-1]), //-- Bit A11 for the chip select
.addr (S[AW-2:0]), //-- Bits A10 - A0 for addressing the Rom (2K)
.data_out(rom_dout)
);
//-- Configure the pull-up resistors for clk and rst inputs
wire next_p; //-- Next input with pull-up activated
wire clk_in;
wire prev_p; //-- Prev input with pull-up activated
wire sw2;
wire sw1;
SB_IO #(
.PIN_TYPE(6'b1010_01),
.PULLUP (1'b1)
) io_pin (
.PACKAGE_PIN(next),
.D_IN_0(next_p)
);
SB_IO #(
.PIN_TYPE(6'b1010_01),
.PULLUP (1'b1)
) io_pin2 (
.PACKAGE_PIN(prev),
.D_IN_0(prev_p)
);
//-- rst_in and clk_in are the signals from the switches, with
//-- standar logic (1 pressed, 0 not presssed)
assign sw2 = ~prev_p;
assign sw1 = ~next_p;
//-- switch button debounced
wire sw1_deb;
wire sw2_deb;
debounce_pulse deb1 (
.clk(clk),
.sw_in(sw1),
.sw_out(sw1_deb)
);
debounce_pulse deb2 (
.clk(clk),
.sw_in(sw2),
.sw_out(sw2_deb)
);
assign clk_in = sw1_deb;
//-- Register S: Accessing memory
reg [AW-1:0] S = BOOT_ADDR;
always @(posedge clk) begin
if (sw1_deb) S <= S + 1;
else if (sw2_deb) S <= S - 1;
end
//-- Instruction register
reg [14:0] G = 15'b0;
//-- Control signal for the RI register
//-- Every 15-bit instruction is sotred here before executing
reg WG = 1;
always @(posedge clk) if (WG) G <= rom_dout[14:0];
//-- In ACC0, the 7 more significant bits of the G reg are shown in leds
assign {d6, d5, d4, d3, d2, d1, d0} = G[14:8];
//-- The LED7 is always set to 0
assign d7 = 1'b0;
endmodule
| 8.032778
|
module genrom #(
parameter AW = 11, //-- Adress width
parameter DW = 16, //-- Data witdh
parameter ROMFILE = "rom.list"
) //-- Romfile
(
input wire clk, //-- Clock
input cs, //-- Chip select
input wire [AW-1:0] addr, //-- Address bus
output reg [DW-1:0] data_out
); //-- Data bus
//-- Total position of the address
localparam NPOS = 2 ** AW;
//-- Memory
reg [DW-1:0] rom[0:NPOS-1];
always @(negedge clk) begin
if (cs) data_out <= rom[addr];
end
//-- ROM2: Secuencia
initial begin
$readmemh(ROMFILE, rom);
end
endmodule
| 8.241453
|
module debounce_pulse (
input wire clk,
input wire sw_in,
output wire sw_out
);
//------------------------------
//-- CONTROLLER
//------------------------------
//-- fsm states
localparam IDLE = 0; //-- Idle state. Button not pressed
localparam WAIT_1 = 1; //-- Waiting for the stabilization of 1. Butt pressed
localparam PULSE = 2; //-- 1-clk pulse is generated
localparam WAIT_0 = 3; //-- Button released. Waiting for stabilization of 0
//-- Registers for storing the states
reg [1:0] state = IDLE;
reg [1:0] next_state;
//-- Control signals
reg out = 0;
reg timer_ena = 0;
assign sw_out = out;
//-- Transition between states
always @(posedge clk) state <= next_state;
//-- Control signal generation and next states
always @(*) begin
//-- Default values
next_state = state; //-- Stay in the same state by default
timer_ena = 0;
out = 0;
case (state)
//-- Button not pressed
//-- Remain in this state until the botton is pressed
IDLE: begin
timer_ena = 0;
out = 0;
if (sw_in) next_state = WAIT_1;
end
//-- Wait until x ms has elapsed
WAIT_1: begin
timer_ena = 1;
out = 0;
if (timer_trig) next_state = PULSE;
end
PULSE: begin
timer_ena = 0;
out = 1;
next_state = WAIT_0;
end
WAIT_0: begin
timer_ena = 1;
out = 0;
if (timer_trig && sw_in == 0) next_state = IDLE;
end
default: begin
end
endcase
end
assign sw_out = out;
//-- Timer
wire timer_trig;
prescaler #(
.N(16)
) pres0 (
.clk_in(clk),
.ena(timer_ena),
.clk_out(timer_trig)
);
endmodule
| 6.807373
|
module prescaler (
input wire clk_in,
input wire ena,
output wire clk_out
);
//-- Bits of the prescaler
parameter N = 22;
//-- N bits counter
reg [N-1:0] count = 0;
//-- The most significant bit is used as output
assign clk_out = count[N-1];
always @(posedge (clk_in)) begin
if (!ena) count <= 0;
else count <= count + 1;
end
endmodule
| 7.858126
|
module genrom #(
parameter AW = 11, //-- Adress width
parameter DW = 16, //-- Data witdh
parameter ROMFILE = "rom.list"
) //-- Romfile
(
input wire clk, //-- Clock
input cs, //-- Chip select
input wire [AW-1:0] addr, //-- Address bus
output reg [DW-1:0] data_out
); //-- Data bus
//-- Total position of the address
localparam NPOS = 2 ** AW;
//-- Memory
reg [DW-1:0] rom[0:NPOS-1];
always @(negedge clk) begin
if (cs) data_out <= rom[addr];
end
//-- ROM2: Secuencia
initial begin
$readmemh(ROMFILE, rom);
end
endmodule
| 8.241453
|
module debounce_pulse (
input wire clk,
input wire sw_in,
output wire sw_out
);
//------------------------------
//-- CONTROLLER
//------------------------------
//-- fsm states
localparam IDLE = 0; //-- Idle state. Button not pressed
localparam WAIT_1 = 1; //-- Waiting for the stabilization of 1. Butt pressed
localparam PULSE = 2; //-- 1-clk pulse is generated
localparam WAIT_0 = 3; //-- Button released. Waiting for stabilization of 0
//-- Registers for storing the states
reg [1:0] state = IDLE;
reg [1:0] next_state;
//-- Control signals
reg out = 0;
reg timer_ena = 0;
assign sw_out = out;
//-- Transition between states
always @(posedge clk) state <= next_state;
//-- Control signal generation and next states
always @(*) begin
//-- Default values
next_state = state; //-- Stay in the same state by default
timer_ena = 0;
out = 0;
case (state)
//-- Button not pressed
//-- Remain in this state until the botton is pressed
IDLE: begin
timer_ena = 0;
out = 0;
if (sw_in) next_state = WAIT_1;
end
//-- Wait until x ms has elapsed
WAIT_1: begin
timer_ena = 1;
out = 0;
if (timer_trig) next_state = PULSE;
end
PULSE: begin
timer_ena = 0;
out = 1;
next_state = WAIT_0;
end
WAIT_0: begin
timer_ena = 1;
out = 0;
if (timer_trig && sw_in == 0) next_state = IDLE;
end
default: begin
end
endcase
end
assign sw_out = out;
//-- Timer
wire timer_trig;
prescaler #(
.N(16)
) pres0 (
.clk_in(clk),
.ena(timer_ena),
.clk_out(timer_trig)
);
endmodule
| 6.807373
|
module prescaler (
input wire clk_in,
input wire ena,
output wire clk_out
);
//-- Bits of the prescaler
parameter N = 22;
//-- N bits counter
reg [N-1:0] count = 0;
//-- The most significant bit is used as output
assign clk_out = count[N-1];
always @(posedge (clk_in)) begin
if (!ena) count <= 0;
else count <= count + 1;
end
endmodule
| 7.858126
|
module genrom #(
parameter AW = 11, //-- Adress width
parameter DW = 16, //-- Data witdh
parameter ROMFILE = "rom.list"
) //-- Romfile
(
input wire clk, //-- Clock
input cs, //-- Chip select
input wire [AW-1:0] addr, //-- Address bus
output reg [DW-1:0] data_out
); //-- Data bus
//-- Total position of the address
localparam NPOS = 2 ** AW;
//-- Memory
reg [DW-1:0] rom[0:NPOS-1];
always @(negedge clk) begin
if (cs) data_out <= rom[addr];
end
//-- ROM2: Secuencia
initial begin
$readmemh(ROMFILE, rom);
end
endmodule
| 8.241453
|
module debounce_pulse (
input wire clk,
input wire sw_in,
output wire sw_out
);
//------------------------------
//-- CONTROLLER
//------------------------------
//-- fsm states
localparam IDLE = 0; //-- Idle state. Button not pressed
localparam WAIT_1 = 1; //-- Waiting for the stabilization of 1. Butt pressed
localparam PULSE = 2; //-- 1-clk pulse is generated
localparam WAIT_0 = 3; //-- Button released. Waiting for stabilization of 0
//-- Registers for storing the states
reg [1:0] state = IDLE;
reg [1:0] next_state;
//-- Control signals
reg out = 0;
reg timer_ena = 0;
assign sw_out = out;
//-- Transition between states
always @(posedge clk) state <= next_state;
//-- Control signal generation and next states
always @(*) begin
//-- Default values
next_state = state; //-- Stay in the same state by default
timer_ena = 0;
out = 0;
case (state)
//-- Button not pressed
//-- Remain in this state until the botton is pressed
IDLE: begin
timer_ena = 0;
out = 0;
if (sw_in) next_state = WAIT_1;
end
//-- Wait until x ms has elapsed
WAIT_1: begin
timer_ena = 1;
out = 0;
if (timer_trig) next_state = PULSE;
end
PULSE: begin
timer_ena = 0;
out = 1;
next_state = WAIT_0;
end
WAIT_0: begin
timer_ena = 1;
out = 0;
if (timer_trig && sw_in == 0) next_state = IDLE;
end
default: begin
end
endcase
end
assign sw_out = out;
//-- Timer
wire timer_trig;
prescaler #(
.N(16)
) pres0 (
.clk_in(clk),
.ena(timer_ena),
.clk_out(timer_trig)
);
endmodule
| 6.807373
|
module prescaler (
input wire clk_in,
input wire ena,
output wire clk_out
);
//-- Bits of the prescaler
parameter N = 22;
//-- N bits counter
reg [N-1:0] count = 0;
//-- The most significant bit is used as output
assign clk_out = count[N-1];
always @(posedge (clk_in)) begin
if (!ena) count <= 0;
else count <= count + 1;
end
endmodule
| 7.858126
|
module accarray (
clk,
ena,
clr,
accumulate,
feature,
value,
result
);
parameter WL = 32;
parameter NUM = 128;
input clk, ena, clr, accumulate;
input [WL - 1:0] value;
input [WL*NUM - 1:0] feature;
output wire [WL*NUM - 1:0] result;
genvar i;
generate
for (i = 0; i < NUM; i = i + 1) begin : accgen
acc ins (
.clk0(clk),
.ena(ena),
.clr0(clr),
.result(result[(i+1)*WL-1:i*WL]),
.accumulate(accumulate),
.ay(value),
.az(feature[(i+1)*WL-1:i*WL])
);
end
endgenerate
endmodule
| 7.558144
|
module accbuf (
input [7:0] write_data_accbuf,
output [7:0] read_data_accbuf,
input CLK
); //CLK controls the buffer
wire signed [7:0] write_data_accbuf;
reg signed [7:0] read_data_accbuf;
reg signed [7:0] accbuf; //ACCUMULATOR BUFFER declared here
always @(posedge CLK) //read in values from $acc at positive edge
if (CLK) begin
accbuf[7:0] <= write_data_accbuf[7:0];
read_data_accbuf [7:0] <= write_data_accbuf [7:0]; //so write_data immidieatly goes to read_data
end else begin
read_data_accbuf[7:0] <= accbuf[7:0]; //if not writing to buffer, always read from it
end
endmodule
| 6.954437
|
module f_register #(
parameter width = 32
) (
input clk,
en,
rst,
input [width-1:0] D,
output reg [width-1:0] Q
);
always @(posedge clk, posedge rst) begin
if (rst) Q <= 0;
else if (en) Q <= D;
else Q <= Q;
end
endmodule
| 7.117902
|
module f_output_mux (
input [1:0] sel,
input [31:0] a,
b,
c,
d,
output reg [31:0] Q
);
always @(*) begin
case (sel)
'b00: Q <= a;
'b01: Q <= b;
'b10: Q <= c;
'b11: Q <= d;
default: Q <= a;
endcase
end
endmodule
| 6.850321
|
module AVS_AVALONSLAVE_CTRL #(
// you can add parameters here
// you can change these parameters
parameter integer AVS_AVALONSLAVE_DATA_WIDTH = 32,
parameter integer AVS_AVALONSLAVE_ADDRESS_WIDTH = 4
) (
// user ports begin
output wire Go,
input wire DONE,
output wire [10:0] Number_Out,
output wire [18:0] Size_Out,
output wire [AVS_AVALONSLAVE_DATA_WIDTH - 1:0] slv_reg1_out,
output wire [AVS_AVALONSLAVE_DATA_WIDTH - 1:0] slv_reg2_out,
output wire [AVS_AVALONSLAVE_DATA_WIDTH - 1:0] slv_reg3_out,
output wire Slave_Done,
input wire [2:0] Temp1_State,
// user ports end
// dont change these ports
input wire CSI_CLOCK_CLK,
input wire CSI_CLOCK_RESET,
input wire [AVS_AVALONSLAVE_ADDRESS_WIDTH - 1:0] AVS_AVALONSLAVE_ADDRESS,
output wire AVS_AVALONSLAVE_WAITREQUEST,
input wire AVS_AVALONSLAVE_READ,
input wire AVS_AVALONSLAVE_WRITE,
output wire [AVS_AVALONSLAVE_DATA_WIDTH - 1:0] AVS_AVALONSLAVE_READDATA,
input wire [AVS_AVALONSLAVE_DATA_WIDTH - 1:0] AVS_AVALONSLAVE_WRITEDATA
);
// output wires and registers
// you can change name and type of these ports
wire start;
wire wait_request;
reg [AVS_AVALONSLAVE_DATA_WIDTH - 1:0] read_data;
// these are slave registers. they MUST be here!
reg [AVS_AVALONSLAVE_DATA_WIDTH - 1:0] slv_reg0;
reg [AVS_AVALONSLAVE_DATA_WIDTH - 1:0] slv_reg1;
reg [AVS_AVALONSLAVE_DATA_WIDTH - 1:0] slv_reg2;
reg [AVS_AVALONSLAVE_DATA_WIDTH - 1:0] slv_reg3;
reg [2:0] Temp_Slave_State;
//My registers
wire [10:0] Number;
wire [18:0] Size;
// I/O assignment
// never directly send values to output
assign AVS_AVALONSLAVE_WAITREQUEST = wait_request;
assign AVS_AVALONSLAVE_READDATA = read_data;
//My Assigns
assign Number_Out = Number;
assign Size_Out = Size;
assign slv_reg1_out = slv_reg1;
assign slv_reg2_out = slv_reg2;
assign slv_reg3_out = slv_reg3;
assign wait_request = 0;
// it is an example and you can change it or delete it completely
always @(posedge CSI_CLOCK_CLK) begin
Temp_Slave_State <= Temp1_State;
// usually resets are active low but you can change its trigger type
if (CSI_CLOCK_RESET == 0) begin
slv_reg0 <= 0;
slv_reg1 <= 0;
slv_reg2 <= 0;
slv_reg3 <= 0;
end else if (AVS_AVALONSLAVE_WRITE) begin
// address is always bytewise so must devide it by 4 for 32bit word
case (AVS_AVALONSLAVE_ADDRESS >> 2)
0: slv_reg0 <= AVS_AVALONSLAVE_WRITEDATA;
1: slv_reg1 <= AVS_AVALONSLAVE_WRITEDATA;
2: slv_reg2 <= AVS_AVALONSLAVE_WRITEDATA;
3: slv_reg3 <= AVS_AVALONSLAVE_WRITEDATA;
default: begin
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
end
endcase
end // it is an example design
else if (DONE) begin
slv_reg0[31] <= 1'b1;
slv_reg0[0] <= 1'b0;
end
end
always @(*) begin
if (AVS_AVALONSLAVE_READ) begin
// address is always bytewise so must devide it by 4 for 32bit word
case (AVS_AVALONSLAVE_ADDRESS >> 2)
0: read_data = slv_reg0;
1: read_data = slv_reg1;
2: read_data = slv_reg2;
3: read_data = slv_reg3;
default: begin
read_data = 0;
end
endcase
end else begin
read_data = 0;
end
end
// do the other jobs yourself like last codes
assign Go = slv_reg0[0];
assign Number = slv_reg0[11:1];
assign Size = slv_reg0[30:12];
assign Slave_Done = slv_reg0[31];
endmodule
| 7.359239
|
module accelerator_tb ();
reg clk, reset; // Clock and Reset
// Inputs and outputs of accelerator module
wire [31:0]
image,
result0,
result1,
result2,
result3,
result4,
result5,
result6,
result7,
result8,
result9,
ctr1;
integer i; // Clock loop variable
// Initiating accelerator module
accelerator a1 (
.clk(clk),
.reset(reset),
.image(image),
.result0(result0),
.result1(result1),
.result2(result2),
.result3(result3),
.result4(result4),
.result5(result5),
.result6(result6),
.result7(result7),
.result8(result8),
.result9(result9),
.counter1(ctr1)
);
// Initiating the image data module
xmem u2 (
.ctr1 (ctr1),
.xdata(image)
);
// Set up clock
always #5 clk = ~clk;
initial begin
$display("RUNNING TEST");
clk = 0;
reset = 0;
#3 reset = 1; // This is active high reset
#6 reset = 0; // Reset removed - normal functioning resumes
@(posedge clk);
for (i = 0; i < 1000; i = i + 1) begin
@(posedge clk);
end
$display("Score_0 - %h", $signed(result0));
$display("Score_1 - %h", $signed(result1));
$display("Score_2 - %h", $signed(result2));
$display("Score_3 - %h", $signed(result3));
$display("Score_4 - %h", $signed(result4));
$display("Score_5 - %h", $signed(result5));
$display("Score_6 - %h", $signed(result6));
$display("Score_7 - %h", $signed(result7));
$display("Score_8 - %h", $signed(result8));
$display("Score_9 - %h", $signed(result9));
$finish;
end
endmodule
| 6.686818
|
module accelerator_tb ();
parameter ROW = 16;
parameter COL = 16;
parameter IN_BITWIDTH = 8;
parameter OUT_BITWIDTH = 16;
parameter ACTV_ADDR_BITWIDTH = 2;
parameter ACTV_DEPTH = 4;
parameter WGT_ADDR_BITWIDTH = 2;
parameter WGT_DEPTH = 4;
parameter PSUM_ADDR_BITWIDTH = 2;
parameter PSUM_DEPTH = 4;
parameter GBF_DATA_BITWIDTH = 256;
parameter GBF_ADDR_BITWIDTH = 5;
parameter GBF_DEPTH = 32;
parameter PSUM_GBF_DATA_BITWIDTH = 512;
parameter PSUM_GBF_ADDR_BITWIDTH = 5;
parameter PSUM_GBF_DEPTH = 32;
reg clk, reset;
wire actv_gbf1_need_data, actv_gbf2_need_data, wgt_gbf1_need_data, wgt_gbf2_need_data;
wire [PSUM_GBF_DATA_BITWIDTH-1:0] r_data1b;
wire [PSUM_GBF_DATA_BITWIDTH-1:0] r_data2b;
wire r_en1b_out, r_en2b_out;
accelerator #(
.ROW(ROW),
.COL(COL),
.IN_BITWIDTH(IN_BITWIDTH),
.OUT_BITWIDTH(OUT_BITWIDTH),
.ACTV_ADDR_BITWIDTH(ACTV_ADDR_BITWIDTH),
.ACTV_DEPTH(ACTV_DEPTH),
.WGT_ADDR_BITWIDTH(WGT_ADDR_BITWIDTH),
.WGT_DEPTH(WGT_DEPTH),
.PSUM_ADDR_BITWIDTH(PSUM_ADDR_BITWIDTH),
.PSUM_DEPTH(PSUM_DEPTH),
.GBF_DATA_BITWIDTH(GBF_DATA_BITWIDTH),
.GBF_ADDR_BITWIDTH(GBF_ADDR_BITWIDTH),
.GBF_DEPTH(GBF_DEPTH),
.PSUM_GBF_DATA_BITWIDTH(PSUM_GBF_DATA_BITWIDTH),
.PSUM_GBF_ADDR_BITWIDTH(PSUM_GBF_ADDR_BITWIDTH),
.PSUM_GBF_DEPTH(PSUM_GBF_DEPTH)
) u_accelerator (
.clk(clk),
.reset(reset),
.actv_gbf1_need_data(actv_gbf1_need_data),
.actv_gbf2_need_data(actv_gbf2_need_data),
.wgt_gbf1_need_data(wgt_gbf1_need_data),
.wgt_gbf2_need_data(wgt_gbf2_need_data),
.r_data1b(r_data1b),
.r_data2b(r_data2b),
.r_en1b_out(r_en1b_out),
.r_en2b_out(r_en2b_out)
);
always #5 clk = ~clk;
integer i;
initial begin
clk = 0;
//IDLE state
reset = 0;
#10 reset = 1;
#10 reset = 0;
end
endmodule
| 6.686818
|
module accelerator_tb_synth ();
reg clk, reset; // Clock and Reset
// Inputs and outputs of accelerator module
wire [31:0]
image,
result0,
result1,
result2,
result3,
result4,
result5,
result6,
result7,
result8,
result9,
ctr1;
integer i; // Clock loop variable
// Initiating accelerator module
accelerator a1 (
.clk(clk),
.reset(reset),
.image(image),
.result0(result0),
.result1(result1),
.result2(result2),
.result3(result3),
.result4(result4),
.result5(result5),
.result6(result6),
.result7(result7),
.result8(result8),
.result9(result9),
.counter1(ctr1)
);
// Initiating the image data module
xmem u2 (
.ctr1 (ctr1),
.xdata(image)
);
// Set up clock
always #5 clk = ~clk;
initial begin
$display("RUNNING TEST");
clk = 0;
reset = 0;
#3 reset = 1; // This is active high reset
#6 reset = 0; // Reset removed - normal functioning resumes
@(posedge clk);
for (i = 0; i < 1000; i = i + 1) begin
@(posedge clk);
end
$display("Score_0 - %h", $signed(result0));
$display("Score_1 - %h", $signed(result1));
$display("Score_2 - %h", $signed(result2));
$display("Score_3 - %h", $signed(result3));
$display("Score_4 - %h", $signed(result4));
$display("Score_5 - %h", $signed(result5));
$display("Score_6 - %h", $signed(result6));
$display("Score_7 - %h", $signed(result7));
$display("Score_8 - %h", $signed(result8));
$display("Score_9 - %h", $signed(result9));
$finish;
end
endmodule
| 6.686818
|
module accelerator_tb_synth ();
reg clk, reset; // Clock and Reset
// Inputs and outputs of accelerator module
wire [31:0]
image,
result0,
result1,
result2,
result3,
result4,
result5,
result6,
result7,
result8,
result9,
ctr1;
integer i; // Clock loop variable
// Initiating accelerator module
accelerator a1 (
.clk(clk),
.reset(reset),
.image(image),
.result0(result0),
.result1(result1),
.result2(result2),
.result3(result3),
.result4(result4),
.result5(result5),
.result6(result6),
.result7(result7),
.result8(result8),
.result9(result9),
.counter1(ctr1)
);
// Initiating the image data module
xmem u2 (
.ctr1 (ctr1),
.xdata(image)
);
// Set up clock
always #5 clk = ~clk;
initial begin
$display("RUNNING TEST");
clk = 0;
reset = 0;
#3 reset = 1; // This is active high reset
#6 reset = 0; // Reset removed - normal functioning resumes
@(posedge clk);
for (i = 0; i < 1000; i = i + 1) begin
@(posedge clk);
end
$display("Score_0 - %h", $signed(result0));
$display("Score_1 - %h", $signed(result1));
$display("Score_2 - %h", $signed(result2));
$display("Score_3 - %h", $signed(result3));
$display("Score_4 - %h", $signed(result4));
$display("Score_5 - %h", $signed(result5));
$display("Score_6 - %h", $signed(result6));
$display("Score_7 - %h", $signed(result7));
$display("Score_8 - %h", $signed(result8));
$display("Score_9 - %h", $signed(result9));
$finish;
end
endmodule
| 6.686818
|
module accelerometer (
input wire address, // avalon_accelerometer_spi_mode_slave.address
input wire byteenable, // .byteenable
input wire read, // .read
input wire write, // .write
input wire [7:0] writedata, // .writedata
output wire [7:0] readdata, // .readdata
output wire waitrequest, // .waitrequest
input wire clk, // clk.clk
inout wire I2C_SDAT, // external_interface.I2C_SDAT
output wire I2C_SCLK, // .I2C_SCLK
output wire G_SENSOR_CS_N, // .G_SENSOR_CS_N
input wire G_SENSOR_INT, // .G_SENSOR_INT
output wire irq, // interrupt.irq
input wire reset // reset.reset
);
accelerometer_accelerometer_spi_0 accelerometer_spi_0 (
.clk (clk), // clk.clk
.reset (reset), // reset.reset
.address (address), // avalon_accelerometer_spi_mode_slave.address
.byteenable (byteenable), // .byteenable
.read (read), // .read
.write (write), // .write
.writedata (writedata), // .writedata
.readdata (readdata), // .readdata
.waitrequest (waitrequest), // .waitrequest
.irq (irq), // interrupt.irq
.I2C_SDAT (I2C_SDAT), // external_interface.export
.I2C_SCLK (I2C_SCLK), // .export
.G_SENSOR_CS_N(G_SENSOR_CS_N), // .export
.G_SENSOR_INT (G_SENSOR_INT) // .export
);
endmodule
| 7.098582
|
module AccelTop (
//////////// CLOCK //////////
input CLOCK_50,
input CLOCK2_50,
input CLOCK3_50,
//////////// KEY (Active Low) ///////////
input [3:0] KEY,
//////////// LEDG ////////
output [8:0] LEDG,
//////////// LEDR
output [17:0] LEDR,
//////////// PCIe //////////
input PCIE_PERST_N,
input PCIE_REFCLK_P,
input [0:0] PCIE_RX_P,
output [0:0] PCIE_TX_P,
output PCIE_WAKE_N,
//////////// GPIO, GPIO connect to GPIO Default //////////
inout [35:0] GPIO,
//////////// Fan Control //////////
inout FAN_CTRL
);
wire [4:0] pcie_reconfig_fromgxb_0_data;
wire [3:0] pcie_reconfig_togxb_data;
wire pcie_reconfig_clk;
altgx_reconfig gxreconf0 (
.reconfig_clk(pcie_reconfig_clk),
.reconfig_fromgxb(pcie_reconfig_fromgxb_0_data),
.reconfig_togxb(pcie_reconfig_togxb_data)
);
AccelSystem accelsys0 (
.clk_clk (CLOCK_50),
.reset_reset_n (KEY[0]),
.pcie_hard_ip_0_refclk_export (PCIE_REFCLK_P),
.pcie_hard_ip_0_pcie_rstn_export (PCIE_PERST_N),
.pcie_hard_ip_0_powerdown_pll_powerdown(PCIE_WAKE_N),
.pcie_hard_ip_0_powerdown_gxb_powerdown(PCIE_WAKE_N),
.pcie_hard_ip_0_rx_in_rx_datain_0 (PCIE_RX_P[0]),
.pcie_hard_ip_0_tx_out_tx_dataout_0 (PCIE_TX_P[0]),
.pcie_hard_ip_0_reconfig_fromgxb_0_data(pcie_reconfig_fromgxb_0_data),
.pcie_hard_ip_0_reconfig_togxb_data (pcie_reconfig_togxb_data),
.pcie_hard_ip_0_reconfig_gxbclk_clk (pcie_reconfig_clk),
.altpll_0_c1_clk (pcie_reconfig_clk),
);
//////////// FAN Control //////////
assign FAN_CTRL = 1'bz; // turn on FAN
assign LEDR = 0;
assign LEDG = 0;
endmodule
| 6.699024
|
module operates than I do.
*/
module DspEmu(
input wire [ 1:0] op, // The DSP opcode
input wire [17:0] a, // INPUT A
input wire [17:0] b, // INPUT B
input wire [47:0] c, // INPUT C
output reg [47:0] p, // OUTPUT
input wire clk
);
always @(posedge clk) begin
case (op)
`DSP_INSTRUCTION_CLR: p <= 0; // Clear operation -- sets OUTPUT to zero
`DSP_INSTRUCTION_ACC: p <= p + c; // Accumulate -- increment P by C
`DSP_INSTRUCTION_MAC: p <= p + (a*b); // Multiply and accumulate -- P += (A*B)
`DSP_INSTRUCTION_NOP: p <= p; // No-op -- P should stay where it is
endcase
// This is a debug line so we can see MAC operations as they happen,
// which will be good for debugging, but we might remove it if it gets spammy
//if (op == `DSP_INSTRUCTION_MAC) $display("MAC (%d * %d)", a, b);
end
endmodule
| 7.925834
|
module reads filter data from memory, and sends it out to the
* allocators along with a counter.
*
* Because of that, it's a fairly simple implementation. The biggest worry is
* timing issues coming out of memory, which I think are all solved.
*/
/* TODO
*
* 1. (Shared with allocator) the proper position and filter data to be sent
* to an allocator is available in the previous allocator. This may allow for
* systolic computing, which would cut down on the connection requirements of
* this module.
*/
module FilterBroadcast #(
// We need this only to accept the filter_block signal. Maybe that can
// be done by moving the OR reduction to "accel.v"?
parameter num_allocators = 220
) (
// For each output, we send the weight and a counter.
output reg [12:0] counter,
output wire [17:0] data,
// We also allow the receivers to "block" us if they're out of space,
// preventing further broadcast until block is lowered
output reg en,
input wire [num_allocators-1:0] block,
// How long is the filter? We need to know when to stop reading and
// counting
input wire [12:0] filter_length,
// Memory access -- filter probably won't be the critical path, so we
// can afford to skimp on read lines here and spend them elsewhere (on
// image broadcast, perhaps)
output wire [15:0] filter_read_addr,
input wire [17:0] filter_read_data,
// Done when we've sent the entire filter for the round
output reg done,
input wire clk,
input wire rst
);
// Memory is delayed by one cycle, so we mostly operate on the next value
// of the counter, instead of the present value
reg [12:0] counter_next;
// The address we want to read is represented by just the counter, nothing
// fancy. We pad it out with three bits to fill up the 15 bit address.
assign filter_read_addr = {3'b0, counter_next};
// If any allocators are blocking filter, we should hold
assign blocked = |block;
// Our output is just the value from memory, but we want that to be fast
assign data = filter_read_data;
// Main controls for this module
always @(posedge clk) begin
// Initial: counter is zero, no data ready, not done
if (rst) begin
counter_next <= 0;
en <= 0;
done <= 0;
// If we've sent everything, do nothing
end else if (done) begin
// When we reach the end of the count, we have nothing left to send
end else if (counter_next == filter_length) begin
en <= 0;
done <= 1;
// If a DSP is blocking, don't move, but we should show that there's
// no new data coming out
end else if (blocked) begin
en <= 0;
// Otherwise, count up and send data
end else begin
en <= 1;
counter_next <= counter_next + 1;
end
end
// filter_issue_counter is filter_issue_counter_next, delayed by one cycle
// (which usually means next-1, but not always)
always @(posedge clk) begin
if (rst) begin
counter <= 0;
end else begin
counter <= counter_next;
end
end
endmodule
| 6.99012
|
module Memory (
input wire [20:0] read_addr_a,
output reg [17:0] read_data_a,
input wire [15:0] read_addr_b,
output reg [17:0] read_data_b,
input wire [15:0] write_addr_a,
input wire [17:0] write_data_a,
input wire write_en_a,
input wire [15:0] write_addr_b,
input wire [17:0] write_data_b,
input wire write_en_b,
input wire clk
);
// Allocate 60 Ramb18's
localparam memsize = 2 * 1024 * 1024;
reg [17:0] memory[memsize-1:0];
// Read signals are easy
always @(posedge clk) read_data_a <= memory[read_addr_a];
always @(posedge clk) read_data_b <= memory[read_addr_b];
// Write signals write only when write_en is high
always @(posedge clk) begin
if (write_en_a) begin
memory[write_addr_a] <= write_data_a;
end
end
always @(posedge clk) begin
if (write_en_b) begin
memory[write_addr_b] <= write_data_b;
end
end
// Initialization block: memory is initialized to 0 by default
integer ii;
initial begin
$display("Initializing memory");
for (ii = 0; ii < memsize; ii = ii + 1) begin
`ifdef memory_init_dec
memory[ii] = ii * 10;
`else // memory_init_dec
memory[ii] = 0;
`endif // memory_init_dec
end
$display("Initializing memory done");
end
endmodule
| 7.051739
|
module
* implements the same functionality, and their interfaces should be similar
* enough that swapping them out is a trivial procedure.
*
* The RAMB18 stores 1k entries of 18-bit data, and provides 2 read lines and
* 2 write lines per block.
*
* In the real thing, reading and writing to the same address in the same
* cycle is not supported. Be warned.
*/
module Ramb18Emu(
// Read signals -- every cycle, the output will be written with the
// contents of the memory at the given address
input wire [ 9:0] read_addr,
output reg [17:0] read_data,
// Write signals -- when write_en is high, the input data will be
// written to the specified address.
input wire [ 9:0] write_addr,
input wire [17:0] write_data,
input wire write_en,
input wire clk
);
// Main memory of the emulated RAMB18
reg [17:0] memory [1023:0];
// Two independent write signals, which will each write an 18-bit value to
// the appropriate address every cycle write_en is high
always @(posedge clk) begin
if (write_en) begin
memory[write_addr] <= write_data;
// This is a debug line, which we can uncomment to see memory
// writes as they occur (in simulation).
//$display("%d --> [%d]", write_data_a, write_addr_a);
end
end
always @(posedge clk) read_data <= memory[read_addr];
endmodule
| 7.605316
|
module accel_width_conv #(
parameter DATA_IN_WIDTH = 128,
parameter DATA_OUT_WIDTH = 8,
parameter STRB_OUT_WIDTH = DATA_OUT_WIDTH / 8,
// TUSER is offset of last valid byte
parameter USER_WIDTH = $clog2(DATA_IN_WIDTH / 8)
) (
input wire clk,
input wire rst,
// Read data input
input wire [DATA_IN_WIDTH-1:0] s_axis_tdata,
input wire [ USER_WIDTH-1:0] s_axis_tuser,
input wire s_axis_tlast,
input wire s_axis_tvalid,
output wire s_axis_tready,
// Read data output
output reg [DATA_OUT_WIDTH-1:0] m_axis_tdata,
output reg [STRB_OUT_WIDTH-1:0] m_axis_tkeep,
output reg m_axis_tlast,
output reg m_axis_tvalid,
input wire m_axis_tready
);
localparam SKIP_BITS = $clog2(DATA_OUT_WIDTH / 8);
localparam PTR_WIDTH = USER_WIDTH - SKIP_BITS;
reg [ PTR_WIDTH-1:0] rd_ptr;
wire [STRB_OUT_WIDTH-1:0] strobe;
// Detecting last chunk and setting strobe
wire last_chunk = (rd_ptr == s_axis_tuser[USER_WIDTH-1:SKIP_BITS]);
if (SKIP_BITS == 0) assign strobe = 1'b1;
else assign strobe = ~({{STRB_OUT_WIDTH - 1{1'b1}}, 1'b0} << s_axis_tuser[SKIP_BITS-1:0]);
// out_ready works with accel always asserting tready or
// accepting tvalid in same cycle
wire out_ready = !m_axis_tvalid || m_axis_tready;
assign s_axis_tready = out_ready && last_chunk;
always @(posedge clk) begin
// Since data is coming from a FIFO, tvalid drop without
// tready assertion means there was a stop signal and
// rd_ptr needs to be reset. In normal mode and no
// tvalid it keeps the rd_ptr to be zero.
if (!s_axis_tvalid) rd_ptr <= {PTR_WIDTH{1'b0}};
else if (out_ready) begin
if (last_chunk) rd_ptr <= {PTR_WIDTH{1'b0}};
else rd_ptr <= rd_ptr + 1;
end
if (rst) rd_ptr <= {PTR_WIDTH{1'b0}};
end
// Register the outputs
always @(posedge clk) begin
m_axis_tdata <= s_axis_tdata[rd_ptr*DATA_OUT_WIDTH+:DATA_OUT_WIDTH];
m_axis_tkeep <= (s_axis_tlast && last_chunk) ? strobe : {STRB_OUT_WIDTH{1'b1}};
m_axis_tlast <= s_axis_tlast && last_chunk;
m_axis_tvalid <= s_axis_tvalid;
end
endmodule
| 8.212447
|
module Scheduler (
input wire positioner_round,
output reg positioner_advance,
input wire positioner_done,
output reg positioner_rst,
input wire image_broadcast_round,
output reg image_broadcast_rst,
input wire filter_broadcast_done,
output reg filter_broadcast_rst,
input wire allocator_done,
output reg allocator_rst,
output reg writeback_en,
output reg writeback_rst,
output reg accel_done,
input wire clk,
input wire rst
);
reg [2:0] state;
reg [2:0] delay_counter;
localparam positioner_headstart_delay = 1;
always @(posedge clk) begin
if (rst) begin
state <= `STATE_START_ROUND;
delay_counter <= 0;
end else if (state == `STATE_START_ROUND) begin
state <= `STATE_POSITIONER_HEADSTART;
delay_counter <= 0;
end else if (state == `STATE_POSITIONER_HEADSTART) begin
delay_counter <= delay_counter + 1;
if (delay_counter == positioner_headstart_delay) begin
state <= `STATE_BROADCASTING;
end
end else if (state == `STATE_BROADCASTING) begin
if (image_broadcast_round && (positioner_round || positioner_round) && allocator_done) begin
state <= `STATE_END_ROUND;
end
end else if (state == `STATE_END_ROUND) begin
if (positioner_done) begin
state <= `STATE_DONE;
end else begin
state <= `STATE_START_ROUND;
end
end else if (state == `STATE_DONE) begin
end
end
always @(*) begin
case (state)
`STATE_START_ROUND: begin
positioner_advance = 1;
positioner_rst = 0;
image_broadcast_rst = 1;
filter_broadcast_rst = 1;
allocator_rst = 1;
accel_done = 0;
writeback_en = 0;
writeback_rst = 0;
end
`STATE_POSITIONER_HEADSTART: begin
positioner_advance = 0;
positioner_rst = 0;
image_broadcast_rst = 1;
filter_broadcast_rst = 0;
allocator_rst = 0;
accel_done = 0;
writeback_en = 0;
writeback_rst = 0;
end
`STATE_BROADCASTING: begin
positioner_advance = 0;
positioner_rst = 0;
image_broadcast_rst = 0;
filter_broadcast_rst = 0;
allocator_rst = 0;
accel_done = 0;
writeback_en = 0;
writeback_rst = 0;
end
`STATE_END_ROUND: begin
positioner_advance = 0;
positioner_rst = 0;
image_broadcast_rst = 1;
filter_broadcast_rst = 1;
allocator_rst = 0;
accel_done = 0;
writeback_en = 1;
writeback_rst = 0;
end
`STATE_DONE: begin
positioner_advance = 0;
positioner_rst = 1;
image_broadcast_rst = 1;
filter_broadcast_rst = 1;
allocator_rst = 1;
accel_done = 1;
writeback_en = 0;
writeback_rst = 1;
end
default: begin
positioner_advance = 0;
positioner_rst = 1;
image_broadcast_rst = 1;
filter_broadcast_rst = 1;
allocator_rst = 1;
accel_done = 0;
writeback_en = 0;
writeback_rst = 1;
end
endcase
end
endmodule
| 7.138726
|
module accel_to_mem_bridge (
//qsys inputs
input clk,
input reset,
//accel inputs
input [127:0] writedata_from_accel,
input address_from_accel,
input write_from_accel,
input read_from_accel,
output [127:0] readdata_to_accel,
output waitrequest_to_accel,
//mem outputs
//ignore the upper bit of the address so that the s2 interface
//of on chip memory can sit at 0x0
input waitrequest_from_mem,
output [30:0] address_to_mem,
input [63:0] readdata_from_mem,
output read_to_mem,
output write_to_mem,
output [63:0] writedata_to_mem,
output [7:0] byteenable_to_mem
);
wire mem8, mem16, mem32, mem64;
wire [2:0] atm_byteSel_32bit;
assign mem8 = writedata_from_accel[96];
assign mem16 = writedata_from_accel[97];
assign mem64 = writedata_from_accel[98];
assign mem32 = ~(mem8 & mem16 & mem64);
assign atm_byteSel_32bit = writedata_from_accel[2:0];
assign write_to_mem = write_from_accel;
assign read_to_mem = read_from_accel;
//assign chipselect_to_mem = read_from_accel | write_from_accel;
//set byteenable according to appropiate byte enable signals
assign byteenable_to_mem = ({{4{mem64}}, {2{mem32|mem64}}, {mem16|mem32|mem64}, {1'b1}}) << atm_byteSel_32bit;
//set address to least significant 31 bits of writedata
assign address_to_mem = writedata_from_accel[30:0];
//concatenate readdata with byteenable shifted version
assign readdata_to_accel = {64'd0, readdata_from_mem} >> (atm_byteSel_32bit * 8);
//set actual writedata to middle 64 bits
assign writedata_to_mem = writedata_from_accel[95:32] << (atm_byteSel_32bit * 8);
endmodule
| 8.697892
|
module accel_wrap #(
parameter IO_DATA_WIDTH = 32,
parameter IO_STRB_WIDTH = (IO_DATA_WIDTH / 8),
parameter IO_ADDR_WIDTH = 22,
parameter DATA_WIDTH = 128,
parameter STRB_WIDTH = (DATA_WIDTH / 8),
parameter PMEM_ADDR_WIDTH = 1,
parameter AROM_ADDR_WIDTH = 1,
parameter AROM_DATA_WIDTH = DATA_WIDTH,
parameter SLOW_M_B_LINES = 4096,
parameter ACC_ADDR_WIDTH = $clog2(SLOW_M_B_LINES),
parameter PMEM_SEL_BITS = PMEM_ADDR_WIDTH - $clog2(STRB_WIDTH) - 1 - $clog2(SLOW_M_B_LINES),
parameter ACC_MEM_BLOCKS = 2 ** PMEM_SEL_BITS,
parameter SLOT_COUNT = 16
) (
input wire clk,
input wire rst,
input wire io_en,
input wire io_wen,
input wire [IO_STRB_WIDTH-1:0] io_strb,
input wire [IO_ADDR_WIDTH-1:0] io_addr,
input wire [IO_DATA_WIDTH-1:0] io_wr_data,
output wire [IO_DATA_WIDTH-1:0] io_rd_data,
output wire io_rd_valid,
input wire [AROM_ADDR_WIDTH-1:0] acc_rom_wr_addr,
input wire [AROM_DATA_WIDTH-1:0] acc_rom_wr_data,
input wire acc_rom_wr_en,
output wire [ ACC_MEM_BLOCKS-1:0] acc_en_b1,
output wire [ ACC_MEM_BLOCKS*STRB_WIDTH-1:0] acc_wen_b1,
output wire [ACC_MEM_BLOCKS*ACC_ADDR_WIDTH-1:0] acc_addr_b1,
output wire [ ACC_MEM_BLOCKS*DATA_WIDTH-1:0] acc_wr_data_b1,
input wire [ ACC_MEM_BLOCKS*DATA_WIDTH-1:0] acc_rd_data_b1,
output wire [ ACC_MEM_BLOCKS-1:0] acc_en_b2,
output wire [ ACC_MEM_BLOCKS*STRB_WIDTH-1:0] acc_wen_b2,
output wire [ACC_MEM_BLOCKS*ACC_ADDR_WIDTH-1:0] acc_addr_b2,
output wire [ ACC_MEM_BLOCKS*DATA_WIDTH-1:0] acc_wr_data_b2,
input wire [ ACC_MEM_BLOCKS*DATA_WIDTH-1:0] acc_rd_data_b2,
output wire error,
input wire error_ack
);
assign acc_en_b1 = 0;
assign acc_wen_b1 = 0;
assign acc_addr_b1 = 0;
assign acc_wr_data_b1 = 0;
assign acc_en_b2 = 0;
assign acc_wen_b2 = 0;
assign acc_addr_b2 = 0;
assign acc_wr_data_b2 = 0;
assign io_rd_data = 0;
assign io_rd_valid = 0;
assign error = 1'b0;
endmodule
| 6.941968
|
module accel_wrap #(
parameter IO_DATA_WIDTH = 32,
parameter IO_STRB_WIDTH = (IO_DATA_WIDTH / 8),
parameter IO_ADDR_WIDTH = 22,
parameter DATA_WIDTH = 128,
parameter STRB_WIDTH = (DATA_WIDTH / 8),
parameter PMEM_ADDR_WIDTH = 8,
parameter AROM_ADDR_WIDTH = 1,
parameter AROM_DATA_WIDTH = 1,
parameter SLOW_M_B_LINES = 4096,
parameter ACC_ADDR_WIDTH = $clog2(SLOW_M_B_LINES),
parameter PMEM_SEL_BITS = PMEM_ADDR_WIDTH - $clog2(STRB_WIDTH) - 1 - $clog2(SLOW_M_B_LINES),
parameter ACC_MEM_BLOCKS = 2 ** PMEM_SEL_BITS,
parameter SLOT_COUNT = 16
) (
input wire clk,
input wire rst,
input wire io_en,
input wire io_wen,
input wire [IO_STRB_WIDTH-1:0] io_strb,
input wire [IO_ADDR_WIDTH-1:0] io_addr,
input wire [IO_DATA_WIDTH-1:0] io_wr_data,
output wire [IO_DATA_WIDTH-1:0] io_rd_data,
output wire io_rd_valid,
input wire [AROM_ADDR_WIDTH-1:0] acc_rom_wr_addr,
input wire [AROM_DATA_WIDTH-1:0] acc_rom_wr_data,
input wire acc_rom_wr_en,
output wire [ ACC_MEM_BLOCKS-1:0] acc_en_b1,
output wire [ ACC_MEM_BLOCKS*STRB_WIDTH-1:0] acc_wen_b1,
output wire [ACC_MEM_BLOCKS*ACC_ADDR_WIDTH-1:0] acc_addr_b1,
output wire [ ACC_MEM_BLOCKS*DATA_WIDTH-1:0] acc_wr_data_b1,
input wire [ ACC_MEM_BLOCKS*DATA_WIDTH-1:0] acc_rd_data_b1,
output wire [ ACC_MEM_BLOCKS-1:0] acc_en_b2,
output wire [ ACC_MEM_BLOCKS*STRB_WIDTH-1:0] acc_wen_b2,
output wire [ACC_MEM_BLOCKS*ACC_ADDR_WIDTH-1:0] acc_addr_b2,
output wire [ ACC_MEM_BLOCKS*DATA_WIDTH-1:0] acc_wr_data_b2,
input wire [ ACC_MEM_BLOCKS*DATA_WIDTH-1:0] acc_rd_data_b2,
output wire error,
input wire error_ack
);
assign error = 1'b0;
assign acc_en_b1 = 0;
assign acc_wen_b1 = 0;
assign acc_addr_b1 = 0;
assign acc_wr_data_b1 = 0;
assign acc_en_b2 = 0;
assign acc_wen_b2 = 0;
assign acc_addr_b2 = 0;
assign acc_wr_data_b2 = 0;
reg [ 31:0] hash_data_reg = 0;
reg [ 1:0] hash_data_len_reg = 0;
reg hash_data_valid_reg = 0;
reg hash_clear_reg = 0;
wire [ 31:0] hash_out;
reg [IO_DATA_WIDTH-1:0] read_data_reg;
reg read_data_valid_reg;
assign io_rd_data = read_data_reg;
assign io_rd_valid = read_data_valid_reg;
always @(posedge clk) begin
hash_data_valid_reg <= 1'b0;
hash_clear_reg <= 1'b0;
read_data_valid_reg <= 1'b0;
if (io_en && io_wen) begin
hash_data_reg <= io_wr_data;
case (io_addr[8:0] & ({IO_ADDR_WIDTH{1'b1}} << 2))
9'h100: begin
hash_clear_reg <= 1'b1;
end
9'h104: begin
hash_data_len_reg <= 1;
hash_data_valid_reg <= 1'b1;
end
9'h108: begin
hash_data_len_reg <= 2;
hash_data_valid_reg <= 1'b1;
end
9'h10C: begin
hash_data_len_reg <= 0;
hash_data_valid_reg <= 1'b1;
end
endcase
end
if (io_en && ~io_wen && ({io_addr[8:2], 2'b00} == 9'h110)) begin
read_data_reg <= hash_out;
read_data_valid_reg <= 1'b1;
end
if (rst) begin
hash_data_valid_reg <= 1'b0;
hash_clear_reg <= 1'b0;
read_data_valid_reg <= 1'b0;
end
end
hash_acc #(
.HASH_WIDTH(36)
) hash_acc_inst (
.clk(clk),
.rst(rst),
.hash_data(hash_data_reg),
.hash_data_len(hash_data_len_reg),
.hash_data_valid(hash_data_valid_reg),
.hash_clear(hash_clear_reg),
.hash_key(320'h6d5a56da255b0ec24167253d43a38fb0d0ca2bcbae7b30b477cb2da38030f20c6a42b73bbeac01fa),
.hash_out(hash_out)
);
endmodule
| 6.941968
|
module Writeback (
input wire [17:0] data,
input wire en,
output reg [17:0] out_mem_data,
output reg [15:0] out_mem_addr,
output reg out_mem_en,
input wire clk,
input wire rst
);
reg [12:0] output_counter;
always @(posedge clk) begin
if (rst) begin
output_counter <= 0;
out_mem_data <= 0;
out_mem_addr <= 0;
out_mem_en <= 0;
end else if (en) begin
//$display("Writeback: %d <-- %d", output_counter, data);
out_mem_data <= data;
out_mem_addr <= output_counter;
out_mem_en <= 1;
output_counter <= output_counter + 1;
end else if (out_mem_en) begin
out_mem_en <= 0;
end
end
`ifdef write_out_file
integer fptr;
initial begin
fptr = $fopen("/home/anton/tmp/verilog.out", "w");
end
always @(posedge clk) begin
if (rst) begin
end else if (en) begin
$fwrite(fptr, "%d\n", data);
end
end
`endif // write_out_file
endmodule
| 7.578539
|
module accessControl (
userIDfoundFlag,
loadButton_s,
PASSWORD,
passInput,
clk,
rst,
accessFlag,
blinkFlag,
outOfAttemptsFlag,
state
);
input loadButton_s, rst, clk, userIDfoundFlag;
input [3:0] passInput;
input [15:0] PASSWORD;
output reg accessFlag, blinkFlag, outOfAttemptsFlag;
output reg [2:0] state;
reg isFlagRed;
reg [1:0] attemptCnt;
parameter BIT0 = 3'b000, // 7 States
BIT1 = 3'b001,
BIT2 = 3'b010,
BIT3 = 3'b011,
BIT4 = 3'b100,
BIT5 = 3'b101,
VERIFICATION = 3'b110,
END = 3'b111;
parameter PRESSED = 1'b0, YES = 1'b1, NO = 1'b0;
always @(posedge clk, negedge rst) begin
if (~rst) begin
state <= BIT0;
attemptCnt <= 0;
outOfAttemptsFlag <= NO;
end else begin
case (state)
BIT0: begin
accessFlag <= NO;
isFlagRed <= NO;
blinkFlag <= 0;
if (userIDfoundFlag) begin
if (loadButton_s == YES) begin
if (passInput != PASSWORD[15:12]) begin
isFlagRed <= YES;
end
if (attemptCnt == 2'b111) begin
state <= END;
end else begin
attemptCnt <= attemptCnt + 1;
state <= BIT1;
end
end else begin
state <= BIT0;
end
end else begin
state <= BIT0;
end
end
BIT1: begin
accessFlag <= NO;
if (loadButton_s == YES) begin
if (passInput != PASSWORD[11:8]) begin
isFlagRed = YES;
end
state <= BIT2;
end else begin
state <= BIT1;
end
end
BIT2: begin
accessFlag <= NO;
if (loadButton_s == YES) begin
if (passInput != PASSWORD[7:4]) begin
isFlagRed <= YES;
end
state <= BIT3;
end else begin
state <= BIT2;
end
end
BIT3: begin
accessFlag <= NO;
if (loadButton_s == YES) begin
if (passInput != PASSWORD[3:0]) begin
isFlagRed <= YES;
end
state <= VERIFICATION;
end else begin
state <= BIT3;
end
end
VERIFICATION: begin
if (isFlagRed == NO) begin
accessFlag <= YES;
state <= VERIFICATION;
end else begin
accessFlag <= NO;
blinkFlag <= 1;
state <= BIT0;
end
end
END: begin
outOfAttemptsFlag <= YES;
accessFlag <= NO;
state <= END;
end
default: begin
isFlagRed <= NO;
state <= BIT0;
end
endcase
end
end
endmodule
| 7.760606
|
module AccessMem (
//rw_data
input [31:0] data_w,
output [31:0] data_r,
input [31:0] addr,
//ctrl
input [ 3:0] rw_type, //{u, w, h, b}
//to mem
output [31:2] addr_to_mem,
output [ 3:0] be, //brank enable
output [31:0] data_to_mem,
input [31:0] data_from_mem
);
wire u, w, h, b;
assign {u, w, h, b} = rw_type;
wire [1:0] a;
assign a = addr[1:0];
assign addr_to_mem = addr[31:2];
assign be[0] = ~a[1] & ~a[0] & (b | h | w);
assign be[1] = ~a[1] & a[0] & b | ~a[1] & ~a[0] & (h | w);
assign be[2] = a[1] & ~a[0] & (b | h) | ~a[1] & ~a[0] & w;
assign be[3] = a[1] & a[0] & b | a[1] & ~a[0] & h | ~a[1] & ~a[0] & w;
//write (store)
wire [31:0] data_w_b;
wire [31:0] data_w_h;
assign data_w_b = {4{data_w[7:0]}};
assign data_w_h = {2{data_w[15:0]}};
assign data_to_mem = w == 1 ? data_w :
h == 1 ? data_w_h :
b == 1 ? data_w_b :
{32{1'b0}};
//read (load)
wire [ 7:0] data_r_b;
wire [15:0] data_r_h;
assign data_r_b = {8{be[0]}} & data_from_mem[7:0] |
{8{be[1]}} & data_from_mem[15:8] |
{8{be[2]}} & data_from_mem[23:16] |
{8{be[3]}} & data_from_mem[31:24];
assign data_r_h = {16{be[0]}} & data_from_mem[15:0] | {16{be[2]}} & data_from_mem[31:16];
wire h_ext;
wire b_ext;
assign h_ext = data_r_h[15];
assign b_ext = data_r_b[7];
assign data_r[31:16] = w == 1 ? data_from_mem[31:16]:
u == 1 ? {16{1'b0}} :
h == 1 ? {16{h_ext}} :
b == 1 ? {16{b_ext}} :
{16{1'b0}};
assign data_r[15:8] = w == 1 ? data_from_mem[15:8]:
h == 1 ? data_r_h[15:8]:
u == 1 ? {8{1'b0}} :
b == 1 ? {8{b_ext}} :
{8{1'b0}};
assign data_r[7:0] = w == 1 ? data_from_mem[7:0]:
h == 1 ? data_r_h[7:0] :
b == 1 ? data_r_b :
{8{1'b0}};
endmodule
| 7.583727
|
module accessor (
input logic clk,
input logic reset,
// inputs
input executor_output in,
// memory access
output logic [31:0] mem_addr,
output logic [3:0] mem_wstrb,
output logic [31:0] mem_wdata,
input logic [31:0] mem_rdata,
// outputs
output accessor_output out
);
logic addr16;
assign addr16 = in.mem_addr[1];
logic [1:0] addr24;
assign addr24 = in.mem_addr[1:0];
logic [31:0] write_request;
// make the request
always_comb begin
if (reset) begin
mem_addr = 0;
mem_wstrb = 0;
write_request = 0;
end else begin
write_request = in.mem_data;
// request is synchronous
(* parallel_case, full_case *)
case (1'b1)
in.is_lw || in.is_lh || in.is_lhu || in.is_lb || in.is_lbu: begin
mem_wstrb = 4'b0000;
mem_addr = {in.mem_addr[31:2], 2'b00};
end
in.is_sw || in.is_sh || in.is_sb: begin
(* parallel_case, full_case *)
case (1'b1)
in.is_sw: begin
mem_addr = in.mem_addr;
mem_wstrb = 4'b1111;
write_request = in.mem_data;
end
in.is_sh: begin
// Offset to the right position
mem_wstrb = in.mem_addr[1] ? 4'b1100 : 4'b0011;
write_request = {2{in.mem_data[15:0]}};
end
in.is_sb: begin
mem_wstrb = 4'b0001 << in.mem_addr[1:0];
write_request = {4{in.mem_data[7:0]}};
end
endcase // case (1'b1)
mem_addr = {in.mem_addr[31:2], 2'b00};
end // case: in.is_sw || in.is_sh || in.is_sb
endcase // case (1'b1)
end // else: !if(reset)
end // always_comb
always_ff @(posedge clk) begin
// response is registered
if (reset) begin
out <= 0;
mem_wdata <= 0;
end else begin
mem_wdata <= write_request;
out.rd_data <= in.rd_data;
out.rd <= in.rd;
(* parallel_case, full_case *)
case (1'b1)
// unpack the alignment from above
in.is_lb: begin
case (addr24)
2'b00: out.rd_data <= {{24{mem_rdata[7]}}, mem_rdata[7:0]};
2'b01: out.rd_data <= {{24{mem_rdata[15]}}, mem_rdata[15:8]};
2'b10: out.rd_data <= {{24{mem_rdata[23]}}, mem_rdata[23:16]};
2'b11: out.rd_data <= {{24{mem_rdata[31]}}, mem_rdata[31:24]};
endcase
end
in.is_lbu: begin
case (addr24)
2'b00: out.rd_data <= {24'b0, mem_rdata[7:0]};
2'b01: out.rd_data <= {24'b0, mem_rdata[15:8]};
2'b10: out.rd_data <= {24'b0, mem_rdata[23:16]};
2'b11: out.rd_data <= {24'b0, mem_rdata[31:24]};
endcase
end
in.is_lh: begin
case (addr16)
1'b0: out.rd_data <= {{16{mem_rdata[15]}}, mem_rdata[15:0]};
1'b1: out.rd_data <= {{16{mem_rdata[31]}}, mem_rdata[31:16]};
endcase
end
in.is_lhu: begin
case (addr16)
1'b0: out.rd_data <= {16'b0, mem_rdata[15:0]};
1'b1: out.rd_data <= {16'b0, mem_rdata[31:16]};
endcase
end
in.is_lw: out.rd_data <= mem_rdata;
endcase
end // else: !if(reset)
end
`ifdef FORMAL
logic clocked;
initial clocked = 0;
always_ff @(posedge clk) clocked <= 1;
// assume we've reset at clk 0
initial assume (reset);
always_comb if (!clocked) assume (reset);
// if we've been valid but stalled, we're not valid anymore
always_ff @(posedge clk)
if (clocked && $past(accessor_valid) && $past(!writeback_ready))
assert (!accessor_valid);
// if we're stalled we aren't requesting anytthing, and we're not publishing anything
always_ff @(posedge clk) if (clocked && $past(stalled)) assert (!accessor_valid);
always_ff @(posedge clk) if (clocked && !$past(reset) && $past(stalled)) assert (!accessor_ready);
`endif
endmodule
| 6.695145
|
module access_controler #(
parameter nregwr = 41,
parameter nregr = 6
) (
input clk,
input rst,
output we,
output reg [7:0] data_out,
output reg [$clog2(nregwr+nregr)-1:0] addr,
input [7:0] data_in,
output reg ready,
output reg [7:0] datar,
input [7:0] dataw,
input valid
);
localparam adrr_s = 0;
localparam write = 1;
localparam read = 2;
localparam burst = 3;
reg [$clog2(nregwr)-1:0] burst_cnt;
reg [1:0] state;
always @(posedge clk) begin
if (rst) begin
state <= adrr_s;
end else if (state == adrr_s & dataw == 8'hFF & valid) begin
state <= burst;
end else if (state == adrr_s & dataw[7] & valid) begin
state <= write;
end else if (state == adrr_s & ~dataw[7] & valid) begin
state <= read;
end else if (state == write & valid) begin
state <= adrr_s;
end else if (state == read & valid) state <= adrr_s;
else if (state == burst & burst_cnt == (nregwr + 1)) state <= adrr_s;
end
reg single_we;
reg burst_we;
assign we = single_we | burst_we;
always @(posedge clk) begin
//****sampling address*******
if (rst) addr <= 0;
else if (state == adrr_s & valid) addr <= dataw[$clog2(nregwr+nregr)-1:0];
else if (state == burst) addr <= burst_cnt;
//*********************
//****Write transaction actions***
if (rst) begin
data_out <= 0;
single_we <= 0;
end else if (state == write & valid) begin
single_we <= 1;
data_out <= dataw;
end else single_we <= 0;
//**************
//****Read transaction actions**
if (rst) begin
datar <= 0;
ready <= 0;
end else if (state == read) begin
datar <= data_in;
ready <= 1;
end else ready <= 0;
//**************
//****BURST transaction actions**
if (rst | state == burst & burst_cnt == (nregwr + 1)) begin
burst_cnt <= 0;
data_out <= 0;
burst_we <= 0;
end else if (state == burst & valid) begin
burst_cnt <= burst_cnt + 1;
burst_we <= 1;
data_out <= dataw;
end else burst_we <= 0;
//*******************************
end
endmodule
| 8.723234
|
module access_controller #(
parameter size_word = 8,
parameter nregwr = 121,
parameter nregr = 1
) //You have 122 register on the bank. 121 for write and 1 for read
(
input clk,
input rst,
output reg we, // Indicate if it's write mode (we=1) or read mode (we=0)
output reg [size_word-1:0] data_out, //The data to write on registers bank
output reg [$clog2(nregwr+nregr)-1:0] addr, // Address to write or read
input [size_word-1:0] data_in, //The data to read from registers bank.
output reg ready,
output [size_word-1:0] datar, //The data that will read and send to the Master(PC)
input [size_word-1:0]dataw, //Added a bit more to indicate if will write or read on register banks. The MSB don't care.
input valid // Indicates id everything is working properly.
);
localparam adrr_s = 0;
localparam write = 1;
localparam read = 2;
//localparam burst=3;
reg [$clog2(nregwr)-1:0] write_cnt;
reg [1:0] state;
always @(posedge clk) begin
if (rst) begin
state <= adrr_s;
end
else if( state==adrr_s & dataw[size_word-1] & valid)begin // If data sent has MSB equal to 1 then, to move to Write state
state <= write;
end
else if( state==adrr_s & ~dataw[size_word-1] & valid)begin //If data sent has MSB equal to 0 then, to move to Write state
state <= read;
end else if (state == write & write_cnt == (nregwr)) begin
state <= adrr_s;
end else if (state == read & valid) begin
state <= adrr_s;
end
end
//reg read_we;
//reg write_we;
//assign we = single_we;
assign datar = data_in;
always @(posedge clk) begin
//****sampling address*******
if (rst) addr <= 0;
else if (state == adrr_s & valid)
addr <= dataw[$clog2(nregwr+nregr)-1:0]; // Requiero 8 bits para ubicar los registros
else if (state == write) addr <= write_cnt;
//*********************
//****Read transaction actions**
if (rst) begin
ready <= 0;
end else if (state == read) begin
ready <= 1;
end else ready <= 0;
//**************
//****Write transaction actions**
if (rst | state == write & write_cnt == (nregwr)) begin
write_cnt <= 0;
data_out <= 0;
we <= 0;
end else if (state == write & valid) begin
write_cnt <= write_cnt + 1;
we <= 1;
data_out <= dataw;
end else we <= 0;
//*******************************
end
endmodule
| 8.723234
|
module Access_Control_Top (
clk,
reset,
Pwd_In,
pwd_BS,
user_id_inp,
user_id_BS,
SevSeg_userID,
SevSeg_PWD,
Red_LED,
Green_LED,
RLED_pwd,
GLED_pwd,
Logout_signal,
address_out_user_id
);
input [3:0] Pwd_In, user_id_inp;
input pwd_BS, user_id_BS, clk, reset, Logout_signal;
output Red_LED, Green_LED, RLED_pwd, GLED_pwd;
output [3:0] SevSeg_userID, SevSeg_PWD;
output [4:0] address_out_user_id;
user_id_rom_controller user_id (
user_id_inp,
clk,
reset,
user_id_BS,
Green_LED,
Red_LED,
SevSeg_userID,
Logout_signal,
address_out_user_id
);
password_controller pwd (
Pwd_In,
clk,
reset,
pwd_BS,
GLED_pwd,
RLED_pwd,
SevSeg_PWD,
Logout_signal,
address_out_user_id,
Green_LED
);
endmodule
| 7.118812
|
module access_ctr (
clk,
rst,
re,
update_EVA
);
parameter accessCtrWidth = 13;
input clk;
input rst;
input re;
output reg update_EVA;
reg [(accessCtrWidth-1):0] number_of_access_counter;
////// ****** access counter logic & genrating update_EVA signal ****** ////////////
always @(posedge clk) begin
#0.1
if (rst) begin
number_of_access_counter <= {(accessCtrWidth) {1'b0}}; //////change with ctrLen//////
update_EVA <= 1'b0;
end else if (re) begin
if (number_of_access_counter[accessCtrWidth-1] == 1'b1) begin //////change with ctrLen//////
number_of_access_counter <= 12'b0; //////change with ctrLen//////
update_EVA <= 1'b1; //////////////////generating after every 2048 access///////////
end else begin
number_of_access_counter <= number_of_access_counter + 1;
update_EVA <= 1'b0;
end
end
end
//////////////////////////// ************************* ////////////////////////////
endmodule
| 7.245908
|
module access_dirty_check_unit (
input r_req_store,
input pte_a,
input pte_d,
output AD_bit_not_ok
);
assign AD_bit_not_ok = !pte_d && r_req_store || !pte_a;
endmodule
| 7.116008
|
module accInc (
input signed [`PRECISION-1:0] phaseIn,
input signed [`PRECISION-1:0] accIn,
output reg signed [`PRECISION-1:0] accOut
);
//###################################################################################################
always @(*) begin
accOut = $signed(accIn + phaseIn);
// hangle negative
if ($signed(accOut) < 0) begin
accOut = $signed(accOut + `SCALE_2X);
end
// mod(accInc,2)
if ($signed(accOut) >= $signed(`SCALE_2X)) begin
accOut = $signed(accOut - `SCALE_2X);
end
end
endmodule
| 7.125508
|
module ACCM (
input [ 6:0] X,
output reg [`a-1:0] ACC = 0,
/*input ce,*/ output wire CO, //
input clk,
output reg Mx = 0
); //
parameter M = 625; //F = X * 50Mhz / (50000) = X * 1kHz
assign CO = (X + ACC >= M); // CO=1 X+ACC >= M
always @(posedge clk) begin
ACC <= CO ? ACC + X - M : ACC + X; // M
Mx <= CO ? !Mx : Mx; //
end
endmodule
| 6.79468
|
module accmaskreg2 (
input wire clk,
input wire rst,
input wire cpu, // CPU wuenscht Zugriff
input wire [15:0] reginp, // Registerbus
output wire [15:0] regout // Acceptance Mask Register
);
//tmrg default triplicate
//tmrg tmr_error false
reg [15:0] reg_i;
//triplication signals
wire [15:0] reg_iVoted = reg_i;
assign regout = reg_iVoted;
always@(posedge clk) // steigende Flanke
begin
if (rst == 1'b0) begin // synchroner Reset
reg_i <= 16'd0;
end else begin
reg_i <= reg_iVoted;
if (cpu == 1'b1) begin // cpu schreibt
reg_i <= reginp;
end
end
end
endmodule
| 7.750148
|
module ACControl( //Main ULA input accumulator control unit
jump,
jumpC,
sin,
InA,
twone,
saidaMux,
saidaAc,
);
input jump, jumpC, sin, InA, twone;
output reg saidaMux, saidaAc;
always @(*)
begin
saidaMux <= twone & ~InA;
saidaAc <= ~(jump | jumpC) & (sin | twone);
end
endmodule
| 6.680494
|
module ACControl_tb;
reg jump, jumpC, sin, InA, twone;
wire saidaMux, saidaAc;
accontrol control (
.jump(jump),
.jumpC(jumpC),
.sin(sin),
.InA(InA),
.twone(twone),
.saidaMux(saidaMux),
.saidaAc(saidaAc)
);
initial begin
$monitor("J = %b, Jc = %b, Sin = %b, InA = %b, 1&2 = %b, Mux = %b, AC = %b", jump, jumpC, sin,
InA, twone, saidaMux, saidaAc);
//$dumpfile ("testbench/ACControl.vcd");
//$dumpvars(0, ACControl_tb);
jump = 0;
jumpC = 0;
sin = 0;
InA = 0;
twone = 0;
#20 jump = 1;
jumpC = 0;
sin = 0;
InA = 0;
twone = 0;
#20 jump = 0;
jumpC = 1;
sin = 0;
InA = 0;
twone = 0;
#20 jump = 1;
jumpC = 1;
sin = 0;
InA = 0;
twone = 0;
#20 jump = 0;
jumpC = 0;
sin = 1;
InA = 0;
twone = 0;
#20 jump = 0;
jumpC = 0;
sin = 1;
InA = 0;
twone = 1;
#20 jump = 0;
jumpC = 0;
sin = 0;
InA = 0;
twone = 1;
#20 jump = 0;
jumpC = 0;
sin = 0;
InA = 1;
twone = 1;
#20 jump = 0;
jumpC = 0;
sin = 0;
InA = 1;
twone = 0;
//$monitor("test completed");
$display("test completed");
end
endmodule
| 7.667169
|
module accumCol (
clk,
clear,
rd_en,
wr_en,
rd_addr,
wr_addr,
rd_data,
wr_data
);
parameter DATA_WIDTH = 16; // number of bits for one piece of data
parameter MAX_OUT_ROWS = 128; // output height of largest matrix
parameter MAX_OUT_COLS = 128; // output width of largest possible matrix
parameter SYS_ARR_COLS = 16; // height of the systolic array
localparam NUM_ACCUM_ROWS = MAX_OUT_ROWS * (MAX_OUT_COLS / SYS_ARR_COLS);
input clk;
input clear; // clears array and sets it to 0
input rd_en; // reads the data at rd_addr when high
input wr_en; // writes (and accumulates) data to wr_addr when high
input [$clog2(NUM_ACCUM_ROWS)-1:0] rd_addr;
input [$clog2(NUM_ACCUM_ROWS)-1:0] wr_addr;
output reg signed [DATA_WIDTH-1:0] rd_data;
input signed [DATA_WIDTH-1:0] wr_data;
reg [DATA_WIDTH-1:0] mem[NUM_ACCUM_ROWS-1:0];
integer i; // used for indexing
always @(posedge clk) begin
if (wr_en) begin
mem[wr_addr] <= mem[wr_addr] + wr_data;
end // if (wr_en)
if (rd_en) begin
rd_data <= mem[rd_addr];
end // if (rd_en)
if (clear) begin
for (i = 0; i < NUM_ACCUM_ROWS; i = i + 1) begin // clear all entries to 0
mem[i] <= 0; // not sure if there is a good way to define literal width
end // for (i = 0; i < NUM_ACCUM_ROWS; i = i + 1)
end // if (clear)
end // always @(posedge clk)
endmodule
| 7.407489
|
module accumTable (
clk,
clear,
rd_en,
wr_en,
rd_addr,
wr_addr,
rd_data,
wr_data
);
parameter DATA_WIDTH = 16; // number of bits for one piece of data
parameter MAX_OUT_ROWS = 128; // output number of rows in
parameter MAX_OUT_COLS = 128;
parameter SYS_ARR_ROWS = 16;
parameter SYS_ARR_COLS = 16;
localparam NUM_ACCUM_ROWS = MAX_OUT_ROWS * (MAX_OUT_COLS / SYS_ARR_COLS);
input clk;
input [SYS_ARR_COLS-1:0] clear; // needs to be connected to reset signal
input [SYS_ARR_COLS-1:0] rd_en;
input [SYS_ARR_COLS-1:0] wr_en;
input [$clog2(NUM_ACCUM_ROWS)*SYS_ARR_COLS-1:0] rd_addr;
input [$clog2(NUM_ACCUM_ROWS)*SYS_ARR_COLS-1:0] wr_addr;
output wire [DATA_WIDTH*SYS_ARR_COLS-1:0] rd_data;
input [DATA_WIDTH*SYS_ARR_COLS-1:0] wr_data;
accumCol colArray[0:SYS_ARR_COLS-1] (
.clk (clk),
.clear (clear),
.rd_en (rd_en),
.wr_en (wr_en),
.rd_addr(rd_addr),
.wr_addr(wr_addr),
.rd_data(rd_data),
.wr_data(wr_data)
);
endmodule
| 6.758265
|
module outputs the proper addressing for an accumulator table
* column. The inputs are what number output the systolic array is outputting
* and which sub-matrix of the divide and conquer matrix multiply is currently
* being output by the systolic array. Since each column of the systolic array
* needs to store its outputs at the same address in successive clock cycles,
* the output of this module can be latched into a pipeline that moves between
* the columns of the accumulator (as opposed to calculating all of the columns
* addresses at once).
*/
module accumTableAddr_control(sub_row, submat_m, submat_n, addr);
parameter MAX_OUT_ROWS = 128; // output number of rows in
parameter MAX_OUT_COLS = 128;
parameter SYS_ARR_ROWS = 16;
parameter SYS_ARR_COLS = 16;
localparam NUM_ACCUM_ROWS = MAX_OUT_ROWS*(MAX_OUT_COLS/SYS_ARR_COLS);
localparam NUM_SUBMATS_M = MAX_OUT_ROWS/SYS_ARR_ROWS; // not sure if this will do ceiling like I want
localparam NUM_SUBMATS_N = MAX_OUT_COLS/SYS_ARR_COLS; // not sure if this will do ceiling like I want
input [$clog2(SYS_ARR_ROWS)-1:0] sub_row;
input [$clog2(NUM_SUBMATS_M)-1:0] submat_m; // sub-matrix row number (sub-matrix position in the overall matrix)
input [$clog2(NUM_SUBMATS_N)-1:0] submat_n; // sub-matrix col number (sub-matrix position in the overall matrix)
output wire [$clog2(NUM_ACCUM_ROWS)-1:0] addr; // write addresses for all columns concatenated
assign addr = (submat_n*MAX_OUT_ROWS) + (submat_m*SYS_ARR_ROWS) + (SYS_ARR_ROWS-1-sub_row);
endmodule
| 6.829553
|
module accumulater (
input clk,
input rst,
input setzero,
input [12:0] feed,
input addflag,
output reg [12:0] value
);
/*always @(posedge rst) begin
value = 0;
end*/
reg [13:0] buffer;
always @(posedge clk or posedge rst) begin
if (rst) begin
buffer = 0;
end else begin
value = buffer;
if (setzero) begin
buffer = 0;
end
if (addflag) buffer = buffer + feed;
else buffer = buffer - feed;
end
$display("acc :: value : %b, feed : %b, rst : %b, setzero : %b, buffer : %b", value, feed,
rst, setzero, buffer);
end
endmodule
| 6.559937
|
module accumulator #(
parameter A_IN_PRECISION = 16,
parameter B_IN_PRECISION = 10,
parameter O_OUT_PRECISION = 8,
parameter MULT_LATENCY = 0
) (
input i_arst,
input i_sysclk,
input i_en,
input i_load,
input [A_IN_PRECISION-1:0] i_a,
input [B_IN_PRECISION-1:0] i_b,
output o_en,
output [O_OUT_PRECISION:0] o_O
);
wire [A_IN_PRECISION+B_IN_PRECISION-1:0] w_mult_out;
reg r_en_1P;
reg [A_IN_PRECISION+B_IN_PRECISION-8-1:0] r_adder_1P;
mult_a_signed_b_signed #(
.A_WIDTH(A_IN_PRECISION),
.B_WIDTH(B_IN_PRECISION),
.LATENCY(MULT_LATENCY)
) inst_mult (
.arst(i_arst),
.clk(i_sysclk),
.a(i_a),
.b(i_b),
.o(w_mult_out)
);
always @(posedge i_arst or posedge i_sysclk) begin
if (i_arst) begin
r_en_1P <= 1'b0;
r_adder_1P <= {A_IN_PRECISION + B_IN_PRECISION - 8{1'b0}};
end else begin
r_en_1P <= i_en;
if (i_en) begin
if (i_load) r_adder_1P <= w_mult_out[A_IN_PRECISION+B_IN_PRECISION-1:8];
else r_adder_1P <= r_adder_1P + w_mult_out[A_IN_PRECISION+B_IN_PRECISION-1:8];
end
end
end
assign o_en = r_en_1P;
assign o_O = r_adder_1P[O_OUT_PRECISION+2:2];
endmodule
| 6.937161
|
module Accumulator1 (
Input_Arr,
Output
);
parameter size_Of_Array = 4;
parameter DATA_WIDTH = 32;
input [DATA_WIDTH*size_Of_Array-1:0] Input_Arr;
wire [DATA_WIDTH*(size_Of_Array+1)-1:0] Output_Arr;
output [DATA_WIDTH-1:0] Output;
assign Output_Arr[0+:DATA_WIDTH] = 32'b0;
genvar i;
generate
for (i = 0; i < size_Of_Array; i = i + 1) begin : add
add add1 (
.A_FP(Output_Arr[DATA_WIDTH*i+:DATA_WIDTH]),
.B_FP(Input_Arr[DATA_WIDTH*i+:DATA_WIDTH]),
.out (Output_Arr[DATA_WIDTH*(i+1)+:DATA_WIDTH])
);
end
endgenerate
assign Output = Output_Arr[DATA_WIDTH*size_Of_Array+:DATA_WIDTH];
/* always @(*)
begin
Output_Arr[0+:DATA_WIDTH]=32'b0;
end*/
endmodule
| 7.578767
|
module accumulatorRegister #(
parameter N = 16
) (
input clk,
input rst,
input accLd,
input [N-1:0] in,
output [N-1:0] out
);
reg [N-1:0] register;
always @(posedge clk, posedge rst) begin
if (rst) register <= 0;
else if (accLd) begin
register <= in;
end
end
assign out = register;
endmodule
| 7.67327
|
module EightBitAdder (
A,
B,
SUM,
CO
);
input [7:0] A;
input [7:0] B;
output [7:0] SUM;
output CO;
wire [8:0] tmp;
assign tmp = A + B;
assign SUM = tmp[7:0];
assign CO = tmp[8];
endmodule
| 7.369945
|
module Accumulator_8bit (
clock,
accumulate,
clear,
in1,
accum_out,
overflow
);
input clock;
input accumulate;
input clear;
input [7:0] in1;
output [7:0] accum_out;
output overflow;
reg [7:0] accum_out;
wire [7:0] accum_in;
wire carry;
wire overflow;
wire enable;
wire [7:0] result;
EightBitAdder u1 (
in1,
accum_out,
result,
overflow
);
assign enable = accumulate || clear;
assign accum_in = (clear == 1) ? 8'b0 : result;
always @(posedge clock) if (enable) accum_out <= accum_in;
endmodule
| 6.900037
|
module accumulator_adder (
clk,
adders_flag_i,
stage_finish_pipeline_5_i,
accumulator_0_i,
accumulator_1_i,
accumulator_2_i,
accumulator_3_i,
accumulator_o
);
parameter ACCUMULATOR_BIT_WIDTH = 16 + 6 + 2 + 4; // 16+6+2=24 --> 28
parameter TEMP_BIT_WIDTH = 16 + 6 + 2 + 1 + 3; // 25 --> 28
parameter OUTPUT_BIT_WIDTH = 16 + 6 + 2 + 2 + 6; // 26 --> 32
parameter ADDER_FLAG_BIT_WIDTH = 3;
input clk;
input [ADDER_FLAG_BIT_WIDTH-1:0] adders_flag_i;
input stage_finish_pipeline_5_i;
input [ACCUMULATOR_BIT_WIDTH-1:0] accumulator_0_i;
input [ACCUMULATOR_BIT_WIDTH-1:0] accumulator_1_i;
input [ACCUMULATOR_BIT_WIDTH-1:0] accumulator_2_i;
input [ACCUMULATOR_BIT_WIDTH-1:0] accumulator_3_i;
output reg [OUTPUT_BIT_WIDTH-1:0] accumulator_o;
wire adder_0_flag;
wire adder_1_flag;
wire adder_2_flag;
assign {adder_0_flag, adder_1_flag, adder_2_flag} = adders_flag_i;
reg [TEMP_BIT_WIDTH-1:0] accumulator_temp_0;
always @(posedge clk) begin
if (stage_finish_pipeline_5_i) begin
if (adder_0_flag) begin
accumulator_temp_0 <= accumulator_0_i + accumulator_1_i;
end else begin
accumulator_temp_0 <= accumulator_0_i;
end
end
end
reg [TEMP_BIT_WIDTH-1:0] accumulator_temp_1;
always @(posedge clk) begin
if (stage_finish_pipeline_5_i) begin
if (adder_1_flag) begin
accumulator_temp_1 <= accumulator_2_i + accumulator_3_i;
end else begin
accumulator_temp_1 <= accumulator_2_i;
end
end
end
reg pipeline_finish;
always @(posedge clk) begin
pipeline_finish <= stage_finish_pipeline_5_i;
end
always @(posedge clk) begin
if (pipeline_finish) begin
if (adder_2_flag) begin
accumulator_o <= {{4{accumulator_temp_0[TEMP_BIT_WIDTH-1]}}, accumulator_temp_0} +
{{4{accumulator_temp_1[TEMP_BIT_WIDTH-1]}},accumulator_temp_1};
end else begin
accumulator_o <= {{4{accumulator_temp_0[TEMP_BIT_WIDTH-1]}}, accumulator_temp_0};
end
end
end
endmodule
| 7.084796
|
module v_multipliers_7a (
clk,
reset,
reset_dv,
ce,
A,
accum,
counter
);
input clk, reset, reset_dv, ce;
input [15:0] A;
output reg [9:0] counter;
output reg [31:0] accum;
always @(posedge clk) begin
if (reset_dv) begin
accum <= 0;
end else if (ce) begin
//if overflow is detected then set to maximum
if (accum > 31'b1111111111111111111111111111111)
accum <= 32'b11111111111111111111111111111111;
else accum <= accum + A;
//if(accum == 0) accum <= old_accum; //if we accum 0 then overwrite it with the previous valid (non-zero) value
end
end
always @(posedge clk) begin
if (reset_dv) begin
counter <= 0;
end else begin
if (ce) counter <= counter + 1;
end
end
//http://stackoverflow.com/questions/7931789/24-bit-counter-state-machine
endmodule
| 6.927674
|
module Accumulator_Ram #(
parameter DATA_WIDTH = 14,
parameter DATA_DEPTH = 256
) (
clk,
arstn,
write_addr_A,
write_data_A,
wvalid_A,
read_addr_A,
read_data_A,
rvalid_A,
dvalid_A,
clear
);
function integer clogb2(input integer bit_depth);
begin
for (clogb2 = 0; bit_depth > 0; clogb2 = clogb2 + 1) bit_depth = bit_depth >> 1;
end
endfunction
localparam ADDRESS_WIDTH = clogb2(DATA_DEPTH - 1);
input clk;
input arstn;
input [ADDRESS_WIDTH-1:0] write_addr_A;
input [DATA_WIDTH-1:0] write_data_A;
input wvalid_A;
input [ADDRESS_WIDTH-1:0] read_addr_A;
output [DATA_WIDTH-1:0] read_data_A;
input rvalid_A;
output dvalid_A;
input clear;
reg [DATA_WIDTH-1:0] rdata_A;
reg dvalid_A_reg;
reg [DATA_WIDTH-1:0] mem[DATA_DEPTH-1:0];
integer i;
assign read_data_A = rdata_A;
assign dvalid_A = dvalid_A_reg;
/* async reset mem */
always @(negedge arstn) begin
if (~arstn) begin
for (i = 0; i < DATA_DEPTH; i = i + 1) begin
mem[i] <= 0;
end
end
end
/* port A: write DATA */
always @(posedge clk) begin
if (wvalid_A & arstn) mem[write_addr_A] <= write_data_A;
end
/* port A: read DATA */
always @(posedge clk or negedge arstn) begin
if (~arstn) begin
rdata_A <= 0;
dvalid_A_reg <= 1'b0;
end else begin
if (rvalid_A) begin
rdata_A <= mem[read_addr_A];
dvalid_A_reg <= 1'b1;
if (clear) mem[read_addr_A] <= 0;
end else begin
dvalid_A_reg <= 1'b0;
end
end
end
endmodule
| 7.58199
|
module accumulator_sw (
input clk,
input reset,
input clear,
input [ (INPUT_WIDTH-1):0] baseband_input,
input ca_bit,
//Accumulator state.
input [(OUTPUT_WIDTH-1):0] accumulator_in,
output reg [(OUTPUT_WIDTH-1):0] accumulator_out
);
parameter INPUT_WIDTH = `INPUT_WIDTH;
localparam INPUT_SIGN = INPUT_WIDTH - 1;
localparam INPUT_MAG_MSB = INPUT_SIGN - 1;
parameter OUTPUT_WIDTH = `INPUT_WIDTH;
//Wipe off C/A code.
wire [(INPUT_WIDTH-1):0] wiped_input;
assign wiped_input[INPUT_SIGN] = baseband_input[INPUT_SIGN] ^ (~ca_bit);
assign wiped_input[INPUT_MAG_MSB:0] = baseband_input[INPUT_MAG_MSB:0];
//Sign-extend value and convert to two's complement.
wire [(OUTPUT_WIDTH-1):0] input2c;
ones_extend #(
.IN_WIDTH (INPUT_WIDTH),
.OUT_WIDTH(OUTPUT_WIDTH)
) input_extend (
.value (wiped_input),
.result(input2c)
);
//Pipe to meet timing.
wire [(OUTPUT_WIDTH-1):0] input2c_km1;
delay #(
.WIDTH(OUTPUT_WIDTH)
) value_delay (
.clk(clk),
.reset(reset),
.in(input2c),
.out(input2c_km1)
);
//Accumulate input value.
always @(*) begin
accumulator_out <= reset ? {OUTPUT_WIDTH{1'b0}} :
clear ? input2c_km1 :
accumulator_in+input2c_km1;
end
endmodule
| 6.706006
|
module accumulator_testbench ();
reg clk = 1'b0;
reg reset = 1'b0;
reg load = 1'b0;
reg [13 : 0] a = 0;
wire [14 : 0] y;
wire overflow;
reg [ 2:0] state = 0;
initial begin
clk = 1'b0;
while (1) begin
#20 clk = ~clk;
end
end
initial begin
#500 reset = 1'b1;
#500 reset = 1'b0;
end
accumulator #(
.IN_WIDTH(14)
) accumulator_instance (
.clk (clk)
, .reset(reset)
, .init(15'd0)
, .load(load)
, .a (a)
, .y (y)
, .overflow(overflow)
);
always @(posedge clk) begin
if (reset == 1'b1) begin
load <= 1'b1;
a <= 0;
state <= 0;
end else begin
if (state == 'd7) begin
state <= 0;
end else begin
state <= state + 1;
end
case (state)
0: begin
load <= 1'b0;
a <= 14'd12;
end
1: begin
load <= 1'b0;
a <= -14'd7;
end
2: begin
load <= 1'b0;
a <= 14'd2;
end
3: begin
load <= 1'b0;
a <= 14'd3;
end
4: begin
load <= 1'b1;
a <= -14'd123;
end
5: begin
load <= 1'b0;
a <= -14'd1;
end
6: begin
load <= 1'b0;
a <= 14'd8190;
end
7: begin
load <= 1'b0;
a <= 14'd8190;
end
endcase
end
end
endmodule
| 6.558156
|
module ACCUM_ADDER (
A,
B,
ADDSUB,
CI,
SUM,
COCAS,
CO
);
//parameter A_width =16;
input [15:0] A;
input [15:0] B;
input ADDSUB;
input CI;
output [15:0] SUM;
output COCAS, CO;
wire CLA16_g, CLA16_p;
reg CO;
wire [15:0] CLA16_SUM;
reg [15:0] CLA16_A, SUM;
integer j;
always @(ADDSUB or COCAS or A or CLA16_SUM) begin
if (ADDSUB) begin
CO = ~COCAS;
for (j = 0; j <= 15; j = j + 1) begin
CLA16_A[j] = ~A[j];
SUM[j] = ~CLA16_SUM[j];
end
end else begin
CO = COCAS;
CLA16_A[15:0] = A[15:0];
SUM[15:0] = CLA16_SUM[15:0];
end
end
// synopsys dc_script_begin
// set_implementation cla CLA16_ADDER
// synopsys dc_script_end
// instantiate DW01_add
/*
DW01_add #(16)
CLA16_ADDER(
.SUM(CLA16_SUM[15:0]),
.A(CLA16_A[15:0]),
.B(B[15:0]),
.CO(COCAS),
.CI(CI)
);
*/
fcla16 CLA16_ADDER (
.Sum(CLA16_SUM[15:0]),
.A (CLA16_A[15:0]),
.B (B[15:0]),
.G (CLA16_g),
.P (CLA16_p),
.Cin(CI)
);
assign COCAS = ~(~CLA16_g & ~(CLA16_p & CI));
endmodule
| 6.680991
|
module decoder_hex_16 (
input [3:0] liczba,
output reg [0:6] H
);
always @(*)
case (liczba)
0: H = 7'b0000001;
1: H = 7'b1001111;
2: H = 7'b0010010;
3: H = 7'b0000110;
4: H = 7'b1001100;
5: H = 7'b0100100;
6: H = 7'b0100000;
7: H = 7'b0001111;
8: H = 7'b0000000;
9: H = 7'b0000100;
10: H = 7'b0001000;
11: H = 7'b1100000;
12: H = 7'b0110001;
13: H = 7'b1000010;
14: H = 7'b0110000;
15: H = 7'b0111000;
default: H = 7'b1111111;
endcase
endmodule
| 7.325232
|
module register_N_bits #(
N = 8
) (
input [N-1:0] D,
input clk,
output reg [N-1:0] Q
);
always @(posedge clk) Q <= D;
endmodule
| 7.990572
|
module adder_N_bits #(
parameter N = 8
) (
input [N-1:0] A,
B,
input cin,
output [N-1:0] S,
output cout
);
assign {cout, S} = A + B + cin;
endmodule
| 7.790948
|
module FFD_posedge (
input D,
clk,
output reg Q
);
always @(posedge clk) Q <= D;
endmodule
| 6.82328
|
module accu10 (
out,
enable_out,
in,
clk,
rst
);
// Module to take a single bit input and turn it into a 10 bit output
input in;
input clk;
input rst;
reg [3:0] counter = 0;
reg [7:0] buffer;
output wire [7:0] out;
reg overflow;
always @(posedge clk or negedge rst) begin
if (counter == 7) begin
out <= buffer;
buffer <= 'b0;
count <= 'b0;
enable_out <= 1;
end else begin
enable_out <= 'b0;
{overflow, buffer} <= out + in;
counter <= counter + 1;
end
end
endmodule
| 6.526687
|
module acc_control (
input clk,
input rst,
output sel,
output en
);
reg [1:0] next_state, curr_state;
parameter s1 = 2'b00;
parameter s2 = 2'b01;
parameter s3 = 2'b10;
parameter s4 = 2'b11;
always @(posedge clk) begin
if (rst) curr_state = s1;
else curr_state = next_state;
end
always @(curr_state) begin
case (curr_state)
s1: next_state = s2;
s2: next_state = s3;
s3: next_state = s4;
s4: next_state = s1;
endcase
end
assign sel = (curr_state == s1) ? 1'b1 : 1'b0;
assign en = (curr_state == s4) ? 1'b1 : 1'b0;
endmodule
| 6.665368
|
module ACC_COUNTER #(
// Parameter
parameter PE_SIZE = 14,
parameter WEIGHT_ROW_NUM = 70,
parameter WEIGHT_COL_NUM = 294
) (
// Port
// Special Input
input clk,
input rst_n,
// Control Input
input psum_en_i,
// Valid Output
output ofmap_valid_o,
output fifo_rst_n_o
);
// Local parameter
localparam PSUM_CNT_NUM = WEIGHT_ROW_NUM; // 70
localparam PSUM_CNT_WIDTH = $clog2(PSUM_CNT_NUM); // 7
localparam ACC_CNT_NUM = WEIGHT_COL_NUM / PE_SIZE; // 294 / 14 = 21
localparam ACC_CNT_WIDTH = $clog2(ACC_CNT_NUM); // 5
// 1. Partial Sum Counter
reg [PSUM_CNT_WIDTH-1:0] psum_cnt, psum_cnt_n;
// 1-1) Psum counter seq logic
always @(posedge clk, negedge rst_n) begin
if (!rst_n) begin
psum_cnt <= {(PSUM_CNT_WIDTH) {1'b0}};
end else begin
psum_cnt <= psum_cnt_n;
end
end
// 1-2) Psum counter comb logic
always @(*) begin
if (psum_cnt == PSUM_CNT_NUM) begin
psum_cnt_n = 0;
end else if (psum_en_i) begin
psum_cnt_n = psum_cnt + 'd1;
end else begin
psum_cnt_n = psum_cnt; // maintain
end
end
// 1-3) generate acc counter enable signal by using psum counter
wire psum_cnt_done;
assign psum_cnt_done = (psum_cnt == PSUM_CNT_NUM);
// 2. Accumulation Counter
reg [ACC_CNT_WIDTH-1:0] acc_cnt, acc_cnt_n;
// 2-1) Accumulation counter seq logic
always @(posedge clk, negedge rst_n) begin
if (!rst_n) begin
acc_cnt <= {(ACC_CNT_WIDTH) {1'b0}};
end else begin
acc_cnt <= acc_cnt_n;
end
end
// 2-2) Accumulation counter comb logic
always @(*) begin
if (psum_cnt_done) begin
if (acc_cnt == ACC_CNT_NUM - 1) begin
acc_cnt_n = 'd0;
end else begin
acc_cnt_n = acc_cnt + 'd1;
end
end else begin
acc_cnt_n = acc_cnt; // maintain
end
end
// 2-3) output assignment
assign ofmap_valid_o = (acc_cnt==ACC_CNT_NUM-1) & psum_en_i & (!psum_cnt_done); // ex. acc_cnt = 20, psum_en_i come
assign fifo_rst_n_o = (acc_cnt==ACC_CNT_NUM-1) & psum_cnt_done; // last valid ofmap timing high
endmodule
| 7.396743
|
module ACC_COUNTER_TB #(
// Parameter
parameter PE_SIZE = 14,
parameter WEIGHT_ROW_NUM = 70,
parameter WEIGHT_COL_NUM = 294
) (
// No Port
// This is TB
);
reg clk;
reg rst_n;
reg psum_en_i;
wire ofmap_valid_o;
wire fifo_rst_n_o;
// DUT INST
ACC_COUNTER #(
.PE_SIZE (PE_SIZE),
.WEIGHT_ROW_NUM(WEIGHT_ROW_NUM),
.WEIGHT_COL_NUM(WEIGHT_COL_NUM)
) u_ACC_COUNTER (
.clk (clk),
.rst_n (rst_n),
.psum_en_i (psum_en_i),
.ofmap_valid_o(ofmap_valid_o),
.fifo_rst_n_o (fifo_rst_n_o)
);
// clock signal
initial begin
clk = 1'b0;
forever begin
#(`CLOCK_PERIOD / 2) clk = ~clk;
end
end
integer i;
integer j;
// Stimulus
initial begin
// 0. Initialize
rst_n = 1'b1;
psum_en_i = 1'b0;
// 1. Reset
@(posedge clk);
#(`DELTA) rst_n = 1'b0;
@(posedge clk);
#(`DELTA) rst_n = 1'b1;
// 2. Psum Counting & ACC Counting
for (i = 0; i < (WEIGHT_COL_NUM / PE_SIZE) + 3; i = i + 1) begin
// Ifmap preload
repeat (14) begin
@(posedge clk);
#(`DELTA) psum_en_i = 1'b0;
end
// Weight
for (j = 0; j < WEIGHT_ROW_NUM; j = j + 1) begin
@(posedge clk);
#(`DELTA) psum_en_i = 1'b1;
end
end
// 3. check valid
repeat (10) begin
@(posedge clk);
#(`DELTA) psum_en_i = 1'b0;
end
end
endmodule
| 6.98246
|
module acc_data_reorder_top #(
parameter BANDWIDTH = 512,
BITWIDTH = 32
) (
input clk_calc,
input rst_n,
//////////acc_data//////////
input data_in_vld,
input wire [BITWIDTH*16-1:0] data_in,
output wire net_map_finish,
//////////last_slice_reorder_valid_of_each_layer//////////
output wire last_slice_vld,
output wire calc_res_vld,
output wire [BITWIDTH*16-1:0] calc_res,
output wire data_map_ins_vld,
output wire [BITWIDTH*16+26+7+1-1:0] data_map_ins
);
addr_map addr_map (
.clk_calc (clk_calc),
.rst_n (rst_n),
.data_in (data_in),
.data_in_vld (data_in_vld),
.net_all_finish(net_map_finish),
.last_slice_vld(last_slice_vld),
.calc_res_vld (calc_res_vld),
.calc_res (calc_res),
.ddr_wr_ins_vld(data_map_ins_vld),
.ddr_wr_ins (data_map_ins)
);
endmodule
| 7.93827
|
module acc_register (
clk,
rst,
acc_in,
acc_write,
acc_out
);
input wire clk, rst, acc_write;
input wire [15:0] acc_in;
output reg [15:0] acc_out;
always @(posedge clk) begin
if (rst) acc_out = 13'b0;
else if (acc_write) acc_out = acc_in;
end
endmodule
| 6.990549
|
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