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module acc_shift_i (
output wire mob8,
output wire [3:0] x, // Gating EMFs to ASU II. x[0] corresponds to x1 of original logic, x[1] to x2 and so on.
input wire clk,
input wire g5, // Accumulator shifting gate.
input wire c7, // Right shift.
input wire c8, // Left shift.
input wire acc,
input wire g13,
input wire c19, // Store instructions T, U.
input wire d17,
input wire d35,
input wire f1_neg
);
wire tmp;
assign x[0] = g5 & c7;
assign x[1] = ~x[0];
assign x[2] = ~x[3];
assign x[3] = g5 & c8;
assign tmp = (f1_neg & d17) | d35;
assign mob8 = g13 & acc & c19 & ~tmp & clk;
endmodule
| 7.705233
|
module acc_shift_ii (
output wire adder_a,
input wire clk,
input wire acc1,
input wire [3:0] x // Gating EMFs from ASU I. x[0] corresponds to x1 of original logic, x[1] to x2 and so on.
);
wire in_dl1;
wire in_dl2;
wire in_dl3;
wire out_dl1;
wire out_dl2;
wire out_dl3;
wire or1;
delay #(
.INTERVAL(1)
) d1 (
.out(out_dl1),
.clk(clk),
.in (in_dl1)
);
delay #(
.INTERVAL(1)
) d2 (
.out(out_dl2),
.clk(clk),
.in (in_dl2)
);
delay #(
.INTERVAL(1)
) d3 (
.out(out_dl3),
.clk(clk),
.in (in_dl3)
);
assign in_dl1 = acc1 & x[1];
assign or1 = (x[0] & acc1) | (out_dl1 & clk);
assign in_dl2 = x[3] & or1;
assign in_dl3 = (x[2] & or1) | (out_dl2 & clk);
assign adder_a = out_dl3 & clk;
endmodule
| 7.183291
|
module acc_stage #(
parameter DATA_SIZE = 16
) (
input clk,
input rst,
input rst_sync,
input done_mul,
input [DATA_SIZE-1:0] data,
output [DATA_SIZE-1:0] out_data,
output overflow
);
wire rst_new;
PosEdgeDFF delay_cycle (
clk,
rst,
rst_sync,
1'b1,
rst_new
);
ACCUMULATOR_EULAR #(DATA_SIZE) accumulator (
clk,
rst_new | rst,
data,
out_data,
overflow
);
endmodule
| 6.716321
|
module acc_step_gen (
input clk,
input reset,
input [31:0] dt_val,
input [31:0] steps_val,
input load,
output reg [31:0] steps,
output reg [31:0] dt,
output reg stopped,
output reg step_stb, // combinatorial!
output reg done // combinatorial!
);
reg [31:0] dt_limit;
reg [31:0] steps_limit;
reg [31:0] next_dt;
reg [31:0] next_steps;
reg next_stopped;
always @(posedge clk) begin
if (reset) begin
dt_limit <= 0;
steps_limit <= 0;
end else if (load) begin
dt_limit <= dt_val;
steps_limit <= steps_val;
end
end
always @(load, dt_limit, steps_limit, steps, dt, reset, stopped) begin
if (reset) begin
next_steps <= 0;
next_dt <= 0;
next_stopped <= 1;
end else if (load) begin
next_steps <= 0;
next_dt <= 0;
next_stopped <= 0;
end else if (stopped) begin
next_steps <= 0;
next_dt <= 0;
next_stopped <= 1;
end else begin
next_steps <= steps;
next_dt <= dt + 1;
next_stopped <= 0;
if (dt >= dt_limit - 1) begin
next_dt <= 0;
next_steps <= steps + 1;
if (steps >= steps_limit - 1) begin
next_stopped <= 1;
end
end
end
end
always @(dt_limit, steps_limit, steps, dt, reset, stopped) begin
if (reset) begin
done <= #3 0;
step_stb <= #3 0;
end else if (stopped) begin
done <= #3 0;
step_stb <= #3 0;
end else begin
done <= #3 0;
step_stb <= #3 0;
if (dt >= dt_limit - 1) begin
step_stb <= #3 1;
if (steps >= steps_limit - 1) begin
done <= #3 1;
end
end
end
end
always @(posedge clk) begin
dt <= next_dt;
steps <= next_steps;
stopped <= next_stopped;
end
endmodule
| 7.441427
|
module Acc_Sum (
input clk,
rst,
input ena,
input [16:0] a,
input [16:0] a_d,
output signed [23:0] sum_out
);
reg [23:0] sum_reg;
reg [16:0] ia, ia_d;
wire signed [17:0] delay_sub = $signed({1'b0, ia}) - $signed({1'b0, ia_d});
wire signed [23:0] mov_sum = $signed(sum_reg) + $signed({{6{delay_sub[17]}}, delay_sub});
always @(posedge clk) begin
if (rst) begin
ia <= 17'd0;
ia_d <= 17'd0;
end else if (ena) begin
ia <= a;
ia_d <= a_d;
end
end
always @(posedge clk) begin
if (rst) sum_reg <= 24'd0;
else if (ena) sum_reg <= mov_sum;
end
assign sum_out = mov_sum;
endmodule
| 6.687492
|
module ACC_TB #(
// Parameter
parameter PE_SIZE = 4,
parameter DATA_WIDTH = 32,
parameter FIFO_DEPTH = 4
) (
// No Port
// This is TB
);
// Special input
reg clk;
reg rst_n;
// R/W enable signal
reg [ PE_SIZE-1:0] psum_en_i; // signal from SA, used for fifo write signal
reg [ PE_SIZE-1:0] rden_i; // signal from Top control, read data from fifo to GLB
// I/O data
reg [DATA_WIDTH*PE_SIZE-1:0] psum_row_i;
wire [DATA_WIDTH*PE_SIZE-1:0] psum_row_o;
ACC #(
.PE_SIZE (4),
.DATA_WIDTH(32),
.FIFO_DEPTH(4)
) ACC_INST (
.clk (clk),
.rst_n (rst_n),
.psum_en_i (psum_en_i),
.rden_i (rden_i),
.psum_row_i(psum_row_i),
.psum_row_o(psum_row_o)
);
// Clock Signal
initial begin
clk = 1'b0;
forever begin
#(`CLOCK_PERIOD / 2) clk = ~clk;
end
end
integer cycle;
// Initialization
initial begin
cycle = 0;
rst_n = 1'b1;
psum_en_i = {(PE_SIZE) {1'b0}};
rden_i = {(PE_SIZE) {1'b0}};
psum_row_i = {(DATA_WIDTH * PE_SIZE) {1'b0}};
end
/*
Test strategy
1. Reset module
2. give psum enable and psum value 4line -> psum preload(not full)
3. give psum enable and psum value 4line * 3times -> accumulation(full)
4. give rden signal and check fifo reading activation
*/
// Stimulus
initial begin
// 1. RESET
#(`DELTA) rst_n = 1'b0;
@(posedge clk);
cycle = cycle + 1;
#(`DELTA) rst_n = 1'b1;
// 2. Psum preload
// 2-1) psum row1
@(posedge clk);
cycle = cycle + 1;
#(`DELTA) psum_en_i = 4'b1111;
psum_row_i = 'h00000001_00000002_00000003_00000004;
// 2-2) psum row2
@(posedge clk);
cycle = cycle + 1;
#(`DELTA) psum_en_i = 4'b1111;
psum_row_i = 'h00000002_00000003_00000004_00000005;
// 2-3) psum row3
@(posedge clk);
cycle = cycle + 1;
#(`DELTA) psum_en_i = 4'b1111;
psum_row_i = 'h00000003_00000004_00000005_00000006;
// 2-4) psum row4
@(posedge clk);
cycle = cycle + 1;
#(`DELTA) psum_en_i = 4'b1111;
psum_row_i = 'h00000004_00000005_00000006_00000007;
// 3. Accumulation
repeat (3) begin
@(posedge clk);
cycle = cycle + 1;
#(`DELTA) psum_en_i = 4'b1111;
psum_row_i = 'h00000010_00000010_00000010_00000010;
@(posedge clk);
cycle = cycle + 1;
#(`DELTA) psum_en_i = 4'b1111;
psum_row_i = 'h00000100_00000100_00000100_00000100;
@(posedge clk);
cycle = cycle + 1;
#(`DELTA) psum_en_i = 4'b1111;
psum_row_i = 'h00001000_00001000_00001000_00001000;
@(posedge clk);
cycle = cycle + 1;
#(`DELTA) psum_en_i = 4'b1111;
psum_row_i = 'h00010000_00010000_00010000_00010000;
end
// 4. Rden give for checking value
repeat (4) begin
@(posedge clk);
#(`DELTA) psum_en_i = 4'b0000;
cycle = cycle + 1;
#(`DELTA) rden_i = 4'b1111;
end
// 5. Waiting Activation
repeat (4) begin
@(posedge clk);
psum_en_i = 4'b0000;
#(`DELTA) rden_i = 4'b0000;
cycle = cycle + 1;
end
end
endmodule
| 7.645764
|
module aceito (
caracter,
len_string,
counter_caracter
);
output [3:0] caracter, len_string;
input [3:0] counter_caracter;
wire [3:0] multiplexer_out, len_string, A, C, E, I, T, O;
Multiplexer6 #(4) multiplex (
multiplexer_out,
A,
C,
E,
I,
T,
O,
counter_caracter
);
assign caracter = multiplexer_out;
assign len_string = 4'b0101;
assign A = 4'b0000;
assign C = 4'b0001;
assign E = 4'b0011;
assign I = 4'b0100;
assign T = 4'b1010;
assign O = 4'b0111;
endmodule
| 7.213203
|
module aceusb (
/* WISHBONE interface */
input sys_clk,
input sys_rst,
input [31:0] wb_adr_i,
input [31:0] wb_dat_i,
output [31:0] wb_dat_o,
input wb_cyc_i,
input wb_stb_i,
input wb_we_i,
output reg wb_ack_o,
/* Signals shared between SystemACE and USB */
output [6:0] aceusb_a,
inout [15:0] aceusb_d,
output aceusb_oe_n,
output aceusb_we_n,
/* SystemACE signals */
input ace_clkin,
output ace_mpce_n,
input ace_mpirq,
output usb_cs_n,
output usb_hpi_reset_n,
input usb_hpi_int
);
wire access_read1;
wire access_write1;
wire access_ack1;
/* Avoid potential glitches by sampling wb_adr_i and wb_dat_i only at the appropriate time */
reg load_adr_dat;
reg [5:0] address_reg;
reg [15:0] data_reg;
always @(posedge sys_clk) begin
if (load_adr_dat) begin
address_reg <= wb_adr_i[7:2];
data_reg <= wb_dat_i[15:0];
end
end
aceusb_access access (
.ace_clkin(ace_clkin),
.rst(sys_rst),
.a(address_reg),
.di(data_reg),
.do(wb_dat_o[15:0]),
.read(access_read1),
.write(access_write1),
.ack(access_ack1),
.aceusb_a(aceusb_a),
.aceusb_d(aceusb_d),
.aceusb_oe_n(aceusb_oe_n),
.aceusb_we_n(aceusb_we_n),
.ace_mpce_n(ace_mpce_n),
.ace_mpirq(ace_mpirq),
.usb_cs_n(usb_cs_n),
.usb_hpi_reset_n(usb_hpi_reset_n),
.usb_hpi_int(usb_hpi_int)
);
assign wb_dat_o[31:16] = 16'h0000;
/* Synchronize read, write and acknowledgement pulses */
reg access_read;
reg access_write;
wire access_ack;
aceusb_sync sync_read (
.clk0 (sys_clk),
.flagi(access_read),
.clk1 (ace_clkin),
.flago(access_read1)
);
aceusb_sync sync_write (
.clk0 (sys_clk),
.flagi(access_write),
.clk1 (ace_clkin),
.flago(access_write1)
);
aceusb_sync sync_ack (
.clk0 (ace_clkin),
.flagi(access_ack1),
.clk1 (sys_clk),
.flago(access_ack)
);
/* Main FSM */
reg state;
reg next_state;
parameter IDLE = 1'd0;
parameter WAIT = 1'd1;
always @(posedge sys_clk) begin
if (sys_rst) state <= IDLE;
else state <= next_state;
end
always @(*) begin
load_adr_dat = 1'b0;
wb_ack_o = 1'b0;
access_read = 1'b0;
access_write = 1'b0;
next_state = state;
case (state)
IDLE: begin
if (wb_cyc_i & wb_stb_i) begin
load_adr_dat = 1'b1;
if (wb_we_i) access_write = 1'b1;
else access_read = 1'b1;
next_state = WAIT;
end
end
WAIT: begin
if (access_ack) begin
wb_ack_o = 1'b1;
next_state = IDLE;
end
end
endcase
end
endmodule
| 8.265793
|
module aceusb_access(
/* Control */
input ace_clkin,
input rst,
input [5:0] a,
input [15:0] di,
output reg [15:0] do,
input read,
input write,
output reg ack,
/* SystemACE/USB interface */
output [6:0] aceusb_a,
inout [15:0] aceusb_d,
output reg aceusb_oe_n,
output reg aceusb_we_n,
output reg ace_mpce_n,
input ace_mpirq,
output usb_cs_n,
output usb_hpi_reset_n,
input usb_hpi_int
);
/* USB is not supported yet. Disable the chip. */
assign usb_cs_n = 1'b1;
assign usb_hpi_reset_n = 1'b1;
/* 16-bit mode only */
assign aceusb_a = {a, 1'b0};
reg d_drive;
assign aceusb_d = d_drive ? di : 16'hzz;
reg d_drive_r;
reg aceusb_oe_n_r;
reg aceusb_we_n_r;
reg ace_mpce_n_r;
always @(posedge ace_clkin) begin
d_drive <= d_drive_r;
aceusb_oe_n <= aceusb_oe_n_r;
aceusb_we_n <= aceusb_we_n_r;
ace_mpce_n <= ace_mpce_n_r;
end
reg d_in_sample;
always @(posedge ace_clkin)
if(d_in_sample)
do <= aceusb_d;
reg [2:0] state;
reg [2:0] next_state;
localparam
IDLE = 3'd0,
READ = 3'd1,
READ1 = 3'd2,
READ2 = 3'd3,
WRITE = 3'd4,
ACK = 3'd5;
always @(posedge ace_clkin) begin
if(rst)
state <= IDLE;
else
state <= next_state;
end
always @(*) begin
d_drive_r = 1'b0;
aceusb_oe_n_r = 1'b1;
aceusb_we_n_r = 1'b1;
ace_mpce_n_r = 1'b1;
d_in_sample = 1'b0;
ack = 1'b0;
next_state = state;
case(state)
IDLE: begin
if(read) begin
ace_mpce_n_r = 1'b0;
next_state = READ;
end
if(write) begin
ace_mpce_n_r = 1'b0;
next_state = WRITE;
end
end
READ: begin
ace_mpce_n_r = 1'b0;
next_state = READ1;
end
READ1: begin
ace_mpce_n_r = 1'b0;
aceusb_oe_n_r = 1'b0;
next_state = READ2;
end
READ2: begin
d_in_sample = 1'b1;
next_state = ACK;
end
WRITE: begin
d_drive_r = 1'b1;
ace_mpce_n_r = 1'b0;
aceusb_we_n_r = 1'b0;
next_state = ACK;
end
ACK: begin
ack = 1'b1;
next_state = IDLE;
end
endcase
end
endmodule
| 6.606503
|
module aceusb_sync (
input clk0,
input flagi,
input clk1,
output flago
);
/* Turn the flag into a level change */
reg toggle;
initial toggle = 1'b0;
always @(posedge clk0) if (flagi) toggle <= ~toggle;
/* Synchronize the level change to clk1.
* We add a third flip-flop to be able to detect level changes. */
reg [2:0] sync;
initial sync = 3'b000;
always @(posedge clk1) sync <= {sync[1:0], toggle};
/* Recreate the flag from the level change into the clk1 domain */
assign flago = sync[2] ^ sync[1];
endmodule
| 7.594977
|
module ace_ac_reg_slice (
acreadys,
acvalidm,
acaddrm,
acprotm,
acsnoopm,
aclk,
aresetn,
acvalids,
acaddrs,
acprots,
acsnoops,
acreadym
);
parameter AC_ADDR_WIDTH = 32;
parameter HNDSHK_MODE = `AXI_RS_FULL;
localparam PAYLD_WIDTH = AC_ADDR_WIDTH + 7;
input aclk;
input aresetn;
output acvalids;
input acreadys;
output [AC_ADDR_WIDTH-1:0] acaddrs;
output [2:0] acprots;
output [3:0] acsnoops;
input acvalidm;
output acreadym;
input [AC_ADDR_WIDTH-1:0] acaddrm;
input [2:0] acprotm;
input [3:0] acsnoopm;
wire valid_src;
wire ready_src;
wire [PAYLD_WIDTH-1:0] payload_src;
wire valid_dst;
wire ready_dst;
wire [PAYLD_WIDTH-1:0] payload_dst;
assign valid_src = acvalidm;
assign payload_src = {acaddrm, acprotm, acsnoopm};
assign acreadym = ready_src;
assign acvalids = valid_dst;
assign {acaddrs, acprots, acsnoops} = payload_dst;
assign ready_dst = acreadys;
axi_channel_reg_slice #(
.PAYLD_WIDTH(PAYLD_WIDTH),
.HNDSHK_MODE(HNDSHK_MODE)
) reg_slice (
.ready_src (ready_src),
.valid_dst (valid_dst),
.payload_dst(payload_dst[PAYLD_WIDTH-1:0]),
.aclk (aclk),
.aresetn (aresetn),
.valid_src (valid_src),
.payload_src(payload_src[PAYLD_WIDTH-1:0]),
.ready_dst (ready_dst)
);
endmodule
| 6.649601
|
module ace_ax_reg_slice (
axreadys,
axvalidm,
axidm,
axaddrm,
axlenm,
axsizem,
axburstm,
axlockm,
axcachem,
axprotm,
axregionm,
axqosm,
axuserm,
axbarm,
axdomainm,
axsnoopm,
awuniquem,
aclk,
aresetn,
axvalids,
axids,
axaddrs,
axlens,
axsizes,
axbursts,
axlocks,
axcaches,
axprots,
axregions,
axqoss,
axusers,
axbars,
axdomains,
axsnoops,
awuniques,
axreadym
);
parameter ADDR_WIDTH = 32;
parameter ID_WIDTH = 4;
parameter USER_WIDTH = 1;
parameter HNDSHK_MODE = `AXI_RS_FULL;
parameter SNOOP_WIDTH = 3;
localparam PAYLD_WIDTH = ID_WIDTH + ADDR_WIDTH + USER_WIDTH + SNOOP_WIDTH + 34;
input aclk;
input aresetn;
input axvalids;
output axreadys;
input [ID_WIDTH-1:0] axids;
input [ADDR_WIDTH-1:0] axaddrs;
input [7:0] axlens;
input [2:0] axsizes;
input [1:0] axbursts;
input axlocks;
input [3:0] axcaches;
input [2:0] axprots;
input [3:0] axregions;
input [3:0] axqoss;
input [USER_WIDTH-1:0] axusers;
input [1:0] axbars;
input [1:0] axdomains;
input [SNOOP_WIDTH-1:0] axsnoops;
input awuniques;
output axvalidm;
input axreadym;
output [ID_WIDTH-1:0] axidm;
output [ADDR_WIDTH-1:0] axaddrm;
output [7:0] axlenm;
output [2:0] axsizem;
output [1:0] axburstm;
output axlockm;
output [3:0] axcachem;
output [2:0] axprotm;
output [3:0] axregionm;
output [3:0] axqosm;
output [USER_WIDTH-1:0] axuserm;
output [1:0] axbarm;
output [1:0] axdomainm;
output [SNOOP_WIDTH-1:0] axsnoopm;
output awuniquem;
wire valid_src;
wire ready_src;
wire [PAYLD_WIDTH-1:0] payload_src;
wire valid_dst;
wire ready_dst;
wire [PAYLD_WIDTH-1:0] payload_dst;
assign valid_src = axvalids;
assign payload_src = {
axids,
axaddrs,
axlens,
axsizes,
axbursts,
axlocks,
axcaches,
axprots,
axregions,
axqoss,
axusers,
axbars,
axdomains,
axsnoops,
awuniques
};
assign axreadys = ready_src;
assign axvalidm = valid_dst;
assign {axidm,
axaddrm,
axlenm,
axsizem,
axburstm,
axlockm,
axcachem,
axprotm,
axregionm,
axqosm,
axuserm,
axbarm,
axdomainm,
axsnoopm,
awuniquem} = payload_dst;
assign ready_dst = axreadym;
axi_channel_reg_slice #(
.PAYLD_WIDTH(PAYLD_WIDTH),
.HNDSHK_MODE(HNDSHK_MODE)
) reg_slice (
.ready_src (ready_src),
.valid_dst (valid_dst),
.payload_dst(payload_dst[PAYLD_WIDTH-1:0]),
.aclk (aclk),
.aresetn (aresetn),
.valid_src (valid_src),
.payload_src(payload_src[PAYLD_WIDTH-1:0]),
.ready_dst (ready_dst)
);
endmodule
| 7.2488
|
module ace_cd_reg_slice (
cdreadys,
cdvalidm,
cddatam,
cdlastm,
aclk,
aresetn,
cdvalids,
cddatas,
cdlasts,
cdreadym
);
parameter CD_DATA_WIDTH = 32;
parameter HNDSHK_MODE = `AXI_RS_FULL;
localparam PAYLD_WIDTH = CD_DATA_WIDTH + 1;
input aclk;
input aresetn;
input cdvalids;
output cdreadys;
input [CD_DATA_WIDTH-1:0] cddatas;
input cdlasts;
output cdvalidm;
input cdreadym;
output [CD_DATA_WIDTH-1:0] cddatam;
output cdlastm;
wire valid_src;
wire ready_src;
wire [PAYLD_WIDTH-1:0] payload_src;
wire valid_dst;
wire ready_dst;
wire [PAYLD_WIDTH-1:0] payload_dst;
assign valid_src = cdvalids;
assign payload_src = {cddatas, cdlasts};
assign cdreadys = ready_src;
assign cdvalidm = valid_dst;
assign {cddatam, cdlastm} = payload_dst;
assign ready_dst = cdreadym;
axi_channel_reg_slice #(
.PAYLD_WIDTH(PAYLD_WIDTH),
.HNDSHK_MODE(HNDSHK_MODE)
) reg_slice (
.ready_src (ready_src),
.valid_dst (valid_dst),
.payload_dst(payload_dst[PAYLD_WIDTH-1:0]),
.aclk (aclk),
.aresetn (aresetn),
.valid_src (valid_src),
.payload_src(payload_src[PAYLD_WIDTH-1:0]),
.ready_dst (ready_dst)
);
endmodule
| 7.199401
|
module ace_r_reg_slice (
rvalids,
rids,
rdatas,
rresps,
rlasts,
rusers,
rreadym,
aclk,
aresetn,
rreadys,
rvalidm,
ridm,
rdatam,
rrespm,
rlastm,
ruserm
);
parameter DATA_WIDTH = 32;
parameter ID_WIDTH = 4;
parameter USER_WIDTH = 1;
parameter HNDSHK_MODE = `AXI_RS_FULL;
localparam PAYLD_WIDTH = ID_WIDTH + DATA_WIDTH + USER_WIDTH + 5;
input aclk;
input aresetn;
output rvalids;
input rreadys;
output [ID_WIDTH-1:0] rids;
output [DATA_WIDTH-1:0] rdatas;
output [3:0] rresps;
output rlasts;
output [USER_WIDTH-1:0] rusers;
input rvalidm;
output rreadym;
input [ID_WIDTH-1:0] ridm;
input [DATA_WIDTH-1:0] rdatam;
input [3:0] rrespm;
input rlastm;
input [USER_WIDTH-1:0] ruserm;
wire valid_src;
wire ready_src;
wire [PAYLD_WIDTH-1:0] payload_src;
wire valid_dst;
wire ready_dst;
wire [PAYLD_WIDTH-1:0] payload_dst;
assign valid_src = rvalidm;
assign rreadym = ready_src;
assign payload_src = {ridm, rdatam, rrespm, rlastm, ruserm};
assign rvalids = valid_dst;
assign ready_dst = rreadys;
assign {rids, rdatas, rresps, rlasts, rusers} = payload_dst;
axi_channel_reg_slice #(
.PAYLD_WIDTH(PAYLD_WIDTH),
.HNDSHK_MODE(HNDSHK_MODE)
) reg_slice (
.ready_src (ready_src),
.valid_dst (valid_dst),
.payload_dst(payload_dst[PAYLD_WIDTH-1:0]),
.aclk (aclk),
.aresetn (aresetn),
.valid_src (valid_src),
.payload_src(payload_src[PAYLD_WIDTH-1:0]),
.ready_dst (ready_dst)
);
endmodule
| 7.806625
|
module ACFDivider (
input wire iClock,
input wire iEnable,
input wire iReset,
input wire [63:0] iACF,
input wire iValid,
output wire [31:0] ofACF,
output wire oValid
);
parameter ORDER = 12;
parameter DIVIDER_DELAY = 14;
parameter CONVERTER_DELAY = 7;
wire [31:0] one = 32'h3f800000;
reg first;
reg [63:0] integer_data;
reg [31:0] numerator, denominator;
wire [31:0] floating_data;
wire [31:0] result;
reg div_en, conv_en, div_valid, first_valid;
reg [31:0] dividend;
reg [3:0] div_count;
reg [CONVERTER_DELAY:0] conv_delay;
reg [DIVIDER_DELAY:0] div_delay;
wire converter_valid = conv_delay[CONVERTER_DELAY-1];
wire divider_valid = div_delay[DIVIDER_DELAY];
assign oValid = divider_valid | first_valid;
assign ofACF = dividend;
fp_convert conv (
.clk_en(conv_en),
.clock (iClock),
.dataa (integer_data),
.result(floating_data)
);
fp_divider div (
.clk_en(div_en),
.clock (iClock),
.dataa (numerator),
.datab (denominator),
.result(result)
);
always @(posedge iClock) begin
if (iReset) begin
conv_delay <= 0;
numerator <= 0;
denominator <= 1;
integer_data <= 0;
first_valid <= 0;
dividend <= 0;
div_delay <= 0;
conv_delay <= 0;
div_valid <= 0;
div_count <= 0;
div_en <= 0;
conv_en <= 0;
first <= 1;
end else if (iEnable) begin
conv_delay <= conv_delay << 1 | iValid;
div_delay <= div_delay << 1 | div_valid;
dividend <= result;
first_valid <= 0;
if (iValid) begin
conv_en <= 1;
integer_data <= iACF;
end
if (converter_valid) begin
if (first) begin
denominator <= floating_data;
dividend <= 32'h3f800000;
first_valid <= 1;
first <= 0;
end else begin
numerator <= floating_data;
div_en <= 1;
div_valid <= 1;
end
end
if (div_en) begin
div_count <= div_count + 1;
end
if (div_count == ORDER - 1) begin
div_valid <= 0;
end
if (div_count == ORDER - 1 + DIVIDER_DELAY) begin
div_en <= 0;
end
end
end
endmodule
| 6.726101
|
module ACFDividerTB;
reg clk, ena, rst;
reg signed [15:0] sample;
integer infile, i, cycles;
wire [31:0] facf;
wire fvalid;
wire [42:0] acf;
wire valid;
GenerateAutocorrelationSums ga (
.iClock (clk),
.iEnable(ena),
.iReset (rst),
.iSample(sample),
.oACF (acf),
.oValid(valid)
);
ACFDivider div (
.iClock (clk),
.iEnable(ena),
.iReset (rst),
.iACF (acf),
.iValid(valid),
.ofACF (facf),
.oValid(fvalid)
);
always begin
#0 clk = 0;
#10 clk = 1;
cycles <= cycles + 1;
#10;
end
always @(posedge clk) begin
if (fvalid) $display("%f", `DFP(facf));
end
initial begin
ena = 0;
rst = 1;
cycles = 0;
// Fill the internal sample RAM
infile = $fopen("Pavane16Blocks.txt", "r");
/* skip the first block...
for (i = 0; i < 4096; i = i + 1) begin
$fscanf(infile, "%d\n", sample);
end*/
#30;
ena = 1;
rst = 0;
for (i = 0; i < 4096; i = i + 1) begin
$fscanf(infile, "%d\n", sample);
#20;
end
/*
for (i = 0; i < 4096; i = i + 1) begin
$fscanf(infile, "%d\n", sample);
#20;
end*/
/* Step 2 - Division */
ena = 1;
rst = 0;
for (i = 0; i < 60; i = i + 1) begin
#20;
end
$stop;
end
endmodule
| 6.650239
|
module ACF_AXI_v1_0 #(
// Users to add parameters here
parameter BIN_SIZE = 8,
parameter NUM_BINS = 20,
parameter CNTR_SIZE = 32,
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 4
) (
// Users to add ports here
input wire CE,
input wire CH_In,
input wire initTX,
input wire [CNTR_SIZE-1:0] presentTime,
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S00_AXI
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
input wire [2 : 0] s00_axi_awprot,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [1 : 0] s00_axi_bresp,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
input wire [2 : 0] s00_axi_arprot,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
output wire [1 : 0] s00_axi_rresp,
output wire s00_axi_rvalid,
input wire s00_axi_rready
);
reg [NUM_BINS+33-1:0] acfEl = 0;
reg wrEn = 0;
// Instantiation of Axi Bus Interface S00_AXI
ACF_AXI_v1_0_S00_AXI #(
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH),
.NUM_BINS(NUM_BINS)
) ACF_AXI_v1_0_S00_AXI_inst (
.acfEl(acfEl),
.wrEn(wrEn),
.S_AXI_ACLK(s00_axi_aclk),
.S_AXI_ARESETN(s00_axi_aresetn),
.S_AXI_AWADDR(s00_axi_awaddr),
.S_AXI_AWPROT(s00_axi_awprot),
.S_AXI_AWVALID(s00_axi_awvalid),
.S_AXI_AWREADY(s00_axi_awready),
.S_AXI_WDATA(s00_axi_wdata),
.S_AXI_WSTRB(s00_axi_wstrb),
.S_AXI_WVALID(s00_axi_wvalid),
.S_AXI_WREADY(s00_axi_wready),
.S_AXI_BRESP(s00_axi_bresp),
.S_AXI_BVALID(s00_axi_bvalid),
.S_AXI_BREADY(s00_axi_bready),
.S_AXI_ARADDR(s00_axi_araddr),
.S_AXI_ARPROT(s00_axi_arprot),
.S_AXI_ARVALID(s00_axi_arvalid),
.S_AXI_ARREADY(s00_axi_arready),
.S_AXI_RDATA(s00_axi_rdata),
.S_AXI_RRESP(s00_axi_rresp),
.S_AXI_RVALID(s00_axi_rvalid),
.S_AXI_RREADY(s00_axi_rready)
);
// Add user logic here
always @(posedge s00_axi_aclk) begin
acfEl <= 8'h37 & {NUM_BINS + 33{CE}};
end
// User logic ends
endmodule
| 6.828937
|
module acia (
input clk, // system clock
input rst, // system reset
input cs, // chip select
input we, // write enable
input rs, // register select
input rx, // serial receive
input [7:0] din, // data bus input
output reg [7:0] dout, // data bus output
output tx, // serial tx_start
output irq // high-true interrupt request
);
// hard-coded bit-rate
localparam sym_rate = 115200;
localparam clk_freq = 24000000;
localparam sym_cnt = clk_freq / sym_rate;
localparam SCW = $clog2(sym_cnt);
wire [SCW-1:0] sym_cntr = sym_cnt;
// generate tx_start signal on write to register 1
wire tx_start = cs & rs & we;
// load control register
reg [1:0] counter_divide_select, tx_start_control;
reg [2:0] word_select; // dummy
reg receive_interrupt_enable;
always @(posedge clk) begin
if (rst) begin
counter_divide_select <= 2'b00;
word_select <= 3'b000;
tx_start_control <= 2'b00;
receive_interrupt_enable <= 1'b0;
end else if (cs & ~rs & we)
{receive_interrupt_enable, tx_start_control, word_select, counter_divide_select} <= din;
end
// acia reset generation
wire acia_rst = rst | (counter_divide_select == 2'b11);
// load dout with either status or rx data
wire [7:0] rx_dat, status;
always @(posedge clk) begin
if (rst) begin
dout <= 8'h00;
end else begin
if (cs & ~we) begin
if (rs) dout <= rx_dat;
else dout <= status;
end
end
end
// tx empty is cleared when tx_start starts, cleared when tx_busy deasserts
reg txe;
wire tx_busy;
reg prev_tx_busy;
always @(posedge clk) begin
if (rst) begin
txe <= 1'b1;
prev_tx_busy <= 1'b0;
end else begin
prev_tx_busy <= tx_busy;
if (tx_start) txe <= 1'b0;
else if (prev_tx_busy & ~tx_busy) txe <= 1'b1;
end
end
// rx full is set when rx_stb pulses, cleared when data reg read
wire rx_stb;
reg rxf;
always @(posedge clk) begin
if (rst) rxf <= 1'b0;
else begin
if (rx_stb) rxf <= 1'b1;
else if (cs & rs & ~we) rxf <= 1'b0;
end
end
// assemble status byte
wire rx_err;
assign status = {
irq, // bit 7 = irq - forced inactive
1'b0, // bit 6 = parity error - unused
rx_err, // bit 5 = overrun error - same as all errors
rx_err, // bit 4 = framing error - same as all errors
1'b0, // bit 3 = /CTS - forced active
1'b0, // bit 2 = /DCD - forced active
txe, // bit 1 = tx_start empty
rxf // bit 0 = receive full
};
// Async Receiver
acia_rx #(
.SCW(SCW), // rate counter width
.sym_cnt(sym_cnt) // rate count value
) my_rx (
.clk (clk), // system clock
.rst (acia_rst), // system reset
.rx_serial(rx), // raw serial input
.rx_dat (rx_dat), // received byte
.rx_stb (rx_stb), // received data available
.rx_err (rx_err) // received data error
);
// Transmitter
acia_tx #(
.SCW (SCW), // rate counter width
.sym_cnt(sym_cnt) // rate count value
) my_tx (
.clk (clk), // system clock
.rst (acia_rst), // system reset
.tx_dat (din), // transmit data byte
.tx_start (tx_start), // trigger transmission
.tx_serial(tx), // tx serial output
.tx_busy (tx_busy) // tx is active (not ready)
);
// generate IRQ
assign irq = (rxf & receive_interrupt_enable) | ((tx_start_control == 2'b01) & txe);
endmodule
| 7.780569
|
module ACIA_BRGEN (
input wire RESET,
input wire XTLI,
output wire BCLK,
input wire [3:0] R_SBR
);
reg [31:0] r_clk = 0;
reg r_bclk = 1'b0;
assign BCLK = (R_SBR == 3'b000) ? XTLI : r_bclk;
always @(posedge XTLI, negedge RESET) begin
if ((RESET == 1'b0)) begin
r_clk <= 0;
r_bclk <= 1'b0;
end else begin
if ((r_clk == 0)) begin
r_bclk <= ~r_bclk;
case (R_SBR)
4'b0000: begin
r_clk <= 0;
end
4'b0001: begin
r_clk <= (36864 - 1) / 32;
end
4'b0010: begin
r_clk <= (24576 - 1) / 32;
end
4'b0011: begin
r_clk <= (16769 - 1) / 32;
end
4'b0100: begin
r_clk <= (13704 - 1) / 32;
end
4'b0101: begin
r_clk <= (12288 - 1) / 32;
end
4'b0110: begin
r_clk <= (6144 - 1) / 32;
end
4'b0111: begin
r_clk <= (3072 - 1) / 32;
end
4'b1000: begin
r_clk <= (1536 - 1) / 32;
end
4'b1001: begin
r_clk <= (1024 - 1) / 32;
end
4'b1010: begin
r_clk <= (768 - 1) / 32;
end
4'b1011: begin
r_clk <= (512 - 1) / 32;
end
4'b1100: begin
r_clk <= (384 - 1) / 32;
end
4'b1101: begin
r_clk <= (256 - 1) / 32;
end
4'b1110: begin
r_clk <= (192 - 1) / 32;
end
4'b1111: begin
r_clk <= (96 - 1) / 32;
end
default: begin
r_clk <= 0;
end
endcase
end else begin
r_clk <= r_clk - 1;
end
end
end
endmodule
| 6.603484
|
module
// 06-02-19 E. Brombaugh
module acia_rx(
input clk, // system clock
input rst, // system reset
input rx_serial, // raw serial input
output reg [7:0] rx_dat, // received byte
output reg rx_stb, // received data available
output reg rx_err // received data error
);
// sym rate counter for 115200bps @ 16MHz clk
parameter SCW = 8;
parameter sym_cnt = 139;
// input sync & deglitch
reg [7:0] in_pipe;
reg in_state;
wire all_zero = ~|in_pipe;
wire all_one = &in_pipe;
always @(posedge clk)
if(rst)
begin
// assume RX input idle at start
in_pipe <= 8'hff;
in_state <= 1'b1;
end
else
begin
// shift in a bit
in_pipe <= {in_pipe[6:0],rx_serial};
// update state
if(in_state && all_zero)
in_state <= 1'b0;
else if(!in_state && all_one)
in_state <= 1'b1;
end
// receive machine
reg [8:0] rx_sr;
reg [3:0] rx_bcnt;
reg [SCW-1:0] rx_rcnt;
reg rx_busy;
always @(posedge clk)
if(rst)
begin
rx_busy <= 1'b0;
rx_stb <= 1'b0;
rx_err <= 1'b0;
end
else
begin
if(!rx_busy)
begin
if(!in_state)
begin
// found start bit - wait 1/2 bit to sample
rx_bcnt <= 4'h9;
rx_rcnt <= sym_cnt/2;
rx_busy <= 1'b1;
end
// clear the strobe
rx_stb <= 1'b0;
end
else
begin
if(~|rx_rcnt)
begin
// sample data and restart for next bit
rx_sr <= {in_state,rx_sr[8:1]};
rx_rcnt <= sym_cnt;
rx_bcnt <= rx_bcnt - 1;
if(~|rx_bcnt)
begin
// final bit - check for err and finish
rx_dat <= rx_sr[8:1];
rx_busy <= 1'b0;
if(in_state && ~rx_sr[0])
begin
// framing OK
rx_err <= 1'b0;
rx_stb <= 1'b1;
end
else
// framing err
rx_err <= 1'b1;
end
end
else
rx_rcnt <= rx_rcnt - 1;
end
end
endmodule
| 8.50055
|
module
// 06-02-19 E. Brombaugh
module acia_tx(
input clk, // system clock
input rst, // system reset
input [7:0] tx_dat, // transmit data byte
input tx_start, // trigger transmission
output tx_serial, // tx serial output
output reg tx_busy // tx is active (not ready)
);
// sym rate counter for 115200bps @ 16MHz clk
parameter SCW = 8; // rate counter width
parameter sym_cnt = 139; // rate count value
// transmit machine
reg [8:0] tx_sr;
reg [3:0] tx_bcnt;
reg [SCW-1:0] tx_rcnt;
always @(posedge clk)
begin
if(rst)
begin
tx_sr <= 9'h1ff;
tx_bcnt <= 4'h0;
tx_rcnt <= {SCW{1'b0}};
tx_busy <= 1'b0;
end
else
begin
if(!tx_busy)
begin
if(tx_start)
begin
// start transmission
tx_busy <= 1'b1;
tx_sr <= {tx_dat,1'b0};
tx_bcnt <= 4'd9;
tx_rcnt <= sym_cnt;
end
end
else
begin
if(~|tx_rcnt)
begin
// shift out next bit and restart
tx_sr <= {1'b1,tx_sr[8:1]};
tx_bcnt <= tx_bcnt - 1;
tx_rcnt <= sym_cnt;
if(~|tx_bcnt)
begin
// done - return to inactive state
tx_busy <= 1'b0;
end
end
else
tx_rcnt <= tx_rcnt - 1;
end
end
end
// hook up output
assign tx_serial = tx_sr;
endmodule
| 8.50055
|
module amsacid (
PinCLK,
PinA,
PinOE,
PinCCLR,
PinSIN
);
input PinCLK;
input [7:0] PinA;
input PinOE;
input PinCCLR;
output [7:0] PinSIN;
wire PinCLK;
reg [16:0] ShiftReg = 17'h1FFFF;
wire [16:0] CmpVal;
wire [16:0] XorVal;
assign CmpVal = 17'h13596 ^ (PinA[0] ? 17'h0000c : 0)
^ (PinA[1] ? 17'h06000 : 0)
^ (PinA[2] ? 17'h000c0 : 0)
^ (PinA[3] ? 17'h00030 : 0)
^ (PinA[4] ? 17'h18000 : 0)
^ (PinA[5] ? 17'h00003 : 0)
^ (PinA[6] ? 17'h00600 : 0)
^ (PinA[7] ? 17'h01800 : 0);
assign XorVal = 17'h0C820 ^ (PinA[0] ? 17'h00004 : 0)
^ (PinA[1] ? 17'h06000 : 0)
^ (PinA[2] ? 17'h00080 : 0)
^ (PinA[3] ? 17'h00020 : 0)
^ (PinA[4] ? 17'h08000 : 0)
^ (PinA[5] ? 17'h00000 : 0)
^ (PinA[6] ? 17'h00000 : 0)
^ (PinA[7] ? 17'h00800 : 0);
always @(negedge PinCLK) begin
if (PinCCLR) // not in reset state
begin
if (!PinOE && ((ShiftReg | 17'h00100) == CmpVal)) begin
ShiftReg <= (ShiftReg ^ XorVal) >> 1;
ShiftReg[16] <= ShiftReg[0] ^ ShiftReg[9] ^ ShiftReg[12] ^ ShiftReg[16] ^ XorVal[0]; // hier xorval mit berchsichtigen
end else begin
ShiftReg <= ShiftReg >> 1;
ShiftReg[16] <= ShiftReg[0] ^ ShiftReg[9] ^ ShiftReg[12] ^ ShiftReg[16];
end
end else begin
ShiftReg <= 17'h1FFFF;
end
end
//assign PinSIN = ShiftReg[7:0] ^ 8'hff;
assign PinSIN = ShiftReg[7:0];
//assign PinSIN[0] = PinCLK;
endmodule
| 7.213967
|
module acIn_tb;
reg [7:0] newData;
reg accept;
wire [7:0] data;
acIn uut (
newData,
accept,
data
);
initial begin
$dumpfile("testbench/acIn_tb.vcd");
$dumpvars(0, acIn_tb);
newData = 8'b00000001;
accept = 1'b1;
#20;
newData = 8'b00000010;
accept = 1'b0;
#20;
newData = 8'b00000100;
accept = 1'b1;
#20;
newData = 8'b00000101;
accept = 1'b1;
#20;
$display("test completed");
end
endmodule
| 7.829369
|
module ACI_decoder (
A_sel,
MDDR,
K0,
K1,
G,
AC
);
input [4:0] A_sel;
output MDDR, K0, K1, G, AC;
assign AC = A_sel[0];
assign MDDR = A_sel[1];
assign K0 = A_sel[2];
assign K1 = A_sel[3];
assign G = A_sel[4];
endmodule
| 7.103431
|
module ackor (
input a0,
a1,
a2,
a3,
output ao
);
assign ao = a0 | a1 | a2 | a3;
endmodule
| 7.612201
|
module ack_counter (
clock, // 156 MHz clock
reset, // active high, asynchronous Reset input
ready,
tx_start, // Active high tx_start signal for counter
max_count, //16 bit reg for the maximum count to generate the ack signal
tx_ack // Active high signal
);
// Ports declaration
input clock;
input reset;
input ready;
input tx_start;
input [15:0] max_count;
output tx_ack;
// Wire connections
//Input
wire clock;
wire reset;
wire ready;
wire tx_start;
wire [15:0] max_count;
//Output
reg tx_ack;
//Internal wires
reg start_count;
reg start_count_del;
reg [15:0] counter;
always @(reset or tx_start or counter or max_count) begin
if (reset) begin
start_count <= 0;
end else if (tx_start) begin
start_count <= 1;
end else if ((counter == max_count) & !ready) begin //& !ready
start_count <= 0;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
counter <= 0;
end else if (counter == max_count) begin
counter <= 0;
end else if (start_count) begin
counter <= counter + 1;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
start_count_del <= 0;
tx_ack <= 0;
end else begin
start_count_del <= start_count;
tx_ack <= ~start_count & start_count_del;
end
end
endmodule
| 7.485899
|
module ack_generator(
input clk,
input reset,
input generate_ack,
input generate_nak,
input [7:0] eid_in,
output reg [7:0] message_data,
output reg message_data_valid,
output reg message_frame_valid
);
parameter STATE_IDLE = 0;
parameter STATE_ACK0 = 1;
parameter STATE_NAK0 = 2;
parameter STATE_EID = 3;
parameter STATE_LEN = 4;
reg [2:0] state, next_state;
always @* begin
next_state = state;
message_data = 8'h00;
message_data_valid = 1'b1;
message_frame_valid = 1'b1;
case(state)
STATE_IDLE: begin
message_data_valid = 1'b0;
message_frame_valid = 1'b0;
if(generate_ack)
next_state = STATE_ACK0;
else if(generate_nak)
next_state = STATE_NAK0;
end
STATE_ACK0: begin
message_data = 8'h00;
next_state = STATE_EID;
end
STATE_NAK0: begin
message_data = 8'h01;
next_state = STATE_EID;
end
STATE_EID: begin
message_data = eid_in;
next_state = STATE_LEN;
end
STATE_LEN: begin
next_state = STATE_IDLE;
end
endcase
end
always @(posedge reset or posedge clk) begin
if(reset) begin
state <= `SD STATE_IDLE;
end else begin
state <= `SD next_state;
end
end
endmodule
| 8.005814
|
module ack_led (
input wire i_clk,
input wire i_res_n,
input wire i_trig,
output wire o_led
);
reg [20:0] r_ack_led;
always @(posedge i_clk or negedge i_res_n) begin
if (~i_res_n) begin
r_ack_led <= 21'd0;
end else begin
if (i_trig && (r_ack_led == 21'd0)) begin
r_ack_led <= 21'd1250000;
end else begin
if (r_ack_led != 21'd0) begin
r_ack_led <= r_ack_led - 21'd1;
end
end
end
end
assign o_led = ~(r_ack_led >= 21'd625000);
endmodule
| 6.983309
|
module ack_pipe (
output latch,
input latchd,
input ack,
input clk,
input resetl,
input sys_clk // Generated
);
wire notack;
wire d0;
wire q;
wire d1;
wire d;
// OB.NET (689) - notack : iv
assign notack = ~ack;
// OB.NET (690) - d0 : nd2
assign d0 = ~(q & notack);
// OB.NET (691) - d1 : iv
assign d1 = ~latchd;
// OB.NET (692) - d : nd2
assign d = ~(d0 & d1);
// OB.NET (693) - q : fd2q
fd2q q_inst (
.q /* OUT */ (q),
.d /* IN */ (d),
.cp /* IN */ (clk),
.cd /* IN */ (resetl),
.sys_clk(sys_clk) // Generated
);
// OB.NET (694) - latch : an2
assign latch = q & ack;
endmodule
| 7.631131
|
module name - ack_type_parse
// Version: V3.3.0.20211123
// Created:
// Created:
// by - fenglin
////////////////////////////////////////////////////////////////////////////
// Description:
// parse command ack type
///////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module ack_type_parse
(
i_clk,
i_rst_n,
iv_command_ack,
i_command_ack_wr,
ov_rd_command_ack,
o_rd_command_ack_wr
);
// I/O
// i_clk & rst
input i_clk;
input i_rst_n;
//nmac data
input [65:0] iv_command_ack;
input i_command_ack_wr;
output reg [63:0] ov_rd_command_ack;
output reg o_rd_command_ack_wr;
//***************************************************
// command ack type
//***************************************************
always @(posedge i_clk or negedge i_rst_n) begin
if(i_rst_n == 1'b0)begin
ov_rd_command_ack <= 64'b0;
o_rd_command_ack_wr <= 1'b0;
end
else begin
if(i_command_ack_wr && (iv_command_ack[65:64] == 2'b11))begin
ov_rd_command_ack <= iv_command_ack[63:0];
o_rd_command_ack_wr <= 1'b1;
end
else begin
ov_rd_command_ack <= 64'b0;
o_rd_command_ack_wr <= 1'b0;
end
end
end
endmodule
| 7.665505
|
module contains the minimum number of modules needed to generate ACLK1/#ACLK2 signals.
module AclkGenStandalone (CLK, RES, PHI1, ACLK1, nACLK2);
input CLK;
input RES;
output PHI1; // Sometimes it is required from the outside (triangle channel for example)
output ACLK1;
output nACLK2;
wire PHI0;
wire PHI2;
// The ACLK pattern requires all of these "spares".
CLK_Divider div (
.n_CLK_frompad(~CLK),
.PHI0_tocore(PHI0));
BogusCorePhi phi (.PHI0(PHI0), .PHI1(PHI1), .PHI2(PHI2));
ACLKGen clkgen (
.PHI1(PHI1),
.PHI2(PHI2),
.nACLK2(nACLK2),
.ACLK1(ACLK1),
.RES(RES));
endmodule
| 7.358377
|
module BogusCorePhi (
PHI0,
PHI1,
PHI2
);
input PHI0;
output PHI1;
output PHI2;
assign PHI1 = ~PHI0;
assign PHI2 = PHI0;
endmodule
| 7.227435
|
module aclk_areg (
input load_new_alarm,
clock,
reset,
input [3:0] new_alarm_ms_hr,
new_alarm_ls_hr,
new_alarm_ms_min,
new_alarm_ls_min,
output reg [3:0] alarm_time_ms_hr,
alarm_time_ls_hr,
alarm_time_ms_min,
alarm_time_ls_min
);
always @(posedge clock or posedge reset) begin
// Upon reset, store reset value(1'b0) to the alarm_time registers
if (reset) begin
alarm_time_ms_hr <= 4'b0;
alarm_time_ls_hr <= 4'b0;
alarm_time_ms_min <= 4'b0;
alarm_time_ls_min <= 4'b0;
end
// Else if no reset, check for load_new_alarm signal and load new_alarm time to alarm_time registers
else if (load_new_alarm) begin
alarm_time_ms_hr <= new_alarm_ms_hr;
alarm_time_ls_hr <= new_alarm_ls_hr;
alarm_time_ms_min <= new_alarm_ms_min;
alarm_time_ls_min <= new_alarm_ls_min;
end
end
endmodule
| 7.330185
|
module aclk_counter (
input clk,
reset,
one_minute,
load_new_c,
input [3:0] new_current_time_ms_hr,
new_current_time_ms_min,
new_current_time_ls_hr,
new_current_time_ls_min,
output reg [3:0] current_time_ms_hr,
current_time_ms_min,
current_time_ls_hr,
current_time_ls_min
);
// Lodable Binary up synchronous Counter logic
// Write an always block with asynchronous reset
always @(posedge clk or posedge reset) begin
// Check for reset signal and upon reset load the current_time register with default value (1'b0)
if (reset) begin
current_time_ms_hr <= 4'd0;
current_time_ls_hr <= 4'd0;
current_time_ms_min <= 4'd0;
current_time_ls_min <= 4'd0;
end
// Else if there is no reset, then check for load_new_c signal and load new_current_time to current_time register
else if (load_new_c) begin
current_time_ms_hr <= new_current_time_ms_hr;
current_time_ls_hr <= new_current_time_ls_hr;
current_time_ms_min <= new_current_time_ms_min;
current_time_ls_min <= new_current_time_ls_min;
end // 0 0 0 9 -> 00:10
// Else if there is no load_new_c signal, then check for one_minute signal and implement the counting algorithm
else if (one_minute) begin
if(current_time_ms_hr == 4'd2 && current_time_ls_hr == 4'd3 && current_time_ms_min == 4'd5 && current_time_ls_min == 4'd9)
begin
current_time_ms_hr <= 4'd0;
current_time_ls_hr <= 4'd0;
current_time_ms_min <= 4'd0;
current_time_ls_min <= 4'd0;
end
else if (current_time_ls_hr == 4'd9 && current_time_ms_min == 4'd5 && current_time_ls_min == 4'd9)
begin
current_time_ms_hr <= current_time_ms_hr + 1'b1;
current_time_ls_hr <= 4'd0;
current_time_ms_min <= 4'd0;
current_time_ls_min <= 4'd0;
end else if (current_time_ms_min == 4'd5 && current_time_ls_min == 4'd9) begin
current_time_ls_hr <= current_time_ls_hr + 1'b1;
current_time_ms_min <= 4'd0;
current_time_ls_min <= 4'd0;
end else if (current_time_ls_min == 4'd9) begin
current_time_ms_min <= current_time_ms_min + 1'b1;
current_time_ls_min <= 4'd0;
end else current_time_ls_min <= current_time_ls_min + 1'b1;
end
end
endmodule
| 7.171789
|
module aclk_keyreg (
input reset,
clock,
shift,
input [3:0] key,
output reg [3:0] key_buffer_ls_min,
key_buffer_ms_min,
key_buffer_ls_hr,
key_buffer_ms_hr
);
// This procedure stores the last 4 keys pressed. The FSM block
// detects the new key value and triggers the shift pulse to shift
// in the new key value.
///////////////////////////////////////////////////////////////////
always @(posedge clock or posedge reset) begin
// For asynchronous reset, reset the key_buffer output register to 1'b0
if (reset) begin
key_buffer_ls_min <= 4'b0;
key_buffer_ms_min <= 4'b0;
key_buffer_ls_hr <= 4'b0;
key_buffer_ms_hr <= 4'b0;
end // Else if there is a shift, perform left shift from LS_MIN to MS_HR
else if (shift) begin
key_buffer_ls_min <= key;
key_buffer_ms_min <= key_buffer_ls_min;
key_buffer_ls_hr <= key_buffer_ms_min;
key_buffer_ms_hr <= key_buffer_ls_hr;
end
end
endmodule
| 7.249245
|
module aclk_lcd_driver (
input [3:0] alarm_time,
key,
current_time,
input show_alarm,
show_new_time,
output reg [7:0] display_time,
output reg sound_alarm
);
reg [3:0] display_value; //Defining the internal signals
//Define the Parameter constants to represent LCD numbers
parameter ZERO = 8'h30,ONE = 8'h31,TWO = 8'h32, THREE = 8'h33, FOUR = 8'h34, FIVE = 8'h35,
SIX = 8'h36, SEVEN = 8'h37, EIGHT = 8'h38, NINE = 8'h39, ERROR = 8'h3A;
always @(alarm_time or current_time or show_alarm or show_new_time or key) begin
case ({
show_alarm, show_new_time
})
2'b00: display_value = current_time;
2'b01: display_value = key;
2'b10: display_value = alarm_time;
default: display_value = display_value;
endcase
//Generates sound_alarm logic i,e when current_time is equal to alarm_time
sound_alarm <= (current_time == alarm_time);
end
//Decoder logic
always @(display_value) begin
// For number stored in display_value register, load display_time register with LCD equivalent
case (display_value)
4'd0: display_time = ZERO;
4'd1: display_time = ONE;
4'd2: display_time = TWO;
4'd3: display_time = THREE;
4'd4: display_time = FOUR;
4'd5: display_time = FIVE;
4'd6: display_time = SIX;
4'd7: display_time = SEVEN;
4'd8: display_time = EIGHT;
4'd9: display_time = NINE;
default: display_time = ERROR;
endcase
end
endmodule
| 6.839147
|
module aclk_timegen (
input clk,
reset,
reset_count,
fast_watch,
output reg one_minute,
one_second
);
reg [14:0] i = 15'd0;
always @(posedge clk or posedge reset) begin
if (reset) begin
one_minute <= 0;
one_second <= 0;
end else if (reset_count) begin
one_minute <= 0;
one_second <= 0;
end else if (!fast_watch) begin
if (i[7:0] == 8'd255) one_second <= 1;
else one_second <= 0;
if (i[13:0] == 14'd15359) begin
one_minute <= 1;
i = 15'd0;
end else one_minute <= 0;
i = i + 1'b1;
end else if (fast_watch) begin
if (i[7:0] == 8'd255) one_minute <= 1;
else one_minute <= 0;
i = i + 1'b1;
end
end
endmodule
| 7.358694
|
module aclr_filter (
input aclr, // no domain
input clk,
output aclr_sync
);
reg [2:0]
aclr_meta = 3'b0 /* synthesis preserve dont_replicate */
/* synthesis ALTERA_ATTRIBUTE = "-name SDC_STATEMENT \"set_false_path -from [get_fanins -async *aclr_filter*aclr_meta\[*\]] -to [get_keepers *aclr_filter*aclr_meta\[*\]]\" " */;
always @(posedge clk or posedge aclr) begin
if (aclr) aclr_meta <= 3'b0;
else aclr_meta <= {aclr_meta[1:0], 1'b1};
end
assign aclr_sync = ~aclr_meta[2];
endmodule
| 7.179529
|
module acl_address_to_bankaddress #(
parameter integer ADDRESS_W = 32, // > 0
parameter integer NUM_BANKS = 2, // > 1
parameter integer BANK_SEL_BIT = ADDRESS_W - $clog2(NUM_BANKS)
) (
input logic [ADDRESS_W-1:0] address,
output logic [NUM_BANKS-1:0] bank_sel, // one-hot
output logic [ADDRESS_W-$clog2(NUM_BANKS)-1:0] bank_address
);
integer i;
// To support NUM_BANKS=1 we need a wider address
logic [ADDRESS_W:0] wider_address;
assign wider_address = {1'b0, address};
always @* begin
for (i = 0; i < NUM_BANKS; i = i + 1)
bank_sel[i] = (wider_address[BANK_SEL_BIT+$clog2(NUM_BANKS)-1 : BANK_SEL_BIT] == i);
end
assign bank_address = ((address >> (BANK_SEL_BIT + $clog2(
NUM_BANKS
))) << (BANK_SEL_BIT)) |
// Take address[BANKS_SEL_BIT-1:0] in a manner that allows BANK_SEL_BIT=0
((~({ADDRESS_W{1'b1}} << BANK_SEL_BIT)) & address);
endmodule
| 6.766817
|
module generates a sequence of valid signals after the writes for the corresponding threads have been handled.
module valid_generator(clock, resetn, i_valid, o_stall, i_thread_count, o_valid, i_stall);
parameter MAX_THREADS = 64; // Must be a power of 2
localparam NUM_THREAD_BITS = $clog2(MAX_THREADS) + 1;
input clock, resetn, i_valid, i_stall;
input [NUM_THREAD_BITS-1:0] i_thread_count;
output o_valid;
output o_stall;
reg [NUM_THREAD_BITS:0] local_thread_count;
reg valid_sr;
reg valid_reg;
wire stall_counter;
// Stall when you have a substantial amount of threads
// to dispense to prevent the counter from overflowing.
assign o_stall = local_thread_count[NUM_THREAD_BITS];
// This is a local counter. It will accept a new thread ID if it is not stalling out.
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
local_thread_count <= {{NUM_THREAD_BITS}{1'b0}};
end
else
begin
local_thread_count <= local_thread_count +
{1'b0, i_thread_count & {{NUM_THREAD_BITS}{i_valid & ~o_stall}}} +
{{NUM_THREAD_BITS+1}{~stall_counter & (|local_thread_count)}};
end
end
// The counter state is checked in the next cycle, which can stall the counter using the stall_counter signal.
assign stall_counter = valid_reg & valid_sr;
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
valid_reg <= 1'b0;
end
else
begin
if (~stall_counter)
begin
valid_reg <= (|local_thread_count);
end
end
end
// Finally we put a staging register at the end.
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
valid_sr <= 1'b0;
end
else
begin
valid_sr <= valid_sr ? i_stall : (valid_reg & i_stall);
end
end
assign o_valid = valid_sr | valid_reg;
endmodule
| 6.670138
|
module performs a comparison of two n-bit values. This is not that complicated, but we did
// want to break the comparison with a register.
module acl_registered_comparison(clock, left, right, enable, result);
parameter WIDTH = 32;
input clock, enable;
input [WIDTH-1:0] left;
input [WIDTH-1:0] right;
output result;
localparam SECTION_SIZE = 4;
localparam SECTIONS = ((WIDTH % SECTION_SIZE) == 0) ? (WIDTH/SECTION_SIZE) : (WIDTH/SECTION_SIZE + 1);
reg [SECTIONS-1:0] comparisons;
wire [SECTIONS*SECTION_SIZE : 0] temp_left = {{{SECTIONS*SECTION_SIZE-WIDTH + 1}{1'b0}}, left};
wire [SECTIONS*SECTION_SIZE : 0] temp_right = {{{SECTIONS*SECTION_SIZE-WIDTH + 1}{1'b0}}, right};
genvar i;
generate
for (i=0; i < SECTIONS; i = i + 1)
begin: cmp
always@(posedge clock)
begin
if(enable) comparisons[i] <= (temp_left[(i+1)*SECTION_SIZE-1:SECTION_SIZE*i] == temp_right[(i+1)*SECTION_SIZE-1:SECTION_SIZE*i]);
end
end
endgenerate
assign result = &comparisons;
endmodule
| 7.754737
|
module acl_arb_pipeline_reg #(
parameter integer DATA_W = 32, // > 0
parameter integer BURSTCOUNT_W = 4, // > 0
parameter integer ADDRESS_W = 32, // > 0
parameter integer BYTEENA_W = DATA_W / 8, // > 0
parameter integer ID_W = 1, // > 0
parameter ASYNC_RESET = 1, // 1 = Registers are reset asynchronously. 0 = Registers are reset synchronously -- the reset signal is pipelined before consumption. In both cases, some registesr are not reset at all.
parameter SYNCHRONIZE_RESET = 0 // 1 = resetn is synchronized before consumption. The consumption itself is either asynchronous or synchronous, as specified by ASYNC_RESET.
) (
input wire clock,
input wire resetn,
acl_arb_intf in_intf,
acl_arb_intf out_intf
);
localparam NUM_RESET_COPIES = 1;
localparam RESET_PIPE_DEPTH = 3;
logic aclrn;
logic [NUM_RESET_COPIES-1:0] sclrn;
acl_reset_handler #(
.ASYNC_RESET (ASYNC_RESET),
.USE_SYNCHRONIZER (SYNCHRONIZE_RESET),
.SYNCHRONIZE_ACLRN(SYNCHRONIZE_RESET),
.PIPE_DEPTH (RESET_PIPE_DEPTH),
.NUM_COPIES (NUM_RESET_COPIES)
) acl_reset_handler_inst (
.clk (clock),
.i_resetn (resetn),
.o_aclrn (aclrn),
.o_resetn_synchronized(),
.o_sclrn (sclrn)
);
acl_arb_data #(
.DATA_W(DATA_W),
.BURSTCOUNT_W(BURSTCOUNT_W),
.ADDRESS_W(ADDRESS_W),
.BYTEENA_W(BYTEENA_W),
.ID_W(ID_W)
) pipe_r ();
// Pipeline register.
always @(posedge clock or negedge aclrn) begin
if (!aclrn) begin
pipe_r.req <= 'x; // only signals reset explicitly below need to be reset at all
pipe_r.req.request <= 1'b0;
pipe_r.req.read <= 1'b0;
pipe_r.req.write <= 1'b0;
end else begin
if (!(out_intf.stall & pipe_r.req.request) & in_intf.req.enable) begin
pipe_r.req <= in_intf.req;
end
if (!sclrn[0]) begin
pipe_r.req.request <= 1'b0;
pipe_r.req.read <= 1'b0;
pipe_r.req.write <= 1'b0;
end
end
end
// Request for downstream blocks.
assign out_intf.req.enable = in_intf.req.enable; //the enable must bypass the register
assign out_intf.req.request = pipe_r.req.request;
assign out_intf.req.read = pipe_r.req.read;
assign out_intf.req.write = pipe_r.req.write;
assign out_intf.req.writedata = pipe_r.req.writedata;
assign out_intf.req.burstcount = pipe_r.req.burstcount;
assign out_intf.req.address = pipe_r.req.address;
assign out_intf.req.byteenable = pipe_r.req.byteenable;
assign out_intf.req.id = pipe_r.req.id;
// Upstream stall signal.
assign in_intf.stall = out_intf.stall & pipe_r.req.request;
endmodule
| 9.042726
|
module acl_arb_staging_reg #(
parameter integer DATA_W = 32, // > 0
parameter integer BURSTCOUNT_W = 4, // > 0
parameter integer ADDRESS_W = 32, // > 0
parameter integer BYTEENA_W = DATA_W / 8, // > 0
parameter integer ID_W = 1, // > 0
parameter ASYNC_RESET = 1, // 1 = Registers are reset asynchronously. 0 = Registers are reset synchronously -- the reset signal is pipelined before consumption. In both cases, some registesr are not reset at all.
parameter SYNCHRONIZE_RESET = 0 // 1 = resetn is synchronized before consumption. The consumption itself is either asynchronous or synchronous, as specified by ASYNC_RESET.
) (
input wire clock,
input wire resetn,
acl_arb_intf in_intf,
acl_arb_intf out_intf
);
logic stall_r;
localparam NUM_RESET_COPIES = 1;
localparam RESET_PIPE_DEPTH = 3;
logic aclrn;
logic [NUM_RESET_COPIES-1:0] sclrn;
acl_reset_handler #(
.ASYNC_RESET (ASYNC_RESET),
.USE_SYNCHRONIZER (SYNCHRONIZE_RESET),
.SYNCHRONIZE_ACLRN(SYNCHRONIZE_RESET),
.PIPE_DEPTH (RESET_PIPE_DEPTH),
.NUM_COPIES (NUM_RESET_COPIES)
) acl_reset_handler_inst (
.clk (clock),
.i_resetn (resetn),
.o_aclrn (aclrn),
.o_resetn_synchronized(),
.o_sclrn (sclrn)
);
acl_arb_data #(
.DATA_W(DATA_W),
.BURSTCOUNT_W(BURSTCOUNT_W),
.ADDRESS_W(ADDRESS_W),
.BYTEENA_W(BYTEENA_W),
.ID_W(ID_W)
) staging_r ();
// Staging register.
always @(posedge clock or negedge aclrn) begin
if (!aclrn) begin
staging_r.req <= 'x; // only signals reset explicitly below need to be reset at all
staging_r.req.request <= 1'b0;
staging_r.req.read <= 1'b0;
staging_r.req.write <= 1'b0;
end else begin
if (!stall_r) begin
staging_r.req <= in_intf.req;
end
if (!sclrn[0]) begin
staging_r.req.request <= 1'b0;
staging_r.req.read <= 1'b0;
staging_r.req.write <= 1'b0;
end
end
end
// Stall register.
always @(posedge clock or negedge aclrn) begin
if (!aclrn) begin
stall_r <= 1'b0;
end else begin
stall_r <= out_intf.stall & (stall_r | in_intf.req.request);
if (!sclrn[0]) begin
stall_r <= 1'b0;
end
end
end
// Request for downstream blocks.
assign out_intf.req = stall_r ? staging_r.req : in_intf.req;
// Upstream stall signal.
assign in_intf.stall = stall_r;
endmodule
| 9.149296
|
module acl_atomics_arb_stall #(
// Configuration
parameter integer STALL_CYCLES = 6
) (
input logic clock,
input logic resetn,
acl_arb_intf in_intf,
acl_arb_intf out_intf
);
/******************
* Local Variables *
******************/
reg shift_register[0:STALL_CYCLES-1];
wire atomic;
wire stall;
integer t;
/******************
* Local Variables *
******************/
assign out_intf.req.request = (in_intf.req.request & ~stall); // mask request
assign out_intf.req.read = (in_intf.req.read & ~stall); // mask read
assign out_intf.req.write = (in_intf.req.write & ~stall); // mask write
assign out_intf.req.writedata = in_intf.req.writedata;
assign out_intf.req.burstcount = in_intf.req.burstcount;
assign out_intf.req.address = in_intf.req.address;
assign out_intf.req.byteenable = in_intf.req.byteenable;
assign out_intf.req.id = in_intf.req.id;
assign in_intf.stall = (out_intf.stall | stall);
/*****************
* Detect Atomic *
******************/
assign atomic = ( out_intf.req.request == 1'b1 &&
out_intf.req.read == 1'b1 &&
out_intf.req.writedata[0:0] == 1'b1 ) ? 1'b1 : 1'b0;
always @(posedge clock or negedge resetn) begin
if (!resetn) begin
shift_register[0] <= 1'b0;
end else begin
shift_register[0] <= atomic;
end
end
/*****************
* Shift Register *
******************/
always @(posedge clock or negedge resetn) begin
for (t = 1; t < STALL_CYCLES; t = t + 1) begin
if (!resetn) begin
shift_register[t] <= 1'b0;
end else begin
shift_register[t] <= shift_register[t-1];
end
end
end
/***************
* Detect Stall *
***************/
assign stall = (shift_register[STALL_CYCLES-1] == 1'b1);
endmodule
| 6.546222
|
module atomic_alu (
readdata,
atomic_op,
operand0,
operand1,
atomic_out
);
parameter ATOMIC_OP_WIDTH = 3; // this many atomic operations
parameter OPERATION_WIDTH = 32; // atomic operations are ALL 32-bit
parameter USED_ATOMIC_OPERATIONS = 8'b00000001;
// WARNING: these MUST match ACLIntrinsics::ID enum in ACLIntrinsics.h
localparam a_ADD = 0;
localparam a_XCHG = 1;
localparam a_CMPXCHG = 2;
localparam a_MIN = 3;
localparam a_MAX = 4;
localparam a_AND = 5;
localparam a_OR = 6;
localparam a_XOR = 7;
// Standard global signals
input logic [OPERATION_WIDTH-1:0] readdata;
input logic [ATOMIC_OP_WIDTH-1:0] atomic_op;
input logic [OPERATION_WIDTH-1:0] operand0;
input logic [OPERATION_WIDTH-1:0] operand1;
output logic [OPERATION_WIDTH-1:0] atomic_out;
wire [31:0] atomic_out_add /* synthesis keep */;
wire [31:0] atomic_out_cmp /* synthesis keep */;
wire [31:0] atomic_out_cmpxchg /* synthesis keep */;
wire [31:0] atomic_out_min /* synthesis keep */;
wire [31:0] atomic_out_max /* synthesis keep */;
wire [31:0] atomic_out_and /* synthesis keep */;
wire [31:0] atomic_out_or /* synthesis keep */;
wire [31:0] atomic_out_xor /* synthesis keep */;
generate
if ((USED_ATOMIC_OPERATIONS & (1 << a_ADD)) != 0) assign atomic_out_add = readdata + operand0;
else assign atomic_out_add = {ATOMIC_OP_WIDTH{1'bx}};
endgenerate
generate
if ((USED_ATOMIC_OPERATIONS & (1 << a_XCHG)) != 0) assign atomic_out_cmp = operand0;
else assign atomic_out_cmp = {ATOMIC_OP_WIDTH{1'bx}};
endgenerate
generate
if ((USED_ATOMIC_OPERATIONS & (1 << a_CMPXCHG)) != 0)
assign atomic_out_cmpxchg = (readdata == operand0) ? operand1 : readdata;
else assign atomic_out_cmpxchg = {ATOMIC_OP_WIDTH{1'bx}};
endgenerate
generate
if ((USED_ATOMIC_OPERATIONS & (1 << a_MIN)) != 0)
assign atomic_out_min = (readdata < operand0) ? readdata : operand0;
else assign atomic_out_min = {ATOMIC_OP_WIDTH{1'bx}};
endgenerate
generate
if ((USED_ATOMIC_OPERATIONS & (1 << a_MAX)) != 0)
assign atomic_out_max = (readdata > operand0) ? readdata : operand0;
else assign atomic_out_max = {ATOMIC_OP_WIDTH{1'bx}};
endgenerate
generate
if ((USED_ATOMIC_OPERATIONS & (1 << a_AND)) != 0) assign atomic_out_and = (readdata & operand0);
else assign atomic_out_and = {ATOMIC_OP_WIDTH{1'bx}};
endgenerate
generate
if ((USED_ATOMIC_OPERATIONS & (1 << a_OR)) != 0) assign atomic_out_or = (readdata | operand0);
else assign atomic_out_or = {ATOMIC_OP_WIDTH{1'bx}};
endgenerate
generate
if ((USED_ATOMIC_OPERATIONS & (1 << a_XOR)) != 0) assign atomic_out_xor = (readdata ^ operand0);
else assign atomic_out_xor = {ATOMIC_OP_WIDTH{1'bx}};
endgenerate
always @(*) begin
case (atomic_op)
a_ADD: begin
atomic_out = atomic_out_add;
end
a_XCHG: begin
atomic_out = atomic_out_cmp;
end
a_CMPXCHG: begin
atomic_out = atomic_out_cmpxchg;
end
a_MIN: begin
atomic_out = atomic_out_min;
end
a_MAX: begin
atomic_out = atomic_out_max;
end
a_AND: begin
atomic_out = atomic_out_and;
end
a_OR: begin
atomic_out = atomic_out_or;
end
default: begin
atomic_out = atomic_out_xor;
end
endcase
end
endmodule
| 9.348283
|
module acl_avm_to_ic #(
parameter integer DATA_W = 256,
parameter integer WRITEDATA_W = 256,
parameter integer BURSTCOUNT_W = 6,
parameter integer ADDRESS_W = 32,
parameter integer BYTEENA_W = DATA_W / 8,
parameter integer ID_W = 1,
parameter ADDR_SHIFT = 1 // shift the address?
) (
// AVM interface
input logic avm_enable,
input logic avm_read,
input logic avm_write,
input logic [WRITEDATA_W-1:0] avm_writedata,
input logic [BURSTCOUNT_W-1:0] avm_burstcount,
input logic [ADDRESS_W-1:0] avm_address,
input logic [BYTEENA_W-1:0] avm_byteenable,
output logic avm_waitrequest,
output logic avm_readdatavalid,
output logic [WRITEDATA_W-1:0] avm_readdata,
output logic avm_writeack, // not a true Avalon signal
// IC interface
output logic ic_arb_request,
output logic ic_arb_enable,
output logic ic_arb_read,
output logic ic_arb_write,
output logic [WRITEDATA_W-1:0] ic_arb_writedata,
output logic [BURSTCOUNT_W-1:0] ic_arb_burstcount,
output logic [ADDRESS_W-$clog2(DATA_W / 8)-1:0] ic_arb_address,
output logic [BYTEENA_W-1:0] ic_arb_byteenable,
output logic [ID_W-1:0] ic_arb_id,
input logic ic_arb_stall,
input logic ic_wrp_ack,
input logic ic_rrp_datavalid,
input logic [WRITEDATA_W-1:0] ic_rrp_data
);
// The logic for ic_arb_request (below) makes a MAJOR ASSUMPTION:
// avm_write will never be deasserted in the MIDDLE of a write burst
// (read bursts are fine since they are single cycle requests)
//
// For proper burst functionality, ic_arb_request must remain asserted
// for the ENTIRE duration of a burst request, otherwise the burst may be
// interrupted and lead to all sorts of chaos. At this time, LSUs do not
// deassert avm_write in the middle of a write burst, so this assumption
// is valid.
//
// If there comes a time when this assumption is no longer valid,
// logic needs to be added to detect when a burst begins/ends.
assign ic_arb_request = avm_read | avm_write;
assign ic_arb_read = avm_read;
assign ic_arb_write = avm_write;
assign ic_arb_writedata = avm_writedata;
assign ic_arb_burstcount = avm_burstcount;
assign ic_arb_id = {ID_W{1'bx}};
assign ic_arb_enable = avm_enable;
generate
if (ADDR_SHIFT == 1) begin
assign ic_arb_address = avm_address[ADDRESS_W-1:$clog2(DATA_W/8)];
end else begin
assign ic_arb_address = avm_address[ADDRESS_W-$clog2(DATA_W/8)-1:0];
end
endgenerate
assign ic_arb_byteenable = avm_byteenable;
assign avm_waitrequest = ic_arb_stall;
assign avm_readdatavalid = ic_rrp_datavalid;
assign avm_readdata = ic_rrp_data;
assign avm_writeack = ic_wrp_ack;
endmodule
| 8.631634
|
module to ensure that the clock2x net is preserved in the design.
module acl_clock2x_holder(clock, clock2x, resetn, myout);
input clock, clock2x, resetn;
output myout;
reg twoXclock_consumer_NO_SHIFT_REG /* synthesis preserve noprune */;
always @(posedge clock2x or negedge resetn)
begin
if (~(resetn))
begin
twoXclock_consumer_NO_SHIFT_REG <= 1'b0;
end
else
begin
twoXclock_consumer_NO_SHIFT_REG <= 1'b1;
end
end
assign myout = twoXclock_consumer_NO_SHIFT_REG;
endmodule
| 6.984947
|
module acl_debug_mem #(
parameter WIDTH = 16,
parameter SIZE = 10
) (
input logic clk,
input logic resetn,
input logic write,
input logic [WIDTH-1:0] data [SIZE]
);
/******************
* LOCAL PARAMETERS
*******************/
localparam ADDRWIDTH = $clog2(SIZE);
/******************
* SIGNALS
*******************/
logic [ADDRWIDTH-1:0] addr;
logic do_write;
/******************
* ARCHITECTURE
*******************/
always @(posedge clk or negedge resetn)
if (!resetn) addr <= {ADDRWIDTH{1'b0}};
else if (addr != {ADDRWIDTH{1'b0}}) addr <= addr + 2'b01;
else if (write) addr <= addr + 2'b01;
assign do_write = write | (addr != {ADDRWIDTH{1'b0}});
// Instantiate In-System Modifiable Memory
altsyncram altsyncram_component (
.address_a(addr),
.clock0(clk),
.data_a(data[addr]),
.wren_a(do_write),
.q_a(),
.aclr0(1'b0),
.aclr1(1'b0),
.address_b(1'b1),
.addressstall_a(1'b0),
.addressstall_b(1'b0),
.byteena_a(1'b1),
.byteena_b(1'b1),
.clock1(1'b1),
.clocken0(1'b1),
.clocken1(1'b1),
.clocken2(1'b1),
.clocken3(1'b1),
.data_b(1'b1),
.eccstatus(),
.q_b(),
.rden_a(1'b1),
.rden_b(1'b1),
.wren_b(1'b0)
);
defparam altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Stratix IV",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=ACLDEBUGMEM",
altsyncram_component.lpm_type = "altsyncram", altsyncram_component.numwords_a = SIZE,
altsyncram_component.widthad_a = ADDRWIDTH, altsyncram_component.width_a = WIDTH,
altsyncram_component.operation_mode = "SINGLE_PORT", altsyncram_component.outdata_aclr_a =
"NONE", altsyncram_component.read_during_write_mode_port_a = "DONT_CARE",
altsyncram_component.width_byteena_a = 1;
endmodule
| 7.555268
|
module acl_dspba_buffer (
buffer_in,
buffer_out
);
parameter WIDTH = 32;
input [WIDTH-1:0] buffer_in;
output [WIDTH-1:0] buffer_out;
assign buffer_out = buffer_in;
endmodule
| 8.392748
|
module acl_dspba_valid_fifo_counter #(
parameter integer DEPTH = 32, // >0
parameter integer STRICT_DEPTH = 0, // 0|1
parameter integer ALLOW_FULL_WRITE = 0 // 0|1
) (
input logic clock,
input logic resetn,
input logic valid_in,
output logic valid_out,
input logic stall_in,
output logic stall_out,
output logic empty,
output logic full
);
// No data, so just build a counter to count the number of valids stored in this "FIFO".
//
// The counter is constructed to count up to a MINIMUM value of DEPTH entries.
// * Logical range of the counter C0 is [0, DEPTH].
// * empty = (C0 <= 0)
// * full = (C0 >= DEPTH)
//
// To have efficient detection of the empty condition (C0 == 0), the range is offset
// by -1 so that a negative number indicates empty.
// * Logical range of the counter C1 is [-1, DEPTH-1].
// * empty = (C1 < 0)
// * full = (C1 >= DEPTH-1)
// The size of counter C1 is $clog2((DEPTH-1) + 1) + 1 => $clog2(DEPTH) + 1.
//
// To have efficient detection of the full condition (C1 >= DEPTH-1), change the
// full condition to C1 == 2^$clog2(DEPTH-1), which is DEPTH-1 rounded up
// to the next power of 2. This is only done if STRICT_DEPTH == 0, otherwise
// the full condition is comparison vs. DEPTH-1.
// * Logical range of the counter C2 is [-1, 2^$clog2(DEPTH-1)]
// * empty = (C2 < 0)
// * full = (C2 == 2^$clog2(DEPTH - 1))
// The size of counter C2 is $clog2(DEPTH-1) + 2.
// * empty = MSB
// * full = ~[MSB] & [MSB-1]
localparam COUNTER_WIDTH = (STRICT_DEPTH == 0) ? ((DEPTH > 1 ? $clog2(
DEPTH - 1
) : 0) + 2) : ($clog2(
DEPTH
) + 1);
logic [COUNTER_WIDTH - 1:0] valid_counter;
logic incr, decr;
wire [1:0] counter_update;
wire [COUNTER_WIDTH-1:0] counter_update_extended;
assign counter_update = {1'b0, incr} - {1'b0, decr};
assign counter_update_extended = $signed(counter_update);
assign empty = valid_counter[$bits(valid_counter)-1];
assign full = (STRICT_DEPTH == 0) ? (~valid_counter[$bits(
valid_counter
)-1] & valid_counter[$bits(
valid_counter
)-2]) : (valid_counter == DEPTH - 1);
assign incr = valid_in & ~stall_out;
assign decr = valid_out & ~stall_in;
assign valid_out = ~empty;
assign stall_out = ALLOW_FULL_WRITE ? (full & stall_in) : full;
always @(posedge clock or negedge resetn)
if (!resetn) valid_counter <= {$bits(valid_counter) {1'b1}}; // -1
else valid_counter <= valid_counter + counter_update_extended;
endmodule
| 7.318019
|
module acl_embedded_workgroup_issuer #(
parameter unsigned MAX_SIMULTANEOUS_WORKGROUPS = 2, // >0
parameter unsigned MAX_WORKGROUP_SIZE = 2147483648, // >0
parameter string WORKGROUP_EXIT_ORDER = "fifo", // fifo|noninterleaved|unknown
parameter unsigned WG_SIZE_BITS = $clog2({1'b0, MAX_WORKGROUP_SIZE} + 1),
parameter unsigned LLID_BITS = (MAX_WORKGROUP_SIZE > 1 ? $clog2(MAX_WORKGROUP_SIZE) : 1),
parameter unsigned WG_ID_BITS = (MAX_SIMULTANEOUS_WORKGROUPS > 1 ? $clog2(
MAX_SIMULTANEOUS_WORKGROUPS
) : 1)
) (
input logic clock,
input logic resetn,
// Handshake for item entry into function.
input logic valid_in,
output logic stall_out,
// Handshake with entry basic block
output logic valid_entry,
input logic stall_entry,
// Observe threads exiting the function .
// This is asserted when items are ready to be retired from the workgroup.
input logic valid_exit,
// This is asserted when downstream is not ready to retire an item from
// the workgroup.
input logic stall_exit,
// Need workgroup_size to know when one workgroup ends
// and another begins.
input logic [WG_SIZE_BITS - 1:0] workgroup_size,
// Linearized local id. In range of [0, workgroup_size - 1].
output logic [LLID_BITS - 1:0] linear_local_id_out,
// Hardware work-group id. In range of [0, MAX_SIMULTANEOUS_WORKGROUPS - 1].
output logic [WG_ID_BITS - 1:0] hw_wg_id_out,
// The hardware work-group id of the work-group that is exiting.
input logic [WG_ID_BITS - 1:0] done_hw_wg_id_in,
// Pass though global_id, local_id and group_id.
input logic [31:0] global_id_in [2:0],
input logic [31:0] local_id_in [2:0],
input logic [31:0] group_id_in [2:0],
output logic [31:0] global_id_out[2:0],
output logic [31:0] local_id_out [2:0],
output logic [31:0] group_id_out [2:0]
);
generate
if (WORKGROUP_EXIT_ORDER == "fifo") begin
acl_embedded_workgroup_issuer_fifo #(
.MAX_SIMULTANEOUS_WORKGROUPS(MAX_SIMULTANEOUS_WORKGROUPS),
.MAX_WORKGROUP_SIZE(MAX_WORKGROUP_SIZE)
) issuer (
.*
);
end
else if( WORKGROUP_EXIT_ORDER == "noninterleaved" || WORKGROUP_EXIT_ORDER == "unknown" )
begin
acl_embedded_workgroup_issuer_complex #(
.MAX_SIMULTANEOUS_WORKGROUPS(MAX_SIMULTANEOUS_WORKGROUPS),
.MAX_WORKGROUP_SIZE(MAX_WORKGROUP_SIZE)
) issuer (
.*
);
end else begin
// synthesis translate off
initial
$fatal("%m: unsupported configuration (WORKGROUP_EXIT_ORDER=%s)", WORKGROUP_EXIT_ORDER);
// synthesis translate on
end
endgenerate
endmodule
| 7.655783
|
module acl_embedded_workgroup_issuer_fifo #(
parameter unsigned MAX_SIMULTANEOUS_WORKGROUPS = 2, // >0
parameter unsigned MAX_WORKGROUP_SIZE = 2147483648, // >0
parameter unsigned WG_SIZE_BITS = $clog2({1'b0, MAX_WORKGROUP_SIZE} + 1),
parameter unsigned LLID_BITS = (MAX_WORKGROUP_SIZE > 1 ? $clog2(MAX_WORKGROUP_SIZE) : 1),
parameter unsigned WG_ID_BITS = (MAX_SIMULTANEOUS_WORKGROUPS > 1 ? $clog2(
MAX_SIMULTANEOUS_WORKGROUPS
) : 1)
) (
input logic clock,
input logic resetn,
// Handshake for item entry into function.
input logic valid_in,
output logic stall_out,
// Handshake with entry basic block
output logic valid_entry,
input logic stall_entry,
// Observe threads exiting the function .
// This is asserted when items are ready to be retired from the workgroup.
input logic valid_exit,
// This is asserted when downstream is not ready to retire an item from
// the workgroup.
input logic stall_exit,
// Need workgroup_size to know when one workgroup ends
// and another begins.
input logic [WG_SIZE_BITS - 1:0] workgroup_size,
// Linearized local id. In range of [0, workgroup_size - 1].
output logic [LLID_BITS - 1:0] linear_local_id_out,
// Hardware work-group id. In range of [0, MAX_SIMULTANEOUS_WORKGROUPS - 1].
output logic [WG_ID_BITS - 1:0] hw_wg_id_out,
// The hardware work-group id of the work-group that is exiting.
input logic [WG_ID_BITS - 1:0] done_hw_wg_id_in,
// Pass though global_id, local_id and group_id.
input logic [31:0] global_id_in [2:0],
input logic [31:0] local_id_in [2:0],
input logic [31:0] group_id_in [2:0],
output logic [31:0] global_id_out[2:0],
output logic [31:0] local_id_out [2:0],
output logic [31:0] group_id_out [2:0]
);
// Entry: 1 cycle latency
// Exit: 1 cycle latency
acl_work_group_limiter #(
.WG_LIMIT(MAX_SIMULTANEOUS_WORKGROUPS),
.KERNEL_WG_LIMIT(MAX_SIMULTANEOUS_WORKGROUPS),
.MAX_WG_SIZE(MAX_WORKGROUP_SIZE),
.WG_FIFO_ORDER(1),
.IMPL("kernel") // this parameter is very important to get the right implementation
) limiter (
.clock (clock),
.resetn (resetn),
.wg_size(workgroup_size),
.entry_valid_in(valid_in),
.entry_k_wgid(),
.entry_stall_out(stall_out),
.entry_valid_out(valid_entry),
.entry_l_wgid(hw_wg_id_out),
.entry_stall_in(stall_entry),
.exit_valid_in (valid_exit & ~stall_exit),
.exit_stall_out(),
.exit_valid_out(),
.exit_stall_in (1'b0)
);
// Pass through ids (global, local, group).
// Match the latency of the work-group limiter, which is one cycle.
always @(posedge clock)
if (~stall_entry) begin
global_id_out <= global_id_in;
local_id_out <= local_id_in;
group_id_out <= group_id_in;
end
// local id 3 generator
always @(posedge clock or negedge resetn)
if (~resetn) linear_local_id_out <= '0;
else if (valid_entry & ~stall_entry) begin
if (linear_local_id_out == workgroup_size - 'd1) linear_local_id_out <= '0;
else linear_local_id_out <= linear_local_id_out + 'd1;
end
endmodule
| 7.655783
|
module acl_enable_sink #(
parameter integer DATA_WIDTH = 32,
parameter integer PIPELINE_DEPTH = 32,
parameter integer SCHEDULEII = 1,
// these parameters are dependent on the latency of the cluster entry and exit nodes
// overall latency of this IP
parameter integer IP_PIPELINE_LATENCY_PLUS1 = 1,
// to support the 0-latency stall free entry, add one more valid bit
parameter integer ZERO_LATENCY_OFFSET = 1
) (
input logic clock,
input logic resetn,
input logic [DATA_WIDTH-1:0] data_in,
output logic [DATA_WIDTH-1:0] data_out,
input logic input_accepted,
input logic valid_in,
output logic valid_out,
input logic stall_in,
output logic stall_entry,
output logic enable,
input logic inc_pipelined_thread,
input logic dec_pipelined_thread,
output logic valid_mask
);
wire throttle_pipelined_iterations;
wire [1:0] threads_count_update;
wire [$clog2(SCHEDULEII):0] threads_count_update_extended;
//output of the enable cluster
assign data_out = data_in;
assign valid_out = valid_in;
// if there is no register at the output of this IP than we need to add the valid input to the enable to ensure a capacity of 1
// Only the old backend has ip latency > 0
assign enable = (IP_PIPELINE_LATENCY_PLUS1 == 1) ? (~valid_out | ~stall_in) : ~stall_in;
assign stall_entry = ~enable | throttle_pipelined_iterations;
// This will be used to mask the valid in order to indicate whether an input is
// accepted or not. An input is accepted when valid_mask is 0.
assign valid_mask = (PIPELINE_DEPTH == 0) ? throttle_pipelined_iterations : stall_entry;
assign threads_count_update = inc_pipelined_thread - dec_pipelined_thread;
assign threads_count_update_extended = $signed(threads_count_update);
//handle II > 1
reg [$clog2(SCHEDULEII):0] IIschedcount;
reg [$clog2(SCHEDULEII):0] threads_count;
always @(posedge clock or negedge resetn) begin
if (!resetn) begin
IIschedcount <= 0;
threads_count <= 0;
end else if (enable) begin
// do not increase the counter if a thread is exiting
// increasing threads_count is already decreasing the window
// increasing IIschedcount ends up accepting the next thread too early
IIschedcount <= (input_accepted && dec_pipelined_thread) ? IIschedcount : (IIschedcount == (SCHEDULEII - 1) ? 0 : (IIschedcount + 1));
if (input_accepted) begin
threads_count <= threads_count + threads_count_update_extended;
end
end
end
// allow threads in a window of the II cycles
// this prevents the next iteration from entering too early
assign throttle_pipelined_iterations = (IIschedcount >= (threads_count > 0 ? threads_count : 1));
endmodule
| 7.722543
|
module acl_ic_local_mem_router #(
parameter integer DATA_W = 256,
parameter integer BURSTCOUNT_W = 6,
parameter integer ADDRESS_W = 32,
parameter integer BYTEENA_W = DATA_W / 8,
parameter integer NUM_BANKS = 8
) (
input logic clock,
input logic resetn,
// Bank select (one-hot)
input logic [NUM_BANKS-1:0] bank_select,
// Master
input logic m_arb_request,
input logic m_arb_enable,
input logic m_arb_read,
input logic m_arb_write,
input logic [DATA_W-1:0] m_arb_writedata,
input logic [BURSTCOUNT_W-1:0] m_arb_burstcount,
input logic [ADDRESS_W-1:0] m_arb_address,
input logic [BYTEENA_W-1:0] m_arb_byteenable,
output logic m_arb_stall,
output logic m_wrp_ack,
output logic m_rrp_datavalid,
output logic [DATA_W-1:0] m_rrp_data,
// To each bank
output logic b_arb_request[NUM_BANKS],
output logic b_arb_enable[NUM_BANKS],
output logic b_arb_read[NUM_BANKS],
output logic b_arb_write[NUM_BANKS],
output logic [DATA_W-1:0] b_arb_writedata[NUM_BANKS],
output logic [BURSTCOUNT_W-1:0] b_arb_burstcount[NUM_BANKS],
output logic [ADDRESS_W-$clog2(NUM_BANKS)-1:0] b_arb_address[NUM_BANKS],
output logic [BYTEENA_W-1:0] b_arb_byteenable[NUM_BANKS],
input logic b_arb_stall[NUM_BANKS],
input logic b_wrp_ack[NUM_BANKS],
input logic b_rrp_datavalid[NUM_BANKS],
input logic [DATA_W-1:0] b_rrp_data[NUM_BANKS]
);
integer i;
always_comb begin
m_arb_stall = 1'b0;
m_wrp_ack = 1'b0;
for (i = 0; i < NUM_BANKS; i = i + 1) begin : b
b_arb_request[i] = m_arb_request & bank_select[i];
b_arb_read[i] = m_arb_read & bank_select[i];
b_arb_enable[i] = m_arb_enable;
b_arb_write[i] = m_arb_write & bank_select[i];
b_arb_writedata[i] = m_arb_writedata;
b_arb_burstcount[i] = m_arb_burstcount;
b_arb_address[i] = m_arb_address[ADDRESS_W-$clog2(NUM_BANKS)-1:0];
b_arb_byteenable[i] = m_arb_byteenable;
m_arb_stall |= b_arb_stall[i] & bank_select[i];
m_wrp_ack |= b_wrp_ack[i];
end
if (NUM_BANKS == 1) begin
m_rrp_data = b_rrp_data[0]; // If only 1 bank, no mux is needed, just pass straight through.
m_rrp_datavalid = b_rrp_datavalid[0];
end else begin
m_rrp_datavalid = 1'b0;
m_rrp_data = '0;
for (i = 0; i < NUM_BANKS; i = i + 1) begin : b_rrp
m_rrp_datavalid |= b_rrp_datavalid[i];
m_rrp_data |= (b_rrp_datavalid[i] ? b_rrp_data[i] : '0);
end
end
end
// Simulation-only assert - should eventually become hardware exception
// Check that only one return path has active data. Colliding rrps
// will lead to incorrect data, and may mean that there is a mismatch in
// arbitration latency.
// synthesis_off
always @(posedge clock) begin
logic [NUM_BANKS-1:0] b_rrp_datavalid_packed;
for (int bitnum = 0; bitnum < NUM_BANKS; bitnum++) begin
b_rrp_datavalid_packed[bitnum] = b_rrp_datavalid[bitnum];
end
#1
assert ($onehot0(b_rrp_datavalid_packed))
else $fatal(0, "Local memory router: rrp collision. Data corrupted");
end
// synthesis_on
endmodule
| 6.737592
|
module - intended for simulation
// until new performance monitor complete.
module acl_ic_local_mem_router_terminator #(
parameter integer DATA_W = 256
)
(
input logic clock,
input logic resetn,
// To each bank
input logic b_arb_request,
input logic b_arb_read,
input logic b_arb_write,
output logic b_arb_stall,
output logic b_wrp_ack,
output logic b_rrp_datavalid,
output logic [DATA_W-1:0] b_rrp_data,
output logic b_invalid_access
);
reg saw_unexpected_access;
reg first_unexpected_was_read;
assign b_arb_stall = 1'b0;
assign b_wrp_ack = 1'b0;
assign b_rrp_datavalid = 1'b0;
assign b_rrp_data = '0;
assign b_invalid_access = saw_unexpected_access;
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
saw_unexpected_access <= 1'b0;
first_unexpected_was_read <= 1'b0;
end
else
begin
if (b_arb_request && ~saw_unexpected_access)
begin
saw_unexpected_access <= 1'b1;
first_unexpected_was_read <= b_arb_read;
// Simulation-only failure message
// synthesis_off
$fatal(0,"Local memory router: accessed bank that isn't connected. Hardware will hang.");
// synthesis_on
end
end
end
endmodule
| 7.407825
|
module acl_ic_master_endpoint #(
parameter integer DATA_W = 32, // > 0
parameter integer BURSTCOUNT_W = 4, // > 0
parameter integer ADDRESS_W = 32, // > 0
parameter integer BYTEENA_W = DATA_W / 8, // > 0
parameter integer ID_W = 1, // > 0
// (NUM_READ_MASTERS + NUM_WRITE_MASTERS) should be > 0
parameter integer NUM_READ_MASTERS = 1, // >= 0
parameter integer NUM_WRITE_MASTERS = 1, // >= 0
parameter integer ID = 0 // [0..2^ID_W-1]
) (
input logic clock,
input logic resetn,
acl_ic_master_intf m_intf,
acl_arb_intf arb_intf,
acl_ic_wrp_intf wrp_intf,
acl_ic_rrp_intf rrp_intf
);
// There shouldn't be any truncation, but be explicit about the id width.
logic [ID_W-1:0] id = ID;
// Pass-through arbitration data.
assign arb_intf.req = m_intf.arb.req;
assign m_intf.arb.stall = arb_intf.stall;
// If only one master, no need to check ID
generate
// Write return path.
if (NUM_WRITE_MASTERS > 1) begin
assign m_intf.wrp.ack = wrp_intf.ack & (wrp_intf.id == id);
end else begin
assign m_intf.wrp.ack = wrp_intf.ack;
end
// Read return path.
if (NUM_READ_MASTERS > 1) begin
assign m_intf.rrp.datavalid = rrp_intf.datavalid & (rrp_intf.id == id);
assign m_intf.rrp.data = rrp_intf.data;
end else begin
assign m_intf.rrp.datavalid = rrp_intf.datavalid;
assign m_intf.rrp.data = rrp_intf.data;
end
endgenerate
endmodule
| 7.198973
|
module acl_ic_rrp_reg (
input logic clock,
input logic resetn,
acl_ic_rrp_intf rrp_in,
(* dont_merge, altera_attribute = "-name auto_shift_register_recognition OFF" *) acl_ic_rrp_intf rrp_out
);
always @(posedge clock or negedge resetn)
if (~resetn) begin
rrp_out.datavalid <= 1'b0;
rrp_out.id <= 'x;
rrp_out.data <= 'x;
end else begin
rrp_out.datavalid <= rrp_in.datavalid;
rrp_out.id <= rrp_in.id;
rrp_out.data <= rrp_in.data;
end
endmodule
| 7.56817
|
module acl_ic_slave_wrp #(
parameter integer DATA_W = 32, // > 0
parameter integer BURSTCOUNT_W = 4, // > 0
parameter integer ADDRESS_W = 32, // > 0
parameter integer BYTEENA_W = DATA_W / 8, // > 0
parameter integer ID_W = 1, // > 0
parameter integer NUM_MASTERS = 1, // > 0
// If the fifo depth is zero, the module will perform the write ack here,
// otherwise it will take the write ack from the input s_writeack.
parameter integer FIFO_DEPTH = 0, // >= 0 (0 disables)
parameter integer PIPELINE = 1 // 0|1
) (
input clock,
input resetn,
acl_arb_intf m_intf,
input logic s_writeack,
acl_ic_wrp_intf wrp_intf,
output logic stall
);
generate
if (NUM_MASTERS > 1) begin
// This slave endpoint may not directly talk to the ACTUAL slave. In
// this case we need a fifo to store which master each write ack should
// go to. If FIFO_DEPTH is 0 then we assume the writeack can be
// generated right here (the way it was done originally)
if (FIFO_DEPTH > 0) begin
// We don't have to worry about bursts, we'll fifo each transaction
// since writeack behaves like readdatavalid
logic rf_empty, rf_full;
acl_ll_fifo #(
.WIDTH(ID_W),
.DEPTH(FIFO_DEPTH)
) write_fifo (
.clk(clock),
.reset(~resetn),
.data_in(m_intf.req.id),
.write(~m_intf.stall & m_intf.req.write),
.data_out(wrp_intf.id),
.read(wrp_intf.ack & ~rf_empty),
.empty(rf_empty),
.full(rf_full)
);
// Register slave writeack to guarantee fifo output is ready
always @(posedge clock or negedge resetn) begin
if (!resetn) wrp_intf.ack <= 1'b0;
else wrp_intf.ack <= s_writeack;
end
assign stall = rf_full;
end else if (PIPELINE == 1) begin
assign stall = 1'b0;
always @(posedge clock or negedge resetn)
if (!resetn) begin
wrp_intf.ack <= 1'b0;
wrp_intf.id <= 'x; // don't need to reset
end else begin
// Always register the id. The ack signal acts as the enable.
wrp_intf.id <= m_intf.req.id;
wrp_intf.ack <= 1'b0;
if (~m_intf.stall & m_intf.req.write)
// A valid write cycle. Ack it.
wrp_intf.ack <= 1'b1;
end
end else begin
assign wrp_intf.id = m_intf.req.id;
assign wrp_intf.ack = ~m_intf.stall & m_intf.req.write;
assign stall = 1'b0;
end
end else // NUM_MASTERS == 1
begin
// Only one master so don't need to check the id.
if (FIFO_DEPTH == 0) begin
assign wrp_intf.ack = ~m_intf.stall & m_intf.req.write;
assign stall = 1'b0;
end else begin
assign wrp_intf.ack = s_writeack;
assign stall = 1'b0;
end
end
endgenerate
endmodule
| 8.764456
|
module acl_ic_to_avm #(
parameter integer DATA_W = 256,
parameter integer BURSTCOUNT_W = 6,
parameter integer ADDRESS_W = 32,
parameter integer BYTEENA_W = DATA_W / 8,
parameter integer ID_W = 1,
parameter integer LATENCY = 0,
parameter integer USE_WRITE_ACK = 0,
parameter integer NO_IDLE_STALL = 0 // De-assert upstream wait_request when the input is idle to allow upstream read/writes to propagate to interface
) (
// Clock/Reset
input logic clock,
input logic resetn,
// AVM interface
output logic avm_enable,
output logic avm_read,
output logic avm_write,
output logic [DATA_W-1:0] avm_writedata,
output logic [BURSTCOUNT_W-1:0] avm_burstcount,
output logic [ADDRESS_W-1:0] avm_address,
output logic [BYTEENA_W-1:0] avm_byteenable,
input logic avm_waitrequest,
input logic avm_readdatavalid,
input logic [DATA_W-1:0] avm_readdata,
input logic avm_writeack, // not a true Avalon signal, so ignore this
// IC interface
input logic ic_arb_request,
input logic ic_arb_enable,
input logic ic_arb_read,
input logic ic_arb_write,
input logic [DATA_W-1:0] ic_arb_writedata,
input logic [BURSTCOUNT_W-1:0] ic_arb_burstcount,
input logic [ADDRESS_W-$clog2(DATA_W / 8)-1:0] ic_arb_address,
input logic [BYTEENA_W-1:0] ic_arb_byteenable,
input logic [ID_W-1:0] ic_arb_id,
output logic ic_arb_stall,
output logic ic_wrp_ack,
output logic ic_rrp_datavalid,
output logic [DATA_W-1:0] ic_rrp_data
);
logic readdatavalid;
logic waitrequest;
assign avm_enable = ic_arb_enable;
assign avm_read = ic_arb_read;
assign avm_write = ic_arb_write;
assign avm_writedata = ic_arb_writedata;
assign avm_burstcount = ic_arb_burstcount;
assign avm_address = {ic_arb_address, {$clog2(DATA_W / 8) {1'b0}}};
assign avm_byteenable = ic_arb_byteenable;
assign ic_arb_stall = NO_IDLE_STALL ? waitrequest && (ic_arb_read || ic_arb_write) : waitrequest;
assign ic_rrp_datavalid = readdatavalid;
assign ic_rrp_data = avm_readdata;
generate
if (USE_WRITE_ACK == 1) begin
assign ic_wrp_ack = avm_writeack;
end else begin
assign ic_wrp_ack = avm_write & ~waitrequest;
end
if (LATENCY == 0) begin
assign readdatavalid = avm_readdatavalid;
assign waitrequest = avm_waitrequest;
end else begin
logic [LATENCY-1:0] readdatavalid_sr;
always @(posedge clock or negedge resetn) begin
if (!resetn) begin
readdatavalid_sr <= {LATENCY{1'b0}};
end else begin
for (integer i = LATENCY - 1; i > 0; i--) begin
readdatavalid_sr[i] <= readdatavalid_sr[i-1];
end
readdatavalid_sr[0] <= avm_read;
end
end
assign readdatavalid = readdatavalid_sr[LATENCY-1];
assign waitrequest = 1'b0;
end
endgenerate
endmodule
| 8.780198
|
module acl_ic_wrp_reg (
input logic clock,
input logic resetn,
acl_ic_wrp_intf wrp_in,
(* dont_merge, altera_attribute = "-name auto_shift_register_recognition OFF" *) acl_ic_wrp_intf wrp_out
);
always @(posedge clock or negedge resetn)
if (~resetn) begin
wrp_out.ack <= 1'b0;
wrp_out.id <= 'x;
end else begin
wrp_out.ack <= wrp_in.ack;
wrp_out.id <= wrp_in.id;
end
endmodule
| 7.382832
|
module acl_iface_ll_fifo (
clk,
reset,
data_in,
write,
data_out,
read,
empty,
full
);
/* Parameters */
parameter WIDTH = 32;
parameter DEPTH = 32;
/* Ports */
input clk;
input reset;
input [WIDTH-1:0] data_in;
input write;
output [WIDTH-1:0] data_out;
input read;
output empty;
output full;
/* Architecture */
// One-hot write-pointer bit (indicates next position to write at),
// last bit indicates the FIFO is full
reg [ DEPTH:0] wptr;
// Replicated copy of the stall / valid logic
reg [ DEPTH:0] wptr_copy /* synthesis dont_merge */;
// FIFO data registers
reg [DEPTH-1:0][WIDTH-1:0] data;
// Write pointer updates:
wire wptr_hold; // Hold the value
wire wptr_dir; // Direction to shift
// Data register updates:
wire [DEPTH-1:0] data_hold; // Hold the value
wire [DEPTH-1:0] data_new; // Write the new data value in
// Write location is constant unless the occupancy changes
assign wptr_hold = !(read ^ write);
assign wptr_dir = read;
// Hold the value unless we are reading, or writing to this
// location
genvar i;
generate
for (i = 0; i < DEPTH; i++) begin : data_mux
assign data_hold[i] = !(read | (write & wptr[i]));
assign data_new[i] = !read | wptr[i+1];
end
endgenerate
// The data registers
generate
for (i = 0; i < DEPTH - 1; i++) begin : data_reg
always @(posedge clk or posedge reset) begin
if (reset == 1'b1) data[i] <= {WIDTH{1'b0}};
else data[i] <= data_hold[i] ? data[i] : data_new[i] ? data_in : data[i+1];
end
end
endgenerate
always @(posedge clk or posedge reset) begin
if (reset == 1'b1) data[DEPTH-1] <= {WIDTH{1'b0}};
else data[DEPTH-1] <= data_hold[DEPTH-1] ? data[DEPTH-1] : data_in;
end
// The write pointer
always @(posedge clk or posedge reset) begin
if (reset == 1'b1) begin
wptr <= {{DEPTH{1'b0}}, 1'b1};
wptr_copy <= {{DEPTH{1'b0}}, 1'b1};
end else begin
wptr <= wptr_hold ? wptr : wptr_dir ? {1'b0, wptr[DEPTH:1]} : {wptr[DEPTH-1:0], 1'b0};
wptr_copy <= wptr_hold ? wptr_copy :
wptr_dir ? {1'b0, wptr_copy[DEPTH:1]} : {wptr_copy[DEPTH-1:0], 1'b0};
end
end
// Outputs
assign empty = wptr_copy[0];
assign full = wptr_copy[DEPTH];
assign data_out = data[0];
endmodule
| 7.246552
|
modules. The spi_master
// selects the data to be transmitted and stores all data received
// from the PmodACL. The data is then made available to the rest of
// the design on the xAxis, yAxis, and zAxis outputs.
//
//
// Inputs:
// CLK 100MHz onboard system clock
// RST Main Reset Controller
// START Signal to initialize a data transfer
// SDI Serial Data In
//
// Outputs:
// SDO Serial Data Out
// SCLK Serial Clock
// SS Slave Select
// xAxis x-axis data received from PmodACL
// yAxis y-axis data received from PmodACL
// zAxis z-axis data received from PmodACL
//
// Revision History:
// Revision 0.01 - File Created (Andrew Skreen)
// Revision 1.00 - Added comments and modified code (Josh Sackos)
////////////////////////////////////////////////////////////////////////////////////
// ===================================================================================
// Define Module, Inputs and Outputs
// ===================================================================================
module ACL_Interface(
CLK,
RST,
SDI,
SDO,
SCLK,
SS,
xAxis,
yAxis,
zAxis
);
// ====================================================================================
// Port Declarations
// ====================================================================================
input CLK;
input RST;
input SDI;
output SDO;
output SCLK;
output SS;
output [9:0] xAxis;
output [9:0] yAxis;
output [9:0] zAxis;
// ====================================================================================
// Parameters, Register, and Wires
// ====================================================================================
wire [9:0] xAxis;
wire [9:0] yAxis;
wire [9:0] zAxis;
wire [15:0] TxBuffer;
wire [7:0] RxBuffer;
wire doneConfigure;
wire done;
wire transmit;
// ===================================================================================
// Implementation
// ===================================================================================
//-----------------------------------------------
// Generates a 5Hz Data Transfer Request Signal
//-----------------------------------------------
ClkDiv_5Hz genStart(
.CLK(CLK),
.RST(RST),
.CLKOUT(start)
);
//-------------------------------------------------------------------------
// Controls SPI Interface, Stores Received Data, and Controls Data to Send
//-------------------------------------------------------------------------
SPImaster C0(
.rst(RST),
.start(start),
.clk(CLK),
.transmit(transmit),
.txdata(TxBuffer),
.rxdata(RxBuffer),
.done(done),
.x_axis_data(xAxis),
.y_axis_data(yAxis),
.z_axis_data(zAxis)
);
//-------------------------------------------------------------------------
// Produces Timing Signal, Reads ACL Data, and Writes Data to ACL
//-------------------------------------------------------------------------
SPIinterface C1(
.sdi(SDI),
.sdo(SDO),
.rst(RST),
.clk(CLK),
.sclk(SCLK),
.txbuffer(TxBuffer),
.rxbuffer(RxBuffer),
.done_out(done),
.transmit(transmit)
);
//-------------------------------------------------------------------------
// Enables/Disables PmodACL Communication
//-------------------------------------------------------------------------
slaveSelect C2(
.clk(CLK),
.ss(SS),
.done(done),
.transmit(transmit),
.rst(RST)
);
endmodule
| 8.292332
|
module acl_ll_fifo (
clk,
reset,
data_in,
write,
data_out,
read,
empty,
full,
almost_full
);
/* Parameters */
parameter WIDTH = 32;
parameter DEPTH = 32;
parameter ALMOST_FULL_VALUE = 0;
/* Ports */
input clk;
input reset;
input [WIDTH-1:0] data_in;
input write;
output [WIDTH-1:0] data_out;
input read;
output empty;
output full;
output almost_full;
/* Architecture */
// One-hot write-pointer bit (indicates next position to write at),
// last bit indicates the FIFO is full
reg [ DEPTH:0] wptr;
// Replicated copy of the stall / valid logic
reg [ DEPTH:0] wptr_copy /* synthesis dont_merge */;
// FIFO data registers
reg [DEPTH-1:0][WIDTH-1:0] data;
// Write pointer updates:
wire wptr_hold; // Hold the value
wire wptr_dir; // Direction to shift
// Data register updates:
wire [DEPTH-1:0] data_hold; // Hold the value
wire [DEPTH-1:0] data_new; // Write the new data value in
// Write location is constant unless the occupancy changes
assign wptr_hold = !(read ^ write);
assign wptr_dir = read;
// Hold the value unless we are reading, or writing to this
// location
genvar i;
generate
for (i = 0; i < DEPTH; i++) begin : data_mux
assign data_hold[i] = !(read | (write & wptr[i]));
assign data_new[i] = !read | wptr[i+1];
end
endgenerate
// The data registers
generate
for (i = 0; i < DEPTH - 1; i++) begin : data_reg
always @(posedge clk or posedge reset) begin
if (reset == 1'b1) data[i] <= {WIDTH{1'b0}};
else data[i] <= data_hold[i] ? data[i] : data_new[i] ? data_in : data[i+1];
end
end
endgenerate
always @(posedge clk or posedge reset) begin
if (reset == 1'b1) data[DEPTH-1] <= {WIDTH{1'b0}};
else data[DEPTH-1] <= data_hold[DEPTH-1] ? data[DEPTH-1] : data_in;
end
// The write pointer
always @(posedge clk or posedge reset) begin
if (reset == 1'b1) begin
wptr <= {{DEPTH{1'b0}}, 1'b1};
wptr_copy <= {{DEPTH{1'b0}}, 1'b1};
end else begin
wptr <= wptr_hold ? wptr : wptr_dir ? {1'b0, wptr[DEPTH:1]} : {wptr[DEPTH-1:0], 1'b0};
wptr_copy <= wptr_hold ? wptr_copy :
wptr_dir ? {1'b0, wptr_copy[DEPTH:1]} : {wptr_copy[DEPTH-1:0], 1'b0};
end
end
// Outputs
assign empty = wptr_copy[0];
assign full = wptr_copy[DEPTH];
assign almost_full = |wptr_copy[DEPTH:ALMOST_FULL_VALUE];
assign data_out = data[0];
endmodule
| 7.025547
|
module acl_ll_ram_fifo #(
parameter integer DATA_WIDTH = 32, // >0
parameter integer DEPTH = 32 // >3
) (
input logic clock,
input logic resetn,
input logic [DATA_WIDTH-1:0] data_in,
output logic [DATA_WIDTH-1:0] data_out,
input logic valid_in,
output logic valid_out,
input logic stall_in,
output logic stall_out,
output logic empty,
output logic full
);
localparam SEL_RAM = 0;
localparam SEL_LL = 1;
// Three FIFOs:
// 1. data - RAM FIFO (normal latency)
// 2. data - LL REG FIFO
// 3. selector - LL REG FIFO
//
// Selector determines which of the two data FIFOs to select the current
// output from.
//
// TODO Implementation note:
// It's probably possible to use a more compact storage mechanism than
// a FIFO for the selector because the sequence of selector values
// should be highly compressible (e.g. long sequences of SEL_RAM). The
// selector FIFO can probably be replaced with a small number of counters.
// A future enhancement.
logic [DATA_WIDTH-1:0] ram_data_in, ram_data_out;
logic ram_valid_in, ram_valid_out, ram_stall_in, ram_stall_out;
logic [DATA_WIDTH-1:0] ll_data_in, ll_data_out;
logic ll_valid_in, ll_valid_out, ll_stall_in, ll_stall_out;
logic sel_data_in, sel_data_out;
logic sel_valid_in, sel_valid_out, sel_stall_in, sel_stall_out;
// Top-level outputs.
assign data_out = sel_data_out == SEL_LL ? ll_data_out : ram_data_out;
assign valid_out = sel_valid_out; // the required ll_valid_out/ram_valid_out must also be asserted
assign stall_out = sel_stall_out;
// RAM FIFO.
acl_data_fifo #(
.DATA_WIDTH(DATA_WIDTH),
.DEPTH(DEPTH - 3),
.IMPL("ram")
) ram_fifo (
.clock(clock),
.resetn(resetn),
.data_in(ram_data_in),
.data_out(ram_data_out),
.valid_in(ram_valid_in),
.valid_out(ram_valid_out),
.stall_in(ram_stall_in),
.stall_out(ram_stall_out)
);
assign ram_data_in = data_in;
assign ram_valid_in = valid_in & ll_stall_out; // only write to RAM FIFO if LL FIFO is stalled
assign ram_stall_in = (sel_data_out != SEL_RAM) | stall_in;
// Low-latency FIFO.
acl_data_fifo #(
.DATA_WIDTH(DATA_WIDTH),
.DEPTH(3),
.IMPL("ll_reg")
) ll_fifo (
.clock(clock),
.resetn(resetn),
.data_in(ll_data_in),
.data_out(ll_data_out),
.valid_in(ll_valid_in),
.valid_out(ll_valid_out),
.stall_in(ll_stall_in),
.stall_out(ll_stall_out)
);
assign ll_data_in = data_in;
assign ll_valid_in = valid_in & ~ll_stall_out; // write to LL FIFO if it is not stalled
assign ll_stall_in = (sel_data_out != SEL_LL) | stall_in;
// Selector FIFO.
acl_data_fifo #(
.DATA_WIDTH(1),
.DEPTH(DEPTH),
.IMPL("ll_reg")
) sel_fifo (
.clock(clock),
.resetn(resetn),
.data_in(sel_data_in),
.data_out(sel_data_out),
.valid_in(sel_valid_in),
.valid_out(sel_valid_out),
.stall_in(sel_stall_in),
.stall_out(sel_stall_out),
.empty(empty),
.full(full)
);
assign sel_data_in = ll_valid_in ? SEL_LL : SEL_RAM;
assign sel_valid_in = valid_in;
assign sel_stall_in = stall_in;
endmodule
| 9.272834
|
module _acl_mem1x_shiftreg (
D,
clock,
resetn,
enable,
Q
);
parameter WIDTH = 32;
parameter DEPTH = 1;
input logic [WIDTH-1:0] D;
input logic clock, resetn, enable;
output logic [WIDTH-1:0] Q;
reg [DEPTH-1:0][WIDTH-1:0] local_ffs /* synthesis preserve */;
always @(posedge clock or negedge resetn)
if (!resetn) local_ffs <= '0;
else if (enable) local_ffs <= {local_ffs[DEPTH-2:0], D};
assign Q = local_ffs[DEPTH-1];
endmodule
| 7.517557
|
module _acl_mem2x_shiftreg (
D,
clock,
resetn,
enable,
Q
);
parameter WIDTH = 32;
parameter DEPTH = 1;
input [WIDTH-1:0] D;
input clock, resetn, enable;
output [WIDTH-1:0] Q;
reg [DEPTH-1:0][WIDTH-1:0] local_ffs /* synthesis preserve */;
always @(posedge clock or negedge resetn)
if (!resetn) local_ffs <= '0;
else if (enable) local_ffs <= {local_ffs[DEPTH-2:0], D};
assign Q = local_ffs[DEPTH-1];
endmodule
| 7.880124
|
module acl_mem_staging_reg #(
parameter WIDTH = 32,
parameter LOW_LATENCY = 0 //used by mem1x when the latency through the memory is only 1 cycle
) (
input wire clk,
input wire resetn,
input wire enable,
input wire [WIDTH-1:0] rdata_in,
output logic [WIDTH-1:0] rdata_out
);
generate
if (LOW_LATENCY) begin
reg [WIDTH-1:0] rdata_r;
reg enable_r;
always @(posedge clk or negedge resetn) begin
if (!resetn) begin
enable_r <= 1'b1;
end else begin
enable_r <= enable;
if (enable_r) begin
rdata_r <= rdata_in;
end
end
end
assign rdata_out = enable_r ? rdata_in : rdata_r;
end else begin
reg [WIDTH-1:0] rdata_r[0:1];
reg [1:0] rdata_vld_r;
reg enable_r;
always @(posedge clk or negedge resetn) begin
if (!resetn) begin
rdata_vld_r <= 2'b00;
enable_r <= 1'b0;
end else begin
if (~rdata_vld_r[1] | enable) begin
enable_r <= enable;
rdata_vld_r[0] <= ~enable | (~rdata_vld_r[1] & ~enable_r & enable); //use the first staging register if disabled, or re-enabled after only one cycle
rdata_vld_r[1] <= rdata_vld_r[0] & (rdata_vld_r[1] | ~enable);
rdata_r[1] <= rdata_r[0];
rdata_r[0] <= rdata_in;
end
end
end
always @(*) begin
case (rdata_vld_r)
2'b00: rdata_out = rdata_in;
2'b01: rdata_out = rdata_r[0];
2'b10: rdata_out = rdata_r[1];
2'b11: rdata_out = rdata_r[1];
default: rdata_out = {WIDTH{1'bx}};
endcase
end
end
endgenerate
endmodule
| 9.445486
|
module acl_pipeline (
clock,
resetn,
data_in,
valid_out,
stall_in,
stall_out,
valid_in,
data_out,
initeration_in,
initeration_stall_out,
initeration_valid_in,
not_exitcond_in,
not_exitcond_stall_out,
not_exitcond_valid_in,
pipeline_valid_out,
pipeline_stall_in,
exiting_valid_out
);
parameter FIFO_DEPTH = 1;
parameter string STYLE = "SPECULATIVE"; // "NON_SPECULATIVE"/"SPECULATIVE"
parameter ENABLED = 0;
input clock, resetn, stall_in, valid_in, initeration_valid_in, not_exitcond_valid_in, pipeline_stall_in;
output stall_out, valid_out, initeration_stall_out, not_exitcond_stall_out, pipeline_valid_out;
input data_in, initeration_in, not_exitcond_in;
output data_out;
output exiting_valid_out;
generate
// Instantiate 2 pops and 1 push
if (STYLE == "SPECULATIVE") begin
wire valid_pop1, valid_pop2;
wire stall_push, stall_pop2;
wire data_pop2, data_push;
acl_pop pop1 (
.clock(clock),
.resetn(resetn),
.dir(data_in),
.predicate(1'b0),
.data_in(1'b1),
.valid_out(valid_pop1),
.stall_in(stall_pop2),
.stall_out(stall_out),
.valid_in(valid_in),
.data_out(data_pop2),
.feedback_in(initeration_in),
.feedback_valid_in(initeration_valid_in),
.feedback_stall_out(initeration_stall_out)
);
defparam pop1.DATA_WIDTH = 1;
acl_pop pop2 (
.clock(clock),
.resetn(resetn),
.dir(data_pop2),
.predicate(1'b0),
.data_in(1'b0),
.valid_out(valid_pop2),
.stall_in(stall_push),
.stall_out(stall_pop2),
.valid_in(valid_pop1),
.data_out(data_push),
.feedback_in(~not_exitcond_in),
.feedback_valid_in(not_exitcond_valid_in),
.feedback_stall_out(not_exitcond_stall_out)
);
defparam pop2.DATA_WIDTH = 1;
wire p_out, p_valid_out, p_stall_in;
acl_push push (
.clock(clock),
.resetn(resetn),
.dir(1'b1),
.predicate(1'b0),
.data_in(~data_push),
.valid_out(valid_out),
.stall_in(stall_in),
.stall_out(stall_push),
.valid_in(valid_pop2),
.data_out(data_out),
.feedback_out(p_out),
.feedback_valid_out(p_valid_out),
.feedback_stall_in(p_stall_in)
);
// signal when to spawn a new iteration
assign pipeline_valid_out = p_out & p_valid_out;
assign p_stall_in = pipeline_stall_in;
// signal when the last iteration is exiting
assign exiting_valid_out = ~p_out & p_valid_out & ~pipeline_stall_in;
defparam push.DATA_WIDTH = 1; defparam push.FIFO_DEPTH = FIFO_DEPTH;
defparam push.ENABLED = ENABLED;
end // Instantiate 1 pop and 1 push
else begin
//////////////////////////////////////////////////////
// If there is no speculation, directly connect
// exit condition to valid
wire valid_pop2;
wire stall_push;
wire data_push;
wire p_out, p_valid_out, p_stall_in;
assign p_out = not_exitcond_in;
assign p_valid_out = not_exitcond_valid_in;
assign not_exitcond_stall_out = p_stall_in;
acl_staging_reg asr (
.clk(clock),
.reset(~resetn),
.i_valid(valid_in),
.o_stall(stall_out),
.o_valid(valid_out),
.i_stall(stall_in)
);
// signal when to spawn a new iteration
assign pipeline_valid_out = p_out & p_valid_out;
assign p_stall_in = pipeline_stall_in;
// signal when the last iteration is exiting
assign exiting_valid_out = ~p_out & p_valid_out & ~pipeline_stall_in;
assign initeration_stall_out = 1'b0; // never stall
end
endgenerate
endmodule
| 8.380137
|
module acl_pop (
clock,
resetn,
// input stream from kernel pipeline
dir,
valid_in,
data_in,
stall_out,
predicate,
// downstream, to kernel pipeline
valid_out,
stall_in,
data_out,
// feedback downstream, from feedback acl_push
feedback_in,
feedback_valid_in,
feedback_stall_out
);
parameter DATA_WIDTH = 32;
parameter string STYLE = "REGULAR"; // REGULAR vs COALESCE
parameter COALESCE_DISTANCE = 1;
parameter INF_LOOP = 0;
// this will pop garbage off of the feedback
localparam POP_GARBAGE = STYLE == "COALESCE" ? 1 : 0;
input clock, resetn, stall_in, valid_in, feedback_valid_in;
output stall_out, valid_out, feedback_stall_out;
input [DATA_WIDTH-1:0] data_in;
input dir;
input predicate;
output [DATA_WIDTH-1:0] data_out;
input [DATA_WIDTH-1:0] feedback_in;
localparam DISTANCE_WIDTH = ((POP_GARBAGE == 1) && (COALESCE_DISTANCE > 1)) ? $clog2(
COALESCE_DISTANCE
) : 1;
wire feedback_downstream, data_downstream;
wire pop_garbage;
wire actual_dir;
generate
if (STYLE == "BYPASS") begin
// Turn this pop into wires
assign valid_out = valid_in;
assign stall_out = stall_in;
assign feedback_stall_out = 1'b0;
assign data_out = data_in;
end else begin
if (POP_GARBAGE == 0) begin
// For non-coalesced pops, we don't need to generate the
// counter logic. Though quartus probably would have sweeped
// away the extraneous logic, this makes it clear.
assign pop_garbage = 0;
end else begin
reg [DISTANCE_WIDTH-1:0] garbage_count;
reg pop_garbage_r;
always @(posedge clock or negedge resetn) begin
if (!resetn) begin
pop_garbage_r = 0;
end
else if ( ( garbage_count == {(DISTANCE_WIDTH){1'b0}} ) && (valid_out & ~stall_in & ~predicate) ) begin
// If the garbage count will hit -1 next cycle then we can start popping garbage
pop_garbage_r = POP_GARBAGE;
end
end
assign pop_garbage = pop_garbage_r;
always @(posedge clock or negedge resetn) begin
if (!resetn) begin
garbage_count = COALESCE_DISTANCE - 1;
end else if (valid_out & ~stall_in & ~predicate) begin
// If we're predicated then we can't decrement the garbage count this cycle because valid data wasn't fed into the push
garbage_count = garbage_count - 1'b1;
end
end
end
if (INF_LOOP == 1) begin
// If we're in an infinite loop where feedback_in clears to the value of data_in, we don't need
// to ever select data_in. Case:432276
assign actual_dir = 1'b0;
end else begin
assign actual_dir = dir;
end
assign feedback_downstream = valid_in & ~actual_dir & feedback_valid_in;
assign data_downstream = valid_in & actual_dir;
assign valid_out = feedback_downstream | ( data_downstream & (~pop_garbage | feedback_valid_in ) ) ;
assign data_out = ~actual_dir ? feedback_in : data_in;
//assign stall_out = stall_in;
//assign stall_out = valid_in & ~((feedback_downstream | data_downstream) & ~stall_in);
// assign stall_out = ~((feedback_downstream | data_downstream) & ~stall_in);
// stall upstream if
// downstream is stalling (stall_in)
// I'm waiting for data from feedback (valid_in&~actual_dir&~feedback_valid_in)
assign stall_out = ( valid_in & ( ( ~actual_dir & ~feedback_valid_in ) | ( actual_dir & ~feedback_valid_in & pop_garbage ) ) ) | stall_in;
// don't accept data if:
// downstream cannot accept data (stall_in)
// data from upstream is selected (data_downstream)
// no thread exists to read data (~valid_in)
// predicate is high
assign feedback_stall_out = stall_in | (data_downstream & ~pop_garbage) | ~valid_in | predicate;
end
endgenerate
endmodule
| 7.557809
|
module records profiling information. It is connected to the desired
// pipeline ports that are needed to be profiled.
// cntl_in signal determines when a profiling register is updated.
// incr_in signal determines the increment value for each counter.
// NUM_COUNTERS of profiling registers are instantiated. When the profile_shift
// signal is high, profiling registers are shifted out DAISY_WIDTH bits (64-bits) at a time.
//
module acl_profiler
(
clock,
resetn,
enable,
profile_shift,
incr_cntl,
incr_val,
daisy_out
);
parameter COUNTER_WIDTH=64;
parameter INCREMENT_WIDTH=32;
parameter NUM_COUNTERS=4;
parameter TOTAL_INCREMENT_WIDTH=INCREMENT_WIDTH * NUM_COUNTERS;
parameter DAISY_WIDTH=64;
input clock;
input resetn;
input enable;
input profile_shift;
input [NUM_COUNTERS-1:0] incr_cntl;
input [TOTAL_INCREMENT_WIDTH-1:0] incr_val;
output [DAISY_WIDTH-1:0] daisy_out;
// if there are NUM_COUNTER counters, there are NUM_COUNTER-1 connections between them
wire [NUM_COUNTERS-2:0][DAISY_WIDTH-1:0] shift_wire;
wire [31:0] data_out [0:NUM_COUNTERS-1];// for debugging, always 32-bit for ease of modelsim
genvar n;
generate
for(n=0; n<NUM_COUNTERS; n++)
begin : counter_n
if(n == 0)
acl_profile_counter #(
.COUNTER_WIDTH( COUNTER_WIDTH ),
.INCREMENT_WIDTH( INCREMENT_WIDTH ),
.DAISY_WIDTH( DAISY_WIDTH )
) counter (
.clock( clock ),
.resetn( resetn ),
.enable( enable ),
.shift( profile_shift ),
.incr_cntl( incr_cntl[n] ),
.shift_in( shift_wire[n] ),
.incr_val( incr_val[ ((n+1)*INCREMENT_WIDTH-1) : (n*INCREMENT_WIDTH) ] ),
.data_out( data_out[ n ] ),
.shift_out( daisy_out )
);
else if(n == NUM_COUNTERS-1)
acl_profile_counter #(
.COUNTER_WIDTH( COUNTER_WIDTH ),
.INCREMENT_WIDTH( INCREMENT_WIDTH ),
.DAISY_WIDTH( DAISY_WIDTH )
) counter (
.clock( clock ),
.resetn( resetn ),
.enable( enable ),
.shift( profile_shift ),
.incr_cntl( incr_cntl[n] ),
.shift_in( {DAISY_WIDTH{1'b0}} ),
.incr_val( incr_val[ ((n+1)*INCREMENT_WIDTH-1) : (n*INCREMENT_WIDTH) ] ),
.data_out( data_out[ n ] ),
.shift_out( shift_wire[n-1] )
);
else
acl_profile_counter #(
.COUNTER_WIDTH( COUNTER_WIDTH ),
.INCREMENT_WIDTH( INCREMENT_WIDTH ),
.DAISY_WIDTH( DAISY_WIDTH )
) counter (
.clock( clock ),
.resetn( resetn ),
.enable( enable ),
.shift( profile_shift ),
.incr_cntl( incr_cntl[n] ),
.shift_in( shift_wire[n] ),
.incr_val( incr_val[ ((n+1)*INCREMENT_WIDTH-1) : (n*INCREMENT_WIDTH) ] ),
.data_out( data_out[ n ] ),
.shift_out( shift_wire[n-1] )
);
end
endgenerate
endmodule
| 7.280308
|
module acl_profile_counter (
clock,
resetn,
enable,
shift,
incr_cntl,
shift_in,
incr_val,
data_out,
shift_out
);
parameter COUNTER_WIDTH = 64;
parameter INCREMENT_WIDTH = 32;
parameter DAISY_WIDTH = 64;
input clock;
input resetn;
input enable;
input shift;
input incr_cntl;
input [DAISY_WIDTH-1:0] shift_in;
input [INCREMENT_WIDTH-1:0] incr_val;
output [31:0] data_out; // for debugging, always 32-bit for ease of modelsim
output [DAISY_WIDTH-1:0] shift_out;
reg [COUNTER_WIDTH-1:0] counter;
always @(posedge clock or negedge resetn) begin
if (!resetn) counter <= {COUNTER_WIDTH{1'b0}};
else if (shift) // shift by DAISY_WIDTH bits
counter <= {counter, shift_in};
else if (enable && incr_cntl) // increment counter
counter <= counter + incr_val;
end
assign data_out = counter;
assign shift_out = {counter, shift_in} >> COUNTER_WIDTH;
endmodule
| 6.820998
|
module acl_reset_wire (
input clock,
input resetn,
output o_resetn
);
assign o_resetn = resetn;
endmodule
| 6.811904
|
module acl_shift_register (
clock,
resetn,
clear,
enable,
Q,
D
);
parameter WIDTH = 32;
parameter STAGES = 1;
input clock, resetn, clear, enable;
input [WIDTH-1:0] D;
output [WIDTH-1:0] Q;
wire clock, resetn, clear, enable;
wire [WIDTH-1:0] D;
reg [WIDTH-1:0] stages[STAGES-1:0];
generate
if (STAGES == 0) begin
assign Q = D;
end else begin
genvar istage;
for (istage = 0; istage < STAGES; istage = istage + 1) begin : stages_loop
always @(posedge clock or negedge resetn) begin
if (!resetn) begin
stages[istage] <= {(WIDTH) {1'b0}};
end else if (clear) begin
stages[istage] <= {(WIDTH) {1'b0}};
end else if (enable) begin
if (istage == 0) begin
stages[istage] <= D;
end else begin
stages[istage] <= stages[istage-1];
end
end
end
end
assign Q = stages[STAGES-1];
end
endgenerate
endmodule
| 7.732309
|
module acl_staging_reg (
clk,
reset,
i_data,
i_valid,
o_stall,
o_data,
o_valid,
i_stall
);
/*************
* Parameters *
*************/
parameter WIDTH = 32;
/********
* Ports *
********/
// Standard global signals
input clk;
input reset;
// Upstream interface
input [WIDTH-1:0] i_data;
input i_valid;
output o_stall;
// Downstream interface
output [WIDTH-1:0] o_data;
output o_valid;
input i_stall;
/***************
* Architecture *
***************/
reg [WIDTH-1:0] r_data;
reg r_valid;
// Upstream
assign o_stall = r_valid;
// Downstream
assign o_data = (r_valid) ? r_data : i_data;
assign o_valid = (r_valid) ? r_valid : i_valid;
// Storage reg
always @(posedge clk or posedge reset) begin
if (reset == 1'b1) begin
r_valid <= 1'b0;
r_data <= 'x; // don't need to reset
end else begin
if (~r_valid) r_data <= i_data;
r_valid <= i_stall && (r_valid || i_valid);
end
end
endmodule
| 7.452121
|
module acl_start_signal_chain_element #(
parameter int ASYNC_RESET = 1, // how do we use reset: 1 means registers are reset asynchronously, 0 means registers are reset synchronously
parameter int SYNCHRONIZE_RESET = 0 // based on how reset gets to us, what do we need to do: 1 means synchronize reset before consumption (if reset arrives asynchronously), 0 means passthrough (managed externally)
) (
input wire clock,
input wire resetn,
input wire start_in,
output reg start_kernel,
output reg start_finish_detector,
output reg start_finish_chain_element,
output reg start_chain
);
logic aclrn, sclrn;
acl_reset_handler #(
.ASYNC_RESET (ASYNC_RESET),
.USE_SYNCHRONIZER (SYNCHRONIZE_RESET),
.SYNCHRONIZE_ACLRN(SYNCHRONIZE_RESET),
.PIPE_DEPTH (1),
.NUM_COPIES (1)
) acl_reset_handler_inst (
.clk (clock),
.i_resetn (resetn),
.o_aclrn (aclrn),
.o_resetn_synchronized(),
.o_sclrn (sclrn)
);
always @(posedge clock or negedge aclrn) begin
if (~aclrn) begin
start_chain <= 1'b0;
end else begin
start_chain <= start_in;
if (~sclrn) begin
start_chain <= 1'b0;
end
end
end
always @(posedge clock or negedge aclrn) begin
if (~aclrn) begin
start_kernel <= 1'b0;
start_finish_detector <= 1'b0;
start_finish_chain_element <= 1'b0;
end else begin
start_kernel <= start_chain;
start_finish_detector <= start_chain;
start_finish_chain_element <= start_chain;
if (~sclrn) begin
start_kernel <= 1'b0;
start_finish_detector <= 1'b0;
start_finish_chain_element <= 1'b0;
end
end
end
endmodule
| 8.339949
|
module captures the relative frequency with which each bit in 'value'
* toggles. This can be useful for detecting address patterns for example.
*
* Eg. (in hex)
* Linear: 1ff ff 80 40 20 10 08 04 02 1 0 0 0 ...
* Linear predicated: 1ff ff 80 40 00 00 00 20 10 8 4 2 1 0 0 0 ...
* Strided: 00 00 ff 80 40 20 10 08 04 02 1 0 0 0 ...
* Random: ff ff ff ff ff ff ff ff ff ...
*
* The counters that track the toggle rates automatically get divided by 2 once
* any of their values comes close to overflowing. Hence the toggle rates are
* relative, and comparable only within a single module instance.
*
* The last counter (count[WIDTH]) is a saturating counter storing the number of
* times a scaledown was performed. If you assume the relative rates don't
* change between scaledowns, this can be used to approximate absolute toggle
* rates (which can be compared against rates from another instance).
*****************/
module acl_toggle_detect
#(
parameter WIDTH=13, // Width of input signal in bits
parameter COUNTERWIDTH=10 // in bits, MUST be greater than 3
)
(
input logic clk,
input logic resetn,
input logic valid,
input logic [WIDTH-1:0] value,
output logic [COUNTERWIDTH-1:0] count[WIDTH+1]
);
/******************
* LOCAL PARAMETERS
*******************/
/******************
* SIGNALS
*******************/
logic [WIDTH-1:0] last_value;
logic [WIDTH-1:0] bits_toggled;
logic scaledown;
/******************
* ARCHITECTURE
*******************/
always@(posedge clk or negedge resetn)
if (!resetn)
last_value<={WIDTH{1'b0}};
else if (valid)
last_value<=value;
// Compute which bits toggled via XOR
always@(posedge clk or negedge resetn)
if (!resetn)
bits_toggled<={WIDTH{1'b0}};
else if (valid)
bits_toggled<=value^last_value;
else
bits_toggled<={WIDTH{1'b0}};
// Create one counter for each bit in value. Increment the respective
// counter if that bit toggled.
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1)
begin:counters
always@(posedge clk or negedge resetn)
if (!resetn)
count[i] <= {COUNTERWIDTH{1'b0}};
else if (bits_toggled[i] && scaledown)
count[i] <= (count[i] + 2'b1) >> 1;
else if (bits_toggled[i])
count[i] <= count[i] + 2'b1;
else if (scaledown)
count[i] <= count[i] >> 1;
end
endgenerate
// Count total number of times scaled down - saturating counter
// This can be used to approximate absolute toggle rates
always@(posedge clk or negedge resetn)
if (!resetn)
count[WIDTH] <= 1'b0;
else if (scaledown && count[WIDTH]!={COUNTERWIDTH{1'b1}})
count[WIDTH] <= count[WIDTH] + 2'b1;
// If any counter value's top 3 bits are 1s, scale down all counter values
integer j;
always@(posedge clk or negedge resetn)
if (!resetn)
scaledown <= 1'b0;
else if (scaledown)
scaledown <= 1'b0;
else
for (j = 0; j < WIDTH; j = j + 1)
if (&count[j][COUNTERWIDTH-1:COUNTERWIDTH-3])
scaledown <= 1'b1;
endmodule
| 8.621096
|
module acl_token_fifo_counter #(
parameter integer DEPTH = 32, // >0
parameter integer STRICT_DEPTH = 1, // 0|1
parameter integer ALLOW_FULL_WRITE = 0 // 0|1
) (
clock,
resetn,
data_out, // the width of this signal is set by this module, it is the
// responsibility of the top module to make sure the signal
// widths match across this interface.
valid_in,
valid_out,
stall_in,
stall_out,
empty,
full
);
// This fifo is based on acl_valid_fifo
// However, there are 2 differences:
// 1. The fifo is intialized as full
// 2. We keep another counter to serve as the actual token
// STRICT_DEPTH increases FIFO depth to a power of 2 + 1 depth.
// No data, so just build a counter to count the number of valids stored in this "FIFO".
//
// The counter is constructed to count up to a MINIMUM value of DEPTH entries.
// * Logical range of the counter C0 is [0, DEPTH].
// * empty = (C0 <= 0)
// * full = (C0 >= DEPTH)
//
// To have efficient detection of the empty condition (C0 == 0), the range is offset
// by -1 so that a negative number indicates empty.
// * Logical range of the counter C1 is [-1, DEPTH-1].
// * empty = (C1 < 0)
// * full = (C1 >= DEPTH-1)
// The size of counter C1 is $clog2((DEPTH-1) + 1) + 1 => $clog2(DEPTH) + 1.
//
// To have efficient detection of the full condition (C1 >= DEPTH-1), change the
// full condition to C1 == 2^$clog2(DEPTH-1), which is DEPTH-1 rounded up
// to the next power of 2. This is only done if STRICT_DEPTH == 0, otherwise
// the full condition is comparison vs. DEPTH-1.
// * Logical range of the counter C2 is [-1, 2^$clog2(DEPTH-1)]
// * empty = (C2 < 0)
// * full = (C2 == 2^$clog2(DEPTH - 1))
// The size of counter C2 is $clog2(DEPTH-1) + 2.
// * empty = MSB
// * full = ~[MSB] & [MSB-1]
localparam COUNTER_WIDTH = (STRICT_DEPTH == 0) ? ((DEPTH > 1 ? $clog2(
DEPTH - 1
) : 0) + 2) : ($clog2(
DEPTH
) + 1);
input clock;
input resetn;
output [COUNTER_WIDTH-1:0] data_out;
input valid_in;
output valid_out;
input stall_in;
output stall_out;
output empty;
output full;
logic [COUNTER_WIDTH - 1:0] valid_counter /* synthesis maxfan=1 dont_merge */;
logic incr, decr;
wire [1:0] valid_counter_update;
wire [COUNTER_WIDTH - 1:0] valid_counter_update_extended;
// The logical range for the token is [0,REAL_DEPTH-1], where REAL_DEPTH
// is the actual depth of the fifo taking STRICT_DEPTH into account
// This counter is 1-bit less wide than valid_counter because it is
// unsigned
logic [COUNTER_WIDTH - 2:0] token;
logic token_max;
assign data_out = token;
assign token_max = (STRICT_DEPTH == 0) ? (~token[$bits(
token
)-1] & token[$bits(
token
)-2]) : (token == DEPTH - 1);
assign empty = valid_counter[$bits(valid_counter)-1];
assign full = (STRICT_DEPTH == 0) ? (~valid_counter[$bits(
valid_counter
)-1] & valid_counter[$bits(
valid_counter
)-2]) : (valid_counter == DEPTH - 1);
assign incr = valid_in & ~stall_out; // push
assign decr = valid_out & ~stall_in; // pop
assign valid_out = ~empty;
assign stall_out = ALLOW_FULL_WRITE ? (full & stall_in) : full;
assign valid_counter_update = incr - decr;
assign valid_counter_update_extended = $signed(valid_counter_update);
always @(posedge clock or negedge resetn)
if (!resetn) begin
valid_counter <= (STRICT_DEPTH == 0) ? (2 ^ $clog2(DEPTH - 1)) : DEPTH - 1; // full
token <= 0;
end else begin
valid_counter <= valid_counter + valid_counter_update_extended;
if (decr) // increment token, if popping
token <= token_max ? 0 : token + 1;
end
endmodule
| 8.202386
|
module has two interface points: the entry point
// and the exit point. The purpose of the module is to ensure that there are
// no more than WG_LIMIT work-groups in the pipeline between the entry and
// exit points. The limiter also remaps the kernel-level work-group id into
// a local work-group id; this is needed because in general the kernel-level
// work-group id space is larger than the local work-group id space. It is
// assumed that any work-item that passes through the entry point will pass
// through the exit point at some point.
//
// The ordering of the work-groups affects the implementation. In particular,
// if the work-group order is the same through the entry point and the exit
// point, the implementation is simple. This is referred to as work-group FIFO
// (first-in-first-out) order. It remains a TODO to support work-group
// non-FIFO order (through the exit point).
//
// The work-group order does NOT matter if WG_LIMIT >= KERNEL_WG_LIMIT.
// In this configuration, the real limiter is at the kernel-level and this
// work-group limiter does not do anything useful. It does match the latency
// specifiction though so that the latency and capacity of the core is the
// same regardless of the configuration.
//
// Latency/capacity:
// Through entry: 1 cycle
// Through exit: 1 cycle
module acl_work_group_limiter_dspba(
clock,
resetn,
wg_size,
// Limiter entry
entry_valid_in,
entry_k_wgid,
entry_stall_out,
entry_valid_out,
entry_l_wgid,
entry_stall_in,
// Limiter exit
exit_valid_in,
exit_stall_out,
exit_valid_out,
exit_stall_in
);
parameter WG_LIMIT = 1;
parameter KERNEL_WG_LIMIT = 1;
parameter MAX_WG_SIZE = 1;
parameter WG_FIFO_ORDER = 1;
function integer my_max;
input integer a;
input integer b;
begin
my_max = (a > b) ? a : b;
end
endfunction
localparam MAX_WG_SIZE_WIDTH = $clog2({1'b0, MAX_WG_SIZE} + 1);
localparam KWG_BIT_LIMIT = my_max($clog2(KERNEL_WG_LIMIT),1);
localparam WG_BIT_LIMIT = my_max($clog2(WG_LIMIT),1);
input logic clock;
input logic resetn;
input logic [31:0] wg_size;
// Limiter entry
input logic entry_valid_in;
input logic [31:0] entry_k_wgid; // not used if WG_FIFO_ORDER==1
output logic entry_stall_out;
output logic entry_valid_out;
output logic [31:0] entry_l_wgid;
input logic entry_stall_in;
// Limiter exit
input logic exit_valid_in;
output logic exit_stall_out;
output logic exit_valid_out;
input logic exit_stall_in;
wire [WG_BIT_LIMIT-1:0] wgid;
wire entry_reg_valid_in;
wire entry_reg_stall_in;
acl_work_group_limiter limiter(
.clock(clock),
.resetn(resetn),
.wg_size(wg_size[MAX_WG_SIZE_WIDTH-1:0]),
// Limiter entry
.entry_valid_in(entry_valid_in),
.entry_k_wgid(entry_k_wgid[KWG_BIT_LIMIT-1:0]),
.entry_stall_out(entry_stall_out),
.entry_valid_out(entry_valid_out),
.entry_l_wgid(wgid),
.entry_stall_in(entry_stall_in),
// Limiter exit
.exit_valid_in(exit_valid_in),
.exit_stall_out(exit_stall_out),
.exit_valid_out(exit_valid_out),
.exit_stall_in(exit_stall_in));
defparam limiter.WG_LIMIT = WG_LIMIT;
defparam limiter.KERNEL_WG_LIMIT = KERNEL_WG_LIMIT;
defparam limiter.MAX_WG_SIZE = MAX_WG_SIZE;
defparam limiter.WG_FIFO_ORDER = WG_FIFO_ORDER;
defparam limiter.IMPL = "local";
assign entry_l_wgid[31:WG_BIT_LIMIT] = '0;
assign entry_l_wgid[WG_BIT_LIMIT-1:0] = wgid;
endmodule
| 8.852575
|
module ACM (
input [5:0] x,
input rst,
input clk,
output [5:0] s
);
wire [5:0] op_1, op_2, out;
wire [2:0] f;
assign s = out;
REG r1 (
.in (x),
.en (1),
.rst(rst),
.clk(clk),
.out(op_1)
);
REG r2 (
.in (out),
.en (1),
.rst(rst),
.clk(clk),
.out(op_2)
);
ALU a1 (
.s(3'b000),
.a(op_1),
.b(op_2),
.y(out),
.f(f)
);
endmodule
| 6.867785
|
module acmpc01_3v3 ( OUT, EN, IBN, INN, INP, VDDA, VSSA );
input IBN;
input EN;
input VSSA;
input VDDA;
input INN;
input INP;
output OUT;
wire real IBN, VSSA, VDDA, INN, INP;
reg OUT;
real NaN;
initial begin
NaN = 0.0 / 0.0;
if (EN == 1'b1) begin
if (INP == NaN) begin
OUT <= 1'bx;
end else if (INN == NaN) begin
OUT <= 1'bx;
end else if (INP > INN) begin
OUT <= 1'b1;
end else begin
OUT <= 1'b0;
end
end else begin
OUT <= 1'b0;
end
end
always @(INN or INP or EN) begin
if (EN == 1'b1) begin
if (INP == NaN) begin
OUT <= 1'bx;
end else if (INN == NaN) begin
OUT <= 1'bx;
end else if (INP > INN) begin
OUT <= 1'b1;
end else begin
OUT <= 1'b0;
end
end else begin
OUT <= 1'b0;
end
end
endmodule
| 6.561245
|
module latch_nand3 (
CLK,
VP,
VN,
Q,
Qb
);
(* src = "../verilog/rtl/ACMP_HVL.v:77" *)
input CLK;
(* src = "../verilog/rtl/ACMP_HVL.v:80" *)
output Q;
(* src = "../verilog/rtl/ACMP_HVL.v:83" *)
wire Q0;
(* src = "../verilog/rtl/ACMP_HVL.v:83" *)
wire Q0b;
(* src = "../verilog/rtl/ACMP_HVL.v:81" *)
output Qb;
(* src = "../verilog/rtl/ACMP_HVL.v:79" *)
input VN;
(* src = "../verilog/rtl/ACMP_HVL.v:78" *)
input VP;
(* module_not_derived = 32'd1 *) (* src = "../verilog/rtl/ACMP_HVL.v:85" *)
sky130_fd_sc_hvl__nand3_1 x1 (
.A(CLK),
.B(VP),
.C(Q0),
.Y(Q0b)
);
(* module_not_derived = 32'd1 *) (* src = "../verilog/rtl/ACMP_HVL.v:91" *)
sky130_fd_sc_hvl__nand3_1 x2 (
.A(CLK),
.B(VN),
.C(Q0b),
.Y(Q0)
);
(* module_not_derived = 32'd1 *) (* src = "../verilog/rtl/ACMP_HVL.v:98" *)
sky130_fd_sc_hvl__inv_4 x3 (
.A(Q0),
.Y(Qb)
);
(* module_not_derived = 32'd1 *) (* src = "../verilog/rtl/ACMP_HVL.v:103" *)
sky130_fd_sc_hvl__inv_4 x4 (
.A(Q0b),
.Y(Q)
);
endmodule
| 6.77402
|
module latch_nor3 (
CLK,
VP,
VN,
Q,
Qb
);
(* src = "../verilog/rtl/ACMP_HVL.v:54" *)
input CLK;
(* src = "../verilog/rtl/ACMP_HVL.v:57" *)
output Q;
(* src = "../verilog/rtl/ACMP_HVL.v:58" *)
output Qb;
(* src = "../verilog/rtl/ACMP_HVL.v:56" *)
input VN;
(* src = "../verilog/rtl/ACMP_HVL.v:55" *)
input VP;
(* module_not_derived = 32'd1 *) (* src = "../verilog/rtl/ACMP_HVL.v:61" *)
sky130_fd_sc_hvl__nor3_1 x1 (
.A(CLK),
.B(VP),
.C(Q),
.Y(Qb)
);
(* module_not_derived = 32'd1 *) (* src = "../verilog/rtl/ACMP_HVL.v:67" *)
sky130_fd_sc_hvl__nor3_1 x2 (
.A(CLK),
.B(VN),
.C(Qb),
.Y(Q)
);
endmodule
| 7.218053
|
module latch_nand3 (
CLK,
VP,
VN,
Q,
Qb,
VGND,
VNB,
VPB,
VPWR
);
input VPWR;
input VGND;
input VPB;
input VNB;
(* src = "../verilog/rtl/ACMP_HVL.v:77" *)
input CLK;
(* src = "../verilog/rtl/ACMP_HVL.v:80" *)
output Q;
(* src = "../verilog/rtl/ACMP_HVL.v:83" *)
wire Q0;
(* src = "../verilog/rtl/ACMP_HVL.v:83" *)
wire Q0b;
(* src = "../verilog/rtl/ACMP_HVL.v:81" *)
output Qb;
(* src = "../verilog/rtl/ACMP_HVL.v:79" *)
input VN;
(* src = "../verilog/rtl/ACMP_HVL.v:78" *)
input VP;
(* module_not_derived = 32'd1 *) (* src = "../verilog/rtl/ACMP_HVL.v:85" *)
sky130_fd_sc_hvl__nand3_1 x1 (
.A(CLK),
.B(VP),
.C(Q0),
.Y(Q0b)
, .VGND(VGND),
.VNB(VNB),
.VPB(VPB),
.VPWR(VPWR)
);
(* module_not_derived = 32'd1 *) (* src = "../verilog/rtl/ACMP_HVL.v:91" *)
sky130_fd_sc_hvl__nand3_1 x2 (
.A(CLK),
.B(VN),
.C(Q0b),
.Y(Q0)
, .VGND(VGND),
.VNB(VNB),
.VPB(VPB),
.VPWR(VPWR)
);
(* module_not_derived = 32'd1 *) (* src = "../verilog/rtl/ACMP_HVL.v:98" *)
sky130_fd_sc_hvl__inv_4 x3 (
.A(Q0),
.Y(Qb)
, .VGND(VGND),
.VNB(VNB),
.VPB(VPB),
.VPWR(VPWR)
);
(* module_not_derived = 32'd1 *) (* src = "../verilog/rtl/ACMP_HVL.v:103" *)
sky130_fd_sc_hvl__inv_4 x4 (
.A(Q0b),
.Y(Q)
, .VGND(VGND),
.VNB(VNB),
.VPB(VPB),
.VPWR(VPWR)
);
endmodule
| 6.77402
|
module latch_nor3 (
CLK,
VP,
VN,
Q,
Qb,
VGND,
VNB,
VPB,
VPWR
);
input VPWR;
input VGND;
input VPB;
input VNB;
(* src = "../verilog/rtl/ACMP_HVL.v:54" *)
input CLK;
(* src = "../verilog/rtl/ACMP_HVL.v:57" *)
output Q;
(* src = "../verilog/rtl/ACMP_HVL.v:58" *)
output Qb;
(* src = "../verilog/rtl/ACMP_HVL.v:56" *)
input VN;
(* src = "../verilog/rtl/ACMP_HVL.v:55" *)
input VP;
(* module_not_derived = 32'd1 *) (* src = "../verilog/rtl/ACMP_HVL.v:61" *)
sky130_fd_sc_hvl__nor3_1 x1 (
.A(CLK),
.B(VP),
.C(Q),
.Y(Qb)
, .VGND(VGND),
.VNB(VNB),
.VPB(VPB),
.VPWR(VPWR)
);
(* module_not_derived = 32'd1 *) (* src = "../verilog/rtl/ACMP_HVL.v:67" *)
sky130_fd_sc_hvl__nor3_1 x2 (
.A(CLK),
.B(VN),
.C(Qb),
.Y(Q)
, .VGND(VGND),
.VNB(VNB),
.VPB(VPB),
.VPWR(VPWR)
);
endmodule
| 7.218053
|
module ACMP_HVL (
`ifdef USE_POWER_PINS
input wire vccd2,
input wire vssd2,
`endif
input wire clk,
input wire INP,
input wire INN,
output wire Q
);
wire clkb;
wire Q1b, Q1;
wire Q2b, Q2;
wire Qb;
sky130_fd_sc_hvl__inv_1 x0 (
.Y(clkb),
.A(clk)
);
sky130_fd_sc_hvl__nor3_1 x5 (
.Y(Q),
.A(Q1b),
.B(Q2b),
.C(Qb)
);
sky130_fd_sc_hvl__nor3_1 x6 (
.Y(Qb),
.A(Q1),
.B(Q2),
.C(Q)
);
latch_nand3 x1 (
.CLK(clk),
.VP (INP),
.VN (INN),
.Q (Q1),
.Qb (Q1b)
);
latch_nor3 x2 (
.CLK(clkb),
.VP (INP),
.VN (INN),
.Q (Q2),
.Qb (Q2b)
);
endmodule
| 6.697507
|
module latch_nor3 (
input wire CLK,
input wire VP,
input wire VN,
output wire Q,
output wire Qb
);
sky130_fd_sc_hvl__nor3_1 x1 (
.Y(Qb),
.A(CLK),
.B(VP),
.C(Q)
);
sky130_fd_sc_hvl__nor3_1 x2 (
.Y(Q),
.A(CLK),
.B(VN),
.C(Qb)
);
endmodule
| 7.218053
|
module latch_nand3 (
input wire CLK,
input wire VP,
input wire VN,
output wire Q,
output wire Qb
);
wire Q0, Q0b;
sky130_fd_sc_hvl__nand3_1 x1 (
.Y(Q0b),
.A(CLK),
.B(VP),
.C(Q0)
);
sky130_fd_sc_hvl__nand3_1 x2 (
.Y(Q0),
.A(CLK),
.B(VN),
.C(Q0b)
);
sky130_fd_sc_hvl__inv_4 x3 (
.Y(Qb),
.A(Q0)
);
sky130_fd_sc_hvl__inv_4 x4 (
.Y(Q),
.A(Q0b)
);
endmodule
| 6.77402
|
module acm_controller (
wb_clk_i,
wb_rst_i,
wb_cyc_i,
wb_stb_i,
wb_we_i,
wb_adr_i,
wb_dat_i,
wb_dat_o,
wb_ack_o,
acm_wdata,
acm_rdata,
acm_addr,
acm_wen,
acm_clk,
acm_reset
);
input wb_clk_i, wb_rst_i;
input wb_cyc_i, wb_stb_i, wb_we_i;
input [15:0] wb_adr_i;
input [15:0] wb_dat_i;
output [15:0] wb_dat_o;
output wb_ack_o;
output acm_clk, acm_reset;
output acm_wen;
output [7:0] acm_wdata;
input [7:0] acm_rdata;
output [7:0] acm_addr;
assign acm_reset = ~wb_rst_i;
reg [1:0] acm_clk_counter;
assign acm_clk = acm_clk_counter[1];
reg wb_ack_o;
reg [1:0] state;
localparam STATE_IDLE = 2'd0;
localparam STATE_WAITCLK = 2'd1;
localparam STATE_WAITTRANS = 2'd2;
assign acm_wdata = wb_dat_i[7:0];
assign acm_addr = wb_adr_i[7:0];
reg acm_wen;
reg [7:0] acm_rdata_reg;
assign wb_dat_o = {8'b0, acm_rdata_reg[7:0]};
always @(posedge wb_clk_i) begin
wb_ack_o <= 1'b0;
if (wb_rst_i) begin
state <= STATE_IDLE;
acm_wen <= 1'b0;
acm_clk_counter <= 2'b0;
end else begin
acm_clk_counter <= acm_clk_counter + 2'b1;
case (state)
STATE_IDLE: begin
if (wb_cyc_i & wb_stb_i & ~wb_ack_o) begin
state <= STATE_WAITCLK;
end
end
STATE_WAITCLK: begin
if (acm_clk_counter == 2'b00) begin
if (wb_we_i) acm_wen <= 1'b1;
state <= STATE_WAITTRANS;
end
end
STATE_WAITTRANS: begin
if (acm_clk_counter == 2'b11) begin
acm_wen <= 1'b0;
wb_ack_o <= 1'b1;
acm_rdata_reg <= acm_rdata;
state <= STATE_IDLE;
end
end
endcase
end
end
endmodule
| 8.409205
|
module ACM_tb ();
reg [5 : 0] x;
reg reset;
wire clock;
wire [5 : 0] s;
GenerateClock CLK (clock);
ACM acm (
.x(x),
.reset(reset),
.clock(clock),
.s(s)
);
integer i = 0;
initial begin
x = 'b0;
reset = 'b1;
#20 reset = 'b0;
#20
for (i = 0; i <= 6'b111111; i = i + 1) begin
x = i;
#20;
end
end
endmodule
| 6.713351
|
module acog_logic (
input wire [5:0] opcode_in,
input wire flag_c_in,
input wire flag_z_in,
input wire [31:0] s_in,
input wire [31:0] s_negated_in,
input wire [31:0] d_in,
output reg [31:0] q_o,
output wire flag_c_o
);
wire [15:0] odd16;
wire [ 7:0] odd8;
wire [ 3:0] odd4;
wire [ 2:0] odd2;
always @(*)
case (opcode_in[2:0])
3'b000: q_o = d_in & s_in; // AND
3'b001: q_o = d_in & (~s_in); // ANDN
3'b010: q_o = d_in | s_in; // OR
3'b011: q_o = d_in ^ s_in; // XOR
3'b100: q_o = (d_in & s_negated_in) | (flag_c_in ? s_in : 32'h0); //`I_MUXC:
3'b101: q_o = (d_in & s_negated_in) | (!flag_c_in ? s_in : 32'h0); //`I_MUXNC:
3'b110: q_o = (d_in & s_negated_in) | (!flag_z_in ? s_in : 32'h0); //`I_MUXNZ:
3'b111: q_o = (d_in & s_negated_in) | (flag_z_in ? s_in : 32'h0); //`I_MUXZ:
endcase
assign odd16 = q_o[31:16] ^ q_o[15:0];
assign odd8 = odd16[15:8] ^ odd16[7:0];
assign odd4 = odd8[7:4] ^ odd8[3:0];
assign odd2 = odd4[3:2] ^ odd4[1:0];
assign flag_c_o = odd2[1] ^ odd2[0];
endmodule
| 7.113755
|
module acog_parity (
input wire [31:0] q_in,
output wire odd
);
wire [15:0] odd16;
wire [ 7:0] odd8;
wire [ 3:0] odd4;
wire [ 2:0] odd2;
assign odd16 = q_in[31:16] ^ q_in[15:0];
assign odd8 = odd16[15:8] ^ odd16[7:0];
assign odd4 = odd8[7:4] ^ odd8[3:0];
assign odd2 = odd4[3:2] ^ odd4[1:0];
assign odd = odd2[1] ^ odd2[0];
endmodule
| 6.960233
|
module barrel_shr (
input wire [31:0] a,
output wire [31:0] q_shr,
output wire [31:0] q_sar,
input wire [ 4:0] shift
);
reg [31:0] rq, mask;
assign q_shr = rq;
assign q_sar = a[31] ? mask | rq : rq;
always @(a, shift) begin
case (shift[4:2])
3'h0: rq = a;
3'h1: rq = {4'b0, a[31:4]};
3'h2: rq = {8'b0, a[31:8]};
3'h3: rq = {12'b0, a[31:12]};
3'h4: rq = {16'b0, a[31:16]};
3'h5: rq = {20'b0, a[31:20]};
3'h6: rq = {24'b0, a[31:24]};
3'h7: rq = {28'b0, a[31:28]};
endcase
end
always @(shift) begin
case (shift)
5'h00: mask = 32'h0000_0000;
5'h01: mask = 32'h8000_0000;
5'h02: mask = 32'hc000_0000;
5'h03: mask = 32'he000_0000;
5'h04: mask = 32'hf000_0000;
5'h05: mask = 32'hf800_0000;
5'h06: mask = 32'hfc00_0000;
5'h07: mask = 32'hfe00_0000;
5'h08: mask = 32'hff00_0000;
5'h09: mask = 32'hff80_0000;
5'h0a: mask = 32'hffc0_0000;
5'h0b: mask = 32'hffe0_0000;
5'h0c: mask = 32'hfff0_0000;
5'h0d: mask = 32'hfff8_0000;
5'h0e: mask = 32'hfffc_0000;
5'h0f: mask = 32'hfffe_0000;
5'h10: mask = 32'hffff_0000;
5'h11: mask = 32'hffff_8000;
5'h12: mask = 32'hffff_c000;
5'h13: mask = 32'hffff_e000;
5'h14: mask = 32'hffff_f000;
5'h15: mask = 32'hffff_f800;
5'h16: mask = 32'hffff_fc00;
5'h17: mask = 32'hffff_fe00;
5'h18: mask = 32'hffff_ff00;
5'h19: mask = 32'hffff_ff80;
5'h1a: mask = 32'hffff_ffc0;
5'h1b: mask = 32'hffff_ffe0;
5'h1c: mask = 32'hffff_fff0;
5'h1d: mask = 32'hffff_fff8;
5'h1e: mask = 32'hffff_fffc;
5'h1f: mask = 32'hffff_fffe;
endcase
end
endmodule
| 7.041569
|
module acog_if (
input wire clk_in,
input wire [1:0] state_in
);
endmodule
| 7.631882
|
module memblock_dp_x32(
input wire clk_i,
input wire [8:0] port_a_addr_i,
input wire [8:0] port_b_addr_i,
input wire port_a_rden_i,
input wire port_b_rden_i,
output reg [31:0] port_a_q_o,
output reg [31:0] port_b_q_o,
input wire port_b_wen_i,
input wire [31:0] port_b_data_i
);
reg [31:0] mem[511:0];
always @(posedge clk_i)
begin
if (port_a_rden_i)
port_a_q_o <= mem[port_a_addr_i];
if (port_b_rden_i)
port_b_q_o <= mem[port_b_addr_i];
if (port_b_wen_i)
mem[port_b_addr_i] <= port_b_data_i;
end
integer i;
initial
begin
for ( i = 32'd0; i < 32'd511; i = i + 32'd1)
mem[i] = { i[15:0], i[15:0] };//32'hDEADBEEF;
#0
// HUB loader
mem[9'h1f4] = { `I_MOV, 4'b0010, 4'hf, 9'h1f1, `R_PAR}; // mov $1f1, PAR ' load src ptr
mem[9'h1f5] = { `I_MOV, 4'b0011, 4'hf, 9'h1f2, 9'h000}; // mov $1f2, #0 ' load src ptr
mem[9'h1f6] = { `I_MOV, 4'b0011, 4'hf, 9'h1f3, 9'h1f0}; // mov $1f3, #1f0 ' load counter
mem[9'h1f7] = { `I_MOVD, 4'b0010, 4'hf, 9'h1f8, 9'h1f2}; // loop movd $1fa, $1f2 ' dest ptr
mem[9'h1f8] = { `I_RDLONG, 4'b0010, 4'hf, 9'h000, 9'h1f1}; // rdlong $0-0, $1f1 ' load long
mem[9'h1f9] = { `I_ADD, 4'b0011, 4'hf, 9'h1f1, 9'h004}; // add $1f1, #$4 ' icr dest addr
mem[9'h1fa] = { `I_ADD, 4'b0011, 4'hf, 9'h1f2, 9'h001}; // add $1f2, #$1 ' icr dest addr
mem[9'h1fb] = { `I_DJNZ, 4'b0011, 4'hf, 9'h1f3, 9'h1f7}; // djnz $1f3, loop
mem[9'h1fc] = { `I_JMP, 4'b0001, 4'hf, 9'h00, 9'h000}; // jmp #$0 ' jump to start
//OOOOOOZCRiCCCCDDDDDDDDDSSSSSSSSS
/*
mem[ 0] = 32'b10100000111111111110100000000011; //-- mov dira, #3
mem[ 1] = 32'b10100000101111111100000111110001; //-- mov temp, CNT ($1E0)
mem[ 2] = 32'b10000000111111111100000000100000; //-- add temp, #32
mem[ 3] = 32'b11111000111111111100000000010100; //-- waitcnt temp, #20
mem[ 4] = 32'b10100000111111111110110000000010; //-- mov porta, #2
mem[ 5] = 32'b11111000111111111100000000010100; //-- waitcnt temp, #20
mem[ 6] = 32'b10100000111111111110110000000001; //-- mov porta, #1
mem[ 7] = 32'b01011100011111000000000000000011; //-- jmp #3
mem[ 8] = 32'b001110_1111_0010_001000100_001000001; // mov rt, rA20
mem[ 9] = 32'b001110_1111_0010_001000100_001000001; // mov rt, rA20
mem[ 128] = 32'b111100_0011_1100_001111000_011110000; // mov rt, rA20
*/
end
endmodule
| 6.572658
|
module acog_seq (
input wire clk_in,
input wire reset_in,
output wire [1:0] state_o,
input wire [31:0] opcode_in,
input wire flag_c_in,
input wire port_pne_pina_in,
input wire port_peq_pina_in,
input wire port_pne_pinb_in,
input wire port_peq_pinb_in,
input wire port_cnt_eq_d_in,
input wire execute_in,
input wire hub_ack_in,
input wire [4:0] hub_op_in,
output wire hub_data_rdy_o // this signal will be asserted on the READ stage after D&S are read
);
reg [1:0] state;
reg read_rdy, data_to_hub_rdy;
assign state_o = state;
assign hub_data_rdy_o = data_to_hub_rdy;
always @(posedge clk_in) begin
if (reset_in) begin
state <= 0;
end else begin
case (state)
`ST_FETCH: begin
state <= state + 2'h1;
end
`ST_DECODE: state <= state + 2'h1;
`ST_READ: begin
if (hub_ack_in) begin
state <= state + 2'h1;
read_rdy <= 1'b0;
data_to_hub_rdy <= 1'b0;
end else if (execute_in) begin
if (read_rdy) begin
case (opcode_in[31:26])
`I_RDBYTE, `I_RDWORD, `I_RDLONG: begin
end
`I_WAITCNT: if (port_cnt_eq_d_in) state <= state + 2'h1;
`I_WAITPEQ:
if (flag_c_in & port_peq_pinb_in) state <= state + 2'h1;
else if ((!flag_c_in) & port_peq_pina_in) state <= state + 2'h1;
`I_WAITPNE:
if (flag_c_in & port_pne_pinb_in) state <= state + 2'h1;
else if ((!flag_c_in) & port_pne_pina_in) state <= state + 2'h1;
default: begin
state <= state + 2'h1;
read_rdy <= 1'b0;
end
endcase
end else // if (read_rdy) : not yet ready, set ready
begin
case (opcode_in[31:26])
`I_RDBYTE, `I_RDWORD, `I_RDLONG: begin
read_rdy <= 1'b1;
data_to_hub_rdy <= 1'b1;
end
`I_WAITCNT, `I_WAITPEQ, `I_WAITPNE: read_rdy <= 1'b1;
default: state <= state + 2'h1;
endcase
end
end else // if (execute_in)
state <= state + 2'h1; // if we do not execute this opcode...
end
`ST_WBACK: state <= state + 2'h1;
endcase
end
end
initial begin
end
endmodule
| 6.750794
|
module acog_wback (
input wire clk_in,
input wire reset_in,
input wire [1:0] state_in,
input wire [31:0] opcode_in,
input wire d_is_zero_in,
input wire d_is_one_in,
input wire execute_in,
input wire save_c_in,
input wire save_z_in,
input wire save_pc_from_s_in,
input wire save_pc_from_pc_plus_1_in,
input wire flag_c_in,
input wire flag_z_in,
output wire flag_c_o,
output wire flag_z_o,
output wire [`MEM_WIDTH-1:0] pc_o,
output wire [`MEM_WIDTH-1:0] pc_plus_1_o,
input wire [31:0] s_data_in
);
reg flag_c, flag_z;
reg [`MEM_WIDTH-1:0] pc;
wire [`MEM_WIDTH-1:0] pc_plus_1;
assign flag_c_o = flag_c;
assign flag_z_o = flag_z;
assign pc_o = pc;
assign pc_plus_1 = pc + `MEM_WIDTH'h1;
assign pc_plus_1_o = pc_plus_1;
always @(posedge clk_in) begin
if (reset_in) begin
pc <= 9'h1f4; // start of HUB loader
flag_c <= 1'b0;
flag_z <= 1'b0;
end else
case (state_in)
`ST_WBACK: begin
if (save_c_in) flag_c <= flag_c_in;
if (save_z_in) flag_z <= flag_z_in;
case (opcode_in[31:26])
`I_DJNZ:
if (execute_in & (d_is_one_in)) pc <= pc_plus_1; // jump not taken
else pc <= s_data_in[`MEM_WIDTH-1:0]; // jump taken
`I_TJNZ:
if (execute_in & (!d_is_zero_in)) pc <= s_data_in[`MEM_WIDTH-1:0]; // jump taken
else pc <= pc_plus_1; // jump not taken
`I_TJZ:
if (execute_in & d_is_zero_in) pc <= s_data_in[`MEM_WIDTH-1:0]; // jump taken
else pc <= pc_plus_1; // jump not taken
default:
if (save_pc_from_pc_plus_1_in) pc <= pc_plus_1;
else if (save_pc_from_s_in) // call, jump
if (opcode_in[`OP_I]) pc <= opcode_in[`MEM_WIDTH-1:0];
else pc <= s_data_in[`MEM_WIDTH-1:0]; // indirect
endcase
end
endcase
end
initial begin
flag_c = 0;
flag_z = 0;
pc = 0;
end
endmodule
| 7.520405
|
module Acondicionamiento #(
parameter Magnitud = 17,
Decimal = 0,
N = Magnitud + Decimal + 1,
ADC = 12
) //Se parametriza para hacer flexible el cambio de ancho de palabra
//Declaracion de senales de entrada y salida
(
input wire clk,
reset,
enable,
input wire signed [N-1:0] referencia,
y,
output wire signed [7:0] Entrada_PWM,
output wire signed [N-1:0] IPD
);
//Declaracion de senales utilizadas dentro del modulo
wire signed [N-1:0] SalidaMultiplicacion, IPD_R;
wire signed [ADC-1:0] Sal;
//Modulo que implementa el I_PD
I_PD #(
.Magnitud(Magnitud),
.Decimal(Decimal),
.N(N)
) Sal_IPD (
.clk(clk),
.reset(reset),
.enable(enable),
.referencia(referencia),
.y(y),
.IPD(IPD)
);
//Registro que guarda el valor de salida del I_PD para ajuste aritmetico
Registro_N_bits #(
.N(N)
) Reg_Timing (
.clock(clk),
.reset(reset),
.d(IPD),
.q(IPD_R)
);
//Las siguientes operaciones ajustan aritmeticamente el valor final del I_PD para compensar los cambios hechos a la entrada y durante las operaciones
//del I_PD
Multiplicacion #(
.Magnitud(Magnitud),
.Decimal (Decimal)
) mult (
.A(18'd2),
.B(IPD_R),
.multi(SalidaMultiplicacion)
);
//Suma de offset eliminado a la entrada de los datos provenientes del ADC y la referencia
Suma #(
.N(ADC)
) Suma_Integrador_Proporcional (
.A(SalidaMultiplicacion[N-1:N-12]),
.B(12'd2048),
.SUMA(Sal)
);
assign Entrada_PWM = Sal[ADC-1:ADC-8]; //Truncamiento de 8 bits de la senal de salida del I_PD
endmodule
| 7.80019
|
module: ALUControl
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Acontrol_tb;
// Inputs
reg [1:0] ALUOp;
reg [2:0] func3;
reg func7;
// Outputs
wire [3:0] sel;
// Instantiate the Unit Under Test (UUT)
ALUControl uut (
.ALUOp(ALUOp),
.func3(func3),
.func7(func7),
.sel(sel)
);
initial begin
// Initialize Inputs
ALUOp = 0;
func3 = 3'b010;
func7 = 1;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 7.099352
|
module acorn_prng (
`ifdef USE_POWER_PINS
inout vccd1, // User area 1 1.8V power
inout vssd1, // User area 1 digital ground
`endif
input clk,
input reset,
input wire load,
input wire [1:0] select,
input wire [11:0] gpio_seed,
input wire [11:0] LA1_seed,
output reg [11:0] out,
output [12:0] io_oeb,
output wire reset_out
);
assign io_oeb = 13'b0;
assign reset_out = reset;
reg [11:0] seed;
reg [11:0] r01;
reg [11:0] r02;
reg [11:0] r03;
reg [11:0] r04;
reg [11:0] r05;
reg [11:0] r06;
reg [11:0] r07;
reg [11:0] r08;
reg [11:0] r09;
reg [11:0] r010;
reg [11:0] r011;
reg [11:0] r012;
reg [11:0] r013;
reg [11:0] r014;
reg [11:0] r015;
reg [11:0] r10;
reg [11:0] r11;
reg [11:0] r12;
reg [11:0] r13;
reg [11:0] r14;
reg [11:0] r15;
reg [11:0] r16;
reg [11:0] r17;
reg [11:0] r18;
reg [11:0] r19;
reg [11:0] r110;
reg [11:0] r111;
reg [11:0] r112;
reg [11:0] r113;
reg [11:0] r114;
reg [11:0] r115;
reg [ 3:0] counter;
always @(posedge clk) begin
if (reset) begin
//everything to zero
counter <= 0;
r01 <= 0;
r02 <= 0;
r03 <= 0;
r04 <= 0;
r05 <= 0;
r06 <= 0;
r07 <= 0;
r08 <= 0;
r09 <= 0;
r010 <= 0;
r011 <= 0;
r012 <= 0;
r013 <= 0;
r014 <= 0;
r015 <= 0;
r11 <= 0;
r12 <= 0;
r13 <= 0;
r14 <= 0;
r15 <= 0;
r16 <= 0;
r17 <= 0;
r18 <= 0;
r19 <= 0;
r110 <= 0;
r111 <= 0;
r112 <= 0;
r113 <= 0;
r114 <= 0;
r115 <= 0;
out <= 0;
seed <= 0;
end else if (load) begin
if (select == 2'b00) seed <= 12'b100000000001;
if (select == 2'b11) seed <= 12'b111111111111;
if (select == 2'b01) seed <= gpio_seed;
if (select == 2'b10) seed <= LA1_seed;
end else begin
counter <= counter + 1;
if (counter == 0) r11 <= r01 + seed;
if (counter == 1) r12 <= r02 + r11;
if (counter == 2) r13 <= r03 + r12;
if (counter == 3) r14 <= r04 + r13;
if (counter == 4) r15 <= r05 + r14;
if (counter == 5) r16 <= r06 + r15;
if (counter == 6) r17 <= r07 + r16;
if (counter == 7) r18 <= r08 + r17;
if (counter == 8) r19 <= r09 + r18;
if (counter == 9) r110 <= r010 + r19;
if (counter == 10) r111 <= r011 + r110;
if (counter == 11) r112 <= r012 + r111;
if (counter == 12) r113 <= r013 + r112;
if (counter == 13) r114 <= r014 + r113;
if (counter == 14) r115 <= r015 + r114;
if (counter == 15) out <= r115;
r01 <= r11;
r02 <= r12;
r03 <= r13;
r04 <= r14;
r05 <= r15;
r06 <= r16;
r07 <= r17;
r08 <= r18;
r09 <= r19;
r010 <= r110;
r011 <= r111;
r012 <= r112;
r013 <= r113;
r014 <= r114;
r015 <= r115;
end
end
endmodule
| 6.752421
|
module acoustic_pulse_train (
input clk,
input rst,
output reg signal
);
reg [10:0] cntr_q, cntr_d;
reg [26:0] sleep_q, sleep_d;
reg [26:0] compare = 'd99996615;
always @(cntr_q) begin
cntr_d = cntr_q + 1'b1;
/* reset counter if > 2500 */
if (cntr_d > 'd1250) begin
cntr_d = 11'd0;
end
end
always @(sleep_q) begin
sleep_d = sleep_q + 1'b1;
/* manual overflow for sleep after 2s+2ms */
if (sleep_d > 'd100100000) sleep_d = 27'd0;
end
always @(cntr_q or sleep_q) begin
if (cntr_d > 'd625) signal = 1'b0;
else signal = 1'b1 & (sleep_q > compare);
end
always @(posedge clk) begin
if (rst) begin
cntr_q <= 1'b0;
end else begin
cntr_q <= cntr_d;
sleep_q <= sleep_d;
end
end
endmodule
| 7.016656
|
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