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stringlengths 35
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module top_module (
input clk,
input resetn, // synchronous reset
input in,
output out
);
wire q1, q2, q3;
always @(posedge clk) begin
if (~resetn) begin
q1 <= 0;
q2 <= 0;
q3 <= 0;
out <= 0;
end else begin
q1 <= in;
q2 <= q1;
q3 <= q2;
out <= q3;
end
end
endmodule
| 7.203305
|
module top_module (
input clk,
input resetn,
input in,
output out
);
reg [3:0] sr;
// Create a shift register named sr. It shifts in "in".
always @(posedge clk) begin
if (~resetn) // Synchronous active-low reset
sr <= 0;
else sr <= {sr[2:0], in};
end
assign out = sr[3]; // Output the final bit (sr[3])
endmodule
| 7.203305
|
module top_module (
input in,
input [1:0] state,
output reg [1:0] next_state,
output reg out
);
always @(*) begin
case (state)
'b00: begin
if (in) begin
next_state = 'b01;
end else next_state = 'b00;
out = 0;
end
'b01: begin
if (in) next_state = 'b01;
else next_state = 'b10;
out = 0;
end
'b10: begin
if (in) next_state = 'b11;
else next_state = 'b00;
out = 0;
end
'b11: begin
if (in) next_state = 'b01;
else next_state = 'b10;
out = 1;
end
endcase
end
endmodule
| 7.203305
|
module top_module (
input [7:0] a,
input [7:0] b,
output [7:0] s,
output overflow
); //
assign s = a + b;
assign overflow = (~(a[7] ^ b[7])) & (s[7] != a[7]);
endmodule
| 7.203305
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always begin
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module top_module (
input [99:0] a,
b,
input cin,
output cout,
output [99:0] sum
);
assign {cout, sum} = cin + a + b;
endmodule
| 7.203305
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (~(memory ? displacement : (sub ? (~B) : B)));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = '0;
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = '1;
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module top_module (
input [15:0] a,
b,
input cin,
output cout,
output [15:0] sum
);
wire [3:0] cout_temp;
bcd_fadd u_bcd_fadd (
.a(a[3:0]),
.b(b[3:0]),
.cin(cin),
.cout(cout_temp[0]),
.sum(sum[3:0])
);
generate
genvar i;
for (i = 1; i < 4; i++) begin : adding
bcd_fadd u_bcd_fadd (
.a(a[4*i+3 : 4*i]),
.b(b[4*i+3 : 4*i]),
.cin(cout_temp[i-1]),
.cout(cout_temp[i]),
.sum(sum[4*i+3 : 4*i])
);
end
endgenerate
assign cout = cout_temp[3];
endmodule
| 7.203305
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~(~B)) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~'0) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~'1) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (-B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module top_module (
input a,
input b,
input c,
output out
);
assign out = a | b | c;
endmodule
| 7.203305
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~(~B)) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? '0 : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? '1 : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : (~B)));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : '0));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : '1));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : ((!sub) ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (0 ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (1 ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module top_module (
input a,
input b,
input c,
input d,
output out
);
assign out = (~a & ~d) | (~a & ~b & ~c) | (b & c & d) | (~c & a & ~b) | (d & a & ~b);
endmodule
| 7.203305
|
module mod_7401 (
input A1,
input B1,
output Y1,
input A2,
input B2,
output Y2,
input A3,
input B3,
output Y3,
input A4,
input B4,
output Y4
);
assign Y1 = !(A1 & B1);
assign Y2 = !(A2 & B2);
assign Y3 = !(A3 & B3);
assign Y4 = !(A4 & B4);
endmodule
| 7.759477
|
module mod_7403 (
input A1,
input B1,
output Y1,
input A2,
input B2,
output Y2,
input A3,
input B3,
output Y3,
input A4,
input B4,
output Y4
);
assign Y1 = !(A1 & B1);
assign Y2 = !(A2 & B2);
assign Y3 = !(A3 & B3);
assign Y4 = !(A4 & B4);
endmodule
| 7.622274
|
module mod_7405 (
input A1,
output Y1,
input A2,
output Y2,
input A3,
output Y3,
input A4,
output Y4,
input A5,
output Y5,
input A6,
output Y6
);
assign Y1 = !A1;
assign Y2 = !A2;
assign Y3 = !A3;
assign Y4 = !A4;
assign Y5 = !A5;
assign Y6 = !A6;
endmodule
| 6.627999
|
module mod_7409 (
input A1,
input B1,
output Y1,
input A2,
input B2,
output Y2,
input A3,
input B3,
output Y3,
input A4,
input B4,
output Y4
);
assign Y1 = A1 & B1;
assign Y2 = A2 & B2;
assign Y3 = A3 & B3;
assign Y4 = A4 & B4;
endmodule
| 7.625943
|
module ttl_7410 #(
parameter BLOCKS = 3,
WIDTH_IN = 3,
DELAY_RISE = 0,
DELAY_FALL = 0
) (
input [BLOCKS*WIDTH_IN-1:0] A_2D,
output [BLOCKS-1:0] Y
);
//------------------------------------------------//
wire [WIDTH_IN-1:0] A[0:BLOCKS-1];
reg [BLOCKS-1:0] computed;
integer i;
always @(*) begin
for (i = 0; i < BLOCKS; i++) computed[i] = ~(&A[i]);
end
//------------------------------------------------//
`ASSIGN_UNPACK_ARRAY(BLOCKS, WIDTH_IN, A, A_2D)
assign #(DELAY_RISE, DELAY_FALL) Y = computed;
endmodule
| 7.102548
|
module ttl_7411 #(
parameter BLOCKS = 3,
WIDTH_IN = 3,
DELAY_RISE = 0,
DELAY_FALL = 0
) (
input [BLOCKS*WIDTH_IN-1:0] A_2D,
output [BLOCKS-1:0] Y
);
//------------------------------------------------//
wire [WIDTH_IN-1:0] A[0:BLOCKS-1];
reg [BLOCKS-1:0] computed;
integer i;
always @(*) begin
for (i = 0; i < BLOCKS; i++) computed[i] = &A[i];
end
//------------------------------------------------//
`ASSIGN_UNPACK_ARRAY(BLOCKS, WIDTH_IN, A, A_2D)
assign #(DELAY_RISE, DELAY_FALL) Y = computed;
endmodule
| 7.044261
|
module ttl_74112 #(
parameter BLOCKS = 2,
DELAY_RISE = 0,
DELAY_FALL = 0
) (
input [BLOCKS-1:0] Preset_bar,
input [BLOCKS-1:0] Clear_bar,
input [BLOCKS-1:0] J,
input [BLOCKS-1:0] K,
input [BLOCKS-1:0] Clk,
output [BLOCKS-1:0] Q,
output [BLOCKS-1:0] Q_bar
);
//------------------------------------------------//
reg [BLOCKS-1:0] Q_current;
reg [BLOCKS-1:0] Preset_bar_previous;
generate
genvar i;
for (i = 0; i < BLOCKS; i = i + 1) begin : gen_blocks
always @(negedge Clk[i] or negedge Clear_bar[i]) begin
if (!Clear_bar[i]) Q_current[i] <= 1'b0;
else if (!Preset_bar[i] && Preset_bar_previous[i]) // falling edge has occurred
Q_current[i] <= 1'b1;
else begin
if (J[i] && !K[i] || !J[i] && K[i]) Q_current[i] <= J[i];
else if (J[i] && K[i]) Q_current[i] <= !Q_current[i];
else Q_current[i] <= Q_current[i];
Preset_bar_previous[i] <= Preset_bar[i];
end
end
end
endgenerate
//------------------------------------------------//
assign #(DELAY_RISE, DELAY_FALL) Q = Q_current;
assign #(DELAY_RISE, DELAY_FALL) Q_bar = ~Q_current;
endmodule
| 6.837249
|
module mod_7412 (
input A1,
input B1,
input C1,
output Y1,
input A2,
input B2,
input C2,
output Y2,
input A3,
input B3,
input C3,
output Y3
);
assign Y1 = !(A1 & B1 & C1);
assign Y2 = !(A2 & B2 & C2);
assign Y3 = !(A3 & B3 & C3);
endmodule
| 8.226838
|
module mod_7413 (
input A1,
input B1,
input C1,
input D1,
output Y1,
input A2,
input B2,
input C2,
input D2,
output Y2
);
assign Y1 = !(A1 & B1 & C1 & D1);
assign Y2 = !(A2 & B2 & C2 & D2);
endmodule
| 7.525552
|
module mod_7414 (
input A1,
output Y1,
input A2,
output Y2,
input A3,
output Y3,
input A4,
output Y4,
input A5,
output Y5,
input A6,
output Y6
);
assign Y1 = !A1;
assign Y2 = !A2;
assign Y3 = !A3;
assign Y4 = !A4;
assign Y5 = !A5;
assign Y6 = !A6;
endmodule
| 7.791115
|
module ttl_74147 #(
parameter WIDTH_IN = 9,
WIDTH_OUT = 4,
DELAY_RISE = 0,
DELAY_FALL = 0
) (
input [ WIDTH_IN-1:0] A_bar,
output [WIDTH_OUT-1:0] Y_bar
);
//------------------------------------------------//
reg [WIDTH_OUT-1:0] computed;
always @(*) begin
casez (A_bar)
9'b0????????: computed = 4'b1001; // highest priority (inverted)
9'b10???????: computed = 4'b1000;
9'b110??????: computed = 4'b0111;
9'b1110?????: computed = 4'b0110;
9'b11110????: computed = 4'b0101;
9'b111110???: computed = 4'b0100;
9'b1111110??: computed = 4'b0011;
9'b11111110?: computed = 4'b0010;
9'b111111110: computed = 4'b0001;
9'b111111111: computed = 4'b0000;
default: computed = 4'b0000;
endcase
end
//------------------------------------------------//
assign #(DELAY_RISE, DELAY_FALL) Y_bar = ~computed;
endmodule
| 7.476256
|
module ttl_74148 #(
parameter WIDTH_IN = 8,
WIDTH_OUT = 3,
DELAY_RISE = 0,
DELAY_FALL = 0
) (
input EI_bar,
input [WIDTH_IN-1:0] A_bar,
output EO_bar,
output GS_bar,
output [WIDTH_OUT-1:0] Y_bar
);
//------------------------------------------------//
reg EO_computed;
reg GS_computed;
reg [WIDTH_OUT-1:0] Y_computed;
always @(*) begin
if (EI_bar) begin
// equal to EI (inverted)
EO_computed = 0;
// equal to EI (inverted)
GS_computed = 0;
// lowest priority (inverted)
Y_computed = 3'b000;
end else begin
// normally opposite of EI (inverted)
EO_computed = 0;
// normally equal to EI (inverted)
GS_computed = 1;
casez (A_bar)
8'b0???????: Y_computed = 3'b111;
8'b10??????: Y_computed = 3'b110;
8'b110?????: Y_computed = 3'b101;
8'b1110????: Y_computed = 3'b100;
8'b11110???: Y_computed = 3'b011;
8'b111110??: Y_computed = 3'b010;
8'b1111110?: Y_computed = 3'b001;
8'b11111110: Y_computed = 3'b000;
8'b11111111: begin
// exception: equal to EI (inverted)
EO_computed = 1;
// exception: opposite of EI (inverted)
GS_computed = 0;
// lowest priority (inverted)
Y_computed = 3'b000;
end
default: Y_computed = 3'b000;
endcase
end
end
//------------------------------------------------//
assign #(DELAY_RISE, DELAY_FALL) EO_bar = ~EO_computed;
assign #(DELAY_RISE, DELAY_FALL) GS_bar = ~GS_computed;
assign #(DELAY_RISE, DELAY_FALL) Y_bar = ~Y_computed;
endmodule
| 7.295172
|
module mod_7415 (
input A1,
input B1,
input C1,
output Y1,
input A2,
input B2,
input C2,
output Y2,
input A3,
input B3,
input C3,
output Y3
);
assign Y1 = A1 & B1 & C1;
assign Y2 = A2 & B2 & C2;
assign Y3 = A3 & B3 & C3;
endmodule
| 8.082515
|
module ttl_74150 #(
parameter WIDTH_IN = 16,
WIDTH_SELECT = $clog2(WIDTH_IN),
DELAY_RISE = 0,
DELAY_FALL = 0
) (
input Enable_bar,
input [WIDTH_SELECT-1:0] Select,
input [WIDTH_IN-1:0] D,
output Y_bar
);
//------------------------------------------------//
reg computed;
always @(*) begin
if (!Enable_bar) computed = D[Select];
else computed = 1'b0;
end
//------------------------------------------------//
assign #(DELAY_RISE, DELAY_FALL) Y_bar = ~computed;
endmodule
| 8.426074
|
module part_74S151 (
I0,
I1,
I2,
I3,
I4,
I5,
I6,
I7,
SEL0,
SEL1,
SEL2,
CE_N,
Q,
Q_N
);
input I0, I1, I2, I3, I4, I5, I6, I7;
input SEL0, SEL1, SEL2, CE_N;
output Q, Q_N;
// assign #(`REG_DELAY) Q =
assign Q =
( { SEL2, SEL1, SEL0 } == 3'b000 ) ? (I0 & ! CE_N) :
( { SEL2, SEL1, SEL0 } == 3'b001 ) ? (I1 & ! CE_N) :
( { SEL2, SEL1, SEL0 } == 3'b010 ) ? (I2 & ! CE_N) :
( { SEL2, SEL1, SEL0 } == 3'b011 ) ? (I3 & ! CE_N) :
( { SEL2, SEL1, SEL0 } == 3'b100 ) ? (I4 & ! CE_N) :
( { SEL2, SEL1, SEL0 } == 3'b101 ) ? (I5 & ! CE_N) :
( { SEL2, SEL1, SEL0 } == 3'b110 ) ? (I6 & ! CE_N) : (I7 & ! CE_N) ;
assign Q_N = !Q;
endmodule
| 6.925758
|
module ttl74151 (
Out,
S,
In
);
output Out;
input [2:0] S;
input [7:0] In;
// ON 74LS151, simplified (Select -> Z)
// data -> negZ is #(0:12:20)
// select -> negZ is #(0:20:32)
assign #(0:27:43) Out[0] =
( S[2] & S[1] & S[0] & In[7])
| ( S[2] & S[1] & !S[0] & In[6])
| ( S[2] & !S[1] & S[0] & In[5])
| ( S[2] & !S[1] & !S[0] & In[4])
| (!S[2] & S[1] & S[0] & In[3])
| (!S[2] & S[1] & !S[0] & In[2])
| (!S[2] & !S[1] & S[0] & In[1])
| (!S[2] & !S[1] & !S[0] & In[0]);
endmodule
| 7.016874
|
module ttl_74154 #(
parameter WIDTH_OUT = 16,
WIDTH_IN = $clog2(WIDTH_OUT),
DELAY_RISE = 0,
DELAY_FALL = 0
) (
input Enable1_bar,
input Enable2_bar,
input [WIDTH_IN-1:0] A,
output [WIDTH_OUT-1:0] Y
);
//------------------------------------------------//
reg [WIDTH_OUT-1:0] computed;
integer i;
always @(*) begin
for (i = 0; i < WIDTH_OUT; i++) begin
if (!Enable1_bar && !Enable2_bar && i == A) computed[i] = 1'b0;
else computed[i] = 1'b1;
end
end
//------------------------------------------------//
assign #(DELAY_RISE, DELAY_FALL) Y = computed;
endmodule
| 7.447309
|
module ttl_74155 #(parameter BLOCKS_DIFFERENT = 2, BLOCK0 = 0, BLOCK1 = 1, WIDTH_OUT = 4,
WIDTH_IN = $clog2(WIDTH_OUT), DELAY_RISE = 0, DELAY_FALL = 0)
(
input Enable1C,
input Enable1G_bar,
input Enable2C_bar,
input Enable2G_bar,
input [WIDTH_IN-1:0] A,
output [BLOCKS_DIFFERENT*WIDTH_OUT-1:0] Y_2D
);
//------------------------------------------------//
reg [WIDTH_OUT-1:0] computed [0:BLOCKS_DIFFERENT-1];
integer i;
always @(*)
begin
for (i = 0; i < WIDTH_OUT; i++)
begin
if (Enable1C && !Enable1G_bar && i == A)
computed[BLOCK0][i] = 1'b0;
else
computed[BLOCK0][i] = 1'b1;
if (!Enable2C_bar && !Enable2G_bar && i == A)
computed[BLOCK1][i] = 1'b0;
else
computed[BLOCK1][i] = 1'b1;
end
end
//------------------------------------------------//
assign #(DELAY_RISE, DELAY_FALL) Y_2D = `PACK_ARRAY(BLOCKS_DIFFERENT, WIDTH_OUT, computed)
endmodule
| 6.865215
|
module part_74S157 (
A1,
B1,
A2,
B2,
A3,
B3,
B4,
A4,
Y1,
Y2,
Y3,
Y4,
SEL,
ENB_N
);
input A1, B1, A2, B2, A3, B3, B4, A4;
output Y1, Y2, Y3, Y4;
input SEL, ENB_N;
assign Y1 = (SEL ? B1 : A1) & !ENB_N;
assign Y2 = (SEL ? B2 : A2) & !ENB_N;
assign Y3 = (SEL ? B3 : A3) & !ENB_N;
assign Y4 = (SEL ? B4 : A4) & !ENB_N;
/*
not
g1(_select, SEL),g2(_strobe, ENB_N);
buf #(`REG_DELAY)
g3(select2, SEL);
and #(`REG_DELAY)
g4(A_select, _strobe, _select),
g5(B_select, _strobe, select2);
and #(`REG_DELAY)
g6(l1, A1, A_select),
g7(l2, A2, A_select),
g8(l3, A3, A_select),
g9(l4, A4, A_select),
g10(l5, B1, B_select),
g11(l6, B2, B_select),
g12(l7, B3, B_select),
g13(l8, B4, B_select);
or #(`REG_DELAY)
g14(Y1, l1, l5),
g15(Y2, l2, l6),
g16(Y3, l3, l7),
g17(Y4, l4, l8);
*/
endmodule
| 6.800439
|
module ttl_74158 #(
parameter BLOCKS = 4,
WIDTH_IN = 2,
WIDTH_SELECT = $clog2(WIDTH_IN),
DELAY_RISE = 0,
DELAY_FALL = 0
) (
input Enable_bar,
input [WIDTH_SELECT-1:0] Select,
input [BLOCKS*WIDTH_IN-1:0] A_2D,
output [BLOCKS-1:0] Y_bar
);
//------------------------------------------------//
wire [WIDTH_IN-1:0] A[0:BLOCKS-1];
reg [BLOCKS-1:0] computed;
integer i;
always @(*) begin
for (i = 0; i < BLOCKS; i++) begin
if (!Enable_bar) computed[i] = A[i][Select];
else computed[i] = 1'b0;
end
end
//------------------------------------------------//
`ASSIGN_UNPACK_ARRAY(BLOCKS, WIDTH_IN, A, A_2D)
assign #(DELAY_RISE, DELAY_FALL) Y_bar = ~computed;
endmodule
| 7.874428
|
module mod_7416 (
input A1,
output Y1,
input A2,
output Y2,
input A3,
output Y3,
input A4,
output Y4,
input A5,
output Y5,
input A6,
output Y6
);
assign Y1 = A1 ? 1'b0 : 1'bz;
assign Y2 = A2 ? 1'b0 : 1'bz;
assign Y3 = A3 ? 1'b0 : 1'bz;
assign Y4 = A4 ? 1'b0 : 1'bz;
assign Y5 = A5 ? 1'b0 : 1'bz;
assign Y6 = A6 ? 1'b0 : 1'bz;
endmodule
| 6.857368
|
module ttl_74160 #(
parameter WIDTH = 4,
DELAY_RISE = 0,
DELAY_FALL = 0
) (
input Clear_bar,
input Load_bar,
input ENT,
input ENP,
input [WIDTH-1:0] D,
input Clk,
output RCO,
output [WIDTH-1:0] Q
);
//------------------------------------------------//
wire RCO_current;
reg [WIDTH-1:0] Q_current;
wire [WIDTH-1:0] Q_next;
assign Q_next = Q_current + 1;
always @(posedge Clk or negedge Clear_bar) begin
if (!Clear_bar) begin
Q_current <= 4'b0000;
end else begin
if (!Load_bar) begin
Q_current <= D;
end
if (Load_bar && ENT && ENP) begin
case (Q_current)
// abnormal inputs above BCD 9: return to the count range
4'b1010: Q_current <= 4'b1001;
4'b1100: Q_current <= 4'b1001;
4'b1110: Q_current <= 4'b1001;
4'b1011: Q_current <= 4'b0100;
4'b1101: Q_current <= 4'b0000;
4'b1111: Q_current <= 4'b0000;
// normal inputs
4'b1001: Q_current <= 4'b0000;
default: Q_current <= Q_next;
endcase
end
end
end
// output
assign RCO_current = ENT && Q_current == 4'b1001;
//------------------------------------------------//
assign #(DELAY_RISE, DELAY_FALL) RCO = RCO_current;
assign #(DELAY_RISE, DELAY_FALL) Q = Q_current;
endmodule
| 7.239641
|
module ttl_74161 #(
parameter WIDTH = 4,
DELAY_RISE = 0,
DELAY_FALL = 0
) (
input Clear_bar,
input Load_bar,
input ENT,
input ENP,
input [WIDTH-1:0] D,
input Clk,
output RCO,
output [WIDTH-1:0] Q
);
//------------------------------------------------//
wire RCO_current;
reg [WIDTH-1:0] Q_current;
wire [WIDTH-1:0] Q_next;
assign Q_next = Q_current + 1;
always @(posedge Clk or negedge Clear_bar) begin
if (!Clear_bar) begin
Q_current <= {WIDTH{1'b0}};
end else begin
if (!Load_bar) begin
Q_current <= D;
end
if (Load_bar && ENT && ENP) begin
Q_current <= Q_next;
end
end
end
// output
assign RCO_current = ENT && (&Q_current);
//------------------------------------------------//
assign #(DELAY_RISE, DELAY_FALL) RCO = RCO_current;
assign #(DELAY_RISE, DELAY_FALL) Q = Q_current;
endmodule
| 7.566493
|
module ttl_74162 #(
parameter WIDTH = 4,
DELAY_RISE = 0,
DELAY_FALL = 0
) (
input Clear_bar,
input Load_bar,
input ENT,
input ENP,
input [WIDTH-1:0] D,
input Clk,
output RCO,
output [WIDTH-1:0] Q
);
//------------------------------------------------//
wire RCO_current;
reg [WIDTH-1:0] Q_current;
wire [WIDTH-1:0] Q_next;
assign Q_next = Q_current + 1;
always @(posedge Clk) begin
if (!Clear_bar) begin
Q_current <= 4'b0000;
end else begin
if (!Load_bar) begin
Q_current <= D;
end
if (Load_bar && ENT && ENP) begin
case (Q_current)
// abnormal inputs above BCD 9: return to the count range
4'b1010: Q_current <= 4'b1001;
4'b1100: Q_current <= 4'b1001;
4'b1110: Q_current <= 4'b1001;
4'b1011: Q_current <= 4'b0100;
4'b1101: Q_current <= 4'b0000;
4'b1111: Q_current <= 4'b0000;
// normal inputs
4'b1001: Q_current <= 4'b0000;
default: Q_current <= Q_next;
endcase
end
end
end
// output
assign RCO_current = ENT && Q_current == 4'b1001;
//------------------------------------------------//
assign #(DELAY_RISE, DELAY_FALL) RCO = RCO_current;
assign #(DELAY_RISE, DELAY_FALL) Q = Q_current;
endmodule
| 7.213367
|
module ttl_74163 #(
parameter WIDTH = 4,
DELAY_RISE = 0,
DELAY_FALL = 0
) (
input Clear_bar,
input Load_bar,
input ENT,
input ENP,
input [WIDTH-1:0] D,
input Clk,
output RCO,
output [WIDTH-1:0] Q
);
//------------------------------------------------//
wire RCO_current;
reg [WIDTH-1:0] Q_current;
wire [WIDTH-1:0] Q_next;
assign Q_next = Q_current + 1;
always @(posedge Clk) begin
if (!Clear_bar) begin
Q_current <= {WIDTH{1'b0}};
end else begin
if (!Load_bar) begin
Q_current <= D;
end
if (Load_bar && ENT && ENP) begin
Q_current <= Q_next;
end
end
end
// output
assign RCO_current = ENT && (&Q_current);
//------------------------------------------------//
assign #(DELAY_RISE, DELAY_FALL) RCO = RCO_current;
assign #(DELAY_RISE, DELAY_FALL) Q = Q_current;
endmodule
| 7.201072
|
module dff (
q,
qbar,
d,
clock,
preset,
clear
);
output q, qbar;
input d, clock, preset, clear;
/*
nand #(`REG_DELAY)
g1(l1,preset,l4,l2),
g2(l2,l1,clear,clock),
g3(l3,l2,clock,l4),
g4(l4,l3,clear,d),
g5(q,preset,l2,qbar),
g6(qbar,q,clear,l3);
*/
reg q, qbar;
initial begin
q <= 0;
qbar <= 1;
end
always @(posedge clock) begin
q <= #(`REG_DELAY) d;
qbar <= #(`REG_DELAY) !d;
end
always @(clear or preset)
case ({
clear, preset
})
2'b01: begin
assign q = 0;
assign qbar = 1;
end
2'b10: begin
assign q = 1;
assign qbar = 0;
end
2'b11: begin
deassign q;
deassign qbar;
end
default: begin
assign q = 1'bx;
assign qbar = 1'bx;
end
endcase
endmodule
| 8.035763
|
module dff_no_rs (
q,
qbar,
d,
clock
);
output q, qbar;
input d, clock;
reg q, qbar;
initial begin
q <= #5 0;
qbar <= #5 1;
end
always @(posedge clock) begin
q <= #(`REG_DELAY) d;
qbar <= #(`REG_DELAY) !d;
end
endmodule
| 7.192117
|
module mod_7417 (
input A1,
output Y1,
input A2,
output Y2,
input A3,
output Y3,
input A4,
output Y4,
input A5,
output Y5,
input A6,
output Y6
);
assign Y1 = A1 ? 1'bz : 1'b0;
assign Y2 = A2 ? 1'bz : 1'b0;
assign Y3 = A3 ? 1'bz : 1'b0;
assign Y4 = A4 ? 1'bz : 1'b0;
assign Y5 = A5 ? 1'bz : 1'b0;
assign Y6 = A6 ? 1'bz : 1'b0;
endmodule
| 6.725798
|
module mod_7418 (
input A1,
input B1,
input C1,
input D1,
output Y1,
input A2,
input B2,
input C2,
input D2,
output Y2
);
assign Y1 = !(A1 & B1 & C1 & D1);
assign Y2 = !(A2 & B2 & C2 & D2);
endmodule
| 7.776845
|
module part_74S181 (
A0,
A1,
A2,
A3,
B0,
B1,
B2,
B3,
S0,
S1,
S2,
S3,
M,
CIN_N,
F0,
F1,
F2,
F3,
COUT_N,
Y,
X,
AEB
);
input A0, A1, A2, A3;
input B0, B1, B2, B3;
input S0, S1, S2, S3, M, CIN_N;
output F0, F1, F2, F3;
output COUT_N, Y, X, AEB;
wire [3:0] AA, BB, SS, FF;
assign AA[0] = A0;
assign AA[1] = A1;
assign AA[2] = A2;
assign AA[3] = A3;
assign BB[0] = B0;
assign BB[1] = B1;
assign BB[2] = B2;
assign BB[3] = B3;
assign SS[0] = S0;
assign SS[1] = S1;
assign SS[2] = S2;
assign SS[3] = S3;
ic_74S181 blah (
SS,
AA,
BB,
M,
CIN_N,
FF,
X,
Y,
COUT_N,
AEB
);
assign F0 = FF[0];
assign F1 = FF[1];
assign F2 = FF[2];
assign F3 = FF[3];
endmodule
| 6.505563
|
module ic_74S181 (
S,
A,
B,
M,
CNb,
F,
X,
Y,
CN4b,
AEB
);
input [3:0] A, B, S;
input CNb, M;
output [3:0] F;
output AEB, X, Y, CN4b;
TopLevel74181 Ckt74181 (
S,
A,
B,
M,
CNb,
F,
X,
Y,
CN4b,
AEB
);
endmodule
| 6.597979
|
module TopLevel74181 (
S,
A,
B,
M,
CNb,
F,
X,
Y,
CN4b,
AEB
);
input [3:0] A, B, S;
input CNb, M;
output [3:0] F;
output AEB, X, Y, CN4b;
wire [3:0] E, D, C, Bb;
Emodule Emod1 (
A,
B,
S,
E,
Bb
);
Dmodule Dmod2 (
A,
B,
Bb,
S,
D
);
CLAmodule CLAmod3 (
E,
D,
CNb,
C,
X,
Y,
CN4b
);
Summodule Summod4 (
E,
D,
C,
M,
F,
AEB
);
endmodule
| 6.940936
|
module part_74S182 (
X0,
X1,
X2,
Y0,
Y1,
Y2,
CIN_N,
XOUT,
YOUT,
X3,
Y3,
COUT0_N,
COUT1_N,
COUT2_N
);
input X0, X1, X2, Y0, Y1, Y2, CIN_N;
output XOUT, YOUT, X3, Y3;
output COUT0_N, COUT1_N, COUT2_N;
wire [3:0] XX, YY;
assign XX[0] = X0;
assign XX[1] = X1;
assign XX[2] = X2;
assign XX[3] = X3;
assign YY[0] = Y0;
assign YY[1] = Y1;
assign YY[2] = Y2;
assign YY[3] = Y3;
ic_74S182 blah (
CIN_N,
XX,
YY,
XOUT,
YOUT,
COUT0_N,
COUT1_N,
COUT2_N
);
endmodule
| 6.679769
|
module mod_7419 (
input A1,
output Y1,
input A2,
output Y2,
input A3,
output Y3,
input A4,
output Y4,
input A5,
output Y5,
input A6,
output Y6
);
assign Y1 = !A1;
assign Y2 = !A2;
assign Y3 = !A3;
assign Y4 = !A4;
assign Y5 = !A5;
assign Y6 = !A6;
endmodule
| 7.061951
|
module top_module (
input p1a,
p1b,
p1c,
p1d,
output p1y,
input p2a,
p2b,
p2c,
p2d,
output p2y
);
assign p1y = ~(p1a & p1b & p1c & p1d);
assign p2y = ~(p2a & p2b & p2c & p2d);
endmodule
| 7.203305
|
module top_module (
input p1a,
p1b,
p1c,
p1d,
output p1y,
input p2a,
p2b,
p2c,
p2d,
output p2y
);
assign p1y = !(p1a & p1b & p1c & p1d);
assign p2y = !(p2a & p2b & p2c & p2d);
endmodule
| 7.203305
|
module ttl_7421 #(
parameter BLOCKS = 2,
WIDTH_IN = 4,
DELAY_RISE = 0,
DELAY_FALL = 0
) (
input [BLOCKS*WIDTH_IN-1:0] A_2D,
output [BLOCKS-1:0] Y
);
//------------------------------------------------//
wire [WIDTH_IN-1:0] A[0:BLOCKS-1];
reg [BLOCKS-1:0] computed;
integer i;
always @(*) begin
for (i = 0; i < BLOCKS; i++) computed[i] = &A[i];
end
//------------------------------------------------//
`ASSIGN_UNPACK_ARRAY(BLOCKS, WIDTH_IN, A, A_2D)
assign #(DELAY_RISE, DELAY_FALL) Y = computed;
endmodule
| 6.725435
|
module mod_7422 (
input A1,
input B1,
input C1,
input D1,
output Y1,
input A2,
input B2,
input C2,
input D2,
output Y2
);
assign Y1 = !(A1 & B1 & C1 & D1);
assign Y2 = !(A2 & B2 & C2 & D2);
endmodule
| 7.285676
|
module mod_7423 (
input A1,
input B1,
input C1,
input D1,
input G1,
output Y1,
input A2,
input B2,
input C2,
input D2,
input G2,
output Y2
);
assign Y1 = !((A1 & G1) | (B1 & G1) | (C1 & G1) | (D1 & G1));
assign Y2 = !((A2 & G2) | (B2 & G2) | (C2 & G2) | (D2 & G2));
endmodule
| 6.932947
|
module ttl_74238 #(
parameter WIDTH_OUT = 8,
WIDTH_IN = $clog2(WIDTH_OUT),
DELAY_RISE = 0,
DELAY_FALL = 0
) (
input Enable1_bar,
input Enable2_bar,
input Enable3,
input [WIDTH_IN-1:0] A,
output [WIDTH_OUT-1:0] Y
);
//------------------------------------------------//
reg [WIDTH_OUT-1:0] computed;
integer i;
always @(*) begin
for (i = 0; i < WIDTH_OUT; i++) begin
if (!Enable1_bar && !Enable2_bar && Enable3 && i == A) computed[i] = 1'b1;
else computed[i] = 1'b0;
end
end
//------------------------------------------------//
assign #(DELAY_RISE, DELAY_FALL) Y = computed;
endmodule
| 7.205412
|
module mod_7424 (
input A1,
input B1,
output Y1,
input A2,
input B2,
output Y2,
input A3,
input B3,
output Y3,
input A4,
input B4,
output Y4
);
assign Y1 = !(A1 & B1);
assign Y2 = !(A2 & B2);
assign Y3 = !(A3 & B3);
assign Y4 = !(A4 & B4);
endmodule
| 8.208133
|
module mod_7425 (
input A1,
input B1,
input C1,
input D1,
input G1,
output Y1,
input A2,
input B2,
input C2,
input D2,
input G2,
output Y2
);
assign Y1 = !((A1 & G1) | (B1 & G1) | (C1 & G1) | (D1 & G1));
assign Y2 = !((A2 & G2) | (B2 & G2) | (C2 & G2) | (D2 & G2));
endmodule
| 7.404441
|
module mod_7426 (
input A1,
input B1,
output Y1,
input A2,
input B2,
output Y2,
input A3,
input B3,
output Y3,
input A4,
input B4,
output Y4
);
assign Y1 = !(A1 & B1);
assign Y2 = !(A2 & B2);
assign Y3 = !(A3 & B3);
assign Y4 = !(A4 & B4);
endmodule
| 7.713358
|
module ttl_74266 #(
parameter BLOCKS = 4,
WIDTH_IN = 2,
DELAY_RISE = 0,
DELAY_FALL = 0
) (
input [BLOCKS*WIDTH_IN-1:0] A_2D,
output [BLOCKS-1:0] Y
);
//------------------------------------------------//
wire [WIDTH_IN-1:0] A[0:BLOCKS-1];
reg [BLOCKS-1:0] computed;
integer i;
always @(*) begin
for (i = 0; i < BLOCKS; i++) computed[i] = ~(^A[i]);
end
//------------------------------------------------//
`ASSIGN_UNPACK_ARRAY(BLOCKS, WIDTH_IN, A, A_2D)
assign #(DELAY_RISE, DELAY_FALL) Y = computed;
endmodule
| 6.642506
|
module ttl_7427 #(
parameter BLOCKS = 3,
WIDTH_IN = 3,
DELAY_RISE = 0,
DELAY_FALL = 0
) (
input [BLOCKS*WIDTH_IN-1:0] A_2D,
output [BLOCKS-1:0] Y
);
//------------------------------------------------//
wire [WIDTH_IN-1:0] A[0:BLOCKS-1];
reg [BLOCKS-1:0] computed;
integer i;
always @(*) begin
for (i = 0; i < BLOCKS; i++) computed[i] = ~(|A[i]);
end
//------------------------------------------------//
`ASSIGN_UNPACK_ARRAY(BLOCKS, WIDTH_IN, A, A_2D)
assign #(DELAY_RISE, DELAY_FALL) Y = computed;
endmodule
| 7.1469
|
module mod_7428 (
input A1,
input B1,
output Y1,
input A2,
input B2,
output Y2,
input A3,
input B3,
output Y3,
input A4,
input B4,
output Y4
);
assign Y1 = !(A1 | B1);
assign Y2 = !(A2 | B2);
assign Y3 = !(A3 | B3);
assign Y4 = !(A4 | B4);
endmodule
| 7.922414
|
module part_74S280 (
I0,
I1,
I2,
I3,
I4,
I5,
I6,
I7,
I8,
EVEN,
ODD
);
input I0, I1, I2, I3, I4, I5, I6, I7, I8;
output EVEN, ODD;
//should change model to use A-G
// wire i1 = !( (A&!B&!C) | (!A&B&!C) | (!A&!B&C) | (A&B&C) );
// wire i2 = !( (D&!E&!F) | (!D&E&!F) | (!D&!E&F) | (D&E&F) );
// wire i3 = !( (G&!H&!I) | (!G&H&!I) | (!G&!H&I) | (G&H&I) );
wire i1 = !((I0 & !I1 & !I2) | (!I0 & I1 & !I2) | (!I0 & !I1 & I2) | (I0 & I1 & I2));
wire i2 = !((I3 & !I4 & !I5) | (!I3 & I4 & !I5) | (!I3 & !I4 & I5) | (I3 & I4 & I5));
wire i3 = !((I6 & !I7 & !I8) | (!I6 & I7 & !I8) | (!I6 & !I7 & I8) | (I6 & I7 & I8));
assign EVEN = !((!i1 & i2 & i3) | (i1 & !i2 & i3) | (i1 & i2 & !i3) | (!i1 & !i2 & !i3));
assign ODD = !((i1 & !i2 & !i3) | (!i1 & !i2 & !i3) | (!i1 & !i2 & i3) | (i1 & i2 & i3));
endmodule
| 6.852132
|
module ic_74S283 (
C0,
A,
B,
S,
C4
);
input [3:0] A, B;
input C0;
output [3:0] S;
output C4;
TopLevel74283 Ckt74283 (
C0,
A,
B,
S,
C4
);
endmodule
| 6.859582
|
module TopLevel74283 (
C0,
A,
B,
S,
C4
);
input [3:0] A, B;
input C0;
output [3:0] S;
output C4;
wire [3:0] GB, PB, AxB;
wire [3:0] C;
GP_Module GP_Mod1 (
A,
B,
GB,
PB,
AxB
);
CLA_Module CLA_Mod2 (
GB,
PB,
C0,
C,
C4
);
Sum_Module Sum_Mod3 (
AxB,
C,
S
);
endmodule
| 7.006232
|
module mod_7429 (
input A1,
input B1,
input C1,
input D1,
output Y1,
input A2,
input B2,
input C2,
input D2,
output Y2
);
assign Y1 = !(A1 | B1 | C1 | D1);
assign Y2 = !(A2 | B2 | C2 | D2);
endmodule
| 7.181854
|
module ttl_74352 #(
parameter BLOCKS = 2,
WIDTH_IN = 4,
WIDTH_SELECT = $clog2(WIDTH_IN),
DELAY_RISE = 0,
DELAY_FALL = 0
) (
input [BLOCKS-1:0] Enable_bar,
input [WIDTH_SELECT-1:0] Select,
input [BLOCKS*WIDTH_IN-1:0] A_2D,
output [BLOCKS-1:0] Y_bar
);
//------------------------------------------------//
wire [WIDTH_IN-1:0] A[0:BLOCKS-1];
reg [BLOCKS-1:0] computed;
integer i;
always @(*) begin
for (i = 0; i < BLOCKS; i++) begin
if (!Enable_bar[i]) computed[i] = A[i][Select];
else computed[i] = 1'b0;
end
end
//------------------------------------------------//
`ASSIGN_UNPACK_ARRAY(BLOCKS, WIDTH_IN, A, A_2D)
assign #(DELAY_RISE, DELAY_FALL) Y_bar = ~computed;
endmodule
| 8.251655
|
module part_74S373 (
I0,
I1,
I2,
I3,
I4,
I5,
I6,
I7,
O0,
O1,
O2,
O3,
O4,
O5,
O6,
O7,
HOLD_N,
OENB_N
);
input I0, I1, I2, I3, I4, I5, I6, I7;
input HOLD_N, OENB_N;
output O0, O1, O2, O3, O4, O5, O6, O7;
reg q0, q1, q2, q3, q4, q5, q6, q7;
initial begin
{q0, q1, q2, q3, q4, q5, q6, q7} <= 8'b0;
end
always @(I0 or I1 or I2 or I3 or I4 or I5 or I6 or I7 or HOLD_N)
if (HOLD_N) begin
{q0, q1, q2, q3, q4, q5, q6, q7} <= {I0, I1, I2, I3, I4, I5, I6, I7};
end
assign O0 = OENB_N ? 1'bz : q0;
assign O1 = OENB_N ? 1'bz : q1;
assign O2 = OENB_N ? 1'bz : q2;
assign O3 = OENB_N ? 1'bz : q3;
assign O4 = OENB_N ? 1'bz : q4;
assign O5 = OENB_N ? 1'bz : q5;
assign O6 = OENB_N ? 1'bz : q6;
assign O7 = OENB_N ? 1'bz : q7;
endmodule
| 6.742511
|
module ttl_74377 #(
parameter WIDTH = 8,
DELAY_RISE = 0,
DELAY_FALL = 0
) (
input Enable_bar,
input [WIDTH-1:0] D,
input Clk,
output [WIDTH-1:0] Q
);
//------------------------------------------------//
reg [WIDTH-1:0] Q_current;
always @(posedge Clk) begin
if (!Enable_bar) Q_current <= D;
end
//------------------------------------------------//
assign #(DELAY_RISE, DELAY_FALL) Q = Q_current;
endmodule
| 7.717928
|
module ttl7442 (
Out,
In,
En
);
output [7:0] Out;
input [2:0] In;
input En;
assign #20 Out[0] = En & !In[0] & !In[1] & !In[2];
assign #20 Out[1] = En & In[0] & !In[1] & !In[2];
assign #20 Out[2] = En & !In[0] & In[1] & !In[2];
assign #20 Out[3] = En & In[0] & In[1] & !In[2];
assign #20 Out[4] = En & !In[0] & !In[1] & In[2];
assign #20 Out[5] = En & In[0] & !In[1] & In[2];
assign #20 Out[6] = En & !In[0] & In[1] & In[2];
assign #20 Out[7] = En & In[0] & In[1] & In[2];
endmodule
| 6.880511
|
module ttl7442 (
Out,
In,
En
);
output [7:0] Out;
input [2:0] In;
input En;
// ON 74LS42, simplified
assign #(0: 20: 30) Out[0] = En & !In[0] & !In[1] & !In[2];
assign #(0: 20: 30) Out[1] = En & In[0] & !In[1] & !In[2];
assign #(0: 20: 30) Out[2] = En & !In[0] & In[1] & !In[2];
assign #(0: 20: 30) Out[3] = En & In[0] & In[1] & !In[2];
assign #(0: 20: 30) Out[4] = En & !In[0] & !In[1] & In[2];
assign #(0: 20: 30) Out[5] = En & In[0] & !In[1] & In[2];
assign #(0: 20: 30) Out[6] = En & !In[0] & In[1] & In[2];
assign #(0: 20: 30) Out[7] = En & In[0] & In[1] & In[2];
endmodule
| 6.880511
|
module part_74S472 (
A0,
A1,
A2,
A3,
A4,
A5,
A6,
A7,
A8,
D0,
D1,
D2,
D3,
D4,
D5,
D6,
D7,
CE_N
);
input A0, A1, A2, A3, A4, A5, A6, A7, A8, CE_N;
output D0, D1, D2, D3, D4, D5, D6, D7;
reg [7:0] prom[0:512];
initial begin
prom[0] = 0;
prom[511] = 0;
end
// assign #(`ROM_DELAY) {D7,D6,D5,D4,D3,D2,D1,D0} =
// CE_N ? 8'bzzzzzzzz : prom[ { A8, A7, A6, A5, A4, A3, A2, A1, A0 } ];
reg D0, D1, D2, D3, D4, D5, D6, D7;
always @(A8 or A7 or A6 or A5 or A4 or A3 or A2 or A1 or A0 or CE_N) begin
// if (CE_N == 0)
// $display("74472: prom ", {A8,A7,A6,A5,A4,A3,A2,A1,A0}, " CE_N ", CE_N);
case (CE_N)
1'b1: {D7, D6, D5, D4, D3, D2, D1, D0} <= 8'bzzzzzzzz;
1'b0: {D7, D6, D5, D4, D3, D2, D1, D0} <= prom[{A8, A7, A6, A5, A4, A3, A2, A1, A0}];
default: begin
{D7, D6, D5, D4, D3, D2, D1, D0} <= 8'bzzzzzzzz;
$display("jam ", {A8, A7, A6, A5, A4, A3, A2, A1, A0}, " CE_N ", CE_N);
end
endcase
end
endmodule
| 6.511965
|
module top_module (
input p1a,
p1b,
p1c,
p1d,
p1e,
p1f,
output p1y,
input p2a,
p2b,
p2c,
p2d,
output p2y
);
wire w1, w2, w3, w4;
and (w1, p2c, p2d);
and (w2, p2a, p2b);
or (p2y, w1, w2);
and (w3, p1a, p1b, p1c);
and (w4, p1f, p1e, p1d);
or (p1y, w3, w4);
endmodule
| 7.203305
|
module part_74S64 (
A1,
B1,
A2,
B2,
A3,
B3,
C3,
A4,
B4,
C4,
D4,
OUT
);
input A1, B1, A2, B2;
input A3, B3, C3;
input A4, B4, C4, D4;
output OUT;
// assign #(`REG_DELAY) OUT = ! ( (A1&B1) | (A2&B2) | (A3&B3&C3) | (A4&B4&C4&D4) );
assign OUT = !((A1 & B1) | (A2 & B2) | (A3 & B3 & C3) | (A4 & B4 & C4 & D4));
endmodule
| 6.967832
|
module C74669 (
input [3:0] DIN,
input CLK,
input DU,
input nLOAD,
output reg [3:0] QOUT,
output RCO
);
assign RCO = DU ? (QOUT == 4'd0) : (QOUT == 4'd15);
always @(posedge CLK or negedge nLOAD) begin
if (!nLOAD) QOUT <= DIN;
else QOUT <= DU ? QOUT - 4'd1 : QOUT + 4'd1;
end
endmodule
| 6.876684
|
module ttl7483 (
Out,
Kout,
A,
B,
Kin
);
output [3:0] Out;
output Kout;
input [3:0] A;
input [3:0] B;
input Kin;
assign #50{Kout, Out} = A + B + Kin;
endmodule
| 6.508535
|
module ttl7483 (
Out,
Kout,
A,
B,
Kin
);
output [3:0] Out;
output Kout;
input [3:0] A;
input [3:0] B;
input Kin;
// Motorola 74LS83
// C0->C4 propagation #(0:15:22)
assign #(0: 16: 24) {Kout, Out} = A + B + Kin;
endmodule
| 6.508535
|
module ttl_7485 #(
parameter WIDTH_IN = 4,
DELAY_RISE = 0,
DELAY_FALL = 0
) (
input [WIDTH_IN-1:0] A,
input [WIDTH_IN-1:0] B,
input ALess_in,
input Equal_in,
input AGreater_in,
output ALess_out,
output Equal_out,
output AGreater_out
);
//------------------------------------------------//
reg ALess_computed;
reg Equal_computed;
reg AGreater_computed;
always @(*) begin
if (A == B && !Equal_in && ALess_in == AGreater_in) begin
// abnormal inputs used in parallel expansion configuration
Equal_computed = 1'b0;
ALess_computed = !ALess_in;
AGreater_computed = !AGreater_in;
end else begin
// normal inputs
Equal_computed = A == B && Equal_in;
ALess_computed = !Equal_computed && {A, 1'b0} < {B, ALess_in};
AGreater_computed = !Equal_computed && {A, AGreater_in} > {B, 1'b0};
end
end
//------------------------------------------------//
assign #(DELAY_RISE, DELAY_FALL) ALess_out = ALess_computed;
assign #(DELAY_RISE, DELAY_FALL) Equal_out = Equal_computed;
assign #(DELAY_RISE, DELAY_FALL) AGreater_out = AGreater_computed;
endmodule
| 8.198788
|
module ttl7486 (
Out,
A,
B
);
output [3:0] Out;
input [3:0] A;
input [3:0] B;
xor #20 (Out[0], A[0], B[0]);
xor #20 (Out[1], A[1], B[1]);
xor #20 (Out[2], A[2], B[2]);
xor #20 (Out[3], A[3], B[3]);
endmodule
| 6.653544
|
module ttl7486 (
Out,
A,
B
);
output [3:0] Out;
input [3:0] A;
input [3:0] B;
// ON 74LS86, simplified assumptions
xor #(0: 20: 30) (Out[0], A[0], B[0]);
xor #(0: 20: 30) (Out[1], A[1], B[1]);
xor #(0: 20: 30) (Out[2], A[2], B[2]);
xor #(0: 20: 30) (Out[3], A[3], B[3]);
endmodule
| 6.653544
|
module mux_8_to_1 (
input G_n,
S2,
S1,
S0,
D7,
D6,
D5,
D4,
D3,
D2,
D1,
D0,
output Y,
Y_n
);
reg Y_r;
wire [2:0] S;
assign S = {S2, S1, S0};
always @(*) begin
if (G_n) Y_r <= 1'bz;
else
case (S)
3'b000: Y_r <= D0;
3'b001: Y_r <= D1;
3'b010: Y_r <= D2;
3'b011: Y_r <= D3;
3'b100: Y_r <= D4;
3'b101: Y_r <= D5;
3'b110: Y_r <= D6;
3'b111: Y_r <= D7;
endcase
end
assign Y = Y_r;
assign Y_n = ~Y;
endmodule
| 6.877137
|
module counter_74LS161 (
input CR,
input CP,
input LD,
input EP,
input ET,
input D0,
input D1,
input D2,
input D3,
output Q3,
output Q2,
output Q1,
output Q0,
output QC
);
reg [3:0] Q_tmp;
assign Q3 = (CR == 0) ? 0 : Q_tmp[3];
assign Q2 = (CR == 0) ? 0 : Q_tmp[2];
assign Q1 = (CR == 0) ? 0 : Q_tmp[1];
assign Q0 = (CR == 0) ? 0 : Q_tmp[0];
always @(posedge CP or negedge CR)
if (CR == 0) Q_tmp <= 0;
else if (CR == 1) begin
if (LD == 0) Q_tmp <= {D3, D2, D1, D0};
else if ((LD == 1 && EP == 0) | (LD == 1 && ET == 0)) Q_tmp <= Q_tmp;
else if (LD == 1 && EP == 1 && ET == 1) Q_tmp <= Q_tmp + 1;
end
endmodule
| 6.706131
|
module two_mux4_1 (
input A,
B,
input G1_n,
G2_n,
input D1_3,
D1_2,
D1_1,
D1_0,
input D2_3,
D2_2,
D2_1,
D2_0,
output Y1,
Y2
);
// module instantiation
mux4_1 A1 (
A,
B,
G1_n,
D1_3,
D1_2,
D1_1,
D1_0,
Y1
);
mux4_1 A2 (
A,
B,
G2_n,
D2_3,
D2_2,
D2_1,
D2_0,
Y2
);
endmodule
| 6.839577
|
module 74LS374(D,clk,en_able,Q);
input [7:0] D;
input en_able;
input clk;
output [7:0] Q;
wire [7:0] D;
reg [7:0] Q;
always @ ( posedge clk )
begin
if (en_able==0)
Q <= D;
else
Q <= 8'bzzzzzzzz;
end
endmodule
| 6.749774
|
module H7442 #(.delay(14)) (A0,A1,A2,A3,_Y0,_Y1,_Y2,_Y3,_Y4,_Y5,_Y6,_Y7,_Y8,_Y9);
input A0,A1,A2,A3;
output _Y0,_Y1,_Y2,_Y3,_Y4,_Y5,_Y6,_Y7,_Y8,_Y9;
wire c1_0, c1_1, c1_2, c1_3, c1_4, c1_5, c1_6;
assign c1_0 = ~(~A0 & ~A1);
assign c1_1 = ~(A0 & ~A1);
assign c1_2 = ~(~A0 & A1);
assign c1_3 = ~(A0 & A1);
assign c1_4 = ~(~A2 & ~A3);
assign c1_5 = ~(A2 & ~A3);
assign c1_6 = ~(~A2 & A3);
assign _Y0 = ~(~c1_0 & ~c1_4);
assign _Y1 = ~(~c1_1 & ~c1_4);
assign _Y2 = ~(~c1_2 & ~c1_4);
assign _Y3 = ~(~c1_3 & ~c1_4);
assign _Y4 = ~(~c1_0 & ~c1_5);
assign _Y5 = ~(~c1_1 & ~c1_5);
assign _Y6 = ~(~c1_2 & ~c1_5);
assign _Y7 = ~(~c1_3 & ~c1_5);
assign _Y8 = ~(~c1_0 & ~c1_6);
assign _Y9 = ~(~c1_1 & ~c1_6);
endmodule
| 6.834855
|
module H7402 #(.delay(4)) (A1,A2,A3,A4,B1,B2,B3,B4,Y1,Y2,Y3,Y4);
input A1,A2,A3,A4,B1,B2,B3,B4;
output Y1,Y2,Y3,Y4;
assign #delay Y1 = A1 ~| B1;
assign #delay Y2 = A2 ~| B2;
assign #delay Y3 = A3 ~| B3;
assign #delay Y4 = A4 ~| B4;
endmodule
| 7.230534
|
module H74181 #(.delay(4)) (_A0,_A1,_A2,_A3,_B0,_B1,_B2,_B3,S0,S1,S2,S3,Cn,M,_F0,_F1,_F2,_F3,AEB,CnP4,_G,_P);
input _A0,_A1,_A2,_A3;
input _B0,_B1,_B2,_B3;
input Cn,M;
input S0,S1,S2,S3;
output _F0,_F1,_F2,_F3;
output AEB,CnP4,_G,_P;
// First level gates outputs
wire L1_0,L1_1,L1_2,L1_3,L1_4,L1_5,L1_6,L1_7;
assign #delay L1_0 = ~( _A0 | (_B0 & S0) | (~_B0 & S1) );
assign #delay L1_1 = ~( (_A0 & ~_B0 & S2 ) | (_A0 & _B0 & S3) );
assign #delay L1_2 = ~( _A1 | (_B1 & S0) | (~_B1 & S1) );
assign #delay L1_3 = ~( (_A1 & ~_B1 & S2 ) | (_A1 & _B1 & S3) );
assign #delay L1_4 = ~( _A2 | (_B2 & S0) | (~_B2 & S1) );
assign #delay L1_5 = ~( (_A2 & ~_B2 & S2 ) | (_A2 & _B2 & S3) );
assign #delay L1_6 = ~( _A3 | (_B3 & S0) | (~_B3 & S1) );
assign #delay L1_7 = ~( (_A3 & ~_B3 & S2 ) | (_A3 & _B3 & S3) );
// Second level gates output
wire L2_0,L2_1,L2_2,L2_3;
assign #delay L2_0 = ~(~M & Cn);
assign #delay L2_1 = ~( (~M & L1_0) | (~M & L1_1 & Cn) );
assign #delay L2_2 = ~( (~M & L1_2) | (~M & L1_0 & L1_3) | (~M & L1_1 & L1_3 & Cn) );
assign #delay L2_3 = ~( (~M & L1_4) | (~M & L1_2 & L1_5) | (~M & L1_0 & L1_3 & L1_5) | (~M & L1_1 & L1_3 & L1_5 &Cn) );
assign #delay _F0 = L2_0 ^ (L1_0 ^ L1_1);
assign #delay _F1 = L2_1 ^ (L1_2 ^ L1_3);
assign #delay _F2 = L2_2 ^ (L1_4 ^ L1_5);
assign #delay _F3 = L2_3 ^ (L1_6 ^ L1_7);
assign #delay AEB = _F0 & _F1 & _F2 & _F3;
assign #delay _G = ~( L1_6 | (L1_4 & L1_7) | (L1_2 & L1_5 & L1_7) | (L1_0 & L1_3 & L1_5 & L1_7) );
assign #delay CnP4 = ~_G | ( L1_1 & L1_3 & L1_5 & L1_7 & Cn );
assign #delay _P = ~( L1_1 & L1_3 & L1_5 & L1_7 );
endmodule
| 8.029435
|
module H7486 #(.delay(4)) (A1,A2,A3,A4,B1,B2,B3,B4,Y1,Y2,Y3,Y4);
input A1,A2,A3,A4,B1,B2,B3,B4;
output Y1,Y2,Y3,Y4;
assign #delay Y1 = A1 ^ B1;
assign #delay Y2 = A2 ^ B2;
assign #delay Y3 = A3 ^ B3;
assign #delay Y4 = A4 ^ B4;
endmodule
| 7.125615
|
module H7408 #(.delay(4)) (A1,A2,A3,A4,B1,B2,B3,B4,Y1,Y2,Y3,Y4);
input A1,A2,A3,A4,B1,B2,B3,B4;
output Y1,Y2,Y3,Y4;
assign #delay Y1 = A1 & B1;
assign #delay Y2 = A2 & B2;
assign #delay Y3 = A3 & B3;
assign #delay Y4 = A4 & B4;
endmodule
| 6.961951
|
module H7410 #(.delay(6)) (A1,A2,A3,B1,B2,B3,C1,C2,C3,Y1,Y2,Y3);
input A1,A2,A3,B1,B2,B3,C1,C2,C3;
output Y1,Y2,Y3;
assign #delay Y1 = ~(A1 & B1 & C1);
assign #delay Y2 = ~(A2 & B2 & C2);
assign #delay Y3 = ~(A3 & B3 & C3);
endmodule
| 6.66199
|
module H7400 #(.delay(4)) (A1,A2,A3,A4,B1,B2,B3,B4,Y1,Y2,Y3,Y4);
input A1,A2,A3,A4,B1,B2,B3,B4;
output Y1,Y2,Y3,Y4;
assign #delay Y1 = A1 ~& B1;
assign #delay Y2 = A2 ~& B2;
assign #delay Y3 = A3 ~& B3;
assign #delay Y4 = A4 ~& B4;
endmodule
| 7.058931
|
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