code
stringlengths 35
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| score
float64 6.5
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|
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module Multiplexer_64Bit (
A,
B,
Select,
Result
);
input [63:0] A;
input [63:0] B;
input Select;
output reg [63:0] Result;
always @(A, B, Select) begin
case (Select)
0: assign Result = A;
1: assign Result = B;
endcase
end
endmodule
| 6.970876
|
module p_sbox (
input [32:1] msg,
output [32:1] p_msg
);
assign p_msg[1] = msg[16];
assign p_msg[2] = msg[7];
assign p_msg[3] = msg[20];
assign p_msg[4] = msg[21];
assign p_msg[5] = msg[29];
assign p_msg[6] = msg[12];
assign p_msg[7] = msg[28];
assign p_msg[8] = msg[17];
assign p_msg[9] = msg[1];
assign p_msg[10] = msg[15];
assign p_msg[11] = msg[23];
assign p_msg[12] = msg[26];
assign p_msg[13] = msg[5];
assign p_msg[14] = msg[18];
assign p_msg[15] = msg[31];
assign p_msg[16] = msg[10];
assign p_msg[17] = msg[2];
assign p_msg[18] = msg[8];
assign p_msg[19] = msg[24];
assign p_msg[20] = msg[14];
assign p_msg[21] = msg[32];
assign p_msg[22] = msg[27];
assign p_msg[23] = msg[3];
assign p_msg[24] = msg[9];
assign p_msg[25] = msg[19];
assign p_msg[26] = msg[13];
assign p_msg[27] = msg[30];
assign p_msg[28] = msg[6];
assign p_msg[29] = msg[22];
assign p_msg[30] = msg[11];
assign p_msg[31] = msg[4];
assign p_msg[32] = msg[25];
endmodule
| 6.76519
|
module f (
input [32:1] msg_r,
input [48:1] key,
output [32:1] f_out
);
wire [48:1] temp, emsg_r;
wire [32:1] temp_s_box;
wire [4:1] s_box1, s_box2, s_box3, s_box4, s_box5, s_box6, s_box7, s_box8;
wire [5:0] B1, B2, B3, B4, B5, B6, B7, B8;
e inst (
msg_r,
emsg_r
);
assign temp = key ^ emsg_r;
assign B8 = temp[48:43];
assign B7 = temp[42:37];
assign B6 = temp[36:31];
assign B5 = temp[30:25];
assign B4 = temp[24:19];
assign B3 = temp[18:13];
assign B2 = temp[12:7];
assign B1 = temp[6:1];
s_box s1 (
B1,
4'd1,
s_box1
);
s_box s2 (
B2,
4'd2,
s_box2
);
s_box s3 (
B3,
4'd3,
s_box3
);
s_box s4 (
B4,
4'd4,
s_box4
);
s_box s5 (
B5,
4'd5,
s_box5
);
s_box s6 (
B6,
4'd6,
s_box6
);
s_box s7 (
B7,
4'd7,
s_box7
);
s_box s8 (
B8,
4'd8,
s_box8
);
assign temp_s_box = {s_box1, s_box2, s_box3, s_box4, s_box5, s_box6, s_box7, s_box8};
p_sbox obj (
temp_s_box,
f_out
);
initial begin
#6 $display("e_msg_r = %b", emsg_r);
$display("key = %b", key);
$display("sbox_i = %b", temp);
$display("sbox_o = %b", temp_s_box);
$display("f_out = %b", f_out);
end
endmodule
| 6.572024
|
module gf2m #(
parameter DIGITAL = 64,
parameter DATA_WIDTH = 163
) (
input wire rst,
input wire clk,
input wire start,
input wire [DATA_WIDTH - 1 : 0] a,
input wire [DATA_WIDTH - 1 : 0] g,
input wire [DIGITAL - 1:0] b,
output reg [DATA_WIDTH - 1 : 0] t_i_j,
output reg done
);
parameter ITERATION_NUMBER = DATA_WIDTH / DIGITAL;
parameter IDLE = 1'b0;
parameter CAL = 1'b1;
reg state;
reg [12:0] counter;
wire [DATA_WIDTH - 1 : 0] wire_t_i_j;
serial serial_8_bit (
.b(b),
.a(a),
.g(g),
.t_i1_j1(t_i_j),
.t_i_j(wire_t_i_j)
);
always @(posedge clk or negedge rst) begin : proc_counter
if (~rst) begin
counter <= 0;
end else begin
case (state)
IDLE: begin
counter <= 6'd0;
end
CAL: begin
if (counter < ITERATION_NUMBER) counter <= counter + 1;
else counter <= 6'd0;
end
default: /* default */;
endcase
end
end
always @(posedge clk or negedge rst) begin : proc_t_i_j
if (~rst) begin
t_i_j <= 0;
end else begin
case (state)
IDLE: t_i_j <= 0;
CAL: t_i_j <= wire_t_i_j;
default: t_i_j <= 0;
endcase
end
end
always @(posedge clk or negedge rst) begin : proc_done
if (~rst) begin
done <= 0;
end else begin
case (state)
IDLE: done <= 0;
CAL: begin
if (counter < ITERATION_NUMBER) done <= 0;
else done <= 1'b1;
end
default: done <= 0;
endcase
end
end
always @(posedge clk or negedge rst) begin : proc_state
if (~rst) begin
state <= IDLE;
end else begin
case (state)
IDLE: begin : IDLE_STATE
if (start) state <= CAL;
else state <= state;
end
CAL: begin : CAL_STATE
if (counter < ITERATION_NUMBER) state <= CAL;
else state <= IDLE;
end
default: state <= IDLE;
endcase
end
end
endmodule
| 7.196913
|
module p_sbox (
input [1:32] msg,
output [1:32] p_msg
);
assign p_msg[1] = msg[16];
assign p_msg[2] = msg[7];
assign p_msg[3] = msg[20];
assign p_msg[4] = msg[21];
assign p_msg[5] = msg[29];
assign p_msg[6] = msg[12];
assign p_msg[7] = msg[28];
assign p_msg[8] = msg[17];
assign p_msg[9] = msg[1];
assign p_msg[10] = msg[15];
assign p_msg[11] = msg[23];
assign p_msg[12] = msg[26];
assign p_msg[13] = msg[5];
assign p_msg[14] = msg[18];
assign p_msg[15] = msg[31];
assign p_msg[16] = msg[10];
assign p_msg[17] = msg[2];
assign p_msg[18] = msg[8];
assign p_msg[19] = msg[24];
assign p_msg[20] = msg[14];
assign p_msg[21] = msg[32];
assign p_msg[22] = msg[27];
assign p_msg[23] = msg[3];
assign p_msg[24] = msg[9];
assign p_msg[25] = msg[19];
assign p_msg[26] = msg[13];
assign p_msg[27] = msg[30];
assign p_msg[28] = msg[6];
assign p_msg[29] = msg[22];
assign p_msg[30] = msg[11];
assign p_msg[31] = msg[4];
assign p_msg[32] = msg[25];
endmodule
| 6.76519
|
module f (
input [1:32] msg_r,
input [1:48] key,
output [1:32] f_out
);
wire [1:48] temp, emsg_r;
wire [1:32] temp_s_box;
wire [4:1] s_box1, s_box2, s_box3, s_box4, s_box5, s_box6, s_box7, s_box8;
wire [5:0] B1, B2, B3, B4, B5, B6, B7, B8;
e inst (
msg_r,
emsg_r
);
assign temp = key ^ emsg_r;
assign B8 = temp[43:48];
assign B7 = temp[37:42];
assign B6 = temp[31:36];
assign B5 = temp[25:30];
assign B4 = temp[19:24];
assign B3 = temp[13:18];
assign B2 = temp[7:12];
assign B1 = temp[1:6];
s_box s1 (
B1,
4'd1,
s_box1
);
s_box s2 (
B2,
4'd2,
s_box2
);
s_box s3 (
B3,
4'd3,
s_box3
);
s_box s4 (
B4,
4'd4,
s_box4
);
s_box s5 (
B5,
4'd5,
s_box5
);
s_box s6 (
B6,
4'd6,
s_box6
);
s_box s7 (
B7,
4'd7,
s_box7
);
s_box s8 (
B8,
4'd8,
s_box8
);
assign temp_s_box = {s_box1, s_box2, s_box3, s_box4, s_box5, s_box6, s_box7, s_box8};
p_sbox obj (
temp_s_box,
f_out
);
// initial begin
// #6
// $display("e_msg_r = %b",emsg_r);
// $display("key1 = %b",key);
// $display("sbox_i = %b",temp);
// $display("sbox_o = %b",temp_s_box);
// $display("f_out = %b",f_out);
// end
endmodule
| 6.572024
|
module fpga_gf2m #(
parameter DIGITAL = 64,
parameter DATA_WIDTH = 163
) (
input clk, // Clock
input rst, // Asynchronous reset active low
input wire start,
input wire [DATA_WIDTH - 1 : 0] a,
input wire [DATA_WIDTH - 1 : 0] g,
input wire [BWIDTH - 1:0] b,
output reg [DATA_WIDTH - 1 : 0] t_i_j,
output reg done
);
parameter ITERATION_NUMBER = DATA_WIDTH / DIGITAL;
parameter BWIDTH = (ITERATION_NUMBER + 1) * DIGITAL;
parameter IDLE = 2'b00;
parameter CAL = 2'b01;
parameter DONE = 2'b10;
reg state;
reg [12:0] counter;
reg [DATA_WIDTH - 1 : 0] reg_a;
reg [DATA_WIDTH - 1 : 0] reg_g;
reg [BWIDTH - 1:0] reg_b;
wire [DIGITAL - 1:0] b_in;
wire [DATA_WIDTH - 1 : 0] out_t_i_j;
wire wire_done;
gf2m fpgainst (
.rst(rst),
.clk(clk),
.start(start),
.a(reg_a),
.g(reg_g),
.b(b_in),
.t_i_j(out_t_i_j),
.done(wire_done)
);
// done
always @(posedge clk or negedge rst) begin : proc_done
if (~rst) begin
done <= 0;
end else begin
case (wire_done)
1'b0: done <= done;
1'b1: done <= 1'b1;
default: done <= done;
endcase
end
end
always @(posedge clk or negedge rst) begin : proc_t_i_j
if (~rst) begin
t_i_j <= 0;
end else begin
case (wire_done)
1'b0: t_i_j <= t_i_j;
1'b1: t_i_j <= out_t_i_j;
default: t_i_j <= t_i_j;
endcase
end
end
// counter
always @(posedge clk or negedge rst) begin : proc_counter
if (~rst) begin
counter <= 0;
end else begin
case (state)
IDLE: begin
counter <= 12'd0;
end
CAL: begin
if (counter < ITERATION_NUMBER) counter <= counter + 1;
else counter <= 12'd0;
end
default: counter <= 12'd0;
endcase
end
end
// reg_b_in
assign b_in = reg_b[(ITERATION_NUMBER+1)*DIGITAL-1 : (ITERATION_NUMBER)*DIGITAL];
// reg_a
always @(posedge clk or negedge rst) begin : reg_a34
if (~rst) begin
reg_a <= 0;
end else begin
case (state)
IDLE: begin
if (start) reg_a <= a;
else reg_a <= 0;
end
default: reg_a <= reg_a;
endcase
end
end
// reg_b
always @(posedge clk or negedge rst) begin : reg_b24
if (~rst) begin
reg_b <= 0;
end else begin
case (state)
IDLE: begin
if (start) reg_b <= b;
else reg_b <= 0;
end
CAL: begin
reg_b = reg_b <<< DIGITAL;
end
default: reg_b <= reg_b;
endcase
end
end
// reg_g
always @(posedge clk or negedge rst) begin : proc_reg_g32
if (~rst) begin
reg_g <= 0;
end else begin
case (state)
IDLE: begin
if (start) reg_g <= g;
else reg_g <= 0;
end
default: reg_g <= reg_g;
endcase
end
end
always @(posedge clk or negedge rst) begin : proc_state_machine
if (~rst) begin
state <= IDLE;
end else begin
case (state)
IDLE: begin
if (start) begin
state <= CAL;
end else begin
state <= state;
end
end
CAL: begin
if (counter < ITERATION_NUMBER) state <= CAL;
else state <= DONE;
end
DONE: begin
state <= DONE;
end
default: state <= IDLE;
endcase
end
end
endmodule
| 6.91314
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? (~distance) : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? '0 : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? '1 : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : (~0)));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : '0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : '1));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + ((!btaken) ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (0 ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (1 ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module full_and (
input [63:0] a,
b,
output [63:0] o
);
genvar i;
for (i = 0; i < 64; i = i + 1) begin
and (o[i], a[i], b[i]);
end
endmodule
| 7.417589
|
module full_xor (
input [63:0] a,
b,
output [63:0] o
);
genvar i;
for (i = 0; i < 64; i = i + 1) begin
xor (o[i], a[i], b[i]);
end
endmodule
| 7.075206
|
module top_module (
input [1023:0] in,
input [7:0] sel,
output [3:0] out
);
assign out = in[sel*4+3-:4];
endmodule
| 7.203305
|
module decadj_half_adder (
input [3:0] dec_in,
output wire [3:0] dec_out,
input carry_in,
input dec_add,
input dec_sub,
input half
);
wire [3:0] correction_factor;
wire add_adj, sub_adj;
assign add_adj = dec_add & carry_in;
assign sub_adj = dec_sub & ~carry_in;
assign correction_factor = {sub_adj, add_adj, add_adj | sub_adj, 1'b0};
assign dec_out = dec_in + correction_factor;
endmodule
| 7.382223
|
module alu_adder (
input [7:0] add_in1,
input [7:0] add_in2,
input add_cin,
input dec_add,
output wire [7:0] add_out,
output wire carry_out,
output wire half_carry_out
);
wire dec_carry_out; // unused
alu_half_adder low (
add_in1[3:0],
add_in2[3:0],
add_cin,
dec_add,
add_out[3:0],
half_carry_out,
dec_half_carry_out,
1'b0
);
alu_half_adder high (
add_in1[7:4],
add_in2[7:4],
half_carry_out,
dec_add,
add_out[7:4],
carry_out,
dec_carry_out,
1'b1
);
endmodule
| 6.784883
|
module alu_unit (
input clk,
input ready,
input [7:0] a,
input [7:0] b,
output reg [7:0] alu_out,
input c_in,
input dec_add,
input [3:0] op,
output reg carry_out,
output wire half_carry_out,
output wire overflow_out,
output reg alu_carry_out_last
);
reg c;
wire [7:0] add_out;
reg [7:0] tmp;
wire adder_carry_out;
alu_adder add_u (
a,
b,
c_in,
dec_add,
add_out,
adder_carry_out,
half_carry_out
);
assign overflow_out = a[7] == b[7] && a[7] != add_out[7];
always @(*) begin
case (op) // synthesis full_case parallel_case
`ALU_ORA: begin
c = 0;
tmp = a | b;
end
`ALU_AND: begin
tmp = a & b;
c = |tmp; // This is a bit of a hack, used for 65C02 branch bit tests.
end
`ALU_EOR: begin
c = 0;
tmp = a ^ b;
end
`ALU_ADC, `ALU_SBC: begin
c = adder_carry_out;
tmp = add_out;
end
`ALU_ROR: begin
{tmp, c} = {c_in, a};
end
//`ALU_TST:
// begin
// c = 0;
// tmp = ~a & b;
// end
`ALU_PSA: // Passthrough, used when I just needed the ALU to hold onto something for a cycle. The real 6502 has an output hold register.
begin
c = 0;
tmp = a;
end
endcase
alu_out = tmp;
carry_out = c;
//$strobe("ALU a: %02x b: %02x c_in: %d -> %02x daa: %d flags vc: %d%d hc: %d",a,b,c_in,tmp,dec_add,overflow_out,carry_out,half_carry_out);
end
always @(posedge clk) begin
if (ready) alu_carry_out_last <= carry_out;
end
endmodule
| 7.428704
|
module decoder3to8 (
input [2:0] index,
output reg [7:0] outbits
);
always @(*) begin
case (index)
0: outbits = 8'b00000001;
1: outbits = 8'b00000010;
2: outbits = 8'b00000100;
3: outbits = 8'b00001000;
4: outbits = 8'b00010000;
5: outbits = 8'b00100000;
6: outbits = 8'b01000000;
7: outbits = 8'b10000000;
endcase
end
endmodule
| 8.532605
|
module alua_mux (
input clk,
input ready,
input [2:0] alu_a,
input [7:0] sb,
input [7:0] ir_dec,
output reg [7:0] alua
);
reg [7:0] aluas;
// ALU A input select
always @(*) begin
case (alu_a) // synthesis full_case parallel_case
`ALU_A_0: aluas = 8'h00;
`ALU_A_SB: aluas = sb;
`ALU_A_NSB: aluas = ~sb;
`ifdef CMOS
`ALU_A_IR: aluas = ir_dec;
`ALU_A_NIR: aluas = ~ir_dec;
`endif
endcase
end
always @(posedge clk) begin
if (ready) begin
alua <= aluas;
end
end
endmodule
| 6.528778
|
module alub_mux (
input clk,
input ready,
input [1:0] alu_b,
input [7:0] db,
input [7:0] adl,
output reg [7:0] alub
);
reg [7:0] alubs;
// ALU B input select
always @(*) begin
case (alu_b) // synthesis full_case parallel_case
`ALU_B_DB: alubs = db;
`ALU_B_NDB: alubs = ~db;
`ALU_B_ADL: alubs = adl;
endcase
end
always @(posedge clk) begin
if (ready) begin
alub <= alubs;
end
end
endmodule
| 6.888262
|
module aluc_mux (
input [1:0] alu_c,
input carry,
input last_carry,
output reg carrys
);
// ALU C (carry) input select
always @(*) begin
case (alu_c) // synthesis full_case parallel_case
`ALU_C_0: carrys = 0;
`ALU_C_1: carrys = 1;
`ALU_C_P: carrys = carry;
`ALU_C_A: carrys = last_carry;
endcase
end
endmodule
| 6.903394
|
module db_in_mux (
input [2:0] db_sel,
input [7:0] data_i,
input [7:0] reg_a,
input alua_highbit,
output reg [7:0] db_in
);
// DB input mux
always @(*) begin
case (db_sel) // synthesis full_case parallel_case
`DB_0: db_in = 8'h00;
//`DB_DI : db_in = data_i;
//`DB_SB : db_in = data_i; // Temp hack
//`DB_PCH : db_in = data_i;
`DB_A: db_in = reg_a;
`DB_BO:
db_in = {8{alua_highbit}}; // The high bit of the last ALU A input is the sign bit for branch offsets
default: db_in = data_i;
endcase
//$display("data_i: %02x db_in: %02x",data_i,db_in);
end
endmodule
| 7.905946
|
module db_out_mux (
input [2:0] db_sel,
input [7:0] reg_a,
input [7:0] sb,
input [7:0] pcl,
input [7:0] pch,
input [7:0] reg_p,
output reg [7:0] db_out
);
// DB output mux
always @(*) begin
case (db_sel) // synthesis full_case parallel_case
`DB_A: db_out = reg_a;
`DB_SB: db_out = sb;
`DB_PCL: db_out = pcl;
`DB_PCH: db_out = pch;
`DB_P: db_out = reg_p;
`DB_0: db_out = 8'h00;
endcase
end
endmodule
| 7.307923
|
module ir_next_mux (
input sync,
input intg,
input [7:0] data_i,
input [7:0] ir,
output reg [7:0] ir_next
);
// IR input
always @(*) begin
if (sync) begin
if (intg) ir_next = 8'h00;
else ir_next = data_i;
end else ir_next = ir;
end
endmodule
| 7.073816
|
module flags_decode (
input [3:0] load_flags,
output reg [14:0] load_flags_decode
);
always @(*)
case (load_flags) // synthesis full_case parallel_case
`none: load_flags_decode = 0;
`FLAGS_DB:
load_flags_decode = (`LM_C_DB0 | `LM_Z_DB1 | `LM_I_DB2 | `LM_D_DB3 | `LM_V_DB6 | `LM_N_DB7);
`FLAGS_SBZN: load_flags_decode = (`LM_Z_SBZ | `LM_N_SBN);
`FLAGS_D: load_flags_decode = (`LM_D_IR5);
`FLAGS_I: load_flags_decode = (`LM_I_IR5);
`FLAGS_C: load_flags_decode = (`LM_C_IR5);
`FLAGS_V: load_flags_decode = (`LM_V_0);
`FLAGS_Z: load_flags_decode = (`LM_Z_SBZ);
`FLAGS_CNZ: load_flags_decode = (`LM_C_ACR | `LM_Z_SBZ | `LM_N_SBN);
`FLAGS_ALU: load_flags_decode = (`LM_C_ACR | `LM_V_AVR | `LM_Z_SBZ | `LM_N_SBN);
`FLAGS_BIT: load_flags_decode = (`LM_V_DB6 | `LM_N_DB7);
`ifdef CMOS
`FLAGS_SETI: load_flags_decode = (`LM_I_1 | `LM_D_IR5); // Clear D flag too
`else
`FLAGS_SETI: load_flags_decode = (`LM_I_1);
`endif
endcase
endmodule
| 6.585277
|
module clocked_reg8 (
input clk,
input ready,
input [7:0] register_in,
output reg [7:0] register_out
);
always @(posedge clk) begin
if (ready) begin
register_out <= register_in;
end
end
endmodule
| 7.084839
|
module clocked_reset_reg8 (
input clk,
input reset,
input ready,
input [7:0] register_in,
output reg [7:0] register_out
);
always @(posedge clk) begin
if (reset) register_out <= 0;
else if (ready) begin
register_out <= register_in;
end
end
endmodule
| 7.653837
|
module p_reg (
input clk,
input reset,
input ready,
input intg,
input [14:0] load_flag_decode,
input load_b,
input [7:0] db_in,
input sb_z,
input sb_n,
input carry,
input overflow,
input ir5,
output reg [7:0] reg_p
);
always @(*) begin
reg_p[`PF_B] = ~intg;
reg_p[`PF_U] <= 1;
end
always @(posedge clk) begin
if (ready) begin
if (load_flag_decode[`LF_C_ACR]) reg_p[`PF_C] = carry;
else if (load_flag_decode[`LF_C_IR5]) reg_p[`PF_C] = ir5;
else if (load_flag_decode[`LF_C_DB0]) reg_p[`PF_C] = db_in[0];
if (load_flag_decode[`LF_Z_SBZ]) reg_p[`PF_Z] = sb_z;
else if (load_flag_decode[`LF_Z_DB1]) reg_p[`PF_Z] = db_in[1];
if (load_flag_decode[`LF_I_DB2]) reg_p[`PF_I] = db_in[2];
else if (load_flag_decode[`LF_I_IR5]) reg_p[`PF_I] = ir5;
else if (load_flag_decode[`LF_I_1]) reg_p[`PF_I] = 1;
if (load_flag_decode[`LF_D_DB3]) reg_p[`PF_D] = db_in[3];
else if (load_flag_decode[`LF_D_IR5]) reg_p[`PF_D] = ir5;
if (load_flag_decode[`LF_V_AVR]) reg_p[`PF_V] = overflow;
else if (load_flag_decode[`LF_V_DB6]) reg_p[`PF_V] = db_in[6];
else if (load_flag_decode[`LF_V_0]) reg_p[`PF_V] = 0;
if (load_flag_decode[`LF_N_SBN]) reg_p[`PF_N] = sb_n;
else if (load_flag_decode[`LF_N_DB7]) reg_p[`PF_N] = db_in[7];
end
end
endmodule
| 6.738303
|
module adl_abl_reg (
input clk,
input ready,
input load_abl,
input [2:0] adl_sel,
input [7:0] data_i,
input [7:0] pcls,
input [7:0] reg_s,
input [7:0] alu,
input [7:0] vector_lo,
output reg [7:0] adl_abl,
output reg [7:0] abl_next,
output reg [7:0] abl
);
// ADL -> ABL
always @(*) begin
case (adl_sel) // synthesis full_case parallel_case
`ADL_DI: adl_abl = data_i;
`ADL_PCLS: adl_abl = pcls;
`ADL_S: adl_abl = reg_s;
`ADL_ALU: adl_abl = alu;
`ADL_VECLO: adl_abl = vector_lo;
`ADL_VECHI: adl_abl = {vector_lo[7:1], 1'b1};
endcase
end
always @(*) begin
if (load_abl && ready) abl_next = adl_abl;
else abl_next = abl;
end
always @(posedge clk) begin
if (load_abl && ready) begin
abl <= adl_abl;
end
end
endmodule
| 6.799146
|
module rom_6502 (
input clk,
input [11:0] address,
input oe,
output reg valid,
output reg [ 7:0] q_a
);
reg [127:0] mem[255:0];
integer i;
initial begin
for (i = 0; i < 255; i = i + 1) begin
mem[i] = 8'd0; // This will be changed with the orginal rom
end
$readmemh("6502.mem", mem);
end
always @(posedge clk) begin
case (address[3:0])
5'hf: q_a <= mem[address[11:4]][7:0];
5'he: q_a <= mem[address[11:4]][15:8];
5'hd: q_a <= mem[address[11:4]][23:16];
5'hc: q_a <= mem[address[11:4]][31:24];
5'hb: q_a <= mem[address[11:4]][39:32];
5'ha: q_a <= mem[address[11:4]][47:40];
5'h9: q_a <= mem[address[11:4]][55:48];
5'h8: q_a <= mem[address[11:4]][63:56];
5'h7: q_a <= mem[address[11:4]][71:64];
5'h6: q_a <= mem[address[11:4]][79:72];
5'h5: q_a <= mem[address[11:4]][87:80];
5'h4: q_a <= mem[address[11:4]][95:88];
5'h3: q_a <= mem[address[11:4]][103:96];
5'h2: q_a <= mem[address[11:4]][111:104];
5'h1: q_a <= mem[address[11:4]][119:112];
5'h0: q_a <= mem[address[11:4]][127:120];
endcase
valid <= oe;
end
endmodule
| 6.621719
|
module timing_ctrl(input clk, input reset, input ready, output reg [2:0] t, output reg [2:0] t_next,
input [2:0] tnext_mc, input alu_carry_out, input taken_branch, input branch_page_cross,
input intg, output wire pc_hold,
output wire sync, input load_sbz, input onecycle, input twocycle, input decimal_cycle,
output reg write_allowed, output wire decimal_extra_cycle);
// TODO - Separate the state machine from the output encoding?
parameter T0 = 3'b000,
T1 = 3'b001,
T2 = 3'b010,
T3 = 3'b011,
T4 = 3'b100,
T5 = 3'b101,
T6 = 3'b110,
T7 = 3'b111;
`ifdef CMOS
assign decimal_extra_cycle = (t == 7 && load_sbz);
assign sync = (t == 1 && ~(decimal_cycle)) | decimal_extra_cycle;
// Disable PC increment when processing a BRK with recognized IRQ/NMI, or when about to perform the extra decimal correction cycle
assign pc_hold = intg | decimal_cycle;
`else
assign decimal_extra_cycle = 0;
assign sync = (t == 1);
assign pc_hold = intg;
`endif
always @(posedge clk)
begin
if(reset) t <= T2;
else if(ready) begin
t <= t_next;
//$display("T: %d t_next: %d",t,t_next);
end
end
always @(*)
begin
t_next = t+1;
write_allowed = 1;
if(onecycle & sync)
t_next = T1;
else if(twocycle & sync)
t_next = T0;
`ifdef CMOS
else if(decimal_cycle) // Note: The 'if' and not 'else if' here is important in the case where a twocycle instruction follows a decimal extra cycle
t_next = T7;
else if(decimal_extra_cycle)
t_next = T2;
`endif
if(tnext_mc == `T0)
t_next = T0;
else if(tnext_mc == `TNC && alu_carry_out == 0)
t_next = T0;
else if(tnext_mc == `TNC && alu_carry_out == 1)
write_allowed = 0;
else if(tnext_mc == `TBR && taken_branch == 0)
t_next = T1;
else if(tnext_mc == `TBE)
begin
if(branch_page_cross == 1)
t_next = T0;
else
t_next = T1;
end
else if(tnext_mc == `TBT && alu_carry_out == 0)
t_next = T1;
// synthesis translate_off
else if(t != 1 && tnext_mc == `TKL)
begin
$display("Microcode KIL encountered");
$finish;
end
// synthesis translate_on
end
endmodule
| 7.483161
|
module predecode(input [7:0] ir_next, input active, output reg onecycle, output reg twocycle);
// This detects single-cycle instructions
always @(ir_next)
begin
`ifdef CMOS
if((ir_next & 8'b00000111) == 8'b00000011)
onecycle = active;
else
`endif
onecycle = 0;
end
// This detects the instruction patterns where we need to go immediately to T0 instead of T2 during a fetch cycle.
always @(*)
begin
casez(ir_next)
`ifdef CMOS
8'b?1?1_1010: twocycle = 0;
8'b???0_0010: twocycle = active;
`endif
8'b???0_10?1: twocycle = active;
8'b1??0_00?0: // This would hit the CMOS BRA, but is disabled below
begin
twocycle = active;
`ifdef CMOS
casez(ir_next)
8'b?00???0?: twocycle = 0;
endcase
`endif
end
8'b????_10?0:
begin
twocycle = active;
casez(ir_next)
8'b0??0??0?: twocycle = 0;
endcase
end
default: twocycle = 0;
endcase;
end
endmodule
| 6.735207
|
module branch_control (
input [7:0] reg_p,
input [7:5] ir,
output reg taken_branch
);
always @(*) begin
taken_branch = 0;
case ({
ir[7], ir[6]
}) // synthesis full_case parallel_case
2'b00: taken_branch = (reg_p[`PF_N] == ir[5]);
2'b01: taken_branch = (reg_p[`PF_V] == ir[5]);
2'b10: taken_branch = (reg_p[`PF_C] == ir[5]);
2'b11: taken_branch = (reg_p[`PF_Z] == ir[5]);
endcase
end
endmodule
| 6.648487
|
module via6522 (
input cs, // Chip select. The real VIA has CS1 and nCS2. You can get the same functionality by defining this cs to be (cs1 & !cs2)
input phi2, // Phase 2 Internal Clock
input nReset, // Reset (active low)
input [3:0] rs, // Register select
input rWb, // read (high) write (low)
input [7:0] dataIn,
output reg [7:0] dataOut,
input [7:0] paIn, // Peripheral data port A input
output reg [7:0] paOut, // Peripheral data port A
output reg [7:0] paMask, // Peripheral data port A mask: 0 - input, 1 - output
input [7:0] pbIn, // Peripheral data port B
output reg [7:0] pbOut, // Peripheral data port B
output reg [7:0] pbMask,
output reg nIrq
); // Interrupt request
initial begin
reset();
end
always @(posedge phi2, negedge nReset) begin
if (~nReset) begin
reset();
end else begin
if (cs) begin
// This is a clock edge and we're chip selected
if (~rWb) begin
// Rising edge of clock on write operation
case (rs)
4'd0: begin
writePb();
end
4'd1: begin
writePa();
end
4'd2: begin
writePbDir();
end
4'd3: begin
writePaDir();
end
default: begin
// All other registers are not yet implemented
dataOut <= 0;
end
endcase
end else begin
// Falling edge of clock on read operation
// Well, fudge. It seems FPGAs can't trigger on both positive and negative edges of same signal. The 6522 datasheet requires that
// we make the results available on the falling edge of the clock. The reason it requires this, however, is to give the CPU time
// to put the data bus in high impedance mode. Since we're using separate in and out lines, we'll load the the data on the rising
// edge and no one should be the wiser of it.
case (rs)
4'd0: begin
readPb();
end
4'd1: begin
readPa();
end
4'd2: begin
readPbDir();
end
4'd3: begin
readPaDir();
end
default: begin
// All other registers are not yet implemented
end
endcase
end
end
end
end
task readPb();
begin
// Read. Give true input where applicable, and *desired* output elsewhere. See section 2.1 of the datasheet
dataOut <= (pbIn & ~pbMask) | (pbOut & pbMask);
end
endtask
task writePb();
pbOut <= dataIn;
endtask
task readPa();
dataOut <= paIn;
endtask
task writePa();
paOut <= dataIn;
endtask
task readPbDir();
dataOut <= pbMask;
endtask
task writePbDir();
pbMask <= dataIn;
endtask
task readPaDir();
dataOut <= paMask;
endtask
task writePaDir();
paMask <= dataIn;
endtask
task reset();
begin
dataOut <= 0; // High impedance on start
nIrq <= 1; // Don't request interrupt
paOut <= 0;
paMask <= 0;
pbOut <= 0;
pbMask <= 0;
end
endtask
endmodule
| 8.377154
|
module uart51_rx (
RESET_N,
BAUD_CLK,
RX_DATA,
RX_BUFFER,
RX_WORD,
RX_PAR_DIS,
RX_PARITY,
PARITY_ERR,
FRAME,
READY
);
input RESET_N;
input BAUD_CLK;
input RX_DATA;
output [7:0] RX_BUFFER;
reg [7:0] RX_BUFFER;
input [1:0] RX_WORD;
input RX_PAR_DIS;
input [1:0] RX_PARITY;
output PARITY_ERR;
reg PARITY_ERR;
output FRAME;
reg FRAME;
output READY;
reg READY;
reg [5:0] STATE;
reg [2:0] BIT;
reg RX_DATA0;
reg RX_DATA1;
always @(posedge BAUD_CLK or negedge RESET_N) begin
if (!RESET_N) begin
RX_BUFFER <= 8'h00;
STATE <= 6'b000000;
FRAME <= 1'b0;
BIT <= 3'b000;
RX_DATA0 <= 1'b1;
RX_DATA1 <= 1'b1;
READY <= 1'b0;
end else begin
RX_DATA0 <= RX_DATA;
RX_DATA1 <= RX_DATA0;
case (STATE)
6'b000000: // States 0-15 will be start bit
begin
BIT <= 3'b000;
if (~RX_DATA1) STATE <= 6'b000001;
end
6'b001111: // End of start bit, flag data not ready
begin // If data is not retrieved before this, then overrun
READY <= 1'b0;
STATE <= 6'b010000;
end
6'b010111: // Each data bit is states 16-31, the middle is 23
begin
RX_BUFFER[BIT] <= RX_DATA1;
STATE <= 6'b011000;
end
6'b011111: // End of the data bits
begin
if (BIT == 3'b111) begin
STATE <= 6'b100000;
end else begin
if ((RX_WORD == 2'b01) && (BIT == 3'b110)) begin
STATE <= 6'b100000;
end else begin
if ((RX_WORD == 2'b10) && (BIT == 3'b101)) begin
STATE <= 6'b100000;
end else begin
if ((RX_WORD == 2'b11) && (BIT == 3'b100)) begin
STATE <= 6'b100000;
end else begin
BIT <= BIT + 1'b1;
STATE <= 6'b010000;
end
end
end
end
end
6'b100000: // First tick of Stop or Parity, Parity is 32 - 47
begin
if (RX_PAR_DIS) STATE <= 6'b110001; // get stop
else STATE <= 6'b100001; // get parity
end
6'b100111: // Middle of Parity is 39
begin
PARITY_ERR <= ~RX_PARITY[1] & // Get but do not check Parity if 1 is set
(((RX_BUFFER[0] ^ RX_BUFFER[1])
^ (RX_BUFFER[2] ^ RX_BUFFER[3]))
^((RX_BUFFER[4] ^ RX_BUFFER[5])
^ (RX_BUFFER[6] ^ RX_BUFFER[7])) // clear bit #8 if only 7 bits
^ (~RX_PARITY[0] ^ RX_DATA1));
STATE <= 6'b101000;
// 1 bit early for timing reasons
end
6'b110111: // first stop bit is 32 or 48 then 49 - 63
begin
FRAME <= !RX_DATA1; // if data != 1 then not stop bit
READY <= 1'b1;
STATE <= 6'b111000;
end
// In case of a framing error, wait until data is 1 then start over
// We skipped this check for 6 clock cycles so CPU speed is not a factor
// in the RX_READY state machine above
6'b111000: begin
if (RX_DATA1) STATE <= 6'b000000;
end
default: STATE <= STATE + 1'b1;
endcase
end
end
endmodule
| 7.865783
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((-(IP + length)) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ('0 + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ('1 + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (-(btaken ? distance : 0)));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + '0);
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + '1);
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) - (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) * (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) / (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) % (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module top_module (
input a,
b,
output cout,
sum
);
assign sum = a ^ b;
assign cout = a & b;
endmodule
| 7.203305
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= (~((IP + length) + (btaken ? distance : 0)));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= '0;
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= '1;
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module top_module (
input a,
b,
cin,
output cout,
sum
);
assign sum = a ^ b ^ cin;
assign cout = (a & b) | (a & cin) | (b & cin);
endmodule
| 7.203305
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!(!halt))) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if (0) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if (1) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module top_module (
input [2:0] a,
b,
input cin,
output [2:0] cout,
output [2:0] sum
);
integer i;
assign sum[0] = a[0] ^ b[0] ^ cin;
assign cout[0] = (a[0] & b[0]) | (a[0] & cin) | (b[0] & cin);
always @(*) begin
for (i = 1; i < 3; i++) begin
sum[i] = a[i] ^ b[i] ^ cout[i-1];
cout[i] = (a[i] & b[i]) | (a[i] & cout[i-1]) | (b[i] & cout[i-1]);
end
end
endmodule
| 7.203305
|
module UART_RX (
RESET_N,
BAUD_CLK,
RX_DATA,
RX_BUFFER,
//RX_READY,
RX_WORD,
RX_PAR_DIS,
RX_PARITY,
PARITY_ERR,
//OVERRUN,
FRAME,
READY
);
input RESET_N;
input BAUD_CLK;
input RX_DATA;
output [7:0] RX_BUFFER;
reg [7:0] RX_BUFFER;
input RX_WORD;
input RX_PAR_DIS;
input RX_PARITY;
output PARITY_ERR;
reg PARITY_ERR;
output FRAME;
reg FRAME;
output READY;
reg READY;
reg [5:0] STATE;
reg [2:0] BIT;
reg RX_DATA0;
reg RX_DATA1;
always @(posedge BAUD_CLK or negedge RESET_N) begin
if (!RESET_N) begin
RX_BUFFER <= 8'h00;
STATE <= 6'b000000;
FRAME <= 1'b0;
BIT <= 3'b000;
RX_DATA0 <= 1'b1;
RX_DATA1 <= 1'b1;
READY <= 1'b0;
end else begin
RX_DATA0 <= RX_DATA;
RX_DATA1 <= RX_DATA0;
case (STATE)
6'b000000: begin
BIT <= 3'b000;
if (~RX_DATA1) STATE <= 6'b000001;
end
6'b001111: // End of start bit, flag data not ready
begin // If data is not retrieved before this, then overrun
READY <= 1'b0;
STATE <= 6'b010000;
end
6'b010111: // Middle of data bits
begin
RX_BUFFER[BIT] <= RX_DATA1;
STATE <= 6'b011000;
end
6'b011111: // End of data bit
begin
if (BIT == 3'b111) STATE <= 6'b100000;
else begin
if ((BIT == 3'b110) && !RX_WORD) STATE <= 6'b100000;
else begin
BIT <= BIT + 1'b1;
STATE <= 6'b010000;
end
end
end
6'b100000: // Start of parity bit, if enabled
begin
if (RX_PAR_DIS) STATE <= 6'b110001; // get stop
else STATE <= 6'b100001; // get parity
end
6'b100111: //39 middle of parity bit
begin
PARITY_ERR <=((((RX_BUFFER[0] ^ RX_BUFFER[1])
^ (RX_BUFFER[2] ^ RX_BUFFER[3]))
^ ((RX_BUFFER[4] ^ RX_BUFFER[5])
^ (RX_BUFFER[6] ^ (RX_BUFFER[7] & RX_WORD)))) // clear bit #8 if only 7 bits
^ (RX_PARITY ^ RX_DATA1));
STATE <= 6'b101000;
end
6'b110111: //55 middle of stop bit
begin
READY <= 1'b1; // This is the last info we need, so signal ready
FRAME <= !RX_DATA1; // if data != 1 then not stop bit
STATE <= 6'b111000;
end
// In case of a framing error, wait until data is 1 then start over
6'b111000: begin
if (RX_DATA1) // wait until data = 1
STATE <= 6'b000000;
end
default: STATE <= STATE + 1'b1;
endcase
end
end
endmodule
| 7.513316
|
module UART_TX (
BAUD_CLK,
RESET_N,
TX_DATA,
TX_START,
TX_DONE,
TX_STOP,
TX_WORD,
TX_PAR_DIS,
TX_PARITY,
TX_BUFFER
);
input BAUD_CLK;
input RESET_N;
output TX_DATA;
reg TX_DATA;
input TX_START;
output TX_DONE;
reg TX_DONE;
input TX_STOP;
input TX_WORD;
input TX_PAR_DIS;
input TX_PARITY;
input [7:0] TX_BUFFER;
reg [6:0] STATE;
reg [2:0] BIT;
wire PARITY;
reg TX_START0;
reg TX_START1;
assign PARITY = ((TX_BUFFER[0] ^ TX_BUFFER[1])
^ (TX_BUFFER[2] ^ TX_BUFFER[3]))
^ ((TX_BUFFER[4] ^ TX_BUFFER[5])
^ (TX_BUFFER[6] ^ (TX_BUFFER[7] & TX_WORD))) // clear bit #8 if only 7 bits
^ TX_PARITY;
always @(negedge BAUD_CLK or negedge RESET_N) begin
if (!RESET_N) begin
STATE <= 7'b0000000;
TX_DATA <= 1'b1;
TX_DONE <= 1'b1;
BIT <= 3'b000;
TX_START0 <= 1'b0;
TX_START1 <= 1'b0;
end else begin
TX_START0 <= TX_START;
TX_START1 <= TX_START0;
case (STATE)
7'b0000000: begin
BIT <= 3'b000;
TX_DATA <= 1'b1;
if (TX_START1) begin
TX_DONE <= 1'b0;
STATE <= 7'b0000001;
end
end
7'b0000001: begin
TX_DATA <= 1'b0;
STATE <= 7'b0000010;
end
7'b0010001: begin
TX_DATA <= TX_BUFFER[BIT];
STATE <= 7'b0010010;
end
7'b0100000: begin
BIT <= BIT + 1'b1;
if (BIT != {2'b11, TX_WORD}) STATE <= 7'b0010001;
else if (!TX_PAR_DIS) STATE <= 7'b0100001; // do parity
else STATE <= 7'b0110001; // do stop
end
// Start parity bit
7'b0100001: begin
TX_DATA <= PARITY;
STATE <= 7'b0100010;
end
// start stop
7'b0110001: begin
TX_DONE <= 1'b1;
TX_DATA <= 1'b1;
STATE <= 7'b0110010;
end
// end of first stop bit
7'b0111111: begin
if (!TX_STOP) STATE <= 7'b1001111;
else STATE <= 7'b1000000;
end
7'b1001111: begin
STATE <= 7'b0000000;
end
default: STATE <= STATE + 1'b1;
endcase
end
end
endmodule
| 7.089095
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if ((!ue[1])) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (0) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (1) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module top_module (
input [3:0] x,
input [3:0] y,
output [4:0] sum
);
integer i;
wire [3:0] cout;
assign sum[0] = x[0] ^ y[0];
assign cout[0] = x[0] & y[0];
always @(*) begin
for (i = 1; i < 4; i++) begin
sum[i] = x[i] ^ y[i] ^ cout[i-1];
cout[i] = (x[i] & y[i]) | (x[i] & cout[i-1]) | (y[i] & cout[i-1]);
end
sum[4] = cout[3];
end
endmodule
| 7.203305
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if ((!rst)) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (0) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (1) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) begin
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module syncnt (
clk,
rst,
b
);
input clk, rst;
output [3:0] b;
reg [3:0] b = 4'b0;
wire clk, rst;
always @(posedge clk)
if (rst) b <= 4'b0;
else b <= b + 1;
endmodule
| 6.783074
|
module test;
wire [3:0] b;
reg clk = 0;
reg rst = 0;
integer i;
syncnt s1 (
clk,
rst,
b
);
initial begin
$dumpfile("6a_4bitbinarysynccounter.vcd");
$dumpvars(0, test);
for (i = 0; i < 40; i++) begin
#5 begin
clk = !clk;
if (b == 4'hf) rst = 1;
else rst = 0;
end
end
#5 $finish;
end
always @(clk) $strobe("At time = (%0t),clk = (%b),b = (%b)", $time, clk, b);
endmodule
| 6.964054
|
module bit6_is_less_than (
input [5:0] a,
b,
output reg [5:0] result
);
wire result0;
wire result1;
wire result2;
// calling the 2 bit less than operation 3 times for the 3 pairs of bits (because total=6 bits)
bit2_less_than op0 (
a[1:0],
b[1:0],
result0
); //LSB pair
bit2_less_than op1 (
a[3:2],
b[3:2],
result1
);
bit2_less_than op2 (
a[5:4],
b[5:4],
result2
); //MSB pair
//start checking from the result of MSB side of the 6bit for less than comparison
always @*
if (result2) result = 6'b00_0001;
else if (result1) result = 6'b00_0001;
else if (result0) result = 6'b00_0001;
else result = 6'b00_0000;
endmodule
| 6.87276
|
module ripple_adder (
// x and y are the 6-bit two's complement numbers to be added
// sel allows to select between add/subtract
input wire [5:0] x,
input wire [5:0] y,
input wire sel,
// overflow is used to flag overflow in sum output
// c_out is the MSB carry out from the sum
// sum is the sum of a and b
output wire overflow,
output wire [5:0] sum,
output wire cout
);
//internal c_out wire
wire [6:0] c_out;
assign cout = c_out[6]; // the output cout is c_out[6]
// Overflow in two's complement addition is defined as
// XOR of carry_in and carry_out of MSB adder
assign overflow = c_out[6] ^ c_out[5];
// initialise LSB of c_out to 0 (since there is no carry_in on first adder)
assign c_out[0] = 1'b0;
// Instantiate six seperate FullAdder modules
FullAdder adder_1 (
.a(x[0]),
.b(y[0] ^ sel), // this will negate bits if performing subtraction
.cin(sel), // first cin is sel because is sel=1, must get two's complement, this adds 1
.s(sum[0]),
.cout(c_out[1])
);
FullAdder adder_2 (
.a(x[1]),
.b(y[1] ^ sel), // this will negate bits if performing subtraction
.cin(c_out[1]),
.s(sum[1]),
.cout(c_out[2])
);
FullAdder adder_3 (
.a(x[2]),
.b(y[2] ^ sel), // this will negate bits if performing subtractionv
.cin(c_out[2]),
.s(sum[2]),
.cout(c_out[3])
);
FullAdder adder_4 (
.a(x[3]),
.b(y[3] ^ sel), // this will negate bits if performing subtraction
.cin(c_out[3]),
.s(sum[3]),
.cout(c_out[4])
);
FullAdder adder_5 (
.a(x[4]),
.b(y[4] ^ sel), // this will negate bits if performing subtraction
.cin(c_out[4]),
.s(sum[4]),
.cout(c_out[5])
);
FullAdder adder_6 (
.a(x[5]),
.b(y[5] ^ sel), // this will negate bits if performing subtraction
.cin(c_out[5]),
.s(sum[5]),
.cout(c_out[6])
);
endmodule
| 9.165067
|
module S6MUX (
flush,
stall,
x,
y
);
input flush, stall;
input [5:0] x;
output [5:0] y;
assign y = ((flush || stall) == 1) ? 0 : x;
endmodule
| 7.453245
|
module bit6_xnor_gate (
input wire [5:0] a,
b, // a and b are the two 6-bit numbers to XNOR
output wire [5:0] result
);
//xnor-ing each corresponding bit of the 6 bit numbers A and B to get the result
xnor_gate op0 (
a[0],
b[0],
result[0]
);
xnor_gate op1 (
a[1],
b[1],
result[1]
);
xnor_gate op2 (
a[2],
b[2],
result[2]
);
xnor_gate op3 (
a[3],
b[3],
result[3]
);
xnor_gate op4 (
a[4],
b[4],
result[4]
);
xnor_gate op5 (
a[5],
b[5],
result[5]
);
endmodule
| 7.05156
|
module syncnt (
clk,
rst,
b
);
input clk, rst;
output [3:0] b;
reg [3:0] b = 4'b0;
wire clk, rst;
always @(posedge clk)
if (rst) b <= 4'b0;
else b <= b + 1;
endmodule
| 6.783074
|
module test;
wire [3:0] b;
reg clk = 0;
reg rst = 0;
integer i;
syncnt s1 (
clk,
rst,
b
);
initial begin
$dumpfile("6c_BCDsynccounter.vcd");
$dumpvars(0, test);
for (i = 0; i < 40; i++) begin
#5 begin
clk = !clk;
if (b == 4'h9) rst = 1;
else rst = 0;
end
end
#5 $finish;
end
always @(clk) $strobe("At time = (%0t),clk = (%b),b = (%b)", $time, clk, b);
endmodule
| 6.964054
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= (~{ue[4], ue[3], ue[2], ue[1], ue[0]});
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= '0;
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= '1;
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module top_module (
input p1a,
p1b,
p1c,
p1d,
output p1y,
input p2a,
p2b,
p2c,
p2d,
output p2y
);
assign p1y = ~(p1a && p1b && p1c && p1d);
assign p2y = ~(p2a && p2b && p2c && p2d);
endmodule
| 7.203305
|
module top_module (
input [31:0] a,
input [31:0] b,
output [31:0] sum
); //
wire con1, con2;
add16 adder_1 (
a[15:0],
b[15:0],
0,
sum[15:0],
con1
);
add16 adder_2 (
a[31:16],
b[31:16],
con1,
sum[31:16],
con2
);
endmodule
| 7.203305
|
module add1 (
input a,
input b,
input cin,
output sum,
output cout
);
assign sum = a ^ b ^ cin;
assign cout = (a & b) | (a & cin) | (b & cin);
endmodule
| 6.640243
|
module top_module (
input d,
input ena,
output q
);
//Latches are level-sensitive (not edge-sensitive) circuits, so in an always block, they use level-sensitive sensitivity lists.
//However, they are still sequential elements, so should use non-blocking assignments.
//A D-latch acts like a wire (or non-inverting buffer) when enabled, and preserves the current value when disabled.
always @(*) begin
if (ena) q <= d;
end
endmodule
| 7.203305
|
module top_module (
input [399:0] a,
b,
input cin,
output cout,
output [399:0] sum
);
wire [99:0] cout_wires;
genvar i;
generate
bcd_fadd(
a[3:0], b[3:0], cin, cout_wires[0], sum[3:0]
);
for (i = 4; i < 400; i = i + 4) begin : bcd_adder_instances
bcd_fadd bcd_adder (
a[i+3:i],
b[i+3:i],
cout_wires[i/4-1],
cout_wires[i/4],
sum[i+3:i]
);
end
endgenerate
assign cout = cout_wires[99];
endmodule
| 7.203305
|
module top_module (
input [4:1] x,
output f
);
assign f = (~x[1] & x[3]) | (~x[2] & ~x[4]) | (x[2] & x[3] & x[4]);
endmodule
| 7.203305
|
module top_module (
input [7:0] in,
output reg [2:0] pos
);
// casez treats bits that have the value z as don't-care in the comparison.
//Notice how there are certain inputs (e.g., 4'b1111) that will match more than one case item.
//The first match is chosen (so 4'b1111 matches the first item, out = 0, but not any of the later ones).
//There is also a similar casex that treats both x and z as don't-care. I don't see much purpose to using it over casez.
//The digit ? is a synonym for z. so 2'bz0 is the same as 2'b?0
always @(*) begin
casez (in[7:0])
8'bzzzzzzz1: pos = 0;
8'bzzzzzz1z: pos = 1;
8'bzzzzz1zz: pos = 2;
8'bzzzz1zzz: pos = 3;
8'bzzz1zzzz: pos = 4;
8'bzz1zzzzz: pos = 5;
8'bz1zzzzzz: pos = 6;
8'b1zzzzzzz: pos = 7;
default: pos = 0;
endcase
end
endmodule
| 7.203305
|
module top_module (
input [7:0] a,
input [7:0] b,
output [7:0] s,
output overflow
); //
//2's complement for a binary number is found by inverting the numbers and adding 1
// i.e: 2'scomplement of 0011 is : 1100+0001 = 1101
//
//Also remember that MSB of the 2's complement number represents the sign. i.e if MSB is one then the number is -ve
// i.e: 1101 = -8+4+0+1=-3
//
//If 2= 0010 then -2= 1101+1 = 1110
//Also 2+(-2) = 1111 (This property holds for all the numbers)
//
//While adding two 2's complement numbers, overflow can be detected two ways:
// 1. If carryout and crry-on to MSB are different then overflow occured
// 2. If both numbers are +ve and result is-ve or vise versa, overflow occurs
assign s = a + b;
assign overflow = a[7] && b[7] && (~s[7]) || (~a[7]) && (~b[7]) && (s[7]);
endmodule
| 7.203305
|
module top_module (
input [7:0] in,
output [7:0] out
);
assign out = {in[0], in[1], in[2], in[3], in[4], in[5], in[6], in[7]};
endmodule
| 7.203305
|
module top_module (
input [15:0] a,
b,
input cin,
output cout,
output [15:0] sum
);
wire [2:0] incout;
bcd_fadd b1 (
a[3:0],
b[3:0],
cin,
incout[0],
sum[3:0]
);
bcd_fadd b2 (
a[7:4],
b[7:4],
incout[0],
incout[1],
sum[7:4]
);
bcd_fadd b3 (
a[11:8],
b[11:8],
incout[1],
incout[2],
sum[11:8]
);
bcd_fadd b4 (
a[15:12],
b[15:12],
incout[2],
cout,
sum[15:12]
);
endmodule
| 7.203305
|
module top_module (
input p1a,
p1b,
p1c,
p1d,
output p1y,
input p2a,
p2b,
p2c,
p2d,
output p2y
);
assign p1y = ~(p1a & p1b & p1c & p1d);
assign p2y = ~(p2a & p2b & p2c & p2d);
endmodule
| 7.203305
|
module top_module (
input clk,
input reset, // Synchronous active-high reset
output [3:1] ena,
output [15:0] q
);
onebcd bcd0 (
clk,
reset,
1'b1,
q[3:0]
);
onebcd bcd1 (
clk,
reset,
ena[1],
q[7:4]
);
onebcd bcd2 (
clk,
reset,
ena[2],
q[11:8]
);
onebcd bcd3 (
clk,
reset,
ena[3],
q[15:12]
);
assign ena[1] = (q[3:0] == 4'b1001);
assign ena[2] = (q[7:4] == 4'b1001) && (q[3:0] == 4'b1001);
assign ena[3] = (q[11:8] == 4'b1001) && (q[7:4] == 4'b1001) && (q[3:0] == 4'b1001);
endmodule
| 7.203305
|
module onebcd (
input clk,
input reset,
input enable,
output [3:0] Q
);
always @(posedge clk) begin
if (reset || (Q == 4'd9 && enable)) Q <= 0;
else Q <= enable ? Q + 1 : Q;
end
endmodule
| 7.231844
|
module top_module (
input d,
input ena,
output q
);
always @(*) begin
q <= ena ? d : q;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input in,
input areset,
output out
); //
// State transition logic
parameter A = 0, B = 1, C = 2, D = 3;
reg [3:0] state, next_state;
assign next_state[A] = state[A] & (~in) | state[C] & (~in);
assign next_state[B] = state[A] & (in) | state[B] & (in) | state[D] & (in);
assign next_state[C] = state[B] & (~in) | state[D] & (~in);
assign next_state[D] = state[C] & (in);
// State flip-flops with asynchronous reset
always @(posedge clk, posedge areset) begin
if (areset) state = 4'b0001;
else state <= next_state;
end
// Output logic
assign out = state[D];
endmodule
| 7.203305
|
module top_module (
input clk,
input in,
input areset,
output out
);
// Give state names and assignments. I'm lazy, so I like to use decimal numbers.
// It doesn't really matter what assignment is used, as long as they're unique.
parameter A = 0, B = 1, C = 2, D = 3;
reg [1:0] state; // Make sure state and next are big enough to hold the state encodings.
reg [1:0] next;
// Combinational always block for state transition logic. Given the current state and inputs,
// what should be next state be?
// Combinational always block: Use blocking assignments.
always @(*) begin
case (state)
A: next = in ? B : A;
B: next = in ? B : C;
C: next = in ? D : A;
D: next = in ? B : C;
endcase
end
// Edge-triggered always block (DFFs) for state flip-flops. Asynchronous reset.
always @(posedge clk, posedge areset) begin
if (areset) state <= A;
else state <= next;
end
// Combinational output logic. In this problem, an assign statement is the simplest.
assign out = (state == D);
endmodule
| 7.203305
|
module top_module (
input [4:1] x,
output f
);
assign f = ~x[1] & x[3] | x[2] & x[3] & x[4] | ~x[2] & ~x[3] & ~x[4] | x[1] & ~x[2] & ~x[4];
endmodule
| 7.203305
|
module Seven_SEG (
input clk,
input [3:0] BCD0,
BCD1,
BCD2,
BCD3,
output reg [3:0] DIGIT,
output reg [6:0] DISPLAY
);
wire clk1;
clock_divider #(
.width(13)
) clk_13 (
.clk(clk),
.clk_div(clk1)
);
reg [3:0] value;
reg [1:0] digit, digit_next;
always @(posedge clk1) begin
digit <= digit_next;
case (digit)
2'b00: begin
value = BCD0;
DIGIT = 4'b1110;
end
2'b01: begin
value = BCD1;
DIGIT = 4'b1101;
end
2'b10: begin
value = BCD2;
DIGIT = 4'b1011;
end
2'b11: begin
value = BCD3;
DIGIT = 4'b0111;
end
endcase
end
always @* begin
digit_next = digit + 1;
case (value)
4'd0: DISPLAY = 7'b0000001;
4'd1: DISPLAY = 7'b1001111;
4'd2: DISPLAY = 7'b0010010;
4'd3: DISPLAY = 7'b0000110;
4'd4: DISPLAY = 7'b1001100;
4'd5: DISPLAY = 7'b0100100;
4'd6: DISPLAY = 7'b0100000;
4'd7: DISPLAY = 7'b0001111;
4'd8: DISPLAY = 7'b0000000;
4'd9: DISPLAY = 7'b0000100;
default: DISPLAY = 7'b1111111;
endcase
end
endmodule
| 7.108068
|
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