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stringlengths 35
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| score
float64 6.5
11.5
|
|---|---|
module top_module (
input [31:0] in,
output [31:0] out
); //
assign out[7:0] = in[31:24];
assign out[15:8] = in[23:16];
assign out[23:16] = in[15:8];
assign out[31:24] = in[7:0];
endmodule
| 7.203305
|
module rxtx #(
parameter baud = 9600,
mhz = 25
) (
clk,
rst,
rx,
tx_vld,
tx_data,
rx_vld,
rx_data,
tx,
txrdy
);
input clk;
input rst;
input rx;
input tx_vld;
input [7:0] tx_data;
output rx_vld;
output [7:0] rx_data;
output tx;
output txrdy;
/***********************************/
reg rx_dly;
reg [13:0] rx_cnt;
reg data_vld;
reg [ 3:0] data_cnt;
reg rx_vld;
reg [ 7:0] rx_data;
reg [ 7:0] tx_rdy_data;
reg tran_vld;
reg [ 3:0] tran_cnt;
reg tx;
wire txrdy;
/***********************************/
wire rx_change;
wire rx_en;
/***********************************/
localparam period = (mhz * 1000000) / baud, half = period / 2;
reg rx1, rx2, rx3, rxx;
always @(posedge clk) begin
rx1 <= #`DEL rx;
rx2 <= #`DEL rx1;
rx3 <= #`DEL rx2;
rxx <= #`DEL rx3;
end
always @(posedge clk) rx_dly <= #`DEL rxx;
assign rx_change = (rxx != rx_dly);
always @(posedge clk or posedge rst)
if (rst) rx_cnt <= #`DEL 0;
else if (rx_change | (rx_cnt == period)) rx_cnt <= #`DEL 0;
else rx_cnt <= #`DEL rx_cnt + 1'b1;
assign rx_en = (rx_cnt == half);
always @(posedge clk or posedge rst)
if (rst) data_vld <= #`DEL 1'b0;
else if (rx_en & ~rxx & ~data_vld) data_vld <= #`DEL 1'b1;
else if (data_vld & (data_cnt == 4'h9) & rx_en) data_vld <= #`DEL 1'b0;
else;
always @(posedge clk or posedge rst)
if (rst) data_cnt <= #`DEL 4'b0;
else if (data_vld)
if (rx_en) data_cnt <= #`DEL data_cnt + 1'b1;
else;
else data_cnt <= #`DEL 4'b0;
always @(posedge clk or posedge rst)
if (rst) rx_data <= #`DEL 7'b0;
else if (data_vld & rx_en & ~data_cnt[3]) rx_data <= #`DEL{rxx, rx_data[7:1]};
else;
always @(posedge clk or posedge rst)
if (rst) rx_vld <= #`DEL 1'b0;
else rx_vld <= #`DEL data_vld & rx_en & (data_cnt == 4'h9);
always @(posedge clk or posedge rst)
if (rst) tx_rdy_data <= #`DEL 8'b0;
else if (tx_vld & txrdy) tx_rdy_data <= #`DEL tx_data;
else;
always @(posedge clk or posedge rst)
if (rst) tran_vld <= #`DEL 1'b0;
else if (tx_vld) tran_vld <= #`DEL 1'b1;
else if (tran_vld & rx_en & (tran_cnt == 4'd10)) tran_vld <= #`DEL 1'b0;
else;
always @(posedge clk or posedge rst)
if (rst) tran_cnt <= #`DEL 4'b0;
else if (tran_vld)
if (rx_en) tran_cnt <= #`DEL tran_cnt + 1'b1;
else;
else tran_cnt <= #`DEL 4'b0;
always @(posedge clk or posedge rst)
if (rst) tx <= #`DEL 1'b1;
else if (tran_vld)
if (rx_en)
case (tran_cnt)
4'd0: tx <= #`DEL 1'b0;
4'd1: tx <= #`DEL tx_rdy_data[0];
4'd2: tx <= #`DEL tx_rdy_data[1];
4'd3: tx <= #`DEL tx_rdy_data[2];
4'd4: tx <= #`DEL tx_rdy_data[3];
4'd5: tx <= #`DEL tx_rdy_data[4];
4'd6: tx <= #`DEL tx_rdy_data[5];
4'd7: tx <= #`DEL tx_rdy_data[6];
4'd8: tx <= #`DEL tx_rdy_data[7];
4'd9: tx <= #`DEL ^tx_rdy_data;
4'd10: tx <= #`DEL 1'b1;
default: tx <= #`DEL 1'b1;
endcase
else;
else tx <= #`DEL 1'b1;
assign txrdy = ~tran_vld;
endmodule
| 7.896606
|
module mod3_31_a (
F,
A,
B,
C,
D
);
output F;
input A, B, C, D;
wire and1_wire, and2_wire, or2_wire, and3_wire;
and G1 (and1_wire, C, D);
or G2 (or2_wire, and1_wire, B);
and G3 (and2_wire, B, ~C);
and G4 (and3_wire, or2_wire, A);
or G5 (F, and3_wire, and2_wire);
endmodule
| 6.770745
|
module mod3_31_c (
F,
A,
B,
C,
D
);
output F;
input A, B, C, D;
wire and1_wire, and2_wire, or1_wire, or2_wire;
and G1 (and1_wire, A, ~B);
and G2 (and2_wire, ~A, B);
or G3 (or1_wire, C, ~D);
or G4 (or2_wire, and1_wire, and2_wire);
and G5 (F, or1_wire, or2_wire);
endmodule
| 6.863443
|
module mod3_32_a (
F,
A,
B,
C,
D
);
output F;
input A, B, C, D;
assign F = (((C && D) || B) && A) || (B && !C);
endmodule
| 7.408765
|
module mod3_32_b (
F,
A,
B,
C,
D
);
output F;
input A, B, C, D;
assign F = (!(!((!(!(C && D)) || B) && A))) || (!(!(B && !C)));
endmodule
| 7.387534
|
module mod3_32_c (
F,
A,
B,
C,
D
);
output F;
input A, B, C, D;
//wire and1_wire, and2_wire, or1_wire, or2_wire;
assign F = ((A && ~B) || (~A && B)) && (C || ~D);
endmodule
| 7.397287
|
module mod3_32_d (
F,
A,
B,
C,
D
);
output F;
input A, B, C, D;
//wire nand1_wire, nand2_wire, or1_wire, or2_wire, nand3_wire;
assign F = !(!((!(!(A && !B)) || !(!(!A && B))) && (C || !D)));
endmodule
| 7.178218
|
module mod3_32_f (
F,
A,
B,
C,
D
);
output F;
input A, B, C, D;
//wire and1_wire, and2_wire, nor1_wire, nor2_wire;
assign F = !(!((A && !B) || (!A && B))) && !(!(C || !D));
endmodule
| 6.952107
|
module xor_gate_tb;
reg x, y;
wire f;
xor_gate_2 gate (
f,
x,
y
);
initial begin
$dumpfile("xorgate.vcd");
$dumpvars(0, gate);
x = 1'b0;
y = 1'b0;
#10 y = 1'b1;
end
initial #50 $finish;
endmodule
| 6.770103
|
module mod3_34 (
Out_1,
Out_2,
Out_3,
A,
B,
C,
D
);
output Out_1, Out_2, Out_3;
input A, B, C, D;
assign Out_1 = (C || B) && (!A || D) && B;
assign Out_2 = ((C && !B) || (A && B && C) || (!C && B)) && (A || !D);
assign Out_3 = (C && ((A && D) || B)) || (C && !A);
endmodule
| 7.076816
|
module Circuit_A (
A,
B,
C,
F
);
input A, B, C;
output F;
wire w, x, y;
xor (w, A, B);
and (x, w, C);
and (y, A, B);
or (F, x, y);
endmodule
| 7.628113
|
module Circuit_B (
F1,
F2,
F3,
A0,
A1,
B0,
B1
);
output F1, F2, F3;
input A0, A1, B0, B1;
nor (F1, F2, F3);
or (F2, w1, w2, w3);
and (F3, w4, w5);
and (w1, w6, B1);
or (w2, w6, w7, B0);
and (w3, w7, B0, B1);
not (w6, A1);
not (w7, A0);
xor (w4, A1, B1);
xnor (w5, A0, B0);
endmodule
| 7.247974
|
module Circuit_C (
y1,
y2,
a,
b
);
output y1, y2;
input a, b;
assign y1 = a & b;
or (y2, a, b);
endmodule
| 7.74047
|
module add_half (
s,
c,
a,
b
);
output s, c;
input a, b;
xor (s, a, b);
and (c, a, b);
endmodule
| 7.260022
|
module Decoder3_8andFullAdder (
Sw1,
Sw2,
Sw3,
Sa,
LED
);
//输入端口
input Sw1;
input Sw2;
input Sw3;
input Sa;
//输出端口
//LED[1] 代表这一位求和 LED[0]代表这一位给上一位进位
output [1:0] LED;
reg [1:0] LEDi;
reg [3:0] Sw;
//3-8译码器
always @(Sw1, Sw2, Sw3, Sa) begin
Sw = {Sw1, Sw2, Sw3};
if (Sa == 1'b1)
case (Sw)
3'b000: LEDi = ~2'b00;
3'b001: LEDi = ~2'b10;
3'b010: LEDi = ~2'b10;
3'b011: LEDi = ~2'b01;
3'b100: LEDi = ~2'b10;
3'b101: LEDi = ~2'b01;
3'b110: LEDi = ~2'b01;
3'b111: LEDi = ~2'b11;
default: LEDi = ~2'b00;
endcase
else LEDi = 2'b00;
end
assign LED = LEDi;
/*
//输出端口
output [7:0] LED;
reg [7:0] LEDi;
reg [3:0] Sw;
//3-8译码器
always@(Sw1,Sw2,Sw3,Sa)begin
Sw = {Sw1,Sw2,Sw3};
if(Sa == 1'b1)
case(Sw)
3'b000: LEDi = ~8'b00000001;
3'b001: LEDi = ~8'b00000010;
3'b010: LEDi = ~8'b00000100;
3'b011: LEDi = ~8'b00001000;
3'b100: LEDi = ~8'b00010000;
3'b101: LEDi = ~8'b00100000;
3'b110: LEDi = ~8'b01000000;
3'b111: LEDi = ~8'b10000000;
default: LEDi = ~8'b00000000;
endcase
else
LEDi = 8'b11111111;
end
assign LED = LEDi;
*/
endmodule
| 7.346865
|
module top_module (
input [2:0] a,
b,
input cin,
output [2:0] cout,
output [2:0] sum
);
fadd a1 (
a[0],
b[0],
cin,
cout[0],
sum[0]
);
fadd a2 (
a[1],
b[1],
cout[0],
cout[1],
sum[1]
);
fadd a3 (
a[2],
b[2],
cout[1],
cout[2],
sum[2]
);
endmodule
| 7.203305
|
module fadd (
input a,
b,
cin,
output cout,
sum
);
assign sum = a ^ b ^ cin;
assign cout = a & b | a & cin | b & cin;
endmodule
| 7.084872
|
module top_module (
input clk,
input load,
input ena,
input [1:0] amount,
input [63:0] data,
output reg [63:0] q
);
reg signbit;
reg [7:0] signbit8;
always @(posedge clk) begin
if (load) q <= data;
else if (ena) begin
if (amount == 2'b00) q <= q << 1;
else if (amount == 2'b01) q <= q << 8;
else if (amount == 2'b10) begin
if (q[63] == 0) q <= q >> 1;
else begin
q <= q >> 1;
q[63] <= 1'b1;
end
end else if (amount == 2'b11) begin
if (q[63] == 0) q <= q >> 8;
else begin
q <= q >> 8;
q[63:56] <= {8{1'b1}};
end
end
end else q <= q;
end
endmodule
| 7.203305
|
module top_module (
input [2:0] in,
output [1:0] out
);
always @(*) begin
case (in)
3'd0: out = 2'd0;
3'd1: out = 2'd1;
3'd2: out = 2'd1;
3'd3: out = 2'd2;
3'd4: out = 2'd1;
3'd5: out = 2'd2;
3'd6: out = 2'd2;
3'd7: out = 2'd3;
endcase
end
endmodule
| 7.203305
|
module top_module (
input [2:0] a,
b,
input cin,
output [2:0] cout,
output [2:0] sum
);
full_adder A (
a[0],
b[0],
cin,
sum[0],
cout[0]
);
full_adder B (
a[1],
b[1],
cout[0],
sum[1],
cout[1]
);
full_adder C (
a[2],
b[2],
cout[1],
sum[2],
cout[2]
);
endmodule
| 7.203305
|
module SevenSegment (
in,
out
);
input [3:0] in;
output reg [6:0] out;
always @(in) begin
case (in)
4'h0: out = 7'b1000000;
4'h1: out = 7'b1111001;
4'h2: out = 7'b0100100;
4'h3: out = 7'b0110000;
4'h4: out = 7'b0011001;
4'h5: out = 7'b0010010;
4'h6: out = 7'b0000010;
4'h7: out = 7'b1111000;
4'h8: out = 7'b0000000;
4'h9: out = 7'b0010000;
4'ha: out = 7'b0001000;
4'hb: out = 7'b0000011;
4'hc: out = 7'b1000110;
4'hd: out = 7'b0100001;
4'he: out = 7'b0000110;
4'hf: out = 7'b0001110;
endcase
end
endmodule
| 7.922915
|
module threeBitsAdder (
a,
b,
out
);
input [2:0] a, b;
wire [3:0] sum;
output [6:0] out;
assign sum = a + b;
SevenSegment display (
sum,
out
);
endmodule
| 8.786153
|
module top_module (
input clk,
input load,
input [255:0] data,
output [255:0] q
);
reg [2:0] sum;
always @(posedge clk) begin
if (load) q <= data;
else begin
for (int i = 0; i < 256; i++) begin // non-blocking assign, change immediately
if (i == 0) //left upper corner
sum = q[1] + q[16] + q[17] + q[240] + q[241] + q[15] + q[31] + q[255];
else if (i == 15) //right upper corner
sum = q[14] + q[16] + q[0] + q[240] + q[254] + q[30] + q[31] + q[255];
else if (i == 240) //left bottom corner
sum = q[0] + q[15] + q[239] + q[241] + q[1] + q[224] + q[225] + q[255];
else if (i == 255) //right bottom corner
sum = q[0] + q[15] + q[14] + q[224] + q[238] + q[240] + q[239] + q[254];
else if (0 < i & i < 15) //upper bound
sum = q[i-1] + q[i+1] + q[i+15] + q[i+16] + q[i+17] + q[i+239] + q[i+240] + q[i+241];
else if (i % 16 == 0) //left bound
sum = q[i-1] + q[i+1] + q[i+15] + q[i+16] + q[i+17] + q[i-16] + q[i-15] + q[i+31];
else if (i % 16 == 15) //right bound
sum = q[i-1] + q[i+1] + q[i+15] + q[i+16] + q[i-17] + q[i-16] + q[i-15] + q[i-31];
else if (240 < i & i < 255) //bottom bound
sum = q[i-1] + q[i+1] + q[i-17] + q[i-16] + q[i-15] + q[i-239] + q[i-240] + q[i-241];
else //non-bound
sum = q[i-1] + q[i+1] + q[i-17] + q[i-16] + q[i-15] + q[i+15] + q[i+16] + q[i+17];
case (sum) //根据邻居数量判断次态
2: q[i] <= q[i];
3: q[i] <= 1;
default: q[i] <= 0;
endcase
end
end
end
endmodule
| 7.203305
|
module top_module (
input clk,
input reset,
output [3:0] q
);
always @(posedge clk) begin
q <= (reset || q == 10) ? 1 : q + 1;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input reset, // Synchronous reset (active high)
input [7:0] d,
output [7:0] q
);
always @(posedge clk) begin
q <= {8{~reset}} & d;
end
endmodule
| 7.203305
|
module ext (
input [15:0] imm,
input [1:0] EOp,
output reg [31:0] ext
);
always @(*) begin
case (EOp)
2'b00: begin // signed extend to 32 digits
if (imm[15] == 1) begin
ext <= {16'hffff, imm};
end else begin
ext <= {16'h0000, imm};
end
end
2'b01: begin
ext <= {16'h0000, imm};
end
2'b10: begin
ext <= {imm, 16'h0000};
end
2'b11: begin
if (imm[15] == 1) begin
ext <= {16'hffff, imm} >> 2;
end else begin
ext <= {16'h0000, imm} >> 2;
end
end
endcase
end
endmodule
| 8.64485
|
module top_module (
input clk,
input areset, // Asynchronous reset to OFF
input j,
input k,
output out
); //
parameter OFF = 0, ON = 1;
reg state, next_state;
always @(*) begin
// State transition logic
case (state)
OFF: next_state = (j == 1) ? ON : OFF;
ON: next_state = (k == 1) ? OFF : ON;
endcase
end
always @(posedge clk, posedge areset) begin
// State flip-flops with asynchronous reset
if (areset) state <= OFF;
else begin
state <= next_state;
end
end
// Output logic
// assign out = (state == ...);
assign out = (state == ON);
endmodule
| 7.203305
|
module top_module (
input a,
input b,
input c,
input d,
output out
);
assign out = a | ~b & c;
endmodule
| 7.203305
|
module top_module (
input [15:0] a,
b,
c,
d,
e,
f,
g,
h,
i,
input [ 3:0] sel,
output [15:0] out
);
always @(*) begin
case (sel)
4'd0: out = a;
4'd1: out = b;
4'd2: out = c;
4'd3: out = d;
4'd4: out = e;
4'd5: out = f;
4'd6: out = g;
4'd7: out = h;
4'd8: out = i;
default: out = 16'hffff;
endcase
end
endmodule
| 7.203305
|
module top_module (
input in1,
input in2,
output out
);
assign out = ~(in1 | in2);
endmodule
| 7.203305
|
module top_module (
input a,
input b,
input c,
output out
);
// SOP form: Three prime implicants (1 term each), summed.
// POS form: One prime implicant (of 3 terms)
// In this particular case, the result is the same for both SOP and POS.
assign out = (a | b | c);
endmodule
| 7.203305
|
module top_module (
input in,
output out
);
assign out = in;
endmodule
| 7.203305
|
module top_module (
input x,
input y,
output z
);
assign z = (x ^ y) & x;
endmodule
| 7.203305
|
module top_module (
input x,
input y,
output z
);
assign z = ~(x ^ y);
endmodule
| 7.203305
|
module top_module (
input x,
input y,
output z
);
wire o1, o2, o3, o4;
A ia1 (
x,
y,
o1
);
B ib1 (
x,
y,
o2
);
A ia2 (
x,
y,
o3
);
B ib2 (
x,
y,
o4
);
assign z = (o1 | o2) ^ (o3 & o4);
// Or you could simplify the circuit including the sub-modules:
// assign z = x|~y;
endmodule
| 7.203305
|
module A (
input x,
input y,
output z
);
assign z = (x ^ y) & x;
endmodule
| 8.429663
|
module B (
input x,
input y,
output z
);
assign z = ~(x ^ y);
endmodule
| 9.609894
|
module top_module (
input ring,
input vibrate_mode,
output ringer,
output motor
);
// When should ringer be on? When (phone is ringing) and (phone is not in vibrate mode)
assign ringer = ring & ~vibrate_mode;
// When should motor be on? When (phone is ringing) and (phone is in vibrate mode)
assign motor = ring & vibrate_mode;
endmodule
| 7.203305
|
module top_module (
input too_cold,
input too_hot,
input mode,
input fan_on,
output heater,
output aircon,
output fan
);
assign fan = fan_on | heater | aircon;
assign heater = mode & too_cold;
assign aircon = ~mode & too_hot;
endmodule
| 7.203305
|
module top_module (
input [2:0] in,
output [1:0] out
);
integer i, count;
always @* begin
count = 0;
for (i = 0; i < 3; i = i + 1) begin
if (in[i] == 1'b1) count = count + 1;
end
out = count;
end
endmodule
| 7.203305
|
module top_module (
input [3:0] in,
output [2:0] out_both,
output [3:1] out_any,
output [3:0] out_different
);
assign out_both = {in[3] & in[2], in[2] & in[1], in[1] & in[0]};
assign out_any = {in[3] | in[2], in[2] | in[1], in[1] | in[0]};
assign out_different = {in[0] ^ in[3], in[3] ^ in[2], in[2] ^ in[1], in[1] ^ in[0]};
/*
// Use bitwise operators and part-select to do the entire calculation in one line of code
// in[3:1] is this vector: in[3] in[2] in[1]
// in[2:0] is this vector: in[2] in[1] in[0]
// Bitwise-OR produces a 3 bit vector. | | |
// Assign this 3-bit result to out_any[3:1]: o_a[3] o_a[2] o_a[1]
// Thus, each output bit is the OR of the input bit and its neighbour to the right:
// e.g., out_any[1] = in[1] | in[0];
// Notice how this works even for long vectors.
assign out_any = in[3:1] | in[2:0];
assign out_both = in[2:0] & in[3:1];
// XOR 'in' with a vector that is 'in' rotated to the right by 1 position: {in[0], in[3:1]}
// The rotation is accomplished by using part selects[] and the concatenation operator{}.
assign out_different = in ^ {in[0], in[3:1]};
*/
endmodule
| 7.203305
|
module top_module (
input [99:0] in,
output [98:0] out_both,
output [99:1] out_any,
output [99:0] out_different
);
assign out_any = in[99:1] | in[98:0];
assign out_both = in[98:0] & in[99:1];
assign out_different = in ^ {in[0], in[99:1]};
endmodule
| 7.203305
|
module top_module (
output out
);
assign out = 1'b0;
endmodule
| 7.203305
|
module top_module (
input in1,
input in2,
output out
);
assign out = ~(in1 | in2);
endmodule
| 7.203305
|
module top_module (
input in1,
input in2,
input in3,
output out
);
assign out = in3 ^ ~(in1 ^ in2);
endmodule
| 7.203305
|
module top_module (
input a,
b,
output out_and,
output out_or,
output out_xor,
output out_nand,
output out_nor,
output out_xnor,
output out_anotb
);
assign out_and = a & b;
assign out_or = a | b;
assign out_xor = a ^ b;
assign out_nand = ~out_and;
assign out_nor = ~out_or;
assign out_xnor = ~out_xor;
assign out_anotb = a & ~b;
endmodule
| 7.203305
|
module top_module (
input p1a,
p1b,
p1c,
p1d,
output p1y,
input p2a,
p2b,
p2c,
p2d,
output p2y
);
assign p1y = ~(p1a && p1b && p1c && p1d);
assign p2y = ~(p2a && p2b && p2c && p2d);
endmodule
| 7.203305
|
module top_module (
input x3,
input x2,
input x1,
output f
);
// This truth table has four minterms.
assign f = (~x3 & x2 & ~x1) | (~x3 & x2 & x1) | (x3 & ~x2 & x1) | (x3 & x2 & x1);
// It can be simplified, by boolean algebra or Karnaugh maps.
// assign f = (~x3 & x2) | (x3 & x1);
// You may then notice that this is actually a 2-to-1 mux, selected by x3:
// assign f = x3 ? x1 : x2;
endmodule
| 7.203305
|
module top_module (
input [1:0] A,
input [1:0] B,
output z
);
// assign z = (A[0] == B[0]) && (A[1] == B[1]);
assign z = (A[1:0] == B[1:0]); // Comparisons produce a 1 or 0 result.
// Another option is to use a 16-entry truth table ( {A,B} is 4 bits, with 16 combinations ).
// There are 4 rows with a 1 result. 0000, 0101, 1010, and 1111.
endmodule
| 7.203305
|
module top_module (
input a,
b,
sel,
output out
);
assign out = (sel == 1) ? b : a;
endmodule
| 7.203305
|
module top_module (
input [99:0] a,
b,
input sel,
output [99:0] out
);
assign out = (sel) ? b : a;
endmodule
| 7.203305
|
module top_module (
input [15:0] a,
b,
c,
d,
e,
f,
g,
h,
i,
input [ 3:0] sel,
output [15:0] out
);
always @(*) begin
case (sel)
4'd0: out = a;
4'd1: out = b;
4'd2: out = c;
4'd3: out = d;
4'd4: out = e;
4'd5: out = f;
4'd6: out = g;
4'd7: out = h;
4'd8: out = i;
default: out = {16{1'b1}};
endcase
end
endmodule
| 7.203305
|
module top_module (
input [15:0] a,
input [15:0] b,
input [15:0] c,
input [15:0] d,
input [15:0] e,
input [15:0] f,
input [15:0] g,
input [15:0] h,
input [15:0] i,
input [3:0] sel,
output logic [15:0] out
);
// Case statements can only be used inside procedural blocks (always block)
// This is a combinational circuit, so use a combinational always @(*) block.
always @(*) begin
out = '1; // '1 is a special literal syntax for a number with all bits set to 1.
// '0, 'x, and 'z are also valid.
// I prefer to assign a default value to 'out' instead of using a
// default case.
case (sel)
4'h0: out = a;
4'h1: out = b;
4'h2: out = c;
4'h3: out = d;
4'h4: out = e;
4'h5: out = f;
4'h6: out = g;
4'h7: out = h;
4'h8: out = i;
endcase
end
endmodule
| 7.203305
|
module top_module (
input [255:0] in,
input [7:0] sel,
output out
);
assign out = in[sel];
endmodule
| 7.203305
|
module top_module (
input [1023:0] in,
input [7:0] sel,
output [3:0] out
);
// We can't part-select multiple bits without an error, but we can select one bit at a time,
// four times, then concatenate them together.
assign out = {in[sel*4+3], in[sel*4+2], in[sel*4+1], in[sel*4+0]};
// Alternatively, "indexed vector part select" works better, but has an unfamiliar syntax:
// assign out = in[sel*4 +: 4]; // Select starting at index "sel*4", then select a total width of 4 bits with increasing (+:) index number.
// assign out = in[sel*4+3 -: 4]; // Select starting at index "sel*4+3", then select a total width of 4 bits with decreasing (-:) index number.
// Note: The width (4 in this case) must be constant.
endmodule
| 7.203305
|
module top_module (
input a,
b,
output cout,
sum
);
assign cout = a & b;
assign sum = a ^ b;
endmodule
| 7.203305
|
module top_module (
input a,
b,
cin,
output cout,
sum
);
assign cout = a & b | b & cin | a & cin;
assign sum = a ^ b ^ cin;
endmodule
| 7.203305
|
module top_module (
input [2:0] a,
b,
input cin,
output [2:0] cout,
output [2:0] sum
);
FA FA1 (
a[0],
b[0],
cin,
cout[0],
sum[0]
);
FA FA2 (
a[1],
b[1],
cout[0],
cout[1],
sum[1]
);
FA FA3 (
a[2],
b[2],
cout[1],
cout[2],
sum[2]
);
endmodule
| 7.203305
|
module FA (
input a,
b,
cin,
output cout,
sum
);
assign cout = a & b | b & cin | a & cin;
assign sum = a ^ b ^ cin;
endmodule
| 8.362615
|
module top_module (
input [3:0] x,
input [3:0] y,
output [4:0] sum
);
// This circuit is a 4-bit ripple-carry adder with carry-out.
assign sum = x + y; // Verilog addition automatically produces the carry-out bit.
// Verilog quirk: Even though the value of (x+y) includes the carry-out, (x+y) is still considered to be a 4-bit number (The max width of the two operands).
// This is correct:
// assign sum = (x+y);
// But this is incorrect:
// assign sum = {x+y}; // Concatenation operator: This discards the carry-out
endmodule
| 7.203305
|
module top_module (
input [7:0] a,
input [7:0] b,
output [7:0] s,
output overflow
); //
wire [8:0] sum;
assign sum = a + b;
assign s = sum[7:0];
assign overflow = a[7] && b[7] && (~s[7]) || (~a[7]) && (~b[7]) && (s[7]);
endmodule
| 7.203305
|
module top_module (
input [99:0] a,
b,
input cin,
output cout,
output [99:0] sum
);
assign {cout, sum} = a + b + cin;
endmodule
| 7.203305
|
module top_module (
input [15:0] a,
b,
input cin,
output cout,
output [15:0] sum
);
wire c1, c2, c3;
bcd_fadd b1 (
a[3:0],
b[3:0],
cin,
c1,
sum[3:0]
);
bcd_fadd b2 (
a[7:4],
b[7:4],
c1,
c2,
sum[7:4]
);
bcd_fadd b3 (
a[11:8],
b[11:8],
c2,
c3,
sum[11:8]
);
bcd_fadd b4 (
a[15:12],
b[15:12],
c3,
cout,
sum[15:12]
);
endmodule
| 7.203305
|
module top_module (
input a,
input b,
input c,
output out
);
assign out = (a | b | c);
endmodule
| 7.203305
|
module top_module (
input a,
input b,
input c,
input d,
output out
);
assign out = ~d & ~a | ~c & ~b | c & d & (a | b);
endmodule
| 7.203305
|
module top_module (
input a,
input b,
input c,
input d,
output out
);
assign out = a | ~b & c;
endmodule
| 7.203305
|
module top_module (
input a,
input b,
input c,
input d,
output out
);
assign out = a ^ b ^ c ^ d;
endmodule
| 7.203305
|
module top_module (
input a,
input b,
input c,
input d,
output out_sop,
output out_pos
);
assign out_sop = (c & d) | (~a & ~b & c);
assign out_pos = c & (~b | ~c | d) & (~a | ~c | d);
endmodule
| 7.203305
|
module top_module (
input [4:1] x,
output f
);
assign f = ~x[1] & x[3] | x[1] & x[2] & x[4];
endmodule
| 7.203305
|
module top_module (
input [4:1] x,
output f
);
assign f = (~x[1] & x[3]) | (~x[2] & ~x[4]) | (x[2] & x[3] & x[4]);
endmodule
| 7.203305
|
module top_module (
input c,
input d,
output [3:0] mux_in
);
assign mux_in = (c & d) ? 4'b1001 : (c) ? 4'b0101 : (d) ? 4'b0001 : 4'b0100;
endmodule
| 7.203305
|
module logic_gates(oY, iA, iB, iC)
output oY;
input iA,iB, iC;
and(and1, iA, iB)
and (and2, iA, iC)
or (oY, and1, and2);
endmodule
| 7.336286
|
module top_module (
input clk,
input d,
output reg q
);
// Use non-blocking assignment for edge-triggered always blocks
always @(posedge clk) q <= d;
// Undefined simulation behaviour can occur if there is more than one edge-triggered
// always block and blocking assignment is used. Which always block is simulated first?
endmodule
| 7.203305
|
module top_module (
input clk,
input in,
output out
);
always @(posedge clk) begin
out <= out ^ in;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input L,
input r_in,
input q_in,
output reg Q
);
always @(posedge clk) begin
case (L)
1'b0: Q <= q_in;
1'b1: Q <= r_in;
endcase
end
endmodule
| 7.203305
|
module top_module (
input clk,
input w,
R,
E,
L,
output Q
);
wire [1:0] con = {E, L};
always @(posedge clk) begin
case (con)
2'b00: Q <= Q;
2'b01: Q <= R;
2'b11: Q <= R;
2'b10: Q <= w;
endcase
end
endmodule
| 7.203305
|
module top_module (
input clk,
input x,
output z
);
reg q, q1, q2;
always @(posedge clk) begin
q <= q ^ x;
q1 <= ~q1 && x;
q2 <= ~q2 || x;
end
assign z = ~(q | q1 | q2);
endmodule
| 7.203305
|
module top_module (
input clk,
input j,
input k,
output Q
);
always @(posedge clk) begin
case ({
j, k
})
2'b00: Q <= Q;
2'b01: Q <= 1'b0;
2'b10: Q <= 1'b1;
2'b11: Q <= ~Q;
endcase
end
endmodule
| 7.203305
|
module top_module (
input clk,
input [7:0] in,
output reg [7:0] pedge
);
reg [7:0] d_last;
always @(posedge clk) begin
d_last <= in; // Remember the state of the previous cycle
pedge <= in & ~d_last; // A positive edge occurred if input was 0 and is now 1.
end
endmodule
| 7.203305
|
module top_module (
input clk,
input [7:0] in,
output [7:0] anyedge
);
reg [7:0] dlast;
always @(posedge clk) begin
dlast <= in;
anyedge <= dlast ^ in;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input reset,
input [31:0] in,
output [31:0] out
);
reg [31:0] d_last;
wire [31:0] state;
assign state = d_last & ~in;
always @(posedge clk) begin
d_last <= in;
if (reset) begin
out <= '0;
end else begin
for (int i = 0; i < 32; i++) begin
if (state[i] == 1'b1) out[i] <= 1'b1;
end
end
end
endmodule
| 7.203305
|
module top_module (
input clk,
input d,
output q
);
reg p, n;
// A positive-edge triggered flip-flop
always @(posedge clk) p <= d ^ n;
// A negative-edge triggered flip-flop
always @(negedge clk) n <= d ^ p;
// Why does this work?
// After posedge clk, p changes to d^n. Thus q = (p^n) = (d^n^n) = d.
// After negedge clk, n changes to p^n. Thus q = (p^n) = (p^p^n) = d.
// At each (positive or negative) clock edge, p and n FFs alternately
// load a value that will cancel out the other and cause the new value of d to remain.
assign q = p ^ n;
// Can't synthesize this.
/*always @(posedge clk, negedge clk) begin
q <= d;
end*/
endmodule
| 7.203305
|
module top_module (
input clk,
input d,
output q
);
reg q1, q2;
assign q = clk ? q1 : q2;
always @(posedge clk) begin
q1 <= d;
end
always @(negedge clk) begin
q2 <= d;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input [7:0] d,
output reg [7:0] q
);
// Because q is a vector, this creates multiple DFFs.
always @(posedge clk) q <= d;
endmodule
| 7.203305
|
module top_module (
input clk,
input reset, // Synchronous reset
input [7:0] d,
output [7:0] q
);
always @(posedge clk) begin
q <= (reset) ? 8'd0 : d;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input reset,
input [7:0] d,
output [7:0] q
);
always @(negedge clk) begin
q <= (reset) ? 8'h34 : d;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input [7:0] d,
input areset,
output reg [7:0] q
);
// The only difference in code compared to synchronous reset is in the sensitivity list.
always @(posedge clk, posedge areset)
if (areset) q <= 0;
else q <= d;
// In Verilog, the sensitivity list looks strange. The FF's reset is sensitive to the
// *level* of areset, so why does using "posedge areset" work?
// To see why it works, consider the truth table for all events that change the input
// signals, assuming clk and areset do not switch at precisely the same time:
// clk areset output
// x 0->1 q <= 0; (because areset = 1)
// x 1->0 no change (always block not triggered)
// 0->1 0 q <= d; (not resetting)
// 0->1 1 q <= 0; (still resetting, q was 0 before too)
// 1->0 x no change (always block not triggered)
endmodule
| 7.203305
|
module top_module (
input clk,
input resetn,
input [1:0] byteena,
input [15:0] d,
output [15:0] q
);
always @(posedge clk) begin
case (byteena)
2'b01: q <= (~resetn) ? 16'd0 : {q[15:8], d[7:0]};
2'b10: q <= (~resetn) ? 16'd0 : {d[15:8], q[7:0]};
2'b11: q <= (~resetn) ? 16'd0 : {d[15:8], d[7:0]};
endcase
end
endmodule
| 7.203305
|
module top_module (
input d,
input ena,
output q
);
always @(*) begin
if (ena) q <= d;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input d,
input ar, // asynchronous reset
output q
);
always @(posedge clk or posedge ar) begin
q <= (ar) ? 0 : d;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input d,
input r, // synchronous reset
output q
);
always @(posedge clk) begin
q <= (r) ? 0 : d;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input reset,
output reg [3:0] q
);
always @(posedge clk)
if (reset) q <= 0;
else q <= q + 1; // Because q is 4 bits, it rolls over from 15 -> 0.
// If you want a counter that counts a range different from 0 to (2^n)-1,
// then you need to add another rule to reset q to 0 when roll-over should occur.
endmodule
| 7.203305
|
module top_module (
input clk,
input reset,
output reg [3:0] q
);
always @(posedge clk)
if (reset || q == 9) // Count to 10 requires rolling over 9->0 instead of the more natural 15->0
q <= 0;
else q <= q + 1;
endmodule
| 7.203305
|
module top_module (
input clk,
input reset,
output [3:0] q
);
always @(posedge clk) begin
if (reset || q == 4'd10) q <= 4'd1;
else q <= q + 1;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input slowena,
input reset,
output [3:0] q
);
always @(posedge clk) begin
if (slowena) begin
if (q == 4'd9) q <= 0;
else q <= q + 1;
end
if (reset) begin
q <= 0;
end
end
endmodule
| 7.203305
|
module top_module (
input clk,
input reset,
input enable,
output [3:0] Q,
output c_enable,
output c_load,
output [3:0] c_d
); //
assign c_enable = enable;
assign c_load = reset | (Q == 4'd12 & enable == 1);
assign c_d = 4'd1;
count4 the_counter (
clk,
c_enable,
c_load,
c_d,
Q
);
endmodule
| 7.203305
|
module top_module (
input clk,
input reset,
output OneHertz,
output [2:0] c_enable
); //
wire [3:0] q0, q1, q2;
assign OneHertz = {q0 == 4'd9 && q1 == 4'd9 && q2 == 4'd9};
assign c_enable = {q1 == 4'd9 && q0 == 4'd9, q0 == 4'd9, 1'b1};
bcdcount counter0 (
clk,
reset,
c_enable[0],
q0
);
bcdcount counter1 (
clk,
reset,
c_enable[1],
q1
);
bcdcount counter2 (
clk,
reset,
c_enable[2],
q2
);
endmodule
| 7.203305
|
module top_module (
input clk,
input reset, // Synchronous active-high reset
output [3:1] ena,
output reg [15:0] q
);
assign ena = {
q[11:8] == 4'd9 && q[7:4] == 4'd9 && q[3:0] == 4'd9,
q[7:4] == 4'd9 && q[3:0] == 4'd9,
q[3:0] == 4'd9
};
BCD bcd0 (
clk,
reset,
1,
q[3:0]
);
BCD bcd1 (
clk,
reset,
ena[1],
q[7:4]
);
BCD bcd2 (
clk,
reset,
ena[2],
q[11:8]
);
BCD bcd3 (
clk,
reset,
ena[3],
q[15:12]
);
endmodule
| 7.203305
|
module top_module (
input clk,
input reset,
input ena,
output pm,
output [7:0] hh,
output [7:0] mm,
output [7:0] ss
);
always @(posedge clk) begin
if (reset) begin
hh <= 8'h12;
mm <= 0;
ss <= 0;
pm <= 0;
end else begin
if (ena) begin
pm <= (hh == 8'h11 && mm == 8'h59 && ss == 8'h59) ? ~pm : pm;
if (ss == 8'h59) begin // ss = 59
ss <= 0;
if (mm == 8'h59) begin // mm = 59
mm <= 0;
if (hh == 8'h12) begin
hh <= 8'h01;
end else begin
if (hh[3:0] == 4'd9) begin
hh[3:0] <= 0;
hh[7:4] <= hh[7:4] + 4'd1;
end else hh[3:0] <= hh[3:0] + 4'd1;
end
end else begin
if (mm[3:0] == 4'd9) begin
mm[3:0] <= 0;
mm[7:4] <= mm[7:4] + 4'd1;
end else mm[3:0] <= mm[3:0] + 4'd1;
end
end else begin
if (ss[3:0] == 4'd9) begin
ss[3:0] <= 0;
ss[7:4] <= ss[7:4] + 4'd1;
end else ss[3:0] <= ss[3:0] + 4'd1;
end
end
end
end
endmodule
| 7.203305
|
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