code
stringlengths 35
6.69k
| score
float64 6.5
11.5
|
|---|---|
module top_module (
input clk,
input areset,
input load,
input ena,
input [3:0] data,
output reg [3:0] q
);
// Asynchronous reset: Notice the sensitivity list.
// The shift register has four modes:
// reset
// load
// enable shift
// idle -- preserve q (i.e., DFFs)
always @(posedge clk, posedge areset) begin
if (areset) // reset
q <= 0;
else if (load) // load
q <= data;
else if (ena) // shift is enabled
q <= q[3:1]; // Use vector part select to express a shift.
end
endmodule
| 7.203305
|
module top_module (
input clk,
input load,
input [1:0] ena,
input [99:0] data,
output reg [99:0] q
);
// This rotator has 4 modes:
// load
// rotate left
// rotate right
// do nothing
// I used vector part-select and concatenation to express a rotation.
// Edge-sensitive always block: Use non-blocking assignments.
always @(posedge clk) begin
if (load) // Load
q <= data;
else if (ena == 2'h1) // Rotate right
q <= {q[0], q[99:1]};
else if (ena == 2'h2) // Rotate left
q <= {q[98:0], q[99]};
end
endmodule
| 7.203305
|
module top_module (
input clk,
input load,
input ena,
input [1:0] amount,
input [63:0] data,
output reg [63:0] q
);
always @(posedge clk) begin
if (load) q <= data;
else if (ena) begin
case (amount)
2'b00: q <= {q[62:0], 1'b0};
2'b01: q <= {q[55:0], 8'b0};
2'b10: q <= {q[63], q[63:1]};
2'b11: q <= {{8{q[63]}}, q[63-:56]};
endcase
end
end
endmodule
| 7.203305
|
module top_module (
input clk,
input reset, // Active-high synchronous reset to 5'h1
output [4:0] q
);
always @(posedge clk) begin
if (reset) q <= 5'h1;
else q <= {q[0], q[4], q[3] ^ q[0], q[2], q[1]};
end
endmodule
| 7.203305
|
module top_module (
input clk,
input reset,
output reg [4:0] q
);
reg [4:0] q_next; // q_next is not a register
// Convenience: Create a combinational block of logic that computes
// what the next value should be. For shorter code, I first shift
// all of the values and then override the two bit positions that have taps.
// A logic synthesizer creates a circuit that behaves as if the code were
// executed sequentially, so later assignments override earlier ones.
// Combinational always block: Use blocking assignments.
always @(*) begin
q_next = q[4:1]; // Shift all the bits. This is incorrect for q_next[4] and q_next[2]
q_next[4] = q[0]; // Give q_next[4] and q_next[2] their correct assignments
q_next[2] = q[3] ^ q[0];
end
// This is just a set of DFFs. I chose to compute the connections between the
// DFFs above in its own combinational always block, but you can combine them if you wish.
// You'll get the same circuit either way.
// Edge-triggered always block: Use non-blocking assignments.
always @(posedge clk) begin
if (reset) q <= 5'h1;
else q <= q_next;
end
endmodule
| 7.203305
|
module top_module (
input [2:0] SW, // R
input [1:0] KEY, // L and clk
output reg [2:0] LEDR
); // Q
wire clk = KEY[0];
wire L = KEY[1];
wire [2:0] d = (L) ? SW : {LEDR[1] ^ LEDR[2], LEDR[0], LEDR[2]};
always @(posedge clk) begin
LEDR <= d;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input reset, // Active-high synchronous reset to 32'h1
output [31:0] q
);
reg [31:0] q_next;
always @(*) begin
q_next = q[31:1]; // Shift all the bits. This is incorrect for q_next[4] and q_next[2]
q_next[31] = q[0]; // Give q_next[4] and q_next[2] their correct assignments
q_next[21] = q[22] ^ q[0];
q_next[1] = q[2] ^ q[0];
q_next[0] = q[1] ^ q[0];
end
always @(posedge clk) begin
if (reset) q <= 32'h1;
else q <= q_next;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input resetn, // synchronous reset
input in,
output out
);
reg [3:0] Q;
assign out = Q[0];
always @(posedge clk) begin
if (~resetn) Q <= 4'd0;
else Q <= {in, Q[3:1]};
end
endmodule
| 7.203305
|
module top_module (
input [3:0] SW,
input [3:0] KEY,
output [3:0] LEDR
); //
wire [3:0] w_input = {KEY[3], LEDR[3], LEDR[2], LEDR[1]};
generate
genvar i;
for (i = 0; i < 4; i = i + 1) begin : muxdff
MUXDFF(
.clk(KEY[0]), .w(w_input[i]), .R(SW[i]), .E(KEY[1]), .L(KEY[2]), .Q(LEDR[i])
);
end
endgenerate
endmodule
| 7.203305
|
module top_module (
input clk,
input enable,
input S,
input A,
B,
C,
output reg Z
);
reg [7:0] q;
// The final circuit is a shift register attached to a 8-to-1 mux.
// Create a 8-to-1 mux that chooses one of the bits of q based on the three-bit number {A,B,C}:
// There are many other ways you could write a 8-to-1 mux
// (e.g., combinational always block -> case statement with 8 cases).
assign Z = q[{A, B, C}];
// Edge-triggered always block: This is a standard shift register (named q) with enable.
// When enabled, shift to the left by 1 (discarding q[7] and and shifting in S).
always @(posedge clk) begin
if (enable) q <= {q[6:0], S};
end
endmodule
| 7.203305
|
module top_module (
input clk,
input load,
input [511:0] data,
output reg [511:0] q
);
always @(posedge clk) begin
if (load) q <= data; // Load the DFFs with a value.
else begin
// At each clock, the DFF storing each bit position becomes the XOR of its left neighbour
// and its right neighbour. Since the operation is the same for every
// bit position, it can be written as a single operation on vectors.
// The shifts are accomplished using part select and concatenation operators.
// left right
// neighbour neighbour
q <= {1'b0, q[511:1]} ^ {q[510:0], 1'b0};
end
end
endmodule
| 7.203305
|
module top_module (
input clk,
input load,
input [511:0] data,
output [511:0] q
);
always @(posedge clk) begin
if (load) q <= data;
else q <= q ^ {q[510:0], 1'b0} | q & ~{1'b0, q[511:1]};
end
endmodule
| 7.203305
|
module top_module (
input clk,
input load,
input [255:0] data,
output [255:0] q
);
reg [255:0] temp;
wire [287:0] map = {temp[15:0], temp, temp[255:240]};
int count;
always @(posedge clk) begin
if (load) begin
q <= data;
end else begin
for (int i = 16; i < 272; i = i + 1) begin
if(i == 16 || i == 32 || i == 48 || i == 64 || i == 80 || i == 96 || i==112 || i==128 || i == 144
|| i == 160 || i == 176 || i == 192 || i == 208 || i == 224 || i == 240 || i == 256) begin
count = map[i+1]+map[i+15]+map[i+16]+map[i+17]+map[i+31]+map[i-1]+map[i-15]+map[i-16];
end
else if (i == 31 || i == 47 || i == 63 || i == 79 || i == 95 || i==111 || i==127 || i == 143
|| i == 159 || i == 175 || i == 191 || i == 207 || i == 223 || i == 239 || i == 255 || i == 271) begin
count = map[i-1]+map[i-15]+map[i-16]+map[i-17]+map[i-31]+map[i+1]+map[i+15]+map[i+16];
end else begin
count = map[i+1]+map[i+15]+map[i+16]+map[i+17]+map[i-1]+map[i-15]+map[i-16]+map[i-17];
end
if (count == 2) q[i-16] <= q[i-16];
else if (count == 3) q[i-16] <= 1'b1;
else q[i-16] <= 1'b0;
end
end
end
always @(negedge clk) begin
temp <= q;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input in,
input areset,
output out
);
// Give state names and assignments. I'm lazy, so I like to use decimal numbers.
// It doesn't really matter what assignment is used, as long as they're unique.
parameter A = 0, B = 1;
reg state; // Ensure state and next are big enough to hold the state encoding.
reg next;
// A finite state machine is usually coded in three parts:
// State transition logic
// State flip-flops
// Output logic
// It is sometimes possible to combine one or more of these blobs of code
// together, but be careful: Some blobs are combinational circuits, while some
// are clocked (DFFs).
// Combinational always block for state transition logic. Given the current state and inputs,
// what should be next state be?
// Combinational always block: Use blocking assignments.
always @(*) begin
case (state)
A: next = in ? A : B;
B: next = in ? B : A;
endcase
end
// Edge-triggered always block (DFFs) for state flip-flops. Asynchronous reset.
always @(posedge clk, posedge areset) begin
if (areset) state <= B; // Reset to state B
else state <= next; // Otherwise, cause the state to transition
end
// Combinational output logic. In this problem, an assign statement is the simplest.
// In more complex circuits, a combinational always block may be more suitable.
assign out = (state == B);
endmodule
| 7.203305
|
module top_module (
input clk,
input areset,
input bump_left,
input bump_right,
output walk_left,
output walk_right
);
// Give state names and assignments. I'm lazy, so I like to use decimal numbers.
// It doesn't really matter what assignment is used, as long as they're unique.
parameter WL = 0, WR = 1;
reg state;
reg next;
// Combinational always block for state transition logic. Given the current state and inputs,
// what should be next state be?
// Combinational always block: Use blocking assignments.
always @(*) begin
case (state)
WL: next = bump_left ? WR : WL;
WR: next = bump_right ? WL : WR;
endcase
end
// Combinational always block for state transition logic. Given the current state and inputs,
// what should be next state be?
// Combinational always block: Use blocking assignments.
always @(posedge clk, posedge areset) begin
if (areset) state <= WL;
else state <= next;
end
// Combinational output logic. In this problem, an assign statement are the simplest.
// In more complex circuits, a combinational always block may be more suitable.
assign walk_left = (state == WL);
assign walk_right = (state == WR);
endmodule
| 7.203305
|
module top_module (
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
output walk_left,
output walk_right,
output aaah
);
parameter L = 0, R = 1, LF = 2, RF = 3;
reg [1:0] state, next_state;
always @(*) begin
case (state)
L: next_state = (~ground) ? LF : (bump_left) ? R : L;
R: next_state = (~ground) ? RF : (bump_right) ? L : R;
LF: next_state = (ground) ? L : LF;
RF: next_state = (ground) ? R : RF;
endcase
end
always @(posedge clk or posedge areset) begin
if (areset) state <= L;
else state <= next_state;
end
assign walk_left = (state == L);
assign walk_right = (state == R);
assign aaah = (state == LF) || (state == RF);
endmodule
| 7.203305
|
module top_module (
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
input dig,
output walk_left,
output walk_right,
output aaah,
output digging
);
parameter L = 0, R = 1, LF = 2, RF = 3, LD = 4, RD = 5;
reg [2:0] state, next_state;
always @(*) begin
case (state)
L: next_state = (~ground) ? LF : (dig) ? LD : (bump_left) ? R : L;
R: next_state = (~ground) ? RF : (dig) ? RD : (bump_right) ? L : R;
LF: next_state = (ground) ? L : LF;
RF: next_state = (ground) ? R : RF;
LD: next_state = (ground) ? LD : LF;
RD: next_state = (ground) ? RD : RF;
endcase
end
always @(posedge clk or posedge areset) begin
if (areset) state <= L;
else state <= next_state;
end
assign aaah = (state == LF) || (state == RF);
assign walk_left = (state == L);
assign walk_right = (state == R);
assign digging = (state == LD) || (state == RD);
endmodule
| 7.203305
|
module top_module (
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
input dig,
output walk_left,
output walk_right,
output aaah,
output digging
);
parameter L = 0, R = 1, LF = 2, RF = 3, LD = 4, RD = 5, SP = 6;
reg [2:0] state, next_state;
int second;
always @(*) begin
case (state)
L: next_state = (~ground) ? LF : (dig) ? LD : (bump_left) ? R : L;
R: next_state = (~ground) ? RF : (dig) ? RD : (bump_right) ? L : R;
LF: next_state = (~ground) ? LF : (second > 19) ? SP : L;
RF: next_state = (~ground) ? RF : (second > 19) ? SP : R;
LD: next_state = (ground) ? LD : LF;
RD: next_state = (ground) ? RD : RF;
SP: next_state = SP;
endcase
end
always @(posedge clk or posedge areset) begin
if (areset) begin
state <= L;
second = 0;
end else begin
state <= next_state;
if ((state == LF) || (state == RF)) second = second + 1;
else if (second > 20) second = 20;
else second = 0; // have to reset counter
end
end
assign aaah = ((state == LF) || (state == RF));
assign walk_left = (state == L);
assign walk_right = (state == R);
assign digging = ((state == LD) || (state == RD));
endmodule
| 7.203305
|
module top_module (
input in,
input [9:0] state,
output [9:0] next_state,
output out1,
output out2
);
always @(*) begin
next_state[0] = (state[0] | state[1] | state[2] | state[3] | state[4] | state[7] | state[8] | state[9]) & ~in;
next_state[1] = (state[8] | state[9] | state[0]) & in;
next_state[2] = state[1] & in;
next_state[3] = state[2] & in;
next_state[4] = state[3] & in;
next_state[5] = state[4] & in;
next_state[6] = state[5] & in;
next_state[7] = (state[6] | state[7]) & in;
next_state[8] = state[5] & ~in;
next_state[9] = state[6] & ~in;
end
assign out1 = state[8] || state[9];
assign out2 = state[7] || state[9];
endmodule
| 7.203305
|
module top_module (
input clk,
input [7:0] in,
input reset, // Synchronous reset
output done
); //
parameter init = 0, read = 1, d = 2;
reg [1:0] state, next;
int cnt;
// State transition logic (combinational)
always @(*) begin
case (state)
init: next = (in[3]) ? read : init;
read: next = (cnt == 3) ? d : read;
d: next = (in[3]) ? read : init;
endcase
end
// State flip-flops (sequential)
always @(posedge clk) begin
if (reset) begin
state <= init;
cnt = 1;
end else begin
state <= next;
if (next == read) cnt = cnt + 1;
if (next == d) cnt = 1;
end
end
// Output logic
assign done = (state == d);
endmodule
| 7.203305
|
module top_module (
input clk,
input [7:0] in,
input reset, // Synchronous reset
output [23:0] out_bytes,
output done
); //
parameter B1 = 0, B2 = 1, B3 = 2, d = 3;
reg [1:0] state, next;
// FSM from fsm_ps2
always @(*) begin
case (state)
B1: next = (in[3]) ? B2 : B1;
B2: next = B3;
B3: next = d;
d: next = (in[3]) ? B2 : B1;
endcase
end
always @(posedge clk) begin
if (reset) state <= B1;
else begin
state <= next;
case (next)
B2: out_bytes[23:16] = in;
B3: out_bytes[15:8] = in;
d: out_bytes[7:0] = in;
endcase
end
end
// New: Datapath to store incoming bytes.
assign done = (state == d);
endmodule
| 7.203305
|
module top_module (
input clk,
input in,
input reset, // Synchronous reset
output done
);
parameter i = 0, r = 1, d = 2, e = 3;
reg [1:0] state, next;
int cnt;
always @(*) begin
case (state)
i: next = (~in) ? r : i;
r: next = (cnt == 9 && in) ? d : (cnt == 9 && ~in) ? e : r; // 9 for end bit
d: next = (~in) ? r : i;
e: next = (in) ? i : e;
endcase
end
always @(posedge clk) begin
if (reset) begin
state <= i;
cnt = 0; // 0 for start bit
end else begin
state <= next;
if (next == r) cnt = cnt + 1;
if (next == e || next == d) cnt = 0;
end
end
assign done = (state == d);
endmodule
| 7.203305
|
module top_module (
input clk,
input in,
input reset, // Synchronous reset
output [7:0] out_byte,
output done
); //
parameter i = 0, r = 1, d = 2, e = 3;
reg [1:0] state, next;
int cnt;
always @(*) begin
case (state)
i: next = (~in) ? r : i;
r: next = (cnt == 9 && in) ? d : (cnt == 9 && ~in) ? e : r; // 9 for end bit
d: next = (~in) ? r : i;
e: next = (in) ? i : e;
endcase
end
always @(posedge clk) begin
if (reset) begin
state <= i;
cnt = 0; // 0 for start bit
end else begin
state <= next;
if (next == r) begin
cnt = cnt + 1;
if (cnt > 1) out_byte[cnt-2] = in;
end
if (next == e || next == d) begin
cnt = 0;
end
end
end
assign done = (state == d);
endmodule
| 7.203305
|
module top_module (
input clk,
input in,
input reset, // Synchronous reset
output [7:0] out_byte,
output done
); //
parameter i = 0, r = 1, d = 2, e = 3, dp = 4;
reg [2:0] state, next;
reg odd;
parity p_check (
clk,
~(state == r),
in,
odd
);
int cnt;
always @(*) begin
case (state)
i: next = (~in) ? r : i;
r:
next = (cnt == 9 && in == ~odd)? dp : (cnt==9 && ~(in==~odd))? e : r; // 9 for parity bit
dp: next = (in) ? d : e; // parity check finish
d: next = (~in) ? r : i;
e: next = (in) ? i : e;
endcase
end
always @(posedge clk) begin
if (reset) begin
state <= i;
cnt = 0; // 0 for start bit
end else begin
state <= next;
if (next == r) begin
cnt = cnt + 1;
if (cnt > 1) out_byte[cnt-2] = in;
end
if (next == e || next == d) begin
cnt = 0;
end
end
end
assign done = (state == d);
endmodule
| 7.203305
|
module declaration syntax here:
module top_module(clk, reset, in, out);
input clk;
input reset; // Synchronous reset to state B
input in;
output out;//
reg out;
// Fill in state name declarations
parameter A=0, B=1;
reg present_state, next_state;
always @(posedge clk) begin
if (reset) begin
// Fill in reset logic
present_state <= B;
out = 1;
end else begin
case (present_state)
// Fill in state transition logic
A: next_state = (in)? A : B;
B: next_state = (in)? B : A;
endcase
// State flip-flops
present_state = next_state;
case (present_state)
// Fill in output logic
A: out = 0;
B: out = 1;
endcase
end
end
endmodule
| 6.89453
|
module top_module (
input clk,
input reset, // Synchronous reset
input in,
output disc,
output flag,
output err
);
parameter i = 0, one = 1, two = 2, thr = 3, four = 4, fiv = 5, six = 6, er = 7, ds = 8, flg = 9;
reg [3:0] state, next;
always @(*) begin
case (state)
i: next = (in) ? one : i;
one: next = (in) ? two : i;
two: next = (in) ? thr : i;
thr: next = (in) ? four : i;
four: next = (in) ? fiv : i;
fiv: next = (in) ? six : ds;
six: next = (in) ? er : flg;
er: next = (in) ? er : i;
ds: next = (in) ? one : i;
flg: next = (in) ? one : i;
endcase
end
always @(posedge clk) begin
if (reset) state <= i;
else state <= next;
end
assign disc = (state == ds);
assign flag = (state == flg);
assign err = (state == er);
endmodule
| 7.203305
|
module top_module (
input clk,
input aresetn, // Asynchronous active-low reset
input x,
output z
);
parameter a = 0, b = 1, c = 2;
reg [1:0] state, next;
always @(*) begin
case (state)
a: next = (x) ? b : a;
b: next = (x) ? b : c;
c: next = (x) ? b : a;
endcase
end
always @(posedge clk or negedge aresetn) begin
if (!aresetn) state <= a;
else state <= next;
end
assign z = (state == c) & x;
endmodule
| 7.203305
|
module top_module (
input clk,
input aresetn,
input x,
output reg z
);
// Give state names and assignments. I'm lazy, so I like to use decimal numbers.
// It doesn't really matter what assignment is used, as long as they're unique.
parameter S = 0, S1 = 1, S10 = 2;
reg [1:0] state, next; // Make sure state and next are big enough to hold the state encodings.
// Edge-triggered always block (DFFs) for state flip-flops. Asynchronous reset.
always @(posedge clk, negedge aresetn)
if (!aresetn) state <= S;
else state <= next;
// Combinational always block for state transition logic. Given the current state and inputs,
// what should be next state be?
// Combinational always block: Use blocking assignments.
always @(*) begin
case (state)
S: next = x ? S1 : S;
S1: next = x ? S1 : S10;
S10: next = x ? S1 : S;
default: next = 'x;
endcase
end
// Combinational output logic. I used a combinational always block.
// In a Mealy state machine, the output depends on the current state *and*
// the inputs.
always @(*) begin
case (state)
S: z = 0;
S1: z = 0;
S10:
z = x; // This is a Mealy state machine: The output can depend (combinational) on the input.
default: z = 1'bx;
endcase
end
endmodule
| 7.203305
|
module top_module (
input clk,
input areset,
input x,
output z
);
parameter a = 0, b = 1, c = 2;
reg [1:0] state, next;
always @(*) begin
case (state)
a: next = (x) ? b : a;
b: next = (x) ? c : b;
c: next = (x) ? c : b;
endcase
end
always @(posedge clk or posedge areset) begin
if (areset) state <= a;
else state <= next;
end
assign z = (state == b);
endmodule
| 7.203305
|
module top_module (
input clk,
input areset,
input x,
output z
);
parameter a = 0, b = 1;
reg state, next;
always @(*) begin
case (state)
a: next = (x) ? b : a;
b: next = b;
endcase
end
always @(posedge clk or posedge areset) begin
if (areset) state <= a;
else state <= next;
end
assign z = (state == a) & x || (state == b) & ~x;
endmodule
| 7.203305
|
module top_module (
input clk,
input reset, // Synchronous reset
input s,
input w,
output z
);
parameter a = 0, b = 1;
reg state, next;
always @(*) begin
case (state)
a: next = (s) ? b : a;
b: next = b;
endcase
end
always @(posedge clk) begin
if (reset) state <= a;
else state <= next;
end
int clk_cnt;
reg [1:0] cnt;
always @(posedge clk) begin
if (reset || state == a) begin
clk_cnt = 0;
cnt = 0;
end else begin
if (state == b) begin
if (clk_cnt < 3) clk_cnt = clk_cnt + 1;
else begin // clk_cnt = 3, reset cnt first
clk_cnt = 1;
cnt = 0;
end
end
if (next == b) begin
cnt = cnt + w;
end
end
end
assign z = (cnt == 2'd2) && (clk_cnt == 3);
endmodule
| 7.203305
|
module top_module (
input clk,
input reset, // Synchronous reset
input x,
output z
);
parameter A = 0, B = 1, C = 2, D = 3, E = 4;
reg [2:0] state, next;
always @(*) begin
case (state)
A: next = (~x) ? A : B;
B: next = (~x) ? B : E;
C: next = (~x) ? C : B;
D: next = (~x) ? B : C;
E: next = (~x) ? D : E;
endcase
end
always @(posedge clk) begin
if (reset) state <= A;
else state <= next;
end
assign z = (state == D) || (state == E);
endmodule
| 7.203305
|
module top_module (
input clk,
input [2:0] y,
input x,
output Y0,
output z
);
reg [2:0] state, next;
parameter A = 3'b000, B = 3'b001, C = 3'b010, D = 3'b011, E = 3'b100;
always @(*) begin
case (y)
A: next = (~x) ? A : B;
B: next = (~x) ? B : E;
C: next = (~x) ? C : B;
D: next = (~x) ? B : C;
E: next = (~x) ? D : E;
endcase
end
always @(posedge clk) begin
state <= next;
end
assign z = (y == D) || (y == E);
assign Y0 = next[0];
endmodule
| 7.203305
|
module top_module (
input [3:1] y,
input w,
output Y2
);
parameter E = 3'b100, F = 3'b101, D = 3'b011, C = 3'b010, B = 3'b001;
assign Y2 = (y == B) || (y == F) || (y == C && w) || (y == E && w);
endmodule
| 7.203305
|
module top_module (
input [6:1] y,
input w,
output Y2,
output Y4
);
assign Y2 = y[1] && ~w;
assign Y4 = (y[2] | y[3] | y[5] | y[6]) && w;
endmodule
| 7.203305
|
module top_module (
input clk,
input reset, // synchronous reset
input w,
output z
);
parameter A = 0, B = 1, C = 2, D = 3, E = 4, F = 5;
reg [3:0] state, next;
always @(*) begin
case (state)
A: next = (w) ? A : B;
B: next = (w) ? D : C;
C: next = (w) ? D : E;
D: next = (w) ? A : F;
E: next = (w) ? D : E;
F: next = (w) ? D : C;
endcase
end
always @(posedge clk) begin
if (reset) state <= A;
else state <= next;
end
assign z = (state == E) || (state == F);
endmodule
| 7.203305
|
module top_module (
input clk,
input areset, // Asynchronous reset to OFF
input j,
input k,
output out
); //
parameter OFF = 0, ON = 1;
reg state, next_state;
always @(*) begin
// State transition logic
case (state)
OFF: next_state = (j) ? ON : OFF;
ON: next_state = (k) ? OFF : ON;
endcase
end
always @(posedge clk, posedge areset) begin
// State flip-flops with asynchronous reset
if (areset) state <= OFF;
else state <= next_state;
end
// Output logic
assign out = (state == ON);
endmodule
| 7.203305
|
module top_module (
input clk,
input reset, // synchronous reset
input w,
output z
);
parameter A = 0, B = 1, C = 2, D = 3, E = 4, F = 5;
reg [3:0] state, next;
always @(*) begin
case (state)
A: next = (~w) ? A : B;
B: next = (~w) ? D : C;
C: next = (~w) ? D : E;
D: next = (~w) ? A : F;
E: next = (~w) ? D : E;
F: next = (~w) ? D : C;
endcase
end
always @(posedge clk) begin
if (reset) state <= A;
else state <= next;
end
assign z = (state == E) || (state == F);
endmodule
| 7.203305
|
module top_module (
input [5:0] y,
input w,
output Y1,
output Y3
);
assign Y1 = (y[0]) & w;
assign Y3 = (y[1] | y[2] | y[4] | y[5]) & ~w;
endmodule
| 7.203305
|
module top_module (
input clk,
input resetn, // active-low synchronous reset
input [3:1] r, // request
output [3:1] g // grant
);
wire r1, r2, r3, g1, g2, g3;
assign {r3, r2, r1} = r;
assign g = {g3, g2, g1};
parameter A = 0, B = 1, C = 2, D = 3;
reg [1:0] state, next;
always @(*) begin
case (state)
A: next = (r1) ? B : (r2) ? C : (r3) ? D : A;
B: next = (r1) ? B : A;
C: next = (r2) ? C : A;
D: next = (r3) ? D : A;
default next = A;
endcase
end
always @(posedge clk) begin
if (!resetn) state <= A;
else state <= next;
end
assign g1 = (state == B);
assign g2 = (state == C);
assign g3 = (state == D);
endmodule
| 7.203305
|
module logic_gates(oY, iA, iB, iC);
output oY;
input iA,iB,iC;
...
endmodule
| 7.336286
|
module top_module (
input clk,
input reset,
output reg [9:0] q
);
always @(posedge clk) begin
if (reset) q <= 0;
else if (q == 10'd999) q <= 0;
else q <= q + 1;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input shift_ena,
input count_ena,
input data,
output [3:0] q
);
always @(posedge clk) begin
if (shift_ena) begin
q <= {q[2:0], data};
end else if (count_ena) begin
q <= q - 1'b1;
end
end
endmodule
| 7.203305
|
module top_module (
input clk,
input reset, // Synchronous reset
input data,
output start_shifting
);
parameter A = 0, B = 1, C = 2, D = 3, E = 4;
reg [2:0] state, next;
always @(*) begin
case (state)
A: next = (data) ? B : A;
B: next = (data) ? C : A;
C: next = (data) ? C : D;
D: next = (data) ? E : A;
E: next = (reset) ? A : E;
endcase
end
always @(posedge clk) begin
if (reset) state <= A;
else state <= next;
end
assign start_shifting = (state == E);
endmodule
| 7.203305
|
module top_module (
input clk,
input reset, // Synchronous reset
output shift_ena
);
parameter A = 0, B = 1, C = 2, D = 3, E = 4;
reg [2:0] state, next;
always @(*) begin
case (state)
A: next = (reset) ? B : A;
B: next = (reset) ? B : C;
C: next = (reset) ? B : D;
D: next = (reset) ? B : E;
E: next = (reset) ? B : A;
endcase
end
always @(posedge clk) begin
if (reset) state <= B;
else state <= next;
end
assign shift_ena = (state != A);
endmodule
| 7.203305
|
module top_module (
input clk,
input reset, // Synchronous reset
input data,
output shift_ena,
output counting,
input done_counting,
output done,
input ack
);
parameter S = 0, S1 = 1, S11 = 2, S110 = 3, B0 = 4, B1 = 5, B2 = 6, B3 = 7, cnt = 8, hold = 9;
reg [3:0] state, next;
always @(*) begin
case (state)
S: next = (data) ? S1 : S;
S1: next = (data) ? S11 : S;
S11: next = (~data) ? S110 : S11;
S110: next = (data) ? B0 : S;
B0: next = B1;
B1: next = B2;
B2: next = B3;
B3: next = cnt;
cnt: next = (done_counting) ? hold : cnt;
hold: next = (ack) ? S : hold;
endcase
end
always @(posedge clk) begin
if (reset) state <= S;
else state <= next;
end
assign shift_ena = (state == B0) || (state == B1) || (state == B2) || (state == B3);
assign counting = (state == cnt);
assign done = (state == hold);
endmodule
| 7.203305
|
module top_module (
input clk,
input reset, // Synchronous reset
input data,
output [3:0] count,
output counting,
output done,
input ack
);
parameter S=0,S1=1,S11=2,S110=3, B0=4, B1=5, B2=6, B3=7, cnt=8, delay_cnt=9, last_cnt=10, hold=11;
reg [3:0] state, next, delay;
reg [9:0] thousand;
reg [3:0] counter;
always @(*) begin
case (state)
S: next = (data) ? S1 : S;
S1: next = (data) ? S11 : S;
S11: next = (~data) ? S110 : S11;
S110: next = (data) ? B0 : S;
B0: begin
next = B1;
delay[3] = data;
end
B1: begin
next = B2;
delay[2] = data;
end
B2: begin
next = B3;
delay[1] = data;
end
B3: begin
next = cnt;
delay[0] = data;
end
cnt: next = (delay == 4'd0) ? last_cnt : (thousand == 10'd998) ? delay_cnt : cnt;
delay_cnt: next = (counter == 4'd1) ? last_cnt : cnt; // one clock count
last_cnt: next = (thousand == 10'd999) ? hold : last_cnt;
hold: next = (ack) ? S : hold;
endcase
end
always @(posedge clk) begin
if (state == B3) begin
counter <= {delay[3:1], data};
thousand <= 0;
end
if (state == cnt || state == last_cnt) thousand <= thousand + 1'b1;
if (state == delay_cnt) begin
thousand <= 0;
counter <= counter - 1'b1;
end
end
always @(posedge clk) begin
if (reset) state <= S;
else begin
state <= next;
end
end
assign counting = (state == cnt) || (state == delay_cnt) || (state == last_cnt);
assign done = (state == hold);
assign count = counter;
endmodule
| 7.203305
|
module top_module (
input d,
input done_counting,
input ack,
input [9:0] state, // 10-bit one-hot current state
output B3_next,
output S_next,
output S1_next,
output Count_next,
output Wait_next,
output done,
output counting,
output shift_ena
); //
// You may use these parameters to access state bits using e.g., state[B2] instead of state[6].
parameter S = 0, S1 = 1, S11 = 2, S110 = 3, B0 = 4, B1 = 5, B2 = 6, B3 = 7, Count = 8, Wait = 9;
assign B3_next = state[B2];
assign S_next = ~d & state[S] | ~d & state[S1] | ~d & state[S110] | ack & state[Wait];
assign S1_next = d & state[S];
assign Count_next = state[B3] | ~done_counting & state[Count];
assign Wait_next = done_counting & state[Count] | ~ack & state[Wait];
assign done = state[Wait];
assign counting = state[Count];
assign shift_ena = state[B0] | state[B1] | state[B2] | state[B3];
endmodule
| 7.203305
|
module dff2 (
clock,
reset,
d,
q
);
input clock, reset, d;
output q;
reg q;
always @(posedge clock or negedge reset) begin
if (!reset) q <= 0;
else q <= d;
end
endmodule
| 6.764726
|
module logic_gates(oY, iA, iB, iC);
output oY;
inputiA,iB,iC;
wire andl, and2 //连接线
and(and1, iA, iB);
and(and2, iA, iC);
or(oY, andl, and2)
endmodule
| 7.336286
|
module logic_gates(oY, iA, iB, iC);
output oY;
inputiA,iB,iC;
assign oY=(iA&iB)|(iA&iC);
endmodule
| 7.336286
|
module fsm_eg_mult_seg
(
input wire clk, reset,
input wire a, b,
output wire y0, y1
);
//符号状态声明
localparam [1: 0] s0=2'b00,
s1=2'b01,
s2=2'b10;
//信号声明
reg [1: 0] state_reg, state_next;
//状态寄存器
always@ (posedge clk, posedge reset)
begin
if (reset)
state_reg <= s0;
else
state_reg <= state_next;
end
//下一状态逻辑
always @*
case (state_reg)
s0: begin if (a)
begin
if(b)
state_next=s2;
else
state_next=s1;
end
else
state_next = s0;
end
s1: begin
if (a)
state_next = s0;
else
state_next=s1;
end
s2： state next=s0;
default: state_next=s0
endcase
end
//摩尔输出逻辑
assign yl =(state_reg==s0)||(state_reg = s1);
//米里输出逻辑
assign y0 =(state_ reg== s0)&a&b;
endmodule
| 7.419378
|
module fsm_eg_2_seg
{
input wire clk, reset,
input wire a, b ,
output reg y0, yi
};
//符号状态声明
localparam [1: 0] s0 =2'b00,
s1=2'b01,
s2=2'b10;
//信号声明
reg [1: 0] state_reg, state_next;//状态寄存器
always @(posedge clk, posedge reset)begin
if (reset)
state_reg<= s0;
else
state_reg<=state_next;
end
//下ー状态逻辑和输出逻辑
always@*
begin
state_next= state_reg;//默认输出：
y1=1'b0;
y0=1'b0;
case(state_reg)
s0: begin
y1=1'b1;
if (a)
begin
if (b)
begin
state_next = s2;
y0=1'b1;
end
else
state_next = sl;
end
end
s1: begin
y1=1'b1;
if (a)
state_next= s0;
end
s2: state_next = s0;
default: state_next=s0;
endcase
end
endmodule
| 8.234733
|
module edge_detect_moore
{
input wire clk, reset,
input wire level,
output reg tick
}
//符号状态声明
localparam [1: 0]
zero =2'b00,
eda=2'b01,
one =2'b10;//信号声明
reg [1: 0] state_reg, state_next;//状态寄存器
always@(posedge clk, posedge reset)
begin
if (reset)state_reg <= zero;
else
state_reg <=state_next;
end
//下一状态逻辑和输出逻辑
always@*
begin
state_next=state_reg;
tick=1'b0;
case (state_reg)
zero:
if (level)
state_next= edg;
edg:
begin
tick = 1'b1;
if (level)
state_next=one;
else
state_next =zero;
end
one:
if (~level)
state_next=zero;
default: state_next=zero;
endcase
end
endmodule
| 8.503577
|
module edge_detect_mealy
{
input wire clk, reset,
input wire level,
output reg tick
}
//符号状态声明
local param zero=1'b0,
one=1'b1;
reg state_reg, state_next;//状态寄存器
always@(posedge clk, posedge reset)
begin
if (reset)state_reg <= zero;
else
state_reg <=state_next;
end
//下一状态逻辑和输出逻辑
always@*
begin
state_next=state_reg;
tick=1'b0;
case (state_reg)
zero:begin
if (level)begin
tick = 1'b1;
state_next=one;
end
end
one:
if (~level)
state_next=zero;
default: state_next=zero;
endcase
end
endmodule
| 8.503577
|
module edge_detect_gate (
input wire clk,
reset,
input wire level,
output wire tick
);
reg delay_reg;
always @(posedge clk, posedge reset) begin
if (reset) delay_reg <= 1'b0;
else delay_reg <= level;
end
assign tick = ~delay_reg & level;
endmodule
| 7.357013
|
module top_module (
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
input dig,
output reg walk_left,
output reg walk_right,
output reg aaah,
output reg digging
);
reg walk_temp[1:0];
initial begin
walk_left = 1;
walk_right = 0;
aaah = 0;
digging = 0;
end
always @(posedge clk) begin
if (areset) begin
walk_left = 1;
walk_right = 0;
aaah = 0;
digging = 0;
end else begin
if (ground == 0) begin
if (digging) begin
aaah = 1;
digging = 0;
end
if (aaah == 0) begin
walk_temp[0] = walk_left;
walk_temp[1] = walk_right;
aaah = 1;
digging = 0;
end
walk_left = 0;
walk_right = 0;
end else begin
if (aaah == 1) begin
walk_left = walk_temp[0];
walk_right = walk_temp[1];
aaah = 0;
end else begin
if (dig) begin
digging = 1;
walk_temp[0] = walk_left;
walk_temp[1] = walk_right;
walk_left = 0;
walk_right = 0;
end
if (digging == 0) begin
if (walk_left) begin
if (bump_left) begin
walk_left = 0;
walk_right = 1;
end
end else begin
if (bump_right) begin
walk_left = 1;
walk_right = 0;
end
end
end
end
end
end
end
endmodule
| 7.203305
|
module top_module (
input clk,
input a,
input b,
output wire out_assign,
output reg out_always_comb,
output reg out_always_ff
);
assign out_assign = a ^ b;
always @(*) begin
out_always_comb = a ^ b;
end
always @(posedge clk) begin
out_always_ff <= a ^ b;
end
endmodule
| 7.203305
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = ((~opcode) == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = ('0 == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = ('1 == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == (~'b01));
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == '0);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == '1);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode != 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module top_module (
input clk,
input reset, // Synchronous active-high reset
input w,
output z
);
parameter A = 3'b000;
parameter B = 3'b001;
parameter C = 3'b010;
parameter D = 3'b011;
parameter E = 3'b100;
parameter F = 3'b101;
reg [2:0] cstate, nstate;
always @(posedge clk) begin
if (reset) begin
cstate <= A;
end else begin
cstate <= nstate;
end
end
always @(*) begin
case (cstate)
A: nstate = w ? B : A;
B: nstate = w ? C : D;
C: nstate = w ? E : D;
D: nstate = w ? F : A;
E: nstate = w ? E : D;
F: nstate = w ? C : D;
endcase
end
assign z = (cstate == E || cstate == F);
endmodule
| 7.203305
|
module top_module (
input a,
input b,
input sel_b1,
input sel_b2,
output wire out_assign,
output reg out_always
);
assign out_assign = ({sel_b2, sel_b1} == 2'b11) ? b : a;
always @(*) begin
if ({sel_b2, sel_b1} == 2'b11) out_always = b;
else out_always = a;
end
endmodule
| 7.203305
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (~(opcode == 'b0101001));
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = '0;
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = '1;
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module top_module (
input [5:0] y,
input w,
output Y1,
output Y3
);
assign Y1 = w && y[0];
assign Y3 = (~w) && (y[1] || y[2] || y[4] || y[5]);
endmodule
| 7.203305
|
module top_module (
input cpu_overheated,
output reg shut_off_computer,
input arrived,
input gas_tank_empty,
output reg keep_driving
); //
always @(*) begin
if (cpu_overheated) shut_off_computer = 1;
else begin
shut_off_computer = 0;
end
end
always @(*) begin
if ((~arrived) & (~gas_tank_empty)) keep_driving = 1;
else begin
keep_driving = 0;
end
end
endmodule
| 7.203305
|
module CLA2 (
input [1:0] iG,
input [1:0] iP,
input iC,
output oG,
output oP,
output [2:0] oC
);
assign oC[0] = iC;
assign oC[1] = iG[0] | (iP[0] & oC[0]);
assign oG = iG[1] | (iP[1] & iG[0]);
assign oP = iP[1] & iP[0];
assign oC[2] = oG | (oP & oC[0]);
endmodule
| 7.086682
|
module CLA4 (
input [3:0] iG,
input [3:0] iP,
input iC,
output oG,
output oP,
output [4:0] oC
);
assign oC[0] = iC;
assign oC[1] = iG[0] | (iP[0] & oC[0]);
assign oC[2] = iG[1] | (iP[1] & iG[0]) | (iP[1] & iP[0] & oC[0]);
assign oC[3] = iG[2] | (iP[2] & iG[1]) | (iP[2] & iP[1] & iG[0]) | (iP[2] & iP[1] & iP[0] & oC[0]);
assign oG = iG[3] | (iP[3] & iG[2]) | (iP[3] & iP[2] & iG[1]) | (iP[3] & iP[2] & iP[1] & iG[0]);
assign oP = iP[3] & iP[2] & iP[1] & iP[0];
assign oC[4] = oG | (oP & oC[0]);
endmodule
| 7.783567
|
module Adder4 (
input [3:0] iA,
input [3:0] iB,
input iC,
output [3:0] oS,
output oG,
output oP,
output oC
);
wire [3:0] G = iA & iB;
wire [3:0] P = iA | iB;
wire [3:0] C;
CLA4 cla (
.iG(G),
.iP(P),
.iC(iC),
.oG(oG),
.oP(oP),
.oC({oC, C})
);
assign oS = iA ^ iB ^ C;
endmodule
| 7.84746
|
module Adder8 (
input [7:0] iA,
input [7:0] iB,
input iC,
output [7:0] oS,
output oG,
output oP,
output oC
);
wire [1:0] G;
wire [1:0] P;
wire [1:0] C;
Adder4 adder0 (
.iA(iA[3:0]),
.iB(iB[3:0]),
.iC(C[0]),
.oS(oS[3:0]),
.oG(G[0]),
.oP(P[0])
);
Adder4 adder1 (
.iA(iA[7:4]),
.iB(iB[7:4]),
.iC(C[1]),
.oS(oS[7:4]),
.oG(G[1]),
.oP(P[1])
);
CLA2 cla (
.iG(G),
.iP(P),
.iC(iC),
.oG(oG),
.oP(oP),
.oC({oC, C})
);
endmodule
| 8.497707
|
module Adder16 (
input [15:0] iA,
input [15:0] iB,
input iC,
output [15:0] oS,
output oG,
output oP,
output oC
);
wire [3:0] G;
wire [3:0] P;
wire [3:0] C;
Adder4 adder0 (
.iA(iA[3:0]),
.iB(iB[3:0]),
.iC(C[0]),
.oS(oS[3:0]),
.oG(G[0]),
.oP(P[0])
);
Adder4 adder1 (
.iA(iA[7:4]),
.iB(iB[7:4]),
.iC(C[1]),
.oS(oS[7:4]),
.oG(G[1]),
.oP(P[1])
);
Adder4 adder2 (
.iA(iA[11:8]),
.iB(iB[11:8]),
.iC(C[2]),
.oS(oS[11:8]),
.oG(G[2]),
.oP(P[2])
);
Adder4 adder3 (
.iA(iA[15:12]),
.iB(iB[15:12]),
.iC(C[3]),
.oS(oS[15:12]),
.oG(G[3]),
.oP(P[3])
);
CLA4 cla (
.iG(G),
.iP(P),
.iC(iC),
.oG(oG),
.oP(oP),
.oC({oC, C})
);
endmodule
| 8.053466
|
module Adder32 (
input [31:0] iA,
input [31:0] iB,
input iC,
output [31:0] oS,
output oG,
output oP,
output oC
);
wire [1:0] G;
wire [1:0] P;
wire [1:0] C;
Adder16 adder0 (
.iA(iA[15:0]),
.iB(iB[15:0]),
.iC(C[0]),
.oS(oS[15:0]),
.oG(G[0]),
.oP(P[0])
);
Adder16 adder1 (
.iA(iA[31:16]),
.iB(iB[31:16]),
.iC(C[1]),
.oS(oS[31:16]),
.oG(G[1]),
.oP(P[1])
);
CLA2 cla (
.iG(G),
.iP(P),
.iC(iC),
.oG(oG),
.oP(oP),
.oC({oC, C})
);
endmodule
| 7.953506
|
module alu (
a,
b,
opcode,
c
);
output signed [31:0] c;
//output zero;
//output overflow;
//output neg;
input signed [31:0] a, b;
input [2:0] opcode;
reg [32:0] reg_C;
//reg zf;
//reg nf;
reg [31:0] reg_A, reg_B;
parameter sla = 3'b000, srai = 3'b001;
always @(a, b, opcode) begin
reg_A = a;
reg_B = b;
case (opcode)
sla: // arith left shift
begin
reg_C = {reg_A[30:0], 1'b0};
end
srai: // arith right shift
begin
reg_C = {reg_A[31:1]};
reg_A = reg_C;
end
endcase
end
assign c = reg_C[31:0];
endmodule
| 6.634214
|
module mux4x1 (
input [31:0] a,
input [31:0] b,
input [31:0] c,
input [31:0] d,
input [1:0] sel,
output reg [31:0] y
);
always @(sel or a or b or c or d) begin
begin : mux4x1
case (sel)
2'b00: y = a;
2'b01: y = b;
2'b10: y = c;
2'b11: y = d;
endcase
end
end
endmodule
| 6.791623
|
module adder1b (
input a,
input b,
input c,
output s,
output cout
);
assign s = a ^ b ^ c;
assign cout = (a & b) | (b & c) | (c & a);
endmodule
| 8.20245
|
module zeroextend (
input a,
output [31:0] b
);
assign b[0] = a;
assign b[31:1] = 31'd0;
endmodule
| 8.72426
|
module main (
input [31:0] a,
input [31:0] b,
input [2:0] f,
output cout,
output [31:0] y,
output of,
output reg zf
);
wire [31:0] bout;
wire [31:0] orgate;
wire [31:0] andgate;
wire [31:0] temp;
wire [31:0] s;
mux2x1 mx (
b,
~b,
f[2],
bout
);
assign andgate = a & bout;
assign orgate = a | bout;
adder32b adder (
a,
bout,
f[2],
s,
cout,
of
);
zeroextend sx (
s[31],
temp
);
mux4x1 mx41 (
andgate,
orgate,
s,
temp,
f[1:0],
y
);
always @(*) begin
if (y == 32'd0) zf = 1'b1;
else zf = 1'b0;
end
endmodule
| 7.081372
|
module Adder32bit (
A,
B,
Sum
);
input [31:0] A, B;
output reg [31:0] Sum;
always @(*) begin
Sum <= A + B;
end
endmodule
| 8.498695
|
module decoder (
fetchoutput,
destination,
operationnumber,
source_1,
source_2,
unsigned_1,
unsigned_2,
unsigned_3,
unsigned_4,
unsigned_5,
signed_1,
signed_2,
signed_3,
flush,
super_duper_a,
super_duper_b
);
// Inputs & Putputs //
output [05:00] destination;
output [05:00] operationnumber;
output [05:00] source_1;
output [05:00] source_2;
output [05:00] unsigned_1;
output [15:00] unsigned_2;
output [08:00] unsigned_3;
output [09:00] unsigned_4;
output [08:00] unsigned_5;
output [21:00] signed_1;
output [15:00] signed_2;
output [09:00] signed_3;
output super_duper_a;
output super_duper_b;
output flush;
input [31:00] fetchoutput;
// Registers //
reg [05:00] opcode;
reg operation;
reg [05:00] destination;
reg [05:00] source_1;
reg [05:00] source_2;
reg [05:00] unsigned_1;
reg [15:00] unsigned_2;
reg [08:00] unsigned_3;
reg [09:00] unsigned_4;
reg [08:00] unsigned_5;
reg [05:00] operationnumber;
reg [21:00] signed_1;
reg [15:00] signed_2;
reg [09:00] signed_3;
reg super_duper_a; // used for 32 bit instructions that cannot be different using operation number alone
reg super_duper_b;
// Memory write //
// Wire Declarations //
wire [31:00] fetchoutput;
wire bit_check;
wire flush;
///////////////////////////////////
assign bit_check = fetchoutput[31];
assign flush = bit_check;
/* fetchoutput[01:07] = opcode; */
always @(fetchoutput) begin
if (bit_check == 0) begin
opcode = fetchoutput[30:25];
destination = fetchoutput[24:22];
source_1 = fetchoutput[21:19];
source_2 = fetchoutput[18:16];
unsigned_1 = fetchoutput[18:16];
unsigned_2 = fetchoutput[21:16];
unsigned_3 = fetchoutput[24:16];
signed_1 = fetchoutput[24:16];
signed_2 = fetchoutput[24:16];
signed_3 = fetchoutput[24:16];
operationnumber = opcode;
super_duper_a = 0;
super_duper_b = 0;
end else if (bit_check == 1) begin
destination[02:00] = fetchoutput[24:22];
destination[05:03] = fetchoutput[08:06];
source_1[02:00] = fetchoutput[21:19];
source_1[05:03] = fetchoutput[05:03];
source_2[02:00] = fetchoutput[18:16];
source_2[05:03] = fetchoutput[02:00];
unsigned_1[02:00] = fetchoutput[18:16];
unsigned_1[05:03] = fetchoutput[02:00];
unsigned_2[05:00] = fetchoutput[21:16];
unsigned_2[09:06] = fetchoutput[12:09];
unsigned_2[15:10] = fetchoutput[05:00];
unsigned_4[02:00] = fetchoutput[18:16];
unsigned_4[06:03] = fetchoutput[12:09];
unsigned_4[09:07] = fetchoutput[02:00];
unsigned_5[02:00] = fetchoutput[18:16];
unsigned_5[05:03] = fetchoutput[12:08];
unsigned_5[08:06] = fetchoutput[02:00];
signed_1[08:00] = fetchoutput[24:16];
signed_1[21:09] = fetchoutput[12:00];
signed_2[02:00] = fetchoutput[24:22];
signed_2[05:03] = fetchoutput[18:16];
signed_2[12:06] = fetchoutput[12:06];
signed_2[15:13] = fetchoutput[02:00];
signed_3[02:00] = fetchoutput[24:22];
signed_3[09:03] = fetchoutput[12:06];
opcode = fetchoutput[30:25];
operationnumber = opcode;
if (fetchoutput[15:09] !== 0) begin // for 32 bit commands that have the same operation code but extra criteria
super_duper_a = 1;
end
if (fetchoutput[9] !== 0) begin // for the b_itwise commands that need to be different
super_duper_b = 1;
end else begin
super_duper_a = 0;
super_duper_b = 0;
end
end
end
endmodule
| 7.018254
|
module testbench_32BFA;
reg [31:0] A, B;
reg CarryIn;
wire [31:0] Sum;
wire Carry;
integer i, j;
FADDER32 mod (
Sum,
Carry,
A,
B,
CarryIn
);
initial begin
$monitor($time, " A = %b, B = %b, Carry In = %b, Carry = %b, Sum = %b.", A, B, CarryIn, Carry,
Sum);
#0 A = 32'b11110000000000000000000000000000;
B = 32'b00000000000000000000000000000111;
CarryIn = 1'b0;
#5 A = 32'b11111111111111111111111111111111;
B = 32'b11111111111111111111111111111111;
CarryIn = 1'b0;
#5 A = 32'b11110000000000001111000000000000;
B = 32'b00001010101000000000000000000111;
CarryIn = 1'b1;
end
endmodule
| 6.607722
|
module a_32bitRegester_tb;
wire q;
reg c, l, r;
reg [31:0] d;
bit32_regester b (
q,
c,
l,
d,
r
);
initial begin
#5 d = 'h00000000;
r = 'b1;
l = 'b0;
#5 c = 'b0;
#5 c = 'b1;
#5 golden(q, 'h00000000, l, d, r);
#5;
#5 d = 'h00000001;
r = 'b0;
l = 'b1;
#5 c = 'b0;
#5 c = 'b1;
#5 golden(q, 'h00000001, l, d, r);
#5;
#5 d = 'h00000111;
r = 'b0;
l = 'b0;
#5 c = 'b0;
#5 c = 'b1;
#5 golden(q, 'h00000001, l, d, r);
#5;
end
task golden;
input result, expected, l, d, r;
begin
$write("d:%d r:%d l:%d so Exp-q:%d and Act-q:%d ", d, r, l, expected, result);
if (result == expected) begin
$write("[PASSED]");
end else begin
$write("[FAILED]");
end
$write("\n");
$write("Ran bitReg TB\n");
end
endtask
endmodule
| 6.679986
|
module fulladdr_1_bit (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
xor (w1, a, b);
xor (sum, w1, c_in);
and (w2, a, b);
and (w3, w1, c_in);
or (c_out, w2, w3);
endmodule
| 7.174501
|
module fulladdr_4_bit (
sum,
c_out,
a,
b,
c_in
);
input [3:0] a, b;
input c_in;
output [3:0] sum;
output c_out;
wire w1, w2, w3;
fulladdr_1_bit fa0 (
sum[0],
w1,
a[0],
b[0],
c_in
);
fulladdr_1_bit fa1 (
sum[1],
w2,
a[1],
b[1],
w1
);
fulladdr_1_bit fa2 (
sum[2],
w3,
a[2],
b[2],
w2
);
fulladdr_1_bit fa3 (
sum[3],
c_out,
a[3],
b[3],
w3
);
endmodule
| 7.111335
|
module fulladdr_16_bit (
sum,
c_out,
a,
b,
c_in
);
input [15:0] a, b;
input c_in;
output [15:0] sum;
output c_out;
wire w1, w2, w3;
fulladdr_4_bit fa4_0 (
sum[3:0],
w1,
a[3:0],
b[3:0],
c_in
);
fulladdr_4_bit fa4_1 (
sum[7:4],
w2,
a[7:4],
b[7:4],
w1
);
fulladdr_4_bit fa4_2 (
sum[11:8],
w3,
a[11:8],
b[11:8],
w2
);
fulladdr_4_bit fa4_3 (
sum[15:12],
c_out,
a[15:12],
b[15:12],
w3
);
endmodule
| 6.986683
|
module fulladdr_32_bit (
sum,
c_out,
a,
b,
c_in
);
input [31:0] a, b;
input c_in;
output [31:0] sum;
output c_out;
wire w1;
fulladdr_16_bit fa16_0 (
sum[15:0],
w1,
a[15:0],
b[15:0],
c_in
);
fulladdr_16_bit fa16_1 (
sum[31:16],
c_out,
a[31:16],
b[31:16],
w1
);
endmodule
| 7.255391
|
module mux8x1 (
input in0,
input in1,
input in2,
input in3,
input in4,
input in5,
input [2:0] sel,
output reg muxOut
);
always @(sel, in0, in1, in2, in3, in4, in5)
case (sel)
3'b000: muxOut = in0;
3'b001: muxOut = in1;
3'b010: muxOut = in2;
3'b011: muxOut = in3;
3'b100: muxOut = in4;
3'b101: muxOut = in5;
3'b110: muxOut = 1'b0;
3'b111: muxOut = 1'b0;
endcase
endmodule
| 7.340408
|
module Adder32Bit (
input1,
input2,
out,
overflowBit
);
input [31:0] input1, input2;
output [31:0] out;
reg [31:0] out;
output overflowBit;
reg overflowBit;
always @(input1 or input2) begin
{overflowBit, out} = input1 + input2;
end
endmodule
| 7.363356
|
module ripple_carry_adder #(
parameter WIDTH = 32
) (
input [WIDTH-1:0] input_a,
input [WIDTH-1:0] input_b,
input carry_in,
output [WIDTH-1:0] final_sum,
output carry_out
);
wire [ WIDTH:0] carry;
wire [WIDTH-1:0] incr_sum;
// First full-adder has cin as logic 0
assign carry_in = 1'b0;
assign carry[0] = carry_in;
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin
fa_1bit fa_1bit_inst (
.sum(incr_sum[i]),
.cout(carry[i+1]),
.a(input_a[i]),
.b(input_b[i]),
.cin(carry[i])
);
end
endgenerate
// Concatenate final_sum
assign final_sum = {carry[WIDTH-1], incr_sum};
assign carry_out = carry[WIDTH];
endmodule
| 7.682509
|
module CLA_32_4 (
input [31:0] a_inp,
input [31:0] b_inp,
output reg [31:0] s_out,
output reg c_out,
input clock,
input reset
);
wire Cin_1, Cin_2, Cin_3, Cin_4, Cin_5, Cin_6, Cin_7, Cin_8;
wire Cout_1, Cout_2, Cout_3, Cout_4, Cout_5, Cout_6, Cout_7, Cout_8;
reg [3:0] A_1, A_2, A_3, A_4, A_5, A_6, A_7, A_8;
reg [3:0] B_1, B_2, B_3, B_4, B_5, B_6, B_7, B_8;
wire [3:0] Sum_1, Sum_2, Sum_3, Sum_4, Sum_5, Sum_6, Sum_7, Sum_8;
wire [3:0] Generate_1 ,Generate_2 ,Generate_3 /*,Generate_4*/ ,Generate_5 ,Generate_6 ,Generate_7 /*,Generate_8*/;
wire [3:0] Propogate_1 ,Propogate_2 ,Propogate_3 /*,Propogate_4*/ ,Propogate_5 ,Propogate_6 ,Propogate_7 /*,Propogate_8*/;
wire [3:0] Ignore_1, Ignore_2, Ignore_3, Ignore_4;
wire [15:0] Propogate_4, Generate_4, Propogate_8, Generate_8;
assign {Generate_8 ,Generate_4 } = ({A_8,A_7,A_6,A_5,A_4,A_3,A_2,A_1} & {B_8,B_7,B_6,B_5,B_4,B_3,B_2,B_1});
assign {Propogate_8,Propogate_4} = ({A_8,A_7,A_6,A_5,A_4,A_3,A_2,A_1} ^ {B_8,B_7,B_6,B_5,B_4,B_3,B_2,B_1});
assign Cin_1 = 0;
assign Cin_2 = Cout_1;
assign Cin_3 = Cout_2;
assign Cin_4 = Cout_3;
assign Cin_5 = Cout_4;
assign Cin_6 = Cout_5;
assign Cin_7 = Cout_6;
assign Cin_8 = Cout_7;
always @(posedge clock or posedge reset) begin
if (reset) begin
s_out <= 'b0;
c_out <= 'b0;
A_1 <= 'b0;
A_2 <= 'b0;
A_3 <= 'b0;
A_4 <= 'b0;
A_5 <= 'b0;
A_6 <= 'b0;
A_7 <= 'b0;
A_8 <= 'b0;
B_1 <= 'b0;
B_2 <= 'b0;
B_3 <= 'b0;
B_4 <= 'b0;
B_5 <= 'b0;
B_6 <= 'b0;
B_7 <= 'b0;
B_8 <= 'b0;
end else begin
{A_8, A_7, A_6, A_5, A_4, A_3, A_2, A_1} <= a_inp;
{B_8, B_7, B_6, B_5, B_4, B_3, B_2, B_1} <= b_inp;
s_out <= {Sum_8, Sum_7, Sum_6, Sum_5, Sum_4, Sum_3, Sum_2, Sum_1};
c_out <= Cout_8;
end
end
CLA_4 U1 (
Cin_1,
A_1,
B_1,
Sum_1,
Generate_1,
Propogate_1
); // CLA Adder with first level carry generator using 4 bit adder group
CLA_4 U2 (
Cin_2,
A_2,
B_2,
Sum_2,
Generate_2,
Propogate_2
);
CLA_4 U3 (
Cin_3,
A_3,
B_3,
Sum_3,
Generate_3,
Propogate_3
);
CLA_4 U4 (
Cin_4,
A_4,
B_4,
Sum_4,
Ignore_1,
Ignore_2
);
CLA_4 U5 (
Cin_5,
A_5,
B_5,
Sum_5,
Generate_5,
Propogate_5
);
CLA_4 U6 (
Cin_6,
A_6,
B_6,
Sum_6,
Generate_6,
Propogate_6
);
CLA_4 U7 (
Cin_7,
A_7,
B_7,
Sum_7,
Generate_7,
Propogate_7
);
CLA_4 U8 (
Cin_8,
A_8,
B_8,
Sum_8,
Ignore_3,
Ignore_4
);
carry_out_4 U9 (
Cin_1,
Generate_1,
Propogate_1,
Cout_1
); // CLA Adder with second level carry generator using 4 bit adder group
carry_out_4 U10 (
Cin_2,
Generate_2,
Propogate_2,
Cout_2
);
carry_out_4 U11 (
Cin_3,
Generate_3,
Propogate_3,
Cout_3
);
//carry_out_4 U12 (Cin_4, Generate_4 ,Propogate_4, Cout_4);
carry_out_16 U12 (
Cin_1,
Generate_4,
Propogate_4,
Cout_4
); // 3rd level CLA
carry_out_4 U13 (
Cin_5,
Generate_5,
Propogate_5,
Cout_5
);
carry_out_4 U14 (
Cin_6,
Generate_6,
Propogate_6,
Cout_6
);
carry_out_4 U15 (
Cin_7,
Generate_7,
Propogate_7,
Cout_7
);
//carry_out_4 U16 (Cin_8, Generate_8 ,Propogate_8, Cout_8);
carry_out_16 U16 (
Cin_5,
Generate_8,
Propogate_8,
Cout_8
); // 3rd level CLA
endmodule
| 7.993192
|
module CLA_32_4_tb ();
reg [31:0] A = 0, B = 0;
wire [31:0] Sum;
wire Cout;
reg reset, clock;
initial begin : A_TB
A = 0;
#10 A = 32'h00FF_00FF;
#30 A = 32'h0000_0000; // Making input = 0 so that next transition can be noted
#30 A = 32'h8080_8080;
#30 A = 32'h0000_0000; // Making input = 0 so that next transition can be noted
#30 A = 32'h0000_00FF;
#30 A = 32'h0000_0000; // Making input = 0 so that next transition can be noted
#30 A = 32'h1111_1111;
end
initial begin : B_TB
B = 0;
#10 B = 32'hFF00_FF01;
#30 B = 32'h0000_0000; // Making input = 0 so that next transition can be noted
#30 B = 32'h8080_8080;
#30 B = 32'h0000_0000; // Making input = 0 so that next transition can be noted
#30 B = 32'hFFFF_FF80;
#30 B = 32'h0000_0000; // Making input = 0 so that next transition can be noted
#30 B = 32'h2222_2222;
end
initial begin : reset_TB
reset = 0;
#2 reset = 1;
#5 reset = 0;
#55 reset = 1;
#5 reset = 0;
#55 reset = 1;
#5 reset = 0;
#55 reset = 1;
#5 reset = 0;
#65 $finish;
end
initial begin : clock_TB
clock = 0;
#5 clock = 1;
forever #5 clock = ~clock;
end
CLA_32_4 U1 (
A,
B,
Sum,
Cout,
clock,
reset
);
initial begin
$monitor("TIME :", $time,
" HEX VALUES : a_inp = %h b_inp = %h s_out = %h c_out = %h", A, B, Sum,
Cout);
end
initial begin
$dumpfile("CLA_32_4_tb.vcd");
$dumpvars(0, CLA_32_4_tb);
end
endmodule
| 7.828759
|
module gf2m #(
parameter DIGITAL = 32,
parameter DATA_WIDTH = 163
) (
input wire rst,
input wire clk,
input wire start,
input wire [DATA_WIDTH - 1 : 0] a,
input wire [DATA_WIDTH - 1 : 0] g,
input wire [DIGITAL - 1:0] b,
output reg [DATA_WIDTH - 1 : 0] t_i_j,
output reg done
);
parameter ITERATION_NUMBER = DATA_WIDTH / DIGITAL;
parameter IDLE = 1'b0;
parameter CAL = 1'b1;
reg state;
reg [12:0] counter;
wire [DATA_WIDTH - 1 : 0] wire_t_i_j;
serial #(
.DATA_WIDTH(DATA_WIDTH),
.DIGITAL(DIGITAL)
) serial_8_bit (
.b(b),
.a(a),
.g(g),
.t_i1_j1(t_i_j),
.t_i_j(wire_t_i_j)
);
always @(posedge clk or negedge rst) begin : proc_counter
if (~rst) begin
counter <= 0;
end else begin
case (state)
IDLE: begin
counter <= 6'd0;
end
CAL: begin
if (counter < ITERATION_NUMBER) counter <= counter + 1;
else counter <= 6'd0;
end
default: /* default */;
endcase
end
end
always @(posedge clk or negedge rst) begin : proc_t_i_j
if (~rst) begin
t_i_j <= 0;
end else begin
case (state)
IDLE: t_i_j <= 0;
CAL: t_i_j <= wire_t_i_j;
default: t_i_j <= 0;
endcase
end
end
always @(posedge clk or negedge rst) begin : proc_done
if (~rst) begin
done <= 0;
end else begin
case (state)
IDLE: done <= 0;
CAL: begin
if (counter < ITERATION_NUMBER) done <= 0;
else done <= 1'b1;
end
default: done <= 0;
endcase
end
end
always @(posedge clk or negedge rst) begin : proc_state
if (~rst) begin
state <= IDLE;
end else begin
case (state)
IDLE: begin : IDLE_STATE
if (start) state <= CAL;
else state <= state;
end
CAL: begin : CAL_STATE
if (counter < ITERATION_NUMBER) state <= CAL;
else state <= IDLE;
end
default: state <= IDLE;
endcase
end
end
endmodule
| 7.196913
|
module top_module (
input clk,
input reset, // Active-high synchronous reset to 32'h1
output [31:0] q
);
reg [31:0] d;
assign d[31:0] = {q[0], q[31:23], q[22] ^ q[0], q[21:3], q[2] ^ q[0], q[1] ^ q[0]};
always @(posedge clk) begin
if (reset) q <= 32'h1;
else q <= d;
end
endmodule
| 7.203305
|
module DataReg(Q,D,Le,Clk);
// BUS width
parameter DATA_WIDTH = 32;
// Outputs
output reg [DATA_WIDTH-1:0]Q;
// Inputs
input[DATA_WIDTH-1:0]D;
input Le,Clr,Clk;
always @ (posedge Clk,)
if (Le) Q <= D;
endmodule
| 7.028105
|
module kpg_init (
output reg out1,
out0,
input a,
b,
clk
);
always @(posedge clk)
case ({
a, b
})
2'b00: begin
out0 = 1'b0;
out1 = 1'b0;
end
2'b11: begin
out0 = 1'b1;
out1 = 1'b1;
end
default: begin
out0 = 1'b0;
out1 = 1'b1;
end
endcase
endmodule
| 6.603491
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.