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stringlengths 35
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float64 6.5
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module top_module (
input [3:1] y,
input w,
output Y2
);
always @(*) begin
case (y)
3'b010, 3'b100: Y2 = w;
3'b000, 3'b011: Y2 = 0;
default: Y2 = 1;
endcase
end
endmodule
| 7.203305
|
module top_module (
input [31:0] a,
input [31:0] b,
input sub,
output [31:0] sum
);
wire cout1, cout2;
wire [15:0] b_lo;
wire [15:0] b_hi;
wire [15:0] sum_lo;
wire [15:0] sum_hi;
always @(a or b or sub) begin
if (sub == 0) begin
b_lo = b[15:0];
b_hi = b[31:16];
end else begin
b_lo = {16{sub}} ^ b[15:0];
b_hi = {16{sub}} ^ b[31:16];
end
end
add16 u_add16_1 (
.a(a[15:0]),
.b(b_lo),
.cin(sub),
.sum(sum_lo),
.cout(cout1)
);
add16 u_add16_2 (
.a(a[31:16]),
.b(b_hi),
.cin(cout1),
.sum(sum_hi),
.cout(cout2)
);
assign sum = {sum_hi, sum_lo};
endmodule
| 7.203305
|
module CFIqueryModule (); //, isCFI);
//input isCFI;
reg [`BYTE_range] CFIarray[0:`CFI_dim];
reg error;
reg [8*30:1] CFI_file;
integer i;
initial begin
`ifdef x128P30T
CFI_file = "CFImemory_top.mem";
`elsif x128P30B
CFI_file = "CFImemory_bottom.mem";
`elsif x64P30T
CFI_file = "CFImemory64Mb_top.mem";
`elsif x64P30B
CFI_file = "CFImemory64Mb_bottom.mem";
`endif
for (i = 0; i <= `CFI_dim; i = i + 1) CFIarray[i] = {8{`HIGH}}; // CFI Memory Init
$readmemb(CFI_file, CFIarray);
end
always @(posedge error) begin
Kernel.SetWarning(`RCFI_cmd, 16'h00, `CFIAddrRange_msg);
error = `FALSE;
end
function [`WORD_range] Get;
input [`ADDRBUS_range] address;
begin
if (address[`BYTE_range] >= 9'h10 && address[`BYTE_range] <= `CFI_dim ) //verificare se tener conto che il primo indirizzo accessibile e' 10h
begin
if (address[`BYTE_range] >= 9'h39 && address[`BYTE_range] <= 9'h109) begin
Get = 8'hXX;
error = `TRUE;
end else begin
Get[`LOW_range] = CFIarray[address[`BYTE_range]];
Get[`HIGH_range] = 8'h00;
end
end else begin
Get = 8'hXX;
error = `TRUE;
end
end
endfunction
endmodule
| 6.718754
|
module Erase
// *********************
//
// Memory Manager :
// the memory array
//
// *********************
module MemoryModule(Info);
input Info;
reg [`WORD_range] memory [0:(`MEMORY_dim) - 1]; // the Memory: word organization
parameter FILENAME_MEM="";
initial begin
LoadMemory;
end
task LoadMemory; // Initialize and load the memory from a file
integer i;
integer fd, init_size;
begin
#0 if (Info) $display("[%t] Inizialize the Memory to default value",$time);
for (i = 0; i < `MEMORY_dim; i = i + 1) memory[i] = {16{`HIGH}}; // Memory Init
if (FILENAME_MEM !== "") begin
// $readmemb(FILENAME_MEM, memory);
fd = $fopen(FILENAME_MEM ,"rb");
if(fd)begin
if (Info) $display("[%t] Load Memory from file: %s",$time, FILENAME_MEM);
init_size = $fread(memory, fd) / 2;
$fclose(fd);
for (i = 0; i < init_size; i = i + 1)
memory[i] = {memory[i][0+:8],memory[i][8+:8]};
end
else begin
if (Info) $display("[%t] Warning: File: %s not found",$time, FILENAME_MEM);
end
end
end
endtask
function [`WORD_range] Get;
input [`ADDRBUS_range] address;
Get = memory[address];
endfunction
function IsSuspended;
input [`ADDRBUS_range] address;
IsSuspended = Program_man.IsAddrSuspended(address) || Erase_man.IsAddrSuspended(address) || ProgramBuffer_man.IsAddrSuspended(address);
endfunction
function IsBlockSuspended;
input [`ADDRBUS_range] address;
IsBlockSuspended = Program_man.IsBlockSuspended(address) || Erase_man.IsBlockSuspended(address);
endfunction
task Program;
input [`WORD_range] data;
input [`ADDRBUS_range] address;
output [`BYTE_range] Status;
begin
Status = `NoError_msg;
memory[address] = memory[address] & data;
if (memory[address] != data) Status = `PreProg_msg;
end
endtask
task EraseBlock;
input [`INTEGER] block;
output [`BYTE_range] ErrFlag;
reg [`ADDRBUS_range] start_address;
reg [`ADDRBUS_range] end_address;
reg [`ADDRBUS_range] address;
begin
ErrFlag = `NoError_msg;
start_address = BankLib_man.getBlockAddress(block);
end_address = BankLib_man.BlockBoundaryEndAddr[block];
if (start_address > end_address)
begin
address = start_address;
start_address = end_address;
end_address = address;
end
for (address = start_address; address <= end_address; address = address + 1)
memory[address] = `WORDNP;
end
endtask
task BlockBlankCheck;
input [`INTEGER] block;
output [`BYTE_range] ErrFlag;
reg [`ADDRBUS_range] start_address;
reg [`ADDRBUS_range] end_address;
reg [`ADDRBUS_range] address;
begin
ErrFlag = `NoError_msg;
start_address = BankLib_man.BlockBoundaryStartAddr[block];
end_address = BankLib_man.BlockBoundaryEndAddr[block];
if (start_address > end_address)
begin
address = start_address;
start_address = end_address;
end_address = address;
end
ErrFlag = `NoError_msg;
address = start_address;
while (memory[address] == `WORDNP && address <= end_address )
address = address + 1;
if (memory[address] != `WORDNP)
ErrFlag = `BlankCheckFailed_msg;
end
endtask
endmodule
| 7.196549
|
module OutputBufferModule (
DataInput,
DataInputBurst,
DataOutput,
OutputEnable
);
input [`WORD_range] DataInput;
input [`WORD_range] DataInputBurst;
output [`WORD_range] DataOutput;
input OutputEnable;
reg [`WORD_range] DataOutput;
time timeDataV, timeDataX, timeDataZ;
initial begin
timeDataV = 0;
timeDataX = 0;
timeDataZ = 0;
SetZ(0);
end
task SetValid;
input [63:0] delayTime;
begin
if ((delayTime + $time > timeDataV) || (timeDataV < $time)) begin
timeDataV = delayTime + $time;
disable waitValid;
disable goValid;
end
end
endtask
always
fork
begin : goValid
#(timeDataV - $time)
if (OutputEnable == 1'b0) begin
if (ConfigReg_man.isASynchronous) DataOutput = DataInput;
else DataOutput = DataInputBurst;
end
end // goValid
begin : waitValid
wait (`FALSE);
end
join
task SetX;
input [63:0] delayTime;
begin
if ((delayTime + $time < timeDataX) || (timeDataX < $time)) begin
timeDataX = delayTime + $time;
disable waitX;
end
end
endtask
always
fork
begin : goX
#(timeDataX - $time)
if ((OutputEnable == `LOW) || (timeDataZ > timeDataX))
DataOutput = 16'hX;
end // goX
begin : waitX
wait (`FALSE);
end
join
task SetZ;
input [63:0] delayTime;
begin
if ((delayTime + $time < timeDataZ) || (timeDataZ < $time)) begin
timeDataZ = delayTime + $time;
disable waitZ;
if (timeDataZ < timeDataV) disable goValid;
if (timeDataZ < timeDataX) disable goX;
end
end
endtask
always begin : waitZ
#(timeDataZ - $time) DataOutput = 16'hZ;
wait (`FALSE);
end
endmodule
| 6.818094
|
module ReadModule (
dataOutput,
address,
voltOK,
Info
);
output [`WORD_range] dataOutput;
input [`ADDRBUS_range] address;
input voltOK;
input Info;
reg [`WORD_range] dataOutput, regRead;
reg [1:0] Mode, oldMode;
reg [`BYTE_range] Status;
integer i;
initial begin
regRead = 0;
Mode = `ReadArray_bus;
oldMode = `ReadArray_bus;
dataOutput = `DATABUS_dim'hzzzz;
end
task SetMode;
input [1:0] newMode;
output [`BYTE_range] Status;
begin
Status = `NoError_msg;
if (Info && (newMode != Mode)) begin
case (newMode)
`ReadArray_bus: $display("[%t] Device now in Read Array mode ", $time);
`ReadCFI_bus: $display("[%t] Device now in Read CFI mode ", $time);
`ReadSignature_bus:
$display("[%t] Device now in Read Electronic Signature Mode ", $time);
`ReadStatusReg_bus: $display("[%t] Device now in Read Status Register Mode ", $time);
default: $display("[%t] !!!Model Error: Read mode not recognized!!!", $time);
endcase
oldMode = Mode;
Mode = newMode;
end
end
endtask
always @Kernel.ResetEvent begin
Mode = `ReadArray_bus;
end
always @(negedge Kernel.Ready) begin // Configure according to status register
Mode = `ReadStatusReg_bus;
end
always @Kernel.ReadEvent begin // Main execution of a read is based on an event
case (Mode)
`ReadArray_bus: begin
dataOutput = Memory_man.Get(address);
if (Info) $display("[%t] Data Read result: memory[%h]=%h", $time, address, dataOutput);
end
`ReadCFI_bus: begin
dataOutput = CFIquery_man.Get(address);
if (Info) $display("[%t] Data Read result: CFI_memory[%h]=%h", $time, address, dataOutput);
end
`ReadSignature_bus: begin
dataOutput = Signature_man.Get(address);
if (Info) $display("[%t] Read Device Identifier(addr=%h) :%h", $time, address, dataOutput);
end
`ReadStatusReg_bus: begin
dataOutput = SR_man.SR;
if (Info) $display("[%t] Read Status Register: %b", $time, dataOutput[`BYTE_range]);
end
default: $display("[%t] !!!Model Error: Read mode not recognized!!!", $time);
endcase
if ((Mode == `ReadArray_bus) && (Memory_man.IsSuspended(address) == `TRUE)) begin
dataOutput = 16'hXX;
Kernel.SetWarning(`RD_cmd, 8'hXX, `SuspAcc_msg);
end
end
endmodule
| 6.789247
|
module BlankCheckModule(address, data, progVoltOK, progHighVoltOK,Info);
input [`WORD_range] data;
input [`ADDRBUS_range] address;
input progVoltOK, progHighVoltOK;
input Info;
event ErrorCheckEvent, CompleteEvent;
reg [`BYTE_range] Status;
reg [`ADDRBUS_range] hold_address;
reg [`BLOCKADDR_range] hold_block;
reg Busy;
integer i;
time startTime, delayTime, Erase_time;
initial begin // constructor sequence
Busy = `FALSE;
Erase_time = `MainBlockErase_time; //modificato
delayTime = Erase_time;
end
always @(progVoltOK,progHighVoltOK,address) begin
if (progHighVoltOK)
if (BankLib_man.isMainBlock(address)) Erase_time=`FastMainBlockErase_time;
else Erase_time=`FastParameterBlockErase_time;
else
if (BankLib_man.isMainBlock(address)) Erase_time=`MainBlockErase_time;
else Erase_time=`ParameterBlockErase_time;
end
function IsBusy; // boolean function primitive
input obbl; // all functions require a parameter
IsBusy = Busy; // return Boolean value
endfunction
// *********************
//
// Task checkConfirm :
// check confirm code
//
// *********************
task checkConfirm;
output [`BYTE_range] outStatus;
reg [`BYTE_range] outStatus;
begin
if (data == `BLNKCHKconfirm_cmd) outStatus = `NoError_msg;
else outStatus = `WrongBlankCheckConfirm_msg;
end
endtask
// ****************
//
// Task Blank Check
//
// ****************
task BlankCheck;
output [`BYTE_range] outStatus;
reg [`BYTE_range] outStatus;
integer hold_block;
reg [`ADDRBUS_range] hold_address;
begin
hold_address = address;
hold_block = BankLib_man.getBlock(hold_address);
if (BankLib_man.isMainBlock(address)) begin
// Main Block
delayTime = `MainBlankCheck_time;
end else // Parameter Block
-> ErrorCheckEvent;
disable Operation;
fork
begin: Operation
Busy = `TRUE;
startTime = $time;
-> ErrorCheckEvent;
#delayTime
Memory_man.BlockBlankCheck(hold_block, Status);
-> CompleteEvent;
end
@CompleteEvent
disable Operation;
join
outStatus = Status;
Busy = `FALSE;
end
endtask
always @(ErrorCheckEvent) begin
Status = `NoError_msg;
if (!progVoltOK)
Status = `InvVDD_msg;
if (BankLib_man.isParameterBlock(address)) begin
Status = `WrongBlankCheckBlock;
$display("parameter block");
end
if (Status != `NoError_msg) begin
->CompleteEvent;
disable ErrorCheck;
end
else
fork : ErrorCheck
@(negedge progVoltOK) Status = `InvVDD_msg;
@(Status) -> CompleteEvent;
@(CompleteEvent) disable ErrorCheck;
join
end
endmodule
| 6.629661
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = ((!load) || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = ('0 || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = ('1 || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || (!store));
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || '0);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || '1);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load && store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module top_module (
input [6:1] y,
input w,
output Y2,
output Y4
);
assign Y2 = y[1] && (~w);
assign Y4 = (y[2] || y[3] || y[5] || y[6]) && w;
endmodule
| 7.203305
|
module top_module (
input a,
input b,
output wire out_assign,
output reg out_alwaysblock
);
assign out_assign = a & b;
always @(*) begin
out_alwaysblock = a & b;
end
endmodule
| 7.203305
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (~(opcode == 'b01));
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = '0;
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = '1;
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module key_scan (
clk,
rst_n,
col,
row,
key_out
);
input clk; //10KHz
input rst_n;
input [3:0] col;
output reg [3:0] row;
output reg [15:0] key_out;
parameter s1 = 2'b00, s2 = 2'b01, s3 = 2'b10, s4 = 2'b11;
reg [1:0] state;
reg clk_200hz;
reg [4:0] cnt;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
cnt <= 5'd0;
clk_200hz = 1'b0;
end else begin
if (cnt == 25) begin
cnt <= 5'd0;
clk_200hz <= ~clk_200hz;
end else begin
cnt <= cnt + 1'b1;
clk_200hz <= clk_200hz;
end
end
end
always @(posedge clk_200hz or negedge rst_n) begin
if (!rst_n) begin
state <= s1;
row <= 4'b1111;
end else begin
case (state)
s1: begin
state <= s2;
row <= 4'b1101;
end
s2: begin
state <= s3;
row <= 4'b1011;
end
s3: begin
state <= s4;
row <= 4'b0111;
end
s4: begin
state <= s1;
row <= 4'b1110;
end
default: state <= s2;
endcase
end
end
always @(posedge clk_200hz or negedge rst_n) begin
if (!rst_n) begin
key_out <= 16'hffff;
end else begin
case (state)
s1: key_out[3:0] <= col ^ key_out[3:0]; //filter
s2: key_out[7:4] <= col ^ key_out[7:4];
s3: key_out[11:8] <= col ^ key_out[11:8];
s4: key_out[15:12] <= col ^ key_out[15:12];
endcase
end
end
endmodule
| 6.821826
|
module top_module (
input clk,
input reset, // synchronous reset
input w,
output z
);
parameter A = 3'b000;
parameter B = 3'b001;
parameter C = 3'b010;
parameter D = 3'b011;
parameter E = 3'b100;
parameter F = 3'b101;
reg [2:0] cstate, nstate;
always @(posedge clk) begin
if (reset) begin
cstate <= A;
end else begin
cstate <= nstate;
end
end
always @(*) begin
case (cstate)
A: nstate = w ? A : B;
B: nstate = w ? D : C;
C: nstate = w ? D : E;
D: nstate = w ? A : F;
E: nstate = w ? D : E;
F: nstate = w ? D : C;
endcase
end
assign z = (cstate == E || cstate == F);
endmodule
| 7.203305
|
module decoder (
a,
y
);
input [1:0] a;
output [3:0] y;
reg [3:0] y = 4'b1111;
always @(a)
case (a)
2'b00: y = 4'b1110;
2'b01: y = 4'b1101;
2'b10: y = 4'b1011;
2'b11: y = 4'b0111;
endcase
endmodule
| 7.018254
|
module test;
wire [3:0] y;
reg [1:0] a = 2'b00;
decoder d1 (
a,
y
);
initial begin
$dumpfile("2a_decoder_test.vcd");
$dumpvars(0, test);
#5 a = 2'b01;
#5 a = 2'b10;
#5 a = 2'b11;
#5 $finish;
end
always @(a) $strobe("At time = (%0t) a = (%b),y = (%b)", $time, a, y);
endmodule
| 6.964054
|
module AND (
a,
b,
y
);
input a, b;
output y;
assign y = a & b;
endmodule
| 7.053445
|
module OR (
a,
b,
y
);
input a, b;
output y;
assign y = a | b;
endmodule
| 7.086775
|
module NOR (
a,
b,
y
);
input a, b;
output y;
assign y = ~(a | b);
endmodule
| 7.611112
|
module XOR (
a,
b,
y
);
input a, b;
output y;
assign y = (a ^ b);
endmodule
| 7.915029
|
module NOT (
a,
b
);
output b;
input a;
assign b = !a;
endmodule
| 7.483426
|
module comp (
input [6:0] A,
input [6:0] B,
output reg Q
);
wire [6:0] temp1;
wire [6:0] temp2;
//XOR x1(.A(A[7]),.B(B[7]),.Q(temp));
assign temp1[0] = A[0];
assign temp1[1] = A[1];
assign temp1[2] = A[2];
assign temp1[3] = A[3];
assign temp1[4] = A[4];
assign temp1[5] = A[5];
assign temp1[6] = A[6];
assign temp2[0] = B[0];
assign temp2[1] = B[1];
assign temp2[2] = B[2];
assign temp2[3] = B[3];
assign temp2[4] = B[4];
assign temp2[5] = B[5];
assign temp2[6] = B[6];
always @(A or B) begin
if (temp1 > temp2) begin
Q = 1;
end else begin
Q = 0;
end
end
endmodule
| 6.601597
|
module p_node (
input [7:0] LLR_C,
input [7:0] LLR_D,
input frozen1,
input frozen2,
output u2i_1,
output u2i
);
wire h, i, j, k, l, m, n, comp, o, p, q, r, s, t, u;
signum S1 (
.A(LLR_C),
.Q(h)
);
signum S2 (
.A(LLR_D),
.Q(i)
);
XOR X1 (
.a(h),
.b(i),
.y(j)
);
NOT N1 (
.a(frozen1),
.b(k)
);
AND A1 (
.a(k),
.b(j),
.y(u2i_1)
);
comp C1 (
.A(LLR_C),
.B(LLR_D),
.Q(comp)
);
NOT N2 (
.a(frozen2),
.b(l)
);
NOT N3 (
.a(comp),
.b(m)
);
AND A2 (
.a(comp),
.b(l),
.y(n)
);
AND A3 (
.a(l),
.b(m),
.y(o)
);
AND A4 (
.a(i),
.b(n),
.y(p)
);
AND A5 (
.a(frozen1),
.b(h),
.y(q)
);
AND A6 (
.a(i),
.b(k),
.y(r)
);
AND A7 (
.a(n),
.b(q),
.y(s)
);
AND A8 (
.a(r),
.b(n),
.y(t)
);
OR O1 (
.a(s),
.b(t),
.y(u)
);
OR O2 (
.a(u),
.b(p),
.y(u2i)
);
endmodule
| 7.849494
|
module Half_adder (
input p,
input q,
output S,
output C
);
assign C = p & q;
assign S = p ^ q;
endmodule
| 7.033118
|
module Full_adder (
input IN,
input IN2,
input Cin,
output R,
output Cout
);
wire x1;
wire y1;
wire z;
Half_adder Ha1 (
.p(IN),
.q(IN2),
.S(x1),
.C(y1)
);
Half_adder Ha2 (
.p(x1),
.q(Cin),
.S(R),
.C(z)
);
assign Cout = y1 | z;
endmodule
| 7.225676
|
module Adder (
input [7:0] A,
input [7:0] B,
output [9:0] Q
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
Full_adder Fa0 (
.IN(A[0]),
.IN2(B[0]),
.Cin(0),
.R(Q[0]),
.Cout(w0)
);
Full_adder Fa1 (
.IN(A[1]),
.IN2(B[1]),
.Cin(w0),
.R(Q[1]),
.Cout(w1)
);
Full_adder Fa2 (
.IN(A[2]),
.IN2(B[2]),
.Cin(w1),
.R(Q[2]),
.Cout(w2)
);
Full_adder Fa3 (
.IN(A[3]),
.IN2(B[3]),
.Cin(w2),
.R(Q[3]),
.Cout(w3)
);
Full_adder Fa4 (
.IN(A[4]),
.IN2(B[4]),
.Cin(w3),
.R(Q[4]),
.Cout(w4)
);
Full_adder Fa5 (
.IN(A[5]),
.IN2(B[5]),
.Cin(w4),
.R(Q[5]),
.Cout(w5)
);
Full_adder Fa6 (
.IN(A[6]),
.IN2(B[6]),
.Cin(w5),
.R(Q[6]),
.Cout(w6)
);
Full_adder Fa7 (
.IN(A[7]),
.IN2(B[7]),
.Cin(w6),
.R(Q[7]),
.Cout(Q[8])
);
assign Q[9] = 0;
endmodule
| 7.642138
|
module Subtracter (
input [7:0] A,
input [7:0] B,
output [9:0] Q
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
wire w7;
Full_adder Fa0 (
.IN(A[0]),
.IN2(~B[0]),
.Cin(1),
.R(Q[0]),
.Cout(w0)
);
Full_adder Fa1 (
.IN(A[1]),
.IN2(~B[1]),
.Cin(w0),
.R(Q[1]),
.Cout(w1)
);
Full_adder Fa2 (
.IN(A[2]),
.IN2(~B[2]),
.Cin(w1),
.R(Q[2]),
.Cout(w2)
);
Full_adder Fa3 (
.IN(A[3]),
.IN2(~B[3]),
.Cin(w2),
.R(Q[3]),
.Cout(w3)
);
Full_adder Fa4 (
.IN(A[4]),
.IN2(~B[4]),
.Cin(w3),
.R(Q[4]),
.Cout(w4)
);
Full_adder Fa5 (
.IN(A[5]),
.IN2(~B[5]),
.Cin(w4),
.R(Q[5]),
.Cout(w5)
);
Full_adder Fa6 (
.IN(A[6]),
.IN2(~B[6]),
.Cin(w5),
.R(Q[6]),
.Cout(w6)
);
Full_adder Fa7 (
.IN(A[7]),
.IN2(~B[7]),
.Cin(w6),
.R(Q[7]),
.Cout(w7)
);
Full_adder Fa8 (
.IN(0),
.IN2(1),
.Cin(w7),
.R(Q[8]),
.Cout(Q[9])
);
assign Q[9] = 0;
endmodule
| 6.986633
|
module FA_2 (
input [1:0] A,
input [1:0] B,
output [2:0] O
);
wire [2:0] Cout;
wire [1:0] S;
assign Cout[0] = 1'b0;
FA FA1 (
.A(A[0]),
.B(B[0]),
.Cin(Cout[0]),
.S(S[0]),
.Cout(Cout[1])
);
FA FA2 (
.A(A[1]),
.B(B[1]),
.Cin(Cout[1]),
.S(S[1]),
.Cout(Cout[2])
);
assign O = {Cout[2], S};
endmodule
| 7.130943
|
module gr (
input wire [1:0] num0,
num1,
output wire gr
);
// signal declaration
wire p0, p1, p2;
// body - includes the logical expressions used and the final SOP form to achieve the desired result
assign gr = p0 | p1 | p2; // gr = p0 + p1 + p2
// = (A1.~B1) + (A0.~B1.~B0) + (A1.A0.~B0)
assign p0 = (num0[1] & ~num1[1]); // p0 = A1.~B1
assign p1 = (num0[0] & ~num1[1] & ~num1[0]); // p1 = A0.~B1.~B0
assign p2 = (num0[1] & num0[0] & ~num1[0]); // p2 = A1.A0.~B0
endmodule
| 7.314663
|
module bit2_less_than (
input wire [1:0] a,
b, // a and b are the two 2-bit numbers to compare
output wire alessb
);
wire aeqb;
wire agrb;
// body
// instantiate the result from the SOP of both
// 2 bit greater than comparator and
// 2 bit equality comparator
// and OR them to get the final result that is
// 2 bit greater than AND equals circuit
eq eq_calc (
.num0(a),
.num1(b),
.eq (aeqb)
); // 2 bit equality comparator
gr gr_calc (
.num0(a),
.num1(b),
.gr (agrb)
); // 2 bit greater than comparator
wire agreqb = aeqb | agrb;
//negating the result to get the less than result
assign alessb = !agreqb;
endmodule
| 6.705786
|
module encoder_8to3 (
a,
y
);
input [7:0] a;
output [2:0] y;
reg [2:0] y;
always @(a) begin
if (a == 8'b00000001) y = 3'b000;
else if (a == 8'b00000010) y = 3'b001;
else if (a == 8'b00000100) y = 3'b010;
else if (a == 8'b00001000) y = 3'b011;
else if (a == 8'b00010000) y = 3'b100;
else if (a == 8'b00100000) y = 3'b101;
else if (a == 8'b01000000) y = 3'b110;
else if (a == 8'b10000000) y = 3'b111;
else y = 3'bx;
end
endmodule
| 7.526774
|
module test;
wire [2:0] y;
reg [7:0] a;
encoder_8to3 e1 (
a,
y
);
initial begin
$dumpfile("2b_encoder_8to3_test.vcd");
$dumpvars(0, test);
#5 a = 8'b00000001;
#5 a = 8'b00000010;
#5 a = 8'b00000100;
#5 a = 8'b00001000;
#5 a = 8'b00010000;
#5 a = 8'b00100000;
#5 a = 8'b01000000;
#5 a = 8'b10000000;
#5 $finish;
end
always @(a) $strobe("At time = (%0t) a = (%b),y = (%b)", $time, a, y);
endmodule
| 6.964054
|
module fulladder (
a,
b,
c,
carry,
sum
);
input a, b, c;
output carry, sum;
assign carry = a & b | a & c | b & c;
assign sum = a ^ b ^ c;
endmodule
| 7.454465
|
module encoder_8to3 (
a,
y
);
input [7:0] a;
output [2:0] y;
reg [2:0] y;
always @(a) begin
case (a)
8'b00000001: y = 3'b000;
8'b0000001x: y = 3'b001;
8'b000001xx: y = 3'b010;
8'b00001xxx: y = 3'b011;
8'b0001xxxx: y = 3'b100;
8'b001xxxxx: y = 3'b101;
8'b01xxxxxx: y = 3'b110;
8'b1xxxxxxx: y = 3'b111;
default: y = 3'bx;
endcase
end
endmodule
| 7.526774
|
module test;
wire [2:0] y;
reg [7:0] a;
encoder_8to3 e1 (
a,
y
);
initial begin
$dumpfile("2c_priorityencoder_8to3_test.vcd");
$dumpvars(0, test);
#5 a = 8'b00000001;
#5 a = 8'b0000001x;
#5 a = 8'b000001xx;
#5 a = 8'b00001xxx;
#5 a = 8'b0001xxxx;
#5 a = 8'b001xxxxx;
#5 a = 8'b01xxxxxx;
#5 a = 8'b1xxxxxxx;
#5 $finish;
end
always @(a) $strobe("At time = (%0t) a = (%b),y = (%b)", $time, a, y);
endmodule
| 6.964054
|
module test;
wire a;
reg [7:0] y = 8'd82;
reg [2:0] sel;
multiplexer_8to1 m1 (
a,
sel,
y
);
initial begin
$dumpfile("2d_multiplexer_8to1_test.vcd");
$dumpvars(0, test);
#5 sel = 3'b000;
#5 sel = 3'b001;
#5 sel = 3'b010;
#5 sel = 3'b011;
#5 sel = 3'b100;
#5 sel = 3'b101;
#5 sel = 3'b110;
#5 sel = 3'b111;
#5 $finish;
end
always @(a, sel) $strobe("At time = (%0t) sel = (%b),y = (%b),a = (%b)", $time, sel, y, a);
endmodule
| 6.964054
|
module test;
wire [3:0] y;
reg [3:0] a;
bintograyconv4bit bg1 (
a,
y
);
initial begin
$dumpfile("2e_4bit_binarytograyconverter.vcd");
$dumpvars(0, test);
#5 a = 4'd0;
#5 a = 4'd1;
#5 a = 4'd2;
#5 a = 4'd3;
#5 a = 4'd4;
#5 a = 4'd5;
#5 a = 4'd6;
#5 a = 4'd7;
#5 a = 4'd8;
#5 a = 4'd9;
#5 a = 4'd10;
#5 a = 4'd11;
#5 a = 4'd12;
#5 a = 4'd13;
#5 a = 4'd14;
#5 a = 4'd15;
#5 $finish;
end
always @(a) $strobe("At time = (%0t) a = (%b),y = (%b)", $time, a, y);
endmodule
| 6.964054
|
module test;
wire [7:0] y;
reg a = 1'b1;
reg [2:0] sel;
demultiplexer1to8 d1 (
a,
sel,
y
);
initial begin
$dumpfile("2f_demultiplexer_1to8.vcd");
$dumpvars(0, test);
#5 sel = 3'd0;
#5 sel = 3'd1;
#5 sel = 3'd2;
#5 sel = 3'd3;
#5 sel = 3'd4;
#5 sel = 3'd5;
#5 sel = 3'd6;
#5 sel = 3'd7;
#5 $finish;
end
always @(a, sel) $strobe("At time = (%0t),a = (%b),sel = (%b),y = (%b)", $time, a, sel, y);
endmodule
| 6.964054
|
module test;
wire l, e, g;
reg [3:0] a;
reg [3:0] b;
comparator c1 (
a,
b,
l,
e,
g
);
initial begin
$dumpfile("2g_comparator.vcd");
$dumpvars(0, test);
#5 begin
a = 4'b1111;
b = 4'b1100;
end
#5 begin
a = 4'b1111;
b = 4'b1111;
end
#5 begin
a = 4'b0000;
b = 4'b1111;
end
#5 $finish;
end
always @(a, b)
$strobe(
"At time = (%0t),a = (%b),b = (%b),l = (%b),e = (%b),g = (%b)", $time, a, b, l, e, g
);
endmodule
| 6.964054
|
module mux2 (
in0,
in1,
select,
out
);
input in0, in1, select;
output out;
wire s0, w0, w1;
not n1 (s0, select);
and a1 (w0, s0, in0);
and a2 (w1, select, in1);
or g3 (out, w0, w1);
endmodule
| 7.816424
|
module tb_mux;
// Declaring Inputs
reg Data_in_0;
reg Data_in_1;
reg sel;
// Declaring Outputs
wire Data_out;
// Instantiate the Unit Under Test (UUT)
mux2 uut (
.in0(Data_in_0),
.in1(Data_in_1),
.select(sel),
.out(Data_out)
);
initial begin
//for creating vcd waveform file to view in gtkwave
$dumpfile("mux_out.vcd");
$dumpvars(0, tb_mux);
// Apply Inputs
Data_in_0 = 0;
Data_in_1 = 0;
sel = 0;
// Wait 100 ns
#100;
//Similarly apply Inputs and wait for 100 ns
Data_in_0 = 0;
Data_in_1 = 0;
sel = 1;
#10;
Data_in_0 = 0;
Data_in_1 = 1;
sel = 0;
#10;
Data_in_0 = 0;
Data_in_1 = 1;
sel = 1;
#10;
Data_in_0 = 1;
Data_in_1 = 0;
sel = 0;
#50;
Data_in_0 = 1;
Data_in_1 = 0;
sel = 1;
#10;
Data_in_0 = 1;
Data_in_1 = 1;
sel = 0;
#10;
Data_in_0 = 1;
Data_in_1 = 1;
sel = 1;
#10;
end
endmodule
| 7.600974
|
module mux1_2_4 (
A,
B,
sel,
Y
);
input [3:0] A;
input [3:0] B;
input sel;
output reg [3:0] Y;
always @(A, B, sel) begin
Y <= sel ? A : B;
end
endmodule
| 6.8861
|
module Second_register (
input [31:0] PCD,
input [31:0] ImmExtD,
input [31:0] PCPlus4D,
input [31:0] RD1,
input [31:0] RD2,
input [ 4:0] RdD,
input [ 4:0] Rs1D,
input [ 4:0] Rs2D,
input [ 2:0] funct3,
input rst,
input clk,
input RegWriteD,
input MemWriteD,
input JumpD,
input BranchD,
input ALUSrcD,
input ZeroE,
input FlushE,
input [ 1:0] ResultSrcD,
input [ 4:0] ALUControlD,
output reg RegWriteE,
output reg MemWriteE,
output reg JumpE,
output reg BranchE,
output reg ALUSrcE,
output reg PCSrcE,
output reg [ 1:0] ResultSrcE,
output reg [ 4:0] ALUControlE,
output reg [31:0] PCE,
output reg [31:0] ImmExtE,
output reg [31:0] PCPlus4E,
output reg [31:0] RD1E,
output reg [31:0] RD2E,
output reg [ 2:0] funct3E,
output reg [ 4:0] RdE,
output reg [ 4:0] Rs1E,
output reg [ 4:0] Rs2E
);
always @(posedge clk) begin
if (rst) begin
RegWriteE <= 0;
MemWriteE <= 0;
JumpE <= 0;
BranchE <= 0;
ALUSrcE <= 0;
ResultSrcE <= 2'b00;
ALUControlE <= 5'b00000;
PCE <= 32'd0;
ImmExtE <= 32'd0;
PCPlus4E <= 32'd0;
RD1E <= 32'd0;
RD2E <= 32'd0;
funct3E <= 3'd0;
RdE <= 5'd0;
Rs1E <= 5'd0;
Rs2E <= 5'd0;
end else if (FlushE) begin
RegWriteE <= 0;
MemWriteE <= 0;
JumpE <= 0;
BranchE <= 0;
ALUSrcE <= 0;
ResultSrcE <= 2'b00;
ALUControlE <= 5'b00000;
PCE <= 32'd0;
ImmExtE <= 32'd0;
PCPlus4E <= 32'd0;
RD1E <= 32'd0;
RD2E <= 32'd0;
funct3E <= 3'd0;
RdE <= 5'd0;
Rs1E <= 5'd0;
Rs2E <= 5'd0;
end else begin
RegWriteE <= RegWriteD;
MemWriteE <= MemWriteD;
JumpE <= JumpD;
BranchE <= BranchD;
ALUSrcE <= ALUSrcD;
ResultSrcE <= ResultSrcD;
ALUControlE <= ALUControlD;
PCE <= PCD;
ImmExtE <= ImmExtD;
PCPlus4E <= PCPlus4D;
RD1E <= RD1;
RD2E <= RD2;
funct3E <= funct3;
RdE <= RdD;
Rs1E <= Rs1D;
Rs2E <= Rs2D;
end
end
always @(*) begin //this is a combinational block, so block assignment should be used
PCSrcE = (ZeroE && BranchE) || JumpE;
end
endmodule
| 7.65325
|
module iob_2p_mem_tiled #(
parameter DATA_W = 32, // data width
parameter N_WORDS = 8192, // number of words (each word has 'DATA_W/8' bytes)
parameter ADDR_W = $clog2(N_WORDS * DATA_W / 8.0), // address width
parameter TILE_ADDR_W = 11, // log2 of block size
parameter USE_RAM = 0
) (
// Inputs
input clk,
input w_en,
input r_en,
input [DATA_W-1:0] data_in, // input data to write port
input [ADDR_W-1:0] addr, // address for write/read port
// Outputs
output reg [DATA_W-1:0] data_out //output port
);
// Number of BRAMs to generate, each containing 2048 bytes maximum
localparam K = $ceil(2 ** (ADDR_W - TILE_ADDR_W)); // 2**11 == 2048
// Address decoder: enables write on selected BRAM
wire [K-1:0] addr_en; // address decoder output
decN #(
.N_OUTPUTS(K)
) addr_dec (
.dec_in (addr[ADDR_W-1:ADDR_W-$clog2(K)]), // only the first clog2(K) MSBs select the BRAM
.dec_out(addr_en)
);
// Generate K BRAMs
genvar i;
generate
// Vector containing all BRAM outputs
wire [DATA_W-1:0] data_out_vec[K-1:0];
for (i = 0; i < K; i = i + 1) begin
iob_2p_mem #(
.DATA_W (DATA_W),
.ADDR_W (ADDR_W - $clog2(K)),
.USE_RAM(USE_RAM)
) bram (
.clk(clk),
.w_en(w_en & addr_en[i]),
.r_en(r_en & addr_en[i]),
.data_in(data_in),
.w_addr(addr[ADDR_W-$clog2(K)-1:0]),
.r_addr(addr[ADDR_W-$clog2(K)-1:0]),
.data_out(data_out_vec[i])
);
end
endgenerate
// bram mux: outputs selected BRAM
muxN #(
.N_INPUTS(K),
.INPUT_W (DATA_W)
) bram_out_sel (
.data_in(data_out_vec),
.sel(addr[ADDR_W-1:ADDR_W-$clog2(K)]),
.data_out(data_out)
);
endmodule
| 6.757707
|
module decN #(
parameter N_OUTPUTS = 16
) (
input [$clog2(N_OUTPUTS)-1:0] dec_in,
output reg [N_OUTPUTS-1:0] dec_out
);
always @* begin
dec_out = 0;
dec_out[dec_in] = 1'b1;
end
endmodule
| 6.877415
|
module muxN #(
parameter N_INPUTS = 4, // number of inputs
parameter INPUT_W = 8, // input bit width
parameter S = $clog2(N_INPUTS), // number of select lines
parameter W = N_INPUTS * INPUT_W // total data width
) (
// Inputs
input [INPUT_W-1:0] data_in[N_INPUTS-1:0], // input port
input [ S-1:0] sel, // selection port
// Outputs
output reg [INPUT_W-1:0] data_out // output port
);
always @* begin
data_out = data_in[sel];
end
endmodule
| 8.176797
|
module iob_2p_mem_tiled_tb;
// Inputs
reg clk;
reg w_en;
reg r_en;
reg [`DATA_W-1:0] data_in;
reg [`ADDR_W-1:0] addr;
// Outputs
wire [`DATA_W-1:0] data_out;
integer i, seq_ini;
integer test, base_block;
parameter clk_per = 10; // clk period = 10 timeticks
// Instantiate the Unit Under Test (UUT)
iob_2p_mem_tiled #(
.DATA_W(`DATA_W),
.N_WORDS(`N_WORDS),
.USE_RAM(`USE_RAM),
.TILE_ADDR_W(`TILE_ADDR_W)
) uut (
.clk(clk),
.w_en(w_en),
.r_en(r_en),
.data_in(data_in),
.addr(addr),
.data_out(data_out)
);
// system clock
always #(clk_per / 2) clk = ~clk;
initial begin
// Initialize Inputs
clk = 1;
addr = 0;
w_en = 0;
r_en = 0;
data_in = 0;
// Number from which to start the incremental sequence to write into the RAM
seq_ini = 32;
// optional VCD
`ifdef VCD
if (`USE_RAM == 1) begin
$dumpfile("tiled_ram.vcd");
$dumpvars();
end
if (`USE_RAM == 0) begin
$dumpfile("tiled.vcd");
$dumpvars();
end
`endif
@(posedge clk) #1;
w_en = 1;
//Write all the locations of RAM
for (i = 0; i < 16; i = i + 1) begin
data_in = i + 32;
addr = i;
@(posedge clk) #1;
end
w_en = 0;
@(posedge clk) #1;
//Read all the locations of RAM with r_en = 0
r_en = 0;
@(posedge clk) #1;
if (`USE_RAM == 1) begin
for (i = 0; i < 16; i = i + 1) begin
addr = i;
@(posedge clk) #1;
if (data_out != 0) begin
$display("Test 1 failed: with r_en = 0, at position %0d, data_out should be 0 but is %d",
i, data_out);
$finish;
end
end
end
r_en = 1;
@(posedge clk) #1;
//Read all the locations of RAM with r_en = 1
for (i = 0; i < 16; i = i + 1) begin
addr = i;
@(posedge clk) #1;
if (data_out != i + 32) begin
$display("Test 2 failed: on position %0d, data_out is %d where it should be %0d", i,
data_out, i + 32);
$finish;
end
end
r_en = 0;
#(5 * clk_per);
$display("%c[1;34m", 27);
$display("Test completed successfully.");
$display("%c[0m", 27);
$finish;
end
endmodule
| 6.757707
|
module comp (
input [31:0] inp,
output [31:0] out
);
wire [31:0] o1;
wire carry;
assign o1[31:0] = ~(inp[31:0]);
thirtytwoBitAdder a1 (
o1,
32'd1,
1'b0,
out,
carry
);
endmodule
| 6.601597
|
module pipe_2stage_data (
out,
in,
clk
);
input [29:0] in;
input clk;
output reg [29:0] out;
reg [29:0] pipe1, pipe2, pipe3, pipe4;
always @(posedge clk) begin
pipe1 <= in;
pipe2 <= pipe1;
pipe3 <= pipe2;
pipe4 <= pipe3;
out <= pipe4;
end
endmodule
| 6.738391
|
module simon2share (
clk,
data_ina,
data_inb,
data_rdy,
cipher_out,
Done,
Trig
);
input clk;
input data_ina, data_inb;
input [1:0] data_rdy;
output [127:0] cipher_out;
output reg Done, Trig;
reg [7:0] counter;
wire [63:0] keya, keyb;
always @(posedge clk) begin
if (data_rdy == 0) begin
counter <= 0;
end else if (data_rdy == 3) begin
counter <= counter + 1;
end
end
always @(posedge clk) begin
if (counter == 1) //So it means first 1 rounds
Trig <= 1;
else Trig <= 0;
if (data_rdy == 3 && (counter == 134)) Done <= 1;
else Done <= 0;
end
p_datapath mydatapath (
.clk(clk),
.counter(counter),
.data_ina(data_ina),
.data_inb(data_inb),
.data_rdy(data_rdy),
.key_ina(keya),
.key_inb(keyb),
.cipher_out(cipher_out)
);
p_keysch10 mykeysch_a (
.clk(clk),
.counter(counter),
.data_in(data_ina),
.data_rdy(data_rdy),
.key_out(keya)
);
p_keysch11 mykeysch_b (
.clk(clk),
.counter(counter),
.data_in(data_inb),
.data_rdy(data_rdy),
.key_out(keyb)
);
endmodule
| 6.990502
|
module data_share2 (
clk,
data_rdy,
counter,
data_in,
key_in,
X_out,
Y_out,
Y_in
);
input clk, counter, data_in;
input [63:0] key_in;
input [1:0] data_rdy;
input [63:0] Y_in;
output [63:0] X_out, Y_out;
reg [63:0] X, Y;
wire [63:0] XL1_1, XL2_1, XL8_1;
assign XL1_1 = {X[62:0], X[63]};
assign XL2_1 = {X[61:0], X[63:62]};
assign XL8_1 = {X[55:0], X[63:56]};
wire [63:0] YL1_1, YL8_2;
assign YL1_1 = {Y[62:0], Y[63]};
assign YL8_2 = {Y_in[55:0], Y_in[63:56]};
wire [63:0] sout1, sout2;
sub1 s1 (
Y,
XL2_1,
XL8_1,
XL1_1,
sout1
);
sub1 s2 (
X,
key_in,
YL1_1,
YL8_2,
sout2
);
always @(posedge clk) begin
if (data_rdy == 1) begin
{X, Y} <= {data_in, X, Y[63:1]};
end else if (data_rdy == 3) begin
if (counter == 1'b0) begin
X <= sout1;
Y <= X;
end else begin
X <= sout2;
end
end
end
assign X_out = X;
assign Y_out = Y;
endmodule
| 7.29868
|
module quick_mux_128 (
in1,
in2,
out,
sel
);
input [127:0] in1, in2;
input sel;
output [127:0] out;
assign out = sel ? (in1) : in2;
endmodule
| 7.428361
|
module p_keysch10 (
clk,
counter,
data_in,
data_rdy,
key_out
);
input clk, data_in;
input [1:0] data_rdy;
input [7:0] counter;
output [63:0] key_out;
reg [63:0] KX, KY;
reg [0:67] Z = 68'b10101111011100000011010010011000101000010001111110010110110011101011;
reg [63:0] c = 64'hfffffffffffffffc;
always @(posedge clk) begin
if (data_rdy == 2) begin
{KX, KY} <= {data_in, KX, KY[63:1]};
end else if (data_rdy == 3) begin
if (counter[0] == 1'b1) begin
KX <= c ^ Z[counter[7:1]] ^ KY ^ {KX[2:0], KX[63:3]} ^ {KX[3:0], KX[63:4]};
KY <= KX;
end
end
end
assign key_out = KY;
endmodule
| 6.723774
|
module p_keysch11 (
clk,
counter,
data_in,
data_rdy,
key_out
);
input clk, data_in;
input [1:0] data_rdy;
input [7:0] counter;
output [63:0] key_out;
reg [63:0] KX, KY;
always @(posedge clk) begin
if (data_rdy == 2) begin
{KX, KY} <= {data_in, KX, KY[63:1]};
end else if (data_rdy == 3) begin
if (counter[0] == 1'b1) begin
KX <= KY ^ {KX[2:0], KX[63:3]} ^ {KX[3:0], KX[63:4]};
KY <= KX;
end
end
end
assign key_out = KY;
endmodule
| 6.688182
|
module and4 (
a1,
a2,
andout
);
input [3:0] a1, a2;
output [3:0] andout;
assign andout = a1 & a2;
endmodule
| 7.593419
|
module MUX2to1 (
In0,
In1,
Sel,
Out
);
input In0, In1, Sel;
output Out;
assign Out = (Sel) ? In1 : In0;
endmodule
| 7.21075
|
module toMod (
output [7:0] Pos,
input [7:0] A
);
assign Pos = (A[7] ? ~A + 1 : A);
endmodule
| 6.963467
|
module TwoXOneMUX (
input A,
B,
S,
output reg C
);
always @(*) begin
C = (A & ~S) | (S & B);
end
endmodule
| 7.48674
|
module 2x1(input a,b,s, output y);
wire r,w1,w2;
not(r,s);
and(w1,b,s);
and(w2,a,r);
or(y,w1,w2);
endmodule
| 6.775103
|
module adder (
a,
b,
s,
co
);
input a, b;
output s, co;
and (co, a, b);
xor (s, a, b);
endmodule
| 7.4694
|
module Mux (
output saida,
input entrada0,
input entrada1,
input chave
);
wire [1:0] s;
wire saida_not;
not NOT0 (saida_not, chave);
and AND0 (s[0], entrada0, saida_not);
and AND1 (s[1], entrada1, chave);
or OR0 (saida, s[0], s[1]);
endmodule
| 7.736456
|
module Demux (
output saida0,
output saida1,
input chave
);
wire saida_not;
not NOT0 (saida_not, chave);
and AND0 (saida0, 1, saida_not);
and AND1 (saida1, 1, chave);
endmodule
| 7.090619
|
module Mem_2por4 (
output [3:0] OUT0,
input [3:0] entrada,
input clk,
input addr,
input rw,
input clr
);
wire [1:0] s;
wire [3:0] saida0;
wire [3:0] saida1;
Demux demux0 (
s[0],
s[1],
addr
);
Mem_1por4 MEM1 (
saida0,
entrada,
clk,
s[0],
rw,
clr
);
Mem_1por4 MEM2 (
saida1,
entrada,
clk,
s[1],
rw,
clr
);
Mux mux0 (
OUT0[0],
saida0[0],
saida1[0],
addr
);
Mux mux1 (
OUT0[1],
saida0[1],
saida1[1],
addr
);
Mux mux2 (
OUT0[2],
saida0[2],
saida1[2],
addr
);
Mux mux3 (
OUT0[3],
saida0[3],
saida1[3],
addr
);
endmodule
| 6.523387
|
module test_Mem_2por4;
// ------------------------- definir dados
reg [3:0] entrada;
reg clk;
reg addr;
reg rw;
reg clr;
wire [3:0] saida;
// ------------------------- instancia
Mem_2por4 modulo (
saida,
entrada,
clk,
addr,
rw,
clr
);
// ------------------------- parte principal
initial begin
$display("Memria RAM 2x4 \n");
$display("Entrada\tClk\tAddr\tR/W\tClr\tSaida\n");
#1 entrada = 0001;
clk = 0;
addr = 0;
rw = 0;
clr = 1;
$monitor("%4b\t%1b\t%1b\t%1b\t%1b\t%4b", entrada, clk, addr, rw, clr, saida);
#1 entrada = 0000;
clk = 1;
addr = 0;
rw = 1;
clr = 0;
#1 entrada = 1000;
clk = 0;
addr = 0;
rw = 0;
clr = 0;
#1 entrada = 0000;
clk = 1;
addr = 1;
rw = 1;
clr = 0;
#1 entrada = 0000;
clk = 0;
addr = 1;
rw = 0;
clr = 0;
end
endmodule
| 7.504431
|
module 2x4decoder(input a,b output s,d,f,g);
assign s = ~a&~b;
assign d = ~a& b;
assign f = a&~b;
assign g = a& b;
endmodule
| 6.855172
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {(~full[4:1]), full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module mux2to1 (
out,
in1,
in2,
sel
);
input in1, in2, sel;
output out;
assign out = sel ? in2 : in1;
endmodule
| 7.107199
|
module MUX (
i,
s,
y
);
input [1:0] i;
input s;
output y;
reg y;
always @(s or i) begin
case (s)
1'b0: y = i[00];
1'b1: y = i[01];
default: y = 0;
endcase
end
endmodule
| 6.699278
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], (~full[5])};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module decoder (
en,
a,
b,
y
);
// input port
input en, a, b;
// use reg to store the output value
output reg [3:0] y;
// always is used in design block
// only in Behavioural modeling.
always @(en, a, b) begin
// using condition if statement
// implement the 2:4 truth table
if (en == 0) begin
if (a == 1'b0 & b == 1'b0) y = 4'b1110;
else if (a == 1'b0 & b == 1'b1) y = 4'b1101;
else if (a == 1'b1 & b == 1'b0) y = 4'b1011;
else if (a == 1 & b == 1) y = 4'b0111;
else y = 4'bxxxx;
end else y = 4'b1111;
end
endmodule
| 7.018254
|
module Arbiter_cell #(
parameter W = 4
) (
input clk,
input rst,
input [1:0] req,
input [2*(W-1)-1:0] grant,
output req_out,
output [W-1:0] grant_out
);
wire [1:0] op1, op2;
reg priority_;
assign op1[0] = ~priority_ | ~req[1];
assign op1[1] = priority_ | ~req[0];
assign op2[0] = req[0] & op1[0];
assign op2[1] = req[1] & op1[1];
assign req_out = op2[0] | op2[1];
assign grant_out[W-1] = op2[1];
assign grant_out[W-2:0] = (op2[1]) ? grant[2*(W-1)-1:W-1] : grant[W-2:0];
always @(posedge clk, posedge rst) begin
if (rst) priority_ <= 0;
else priority_ <= (req[0] | req[1]) ? !priority_ : priority_;
end
endmodule
| 6.97395
|
module of RTHS design, you can find description about this module from paper below.
// ("RTHS: A Low-Cost High-Performance Real-Time Hardware Sorter, Using
// a Multidimensional Sorting Algorithm", doi: 10.1109/TVLSI.2019.2912554)
// In this module, one dimentional input array is transfered to 2D matrix form and send to
// the parallel bitonic sorting networks for sorting. After each phase of sorting the outputs
// of the parallel units have to switch from column to row or vice versa.
//
// Licence: These project have been published for academic use only under GPLv3 License.
// Copyright 2018
// All Rights Reserved
///////////////////////////////////////////////////////////
module SorterMain #( parameter NUM = 4 , W = 64)(
//INPUT
input clk,
input start,
input [(NUM*NUM*W)-1:0] keyIn,
//OUTPUT
output [(NUM*NUM*W)-1:0] keyOut,
output ready
);
reg [W-1:0] key_reg [NUM*NUM-1:0]; //temporary key registers
wire [W-1:0] switch_In [NUM*NUM-1:0]; //using for the input of the switch module
wire [W-1:0] switch_Out [NUM*NUM-1:0];//using for the output of the switch module
wire [3:0] direction; //set by control unit to obtain the order mode of sorting
integer o, p;
initial
for(p=0; p<NUM*NUM; p = p+1)
key_reg[p] <= 0; // initialization
////////////////////////////
/// convert input and output
wire [W-1:0] _keyIn [NUM*NUM-1:0];
wire [W-1:0] _keyOut [NUM*NUM-1:0];
genvar vnf;
generate
for (vnf=0; vnf<NUM*NUM; vnf=vnf+1) begin : convert_signals
assign _keyIn[vnf][W-1:0] = keyIn[W*vnf+(W-1):W*vnf]; //unpacked
assign keyOut[W*vnf+(W-1):W*vnf] = switch_Out[vnf][W-1:0]; //packed
end
endgenerate
//
///
////////////////////////////
/******************************/
/*********** SORTER ***********/
/******************************/
genvar q;
generate
for(q = 0; q < NUM; q = q+1) //using "Num" bitonic sorting network in parallel for sorting the 2D matrix
begin: BN
BitonicNetwork #(NUM, W) BN (
.clk (clk),
.rst (start),
.direction(direction[q]),
.IN ({key_reg[4*q+3], key_reg[4*q+2], key_reg[4*q+1], key_reg[4*q]}),
.OUT({switch_In[4*q+3], switch_In[4*q+2], switch_In[4*q+1], switch_In[4*q]})
);
end
endgenerate
always @(posedge clk) begin
for(o=0; o<NUM*NUM; o = o+1)
key_reg[o] <= (start)? _keyIn[o] : switch_Out[o]; // input of the temporary key registers
end
/******************************/
/*********** SWITCH ***********/
/******************************/
Switch #(NUM, W) SW(
//INPUT
.IN1 ({switch_In[3] , switch_In[2] , switch_In[1] , switch_In[0]}),
.IN2 ({switch_In[7] , switch_In[6] , switch_In[5] , switch_In[4]}),
.IN3 ({switch_In[11], switch_In[10], switch_In[9] , switch_In[8]}),
.IN4 ({switch_In[15], switch_In[14], switch_In[13], switch_In[12]}),
//OUTPUT
.OUT1 ({switch_Out[3] , switch_Out[2] , switch_Out[1] , switch_Out[0]}),
.OUT2 ({switch_Out[7] , switch_Out[6] , switch_Out[5] , switch_Out[4]}),
.OUT3 ({switch_Out[11], switch_Out[10], switch_Out[9] , switch_Out[8]}),
.OUT4 ({switch_Out[15], switch_Out[14], switch_Out[13], switch_Out[12]})
);
/******************************/
/************ CTRL ************/
/******************************/
Control CTRL(
//INPUT
.clk (clk),
.start (start),
//OUTPUT
.direction (direction),
.ready (ready)
);
endmodule
| 8.47808
|
module MAC_Unit (
input [7:0] Activation,
weight,
input clk,
rstn,
en,
input [1:0] ReducePrecLevel,
output reg [2:0] count,
output reg [15:0] PRODUCT,
output reg [19:0] RESULT
);
// counter part
always @(posedge clk, negedge rstn) begin
if (rstn == 0) count = 0;
else if (en == 1) begin
count = count + 1;
end
end
// logic minimized count signal (triger = 1 when last weight bit enter, done = 1 when first weight bit enter)
assign trigger = count[0] & ((count[1]&ReducePrecLevel[0])|(count[2]&count[1])|(ReducePrecLevel[1]&~ReducePrecLevel[0]));
assign done = ~count[0] & ((~count[1]&ReducePrecLevel[0])|(~count[2]&~count[1])|(ReducePrecLevel[1]&~ReducePrecLevel[0]));
// calculate partial product
wire Win = weight[count];
wire [7:0] WA = {8{Win}} & Activation;
// partial products summation
wire [8:0] op1, op2;
wire [7:0] WAprime = ~WA;
genvar i;
generate // op1: new partial product WA, if last PP, ~WA
for (i = 0; i < 8; i = i + 1) begin
MUX_2 mux (
WA[i],
WAprime[i],
trigger,
op1[i]
);
end
endgenerate
assign op1[8] = op1[7]; // sign extention
wire [15:0] prevProduct = PRODUCT;
wire [ 8:0] presum = {prevProduct[15], prevProduct[15:8]};
generate // op2: accumulated partial products, if first PP, 0
for (i = 0; i < 9; i = i + 1) begin
MUX_2 mux (
presum[i],
0,
done,
op2[i]
);
end
endgenerate
wire [8:0] partsumres;
ADDER #(
.size(9)
) productACCUM (
op1,
op2,
trigger,
partsumres
);
// product result register
wire [15:0] dPRODUCT = {partsumres, prevProduct[7:1]}; // 1bit shift right
always @(posedge clk, negedge rstn) begin
if (rstn == 0) PRODUCT = 0;
else if (en == 1) PRODUCT = dPRODUCT;
end
// accumulator part (accumres = accold + accnew)
wire [19:0] accold, accnew, accumres;
assign accold = RESULT;
assign accnew = {{4{PRODUCT[15]}}, PRODUCT};
wire [2:1] CIN;
wire [2:0] COUT;
MUX_2 cin2control (
COUT[1],
0,
ReducePrecLevel[1],
CIN[2]
); // decide adder carry in
MUX_2 cin1control (
COUT[0],
0,
ReducePrecLevel[0],
CIN[1]
);
ADDERc #(14) acc2 (
accold[19:6],
accnew[19:6],
CIN[2],
accumres[19:6],
COUT[2]
);
ADDERc #(2) acc1 (
accold[5:4],
accnew[5:4],
CIN[1],
accumres[5:4],
COUT[1]
);
ADDERc #(4) acc0 (
accold[3:0],
accnew[3:0],
0,
accumres[3:0],
COUT[0]
);
// accumulator register, update whenever product calculate done
always @(negedge done, negedge rstn) begin
if (rstn == 0) RESULT = 0;
else if (en == 1) RESULT = accumres;
end
endmodule
| 6.805864
|
module MUX_2 (
input A,
B,
sel,
output O
);
wire asp, bs, notsel;
not (notsel, sel);
nand (asp, A, notsel);
nand (bs, B, sel);
nand (O, asp, bs);
endmodule
| 6.660624
|
module ADDERc (
op1,
op2,
cin,
res,
cout
); // with carry out
parameter size = 12;
input [size-1:0] op1, op2;
input cin;
output [size-1:0] res;
output cout;
wire [size:0] C;
genvar i;
assign C[0] = cin;
assign cout = C[size];
generate
for (i = 0; i < size; i = i + 1) begin
fullAdder FAwc (
.A (op1[i]),
.B (op2[i]),
.ci(C[i]),
.s (res[i]),
.co(C[i+1])
);
end
endgenerate
endmodule
| 6.952629
|
module ADDER (
op1,
op2,
cin,
res
); // without carry out
parameter size = 12;
input [size-1:0] op1, op2;
input cin;
output [size-1:0] res;
wire [size:0] C;
genvar i;
assign C[0] = cin;
generate
for (i = 0; i < size; i = i + 1) begin
fullAdder FAwoc (
.A (op1[i]),
.B (op2[i]),
.ci(C[i]),
.s (res[i]),
.co(C[i+1])
);
end
endgenerate
endmodule
| 7.255631
|
module two_bit_adder (
sum,
carryout,
S0,
A0,
B0,
A1,
B1
);
input A0, B0, A1, B1;
output sum, carryout, S0;
HA HA1 (
S0,
C1,
A0,
B0
);
FA FA1 (
sum,
carryout,
A1,
B1,
C1
);
endmodule
| 6.650749
|
module tb_comparator;
reg [1:0] A, B;
wire gt, eq, lt;
integer i;
comp_2_bit dut (
A,
B,
gt,
eq,
lt
);
initial begin
$dumpfile("2 bit comp.vcd");
$dumpvars(0, tb_comparator);
for (i = 0; i < 4; i = i + 1) begin
A = i;
B = i + 1;
#20;
end
for (i = 0; i < 4; i = i + 1) begin
A = i;
B = i;
#20;
end
for (i = 0; i < 4; i = i + 1) begin
A = i + 1;
B = i;
#20;
end
end
endmodule
| 6.843472
|
module fulladder (
input x,
input y,
input cin,
output A,
output cout
);
assign {cout, A} = cin + y + x;
endmodule
| 7.454465
|
module nand2 (
Y,
A,
B
);
output Y;
input A, B;
supply0 GND;
supply1 PWR;
pmos (Y, PWR, A);
pmos (Y, PWR, B);
nmos (Y, w1, A);
nmos (w1, GND, B);
endmodule
| 9.113032
|
module mux2 (
input a,
b,
s,
output x
);
assign x = s ? b : a;
endmodule
| 7.816424
|
module TriState_TB ();
reg aa = 0, enable = 0;
wire yy;
integer i;
Tri_State UUT (
aa,
enable,
yy
);
initial begin
//examing To 1 worst case senario:
#20 enable = 1;
#20 aa = 1;
#20 aa = 0;
#20 enable = 0;
#25 $stop;
end
endmodule
| 6.982755
|
module top_module (
input [2:0] a,
b,
input cin,
output [2:0] cout,
output [2:0] sum
);
FA FA1 (
a[0],
b[0],
cin,
cout[0],
sum[0]
);
FA FA2 (
a[1],
b[1],
cout[0],
cout[1],
sum[1]
);
FA FA3 (
a[2],
b[2],
cout[1],
cout[2],
sum[2]
);
endmodule
| 7.203305
|
module FA (
input a,
b,
cin,
output cout,
sum
);
assign cout = a & b | b & cin | a & cin;
assign sum = a ^ b ^ cin;
endmodule
| 8.362615
|
module top_module (
input [1:0] sel,
input [7:0] a,
input [7:0] b,
input [7:0] c,
input [7:0] d,
output [7:0] out
);
wire [7:0] mux_con_0, mux_con_1;
mux2 mux_inst_0 (
sel[0],
a,
b,
mux_con_0
);
mux2 mux_inst_1 (
sel[0],
c,
d,
mux_con_1
);
mux2 mux_inst_2 (
sel[1],
mux_con_0,
mux_con_1,
out
);
endmodule
| 7.203305
|
module top_module (
input [15:0] a,
b,
c,
d,
e,
f,
g,
h,
i,
input [ 3:0] sel,
output [15:0] out
);
always @* begin
case (sel)
4'b0000: out = a;
4'b0001: out = b;
4'b0010: out = c;
4'b0011: out = d;
4'b0100: out = e;
4'b0101: out = f;
4'b0110: out = g;
4'b0111: out = h;
4'b1000: out = i;
default: out = {16{1'b1}};
endcase
end
endmodule
| 7.203305
|
module top_module (
input a,
input b,
input c,
input d,
output out1,
output out2
);
//connect ports by name
mod_a inst_1 (
.in1 (a),
.in2 (b),
.in3 (c),
.in4 (d),
.out1(out1),
.out2(out2)
);
endmodule
| 7.203305
|
module top_module (
input clk,
input reset,
output [3:0] q
);
always @(posedge clk) begin
if (reset) q <= 4'd1;
else if (q == 4'd10) q <= 4'd1;
else q <= q + 4'd1;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input reset, // Synchronous reset
input [7:0] d,
output [7:0] q
);
always @(posedge clk) begin
//this is an active high synchronous reset
if (reset) q <= 8'b0;
else q <= d;
end
endmodule
| 7.203305
|
module top_module (
input a,
input b,
input c,
input d,
output out
);
assign out = a | (~a & ~b & c);
endmodule
| 7.203305
|
module top_module (
input a,
input b,
input sel_b1,
input sel_b2,
output wire out_assign,
output reg out_always
);
assign out_assign = (sel_b1 == 1'b1 && sel_b2 == 1'b1) ? b : a;
always @(*) begin
if (sel_b1 == 1'b1 && sel_b2 == 1'b1) begin
out_always = b;
end else begin
out_always = a;
end
end
endmodule
| 7.203305
|
module top_module (
input in1,
input in2,
output out
);
assign out = ~(in1 | in2);
endmodule
| 7.203305
|
module top_module (
input [99:0] in,
output out_and,
output out_or,
output out_xor
);
assign out_and = ∈
assign out_or = |in;
assign out_xor = ^in;
endmodule
| 7.203305
|
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