code
stringlengths 35
6.69k
| score
float64 6.5
11.5
|
|---|---|
module clk_div (
clk,
clk_sel,
clk_out
);
input clk;
input [3:0] clk_sel;
output reg clk_out;
reg [15:0] counter;
reg [15:0] next_counter;
always @(posedge clk) begin
counter = next_counter;
end
always @* begin
next_counter = counter + 1;
case (clk_sel[3:0])
0: clk_out = counter[0];
1: clk_out = counter[1];
2: clk_out = counter[2];
3: clk_out = counter[3];
4: clk_out = counter[4];
5: clk_out = counter[5];
6: clk_out = counter[6];
7: clk_out = counter[7];
8: clk_out = counter[8];
9: clk_out = counter[9];
10: clk_out = counter[10];
11: clk_out = counter[11];
12: clk_out = counter[12];
13: clk_out = counter[13];
14: clk_out = counter[14];
15: clk_out = counter[15];
endcase
end
endmodule
| 7.520262
|
module Complement_test;
reg [3:0] D;
wire [3:0] Q;
Complement u1 (
D,
Q
);
initial begin
#800 $finish;
end
initial begin
D = 4'b0000;
#100;
D = 4'b0001;
#50;
D = 4'b0010;
#50;
D = 4'b0011;
#50;
D = 4'b0100;
#50;
D = 4'b0101;
#50;
D = 4'b0110;
#50;
D = 4'b0111;
#50;
D = 4'b1000;
#50;
D = 4'b1001;
#50;
D = 4'b1010;
#50;
D = 4'b1011;
#50;
D = 4'b1100;
#50;
D = 4'b1101;
#50;
D = 4'b1110;
#50;
D = 4'b1111;
end
endmodule
| 6.605957
|
module MUX_2to1_32bit (
input [31:0] IN1,
input [31:0] IN2,
output [31:0] OP,
input CONTROL
);
reg [31:0] OP_REG;
always @(*) begin
case (CONTROL)
1'b0: OP_REG = IN1;
1'b1: OP_REG = IN2;
endcase
end
assign OP = OP_REG;
endmodule
| 8.487995
|
module MUX_4to1_32bit (
input [31:0] IN1,
input [31:0] IN2,
input [31:0] IN3,
input [31:0] IN4,
output [31:0] OP,
input [ 1:0] CONTROL
);
reg [31:0] OP_REG;
always @(*) begin
case (CONTROL)
2'b00: OP_REG = IN1;
2'b01: OP_REG = IN2;
2'b10: OP_REG = IN3;
2'b11: OP_REG = IN4;
endcase
end
assign OP = OP_REG;
endmodule
| 8.96532
|
module priority_decoder_1
(input wire [3:0] select,
output reg [2:0] priority // "priority" is not a keyword
);
// return bit number of highest bit set, or 7 if none set
always @(select) begin
casez (select) // synthesis full_case
4'b1???: priority = 4'h3;
4'b01??: priority = 4'h2;
4'b001?: priority = 4'h1;
4'b0001: priority = 4'h0;
4'b0000: priority = 4'h7;
endcase
end
endmodule
| 6.546663
|
module FA (
input A,
B,
Cin,
output S,
Cout
);
wire T0, T1, T2;
xor3 X1 (
A,
B,
Cin,
S
);
and2 A1 (
A,
B,
T0
);
and2 A2 (
B,
Cin,
T1
);
and2 A3 (
Cin,
A,
T2
);
or3 O1 (
T0,
T1,
T2,
Cout
);
endmodule
| 8.362615
|
module FS (
input Dec,
input A,
B,
Cin,
output Diff,
Cout
);
wire T0;
xor2 A4 (
B,
Dec,
T0
);
FA d (
A,
T0,
Cin,
Diff,
Cout
);
endmodule
| 7.689649
|
module FS_TB;
wire t_s, t_cout, t_diff, t_cout1;
reg t_a, t_b, t_cin, t_d;
FS I1 (
.Dec(t_d),
.A(t_a),
.B(t_b),
.Cin(t_cin),
.Diff(t_diff),
.Cout(t_cout1)
);
initial begin
$dumpfile("FS.vcd");
$dumpvars(0, FS_TB);
end
initial begin
$monitor(t_a, t_b, t_cin, t_s, t_cout);
t_a = 1'b0;
t_b = 1'b0;
t_cin = 1'b0;
#5 t_a = 1'b0;
t_b = 1'b0;
t_cin = 1'b0;
#5 t_a = 1'b0;
t_b = 1'b0;
t_cin = 1'b1;
#5 t_a = 1'b0;
t_b = 1'b1;
t_cin = 1'b0;
#5 t_a = 1'b0;
t_b = 1'b1;
t_cin = 1'b1;
#5 t_a = 1'b1;
t_b = 1'b0;
t_cin = 1'b0;
#5 t_a = 1'b1;
t_b = 1'b0;
t_cin = 1'b1;
#5 t_a = 1'b1;
t_b = 1'b1;
t_cin = 1'b0;
#5 t_a = 1'b1;
t_b = 1'b1;
t_cin = 1'b1;
end
endmodule
| 6.717657
|
module top_module (
input clk,
input reset, // Synchronous active-high reset
output [3:0] q
);
always @(posedge clk) begin
q <= (reset | q == 4'd9) ? 0 : q + 1;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input [7:0] d,
output reg [7:0] q
);
// Because q is a vector, this creates multiple DFFs.
always @(posedge clk) q <= d;
endmodule
| 7.203305
|
module top_module (
input a,
b,
cin,
output cout,
sum
);
assign sum = a ^ b ^ cin;
assign cout = a & b | a & cin | b & cin;
endmodule
| 7.203305
|
module declaration syntax here:
module top_module(clk, reset, in, out);
input clk;
input reset; // Synchronous reset to state B
input in;
output out;//
reg out;
// Fill in state name declarations
reg present_state, next_state;
always @(posedge clk) begin
if (reset) begin
// Fill in reset logic
present_state <= 1;
out <= 1;
end
else begin
case (present_state)
// Fill in state transition logic
0: next_state = (in == 1) ? 0 : 1;
1: next_state = (in == 1) ? 1 : 0;
endcase
// State flip-flops
present_state = next_state;
case (present_state)
// Fill in output logic
0: out = 0;
1: out = 1;
default: out = 0;
endcase
end
end
endmodule
| 6.89453
|
module top_module (
output out
);
assign out = 0;
endmodule
| 7.203305
|
module top_module (
input a,
input b,
input c,
input d,
output out
);
assign out = ~a & ~b & ~c | ~a & ~c & ~d | a & ~b & ~c | b & c & d | a & ~b & c & d | ~a & c & ~d;
endmodule
| 7.203305
|
module top_module (
input [99:0] a,
b,
input sel,
output [99:0] out
);
assign out = sel ? b : a;
endmodule
| 7.203305
|
module top_module (
input clk,
input load,
input [1:0] ena,
input [99:0] data,
output reg [99:0] q
);
always @(posedge clk) begin
if (load) begin
q <= data;
end else begin
if (ena == 2'b01) begin
q <= {q[0], q[99:1]};
end else if (ena == 2'b10) begin
q <= {q[98:0], q[99]};
end else begin
q <= q;
end
end
end
endmodule
| 7.203305
|
module top_module (
input clk,
input load,
input [511:0] data,
output [511:0] q
);
always @(posedge clk) begin
if (load) q <= data;
else begin
q <= q ^ {q << 1} | ({~(q >> 1)} & q & {q << 1});
end
end
endmodule
| 7.203305
|
module top_module (
input [99:0] a,
b,
input sel,
output [99:0] out
);
assign out = (sel == 0 ? a : b);
endmodule
| 7.203305
|
module top_module (
input a,
b,
sel,
output out
);
always @(*) begin
if (sel == 1'b0) begin
out = a;
end else begin
out = b;
end
end
endmodule
| 7.203305
|
module top_module (
input in,
output out
);
assign out = in;
endmodule
| 7.203305
|
module top_module (
input a,
b,
c,
output w,
x,
y,
z
);
assign w = a;
assign x = b;
assign y = b;
assign z = c;
endmodule
| 7.203305
|
module top_module (
input in,
output out
);
assign out = ~in;
endmodule
| 7.203305
|
module top_module (
input a,
input b,
output out
);
assign out = a & b;
endmodule
| 7.203305
|
module top_module (
input a,
input b,
output out
);
assign out = ~(a | b);
endmodule
| 7.203305
|
module top_module (
input a,
input b,
output out
);
assign out = ~a ^ b;
endmodule
| 7.203305
|
module top_module (
input a,
input b,
input c,
input d,
output out,
output out_n
);
wire in1, in2;
assign in1 = a & b;
assign in2 = c & d;
assign out = in1 | in2;
assign out_n = ~(in1 | in2);
endmodule
| 7.203305
|
module top_module (
input p1a,
p1b,
p1c,
p1d,
p1e,
p1f,
output p1y,
input p2a,
p2b,
p2c,
p2d,
output p2y
);
assign p1y = (p1a & p1b & p1c) | (p1d & p1e & p1f);
assign p2y = (p2a & p2b) | (p2d & p2c);
endmodule
| 7.203305
|
module top_module (
input wire [2:0] vec,
output wire [2:0] outv,
output wire o2,
output wire o1,
output wire o0
); // Module body starts after module declaration
assign outv = vec;
assign o2 = vec[2];
assign o1 = vec[1];
assign o0 = vec[0];
endmodule
| 7.203305
|
module top_module (
input wire [15:0] in,
output wire [ 7:0] out_hi,
output wire [ 7:0] out_lo
);
assign {out_hi, out_lo} = in;
endmodule
| 7.203305
|
module top_module (
input [31:0] in,
output [31:0] out
); //
assign {out[7:0], out[15:8], out[23:16], out[31:24]} = in;
endmodule
| 7.203305
|
module top_module (
input [2:0] a,
input [2:0] b,
output [2:0] out_or_bitwise,
output out_or_logical,
output [5:0] out_not
);
assign out_or_bitwise = a | b;
assign out_or_logical = a || b;
assign out_not[2:0] = ~a; // Part-select on left side is o.
assign out_not[5:3] = ~b; //Assigning to [5:3] does not conflict with [2:0]
endmodule
| 7.203305
|
module top_module (
input [3:0] in,
output out_and,
output out_or,
output out_xor
);
assign out_and = in[0] & in[1] & in[2] & in[3];
assign out_or = in[0] | in[1] | in[2] | in[3];
assign out_xor = in[0] ^ in[1] ^ in[2] ^ in[3];
endmodule
| 7.203305
|
module top_module (
input [4:0] a,
b,
c,
d,
e,
f,
output [7:0] w,
x,
y,
z
); //
assign w = {a[4:0], b[4:2]};
assign x = {b[1:0], c[4:0], d[4]};
assign y = {d[3:0], e[4:1]};
assign z = {e[0], f[4:0], 2'b11};
endmodule
| 7.203305
|
module top_module (
input [7:0] in,
output [7:0] out
);
assign out[7:0] = {in[0], in[1], in[2], in[3], in[4], in[5], in[6], in[7]};
/*
// I know you're dying to know how to use a loop to do this:
// Create a combinational always block. This creates combinational logic that computes the same result
// as sequential code. for-loops describe circuit *behaviour*, not *structure*, so they can only be used
// inside procedural blocks (e.g., always block).
// The circuit created (wires and gates) does NOT do any iteration: It only produces the same result
// AS IF the iteration occurred. In reality, a logic synthesizer will do the iteration at compile time to
// figure out what circuit to produce. (In contrast, a Verilog simulator will execute the loop sequentially
// during simulation.)
always @(*) begin
for (int i=0; i<8; i++) // int is a SystemVerilog type. Use integer for pure Verilog.
out[i] = in[8-i-1];
end
// It is also possible to do this with a generate-for loop. Generate loops look like procedural for loops,
// but are quite different in concept, and not easy to understand. Generate loops are used to make instantiations
// of "things" (Unlike procedural loops, it doesn't describe actions). These "things" are assign statements,
// module instantiations, net/variable declarations, and procedural blocks (things you can create when NOT inside
// a procedure). Generate loops (and genvars) are evaluated entirely at compile time. You can think of generate
// blocks as a form of preprocessing to generate more code, which is then run though the logic synthesizer.
// In the example below, the generate-for loop first creates 8 assign statements at compile time, which is then
// synthesized.
// Note that because of its intended usage (generating code at compile time), there are some restrictions
// on how you use them. Examples: 1. Quartus requires a generate-for loop to have a named begin-end block
// attached (in this example, named "my_block_name"). 2. Inside the loop body, genvars are read only.
generate
genvar i;
for (i=0; i<8; i = i+1) begin: my_block_name
assign out[i] = in[8-i-1];
end
endgenerate
*/
endmodule
| 7.203305
|
module top_module (
input [ 7:0] in,
output [31:0] out
); //
assign out = {{24{in[7]}}, {in}};
endmodule
| 7.203305
|
module top_module (
input a,
b,
c,
d,
e,
output [24:0] out
); //
wire [4:0] k = {a, b, c, d, e};
assign out[24:20] = ~{5{a}} ^ k;
assign out[19:15] = ~{5{b}} ^ k;
assign out[14:10] = ~{5{c}} ^ k;
assign out[9:5] = ~{5{d}} ^ k;
assign out[4:0] = ~{5{e}} ^ k;
endmodule
| 7.203305
|
module top_module (
input a,
input b,
output out
);
// Create an instance of "mod_a" named "inst1", and connect ports by name:
mod_a inst1 (
.in1(a), // Port"in1"connects to wire "a"
.in2(b), // Port "in2" connects to wire "b"
.out(out) // Port "out" connects to wire "out"
// (Note: mod_a's port "out" is not related to top_module's wire "out".
// It is simply coincidence that they have the same name)
);
/*
// Create an instance of "mod_a" named "inst2", and connect ports by position:
mod_a inst2 ( a, b, out ); // The three wires are connected to ports in1, in2, and out, respectively.
*/
endmodule
| 7.203305
|
module top_module (
input a,
input b,
input c,
input d,
output out1,
output out2
);
mod_a aa (
out1,
out2,
a,
b,
c,
d
);
endmodule
| 7.203305
|
module top_module (
input a,
input b,
input c,
input d,
output out1,
output out2
);
mod_a aaaa (
.out1(out1),
.out2(out2),
.in1 (a),
.in2 (b),
.in3 (c),
.in4 (d)
);
endmodule
| 7.203305
|
module top_module (
input clk,
input d,
output q
);
wire q1, q2;
my_dff d1 (
clk,
d,
q1
);
my_dff d2 (
clk,
q1,
q2
);
my_dff d3 (
clk,
q2,
q
);
endmodule
| 7.203305
|
module top_module (
input clk,
input [7:0] d,
input [1:0] sel,
output reg [7:0] q
);
wire [7:0] o1, o2, o3; // output of each my_dff8
// Instantiate three my_dff8s
my_dff8 d1 (
clk,
d,
o1
);
my_dff8 d2 (
clk,
o1,
o2
);
my_dff8 d3 (
clk,
o2,
o3
);
// This is one way to make a 4-to-1 multiplexer
always @(*) // Combinational always block
case (sel)
2'h0: q = d;
2'h1: q = o1;
2'h2: q = o2;
2'h3: q = o3;
endcase
endmodule
| 7.203305
|
module top_module (
input [31:0] a,
input [31:0] b,
output [31:0] sum
);
wire con1, con2;
add16 adder_1 (
a[15:0],
b[15:0],
0,
sum[15:0],
con1
);
add16 adder_2 (
a[31:16],
b[31:16],
con1,
sum[31:16],
con2
);
endmodule
| 7.203305
|
module top_module (
input [31:0] a,
input [31:0] b,
output [31:0] sum
); //
wire con1, con2;
add16 adder_1 (
a[15:0],
b[15:0],
0,
sum[15:0],
con1
);
add16 adder_2 (
a[31:16],
b[31:16],
con1,
sum[31:16],
con2
);
endmodule
| 7.203305
|
module add1 (
input a,
input b,
input cin,
output sum,
output cout
);
assign sum = a ^ b ^ cin;
assign cout = a & b | a & cin | b & cin;
endmodule
| 6.640243
|
module top_module (
input [31:0] a,
input [31:0] b,
output [31:0] sum
);
wire cout1, cout2a, cout2b;
wire [15:0] sum2a, sum2b;
add16 add1 (
a[15:0],
b[15:0],
0,
sum[15:0],
cout1
);
add16 add2a (
a[31:16],
b[31:16],
0,
sum2a,
cout2a
);
add16 add2b (
a[31:16],
b[31:16],
1,
sum2b,
cout2b
);
always @(*) begin
case (cout1)
0: sum[31:16] = sum2a;
1: sum[31:16] = sum2b;
endcase
end
endmodule
| 7.203305
|
module top_module (
input [31:0] a,
input [31:0] b,
input sub,
output [31:0] sum
);
wire cout, cout2;
wire [31:0] b_in;
assign b_in = b ^ {32{sub}};
add16 a1 (
a[15:0],
b_in[15:0],
sub,
sum[15:0],
cout
);
add16 a2 (
a[31:16],
b_in[31:16],
cout,
sum[31:16],
cout2
);
endmodule
| 7.203305
|
module top_module (
input a,
input b,
output wire out_assign,
output reg out_alwaysblock
);
assign out_assign = a & b;
always @(*) out_alwaysblock = a & b;
endmodule
| 7.203305
|
module top_module (
input clk,
input a,
input b,
output wire out_assign,
output reg out_always_comb,
output reg out_always_ff
);
assign out_assign = a ^ b;
always @(*) out_always_comb = a ^ b;
always @(posedge clk) out_always_ff <= a ^ b;
endmodule
| 7.203305
|
module top_module (
input a,
input b,
input sel_b1,
input sel_b2,
output wire out_assign,
output reg out_always
);
assign out_assign = (sel_b1 & sel_b2) ? b : a;
always @(*) begin
if (sel_b1 & sel_b2) begin
out_always = b;
end else begin
out_always = a;
end
end
endmodule
| 7.203305
|
module top_module (
input cpu_overheated,
output reg shut_off_computer,
input arrived,
input gas_tank_empty,
output reg keep_driving
); //
always @(*) begin
if (cpu_overheated) shut_off_computer = 1;
end
always @(*) begin
if (~arrived) keep_driving = ~gas_tank_empty;
end
endmodule
| 7.203305
|
module top_module (
input [2:0] sel,
input [3:0] data0,
input [3:0] data1,
input [3:0] data2,
input [3:0] data3,
input [3:0] data4,
input [3:0] data5,
output reg [3:0] out
); //
always @(*) begin // This is a combinational circuit
case (sel)
3'b000: out = data0;
3'b001: out = data1;
3'b010: out = data2;
3'b011: out = data3;
3'b100: out = data4;
3'b101: out = data5;
default: out = 4'b0000;
endcase
end
endmodule
| 7.203305
|
module top_module (
input [3:0] in,
output reg [1:0] pos
);
always @(*) begin
pos = (in[0] & 1) ? 2'd0 : (in[1] & 1) ? 2'd1 : (in[2] & 1) ? 2'd2 : (in[3] & 1) ? 2'd3 : 2'd0;
end
endmodule
| 7.203305
|
module top_module (
input [7:0] in,
output reg [2:0] pos
);
// casez treats bits that have the value z as don't-care in the comparison.
//Notice how there are certain inputs (e.g., 4'b1111) that will match more than one case item.
//The first match is chosen (so 4'b1111 matches the first item, out = 0, but not any of the later ones).
//There is also a similar casex that treats both x and z as don't-care. I don't see much purpose to using it over casez.
//The digit ? is a synonym for z. so 2'bz0 is the same as 2'b?0
always @(*) begin
casez (in[7:0])
8'bzzzzzzz1: pos = 0;
8'bzzzzzz1z: pos = 1;
8'bzzzzz1zz: pos = 2;
8'bzzzz1zzz: pos = 3;
8'bzzz1zzzz: pos = 4;
8'bzz1zzzzz: pos = 5;
8'bz1zzzzzz: pos = 6;
8'b1zzzzzzz: pos = 7;
default: pos = 0;
endcase
end
endmodule
| 7.203305
|
module top_module (
input [15:0] scancode,
output reg left,
output reg down,
output reg right,
output reg up
);
always @(*) begin
up = 1'b0;
down = 1'b0;
left = 1'b0;
right = 1'b0;
case (scancode)
16'he06b: left = 1'b1;
16'he072: down = 1'b1;
16'he074: right = 1'b1;
16'he075: up = 1'b1;
endcase
end
endmodule
| 7.203305
|
module top_module (
input [7:0] a,
b,
c,
d,
output [7:0] min
); //
wire [7:0] min1 = (a < b) ? a : b;
wire [7:0] min2 = (c < d) ? c : d;
assign min = (min1 < min2) ? min1 : min2;
endmodule
| 7.203305
|
module top_module (
input [7:0] in,
output parity
);
assign parity = ^in;
endmodule
| 7.203305
|
module top_module (
input [99:0] in,
output out_and,
output out_or,
output out_xor
);
assign {out_and, out_or, out_xor} = {&in, |in, ^in};
endmodule
| 7.203305
|
module top_module (
input [99:0] in,
output [99:0] out
);
integer i;
always @(in) begin
for (i = 0; i < 100; i++) begin
out[i] = in[99-i];
end
end
endmodule
| 7.203305
|
module top_module (
input [254:0] in,
output reg [7:0] out
);
always @(*) begin // Combinational always block
out = 0;
for (int i = 0; i < 255; i++) out = out + in[i];
end
endmodule
| 7.203305
|
module top_module (
input [99:0] a,
b,
input cin,
output [99:0] cout,
output [99:0] sum
);
integer i;
always @(*) begin
sum[0] = a[0] ^ b[0] ^ cin;
cout[0] = a[0] & b[0] | cin & (a[0] | b[0]);
for (i = 1; i < 100; i++) begin
sum[i] = a[i] ^ b[i] ^ cout[i-1];
cout[i] = a[i] & b[i] | cout[i-1] & (a[i] | b[i]);
end
end
endmodule
| 7.203305
|
module top_module (
input [399:0] a,
b,
input cin,
output cout,
output [399:0] sum
);
wire [99:0] cout_wires;
genvar i;
generate
bcd_fadd(
a[3:0], b[3:0], cin, cout_wires[0], sum[3:0]
);
for (i = 4; i < 400; i = i + 4) begin : bcd_adder_instances
bcd_fadd bcd_adder (
a[i+3:i],
b[i+3:i],
cout_wires[i/4-1],
cout_wires[i/4],
sum[i+3:i]
);
end
endgenerate
assign cout = cout_wires[99];
endmodule
| 7.203305
|
module top_module (
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
output reg walk_left,
output reg walk_right,
output reg aaah
);
reg walk_temp[1:0];
initial begin
walk_left = 1;
walk_right = 0;
aaah = 0;
walk_temp[0] = walk_left;
walk_temp[1] = walk_right;
end
always @(posedge clk) begin
if (areset) begin
walk_left = 1;
walk_right = 0;
end else begin
if (ground == 0) begin
if (aaah == 0) begin
walk_temp[0] = walk_left;
walk_temp[1] = walk_right;
aaah = 1;
end
walk_left = 0;
walk_right = 0;
end else begin
if (aaah == 1) begin
walk_left = walk_temp[0];
walk_right = walk_temp[1];
aaah = 0;
end else begin
if (walk_left) begin
if (bump_left) begin
walk_left = 0;
walk_right = 1;
end
end else begin
if (bump_right) begin
walk_left = 1;
walk_right = 0;
end
end
end
end
end
end
endmodule
| 7.203305
|
module top_module (
input a,
input b,
output out
);
mod_a(
.in1(a), .in2(b), .out(out)
);
endmodule
| 7.203305
|
module top_module (
input a,
input b,
output out
);
mod_a instance1 (
.in1(a),
.in2(b),
.out(out)
);
endmodule
| 7.203305
|
module DECODER (
sel,
out
);
input [3:0] sel;
output [15:0] out;
reg [15:0] out;
always @(sel) begin
case (sel)
4'h0: out = 16'h8000;
4'h1: out = 16'h4000;
4'h2: out = 16'h2000;
4'h3: out = 16'h1000;
4'h4: out = 16'h0800;
4'h5: out = 16'h0400;
4'h6: out = 16'h0200;
4'h7: out = 16'h0100;
4'h8: out = 16'h0080;
4'h9: out = 16'h0040;
4'hA: out = 16'h0020;
4'hB: out = 16'h0010;
4'hC: out = 16'h0008;
4'hD: out = 16'h0004;
4'hE: out = 16'h0002;
4'hF: out = 16'h0001;
endcase
end
endmodule
| 6.800244
|
module MEMORY (
WE,
DataToWrite,
RegSel,
ReadData
);
input WE;
input [7:0] DataToWrite;
input [15:0] RegSel;
output [7:0] ReadData;
reg [7:0] ReadData;
reg [7:0] Mem[0:15];
always @(WE or DataToWrite or RegSel) begin
case (RegSel)
16'h8000: begin
if (WE) Mem[4'h0] = DataToWrite;
{ReadData} = Mem[4'h0];
end
16'h4000: begin
if (WE) Mem[4'h1] = DataToWrite;
{ReadData} = Mem[4'h1];
end
16'h2000: begin
if (WE) Mem[4'h2] = DataToWrite;
{ReadData} = Mem[4'h2];
end
16'h1000: begin
if (WE) Mem[4'h3] = DataToWrite;
{ReadData} = Mem[4'h3];
end
16'h0800: begin
if (WE) Mem[4'h4] = DataToWrite;
{ReadData} = Mem[4'h4];
end
16'h0400: begin
if (WE) Mem[4'h5] = DataToWrite;
{ReadData} = Mem[4'h5];
end
16'h0200: begin
if (WE) Mem[4'h6] = DataToWrite;
{ReadData} = Mem[4'h6];
end
16'h0100: begin
if (WE) Mem[4'h7] = DataToWrite;
{ReadData} = Mem[4'h7];
end
16'h0080: begin
if (WE) Mem[4'h8] = DataToWrite;
{ReadData} = Mem[4'h8];
end
16'h0040: begin
if (WE) Mem[4'h9] = DataToWrite;
{ReadData} = Mem[4'h9];
end
16'h0020: begin
if (WE) Mem[4'hA] = DataToWrite;
{ReadData} = Mem[4'hA];
end
16'h0010: begin
if (WE) Mem[4'hB] = DataToWrite;
{ReadData} = Mem[4'hB];
end
16'h0008: begin
if (WE) Mem[4'hC] = DataToWrite;
{ReadData} = Mem[4'hC];
end
16'h0004: begin
if (WE) Mem[4'hD] = DataToWrite;
{ReadData} = Mem[4'hD];
end
16'h0002: begin
if (WE) Mem[4'hE] = DataToWrite;
{ReadData} = Mem[4'hE];
end
16'h0001: begin
if (WE) Mem[4'hF] = DataToWrite;
{ReadData} = Mem[4'hF];
end
endcase
end
endmodule
| 6.805941
|
module DATAPATH (
Num,
Key,
StoredValue
);
input [3:0] Num, Key;
output [7:0] StoredValue;
reg clock, EN, WE;
reg [3:0] sel;
wire [3:0] RegOut, RotOut1, RotOut2;
wire [ 7:0] Encrypt;
wire [15:0] Addr;
initial begin
#0 clock = 1'b1;
EN = 1'b1;
WE = 1'b1;
sel = 4'h8;
end
always begin
#2 clock = ~clock;
end
REG1 mod1 (
clock,
EN,
Num,
RegOut
);
ROTATOR mod2 (
clock,
EN,
RegOut,
RotOut1
);
ROTATOR mod3 (
clock,
EN,
RotOut1,
RotOut2
);
MULTIPLIER mod4 (
RotOut2,
Key,
Encrypt
);
DECODER mod5 (
sel,
Addr
);
MEMORY mod6 (
WE,
Encrypt,
Addr,
StoredValue
);
endmodule
| 6.685613
|
module top_module (
input [4:1] x,
output f
);
assign f = (~x[1]) & x[3] | (~x[2]) & (~x[4]) | x[1] & x[2] & x[3] & x[4];
endmodule
| 7.203305
|
module top_module (
input [5:0] y,
input w,
output Y1,
output Y3
);
assign Y1 = y[0] & w;
assign Y3 = y[1] & (~w) | y[2] & (~w) | y[4] & (~w) | y[5] & (~w);
endmodule
| 7.203305
|
module top_module (
input clk,
input reset, // synchronous reset
input w,
output z
);
parameter a = 3'b000, b = 3'b001, c = 3'b010, d = 3'b011, e = 3'b100, f = 3'b101;
reg [2:0] state, next_state;
always @(*) begin
case ({
state, w
})
{a, 1'b0} : next_state = a;
{a, 1'b1} : next_state = b;
{b, 1'b0} : next_state = d;
{b, 1'b1} : next_state = c;
{c, 1'b0} : next_state = d;
{c, 1'b1} : next_state = e;
{d, 1'b0} : next_state = a;
{d, 1'b1} : next_state = f;
{e, 1'b0} : next_state = d;
{e, 1'b1} : next_state = e;
{f, 1'b0} : next_state = d;
{f, 1'b1} : next_state = c;
endcase
end
always @(posedge clk) begin
if (reset) state <= a;
else state <= next_state;
end
assign z = (state == e || state == f);
endmodule
| 7.203305
|
module top_module (
input clk,
input resetn, // active-low synchronous reset
input [3:1] r, // request
output [3:1] g // grant
);
parameter a = 2'd0, b = 2'd1, c = 2'd2, d = 2'd3;
reg [1:0] state, next_state;
always @(*) begin
case (state)
a: begin
if (r[1]) next_state = b;
else if (~r[1] & r[2]) next_state = c;
else if (~r[1] & ~r[2] & r[3]) next_state = d;
else next_state = a;
end
b: begin
if (r[1]) next_state = b;
else next_state = a;
end
c: begin
if (r[2]) next_state = c;
else next_state = a;
end
d: begin
if (r[3]) next_state = d;
else next_state = a;
end
endcase
end
always @(posedge clk) begin
if (~resetn) state <= a;
else state <= next_state;
end
assign g[1] = (state == b);
assign g[2] = (state == c);
assign g[3] = (state == d);
endmodule
| 7.203305
|
module top_module (
input clk,
input resetn, // active-low synchronous reset
input x,
input y,
output reg f,
output reg g
);
parameter A=4'd0, f1=4'd1, tmp0=4'd2, tmp1=4'd3, tmp2=4'd4, g1=4'd5, g1p=4'd6, tmp3=4'd7, g0p=4'd8;
reg [3:0] state, next_state;
always @(*) begin
case (state)
A: begin
if (resetn) next_state = f1;
else next_state = A;
end
f1: next_state = tmp0;
tmp0: begin
if (x) next_state = tmp1;
else next_state = tmp0;
end
tmp1: begin
if (~x) next_state = tmp2;
else next_state = tmp1;
end
tmp2: begin
if (x) next_state = g1;
else next_state = tmp0;
end
g1: begin
if (y) next_state = g1p;
else next_state = tmp3;
end
tmp3: begin
if (y) next_state = g1p;
else next_state = g0p;
end
g1p: begin
if (~resetn) next_state = A;
else next_state = g1p;
end
g0p: begin
if (~resetn) next_state = A;
else next_state = g0p;
end
endcase
end
always @(posedge clk) begin
if (~resetn) state <= A;
else state <= next_state;
end
always @(posedge clk) begin
case (next_state)
f1: f <= 1'b1;
g1, tmp3, g1p: g <= 1'b1;
g0p: g <= 1'b0;
default: begin
f <= 1'b0;
g <= 1'b0;
end
endcase
end
endmodule
| 7.203305
|
module top_module (
input clk,
input reset, // Synchronous reset
input x,
output z
);
parameter y0 = 3'd0, y1 = 3'd1, y2 = 3'd2, y3 = 3'd3, y4 = 3'd4;
reg [2:0] state, next_state;
always @(*) begin
case ({
state, x
})
{y0, 1'b0} : next_state = y0;
{y0, 1'b1} : next_state = y1;
{y1, 1'b0} : next_state = y1;
{y1, 1'b1} : next_state = y4;
{y2, 1'b0} : next_state = y2;
{y2, 1'b1} : next_state = y1;
{y3, 1'b0} : next_state = y1;
{y3, 1'b1} : next_state = y2;
{y4, 1'b0} : next_state = y3;
{y4, 1'b1} : next_state = y4;
endcase
end
always @(posedge clk) begin
if (reset) state <= y0;
else state <= next_state;
end
assign z = (state == y3 || state == y4);
endmodule
| 7.203305
|
module top_module (
input clk,
input [2:0] y,
input x,
output Y0,
output z
);
reg [2:0] Y;
always @(*) begin
case ({
y, x
})
4'b0000: Y = 3'b000;
4'b0001: Y = 3'b001;
4'b0010: Y = 3'b001;
4'b0011: Y = 3'b100;
4'b0100: Y = 3'b010;
4'b0101: Y = 3'b001;
4'b0110: Y = 3'b001;
4'b0111: Y = 3'b010;
4'b1000: Y = 3'b011;
4'b1001: Y = 3'b100;
endcase
end
assign z = (y == 3'b011 || y == 3'b100);
assign Y0 = Y[0];
endmodule
| 7.203305
|
module top_module (
input clk,
input reset, // Synchronous reset
input s,
input w,
output z
);
parameter a = 1'b0, b = 1'b1;
reg state, next_state;
reg [2:0] w3 = 0;
reg [1:0] count = 0;
always @(*) begin
case ({
state, s
})
{a, 1'b0} : next_state = a;
{a, 1'b1} : next_state = b;
{b, 1'b0} : next_state = b;
{b, 1'b1} : next_state = b;
endcase
end
always @(posedge clk) begin
if (reset) state <= a;
else state <= next_state;
end
always @(posedge clk) begin
if (reset) w3 <= 3'b0;
else if (next_state == b) w3 <= {w3[1:0], w};
end
always @(posedge clk) begin
if (reset) count <= 2'd0;
else if (next_state == b) begin
if (count == 3) count <= 2'd1;
else begin
count <= count + 1'b1;
end
end
end
assign z = (count == 1 && (w3 == 3'b011 || w3 == 3'b101 || w3 == 3'b110));
endmodule
| 7.203305
|
module top_module (
input clk,
input w,
R,
E,
L,
output Q
);
wire out1, out2;
always @(posedge clk) begin
case (E)
1'b0: begin
out1 = Q;
end
1'b1: begin
out1 = w;
end
endcase
case (L)
1'b0: begin
Q = out1;
end
1'b1: begin
Q = R;
end
endcase
end
endmodule
| 7.203305
|
module top_module (
input [3:0] SW,
input [3:0] KEY,
output [3:0] LEDR
);
MUXDFF ins0 (
.clk(KEY[0]),
.E (KEY[1]),
.L (KEY[2]),
.w (LEDR[1]),
.R (SW[0]),
.Q (LEDR[0])
);
MUXDFF ins1 (
.clk(KEY[0]),
.E (KEY[1]),
.L (KEY[2]),
.w (LEDR[2]),
.R (SW[1]),
.Q (LEDR[1])
);
MUXDFF ins2 (
.clk(KEY[0]),
.E (KEY[1]),
.L (KEY[2]),
.w (LEDR[3]),
.R (SW[2]),
.Q (LEDR[2])
);
MUXDFF ins3 (
.clk(KEY[0]),
.E (KEY[1]),
.L (KEY[2]),
.w (KEY[3]),
.R (SW[3]),
.Q (LEDR[3])
);
endmodule
| 7.203305
|
module cpu //Do not change top module name or ports.
(
input clk,
input areset,
output [7:0] imem_addr, //Request instruction memory
input [7:0] imem_data, //Returns
output [7:0] tb_data //Testbench wiring.
);
//Data memory and testbench wiring. you may rename them if you like.
wire dmem_write;
wire [7:0] dmem_addr, dmem_write_data, dmem_read_data;
wire Jump, ALUSrc, RegDst, MemtoReg, RegWrite;
wire [7:0] MUXtoPC, PC_out, Sign_out;
wire [7:0] MUXtoAdder, AddertoMUX;
wire [7:0] RFtoALU, MUXtoALU;
wire [7:0] MUXtoRF;
wire [1:0] MUX2toRF, MUX3toRF, ALUOp;
//Data memory module in tb.v.
memory dmem (
.clk(clk),
.areset(areset),
.write(dmem_write),
.addr(dmem_addr),
.write_data(dmem_write_data),
.read_data(dmem_read_data)
);
assign tb_data = dmem_read_data;
//Testbench wiring end.
//Write your code here.
ProgramCounter PC (
.CLK(clk),
.in (MUXtoPC),
.out(PC_out)
);
RegisterFile RF (
.CLK(clk),
.ReadReg1(imem_data[3:2]),
.ReadReg2(MUX2toRF),
.Write_enable(RegWrite),
.WriteReg(MUX3toRF),
.WriteData(MUXtoRF),
.areset(areset),
.ReadData1(RFtoALU),
.ReadData2(dmem_write_data)
);
ControlLogic CL (
.Mode(imem_data[7:6]),
.OpCode(imem_data[5:4]),
.Jump(Jump),
.ALUSrc(ALUSrc),
.ALUOp(ALUOp),
.MemWrite(dmem_write),
.RegDst(RegDst),
.MemtoReg(MemtoReg),
.RegWrite(RegWrite)
);
SignExtensionUnit SEU (
.in (imem_data[5:0]),
.Jump(Jump),
.out (Sign_out)
);
ALU alu (
.opcode(ALUOp),
.ain(RFtoALU),
.bin(MUXtoALU),
.result(dmem_addr)
);
EightBitMUX mux1 (
.control(areset),
.in0(AddertoMUX),
.in1(8'h00),
.out(MUXtoPC)
);
TwoBitMUX mux2 (
.control(dmem_write),
.in0(imem_data[1:0]),
.in1(imem_data[5:4]),
.out(MUX2toRF)
);
TwoBitMUX mux3 (
.control(RegDst),
.in0(imem_data[5:4]),
.in1(imem_data[3:2]),
.out(MUX3toRF)
);
EightBitMUX mux4 (
.control(MemtoReg),
.in0(dmem_addr),
.in1(dmem_read_data),
.out(MUXtoRF)
);
EightBitMUX mux5 (
.control(ALUSrc),
.in0(Sign_out),
.in1(dmem_write_data),
.out(MUXtoALU)
);
EightBitMUX mux6 (
.control(Jump),
.in0(8'h01),
.in1(Sign_out),
.out(MUXtoAdder)
);
EightBitAdder adder (
.a(PC_out),
.b(MUXtoAdder),
.s(AddertoMUX)
);
assign imem_addr = PC_out;
endmodule
| 7.390669
|
module RegisterFile (
input CLK,
input [1:0] ReadReg1,
input [1:0] ReadReg2,
input Write_enable,
input [1:0] WriteReg,
input [7:0] WriteData,
input areset,
output [7:0] ReadData1,
output [7:0] ReadData2
);
reg [7:0] registers[3:0];
initial begin
registers[0] <= 8'b00000000;
registers[1] <= 8'b00000000;
registers[2] <= 8'b00000000;
registers[3] <= 8'b00000000;
end
assign ReadData1 = registers[ReadReg1];
assign ReadData2 = registers[ReadReg2];
always @(posedge areset or posedge CLK) begin
if (areset == 1'b1) begin
registers[0] = 8'b00000000;
registers[1] = 8'b00000000;
registers[2] = 8'b00000000;
registers[3] = 8'b00000000;
end else if (Write_enable == 1'b1) begin
registers[WriteReg] = WriteData;
end
end
endmodule
| 8.108491
|
module SignExtensionUnit (
input [5:0] in,
input Jump,
output reg [7:0] out
);
always @(*) begin
if (Jump == 1'b1) begin
out[5:0] <= in[5:0];
out[7:6] <= {2{in[5]}};
end else begin
out[1:0] <= in[1:0];
out[7:2] <= {6{in[1]}};
end
end
endmodule
| 6.562271
|
module ALU (
input [1:0] opcode,
input [7:0] ain,
bin,
output [7:0] result
);
wire b_l;
assign b_l = ~(bin) + 1;
assign result = (opcode==2'b01) ? (ain+bin) :
(opcode==2'b10) ? (ain-bin) :
(bin[7]==1) ? (ain - (b_l)) :
(ain+bin);
endmodule
| 7.960621
|
module TwoBitMUX (
input control,
input [1:0] in0,
input [1:0] in1,
output reg [1:0] out
);
always @(control or in0 or in1) begin
if (control == 0) begin
out <= in0;
end else begin
out <= in1;
end
end
endmodule
| 7.296648
|
module EightBitMUX (
input control,
input [7:0] in0,
input [7:0] in1,
output reg [7:0] out
);
always @(control or in0 or in1) begin
if (control == 0) begin
out <= in0;
end else begin
out <= in1;
end
end
endmodule
| 6.94892
|
module EightBitAdder (
input [7:0] a,
b,
output [7:0] s
);
assign s = a + b;
endmodule
| 7.369945
|
module MUX_2x1 (
sel,
in1,
in2,
out
);
input sel, in1, in2;
output out;
assign out = (~sel & in1) | (sel & in2);
endmodule
| 7.991836
|
module MUX_8x1 (
sel,
in,
out
);
input [2:0] sel;
input [7:0] in;
output out;
assign out = (sel[2] ? (sel[1] ? (sel[0] ? in[7] : in[6]) : (sel[0] ? in[5] : in[4])) : (sel[1] ? (sel[0] ? in[3] : in[2]) : (sel[0] ? in[1] : in[0])));
endmodule
| 6.799729
|
module COUNTER_3BIT (
Q,
clock,
clear
);
output [2:0] Q;
input clock, clear;
reg [2:0] Q;
initial Q = 3'b0;
always @(posedge clock or posedge clear) begin
if (clear) Q = 3'b0;
else Q = (Q + 1) % 8;
end
endmodule
| 6.61054
|
module DECODER (
EN,
A,
B
);
input EN;
input [2:0] A;
output [7:0] B;
reg [7:0] B;
always @(A) begin
if (EN == 0) B = 8'b00000000;
else begin
case (A)
3'b000: B = 8'b00000001;
3'b001: B = 8'b00000010;
3'b010: B = 8'b00000100;
3'b011: B = 8'b00001000;
3'b100: B = 8'b00010000;
3'b101: B = 8'b00100000;
3'b110: B = 8'b01000000;
3'b111: B = 8'b10000000;
endcase
end
end
endmodule
| 6.800244
|
module MEMORY (
S,
G
);
input [2:0] S;
output [7:0] G;
reg [7:0] mem[0:7];
reg [7:0] G;
//Initialize the memory
initial begin
mem[0] = 8'b00000001; //2'h01;
mem[1] = 8'b00000011; //2'h03;
mem[2] = 8'b00000111; //2'h07;
mem[3] = 8'b00001111; //2'h0F;
mem[4] = 8'b00011111; //2'h1F;
mem[5] = 8'b00111111; //2'h3F;
mem[6] = 8'b01111111; //2'h7F;
mem[7] = 8'b11111111; //2'hFF;
end
always @(S) begin
case (S)
3'b000: G = mem[0];
3'b001: G = mem[1];
3'b010: G = mem[2];
3'b011: G = mem[3];
3'b100: G = mem[4];
3'b101: G = mem[5];
3'b110: G = mem[6];
3'b111: G = mem[7];
endcase
end
endmodule
| 6.805941
|
module TOP_MODULE (
clock,
clear,
S,
EN,
OUT
);
input clock, clear, EN;
input [2:0] S;
output OUT;
wire [2:0] Q;
wire [7:0] B, G, E;
MUX_8x1 M8 (
Q,
E,
OUT
);
MUX_ARRAY MA (
G,
B,
E
);
COUNTER_3BIT CNTR3 (
Q,
clock,
clear
);
DECODER DEC (
EN,
Q,
B
);
MEMORY MEM (
S,
G
);
endmodule
| 6.955484
|
module parity (
A,
B,
C,
I,
P
);
//Inputs
input A;
input B;
input C;
input I;
//Outputs
output P;
//Components
wire w1;
wire w2;
xor g1 (w1, A, B);
xor g2 (w2, w1, C);
xor g3 (P, I, w2);
endmodule
| 6.788563
|
module parity_tb;
//Inputs as registers
reg A;
reg B;
reg C;
reg I;
//Ouputs as wires
wire P;
//Initialiastion
parity uut (
A,
B,
C,
I,
P
);
initial begin
$dumpfile("2019AAPS0331H_tb.vcd");
$dumpvars(0, parity_tb);
// Uncomment a paritcular sequence of Test Bench Inputs for the required result
// Even Parity
A = 0;
B = 0;
C = 0;
I = 0;
#10;
A = 0;
B = 0;
C = 1;
I = 0;
#10;
A = 0;
B = 1;
C = 0;
I = 0;
#10;
A = 0;
B = 1;
C = 1;
I = 0;
#10;
A = 1;
B = 0;
C = 0;
I = 0;
#10;
A = 1;
B = 0;
C = 1;
I = 0;
#10;
A = 1;
B = 1;
C = 0;
I = 0;
#10;
A = 1;
B = 1;
C = 1;
I = 0;
#10;
// Odd Parity
A = 0;
B = 0;
C = 0;
I = 1;
#10;
A = 0;
B = 0;
C = 1;
I = 1;
#10;
A = 0;
B = 1;
C = 0;
I = 1;
#10;
A = 0;
B = 1;
C = 1;
I = 1;
#10;
A = 1;
B = 0;
C = 0;
I = 1;
#10;
A = 1;
B = 0;
C = 1;
I = 1;
#10;
A = 1;
B = 1;
C = 0;
I = 1;
#10;
A = 1;
B = 1;
C = 1;
I = 1;
#10;
$display("Test complete");
end
endmodule
| 7.477246
|
module top (
key, //按键输入
rst, //复位输入
led //led输出
);
input key, rst;
output reg led;
always @(key or rst)
if (!rst) //复位时led熄灭
led = 1;
else if (key == 0) led = ~led; //按键按下时led翻转
else led = led;
endmodule
| 6.85746
|
module LockedBox (
Key1,
Key2,
Key3,
Key4,
LED,
Button1,
Button2,
Seg_Led
);
//输入端口
//四个拨杆开关 用于输入密码
input Key1;
input Key2;
input Key3;
input Key4;
//两个按钮 用于确认两重密码正确性
input Button1;
input Button2;
//输出端口 两个LED灯 代表打开与否 一个七段数码管 代表是否解锁
output [1:0] LED;
output [8:0] Seg_Led;
//两个锁的状态变量，1代表锁定，0代表开启 数码管的状态变量
reg Lock1;
reg Lock2;
reg [8:0] Seg_State;
//初始赋值
initial begin
Lock1 = 1'b1;
Lock2 = 1'b1;
Seg_State = 9'h39;
end
//LED控制函数（同一变量不能在多个always中同时赋值）
assign LED = {Lock1, Lock2};
//数码管赋值函数
assign Seg_Led = Seg_State;
//检测函数1 检测第一次密码 LED1亮起(0)代表密码1正确
always @(Button1) begin
if (Button1 == 1'b0) begin
if ({Key1, Key2, Key3, Key4} == 4'b1010) begin //1010密码1
Lock1 = 1'b0;
end else begin
Lock1 = 1'b1;
end
end
end
//检测函数2 检测第二次密码 LED2亮起(0)代表密码2正确
always @(Button2) begin
if ({Button2, Lock1} == 2'b00) begin
if ({Key1, Key2, Key3, Key4} == 4'b0101) begin //0101密码2
Lock2 = 1'b0;
end
end else begin
Lock2 = 1'b1;
end
end
//检测函数3 检测两个状态变量 如果都为0则开锁
always @(Lock1, Lock2) begin
if ({Lock1, Lock2} == 2'b00) begin
Seg_State = 9'h3f; //显示0 代表Open 开启
end else begin
Seg_State = 9'h39;
end
end
endmodule
| 8.15301
|
module PGU20 (
a,
b,
p,
g
);
input [19:0] a, b;
output [19:0] p, g;
assign p = a ^ b;
assign g = a & b;
endmodule
| 7.929464
|
module D1_20bit (
in,
clk,
out
);
input [19:0] in;
input clk;
output reg [19:0] out;
always @(posedge clk) begin
out <= in;
end
endmodule
| 6.778767
|
module SU20 (
p,
cin,
c,
s
);
input [19:0] p;
input cin;
input [18:0] c;
output [19:0] s;
assign s = p ^ {c, cin};
endmodule
| 7.195935
|
module DD5_3bit (
in,
clk,
out
);
input [2:0] in;
input clk;
output reg [2:0] out;
reg [2:0] r_data[0:3];
always @(posedge clk) begin
r_data[0] <= in;
r_data[1] <= r_data[0];
r_data[2] <= r_data[1];
r_data[3] <= r_data[2];
out <= r_data[3];
end
endmodule
| 6.867734
|
module DD5_20bit (
in,
clk,
out
);
input [19:0] in;
input clk;
output reg [19:0] out;
reg [19:0] r_data[0:3];
always @(posedge clk) begin
r_data[0] <= in;
r_data[1] <= r_data[0];
r_data[2] <= r_data[1];
r_data[3] <= r_data[2];
out <= r_data[3];
end
endmodule
| 6.860049
|
module DD4_4bit (
in,
clk,
out
);
input [3:0] in;
input clk;
output reg [3:0] out;
reg [3:0] r_data[0:2];
always @(posedge clk) begin
r_data[0] <= in;
r_data[1] <= r_data[0];
r_data[2] <= r_data[1];
out <= r_data[2];
end
endmodule
| 6.796279
|
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