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module top_module ();
// input
reg clk;
reg reset;
reg t;
// output
wire q;
// parameter
parameter PERIOD = 10;
initial begin
clk = 1'b0;
reset = 1'b0;
t = 1'b0;
end
// clk
always #(PERIOD / 2) clk = ~clk;
// reset
initial begin
#10 reset = 1;
#10 reset = 0;
end
// toggle
initial begin
#10 t = 1;
end
// instance
tff u_tff (
.clk(clk),
.reset(reset),
.t(t),
.q(q)
);
endmodule
| 6.627149
|
module top_module (
input clk,
input areset,
input predict_valid,
input predict_taken,
output [31:0] predict_history,
input train_mispredicted,
input train_taken,
input [31:0] train_history
);
reg [31:0] predict_history_reg;
always @(posedge clk, posedge areset) begin
if (areset) predict_history_reg <= 31'b0;
else if (train_mispredicted) predict_history_reg <= {train_history[30:0], train_taken};
else if (predict_valid) predict_history_reg <= {predict_history_reg[30:0], predict_taken};
else predict_history_reg <= predict_history_reg;
end
assign predict_history = predict_history_reg;
endmodule
| 7.203305
|
module top_module (
input clk,
input areset,
input predict_valid,
input predict_taken,
output [31:0] predict_history,
input train_mispredicted,
input train_taken,
input [31:0] train_history
);
reg [31:0] n_predict_history;
always @(*) begin
if (train_mispredicted) n_predict_history = {train_history[30:0], train_taken};
else if (predict_valid) n_predict_history = {predict_history[30:0], predict_taken};
else n_predict_history = predict_history;
end
always @(posedge clk, posedge areset) begin
if (areset) predict_history <= 0;
else predict_history <= n_predict_history;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input areset,
input predict_valid,
input [6:0] predict_pc,
output predict_taken,
output [6:0] predict_history,
input train_valid,
input train_taken,
input train_mispredicted,
input [6:0] train_history,
input [6:0] train_pc
);
reg [1:0] PHT[127:0];
integer i;
always @(posedge clk, posedge areset) begin
if (areset) begin
predict_history <= 0;
for (i = 0; i < 128; i = i + 1) PHT[i] <= 2'b01;
end else begin
if (train_valid && train_mispredicted) predict_history <= {train_history[6:0], train_taken};
else if (predict_valid) predict_history <= {predict_history[6:0], predict_taken};
if (train_valid) begin
if (train_taken)
PHT[train_history ^ train_pc] <= (PHT[train_history ^ train_pc] == 2'b11) ? 2'b11 : (PHT[train_history ^ train_pc] + 1);
else
PHT[train_history ^ train_pc] <= (PHT[train_history ^ train_pc] == 2'b00) ? 2'b00 : (PHT[train_history ^ train_pc] - 1);
end
end
end
assign predict_taken = PHT[predict_history^predict_pc][1];
endmodule
| 7.203305
|
module top_module (
input clk,
input areset,
input predict_valid,
input [(N-1):0] predict_pc,
output predict_taken,
output [(N-1):0] predict_history,
input train_valid,
input train_taken,
input train_mispredicted,
input [(N-1):0] train_history,
input [(N-1):0] train_pc
);
parameter N = 7;
parameter SNT = 2'b00, WNT = 2'b01, WT = 2'b10, ST = 2'b11;
reg [1:0] pht[(2**N-1):0];
wire [(N-1):0] index_train, index_predict;
reg [(2**N-1):0] onehot_index_train, onehot_train_valid;
//train
assign index_train = train_pc ^ train_history;
generate
genvar i;
for (i = 0; i < 2 ** N; i++) begin : onehot_index_train_0
assign onehot_index_train[i] = (i == index_train);
end
endgenerate
assign onehot_train_valid = {2 ** N{train_valid}} & onehot_index_train;
counter_2bc #(
.SNT(SNT),
.WNT(WNT),
.WT (WT),
.ST (ST)
) counter_2bc_u0[(2**N-1):0] (
.clk({2 ** N{clk}}),
.areset({2 ** N{areset}}),
.train_valid(onehot_train_valid),
.train_taken({2 ** N{train_taken}}),
.state(pht)
);
//predict
history_shift #(
.N(N)
) history_shift_u0 (
.clk(clk),
.areset(areset),
.predict_valid(predict_valid),
.predict_taken(predict_taken),
.train_valid(train_valid),
.train_mispredicted(train_mispredicted),
.train_taken(train_taken),
.train_history(train_history),
.predict_history(predict_history)
);
assign index_predict = predict_pc ^ predict_history;
assign predict_taken = pht[index_predict][1];
endmodule
| 7.203305
|
module counter_2bc #(
parameter SNT = 2'b00,
WNT = 2'b01,
WT = 2'b10,
ST = 2'b11
) (
input clk,
input areset,
input train_valid,
input train_taken,
output reg [1:0] state
);
reg [1:0] n_state;
always @(*) begin
if (train_valid) begin
case (state)
SNT: n_state = (train_taken) ? WNT : SNT;
WNT: n_state = (train_taken) ? WT : SNT;
WT: n_state = (train_taken) ? ST : WNT;
ST: n_state = (train_taken) ? ST : WT;
endcase
end else n_state = state;
end
always @(posedge clk, posedge areset) begin
if (areset) state <= WNT;
else state <= n_state;
end
endmodule
| 6.553139
|
module history_shift #(
parameter N = 7
) (
input clk,
input areset,
input predict_valid,
input predict_taken,
output [(N-1):0] predict_history,
input train_valid,
input train_mispredicted,
input train_taken,
input [(N-1):0] train_history
);
reg [(N-1):0] n_predict_history;
always @(*) begin
if (train_valid & train_mispredicted) n_predict_history = {train_history[(N-2):0], train_taken};
else if (predict_valid) n_predict_history = {predict_history[(N-2):0], predict_taken};
else n_predict_history = predict_history;
end
always @(posedge clk, posedge areset) begin
if (areset) predict_history <= 0;
else predict_history <= n_predict_history;
end
endmodule
| 6.629959
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((!(opcode == 'b010001011)) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ('0 && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module pre_adder (
mode,
dir,
a,
b,
c
);
input mode;
input dir;
input [18 : 0] a;
input [17 : 0] b;
input [18 : 0] c;
assign c = mode ? (dir ? a - b : a + b) : a;
endmodule
| 6.718407
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ('1 && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (!(mod == 1)));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && '0);
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && '1);
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) || (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module HA (
input a,
b,
output c_out,
s
);
assign s = a ^ b;
assign c_out = a & b;
endmodule
| 9.138493
|
module FA (
input a,
b,
c_in,
output c_out,
s
);
wire wire_1;
wire wire_2;
wire wire_3;
assign wire_1 = a ^ b;
assign wire_2 = wire_1 & c_in;
assign wire_3 = a & b;
assign c_out = wire_2 | wire_3;
assign s = wire_1 ^ c_in;
endmodule
| 8.362615
|
module Adder_2_bits (
input [1:0] a,
b,
input c_in,
output [1:0] s,
output c_out
);
FA fa_00 (
a[0],
b[0],
c_in,
c0,
s[0]
);
FA fa_01 (
a[1],
b[1],
c0,
c_out,
s[1]
);
endmodule
| 7.402012
|
module fsm (
clk,
rst,
in1,
in2,
out1,
out2
);
input clk;
input rst;
input in1, in2;
output reg out1, out2;
reg [1:0] state, next_state; // Register that holds the current state.
// State encodings
localparam STATE_S0 = 2'd0;
localparam STATE_S1 = 2'd1;
localparam STATE_S2 = 2'd2;
// Combinational part of the FSM
always @(*) begin
// Default values (to avoid latches)
next_state = state;
out1 = 1'b0;
out2 = 2'b0;
case (state)
// For each possible state, set the proper value
// of the `next_state` signal as well as the outputs.
STATE_S0: begin
if (in1) begin
next_state = STATE_S1;
end
out1 = 1'b1;
end
STATE_S1: begin
out2 = 1'b1;
next_state = STATE_S2;
end
STATE_S2: begin
if (in1 & in2) begin
next_state = STATE_S1;
end else if (~in1) begin
next_state = STATE_S0;
end
out1 = 1'b1;
end
endcase
end
// Non-combinational part of the FSM
always @(posedge clk or posedge rst) begin
if (rst) begin
state = STATE_S1; // Initial state
end else begin
state = next_state;
end
end
endmodule
| 7.213172
|
module top_module (
input clk,
input in,
input reset, // Synchronous reset
output [7:0] out_byte,
output done
); //
// Use FSM from Fsm_serial
parameter IDLE = 5'b00001;
parameter START = 5'b00010;
parameter DATA = 5'b00100;
parameter WAIT = 5'b01000;
parameter STOP = 5'b10000;
reg [4:0] cstate;
reg [4:0] nstate;
reg [3:0] data_cnt;
reg [7:0] o_byte;
reg data_ena;
reg data_end;
reg o_done;
assign data_ena = (cstate == DATA);
assign done = o_done;
assign out_byte = o_byte;
always @(posedge clk) begin
if (reset) begin
cstate <= IDLE;
end else begin
cstate <= nstate;
end
end
always @(*) begin
case (cstate)
IDLE: nstate = in ? IDLE : START;
START: nstate = DATA;
DATA: nstate = data_end ? (in ? STOP : WAIT) : DATA;
WAIT: nstate = in ? IDLE : WAIT;
STOP: nstate = in ? IDLE : START;
endcase
end
always @(posedge clk) begin
if (reset) begin
data_cnt <= 4'b0000;
data_end <= 1'b0;
end else begin
if (data_ena) begin
if (data_cnt == 6) begin
data_end <= 1'b1;
end else begin
data_cnt <= data_cnt + 1'b1;
end
end else begin
data_cnt <= 4'b0000;
data_end <= 1'b0;
end
end
end
always @(posedge clk) begin
if (reset) begin
o_done <= 1'b0;
end else begin
if (nstate == STOP) begin
o_done <= 1'b1;
end else begin
o_done <= 1'b0;
end
end
end
always @(posedge clk) begin
if (reset) begin
o_byte <= 8'b0;
end else begin
if (nstate == DATA) begin
o_byte <= {in, o_byte[7:1]};
end
end
end
endmodule
| 7.203305
|
module top_module (
input clk,
input in,
input reset, // Synchronous reset
output [7:0] out_byte,
output done
); //
// Modify FSM and datapath from Fsm_serialdata
parameter start=0, bit1=1, bit2=2, bit3=3, bit4=4, bit5=5, bit6=6, bit7=7, bit8=8, stop=9, idle=10, WAIT=11, bit9=12;
reg [3:0] state, nextstate;
reg [7:0] data;
reg odd, tempodd;
reg oddreset;
always @(*) begin
case (state)
start: nextstate = bit1;
bit1: nextstate = bit2;
bit2: nextstate = bit3;
bit3: nextstate = bit4;
bit4: nextstate = bit5;
bit5: nextstate = bit6;
bit6: nextstate = bit7;
bit7: nextstate = bit8;
bit8: nextstate = bit9;
bit9: nextstate = in ? stop : WAIT;
WAIT: nextstate = in ? idle : WAIT;
stop: nextstate = in ? idle : start;
idle: nextstate = in ? idle : start;
default: nextstate = idle;
endcase
end
parity oddcheck (
clk,
(reset | oddreset),
in,
tempodd
);
always @(posedge clk) begin
if (reset) state <= idle;
else begin
state <= nextstate;
if (nextstate == bit1 || nextstate == bit2 || nextstate == bit3 || nextstate == bit4 || nextstate == bit5 || nextstate == bit6 || nextstate == bit7 || nextstate == bit8) begin
data <= {in, data[7], data[6], data[5], data[4], data[3], data[2], data[1]};
end else data <= data;
end
end
always @(posedge clk) begin
if (reset) odd <= 0;
else odd <= tempodd;
end
//Only the IDLE-state and STOP-state are likely to enter the RECEIVE-state,
//so we need to reset the bits to avoid the previous result's affection.
always @(posedge clk) begin
case (nextstate)
idle: oddreset <= 1;
stop: oddreset <= 1;
default: oddreset <= 0;
endcase
end
assign done = (state == stop) && odd;
assign out_byte = done ? data : 8'bx;
// New: Add parity checking.
endmodule
| 7.203305
|
module top_module (
input a,
b,
c,
d,
e,
output [24:0] out
); //
// The output is XNOR of two vectors created by
// concatenating and replicating the five inputs.
// assign out = ~{ ... } ^ { ... };
assign out = {{5{a}}, {5{b}}, {5{c}}, {5{d}}, {5{e}}} ~^ {5{a, b, c, d, e}};
endmodule
| 7.203305
|
module top_module (
input a,
b,
c,
d,
e,
output [24:0] out
); //
// The output is XNOR of two vectors created by
// concatenating and replicating the five inputs.
// assign out = ~{ ... } ^ { ... };
wire [24:0] top, bottom;
assign top = {{5{a}}, {5{b}}, {5{c}}, {5{d}}, {5{e}}};
assign bottom = {5{a, b, c, d, e}};
assign out = ~top ^ bottom;
endmodule
| 7.203305
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = (~((opcode == 'b010001001) && (mod == 3)));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = '0;
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = '1;
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module DMUX_tb ();
reg clk;
reg rst_n;
reg [3:0] din;
wire dout;
initial begin
clk = 0;
rst_n = 1;
din = 4'b1010;
#10 rst_n = 0;
#10 rst_n = 1;
end
always #2 clk <= ~clk;
initial $monitor("din=%b,dout=%b", din, dout);
DMUX dut (
.clk (clk),
.rst_n(rst_n),
.din (din),
.dout (dout)
);
endmodule
| 6.622306
|
module top_module (
input clk,
input in,
input reset, // Synchronous reset
output [7:0] out_byte,
output done
); //
// Modify FSM and datapath from Fsm_serialdata
parameter IDLE = 6'b000001;
parameter START = 6'b000010;
parameter DATA = 6'b000100;
parameter CHECK = 6'b001000;
parameter WAIT = 6'b010000;
parameter STOP = 6'b100000;
reg [5:0] cstate;
reg [5:0] nstate;
reg [3:0] data_cnt;
reg [7:0] o_byte;
reg data_ena;
reg data_end;
reg o_done;
reg o_odd;
reg parity_ena;
parity p (
.clk(clk),
.reset(reset | parity_ena),
.in(in),
.odd(o_odd)
);
assign data_ena = (cstate == DATA);
assign done = o_done;
assign out_byte = o_byte;
assign parity_ena = (nstate != DATA && nstate != CHECK);
always @(posedge clk) begin
if (reset) begin
cstate <= IDLE;
end else begin
cstate <= nstate;
end
end
always @(*) begin
case (cstate)
IDLE: nstate = in ? IDLE : START;
START: nstate = DATA;
DATA: nstate = data_end ? CHECK : DATA;
CHECK: nstate = in ? STOP : WAIT;
WAIT: nstate = in ? IDLE : WAIT;
STOP: nstate = in ? IDLE : START;
endcase
end
always @(posedge clk) begin
if (reset) begin
data_cnt <= 4'b0000;
data_end <= 1'b0;
end else begin
if (data_ena) begin
if (data_cnt == 6) begin
data_end <= 1'b1;
end else begin
data_cnt <= data_cnt + 1'b1;
end
end else begin
data_cnt <= 4'b0000;
data_end <= 1'b0;
end
end
end
always @(posedge clk) begin
if (reset) begin
o_done <= 1'b0;
end else begin
if (nstate == STOP && o_odd) begin
o_done <= 1'b1;
end else begin
o_done <= 1'b0;
end
end
end
always @(posedge clk) begin
if (reset) begin
o_byte <= 8'b0;
end else begin
if (nstate == DATA) begin
o_byte <= {in, o_byte[7:1]};
end
end
end
// New: Add parity checking.
endmodule
| 7.203305
|
module FAS (
M,
A,
B,
Cin,
D,
Cout
);
input M;
input A;
input B;
input Cin;
output D;
output Cout;
wire W4;
xor2 X3 (
B,
M,
W4
);
FA d (
A,
W4,
Cin,
D,
Cout
);
endmodule
| 7.492846
|
module aha_full_adder_subtractor (
A,
B,
Sel,
Cin,
Cout,
S
);
input A, B, Cin, Sel;
output Cout, S;
wire Bs, t1, t2, t3;
assign Bs = B ^ Sel;
assign t1 = Bs ^ A;
assign S = t1 ^ Cin;
assign t2 = A & Bs;
assign t3 = t1 & Cin;
assign Cout = t2 | t3;
endmodule
| 7.24041
|
module single_counter (
out,
clock,
reset
);
input clock, reset;
output out;
reg out;
always @(reset) if (reset == 1) out = 0;
always @(posedge clock) if (reset == 0) out = ~out;
endmodule
| 6.64582
|
module FADDER (
sum,
carry,
x,
y,
z
);
input x, y, z;
output sum, carry;
wire [0:7] d;
DECODER dec (
d,
x,
y,
z
);
assign sum = d[1] | d[2] | d[4] | d[7], carry = d[3] | d[5] | d[6] | d[7];
endmodule
| 6.577998
|
module ror4 (
input [3:0] in,
input [1:0] s,
output [3:0] out
);
assign out = in >> s;
endmodule
| 7.537229
|
module add_1bit (
input a,
input b,
input c0,
output s,
output c1
);
wire s;
wire c1;
assign s = (a ^ b) ^ c0;
assign c1 = (a & b) | (b & c0) | (c0 & a);
endmodule
| 7.224096
|
module one_bit_comp (
input A,
B,
output reg EQ
);
always @(A, B) begin
if (A == B) EQ = 1;
else EQ = 0;
end
endmodule
| 7.149439
|
module flop_1bit (
x,
y,
clk,
rst_n
);
input rst_n, clk;
input x;
output reg y;
always @(posedge clk, negedge rst_n) begin
if (!rst_n) y <= 0;
else y <= x;
end
endmodule
| 7.349013
|
module flop_1bit_with_stall (
clk,
x,
y,
rst_n,
stall
);
input clk, x, rst_n, stall;
output reg y;
always @(posedge clk, negedge rst_n) begin
if (!rst_n) y <= 0;
else if (stall) y <= y;
else y <= x;
end
endmodule
| 7.411333
|
module OneBitFullAdder (
in1,
in2,
out,
cout
);
input wire in1;
input wire in2;
output wire out;
output wire cout;
assign {cout, out} = in1 + in2;
endmodule
| 8.425088
|
module FullAdder (
a,
b,
cin,
s,
cout
);
// 3C7 LabD 2010
// a and b are the bits to add
// cin is carry in
input wire a, b, cin;
// s is the sum of a and b. cout is any carry out bit
// wires since just using assign here
output wire s, cout;
// logic for sum and carry
assign s = cin ^ a ^ b;
assign cout = (b & cin) | (a & cin) | (a & b);
endmodule
| 7.610141
|
module fullsubtractor1 (
output diff,
bout,
input a,
b,
bin
);
//methodology: data flow modeling
assign diff = a ^ b ^ bin;
assign bout = ~a & (b ^ bin) | b & bin;
endmodule
| 6.741456
|
module fullsubtractor1_tb;
wire diff, bout;
reg a, b, bin;
fullsubtractor1 Instance0 (
diff,
bout,
a,
b,
bin
);
initial begin
a = 0;
b = 0;
bin = 0;
#20 a = 0;
b = 0;
bin = 1;
#20 a = 0;
b = 1;
bin = 0;
#20 a = 0;
b = 1;
bin = 1;
#20 a = 1;
b = 0;
bin = 0;
#20 a = 1;
b = 0;
bin = 1;
#20 a = 1;
b = 1;
bin = 0;
#20 a = 1;
b = 1;
bin = 1;
end
initial begin
$dumpfile("dump.vcd");
$dumpvars(1);
end
endmodule
| 6.741456
|
module fullsubtractor1 (
output diff,
bout,
input a,
b,
bin
);
xor a1 (diff, a, b, bin);
and a2 (w1, ~a, b);
and a3 (w2, ~a, bin);
and a4 (w3, b, bin);
or a5 (bout, w1, w2, w3);
endmodule
| 6.741456
|
module fullsubtractor1_tb ();
wire diff;
wire bout;
reg a, b;
reg bin;
fullsubtractor1 m1 (
diff,
bout,
a,
b,
bin
);
initial begin
$dumpfile("dump.vcd");
$dumpvars(1);
a = 0;
b = 0;
bin = 0;
#20 a = 0;
b = 0;
bin = 1;
#20 a = 0;
b = 1;
bin = 0;
#20 a = 0;
b = 1;
bin = 1;
#20 a = 1;
b = 0;
bin = 0;
#20 a = 1;
b = 0;
bin = 1;
#20 a = 1;
b = 1;
bin = 0;
#20 a = 1;
b = 1;
bin = 1;
#30 $stop;
end
endmodule
| 6.741456
|
module xnor_gate
// I/O ports
(
input wire i0,
i1,
output wire op
);
// signal declaration
wire p0, p1;
// body
// sum of two product terms
assign op = p0 | p1;
// product terms
assign p0 = ~i0 & ~i1;
assign p1 = i0 & i1;
endmodule
| 7.843367
|
module clk_div3 (
clk,
reset,
clk_out
);
input clk;
input reset;
output clk_out;
reg [1:0] pos_count, neg_count;
wire [1:0] r_nxt;
always @(posedge clk)
if (reset) pos_count <= 0;
else if (pos_count == 2) pos_count <= 0;
else pos_count <= pos_count + 1;
always @(negedge clk)
if (reset) neg_count <= 0;
else if (neg_count == 2) neg_count <= 0;
else neg_count <= neg_count + 1;
assign clk_out = ((pos_count == 2) | (neg_count == 2));
endmodule
| 6.961143
|
module clk_divn #(
parameter WIDTH = 3,
parameter N = 5
) (
clk,
reset,
clk_out
);
input clk;
input reset;
output clk_out;
reg [WIDTH-1:0] pos_count, neg_count;
wire [WIDTH-1:0] r_nxt;
always @(posedge clk)
if (reset) pos_count <= 0;
else if (pos_count == N - 1) pos_count <= 0;
else pos_count <= pos_count + 1;
always @(negedge clk)
if (reset) neg_count <= 0;
else if (neg_count == N - 1) neg_count <= 0;
else neg_count <= neg_count + 1;
assign clk_out = ((pos_count > (N >> 1)) | (neg_count > (N >> 1)));
endmodule
| 7.317272
|
module time_adv_half #(
parameter M = 2,
WIDTH = 7 //3.5*2
) (
input clk,
input rst,
output reg clk_out
);
wire clk_cnt;
assign clk_cnt = (clk_vld) ? !clk : clk;
reg [WIDTH : 0] counter;
always @(posedge clk_cnt or posedge rst) begin
if (rst) begin
// reset
counter <= 0;
end else if (counter == M) begin
counter <= 0;
end else begin
counter <= counter + 1;
end
end
reg clk_vld;
always @(posedge clk_out or posedge rst) begin
if (rst) begin
// reset
clk_vld <= 0;
end else begin
clk_vld <= !clk_vld;
end
end
always @(posedge clk_cnt or posedge rst) begin
if (rst) begin
// reset
clk_out <= 0;
end else if (counter == M - 1) begin
clk_out <= !clk_out;
end else if (counter == M) begin
clk_out <= !clk_out;
end
end
endmodule
| 6.726844
|
module butterfly (
input clock,
input signed [15:0] x1,
input signed [15:0] y1,
input signed [15:0] x2,
input signed [15:0] y2,
input signed [31:0] zangle,
output signed [15:0] xout1,
output signed [15:0] yout1,
output signed [15:0] xout2,
output signed [15:0] yout2
);
// Temporary variabbles to store output
wire signed [15:0] xtemp3, ytemp3;
// FISRT OUTPUT ---> DIRECT SUM OF THE INPUTS
assign xout1 = (x1 + x2);
assign yout1 = (y1 + y2);
// SECOND OUTPUT ---> ROTATION OF THE DIFFERENCE OF THE INPUTS BY A GIVEN ANGLE
// CORDIC MODULE USED
cordic c3 (
clock,
x1 - x2,
y1 - y2,
zangle,
xtemp3,
ytemp3,
done
);
// Assigning the value of the temporary variables to the second output
assign xout2 = xtemp3;
assign yout2 = ytemp3;
endmodule
| 7.77208
|
module cordic (
input clock,
input signed [15:0] xstart,
input signed [15:0] ystart,
input signed [31:0] zangle,
output signed [15:0] xout,
output signed [15:0] yout,
output reg done
);
reg znext;
wire signed [31:0] atan_table[0:15];
assign atan_table[00] = 'b00100000000000000000000000000000; // 45.000 degrees -> atan(2^0)
assign atan_table[01] = 'b00010010111001000000010100011101; // 26.565 degrees -> atan(2^-1)
assign atan_table[02] = 'b00001001111110110011100001011011; // 14.036 degrees -> atan(2^-2)
assign atan_table[03] = 'b00000101000100010001000111010100; // atan(2^-3)
assign atan_table[04] = 'b00000010100010110000110101000011;
assign atan_table[05] = 'b00000001010001011101011111100001;
assign atan_table[06] = 'b00000000101000101111011000011110;
assign atan_table[07] = 'b00000000010100010111110001010101;
assign atan_table[08] = 'b00000000001010001011111001010011;
assign atan_table[09] = 'b00000000000101000101111100101110;
assign atan_table[10] = 'b00000000000010100010111110011000;
assign atan_table[11] = 'b00000000000001010001011111001100;
assign atan_table[12] = 'b00000000000000101000101111100110;
assign atan_table[13] = 'b00000000000000010100010111110011;
assign atan_table[14] = 'b00000000000000001010001011111001;
assign atan_table[15] = 'b00000000000000000101000101111100;
parameter width = 16;
reg signed [15:0] xcomp_start, ycomp_start;
reg [3:0] out = 4'b0000;
wire [1:0] quad;
assign quad = zangle[31:30];
reg signed [width:0] x[0:width-1];
reg signed [width:0] y[0:width-1];
reg signed [31:0] z[0:width-1]; // col z[rows]
always @(posedge clock) begin
xcomp_start = (xstart >>> 1) + (xstart >>> 4) + (xstart >>> 5);
ycomp_start = (ystart >>> 1) + (ystart >>> 4) + (ystart >>> 5);
// if no scaling done
//xcomp_start = (xstart);
//ycomp_start = (ystart);
case (quad)
2'b00, 2'b11: begin // -90 to 90
x[0] <= xcomp_start;
y[0] <= ycomp_start;
z[0] <= zangle;
end
2'b01: //subtract 90 (second quadrant)
begin
x[0] <= -ycomp_start;
y[0] <= xcomp_start;
z[0] <= {2'b00, zangle[29:0]};
end
2'b10: // add 90 (third quadrant)
begin
x[0] <= ycomp_start;
y[0] <= -xcomp_start;
z[0] <= {2'b11, zangle[29:0]};
end
endcase
end
genvar i;
generate
for (i = 0; i < 15; i = i + 1) begin : iterations
wire signed [width:0] xshift, yshift;
assign xshift = x[i] >>> i; // signed shift right
assign yshift = y[i] >>> i;
always @(posedge clock) begin
x[i+1] <= z[i][31] ? x[i] + yshift : x[i] - yshift;
y[i+1] <= z[i][31] ? y[i] - xshift : y[i] + xshift;
z[i+1] <= z[i][31] ? z[i] + atan_table[i] : z[i] - atan_table[i];
out <= out + 1;
if (out == 4'b1111) done = 'b1;
else done = 'b0;
end
end
endgenerate
assign xout = x[width-1];
assign yout = y[width-1];
endmodule
| 6.912729
|
module fa_1 (
A,
B,
C,
S,
Cout
);
input [3:0] A;
input [3:0] B;
input C;
output [3:0] S, Cout;
reg S;
reg Cout;
always @(A or B or C) begin
{Cout, S} = A + B + C;
end
endmodule
| 7.561253
|
module fa_1 (
A,
B,
C,
S,
Cout
);
input A, B, C;
output S, Cout;
reg S, Cout;
always @(A or B or C) begin
if ((A == B && B != C && A == 1'b1) ||
(A == C && C != B && A == 1'b1) ||
(B == C && A != B && B == 1'b1))
begin
S = 0;
Cout = 1;
end
else if ((A == B && B != C && A == 1'b0) ||
(A == C && C != B && A == 1'b0) ||
(B == C && A != B && B == 1'b0))
begin
S = 1;
Cout = 0;
end else if (A == B && B == C && A == 1'b1) begin
S = 1;
Cout = 1;
end else begin
S = 0;
Cout = 0;
end
end
endmodule
| 7.561253
|
module t1 (N1,N2,N3,N4,N5,N6,N7,N19,N21,N23);
input N1,N2,N3,N4,N5,N6,N7;
output N19,N21,N23;
N16 = NAND(N1, N2)
N19 = NOR(N16, N3)
N21 = NAND(N4, N5)
N23 = NOR(N6, N7)
endmodule
| 7.526928
|
module tri_mode_ethernet_mac_0_reset_sync #(
parameter INITIALISE = 1'b1,
parameter DEPTH = 5
) (
input reset_in,
input clk,
input enable,
output reset_out
);
wire reset_sync_reg0;
wire reset_sync_reg1;
wire reset_sync_reg2;
wire reset_sync_reg3;
wire reset_sync_reg4;
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
FDPE #(
.INIT(INITIALISE[0])
) reset_sync0 (
.C (clk),
.CE (enable),
.PRE(reset_in),
.D (1'b0),
.Q (reset_sync_reg0)
);
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
FDPE #(
.INIT(INITIALISE[0])
) reset_sync1 (
.C (clk),
.CE (enable),
.PRE(reset_in),
.D (reset_sync_reg0),
.Q (reset_sync_reg1)
);
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
FDPE #(
.INIT(INITIALISE[0])
) reset_sync2 (
.C (clk),
.CE (enable),
.PRE(reset_in),
.D (reset_sync_reg1),
.Q (reset_sync_reg2)
);
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
FDPE #(
.INIT(INITIALISE[0])
) reset_sync3 (
.C (clk),
.CE (enable),
.PRE(reset_in),
.D (reset_sync_reg2),
.Q (reset_sync_reg3)
);
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
FDPE #(
.INIT(INITIALISE[0])
) reset_sync4 (
.C (clk),
.CE (enable),
.PRE(reset_in),
.D (reset_sync_reg3),
.Q (reset_sync_reg4)
);
assign reset_out = reset_sync_reg4;
endmodule
| 6.950534
|
module tri_mode_ethernet_mac_0_sync_block #(
parameter INITIALISE = 1'b0,
parameter DEPTH = 5
) (
input clk, // clock to be sync'ed to
input data_in, // Data to be 'synced'
output data_out // synced data
);
// Internal Signals
wire data_sync0;
wire data_sync1;
wire data_sync2;
wire data_sync3;
wire data_sync4;
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
FDRE #(
.INIT(INITIALISE[0])
) data_sync_reg0 (
.C (clk),
.D (data_in),
.Q (data_sync0),
.CE(1'b1),
.R (1'b0)
);
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
FDRE #(
.INIT(INITIALISE[0])
) data_sync_reg1 (
.C (clk),
.D (data_sync0),
.Q (data_sync1),
.CE(1'b1),
.R (1'b0)
);
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
FDRE #(
.INIT(INITIALISE[0])
) data_sync_reg2 (
.C (clk),
.D (data_sync1),
.Q (data_sync2),
.CE(1'b1),
.R (1'b0)
);
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
FDRE #(
.INIT(INITIALISE[0])
) data_sync_reg3 (
.C (clk),
.D (data_sync2),
.Q (data_sync3),
.CE(1'b1),
.R (1'b0)
);
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
FDRE #(
.INIT(INITIALISE[0])
) data_sync_reg4 (
.C (clk),
.D (data_sync3),
.Q (data_sync4),
.CE(1'b1),
.R (1'b0)
);
assign data_out = data_sync4;
endmodule
| 6.950534
|
module first_register (
input clk,
input rst,
input StallD,
input FlushD,
input [31:0] instruction,
input [31:0] PCF,
input [31:0] PCPlus4F,
output reg [31:0] instrD,
output reg [31:0] PCD,
output reg [31:0] PCPlus4D
);
always @(posedge clk) begin
if (rst) begin
instrD <= 32'd0;
PCD <= 32'd0;
PCPlus4D <= 32'd0;
end else if (StallD) begin
instrD <= instrD;
PCD <= PCD;
PCPlus4D <= PCPlus4D;
end else if (FlushD) begin
instrD <= 32'd0;
PCD <= 32'd0;
PCPlus4D <= 32'd0;
end else begin
instrD <= instruction;
PCD <= PCF;
PCPlus4D <= PCPlus4F;
end
end
endmodule
| 7.889146
|
module Mem_1por2 (
output [1:0] saida,
input [1:0] entrada,
input clk,
input addr,
input rw,
input clr
);
Mem_1por1 MEM1 (
saida[0],
entrada[0],
clk,
addr,
rw,
clr
);
Mem_1por1 MEM2 (
saida[1],
entrada[1],
clk,
addr,
rw,
clr
);
endmodule
| 6.819471
|
module Mem_1por4 (
output [3:0] saida,
input [3:0] entrada,
input clk,
input addr,
input rw,
input clr
);
Mem_1por2 MEM1 (
saida[1:0],
entrada[1:0],
clk,
addr,
rw,
clr
);
Mem_1por2 MEM2 (
saida[3:2],
entrada[3:2],
clk,
addr,
rw,
clr
);
endmodule
| 6.891837
|
module test_Mem_1por4;
// ------------------------- definir dados
reg [3:0] entrada;
reg clk;
reg addr;
reg rw;
reg clr;
wire [3:0] saida;
// ------------------------- instancia
Mem_1por4 modulo (
saida,
entrada,
clk,
addr,
rw,
clr
);
// ------------------------- parte principal
initial begin
$display("Memria RAM 1x4 \n");
$display("Entrada\tClk\tAddr\tR/W\tClr\tSaida\n");
#1 entrada = 1100;
clk = 0;
addr = 0;
rw = 0;
clr = 1;
$monitor("%4b\t%1b\t%1b\t%1b\t%1b\t%4b", entrada, clk, addr, rw, clr, saida);
#1 entrada = 1100;
clk = 1;
addr = 1;
rw = 1;
clr = 0;
#1 entrada = 0000;
clk = 0;
addr = 1;
rw = 0;
clr = 0;
end
endmodule
| 7.603961
|
module teste1por8;
reg entrada[0:7], clk, rw, addr, clear;
wire saida[0:7], q[0:7], qnot[0:7], clk_s;
and and0 (clk_s, clk, rw, addr);
jkff jk1 (
q[0],
qnot[0],
entrada[0],
entrada[0],
clk_s
);
jkff jk2 (
q[1],
qnot[0],
entrada[1],
entrada[1],
clk_s
);
jkff jk3 (
q[2],
qnot[0],
entrada[2],
entrada[2],
clk_s
);
jkff jk4 (
q[3],
qnot[0],
entrada[3],
entrada[3],
clk_s
);
jkff jk5 (
q[4],
qnot[0],
entrada[4],
entrada[4],
clk_s
);
jkff jk6 (
q[5],
qnot[0],
entrada[5],
entrada[5],
clk_s
);
jkff jk7 (
q[6],
qnot[0],
entrada[6],
entrada[6],
clk_s
);
jkff jk8 (
q[7],
qnot[0],
entrada[7],
entrada[7],
clk_s
);
and and1 (saida[0], q[0], addr);
and and2 (saida[1], q[1], addr);
and and3 (saida[2], q[2], addr);
and and4 (saida[3], q[3], addr);
and and5 (saida[4], q[4], addr);
and and6 (saida[5], q[5], addr);
and and7 (saida[6], q[6], addr);
and and8 (saida[7], q[7], addr);
initial begin
clk = 0;
addr = 0;
clear = 0;
rw = 0;
entrada[0] = 0;
entrada[1] = 0;
entrada[2] = 1;
entrada[3] = 0;
entrada[4] = 1;
entrada[5] = 1;
entrada[6] = 1;
entrada[7] = 1;
$display("Memria 1x8 com Flip Flop JK");
$display("entrada\tclock\tADDR\tClear\tRW\tsada");
addr = 1;
rw = 1;
clk = 1;
#25 $finish;
end
always begin
#5 clk = ~clk;
end
always @(clk) begin
$display("%b%b%b%b%b%b%b%b\t%1b\t%1b\t%1b\t%1b\t%b%b%b%b%b%b%b%b", entrada[0], entrada[1],
entrada[2], entrada[3], entrada[4], entrada[5], entrada[6], entrada[7], clk_s, addr,
clear, rw, saida[0], saida[1], saida[2], saida[3], saida[4], saida[5], saida[6],
saida[7]);
end
endmodule
| 6.520574
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = (~{full[4:1], full[5]});
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = '0;
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = '1;
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module onebitALU (
y,
z,
a,
b,
cin,
c0,
c1
);
output y, z;
input a, b, cin, c0, c1;
wire y1, y2, y3;
wire cout, z1, z2;
wire w1, w2, w3;
fullAdder f1 (
y1,
cout,
a,
b,
cin
);
and a1 (y2, a, b);
not n1 (y3, a);
xor x1 (w1, a, b);
and a2 (w2, c0, c1);
and a3 (z2, w1, w2);
nor nor1 (w3, c0, c1);
and a4 (z1, cout, w3);
or or1 (z, z1, z2);
mux_4to1 mux2 (
y,
y1,
y2,
y3,
1'b0,
c0,
c1
);
endmodule
| 8.545363
|
module is scalable and suitable for
// expansion.
//
// Licence: These project have been published for
// academic use only under GPLv3 License.
// Copyright 2018
// All Rights Reserved
///////////////////////////////////////////////////////////
module BitonicNetwork #( parameter NUM = 4 , W = 16)(
//INPUT
//input clk, rst,
input direction,
input [(NUM*W)-1:0] IN , //"NUM" input records with "W" data width.
//OUTPUT
output [(NUM*W)-1:0] OUT
);
wire [(NUM*W)-1:0] _stage1;
wire [(NUM*W)-1:0] _stage2_1, _stage2_2;
assign OUT = _stage2_2;
genvar a, b, c ,d ,e;
// Simple bitonic network with 4 input records:
//
// IN[0] -----*----------------*----> OUT[0]
// | |
// IN[1] -----*------------*---|----> OUT[1]
// | |
// IN[2] -----*------------*---|----> OUT[2]
// | |
// IN[3] -----*----------------*----> OUT[3]
// stage 1 stage 2
//
/////////////////////////////////////////////////
/////////////////////////////////////////////////
/// STAGE 1
generate
for(a = 0; a < NUM/2; a = a+1)
begin: Stage1
BitonicPosStage1 #(W) Pos_Bitonic(
//.clk(clk), .rst(rst),
.direction(direction),
.IN (IN [2*W*a +(2*W-1):2*W*a]),
.OUT (_stage1[2*W*a +(2*W-1):2*W*a])
);
end
endgenerate
/// reg bitween two stage
//REG #(NUM*16) REG_STAGE_1( .clk(clk), .rst(rst), .IN(_stage1), .OUT(_reg1));
/////////////////////////////////////////////////
/////////////////////////////////////////////////
/// STAGE 2
generate
for(b = 0; b < NUM/4; b = b+1)
begin: Stage2
BitonicPreStage #(4, W) Pre_Bitonic (
//.clk(clk), .rst(rst),
.direction(direction),
.IN (_stage1 [4*W*b +(4*W-1):4*W*b]),
.OUT (_stage2_1[4*W*b +(4*W-1):4*W*b])
);
BitonicPosStage2 #(W) Pos_Bitonic(
//.clk(clk), .rst(rst),
.direction(direction),
.IN (_stage2_1[4*W*b +(4*W-1):4*W*b]),
.OUT (_stage2_2[4*W*b +(4*W-1):4*W*b])
);
end
endgenerate
/// reg bitween two stage
//REG #(NUM*16) REG_STAGE_2( .clk(clk), .rst(rst), .IN(_stage2_2), .OUT(_reg2));
endmodule
| 6.736964
|
module BitonicPosStage1 #(
parameter W = 16
) (
//INPUT
//input clk, rst,
input direction,
input [(2*W)-1:0] IN,
//OUTPUT
output [(2*W)-1:0] OUT
);
Comparator #(W) COM_1 (
//.clk(clk), .rst(rst),
.direction(direction),
.IN1(IN[W-1:0]),
.IN2(IN[2*W-1:W]),
.OUT1(OUT[W-1:0]),
.OUT2(OUT[2*W-1:W])
);
endmodule
| 6.628381
|
module.
//
// Licence: These project have been published for
// academic use only under GPLv3 License.
// Copyright 2018
// All Rights Reserved
///////////////////////////////////////////////////////////
module BitonicPosStage2 #( parameter W = 16)(
//INPUT
//input clk, rst,
input direction,
input [(4*W)-1:0] IN,
//OUTPUT
output [(4*W)-1:0] OUT
);
genvar i;
generate
for(i = 0; i < 2; i = i+1)
begin: Stage2_
BitonicPosStage1 #(W) Bitonic_ (
//.clk(clk), .rst(rst),
.direction(direction),
.IN (IN [2*W*i +(2*W-1):2*W*i]),
.OUT (OUT [2*W*i +(2*W-1):2*W*i])
);
end
endgenerate
endmodule
| 7.081424
|
module.
//
// Licence: These project have been published for
// academic use only under GPLv3 License.
// Copyright 2018
// All Rights Reserved
///////////////////////////////////////////////////////////
module BitonicPosStage3 #( parameter W = 16)(
//INPUT
//input clk, rst,
input direction,
input [(8*W)-1:0] IN,
//OUTPUT
output [(8*W)-1:0] OUT
);
wire [(8*W)-1:0] _wire;
genvar i;
generate
for(i = 0; i < 2; i = i+1)
begin: Stage3_
Comparator #(W) COM_1 (
//.clk(clk), .rst(rst),
.direction(direction),
.IN1 (IN [4*W*i+(W-1): 4*W*i]),
.IN2 (IN [4*W*i+(3*W-1): 4*W*i+(2*W)]),
.OUT1(_wire[4*W*i+(W-1): 4*W*i]),
.OUT2(_wire[4*W*i+(3*W-1): 4*W*i+(2*W)])
);
Comparator #(W) COM_2 (
//.clk(clk), .rst(rst),
.direction(direction),
.IN1 (IN [4*W*i+(2*W-1): 4*W*i+W]),
.IN2 (IN [4*W*i+(4*W-1): 4*W*i+(3*W)]),
.OUT1(_wire[4*W*i+(2*W-1): 4*W*i+W]),
.OUT2(_wire[4*W*i+(4*W-1): 4*W*i+(3*W)])
);
BitonicPosStage2 #(W) Bitonic_ (
//.clk(clk), .rst(rst),
.direction(direction),
.IN (_wire [4*W*i +(4*W-1):4*W*i]),
.OUT (OUT [4*W*i +(4*W-1):4*W*i])
);
end
endgenerate
endmodule
| 7.081424
|
module BitonicPreStage #(
parameter NUM = 16,
W = 16
) (
//INPUT
//input clk, rst,
input direction,
input [(NUM*W)-1 : 0] IN,
//OUTPUT
output [(NUM*W)-1 : 0] OUT
);
genvar i;
generate
for (i = 0; i < NUM / 2; i = i + 1) begin : PreStage_
Comparator #(W) COM_ (
//.clk(clk), .rst(rst),
.direction(direction),
.IN1(IN[W*i+(W-1) : W*i]),
.IN2(IN[(NUM*W-1)-W*i : (NUM*W-1)-W*i-(W-1)]),
.OUT1(OUT[W*i+(W-1) : W*i]),
.OUT2(OUT[(NUM*W-1)-W*i : (NUM*W-1)-W*i-(W-1)])
);
end
endgenerate
endmodule
| 6.509421
|
module one_bit_full_adder (
a,
b,
cin,
opcode,
sum,
carry
);
input a;
input b;
input cin;
input opcode;
output wire sum;
output wire carry;
assign sum = cin ^ (a ^ (b ^ opcode));
assign carry = ((a & (b ^ opcode)) | ((b ^ opcode) & cin) | (cin & a));
endmodule
| 6.938543
|
module fulladder1 (
output sum,
cout,
input a,
b,
cin
);
assign sum = a ^ b ^ cin;
assign cout = (a & b) | ((a ^ b) & cin);
endmodule
| 6.715059
|
module fulladder1_tb ();
reg a, b;
reg cin;
wire sum;
wire cout;
fulladder1 instance0 (
sum,
cout,
a,
b,
cin
);
initial begin
$dumpfile("dump.vcd");
$dumpvars(1);
a = 0;
b = 0;
cin = 0;
#20 a = 0;
b = 0;
cin = 1;
#20 a = 0;
b = 1;
cin = 0;
#20 a = 0;
b = 1;
cin = 1;
#20 a = 1;
b = 0;
cin = 0;
#20 a = 1;
b = 0;
cin = 1;
#20 a = 1;
b = 1;
cin = 0;
#20 a = 1;
b = 1;
cin = 1;
#30 $stop;
end
endmodule
| 7.232581
|
module fulladder1 (
output sum,
cout,
input a,
b,
cin
);
xor a1 (sum, a, b, cin);
and a2 (w1, a, b);
and a3 (w2, b, cin);
and a4 (w3, a, cin);
or a5 (cout, w1, w2, w3);
endmodule
| 6.715059
|
module fulladder1_tb ();
wire sum;
wire cout;
reg a, b;
reg cin;
fulladder1 m1 (
sum,
cout,
a,
b,
cin
);
initial begin
$dumpfile("dump.vcd");
$dumpvars(1);
a = 0;
b = 0;
cin = 0;
#20 a = 0;
b = 0;
cin = 1;
#20 a = 0;
b = 1;
cin = 0;
#20 a = 0;
b = 1;
cin = 1;
#20 a = 1;
b = 0;
cin = 0;
#20 a = 1;
b = 0;
cin = 1;
#20 a = 1;
b = 1;
cin = 0;
#20 a = 1;
b = 1;
cin = 1;
#30 $stop;
end
endmodule
| 7.232581
|
module halfadder1 (
output sum,
carry,
input a,
b
);
assign sum = a ^ b;
assign carry = a & b;
endmodule
| 6.995975
|
module halfadder1_tb ();
reg a, b;
wire sum;
wire carry;
halfadder1 m1 (
sum,
carry,
a,
b
);
initial begin
$dumpfile("dump.vcd");
$dumpvars(1);
a = 0;
b = 0;
#20 a = 1;
b = 0;
#20 a = 0;
b = 1;
#20 a = 1;
b = 1;
#30 $stop;
end
endmodule
| 6.803674
|
module halfadder1 (
output sum,
carry,
input a,
b
);
xor a1 (sum, a, b);
and a2 (carry, a, b);
endmodule
| 6.995975
|
module halfadder1_tb ();
wire sum;
wire carry;
reg a, b;
halfadder1 m1 (
sum,
carry,
a,
b
);
initial begin
$dumpfile("dump.vcd");
$dumpvars(1);
a = 0;
b = 0;
#20 a = 1;
b = 0;
#20 a = 0;
b = 1;
#20 a = 1;
b = 1;
#30 $stop;
end
endmodule
| 6.803674
|
module of RTHS design, you can find description about this module from paper below.
// ("RTHS: A Low-Cost High-Performance Real-Time Hardware Sorter, Using
// a Multidimensional Sorting Algorithm", doi: 10.1109/TVLSI.2019.2912554)
//
// Licence: These project have been published for
// academic use only under GPLv3 License.
// Copyright 2018
// All Rights Reserved
///////////////////////////////////////////////////////////
module Comparator #( parameter W = 16)(
//INPUT
//input clk, rst,
input direction ,
input[W-1:0] IN1 ,
input[W-1:0] IN2 ,
//OUTPUT
//output reg[W-1:0] OUT1 ,
//output reg[W-1:0] OUT2
output [W-1:0] OUT1 ,
output [W-1:0] OUT2
);
//////////////////////////////////////
// INPUT = {(W/2)key field, //
// (W/2)information field} //
// //
// DIRECTION OUT1 OUT2 //
// ------------------------------ //
// 1'b0 smaller bigger //
// 1'b1 bigger smaller //
//////////////////////////////////////
wire comp = (IN1[W-1:W/2]<IN2[W-1:W/2])^direction;
//always @(posedge clk or posedge rst) begin
// if(rst) begin
// OUT1 <= 0;
// OUT2 <= 0;
// end else begin
// OUT1 <= (comp)? IN1:IN2;
// OUT2 <= (comp)? IN2:IN1;
// end
//end
assign OUT1 = (comp)? IN1:IN2;
assign OUT2 = (comp)? IN2:IN1;
endmodule
| 8.47808
|
module multiplier_8x2 (
input [1:0] W, // signed or unsigned
input [7:0] A, // signed
input mode, // if 1, regards w as signed, else unsigned
output [9:0] Result
);
wire [7:0] W_01A, notA, temp, W_10A;
assign W_01A = {8{W[0]}} & A;
assign notA = ~A;
genvar i;
for (i = 0; i < 8; i = i + 1) begin
MUX_2 mx (
.A (A[i]),
.B (notA[i]),
.sel(mode),
.O (temp[i])
);
end
assign W_10A = {8{W[1]}} & temp;
wire [8:0] OP1, OP2;
wire CIN = W[1] & mode;
wire [8:0] sumres;
signExtender #(
.size(7),
.extsize(9)
) op1se (
W_01A[7:1],
OP1
);
signExtender #(
.size(8),
.extsize(9)
) op2se (
W_10A,
OP2
);
ADDER #(
.size(9)
) sum (
OP1,
OP2,
CIN,
sumres
);
assign Result = {sumres, W_01A[0]};
endmodule
| 7.064293
|
module MUX_2 (
input A,
B,
sel,
output O
);
wire asp, bs, notsel;
not (notsel, sel);
nand (asp, A, notsel);
nand (bs, B, sel);
nand (O, asp, bs);
endmodule
| 6.660624
|
module signExtender (
I,
O
); // size bit 신호 I를 extsize bit 신호 O로 sign extension
parameter size = 10;
parameter extsize = 12;
input [size-1:0] I;
output [extsize-1:0] O;
assign O = {{(extsize - size) {I[size-1]}}, {I}};
endmodule
| 7.592923
|
module ADDER (
op1,
op2,
cin,
res
); // without carry out
parameter size = 12;
input [size-1:0] op1, op2;
input cin;
output [size-1:0] res;
wire [size:0] C;
genvar i;
assign C[0] = cin;
generate
for (i = 0; i < size; i = i + 1) begin
fullAdder FAwoc (
.A (op1[i]),
.B (op2[i]),
.ci(C[i]),
.s (res[i]),
.co(C[i+1])
);
end
endgenerate
endmodule
| 7.255631
|
module ADDERc (
op1,
op2,
cin,
res,
cout
); // with carry out
parameter size = 12;
input [size-1:0] op1, op2;
input cin;
output [size-1:0] res;
output cout;
wire [size:0] C;
genvar i;
assign C[0] = cin;
assign cout = C[size];
generate
for (i = 0; i < size; i = i + 1) begin
fullAdder FAwc (
.A (op1[i]),
.B (op2[i]),
.ci(C[i]),
.s (res[i]),
.co(C[i+1])
);
end
endgenerate
endmodule
| 6.952629
|
module Insertion_block #(
parameter W = 41,
N = 64
) (
input clk,
rst,
input subtract,
input rd,
input wr,
input [W-2:0] data_in,
input repair_period,
output [W-2:0] data_out,
output empty,
output [W-2:0] data_fail,
output fail
);
integer RP_rd = 0;
wire [N:0] wr_;
wire rd_;
wire [W-1:0] data_reg[N:0];
wire [W-2:0] data_in_IB[N:0];
assign data_in_IB[0] = data_in;
assign data_reg[N] = {1'b0, {W - 1{1'b1}}};
assign wr_[0] = wr;
assign rd_ = rd | (repair_period & ~data_reg[0][W-1]);
assign fail = wr_[N];
assign data_fail = data_in_IB[N];
assign data_out = data_reg[0][W-2:0];
assign empty = ~data_reg[0][W-1];
genvar o, i;
generate
for (o = 0; o < N; o = o + 1) begin : IB
Insertion_cell #(
.W(W)
) Ins_cell (
//inputs
.clk (clk),
.rst (rst),
.subtract (subtract),
.wr (wr_[o]),
.data_in (data_in_IB[o]),
.rd (rd_),
.data_in_pre(data_reg[o+1]),
//outputs
.data_reg(data_reg[o]),
.data_out(data_in_IB[o+1]),
.wr_pre (wr_[o+1])
);
end
endgenerate
endmodule
| 6.929352
|
module Insertion_cell #(
parameter W = 41
) (
input clk,
rst,
input subtract,
input wr,
input rd,
input [W-2:0] data_in,
input [W-1:0] data_in_pre, // data from previous cell
output reg [W-1:0] data_reg,
output reg [W-2:0] data_out, // replacement with oldest data_reg or send data_in.
output reg wr_pre
);
wire [W-1:0] data_reg_sub;
wire comp = (data_reg[31:16] <= data_in[31:16]);
///////////////////////////////////////////////
// SUBTRACTOR
///////////////////////////////////////////////
sub_task #(
.W(W)
) subtractor (
.clk(clk),
.rst(rst),
.subtract_en(subtract),
.RT_in(data_reg),
.RT_out(data_reg_sub)
);
///////////////////////////////////////////////
// Cell
///////////////////////////////////////////////
always @(posedge clk or posedge rst) begin
if (rst) begin
data_reg <= {1'b0, {W - 1{1'b1}}};
data_out <= {W - 1{1'b1}};
wr_pre <= 1'b0;
end else begin
if (subtract) begin
data_reg <= data_reg_sub; // subtract
end else begin
///////////////////////////////////////////
// write and read data from insertion sort
case ({
wr, rd
})
//normal
2'b00: data_reg <= data_reg;
//read
2'b01: data_reg <= data_in_pre;
//write
2'b10: data_reg <= (comp & data_reg[W-1]) ? data_reg : {1'b1, data_in};
//read_write
2'b11: data_reg <= data_in_pre;
endcase
end
// outputs
wr_pre <= (~rd) ? (wr & data_reg[W-1]) : wr_pre;
data_out <= (~rd & wr) ? ((comp & data_reg[W-1]) ? data_in : data_reg[W-2:0]) : data_out;
///////////////////////////////////////////
end
end
endmodule
| 6.692141
|
module gates (
a,
b,
not_op,
and_op,
nand_op,
or_op,
nor_op,
xor_op,
xnor_op
);
input a, b;
output not_op, and_op, nand_op, or_op, nor_op, xor_op, xnor_op;
assign not_op = ~(a);
assign and_op = a & b;
assign nand_op = ~(a & b);
assign or_op = a | b;
assign nor_op = ~(a | b);
assign xor_op = a ^ b;
assign xnor_op = ~(a ^ b);
endmodule
| 7.748371
|
module test;
wire not_op, and_op, nand_op, or_op, nor_op, xor_op, xnor_op;
reg a = 1'b0, b = 1'b0;
gates g1 (
a,
b,
not_op,
and_op,
nand_op,
or_op,
nor_op,
xor_op,
xnor_op
);
initial begin
$dumpfile("1_logicgates_test.vcd");
$dumpvars(0, test);
#5 begin
a = 1'b0;
b = 1'b1;
end
#5 begin
a = 1'b1;
b = 1'b0;
end
#5 begin
a = 1'b1;
b = 1'b1;
end
#5 $finish;
end
always @(a or b) $strobe("At time=(%0t),a=(%0d),b=(%0d)", $time, a, b);
endmodule
| 6.964054
|
module m1 (
A,
B,
C,
D,
E,
F,
G,
H,
I
);
input A, B;
output C, D, E, F, G, H, I;
assign C = A & B;
assign D = A | B;
assign E = A ^ B;
assign F = ~(A & B);
assign G = ~(A | B);
assign H = ~(A ^ B);
assign I = ~A;
endmodule
| 6.520877
|
module top_module (
input [99:0] a,
b,
input sel,
output [99:0] out
);
assign out = sel ? b : a;
endmodule
| 7.203305
|
module top_module (
input clk,
input [7:0] d,
output [7:0] q
);
always @(posedge clk) begin
q <= d;
end
endmodule
| 7.203305
|
module top_module (
input a,
input b,
input c,
input d,
output out1,
output out2
);
//connect module by position
mod_a inst_1 (
out1,
out2,
a,
b,
c,
d
);
endmodule
| 7.203305
|
module top_module (
input clk,
input reset, // Synchronous active-high reset
output [3:0] q
);
always @(posedge clk) begin
if (reset) q <= 4'd0;
else if (q == 4'd9) q <= 4'd0;
else q <= q + 4'd1;
end
endmodule
| 7.203305
|
module top_module (
input a,
input b,
input c,
input d,
output out
);
assign out = (c | !d | !b) & (!a | !b | c) & (a | b | !c | !d) & (!a | !c | d);
endmodule
| 7.203305
|
module top_module (
input a,
b,
cin,
output cout,
sum
);
assign cout = a & b | b & cin | a & cin;
assign sum = a ^ b ^ cin;
endmodule
| 7.203305
|
module top_module (
output out
);
assign out = 1'b0;
endmodule
| 7.203305
|
module top_module (
input a,
input b,
input c,
output out
); //
wire con;
andgate inst1 (
con,
a,
b,
c,
1'b1,
1'b1
);
assign out = ~con;
endmodule
| 7.203305
|
module top_module (
input [7:0] in,
output parity
);
//even parity is calculated by XOR ing all the data bits
assign parity = ^in;
endmodule
| 7.203305
|
module top_module (
input wire [15:0] in,
output wire [ 7:0] out_hi,
output wire [ 7:0] out_lo
);
//The unpacked dimensions are declared after the name. They are generally used to declare memory arrays.
//reg [7:0] mem [255:0]; // 256 unpacked elements, each of which is a 8-bit packed vector of reg.
assign out_hi = in[15:8];
assign out_lo = in[7:0];
endmodule
| 7.203305
|
module bldc_motorDriver_2ch (
clk,
en_ch1,
en_ch2,
freq_adj_ch1,
freq_adj_ch2,
out_p1_ch1,
out_p1_inv_ch1,
out_p2_ch1,
out_p2_inv_ch1,
out_p3_ch1,
out_p3_inv_ch1,
out_p1_ch2,
out_p1_inv_ch2,
out_p2_ch2,
out_p2_inv_ch2,
out_p3_ch2,
out_p3_inv_ch2
);
input clk, en_ch1, en_ch2;
input [3:0] freq_adj_ch1;
input [3:0] freq_adj_ch2;
output out_p1_ch1, out_p1_inv_ch1, out_p2_ch1, out_p2_inv_ch1, out_p3_ch1, out_p3_inv_ch1;
output out_p1_ch2, out_p1_inv_ch2, out_p2_ch2, out_p2_inv_ch2, out_p3_ch2, out_p3_inv_ch2;
Three_phase_sin u1 (
.clk(clk),
.freq_adj(freq_adj_ch1),
.en(en_ch1),
.out_p1(out_p1_ch1),
.out_p1_inv(out_p1_inv_ch1),
.out_p2(out_p2_ch1),
.out_p2_inv(out_p2_inv_ch1),
.out_p3(out_p3_ch1),
.out_p3_inv(out_p3_inv_ch1)
);
Three_phase_sin u2 (
.clk(clk),
.freq_adj(freq_adj_ch2),
.en(en_ch2),
.out_p1(out_p1_ch2),
.out_p1_inv(out_p1_inv_ch2),
.out_p2(out_p2_ch2),
.out_p2_inv(out_p2_inv_ch2),
.out_p3(out_p3_ch2),
.out_p3_inv(out_p3_inv_ch2)
);
endmodule
| 7.354324
|
module Three_phase_sin (
clk,
en,
out_p1,
out_p1_inv,
out_p2,
out_p2_inv,
out_p3,
out_p3_inv,
freq_adj
);
input clk, en;
input [3:0] freq_adj;
output out_p1, out_p1_inv, out_p2, out_p2_inv, out_p3, out_p3_inv;
wire [7:0] duty_cycle_1;
wire [7:0] duty_cycle_2;
wire [7:0] duty_cycle_3;
wire [7:0] address_p1;
wire [7:0] address_p2;
wire [7:0] address_p3;
wire en;
wire clock;
pwm u1 (
.duty_cycle(duty_cycle_1),
.clk(clk),
.out(out_p1),
.en(en)
);
pwm u2 (
.duty_cycle(duty_cycle_2),
.clk(clk),
.out(out_p2),
.en(en)
);
pwm u3 (
.duty_cycle(duty_cycle_3),
.clk(clk),
.out(out_p3),
.en(en)
);
sin_look_up u4 (
.address(address_p1),
.duty_cycle(duty_cycle_1)
);
sin_look_up u5 (
.address(address_p2),
.duty_cycle(duty_cycle_2)
);
sin_look_up u6 (
.address(address_p3),
.duty_cycle(duty_cycle_3)
);
clk_div u7 (
.clk(clk),
.clk_sel(freq_adj),
.clk_out(clock)
);
modulation_con u8 (
.clk(clock),
.address_p1(address_p1),
.address_p2(address_p2),
.address_p3(address_p3)
);
assign out_p1_inv = ~out_p1;
assign out_p2_inv = ~out_p2;
assign out_p3_inv = ~out_p3;
endmodule
| 7.248268
|
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