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module tb_delays;
reg clk;
reg rst;
reg d;
initial begin // <- Initial construct are evaluated at t = 0.
// Here, t = 0.
clk = 1'b0;
rst = 1'b1;
d = 1'b0;
#3;
// Here, t = 3;
rst = 1'b0;
#2;
// Here, t = 5.
d = 1'b1;
#2;
// Here, t = 7.
d = 1'b0;
#5;
// Here, t = 12.
d = 1'b1;
#4;
$finish(); // <- finishes the simulation
end
always #2 clk = ~clk; // <- Every 2 units of time, clk is inverted.
endmodule
| 6.522164
|
module top_module (
input clk,
input [7:0] in,
input reset, // Synchronous reset
output done
); //
parameter BYTE1 = 0, BYTE2 = 1, BYTE3 = 2, DONE = 3;
reg [1:0] cstate, nstate;
always @(posedge clk) begin
if (reset) begin
cstate <= BYTE1;
end else begin
cstate <= nstate;
end
end
always @(*) begin
case (cstate)
BYTE1: nstate = in[3] ? BYTE2 : BYTE1;
BYTE2: nstate = BYTE3;
BYTE3: nstate = DONE;
DONE: nstate = in[3] ? BYTE2 : BYTE1;
endcase
end
assign done = (cstate == DONE);
endmodule
| 7.203305
|
module top_module (
input clk,
input [7:0] in,
output [7:0] anyedge
);
reg [7:0] intermediate;
always @(posedge clk) begin
intermediate <= in;
anyedge <= intermediate ^ in;
end
endmodule
| 7.203305
|
module top_module (
input [3:0] in,
output [2:0] out_both,
output [3:1] out_any,
output [3:0] out_different
);
assign out_both = in[2:0] & in[3:1]; //here bits of input vector is shifted right
//and bitwise and is performed to obtain the required output
assign out_any = in[3:1] | in[2:0];
assign out_different = in ^ {in[0], in[3:1]};
endmodule
| 7.203305
|
module approx_fa (
output sum,
cout,
input x,
y,
cin
);
wire s1, c1, c2;
or o1 (s1, x, y);
xor x1 (sum, s1, cin);
and a1 (cout, s1, cin);
endmodule
| 7.10387
|
module XOR4 (
output f,
input a,
input b,
input c,
input d,
input e
);
assign f = a ^ b ^ c ^ d ^ e; // ^ is the XOR operator
endmodule
| 7.338253
|
module ksa4 (
input [2:0] a,
input [2:0] s,
input cin,
output [3:0] B,
output carryout
);
wire [3:0] p, g, cp, cg, ccg, ccp, c;
//initial processing
assign p = a ^ s;
assign g = a & s;
//production of carry
assign cg[0] = (g[0]);
assign cp[0] = (p[0]);
assign cg[1] = (p[1] & g[0]) | g[1];
assign cp[1] = (p[1] & p[0]);
assign cg[2] = (p[2] & g[1]) | g[2];
assign cp[2] = p[2] & p[1];
assign cg[3] = (p[3] & g[2]) | g[3];
assign cp[3] = p[3] & p[2];
assign ccg[0] = cg[0];
assign ccp[0] = cp[0];
assign ccg[1] = cg[1];
assign ccp[1] = cp[1];
assign ccg[2] = (cp[2] & cg[0]) | cg[2];
assign ccp[2] = cp[2] & cp[0];
assign ccg[3] = (cp[3] & cg[1]) | cg[3];
assign ccp[3] = cp[3] & cp[1];
//finall processing
assign c = ccg;
assign B[0] = p[0] ^ cin;
assign B[1] = p[1] ^ c[0];
assign B[2] = p[2] ^ c[1];
assign B[3] = p[3] ^ c[2];
assign carryout = c[3];
endmodule
| 7.621387
|
module top_module (
input clk,
input [7:0] in,
output [7:0] anyedge
);
reg [7:0] q;
always @(posedge clk) begin
q <= in;
anyedge <= q ^ in;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input [7:0] in,
input reset, // Synchronous reset
output [23:0] out_bytes,
output done
); //
// FSM from fsm_ps2
parameter A = 0, B = 1, C = 2, D = 3;
reg [1:0] state, nextstate;
reg [23:0] data;
// State transition logic (combinational)
always @(*) begin
case (state)
A: nextstate = in[3] ? B : A;
B: nextstate = C;
C: nextstate = D;
D: nextstate = in[3] ? B : A;
default: nextstate = 0;
endcase
end
// State flip-flops (sequential)
always @(posedge clk) begin
if (reset) state <= A;
else begin
state <= nextstate;
end
end
// Output logic
assign done = (state == D);
// New: Datapath to store incoming bytes.
always @(posedge clk) begin
if (reset) data <= 24'b0;
else data <= {data[15:8], data[7:0], in};
end
assign out_bytes = done ? data : {24{1'bx}};
endmodule
| 7.203305
|
module top_module (
input [3:0] in,
output [2:0] out_both,
output [3:1] out_any,
output [3:0] out_different
);
assign out_both = {in[2] & in[3], in[1] & in[2], in[0] & in[1]};
assign out_any = {in[3] | in[2], in[2] | in[1], in[1] | in[0]};
assign out_different = {in[3] ^ in[0], in[2] ^ in[3], in[1] ^ in[2], in[0] ^ in[1]};
endmodule
| 7.203305
|
module top_module (
input [4:0] a,
b,
c,
d,
e,
f,
output [7:0] w,
x,
y,
z
); //
// assign { ... } = { ... };
assign {w, x, y, z} = {a, b, c, d, e, f, 2'b11};
endmodule
| 7.203305
|
module top_module (
input a,
input b,
input c,
output out
); //
wire out_tmp;
assign out = ~out_tmp;
andgate inst1 (
out_tmp,
a,
b,
c,
1,
1
);
endmodule
| 7.203305
|
module top_module (
input a,
input b,
input c,
output out
); //
// andgate inst1 ( a, b, c, out );
wire and_out;
andgate inst1 (
.out(and_out),
.a (a),
.b (b),
.c (c),
.d (1'b1),
.e (1'b1)
);
assign out = ~and_out;
endmodule
| 7.203305
|
module top_module (
input [1:0] sel,
input [7:0] a,
input [7:0] b,
input [7:0] c,
input [7:0] d,
output [7:0] out
); //
wire [7:0] mux0;
wire [7:0] mux1;
mux2 u_mux2_1 (
sel[0],
a,
b,
mux0
);
mux2 u_mux2_2 (
sel[0],
c,
d,
mux1
);
mux2 u_mux2_3 (
sel[1],
mux0,
mux1,
out
);
endmodule
| 7.203305
|
module top_module (
input sel,
input [7:0] a,
input [7:0] b,
output [7:0] out
);
assign out = sel ? a : b;
endmodule
| 7.203305
|
module top_module (
input [1:0] sel,
input [7:0] a,
input [7:0] b,
input [7:0] c,
input [7:0] d,
output [7:0] out
); //
// wire mux0, mux1;
// mux2 mux0 ( sel[0], a, b, mux0 );
// mux2 mux1 ( sel[1], c, d, mux1 );
// mux2 mux2 ( sel[1], mux0, mux1, out );
wire [7:0] mux0, mux1;
mux2 mux2_u0 (
sel[0],
a,
b,
mux0
);
mux2 mux2_u1 (
sel[0],
c,
d,
mux1
);
mux2 mux2_u2 (
sel[1],
mux0,
mux1,
out
);
endmodule
| 7.203305
|
module top_module (
input do_sub,
input [7:0] a,
input [7:0] b,
output reg [7:0] out,
output reg result_is_zero
); //
always @(*) begin
case (do_sub)
0: out = a + b;
1: out = a - b;
endcase
if (out == 0) result_is_zero = 1;
else result_is_zero = 0;
end
endmodule
| 7.203305
|
module top_module (
input do_sub,
input [7:0] a,
input [7:0] b,
output reg [7:0] out,
output reg result_is_zero
); //
always @(*) begin
case (do_sub)
0: out = a + b;
1: out = a - b;
endcase
result_is_zero = ~(|out);
end
endmodule
| 7.203305
|
module top_module (
input a,
input b,
input c,
output out
); //
wire out_temp;
andgate inst1 (
.out(out_temp),
.a (a),
.b (b),
.c (c),
.d (1'b1),
.e (1'b1)
);
assign out = ~out_temp;
endmodule
| 7.203305
|
module top_module (
input [7:0] code,
output reg [3:0] out,
output reg valid
); //
always @(*) begin
out = 0;
valid = 1;
case (code)
8'h45: out = 0;
8'h16: out = 1;
8'h1e: out = 2;
8'h26: out = 3;
8'h25: out = 4;
8'h2e: out = 5;
8'h36: out = 6;
8'h3d: out = 7;
8'h3e: out = 8;
8'h46: out = 9;
default: valid = 0;
endcase
end
endmodule
| 7.203305
|
module top_module (
input [7:0] code,
output reg [3:0] out,
output reg valid
); //
always @(*)
case (code)
8'h45: begin
out = 0;
valid = 1;
end
8'h16: begin
out = 1;
valid = 1;
end
8'h1e: begin
out = 2;
valid = 1;
end
8'h26: begin
out = 3;
valid = 1;
end
8'h25: begin
out = 4;
valid = 1;
end
8'h2e: begin
out = 5;
valid = 1;
end
8'h36: begin
out = 6;
valid = 1;
end
8'h3d: begin
out = 7;
valid = 1;
end
8'h3e: begin
out = 8;
valid = 1;
end
8'h46: begin
out = 9;
valid = 1;
end
default: begin
out = 0;
valid = 0;
end
endcase
endmodule
| 7.203305
|
module top_module (
input [1:0] sel,
input [7:0] a,
input [7:0] b,
input [7:0] c,
input [7:0] d,
output [7:0] out
); //
wire [7:0] mux_out_0;
wire [7:0] mux_out_1;
mux2 mux0 (
sel[1],
a,
c,
mux_out_0
);
mux2 mux1 (
sel[1],
b,
d,
mux_out_1
);
mux2 mux2 (
sel[0],
mux_out_0,
mux_out_1,
out
);
endmodule
| 7.203305
|
module top_module (
input a,
input b,
output q
); //
assign q = a & b;
endmodule
| 7.203305
|
module top_module (
input do_sub,
input [7:0] a,
input [7:0] b,
output reg [7:0] out,
output reg result_is_zero
); //
always @(*) begin
case (do_sub)
1'b0: out = a + b;
1'b1: out = a - b;
endcase
if (out == 8'b0000_0000) result_is_zero = 1'b1;
else result_is_zero = 1'b0;
end
endmodule
| 7.203305
|
module top_module (
input a,
input b,
output q
); //
assign q = a & b;
endmodule
| 7.203305
|
module razhas_top_level (
input [7:0] io_in,
output [7:0] io_out
);
wire w_clk = io_in[0];
wire w_rst = io_in[1];
wire [3:0] w_duty = io_in[5:2]; // selects pwm signal duty cycle: 0% to 100% in increments of 10%. Values of 11-15 treated as 100%.
wire [1:0] w_freq = io_in[7:6]; // selects pwm signal frequency: 156.25 Hz, 312.5 Hz, 625 Hz, or 1250 Hz.
wire w_pwm; // pwm signal
assign io_out = {7'b0000000, w_pwm};
pwm_gen u0 (
.i_clk (w_clk),
.i_rst (w_rst),
.i_duty(w_duty),
.i_freq(w_freq),
.o_pwm (w_pwm)
);
endmodule
| 7.293351
|
module top_module (
input a,
input b,
input c,
input d,
output q
); //
assign q = (a + b + c + d == 0 | a + b + c + d == 2 | a + b + c + d == 4);
//you can also try to use Karnaugh map to find the logic.
endmodule
| 7.203305
|
module top_module (
input [7:0] code,
output reg [3:0] out,
output reg valid
); //
always @(*)
case (code)
8'h45: begin
out = 4'b0000;
valid = 1'b1;
end
8'h16: begin
out = 4'b0001;
valid = 1'b1;
end
8'h1e: begin
out = 4'b0010;
valid = 1'b1;
end
8'h26: begin
out = 4'b0011;
valid = 1'b1;
end
8'h25: begin
out = 4'b0100;
valid = 1'b1;
end
8'h2e: begin
out = 4'b0101;
valid = 1'b1;
end
8'h36: begin
out = 4'b0110;
valid = 1'b1;
end
8'h3d: begin
out = 4'b0111;
valid = 1'b1;
end
8'h3e: begin
out = 4'b1000;
valid = 1'b1;
end
8'h46: begin
out = 4'b1001;
valid = 1'b1;
end
default: begin
out = 4'b0000;
valid = 1'b0;
end
endcase
endmodule
| 7.203305
|
module top_module (
input a,
input b,
input c,
input d,
output q
); //
always @(*) begin
case ({
a, b, c, d
})
4'd0: q = 1;
4'd1: q = 0;
4'd2: q = 0;
4'd3: q = 1;
4'd4: q = 0;
4'd5: q = 1;
4'd6: q = 1;
4'd7: q = 0;
4'd8: q = 0;
4'd9: q = 1;
4'd10: q = 1;
4'd11: q = 0;
4'd12: q = 1;
4'd13: q = 0;
4'd14: q = 0;
4'd15: q = 1;
endcase
end
endmodule
| 7.203305
|
module c_BIN_EDGE_DETECTOR (
input [0:0] in_0,
output [0:0] out_0
);
wire net_0 = in_0;
wire net_1 = net_0;
wire net_2;
wire net_3;
wire net_4;
wire net_5;
assign out_0 = net_5;
f_K00 LogicGate_0 (
.in_1 (net_0),
.in_0 (net_4),
.out_0(net_5)
);
f_2 LogicGate_1 (
.in_0 (net_1),
.out_0(net_2)
);
f_2 LogicGate_2 (
.in_0 (net_2),
.out_0(net_3)
);
f_2 LogicGate_3 (
.in_0 (net_3),
.out_0(net_4)
);
endmodule
| 6.553472
|
module c_BIN_NAND_DLATCH (
input [0:0] in_0,
input [0:0] in_1,
output [0:0] out_0,
output [0:0] out_1
);
wire net_0 = in_0;
wire net_1 = net_0;
wire net_2 = in_1;
wire net_3 = net_2;
wire net_4;
wire net_5;
wire net_6;
wire net_7;
wire net_8;
assign out_0 = net_7;
assign out_1 = net_8;
f_22Z LogicGate_0 (
.in_1 (net_0),
.in_0 (net_2),
.out_0(net_4)
);
f_22Z LogicGate_1 (
.in_1 (net_3),
.in_0 (net_6),
.out_0(net_5)
);
f_2 LogicGate_2 (
.in_0 (net_1),
.out_0(net_6)
);
c_BIN_NAND_SR_LATCH SavedGate_0 (
.in_0 (net_4),
.in_1 (net_5),
.out_0(net_7),
.out_1(net_8)
);
endmodule
| 6.60502
|
module c_BIN_NAND_SR_LATCH (
input [0:0] in_0,
input [0:0] in_1,
output [0:0] out_0,
output [0:0] out_1
);
wire net_0 = in_0;
wire net_1 = in_1;
wire net_2;
wire net_3;
wire net_4 = net_2;
wire net_5 = net_3;
assign out_0 = net_4;
assign out_1 = net_5;
f_22Z LogicGate_0 (
.in_1 (net_0),
.in_0 (net_3),
.out_0(net_2)
);
f_22Z LogicGate_1 (
.in_1 (net_2),
.in_0 (net_1),
.out_0(net_3)
);
endmodule
| 6.860786
|
module c_BIN_ZOOK_DLATCH (
input [0:0] in_0,
input [0:0] in_1,
output [0:0] out_0
);
wire net_0 = in_0;
wire net_1 = in_1;
wire net_2;
wire net_3 = net_2;
assign out_0 = net_3;
f_Z00K00KKK LogicGate_0 (
.in_2 (net_0),
.in_0 (net_2),
.in_1 (net_1),
.out_0(net_2)
);
endmodule
| 6.781969
|
module f_2 (
input wire in_0,
output wire out_0
);
assign out_0 = (in_0 == 0);
endmodule
| 7.388176
|
module f_K00 (
input wire in_0,
input wire in_1,
output wire out_0
);
assign out_0 = (in_0 == 1 & in_1 == 1);
endmodule
| 6.889262
|
module f_Z00K00KKK (
input wire in_0,
input wire in_1,
input wire in_2,
output wire out_0
);
assign out_0 = (in_0 == 0 & in_1 == 1 & in_2 == 0) | (in_0 == 1 & in_1 == 1 & in_2 == 0) | (in_0 == 1 & in_1 == 0 & in_2 == 1) | (in_0 == 1 & in_1 == 1 & in_2 == 1);
endmodule
| 6.599243
|
module top_module (
input a,
input b,
input c,
input d,
output q
); //
assign q = (b & d) | (b & c) | (a & d) | (a & c);
endmodule
| 7.203305
|
module top_module (
input a,
input b,
input c,
input d,
output q
); //
always @(*) begin
case ({
a, b, c, d
})
4'd0: q = 0;
4'd1: q = 0;
4'd2: q = 0;
4'd3: q = 0;
4'd4: q = 0;
4'd5: q = 1;
4'd6: q = 1;
4'd7: q = 1;
4'd8: q = 0;
4'd9: q = 1;
4'd10: q = 1;
4'd11: q = 1;
4'd12: q = 0;
4'd13: q = 1;
4'd14: q = 1;
4'd15: q = 1;
endcase
end
endmodule
| 7.203305
|
module top_module (
input a,
input b,
output q
); //
assign q = a & b; // Fix me
endmodule
| 7.203305
|
module top_module (
input a,
input b,
input c,
input d,
output q
); //
assign q = b | c;
endmodule
| 7.203305
|
module top_module (
input a,
input b,
input c,
input d,
output q
); //
always @(*) begin
case ({
a, b, c, d
})
4'd0: q = 0;
4'd1: q = 0;
4'd2: q = 1;
4'd3: q = 1;
4'd4: q = 1;
4'd5: q = 1;
4'd6: q = 1;
4'd7: q = 1;
4'd8: q = 0;
4'd9: q = 0;
4'd10: q = 1;
4'd11: q = 1;
4'd12: q = 1;
4'd13: q = 1;
4'd14: q = 1;
4'd15: q = 1;
endcase
end
endmodule
| 7.203305
|
module top_module (
input a,
input b,
input c,
input d,
output q
); //
assign q = (~a)&(~b)&(~c)&(~d) | (~a)&(~b)&(c)&(d) | (~a)&(b)&(~c)&(d) | (~a)&(b)&(c)&(~d) |
(a)&(b)&(~c)&(~d) |(a)&(b)&(c)&(d) | (a)&(~b)&(~c)&(d) | (a)&(~b)&(c)&(~d); // Fix me
endmodule
| 7.203305
|
module top_module (
input [3:0] a,
input [3:0] b,
input [3:0] c,
input [3:0] d,
input [3:0] e,
output [3:0] q
);
always @(*) begin
case (c)
0: q = b;
1: q = e;
2: q = a;
3: q = d;
default: q = 4'hf;
endcase
end
endmodule
| 7.203305
|
module top_module (
input [3:0] a,
input [3:0] b,
input [3:0] c,
input [3:0] d,
input [3:0] e,
output [3:0] q
);
always @(*) begin
case (c)
4'h0: q = b;
4'h1: q = e;
4'h2: q = a;
4'h3: q = d;
default: q = 4'hf;
endcase
end
endmodule
| 7.203305
|
module top_module (
input a,
input b,
input c,
input d,
output q
); //
assign q = (a | b) & (c | d); // Fix me
endmodule
| 7.203305
|
module top_module (
input [2:0] a,
output reg [15:0] q
);
always @(*) begin
case (a)
0: q = 16'h1232;
1: q = 16'haee0;
2: q = 16'h27d4;
3: q = 16'h5a0e;
4: q = 16'h2066;
5: q = 16'h64ce;
6: q = 16'hc526;
7: q = 16'h2f19;
endcase
end
endmodule
| 7.203305
|
module top_module (
input [ 2:0] a,
output [15:0] q
);
always @(*) begin
case (a)
3'd0: q = 16'h1232;
3'd1: q = 16'haee0;
3'd2: q = 16'h27d4;
3'd3: q = 16'h5a0e;
3'd4: q = 16'h2066;
3'd5: q = 16'h64ce;
3'd6: q = 16'hc526;
3'd7: q = 16'h2f19;
endcase
end
endmodule
| 7.203305
|
module top_module (
input a,
input b,
input c,
input d,
output q
); //
assign q = b | ((~b) & c); // Fix me
endmodule
| 7.203305
|
module shift_ff (
input wire clk,
reset,
shift,
prev_dff,
d_in,
output wire q
);
mux2 m (
d_in,
prev_dff,
shift,
in
); // To select between shift and load operations
dfrl ff (
clk,
reset,
1'b1,
in,
q
);
endmodule
| 6.666654
|
module shift_register (
input wire clk,
reset,
load,
input wire [15:0] in,
output wire out_bit,
output wire [15:0] contents
);
// This is a module for one shift register, i.e a collection of 16 D-Flip Flops
// Loads data parallely and on each clock cycle shifts the data by one bit
// load is used to identify whether data is being loaded into the register or a shift should occur
// out_bit is the least significant bit of the the register that is used by the full adder to perform addition
wire shift; // This will be the inverse of the load input
wire intermediate[14:0];
invert n1 (
load,
shift
);
shift_ff d1 (
clk,
reset,
shift,
1'b0,
in[15],
intermediate[14]
);
shift_ff d2 (
clk,
reset,
shift,
intermediate[14],
in[14],
intermediate[13]
);
shift_ff d3 (
clk,
reset,
shift,
intermediate[13],
in[13],
intermediate[12]
);
shift_ff d4 (
clk,
reset,
shift,
intermediate[12],
in[12],
intermediate[11]
);
shift_ff d5 (
clk,
reset,
shift,
intermediate[11],
in[11],
intermediate[10]
);
shift_ff d6 (
clk,
reset,
shift,
intermediate[10],
in[10],
intermediate[9]
);
shift_ff d7 (
clk,
reset,
shift,
intermediate[9],
in[9],
intermediate[8]
);
shift_ff d8 (
clk,
reset,
shift,
intermediate[8],
in[8],
intermediate[7]
);
shift_ff d9 (
clk,
reset,
shift,
intermediate[7],
in[7],
intermediate[6]
);
shift_ff d10 (
clk,
reset,
shift,
intermediate[6],
in[6],
intermediate[5]
);
shift_ff d11 (
clk,
reset,
shift,
intermediate[5],
in[5],
intermediate[4]
);
shift_ff d12 (
clk,
reset,
shift,
intermediate[4],
in[4],
intermediate[3]
);
shift_ff d13 (
clk,
reset,
shift,
intermediate[3],
in[3],
intermediate[2]
);
shift_ff d14 (
clk,
reset,
shift,
intermediate[2],
in[2],
intermediate[1]
);
shift_ff d15 (
clk,
reset,
shift,
intermediate[1],
in[1],
intermediate[0]
);
shift_ff d16 (
clk,
reset,
shift,
intermediate[0],
in[0],
out_bit
);
assign contents = {
intermediate[14],
intermediate[13],
intermediate[12],
intermediate[11],
intermediate[10],
intermediate[9],
intermediate[8],
intermediate[7],
intermediate[6],
intermediate[5],
intermediate[4],
intermediate[3],
intermediate[2],
intermediate[1],
intermediate[0],
out_bit
};
endmodule
| 6.854847
|
module shift_resgister_out (
input wire clk,
reset,
in1,
output wire [15:0] sum
);
// This register is used to store the sum output
// in1 is the input bit received from the sum output of the fulladder
wire intermediate[14:0];
dfrl d1 (
clk,
reset,
1'b1,
in1,
intermediate[14]
);
dfrl d2 (
clk,
reset,
1'b1,
intermediate[14],
intermediate[13]
);
dfrl d3 (
clk,
reset,
1'b1,
intermediate[13],
intermediate[12]
);
dfrl d4 (
clk,
reset,
1'b1,
intermediate[12],
intermediate[11]
);
dfrl d5 (
clk,
reset,
1'b1,
intermediate[11],
intermediate[10]
);
dfrl d6 (
clk,
reset,
1'b1,
intermediate[10],
intermediate[9]
);
dfrl d7 (
clk,
reset,
1'b1,
intermediate[9],
intermediate[8]
);
dfrl d8 (
clk,
reset,
1'b1,
intermediate[8],
intermediate[7]
);
dfrl d9 (
clk,
reset,
1'b1,
intermediate[7],
intermediate[6]
);
dfrl d10 (
clk,
reset,
1'b1,
intermediate[6],
intermediate[5]
);
dfrl d11 (
clk,
reset,
1'b1,
intermediate[5],
intermediate[4]
);
dfrl d12 (
clk,
reset,
1'b1,
intermediate[4],
intermediate[3]
);
dfrl d13 (
clk,
reset,
1'b1,
intermediate[3],
intermediate[2]
);
dfrl d14 (
clk,
reset,
1'b1,
intermediate[2],
intermediate[1]
);
dfrl d15 (
clk,
reset,
1'b1,
intermediate[1],
intermediate[0]
);
assign sum = {
in1,
intermediate[14],
intermediate[13],
intermediate[12],
intermediate[11],
intermediate[10],
intermediate[9],
intermediate[8],
intermediate[7],
intermediate[6],
intermediate[5],
intermediate[4],
intermediate[3],
intermediate[2],
intermediate[1],
intermediate[0]
};
endmodule
| 6.776277
|
module shift_adder (
input wire clk,
reset,
load,
input wire [15:0] a,
b,
output wire [15:0] contents_a,
contents_b,
op,
output wire carry
);
// This is the serial shift adder module
// It takes two 16 bit numbers a and b as input and loads them to the shift registers a and b
// Their content is monitored using the output wires contents_a and contents_b respectively
// op is the output shift register where the output gets stored
// The full adder adds the LSBs of a and b at every clock cycle and pushes it onto the output shift register
// A DFF is used to hold the carry generated by the fulladder and this is fed back to the fulladder in the next clock cycle
wire t1, t2, fa_out, cin, cout;
shift_register a0 (
clk,
reset,
load,
a,
t1,
contents_a
);
shift_register b0 (
clk,
reset,
load,
b,
t2,
contents_b
);
fulladder fa (
t1,
t2,
cin,
fa_out,
cout
);
dfrl carry_hold (
clk,
reset,
1'b1,
cout,
cin
); // This DFF will hold the carry to be used by the full adder in the next clock cycle
shift_resgister_out ans (
clk,
reset,
fa_out,
op
);
assign carry = cout;
endmodule
| 7.572689
|
module Bit16Adder (
a,
b,
cin,
sum,
cout
);
input [16:1] a, b;
input cin;
output [16:1] sum;
output cout;
wire w1, w2, w3;
Bit4Adder B4A_0 (
a[4:1],
b[4:1],
cin,
sum[4:1],
w1
);
Bit4Adder B4A_1 (
a[8:5],
b[8:5],
w1,
sum[8:5],
w2
);
Bit4Adder B4A_2 (
a[12:9],
b[12:9],
w2,
sum[12:9],
w3
);
Bit4Adder B4A_3 (
a[16:13],
b[16:13],
w3,
sum[16:13],
cout
);
endmodule
| 6.99225
|
module invert (
output ib,
input b
);
assign ib = ~b;
endmodule
| 7.953624
|
module and2 (
input wire i0,
i1,
output wire o
);
assign o = i0 & i1;
endmodule
| 8.35921
|
module or2 (
input wire i0,
i1,
output wire o
);
assign o = i0 | i1;
endmodule
| 8.541431
|
module xor2 (
input wire i0,
i1,
output wire o
);
assign o = i0 ^ i1;
endmodule
| 8.782532
|
module nand2 (
input wire i0,
i1,
output wire o
);
wire t;
and2 and2_0 (
i0,
i1,
t
);
invert invert_0 (
t,
o
);
endmodule
| 7.360689
|
module nor2 (
input wire i0,
i1,
output wire o
);
wire t;
or2 or2_0 (
i0,
i1,
t
);
invert invert_0 (
t,
o
);
endmodule
| 7.781479
|
module xnor2 (
input wire i0,
i1,
output wire o
);
wire t;
xor2 xor2_0 (
i0,
i1,
t
);
invert invert_0 (
t,
o
);
endmodule
| 7.523861
|
module and3 (
input wire i0,
i1,
i2,
output wire o
);
wire t;
and2 and2_0 (
i0,
i1,
t
);
and2 and2_1 (
i2,
t,
o
);
endmodule
| 7.185291
|
module or3 (
input wire i0,
i1,
i2,
output wire o
);
wire t;
or2 or2_0 (
i0,
i1,
t
);
or2 or2_1 (
i2,
t,
o
);
endmodule
| 7.924047
|
module nor3 (
input wire i0,
i1,
i2,
output wire o
);
wire t;
or2 or2_0 (
i0,
i1,
t
);
nor2 nor2_0 (
i2,
t,
o
);
endmodule
| 7.838557
|
module nand3 (
input wire i0,
i1,
i2,
output wire o
);
wire t;
and2 and2_0 (
i0,
i1,
t
);
nand2 nand2_1 (
i2,
t,
o
);
endmodule
| 7.036906
|
module xor3 (
input wire i0,
i1,
i2,
output wire o
);
wire t;
xor2 xor2_0 (
i0,
i1,
t
);
xor2 xor2_1 (
i2,
t,
o
);
endmodule
| 8.362259
|
module xnor3 (
input wire i0,
i1,
i2,
output wire o
);
wire t;
xor2 xor2_0 (
i0,
i1,
t
);
xnor2 xnor2_0 (
i2,
t,
o
);
endmodule
| 7.872322
|
module fa (
input wire i0,
i1,
cin,
output wire sum,
cout
);
wire t0, t1, t2;
xor3 _i0 (
i0,
i1,
cin,
sum
);
and2 _i1 (
i0,
i1,
t0
);
and2 _i2 (
i1,
cin,
t1
);
and2 _i3 (
cin,
i0,
t2
);
or3 _i4 (
t0,
t1,
t2,
cout
);
endmodule
| 7.001699
|
module Adder (
a,
b,
sum
);
input [15:0] a, b;
output [15:0] sum;
wire cout;
wire [15:0] q;
fa fa1 (
a[0],
b[0],
1'b0,
sum[0],
q[0]
);
fa fa2 (
a[1],
b[1],
q[0],
sum[1],
q[1]
);
fa fa3 (
a[2],
b[2],
q[1],
sum[2],
q[2]
);
fa fa4 (
a[3],
b[3],
q[2],
sum[3],
q[3]
);
fa fa5 (
a[4],
b[4],
q[3],
sum[4],
q[4]
);
fa fa6 (
a[5],
b[5],
q[4],
sum[5],
q[5]
);
fa fa7 (
a[6],
b[6],
q[5],
sum[6],
q[6]
);
fa fa8 (
a[7],
b[7],
q[6],
sum[7],
q[7]
);
fa fa9 (
a[8],
b[8],
q[7],
sum[8],
q[8]
);
fa fa10 (
a[9],
b[9],
q[8],
sum[9],
q[9]
);
fa fa11 (
a[10],
b[10],
q[9],
sum[10],
q[10]
);
fa fa12 (
a[11],
b[11],
q[10],
sum[11],
q[11]
);
fa fa13 (
a[12],
b[12],
q[11],
sum[12],
q[12]
);
fa fa14 (
a[13],
b[13],
q[12],
sum[13],
q[13]
);
fa fa15 (
a[14],
b[14],
q[13],
sum[14],
q[14]
);
fa fa16 (
a[15],
b[15],
q[14],
sum[15],
cout
);
endmodule
| 6.808429
|
module booth_substep (
input wire signed [15:0] a,
Q,
input wire signed q0,
input wire signed [15:0] m,
output reg signed [15:0] f8,
output reg signed [15:0] l8,
output reg cq0
);
wire [15:0] addam, subam;
Adder myadd (
a,
m,
addam
);
subtractor mysub (
a,
m,
subam
);
//First if- 0, 0 or 1, 1
always @(*) begin
if (Q[0] == q0) begin
cq0 = Q[0];
l8 = Q >> 1;
l8[15] = a[0];
f8 = a >> 1;
if (a[15] == 1) f8[15] = 1;
end else if (Q[0] == 1 && q0 == 0) begin
cq0 = Q[0];
l8 = Q >> 1;
l8[15] = subam[0];
f8 = subam >> 1;
if (subam[15] == 1) f8[15] = 1;
end else begin
cq0 = Q[0];
l8 = Q >> 1;
l8[15] = addam[0];
f8 = addam >> 1;
if (addam[15] == 1) f8[15] = 1;
end
end
endmodule
| 6.761271
|
module mul16_unsigned (
input signed [15:0] A,
B,
input clk,
output signed [31:0] P
);
mul16_signed(
A, B, clk, P
);
endmodule
| 6.602435
|
module dff (
q,
d,
clk
);
input d, clk;
output q;
reg q;
always @(negedge clk) q <= d;
endmodule
| 8.035763
|
module shiftreg_tb;
reg [15:0] din;
reg sin, ld, mode, clk;
wire [15:0] dout;
shiftreg SR1 (
sin,
din,
dout,
ld,
mode,
clk
);
parameter STDIN = 32'h8000_0000;
integer testid;
integer ret;
initial begin
clk = 1'b1;
forever #50 clk = ~clk;
end
initial begin
ret = $fscanf(STDIN, "%d", testid);
case (testid)
0: begin
din = 16'b1111111111111111;
ld = 1'b1;
end
1: begin
din = 16'b0000000011000000;
ld = 1'b1;
#100 sin = 1'b1;
ld = 1'b0;
mode = 0;
end
2: begin
din = 16'b0000000011000000;
ld = 1'b1;
#100 sin = 1'b0;
ld = 1'b0;
mode = 0;
end
3: begin
din = 16'b0000000011000000;
ld = 1'b1;
#100 sin = 1'b0;
ld = 1'b0;
mode = 1;
end
4: begin
din = 16'b0000111100001111;
ld = 1'b1;
end
5: begin
din = 16'b0000000011000000;
ld = 1'b1;
#100 sin = 1'b1;
ld = 1'b0;
mode = 1;
end
default: begin
$display("Bad testcase id %d", testid);
$finish();
end
endcase
#100;
if ( (testid == 0 && din == 65535 && dout == 65535) ||
(testid == 1 && din == 192 && dout == 32864) ||
(testid == 2 && din == 192 && dout == 96) ||
(testid == 3 && din == 192 && dout == 384) ||
(testid == 4 && din == dout) ||
(testid == 5 && din == 192 && dout == 385) )
pass();
else fail();
end
task fail;
begin
$display("Fail: for clk=%d, mode=%d, ld=%d, sin=%d, din=%d and dout=%d is WRONG", clk, mode,
ld, sin, din, dout);
$finish();
end
endtask
task pass;
begin
$display("Pass: for clk=%d, mode=%d, ld=%d, sin=%d, din=%d and dout=%d", clk, mode, ld, sin,
din, dout);
$finish();
end
endtask
endmodule
| 6.713753
|
module bit16_4way_mux (
out,
i0,
i1,
i2,
i3,
s0,
s1
);
input [15:0] i0, i1, i2, i3;
input s0, s1;
output [15:0] out;
wire [15:0] x, y;
wire inv;
not_gate not_1 (
inv,
s0,
s0
); //complement of s0
//not_gate not_2(inv1,s1,s1); //complement of s1
mux_16 mux_1[15:0] (
x,
i0,
i1,
s0
);
mux_16 mux_2[15:0] (
y,
i2,
i3,
s0
);
mux_16 mux_3[15:0] (
out,
x,
y,
s1
);
endmodule
| 7.474265
|
module mux_8way (
out,
in0,
in1,
in2,
in3,
in4,
in5,
in6,
in7,
s0,
s1,
s2
);
output [15:0] out;
input [15:0] in0, in1, in2, in3, in4, in5, in6, in7;
input s0, s1, s2;
wire [15:0] x, y;
bit16_4way_mux mux_8way_1 (
x,
in0,
in1,
in2,
in3,
s0,
s1
);
bit16_4way_mux mux_8way_2 (
y,
in4,
in5,
in6,
in7,
s0,
s1
);
mux_2x1 mux_8way_3[15:0] (
out,
x,
y,
s2
);
endmodule
| 6.70825
|
module adder_4bit (
a,
b,
cin,
sum,
carry
);
output [3:0] sum;
output carry;
input [3:0] a;
input [3:0] b;
input cin;
wire [2:0] s;
Full_Adder u0 (
a[0],
b[0],
1'b0,
sum[0],
s[0]
);
Full_Adder u1 (
a[1],
b[1],
s[0],
sum[1],
s[1]
);
Full_Adder u2 (
a[2],
b[2],
s[1],
sum[2],
s[2]
);
Full_Adder u3 (
a[3],
b[3],
s[2],
sum[3],
carry
);
endmodule
| 9.041993
|
module adder_16bit (
a,
b,
sum,
carry
);
input [15:0] a;
input [15:0] b;
output [15:0] sum;
output carry;
wire [2:0] s;
adder_4bit u0 (
a[3:0],
b[3:0],
1'b0,
sum[3:0],
s[0]
);
adder_4bit u1 (
a[7:4],
b[7:4],
s[0],
sum[7:4],
s[1]
);
adder_4bit u2 (
a[11:8],
b[11:8],
s[1],
sum[11:8],
s[2]
);
adder_4bit u3 (
a[15:12],
b[15:12],
s[2],
sum[15:12],
carry
);
endmodule
| 7.133988
|
module mux4x1 (
in,
sel,
out
);
input [3:0] in;
input [1:0] sel;
output out;
wire [1:0] sel_bar;
wire in0s0, in1s1, in2s2, in3s3;
not n1 (sel_bar[0], sel[0]);
not n1 (sel_bar[1], sel[1]);
and a1 (in0s0, in[0], sel_bar[1], sel_bar[0]);
and a2 (in1s1, in[1], sel_bar[1], sel[0]);
and a3 (in2s2, in[2], sel[1], sel_bar[0]);
and a4 (in3s3, in[3], sel[1], sel[0]);
or o1 (out, in0s0, in1s1, in2s2, in3s3);
endmodule
| 6.791623
|
module gf2m #(
parameter DIGITAL = 16,
parameter DATA_WIDTH = 163
) (
input wire rst,
input wire clk,
input wire start,
input wire [DATA_WIDTH - 1 : 0] a,
input wire [DATA_WIDTH - 1 : 0] g,
input wire [DIGITAL - 1:0] b,
output reg [DATA_WIDTH - 1 : 0] t_i_j,
output reg done
);
parameter ITERATION_NUMBER = DATA_WIDTH / DIGITAL;
parameter IDLE = 1'b0;
parameter CAL = 1'b1;
reg state;
reg [12:0] counter;
wire [DATA_WIDTH - 1 : 0] wire_t_i_j;
serial serial_8_bit (
.b(b),
.a(a),
.g(g),
.t_i1_j1(t_i_j),
.t_i_j(wire_t_i_j)
);
always @(posedge clk or negedge rst) begin : proc_counter
if (~rst) begin
counter <= 0;
end else begin
case (state)
IDLE: begin
counter <= 6'd0;
end
CAL: begin
if (counter < ITERATION_NUMBER) counter <= counter + 1;
else counter <= 6'd0;
end
default: /* default */;
endcase
end
end
always @(posedge clk or negedge rst) begin : proc_t_i_j
if (~rst) begin
t_i_j <= 0;
end else begin
case (state)
IDLE: t_i_j <= 0;
CAL: t_i_j <= wire_t_i_j;
default: t_i_j <= 0;
endcase
end
end
always @(posedge clk or negedge rst) begin : proc_done
if (~rst) begin
done <= 0;
end else begin
case (state)
IDLE: done <= 0;
CAL: begin
if (counter < ITERATION_NUMBER) done <= 0;
else done <= 1'b1;
end
default: done <= 0;
endcase
end
end
always @(posedge clk or negedge rst) begin : proc_state
if (~rst) begin
state <= IDLE;
end else begin
case (state)
IDLE: begin : IDLE_STATE
if (start) state <= CAL;
else state <= state;
end
CAL: begin : CAL_STATE
if (counter < ITERATION_NUMBER) state <= CAL;
else state <= IDLE;
end
default: state <= IDLE;
endcase
end
end
endmodule
| 7.196913
|
module flop_16bit (
rst_n,
x,
y,
clk,
stall
);
input rst_n, clk, stall;
input [15:0] x;
output reg [15:0] y;
always @(posedge clk, negedge rst_n) begin
if (!rst_n) y <= 0;
else if (stall) y <= y;
else y <= x;
end
endmodule
| 8.140276
|
module PGU (
a,
b,
p,
g
);
input [15:0] a, b;
output [15:0] p, g;
assign p = a ^ b;
assign g = a & b;
endmodule
| 7.368717
|
module BCLU (
p,
g,
cin,
ps,
gs,
c
);
input [3:0] p, g;
input cin;
output ps, gs;
output [2:0] c;
assign ps = p[3] & p[2] & p[1] & p[0];
assign gs = g[3] | p[3] & g[2] | p[3] & p[2] & g[1] | p[3] & p[2] & p[1] & g[0];
assign c[0] = g[0] | p[0] & cin;
assign c[1] = g[1] | p[1] & g[0] | p[1] & p[0] & cin;
assign c[2] = g[2] | p[2] & g[1] | p[2] & p[1] & g[0] | p[2] & p[1] & p[0] & cin;
endmodule
| 7.053402
|
module CLU (
ps,
gs,
cin,
c
);
input ps, gs, cin;
output c;
assign c = gs | ps & cin;
endmodule
| 7.105785
|
module SU (
p,
cin,
c,
s
);
input [15:0] p;
input cin;
input [14:0] c;
output [15:0] s;
assign s = p ^ {c, cin};
endmodule
| 7.057463
|
module D1_3bit (
in,
clk,
out
);
input [2:0] in;
input clk;
output reg [2:0] out;
always @(posedge clk) begin
out <= in;
end
endmodule
| 6.884111
|
module D1_4bit (
in,
clk,
out
);
input [3:0] in;
input clk;
output reg [3:0] out;
always @(posedge clk) begin
out <= in;
end
endmodule
| 7.122843
|
module D1_16bit (
in,
clk,
out
);
input [15:0] in;
input clk;
output reg [15:0] out;
always @(posedge clk) begin
out <= in;
end
endmodule
| 6.605137
|
module DD2 (
in,
clk,
out
);
input in, clk;
output reg out;
reg r_data;
always @(posedge clk) begin
r_data <= in;
out <= r_data;
end
endmodule
| 6.600992
|
module DD4 (
in,
clk,
out
);
input in, clk;
output reg out;
reg [2:0] r_data;
always @(posedge clk) begin
r_data[0] <= in;
r_data[1] <= r_data[0];
r_data[2] <= r_data[1];
out <= r_data[2];
end
endmodule
| 6.511385
|
module DD2_4bit (
in,
clk,
out
);
input [3:0] in;
input clk;
output reg [3:0] out;
reg [3:0] r_data;
always @(posedge clk) begin
r_data <= in;
out <= r_data;
end
endmodule
| 7.031347
|
module DD3_4bit (
in,
clk,
out
);
input [3:0] in;
input clk;
output reg [3:0] out;
reg [3:0] r_data[0:1];
always @(posedge clk) begin
r_data[0] <= in;
r_data[1] <= r_data[0];
out <= r_data[1];
end
endmodule
| 6.638852
|
module DD2_3bit (
in,
clk,
out
);
input [2:0] in;
input clk;
output reg [2:0] out;
reg [2:0] r_data;
always @(posedge clk) begin
r_data <= in;
out <= r_data;
end
endmodule
| 6.963781
|
module DD3_3bit (
in,
clk,
out
);
input [2:0] in;
input clk;
output reg [2:0] out;
reg [2:0] r_data[0:1];
always @(posedge clk) begin
r_data[0] <= in;
r_data[1] <= r_data[0];
out <= r_data[1];
end
endmodule
| 6.61913
|
module DD4_3bit (
in,
clk,
out
);
input [2:0] in;
input clk;
output reg [2:0] out;
reg [2:0] r_data[0:2];
always @(posedge clk) begin
r_data[0] <= in;
r_data[1] <= r_data[0];
r_data[2] <= r_data[1];
out <= r_data[2];
end
endmodule
| 6.941144
|
module DD4_16bit (
in,
clk,
out
);
input [15:0] in;
input clk;
output reg [15:0] out;
reg [15:0] r_data[0:2];
always @(posedge clk) begin
r_data[0] <= in;
r_data[1] <= r_data[0];
r_data[2] <= r_data[1];
out <= r_data[2];
end
endmodule
| 7.075333
|
module Pip16CLA (
a,
b,
cin,
clk,
s,
cout
);
input [15:0] a, b;
input cin;
input clk;
output [15:0] s;
output cout;
wire cin2;
wire cin22;
wire [15:0] a2, b2, p, g, p2, g2, p22; //pccc
wire [11:0] p222, g222; //pcc, gcc
wire [14:0] c;
wire [ 2:0] c2;
wire [15:0] c22;
wire [3:0] ps, gs, ps2, gs2;
//D1 PGU
D1_16bit D1 (
a,
clk,
a2
);
D1_16bit D2 (
b,
clk,
b2
);
PGU PGU0 (
a2,
b2,
p,
g
);
D1_16bit D3 (
p,
clk,
p2
);
D1_16bit D4 (
g,
clk,
g2
);
//BCLU0
DD2 D11 (
cin,
clk,
cin2
);
BCLU BCLU0 (
p2[3:0],
g2[3:0],
cin2,
ps[0],
gs[0],
c[2:0]
);
DD1 D12 (
ps[0],
clk,
ps2[0]
);
DD1 D13 (
gs[0],
clk,
gs2[0]
);
//CLU0
DD3 D21 (
cin,
clk,
cin22
);
CLU CLU0 (
ps2[0],
gs2[0],
cin22,
c[3]
);
//BCLU1
D1_4bit D31 (
p2[7:4],
clk,
p222[3:0]
);
D1_4bit D32 (
g2[7:4],
clk,
g222[3:0]
);
BCLU BCLU1 (
p222[3:0],
g222[3:0],
c[3],
ps[1],
gs[1],
c[6:4]
);
DD1 D33 (
ps[1],
clk,
ps2[1]
);
DD1 D34 (
gs[1],
clk,
gs2[1]
);
//CLU1
DD1 D41 (
c[3],
clk,
c2[0]
);
CLU CLU1 (
ps2[1],
gs2[1],
c2[0],
c[7]
);
//BCLU2
DD2_4bit D42 (
p2[11:8],
clk,
p222[7:4]
);
DD2_4bit D43 (
g2[11:8],
clk,
g222[7:4]
);
BCLU BCLU2 (
p222[7:4],
g222[7:4],
c[7],
ps[2],
gs[2],
c[10:8]
);
DD1 D44 (
ps[2],
clk,
ps2[2]
);
DD1 D45 (
gs[2],
clk,
gs2[2]
);
//CLU2
DD1 D51 (
c[7],
clk,
c2[1]
);
CLU CLU2 (
ps2[2],
gs2[2],
c2[1],
c[11]
);
//BCLU3
DD3_4bit D52 (
p2[15:12],
clk,
p222[11:8]
);
DD3_4bit D53 (
g2[15:12],
clk,
g222[11:8]
);
BCLU BCLU3 (
p222[11:8],
g222[11:8],
c[11],
ps[3],
gs[3],
c[14:12]
);
DD1 D54 (
ps[3],
clk,
ps2[3]
);
DD1 D55 (
gs[3],
clk,
gs2[3]
);
//CLU3
DD1 D61 (
c[11],
clk,
c2[2]
);
CLU CLU3 (
ps2[3],
gs2[3],
c2[2],
cout
);
//SU
DD3 D71 (
cin22,
clk,
c22[0]
);
DD4_3bit D72 (
c[2:0],
clk,
c22[3:1]
);
DD3 D73 (
c[3],
clk,
c22[4]
);
DD3_3bit D74 (
c[6:4],
clk,
c22[7:5]
);
DD2 D75 (
c[7],
clk,
c22[8]
);
DD2_3bit D76 (
c[10:8],
clk,
c22[11:9]
);
DD1 D77 (
c[11],
clk,
c22[12]
);
D1_3bit D81 (
c[14:12],
clk,
c22[15:13]
);
DD4_16bit D82 (
p2[15:0],
clk,
p22[15:0]
);
SU SU0 (
p22,
c22[0],
c22[15:1],
s
);
endmodule
| 6.942108
|
module fulladder (
a,
b,
cin,
s,
cout
);
input a, b, cin;
output s, cout;
assign s = (a ^ b) ^ cin;
assign cout = ((a & b) | ((a ^ b) & cin));
endmodule
| 7.454465
|
module DD2 (
in,
clk,
out
);
input in, clk;
output reg out;
reg r_data;
always @(posedge clk) begin
r_data <= in;
out <= r_data;
end
endmodule
| 6.600992
|
module DD4 (
in,
clk,
out
);
input in, clk;
output reg out;
reg [2:0] r_data;
always @(posedge clk) begin
r_data[0] <= in;
r_data[1] <= r_data[0];
r_data[2] <= r_data[1];
out <= r_data[2];
end
endmodule
| 6.511385
|
module Pip4RCA (
a,
b,
cin,
clk,
s,
cout
);
input [3:0] a, b;
input cin;
input clk;
output [3:0] s;
output cout;
wire [2:0] c;
wire [2:0] c2;
wire [3:0] b2;
wire [3:0] a2;
wire [3:0] out;
wire cin2;
//FA0? ??? ? ?? s0, c0
DD1 D1 (
a[0],
clk,
a2[0]
);
DD1 D2 (
b[0],
clk,
b2[0]
);
DD1 D3 (
cin,
clk,
cin2
);
fulladder AD0 (
a2[0],
b2[0],
cin2,
out[0],
c[0]
);
DD3 D3_1 (
out[0],
clk,
s[0]
);
//FA1? ??? ? ?? s1, c1
DD1 D11 (
c[0],
clk,
c2[0]
);
DD2 D21 (
a[1],
clk,
a2[1]
);
DD2 D22 (
b[1],
clk,
b2[1]
);
fulladder AD1 (
a2[1],
b2[1],
c2[0],
out[1],
c[1]
);
DD2 D2_1 (
out[1],
clk,
s[1]
);
//FA2? ??? ? ?? s2, c2
DD1 D12 (
c[1],
clk,
c2[1]
);
DD3 D31 (
a[2],
clk,
a2[2]
);
DD3 D32 (
b[2],
clk,
b2[2]
);
fulladder AD2 (
a2[2],
b2[2],
c2[1],
out[2],
c[2]
);
DD1 D1_1 (
out[2],
clk,
s[2]
);
//FA3? ??? ? ?? s3, c3
DD1 D13 (
c[2],
clk,
c2[2]
);
DD4 D41 (
a[3],
clk,
a2[3]
);
DD4 D42 (
b[3],
clk,
b2[3]
);
fulladder AD3 (
a2[3],
b2[3],
c2[2],
out[3],
cout
);
assign s[3] = out[3];
endmodule
| 6.853022
|
module DD1_16 (
in,
clk,
out
);
input [15:0] in;
input clk;
output reg [15:0] out;
always @(posedge clk) begin
out <= in;
end
endmodule
| 6.966147
|
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