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stringlengths 35
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module till_60_counter (
input clk,
input reset, // Synchronous active-high reset
input en,
output reg [7:0] q
);
BCD_counter inst_1 (
clk,
reset || q[3:0] == 9,
en,
q[3:0]
);
BCD_counter inst_2 (
clk,
reset || q == 8'h59,
en && q[3:0] == 9,
q[7:4]
);
endmodule
| 7.348284
|
module BCD_counter (
input clk,
input reset, // Synchronous active-high reset
input en,
output reg [3:0] q
);
always @(posedge clk) begin
if (reset) q <= 0;
else if (en) q <= q + 4'd1;
else q <= q;
end
endmodule
| 6.772334
|
module top_module (
input clk,
input reset,
input ena,
output pm,
output [7:0] hh,
output [7:0] mm,
output [7:0] ss
);
wire [1:0] c_reset;
wire [2:1] c_enable;
wire [3:0] h;
countbcd2 count0 (
clk,
c_reset[0] | reset,
ena,
ss
);
countbcd2 count1 (
clk,
c_reset[1] | reset,
c_enable[1] & ena,
mm
);
count12 count2 (
clk,
reset,
c_enable[2] & ena,
h
);
assign c_enable[1] = ss[7:4] == 4'd5 && ss[3:0] == 4'd9;
assign c_enable[2] = mm[7:4] == 4'd5 && mm[3:0] == 4'd9 && ss[7:4] == 4'd5 && ss[3:0] == 4'd9;
assign c_reset[0] = ss[7:4] == 4'd5 && ss[3:0] == 4'd9;
assign c_reset[1] = mm[7:4] == 4'd5 && mm[3:0] == 4'd9 && ss[7:4] == 4'd5 && ss[3:0] == 4'd9;
always @(posedge clk) begin
pm <= ((h == 4'd11 && mm[7:4] == 4'd5 && mm[3:0] == 4'd9 && ss[7:4] == 4'd5 && ss[3:0] == 4'd9) & ~pm)
| (!(h == 4'd11 && mm[7:4] == 4'd5 && mm[3:0] == 4'd9 && ss[7:4] == 4'd5 && ss[3:0] == 4'd9) & pm);
end
always @(*) begin
case (h)
4'd1: hh = 8'h01;
4'd2: hh = 8'h02;
4'd3: hh = 8'h03;
4'd4: hh = 8'h04;
4'd5: hh = 8'h05;
4'd6: hh = 8'h06;
4'd7: hh = 8'h07;
4'd8: hh = 8'h08;
4'd9: hh = 8'h09;
4'd10: hh = 8'h10;
4'd11: hh = 8'h11;
4'd12: hh = 8'h12;
endcase
end
endmodule
| 7.203305
|
module countbcd2 (
input clk,
input reset,
input enable,
output [7:0] q
);
wire c_enable;
count10 count0 (
clk,
reset,
enable,
q[3:0]
);
count10 count1 (
clk,
reset,
c_enable & enable,
q[7:4]
);
assign c_enable = q[3:0] == 4'd9;
endmodule
| 6.811554
|
module count12 (
input clk,
input reset,
input enable,
output [3:0] Q
);
always @(posedge clk) begin
if (reset) begin
Q <= 4'd12;
end else begin
if (enable) begin
if (Q == 4'd12) begin
Q <= 4'd1;
end else begin
Q <= Q + 1'b1;
end
end
end
end
endmodule
| 7.086595
|
module top_module (
input clk,
input reset,
input ena,
output pm,
output [7:0] hh,
output [7:0] mm,
output [7:0] ss
);
always @(posedge clk) begin
if (reset) begin
hh <= 8'h12;
mm <= 0;
ss <= 0;
pm <= 0;
end else begin
if (ena) begin
pm <= (hh == 8'h11 && mm == 8'h59 && ss == 8'h59) ? ~pm : pm;
if (ss == 8'h59) begin // ss = 59
ss <= 0;
if (mm == 8'h59) begin // mm = 59
mm <= 0;
if (hh == 8'h12) begin
hh <= 8'h01;
end else begin
if (hh[3:0] == 4'd9) begin
hh[3:0] <= 0;
hh[7:4] <= hh[7:4] + 4'd1;
end else hh[3:0] <= hh[3:0] + 4'd1;
end
end else begin
if (mm[3:0] == 4'd9) begin
mm[3:0] <= 0;
mm[7:4] <= mm[7:4] + 4'd1;
end else mm[3:0] <= mm[3:0] + 4'd1;
end
end else begin
if (ss[3:0] == 4'd9) begin
ss[3:0] <= 0;
ss[7:4] <= ss[7:4] + 4'd1;
end else ss[3:0] <= ss[3:0] + 4'd1;
end
end
end
end
endmodule
| 7.203305
|
module top_module (
input x,
input y,
output z
);
wire a1, a2, b1, b2;
simA A1 (
x,
y,
a1
);
simB B1 (
x,
y,
b1
);
simA A2 (
x,
y,
a2
);
simB B2 (
x,
y,
b2
);
assign z = (a1 | b1) ^ (a2 & b2);
endmodule
| 7.203305
|
module simA (
input x,
input y,
output z
);
assign z = (x ^ y) & x;
endmodule
| 7.383328
|
module simB (
input x,
input y,
output z
);
assign z = ~(x ^ y);
endmodule
| 7.52887
|
module top_module (
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
input dig,
output walk_left,
output walk_right,
output aaah,
output digging
);
parameter [2:0] left = 3'd0, right = 3'd1, fall_l = 3'd2, fall_r = 3'd3, dig_l = 3'd4, dig_r = 3'd5;
reg [2:0] state, nextstate;
always @(*) begin
case (state)
left: nextstate = (~ground) ? fall_l : ((dig) ? dig_l : ((bump_left) ? right : left));
right: nextstate = (~ground) ? fall_r : ((dig) ? dig_r : ((bump_right) ? left : right));
fall_l: nextstate = (~ground) ? fall_l : left;
fall_r: nextstate = (~ground) ? fall_r : right;
dig_l: nextstate = (~ground) ? fall_l : dig_l;
dig_r: nextstate = (~ground) ? fall_r : dig_r;
default: nextstate = 3'bxxx;
endcase
end
always @(posedge clk, posedge areset) begin
if (areset) state <= left;
else state <= nextstate;
end
assign walk_left = (state == left);
assign walk_right = (state == right);
assign aaah = (state == fall_l | state == fall_r);
assign digging = (state == dig_l | state == dig_r);
endmodule
| 7.203305
|
module top_module (
input clk,
input w,
R,
E,
L,
output Q
);
always @(posedge clk) begin
Q <= L ? R : (E ? w : Q);
end
endmodule
| 7.203305
|
module mips_ram (
Addr_i,
D_in,
W_en,
Mode,
D_out,
clk
);
input [11:0] Addr_i;
input [31:0] D_in;
input [1:0] Mode;
input W_en;
input clk;
output reg [31:0] D_out;
reg [ 7:0] data [2**12-1:0];
reg [11:0] addr;
always @(negedge clk) begin
case (Mode[1:0])
2'b00: begin //32
addr[11:0] = 0;
addr[9:0] = (Addr_i >> 2) << 2;
if (W_en) begin //写
data[addr] = D_in[7:0];
addr = addr + 1;
data[addr] = D_in[15:8];
addr = addr + 1;
data[addr] = D_in[23:16];
addr = addr + 1;
data[addr] = D_in[31:24];
end else begin //读
D_out[7:0] = data[addr];
addr = addr + 1;
D_out[15:8] = data[addr];
addr = addr + 1;
D_out[23:16] = data[addr];
addr = addr + 1;
D_out[31:24] = data[addr];
end
end
2'b10: begin //16
addr[11:0] = 0;
addr[9:0] = (Addr_i >> 2) << 2;
addr = addr + Addr_i[1] * 2;
if (W_en) begin
data[addr] = D_in[7:0];
addr = addr + 1;
data[addr] = D_in[15:8];
end else begin
D_out[7:0] = data[addr];
addr = addr + 1;
D_out[15:8] = data[addr];
D_out[31:16] = 0;
end
end
2'b01: begin //8
if (W_en) begin
//addr[11:0] = 0;
//addr[9:0] = (Addr_i >> 2) << 2;
//addr = addr + Addr_i[1:0];
data[Addr_i] = D_in[7:0];
end else begin
//addr[11:0] = 0;
//addr[9:0] = (Addr_i >> 2) << 2;
//addr = addr + Addr_i[1:0];
D_out[7:0] = data[Addr_i];
D_out[31:8] = 0;
end
end
endcase
end
endmodule
| 7.033707
|
module ALU (
out,
select,
a,
b
);
output reg [4:0] out;
input [2:0] select;
input [3:0] a, b;
initial out = 5'b00000;
always @(a or b or select) begin
case (select)
3'b000: out = a;
3'b001: out = a + b;
3'b010: out = a - b;
3'b011: out = a / b;
3'b100: out = a % b;
3'b101: out = a << 1;
3'b110: out = a << 1;
3'b111: out = (a > b);
endcase
end
endmodule
| 7.50292
|
module top_module (
input wire [15:0] in,
output wire [ 7:0] out_hi,
output wire [ 7:0] out_lo
);
assign out_hi = in[15 : 8];
assign out_lo = in[7 : 0];
endmodule
| 7.203305
|
module declaration syntax here:
module top_module(clk, reset, in, out);
input clk;
input reset; // Synchronous reset to state B
input in;
output out;//
// Fill in state name declarations
parameter A = 0, B = 1;
reg present_state, next_state;
always @(posedge clk) begin
if (reset) present_state <= B;
else present_state <= next_state;
end
always @(*) begin
case (present_state)
B : next_state <= (in == 1) ? B : A;
A : next_state <= (in == 1) ? A : B;
endcase
end
assign out = (present_state == B);
endmodule
| 6.89453
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if ((!((aluop || move) || load)))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (0)
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (1)
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load)) begin
end
assign current_opcode = opcode;
endmodule
| 6.868788
|
module declaration syntax here:
module top_module(clk, reset, in, out);
input clk;
input reset; // Synchronous reset to state B
input in;
output out;//
reg out;
// Fill in state name declarations
reg present_state, next_state;
parameter A = 1'b0;
parameter B = 1'b1;
// sequential logic state transition
always @(posedge clk)
begin
if(reset)
present_state <= B;
else
present_state <= next_state;
end
// combinational logic state transiton logic
always @(*)
begin
case(present_state)
A:
if(in)
next_state = A;
else
next_state = B;
B:
if(in)
next_state = B;
else
next_state = A;
default: next_state = 1'bx;
endcase
end
// combinational logic ouput
always @(*)
begin
if(present_state == A)
out = 0;
else
out = 1;
end
endmodule
| 6.89453
|
module declaration syntax here:
module top_module(clk, reset, in, out);
input clk;
input reset; // Synchronous reset to state B
input in;
output out;//
parameter A=0, B=1; // Fill in state name declarations
reg present_state, next_state;
always @(*) begin
case (present_state)
A: next_state = in ? A : B;
B: next_state = in ? B : A;
endcase
end
always @(posedge clk) begin
if(reset) present_state <= B;
else present_state <= next_state;
end
assign out = (present_state == 1);
endmodule
| 6.89453
|
module top_module (
input clk,
input areset, // Asynchronous reset to OFF
input j,
input k,
output out
); //
parameter OFF = 0, ON = 1;
reg state, next_state;
always @(*) begin
// State transition logic
case (state)
OFF: next_state = (j == 1) ? ON : OFF;
ON: next_state = (k == 1) ? OFF : ON;
endcase
end
always @(posedge clk, posedge areset) begin
// State flip-flops with asynchronous reset
if (areset) state <= OFF;
else state <= next_state;
end
// Output logic
assign out = (state == ON);
endmodule
| 7.203305
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if ((!ue[4]))
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (0)
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (1)
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4]) begin
end
assign current_opcode = opcode;
endmodule
| 6.868788
|
module top_module (
input clk,
input areset, // Asynchronous reset to OFF
input j,
input k,
output reg out
); //
// parameter
parameter OFF = 1'b0;
parameter ON = 1'b1;
// signal declaration
reg present_state;
reg next_state;
// sequential logic state transition
always @(posedge clk or posedge areset) begin
if (areset) present_state <= OFF;
else present_state <= next_state;
end
// combinational logic state transition
always @(*) begin
case (present_state)
OFF:
if (j) next_state = ON;
else next_state = OFF;
ON:
if (k) next_state = OFF;
else next_state = ON;
default: next_state = 1'bx;
endcase
end
// combinational logic output
always @(*) begin
if (present_state == OFF) out = 0;
else out = 1;
end
endmodule
| 7.203305
|
module rglenn_hex_to_7_seg (
input [7:0] io_in,
output [7:0] io_out
);
wire latch = io_in[0];
wire blank = io_in[1];
wire [4:0] data = io_in[5:2];
wire [6:0] led_out;
assign io_out[6:0] = blank ? 7'b0000000 : led_out;
assign io_out[7] = io_in[6]; // decimal point
// external clock is 1000Hz, so need 10 bit counter
reg [3:0] data_reg;
always @(posedge latch) begin
data_reg <= data;
end
// instantiate segment display
hex2seg7 hex2seg7 (
.data(data_reg),
.segments(led_out)
);
endmodule
| 7.211883
|
module top_module (
input clk,
input areset, // Asynchronous reset to OFF
input j,
input k,
output out
); //
parameter OFF = 0, ON = 1;
reg state, next_state;
always @(*) begin
case (state)
OFF: next_state = j ? ON : OFF;
ON: next_state = k ? OFF : ON;
endcase // State transition logic
end
always @(posedge clk, posedge areset) begin
if (areset) state <= OFF; // State flip-flops with asynchronous reset
else state <= next_state;
end
// Output logic
assign out = (state == 0) ? 0 : 1; // assign out = (state == ...);
endmodule
| 7.203305
|
module top_module (
input clk,
input reset, // Asynchronous reset to OFF
input j,
input k,
output out
); //
parameter OFF = 0, ON = 1;
reg state, next_state;
always @(*) begin
// State transition logic
case (state)
OFF: next_state = (j == 1) ? ON : OFF;
ON: next_state = (k == 1) ? OFF : ON;
endcase
end
always @(posedge clk) begin
// State flip-flops with asynchronous reset
if (reset) state <= OFF;
else state <= next_state;
end
// Output logic
assign out = (state == ON);
endmodule
| 7.203305
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if ((!rst)) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (0) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (1) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
end
assign current_opcode = opcode;
endmodule
| 6.868788
|
module top_module (
input clk,
input reset, // Asynchronous reset to OFF
input j,
input k,
output reg out
); //
// parameter
parameter OFF = 1'b0;
parameter ON = 1'b1;
// signal declaration
reg present_state;
reg next_state;
// sequential logic state transition
always @(posedge clk) begin
if (reset) present_state <= OFF;
else present_state <= next_state;
end
// combinational logic state transition
always @(*) begin
case (present_state)
OFF:
if (j) next_state = ON;
else next_state = OFF;
ON:
if (k) next_state = OFF;
else next_state = ON;
default: next_state = 1'bx;
endcase
end
// combinational logic output
always @(*) begin
if (present_state == OFF) out = 0;
else out = 1;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input reset, // Synchronous reset to OFF
input j,
input k,
output out
); //
parameter OFF = 0, ON = 1;
reg state, next_state;
always @(*) begin
case (state)
OFF: next_state = j ? ON : OFF;
ON: next_state = k ? OFF : ON;
endcase // State transition logic
end
always @(posedge clk) begin
if (reset) state <= OFF;
else state <= next_state;
// State flip-flops with synchronous reset
end
// Output logic
assign out = (state == 0) ? 0 : 1; // assign out = (state == ...);
endmodule
| 7.203305
|
module top_module (
input in,
input [1:0] state,
output [1:0] next_state,
output out
); //
parameter A = 0, B = 1, C = 2, D = 3;
// State transition logic: next_state = f(state, in)
always @(*) begin
case (state)
A: next_state = (in == 1) ? B : A;
B: next_state = (in == 1) ? B : C;
C: next_state = (in == 1) ? D : A;
D: next_state = (in == 1) ? B : C;
endcase
end
// Output logic: out = f(state) for a Moore state machine
assign out = (state == D);
endmodule
| 7.203305
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always begin
end
assign current_opcode = opcode;
endmodule
| 6.868788
|
module top_module (
input in,
input [1:0] state,
output reg [1:0] next_state,
output reg out
); //
parameter A = 2'b00;
parameter B = 2'b01;
parameter C = 2'b10;
parameter D = 2'b11;
// State transition logic: next_state = f(state, in)
always @(*) begin
case (state)
A:
if (in) next_state = B;
else next_state = A;
B:
if (in) next_state = B;
else next_state = C;
C:
if (in) next_state = D;
else next_state = A;
D:
if (in) next_state = B;
else next_state = C;
default: next_state = 2'bx;
endcase
end
// Output logic: out = f(state) for a Moore state machine
always @(*) begin
case (state)
A: out = 1'b0;
B: out = 1'b0;
C: out = 1'b0;
D: out = 1'b1;
default: out = 1'bx;
endcase
end
endmodule
| 7.203305
|
module top_module (
input in,
input [1:0] state,
output [1:0] next_state,
output out
); //
parameter A = 0, B = 1, C = 2, D = 3;
// State transition logic: next_state = f(state, in)
always @(*) begin
case (state)
A: next_state = in ? B : A;
B: next_state = in ? B : C;
C: next_state = in ? D : A;
D: next_state = in ? B : C;
endcase
end
// Output logic: out = f(state) for a Moore state machine
assign out = (state == D);
endmodule
| 7.203305
|
module top_module (
input in,
input [3:0] state,
output [3:0] next_state,
output out
); //
parameter A = 0, B = 1, C = 2, D = 3;
// State transition logic: Derive an equation for each state flip-flop.
assign next_state[A] = (state[A] & ~in) | (state[C] & ~in);
assign next_state[B] = (state[A] & in) | (state[B] & in) | (state[D] & in);
assign next_state[C] = (state[B] & ~in) | (state[D] & ~in);
assign next_state[D] = state[C] & in;
// Output logic:
assign out = (state[D]);
endmodule
| 7.203305
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = (~opcode);
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = '0;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = '1;
endmodule
| 6.868788
|
module top_module (
input in,
input [3:0] state,
output [3:0] next_state,
output out
); //
parameter A = 0, B = 1, C = 2, D = 3;
// State transition logic: Derive an equation for each state flip-flop.
assign next_state[A] = state[A] & (~in) | state[C] & (~in);
assign next_state[B] = state[A] & in | state[B] & in | state[D] & in;
assign next_state[C] = state[B] & (~in) | state[D] & (~in);
assign next_state[D] = state[C] & in;
// Output logic:
assign out = state[D] ? 1'b1 : 1'b0;
endmodule
| 7.203305
|
module klei22_ra #(
parameter RA_SIZE = 8,
parameter BITS_PER_ELEM = 5
) (
input [7:0] io_in,
output [7:0] io_out
);
wire clk = io_in[0];
wire rst = io_in[1];
wire i_data_clk = io_in[2];
wire start_calc;
wire [4:0] i_value = io_in[7:3];
wire [BITS_PER_ELEM - 1:0] ra_out;
assign io_out[BITS_PER_ELEM-1:0] = {3'b000, ra_out[4:0]};
parameter SRL_SIZE = RA_SIZE + 1; // RA_SIZE valid inputs and one stale input
parameter TOTAL_SRL_BITS = 5 * SRL_SIZE;
wire [TOTAL_SRL_BITS - 1:0] taps;
shift_register_line #(
.TOTAL_TAPS(SRL_SIZE),
.BITS_PER_ELEM(BITS_PER_ELEM),
.TOTAL_BITS(TOTAL_SRL_BITS)
) srl_1 (
.clk(clk),
.rst(rst),
.i_value(i_value[4:0]),
.i_data_clk(i_data_clk),
.o_start_calc(start_calc),
.o_taps(taps[TOTAL_SRL_BITS-1:0])
);
// rolling sums RA_SIZE elements + 1 stale element
parameter RA_NUM_ELEM = RA_SIZE;
parameter MAX_BITS = 8; // log_2(31 * 8) = 7.9 ~ 8; where 31 is largest valut for 5 bit elem
rolling_average #(
.BITS_PER_ELEM(BITS_PER_ELEM),
.MAX_BITS(8)
) ra_1 (
.clk(clk),
.rst(rst),
.i_new(taps[4:0]),
.i_old(taps[(4+5*9):(0+5*8)]),
.i_start_calc(start_calc),
.o_ra(ra_out[BITS_PER_ELEM-1:0])
);
endmodule
| 7.23466
|
module top_module (
input in,
input [3:0] state,
output [3:0] next_state,
output out
); //
parameter A = 0, B = 1, C = 2, D = 3;
// State transition logic: Derive an equation for each state flip-flop.
assign next_state[A] = (~in & state[A]) | (~in & state[C]);
assign next_state[B] = (in & state[A]) | (in & state[B]) | (in & state[D]);
assign next_state[C] = (~in & state[B]) | (~in & state[D]);
assign next_state[D] = (in & state[C]);
// Output logic:
assign out = (state[D]);
endmodule
| 7.203305
|
module top_module (
input clk,
input in,
input areset,
output out
); //
reg [2:0] state, next_state;
parameter A = 1, B = 2, C = 3, D = 4;
// State transition logic
always @(*) begin
case (state)
A: next_state = (in == 1) ? B : A;
B: next_state = (in == 1) ? B : C;
C: next_state = (in == 1) ? D : A;
D: next_state = (in == 1) ? B : C;
endcase
end
// State flip-flops with asynchronous reset
always @(posedge clk or posedge areset) begin
if (areset) state <= A;
else state <= next_state;
end
// Output logic
assign out = (state == D);
endmodule
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|
module top_module (
input clk,
input in,
input areset,
output reg out
); //
// parameter
parameter A = 2'b00;
parameter B = 2'b01;
parameter C = 2'b10;
parameter D = 2'b11;
// signal declaration
reg [1:0] state;
reg [1:0] next_state;
// state flip-flops with asynchronous reset
always @(posedge clk or posedge areset) begin
if (areset) state <= A;
else state <= next_state;
end
// State transition logic: next_state = f(state, in)
always @(*) begin
case (state)
A:
if (in) next_state = B;
else next_state = A;
B:
if (in) next_state = B;
else next_state = C;
C:
if (in) next_state = D;
else next_state = A;
D:
if (in) next_state = B;
else next_state = C;
default: next_state = 2'bx;
endcase
end
// Output logic: out = f(state) for a Moore state machine
always @(*) begin
case (state)
A: out = 1'b0;
B: out = 1'b0;
C: out = 1'b0;
D: out = 1'b1;
default: out = 1'bx;
endcase
end
endmodule
| 7.203305
|
module top_module (
input clk,
input in,
input areset,
output out
); //
parameter A = 0, B = 1, C = 2, D = 3;
wire [1:0] next_state;
reg [1:0] state;
// State transition logic
always @(*) begin
case (state)
A: next_state = in ? B : A;
B: next_state = in ? B : C;
C: next_state = in ? D : A;
D: next_state = in ? B : C;
endcase
end
// State flip-flops with asynchronous reset
always @(posedge clk, posedge areset) begin
if (areset) state <= A;
else state <= next_state;
end
// Output logic
assign out = (state == D);
endmodule
| 7.203305
|
module afoote_w5s8_tt02_utm_core (
input clock,
input reset,
input mode,
input [2:0] encoded_state_in,
input [2:0] sym_in,
input sym_in_valid,
output [2:0] new_sym,
output direction,
output [2:0] encoded_next_state
);
reg [7:0] stored_state;
reg [2:0] symbuf;
reg symbuf_valid;
wire [7:0] state_in;
wire [7:0] state;
wire [7:0] next_state;
wire [2:0] sym;
always @(posedge clock) begin
if (reset) begin
stored_state <= 8'h01;
end else if (sym_in_valid && symbuf_valid) begin
stored_state <= next_state;
end else begin
stored_state <= stored_state;
end
end
always @(posedge clock) begin
if (reset) begin
symbuf <= 3'b0;
end else if (sym_in_valid) begin
symbuf <= sym_in;
end else begin
symbuf <= symbuf;
end
end
always @(posedge clock) begin
if (reset) begin
symbuf_valid <= 0;
end else if (sym_in_valid) begin
symbuf_valid <= 1;
end else begin
symbuf_valid <= symbuf_valid;
end
end
afoote_w5s8_tt02_decoder_3to8 decode_state_in (
.in (encoded_state_in),
.out(state_in)
);
assign state = (mode == 0) ? state_in : stored_state;
assign sym = (mode == 0) ? sym_in : symbuf;
afoote_w5s8_tt02_direction direction_block (
.state(state),
.s2(sym[2]),
.s1(sym[1]),
.s0(sym[0]),
.direction(direction)
);
afoote_w5s8_tt02_next_state next_state_block (
.state_in(state),
.s2(sym[2]),
.s1(sym[1]),
.s0(sym[0]),
.state_out(next_state)
);
afoote_w5s8_tt02_new_symbol new_sym_block (
.state_in(state),
.s2(sym[2]),
.s1(sym[1]),
.s0(sym[0]),
.z2(new_sym[2]),
.z1(new_sym[1]),
.z0(new_sym[0])
);
afoote_w5s8_tt02_encoder_8to3 encode_state_out (
.in (next_state),
.out(encoded_next_state)
);
endmodule
| 7.830463
|
module afoote_w5s8_tt02_direction (
input [7:0] state,
input s2,
input s1,
input s0,
// 0 = left, 1 = right
output direction
);
wire a, b, c, d, e, f, g, h;
assign a = state[0];
assign b = state[1];
assign c = state[2];
assign d = state[3];
assign e = state[4];
assign f = state[5];
assign g = state[6];
assign h = state[7];
assign direction = ((a | e | f) & s1)
| (((a & s0) | b | c | (e & s0) | f | g | h) & s2)
| ((d | (e & (~s1) & (~s0))) & (~s2))
| (g & (~s1));
endmodule
| 7.830463
|
module afoote_w5s8_tt02_next_state (
input [7:0] state_in,
input s2,
input s1,
input s0,
output [7:0] state_out
);
wire a, b, c, d, e, f, g, h;
assign a = state_in[0];
assign b = state_in[1];
assign c = state_in[2];
assign d = state_in[3];
assign e = state_in[4];
assign f = state_in[5];
assign g = state_in[6];
assign h = state_in[7];
wire sym_0;
assign sym_0 = (~s2) & (~s1) & (~s0);
// next H
assign state_out[7] = s2 & ((s0 & (b | c)) | h);
// next G
assign state_out[6] = (s2 & (((b | c) & (~s0)) | g)) | (f & s1);
// next F
assign state_out[5] = (e & (~s2) & s0) | (f & (~(s2 | s1))) | (s1 & (g | h));
// next E
assign state_out[4] = (a & s2 & (~s0)) | (d & (~s2) & s0) | (e & (s1 | (s2 & s0)));
// next D
assign state_out[3] = (b & s1) | (d & s2) | (e & (~s1) & (~s0));
// next C
assign state_out[2] = (a & (~s2) & s0) | (c & (~(s2 | s1))) | (d & sym_0);
// next B
assign state_out[1] = (a & sym_0) | (b & (~(s2 | s1))) | (c & s1) | (f & s2);
// next A
assign state_out[0] = (a & (s1 | (s2 & s0))) | (d & s1) | ((g | h) & (~(s2 | s1)));
endmodule
| 7.830463
|
module afoote_w5s8_tt02_new_symbol (
input [7:0] state_in,
input s2,
input s1,
input s0,
output z2,
output z1,
output z0
);
wire a, b, c, d, e, f, g, h;
assign a = state_in[0];
assign b = state_in[1];
assign c = state_in[2];
assign d = state_in[3];
assign e = state_in[4];
assign f = state_in[5];
assign g = state_in[6];
assign h = state_in[7];
assign z2 = ((~s2) & b) | (d & s0) | c | (e & (s0 | s1)) | (f & (~(s2 | s1)));
assign z1 = (a & (~s2)) | (d & (s2 | s1) & (~s0)) | (e & s2 & (~s0));
assign z0 = (s0 & ((a & s2) | (~a))) | (h & s1);
endmodule
| 7.830463
|
module afoote_w5s8_tt02_decoder_3to8 (
input [2:0] in,
output [7:0] out
);
assign out[0] = (~in[2]) & (~in[1]) & (~in[0]);
assign out[1] = (~in[2]) & (~in[1]) & (in[0]);
assign out[2] = (~in[2]) & (in[1]) & (~in[0]);
assign out[3] = (~in[2]) & (in[1]) & (in[0]);
assign out[4] = (in[2]) & (~in[1]) & (~in[0]);
assign out[5] = (in[2]) & (~in[1]) & (in[0]);
assign out[6] = (in[2]) & (in[1]) & (~in[0]);
assign out[7] = (in[2]) & (in[1]) & (in[0]);
endmodule
| 7.830463
|
module afoote_w5s8_tt02_encoder_8to3 (
input [7:0] in,
output [2:0] out
);
assign out[0] = in[1] | in[3] | in[5] | in[7];
assign out[1] = in[2] | in[3] | in[6] | in[7];
assign out[2] = in[4] | in[5] | in[6] | in[7];
endmodule
| 7.830463
|
module afoote_w5s8_tt02_top (
input [7:0] io_in,
output [7:0] io_out
);
wire mode;
wire clock;
wire reset;
wire direction;
wire sym_valid;
wire [2:0] sym_in;
wire [2:0] new_sym;
// 1-hot state in & out
wire [7:0] state_in;
wire [7:0] state_out;
// 3-bit dense encoding of state in & out
wire [2:0] encoded_state_in;
wire [2:0] encoded_state_out;
assign mode = io_in[7];
assign clock = io_in[0];
assign reset = (mode == 0) ? 1'b1 : io_in[1];
assign encoded_state_in = (mode == 0) ? io_in[3:1] : 3'b0;
assign io_out[7:5] = encoded_state_out;
assign sym_valid = (mode == 0) ? 1'b0 : io_in[2];
assign sym_in = io_in[6:4];
assign io_out[4:2] = new_sym;
assign io_out[1] = direction;
assign io_out[0] = 1'b0;
afoote_w5s8_tt02_utm_core core (
.clock(clock),
.reset(reset),
.mode(mode),
.encoded_state_in(encoded_state_in),
.sym_in(sym_in),
.sym_in_valid(sym_valid),
.new_sym(new_sym),
.direction(direction),
.encoded_next_state(encoded_state_out)
);
endmodule
| 7.830463
|
module top_module (
input clk,
input in,
input reset,
output out
); //
reg [2:0] state, next_state;
parameter A = 1, B = 2, C = 3, D = 4;
// State transition logic
always @(*) begin
case (state)
A: next_state = (in == 1) ? B : A;
B: next_state = (in == 1) ? B : C;
C: next_state = (in == 1) ? D : A;
D: next_state = (in == 1) ? B : C;
endcase
end
// State flip-flops with asynchronous reset
always @(posedge clk) begin
if (reset) state <= A;
else state <= next_state;
end
// Output logic
assign out = (state == D);
endmodule
| 7.203305
|
module top_module (
input clk,
input in,
input reset,
output reg out
); //
// parameter
parameter A = 2'b00;
parameter B = 2'b01;
parameter C = 2'b10;
parameter D = 2'b11;
// signal declaration
reg [1:0] state;
reg [1:0] next_state;
// state flip-flops with asynchronous reset
always @(posedge clk) begin
if (reset) state <= A;
else state <= next_state;
end
// State transition logic: next_state = f(state, in)
always @(*) begin
case (state)
A:
if (in) next_state = B;
else next_state = A;
B:
if (in) next_state = B;
else next_state = C;
C:
if (in) next_state = D;
else next_state = A;
D:
if (in) next_state = B;
else next_state = C;
default: next_state = 2'bx;
endcase
end
// Output logic: out = f(state) for a Moore state machine
always @(*) begin
case (state)
A: out = 1'b0;
B: out = 1'b0;
C: out = 1'b0;
D: out = 1'b1;
default: out = 1'bx;
endcase
end
endmodule
| 7.203305
|
module top_module (
input clk,
input in,
input reset,
output out
); //
parameter A = 0, B = 1, C = 2, D = 3;
reg [1:0] state;
reg [1:0] next_state;
// State transition logic
always @(*) begin
case (state)
A: next_state = in ? B : A;
B: next_state = in ? B : C;
C: next_state = in ? D : A;
D: next_state = in ? B : C;
endcase
end
// State flip-flops with synchronous reset
always @(posedge clk) begin
if (reset) state <= A;
else state <= next_state;
end
// Output logic
assign out = (state == D);
endmodule
| 7.203305
|
module top_module (
input clk,
input reset,
input [3:1] s,
output fr3,
output fr2,
output fr1,
output dfr
);
localparam [2:0] A = 3'd0, //water level:below s1
B0 = 3'd1, //s1~s2, and previous level is higher
B1 = 3'd2, //s1~s2, and previous level is lower
C0 = 3'd3, //s2~s3, and previous level is higher
C1 = 3'd4, //s2~s3, and previous level is lower
D = 3'd5; //above s3
reg [2:0] state, next_state;
always @(posedge clk) begin
if (reset) state <= A;
else state <= next_state;
end
always @(*) begin
case (state)
A: next_state = (s[1]) ? B1 : A;
B0: next_state = (s[2]) ? C1 : ((s[1]) ? B0 : A);
B1: next_state = (s[2]) ? C1 : ((s[1]) ? B1 : A);
C0: next_state = (s[3]) ? D : ((s[2]) ? C0 : B0);
C1: next_state = (s[3]) ? D : ((s[2]) ? C1 : B0);
D: next_state = (s[3]) ? D : C0;
default: next_state = 3'bxxx;
endcase
end
always @(*) begin
case (state)
A: {fr3, fr2, fr1, dfr} = 4'b1111;
B0: {fr3, fr2, fr1, dfr} = 4'b0111;
B1: {fr3, fr2, fr1, dfr} = 4'b0110;
C0: {fr3, fr2, fr1, dfr} = 4'b0011;
C1: {fr3, fr2, fr1, dfr} = 4'b0010;
D: {fr3, fr2, fr1, dfr} = 4'b0000;
default: {fr3, fr2, fr1, dfr} = 4'bxxxx;
endcase
end
endmodule
| 7.203305
|
module top_module (
input clk,
input reset,
input [3:1] s,
output fr3,
output fr2,
output fr1,
output dfr
);
parameter ON = 1, OFF = 0;
reg [3:1] shift;
always @(posedge clk) begin
if (reset) begin
fr1 <= ON;
fr2 <= ON;
fr3 <= ON;
end else if (s == 3'b000) begin
fr1 <= ON;
fr2 <= ON;
fr3 <= ON;
end else if (s == 3'b001) begin
fr1 <= ON;
fr2 <= ON;
fr3 <= OFF;
end else if (s == 3'b011) begin
fr1 <= ON;
fr2 <= OFF;
fr3 <= OFF;
end else if (s == 3'b111) begin
fr1 <= OFF;
fr2 <= OFF;
fr3 <= OFF;
end
end
always @(posedge clk) begin
if (reset) shift <= OFF;
else shift <= s;
end
always @(posedge clk) begin
if (reset) dfr <= ON;
else if (s > shift) dfr <= OFF;
else if (s < shift) dfr <= ON;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input reset,
input [3:1] s,
output reg fr3,
output reg fr2,
output reg fr1,
output reg dfr
);
// parameter
parameter Below_S1 = 3'b000;
parameter S1_S2_nominal = 3'b001;
parameter S1_S2_supplemental = 3'b010;
parameter S2_S3_nominal = 3'b011;
parameter S2_S3_supplemental = 3'b100;
parameter Above_S3 = 3'b101;
// signal declaration
reg [2:0] present_state;
reg [2:0] next_state;
// sequential logic reset
always @(posedge clk) begin
if (reset) present_state <= Below_S1;
else present_state <= next_state;
end
// combinational logic state transiton
always @(*) begin
case (present_state)
Below_S1:
if (s[1]) next_state = S1_S2_nominal;
else next_state = Below_S1;
S1_S2_nominal:
if (s[2]) next_state = S2_S3_nominal;
else if (s[1]) next_state = S1_S2_nominal;
else next_state = Below_S1;
S1_S2_supplemental:
if (s[2]) next_state = S2_S3_nominal;
else if (s[1]) next_state = S1_S2_supplemental;
else next_state = Below_S1;
S2_S3_nominal:
if (s[3]) next_state = Above_S3;
else if (s[2]) next_state = S2_S3_nominal;
else next_state = S1_S2_supplemental;
S2_S3_supplemental:
if (s[3]) next_state = Above_S3;
else if (s[2]) next_state = S2_S3_supplemental;
else next_state = S1_S2_supplemental;
Above_S3:
if (s[3]) next_state = Above_S3;
else next_state = S2_S3_supplemental;
default: next_state = 3'bxxx;
endcase
end
// Combinational logic output
always @(*) begin
case (present_state)
Below_S1: {fr3, fr2, fr1, dfr} = 4'b1111;
S1_S2_nominal: {fr3, fr2, fr1, dfr} = 4'b0110;
S1_S2_supplemental: {fr3, fr2, fr1, dfr} = 4'b0111;
S2_S3_nominal: {fr3, fr2, fr1, dfr} = 4'b0010;
S2_S3_supplemental: {fr3, fr2, fr1, dfr} = 4'b0011;
Above_S3: {fr3, fr2, fr1, dfr} = 4'b0000;
endcase
end
endmodule
| 7.203305
|
module gregdavill_clock_top (
input [7:0] io_in,
output [7:0] io_out
);
clock clock_top (
.i_clk(io_in[0]),
.i_rst(io_in[1]),
.i_min_up(io_in[2]),
.i_hour_up(io_in[3]),
.o_clk(io_out[0]),
.o_latch(io_out[1]),
.o_bit(io_out[2])
);
endmodule
| 7.264297
|
module top_module (
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
output walk_left,
output walk_right
); //
parameter LEFT = 0, RIGHT = 1;
reg state, next_state;
always @(*) begin
// State transition logic
case (state)
LEFT: next_state = (bump_left) ? RIGHT : LEFT;
RIGHT: next_state = (bump_right) ? LEFT : RIGHT;
endcase
end
always @(posedge clk, posedge areset) begin
// State flip-flops with asynchronous reset
if (areset) state <= LEFT;
else begin
state <= next_state;
end
end
// Output logic
assign walk_left = (state == LEFT);
assign walk_right = (state == RIGHT);
endmodule
| 7.203305
|
module top_module (
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
output walk_left,
output walk_right
); //
parameter LEFT = 0, RIGHT = 1;
reg state, next_state;
always @(*) begin
// State transition logic
case (state)
LEFT: next_state = (bump_left) ? RIGHT : LEFT;
RIGHT: next_state = (bump_right) ? LEFT : RIGHT;
endcase
end
always @(posedge clk, posedge areset) begin
// State flip-flops with asynchronous reset
if (areset) state <= LEFT;
else state <= next_state;
end
// Output logic
assign walk_left = (state == LEFT);
assign walk_right = (state == RIGHT);
endmodule
| 7.203305
|
module top_module (
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
output walk_left,
output walk_right
); //
parameter LEFT = 0;
parameter RIGHT = 1;
reg state, next_state;
always @(*) begin
// State transition logic
case (state)
LEFT:
if (bump_left) next_state = RIGHT;
else next_state = LEFT;
RIGHT:
if (bump_right) next_state = LEFT;
else next_state = RIGHT;
default: next_state = 1'bx;
endcase
end
always @(posedge clk, posedge areset) begin
// State flip-flops with asynchronous reset
if (areset) state <= LEFT;
else state <= next_state;
end
// Output logic
assign walk_left = (state == LEFT) ? 1 : 0;
assign walk_right = (state == RIGHT) ? 1 : 0;
endmodule
| 7.203305
|
module top_module (
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
output walk_left,
output walk_right,
output aaah
);
localparam [1:0] WALK_L = 2'b00, WALK_R = 2'b01, FALL_L = 2'b10, FALL_R = 2'b11;
reg [1:0] state, next;
always @(posedge clk or posedge areset) begin
if (areset) state <= WALK_L;
else begin
state <= next;
end
end
always @(*) begin
case (state)
WALK_L: next = (ground == 0) ? FALL_L : ((bump_left == 1) ? WALK_R : WALK_L);
WALK_R: next = (ground == 0) ? FALL_R : ((bump_right == 1) ? WALK_L : WALK_R);
FALL_L: next = (ground == 1) ? WALK_L : FALL_L;
FALL_R: next = (ground == 1) ? WALK_R : FALL_R;
endcase
end
assign walk_left = (state == WALK_L);
assign walk_right = (state == WALK_R);
assign aaah = ((state == FALL_L) || (state == FALL_R));
endmodule
| 7.203305
|
module top_module (
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
output walk_left,
output walk_right,
output aaah
);
parameter LEFT = 0;
parameter RIGHT = 1;
parameter GROUND_LEFT = 2;
parameter GROUND_RIGHT = 3;
reg [1:0] state;
reg [1:0] next_state;
always @(*) begin
// State transition logic
case (state)
LEFT:
if (ground)
if (bump_left) next_state = RIGHT;
else next_state = LEFT;
else next_state = GROUND_LEFT;
RIGHT:
if (ground)
if (bump_right) next_state = LEFT;
else next_state = RIGHT;
else next_state = GROUND_RIGHT;
GROUND_LEFT:
if (ground) next_state = LEFT;
else next_state = GROUND_LEFT;
GROUND_RIGHT:
if (ground) next_state = RIGHT;
else next_state = GROUND_RIGHT;
default: next_state = 1'bx;
endcase
end
always @(posedge clk, posedge areset) begin
// State flip-flops with asynchronous reset
if (areset) state <= LEFT;
else state <= next_state;
end
// Output logic
assign walk_left = (state == LEFT) ? 1 : 0;
assign walk_right = (state == RIGHT) ? 1 : 0;
assign aaah = (state == GROUND_LEFT || state == GROUND_RIGHT) ? 1 : 0;
endmodule
| 7.203305
|
module top_module (
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
output walk_left,
output walk_right,
output aaah
);
parameter LEFT = 0, RIGHT = 1, FALL_L = 2, FALL_R = 3;
reg [1:0] state, next_state;
always @(*) begin
if (ground)
case (state)
LEFT: next_state = (bump_left) ? RIGHT : LEFT;
RIGHT: next_state = (bump_right) ? LEFT : RIGHT;
FALL_L: next_state = LEFT;
FALL_R: next_state = RIGHT;
endcase
end
always @(posedge clk, posedge areset) begin
if (areset) state <= LEFT;
else if (~ground)
if (state == LEFT | state == FALL_L) state <= FALL_L;
else state <= FALL_R;
else state <= next_state;
end
always @(posedge clk, posedge areset) begin
if (areset) aaah <= 0;
else if (~ground) aaah <= 1;
else aaah <= 0;
end
assign walk_left = (state == LEFT);
assign walk_right = (state == RIGHT);
endmodule
| 7.203305
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always begin
end
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module d_latch (
E,
D,
Q
);
input E;
input D;
output reg Q;
always @(E, D) begin
if (E) begin
Q = D;
end
end
endmodule
| 6.881555
|
module rsd_ff (
CLK,
R,
S,
D,
Q
);
input CLK;
input R;
input S;
input D;
output reg Q;
always @(posedge CLK or posedge R or posedge S) begin
if (R) begin
Q = 1'b0;
end else if (S) begin
Q = 1'b1;
end else begin
Q = D;
end
end
endmodule
| 6.613231
|
module register_8bits (
CLK,
D,
Q
);
input CLK;
input [7:0] D;
output reg [7:0] Q;
always @(posedge CLK) begin
Q = D;
end
endmodule
| 6.578073
|
module top_module (
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
input dig,
output walk_left,
output walk_right,
output aaah,
output digging
);
parameter LEFT = 0, RIGHT = 1, DOWN_L = 2, DOWN_R = 3, DIG_L = 4, DIG_R = 5;
reg [2:0] cstate, nstate;
always @(posedge clk or posedge areset) begin
if (areset) begin
cstate <= LEFT;
end else begin
cstate <= nstate;
end
end
always @(*) begin
case (cstate)
LEFT: nstate = ground ? (dig ? DIG_L : (bump_left ? RIGHT : LEFT)) : DOWN_L;
RIGHT: nstate = ground ? (dig ? DIG_R : (bump_right ? LEFT : RIGHT)) : DOWN_R;
DOWN_L: nstate = ground ? LEFT : DOWN_L;
DOWN_R: nstate = ground ? RIGHT : DOWN_R;
DIG_L: nstate = ground ? DIG_L : DOWN_L;
DIG_R: nstate = ground ? DIG_R : DOWN_R;
endcase
end
assign walk_left = (cstate == LEFT);
assign walk_right = (cstate == RIGHT);
assign aaah = (cstate == DOWN_L || cstate == DOWN_R);
assign digging = (cstate == DIG_L || cstate == DIG_R);
endmodule
| 7.203305
|
module test;
reg [3:0] inp;
wire [6:0] outp;
segment s (
inp,
outp
);
initial begin
$dumpfile("dump.vcd");
$dumpvars(0, test);
$display("hex \t 7segcode");
$monitor("%h \t %b", inp, outp);
#10 inp = 4'b0000;
#10 inp = 4'b0001;
#10 inp = 4'b0010;
#10 inp = 4'b0011;
#10 inp = 4'b0100;
#10 inp = 4'b0101;
#10 inp = 4'b0110;
#10 inp = 4'b0111;
$finish;
end
endmodule
| 6.635152
|
module top_module (
input ring,
input vibrate_mode,
output ringer, // Make sound
output motor // Vibrate
);
assign motor = vibrate_mode && ring;
assign ringer = (~vibrate_mode) && ring;
endmodule
| 7.203305
|
module top_module (
input clk,
input x,
output z
);
reg q0, q1, q2;
always @(posedge clk) begin
q0 <= x ^ q0;
q1 <= x & ~q1;
q2 <= x | ~q2;
end
assign z = ~(q0 | q1 | q2);
endmodule
| 7.203305
|
module top_module (
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
input dig,
output walk_left,
output walk_right,
output aaah,
output digging
);
parameter [2:0] left = 3'd0, right = 3'd1, fall_l = 3'd2, fall_r = 3'd3, dig_l = 3'd4, dig_r = 3'd5, splat = 3'd6;
reg [2:0] state, nextstate;
reg [7:0] count; // set a larger number otherwise it will overflow
always @(*) begin
case (state)
left: nextstate = (~ground) ? fall_l : ((dig) ? dig_l : ((bump_left) ? right : left));
right: nextstate = (~ground) ? fall_r : ((dig) ? dig_r : ((bump_right) ? left : right));
fall_l: nextstate = (~ground) ? fall_l : ((count > 19) ? splat : left);
fall_r: nextstate = (~ground) ? fall_r : ((count > 19) ? splat : right);
dig_l: nextstate = (~ground) ? fall_l : dig_l;
dig_r: nextstate = (~ground) ? fall_r : dig_r;
splat: nextstate = splat;
default: nextstate = 3'bxxx;
endcase
end
always @(posedge clk, posedge areset) begin
if (areset) state <= left;
else begin
if (state == fall_l | state == fall_r) begin
count <= count + 1;
state <= nextstate;
end else begin
state <= nextstate;
count <= 0;
end
end
end
assign walk_left = (state == left);
assign walk_right = (state == right);
assign aaah = (state == fall_l | state == fall_r);
assign digging = (state == dig_l | state == dig_r);
endmodule
| 7.203305
|
module top_module (
input ring,
input vibrate_mode,
output ringer, // Make sound
output motor // Vibrate
);
assign ringer = ring & ~vibrate_mode;
assign motor = ring & vibrate_mode;
endmodule
| 7.203305
|
module mips_regfile (
read_reg1_addr,
read_reg2_addr,
write_reg_addr,
data_in,
write_read_ena,
clk,
read_reg1_data,
read_reg2_data
);
reg [31:0] regs[31:0];
input [4:0] read_reg1_addr;
input [4:0] read_reg2_addr;
input [4:0] write_reg_addr;
input clk, write_read_ena;
input [31:0] data_in;
output reg [31:0] read_reg1_data;
output reg [31:0] read_reg2_data;
always @(negedge clk) begin
if (!read_reg1_addr) read_reg1_data[31:0] = 0;
else read_reg1_data[31:0] = regs[read_reg1_addr];
if (!read_reg2_addr) read_reg2_data[31:0] = 0;
else read_reg2_data[31:0] = regs[read_reg2_addr];
if (write_read_ena) begin
regs[write_reg_addr] = data_in[31:0];
end
end
endmodule
| 7.361273
|
module top_module (
input [31:0] in,
output [31:0] out
); //
assign out[31:24] = in[7:0];
assign out[23:16] = in[15:8];
assign out[15:8] = in[23:16];
assign out[7:0] = in[31:24];
endmodule
| 7.203305
|
module top_module (
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
input dig,
output walk_left,
output walk_right,
output aaah,
output digging
);
localparam [2:0] WALK_L = 3'b000,
WALK_R = 3'b001,
FALL_L = 3'b010,
FALL_R = 3'b011,
DIG_L = 3'b100,
DIG_R = 3'b101;
reg [2:0] state, next;
always @(posedge clk or posedge areset) begin
if (areset) state <= WALK_L;
else state <= next;
end
always @(*) begin
case (state)
WALK_L: begin
if (!ground) next = FALL_L;
else begin
if (dig) next = DIG_L;
else begin
if (bump_left) next = WALK_R;
else next = WALK_L;
end
end
end
WALK_R: begin
if (!ground) next = FALL_R;
else begin
if (dig) next = DIG_R;
else begin
if (bump_right) next = WALK_L;
else next = WALK_R;
end
end
end
FALL_L: next = (ground) ? WALK_L : FALL_L;
FALL_R: next = (ground) ? WALK_R : FALL_R;
DIG_L: next = (ground) ? DIG_L : FALL_L;
DIG_R: next = (ground) ? DIG_R : FALL_R;
endcase
end
assign walk_left = (state == WALK_L);
assign walk_right = (state == WALK_R);
assign aaah = ((state == FALL_L) || (state == FALL_R));
assign digging = ((state == DIG_L) || (state == DIG_R));
endmodule
| 7.203305
|
module top_module (
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
input dig,
output walk_left,
output walk_right,
output aaah,
output digging
);
parameter LEFT = 0;
parameter RIGHT = 1;
parameter DIG_LEFT = 2;
parameter DIG_RIGHT = 3;
parameter GROUND_LEFT = 4;
parameter GROUND_RIGHT = 5;
reg [2:0] state;
reg [2:0] next_state;
always @(*) begin
// State transition logic
case (state)
LEFT:
if (ground)
if (dig) next_state = DIG_LEFT;
else if (bump_left) next_state = RIGHT;
else next_state = LEFT;
else next_state = GROUND_LEFT;
RIGHT:
if (ground)
if (dig) next_state = DIG_RIGHT;
else if (bump_right) next_state = LEFT;
else next_state = RIGHT;
else next_state = GROUND_RIGHT;
DIG_LEFT:
if (ground) next_state = DIG_LEFT;
else next_state = GROUND_LEFT;
DIG_RIGHT:
if (ground) next_state = DIG_RIGHT;
else next_state = GROUND_RIGHT;
GROUND_LEFT:
if (ground) next_state = LEFT;
else next_state = GROUND_LEFT;
GROUND_RIGHT:
if (ground) next_state = RIGHT;
else next_state = GROUND_RIGHT;
default: next_state = 1'bx;
endcase
end
always @(posedge clk, posedge areset) begin
// State flip-flops with asynchronous reset
if (areset) state <= LEFT;
else state <= next_state;
end
// Output logic
assign walk_left = (state == LEFT) ? 1 : 0;
assign walk_right = (state == RIGHT) ? 1 : 0;
assign aaah = (state == GROUND_LEFT || state == GROUND_RIGHT) ? 1 : 0;
assign digging = (state == DIG_LEFT || state == DIG_RIGHT) ? 1 : 0;
endmodule
| 7.203305
|
module top_module (
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
input dig,
output walk_left,
output walk_right,
output aaah,
output digging
);
parameter LEFT = 1'd0, RIGHT = 1'd1;
parameter WALK = 2'd0, FALL = 2'd1, DIG = 2'd2;
reg direction, next_dir;
reg [1:0] state, next_state;
always @(*) begin
if ((state == WALK) & (next_state == WALK))
case (direction)
LEFT: next_dir = (bump_left) ? RIGHT : LEFT;
RIGHT: next_dir = (bump_right) ? LEFT : RIGHT;
endcase
else next_dir = direction;
end
always @(*) begin
if (~ground) next_state = FALL;
else if ((state != FALL) & (dig | (state == DIG))) next_state = DIG;
else next_state = WALK;
end
always @(posedge clk, posedge areset) begin
if (areset) direction <= LEFT;
else direction <= next_dir;
end
always @(posedge clk, posedge areset) begin
if (areset) state <= WALK;
else state <= next_state;
end
assign walk_left = (direction == LEFT) & (state == WALK);
assign walk_right = (direction == RIGHT) & (state == WALK);
assign aaah = (state == FALL);
assign digging = (state == DIG);
endmodule
| 7.203305
|
module top_module (
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
input dig,
output walk_left,
output walk_right,
output aaah,
output digging
);
localparam [2:0] WALK_L = 3'b000,
WALK_R = 3'b001,
FALL_L = 3'b010,
FALL_R = 3'b011,
DIG_L = 3'b100,
DIG_R = 3'b101,
SPLATTER = 3'b110;
reg [2:0] state, next;
reg [6:0] count;
always @(posedge clk or posedge areset) begin
if (areset) state <= WALK_L;
else if (state == FALL_R || state == FALL_L) begin
count <= count + 1;
state <= next;
end else begin
state <= next;
count <= 0;
end
end
always @(*) begin
case (state)
WALK_L: begin
if (!ground) next = FALL_L;
else begin
if (dig) next = DIG_L;
else begin
if (bump_left) next = WALK_R;
else next = WALK_L;
end
end
end
WALK_R: begin
if (!ground) next = FALL_R;
else begin
if (dig) next = DIG_R;
else begin
if (bump_right) next = WALK_L;
else next = WALK_R;
end
end
end
FALL_L: begin
if (ground) begin
if (count > 19) next = SPLATTER;
else next = WALK_L;
end else next = FALL_L;
end
FALL_R: begin
if (ground) begin
if (count > 19) next = SPLATTER;
else next = WALK_R;
end else next = FALL_R;
end
DIG_L: next = (ground) ? DIG_L : FALL_L;
DIG_R: next = (ground) ? DIG_R : FALL_R;
SPLATTER: next = SPLATTER;
endcase
end
assign walk_left = (state == WALK_L);
assign walk_right = (state == WALK_R);
assign aaah = ((state == FALL_L) || (state == FALL_R));
assign digging = ((state == DIG_L) || (state == DIG_R));
endmodule
| 7.203305
|
module top_module (
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
input dig,
output walk_left,
output walk_right,
output aaah,
output digging
);
parameter LEFT = 0;
parameter RIGHT = 1;
parameter DIG_LEFT = 2;
parameter DIG_RIGHT = 3;
parameter GROUND_LEFT = 4;
parameter GROUND_RIGHT = 5;
parameter SPLAT = 6;
reg [2:0] state;
reg [2:0] next_state;
integer i_left = 0;
integer i_right = 0;
always @(*) begin
// State transition logic
case (state)
LEFT:
if (ground)
if (dig) next_state = DIG_LEFT;
else if (bump_left) next_state = RIGHT;
else next_state = LEFT;
else next_state = GROUND_LEFT;
RIGHT:
if (ground)
if (dig) next_state = DIG_RIGHT;
else if (bump_right) next_state = LEFT;
else next_state = RIGHT;
else next_state = GROUND_RIGHT;
DIG_LEFT:
if (ground) next_state = DIG_LEFT;
else next_state = GROUND_LEFT;
DIG_RIGHT:
if (ground) next_state = DIG_RIGHT;
else next_state = GROUND_RIGHT;
GROUND_LEFT:
if (ground)
if (i_left < 20) next_state = LEFT;
else next_state = SPLAT;
else next_state = GROUND_LEFT;
GROUND_RIGHT:
if (ground)
if (i_right < 20) next_state = RIGHT;
else next_state = SPLAT;
else next_state = GROUND_RIGHT;
SPLAT: next_state = SPLAT;
default: next_state = 1'bx;
endcase
end
always @(posedge clk, posedge areset) begin
// State flip-flops with asynchronous reset
if (areset) begin
state <= LEFT;
i_left <= 0;
i_right <= 0;
end else begin
state <= next_state;
if (state == GROUND_LEFT) i_left <= i_left + 1;
else if (state == GROUND_RIGHT) i_right <= i_right + 1;
else begin
i_left <= 0;
i_right <= 0;
end
end
end
// Output logic
assign walk_left = (state == LEFT) ? 1'b1 : 1'b0;
assign walk_right = (state == RIGHT) ? 1'b1 : 1'b0;
assign aaah = ((state == GROUND_LEFT) || (state == GROUND_RIGHT)) ? 1'b1 : 1'b0;
assign digging = ((state == DIG_LEFT) || (state == DIG_RIGHT)) ? 1'b1 : 1'b0;
endmodule
| 7.203305
|
module top_module (
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
input dig,
output walk_left,
output walk_right,
output aaah,
output digging
);
parameter WALK = 2'b00, FALL = 2'b01, DIG = 2'b10, SPLAT = 2'b11;
parameter LEFT = 1'b0, RIGHT = 1'b1;
reg [1:0] state, n_state;
reg direction, n_dir;
reg [4:0] fall_cnt;
reg splatter;
always @(*) begin
if (splatter) n_state = SPLAT;
else if (~ground) n_state = FALL;
else if ((state != FALL) & (dig | (state == DIG))) n_state = DIG;
else n_state = WALK;
end
always @(*) begin
if ((state == WALK) & (n_state == WALK))
case (direction)
LEFT: n_dir = (bump_left) ? RIGHT : LEFT;
RIGHT: n_dir = (bump_right) ? LEFT : RIGHT;
endcase
else n_dir = direction;
end
always @(posedge clk, posedge areset) begin
if (areset) state <= LEFT;
else state <= n_state;
end
always @(posedge clk, posedge areset) begin
if (areset) direction <= WALK;
else direction <= n_dir;
end
always @(posedge clk, posedge areset) begin
if (areset) fall_cnt <= 0;
else if (fall_cnt != 21)
if (n_state == FALL) fall_cnt <= fall_cnt + 1;
else fall_cnt <= 0;
end
always @(posedge clk, posedge areset) begin
if (areset) splatter <= 0;
else if ((fall_cnt == 21) & (ground)) splatter <= 1;
end
assign walk_left = (state == WALK) & (direction == LEFT) & (splatter == 0);
assign walk_right = (state == WALK) & (direction == RIGHT) & (splatter == 0);
assign aaah = (state == FALL);
assign digging = (state == DIG);
endmodule
| 7.203305
|
module top_module (
input in,
input [9:0] state,
output [9:0] next_state,
output out1,
output out2
);
localparam S0 = 0, S1 = 1, S2 = 2, S3 = 3, S4 = 4, S5 = 5, S6 = 6, S7 = 7, S8 = 8, S9 = 9;
//states
assign next_state[S0] = (state[S0] & !in) | (state[S1] & !in) | (state[S2] & !in) | (state[S3] & !in) |
(state[S4] & !in) | (state[S7] & !in) | (state[S8] & !in) | (state[S9] & !in);
assign next_state[S1] = (state[S0] & in) | (state[S8] & in) | (state[S9] & in);
assign next_state[S2] = state[S1] & in;
assign next_state[S3] = state[S2] & in;
assign next_state[S4] = state[S3] & in;
assign next_state[S5] = state[S4] & in;
assign next_state[S6] = state[S5] & in;
assign next_state[S7] = (state[S6] & in) | (state[7] & in);
assign next_state[S8] = state[S5] & !in;
assign next_state[S9] = state[S6] & !in;
//output
assign out1 = state[8] | state[9];
assign out2 = state[7] | state[9];
endmodule
| 7.203305
|
module top_module (
input in,
input [9:0] state,
output [9:0] next_state,
output out1,
output out2
);
always @(*) begin
if (state == 0) next_state = 0;
// begin end 안쓰면 컴파일 에러 발생: 이유 불명
////////////////////
else if (~in) begin
next_state[0] = (|state[4:0]) | (|state[9:7]);
next_state[7:1] = 0;
next_state[8] = state[5];
next_state[9] = state[6];
end else begin
next_state[0] = 0;
next_state[1] = state[0] | state[8] | state[9];
next_state[6:2] = state[5:1];
next_state[7] = (|state[7:6]);
next_state[9:8] = 0;
end
////////////////////
end
assign out1 = (|state[9:8]);
assign out2 = state[7] | state[9];
endmodule
| 7.203305
|
module top_module (
input in,
input [9:0] state,
output [9:0] next_state,
output out1,
output out2
);
// state transition logic
assign next_state[0] = (state[0]&(~in)) | (state[1]&(~in)) | (state[2]&(~in)) | (state[3]&(~in)) |
(state[4]&(~in)) | (state[7]&(~in)) | (state[8]&(~in)) |(state[9]&(~in));
assign next_state[1] = (state[0] & in) | (state[8] & in) | (state[9] & in);
assign next_state[2] = state[1] & in;
assign next_state[3] = state[2] & in;
assign next_state[4] = state[3] & in;
assign next_state[5] = state[4] & in;
assign next_state[6] = state[5] & in;
assign next_state[7] = (state[6] & in) | (state[7] & in);
assign next_state[8] = state[5] & (~in);
assign next_state[9] = state[6] & (~in);
// output logic
assign out1 = (state[8] == 1'b1 || state[9] == 1'b1) ? 1'b1 : 1'b0;
assign out2 = (state[7] == 1'b1 || state[9] == 1'b1) ? 1'b1 : 1'b0;
endmodule
| 7.203305
|
module div4_341628725785264722 (
clk,
rst,
out_clk
);
output out_clk;
input clk;
input rst;
reg [1:0] data;
assign out_clk = data[1];
always @(posedge clk) begin
if (rst) data <= 2'b0;
else data <= data + 1;
end
endmodule
| 7.097321
|
module user_module_341628725785264722 (
input [7:0] io_in,
output [7:0] io_out
);
wire clk, rst_n, shift_clk, shift_dta;
wire [2:0] clk_source;
assign clk = io_in[0];
assign rst_n = io_in[1];
assign shift_clk = io_in[2];
assign shift_dta = io_in[3];
assign clk_source[0] = io_in[4];
assign clk_source[1] = io_in[5];
assign clk_source[2] = io_in[6];
/*Shift register chain, 16-bit*/
reg [11:0] shifter;
always @(posedge shift_clk) begin
shifter[11:1] <= shifter[10:0];
shifter[0] <= shift_dta;
end
/*Clock sources*/
//0
wire c0_1 = clk;
wire c0_output;
div4_341628725785264722 tmp0 (
c0_1,
rst_n,
c0_output
);
//1
wire c1_1, c1_2, c1_3, c1_output;
assign c1_1 = c1_3 ^ shifter[0];
assign c1_2 = c1_1 ^ shifter[1];
assign c1_3 = c1_2 ^ shifter[2];
div4_341628725785264722 tmp1 (
c1_3,
rst_n,
c1_output
);
//2
wire c2_1, c2_2, c2_3, c2_4, c2_5, c2_output;
assign c2_1 = c2_5 ^ shifter[0];
assign c2_2 = c2_1 ^ shifter[1];
assign c2_3 = c2_2 ^ shifter[2];
assign c2_4 = c2_3 ^ shifter[3];
assign c2_5 = c2_4 ^ shifter[4];
div4_341628725785264722 tmp2 (
c2_5,
rst_n,
c2_output
);
//3
wire c3_1, c3_output;
assign c3_1 = c3_1 ^ shifter[0];
div4_341628725785264722 tmp3 (
c3_1,
rst_n,
c3_output
);
//4 - requires shifter configuration to convert one stage to buffer
wire c4_1, c4_2, c4_output;
assign c4_1 = c4_2 ^ shifter[0];
assign c4_2 = c4_1 ^ shifter[1];
div4_341628725785264722 tmp4 (
c4_2,
rst_n,
c4_output
);
//5 - NAND version
wire c5_1, c5_2, c5_3, c5_4, c5_5, c5_output;
assign c5_1 = ~(c5_5 & shifter[0]);
assign c5_2 = ~(c5_1 & shifter[1]);
assign c5_3 = ~(c5_2 & shifter[2]);
assign c5_4 = ~(c5_3 & shifter[3]);
assign c5_5 = ~(c5_4 & shifter[4]);
div4_341628725785264722 tmp5 (
c5_5,
rst_n,
c5_output
);
//6 - NOR version
wire c6_1, c6_2, c6_3, c6_4, c6_5, c6_output;
assign c6_1 = ~(c6_5 | shifter[0]);
assign c6_2 = ~(c6_1 | shifter[1]);
assign c6_3 = ~(c6_2 | shifter[2]);
assign c6_4 = ~(c6_3 | shifter[3]);
assign c6_5 = ~(c6_4 | shifter[4]);
div4_341628725785264722 tmp6 (
c6_5,
rst_n,
c6_output
);
//7 - + version
wire c7_1, c7_2, c7_3, c7_4, c7_5, c7_output;
assign c7_1 = (c7_5 + shifter[0] + shifter[1]);
assign c7_2 = (c7_1 + shifter[2] + shifter[3]);
assign c7_3 = (c7_2 + shifter[4] + shifter[5]);
assign c7_4 = (c7_3 + shifter[6] + shifter[7]);
assign c7_5 = (c7_4 + shifter[8] + shifter[9]);
div4_341628725785264722 tmp7 (
c7_5,
rst_n,
c7_output
);
/*Clock selector*/
reg selected_clock;
always @(*) begin
case (clk_source)
3'b000: selected_clock = c0_output;
3'b001: selected_clock = c1_output;
3'b010: selected_clock = c2_output;
3'b011: selected_clock = c3_output;
3'b100: selected_clock = c4_output;
3'b101: selected_clock = c5_output;
3'b110: selected_clock = c6_output;
3'b111: selected_clock = c7_output;
endcase
end
/*Random generator*/
reg random_out;
always @(posedge clk) begin
case (clk_source)
3'b000: random_out = c1_1 ^ c2_1;
3'b001: random_out = c1_output ^ c2_output;
3'b010: random_out = c4_output ^ c5_output;
3'b011: random_out = c6_output ^ c7_output;
3'b100: random_out = c1_output ^ c2_output ^ c6_output;
3'b101: random_out = c4_output ^ c5_output ^ c6_output ^ c7_output;
3'b110: random_out = c1_1 ^ c2_1 ^ c6_1;
3'b111: random_out = c1_output ^ c2_output;
endcase
end
reg [29 : 0] data;
assign io_out[0] = data[7];
assign io_out[1] = data[11];
assign io_out[2] = data[15];
assign io_out[3] = data[19];
assign io_out[4] = data[23];
assign io_out[5] = data[27];
assign io_out[6] = random_out;
assign io_out[7] = shifter[11];
//div4_341628725785264722 tmp1(clk, rst_n, io_out[6]);
always @(posedge selected_clock or posedge rst_n) begin
if (rst_n) begin
data <= 'b0;
end else begin
data <= data + 1'b1;
end
end
endmodule
| 6.857392
|
module top_module (
input clk,
input [7:0] in,
input reset, // Synchronous reset
output done
); //
localparam [1:0] BYTE1 = 2'b00, BYTE2 = 2'b01, BYTE3 = 2'b10, DONE = 2'b11;
reg [1:0] state, next;
// State transition logic (combinational)
always @(*) begin
case (state)
BYTE1: next = (in[3]) ? BYTE2 : BYTE1;
BYTE2: next = BYTE3;
BYTE3: next = DONE;
DONE: next = (in[3]) ? BYTE2 : BYTE1;
endcase
end
// State flip-flops (sequential)
always @(posedge clk) begin
if (reset) state <= BYTE1;
else state <= next;
end
// Output logic
assign done = (state == DONE);
endmodule
| 7.203305
|
module top_module (
input clk,
input [7:0] in,
input reset, // Synchronous reset
output done
); //
parameter BYTE1 = 2'b00;
parameter BYTE2 = 2'b01;
parameter BYTE3 = 2'b10;
parameter DONE = 2'b11;
reg [2:0] state;
reg [2:0] next_state;
// sequential state transition logic
always @(posedge clk) begin
if (reset) state <= BYTE1;
else state <= next_state;
end
// combinational logic
always @(*) begin
case (state)
BYTE1:
if (in[3]) next_state = BYTE2;
else next_state = BYTE1;
BYTE2: next_state = BYTE3;
BYTE3: next_state = DONE;
DONE:
if (in[3]) next_state = BYTE2;
else next_state = BYTE1;
default: next_state = 2'bx;
endcase
end
// combinational logic output
assign done = (state == DONE) ? 1'b1 : 1'b0;
endmodule
| 7.203305
|
module top_module (
input clk,
input [7:0] in,
input reset, // Synchronous reset
output reg done
); //
reg [3:1] byt, n_byt; // byte: 변수명으로 불가
// State transition logic (combinational)
always @(*) begin
n_byt[3] = byt[2];
n_byt[2] = (in[3]) ? (byt[1] | done) : 0;
n_byt[1] = (~in[3]) ? (byt[1] | done) : 0;
end
// State flip-flops (sequential)
always @(posedge clk) begin
if (reset) byt <= 3'b001;
else byt <= n_byt;
end
// Output logic
always @(posedge clk) begin
if (reset) done <= 0;
else if (byt[3]) done <= 1;
else done <= 0;
end
endmodule
| 7.203305
|
module recepsaid_euclidean_algorithm (
input [7:0] io_in,
output [7:0] io_out
);
wire clk;
wire num_okey;
wire rst;
wire [3:0] number;
reg [3:0] num1;
reg [3:0] num2;
reg [6:0] ssd_out;
reg [2:0] state = S0;
reg start;
wire [3:0] gcd;
wire [6:0] decoder_out;
assign num_okey = io_in[7];
assign rst = io_in[6];
assign number = io_in[4:1];
assign clk = io_in[0];
assign io_out[6:0] = ssd_out;
localparam S0 = 3'd0, S1 = 3'd1, S2 = 3'd2, S3 = 3'd3, S4 = 3'd4;
always @(posedge clk) begin
if (rst) begin
//ssd_out idle state
state <= S0;
ssd_out <= 7'b1000000;
end else begin
case (state)
S0: begin
//ssd_out idle state
start <= 1'b0;
ssd_out <= 7'b1000000;
if (num_okey) begin
state <= S1;
end else begin
state <= S0;
end
end
S1: begin
//ssd_out okey state
num1 <= number;
start <= 1'b0;
ssd_out <= 7'b1011100;
if (~num_okey) begin
state <= S2;
end else begin
state <= S1;
end
end
S2: begin
//ssd_out next state
start <= 1'b0;
ssd_out <= 7'b1010100;
if (num_okey) begin
state <= S3;
end else begin
state <= S2;
end
end
S3: begin
//ssd_out okey state
num2 <= number;
start <= 1'b0;
ssd_out <= 7'b1011100;
if (~num_okey) begin
state <= S4;
end else begin
state <= S3;
end
end
S4: begin
//ssd_out result state
start <= 1'b1;
ssd_out <= decoder_out;
if (rst) begin
state <= S0;
end else begin
state <= S4;
end
end
default: begin
ssd_out <= 7'b1000000;
num1 <= 4'b0000;
num2 <= 4'b0000;
start <= 1'b0;
end
endcase
end
end
gcd_top #(
.DATA_BITS_TOP(4)
) gcdtop (
.okey_i (start),
.rst_i (rst),
.clk_i (clk),
.x_i (num1),
.y_i (num2),
.result_o(gcd)
);
ssd_decoder decoder (
.ssd_i(gcd),
.rst_i(rst),
.ssd_o(decoder_out)
);
endmodule
| 6.614222
|
module top_module (
input clk,
input [7:0] in,
input reset, // Synchronous reset
output [23:0] out_bytes,
output done
); //
localparam [1:0] BYTE1 = 2'b00, BYTE2 = 2'b01, BYTE3 = 2'b10, DONE = 2'b11;
reg [1:0] state, next;
reg [23:0] data;
// State transition logic (combinational)
always @(*) begin
case (state)
BYTE1: next = (in[3]) ? BYTE2 : BYTE1;
BYTE2: next = BYTE3;
BYTE3: next = DONE;
DONE: next = (in[3]) ? BYTE2 : BYTE1;
endcase
end
// State flip-flops (sequential)
always @(posedge clk) begin
if (reset) state <= BYTE1;
else state <= next;
end
// New: Datapath to store incoming bytes.
always @(posedge clk) begin
if (reset) data <= 24'b0;
else data <= {data[15:8], data[7:0], in};
end
// Output logic
assign done = (state == DONE);
assign out_bytes = (done) ? data : 23'b0;
endmodule
| 7.203305
|
module top_module (
input clk,
input [7:0] in,
input reset, // Synchronous reset
output reg [23:0] out_bytes,
output reg done
); //
parameter BYTE1 = 2'b00;
parameter BYTE2 = 2'b01;
parameter BYTE3 = 2'b10;
parameter DONE = 2'b11;
reg [2:0] state;
reg [2:0] next_state;
reg [7:0] in_before_3;
reg [7:0] in_before_2;
reg [7:0] in_before_1;
// sequential logic store data in reg
always @(posedge clk) begin
if (reset) begin
in_before_1 <= 8'd0;
in_before_2 <= 8'd0;
in_before_3 <= 8'd0;
end else begin
in_before_1 <= in;
in_before_2 <= in_before_1;
in_before_3 <= in_before_2;
end
end
// sequential state transition logic
always @(posedge clk) begin
if (reset) state <= BYTE1;
else state <= next_state;
end
// combinational logic
always @(*) begin
case (state)
BYTE1:
if (in[3]) next_state = BYTE2;
else next_state = BYTE1;
BYTE2: next_state = BYTE3;
BYTE3: next_state = DONE;
DONE:
if (in[3]) next_state = BYTE2;
else next_state = BYTE1;
default: next_state = 2'bx;
endcase
end
// combinational logic output
always @(*) begin
case (state)
BYTE1: begin
out_bytes = 24'bx;
done = 1'b0;
end
BYTE2: begin
out_bytes = 24'bx;
done = 1'b0;
end
BYTE3: begin
out_bytes = 24'bx;
done = 1'b0;
end
DONE: begin
out_bytes = {in_before_3, in_before_2, in_before_1};
done = 1'b1;
end
default: begin
out_bytes = 24'bx;
done = 1'bx;
end
endcase
end
endmodule
| 7.203305
|
module top_module (
input clk,
input [7:0] in,
input reset, // Synchronous reset
output [23:0] out_bytes,
output done
); //
// FSM from fsm_ps2
reg [3:1] byt, n_byt;
reg [23:0] data;
always @(*) begin
n_byt[3] = byt[2];
n_byt[2] = (in[3]) ? (byt[1] | done) : 0;
n_byt[1] = (~in[3]) ? (byt[1] | done) : 0;
end
always @(posedge clk) begin
if (reset) byt <= 3'b001;
else byt <= n_byt;
end
always @(posedge clk) begin
if (reset) done <= 0;
else if (byt[3]) done <= 1;
else done <= 0;
end
// New: Datapath to store incoming bytes.
always @(posedge clk) begin
if (reset) data <= 0;
else if (byt[3]) data[7:0] <= in;
else if (byt[2]) data[15:8] <= in;
else data[23:16] <= in;
end
assign out_bytes = (done) ? data : 0;
endmodule
| 7.203305
|
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