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module top_module (
input clk,
input in,
input reset, // Synchronous reset
output done
);
localparam [2:0] IDLE = 3'b000, START = 3'b001, RECEIVE = 3'b010, WAIT = 3'b011, STOP = 3'b100;
reg [2:0] state, next;
reg [3:0] i;
always @(*) begin
case (state)
IDLE: next = (in) ? IDLE : START;
START: next = RECEIVE;
RECEIVE: begin
if (i == 8) begin
if (in) next = STOP;
else next = WAIT;
end else next = RECEIVE;
end
WAIT: next = (in) ? IDLE : WAIT;
STOP: next = (in) ? IDLE : START;
endcase
end
always @(posedge clk) begin
if (reset) state <= IDLE;
else state <= next;
end
always @(posedge clk) begin
if (reset) begin
done <= 0;
i <= 0;
end else begin
case (next)
RECEIVE: begin
done <= 0;
i = i + 1;
end
STOP: begin
done <= 1;
i <= 0;
end
default: begin
done <= 0;
i <= 0;
end
endcase
end
end
endmodule
| 7.203305
|
module top_module (
input clk,
input in,
input reset, // Synchronous reset
output done
);
parameter Idle = 2'b00;
parameter Start = 2'b01;
parameter Data = 2'b10;
parameter Done = 2'b11;
reg [1:0] state;
reg [1:0] next_state;
reg [3:0] i;
reg in_last;
// sequential logic reset
always @(posedge clk) begin
if (reset) state <= Idle;
else state <= next_state;
// control i
case (state)
Idle: i <= 4'b0000;
Start: i <= 4'b0000;
Data: i <= i + 4'b0001;
Done: i <= 4'b0000;
default: i <= 4'b0000;
endcase
in_last <= in;
end
// combinational state transition logic
always @(*) begin
case (state)
Idle:
if ((in == 1'b0) && (in_last == 1'b1)) next_state = Start;
else next_state = Idle;
Start: next_state = Data;
Data:
if (i <= 4'b0110) next_state = Data;
else if ((in == 1'b1) && (in_last == 1'b0)) next_state = Done;
else next_state = Idle;
Done:
if ((in == 1'b0) && (in_last == 1'b1)) next_state = Start;
else next_state = Idle;
default: next_state = 2'bx;
endcase
end
// combinational logic output
assign done = (state == Done) ? 1'b1 : 1'b0;
endmodule
| 7.203305
|
module msaghir_top_level (
input [7:0] io_in,
output [7:0] io_out
);
wire w_clk = io_in[0];
wire w_rst = io_in[1];
wire [3:0] w_sel = io_in[5:2];
wire w_blink = io_in[6];
wire w_fx = io_in[7];
wire [6:0] w_segment;
wire w_clk2Hz;
wire [6:0] w_bus0;
wire [6:0] w_bus1;
assign io_out = {1'b0, w_segment};
digit_gen b0 (
.i_digit (w_sel),
.i_blink (w_blink),
.i_clk2Hz (w_clk2Hz),
.o_segment(w_bus0)
);
fx_gen b1 (
.i_clk(w_clk),
.i_rst(w_rst),
.i_sel(w_sel),
.o_clk2Hz(w_clk2Hz),
.o_segment(w_bus1)
);
mux2 b2 (
.i_in0(w_bus0),
.i_in1(w_bus1),
.i_sel(w_fx),
.o_out(w_segment)
);
endmodule
| 7.957213
|
module top_module (
input clk,
input in,
input reset, // Synchronous reset
output reg done
);
reg [8:1] count;
reg ready, start_data, end_data;
always @(posedge clk) begin
if (reset) start_data <= 1;
else start_data <= in & (start_data | ready | done);
end
always @(posedge clk) begin
if (reset) count <= 0;
else begin // -> 중요! 비트별로 나눠서 표현할때 begin end 없으면 결과 틀리게 나옴!
count[1] <= (~in) & (start_data | done);
count[8:2] <= count[7:1];
end
end
always @(posedge clk) begin
if (reset) end_data <= 0;
else end_data <= count[8];
end
always @(posedge clk) begin
if (reset) ready <= 0;
else ready <= (~in) & (end_data | ready);
end
always @(posedge clk) begin
if (reset) done <= 0;
else done <= in & end_data;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input in,
input reset, // Synchronous reset
output [7:0] out_byte,
output done
);
// Use FSM from Fsm_serial
localparam [2:0] IDLE = 3'b000, START = 3'b001, RECEIVE = 3'b010, WAIT = 3'b011, STOP = 3'b100;
reg [2:0] state, next;
reg [3:0] i;
reg [7:0] out;
always @(*) begin
case (state)
IDLE: next = (in) ? IDLE : START;
START: next = RECEIVE;
RECEIVE: begin
if (i == 8) begin
if (in) next = STOP;
else next = WAIT;
end else next = RECEIVE;
end
WAIT: next = (in) ? IDLE : WAIT;
STOP: next = (in) ? IDLE : START;
endcase
end
always @(posedge clk) begin
if (reset) state <= IDLE;
else state <= next;
end
always @(posedge clk) begin
if (reset) begin
done <= 0;
i <= 0;
end else begin
case (next)
RECEIVE: begin
done <= 0;
i = i + 1;
end
STOP: begin
done <= 1;
i <= 0;
end
default: begin
done <= 0;
i <= 0;
end
endcase
end
end
// New: Datapath to latch input bits.
always @(posedge clk) begin
if (reset) out <= 0;
else if (next == RECEIVE) out[i] <= in;
end
assign out_byte = (done) ? out : 8'b0;
endmodule
| 7.203305
|
module top_module (
input clk,
input in,
input reset, // Synchronous reset
output [7:0] out_byte,
output done
); //
// Use FSM from Fsm_serial
reg [8:1] count, data;
reg ready, start_data, end_data;
wire [8:1] n_count, n_data;
wire n_ready, n_start, n_done;
always @(*) begin
n_start = in & (start_data | ready | done);
begin
n_count[1] = (~in) & (start_data | done);
n_count[8:2] = count[7:1];
end
n_ready = (~in) & (end_data | ready);
n_done = (in & end_data);
if (|count) begin
case (count)
8'b0000_0001: n_data[1] = in;
8'b0000_0010: n_data[2] = in;
8'b0000_0100: n_data[3] = in;
8'b0000_1000: n_data[4] = in;
8'b0001_0000: n_data[5] = in;
8'b0010_0000: n_data[6] = in;
8'b0100_0000: n_data[7] = in;
8'b1000_0000: n_data[8] = in;
endcase
end else n_data = data;
end
always @(posedge clk) begin
if (reset) begin
start_data <= 1;
count <= 0;
end_data <= 0;
ready <= 0;
done <= 0;
data <= 0;
end else begin
start_data <= n_start;
count <= n_count;
end_data <= count[8];
ready <= n_ready;
done <= n_done;
data <= n_data;
end
end
assign out_byte = (done) ? data : 0;
endmodule
| 7.203305
|
module top_module (
input clk,
input in,
input reset, // Synchronous reset
output [7:0] out_byte,
output done
);
// Use FSM from Fsm_serial
localparam [2:0] IDLE = 3'b000,
START = 3'b001,
RECEIVE = 3'b010,
WAIT = 3'b011,
STOP = 3'b100,
CHECK = 3'b101;
reg [2:0] state, next;
reg [3:0] i;
reg [7:0] out;
reg odd_reset;
reg odd_reg;
//We can't use a reg-type variable in the instance module,
//so we need to declare a wire-type to be used in the instance module.
wire odd;
always @(*) begin
case (state)
IDLE : next = (in) ? IDLE : START;
START : next = RECEIVE;
RECEIVE : next = (i == 8) ? CHECK : RECEIVE;
CHECK : next = (in) ? STOP : WAIT;
WAIT : next = (in) ? IDLE : WAIT;
STOP : next = (in) ? IDLE : START;
endcase
end
always @(posedge clk) begin
if (reset) state <= IDLE;
else state <= next;
end
always @(posedge clk) begin
if (reset) begin
i <= 0;
end else begin
case (next)
RECEIVE: begin
i = i + 1;
end
STOP: begin
i <= 0;
end
default: begin
i <= 0;
end
endcase
end
end
// New: Datapath to latch input bits.
always @(posedge clk) begin
if (reset) out <= 0;
else if (next == RECEIVE) out[i] <= in;
end
// New: Add parity checking.
parity u_parity (
.clk(clk),
.reset(reset | odd_reset),
.in(in),
.odd(odd)
);
always @(posedge clk) begin
if (reset) odd_reg <= 0;
else odd_reg <= odd;
end
//Only the IDLE-state and STOP-state are likely to enter the RECEIVE-state,
//so we need to reset the bits to avoid the previous result's affection.
always @(posedge clk) begin
case (next)
IDLE: odd_reset <= 1;
STOP: odd_reset <= 1;
default: odd_reset <= 0;
endcase
end
assign done = ((state == STOP) && odd_reg);
assign out_byte = (done) ? out : 8'b0;
endmodule
| 7.203305
|
module top_module (
input clk,
input in,
input reset, // Synchronous reset
output [7:0] out_byte,
output done
); //
// Use FSM from Fsm_serial
reg [8:1] count, data;
reg ready, start_data, end_data, done_state;
reg [8:1] n_count, n_data;
reg n_ready, n_start, n_done;
reg par_state;
wire din, reset_p, parity;
always @(*) begin
n_start = in & (start_data | ready | done_state);
begin
n_count[1] = (~in) & (start_data | done_state);
n_count[8:2] = count[7:1];
end
n_ready = (~in) & (end_data | ready);
n_done = (in & end_data);
if (|count) begin
case (count)
8'b0000_0001: n_data = {data[8:2], in};
8'b0000_0010: n_data = {data[8:3], in, data[1]};
8'b0000_0100: n_data = {data[8:4], in, data[2:1]};
8'b0000_1000: n_data = {data[8:5], in, data[3:1]};
8'b0001_0000: n_data = {data[8:6], in, data[4:1]};
8'b0010_0000: n_data = {data[8:7], in, data[5:1]};
8'b0100_0000: n_data = {data[8], in, data[6:1]};
8'b1000_0000: n_data = {in, data[7:1]};
endcase
end else n_data = data;
end
always @(posedge clk) begin
if (reset) begin
start_data <= 1;
count <= 0;
end_data <= 0;
ready <= 0;
done_state <= 0;
data <= 0;
par_state <= 0;
end else begin
start_data <= n_start;
count <= n_count;
end_data <= par_state;
ready <= n_ready;
done_state <= n_done;
data <= n_data;
par_state <= count[8];
end
end
assign out_byte = (done_state & parity) ? data : 0;
assign done = (done_state & parity); //done 신호와 done 상태를 구분함으로써 버그 해결
// New: Add parity checking.
assign din = in & ((|count) | par_state);
assign reset_p = reset | ~((|count) | par_state | end_data);
parity parity_u0 (
.clk(clk),
.reset(reset_p),
.in(din),
.odd(parity)
);
endmodule
| 7.203305
|
module top_module;
reg clk;
reg in;
reg reset;
reg [8:1] out_byte;
reg done;
`probe(clk);
`probe(reset);
`probe(in);
initial `probe_start;
initial begin
clk = 0;
in = 1;
reset = 1;
end
always #5 clk = ~clk;
initial begin
repeat (3) @(posedge clk);
reset = 0;
repeat (1) @(posedge clk);
in = 0;
repeat (8) @(posedge clk);
repeat (1) @(posedge clk);
in = 1;
repeat (2) @(posedge clk);
in = 0;
repeat (1) @(posedge clk);
repeat (8) @(posedge clk);
in = 1;
repeat (2) @(posedge clk);
in = 0;
repeat (10) @(posedge clk);
$finish;
end
top_modulee top_module_u0 (
.clk(clk),
.in(in),
.reset(reset), // Synchronous reset
.out_byte(out_byte),
.done(done)
); //
endmodule
| 7.404542
|
module top_modulee (
input clk,
input in,
input reset, // Synchronous reset
output [7:0] out_byte,
output done
); //
// Use FSM from Fsm_serial
reg [8:1] count, data;
reg ready, start_data, end_data, done_state;
reg [8:1] n_count, n_data;
reg n_ready, n_start, n_done;
reg par_state;
wire din, reset_p, parity;
`probe(start_data);
`probe(count);
`probe(par_state);
`probe(end_data);
`probe(done_state);
`probe(ready);
`probe(din);
`probe(reset_p);
`probe(parity);
`probe(done);
always @(*) begin
n_start = in & (start_data | ready | done_state);
begin
n_count[1] = (~in) & (start_data | done_state);
n_count[8:2] = count[7:1];
end
n_ready = (~in) & (end_data | ready);
n_done = (in & end_data) & parity;
if (|count) begin
case (count)
8'b0000_0001: n_data = {data[8:2], in};
8'b0000_0010: n_data = {data[8:3], in, data[1]};
8'b0000_0100: n_data = {data[8:4], in, data[2:1]};
8'b0000_1000: n_data = {data[8:5], in, data[3:1]};
8'b0001_0000: n_data = {data[8:6], in, data[4:1]};
8'b0010_0000: n_data = {data[8:7], in, data[5:1]};
8'b0100_0000: n_data = {data[8], in, data[6:1]};
8'b1000_0000: n_data = {in, data[7:1]};
endcase
end else n_data = data;
end
always @(posedge clk) begin
if (reset) begin
start_data <= 1;
count <= 0;
end_data <= 0;
ready <= 0;
done_state <= 0;
data <= 0;
par_state <= 0;
end else begin
start_data <= n_start;
count <= n_count;
end_data <= par_state;
ready <= n_ready;
done_state <= n_done;
data <= n_data;
par_state <= count[8];
end
end
assign out_byte = (done_state & parity) ? data : 0;
assign done = (done_state & parity);
// New: Add parity checking.
assign din = in & ((|count) | par_state);
assign reset_p = reset | ~((|count) | par_state | end_data);
parity parity_u0 (
.clk(clk),
.reset(reset_p),
.in(din),
.odd(parity)
);
endmodule
| 6.909672
|
module parity (
input clk,
input reset,
input in,
output reg odd
);
always @(posedge clk)
if (reset) odd <= 0;
else if (in) odd <= ~odd;
endmodule
| 6.788563
|
module top_module (
input clk,
input reset, // Synchronous reset
input in,
output disc,
output flag,
output err
);
localparam [3:0] NONE = 0,
ONE = 1,
TWO = 2,
THREE= 3,
FOUR = 4,
FIVE = 5,
SIX = 6,
DISC = 7,
FLAG = 8,
ERR = 9;
reg [3:0] state, next;
always @(*) begin
case (state)
NONE: next = (in) ? ONE : NONE;
ONE: next = (in) ? TWO : NONE;
TWO: next = (in) ? THREE : NONE;
THREE: next = (in) ? FOUR : NONE;
FOUR: next = (in) ? FIVE : NONE;
FIVE: next = (in) ? SIX : DISC;
SIX: next = (in) ? ERR : FLAG;
DISC: next = (in) ? ONE : NONE;
FLAG: next = (in) ? ONE : NONE;
ERR: next = (in) ? ERR : NONE;
endcase
end
always @(posedge clk) begin
if (reset) state <= NONE;
else state <= next;
end
assign disc = (state == DISC);
assign flag = (state == FLAG);
assign err = (state == ERR);
endmodule
| 7.203305
|
module top_module (
input clk,
input reset, // Synchronous reset
input in,
output disc,
output flag,
output err
);
reg ready_stt, disc_stt, flag_stt, err_stt;
reg [6:1] data_stt;
reg n_ready, n_disc, n_flag, n_err;
reg [6:1] n_data;
always @(*) begin
n_ready = (~in) & (ready_stt | (|data_stt[4:1]) | disc_stt | flag_stt | err_stt);
begin
n_data[1] = (in) & (ready_stt | disc_stt | flag_stt);
n_data[6:2] = {5{(in)}} & data_stt[5:1]; // 벡터를 다룰때 (in)도 벡터로 바꿔야 함에 유의
end
n_disc = (~in) & data_stt[5];
n_flag = (~in) & data_stt[6];
n_err = (in) & (data_stt[6] | err_stt);
end
always @(posedge clk) begin
if (reset) begin
ready_stt <= 1;
data_stt <= 0;
disc_stt <= 0;
flag_stt <= 0;
err_stt <= 0;
end else begin
ready_stt <= n_ready;
data_stt <= n_data;
disc_stt <= n_disc;
flag_stt <= n_flag;
err_stt <= n_err;
end
end
assign disc = disc_stt;
assign flag = flag_stt;
assign err = err_stt;
endmodule
| 7.203305
|
module top_module;
reg clk;
reg in;
reg reset;
initial begin
`probe_start;
clk = 0;
reset = 1;
in = 0;
end
always #5 clk = ~clk;
initial begin
repeat (2) @(posedge clk);
reset = 0;
in = 1;
repeat (8) @(posedge clk);
reset = 1;
in = 0;
repeat (1) @(posedge clk);
reset = 0;
in = 1;
repeat (3) @(posedge clk);
$finish;
end
top_modulee top_module_u0 (
.clk(clk),
.in(in),
.reset(reset) // Synchronous reset
); //
endmodule
| 7.404542
|
module top_modulee (
input clk,
input reset, // Synchronous reset
input in,
output disc,
output flag,
output err
);
`probe(clk);
`probe(reset);
`probe(in);
`probe(ready_stt);
`probe(data_stt);
`probe(disc_stt);
`probe(flag_stt);
`probe(err_stt);
reg ready_stt, disc_stt, flag_stt, err_stt;
reg [6:1] data_stt;
reg n_ready, n_disc, n_flag, n_err;
reg [6:1] n_data;
always @(*) begin
n_ready = (~in) & (ready_stt | (|data_stt[4:1]) | disc_stt | flag_stt | err_stt);
begin
n_data[1] = (in) & (ready_stt | disc_stt | flag_stt);
n_data[6:2] = {5{(in)}} & data_stt[5:1];
end
n_disc = (~in) & data_stt[5];
n_flag = (~in) & data_stt[6];
n_err = (in) & (data_stt[6] | err_stt);
end
always @(posedge clk) begin
if (reset) begin
ready_stt <= 1;
data_stt <= 0;
disc_stt <= 0;
flag_stt <= 0;
err_stt <= 0;
end else begin
ready_stt <= n_ready;
data_stt <= n_data;
disc_stt <= n_disc;
flag_stt <= n_flag;
err_stt <= n_err;
end
end
assign disc = disc_stt;
assign flag = flag_stt;
assign err = err_stt;
endmodule
| 6.909672
|
module top_module (
input clk,
input aresetn, // Asynchronous active-low reset
input x,
output z
);
localparam [1:0] IDLE = 0, ONE = 1, ONE_ZERO = 2;
reg [1:0] state, next;
always @(*) begin
case (state)
IDLE: begin
next = (x) ? ONE : IDLE;
z = 0;
end
ONE: begin
next = (x) ? ONE : ONE_ZERO;
z = 0;
end
ONE_ZERO: begin
if (x) begin
next = ONE;
z = 1;
end else begin
next = IDLE;
z = 0;
end
end
endcase
end
always @(posedge clk or negedge aresetn) begin
if (~aresetn) state <= IDLE;
else state <= next;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input aresetn, // Asynchronous active-low reset
input x,
output z
);
reg [2:0] sequence_stt;
reg [2:0] n_sequence;
always @(*) begin
begin
n_sequence[0] = (~x) & (sequence_stt[0] | sequence_stt[2]);
n_sequence[1] = (x);
n_sequence[2] = (~x) & sequence_stt[1];
end
end
always @(posedge clk, negedge aresetn) begin
if (~aresetn) sequence_stt <= 3'b001;
else sequence_stt <= n_sequence;
end
assign z = (x) & sequence_stt[2];
endmodule
| 7.203305
|
module option22 (
input wire [7:0] io_in,
output wire [7:0] io_out
);
parameter WORD_COUNT = 22;
wire clk = io_in[0];
wire reset = io_in[1];
wire write = io_in[2];
wire din = io_in[3];
assign io_out = buffer[7:0];
reg [2:0] count;
reg [8 * WORD_COUNT - 1:0] buffer;
wire [7:0] bh = (write & din) | (!write & buffer[15]);
always @(posedge clk or posedge reset) begin
if (reset) begin
count <= 3'd0;
end else begin
if (count == 3'b111) begin
buffer <= {buffer[7:0], buffer[WORD_COUNT*8-1:16], bh, buffer[15:9]};
end else begin
buffer[15:8] <= {bh, buffer[15:9]};
end
count <= count + 3'd1;
end
end
endmodule
| 6.576128
|
module/cache/src/cache_top_tb.v
// Project Name: cache
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: cache_top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module cache_top_tb;
// Inputs
reg clk_2x;
reg rst_n_2x;
reg [31:0] in_LBA;
reg in_update_cache_2x;
// Outputs
// Instantiate the Unit Under Test (UUT)
cache_top uut (
.clk_2x(clk_2x),
.rst_n_2x(rst_n_2x),
.in_LBA(in_LBA),
.in_update_cache_2x(in_update_cache_2x)
);
initial begin
// Initialize Inputs
rst_n_2x = 0;
clk_2x =0;
in_update_cache_2x<=0;
in_LBA<=0;
// Wait 400 ns for global reset to finish
#100;
// Add stimulus here
rst_n_2x = 1;
#200;
in_update_cache_2x<=1;
in_LBA<=32'h19860001;
#10;
in_update_cache_2x<=0;
#400;
in_update_cache_2x<=1;
in_LBA<=32'h07180001;
#10;
in_update_cache_2x<=0;
end
// Clock generation
always
#5 clk_2x = ~clk_2x;
endmodule
| 7.107939
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = (~IR[7:0]);
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = '0;
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = '1;
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
modules are perfectly functional, it is
// good practice to seperate combinational logic from non-combinational
// logic. In other words, it is recommended to avoid implementing
// flip-flops and regular logic gates in the same `always` construct.
//
// A better manner to implement the above two modules is thus given here:
//
module oscillator_better(
clk,
reset,
out
);
input clk;
input reset;
output reg out;
wire out_next;
assign out_next = ~out; // Combinational logic
always @(posedge clk or posedge reset) begin // Only a flip-flop
if (reset) begin
out = 1'b0;
end else begin
out = out_next;
end
end
endmodule
| 7.018526
|
module right (
in,
dis
);
input [3:0] in;
output [4:0] dis;
assign dis = in >> 1;
endmodule
| 6.997075
|
module test;
reg [3:0] in;
wire [4:0] dis;
wire [4:0] disr;
left l (
in,
dis
);
right r (
in,
disr
);
initial begin
$display("Number\t LeftShift \tRightShift");
$monitor("%h \t %d \t\t%d", in, dis, disr);
in = 4'b0000;
#10 in = 4'b0001;
#10 in = 4'b0010;
#10 in = 4'b0011;
#10 in = 4'b0100;
#10 in = 4'b0101;
#10 in = 4'b0110;
#10 in = 4'b0111;
#10 in = 4'b1000;
#10 in = 4'b1001;
#10 in = 4'b1010;
#10 in = 4'b1011;
#10 in = 4'b1100;
#10 in = 4'b1101;
#10 in = 4'b1110;
#10 in = 4'b1111;
#10 $finish;
end
endmodule
| 6.635152
|
module top_module (
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
input dig,
output walk_left,
output walk_right,
output aaah,
output digging
);
parameter LEFT = 0, RIGHT = 1, DOWN_L = 2, DOWN_R = 3, DIG_L = 4, DIG_R = 5, END = 6;
reg [2:0] cstate, nstate;
reg [4:0] cnt;
reg cnt_end;
always @(posedge clk or posedge areset) begin
if (areset) begin
cnt <= 0;
cnt_end <= 0;
end else begin
if (aaah) begin
if (cnt > 18) begin
cnt_end <= 1;
end else begin
cnt <= cnt + 1;
end
end else begin
cnt <= 0;
end
end
end
always @(posedge clk or posedge areset) begin
if (areset) begin
cstate <= LEFT;
end else begin
cstate <= nstate;
end
end
always @(*) begin
case (cstate)
LEFT: nstate = ground ? (dig ? DIG_L : (bump_left ? RIGHT : LEFT)) : DOWN_L;
RIGHT: nstate = ground ? (dig ? DIG_R : (bump_right ? LEFT : RIGHT)) : DOWN_R;
DOWN_L: nstate = ground ? (cnt_end ? END : LEFT) : DOWN_L;
DOWN_R: nstate = ground ? (cnt_end ? END : RIGHT) : DOWN_R;
DIG_L: nstate = ground ? DIG_L : DOWN_L;
DIG_R: nstate = ground ? DIG_R : DOWN_R;
END: nstate = END;
endcase
end
assign walk_left = (cstate == LEFT);
assign walk_right = (cstate == RIGHT);
assign aaah = (cstate == DOWN_L || cstate == DOWN_R);
assign digging = (cstate == DIG_L || cstate == DIG_R);
endmodule
| 7.203305
|
module top_module (
input too_cold,
input too_hot,
input mode,
input fan_on,
output heater,
output aircon,
output fan
);
assign heater = mode && too_cold;
assign aircon = (~mode) && too_hot;
assign fan = aircon || heater || fan_on;
endmodule
| 7.203305
|
module top_module (
input in,
input [9:0] state,
output [9:0] next_state,
output out1,
output out2
);
assign next_state[0] = state[0]&(~in) | state[1]&(~in) | state[2]&(~in) | state[3]&(~in) | state[4]&(~in) | state[7]&(~in) | state[8]&(~in) | state[9]&(~in);
assign next_state[1] = state[0] & in | state[8] & in | state[9] & in;
assign next_state[2] = state[1] & in;
assign next_state[3] = state[2] & in;
assign next_state[4] = state[3] & in;
assign next_state[5] = state[4] & in;
assign next_state[6] = state[5] & in;
assign next_state[7] = state[6] & in | state[7] & in;
assign next_state[8] = state[5] & (~in);
assign next_state[9] = state[6] & (~in);
assign out1 = (state[8] == 1 | state[9] == 1);
assign out2 = (state[7] == 1 | state[9] == 1);
endmodule
| 7.203305
|
module top_module (
input clk,
input j,
input k,
output Q
);
always @(posedge clk) begin
Q <= j & ~Q | ~k & Q;
end
endmodule
| 7.203305
|
module top_module (
input too_cold,
input too_hot,
input mode,
input fan_on,
output heater,
output aircon,
output fan
);
assign heater = too_cold & mode;
assign aircon = too_hot & ~mode;
assign fan = heater | aircon | fan_on;
endmodule
| 7.203305
|
module top_module (
input [2:0] a,
input [2:0] b,
output [2:0] out_or_bitwise,
output out_or_logical,
output [5:0] out_not
);
assign out_or_bitwise = a | b;
assign out_or_logical = a || b;
assign out_not = {~b, ~a};
endmodule
| 7.203305
|
module top_module (
input clk,
input areset,
input x,
output z
);
parameter A = 2'b00, B = 2'b01, C = 2'b10;
reg [1:0] state, state_next;
always @(posedge clk or posedge areset) begin
if (areset) state <= A;
else state <= state_next;
end
always @(*) begin
case (state)
A: begin
if (x) state_next <= B;
else state_next <= A;
end
B: begin
if (x) state_next <= C;
else state_next <= B;
end
C: begin
if (x) state_next <= C;
else state_next <= B;
end
default: state_next <= A;
endcase
end
assign z = (state == B);
endmodule
| 7.203305
|
module top_module (
input clk,
input areset,
input x,
output z
);
reg buf0_stt, buf1_stt, not0_stt, not1_stt;
reg n_buf0, n_buf1, n_not0, n_not1;
always @(*) begin
n_buf0 = (~x) & buf0_stt;
n_buf1 = (x) & buf0_stt;
n_not0 = (x) & (buf1_stt | not0_stt | not1_stt);
n_not1 = (~x) & (buf1_stt | not0_stt | not1_stt);
end
always @(posedge clk, posedge areset) begin
if (areset) begin
buf0_stt <= 1;
buf1_stt <= 0;
not0_stt <= 0;
not1_stt <= 0;
end else begin
buf0_stt <= n_buf0;
buf1_stt <= n_buf1;
not0_stt <= n_not0;
not1_stt <= n_not1;
end
end
assign z = (buf1_stt | not1_stt);
endmodule
| 7.203305
|
module top_module (
input clk,
input areset,
input x,
output z
);
localparam [1:0] A = 2'b01, B = 2'b10;
reg [1:0] state, next;
always @(*) begin
case (state)
A: begin
if (x) begin
next = B;
z = 1;
end else begin
next = A;
z = 0;
end
end
B: begin
next = B;
z = (x) ? 0 : 1;
end
endcase
end
always @(posedge clk or posedge areset) begin
if (areset) state <= A;
else state <= next;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input areset,
input x,
output z
);
reg A_stt, B_stt;
reg n_A, n_B;
always @(*) begin
n_A = (~x) & A_stt;
n_B = (x) | ((~x) & B_stt);
end
always @(posedge clk, posedge areset) begin
if (areset) begin
A_stt <= 1;
B_stt <= 0;
end else begin
A_stt <= n_A;
B_stt <= n_B;
end
end
assign z = (A_stt) ? x : ~x;
endmodule
| 7.203305
|
module top_module (
input clk,
input reset, // Synchronous reset
input s,
input w,
output z
);
localparam A = 0, B = 1;
reg state, next;
reg [2:0] cnt;
reg [2:0] w_record;
always @(*) begin
case (state)
A: next = (s) ? B : A;
B: next = B;
endcase
end
always @(posedge clk) begin
if (reset) begin
state <= A;
end else state <= next;
end
always @(posedge clk) begin
if (reset) w_record <= 0;
else if (state == B) w_record <= {w_record[1:0], w}; //update the record of w.
end
always @(posedge clk) begin
if (reset) cnt <= 0;
else if (next == B) begin
if (cnt == 3) cnt <= 1;
else cnt <= cnt + 1;
end
end
assign z = ((cnt == 1) & ((w_record == 3'b011) | (w_record == 3'b101) | (w_record == 3'b110)));
endmodule
| 7.203305
|
module top_module (
input clk,
input reset, // Synchronous reset
input s,
input w,
output z
);
reg A_stt, B_stt, B1_stt, B2_stt, B3_stt;
reg n_A, n_B, n_B1, n_B2, n_B3;
reg [1:0] count;
always @(*) begin
n_A = (~s) & A_stt;
n_B = (s) & A_stt;
n_B1 = B_stt | B3_stt;
n_B2 = B1_stt;
n_B3 = B2_stt;
end
always @(posedge clk) begin
if (reset) begin
A_stt <= 1;
B_stt <= 0;
B1_stt <= 0;
B2_stt <= 0;
B3_stt <= 0;
end else begin
A_stt <= n_A;
B_stt <= n_B;
B1_stt <= n_B1;
B2_stt <= n_B2;
B3_stt <= n_B3;
end
end
always @(posedge clk) begin
if (reset) count <= 0;
else if (A_stt | ((~w) & B3_stt)) count <= 0;
else if ((w) & B3_stt) count <= 1;
else if (w) count <= count + 1;
end
assign z = B3_stt & (count == 2);
endmodule
| 7.203305
|
module top_module (
input clk,
input reset, // Synchronous reset
input x,
output z
);
parameter a = 0, b = 1, c = 2, d = 3, e = 4;
reg [2:0] state, next_state;
always @(*) begin
case (state)
a: next_state = x ? b : a;
b: next_state = x ? e : b;
c: next_state = x ? b : c;
d: next_state = x ? c : b;
e: next_state = x ? e : d;
endcase
end
always @(posedge clk) begin
if (reset) begin
state <= a;
end else begin
state <= next_state;
end
end
assign z = (state == d || state == e);
endmodule
| 7.203305
|
module femto_top #(
parameter OPSIZE = 3, //Number of opcodes, power of 2 (3 => 2**3 = 8 opcodes)
parameter NUMRF = 2, //Number of registers in register file, power of 2 (2 => 2**2 = 4 registers)
parameter SIZE = 4 //Size of data in bits
) (
input [7:0] io_in,
output [7:0] io_out
);
wire clk = io_in[0];
reg [1:0] mode;
reg change_state;
reg [1:0] next_mode;
always @(*) begin
if (io_in[3:1] == 0 && io_in[7:6] == 2'b10) begin
change_state = 1'b1;
next_mode = io_in[5:4];
end else begin
change_state = 0;
next_mode = 0;
end
end
always @(posedge clk) begin
if (change_state == 1) begin
mode <= next_mode;
end
end
//Mode:
//00: No action
//01: Run (Read instruction buffer)
//10: Fill (Write instruction buffer)
//11: N/A
wire wren=mode[1]&&(io_in[3:1]!=0&&io_in[7:6]!=2'b10); //Don't write when changing state
wire rden = mode[0];
wire [6:0] instr_in = io_in[7:1];
wire [6:0] instr_out;
ibuffer #(
.ENTRIES(6)
) ibuf (
.clk(clk),
.wren(wren),
.rden(rden),
.instr_in(instr_in),
.instr_out(instr_out)
);
//Decode (from interface)
// wire[OPSIZE-1:0] op=io_in[1+:OPSIZE]; //opcode wire
// wire [NUMRF-1:0] reg_0=io_in[1+OPSIZE+:NUMRF]; //register address 0 (Dest)
// wire [NUMRF-1:0] reg_1=io_in[1+OPSIZE+NUMRF+:NUMRF]; //register address 1 (Src)
wire [OPSIZE-1:0] op = instr_out[2:0]; //opcode wire
wire [ NUMRF-1:0] reg_0 = instr_out[4:3]; //register address 0 (Dest)
wire [ NUMRF-1:0] reg_1 = instr_out[6:5]; //register address 1 (Src)
wire valid = (op == {(OPSIZE) {1'b1}}) ? 1 : 0;
wire rd = (op != 3'h6 && op != 3'h0 && op != 3'h1);
wire wr = (op == 3'h6);
reg [ 3:0] value;
wire [SIZE-1:0] data_0, data_1, data_out;
reg_file #(
.NUMRF(NUMRF),
.SIZE (SIZE)
) rf (
.clk(clk),
.rd(rd),
.wr(wr),
.reg_out(reg_1),
.reg_in(reg_0),
.data_in(data_0),
.data_out(data_1)
);
//Execute
alu_gen #(
.OPSIZE(OPSIZE),
.SIZE (SIZE)
) alu (
.clk (clk),
.op (op),
.inp (data_1),
.outp(data_out)
);
//Output
assign data_0 = data_out;
always @(posedge clk) begin
if (valid == 1) begin
value <= data_out;
end
end
seg7 seg (
.value(value),
.segments(io_out[6:0])
);
endmodule
| 8.54729
|
module top_module (
input clk,
input reset, // Synchronous reset
input x,
output z
);
reg [2:0] y_st;
reg [2:0] n_y;
always @(*) begin
case (y_st)
3'b000: n_y = (x) ? 3'b001 : 3'b000;
3'b001: n_y = (x) ? 3'b100 : 3'b001;
3'b010: n_y = (x) ? 3'b001 : 3'b010;
3'b011: n_y = (x) ? 3'b010 : 3'b001;
3'b100: n_y = (x) ? 3'b100 : 3'b011;
endcase
end
always @(posedge clk) begin
if (reset) y_st <= 0;
else y_st <= n_y;
end
assign z = (y_st == 3'b011) | (y_st == 3'b100);
endmodule
| 7.203305
|
module top_module (
input clk,
input [2:0] y,
input x,
output Y0,
output z
);
reg [2:0] Y;
always @(*) begin
case ({
y, x
})
4'b0000: Y = 3'b000;
4'b0001: Y = 3'b001;
4'b0010: Y = 3'b001;
4'b0011: Y = 3'b100;
4'b0100: Y = 3'b010;
4'b0101: Y = 3'b001;
4'b0110: Y = 3'b001;
4'b0111: Y = 3'b010;
4'b1000: Y = 3'b011;
4'b1001: Y = 3'b100;
endcase
end
assign z = (y == 3'b011 || y == 3'b100);
assign Y0 = Y[0];
endmodule
| 7.203305
|
module logisim_demo (
input [7:0] io_in,
output [7:0] io_out
);
wire s_CLK = io_in[0];
wire s_A;
wire s_B;
wire s_C;
wire s_D;
wire s_E;
wire s_F;
wire s_G;
wire s_DP;
assign io_out[0] = s_A;
assign io_out[1] = s_B;
assign io_out[2] = s_C;
assign io_out[3] = s_D;
assign io_out[4] = s_E;
assign io_out[5] = s_F;
assign io_out[6] = s_G;
assign io_out[7] = s_DP;
wire s_RST = io_in[1];
main CIRCUIT_0 (
.CLK(s_CLK),
.A (s_A),
.B (s_B),
.C (s_C),
.D (s_D),
.E (s_E),
.F (s_F),
.G (s_G),
.DP (s_DP),
.RST(s_RST)
);
endmodule
| 7.371981
|
module top_module (
input clk,
input [2:0] y,
input x,
output Y0,
output z
);
reg [2:0] n_y;
always @(*) begin
case (y)
3'b000: n_y = (x) ? 3'b001 : 3'b000;
3'b001: n_y = (x) ? 3'b100 : 3'b001;
3'b010: n_y = (x) ? 3'b001 : 3'b010;
3'b011: n_y = (x) ? 3'b010 : 3'b001;
3'b100: n_y = (x) ? 3'b100 : 3'b011;
default: n_y = 1;
endcase
end
assign Y0 = n_y[0];
assign z = (y == 3'b011) | (y == 3'b100);
endmodule
| 7.203305
|
module top_module (
input [3:1] y,
input w,
output Y2
);
reg [3:1] Y;
// A000 B001 C010 D011 E100 F101
always @(*) begin
case ({
y, w
})
4'b0000: Y = 3'b001;
4'b0001: Y = 3'b000;
4'b0010: Y = 3'b010;
4'b0011: Y = 3'b011;
4'b0100: Y = 3'b100;
4'b0101: Y = 3'b011;
4'b0110: Y = 3'b101;
4'b0111: Y = 3'b000;
4'b1000: Y = 3'b100;
4'b1001: Y = 3'b011;
4'b1010: Y = 3'b010;
4'b1011: Y = 3'b011;
endcase
end
assign Y2 = Y[2];
endmodule
| 7.203305
|
module top_module (
input [3:1] y,
input w,
output Y2
);
parameter A = 0, B = 1, C = 2, D = 3, E = 4, F = 5;
reg [3:1] n_y;
always @(*) begin
case (y)
A: n_y = (w) ? A : B;
B: n_y = (w) ? D : C;
C: n_y = (w) ? D : E;
D: n_y = (w) ? A : F;
E: n_y = (w) ? D : E;
F: n_y = (w) ? D : C;
endcase
end
assign Y2 = n_y[2];
endmodule
| 7.203305
|
module top_module (
input [6:1] y,
input w,
output Y2,
output Y4
);
assign Y2 = y[1] & (~w);
assign Y4 = (y[2] & w) | (y[3] & w) | (y[5] & w) | (y[6] & w);
endmodule
| 7.203305
|
module top_module (
input [6:1] y,
input w,
output Y2,
output Y4
);
parameter A = 1, B = 2, C = 3, D = 4, E = 5, F = 6;
reg [6:1] n_y;
always @(*) begin
begin
n_y[A] = (w) & (y[A] | y[D]);
n_y[B] = (~w) & y[A];
n_y[C] = (~w) & (y[B] | y[F]);
n_y[D] = (w) & (y[B] | y[C] | y[E] | y[F]);
n_y[E] = (w) & (y[C] | y[E]);
n_y[F] = (w) & y[D];
end
end
assign Y2 = n_y[2];
assign Y4 = n_y[4];
endmodule
| 7.203305
|
module top_module (
input clk,
input reset, // synchronous reset
input w,
output z
);
parameter a = 3'b000, b = 3'b001, c = 3'b010, d = 3'b011, e = 3'b100, f = 3'b101;
reg [2:0] state, next_state;
always @(*) begin
case ({
state, w
})
{a, 1'b0} : next_state = b;
{a, 1'b1} : next_state = a;
{b, 1'b0} : next_state = c;
{b, 1'b1} : next_state = d;
{c, 1'b0} : next_state = e;
{c, 1'b1} : next_state = d;
{d, 1'b0} : next_state = f;
{d, 1'b1} : next_state = a;
{e, 1'b0} : next_state = e;
{e, 1'b1} : next_state = d;
{f, 1'b0} : next_state = c;
{f, 1'b1} : next_state = d;
default: next_state = a;
endcase
end
always @(posedge clk) begin
if (reset) state <= a;
else state <= next_state;
end
assign z = (state == e || state == f);
endmodule
| 7.203305
|
module poisonninja_top (
input logic [7:0] io_in,
output logic [7:0] io_out
);
assign io_out[7:1] = 0;
pwm_generator pwm (
.clk(io_in[0]),
.reset(io_in[1]),
.duty(io_in[7:2]),
.pwm_signal(io_out[0])
);
endmodule
| 7.182896
|
module top_module (
input clk,
input reset, // synchronous reset
input w,
output z
);
parameter A = 1, B = 2, C = 3, D = 4, E = 5, F = 6;
reg [6:1] y_st;
reg [6:1] n_y;
always @(*) begin
begin
n_y[A] = (w) & (y_st[A] | y_st[D]);
n_y[B] = (~w) & y_st[A];
n_y[C] = (~w) & (y_st[B] | y_st[F]);
n_y[D] = (w) & (y_st[B] | y_st[C] | y_st[E] | y_st[F]);
n_y[E] = (~w) & (y_st[C] | y_st[E]);
n_y[F] = (~w) & y_st[D];
end
end
always @(posedge clk) begin
if (reset) y_st <= 6'b000_001;
else y_st <= n_y;
end
assign z = y_st[E] | y_st[F];
endmodule
| 7.203305
|
module top_module (
input clk,
input reset, // synchronous reset
input w,
output z
);
parameter a = 3'b000, b = 3'b001, c = 3'b010, d = 3'b011, e = 3'b100, f = 3'b101;
reg [2:0] state, next_state;
always @(*) begin
case ({
state, w
})
{a, 1'b0} : next_state = a;
{a, 1'b1} : next_state = b;
{b, 1'b0} : next_state = d;
{b, 1'b1} : next_state = c;
{c, 1'b0} : next_state = d;
{c, 1'b1} : next_state = e;
{d, 1'b0} : next_state = a;
{d, 1'b1} : next_state = f;
{e, 1'b0} : next_state = d;
{e, 1'b1} : next_state = e;
{f, 1'b0} : next_state = d;
{f, 1'b1} : next_state = c;
default: next_state = a;
endcase
end
always @(posedge clk) begin
if (reset) state <= a;
else state <= next_state;
end
assign z = (state == e || state == f);
endmodule
| 7.203305
|
module top_module (
input clk,
input reset, // synchronous reset
input w,
output z
);
parameter A = 1, B = 2, C = 3, D = 4, E = 5, F = 6;
reg [6:1] y_st;
reg [6:1] n_y;
always @(*) begin
begin
n_y[A] = (~w) & (y_st[A] | y_st[D]);
n_y[B] = (w) & y_st[A];
n_y[C] = (w) & (y_st[B] | y_st[F]);
n_y[D] = (~w) & (y_st[B] | y_st[C] | y_st[E] | y_st[F]);
n_y[E] = (w) & (y_st[C] | y_st[E]);
n_y[F] = (w) & y_st[D];
end
end
always @(posedge clk) begin
if (reset) y_st <= 6'b000_001;
else y_st <= n_y;
end
assign z = y_st[E] | y_st[F];
endmodule
| 7.203305
|
module top_module (
input [5:0] y,
input w,
output Y1,
output Y3
);
assign Y1 = y[0] & w;
assign Y3 = (y[1] & (~w)) | (y[2] & (~w)) | (y[4] & (~w)) | (y[5] & (~w));
endmodule
| 7.203305
|
module top_module (
input [5:0] y,
input w,
output Y1,
output Y3
);
parameter A = 0, B = 1, C = 2, D = 3, E = 4, F = 5;
reg [5:0] n_y;
always @(*) begin
begin
n_y[A] = (~w) & (y[A] | y[D]);
n_y[B] = (w) & (y[A]);
n_y[C] = (w) & (y[B] | y[F]);
n_y[D] = (~w) & (y[B] | y[C] | y[E] | y[F]);
n_y[E] = (w) & (y[C] | y[E]);
n_y[F] = (w) & (y[D]);
end
end
assign Y1 = n_y[1];
assign Y3 = n_y[3];
endmodule
| 7.203305
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = (~IR[15:14]);
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = '0;
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = '1;
reg ZF;
wire load = ((opcode == 'b010001011) && (mod == 1));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module
//author:WangFW
//date:2020-5-23
module ALU(clk,rst_n,opcode,dina,dinb,cout,dout);
input clk;
input rst_n;
input [2:0] opcode;
input [7:0] dina;
input [7:0] dinb;
output reg cout;
output reg [7:0] dout;
parameter op_add=3'b000;
parameter op_sub=3'b001;
parameter op_and=3'b010;
parameter op_or=3'b011;
parameter op_xor=3'b100;
parameter op_sl=3'b101;
parameter op_sr=3'b110;
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
cout<=1'b0;
dout<=8'd0;
end
else
begin
case(opcode)
op_add:{cout,dout}<=dina+dinb;
op_sub:dout<=(dina>dinb)?(dina-dinb):(dinb-dina);
op_and:dout<=dina&dinb;
op_or:dout<=dina | dinb;
op_xor:dout<=dina^dinb;
op_sl:dout<=dina<<dinb;
op_sr:dout<=dina>>dinb;
default:dout<=8'd0;
endcase
end
end
endmodule
| 7.170771
|
module comb15 (
A,
B,
CIN,
S,
COUT
);
input [3:0] A, B;
input CIN;
output [3:0] S;
output COUT;
wire [1:0] S0, S1, S2, S3;
function signed [1:0] ADD;
input A, B, CIN;
reg S, COUT;
begin
S = A ^ B ^ CIN;
COUT = (A & B) | (A & CIN) | (B & CIN);
ADD = {COUT, S};
end
endfunction
assign S0 = ADD(
A[0], B[0], CIN
),
S1 = ADD(
A[1], B[1], S0[1]
),
S2 = ADD(
A[2], B[2], S1[1]
),
S3 = ADD(
A[3], B[3], S2[1]
),
S = {
S3[0], S2[0], S1[0], S0[0]
},
COUT = S3[1];
endmodule
| 6.620711
|
module implements a 3-cycle delay line.
// Its output is equal to its input delayed by 3 clock cycles.
//
// --a->[reg]--b->[reg]--c->[reg]--d->
//
module delay3(
clk,
a,
d
);
input clk;
input a;
output reg d;
reg b;
reg c;
always @(posedge clk) begin
d = c;
c = b;
b = a;
end
endmodule
| 6.904081
|
module top_module (
input in,
input [9:0] state,
output [9:0] next_state,
output out1,
output out2
);
assign out1 = state[8] || state[9];
assign out2 = state[7] || state[9];
assign next_state[0] = (~in) && (state[0] || state[1]|| state[2]|| state[3]|| state[4] || state[7] || state[8] || state[9]) ;
assign next_state[1] = in && (state[0] || state[8] || state[9]);
assign next_state[2] = in && state[1];
assign next_state[3] = in && state[2];
assign next_state[4] = in && state[3];
assign next_state[5] = in && state[4];
assign next_state[6] = in && state[5];
assign next_state[7] = in && (state[6] || state[7]);
assign next_state[8] = (~in) && state[5];
assign next_state[9] = (~in) && state[6];
endmodule
| 7.203305
|
module top_module (
input [2:0] in,
output [1:0] out
);
integer i, count;
always @* begin
count = 0;
for (i = 0; i < 3; i = i + 1) begin
if (in[i] == 1'b1) count = count + 1;
end
out = count;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input [7:0] in,
output [7:0] pedge
);
reg [7:0] intermediate;
always @(posedge clk) begin
intermediate <= in;
pedge <= (~intermediate) & in;
end
endmodule
| 7.203305
|
module bidirec (
oe,
clk,
inp,
outp,
bidir
);
// Port Declaration
input oe;
input clk;
input [7:0] inp;
output [7:0] outp;
inout [7:0] bidir;
reg [7:0] a;
reg [7:0] b;
assign bidir = oe ? a : 8'bZ;
assign outp = b;
// Always Construct
always @(posedge clk) begin
b <= bidir;
a <= inp;
end
endmodule
| 7.291187
|
module top_module (
input clk,
input [7:0] in,
output [7:0] pedge
);
reg [7:0] q;
always @(posedge clk) begin
q <= in;
pedge <= (q ^ in) & in; // pedge <= in & ~q;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input [7:0] in,
input reset, // Synchronous reset
output done
); //
parameter A = 0, B = 1, C = 2, D = 3;
reg [1:0] state, nextstate;
// State transition logic (combinational)
always @(*) begin
case (state)
A: nextstate = in[3] ? B : A;
B: nextstate = C;
C: nextstate = D;
D: nextstate = in[3] ? B : A;
endcase
end
// State flip-flops (sequential)
always @(posedge clk) begin
if (reset) state <= A;
else state <= nextstate;
end
// Output logic
assign done = (state == D);
endmodule
| 7.203305
|
module top_module (
input [2:0] in,
output [1:0] out
);
assign out[0] = (~in[2] & ~in[1] & in[0]) | (~in[2] & in[1] & ~in[0]) | (in[2] & ~in[1] & ~in[0]) | (in[2] & in[1] & in[0]);
assign out[1] = (~in[2] & in[1] & in[0]) | (in[2] & ~in[1] & in[0]) | (in[2] & in[1] & ~in[0]) | (in[2] & in[1] & in[0]);
endmodule
| 7.203305
|
module top_module (
input [3:0] in,
output out_and,
output out_or,
output out_xor
);
assign out_and = in[0] & in[1] & in[2] & in[3];
assign out_or = in[0] | in[1] | in[2] | in[3];
assign out_xor = in[0] ^ in[1] ^ in[2] ^ in[3];
endmodule
| 7.203305
|
module finite_state_machine (
input clk,
input reset,
input w,
output [2:0] state,
output [2:0] next_state,
output z
);
reg [2:0] state;
reg [2:0] next_state;
reg z;
// 请完成模块的设计
localparam A = 0, B = 1, C = 2, D = 3, E = 4, F = 5;
initial begin
next_state = 0;
z = 0;
end
always @(state, w) begin
case (state)
A: begin
state = A;
z = 0;
if (w) next_state = A;
else next_state = B;
end
B: begin
state = B;
z = 0;
if (w) next_state = D;
else next_state = C;
end
C: begin
state = C;
z = 0;
if (w) next_state = D;
else next_state = E;
end
D: begin
state = D;
z = 0;
if (w) next_state = A;
else next_state = F;
end
E: begin
state = E;
z = 1;
if (w) next_state = D;
else next_state = E;
end
F: begin
state = F;
z = 1;
if (w) next_state = D;
else next_state = C;
end
endcase
end
always @(posedge clk) begin
if (reset == 1) state <= A;
else state <= next_state;
end
endmodule
| 6.962185
|
module top_module (
input clk,
input resetn, // active-low synchronous reset
input [3:1] r, // request
output [3:1] g // grant
);
parameter a = 2'd0, b = 2'd1, c = 2'd2, d = 2'd3;
reg [1:0] state, next_state;
always @(*) begin
case (state)
a: begin
if (r[1]) next_state = b;
else if (~r[1] & r[2]) next_state = c;
else if (~r[1] & ~r[2] & r[3]) next_state = d;
else next_state = a;
end
b: begin
if (r[1]) next_state = b;
else next_state = a;
end
c: begin
if (r[2]) next_state = c;
else next_state = a;
end
d: begin
if (r[3]) next_state = d;
else next_state = a;
end
endcase
end
always @(posedge clk) begin
if (~resetn) state <= a;
else state <= next_state;
end
assign g[1] = (state == b);
assign g[2] = (state == c);
assign g[3] = (state == d);
endmodule
| 7.203305
|
module top_module (
input clk,
input resetn, // active-low synchronous reset
input [3:1] r, // request
output [3:1] g // grant
);
reg A_st, B_st, C_st, D_st;
reg n_A, n_B, n_C, n_D;
always @(*) begin
n_A = ((~(|r)) & A_st) | ((~r[1]) & B_st) | ((~r[2]) & C_st) | ((~r[3]) & D_st);
n_B = r[1] & (A_st | B_st);
n_C = r[2] & (((~r[1]) & A_st) | C_st);
n_D = r[3] & (((~r[1]) & (~r[2]) & A_st) | D_st);
end
always @(posedge clk) begin
if (~resetn) begin
A_st <= 1;
B_st <= 0;
C_st <= 0;
D_st <= 0;
end else begin
A_st <= n_A;
B_st <= n_B;
C_st <= n_C;
D_st <= n_D;
end
end
always @(*) begin
begin
g[1] = B_st;
g[2] = C_st;
g[3] = D_st;
end
end
endmodule
| 7.203305
|
module top_module (
input clk,
input resetn, // active-low synchronous reset
input x,
input y,
output reg f,
output reg g
);
parameter A=4'd0, f1=4'd1, tmp0=4'd2, tmp1=4'd3, tmp2=4'd4, g1=4'd5, g1p=4'd6, tmp3=4'd7, g0p=4'd8;
reg [3:0] state, next_state;
always @(*) begin
case (state)
A: begin
if (resetn) next_state = f1;
else next_state = A;
end
f1: next_state = tmp0;
tmp0: begin
if (x) next_state = tmp1;
else next_state = tmp0;
end
tmp1: begin
if (~x) next_state = tmp2;
else next_state = tmp1;
end
tmp2: begin
if (x) next_state = g1;
else next_state = tmp0;
end
g1: begin
if (y) next_state = g1p;
else next_state = tmp3;
end
tmp3: begin
if (y) next_state = g1p;
else next_state = g0p;
end
g1p: begin
if (~resetn) next_state = A;
else next_state = g1p;
end
g0p: begin
if (~resetn) next_state = A;
else next_state = g0p;
end
endcase
end
always @(posedge clk) begin
if (~resetn) state <= A;
else state <= next_state;
end
always @(posedge clk) begin
case (next_state)
f1: f <= 1'b1;
g1: g <= 1'b1;
tmp3: g <= 1'b1;
g1p: g <= 1'b1;
g0p: g <= 1'b0;
default: begin
f <= 1'b0;
g <= 1'b0;
end
endcase
end
endmodule
| 7.203305
|
module top_module (
input clk,
input resetn, // active-low synchronous reset
input x,
input y,
output f,
output g
);
reg A_st, E_st;
reg [3:1] C_st;
reg [2:1] B_st, D_st;
reg n_A, n_E;
reg [3:1] n_C;
reg [2:1] n_B, n_D;
reg A_shift;
always @(*) begin
n_A = 0;
begin
n_B[1] = A_st;
n_B[2] = B_st[1] | ((~x) & (B_st[2] | C_st[2]));
end
begin
n_C[1] = (x) & (B_st[2] | C_st[1]);
n_C[2] = (~x) & C_st[1];
n_C[3] = (x) & C_st[2];
end
begin
n_D[1] = (~y) & C_st[3];
n_D[2] = ((~y) & D_st[1]) | D_st[2];
end
n_E = ((y) & (C_st[3] | D_st[1])) | E_st;
end
always @(posedge clk) begin
if (~resetn) begin
A_st <= 1;
B_st <= 0;
C_st <= 0;
D_st <= 0;
E_st <= 0;
end else begin
A_st <= n_A;
B_st <= n_B;
C_st <= n_C;
D_st <= n_D;
E_st <= n_E;
end
end
assign f = B_st[1];
assign g = C_st[3] | D_st[1] | E_st;
endmodule
| 7.203305
|
module top_module (
input clk,
input reset,
output [9:0] q
);
always @(posedge clk) begin
if (reset) q <= 0;
else begin
if (q < 999) q <= q + 1;
else q <= 0;
end
end
endmodule
| 7.203305
|
module top_module (
input clk,
input reset,
output [9:0] q
);
always @(posedge clk) begin
if (reset) q <= 0;
else if (q == 10'd999) q <= 0;
else q <= q + 1;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input shift_ena,
input count_ena,
input data,
output [3:0] q
);
reg [3:0] shift_temp;
always @(posedge clk) begin
if (shift_ena) begin
shift_temp <= {shift_temp[2:0], data};
end else if (count_ena) begin
shift_temp <= shift_temp - 1;
end
end
assign q = shift_temp;
endmodule
| 7.203305
|
module top_module (
input clk,
input shift_ena,
input count_ena,
input data,
output [3:0] q
);
initial begin
q = 0;
end
always @(posedge clk) begin
if (shift_ena) q <= {q[2:0], data};
else if (count_ena) q <= q - 1;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input reset, // Synchronous reset
input data,
output start_shifting
);
localparam [2:0] IDLE = 0, S1 = 1, S11 = 2, S110 = 3, S1101 = 4;
reg [2:0] state, next;
always @(*) begin
case (state)
IDLE: next = (data) ? S1 : IDLE;
S1: next = (data) ? S11 : IDLE;
S11: next = (data) ? S11 : S110;
S110: next = (data) ? S1101 : IDLE;
S1101: next = S1101;
endcase
end
always @(posedge clk) begin
if (reset) begin
state <= IDLE;
end else state <= next;
end
assign start_shifting = (state == S1101);
endmodule
| 7.203305
|
module top_module (
input clk,
input reset, // Synchronous reset
input data,
output start_shifting
);
reg none_st;
reg [4:1] A_st;
reg n_none;
reg [4:1] n_A;
always @(*) begin
n_none = (~data) & (none_st | A_st[1] | A_st[3]);
begin
n_A[1] = (data) & none_st;
n_A[2] = (data) & (A_st[1] | A_st[2]);
n_A[3] = (~data) & A_st[2];
n_A[4] = ((data) & A_st[3]) | A_st[4];
end
end
always @(posedge clk) begin
if (reset) begin
none_st <= 1;
A_st <= 0;
end else begin
none_st <= n_none;
A_st <= n_A;
end
end
assign start_shifting = A_st[4];
endmodule
| 7.203305
|
module top_module (
input clk,
input reset, // Synchronous reset
output shift_ena
);
parameter S0 = 3'd0, S1 = 3'd1, S2 = 3'd2, S3 = 3'd3, S4 = 3'd4;
reg [2:0] state, next_state;
always @(*) begin
case (state)
S0: next_state = reset ? S1 : S0;
S1: next_state = S2;
S2: next_state = S3;
S3: next_state = S4;
S4: next_state = S0;
endcase
end
always @(posedge clk) begin
state <= next_state;
end
assign shift_ena = (state == S1 | state == S2 | state == S3 | state == S4);
endmodule
| 7.203305
|
module top_module (
input clk,
input reset, // Synchronous reset
output shift_ena
);
reg [1:0] counter;
always @(posedge clk) begin
if (reset) counter <= 0;
else if (counter < 3) counter <= counter + 1;
end
always @(posedge clk) begin
if (reset) shift_ena <= 1;
else if (counter < 3) shift_ena <= 1;
else shift_ena <= 0;
end
endmodule
| 7.203305
|
module top_module (
input clk,
input reset, // Synchronous reset
input data,
output shift_ena,
output counting,
input done_counting,
output done,
input ack
);
localparam [3:0] IDLE = 0,
S1 = 1,
S11 = 2,
S110 = 3,
S1101 = 4, //'S1101' and 'SHIFT0' can be regarded as one state.
SHIFT1 = 5, SHIFT2 = 6, SHIFT3 = 7, COUNT = 8, DONE = 9;
reg [3:0] state, next;
always @(*) begin
case (state)
IDLE: next = (data) ? S1 : IDLE;
S1: next = (data) ? S11 : IDLE;
S11: next = (data) ? S11 : S110;
S110: next = (data) ? S1101 : IDLE;
S1101: next = SHIFT1;
SHIFT1: next = SHIFT2;
SHIFT2: next = SHIFT3;
SHIFT3: next = COUNT;
COUNT: next = (done_counting) ? DONE : COUNT;
DONE: next = (ack) ? IDLE : DONE;
endcase
end
always @(posedge clk) begin
if (reset) state <= IDLE;
else state <= next;
end
assign shift_ena = ((state == S1101) | (state == SHIFT1) | (state == SHIFT2) | (state == SHIFT3));
assign counting = (state == COUNT);
assign done = (state == DONE);
endmodule
| 7.203305
|
module top_module (
input clk,
input reset, // Synchronous reset
input data,
output shift_ena,
output counting,
input done_counting,
output done,
input ack
);
reg data_st, shift_st, count_st, done_st;
reg n_data, n_shift, n_count, n_done;
reg start_shifting, done_shift, shift;
wire recog_rst, shift_rst;
assign recog_rst = reset | (~data_st);
recognizer_1101 recognizer_1101_u0 (
.clk(clk),
.reset(recog_rst),
.data(data),
.start_shifting(start_shifting)
);
assign shift_rst = ~shift_st;
shift_register shift_register_u0 (
.clk(clk),
.reset(shift_rst),
.shift_ena(shift),
.done_shift(done_shift)
);
assign shift_ena = shift & shift_st;
assign counting = count_st;
assign done = done_st;
// top stage
///////////////////////////////////////////////////
always @(*) begin
n_data = ((ack) & done_st) | ((~start_shifting) & data_st);
n_shift = ((start_shifting) & data_st) | ((~done_shift) & shift_st);
n_count = ((done_shift) & shift_st) | ((~done_counting) & count_st);
n_done = ((done_counting) & count_st) | ((~ack) & done_st);
end
always @(posedge clk) begin
if (reset) begin
data_st <= 1;
shift_st <= 0;
count_st <= 0;
done_st <= 0;
end else begin
data_st <= n_data;
shift_st <= n_shift;
count_st <= n_count;
done_st <= n_done;
end
end
///////////////////////////////////////////////////
endmodule
| 7.203305
|
module recognizer_1101 (
input clk,
input reset, // Synchronous reset
input data,
output start_shifting
);
reg none_st;
reg [4:1] A_st;
reg n_none;
reg [4:1] n_A;
always @(*) begin
n_none = (~data) & (none_st | A_st[1] | A_st[3]);
begin
n_A[1] = (data) & none_st;
n_A[2] = (data) & (A_st[1] | A_st[2]);
n_A[3] = (~data) & A_st[2];
n_A[4] = ((data) & A_st[3]) | A_st[4];
end
end
always @(posedge clk) begin
if (reset) begin
none_st <= 1;
A_st <= 0;
end else begin
none_st <= n_none;
A_st <= n_A;
end
end
assign start_shifting = n_A[4];
endmodule
| 6.715743
|
module shift_register (
input clk,
input reset, // Synchronous reset
output reg shift_ena,
output reg done_shift
);
reg [1:0] counter;
always @(posedge clk) begin
if (reset) counter <= 0;
else if (counter < 3) counter <= counter + 1;
end
always @(posedge clk) begin
if (reset) shift_ena <= 1;
else if (counter < 3) shift_ena <= 1;
else shift_ena <= 0;
end
always @(posedge clk) begin
if (reset) done_shift <= 0;
else if (counter == 2) done_shift <= 1;
else done_shift <= 0;
end
endmodule
| 6.854847
|
module top_module;
reg clk;
reg reset;
reg data;
reg done_counting;
reg ack;
initial begin
`probe_start;
clk = 0;
reset = 1'bx;
data = 1'bx;
done_counting = 1'bx;
ack = 1'bx;
end
always #5 clk = ~clk;
initial begin
repeat (1) @(posedge clk);
reset = 1;
data = 0;
repeat (1) @(posedge clk);
reset = 0;
data = 1;
repeat (1) @(posedge clk);
data = 0;
repeat (2) @(posedge clk);
data = 1;
repeat (2) @(posedge clk);
data = 0;
repeat (1) @(posedge clk);
data = 1;
repeat (1) @(posedge clk);
data = 1'bx;
repeat (10) @(posedge clk);
$finish;
end
top_modulee top_module_u0 (
.clk(clk),
.reset(reset), // Synchronous reset
.data(data),
.done_counting(done_counting),
.ack(ack)
); //
endmodule
| 7.404542
|
module top_modulee (
input clk,
input reset, // Synchronous reset
input data,
output shift_ena,
output counting,
input done_counting,
output done,
input ack
);
`probe(clk);
`probe(reset);
`probe(data);
`probe(done_counting);
`probe(ack);
`probe(start_shifting);
`probe(done_shift);
`probe(shift_ena);
`probe(counting);
`probe(done);
`probe(data_st);
`probe(shift_st);
`probe(count_st);
`probe(done_st);
reg data_st, shift_st, count_st, done_st;
reg n_data, n_shift, n_count, n_done;
reg start_shifting, done_shift, shift;
wire recog_rst, shift_rst;
assign recog_rst = reset | (~data_st);
recognizer_1101 recognizer_1101_u0 (
.clk(clk),
.reset(recog_rst),
.data(data),
.start_shifting(start_shifting)
);
assign shift_rst = ~shift_st;
shift_register shift_register_u0 (
.clk(clk),
.reset(shift_rst),
.shift_ena(shift),
.done_shift(done_shift)
);
assign shift_ena = shift & shift_st;
assign counting = count_st;
assign done = done_st;
// top stage
///////////////////////////////////////////////////
always @(*) begin
n_data = ((ack) & done_st) | ((~start_shifting) & data_st);
n_shift = ((start_shifting) & data_st) | ((~done_shift) & shift_st);
n_count = ((done_shift) & shift_st) | ((~done_counting) & count_st);
n_done = ((done_counting) & count_st) | ((~ack) & done_st);
end
always @(posedge clk) begin
if (reset) begin
data_st <= 1;
shift_st <= 0;
count_st <= 0;
done_st <= 0;
end else begin
data_st <= n_data;
shift_st <= n_shift;
count_st <= n_count;
done_st <= n_done;
end
end
///////////////////////////////////////////////////
endmodule
| 6.909672
|
module recognizer_1101 (
input clk,
input reset, // Synchronous reset
input data,
output start_shifting
);
reg none_st;
reg [4:1] A_st;
reg n_none;
reg [4:1] n_A;
always @(*) begin
n_none = (~data) & (none_st | A_st[1] | A_st[3]);
begin
n_A[1] = (data) & none_st;
n_A[2] = (data) & (A_st[1] | A_st[2]);
n_A[3] = (~data) & A_st[2];
n_A[4] = ((data) & A_st[3]) | A_st[4];
end
end
always @(posedge clk) begin
if (reset) begin
none_st <= 1;
A_st <= 0;
end else begin
none_st <= n_none;
A_st <= n_A;
end
end
assign start_shifting = n_A[4];
endmodule
| 6.715743
|
module shift_register (
input clk,
input reset, // Synchronous reset
output reg shift_ena,
output reg done_shift
);
reg [1:0] counter;
always @(posedge clk) begin
if (reset) counter <= 0;
else if (counter < 3) counter <= counter + 1;
end
always @(posedge clk) begin
if (reset) shift_ena <= 1;
else if (counter < 3) shift_ena <= 1;
else shift_ena <= 0;
end
always @(posedge clk) begin
if (reset) done_shift <= 0;
else if (counter == 2) done_shift <= 1;
else done_shift <= 0;
end
endmodule
| 6.854847
|
module top_module (
input clk,
input reset, // Synchronous reset
input data,
output [3:0] count,
output counting,
output done,
input ack
);
localparam [3:0] IDLE = 0,
S1 = 1,
S11 = 2,
S110 = 3,
S1101 = 4, //'S1101' and 'SHIFT0' can be regarded as one state.
SHIFT1 = 5, SHIFT2 = 6, SHIFT3 = 7, COUNT = 8, DONE = 9;
reg [3:0] state, next;
reg [9:0] count_1000;
always @(*) begin
case (state)
IDLE: next = (data) ? S1 : IDLE;
S1: next = (data) ? S11 : IDLE;
S11: next = (data) ? S11 : S110;
S110: next = (data) ? S1101 : IDLE;
S1101: next = SHIFT1;
SHIFT1: next = SHIFT2;
SHIFT2: next = SHIFT3;
SHIFT3: next = COUNT;
COUNT: next = (count == 0 & count_1000 == 999) ? DONE : COUNT;
DONE: next = (ack) ? IDLE : DONE;
endcase
end
//state transition
always @(posedge clk) begin
if (reset) state <= IDLE;
else state <= next;
end
//shift in and then down count.
always @(posedge clk) begin
case (state)
S1101: count[3] <= data;
SHIFT1: count[2] <= data;
SHIFT2: count[1] <= data;
SHIFT3: count[0] <= data;
COUNT: begin
if (count >= 0) begin
if (count_1000 < 999) count_1000 <= count_1000 + 1;
else begin
count <= count - 1;
count_1000 <= 0;
end
end
end
default: count_1000 <= 0;
endcase
end
assign counting = (state == COUNT);
assign done = (state == DONE);
endmodule
| 7.203305
|
module top_module (
input clk,
input reset, // Synchronous reset
input data,
output [3:0] count,
output counting,
output done,
input ack
);
reg data_st, shift_st, count_st, done_st;
reg n_data, n_shift, n_count, n_done;
reg start_shifting, done_shift, shift;
reg [9:0] counter_1000;
wire recog_rst, shift_rst, shift_ena, done_counting;
assign recog_rst = reset | (~data_st);
recognizer_1101 recognizer_1101_u0 (
.clk(clk),
.reset(recog_rst),
.data(data),
.start_shifting(start_shifting)
);
assign shift_rst = ~shift_st;
shift_register shift_register_u0 (
.clk(clk),
.reset(shift_rst),
.shift_ena(shift),
.done_shift(done_shift)
);
assign shift_ena = shift & shift_st;
always @(posedge clk) begin
if (reset) counter_1000 <= 0;
else if (count_st) begin
if (counter_1000 == 10'd999) counter_1000 <= 0;
else counter_1000 <= counter_1000 + 1;
end else counter_1000 <= 0;
end
always @(posedge clk) begin
if (reset) count <= 0;
else if (shift_ena) count <= {count[2:0], data};
else if (count_st & (counter_1000 == 10'd999) & (|count)) count <= count - 1;
end
assign counting = count_st;
assign done_counting = count_st & (count == 0) & (counter_1000 == 10'd999);
assign done = done_st;
// top stage
///////////////////////////////////////////////////
always @(*) begin
n_data = ((ack) & done_st) | ((~start_shifting) & data_st);
n_shift = ((start_shifting) & data_st) | ((~done_shift) & shift_st);
n_count = ((done_shift) & shift_st) | ((~done_counting) & count_st);
n_done = ((done_counting) & count_st) | ((~ack) & done_st);
end
always @(posedge clk) begin
if (reset) begin
data_st <= 1;
shift_st <= 0;
count_st <= 0;
done_st <= 0;
end else begin
data_st <= n_data;
shift_st <= n_shift;
count_st <= n_count;
done_st <= n_done;
end
end
///////////////////////////////////////////////////
endmodule
| 7.203305
|
module recognizer_1101 (
input clk,
input reset, // Synchronous reset
input data,
output start_shifting
);
reg none_st;
reg [4:1] A_st;
reg n_none;
reg [4:1] n_A;
always @(*) begin
n_none = (~data) & (none_st | A_st[1] | A_st[3]);
begin
n_A[1] = (data) & none_st;
n_A[2] = (data) & (A_st[1] | A_st[2]);
n_A[3] = (~data) & A_st[2];
n_A[4] = ((data) & A_st[3]) | A_st[4];
end
end
always @(posedge clk) begin
if (reset) begin
none_st <= 1;
A_st <= 0;
end else begin
none_st <= n_none;
A_st <= n_A;
end
end
assign start_shifting = n_A[4];
endmodule
| 6.715743
|
module shift_register (
input clk,
input reset, // Synchronous reset
output reg shift_ena,
output reg done_shift
);
reg [1:0] counter;
always @(posedge clk) begin
if (reset) counter <= 0;
else if (counter < 3) counter <= counter + 1;
end
always @(posedge clk) begin
if (reset) shift_ena <= 1;
else if (counter < 3) shift_ena <= 1;
else shift_ena <= 0;
end
always @(posedge clk) begin
if (reset) done_shift <= 0;
else if (counter == 2) done_shift <= 1;
else done_shift <= 0;
end
endmodule
| 6.854847
|
module top_module (
input d,
input done_counting,
input ack,
input [9:0] state, // 10-bit one-hot current state
output B3_next,
output S_next,
output S1_next,
output Count_next,
output Wait_next,
output done,
output counting,
output shift_ena
); //
// You may use these parameters to access state bits using e.g., state[B2] instead of state[6].
parameter S = 0, S1 = 1, S11 = 2, S110 = 3, B0 = 4, B1 = 5, B2 = 6, B3 = 7, Count = 8, Wait = 9;
assign B3_next = state[B2];
assign S_next = (state[S] & (~d)) | (state[S1] & (~d)) | (state[S110] & (~d)) | (state[Wait] & ack);
assign S1_next = state[S] & d;
assign Count_next = state[B3] | (state[Count] & (~done_counting));
assign Wait_next = (state[Count] & (done_counting)) | (state[Wait] & (~ack));
assign done = state[Wait];
assign counting = state[Count];
assign shift_ena = state[B0] | state[B1] | state[B2] | state[B3];
endmodule
| 7.203305
|
module top_module (
input d,
input done_counting,
input ack,
input [9:0] state, // 10-bit one-hot current state
output B3_next,
output S_next,
output S1_next,
output Count_next,
output Wait_next,
output done,
output counting,
output shift_ena
); //
// You may use these parameters to access state bits using e.g., state[B2] instead of state[6].
parameter S = 0, S1 = 1, S11 = 2, S110 = 3, B0 = 4, B1 = 5, B2 = 6, B3 = 7, Count = 8, Wait = 9;
reg S11_next, S111_next, B0_next, B1_next, B2_next;
always @(*) begin
S_next = ((~d) & (state[S] | state[S1] | state[S110])) | ((ack) & state[Wait]);
S1_next = (d) & state[S];
S11_next = (d) & (state[S1] | state[S11]);
S111_next = (~d) & state[S11];
B0_next = (d) & state[S110];
B1_next = state[B0];
B2_next = state[B1];
B3_next = state[B2];
Count_next = state[B3] | ((~done_counting) & state[Count]);
Wait_next = ((done_counting) & state[Count]) | ((~ack) & state[Wait]);
end
assign done = state[Wait];
assign counting = state[Count];
assign shift_ena = (|state[B3:B0]);
endmodule
| 7.203305
|
module top_module (
input sel,
input [7:0] a,
input [7:0] b,
output [7:0] out
);
assign out = sel ? a : b;
endmodule
| 7.203305
|
module top_module (
input sel,
input [7:0] a,
input [7:0] b,
output [7:0] out
);
// assign out = (~sel & a) | (sel & b);
assign out = (sel) ? a : b;
endmodule
| 7.203305
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = (~((opcode == 'b010001011) && (mod == 1)));
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = '0;
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else full <= {ue[4], ue[3], ue[2], ue[1], ue[0]};
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]) IR <= bus_in;
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode = IR[7:0];
wire [1:0] mod = IR[15:14];
reg ZF;
wire load = '1;
wire move = ((opcode == 'b010001001) && (mod == 3));
wire store = ((opcode == 'b010001001) && (mod == 1));
wire memory = (load || store);
wire add = (opcode == 'b01);
wire sub = (opcode == 'b0101001);
wire halt = (opcode == 'b011110100);
wire aluop = (add || sub);
wire jnez = (opcode == 'b01110101);
wire [4:0] RD = IR[10:8];
wire [4:0] RS = IR[13:11];
wire [4:0] Aad = (memory ? 6 : RD), Bad = RS;
wire [31:0] distance = {{24{IR[15]}}, IR[15:8]};
wire [31:0] displacement = {{24{IR[23]}}, IR[23:16]};
wire btaken = (jnez && (!ZF));
wire [1:0] length = (memory ? 3 : (((aluop || move) || jnez) ? 2 : 1));
always @(posedge clk)
if (rst) IP <= 0;
else if (ue[1]) begin
A <= Aop;
B <= Bop;
if ((!halt)) begin
IP <= ((IP + length) + (btaken ? distance : 0));
end else begin
$finish;
end
end
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2 = (memory ? displacement : (sub ? (~B) : B));
wire [31:0] ALUout = ((A + ALU_op2) + sub);
always @(posedge clk)
if (rst) ZF = 0;
else if (ue[2]) begin
MAR <= ALUout;
C <= (move ? B : ALUout);
MDRw <= B;
if (aluop) ZF <= (ALUout == 0);
end
reg [31:0] MDRr;
always @(posedge clk) if ((ue[3] && load)) MDRr <= bus_in;
assign bus_A = (ue[3] ? MAR : (ue[0] ? IP : 0));
assign bus_RE = (ue[0] || (ue[3] && load));
reg [31:0] R[7:0];
assign Aop = R[Aad];
assign Bop = R[Bad];
assign bus_WE = (ue[3] && store);
assign bus_out = MDRw;
always @(posedge clk)
if (rst) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
end else if (ue[4])
if (((aluop || move) || load))
if (load) R[RS] <= MDRr;
else R[RD] <= C;
assign current_opcode = opcode;
endmodule
| 6.868788
|
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