Datasets:
metadata
title: ascad-v2-1
tags:
- side-channel-analysis
- cryptography
- DLSCA
parameters:
HF_ORG: DLSCA
CHUNK_SIZE_Y: 50000
CHUNK_SIZE_X: 200
TOTAL_CHUNKS_ON_Y: 2
TOTAL_CHUNKS_ON_X: 5000
NUM_JOBS: 10
CAN_RUN_LOCALLY: true
CAN_RUN_ON_CLOUD: false
COMPRESSED: true
ascad-v2-1
This script downloads, extracts, and uploads the optimized ASCAD v2 (1-100k traces) dataset to Hugging Face Hub.
Dataset Structure
This dataset is stored in Zarr format, optimized for chunked and compressed cloud storage.
Traces (/traces)
- Shape:
[100000, 1000000](Traces x Time Samples) - Data Type:
int8 - Chunk Shape:
[50000, 200]
Metadata (/metadata)
- ciphertext: shape
[100000, 16], dtypeuint8 - key: shape
[100000, 16], dtypeuint8 - mask: shape
[100000, 16], dtypeuint8 - mask_: shape
[100000, 16], dtypeuint8 - plaintext: shape
[100000, 16], dtypeuint8 - rin: shape
[100000, 1], dtypeuint8 - rin_: shape
[100000, 1], dtypeuint8 - rm: shape
[100000, 1], dtypeuint8 - rm_: shape
[100000, 1], dtypeuint8 - rout: shape
[100000, 1], dtypeuint8 - rout_: shape
[100000, 1], dtypeuint8
Auto-Generated Leakage Plots and Targets
| Dataset | Target | Byte Index | Description | Plot | Zoomed Plot |
|---|---|---|---|---|---|
| ascad-v2-1 | ciphertext |
0 | ViewRaw ciphertext byte at positionbyte_index.ciphertext[i] where i = byte_index. |
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| ascad-v2-1 | key |
0 | ViewRaw key byte at positionbyte_index.key[i] where i = byte_index. |
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| ascad-v2-1 | mask |
0 | ViewRaw per-byte mask at positionbyte_index.mask[i] where i = byte_index. |
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| ascad-v2-1 | mask_ |
0 | ViewRaw per-byte mask for second S-box pass at positionbyte_index.mask_[i] where i = byte_index. |
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| ascad-v2-1 | plaintext |
0 | ViewRaw plaintext byte at positionbyte_index.plaintext[i] where i = byte_index. |
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| ascad-v2-1 | sbi |
0 | ViewUnmasked S-Box Input (SBI) at AES byte positionbyte_index.ptx[i] ^ key[i] where i = byte_index. |
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- |
| ascad-v2-1 | sbo |
0 | ViewUnmasked S-Box Output (SBO) at AES byte positionbyte_index.SBOX[ptx[i] ^ key[i]] where i = byte_index. |
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- |
| ascad-v2-1 | v2_affine_ptx |
0 | ViewState after Map_in_G + Xor_states at slotbyte_index.rm * ptx[j] ^ mask[j] where j = perm[byte_index].The affine-masked plaintext before any round key has been mixed in. |
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| ascad-v2-1 | v2_asym_charge_sbo |
0 | ViewHW(~raw_out & sbo_mid) where raw_out is the LUT output and sbo_mid is post-mask XOR.Models ONLY the bus lines that flipped from 0 to 1 during the register overwrite. Exploits power asymmetry: pulling current from VCC to charge a capacitor (0->1) creates a distinct physical signature compared to discharging it to ground. |
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| ascad-v2-1 | v2_asym_discharge_sbo |
0 | ViewHW(raw_out & ~sbo_mid) where raw_out is the LUT output and sbo_mid is post-mask XOR.Models ONLY the bus lines that flipped from 1 to 0 during the register overwrite. Isolates the ground-dissipation leakage signature from the VCC charging signature. |
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| ascad-v2-1 | v2_bit0_raw_out |
0 | ViewIsolates the Least Significant Bit (LSB) of the data fetched from the LUT. |
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| ascad-v2-1 | v2_bit7_linear_sbi |
0 | ViewNo description available. |
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| ascad-v2-1 | v2_bit7_lut_idx |
0 | ViewIsolates the Most Significant Bit (MSB) of the memory address during the sboxMasked lookup. |
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| ascad-v2-1 | v2_hd_address_bus_transition |
0 | ViewHD between the LUT index of the current time slot and the previous time slot. Models the physical Address Bus bit-flips during the tight SubBytes loop.HD(LUT_idx[i], LUT_idx[i-1]) where i = byte_index. |
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- |
| ascad-v2-1 | v2_hd_affine_sbi |
0 | ViewHD between affine plaintext and masked SBI.HD(rm*ptx[j]^mask[j], rm*(ptx[j]^key[j])^mask[j]) where j = perm[byte_index]. |
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- |
| ascad-v2-1 | v2_hd_ark_operands |
0 | ViewHD between the two operands entering the ALU during AddRoundKey r=0. HD(rmult * ptx[j] ^ mask[j], rmult * key[j]) |
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| ascad-v2-1 | v2_hd_ark_overwrite |
0 | ViewHD modelling the ALU writing the AddRoundKey result back over the scaled key register. HD(rmult * key[j], rmult * (ptx[j] ^ key[j]) ^ mask[j]) |
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| ascad-v2-1 | v2_hd_lut_idx_to_raw_out |
0 | ViewModels the register transition from LUT address to LUT value during SubBytes.HD(rm*x ^ rin, rm*SBOX(x) ^ rout) where x = ptx[j]^key[j] and j = perm[byte_index]. This models the CPU register replacing the computed sboxMasked memory address (LUT key) with the fetched value (LUT value). |
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| ascad-v2-1 | v2_hd_lut_transition |
0 | ViewHD between LUT index and LUT output.HD(rm*(ptx[j]^key[j])^rin, rm*SBOX(ptx[j]^key[j])^rout) where j = perm[byte_index]. |
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| ascad-v2-1 | v2_hd_map_in_g_overwrite |
0 | ViewModels the STM32 register overwriting the raw plaintext with the output of the GTab lookup.HD(ptx[j], rm * ptx[j]) where j = perm[byte_index]. Brilliant for isolating the alpha mask independently of the key. |
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| ascad-v2-1 | v2_hd_mask_interaction |
0 | ViewHD between mask[j] and rin wherej = perm[byte_index]. |
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- |
| ascad-v2-1 | v2_hd_perm_g4_cascade |
0 | ViewHD between Step 1 and Step 2 of the permutation cascade.HD( G[(15-i)^m0], G[G[(15-i)^m0]^m1] ) where i=byte_index, m0=mask[0]&0xF, m1=mask[1]&0xF. Models the register holding the intermediate index as it updates from m0-influence to m1-influence. |
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| ascad-v2-1 | v2_hd_perm_pointer_transition |
0 | ViewHD(perm[byte_index], perm[(byte_index - 1) % 16])Models the CPU address register or general-purpose register updating from the previous physical byte offset to the current physical byte offset. |
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| ascad-v2-1 | v2_hd_ptx_key |
0 | ViewHD between rmptx[j] and rmkey[j] wherej = perm[byte_index]. |
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| ascad-v2-1 | v2_hd_ptx_sbi |
0 | ViewHD between the unmasked plaintext and the unmasked SBI.HD(ptx[j], ptx[j] ^ key[j]) where j = perm[byte_index]. |
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| ascad-v2-1 | v2_hd_rm_rm_sbi |
0 | ViewHD(rm, rm * (ptx[j] ^ key[j])) where j = perm[byte_index]. Models the hardware register transition from the multiplicative mask to the multiplicatively masked SBI. |
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- |
| ascad-v2-1 | v2_hd_rout_mask_interaction |
0 | ViewHamming distance between the global rout mask and the per-byte mask.HD(rout, mask[j]) where j = perm[byte_index]. |
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| ascad-v2-1 | v2_hd_rout_raw_out |
0 | ViewHD(rout, rm * SBOX(ptx[j] ^ key[j]) ^ rout) where j = perm[byte_index]. Models the transition between the global output mask and the raw LUT output. |
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- |
| ascad-v2-1 | v2_hd_rout_sbo_mid |
0 | ViewHD(rout, rm * SBOX(ptx[j] ^ key[j]) ^ rout ^ mask[j]) where j = perm[byte_index]. Models the transition from the global output mask to the state inside the SubBytes inner loop after the per-byte mask has been added, but before rout is stripped. |
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| ascad-v2-1 | v2_hd_sbi |
0 | ViewHamming distance between masked plaintext and masked SBI.HD(rm * ptx[j] ^ mask[j], rm * (ptx[j] ^ key[j]) ^ mask[j]) where j = perm[byte_index]. |
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- |
| ascad-v2-1 | v2_hd_sbi_sbo |
0 | ViewHD between the unmasked SBI and unmasked SBO.HD(ptx[j] ^ key[j], SBOX(ptx[j] ^ key[j])) where j = perm[byte_index]. |
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- |
| ascad-v2-1 | v2_hd_sbo_affine_mc |
0 | ViewHD between the affine SBO and the masked MixColumns output.HD(rm*SBOX(ptx[j]^key[j])^mask[j], MixColumns(...)[j]) where j = perm[byte_index]. |
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- |
| ascad-v2-1 | v2_hd_unmasked_sbi_bus |
0 | ViewHD(ptx[j] ^ key[j], ptx[prev_j] ^ key[prev_j]) where j = perm[byte_index] and prev_j = perm[(byte_index - 1) % 16].Models the memory data bus sequentially carrying the unmasked S-Box Inputs as the firmware loops through the permuted byte indices. |
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- |
| ascad-v2-1 | v2_hd_unmasked_sbo_bus |
0 | ViewHD(SBOX(ptx[j] ^ key[j]), SBOX(ptx[prev_j] ^ key[prev_j])) where j = perm[byte_index] and prev_j = perm[(byte_index - 1) % 16].Models the memory data bus sequentially reading or writing the unmasked S-Box Outputs back to RAM during a permuted loop. |
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| ascad-v2-1 | v2_hd_unmasked_sbo_to_parity |
0 | ViewHD(SBOX(ptx[j] ^ key[j]), SBOX(sbi_0) ^ SBOX(sbi_1) ^ SBOX(sbi_2) ^ SBOX(sbi_3)) where j = perm[byte_index].Models the ALU transitioning from holding a single unmasked column byte to holding the fully XOR'd parity variable for that column during MixColumns. |
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- |
| ascad-v2-1 | v2_hd_unmasking_division |
0 | ViewModels the final GF256 division at the end of Round 10.HD(rm * ciphertext[i], ciphertext[i]) where i = byte_index. Allows reconstruction of the alpha mask from the ciphertext side, completely bypassing R1 noise. |
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| ascad-v2-1 | v2_hd_xor_states_injection |
0 | ViewModels the ALU applying the additive per-byte mask to the scaled plaintext.HD(rm * ptx[j], rm * ptx[j] ^ mask[j]) where j = perm[byte_index]. |
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| ascad-v2-1 | v2_hd_xw_lut_idx |
0 | ViewHD between the pre-LUT state (Xor_Word applied) and the LUT index.HD(rm*(ptx[j]^key[j])^mask[j]^rin, rm*(ptx[j]^key[j])^rin) where j = perm[byte_index]. |
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| ascad-v2-1 | v2_hw_affine_ptx |
0 | ViewHW of the affine-masked plaintext.HW(rm * ptx[j] ^ mask[j]) where j = perm[byte_index]. |
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| ascad-v2-1 | v2_hw_key |
0 | ViewHW of the key byte at the permuted AES position.HW(key[j]) where j = perm[byte_index]. |
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| ascad-v2-1 | v2_hw_lut_idx |
0 | ViewHW of the sboxMasked LUT index.HW(rm * (ptx[j] ^ key[j]) ^ rin) where j = perm[byte_index]. |
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| ascad-v2-1 | v2_hw_mask |
0 | ViewHW of the per-byte additive mask.HW(mask[j]) where j = perm[byte_index]. |
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| ascad-v2-1 | v2_hw_masked_sbi |
0 | ViewHW of the affine-masked SBI entering round 1.HW(rm * (ptx[j] ^ key[j]) ^ mask[j]) where j = perm[byte_index]. |
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| ascad-v2-1 | v2_hw_mc_parity_accumulator |
0 | ViewHW of the MixColumns intermediate 't' variable (the affine column parity). t = a0 ^ a1 ^ a2 ^ a3 |
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| ascad-v2-1 | v2_hw_mixcolumns_masked |
0 | ViewHW of the affine-masked MixColumns output.HW(MixColumns(ShiftRows(rm * SBOX(ptx ^ key) ^ mask))[j]) where j = perm[byte_index]. |
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| ascad-v2-1 | v2_hw_perm_g4_step1 |
0 | ViewHW of the first step of the perm_index generation.HW(G[ (15-i) ^ m0 ]) where i=byte_index and m0=mask[0]&0xF. Targets the lookup G[ (15-i) ^ m0 ], effectively isolating the m0 nibble. |
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| ascad-v2-1 | v2_hw_ptx |
0 | ViewHW of plaintext at the permuted AES position.HW(ptx[j]) where j = perm[byte_index]. |
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| ascad-v2-1 | v2_hw_raw_out |
0 | ViewHW of the sboxMasked LUT output.HW(rm * SBOX(ptx[j] ^ key[j]) ^ rout) where j = perm[byte_index]. |
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| ascad-v2-1 | v2_hw_rm_key |
0 | ViewHW of the multiplicatively masked key byte.HW(rm * key[j]) where j = perm[byte_index]. |
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- |
| ascad-v2-1 | v2_hw_rm_ptx |
0 | ViewHW of the Map_in_G output (multiplicatively masked plaintext).HW(rm * ptx[j]) where j = perm[byte_index]. |
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| ascad-v2-1 | v2_hw_sbi |
0 | ViewHW of the unmasked SBI at the permuted AES position.HW(ptx[j] ^ key[j]) where j = perm[byte_index]. |
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- |
| ascad-v2-1 | v2_hw_sbo |
0 | ViewHW of the unmasked SBO at the permuted AES position.HW(SBOX(ptx[j] ^ key[j])) where j = perm[byte_index]. |
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| ascad-v2-1 | v2_hw_sbo_affine |
0 | ViewHW of the post-SubBytes affine state.HW(rm * SBOX(ptx[j] ^ key[j]) ^ mask[j]) where j = perm[byte_index]. |
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| ascad-v2-1 | v2_hw_sbo_mid |
0 | ViewHW of the mid-SubBytes state (rout and per-byte mask applied).HW(rm * SBOX(ptx[j] ^ key[j]) ^ rout ^ mask[j]) where j = perm[byte_index]. |
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| ascad-v2-1 | v2_hw_unmasked_mc_parity |
0 | ViewHW(SBOX(sbi_0) ^ SBOX(sbi_1) ^ SBOX(sbi_2) ^ SBOX(sbi_3)) where sbi_x are the unmasked S-Box inputs for the column containing perm[byte_index].Models the pure, unmasked algorithmic parity accumulator ('t') computed in the ALU during the MixColumns operation for the current byte's column. |
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| ascad-v2-1 | v2_id_keyschedule_sbox |
0 | ViewNo description available. |
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| ascad-v2-1 | v2_id_linear_add_ptx_key |
0 | ViewNo description available. |
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- |
| ascad-v2-1 | v2_id_masked_sbi |
0 | View256-class Identity target for the affine-masked SBI. Passes the exact byte value directly to the DL model. |
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| ascad-v2-1 | v2_id_mc_partial_xor_unmasked |
0 | ViewNo description available. |
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| ascad-v2-1 | v2_id_mc_xtime_unmasked |
0 | ViewNo description available. |
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- |
| ascad-v2-1 | v2_id_sbo_affine |
0 | View256-class Identity target for the affine-masked SBO (post-rout strip). Passes the exact byte value directly to the DL model. |
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| ascad-v2-1 | v2_id_shifted_unmasked_sbo |
0 | ViewNo description available. |
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- |
| ascad-v2-1 | v2_id_shiftrows_pointer |
0 | ViewNo description available. |
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| ascad-v2-1 | v2_key |
0 | ViewPlain key byte at the AES position consumed by shuffling slotbyte_index.key[j] where j = perm[byte_index].The key byte is loaded unprotected from flash/ROM during AddRoundKey r=0 before being scaled into the GF(256) domain via gtab. Classic first-order DPA target; v2_rm_key is the masked (GF-scaled) version. |
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- |
| ascad-v2-1 | v2_lut_idx |
0 | ViewsboxMasked LUT index computed during SubBytes at round 1, slotbyte_index.rm * (ptx[j] ^ key[j]) ^ rin where j = perm[byte_index].Computed as state[j] ^ state2[j] inside the SubBytes loop: the additive masks (masksState) cancel, leaving only the multiplicatively-masked SBI XORed with rin. This is the value whose hamming weight leaks during the LUT address computation. |
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| ascad-v2-1 | v2_mask_at_perm |
0 | ViewPer-byte additive mask at the AES position consumed by shuffling slotbyte_index.mask[j] where j = perm[byte_index].Distinct from mask[byte_index] whenever the permutation is non-identity. This is the mask that enters and leaves every intermediate in the affine invariant for slot byte_index. |
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| ascad-v2-1 | v2_masked_key_affine |
0 | ViewKey contribution after both multiplicative and additive masking.rm * key[j] ^ mask[j] where j = perm[byte_index]. |
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- |
| ascad-v2-1 | v2_masked_sbi |
0 | ViewState entering round 1 at slotbyte_index: after AddRoundKey r=0.rm * (ptx[j] ^ key[j]) ^ mask[j] where j = perm[byte_index].This is the affine-masked plaintext XOR key value that the round-1 SubBytes call will process. |
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| ascad-v2-1 | v2_mixcolumns_masked |
0 | ViewOutput of MixColumns with affine masks still applied.MixColumns(ShiftRows(rm * SBOX(ptx ^ key) ^ mask))[j] where j = perm[byte_index]. |
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| ascad-v2-1 | v2_perm |
0 | ViewShuffling permutation index at slotbyte_index for ASCAD v2.Returns j = perm[:, byte_index] — for each trace the AES byte position (0–15) processed in shuffling slot byte_index. All other slot-indexed v2_* targets derive j via this method.Original-paper label: perm_index[byte_index] in the ASCAD v2 HDF5 file. Derived as:perm[n, i] = G[G[G[G[(15 - i) XOR x0[n]] XOR x1[n]] XOR x2[n]] XOR x3[n]] where G = _V2_PERM_G and x0..x3 are the lower nibbles of mask[:, 0..3]. |
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| ascad-v2-1 | v2_ptx |
0 | ViewPlaintext byte at the AES position consumed by shuffling slotbyte_index.ptx[j] where j = perm[byte_index].The byte value loaded from the plaintext register before Map_in_G scales it into the GF(256) multiplicative domain. Classic first-order DPA target; v2_rm_ptx is the masked version after Map_in_G. |
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| ascad-v2-1 | v2_raw_out |
0 | ViewSubBytesraw_out at round 1, slot byte_index: the sboxMasked LUT output.rm * SBOX(ptx[j] ^ key[j]) ^ rout where j = perm[byte_index].This is sboxMasked[lut_idx] — the value read from the firmware's masked S-Box LUT before it is XORed with state2[j] (masksState). It sits between :meth:v2_lut_idx (the LUT address) and :meth:v2_sbo_mid (the value written back into state[j]).Original-paper label: sbox_masked[byte_index] in the ASCAD v2 HDF5 file and the NCC Group ML-104 blog 34-task model. |
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| ascad-v2-1 | v2_raw_out_direct |
0 | ViewSubBytesraw_out at round 1 indexed directly by AES byte position.rm * SBOX(ptx[i] ^ key[i]) ^ rout where i = byte_index (no perm).Unlike :meth: v2_raw_out, the shuffle permutation is not applied — byte_index maps directly to the AES state byte position. This is the same formula as :meth:v2_raw_out but over the identity byte ordering, making it practical as an un-permuted SNR or model target.Original-paper label: sbox_masked_with_perm[byte_index] in the ASCAD v2 HDF5 file and the NCC Group ML-104 blog 18-task model (RMmSBOxROUT in scandal/crypto.py). |
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| ascad-v2-1 | v2_rin_mask_interaction |
0 | ViewInteraction between global input mask and per-byte mask.rin ^ mask[j] where j = perm[byte_index]. |
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- |
| ascad-v2-1 | v2_rm_key |
0 | ViewMasked round-key contribution added during AddRoundKey r=0 at slotbyte_index.rm * key[j] where j = perm[byte_index].This is gtab[key[j]] — the value XORed into state during the masked AddRoundKey call, scaled into the same multiplicative domain as the plaintext. |
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- |
| ascad-v2-1 | v2_rm_ptx |
0 | ViewMap_in_G output at slotbyte_index: rm * ptx[j], j = perm[byte_index].The plaintext byte scaled into the GF(256) multiplicative domain. Additive mask (masksState) has not yet been applied at this point. |
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- |
| ascad-v2-1 | v2_rout_mask_interaction |
0 | ViewValue of the interaction between the global rout mask and the per-byte mask. |
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- |
| ascad-v2-1 | v2_sbi_perm |
0 | ViewUnmasked SBI at the AES byte position consumed by shuffling slotbyte_index.ptx[j] ^ key[j] where j = perm[byte_index].Unlike :meth: sbi, which uses byte_index as a direct AES byte position, this target follows the actual byte consumed by the firmware SubBytes shuffle at slot byte_index. |
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| ascad-v2-1 | v2_sbo_affine |
0 | ViewAffine-masked SBO at slotbyte_index after full SubBytes (post-loop rout strip).rm * SBOX(ptx[j] ^ key[j]) ^ mask[j] where j = perm[byte_index].This is the state value after the post-loop state[j] ^= rout pass restores the affine invariant. The rout mask is gone; only the multiplicative mask rm and the per-byte additive mask remain. |
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| ascad-v2-1 | v2_sbo_hd |
0 | ViewHamming distance between mid-SubBytes and affine SBO.HD(rm * SBOX(ptx[j] ^ key[j]) ^ rout ^ mask[j], rm * SBOX(ptx[j] ^ key[j]) ^ mask[j]) where j = perm[byte_index]. |
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| ascad-v2-1 | v2_sbo_mid |
0 | ViewMid-SubBytes state at slotbyte_index before post-loop rout strip.rm * SBOX(ptx[j] ^ key[j]) ^ rout ^ mask[j] where j = perm[byte_index].This is raw_out ^ state2[j], i.e. the value written back into state[j] inside the SubBytes inner loop, before the post-loop state[j] ^= rout pass. The rout mask has not yet been removed. |
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| ascad-v2-1 | v2_sbo_perm |
0 | ViewUnmasked SBO at the AES byte position consumed by shuffling slotbyte_index.SBOX(ptx[j] ^ key[j]) where j = perm[byte_index]. |
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- |
| ascad-v2-1 | v2_xw_state |
0 | ViewState after Xor_Word at round 1 (before SubBytes) at slotbyte_index.rm * (ptx[j] ^ key[j]) ^ mask[j] ^ rin where j = perm[byte_index].This is the state byte written to the register immediately before the firmware issues the sboxMasked lookup. |
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| ascad-v2-1 | v2_zero_flag_linear_sbi |
0 | ViewNo description available. |
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| ascad-v2-1 | v2_zero_flag_sbo_mid |
0 | ViewModels the Zero flag after the raw_out is XOR'd with the per-byte mask.Condition: rm * SBOX(...) ^ rout ^ mask[j] == 0 |
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| ascad-v2-1 | v2_zero_flag_xw_state |
0 | ViewModels the ARM Cortex-M Zero (Z) status flag. Returns 1 if the state entering the LUT lookup is exactly zero, else 0.Condition: rm * (ptx[j] ^ key[j]) ^ mask[j] ^ rin == 0 |
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| ascad-v2-1 | rin |
none | ViewRaw global input maskrin. |
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| ascad-v2-1 | rin_ |
none | ViewRaw global input maskrin_ for second S-box pass. |
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| ascad-v2-1 | rm |
none | ViewRaw global multiplicative maskrm (alpha). |
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| ascad-v2-1 | rm_ |
none | ViewRaw global multiplicative maskrm_ for second S-box pass. |
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| ascad-v2-1 | rout |
none | ViewRaw global output maskrout. |
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| ascad-v2-1 | rout_ |
none | ViewRaw global output maskrout_ for second S-box pass. |
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Parameters Used for Generation
- HF_ORG:
DLSCA - CHUNK_SIZE_Y:
50000 - CHUNK_SIZE_X:
200 - TOTAL_CHUNKS_ON_Y:
2 - TOTAL_CHUNKS_ON_X:
5000 - NUM_JOBS:
10 - CAN_RUN_LOCALLY:
True - CAN_RUN_ON_CLOUD:
False - COMPRESSED:
True
Usage
You can load this dataset directly using Zarr and Hugging Face File System:
import zarr
from huggingface_hub import HfFileSystem
fs = HfFileSystem()
# Map only once to the dataset root
root = zarr.open_group(fs.get_mapper("datasets/DLSCA/ascad-v2-1"), mode="r")
# Access traces directly
traces = root["traces"]
print("Traces shape:", traces.shape)
# Access plaintext metadata directly
plaintext = root["metadata"]["plaintext"]
print("Plaintext shape:", plaintext.shape)